diff --git a/difftest b/difftest
index 5544550b..df9b69fd 160000
--- a/difftest
+++ b/difftest
@@ -1 +1 @@
-Subproject commit 5544550b209477321025c8f58c471bc4ceed2db3
+Subproject commit df9b69fda4c658478a352804c129a1df3d6a1483
diff --git a/src/main/scala/sim/NutShellSim.scala b/src/main/scala/sim/NutShellSim.scala
index ce4edfe3..51b84872 100644
--- a/src/main/scala/sim/NutShellSim.scala
+++ b/src/main/scala/sim/NutShellSim.scala
@@ -23,7 +23,7 @@ import difftest._
 import nutcore.NutCoreConfig
 import system._
 
-class SimTop extends Module {
+class NutShellSim extends Module with HasDiffTestInterfaces {
   lazy val config = NutCoreConfig(FPGAPlatform = false)
   val soc = Module(new NutShell()(config))
   val mem = Module(new AXI4RAM(memByte = 2L * 1024 * 1024 * 1024, useBlackBox = true))
@@ -41,6 +41,11 @@ class SimTop extends Module {
 
   soc.io.meip := mmio.io.meip
 
-  val difftest = DifftestModule.finish("nutshell")
-  difftest.uart <> mmio.io.uart
+  override def cpuName: Option[String] = Some("NutShell")
+
+  val uart = IO(new UARTIO)
+  uart <> mmio.io.uart
+  override def connectTopIOs(difftest: DifftestTopIO): Unit = {
+    difftest.uart <> uart
+  }
 }
diff --git a/src/test/scala/TopMain.scala b/src/test/scala/TopMain.scala
index 8c717898..c4f03437 100644
--- a/src/test/scala/TopMain.scala
+++ b/src/test/scala/TopMain.scala
@@ -20,9 +20,9 @@ import chisel3._
 import chisel3.stage.ChiselGeneratorAnnotation
 import circt.stage._
 import device.AXI4VGA
-import difftest.DifftestModule
+import difftest.{DifftestModule, DifftestTopIO, HasDiffTestInterfaces}
 import nutcore.NutCoreConfig
-import sim.SimTop
+import sim.NutShellSim
 import system.NutShell
 
 class Top extends Module {
@@ -36,15 +36,17 @@ class Top extends Module {
   dontTouch(vga.io)
 }
 
-class FpgaDiffTop extends Module {
-  override lazy val desiredName: String = "SimTop"
+class FpgaDiffTop extends Module with HasDiffTestInterfaces {
   lazy val config = NutCoreConfig(FPGADifftest = true)
   val soc = Module(new NutShell()(config))
   val io = IO(soc.io.cloneType)
   soc.io <> io
 
-  val difftest = DifftestModule.finish("nutshell")
-  dontTouch(soc.io)
+  override def cpuName: Option[String] = Some("NutShell")
+  override def connectTopIOs(difftest: DifftestTopIO): Unit = {
+    val io = IO(chiselTypeOf(this.io))
+    io <> this.io
+  }
 }
 
 object TopMain extends App {
@@ -79,9 +81,9 @@ object TopMain extends App {
   }
 
   val generator = if (board == "sim") {
-    ChiselGeneratorAnnotation(() => new SimTop)
+    ChiselGeneratorAnnotation(() => DifftestModule.top(new NutShellSim))
   } else if (board == "fpgadiff") {
-    ChiselGeneratorAnnotation(() => new FpgaDiffTop)
+    ChiselGeneratorAnnotation(() => DifftestModule.top(new FpgaDiffTop))
   }
   else {
     ChiselGeneratorAnnotation(() => new Top)