From c01a1c2dc8cbdf45254aad09495944e07b8dc6bb Mon Sep 17 00:00:00 2001 From: klin02 Date: Tue, 2 Jun 2026 20:38:05 +0800 Subject: [PATCH] Bump difftest: connect AXI inside when !isFPGA Previous https://github.com/OSCPU/NutShell/pull/258 always expose CPU/MEM AXI ports and connect them in Difftest. This change move the connect back to DUT inside by default, and only override `cpu <> mem` with `cpu <> cpuIO` and `mem <> memIO` when isFPGA with DifftestMemCtrl.exposeIO(cpuAXI,memAXI). --- difftest | 2 +- src/main/scala/sim/NutShellSim.scala | 7 +++++-- 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/difftest b/difftest index ca341b67..261b4413 160000 --- a/difftest +++ b/difftest @@ -1 +1 @@ -Subproject commit ca341b6739b434562959184fc07ae42de4efbffd +Subproject commit 261b4413184c901fa45bb3387f8c40a702d56ebd diff --git a/src/main/scala/sim/NutShellSim.scala b/src/main/scala/sim/NutShellSim.scala index ed6ec884..a6e8af0f 100644 --- a/src/main/scala/sim/NutShellSim.scala +++ b/src/main/scala/sim/NutShellSim.scala @@ -36,14 +36,17 @@ class NutShellSim extends Module with HasDiffTestInterfaces { soc.io.frontend <> mmio.io.dma memdelay.io.in <> soc.io.mem + mem.io.in <> memdelay.io.out mmio.io.rw <> soc.io.mmio soc.io.meip := mmio.io.meip override def cpuName: Option[String] = Some("NutShell") - val memIO = DifftestMemCtrl.exposeIO(memdelay.io.out, mem.io.in) - override def difftestMemIO: Option[DifftestMemIO] = Some(memIO) + val memIO = Option.when(DifftestModule.isFPGA) { + DifftestMemCtrl.exposeIO(memdelay.io.out, mem.io.in) + } + override def difftestMemIO: Option[DifftestMemIO] = memIO val uart = IO(new UARTIO) uart <> mmio.io.uart