/open-fpga-verilog-tutorial

Aprender a diseñar sistemas digitales sintetizables en FPGAs usando SOLO herramientas libres #verilog #icestorm #lattice #Linux
  1. Verilog 40.4%
  2. Makefile 19.3%
  3. SystemVerilog 18.1%
  4. Coq 16.2%
  5. Python 5.6%
  6. Assembly 0.4%
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tutorial Cleanup T03 Makefile to remove make steps for files that don't exist … Mar 30, 2017
.gitignore Ignored output files Jan 27, 2016
LICENSE Initial commit Aug 10, 2015
README.md Update README.md May 10, 2016

README.md

Diseño Digital para FPGAs, con herramientas libres

Aprender a diseñar sistemas digitales sintetizables en FPGAs usando SOLO herramientas libres #verilog #icestorm #lattice #Linux

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