/include/ "system-conf.dtsi"
/include/ "zcu102-rev1.0.dtsi"
/ {
    reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		rproc_0_reserved: rproc@3ed000000 {
				no-map;
				reg = <0x0 0x3ed00000 0x0 0x1000000>;
   		};
	};

    power-domains {
        pd_r5_0: pd_r5_0 {
        	#power-domain-cells = <0x0>;
        	pd-id = <0x7>;
        };

		pd_r5_1: pd_r5_1 {
			#power-domain-cells = <0x0>;
			pd-id = <0x8>;
		};

        pd_tcm_0_a: pd_tcm_0_a {
        	#power-domain-cells = <0x0>;
       	 	pd-id = <0xf>;
        };
        
		pd_tcm_0_b: pd_tcm_0_b {
        	#power-domain-cells = <0x0>;
        	pd-id = <0x10>;
		};

		pd_tcm_1_a: pd_tcm_1_a {
			#power-domain-cells = <0x0>;
			pd-id = <0x11>;
		};

		pd_tcm_1_b: pd_tcm_1_b {
			#power-domain-cells = <0x0>;
			pd-id = <0x12>;
		};
    };


    amba {
        
		vring: vring@0 {
			compatible = "vring_uio";
			reg = <0x0 0x3ed40000 0x0 0x40000>;
        };

    	/* Shared memory */
        shm0: shm@0 {
            compatible = "shm_uio";
            reg = <0x0 0x3ed80000 0x0 0x800000>;
        };
	
	    /* IPI device */
        /*ipi0_amp: ipi@ff340000  {*/
		ipi0: ipi@ {
             compatible = "ipi_uio";
             reg = <0x0 0xff340000 0x0 0x1000>;
             interrupt-parent = <&gic>;
             interrupts = <0 29 4>;
         };

        r5_0_tcm_a: tcm@ffe00000 {
			compatible = "mmio-sram";
			reg = <0 0xFFE00000 0x0 0x10000>;
			pd-handle = <&pd_tcm_0_a>;
		};

		r5_0_tcm_b: tcm@ffe20000 {
			compatible = "mmio-sram";
			reg = <0 0xFFE20000 0x0 0x10000>;
			pd-handle = <&pd_tcm_0_b>;
		};

		r5_1_tcm_a: tcm@ffe90000 {
			compatible = "mmio-sram";
			reg = <0 0xFFE90000 0x0 0x10000>;
			pd-handle = <&pd_tcm_1_a>;
		};

		r5_1_tcm_b: tcm@ffe92000 {
			compatible = "mmio-sram";
			reg = <0 0xFFEB0000 0x0 0x10000>;
			pd-handle = <&pd_tcm_1_b>;
		};
	
		elf_ddr_0: ddr@3ed00000 {
			compatible = "mmio-sram";
			reg = <0 0x3ed00000 0x0 0x40000>;
		};

		elf_ddr_1: ddr@3ed40000 {
			compatible = "mmio-sram";
			reg = <0 0x3ed40000 0x0 0x40000>;
		};

		test_r50: zynqmp_r5_rproc@0 {
			compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
			reg = <0x0 0xff9a0100 0 0x100>, <0x0 0xff340000 0 0x100>, <0x0 0xff9a0000 0 0x100>;
			reg-names = "rpu_base", "rpu_glbl_base";
			dma-ranges;
			core_conf = "split0";
            srams = <&r5_0_tcm_a &r5_0_tcm_b &elf_ddr_0>;
			pd-handle = <&pd_r5_0>;
			interrupt-parent = <&gic>;
			interrupts = <0 29 4>;
		};

		test_r51: zynqmp_r5_rproc@1 {
			compatible = "xlnx,zynqmp-r5-remoteproc-1.0";
			reg =<0x0 0xff9a0200 0 0x100>, <0x0 0xff340000 0 0x100>, <0x0 0xff9a0000 0 0x100>;
			reg-names = "rpu_base", "ipi", "rpu_glbl_base";
			dma-ranges;
			core_conf = "split1";
			srams = <&r5_1_tcm_a &r5_1_tcm_b &elf_ddr_1>;
			pd-handle = <&pd_r5_1>;
			interrupt-parent = <&gic>;
			interrupts = <0 29 4>;

		};
		ttc0: timer@ff110000 {
          compatible = "ttc0_libmetal_demo";
          status = "okay";
		};
    };
};