diff --git a/actions/hls.mk b/actions/hls.mk index d889c6dc1..797fc1a98 100644 --- a/actions/hls.mk +++ b/actions/hls.mk @@ -51,9 +51,14 @@ $(syn_dir): $(srcs) run_hls_script.tcl @if [ ! -d "$(SNAP_ROOT)/hardware/logs" ]; then \ mkdir -p $(SNAP_ROOT)/hardware/logs; \ fi - @echo " Compiling action with Vivado HLS `vivado_hls -version|head -n1|cut -d " " -f 11`" @echo " Clock period used for HLS is $(HLS_ACTION_CLOCK) ns" - vivado_hls -f run_hls_script.tcl > $(SNAP_ROOT)/hardware/logs/action_make.log + @if [ "X$(HLS_VITIS_USED)" = "XTRUE" ]; then \ + echo " Compiling action with Vitis HLS `vitis_hls -version|head -n1|cut -d " " -f 11`"; \ + vitis_hls -f run_hls_script.tcl > $(SNAP_ROOT)/hardware/logs/action_make.log; \ + else \ + echo " Compiling action with Vivado HLS `vivado_hls -version|head -n1|cut -d " " -f 11`"; \ + vivado_hls -f run_hls_script.tcl > $(SNAP_ROOT)/hardware/logs/action_make.log; \ + fi $(RM) -rf $@/systemc $@/verilog # Create symlinks for simpler access @@ -76,7 +81,7 @@ $(SOLUTION_NAME): $(objs) # FIXME That those things are not resulting in an error is problematic. # If we get critical warnings we stay away from continuing now, -# since that will according to our experience with vivado_hls, lead +# since that will according to our experience with vivado/vitis_hls, lead # to strange problems later on. So let us work on fixing the design # if they occur. Rather than challenging our luck. # @@ -84,21 +89,20 @@ $(SOLUTION_NAME): $(objs) # Check for CRITICAL warnings and exit if those occur. Add more if needed. # Check for critical warnings and exit if those occur. Add more if needed. # Check for reserved HLS MMIO reg at offset 0x17c. -# + check: $(syn_dir) - @if [ X$(HLS_ACTION_CLOCK) != X$(shell grep "Setting up clock" vivado_hls.log |cut -d " " -f 12|cut -d "n" -f 1) ]; then \ - echo " ---------------------------------------------------------- "; \ - echo " ERROR: Action was last compiled with a different HLS clock."; \ - echo " Please force the recompilation with a 'make clean' command"; \ - echo " ---------------------------------------------------------- "; exit -1; \ + @if [ "${HLS_ACTION_CLOCK}" != "${shell grep "Setting up clock" *_hls.log |cut -d " " -f 12|cut -d "n" -f 1}" ]; then \ + echo " ERROR with Vivado/Vitis HLS. HLS Action was last compiled with a different HLS clock."; \ + echo " Please force the recompilation with a 'make clean' command"; \ + echo " ---------------------------------------------------------- "; exit 1; \ fi @echo -n " Checking for critical warnings during HLS synthesis .... " - @grep -A8 CRITICAL vivado_hls.log; \ + @grep -A8 CRITICAL *_hls.log; \ test $$? = 1 @echo "OK" @if [ $(HLS_ACTION_CLOCK) == $(HLS_ACTION_CLOCK_DEFAULT) ]; then \ echo -n " Checking for critical timings during HLS synthesis .... "; \ - grep -A8 critical vivado_hls.log; \ + grep -A8 critical *_hls.log; \ if [ $$? -eq 0 ]; then \ echo "------------------------------------------------------------------ "; \ echo "TIMING ERROR: Please correct your action code before going further"!; \ @@ -113,11 +117,11 @@ check: $(syn_dir) echo " By defining a HLS clock different than the default 5ns, the automatic checking"; \ echo " of the critical timings is disabled. You need to manually check them."; \ echo " FYI action was compiled with following HLS clock:"; \ - grep "Setting up clock" vivado_hls.log ; \ + grep "Setting up clock" *_hls.log ; \ echo " --------------------------------------------------------------------------- "; \ echo " please CHECK the below list (if any) for HLS synthesis critical timing .... "; \ echo " --------------------------------------------------------------------------- "; \ - grep -A8 critical vivado_hls.log ; \ + grep -A8 critical *_hls.log ; \ echo " --------------------------------------------------------------------------- "; \ if [ $$? -ne 0 ]; then \ echo "OK"; \ diff --git a/actions/hls_decimal_mult/hw/action_decimal_mult.cpp b/actions/hls_decimal_mult/hw/action_decimal_mult.cpp index f9832c120..ee9a82516 100644 --- a/actions/hls_decimal_mult/hw/action_decimal_mult.cpp +++ b/actions/hls_decimal_mult/hw/action_decimal_mult.cpp @@ -140,7 +140,12 @@ void hls_action(snap_membus_512_t *din_gmem, // Host Memory AXI Lite Master Interface -#pragma HLS DATA_PACK variable=act_reg +#ifdef HLS_VITIS_USED + #pragma HLS AGGREGATE variable=act_reg +#else + #pragma HLS DATA_PACK variable=act_reg +#endif + #pragma HLS INTERFACE s_axilite port=act_reg bundle=ctrl_reg offset=0x100 #pragma HLS INTERFACE s_axilite port=return bundle=ctrl_reg diff --git a/actions/hls_hbm_memcopy_1024/hw/hw_action_hbm_memcopy_1024.cpp b/actions/hls_hbm_memcopy_1024/hw/hw_action_hbm_memcopy_1024.cpp index 451ff6456..e089043b8 100644 --- a/actions/hls_hbm_memcopy_1024/hw/hw_action_hbm_memcopy_1024.cpp +++ b/actions/hls_hbm_memcopy_1024/hw/hw_action_hbm_memcopy_1024.cpp @@ -32,7 +32,7 @@ // the application shouldn't use more interfaces than the number you have defined in Kconfig menu. // (extra interfaces not connected will be removed if not connected to the wrapper) -#define HBM_AXI_IF_NB 12 +#define HBM_AXI_IF_NB 12 //===================================================================================// @@ -835,7 +835,13 @@ void hls_action(snap_membus_1024_t *din_gmem, max_read_burst_length=64 max_write_burst_length=64 // Host Memory AXI Lite Master Interface -#pragma HLS DATA_PACK variable=act_reg + + #ifdef HLS_VITIS_USED + #pragma HLS AGGREGATE variable=act_reg +#else + #pragma HLS DATA_PACK variable=act_reg +#endif + #pragma HLS INTERFACE s_axilite port=act_reg bundle=ctrl_reg offset=0x100 #pragma HLS INTERFACE s_axilite port=return bundle=ctrl_reg diff --git a/actions/hls_helloworld_1024/hw/action_uppercase.cpp b/actions/hls_helloworld_1024/hw/action_uppercase.cpp index e13603873..1ac94c02e 100644 --- a/actions/hls_helloworld_1024/hw/action_uppercase.cpp +++ b/actions/hls_helloworld_1024/hw/action_uppercase.cpp @@ -96,7 +96,11 @@ void hls_action(snap_membus_1024_t *din_gmem, * #pragma HLS INTERFACE s_axilite port=d_ddrmem bundle=ctrl_reg offset=0x050 */ // Host Memory AXI Lite Master Interface - NO CHANGE BELOW -#pragma HLS DATA_PACK variable=act_reg +#ifdef HLS_VITIS_USED + #pragma HLS AGGREGATE variable=act_reg +#else + #pragma HLS DATA_PACK variable=act_reg +#endif #pragma HLS INTERFACE s_axilite port=act_reg bundle=ctrl_reg offset=0x100 #pragma HLS INTERFACE s_axilite port=return bundle=ctrl_reg diff --git a/actions/hls_helloworld_512/hw/action_uppercase.cpp b/actions/hls_helloworld_512/hw/action_uppercase.cpp index cdac4933e..329015d58 100644 --- a/actions/hls_helloworld_512/hw/action_uppercase.cpp +++ b/actions/hls_helloworld_512/hw/action_uppercase.cpp @@ -97,7 +97,11 @@ void hls_action(snap_membus_512_t *din_gmem, * #pragma HLS INTERFACE s_axilite port=d_ddrmem bundle=ctrl_reg offset=0x050 */ // Host Memory AXI Lite Master Interface - NO CHANGE BELOW -#pragma HLS DATA_PACK variable=act_reg +#ifdef HLS_VITIS_USED + #pragma HLS AGGREGATE variable=act_reg +#else + #pragma HLS DATA_PACK variable=act_reg +#endif #pragma HLS INTERFACE s_axilite port=act_reg bundle=ctrl_reg offset=0x100 #pragma HLS INTERFACE s_axilite port=return bundle=ctrl_reg diff --git a/actions/hls_helloworld_python/hw/action_uppercase.cpp b/actions/hls_helloworld_python/hw/action_uppercase.cpp index 166a526ef..7d3866b32 100644 --- a/actions/hls_helloworld_python/hw/action_uppercase.cpp +++ b/actions/hls_helloworld_python/hw/action_uppercase.cpp @@ -95,7 +95,11 @@ void hls_action(snap_membus_1024_t *din_gmem, * #pragma HLS INTERFACE s_axilite port=d_ddrmem bundle=ctrl_reg offset=0x050 */ // Host Memory AXI Lite Master Interface - NO CHANGE BELOW -#pragma HLS DATA_PACK variable=act_reg +#ifdef HLS_VITIS_USED + #pragma HLS AGGREGATE variable=act_reg +#else + #pragma HLS DATA_PACK variable=act_reg +#endif #pragma HLS INTERFACE s_axilite port=act_reg bundle=ctrl_reg offset=0x100 #pragma HLS INTERFACE s_axilite port=return bundle=ctrl_reg diff --git a/actions/hls_image_filter/hw/action_pixel_filter.cpp b/actions/hls_image_filter/hw/action_pixel_filter.cpp index b64e9b761..4d31f58f2 100644 --- a/actions/hls_image_filter/hw/action_pixel_filter.cpp +++ b/actions/hls_image_filter/hw/action_pixel_filter.cpp @@ -225,8 +225,11 @@ void hls_action(snap_membus_512_t *din_gmem, * #pragma HLS INTERFACE s_axilite port=d_ddrmem bundle=ctrl_reg offset=0x050 */ // Host Memory AXI Lite Master Interface - NO CHANGE BELOW - -#pragma HLS DATA_PACK variable=act_reg +#ifdef HLS_VITIS_USED + #pragma HLS AGGREGATE variable=act_reg +#else + #pragma HLS DATA_PACK variable=act_reg +#endif #pragma HLS INTERFACE s_axilite port=act_reg bundle=ctrl_reg offset=0x100 #pragma HLS INTERFACE s_axilite port=return bundle=ctrl_reg diff --git a/actions/hls_memcopy_1024/hw/hw_action_memcopy_1024.cpp b/actions/hls_memcopy_1024/hw/hw_action_memcopy_1024.cpp index 5a8826ba4..9c152e269 100644 --- a/actions/hls_memcopy_1024/hw/hw_action_memcopy_1024.cpp +++ b/actions/hls_memcopy_1024/hw/hw_action_memcopy_1024.cpp @@ -257,7 +257,11 @@ void hls_action(snap_membus_1024_t *din_gmem, // Host Memory AXI Lite Master Interface -#pragma HLS DATA_PACK variable=act_reg +#ifdef HLS_VITIS_USED + #pragma HLS AGGREGATE variable=act_reg +#else + #pragma HLS DATA_PACK variable=act_reg +#endif #pragma HLS INTERFACE s_axilite port=act_reg bundle=ctrl_reg offset=0x100 #pragma HLS INTERFACE s_axilite port=return bundle=ctrl_reg diff --git a/actions/hls_memcopy_512/hw/hw_action_memcopy_512.cpp b/actions/hls_memcopy_512/hw/hw_action_memcopy_512.cpp index 0ad0a762f..8c3571a39 100644 --- a/actions/hls_memcopy_512/hw/hw_action_memcopy_512.cpp +++ b/actions/hls_memcopy_512/hw/hw_action_memcopy_512.cpp @@ -217,7 +217,11 @@ void hls_action(snap_membus_512_t *din_gmem, // Host Memory AXI Lite Master Interface -#pragma HLS DATA_PACK variable=act_reg +#ifdef HLS_VITIS_USED + #pragma HLS AGGREGATE variable=act_reg +#else + #pragma HLS DATA_PACK variable=act_reg +#endif #pragma HLS INTERFACE s_axilite port=act_reg bundle=ctrl_reg offset=0x100 #pragma HLS INTERFACE s_axilite port=return bundle=ctrl_reg diff --git a/actions/hls_udp_512/tests/action_test.h b/actions/hls_udp_512/hw/action_test.h similarity index 93% rename from actions/hls_udp_512/tests/action_test.h rename to actions/hls_udp_512/hw/action_test.h index 886ee8db3..4f7747d18 100644 --- a/actions/hls_udp_512/tests/action_test.h +++ b/actions/hls_udp_512/hw/action_test.h @@ -1,7 +1,6 @@ #include -#include -//#define NO_SYNTH -#include "../hw/hls_udp.h" +//#include +//#include "hls_udp.h" #pragma pack(push) diff --git a/actions/hls_udp_512/hw/eth_decode.cpp b/actions/hls_udp_512/hw/eth_decode.cpp index a4327def5..f57105596 100644 --- a/actions/hls_udp_512/hw/eth_decode.cpp +++ b/actions/hls_udp_512/hw/eth_decode.cpp @@ -14,11 +14,11 @@ * limitations under the License. */ -#include "hls_udp.h" #include -#include "osnap_hls_if.h" +//#include "osnap_hls_if.h" #include "ap_int.h" -#include +//#include +#include "hls_udp.h" enum rcv_state_t {RCV_INIT, RCV_JF_HEADER, RCV_GOOD, RCV_BAD, RCV_IGNORE}; diff --git a/actions/hls_udp_512/hw/hls_udp.cpp b/actions/hls_udp_512/hw/hls_udp.cpp index 493f4a0a9..8ae0b32b5 100644 --- a/actions/hls_udp_512/hw/hls_udp.cpp +++ b/actions/hls_udp_512/hw/hls_udp.cpp @@ -18,9 +18,10 @@ #include #include "ap_int.h" #include -#include "osnap_hls_if.h" - -#include "../tests/action_test.h" +//#include "osnap_hls_if.h" +//#include "hls_snap_1024.H" +#include "hls_udp.h" +#include "action_test.h" void process_frames(AXI_STREAM &din_eth, eth_settings_t eth_settings, eth_stat_t ð_stat, snap_membus_512_t *dout_gmem, uint64_t out_frame_buffer_addr) { #pragma HLS DATAFLOW @@ -144,7 +145,11 @@ void hls_action(snap_membus_512_t *din_gmem, #pragma HLS INTERFACE s_axilite port=dout_gmem bundle=ctrl_reg offset=0x040 // Host Memory AXI Lite Master Interface - NO CHANGE BELOW -#pragma HLS DATA_PACK variable=act_reg +#ifdef HLS_VITIS_USED + #pragma HLS AGGREGATE variable=act_reg +#else + #pragma HLS DATA_PACK variable=act_reg +#endif #pragma HLS INTERFACE s_axilite port=act_reg bundle=ctrl_reg offset=0x100 #pragma HLS INTERFACE s_axilite port=return bundle=ctrl_reg @@ -165,6 +170,7 @@ void hls_action(snap_membus_512_t *din_gmem, } else process_action(din_gmem, dout_gmem, din_eth, dout_eth, act_reg); + } //--------------------------------------------------------------------------------------// diff --git a/actions/hls_udp_512/hw/hls_udp.h b/actions/hls_udp_512/hw/hls_udp.h index e0b2c6601..bb910be5f 100644 --- a/actions/hls_udp_512/hw/hls_udp.h +++ b/actions/hls_udp_512/hw/hls_udp.h @@ -21,11 +21,13 @@ #include #include #include - +#ifdef HLS_VITIS_USED +#include +#endif #include "hls_snap_1024.H" #include "action_udp.H" /* Job definition */ -typedef char word_t[BPERDW_1024]; +//typedef char word_t[BPERDW_512]; //--------------------------------------------------------------------- // This is generic. Just adapt names for a new action // CONTROL is defined and handled by SNAP @@ -36,13 +38,18 @@ typedef struct { uint8_t padding[SNAP_HLS_JOBSIZE - sizeof(rx100G_job_t)]; } action_reg; +#ifdef HLS_VITIS_USED + //redefining the structure to get keep, user and last signals + typedef ap_axiu<512,1,0,0> ap_axiu_for_eth; +#else // Based on https://forums.xilinx.com/t5/High-Level-Synthesis-HLS/ap-axiu-parameters/td-p/635138 -struct ap_axiu_for_eth { + struct ap_axiu_for_eth { ap_uint<512> data; ap_uint<64> keep; ap_uint<1> user; ap_uint<1> last; -}; + }; +#endif struct eth_settings_t { uint64_t expected_packets; @@ -100,7 +107,6 @@ struct packet_header_t { ap_uint<8> jf_detector_type; ap_uint<8> jf_header_version_type; }; - typedef hls::stream AXI_STREAM; typedef hls::stream DATA_STREAM; diff --git a/actions/hls_udp_512/hw/write_data.cpp b/actions/hls_udp_512/hw/write_data.cpp index 1d7395f0d..46cea10d1 100644 --- a/actions/hls_udp_512/hw/write_data.cpp +++ b/actions/hls_udp_512/hw/write_data.cpp @@ -15,11 +15,11 @@ */ -#include "hls_udp.h" #include #include "ap_int.h" -#include "osnap_hls_if.h" -#include +//#include "osnap_hls_if.h" +//#include +#include "hls_udp.h" void write_data(DATA_STREAM &in, snap_membus_512_t *dout_gmem, uint64_t out_frame_buffer_addr) { data_packet_t packet_in; diff --git a/actions/scripts/create_run_hls_script.sh b/actions/scripts/create_run_hls_script.sh index 7079f0ff5..c30a1bb53 100755 --- a/actions/scripts/create_run_hls_script.sh +++ b/actions/scripts/create_run_hls_script.sh @@ -15,7 +15,10 @@ ## limitations under the License. ## -version=1.0 +version=1.1 +# 1.0 : Creation +# 1.1 : adding Vitis_hls support - March 2021 + program=`basename "$0"` # output formatting @@ -103,7 +106,9 @@ done shift $((OPTIND-1)) # now do something with $@ -#### TCL config script for vivado_hls ######################################### +if [ -z $HLS_VITIS_USED ]; then + printf " HLS_VITIS_USED is not set\n" >&2; + #### TCL config script for vivado_hls ######################################### cat <&2; + #### TCL config script for vitis_hls ######################################### +cat <> $log_file + add_files -fileset sim_1 -norecurse -scan_for_includes $ip_dir/ddr4sdram_ex/imports/ddr4_model.sv >> $log_file add_files -fileset sim_1 -norecurse -scan_for_includes $sim_dir/src/ddr4_dimm_ad9v3.sv >> $log_file set_property used_in_synthesis false [get_files $sim_dir/src/ddr4_dimm_ad9v3.sv] @@ -272,15 +277,18 @@ if { $eth_used == TRUE } { # Add HBM if { $hbm_used == TRUE } { - add_files -norecurse $ip_dir/hbm/hbm.srcs/sources_1/bd/hbm_top/hdl/hbm_top_wrapper.vhd >> $log_file + #add_files -norecurse $ip_dir/hbm/hbm.srcs/sources_1/bd/hbm_top/hdl/hbm_top_wrapper.vhd >> $log_file + add_files -norecurse $ip_dir/hbm/hbm.gen/sources_1/bd/hbm_top/hdl/hbm_top_wrapper.vhd >> $log_file if { $bram_used == TRUE } { puts " adding HBM-like block design (BRAM)" } else { # if BRAM model used replacing HBM do not add specific hbm init files puts " adding HBM block design" puts " adding HBM initialization files " - add_files -norecurse $hbm_ip_dir/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_1.mem - add_files -norecurse $hbm_ip_dir/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_0.mem + #add_files -norecurse $hbm_ip_dir/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_1.mem + #add_files -norecurse $hbm_ip_dir/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_0.mem + add_files -norecurse $ip_dir/hbm/hbm.gen/sources_1/bd/hbm_top/ip/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_1.mem + add_files -norecurse $ip_dir/hbm/hbm.gen/sources_1/bd/hbm_top/ip/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_0.mem update_ip_catalog >> $log_file } @@ -291,8 +299,10 @@ if { $hbm_used == TRUE } { #puts " adding HBM initialization files " # if BRAM model used to replace HBM then do not add specific hbm init files if { $bram_used != TRUE } { - import_files -fileset sim_1 -norecurse $hbm_ip_dir/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_sim_1.mem - import_files -fileset sim_1 -norecurse $hbm_ip_dir/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_sim_0.mem + #import_files -fileset sim_1 -norecurse $hbm_ip_dir/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_sim_1.mem + #import_files -fileset sim_1 -norecurse $hbm_ip_dir/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_sim_0.mem + import_files -fileset sim_1 -norecurse $ip_dir/hbm/hbm.gen/sources_1/bd/hbm_top/ip/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_sim_1.mem + import_files -fileset sim_1 -norecurse $ip_dir/hbm/hbm.gen/sources_1/bd/hbm_top/ip/hbm_top_hbm_0/hdl/rtl/xpm_internal_config_file_sim_0.mem } update_compile_order -fileset sim_1 >> $log_file } @@ -318,7 +328,7 @@ if { $unit_sim_used == "TRUE" } { if {$fpga_card == "BW250SOC"} { puts " adding Flash IP " - add_files $ip_dir/flash_ip_project/flash_ip_project.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd -norecurse >> $log_file + #add_files $ip_dir/flash_ip_project/flash_ip_project.srcs/sources_1/bd/design_1/hdl/design_1_wrapper.vhd -norecurse >> $log_file add_files -norecurse $ip_dir/flash_ip_project/flash_ip_project.srcs/sources_1/bd/design_1/design_1.bd >> $log_file export_ip_user_files -of_objects [get_files $ip_dir/flash_ip_project/flash_ip_project.srcs/sources_1/bd/design_1/design_1.bd] -lib_map_path [list {{ies=$root_dir/viv_project/framework.cache/compile_simlib/ies}}] -no_script -sync -force -quiet # puts " adding $fpga_card_dir/ip/qspi_mb.elf" diff --git a/hardware/setup/create_hbm.tcl b/hardware/setup/create_hbm.tcl index 968dc4800..c8c0792dc 100644 --- a/hardware/setup/create_hbm.tcl +++ b/hardware/setup/create_hbm.tcl @@ -39,20 +39,10 @@ set bd_name hbm_top # _______________________________________________________________________________ # In this file, we define all the logic to have independent 256MB/2Gb memories # each with an independent AXI interfaces which will be connected to the action -# Default is hbm_axi_if_num = 12 interfaces -# TO increase/decrease the number of memory needed, just look to #CHANGE_HBM_INTERFACES_NUMBER -# param and 1) change in menu the HBM_AXI_IF_NUM with a value between 1 and 32. -# and 2) set the right params enabling AXI and MC -# ------------------------------------------------------- -# If you modify the number of AXI interfaces, don't forget to modify also : -# actions/hls_hbm_memcopy/hw/hw_action_memcopy.cpp -# hardware/hdl/hls/action_wrapper.v -# hardware/hdl/core/framework_afu.v -# --> follow HBM names <-- +# The number of HBM interfaces is selected by the Kconfig menu +# It needs to be in sync with the param #define HBM_AXI_IF_NB which should be +# defined in actions/hls_hbm_memcopy_1024/hw/hw_action_hbm_memcopy_1024.cpp # _______________________________________________________________________________ -#CHANGE_HBM_INTERFACES_NUMBER -#set HBM_MEM_NUM 12 -##This number is now taken from the Kmenu => hbm_axi_if_num # Create HBM project create_project $prj_name $root_dir/ip/hbm -part $fpga_part -force >> $log_file @@ -110,6 +100,7 @@ set port [create_bd_port -dir I CRESETN] #LEFT stack is used for SNAP/CAPI2.0 since BSP/PSL logic is using right resources of the FPGA #RIGHT stack is used for OC-Accel/OCAPI3.0 since TLX/DLX logic is using left resources of the FPGA set cell [create_bd_cell -quiet -type ip -vlnv {xilinx.com:ip:hbm:*} hbm] + #create_bd_cell -type ip -vlnv xilinx.com:ip:hbm:1.0 hbm #Common params for the HBM not depending on the number of memories enabled # The reference clock provided to HBM is AXI clock @@ -127,8 +118,8 @@ set_property -dict [list \ CONFIG.USER_XSDB_INTF_EN {FALSE} \ ] $cell >> $log_file - -if { $hbm_axi_if_num < 16 } { +# if less or equal than 16 HBM then 1 stack used +if { $hbm_axi_if_num <= 16 } { set_property -dict [list \ CONFIG.USER_HBM_DENSITY {4GB} \ CONFIG.USER_HBM_STACK {1} \ @@ -143,6 +134,7 @@ if { $hbm_axi_if_num < 16 } { CONFIG.USER_SINGLE_STACK_SELECTION {LEFT} \ ] $cell >> $log_file } +# 2 stacks } else { set_property -dict [list \ CONFIG.USER_SINGLE_STACK_SELECTION {LEFT} \ @@ -277,7 +269,7 @@ connect_bd_net [get_bd_pins constant_1_zero/dout] [get_bd_pins hbm/APB_0_PWRITE] connect_bd_net [get_bd_pins refclk_bufg_apb_clk/BUFGCE_O] [get_bd_pins hbm/APB_0_PCLK] connect_bd_net [get_bd_pins ARESETN] [get_bd_pins hbm/APB_0_PRESET_N] -if { $hbm_axi_if_num > 15 } { +if { $hbm_axi_if_num > 16 } { connect_bd_net [get_bd_pins constant_1_zero/dout] [get_bd_pins hbm/APB_1_PENABLE] >> $log_file connect_bd_net [get_bd_pins constant_22_zero/dout] [get_bd_pins hbm/APB_1_PADDR] >> $log_file connect_bd_net [get_bd_pins constant_1_zero/dout] [get_bd_pins hbm/APB_1_PSEL] >> $log_file @@ -320,6 +312,9 @@ for {set i 0} {$i < $hbm_axi_if_num} {incr i} { CONFIG.REG_B {10} \ } $cell + + + #create the ports create_bd_intf_port -mode Slave -vlnv xilinx.com:interface:aximm_rtl:1.0 S_AXI_p$i\_HBM set_property -dict [list \ @@ -352,11 +347,21 @@ for {set i 0} {$i < $hbm_axi_if_num} {incr i} { if { $i < 10} { connect_bd_net [get_bd_pins ARESETN] [get_bd_pins hbm/AXI_0$i\_ARESET_N] connect_bd_net [get_bd_pins axi4_to_axi3_$i/aclk] [get_bd_pins hbm/AXI_0$i\_ACLK] - connect_bd_intf_net [get_bd_intf_pins axi_register_slice_$i\/M_AXI] [get_bd_intf_pins hbm/SAXI_0$i] + # AD9H7 cards require a different AXI name + if { (($fpga_card != "AD9H7" && $fpga_card != "AD9H335") && $vivadoVer >= "2020.2") } { + connect_bd_intf_net [get_bd_intf_pins axi_register_slice_$i\/M_AXI] [get_bd_intf_pins hbm/SAXI_0$i\_RT] + } else { + connect_bd_intf_net [get_bd_intf_pins axi_register_slice_$i\/M_AXI] [get_bd_intf_pins hbm/SAXI_0$i] + } } else { - connect_bd_net [get_bd_pins ARESETN] [get_bd_pins hbm/AXI_$i\_ARESET_N] - connect_bd_net [get_bd_pins axi4_to_axi3_$i/aclk] [get_bd_pins hbm/AXI_$i\_ACLK] - connect_bd_intf_net [get_bd_intf_pins axi_register_slice_$i\/M_AXI] [get_bd_intf_pins hbm/SAXI_$i] + connect_bd_net [get_bd_pins ARESETN] [get_bd_pins hbm/AXI_$i\_ARESET_N] + connect_bd_net [get_bd_pins axi4_to_axi3_$i/aclk] [get_bd_pins hbm/AXI_$i\_ACLK] + + if { (($fpga_card != "AD9H7" && $fpga_card != "AD9H335") && $vivadoVer >= "2020.2") } { + connect_bd_intf_net [get_bd_intf_pins axi_register_slice_$i\/M_AXI] [get_bd_intf_pins hbm/SAXI_$i\_RT] + } else { + connect_bd_intf_net [get_bd_intf_pins axi_register_slice_$i\/M_AXI] [get_bd_intf_pins hbm/SAXI_$i] + } } } #--------------------- end loop ------------------ @@ -364,7 +369,7 @@ for {set i 0} {$i < $hbm_axi_if_num} {incr i} { #This line need to be added after the loop since the S_AXI_p0_HBM_ACLK is not defined before connect_bd_net [get_bd_pins hbm/HBM_REF_CLK_0] [get_bd_pins S_AXI_p0_HBM_ACLK] connect_bd_net [get_bd_ports S_AXI_p0_HBM_ACLK] [get_bd_pins refclk_bufg_apb_clk/BUFGCE_I] -if { $hbm_axi_if_num > 15 } { +if { $hbm_axi_if_num > 16 } { connect_bd_net [get_bd_pins hbm/HBM_REF_CLK_1] [get_bd_pins S_AXI_p0_HBM_ACLK] } diff --git a/hardware/sim/run_sim b/hardware/sim/run_sim index 82376ea82..b0b108dc6 100755 --- a/hardware/sim/run_sim +++ b/hardware/sim/run_sim @@ -302,7 +302,10 @@ SIM_INIT='' # default init value for simulator SIM_ARG='' # -batch overrides -tcl VPI_OPT='libdpi.so' - SIM_ARG+=" -t xsrun.tcl" +#DEBUG 7/22 - add cd later so need to add path + #SIM_ARG+=" -t xsrun.tcl" # -tclbatch arg + SIM_ARG+=" -t $SNAP_ROOT/hardware/sim/xsrun.tcl" # -tclbatch arg + # SIM_ARG+=" -t xsrun.tcl +model_data+." # syntax errors if [ "$AET" == "1" ];then `sed -i "s/#source xsaet.tcl/ source xsaet.tcl/g" xsrun.tcl` # enable/uncomment AET generation in xsrun.tcl @@ -334,7 +337,15 @@ ##### call Simulator if [ "$SIMULATOR" == "irun" ]||[ "$SIMULATOR" == "xrun" ];then SIM_ARG+=" -r";fi echo "**** call simulator=$SIMULATOR $SIM_ARG $SIMTOP $SIM_PARM in background, wait for socket in $SIMULATOR.log->shim_host.dat"|tee -a sim.log & - $SIMULATOR $SIM_ARG $SIMTOP $SIM_PARM |tee -a sim.log & +#DEBUG 7/22 - add cd to remove the 2020.1 issue + if [ "$SIMULATOR" == "xsim" ];then + cd $SNAP_ROOT/hardware/sim/$SIMDIR; + $SIMULATOR $SIM_ARG $SIMTOP $SIM_PARM |tee -a $SIMOUT/sim.log & + cd $SIMOUT; + else + $SIMULATOR $SIM_ARG $SIMTOP $SIM_PARM |tee -a sim.log & + fi + SIMLOG_PID=$! # sim.log records 1st socket SIMLOG_PPID=`ps -ef|grep $SIMLOG_PID |grep tee |awk '{print $3}'` if [ "$SIMLOG_PPID" == "" ];then echo "could not start $SIMULATOR, did you successfully compile the model ?";TCRC=-1;fi diff --git a/scripts/Kconfig b/scripts/Kconfig index 0f8508123..15257f3fa 100644 --- a/scripts/Kconfig +++ b/scripts/Kconfig @@ -757,7 +757,7 @@ config ACTION_USER_CLOCK config HLS_CLOCK_PERIOD_CONSTRAINT prompt "The HLS clock period constraint used when C code (only used for hls action)" string - default "4ns" + default "5ns" range "1ns" "20ns" help The HLS clock period constraint in "ns" used when C code is compiled to rtl, diff --git a/scripts/snap_cfg b/scripts/snap_cfg index 8fbef975d..9a79e5b5d 100755 --- a/scripts/snap_cfg +++ b/scripts/snap_cfg @@ -135,6 +135,17 @@ if [ $Vivado_Major_release -gt 2019 ] && [ $ethernet_used != "" ]; then echo "SNAP_CFLAGS += \"-DCONFIG_ENABLE_EMAC_V3_1=TRUE\"" >> $snap_config_cflags fi +#Starting with Vivado 2020.2 vivado_hls is replaced by vitis_hls +hls_support=`grep HLS_SUPPORT $snap_config|grep TRUE` +Vivado_Major_release=`vivado -version |grep Vivado| cut -d'(' -f1|tr -d "Vivado "|cut -d '.' -f1` +Vivado_Minor_release=`vivado -version |grep Vivado| cut -d'(' -f1|tr -d "Vivado "|cut -d '.' -f2` +if [ $Vivado_Major_release -ge 2020 ] && [ $hls_support != "" ]; then + if [ $Vivado_Minor_release -gt 1 ]; then + echo "export HLS_VITIS_USED=TRUE" >> $snap_config_sh + echo "SNAP_CFLAGS += \"-DCONFIG_HLS_VITIS_USED=TRUE\"" >> $snap_config_cflags + fi +fi + echo "Generation of SNAP config files done." echo diff --git a/snap_env b/snap_env index 94c5dce66..a7e152aae 100755 --- a/snap_env +++ b/snap_env @@ -92,6 +92,19 @@ while [ -z "$SETUP_DONE" ]; do echo "Vivado version is set to: `vivado -version|head -n1`" fi +VIVADO_RELEASE=`vivado -version | grep Vivado | cut -d '(' -f1 | tr -d "Vivado "` +VIVADO_MAJOR_RELEASE=`echo ${VIVADO_RELEASE} |cut -d '.' -f1` +VIVADO_MINOR_RELEASE=`echo ${VIVADO_RELEASE} |cut -d '.' -f2` +if [ "$VIVADO_MAJOR_RELEASE" -ge "2020" ]; then + if [ "$VIVADO_MINOR_RELEASE" -gt "1" ]; then + echo "HLS tool is set to: `vitis_hls -version |head -n1`" + else + #echo "Using Vivado HLS (could use Vitis HLS)" + echo "HLS tool is set to: `vivado_hls -version |head -n1`" + fi +else + echo "HLS tool is set to: `vivado_hls -version |head -n1`" +fi ####### checking path to OCSE (only if simulation is enabled) # Note: SIMULATOR is defined via snap_config