arm: hisilicon: add hi3516cv100 SoC support (DT + mach-hibvt)#46
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Adds device-tree, DEMB board file, mach-hibvt entry, and ARCH_HI3516CV100 Kconfig for the Hi3516CV100 SoC family (V1 generation, ARM926EJ-S / ARMv5TE, the parent of the Hi3516CV200 family already supported in upstream-patches). cv100 is architecturally a strict subset of cv200 — same single ARM926EJ-S core, same SP804 dual-timers, same PL011 UARTs and PL022 SPI controllers, same hisi-femac ethernet, same FMC flash controller, same pinctrl-single pinmux block, all at identical MMIO addresses. The relevant difference for kernel boot is the VIC base — 0x10140000 on cv100 vs 0x100d0000 on cv200 — which is overridden in the cv100 dtsi via a label-based reference (&vic), reusing cv200's full DT scaffold via #include "hi3516cv200.dtsi". The CRG driver (drivers/clk/hisilicon/clk-hi3516cv200.c) handles cv100 unchanged — cv100's CRG register layout is a strict subset of cv200's (cv200 added a handful of extra clock gates for new peripherals that cv100 doesn't have). ARCH_HI3516CV100 just `select COMMON_CLK_HI3516CV200` and the existing "hisilicon,hi3518ev20x-clock" compatible matches both SoCs. The mach-hibvt entry reuses mach-hi3518ev20x.c (the cv200 mach file) verbatim, just adding "hisilicon,hi3516cv100" to its dt_compat array and the cv100 IO header to mach/io.h. HI_ZRELADDR is 0x80008000 (same as the rest of the V1/V2 ARMv5TE family). Sibling V1 SoCs (die-identical per qemu-hisilicon machine model decoding) can attach to this dtsi as overlays: Hi3518AV100, Hi3518CV100, Hi3518EV100. cv100's V1 single-controller register-poll i2c hardware is not driver-compatible with cv200's HiBVT i2c — the inherited i2c_bus0/1/2 DT nodes are explicitly marked disabled in hi3516cv100.dtsi. Boot does not depend on them; userspace can drive the sensor i2c MMIO directly via a separate kernel module if needed. Tested under qemu-system-arm -M hi3516cv100 with the OpenIPC userspace: - Boots to login prompt cleanly, no Oops/panic/BUG - hisi-femac eth0 link UP at 100Mbps/Full, DHCP from SLIRP obtains 10.0.2.15, ICMP echo to gateway 10.0.2.2 succeeds (~17ms)
This was referenced May 24, 2026
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Summary
Adds device-tree, DEMB board file, mach-hibvt entry, and
ARCH_HI3516CV100Kconfig for the Hi3516CV100 SoC family — V1 generation (ARM926EJ-S / ARMv5TE), the parent of the Hi3516CV200 family that #43 added.cv100 is architecturally a strict subset of cv200 — same single ARM926EJ-S core, SP804 dual-timers, PL011 UARTs, PL022 SPI, hisi-femac, FMC, pinctrl-single, all at identical MMIO addresses. The only kernel-relevant difference is the VIC base:
0x10140000(cv100) vs0x100d0000(cv200). The cv100 dtsi#include "hi3516cv200.dtsi"and overrides&vic { reg = <0x10140000 0x1000>; };.Reuses the existing
COMMON_CLK_HI3516CV200driver verbatim — cv100's CRG register layout is a strict subset of cv200's.ARCH_HI3516CV100justselect COMMON_CLK_HI3516CV200; the existing"hisilicon,hi3518ev20x-clock"compatible matches both SoCs.The mach-hibvt entry reuses
mach-hi3518ev20x.c(the cv200 mach file) verbatim — just adding"hisilicon,hi3516cv100"to itsdt_compat[]array and the cv100 entry tomach/io.h.HI_ZRELADDR = 0x80008000matches the rest of the V1/V2 ARMv5TE family.Sibling V1 SoCs (die-identical per qemu-hisilicon machine model decoding) can attach to this dtsi as overlays: Hi3518AV100, Hi3518CV100, Hi3518EV100.
cv100's V1 single-controller register-poll i2c hardware is not driver-compatible with cv200's HiBVT i2c — the inherited i2c_bus0/1/2 DT nodes are explicitly marked
disabledin hi3516cv100.dtsi. Boot does not depend on them; userspace can drive the sensor i2c MMIO directly via a separate kernel module if needed.Test plan
Tested under `qemu-system-arm -M hi3516cv100` with the OpenIPC userspace + a custom `hi3516cv100_neo` firmware build (sibling PR coming to OpenIPC/firmware + OpenIPC/openhisilicon):
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