From dd66dfbf7c6c91fb8daf776c5e113414f94e1401 Mon Sep 17 00:00:00 2001
From: Zenithal <i@zenithal.me>
Date: Sun, 3 Apr 2022 00:20:50 +0800
Subject: [PATCH] Instructions: Separate NMI insts and CSRs

Rocket already implemented NMI in #2711,
however, riscv-opcodes currently does not have NMI
as it is a WIP (See https://github.com/riscv/riscv-opcodes/pull/67)

To avoid generating Instructions.scala from a patched riscv-opcodes,
putting NMI related insts/CSRs into CustomInstructions is reasonable.
---
 src/main/scala/rocket/CSR.scala               | 17 ++++++++--------
 .../scala/rocket/CustomInstructions.scala     | 20 +++++++++++++++++++
 2 files changed, 29 insertions(+), 8 deletions(-)

diff --git a/src/main/scala/rocket/CSR.scala b/src/main/scala/rocket/CSR.scala
index 48463b2cdad..beaa797235e 100644
--- a/src/main/scala/rocket/CSR.scala
+++ b/src/main/scala/rocket/CSR.scala
@@ -13,6 +13,7 @@ import freechips.rocketchip.util._
 import freechips.rocketchip.util.property
 import scala.collection.mutable.LinkedHashMap
 import Instructions._
+import CustomInstructions._
 
 class MStatus extends Bundle {
   // not truly part of mstatus, but convenient
@@ -634,10 +635,10 @@ class CSRFile(
   read_mnstatus.mpv := reg_mnstatus.mpv
   read_mnstatus.mie := reg_rnmie
   val nmi_csrs = if (!usingNMI) LinkedHashMap() else LinkedHashMap[Int,Bits](
-    CSRs.mnscratch -> reg_mnscratch,
-    CSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen),
-    CSRs.mncause -> reg_mncause,
-    CSRs.mnstatus -> read_mnstatus.asUInt)
+    CustomCSRs.mnscratch -> reg_mnscratch,
+    CustomCSRs.mnepc -> readEPC(reg_mnepc).sextTo(xLen),
+    CustomCSRs.mncause -> reg_mncause,
+    CustomCSRs.mnstatus -> read_mnstatus.asUInt)
 
   val context_csrs = LinkedHashMap[Int,Bits]() ++
     reg_mcontext.map(r => CSRs.mcontext -> r) ++
@@ -1212,10 +1213,10 @@ class CSRFile(
 
     if (usingNMI) {
       val new_mnstatus = new MNStatus().fromBits(wdata)
-      when (decoded_addr(CSRs.mnscratch)) { reg_mnscratch := wdata }
-      when (decoded_addr(CSRs.mnepc))     { reg_mnepc := formEPC(wdata) }
-      when (decoded_addr(CSRs.mncause))   { reg_mncause := wdata & UInt((BigInt(1) << (xLen-1)) + BigInt(3)) }
-      when (decoded_addr(CSRs.mnstatus))  {
+      when (decoded_addr(CustomCSRs.mnscratch)) { reg_mnscratch := wdata }
+      when (decoded_addr(CustomCSRs.mnepc))     { reg_mnepc := formEPC(wdata) }
+      when (decoded_addr(CustomCSRs.mncause))   { reg_mncause := wdata & UInt((BigInt(1) << (xLen-1)) + BigInt(3)) }
+      when (decoded_addr(CustomCSRs.mnstatus))  {
         reg_mnstatus.mpp := legalizePrivilege(new_mnstatus.mpp)
         reg_mnstatus.mpv := usingHypervisor && new_mnstatus.mpv
         reg_rnmie := reg_rnmie | new_mnstatus.mie  // mnie bit settable but not clearable from software
diff --git a/src/main/scala/rocket/CustomInstructions.scala b/src/main/scala/rocket/CustomInstructions.scala
index a89c901b011..1f1f41469aa 100644
--- a/src/main/scala/rocket/CustomInstructions.scala
+++ b/src/main/scala/rocket/CustomInstructions.scala
@@ -6,7 +6,27 @@ package freechips.rocketchip.rocket
 import Chisel._
 
 object CustomInstructions {
+  def MNRET              = BitPat("b01110000001000000000000001110011")
   def CEASE              = BitPat("b00110000010100000000000001110011")
   def CFLUSH_D_L1        = BitPat("b111111000000?????000000001110011")
   def CDISCARD_D_L1      = BitPat("b111111000010?????000000001110011")
 }
+
+object CustomCSRs {
+  val mnscratch = 0x350
+  val mnepc = 0x351
+  val mncause = 0x352
+  val mnstatus = 0x353
+  val all = {
+    val res = collection.mutable.ArrayBuffer[Int]()
+    res += mnscratch
+    res += mnepc
+    res += mncause
+    res += mnstatus
+    res.toArray
+  }
+  val all32 = {
+    val res = collection.mutable.ArrayBuffer(all:_*)
+    res.toArray
+  }
+}