lcb [riscv64]: Materialize constants larger than instruction's bit width #129
Description
To materialize constants for riscv32, you need two instructions: LUI and ADDI. However, riscv64 has to materialize integers of the size 64 while the instructions LUI and ADDI have only a total bit width of 32. This is problem and needs to be handled by constant sequences. The problem is, however, that constant sequences need to be able to handle arbitrary expressions for bit manipulation.
For example, imagine you would like to load the constant 0x123456789ABCDEF0.
The following instructions (in pseudo code) have to be emitted to construct such a constant.
Val = 0x123456789ABCDEF0
LUI V, imm = hi(Val >> 32)
ADDI V, V, imm = lo( Val >> 32)
SLLI V, V, 16
ORI V, V, imm = (Val >> 16) as Uint<12>
SLLI V, V, 16
ORI V, V, imm = Val as Uint<12>
which correspondents to
LUI V, 0x12345
ADDI V,V, 0x6789
SLLI V, V, 16
ORI V, V, 0xABCD
SLLI V, V, 16
ORI V, V, 0xDEF0
It is not clear how to define such a constant sequence, since we would need to define the ORI's imm as variant kinds to be handled currently.
constant sequence( rd : Bits<5>, val : UInt<64> ) =
{
LUI { rd = rd, imm = hi( (val >> 32) as Bits<32> ) }
SLLI { rd = rd, rs1 = rd, sft = 16 }
ADDI { rd = rd, rs1 = rd, imm = lo(val >> 32) }
SLLI { rd = rd, rs1 = rd, sft = 16 }
ORI { rd = rd, rs1 = rd, imm = shift(val, 32) }
SLLI { rd = rd, rs1 = rd, sft = 16 }
ORI { rd = rd, rs1 = rd, imm = shift(val, 16) }
}