From 38f78b5dba91bbf073216eed3a080d3af4b9aeef Mon Sep 17 00:00:00 2001 From: xiaofeibao-xjtu <59299641+xiaofeibao-xjtu@users.noreply.github.com> Date: Wed, 10 Jul 2024 17:21:29 +0800 Subject: [PATCH] Backend&MemBlock: feedback use sqidx instead of robidx and uopidx for fix timing (#3172) --- src/main/scala/xiangshan/Bundle.scala | 2 +- src/main/scala/xiangshan/backend/Backend.scala | 7 ++++++- .../xiangshan/backend/datapath/DataPath.scala | 5 ++++- .../scala/xiangshan/backend/issue/Entries.scala | 14 ++++++-------- .../xiangshan/backend/issue/EntryBundles.scala | 3 ++- .../xiangshan/backend/issue/IssueBlockParams.scala | 2 ++ .../scala/xiangshan/backend/issue/IssueQueue.scala | 9 +++++++-- src/main/scala/xiangshan/mem/MemCommon.scala | 3 --- .../scala/xiangshan/mem/pipeline/AtomicsUnit.scala | 1 + .../scala/xiangshan/mem/pipeline/HybridUnit.scala | 11 ----------- .../scala/xiangshan/mem/pipeline/LoadUnit.scala | 14 ++------------ .../scala/xiangshan/mem/pipeline/StoreUnit.scala | 4 ++-- .../scala/xiangshan/mem/vector/VMergeBuffer.scala | 2 +- .../scala/xiangshan/mem/vector/VSegmentUnit.scala | 2 +- 14 files changed, 35 insertions(+), 44 deletions(-) diff --git a/src/main/scala/xiangshan/Bundle.scala b/src/main/scala/xiangshan/Bundle.scala index cc5ef87e7e..7e1a89390e 100644 --- a/src/main/scala/xiangshan/Bundle.scala +++ b/src/main/scala/xiangshan/Bundle.scala @@ -416,7 +416,7 @@ class RSFeedback(isVector: Boolean = false)(implicit p: Parameters) extends XSBu val flushState = Bool() val sourceType = RSFeedbackType() val dataInvalidSqIdx = new SqPtr - val uopIdx = OptionWrapper(isVector, UopIdx()) + val sqIdx = new SqPtr } class MemRSFeedbackIO(isVector: Boolean = false)(implicit p: Parameters) extends XSBundle { diff --git a/src/main/scala/xiangshan/backend/Backend.scala b/src/main/scala/xiangshan/backend/Backend.scala index 5aeea5ead3..c860f694f1 100644 --- a/src/main/scala/xiangshan/backend/Backend.scala +++ b/src/main/scala/xiangshan/backend/Backend.scala @@ -540,6 +540,7 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends memScheduler.io.loadFinalIssueResp(i)(j).bits.resp := RespType.block memScheduler.io.loadFinalIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx memScheduler.io.loadFinalIssueResp(i)(j).bits.uopIdx.foreach(_ := toMem(i)(j).bits.vpu.get.vuopIdx) + memScheduler.io.loadFinalIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) } NewPipelineConnect( @@ -556,6 +557,7 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends memScheduler.io.memAddrIssueResp(i)(j).valid := toMem(i)(j).fire && FuType.isLoad(toMem(i)(j).bits.fuType) memScheduler.io.memAddrIssueResp(i)(j).bits.fuType := toMem(i)(j).bits.fuType memScheduler.io.memAddrIssueResp(i)(j).bits.robIdx := toMem(i)(j).bits.robIdx + memScheduler.io.memAddrIssueResp(i)(j).bits.sqIdx.foreach(_ := toMem(i)(j).bits.sqIdx.get) memScheduler.io.memAddrIssueResp(i)(j).bits.resp := RespType.success // for load inst, firing at toMem means issuing successfully } @@ -566,9 +568,12 @@ class BackendImp(override val wrapper: Backend)(implicit p: Parameters) extends resp.bits.fuType := toMem(i)(j).bits.fuType resp.bits.robIdx := toMem(i)(j).bits.robIdx resp.bits.uopIdx.get := toMem(i)(j).bits.vpu.get.vuopIdx + resp.bits.sqIdx.get := toMem(i)(j).bits.sqIdx.get resp.bits.resp := RespType.success } - dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) + if (backendParams.debugEn){ + dontTouch(memScheduler.io.vecLoadIssueResp(i)(j)) + } } } } diff --git a/src/main/scala/xiangshan/backend/datapath/DataPath.scala b/src/main/scala/xiangshan/backend/datapath/DataPath.scala index 8991e9675b..41972a4718 100644 --- a/src/main/scala/xiangshan/backend/datapath/DataPath.scala +++ b/src/main/scala/xiangshan/backend/datapath/DataPath.scala @@ -14,11 +14,12 @@ import xiangshan.backend.Bundles._ import xiangshan.backend.decode.ImmUnion import xiangshan.backend.datapath.DataConfig._ import xiangshan.backend.datapath.RdConfig._ -import xiangshan.backend.issue.{ImmExtractor, IntScheduler, MemScheduler, VfScheduler, FpScheduler} +import xiangshan.backend.issue.{FpScheduler, ImmExtractor, IntScheduler, MemScheduler, VfScheduler} import xiangshan.backend.issue.EntryBundles._ import xiangshan.backend.regfile._ import xiangshan.backend.PcToDataPathIO import xiangshan.backend.fu.FuType.is0latency +import xiangshan.mem.SqPtr class DataPath(params: BackendParams)(implicit p: Parameters) extends LazyModule { override def shouldBeInlined: Boolean = false @@ -547,6 +548,7 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params og0resp.valid := og0FailedVec2(iqIdx)(iuIdx) og0resp.bits.robIdx := fromIQ(iqIdx)(iuIdx).bits.common.robIdx og0resp.bits.uopIdx.foreach(_ := fromIQ(iqIdx)(iuIdx).bits.common.vpu.get.vuopIdx) + og0resp.bits.sqIdx.foreach(_ := 0.U.asTypeOf(new SqPtr)) og0resp.bits.resp := RespType.block og0resp.bits.fuType := fromIQ(iqIdx)(iuIdx).bits.common.fuType @@ -555,6 +557,7 @@ class DataPathImp(override val wrapper: DataPath)(implicit p: Parameters, params og1resp.valid := s1_toExuValid(iqIdx)(iuIdx) og1resp.bits.robIdx := s1_toExuData(iqIdx)(iuIdx).robIdx og1resp.bits.uopIdx.foreach(_ := s1_toExuData(iqIdx)(iuIdx).vpu.get.vuopIdx) + og1resp.bits.sqIdx.foreach(_ := 0.U.asTypeOf(new SqPtr)) // respType: fuIdle ->IQ entry clear // fuUncertain ->IQ entry no action // fuBusy ->IQ entry issued set false, then re-issue diff --git a/src/main/scala/xiangshan/backend/issue/Entries.scala b/src/main/scala/xiangshan/backend/issue/Entries.scala index 9e43eca280..d879c4e79f 100644 --- a/src/main/scala/xiangshan/backend/issue/Entries.scala +++ b/src/main/scala/xiangshan/backend/issue/Entries.scala @@ -85,7 +85,7 @@ class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule val fuTypeVec = Wire(Vec(params.numEntries, FuType())) val isFirstIssueVec = Wire(Vec(params.numEntries, Bool())) val issueTimerVec = Wire(Vec(params.numEntries, UInt(2.W))) - val uopIdxVec = OptionWrapper(params.isVecMemIQ, Wire(Vec(params.numEntries, UopIdx()))) + val sqIdxVec = OptionWrapper(params.needFeedBackSqIdx, Wire(Vec(params.numEntries, new SqPtr()))) //src status val dataSourceVec = Wire(Vec(params.numEntries, Vec(params.numRegSrc, DataSource()))) val loadDependencyVec = Wire(Vec(params.numEntries, Vec(LoadPipelineWidth, UInt(LoadDependencyWidth.W)))) @@ -268,13 +268,13 @@ class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule } //issueRespVec - if (params.isVecMemIQ) { + if (params.needFeedBackSqIdx) { // vector memory IQ - issueRespVec.lazyZip(robIdxVec.lazyZip(uopIdxVec.get)).lazyZip(issueTimerVec.lazyZip(deqPortIdxReadVec)).foreach { case (issueResp, (robIdx, uopIdx), (issueTimer, deqPortIdx)) => + issueRespVec.lazyZip(sqIdxVec.get).lazyZip(issueTimerVec.lazyZip(deqPortIdxReadVec)).foreach { case (issueResp, sqIdx, (issueTimer, deqPortIdx)) => val respInDatapath = resps(issueTimer(0))(deqPortIdx) val respAfterDatapath = Wire(chiselTypeOf(respInDatapath)) val hitRespsVec = VecInit(memEtyResps.map(x => - x.valid && x.bits.robIdx === robIdx && x.bits.uopIdx.get === uopIdx + x.valid && (x.bits.sqIdx.get === sqIdx) ).toSeq) respAfterDatapath.valid := hitRespsVec.reduce(_ | _) respAfterDatapath.bits := (if (memEtyResps.size == 1) memEtyResps.head.bits @@ -406,7 +406,6 @@ class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule io.compEntryEnqSelVec.foreach(_ := finalCompTransSelVec.get.zip(compEnqVec.get).map(x => x._1 & Fill(CompEntryNum, x._2.valid))) io.othersEntryEnqSelVec.foreach(_ := finalOthersTransSelVec.get.zip(enqEntryTransVec).map(x => x._1 & Fill(OthersEntryNum, x._2.valid))) io.robIdx.foreach(_ := robIdxVec) - io.uopIdx.foreach(_ := uopIdxVec.get) def EntriesConnect(in: CommonInBundle, out: CommonOutBundle, entryIdx: Int) = { @@ -439,8 +438,8 @@ class Entries(implicit p: Parameters, params: IssueBlockParams) extends XSModule if (params.hasIQWakeUp) { srcWakeUpL1ExuOHVec.get(entryIdx) := out.srcWakeUpL1ExuOH.get } - if (params.isVecMemIQ) { - uopIdxVec.get(entryIdx) := out.uopIdx.get + if (params.isVecMemIQ || params.isStAddrIQ) { + sqIdxVec.get(entryIdx) := out.entry.bits.payload.sqIdx } entryInValidVec(entryIdx) := out.entryInValid entryOutDeqValidVec(entryIdx) := out.entryOutDeqValid @@ -576,7 +575,6 @@ class EntriesIO(implicit p: Parameters, params: IssueBlockParams) extends XSBund val resp = Vec(params.numDeq, Flipped(ValidIO(new EntryDeqRespBundle))) }) val robIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, new RobPtr))) - val uopIdx = OptionWrapper(params.isVecMemIQ, Output(Vec(params.numEntries, UopIdx()))) // trans val simpEntryDeqSelVec = OptionWrapper(params.hasCompAndSimp, Vec(params.numEnq, Input(UInt(params.numSimp.W)))) diff --git a/src/main/scala/xiangshan/backend/issue/EntryBundles.scala b/src/main/scala/xiangshan/backend/issue/EntryBundles.scala index c2cdfacbe6..180992fc1b 100644 --- a/src/main/scala/xiangshan/backend/issue/EntryBundles.scala +++ b/src/main/scala/xiangshan/backend/issue/EntryBundles.scala @@ -60,11 +60,12 @@ object EntryBundles extends HasCircularQueuePtrHelper { val numLsElem = NumLsElem() } - class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends Bundle { + class EntryDeqRespBundle(implicit p: Parameters, params: IssueBlockParams) extends XSBundle { val robIdx = new RobPtr val resp = RespType() val fuType = FuType() val uopIdx = OptionWrapper(params.isVecMemIQ, Output(UopIdx())) + val sqIdx = OptionWrapper(params.needFeedBackSqIdx, new SqPtr()) } object RespType { diff --git a/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala b/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala index 4f253ff5e3..67b7d02e8c 100644 --- a/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala +++ b/src/main/scala/xiangshan/backend/issue/IssueBlockParams.scala @@ -61,6 +61,8 @@ case class IssueBlockParams( def isVecMemIQ: Boolean = isVecLduIQ || isVecStuIQ + def needFeedBackSqIdx: Boolean = isVecMemIQ || isStAddrIQ + def numExu: Int = exuBlockParams.count(!_.fakeUnit) def numIntSrc: Int = exuBlockParams.map(_.numIntSrc).max diff --git a/src/main/scala/xiangshan/backend/issue/IssueQueue.scala b/src/main/scala/xiangshan/backend/issue/IssueQueue.scala index 3380e28d38..e5eab24b82 100644 --- a/src/main/scala/xiangshan/backend/issue/IssueQueue.scala +++ b/src/main/scala/xiangshan/backend/issue/IssueQueue.scala @@ -553,6 +553,7 @@ class IssueQueueImp(override val wrapper: IssueQueue)(implicit p: Parameters, va deqResp.valid := finalDeqSelValidVec(i) deqResp.bits.resp := RespType.success deqResp.bits.robIdx := DontCare + deqResp.bits.sqIdx.foreach(_ := DontCare) deqResp.bits.fuType := deqBeforeDly(i).bits.common.fuType deqResp.bits.uopIdx.foreach(_ := DontCare) } @@ -1048,6 +1049,7 @@ class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Paramet entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx + slowResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx) slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) slowResp.bits.fuType := DontCare } @@ -1055,6 +1057,7 @@ class IssueQueueMemAddrImp(override val wrapper: IssueQueue)(implicit p: Paramet entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx + fastResp.bits.sqIdx.foreach( _ := memIO.feedbackIO(i).feedbackFast.bits.sqIdx) fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) fastResp.bits.fuType := DontCare } @@ -1126,17 +1129,19 @@ class IssueQueueVecMemImp(override val wrapper: IssueQueue)(implicit p: Paramete entries.io.fromMem.get.slowResp.zipWithIndex.foreach { case (slowResp, i) => slowResp.valid := memIO.feedbackIO(i).feedbackSlow.valid slowResp.bits.robIdx := memIO.feedbackIO(i).feedbackSlow.bits.robIdx + slowResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.sqIdx slowResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackSlow.bits.hit, RespType.success, RespType.block) slowResp.bits.fuType := DontCare - slowResp.bits.uopIdx.get := memIO.feedbackIO(i).feedbackSlow.bits.uopIdx.get + slowResp.bits.uopIdx.get := DontCare } entries.io.fromMem.get.fastResp.zipWithIndex.foreach { case (fastResp, i) => fastResp.valid := memIO.feedbackIO(i).feedbackFast.valid fastResp.bits.robIdx := memIO.feedbackIO(i).feedbackFast.bits.robIdx + fastResp.bits.sqIdx.get := memIO.feedbackIO(i).feedbackFast.bits.sqIdx fastResp.bits.resp := Mux(memIO.feedbackIO(i).feedbackFast.bits.hit, RespType.success, RespType.block) fastResp.bits.fuType := DontCare - fastResp.bits.uopIdx.get := memIO.feedbackIO(i).feedbackFast.bits.uopIdx.get + fastResp.bits.uopIdx.get := DontCare } entries.io.vecMemIn.get.sqDeqPtr := memIO.sqDeqPtr.get diff --git a/src/main/scala/xiangshan/mem/MemCommon.scala b/src/main/scala/xiangshan/mem/MemCommon.scala index 7acd86ca82..2eaae6d24f 100644 --- a/src/main/scala/xiangshan/mem/MemCommon.scala +++ b/src/main/scala/xiangshan/mem/MemCommon.scala @@ -93,7 +93,6 @@ class LsPipelineBundle(implicit p: Parameters) extends XSBundle val af = Bool() val mmio = Bool() val atomic = Bool() - val rsIdx = UInt(log2Up(MemIQSizeMax).W) val forwardMask = Vec(VLEN/8, Bool()) val forwardData = Vec(VLEN/8, UInt(8.W)) @@ -166,7 +165,6 @@ class LdPrefetchTrainBundle(implicit p: Parameters) extends LsPipelineBundle { if (latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack if (latch) af := RegEnable(input.af, enable) else af := input.af if (latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio - if (latch) rsIdx := RegEnable(input.rsIdx, enable) else rsIdx := input.rsIdx if (latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask if (latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData if (latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch @@ -242,7 +240,6 @@ class LqWriteBundle(implicit p: Parameters) extends LsPipelineBundle { if(latch) ptwBack := RegEnable(input.ptwBack, enable) else ptwBack := input.ptwBack if(latch) mmio := RegEnable(input.mmio, enable) else mmio := input.mmio if(latch) atomic := RegEnable(input.atomic, enable) else atomic := input.atomic - if(latch) rsIdx := RegEnable(input.rsIdx, enable) else rsIdx := input.rsIdx if(latch) forwardMask := RegEnable(input.forwardMask, enable) else forwardMask := input.forwardMask if(latch) forwardData := RegEnable(input.forwardData, enable) else forwardData := input.forwardData if(latch) isPrefetch := RegEnable(input.isPrefetch, enable) else isPrefetch := input.isPrefetch diff --git a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala index 56adf9f5b2..6540036f01 100644 --- a/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala +++ b/src/main/scala/xiangshan/mem/pipeline/AtomicsUnit.scala @@ -127,6 +127,7 @@ class AtomicsUnit(implicit p: Parameters) extends XSModule io.feedbackSlow.valid := GatedValidRegNext(GatedValidRegNext(io.in.valid)) io.feedbackSlow.bits.hit := true.B io.feedbackSlow.bits.robIdx := RegEnable(io.in.bits.uop.robIdx, io.in.valid) + io.feedbackSlow.bits.sqIdx := RegEnable(io.in.bits.uop.sqIdx, io.in.valid) io.feedbackSlow.bits.flushState := DontCare io.feedbackSlow.bits.sourceType := DontCare io.feedbackSlow.bits.dataInvalidSqIdx := DontCare diff --git a/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala b/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala index 285241c1ad..b9ef45767b 100644 --- a/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala +++ b/src/main/scala/xiangshan/mem/pipeline/HybridUnit.scala @@ -168,7 +168,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule val s0_mask = Wire(UInt((VLEN/8).W)) val s0_uop = Wire(new DynInst) val s0_has_rob_entry = Wire(Bool()) - val s0_rsIdx = Wire(UInt(log2Up(MemIQSizeMax).W)) val s0_mshrid = Wire(UInt()) val s0_try_l2l = Wire(Bool()) val s0_rep_carry = Wire(new ReplayCarry(nWays)) @@ -352,7 +351,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule s0_uop := 0.U.asTypeOf(new DynInst) s0_try_l2l := false.B s0_has_rob_entry := false.B - s0_rsIdx := 0.U s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) s0_mshrid := 0.U s0_isFirstIssue := false.B @@ -373,7 +371,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule s0_has_rob_entry := src.hasROBEntry s0_rep_carry := src.rep_info.rep_carry s0_mshrid := src.rep_info.mshr_id - s0_rsIdx := src.rsIdx s0_isFirstIssue := false.B s0_fast_rep := true.B s0_ld_rep := src.isLoadReplay @@ -390,7 +387,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule s0_uop := src.uop s0_try_l2l := false.B s0_has_rob_entry := true.B - s0_rsIdx := src.rsIdx s0_rep_carry := src.replayCarry s0_mshrid := src.mshrid s0_isFirstIssue := false.B @@ -409,7 +405,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule s0_uop := DontCare s0_try_l2l := false.B s0_has_rob_entry := false.B - s0_rsIdx := 0.U s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) s0_mshrid := 0.U s0_isFirstIssue := false.B @@ -428,7 +423,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule s0_uop := src.uop s0_try_l2l := false.B s0_has_rob_entry := true.B - s0_rsIdx := src.iqIdx s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) s0_mshrid := 0.U s0_isFirstIssue := true.B @@ -448,7 +442,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule s0_uop := src.uop s0_try_l2l := false.B s0_has_rob_entry := true.B - s0_rsIdx := 0.U s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) s0_mshrid := 0.U // s0_isFirstIssue := src.isFirstIssue @@ -476,7 +469,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule // we dont care s0_isFirstIssue and s0_rsIdx and s0_sqIdx in S0 when trying pointchasing // because these signals will be updated in S1 s0_has_rob_entry := false.B - s0_rsIdx := 0.U s0_mshrid := 0.U s0_rep_carry := 0.U.asTypeOf(s0_rep_carry.cloneType) s0_isFirstIssue := true.B @@ -516,7 +508,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule // accept load flow if dcache ready (tlb is always ready) // TODO: prefetch need writeback to loadQueueFlag s0_out := DontCare - s0_out.rsIdx := s0_rsIdx s0_out.vaddr := s0_vaddr s0_out.mask := s0_mask s0_out.uop := s0_uop @@ -695,7 +686,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule s1_out.paddr := s1_paddr_dup_lsu s1_out.tlbMiss := s1_tlb_miss s1_out.ptwBack := io.tlb.resp.bits.ptwBack - s1_out.rsIdx := s1_in.rsIdx s1_out.rep_info.debug := s1_in.uop.debugInfo s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf s1_out.lateKill := s1_late_kill @@ -751,7 +741,6 @@ class HybridUnit(implicit p: Parameters) extends XSModule s1_cancel_ptr_chasing := s1_addr_mismatch || s1_addr_misaligned || s1_ptr_chasing_canceled s1_in.uop := io.lsin.bits.uop - s1_in.rsIdx := io.lsin.bits.iqIdx s1_in.isFirstIssue := io.lsin.bits.isFirstIssue s1_vaddr_lo := s1_ptr_chasing_vaddr(5, 0) s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) diff --git a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala index 235c1c2c97..03f99dc872 100644 --- a/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala +++ b/src/main/scala/xiangshan/mem/pipeline/LoadUnit.scala @@ -210,7 +210,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule val uop = new DynInst val try_l2l = Bool() val has_rob_entry = Bool() - val rsIdx = UInt(log2Up(MemIQSizeMax).W) val rep_carry = new ReplayCarry(nWays) val mshrid = UInt(log2Up(cfg.nMissEntries).W) val isFirstIssue = Bool() @@ -421,7 +420,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule out.has_rob_entry := src.hasROBEntry out.rep_carry := src.rep_info.rep_carry out.mshrid := src.rep_info.mshr_id - out.rsIdx := src.rsIdx out.isFirstIssue := false.B out.fast_rep := true.B out.ld_rep := src.isLoadReplay @@ -454,7 +452,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule out.uop := src.uop out.try_l2l := false.B out.has_rob_entry := false.B - out.rsIdx := 0.U out.rep_carry := 0.U.asTypeOf(out.rep_carry) out.mshrid := 0.U out.isFirstIssue := false.B @@ -478,7 +475,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule out.uop := src.uop out.try_l2l := false.B out.has_rob_entry := true.B - out.rsIdx := src.rsIdx out.rep_carry := src.replayCarry out.mshrid := src.mshrid out.isFirstIssue := false.B @@ -513,7 +509,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule out.uop := DontCare out.try_l2l := false.B out.has_rob_entry := false.B - out.rsIdx := 0.U out.rep_carry := 0.U.asTypeOf(out.rep_carry) out.mshrid := 0.U out.isFirstIssue := false.B @@ -534,8 +529,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule out.uop := src.uop out.try_l2l := false.B out.has_rob_entry := true.B - // TODO: VLSU, implement vector feedback - out.rsIdx := 0.U // TODO: VLSU, implement replay carry out.rep_carry := 0.U.asTypeOf(out.rep_carry) out.mshrid := 0.U @@ -578,7 +571,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule out.uop := src.uop out.try_l2l := false.B out.has_rob_entry := true.B - out.rsIdx := src.iqIdx out.rep_carry := 0.U.asTypeOf(out.rep_carry) out.mshrid := 0.U out.isFirstIssue := true.B @@ -607,7 +599,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule // we dont care out.isFirstIssue and out.rsIdx and s0_sqIdx in S0 when trying pointchasing // because these signals will be updated in S1 out.has_rob_entry := false.B - out.rsIdx := 0.U out.mshrid := 0.U out.rep_carry := 0.U.asTypeOf(out.rep_carry) out.isFirstIssue := true.B @@ -658,7 +649,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule // accept load flow if dcache ready (tlb is always ready) // TODO: prefetch need writeback to loadQueueFlag s0_out := DontCare - s0_out.rsIdx := s0_sel_src.rsIdx s0_out.vaddr := s0_sel_src.vaddr s0_out.mask := s0_sel_src.mask s0_out.uop := s0_sel_src.uop @@ -824,7 +814,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule s1_out.gpaddr := s1_gpaddr_dup_lsu s1_out.tlbMiss := s1_tlb_miss s1_out.ptwBack := io.tlb.resp.bits.ptwBack - s1_out.rsIdx := s1_in.rsIdx s1_out.rep_info.debug := s1_in.uop.debugInfo s1_out.rep_info.nuke := s1_nuke && !s1_sw_prf s1_out.delayedLoadError := s1_dly_err @@ -885,7 +874,6 @@ class LoadUnit(implicit p: Parameters) extends XSModule s1_fast_mismatch s1_in.uop := io.ldin.bits.uop - s1_in.rsIdx := io.ldin.bits.iqIdx s1_in.isFirstIssue := io.ldin.bits.isFirstIssue s1_vaddr_lo := s1_ptr_chasing_vaddr(5, 0) s1_paddr_dup_lsu := Cat(io.tlb.resp.bits.paddr(0)(PAddrBits - 1, 6), s1_vaddr_lo) @@ -1139,6 +1127,7 @@ class LoadUnit(implicit p: Parameters) extends XSModule io.feedback_fast.bits.hit := false.B io.feedback_fast.bits.flushState := s2_in.ptwBack io.feedback_fast.bits.robIdx := s2_in.uop.robIdx + io.feedback_fast.bits.sqIdx := s2_in.uop.sqIdx io.feedback_fast.bits.sourceType := RSFeedbackType.lrqFull io.feedback_fast.bits.dataInvalidSqIdx := DontCare @@ -1333,6 +1322,7 @@ class LoadUnit(implicit p: Parameters) extends XSModule io.feedback_slow.bits.hit := !s3_rep_info.need_rep || io.lsq.ldin.ready io.feedback_slow.bits.flushState := s3_in.ptwBack io.feedback_slow.bits.robIdx := s3_in.uop.robIdx + io.feedback_slow.bits.sqIdx := s3_in.uop.sqIdx io.feedback_slow.bits.sourceType := RSFeedbackType.lrqFull io.feedback_slow.bits.dataInvalidSqIdx := DontCare diff --git a/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala b/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala index 0a13003cd1..ba099b37af 100644 --- a/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala +++ b/src/main/scala/xiangshan/mem/pipeline/StoreUnit.scala @@ -80,7 +80,7 @@ class StoreUnit(implicit p: Parameters) extends XSModule val s0_vecstin = Mux(s0_use_flow_vec, io.vecstin.bits, 0.U.asTypeOf(io.vecstin.bits)) val s0_uop = Mux(s0_use_flow_rs, s0_stin.uop, s0_vecstin.uop) val s0_isFirstIssue = s0_use_flow_rs && io.stin.bits.isFirstIssue || s0_use_flow_vec && io.vec_isFirstIssue - val s0_rsIdx = Mux(s0_use_flow_rs, io.stin.bits.iqIdx, 0.U) + val s0_iqIdx = Mux(s0_use_flow_rs, io.stin.bits.iqIdx, 0.U) val s0_size = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.fuOpType(2,0), 0.U)// may broken if use it in feature val s0_mem_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.sqIdx.value, 0.U) val s0_rob_idx = Mux(s0_use_flow_rs || s0_use_flow_vec, s0_uop.robIdx, 0.U.asTypeOf(s0_uop.robIdx)) @@ -164,7 +164,6 @@ class StoreUnit(implicit p: Parameters) extends XSModule s0_out.data := s0_stin.src(1) s0_out.uop := s0_uop s0_out.miss := false.B - s0_out.rsIdx := s0_rsIdx s0_out.mask := s0_mask s0_out.isFirstIssue := s0_isFirstIssue s0_out.isHWPrefetch := s0_use_flow_prf @@ -252,6 +251,7 @@ class StoreUnit(implicit p: Parameters) extends XSModule s1_feedback.bits.robIdx := s1_out.uop.robIdx s1_feedback.bits.sourceType := RSFeedbackType.tlbMiss s1_feedback.bits.dataInvalidSqIdx := DontCare + s1_feedback.bits.sqIdx := s1_out.uop.sqIdx XSDebug(s1_feedback.valid, "S1 Store: tlbHit: %d robIdx: %d\n", diff --git a/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala b/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala index b9c2964ae2..153943ceff 100644 --- a/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala +++ b/src/main/scala/xiangshan/mem/vector/VMergeBuffer.scala @@ -302,7 +302,7 @@ abstract class BaseVMergeBuffer(isVStore: Boolean=false)(implicit p: Parameters) io.feedback(i).bits.sourceType := selEntry.sourceType io.feedback(i).bits.flushState := selEntry.flushState io.feedback(i).bits.dataInvalidSqIdx := DontCare - io.feedback(i).bits.uopIdx.get := selEntry.uop.uopIdx + io.feedback(i).bits.sqIdx := selEntry.uop.sqIdx } QueuePerf(uopSize, freeList.io.validCount, freeList.io.validCount === 0.U) diff --git a/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala b/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala index 63447b6ebe..dd3d17556b 100644 --- a/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala +++ b/src/main/scala/xiangshan/mem/vector/VSegmentUnit.scala @@ -622,7 +622,7 @@ class VSegmentUnit (implicit p: Parameters) extends VLSUModule io.feedback.bits.sourceType := DontCare io.feedback.bits.flushState := DontCare io.feedback.bits.dataInvalidSqIdx := DontCare - io.feedback.bits.uopIdx.get := uopq(deqPtr.value).uop.vpu.vuopIdx + io.feedback.bits.sqIdx := uopq(deqPtr.value).uop.sqIdx // exception io.exceptionInfo := DontCare