diff --git a/src/main/scala/xiangshan/frontend/icache/ICache.scala b/src/main/scala/xiangshan/frontend/icache/ICache.scala
index a415231b7d..2b063a645f 100644
--- a/src/main/scala/xiangshan/frontend/icache/ICache.scala
+++ b/src/main/scala/xiangshan/frontend/icache/ICache.scala
@@ -135,15 +135,11 @@ trait HasICacheParameters extends HasL1CacheParameters with HasInstrMMIOConst wi
     codes.asTypeOf(UInt(ICacheCodeBits.W))
   }
 
-  def getBankSel(blkOffset: UInt):Vec[UInt] = {
+  def getBankSel(blkOffset: UInt, valid: Bool = true.B): Vec[UInt] = {
     val bankIdxLow  = Cat(0.U(1.W), blkOffset) >> log2Ceil(blockBytes/ICacheDataBanks)
     val bankIdxHigh = (Cat(0.U(1.W), blkOffset) + 32.U) >> log2Ceil(blockBytes/ICacheDataBanks)
     val bankSel = VecInit((0 until ICacheDataBanks * 2).map(i => (i.U >= bankIdxLow) && (i.U <= bankIdxHigh)))
-    /* FIXME: when blkOffset is invalid, it can be anything and causing fake assertion-fails
-     *        maybe it's better to do this assert outside getBankSel(), or pass a valid signal here
-     *        the current solution is ensuring blkOffset is valid by defaulting it to 0.U
-     */
-    assert(PopCount(bankSel) === ICacheBankVisitNum.U, "The number of bank visits must be %d, but bankSel=0x%x", ICacheBankVisitNum.U, bankSel.asUInt)
+    assert(!valid || PopCount(bankSel) === ICacheBankVisitNum.U, "The number of bank visits must be %d, but bankSel=0x%x", ICacheBankVisitNum.U, bankSel.asUInt)
     bankSel.asTypeOf(UInt((ICacheDataBanks * 2).W)).asTypeOf(Vec(2, UInt(ICacheDataBanks.W)))
   }
 
@@ -337,7 +333,7 @@ class ICacheDataArray(implicit p: Parameters) extends ICacheArray
   val writeDatas   = io.write.bits.data.asTypeOf(Vec(ICacheDataBanks, UInt(ICacheDataBits.W)))
   val writeEntries = writeDatas.map(ICacheDataEntry(_).asUInt)
 
-  val bankSel = getBankSel(io.read(0).bits.blkOffset)
+  val bankSel = getBankSel(io.read(0).bits.blkOffset, io.read(0).valid)
   val lineSel = getLineSel(io.read(0).bits.blkOffset)
   val waymasks = io.read(0).bits.wayMask
   val masks = Wire(Vec(nWays, Vec(ICacheDataBanks, Bool())))
diff --git a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
index 1a266da5c8..06b7216e0b 100644
--- a/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
+++ b/src/main/scala/xiangshan/frontend/icache/ICacheMainPipe.scala
@@ -321,7 +321,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
     * report data parity error
     ******************************************************************************
     */
-  val s2_bankSel        = getBankSel(s2_req_offset)
+  val s2_bankSel        = getBankSel(s2_req_offset, s2_valid)
   val s2_bank_errors    = (0 until ICacheDataBanks).map(i => (encode(s2_datas(i)) =/= s2_codes(i)))
   val s2_parity_errors  = (0 until PortNumber).map(port => (0 until ICacheDataBanks).map(bank =>
                             s2_bank_errors(bank) && s2_bankSel(port)(bank).asBool).reduce(_||_) && s2_SRAMhits(port))
@@ -522,7 +522,7 @@ class ICacheMainPipe(implicit p: Parameters) extends ICacheModule
       diffMainPipeOut.coreid := io.hartId
       diffMainPipeOut.index := (3 + i).U
 
-      val bankSel = getBankSel(s2_req_offset).reduce(_|_)
+      val bankSel = getBankSel(s2_req_offset, s2_valid).reduce(_|_)
       val lineSel = getLineSel(s2_req_offset)
 
       diffMainPipeOut.valid := s2_fire && bankSel(i).asBool && Mux(lineSel(i), !discards(1), !discards(0))