From c6655c9aede4e74d18bffa42a448c843b4fd77a3 Mon Sep 17 00:00:00 2001 From: Xiaokun-Pei Date: Tue, 9 Jul 2024 16:58:58 +0800 Subject: [PATCH] LLPTW, RVH: fix wrong state transition when onlyStage1 in LLPTW (#3160) The onlyStage1 req is same as the noS2xlate req in LLPTW. So to_mem_out is also applied to the onlyStage1 req. Co-authored-by: Haoyuan Feng --- src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala b/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala index 500e40e116..62865fbb24 100644 --- a/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala +++ b/src/main/scala/xiangshan/cache/mmu/PageTableWalker.scala @@ -481,7 +481,7 @@ class LLPTW(implicit p: Parameters) extends XSModule with HasPtwConst with HasPe val wait_id = Mux(dup_req_fire, mem_arb.io.chosen, ParallelMux(dup_vec_wait zip entries.map(_.wait_id))) val dup_wait_resp = io.mem.resp.fire && VecInit(dup_vec_wait)(io.mem.resp.bits.id) // dup with the entry that data coming next cycle val to_wait = Cat(dup_vec_wait).orR || dup_req_fire - val to_mem_out = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate + val to_mem_out = dup_wait_resp && ((entries(io.mem.resp.bits.id).req_info.s2xlate === noS2xlate) || (entries(io.mem.resp.bits.id).req_info.s2xlate === onlyStage1)) val to_cache = Cat(dup_vec_having).orR || Cat(dup_vec_last_hptw).orR val to_hptw_req = io.in.bits.req_info.s2xlate === allStage val to_last_hptw_req = dup_wait_resp && entries(io.mem.resp.bits.id).req_info.s2xlate === allStage @@ -855,4 +855,4 @@ class HPTW()(implicit p: Parameters) extends XSModule with HasPtwConst { accessFault := false.B mem_addr_update := false.B } -} \ No newline at end of file +}