From fd3aa0577117b390ca78476eb2755133f758af37 Mon Sep 17 00:00:00 2001 From: Yuandongliang <42736386+sleep-zzz@users.noreply.github.com> Date: Fri, 14 Jun 2024 18:49:09 +0800 Subject: [PATCH] FTB: Merge ftb low power & fix fallThroughAddr calculation. (#2997) --- src/main/scala/xiangshan/Parameters.scala | 3 + src/main/scala/xiangshan/frontend/BPU.scala | 19 +- .../scala/xiangshan/frontend/Composer.scala | 1 + src/main/scala/xiangshan/frontend/FTB.scala | 179 +++++++++++++++++- .../scala/xiangshan/frontend/FauFTB.scala | 17 ++ .../xiangshan/frontend/FrontendBundle.scala | 7 +- .../scala/xiangshan/frontend/NewFtq.scala | 2 + 7 files changed, 213 insertions(+), 15 deletions(-) diff --git a/src/main/scala/xiangshan/Parameters.scala b/src/main/scala/xiangshan/Parameters.scala index 2c4f221436..2cca17d835 100644 --- a/src/main/scala/xiangshan/Parameters.scala +++ b/src/main/scala/xiangshan/Parameters.scala @@ -125,6 +125,9 @@ case class XSCoreParameters val preds = Seq(uftb, tage, ftb, ittage, ras) preds.map(_.io := DontCare) + ftb.io.fauftb_entry_in := uftb.io.fauftb_entry_out + ftb.io.fauftb_entry_hit_in := uftb.io.fauftb_entry_hit_out + uftb.io.in.bits.resp_in(0) := resp_in tage.io.in.bits.resp_in(0) := uftb.io.out ftb.io.in.bits.resp_in(0) := tage.io.out diff --git a/src/main/scala/xiangshan/frontend/BPU.scala b/src/main/scala/xiangshan/frontend/BPU.scala index 08f6747a7b..042e1b3ecd 100644 --- a/src/main/scala/xiangshan/frontend/BPU.scala +++ b/src/main/scala/xiangshan/frontend/BPU.scala @@ -146,6 +146,11 @@ class BasePredictorIO (implicit p: Parameters) extends XSBundle with HasBPUConst val out = Output(new BasePredictorOutput) // val flush_out = Valid(UInt(VAddrBits.W)) + val fauftb_entry_in = Input(new FTBEntry) + val fauftb_entry_hit_in = Input(Bool()) + val fauftb_entry_out = Output(new FTBEntry) + val fauftb_entry_hit_out = Output(Bool()) + val ctrl = Input(new BPUCtrl) val s0_fire = Input(Vec(numDup, Bool())) @@ -162,6 +167,7 @@ class BasePredictorIO (implicit p: Parameters) extends XSBundle with HasBPUConst val update = Flipped(Valid(new BranchPredictionUpdate)) val redirect = Flipped(Valid(new BranchPredictionRedirect)) + val redirectFromIFU = Input(Bool()) } abstract class BasePredictor(implicit p: Parameters) extends XSModule @@ -173,6 +179,9 @@ abstract class BasePredictor(implicit p: Parameters) extends XSModule io.out := io.in.bits.resp_in(0) + io.fauftb_entry_out := io.fauftb_entry_in + io.fauftb_entry_hit_out := io.fauftb_entry_hit_in + io.out.last_stage_meta := 0.U io.in.ready := !io.redirect.valid @@ -342,6 +351,9 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H predictors.io.in.bits.ghist := s0_ghist predictors.io.in.bits.folded_hist := s0_folded_gh_dup predictors.io.in.bits.resp_in(0) := (0.U).asTypeOf(new BranchPredictionResp) + predictors.io.fauftb_entry_in := (0.U).asTypeOf(new FTBEntry) + predictors.io.fauftb_entry_hit_in := false.B + predictors.io.redirectFromIFU := RegNext(io.ftq_to_bpu.redirctFromIFU, init=false.B) // predictors.io.in.bits.resp_in(0).s1.pc := s0_pc // predictors.io.in.bits.toFtq_fire := toFtq_fire @@ -675,12 +687,13 @@ class Predictor(implicit p: Parameters) extends XSModule with HasBPUConst with H val s3_redirect_on_target_dup = resp.s3.getTarget.zip(previous_s2_pred.getTarget).map {case (t1, t2) => t1 =/= t2} val s3_redirect_on_jalr_target_dup = resp.s3.full_pred.zip(previous_s2_pred.full_pred).map {case (fp1, fp2) => fp1.hit_taken_on_jalr && fp1.jalr_target =/= fp2.jalr_target} val s3_redirect_on_fall_thru_error_dup = resp.s3.fallThruError + val s3_redirect_on_ftb_multi_hit_dup = resp.s3.ftbMultiHit - for ((((((s3_redirect, s3_fire), s3_redirect_on_br_taken), s3_redirect_on_target), s3_redirect_on_fall_thru_error), s3_both_first_taken) <- - s3_redirect_dup zip s3_fire_dup zip s3_redirect_on_br_taken_dup zip s3_redirect_on_target_dup zip s3_redirect_on_fall_thru_error_dup zip s3_both_first_taken_dup) { + for (((((((s3_redirect, s3_fire), s3_redirect_on_br_taken), s3_redirect_on_target), s3_redirect_on_fall_thru_error), s3_redirect_on_ftb_multi_hit), s3_both_first_taken) <- + s3_redirect_dup zip s3_fire_dup zip s3_redirect_on_br_taken_dup zip s3_redirect_on_target_dup zip s3_redirect_on_fall_thru_error_dup zip s3_redirect_on_ftb_multi_hit_dup zip s3_both_first_taken_dup) { s3_redirect := s3_fire && ( - (s3_redirect_on_br_taken && !s3_both_first_taken) || s3_redirect_on_target || s3_redirect_on_fall_thru_error + (s3_redirect_on_br_taken && !s3_both_first_taken) || s3_redirect_on_target || s3_redirect_on_fall_thru_error || s3_redirect_on_ftb_multi_hit ) } diff --git a/src/main/scala/xiangshan/frontend/Composer.scala b/src/main/scala/xiangshan/frontend/Composer.scala index 69e5cfff29..8d600e8ab4 100644 --- a/src/main/scala/xiangshan/frontend/Composer.scala +++ b/src/main/scala/xiangshan/frontend/Composer.scala @@ -54,6 +54,7 @@ class Composer(implicit p: Parameters) extends BasePredictor with HasBPUConst wi c.io.redirect := io.redirect c.io.ctrl := DelayN(io.ctrl, 1) + c.io.redirectFromIFU := io.redirectFromIFU if (c.meta_size > 0) { metas = (metas << c.meta_size) | c.io.out.last_stage_meta(c.meta_size-1,0) diff --git a/src/main/scala/xiangshan/frontend/FTB.scala b/src/main/scala/xiangshan/frontend/FTB.scala index e2cba3966d..8cd916d791 100644 --- a/src/main/scala/xiangshan/frontend/FTB.scala +++ b/src/main/scala/xiangshan/frontend/FTB.scala @@ -43,6 +43,9 @@ trait FTBParams extends HasXSParameter with HasBPUConst { def BR_OFFSET_LEN = 12 def JMP_OFFSET_LEN = 20 + + def FTBCLOSE_THRESHOLD_SZ = log2Ceil(500) + def FTBCLOSE_THRESHOLD = 500.U(FTBCLOSE_THRESHOLD_SZ.W) //can be modified } class FtbSlot_FtqMem(implicit p: Parameters) extends XSBundle with FTBParams { @@ -128,6 +131,16 @@ class FtbSlot(val offsetLen: Int, val subOffsetLen: Option[Int] = None)(implicit this.lower := ZeroExt(that.lower, this.offsetLen) } + def slotConsistent(that: FtbSlot) = { + VecInit( + this.offset === that.offset, + this.lower === that.lower, + this.tarStat === that.tarStat, + this.sharing === that.sharing, + this.valid === that.valid + ).reduce(_&&_) + } + } @@ -257,6 +270,37 @@ class FTBEntry(implicit p: Parameters) extends FTBEntry_part with FTBParams with VecInit(brSlots.map(_.offset) :+ tailSlot.offset) } + def entryConsistent(that: FTBEntry) = { + val validDiff = this.valid === that.valid + val brSlotsDiffSeq : IndexedSeq[Bool] = + this.brSlots.zip(that.brSlots).map{ + case(x,y) => x.slotConsistent(y) + } + val tailSlotDiff = this.tailSlot.slotConsistent(that.tailSlot) + val pftAddrDiff = this.pftAddr === that.pftAddr + val carryDiff = this.carry === that.carry + val isCallDiff = this.isCall === that.isCall + val isRetDiff = this.isRet === that.isRet + val isJalrDiff = this.isJalr === that.isJalr + val lastMayBeRviCallDiff = this.last_may_be_rvi_call === that.last_may_be_rvi_call + val alwaysTakenDiff : IndexedSeq[Bool] = + this.always_taken.zip(that.always_taken).map{ + case(x,y) => x === y + } + VecInit( + validDiff, + brSlotsDiffSeq.reduce(_&&_), + tailSlotDiff, + pftAddrDiff, + carryDiff, + isCallDiff, + isRetDiff, + isJalrDiff, + lastMayBeRviCallDiff, + alwaysTakenDiff.reduce(_&&_) + ).reduce(_&&_) + } + def display(cond: Bool): Unit = { XSDebug(cond, p"-----------FTB entry----------- \n") XSDebug(cond, p"v=${valid}\n") @@ -334,6 +378,9 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU val read_resp = Output(new FTBEntry) val read_hits = Valid(UInt(log2Ceil(numWays).W)) + val read_multi_entry = Output(new FTBEntry) + val read_multi_hits = Valid(UInt(log2Ceil(numWays).W)) + val u_req_pc = Flipped(DecoupledIO(UInt(VAddrBits.W))) val update_hits = Valid(UInt(log2Ceil(numWays).W)) val update_access = Input(Bool()) @@ -370,6 +417,32 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU // val hit_way_1h = VecInit(PriorityEncoderOH(total_hits)) val hit_way = OHToUInt(total_hits) + //There may be two hits in the four paths of the ftbBank, and the OHToUInt will fail. + //If there is a redirect in s2 at this time, the wrong FTBEntry will be used to calculate the target, + //resulting in an address error and affecting performance. + //The solution is to select a hit entry during multi hit as the entry for s2. + //Considering timing, use this entry in s3 and trigger s3-redirect. + val total_hits_reg = RegEnable(total_hits,io.s1_fire) + val read_entries_reg = read_entries.map(w => RegEnable(w,io.s1_fire)) + + val multi_hit = VecInit((0 until numWays).map{ + i => (0 until numWays).map(j => { + if(i < j) total_hits_reg(i) && total_hits_reg(j) + else false.B + }).reduce(_||_) + }).reduce(_||_) + val multi_way = PriorityMux(Seq.tabulate(numWays)(i => ((total_hits_reg(i)) -> i.asUInt(log2Ceil(numWays).W)))) + val multi_hit_selectEntry = PriorityMux(Seq.tabulate(numWays)(i => ((total_hits_reg(i)) -> read_entries_reg(i)))) + + //Check if the entry read by ftbBank is legal. + for (n <- 0 to numWays -1 ) { + val req_pc_reg = RegEnable(io.req_pc.bits, io.req_pc.valid) + val ftb_entry_fallThrough = read_entries(n).getFallThrough(req_pc_reg) + when(read_entries(n).valid && total_hits(n) && io.s1_fire){ + assert(req_pc_reg + (2*PredictWidth).U >= ftb_entry_fallThrough, s"FTB sram entry in way${n} fallThrough address error!") + } + } + val u_total_hits = VecInit((0 until numWays).map(b => ftb.io.r.resp.data(b).tag === u_req_tag && ftb.io.r.resp.data(b).entry.valid && RegNext(io.update_access))) val u_hit = u_total_hits.reduce(_||_) @@ -427,6 +500,10 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU io.read_hits.valid := hit io.read_hits.bits := hit_way + io.read_multi_entry := multi_hit_selectEntry + io.read_multi_hits.valid := multi_hit + io.read_multi_hits.bits := multi_way + io.update_hits.valid := u_hit io.update_hits.bits := u_hit_way @@ -455,23 +532,98 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU Mux1H(total_hits, ftb.io.r.resp.data).display(true.B) } // FTBBank + //FTB switch register & temporary storage of fauftb prediction results + val s0_close_ftb_req = RegInit(false.B) + val s1_close_ftb_req = RegEnable(s0_close_ftb_req, false.B, io.s0_fire(0)) + val s2_close_ftb_req = RegEnable(s1_close_ftb_req, false.B, io.s1_fire(0)) + val s2_fauftb_ftb_entry_dup = io.s1_fire.map(f => RegEnable(io.fauftb_entry_in, f)) + val s2_fauftb_ftb_entry_hit_dup = io.s1_fire.map(f => RegEnable(io.fauftb_entry_hit_in, f)) + val ftbBank = Module(new FTBBank(numSets, numWays)) - ftbBank.io.req_pc.valid := io.s0_fire(0) + //for close ftb read_req + ftbBank.io.req_pc.valid := io.s0_fire(0) && !s0_close_ftb_req ftbBank.io.req_pc.bits := s0_pc_dup(0) + val s2_multi_hit = ftbBank.io.read_multi_hits.valid && io.s2_fire(0) + val s2_multi_hit_way = ftbBank.io.read_multi_hits.bits + val s2_multi_hit_entry = ftbBank.io.read_multi_entry + val s2_multi_hit_enable = s2_multi_hit && io.s2_redirect(0) + XSPerfAccumulate("ftb_s2_multi_hit",s2_multi_hit) + XSPerfAccumulate("ftb_s2_multi_hit_enable",s2_multi_hit_enable) + + //After closing ftb, the entry output from s2 is the entry of FauFTB cached in s1 val btb_enable_dup = dup(RegNext(io.ctrl.btb_enable)) - val s2_ftb_entry_dup = io.s1_fire.map(f => RegEnable(ftbBank.io.read_resp, f)) - val s3_ftb_entry_dup = io.s2_fire.zip(s2_ftb_entry_dup).map {case (f, e) => RegEnable(e, f)} + val s1_read_resp = Mux(s1_close_ftb_req,io.fauftb_entry_in,ftbBank.io.read_resp) + val s2_ftbBank_dup = io.s1_fire.map(f => RegEnable(ftbBank.io.read_resp, f)) + val s2_ftb_entry_dup = dup(0.U.asTypeOf(new FTBEntry)) + for(((s2_fauftb_entry,s2_ftbBank_entry),s2_ftb_entry) <- + s2_fauftb_ftb_entry_dup zip s2_ftbBank_dup zip s2_ftb_entry_dup){ + s2_ftb_entry := Mux(s2_close_ftb_req,s2_fauftb_entry,s2_ftbBank_entry) + } + val s3_ftb_entry_dup = io.s2_fire.zip(s2_ftb_entry_dup).map {case (f, e) => RegEnable(Mux(s2_multi_hit_enable, s2_multi_hit_entry, e), f)} + + //After closing ftb, the hit output from s2 is the hit of FauFTB cached in s1. + //s1_hit is the ftbBank hit. + val s1_hit = Mux(s1_close_ftb_req,false.B,ftbBank.io.read_hits.valid && io.ctrl.btb_enable) + val s2_ftb_hit_dup = io.s1_fire.map(f => RegEnable(s1_hit, 0.B, f)) + val s2_hit_dup = dup(0.U.asTypeOf(Bool())) + for(((s2_fauftb_hit,s2_ftb_hit),s2_hit) <- + s2_fauftb_ftb_entry_hit_dup zip s2_ftb_hit_dup zip s2_hit_dup){ + s2_hit := Mux(s2_close_ftb_req,s2_fauftb_hit,s2_ftb_hit) + } + val s3_hit_dup = io.s2_fire.zip(s2_hit_dup).map {case (f, h) => RegEnable(Mux(s2_multi_hit_enable, s2_multi_hit, h), 0.B, f)} + val s3_mult_hit_dup = io.s2_fire.map(f => RegEnable(s2_multi_hit_enable,f)) + val writeWay = Mux(s1_close_ftb_req,0.U,ftbBank.io.read_hits.bits) + val s2_ftb_meta = RegEnable(FTBMeta(writeWay.asUInt, s1_hit, GTimer()).asUInt, io.s1_fire(0)) + val s2_multi_hit_meta = FTBMeta(s2_multi_hit_way.asUInt, s2_multi_hit, GTimer()).asUInt + + //Consistent count of entries for fauftb and ftb + val fauftb_ftb_entry_consistent_counter = RegInit(0.U(FTBCLOSE_THRESHOLD_SZ.W)) + val fauftb_ftb_entry_consistent = s2_fauftb_ftb_entry_dup(0).entryConsistent(s2_ftbBank_dup(0)) + + //if close ftb_req, the counter need keep + when(io.s2_fire(0) && s2_fauftb_ftb_entry_hit_dup(0) && s2_ftb_hit_dup(0) ){ + fauftb_ftb_entry_consistent_counter := Mux(fauftb_ftb_entry_consistent, fauftb_ftb_entry_consistent_counter + 1.U, 0.U) + } .elsewhen(io.s2_fire(0) && !s2_fauftb_ftb_entry_hit_dup(0) && s2_ftb_hit_dup(0) ){ + fauftb_ftb_entry_consistent_counter := 0.U + } + + when((fauftb_ftb_entry_consistent_counter >= FTBCLOSE_THRESHOLD) && io.s0_fire(0)){ + s0_close_ftb_req := true.B + } + + //Clear counter during false_hit or ifuRedirect + val ftb_false_hit = WireInit(false.B) + val needReopen = s0_close_ftb_req && (ftb_false_hit || io.redirectFromIFU) + ftb_false_hit := io.update.valid && io.update.bits.false_hit + when(needReopen){ + fauftb_ftb_entry_consistent_counter := 0.U + s0_close_ftb_req := false.B + } + + val s2_close_consistent = s2_fauftb_ftb_entry_dup(0).entryConsistent(s2_ftb_entry_dup(0)) + val s2_not_close_consistent = s2_ftbBank_dup(0).entryConsistent(s2_ftb_entry_dup(0)) + + when(s2_close_ftb_req && io.s2_fire(0)){ + assert(s2_close_consistent, s"Entry inconsistency after ftb req is closed!") + }.elsewhen(!s2_close_ftb_req && io.s2_fire(0)){ + assert(s2_not_close_consistent, s"Entry inconsistency after ftb req is not closed!") + } - val s1_hit = ftbBank.io.read_hits.valid && io.ctrl.btb_enable - val s2_hit_dup = io.s1_fire.map(f => RegEnable(s1_hit, 0.B, f)) - val s3_hit_dup = io.s2_fire.zip(s2_hit_dup).map {case (f, h) => RegEnable(h, 0.B, f)} - val writeWay = ftbBank.io.read_hits.bits + val reopenCounter = !s1_close_ftb_req && s2_close_ftb_req && io.s2_fire(0) + val falseHitReopenCounter = ftb_false_hit && s1_close_ftb_req + XSPerfAccumulate("ftb_req_reopen_counter",reopenCounter) + XSPerfAccumulate("false_hit_reopen_Counter",falseHitReopenCounter) + XSPerfAccumulate("ifuRedirec_needReopen",s1_close_ftb_req && io.redirectFromIFU) + XSPerfAccumulate("this_cycle_is_close",s2_close_ftb_req && io.s2_fire(0)) + XSPerfAccumulate("this_cycle_is_open",!s2_close_ftb_req && io.s2_fire(0)) // io.out.bits.resp := RegEnable(io.in.bits.resp_in(0), 0.U.asTypeOf(new BranchPredictionResp), io.s1_fire) io.out := io.in.bits.resp_in(0) + io.out.s2.full_pred.map {case fp => fp.multiHit := false.B} + io.out.s2.full_pred.zip(s2_hit_dup).map {case (fp, h) => fp.hit := h} io.out.s2.pc := s2_pc_dup for (full_pred & s2_ftb_entry & s2_pc & s1_pc & s1_fire <- @@ -480,18 +632,19 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU s2_pc, // Previous stage meta for better timing Some(s1_pc, s1_fire), - Some(ftbBank.io.read_resp, s1_fire) + Some(s1_read_resp, s1_fire) ) } io.out.s3.full_pred.zip(s3_hit_dup).map {case (fp, h) => fp.hit := h} + io.out.s3.full_pred.zip(s3_mult_hit_dup).map {case (fp, m) => fp.multiHit := m} io.out.s3.pc := s3_pc_dup for (full_pred & s3_ftb_entry & s3_pc & s2_pc & s2_fire <- io.out.s3.full_pred zip s3_ftb_entry_dup zip s3_pc_dup zip s2_pc_dup zip io.s2_fire) full_pred.fromFtbEntry(s3_ftb_entry, s3_pc, Some((s2_pc, s2_fire))) io.out.last_stage_ftb_entry := s3_ftb_entry_dup(0) - io.out.last_stage_meta := RegEnable(RegEnable(FTBMeta(writeWay.asUInt, s1_hit, GTimer()).asUInt, io.s1_fire(0)), io.s2_fire(0)) + io.out.last_stage_meta := RegEnable(Mux(s2_multi_hit_enable, s2_multi_hit_meta, s2_ftb_meta), io.s2_fire(0)) // always taken logic for (i <- 0 until numBr) { @@ -528,15 +681,21 @@ class FTB(implicit p: Parameters) extends BasePredictor with FTBParams with BPUU ftb_write.tag := ftbAddr.getTag(Mux(update_now, update.pc, delay2_pc))(tagSize-1, 0) val write_valid = update_now || DelayN(u_valid && !u_meta.hit, 2) + val write_pc = Mux(update_now, update.pc, delay2_pc) ftbBank.io.update_write_data.valid := write_valid ftbBank.io.update_write_data.bits := ftb_write - ftbBank.io.update_pc := Mux(update_now, update.pc, delay2_pc) + ftbBank.io.update_pc := write_pc ftbBank.io.update_write_way := Mux(update_now, u_meta.writeWay, RegNext(ftbBank.io.update_hits.bits)) // use it one cycle later ftbBank.io.update_write_alloc := Mux(update_now, false.B, RegNext(!ftbBank.io.update_hits.valid)) // use it one cycle later ftbBank.io.update_access := u_valid && !u_meta.hit ftbBank.io.s1_fire := io.s1_fire(0) + val ftb_write_fallThrough = ftb_write.entry.getFallThrough(write_pc) + when(write_valid){ + assert(write_pc + (FetchWidth * 4).U >= ftb_write_fallThrough, s"FTB write_entry fallThrough address error!") + } + XSDebug("req_v=%b, req_pc=%x, ready=%b (resp at next cycle)\n", io.s0_fire(0), s0_pc_dup(0), ftbBank.io.req_pc.ready) XSDebug("s2_hit=%b, hit_way=%b\n", s2_hit_dup(0), writeWay.asUInt) XSDebug("s2_br_taken_mask=%b, s2_real_taken_mask=%b\n", diff --git a/src/main/scala/xiangshan/frontend/FauFTB.scala b/src/main/scala/xiangshan/frontend/FauFTB.scala index 656f8a3647..505bef8721 100644 --- a/src/main/scala/xiangshan/frontend/FauFTB.scala +++ b/src/main/scala/xiangshan/frontend/FauFTB.scala @@ -106,16 +106,26 @@ class FauFTB(implicit p: Parameters) extends BasePredictor with FauFTBParams { val s1_all_entries = VecInit(ways.map(_.io.resp)) for (c & fp & e <- ctrs zip s1_possible_full_preds zip s1_all_entries) { fp.hit := DontCare + fp.multiHit := false.B fp.fromFtbEntry(e, s1_pc_dup(0)) for (i <- 0 until numBr) { fp.br_taken_mask(i) := c(i)(1) || e.always_taken(i) } } val s1_hit_full_pred = Mux1H(s1_hit_oh, s1_possible_full_preds) + val s1_hit_fauftbentry = Mux1H(s1_hit_oh, s1_all_entries) XSError(PopCount(s1_hit_oh) > 1.U, "fauftb has multiple hits!\n") val fauftb_enable = RegNext(io.ctrl.ubtb_enable) io.out.s1.full_pred.map(_ := s1_hit_full_pred) io.out.s1.full_pred.map(_ .hit := s1_hit && fauftb_enable) + io.fauftb_entry_out := s1_hit_fauftbentry + io.fauftb_entry_hit_out := s1_hit && fauftb_enable + + // Illegal check for FTB entry reading + val uftb_read_fallThrough = s1_hit_fauftbentry.getFallThrough(s1_pc_dup(0)) + when(io.s1_fire(0) && s1_hit){ + assert(s1_pc_dup(0) + (FetchWidth * 4).U >= uftb_read_fallThrough, s"FauFTB entry fallThrough address error!") + } // assign metas io.out.last_stage_meta := resp_meta.asUInt @@ -158,6 +168,13 @@ class FauFTB(implicit p: Parameters) extends BasePredictor with FauFTBParams { ways(w).io.write_entry := u_s1_ftb_entry } + // Illegal check for FTB entry writing + val uftb_write_pc = RegEnable(u.bits.pc, u.valid) + val uftb_write_fallThrough = u_s1_ftb_entry.getFallThrough(uftb_write_pc) + when(u_s1_valid && u_s1_hit){ + assert(uftb_write_pc + (FetchWidth * 4).U >= uftb_write_fallThrough, s"FauFTB write entry fallThrough address error!") + } + // update saturating counters val u_s1_br_update_valids = RegEnable(u_s0_br_update_valids, u.valid) val u_s1_br_takens = RegEnable(u.bits.br_taken_mask, u.valid) diff --git a/src/main/scala/xiangshan/frontend/FrontendBundle.scala b/src/main/scala/xiangshan/frontend/FrontendBundle.scala index a7acc677b4..bcfafc3ed3 100644 --- a/src/main/scala/xiangshan/frontend/FrontendBundle.scala +++ b/src/main/scala/xiangshan/frontend/FrontendBundle.scala @@ -48,7 +48,7 @@ class FetchRequestBundle(implicit p: Parameters) extends XSBundle with HasICache this.startAddr := b.startAddr this.nextlineStart := b.nextLineAddr when (b.fallThruError) { - val nextBlockHigherTemp = Mux(startAddr(log2Ceil(PredictWidth)+instOffsetBits), b.startAddr, b.nextLineAddr) + val nextBlockHigherTemp = Mux(startAddr(log2Ceil(PredictWidth)+instOffsetBits), b.nextLineAddr, b.startAddr) val nextBlockHigher = nextBlockHigherTemp(VAddrBits-1, log2Ceil(PredictWidth)+instOffsetBits+1) this.nextStartAddr := Cat(nextBlockHigher, @@ -429,6 +429,7 @@ class FullBranchPrediction(implicit p: Parameters) extends XSBundle with HasBPUC val offsets = Vec(totalSlot, UInt(log2Ceil(PredictWidth).W)) val fallThroughAddr = UInt(VAddrBits.W) val fallThroughErr = Bool() + val multiHit = Bool() val is_jal = Bool() val is_jalr = Bool() @@ -502,6 +503,7 @@ class FullBranchPrediction(implicit p: Parameters) extends XSBundle with HasBPUC } def fallThruError: Bool = hit && fallThroughErr + def ftbMultiHit: Bool = hit && multiHit def hit_taken_on_jmp = !real_slot_taken_mask().init.reduce(_||_) && @@ -542,7 +544,7 @@ class FullBranchPrediction(implicit p: Parameters) extends XSBundle with HasBPUC val startLower = Cat(0.U(1.W), pc(instOffsetBits+log2Ceil(PredictWidth)-1, instOffsetBits)) val endLowerwithCarry = Cat(entry.carry, entry.pftAddr) - fallThroughErr := startLower >= endLowerwithCarry + fallThroughErr := startLower >= endLowerwithCarry || endLowerwithCarry > (startLower + (PredictWidth).U) fallThroughAddr := Mux(fallThroughErr, pc + (FetchWidth * 4).U, entry.getFallThrough(pc, last_stage_entry)) } @@ -579,6 +581,7 @@ class BranchPredictionBundle(implicit p: Parameters) extends XSBundle def brTaken = VecInit(full_pred.map(_.brTaken)) def shouldShiftVec = VecInit(full_pred.map(_.shouldShiftVec)) def fallThruError = VecInit(full_pred.map(_.fallThruError)) + def ftbMultiHit = VecInit(full_pred.map(_.ftbMultiHit)) def taken = VecInit(cfiIndex.map(_.valid)) diff --git a/src/main/scala/xiangshan/frontend/NewFtq.scala b/src/main/scala/xiangshan/frontend/NewFtq.scala index 9ebcdb6c87..bf08168fd9 100644 --- a/src/main/scala/xiangshan/frontend/NewFtq.scala +++ b/src/main/scala/xiangshan/frontend/NewFtq.scala @@ -181,6 +181,7 @@ class FtqToBpuIO(implicit p: Parameters) extends XSBundle { val redirect = Valid(new BranchPredictionRedirect) val update = Valid(new BranchPredictionUpdate) val enq_ptr = Output(new FtqPtr) + val redirctFromIFU = Output(Bool()) } class FtqToIfuIO(implicit p: Parameters) extends XSBundle with HasCircularQueuePtrHelper { @@ -1181,6 +1182,7 @@ class Ftq(implicit p: Parameters) extends XSModule with HasCircularQueuePtrHelpe // **************************** to bpu **************************** // **************************************************************** + io.toBpu.redirctFromIFU := ifuRedirectToBpu.valid io.toBpu.redirect := Mux(fromBackendRedirect.valid, fromBackendRedirect, ifuRedirectToBpu) val dummy_s1_pred_cycle_vec = VecInit(List.tabulate(FtqSize)(_=>0.U(64.W))) val redirect_latency = GTimer() - pred_s1_cycle.getOrElse(dummy_s1_pred_cycle_vec)(io.toBpu.redirect.bits.ftqIdx.value) + 1.U