From de5336016edbe1e90327d0ed1cba5c4e49114366 Mon Sep 17 00:00:00 2001 From: OryxEmbeddedAdmin Date: Fri, 8 Jan 2021 10:16:26 +0100 Subject: [PATCH] Version 2.0.2 --- coap/coap_client.c | 4 +- coap/coap_client.h | 4 +- coap/coap_client_block.c | 44 +- coap/coap_client_block.h | 4 +- coap/coap_client_misc.c | 4 +- coap/coap_client_misc.h | 4 +- coap/coap_client_observe.c | 4 +- coap/coap_client_observe.h | 4 +- coap/coap_client_request.c | 5 +- coap/coap_client_request.h | 4 +- coap/coap_client_transport.c | 4 +- coap/coap_client_transport.h | 4 +- coap/coap_common.h | 5 +- coap/coap_debug.c | 4 +- coap/coap_debug.h | 4 +- coap/coap_message.c | 4 +- coap/coap_message.h | 4 +- coap/coap_option.c | 4 +- coap/coap_option.h | 6 +- coap/coap_server.c | 4 +- coap/coap_server.h | 4 +- coap/coap_server_misc.c | 11 +- coap/coap_server_misc.h | 4 +- coap/coap_server_request.c | 32 +- coap/coap_server_request.h | 4 +- coap/coap_server_transport.c | 15 +- coap/coap_server_transport.h | 4 +- core/bsd_socket.c | 5 +- core/bsd_socket.h | 4 +- core/ethernet.c | 4 +- core/ethernet.h | 7 +- core/ethernet_misc.c | 4 +- core/ethernet_misc.h | 4 +- core/ip.c | 8 +- core/ip.h | 4 +- core/net.c | 4 +- core/net.h | 8 +- core/net_legacy.h | 4 +- core/net_mem.c | 4 +- core/net_mem.h | 4 +- core/net_misc.c | 4 +- core/net_misc.h | 4 +- core/nic.c | 10 +- core/nic.h | 4 +- core/ping.c | 4 +- core/ping.h | 4 +- core/raw_socket.c | 41 +- core/raw_socket.h | 4 +- core/socket.c | 9 +- core/socket.h | 32 +- core/tcp.c | 4 +- core/tcp.h | 4 +- core/tcp_fsm.c | 4 +- core/tcp_fsm.h | 4 +- core/tcp_misc.c | 157 +-- core/tcp_misc.h | 4 +- core/tcp_timer.c | 4 +- core/tcp_timer.h | 4 +- core/udp.c | 31 +- core/udp.h | 4 +- dhcp/dhcp_client.c | 18 +- dhcp/dhcp_client.h | 4 +- dhcp/dhcp_common.c | 78 +- dhcp/dhcp_common.h | 4 +- dhcp/dhcp_debug.c | 4 +- dhcp/dhcp_debug.h | 4 +- dhcp/dhcp_server.c | 8 +- dhcp/dhcp_server.h | 4 +- dhcpv6/dhcpv6_client.c | 4 +- dhcpv6/dhcpv6_client.h | 4 +- dhcpv6/dhcpv6_common.c | 4 +- dhcpv6/dhcpv6_common.h | 4 +- dhcpv6/dhcpv6_debug.c | 4 +- dhcpv6/dhcpv6_debug.h | 4 +- dhcpv6/dhcpv6_relay.c | 4 +- dhcpv6/dhcpv6_relay.h | 4 +- dns/dns_cache.c | 4 +- dns/dns_cache.h | 4 +- dns/dns_client.c | 4 +- dns/dns_client.h | 4 +- dns/dns_common.c | 4 +- dns/dns_common.h | 4 +- dns/dns_debug.c | 4 +- dns/dns_debug.h | 4 +- dns_sd/dns_sd.c | 4 +- dns_sd/dns_sd.h | 4 +- drivers/eth/dm9000_driver.c | 160 +-- drivers/eth/dm9000_driver.h | 759 ++++++++------ drivers/eth/enc28j60_driver.c | 308 +++--- drivers/eth/enc28j60_driver.h | 683 +++++++------ drivers/eth/enc624j600_driver.c | 250 +++-- drivers/eth/enc624j600_driver.h | 794 ++++++++------- drivers/eth/ksz8851_driver.c | 155 +-- drivers/eth/ksz8851_driver.h | 782 +++++++------- drivers/loopback/loopback_driver.c | 4 +- drivers/loopback/loopback_driver.h | 4 +- drivers/mac/a2fxxxm3_eth_driver.c | 4 +- drivers/mac/a2fxxxm3_eth_driver.h | 4 +- drivers/mac/am335x_eth_driver.c | 12 +- drivers/mac/am335x_eth_driver.h | 4 +- drivers/mac/aps3_eth_driver.c | 4 +- drivers/mac/aps3_eth_driver.h | 4 +- drivers/mac/avr32_eth_driver.c | 4 +- drivers/mac/avr32_eth_driver.h | 4 +- drivers/mac/efm32gg11_eth_driver.c | 4 +- drivers/mac/efm32gg11_eth_driver.h | 4 +- drivers/mac/esp32_eth_driver.c | 6 +- drivers/mac/esp32_eth_driver.h | 4 +- drivers/mac/f28m35x_eth_driver.c | 6 +- drivers/mac/f28m35x_eth_driver.h | 4 +- drivers/mac/fm4_eth_driver.c | 4 +- drivers/mac/fm4_eth_driver.h | 4 +- drivers/mac/gd32f307_eth_driver.c | 4 +- drivers/mac/gd32f307_eth_driver.h | 4 +- drivers/mac/lm3s_eth_driver.c | 4 +- drivers/mac/lm3s_eth_driver.h | 4 +- drivers/mac/lpc175x_eth_driver.c | 4 +- drivers/mac/lpc175x_eth_driver.h | 4 +- drivers/mac/lpc176x_eth_driver.c | 4 +- drivers/mac/lpc176x_eth_driver.h | 4 +- drivers/mac/lpc178x_eth_driver.c | 4 +- drivers/mac/lpc178x_eth_driver.h | 4 +- drivers/mac/lpc18xx_eth_driver.c | 4 +- drivers/mac/lpc18xx_eth_driver.h | 4 +- drivers/mac/lpc23xx_eth_driver.c | 4 +- drivers/mac/lpc23xx_eth_driver.h | 4 +- drivers/mac/lpc43xx_eth_driver.c | 4 +- drivers/mac/lpc43xx_eth_driver.h | 4 +- ...6xx_eth_driver.c => lpc54xxx_eth_driver.c} | 214 ++-- ...6xx_eth_driver.h => lpc54xxx_eth_driver.h} | 104 +- drivers/mac/m2sxxx_eth_driver.c | 4 +- drivers/mac/m2sxxx_eth_driver.h | 4 +- drivers/mac/m487_eth_driver.c | 4 +- drivers/mac/m487_eth_driver.h | 4 +- drivers/mac/mcf5225x_eth_driver.c | 4 +- drivers/mac/mcf5225x_eth_driver.h | 4 +- drivers/mac/mcimx6ul_eth1_driver.c | 4 +- drivers/mac/mcimx6ul_eth1_driver.h | 4 +- drivers/mac/mcimx6ul_eth2_driver.c | 4 +- drivers/mac/mcimx6ul_eth2_driver.h | 4 +- drivers/mac/mimxrt1020_eth_driver.c | 4 +- drivers/mac/mimxrt1020_eth_driver.h | 4 +- drivers/mac/mimxrt1050_eth_driver.c | 4 +- drivers/mac/mimxrt1050_eth_driver.h | 4 +- drivers/mac/mimxrt1060_eth_driver.c | 4 +- drivers/mac/mimxrt1060_eth_driver.h | 4 +- drivers/mac/mk6x_eth_driver.c | 4 +- drivers/mac/mk6x_eth_driver.h | 4 +- drivers/mac/mk7x_eth_driver.c | 4 +- drivers/mac/mk7x_eth_driver.h | 4 +- drivers/mac/mkv5x_eth_driver.c | 4 +- drivers/mac/mkv5x_eth_driver.h | 4 +- drivers/mac/mpc57xx_eth_driver.c | 4 +- drivers/mac/mpc57xx_eth_driver.h | 4 +- drivers/mac/mpfsxxx_eth1_driver.c | 4 +- drivers/mac/mpfsxxx_eth1_driver.h | 4 +- drivers/mac/mpfsxxx_eth2_driver.c | 4 +- drivers/mac/mpfsxxx_eth2_driver.h | 4 +- drivers/mac/msp432e4_eth_driver.c | 4 +- drivers/mac/msp432e4_eth_driver.h | 4 +- drivers/mac/nuc472_eth_driver.c | 4 +- drivers/mac/nuc472_eth_driver.h | 4 +- drivers/mac/omapl138_eth_driver.c | 6 +- drivers/mac/omapl138_eth_driver.h | 4 +- drivers/mac/pic32mx_eth_driver.c | 4 +- drivers/mac/pic32mx_eth_driver.h | 4 +- drivers/mac/pic32mz_eth_driver.c | 4 +- drivers/mac/pic32mz_eth_driver.h | 4 +- drivers/mac/ra6m3_eth_driver.c | 4 +- drivers/mac/ra6m3_eth_driver.h | 4 +- drivers/mac/rx62n_eth_driver.c | 6 +- drivers/mac/rx62n_eth_driver.h | 4 +- drivers/mac/rx63n_eth_driver.c | 11 +- drivers/mac/rx63n_eth_driver.h | 4 +- drivers/mac/rza1_eth_driver.c | 22 +- drivers/mac/rza1_eth_driver.h | 9 +- drivers/mac/s32k148_eth_driver.c | 4 +- drivers/mac/s32k148_eth_driver.h | 4 +- drivers/mac/s5d9_eth_driver.c | 4 +- drivers/mac/s5d9_eth_driver.h | 4 +- drivers/mac/s7g2_eth_driver.c | 4 +- drivers/mac/s7g2_eth_driver.h | 4 +- drivers/mac/sam3x_eth_driver.c | 4 +- drivers/mac/sam3x_eth_driver.h | 4 +- drivers/mac/sam4e_eth_driver.c | 4 +- drivers/mac/sam4e_eth_driver.h | 4 +- drivers/mac/sam7x_eth_driver.c | 4 +- drivers/mac/sam7x_eth_driver.h | 4 +- drivers/mac/sam9263_eth_driver.c | 4 +- drivers/mac/sam9263_eth_driver.h | 4 +- drivers/mac/sama5d2_eth_driver.c | 4 +- drivers/mac/sama5d2_eth_driver.h | 4 +- drivers/mac/sama5d3_eth_driver.c | 4 +- drivers/mac/sama5d3_eth_driver.h | 4 +- drivers/mac/sama5d3_geth_driver.c | 4 +- drivers/mac/sama5d3_geth_driver.h | 4 +- drivers/mac/same54_eth_driver.c | 4 +- drivers/mac/same54_eth_driver.h | 4 +- drivers/mac/same70_eth_driver.c | 4 +- drivers/mac/same70_eth_driver.h | 4 +- drivers/mac/samv71_eth_driver.c | 4 +- drivers/mac/samv71_eth_driver.h | 4 +- drivers/mac/stm32f1xx_eth_driver.c | 4 +- drivers/mac/stm32f1xx_eth_driver.h | 4 +- drivers/mac/stm32f2xx_eth_driver.c | 4 +- drivers/mac/stm32f2xx_eth_driver.h | 4 +- drivers/mac/stm32f4xx_eth_driver.c | 4 +- drivers/mac/stm32f4xx_eth_driver.h | 4 +- drivers/mac/stm32f7xx_eth_driver.c | 4 +- drivers/mac/stm32f7xx_eth_driver.h | 4 +- drivers/mac/stm32h7xx_eth_driver.c | 56 +- drivers/mac/stm32h7xx_eth_driver.h | 4 +- drivers/mac/stm32mp1xx_eth_driver.c | 4 +- drivers/mac/stm32mp1xx_eth_driver.h | 4 +- drivers/mac/str912_eth_driver.c | 4 +- drivers/mac/str912_eth_driver.h | 4 +- drivers/mac/tm4c129_eth_driver.c | 4 +- drivers/mac/tm4c129_eth_driver.h | 4 +- drivers/mac/tms570_eth_driver.c | 6 +- drivers/mac/tms570_eth_driver.h | 4 +- drivers/mac/xmc4400_eth_driver.c | 956 ++++++++++++++++++ drivers/mac/xmc4400_eth_driver.h | 304 ++++++ drivers/mac/xmc4500_eth_driver.c | 4 +- drivers/mac/xmc4500_eth_driver.h | 4 +- drivers/mac/xmc4700_eth_driver.c | 4 +- drivers/mac/xmc4700_eth_driver.h | 4 +- drivers/mac/xmc4800_eth_driver.c | 4 +- drivers/mac/xmc4800_eth_driver.h | 4 +- drivers/mac/zynq7000_eth_driver.c | 6 +- drivers/mac/zynq7000_eth_driver.h | 4 +- drivers/pcap/pcap_driver.c | 4 +- drivers/pcap/pcap_driver.h | 4 +- drivers/phy/ar8031_driver.c | 4 +- drivers/phy/ar8031_driver.h | 4 +- drivers/phy/ar8035_driver.c | 4 +- drivers/phy/ar8035_driver.h | 4 +- drivers/phy/dm9161_driver.c | 4 +- drivers/phy/dm9161_driver.h | 4 +- drivers/phy/dp83620_driver.c | 4 +- drivers/phy/dp83620_driver.h | 4 +- drivers/phy/dp83630_driver.c | 4 +- drivers/phy/dp83630_driver.h | 4 +- drivers/phy/dp83640_driver.c | 4 +- drivers/phy/dp83640_driver.h | 4 +- drivers/phy/dp83822_driver.c | 4 +- drivers/phy/dp83822_driver.h | 4 +- drivers/phy/dp83848_driver.c | 4 +- drivers/phy/dp83848_driver.h | 4 +- drivers/phy/dp83tc811_driver.c | 4 +- drivers/phy/dp83tc811_driver.h | 4 +- drivers/phy/ip101_driver.c | 4 +- drivers/phy/ip101_driver.h | 4 +- drivers/phy/ksz8031_driver.c | 4 +- drivers/phy/ksz8031_driver.h | 4 +- drivers/phy/ksz8041_driver.c | 4 +- drivers/phy/ksz8041_driver.h | 4 +- drivers/phy/ksz8051_driver.c | 4 +- drivers/phy/ksz8051_driver.h | 4 +- drivers/phy/ksz8061_driver.c | 4 +- drivers/phy/ksz8061_driver.h | 4 +- drivers/phy/ksz8081_driver.c | 4 +- drivers/phy/ksz8081_driver.h | 4 +- drivers/phy/ksz8091_driver.c | 4 +- drivers/phy/ksz8091_driver.h | 4 +- drivers/phy/ksz8721_driver.c | 4 +- drivers/phy/ksz8721_driver.h | 4 +- drivers/phy/ksz9031_driver.c | 4 +- drivers/phy/ksz9031_driver.h | 4 +- drivers/phy/ksz9131_driver.c | 324 ++++++ drivers/phy/ksz9131_driver.h | 315 ++++++ drivers/phy/lan8700_driver.c | 4 +- drivers/phy/lan8700_driver.h | 4 +- drivers/phy/lan8710_driver.c | 4 +- drivers/phy/lan8710_driver.h | 4 +- drivers/phy/lan8720_driver.c | 4 +- drivers/phy/lan8720_driver.h | 4 +- drivers/phy/lan8740_driver.c | 4 +- drivers/phy/lan8740_driver.h | 4 +- drivers/phy/lan8742_driver.c | 4 +- drivers/phy/lan8742_driver.h | 4 +- drivers/phy/lan8770_driver.c | 4 +- drivers/phy/lan8770_driver.h | 4 +- drivers/phy/mv88e1512_driver.c | 4 +- drivers/phy/mv88e1512_driver.h | 4 +- drivers/phy/pef7071_driver.c | 302 ++++++ drivers/phy/pef7071_driver.h | 849 ++++++++++++++++ drivers/phy/rtl8211e_driver.c | 4 +- drivers/phy/rtl8211e_driver.h | 4 +- drivers/phy/rtl8211f_driver.c | 4 +- drivers/phy/rtl8211f_driver.h | 4 +- drivers/phy/st802rt1a_driver.c | 4 +- drivers/phy/st802rt1a_driver.h | 4 +- drivers/phy/tja1100_driver.c | 6 +- drivers/phy/tja1100_driver.h | 428 ++++---- drivers/phy/tja1101_driver.c | 8 +- drivers/phy/tja1101_driver.h | 450 +++++---- drivers/phy/upd60611_driver.c | 4 +- drivers/phy/upd60611_driver.h | 4 +- drivers/switch/ksz8463_driver.c | 5 +- drivers/switch/ksz8463_driver.h | 4 +- drivers/switch/ksz8563_driver.c | 5 +- drivers/switch/ksz8563_driver.h | 4 +- drivers/switch/ksz8775_driver.c | 5 +- drivers/switch/ksz8775_driver.h | 4 +- drivers/switch/ksz8794_driver.c | 5 +- drivers/switch/ksz8794_driver.h | 4 +- drivers/switch/ksz8795_driver.c | 5 +- drivers/switch/ksz8795_driver.h | 4 +- drivers/switch/ksz8863_driver.c | 5 +- drivers/switch/ksz8863_driver.h | 4 +- drivers/switch/ksz8864_driver.c | 5 +- drivers/switch/ksz8864_driver.h | 4 +- drivers/switch/ksz8873_driver.c | 5 +- drivers/switch/ksz8873_driver.h | 4 +- drivers/switch/ksz8895_driver.c | 5 +- drivers/switch/ksz8895_driver.h | 4 +- drivers/switch/ksz9477_driver.c | 5 +- drivers/switch/ksz9477_driver.h | 4 +- drivers/switch/ksz9563_driver.c | 5 +- drivers/switch/ksz9563_driver.h | 4 +- drivers/switch/ksz9893_driver.c | 5 +- drivers/switch/ksz9893_driver.h | 4 +- drivers/switch/ksz9897_driver.c | 5 +- drivers/switch/ksz9897_driver.h | 4 +- drivers/switch/lan9303_driver.c | 5 +- drivers/switch/lan9303_driver.h | 4 +- drivers/switch/mv88e6060_driver.c | 5 +- drivers/switch/mv88e6060_driver.h | 4 +- drivers/usb_rndis/rndis.c | 4 +- drivers/usb_rndis/rndis.h | 4 +- drivers/usb_rndis/rndis_debug.c | 4 +- drivers/usb_rndis/rndis_debug.h | 4 +- drivers/usb_rndis/rndis_driver.c | 4 +- drivers/usb_rndis/rndis_driver.h | 6 +- drivers/usb_rndis/usbd_desc.c | 4 +- drivers/usb_rndis/usbd_desc.h | 4 +- drivers/usb_rndis/usbd_rndis.c | 4 +- drivers/usb_rndis/usbd_rndis.h | 4 +- drivers/wifi/bcm43362_driver.c | 4 +- drivers/wifi/bcm43362_driver.h | 4 +- drivers/wifi/esp32_wifi_driver.c | 4 +- drivers/wifi/esp32_wifi_driver.h | 4 +- drivers/wifi/esp8266_driver.c | 4 +- drivers/wifi/esp8266_driver.h | 4 +- drivers/wifi/mrf24wg_driver.c | 4 +- drivers/wifi/mrf24wg_driver.h | 4 +- drivers/wifi/wf200_driver.c | 4 +- drivers/wifi/wf200_driver.h | 4 +- drivers/wifi/wilc1000_driver.c | 4 +- drivers/wifi/wilc1000_driver.h | 4 +- drivers/wifi/winc1500_driver.c | 4 +- drivers/wifi/winc1500_driver.h | 4 +- ftp/ftp_client.c | 8 +- ftp/ftp_client.h | 4 +- ftp/ftp_client_misc.c | 19 +- ftp/ftp_client_misc.h | 4 +- ftp/ftp_client_transport.c | 4 +- ftp/ftp_client_transport.h | 4 +- ftp/ftp_server.c | 4 +- ftp/ftp_server.h | 4 +- ftp/ftp_server_commands.c | 9 +- ftp/ftp_server_commands.h | 4 +- ftp/ftp_server_control.c | 4 +- ftp/ftp_server_control.h | 4 +- ftp/ftp_server_data.c | 4 +- ftp/ftp_server_data.h | 4 +- ftp/ftp_server_misc.c | 4 +- ftp/ftp_server_misc.h | 4 +- ftp/ftp_server_transport.c | 4 +- ftp/ftp_server_transport.h | 4 +- http/http_client.c | 16 +- http/http_client.h | 4 +- http/http_client_auth.c | 12 +- http/http_client_auth.h | 4 +- http/http_client_misc.c | 6 +- http/http_client_misc.h | 4 +- http/http_client_transport.c | 4 +- http/http_client_transport.h | 4 +- http/http_common.c | 17 +- http/http_common.h | 4 +- http/http_server.c | 4 +- http/http_server.h | 4 +- http/http_server_auth.c | 8 +- http/http_server_auth.h | 4 +- http/http_server_misc.c | 10 +- http/http_server_misc.h | 4 +- http/mime.c | 4 +- http/mime.h | 4 +- http/ssi.c | 10 +- http/ssi.h | 4 +- icecast/icecast_client.c | 6 +- icecast/icecast_client.h | 4 +- ipv4/arp.c | 4 +- ipv4/arp.h | 4 +- ipv4/auto_ip.c | 4 +- ipv4/auto_ip.h | 4 +- ipv4/icmp.c | 4 +- ipv4/icmp.h | 4 +- ipv4/igmp.c | 4 +- ipv4/igmp.h | 4 +- ipv4/ipv4.c | 4 +- ipv4/ipv4.h | 4 +- ipv4/ipv4_frag.c | 4 +- ipv4/ipv4_frag.h | 4 +- ipv4/ipv4_misc.c | 4 +- ipv4/ipv4_misc.h | 4 +- ipv4/ipv4_routing.h | 4 +- ipv6/icmpv6.c | 4 +- ipv6/icmpv6.h | 4 +- ipv6/ipv6.c | 4 +- ipv6/ipv6.h | 4 +- ipv6/ipv6_frag.c | 4 +- ipv6/ipv6_frag.h | 4 +- ipv6/ipv6_misc.c | 6 +- ipv6/ipv6_misc.h | 4 +- ipv6/ipv6_pmtu.c | 4 +- ipv6/ipv6_pmtu.h | 4 +- ipv6/ipv6_routing.c | 6 +- ipv6/ipv6_routing.h | 4 +- ipv6/mld.c | 4 +- ipv6/mld.h | 4 +- ipv6/ndp.c | 4 +- ipv6/ndp.h | 4 +- ipv6/ndp_cache.c | 4 +- ipv6/ndp_cache.h | 4 +- ipv6/ndp_misc.c | 8 +- ipv6/ndp_misc.h | 4 +- ipv6/ndp_router_adv.c | 4 +- ipv6/ndp_router_adv.h | 4 +- ipv6/slaac.c | 4 +- ipv6/slaac.h | 4 +- llmnr/llmnr_client.c | 4 +- llmnr/llmnr_client.h | 4 +- llmnr/llmnr_common.c | 4 +- llmnr/llmnr_common.h | 4 +- llmnr/llmnr_responder.c | 4 +- llmnr/llmnr_responder.h | 4 +- mdns/mdns_client.c | 4 +- mdns/mdns_client.h | 4 +- mdns/mdns_common.c | 4 +- mdns/mdns_common.h | 4 +- mdns/mdns_responder.c | 4 +- mdns/mdns_responder.h | 4 +- mibs/if_mib_impl.c | 4 +- mibs/if_mib_impl.h | 4 +- mibs/if_mib_module.c | 4 +- mibs/if_mib_module.h | 4 +- mibs/ip_mib_impl.c | 4 +- mibs/ip_mib_impl.h | 4 +- mibs/ip_mib_module.c | 4 +- mibs/ip_mib_module.h | 4 +- mibs/mib2_impl.c | 4 +- mibs/mib2_impl.h | 4 +- mibs/mib2_module.c | 4 +- mibs/mib2_module.h | 4 +- mibs/mib_common.c | 4 +- mibs/mib_common.h | 4 +- mibs/snmp_community_mib_impl.c | 4 +- mibs/snmp_community_mib_impl.h | 4 +- mibs/snmp_community_mib_module.c | 4 +- mibs/snmp_community_mib_module.h | 4 +- mibs/snmp_framework_mib_impl.c | 4 +- mibs/snmp_framework_mib_impl.h | 4 +- mibs/snmp_framework_mib_module.c | 4 +- mibs/snmp_framework_mib_module.h | 4 +- mibs/snmp_mib_impl.c | 4 +- mibs/snmp_mib_impl.h | 4 +- mibs/snmp_mib_module.c | 4 +- mibs/snmp_mib_module.h | 4 +- mibs/snmp_mpd_mib_impl.c | 4 +- mibs/snmp_mpd_mib_impl.h | 4 +- mibs/snmp_mpd_mib_module.c | 4 +- mibs/snmp_mpd_mib_module.h | 4 +- mibs/snmp_usm_mib_impl.c | 4 +- mibs/snmp_usm_mib_impl.h | 4 +- mibs/snmp_usm_mib_module.c | 4 +- mibs/snmp_usm_mib_module.h | 4 +- mibs/snmp_vacm_mib_impl.c | 4 +- mibs/snmp_vacm_mib_impl.h | 4 +- mibs/snmp_vacm_mib_module.c | 4 +- mibs/snmp_vacm_mib_module.h | 4 +- mibs/tcp_mib_impl.c | 4 +- mibs/tcp_mib_impl.h | 4 +- mibs/tcp_mib_module.c | 4 +- mibs/tcp_mib_module.h | 4 +- mibs/udp_mib_impl.c | 4 +- mibs/udp_mib_impl.h | 4 +- mibs/udp_mib_module.c | 4 +- mibs/udp_mib_module.h | 4 +- modbus/modbus_client.c | 4 +- modbus/modbus_client.h | 4 +- modbus/modbus_client_misc.c | 4 +- modbus/modbus_client_misc.h | 4 +- modbus/modbus_client_pdu.c | 4 +- modbus/modbus_client_pdu.h | 4 +- modbus/modbus_client_transport.c | 4 +- modbus/modbus_client_transport.h | 4 +- modbus/modbus_common.h | 4 +- modbus/modbus_debug.c | 4 +- modbus/modbus_debug.h | 4 +- modbus/modbus_server.c | 4 +- modbus/modbus_server.h | 4 +- modbus/modbus_server_misc.c | 4 +- modbus/modbus_server_misc.h | 4 +- modbus/modbus_server_pdu.c | 4 +- modbus/modbus_server_pdu.h | 4 +- modbus/modbus_server_security.c | 4 +- modbus/modbus_server_security.h | 4 +- modbus/modbus_server_transport.c | 4 +- modbus/modbus_server_transport.h | 4 +- mqtt/mqtt_client.c | 4 +- mqtt/mqtt_client.h | 4 +- mqtt/mqtt_client_misc.c | 4 +- mqtt/mqtt_client_misc.h | 4 +- mqtt/mqtt_client_packet.c | 4 +- mqtt/mqtt_client_packet.h | 4 +- mqtt/mqtt_client_transport.c | 4 +- mqtt/mqtt_client_transport.h | 4 +- mqtt/mqtt_common.h | 4 +- mqtt_sn/mqtt_sn_client.c | 14 +- mqtt_sn/mqtt_sn_client.h | 8 +- mqtt_sn/mqtt_sn_client_message.c | 8 +- mqtt_sn/mqtt_sn_client_message.h | 4 +- mqtt_sn/mqtt_sn_client_misc.c | 6 +- mqtt_sn/mqtt_sn_client_misc.h | 4 +- mqtt_sn/mqtt_sn_client_transport.c | 4 +- mqtt_sn/mqtt_sn_client_transport.h | 4 +- mqtt_sn/mqtt_sn_common.h | 4 +- mqtt_sn/mqtt_sn_debug.c | 4 +- mqtt_sn/mqtt_sn_debug.h | 4 +- mqtt_sn/mqtt_sn_message.c | 4 +- mqtt_sn/mqtt_sn_message.h | 4 +- netbios/nbns_client.c | 4 +- netbios/nbns_client.h | 4 +- netbios/nbns_common.c | 4 +- netbios/nbns_common.h | 4 +- netbios/nbns_responder.c | 4 +- netbios/nbns_responder.h | 4 +- ppp/chap.c | 4 +- ppp/chap.h | 4 +- ppp/ipcp.c | 4 +- ppp/ipcp.h | 4 +- ppp/ipv6cp.c | 4 +- ppp/ipv6cp.h | 4 +- ppp/lcp.c | 4 +- ppp/lcp.h | 4 +- ppp/pap.c | 4 +- ppp/pap.h | 4 +- ppp/ppp.c | 4 +- ppp/ppp.h | 4 +- ppp/ppp_debug.c | 4 +- ppp/ppp_debug.h | 4 +- ppp/ppp_fsm.c | 4 +- ppp/ppp_fsm.h | 4 +- ppp/ppp_hdlc.c | 4 +- ppp/ppp_hdlc.h | 4 +- ppp/ppp_misc.c | 4 +- ppp/ppp_misc.h | 4 +- smtp/smtp_client.c | 4 +- smtp/smtp_client.h | 4 +- smtp/smtp_client_auth.c | 4 +- smtp/smtp_client_auth.h | 4 +- smtp/smtp_client_misc.c | 4 +- smtp/smtp_client_misc.h | 4 +- smtp/smtp_client_transport.c | 4 +- smtp/smtp_client_transport.h | 4 +- snmp/snmp_agent.c | 4 +- snmp/snmp_agent.h | 4 +- snmp/snmp_agent_dispatch.c | 4 +- snmp/snmp_agent_dispatch.h | 4 +- snmp/snmp_agent_inform.c | 4 +- snmp/snmp_agent_inform.h | 4 +- snmp/snmp_agent_message.c | 4 +- snmp/snmp_agent_message.h | 4 +- snmp/snmp_agent_misc.c | 4 +- snmp/snmp_agent_misc.h | 4 +- snmp/snmp_agent_object.c | 4 +- snmp/snmp_agent_object.h | 4 +- snmp/snmp_agent_pdu.c | 4 +- snmp/snmp_agent_pdu.h | 4 +- snmp/snmp_agent_trap.c | 4 +- snmp/snmp_agent_trap.h | 4 +- snmp/snmp_agent_usm.c | 4 +- snmp/snmp_agent_usm.h | 4 +- snmp/snmp_agent_vacm.c | 4 +- snmp/snmp_agent_vacm.h | 4 +- snmp/snmp_common.h | 4 +- sntp/ntp_common.h | 4 +- sntp/sntp_client.c | 4 +- sntp/sntp_client.h | 4 +- sntp/sntp_client_misc.c | 4 +- sntp/sntp_client_misc.h | 4 +- tftp/tftp_client.c | 4 +- tftp/tftp_client.h | 4 +- tftp/tftp_client_misc.c | 4 +- tftp/tftp_client_misc.h | 4 +- tftp/tftp_common.h | 4 +- tftp/tftp_server.c | 4 +- tftp/tftp_server.h | 4 +- tftp/tftp_server_misc.c | 4 +- tftp/tftp_server_misc.h | 4 +- web_socket/web_socket.c | 4 +- web_socket/web_socket.h | 4 +- web_socket/web_socket_auth.c | 6 +- web_socket/web_socket_auth.h | 4 +- web_socket/web_socket_frame.c | 4 +- web_socket/web_socket_frame.h | 4 +- web_socket/web_socket_misc.c | 8 +- web_socket/web_socket_misc.h | 4 +- web_socket/web_socket_transport.c | 4 +- web_socket/web_socket_transport.h | 4 +- 611 files changed, 7465 insertions(+), 3730 deletions(-) rename drivers/mac/{lpc546xx_eth_driver.c => lpc54xxx_eth_driver.c} (77%) rename drivers/mac/{lpc546xx_eth_driver.h => lpc54xxx_eth_driver.h} (67%) create mode 100644 drivers/mac/xmc4400_eth_driver.c create mode 100644 drivers/mac/xmc4400_eth_driver.h create mode 100644 drivers/phy/ksz9131_driver.c create mode 100644 drivers/phy/ksz9131_driver.h create mode 100644 drivers/phy/pef7071_driver.c create mode 100644 drivers/phy/pef7071_driver.h diff --git a/coap/coap_client.c b/coap/coap_client.c index a87eaaf4..afd031bd 100644 --- a/coap/coap_client.c +++ b/coap/coap_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/coap/coap_client.h b/coap/coap_client.h index b6ef191d..76fc042b 100644 --- a/coap/coap_client.h +++ b/coap/coap_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_CLIENT_H diff --git a/coap/coap_client_block.c b/coap/coap_client_block.c index ae6d8c4f..6e493f8e 100644 --- a/coap/coap_client_block.c +++ b/coap/coap_client_block.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -61,23 +61,39 @@ error_t coapClientSetTxBlockSize(CoapClientRequest *request, uint_t blockSize) //Set TX block size if(blockSize == 16) + { request->txBlockSzx = COAP_BLOCK_SIZE_16; + } else if(blockSize == 32) + { request->txBlockSzx = COAP_BLOCK_SIZE_32; + } else if(blockSize == 64) + { request->txBlockSzx = COAP_BLOCK_SIZE_64; + } else if(blockSize == 128) + { request->txBlockSzx = COAP_BLOCK_SIZE_128; + } else if(blockSize == 256) + { request->txBlockSzx = COAP_BLOCK_SIZE_256; + } else if(blockSize == 512) + { request->txBlockSzx = COAP_BLOCK_SIZE_512; + } else + { request->txBlockSzx = COAP_BLOCK_SIZE_1024; + } //Ensure the block size is acceptable if(request->txBlockSzx > coapClientGetMaxBlockSize()) + { request->txBlockSzx = coapClientGetMaxBlockSize(); + } //Release exclusive access to the CoAP client context osReleaseMutex(&request->context->mutex); @@ -105,23 +121,39 @@ error_t coapClientSetRxBlockSize(CoapClientRequest *request, uint_t blockSize) //Set RX block size if(blockSize == 16) + { request->rxBlockSzx = COAP_BLOCK_SIZE_16; + } else if(blockSize == 32) + { request->rxBlockSzx = COAP_BLOCK_SIZE_32; + } else if(blockSize == 64) + { request->rxBlockSzx = COAP_BLOCK_SIZE_64; + } else if(blockSize == 128) + { request->rxBlockSzx = COAP_BLOCK_SIZE_128; + } else if(blockSize == 256) + { request->rxBlockSzx = COAP_BLOCK_SIZE_256; + } else if(blockSize == 512) + { request->rxBlockSzx = COAP_BLOCK_SIZE_512; + } else + { request->rxBlockSzx = COAP_BLOCK_SIZE_1024; + } //Ensure the block size is acceptable if(request->rxBlockSzx > coapClientGetMaxBlockSize()) + { request->rxBlockSzx = coapClientGetMaxBlockSize(); + } //Release exclusive access to the CoAP client context osReleaseMutex(&request->context->mutex); @@ -224,9 +256,13 @@ error_t coapClientWriteBody(CoapClientRequest *request, //The M bit indicates whether further blocks need to be transferred //to complete the transfer of the body if(length == 0 && last) + { COAP_SET_BLOCK_M(value, 0); + } else + { COAP_SET_BLOCK_M(value, 1); + } //Set block size COAP_SET_BLOCK_SZX(value, blockSzx); @@ -517,9 +553,13 @@ error_t coapClientReadBody(CoapClientRequest *request, void *data, { //The Block2 option is not present in the response if(blockPos == 0) + { error = ERROR_END_OF_STREAM; + } else + { error = ERROR_FAILURE; + } //Exit immediately break; diff --git a/coap/coap_client_block.h b/coap/coap_client_block.h index c0c735af..12b38a87 100644 --- a/coap/coap_client_block.h +++ b/coap/coap_client_block.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_CLIENT_BLOCK_H diff --git a/coap/coap_client_misc.c b/coap/coap_client_misc.c index 9bb16dba..84597d9d 100644 --- a/coap/coap_client_misc.c +++ b/coap/coap_client_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/coap/coap_client_misc.h b/coap/coap_client_misc.h index d70106aa..8697a80a 100644 --- a/coap/coap_client_misc.h +++ b/coap/coap_client_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_CLIENT_MISC_H diff --git a/coap/coap_client_observe.c b/coap/coap_client_observe.c index 6b7846b6..994b4e06 100644 --- a/coap/coap_client_observe.c +++ b/coap/coap_client_observe.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/coap/coap_client_observe.h b/coap/coap_client_observe.h index 858f0a7f..835ee26c 100644 --- a/coap/coap_client_observe.h +++ b/coap/coap_client_observe.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_CLIENT_OBSERVE_H diff --git a/coap/coap_client_request.c b/coap/coap_client_request.c index f867dab6..9210e2b5 100644 --- a/coap/coap_client_request.c +++ b/coap/coap_client_request.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -344,7 +344,6 @@ error_t coapClientCancelRequest(CoapClientRequest *request) /** * @brief Release the resources associated with a CoAP request * @param[in] request CoAP request handle - * @return Pointer to the CoAP request **/ void coapClientDeleteRequest(CoapClientRequest *request) diff --git a/coap/coap_client_request.h b/coap/coap_client_request.h index 2fd9a68a..16fc70c5 100644 --- a/coap/coap_client_request.h +++ b/coap/coap_client_request.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_CLIENT_REQUEST_H diff --git a/coap/coap_client_transport.c b/coap/coap_client_transport.c index 9a431894..8e59fbcb 100644 --- a/coap/coap_client_transport.c +++ b/coap/coap_client_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/coap/coap_client_transport.h b/coap/coap_client_transport.h index 54427a3a..346cb81c 100644 --- a/coap/coap_client_transport.h +++ b/coap/coap_client_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_CLIENT_TRANSPORT_H diff --git a/coap/coap_common.h b/coap/coap_common.h index 4c2b9715..e44faa9a 100644 --- a/coap/coap_common.h +++ b/coap/coap_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_COMMON_H @@ -142,6 +142,7 @@ typedef enum COAP_CODE_SERVICE_UNAVAILABLE = COAP_CODE(5, 3), COAP_CODE_GATEWAY_TIMEOUT = COAP_CODE(5, 4), COAP_CODE_PROXYING_NOT_SUPPORTED = COAP_CODE(5, 5), + COAP_CODE_HOP_LIMIT_REACHED = COAP_CODE(5, 8), COAP_CODE_CSM = COAP_CODE(7, 1), COAP_CODE_PING = COAP_CODE(7, 2), COAP_CODE_PONG = COAP_CODE(7, 3), diff --git a/coap/coap_debug.c b/coap/coap_debug.c index 34c07198..0954a2aa 100644 --- a/coap/coap_debug.c +++ b/coap/coap_debug.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/coap/coap_debug.h b/coap/coap_debug.h index 880cbe23..dfe8a63e 100644 --- a/coap/coap_debug.h +++ b/coap/coap_debug.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_DEBUG_H diff --git a/coap/coap_message.c b/coap/coap_message.c index e5b052a6..bb1325e4 100644 --- a/coap/coap_message.c +++ b/coap/coap_message.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/coap/coap_message.h b/coap/coap_message.h index 963ac6da..549c96f7 100644 --- a/coap/coap_message.h +++ b/coap/coap_message.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_MESSAGE_H diff --git a/coap/coap_option.c b/coap/coap_option.c index ad20297e..e3b0713d 100644 --- a/coap/coap_option.c +++ b/coap/coap_option.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/coap/coap_option.h b/coap/coap_option.h index 34f0512b..13a7534d 100644 --- a/coap/coap_option.h +++ b/coap/coap_option.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_OPTION_H @@ -179,6 +179,8 @@ typedef enum COAP_CONTENT_FORMAT_APP_PKIX_CERT = 287, COAP_CONTENT_FORMAT_APP_SENML_XML = 310, COAP_CONTENT_FORMAT_APP_SENSML_XML = 311, + COAP_CONTENT_FORMAT_SENML_ETCH_JSON = 320, + COAP_CONTENT_FORMAT_SENML_ETCH_CBOR = 322, COAP_CONTENT_FORMAT_APP_VND_OCF_CBOR = 10000, COAP_CONTENT_FORMAT_APP_OSCORE = 10001, COAP_CONTENT_FORMAT_APP_JSON_DEFLATE = 11050, diff --git a/coap/coap_server.c b/coap/coap_server.c index ae6e1766..a7d009b4 100644 --- a/coap/coap_server.c +++ b/coap/coap_server.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/coap/coap_server.h b/coap/coap_server.h index 07777ee9..86b9c36e 100644 --- a/coap/coap_server.h +++ b/coap/coap_server.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_SERVER_H diff --git a/coap/coap_server_misc.c b/coap/coap_server_misc.c index fc3fd19e..eb0923e8 100644 --- a/coap/coap_server_misc.c +++ b/coap/coap_server_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -106,7 +106,8 @@ void coapServerTick(CoapServerContext *context) /** * @brief Process CoAP request * @param[in] context Pointer to the CoAP server context - * @param[in] request Pointer to the request message + * @param[in] data Pointer to the incoming CoAP message + * @param[in] length Length of the CoAP message, in bytes * @return Error code **/ @@ -332,7 +333,7 @@ error_t coapServerInitResponse(CoapServerContext *context) context->response.length = sizeof(CoapMessageHeader) + responseHeader->tokenLen; context->response.pos = 0; - //Sucessful processing + //Successful processing return NO_ERROR; } @@ -428,7 +429,7 @@ error_t coapServerFormatReset(CoapServerContext *context, uint16_t mid) //Set the length of the CoAP message context->response.length = sizeof(CoapMessageHeader); - //Sucessful processing + //Successful processing return NO_ERROR; } diff --git a/coap/coap_server_misc.h b/coap/coap_server_misc.h index 0003d4df..7f4afbd8 100644 --- a/coap/coap_server_misc.h +++ b/coap/coap_server_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_SERVER_MISC_H diff --git a/coap/coap_server_request.c b/coap/coap_server_request.c index ffb0280e..294c589f 100644 --- a/coap/coap_server_request.c +++ b/coap/coap_server_request.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -102,7 +102,7 @@ error_t coapServerGetUriQuery(CoapServerContext *context, char_t *queryString, /** * @brief Read an opaque option from the CoAP request - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] optionNum Option number to search for * @param[in] optionIndex Occurrence index (for repeatable options only) * @param[out] optionValue Pointer to the first byte of the option value @@ -125,7 +125,7 @@ error_t coapServerGetOpaqueOption(CoapServerContext *context, uint16_t optionNum /** * @brief Read a string option from the CoAP request - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] optionNum Option number to search for * @param[in] optionIndex Occurrence index (for repeatable options only) * @param[out] optionValue Pointer to the first byte of the option value @@ -148,7 +148,7 @@ error_t coapServerGetStringOption(CoapServerContext *context, uint16_t optionNum /** * @brief Read an uint option from the CoAP request - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] optionNum Option number to search for * @param[in] optionIndex Occurrence index (for repeatable options only) * @param[out] optionValue Option value (unsigned integer) @@ -170,7 +170,7 @@ error_t coapServerGetUintOption(CoapServerContext *context, uint16_t optionNum, /** * @brief Get request payload - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[out] payload Pointer to the first byte of the payload * @param[out] payloadLen Length of the payload, in bytes * @return Error code @@ -190,7 +190,7 @@ error_t coapServerGetPayload(CoapServerContext *context, const uint8_t **payload /** * @brief Read request payload data - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[out] data Buffer into which received data will be placed * @param[in] size Maximum number of bytes that can be received * @param[out] length Number of bytes that have been received @@ -211,7 +211,7 @@ error_t coapServerReadPayload(CoapServerContext *context, void *data, size_t siz /** * @brief Set response method - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] code Response code * @return Error code **/ @@ -229,7 +229,7 @@ error_t coapServerSetResponseCode(CoapServerContext *context, CoapCode code) /** * @brief Set Location-Path option - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] path NULL-terminated string that contains the path component * @return Error code **/ @@ -249,7 +249,7 @@ error_t coapServerSetLocationPath(CoapServerContext *context, /** * @brief Set Location-Query option - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] queryString NULL-terminated string that contains the query string * @return Error code **/ @@ -269,7 +269,7 @@ error_t coapServerSetLocationQuery(CoapServerContext *context, /** * @brief Add an opaque option to the CoAP response - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] optionNum Option number * @param[in] optionIndex Occurrence index (for repeatable options only) * @param[in] optionValue Pointer to the first byte of the option value @@ -296,7 +296,7 @@ error_t coapServerSetOpaqueOption(CoapServerContext *context, uint16_t optionNum /** * @brief Add a string option to the CoAP response - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] optionNum Option number * @param[in] optionIndex Occurrence index (for repeatable options only) * @param[in] optionValue NULL-terminated string that contains the option value @@ -323,7 +323,7 @@ error_t coapServerSetStringOption(CoapServerContext *context, uint16_t optionNum /** * @brief Add a uint option to the CoAP response - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] optionNum Option number * @param[in] optionIndex Occurrence index (for repeatable options only) * @param[in] optionValue Option value (unsigned integer) @@ -345,7 +345,7 @@ error_t coapServerSetUintOption(CoapServerContext *context, uint16_t optionNum, /** * @brief Remove an option from the CoAP response - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] optionNum Option number * @param[in] optionIndex Occurrence index (for repeatable options only) * @return Error code @@ -365,7 +365,7 @@ error_t coapServerDeleteOption(CoapServerContext *context, uint16_t optionNum, /** * @brief Set response payload - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[out] payload Pointer to request payload * @param[out] payloadLen Length of the payload, in bytes * @return Error code @@ -389,7 +389,7 @@ error_t coapServerSetPayload(CoapServerContext *context, const void *payload, /** * @brief Write payload data - * @param[in] message Pointer to the CoAP message + * @param[in] context Pointer to the CoAP server context * @param[in] data Pointer to a buffer containing the data to be written * @param[in] length Number of bytes to written * @return Error code diff --git a/coap/coap_server_request.h b/coap/coap_server_request.h index cea24a3d..bcd90fd5 100644 --- a/coap/coap_server_request.h +++ b/coap/coap_server_request.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_SERVER_REQUEST_H diff --git a/coap/coap_server_transport.c b/coap/coap_server_transport.c index ecea436d..64743877 100644 --- a/coap/coap_server_transport.c +++ b/coap/coap_server_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -411,11 +411,11 @@ error_t coapServerReceiveCallback(void *handle, void *data, /** * @brief DTLS cookie generation callback function - * @param[in] context Pointer to the TLS context - * @param[in] clientParams Client parameters + * @param[in] context Pointer to the DTLS context + * @param[in] clientParams Client's parameters * @param[out] cookie Pointer to the first byte of the cookie * @param[in,out] length Length of the cookie, in bytes - * @param[in] param An opaque pointer provided by the user + * @param[in] param Pointer to the DTLS session * @return Error code **/ @@ -480,10 +480,11 @@ error_t coapServerCookieGenerateCallback(TlsContext *context, /** * @brief DTLS cookie verification callback function - * @param[in] handle An opaque pointer specified by the user - * @param[in] params Client parameters + * @param[in] context Pointer to the DTLS context + * @param[in] clientParams Client's parameters * @param[in] cookie Pointer to the first byte of the cookie * @param[in] length Length of the cookie, in bytes + * @param[in] param Pointer to the DTLS session * @return Error code **/ diff --git a/coap/coap_server_transport.h b/coap/coap_server_transport.h index 472dc9a8..5ae31bb0 100644 --- a/coap/coap_server_transport.h +++ b/coap/coap_server_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _COAP_SERVER_TRANSPORT_H diff --git a/core/bsd_socket.c b/core/bsd_socket.c index 0fef7c62..082cb33c 100644 --- a/core/bsd_socket.c +++ b/core/bsd_socket.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -1915,7 +1915,6 @@ int_t selectFdIsSet(fd_set *fds, int_t s) /** * @brief Host name resolution * @param[in] name Name of the host to resolve - * @param[out] info Address of the specified host * @return Pointer to the hostent structure or a NULL if an error occurs **/ diff --git a/core/bsd_socket.h b/core/bsd_socket.h index f5bfa733..bffbe8f8 100644 --- a/core/bsd_socket.h +++ b/core/bsd_socket.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _BSD_SOCKET_H diff --git a/core/ethernet.c b/core/ethernet.c index acde2a56..e86d4fb7 100644 --- a/core/ethernet.c +++ b/core/ethernet.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/core/ethernet.h b/core/ethernet.h index 8de6d2c6..b26db4f3 100644 --- a/core/ethernet.h +++ b/core/ethernet.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ETHERNET_H @@ -158,7 +158,8 @@ typedef enum ETH_TYPE_VLAN = 0x8100, ETH_TYPE_IPV6 = 0x86DD, ETH_TYPE_EAPOL = 0x888E, - ETH_TYPE_VMAN = 0x88A8 + ETH_TYPE_VMAN = 0x88A8, + ETH_TYPE_LLDP = 0x88CC } EthType; diff --git a/core/ethernet_misc.c b/core/ethernet_misc.c index b3fae86f..9c9fa5fe 100644 --- a/core/ethernet_misc.c +++ b/core/ethernet_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/core/ethernet_misc.h b/core/ethernet_misc.h index 6ebe3d0f..cab482b2 100644 --- a/core/ethernet_misc.h +++ b/core/ethernet_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ETHERNET_MISC_H diff --git a/core/ip.c b/core/ip.c index 90e04e64..ac9367f7 100644 --- a/core/ip.c +++ b/core/ip.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -686,7 +686,7 @@ error_t ipStringToAddr(const char_t *str, IpAddr *ipAddr) #if (IPV6_SUPPORT == ENABLED) //IPv6 address? - if(strchr(str, ':')) + if(osStrchr(str, ':') != NULL) { //IPv6 addresses are 16-byte long ipAddr->length = sizeof(Ipv6Addr); @@ -697,7 +697,7 @@ error_t ipStringToAddr(const char_t *str, IpAddr *ipAddr) #endif #if (IPV4_SUPPORT == ENABLED) //IPv4 address? - if(strchr(str, '.')) + if(osStrchr(str, '.') != NULL) { //IPv4 addresses are 4-byte long ipAddr->length = sizeof(Ipv4Addr); diff --git a/core/ip.h b/core/ip.h index a8d1cc73..8af2277a 100644 --- a/core/ip.h +++ b/core/ip.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IP_H diff --git a/core/net.c b/core/net.c index 10fe619e..d31da946 100644 --- a/core/net.c +++ b/core/net.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/core/net.h b/core/net.h index 962f04ac..7c8fb68e 100644 --- a/core/net.h +++ b/core/net.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NET_H @@ -90,13 +90,13 @@ struct _NetInterface; #endif //Version string -#define CYCLONE_TCP_VERSION_STRING "2.0.0" +#define CYCLONE_TCP_VERSION_STRING "2.0.2" //Major version #define CYCLONE_TCP_MAJOR_VERSION 2 //Minor version #define CYCLONE_TCP_MINOR_VERSION 0 //Revision number -#define CYCLONE_TCP_REV_NUMBER 0 +#define CYCLONE_TCP_REV_NUMBER 2 //RTOS support #ifndef NET_RTOS_SUPPORT diff --git a/core/net_legacy.h b/core/net_legacy.h index 380649ad..b1672cef 100644 --- a/core/net_legacy.h +++ b/core/net_legacy.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NET_LEGACY_H diff --git a/core/net_mem.c b/core/net_mem.c index ae4f253f..a99eb1b1 100644 --- a/core/net_mem.c +++ b/core/net_mem.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/core/net_mem.h b/core/net_mem.h index d888b5ee..a21e2e1c 100644 --- a/core/net_mem.h +++ b/core/net_mem.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NET_MEM_H diff --git a/core/net_misc.c b/core/net_misc.c index e57b7666..f75b1ac1 100644 --- a/core/net_misc.c +++ b/core/net_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/core/net_misc.h b/core/net_misc.h index f6fc971a..807b3657 100644 --- a/core/net_misc.h +++ b/core/net_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NET_MISC_H diff --git a/core/nic.c b/core/nic.c index 7f834d25..7c83adbd 100644 --- a/core/nic.c +++ b/core/nic.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -283,9 +283,6 @@ error_t nicSendPacket(NetInterface *interface, const NetBuffer *buffer, error_t error; bool_t status; - //Gather entropy - netContext.entropy += netGetSystemTickCount(); - #if (TRACE_LEVEL >= TRACE_LEVEL_DEBUG) //Retrieve the length of the packet size_t length = netBufferGetLength(buffer) - offset; @@ -295,6 +292,9 @@ error_t nicSendPacket(NetInterface *interface, const NetBuffer *buffer, TRACE_DEBUG_NET_BUFFER(" ", buffer, offset, length); #endif + //Gather entropy + netContext.entropy += netGetSystemTickCount(); + //Check whether the interface is enabled for operation if(interface->configured && interface->nicDriver != NULL) { diff --git a/core/nic.h b/core/nic.h index 5556225b..9cce89ee 100644 --- a/core/nic.h +++ b/core/nic.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NIC_H diff --git a/core/ping.c b/core/ping.c index c3da8b98..6658a153 100644 --- a/core/ping.c +++ b/core/ping.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/core/ping.h b/core/ping.h index 0e44f074..5934131a 100644 --- a/core/ping.h +++ b/core/ping.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _PING_H diff --git a/core/raw_socket.c b/core/raw_socket.c index d4bb38ed..2f0958af 100644 --- a/core/raw_socket.c +++ b/core/raw_socket.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * underlying transport provider * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -246,6 +246,8 @@ error_t rawSocketProcessIpPacket(NetInterface *interface, //Initialize next field queueItem->next = NULL; + //Network interface where the packet was received + queueItem->interface = interface; //Port number is unused queueItem->srcPort = 0; @@ -426,6 +428,9 @@ void rawSocketProcessEthPacket(NetInterface *interface, EthHeader *header, //Initialize next field queueItem->next = NULL; + //Network interface where the packet was received + queueItem->interface = interface; + //Other fields are meaningless queueItem->srcPort = 0; queueItem->srcIpAddr = IP_ADDR_ANY; @@ -468,8 +473,15 @@ error_t rawSocketSendIpPacket(Socket *socket, const SocketMsg *message, IpPseudoHeader pseudoHeader; NetTxAncillary ancillary; - //The socket may be bound to a particular network interface - interface = socket->interface; + //Select the relevant network interface + if(message->interface != NULL) + { + interface = message->interface; + } + else + { + interface = socket->interface; + } //Allocate a buffer memory to hold the raw IP datagram buffer = ipAllocBuffer(0, &offset); @@ -635,7 +647,11 @@ error_t rawSocketSendEthPacket(Socket *socket, const SocketMsg *message, NetInterface *interface; //Select the relevant network interface - if(socket->interface != NULL) + if(message->interface != NULL) + { + interface = message->interface; + } + else if(socket->interface != NULL) { interface = socket->interface; } @@ -751,11 +767,7 @@ error_t rawSocketSendEthPacket(Socket *socket, const SocketMsg *message, /** * @brief Receive an IP packet from a raw socket * @param[in] socket Handle referencing the socket - * @param[out] srcIpAddr Source IP address (optional) - * @param[out] destIpAddr Destination IP address (optional) - * @param[out] data Buffer where to store the incoming data - * @param[in] size Maximum number of bytes that can be received - * @param[out] received Number of bytes that have been received + * @param[out] message Received IP packet and ancillary data * @param[in] flags Set of flags that influences the behavior of this function * @return Error code **/ @@ -797,6 +809,8 @@ error_t rawSocketReceiveIpPacket(Socket *socket, SocketMsg *message, message->length = netBufferRead(message->data, queueItem->buffer, queueItem->offset, message->size); + //Network interface where the packet was received + message->interface = queueItem->interface; //Save the source IP address message->srcIpAddr = queueItem->srcIpAddr; //Save the source port number @@ -857,9 +871,7 @@ error_t rawSocketReceiveIpPacket(Socket *socket, SocketMsg *message, /** * @brief Receive an Ethernet packet from a raw socket * @param[in] socket Handle referencing the socket - * @param[out] data Buffer where to store the incoming data - * @param[in] size Maximum number of bytes that can be received - * @param[out] received Number of bytes that have been received + * @param[out] message Received Ethernet packet and ancillary data * @param[in] flags Set of flags that influences the behavior of this function * @return Error code **/ @@ -901,6 +913,9 @@ error_t rawSocketReceiveEthPacket(Socket *socket, SocketMsg *message, message->length = netBufferRead(message->data, queueItem->buffer, queueItem->offset, message->size); + //Network interface where the packet was received + message->interface = queueItem->interface; + #if (ETH_SUPPORT == ENABLED) //Save source and destination MAC addresses message->srcMacAddr = queueItem->ancillary.srcMacAddr; diff --git a/core/raw_socket.h b/core/raw_socket.h index 651e7810..f7b1c585 100644 --- a/core/raw_socket.h +++ b/core/raw_socket.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _RAW_SOCKET_H diff --git a/core/socket.c b/core/socket.c index 446804b8..68d8164b 100644 --- a/core/socket.c +++ b/core/socket.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -55,6 +55,7 @@ const SocketMsg SOCKET_DEFAULT_MSG = 0, //Size of the payload, in bytes 0, //Actual length of the payload, in bytes 0, //Time-to-live value + NULL, //Underlying network interface {0}, //Source IP address 0, //Source port {0}, //Destination IP address @@ -1603,14 +1604,14 @@ error_t getHostByName(NetInterface *interface, protocol = HOST_NAME_RESOLVER_MDNS; #endif } - else if(n <= 15 && !strchr(name, '.') && type == HOST_TYPE_IPV4) + else if(n <= 15 && !osStrchr(name, '.') && type == HOST_TYPE_IPV4) { #if (NBNS_CLIENT_SUPPORT == ENABLED) //Use NetBIOS Name Service to resolve the specified host name protocol = HOST_NAME_RESOLVER_NBNS; #endif } - else if(!strchr(name, '.')) + else if(!osStrchr(name, '.')) { #if (LLMNR_CLIENT_SUPPORT == ENABLED) //Use LLMNR to resolve the specified host name diff --git a/core/socket.h b/core/socket.h index 4a3fae56..d496399a 100644 --- a/core/socket.h +++ b/core/socket.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SOCKET_H @@ -198,24 +198,25 @@ typedef enum typedef struct { - void *data; ///flags & TCP_FLAG_SYN) + { ackNum++; + } + if(segment->flags & TCP_FLAG_FIN) + { ackNum++; + } } //Allocate a memory buffer to hold the reset segment @@ -426,6 +431,7 @@ error_t tcpSendResetSegment(NetInterface *interface, //Debug message TRACE_DEBUG("%s: Sending TCP reset segment...\r\n", formatSystemTime(osGetSystemTime(), NULL)); + //Dump TCP header contents for debugging purpose tcpDumpHeader(segment2, length, 0, 0); @@ -456,40 +462,55 @@ error_t tcpSendResetSegment(NetInterface *interface, error_t tcpAddOption(TcpHeader *segment, uint8_t kind, const void *value, uint8_t length) { - uint_t i; + error_t error; + size_t i; size_t paddingSize; TcpOption *option; - //Length of the complete option field + //The option-length counts the two octets of option-kind and option-length + //as well as the option-data octets (refer to RFC 793, section 3.1) length += sizeof(TcpOption); - //Make sure there is enough space to add the specified option - if((segment->dataOffset * 4 + length) > TCP_MAX_HEADER_LENGTH) - return ERROR_FAILURE; + //Make sure there is enough room to add the option + if((segment->dataOffset * 4 + length) <= TCP_MAX_HEADER_LENGTH) + { + //Index of the first available byte + i = (segment->dataOffset * 4) - sizeof(TcpHeader); - //Index of the first available byte - i = segment->dataOffset * 4 - sizeof(TcpHeader); + //Calculate the number of padding bytes + paddingSize = (length % 4) ? 4 - (length % 4) : 0; - //Calculate the number of padding bytes - paddingSize = (length % 4) ? 4 - (length % 4) : 0; - //Write padding bytes - while(paddingSize--) - segment->options[i++] = TCP_OPTION_NOP; + //Write padding bytes + while(paddingSize--) + { + segment->options[i++] = TCP_OPTION_NOP; + } - //Point to the current location - option = (TcpOption *) (segment->options + i); - //Write specified option - option->kind = kind; - option->length = length; - osMemcpy(option->value, value, length - sizeof(TcpOption)); - //Adjust index value - i += length; + //Point to the current location + option = (TcpOption *) (segment->options + i); - //Update TCP header length - segment->dataOffset = (sizeof(TcpHeader) + i) / 4; + //Format option + option->kind = kind; + option->length = length; + osMemcpy(option->value, value, length - sizeof(TcpOption)); - //Option successfully added - return NO_ERROR; + //Adjust index value + i += length; + + //Update the length of the TCP header + segment->dataOffset = (sizeof(TcpHeader) + i) / 4; + + //Successful processing + error = NO_ERROR; + } + else + { + //Report an error + error = ERROR_FAILURE; + } + + //Return status code + return error; } @@ -503,48 +524,57 @@ error_t tcpAddOption(TcpHeader *segment, uint8_t kind, const void *value, TcpOption *tcpGetOption(TcpHeader *segment, uint8_t kind) { + size_t i; size_t length; - uint_t i; TcpOption *option; //Make sure the TCP header is valid - if(segment->dataOffset < 5) - return NULL; + if(segment->dataOffset >= (sizeof(TcpHeader) / 4)) + { + //Compute the length of the options field + length = (segment->dataOffset * 4) - sizeof(TcpHeader); - //Compute the length of the options field - length = segment->dataOffset * 4 - sizeof(TcpHeader); + //Point to the very first option + i = 0; - //Point to the very first option - i = 0; + //Loop through the list of options + while(i < length) + { + //Point to the current option + option = (TcpOption *) (segment->options + i); - //Parse TCP options - while(i < length) - { - //Point to the current option - option = (TcpOption *) (segment->options + i); + //Check option code + if(option->kind == TCP_OPTION_END) + { + //This option code indicates the end of the option list + break; + } + else if(option->kind == TCP_OPTION_NOP) + { + //This option consists of a single octet + i++; + } + else + { + //The option code is followed by a one-byte length field + if((i + 1) >= length) + break; - //NOP option detected? - if(option->kind == TCP_OPTION_NOP) - { - i++; - continue; - } - //END option detected? - if(option->kind == TCP_OPTION_END) - break; - //Check option length - if((i + 1) >= length || (i + option->length) > length) - break; + //Check the length of the option + if(option->length < sizeof(TcpOption) || (i + option->length) > length) + break; - //Current option kind match the specified one? - if(option->kind == kind) - return option; + //Matching option code? + if(option->kind == kind) + return option; - //Jump to next the next option - i += option->length; + //Jump to the next option + i += option->length; + } + } } - //Specified option code not found + //The specified option code does not exist return NULL; } @@ -641,10 +671,13 @@ error_t tcpCheckSeqNum(Socket *socket, TcpHeader *segment, size_t length) //Debug message TRACE_WARNING("Sequence number is not acceptable!\r\n"); - //If an incoming segment is not acceptable, an acknowledgment - //should be sent in reply (unless the RST bit is set) + //If an incoming segment is not acceptable, an acknowledgment should + //be sent in reply (unless the RST bit is set) if(!(segment->flags & TCP_FLAG_RST)) - tcpSendSegment(socket, TCP_FLAG_ACK, socket->sndNxt, socket->rcvNxt, 0, FALSE); + { + tcpSendSegment(socket, TCP_FLAG_ACK, socket->sndNxt, socket->rcvNxt, + 0, FALSE); + } //Return status code return ERROR_FAILURE; @@ -1239,11 +1272,17 @@ void tcpUpdateRetransmitQueue(Socket *socket) //Calculate the length of the TCP segment if(header->flags & TCP_FLAG_SYN) + { length = 1; + } else if(header->flags & TCP_FLAG_FIN) + { length = queueItem->length + 1; + } else + { length = queueItem->length; + } //If an acknowledgment is received for a segment before its timer //expires, the segment is removed from the retransmission queue diff --git a/core/tcp_misc.h b/core/tcp_misc.h index 42b901a2..e0cb8fe0 100644 --- a/core/tcp_misc.h +++ b/core/tcp_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TCP_MISC_H diff --git a/core/tcp_timer.c b/core/tcp_timer.c index f29a8fa2..cbba9ae0 100644 --- a/core/tcp_timer.c +++ b/core/tcp_timer.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/core/tcp_timer.h b/core/tcp_timer.h index 2e018da9..71a40b35 100644 --- a/core/tcp_timer.h +++ b/core/tcp_timer.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TCP_TIMER_H diff --git a/core/udp.c b/core/udp.c index a1fd73a7..d89b067c 100644 --- a/core/udp.c +++ b/core/udp.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -363,6 +363,8 @@ error_t udpProcessDatagram(NetInterface *interface, IpPseudoHeader *pseudoHeader //Initialize next field queueItem->next = NULL; + //Network interface where the packet was received + queueItem->interface = interface; //Record the source port number queueItem->srcPort = ntohs(header->srcPort); @@ -427,8 +429,19 @@ error_t udpSendDatagram(Socket *socket, const SocketMsg *message, uint_t flags) error_t error; size_t offset; NetBuffer *buffer; + NetInterface *interface; NetTxAncillary ancillary; + //Select the relevant network interface + if(message->interface != NULL) + { + interface = message->interface; + } + else + { + interface = socket->interface; + } + //Allocate a memory buffer to hold the UDP datagram buffer = udpAllocBuffer(0, &offset); //Failed to allocate buffer? @@ -499,9 +512,8 @@ error_t udpSendDatagram(Socket *socket, const SocketMsg *message, uint_t flags) #endif //Send UDP datagram - error = udpSendBuffer(socket->interface, &message->srcIpAddr, - socket->localPort, &message->destIpAddr, message->destPort, buffer, - offset, &ancillary); + error = udpSendBuffer(interface, &message->srcIpAddr, socket->localPort, + &message->destIpAddr, message->destPort, buffer, offset, &ancillary); } //Free previously allocated memory @@ -678,12 +690,7 @@ error_t udpSendBuffer(NetInterface *interface, const IpAddr *srcIpAddr, /** * @brief Receive data from a UDP socket * @param[in] socket Handle referencing the socket - * @param[out] srcIpAddr Source IP address (optional) - * @param[out] srcPort Source port number (optional) - * @param[out] destIpAddr Destination IP address (optional) - * @param[out] data Buffer where to store the incoming data - * @param[in] size Maximum number of bytes that can be received - * @param[out] received Number of bytes that have been received + * @param[out] message Received UDP datagram and ancillary data * @param[in] flags Set of flags that influences the behavior of this function * @return Error code **/ @@ -724,6 +731,8 @@ error_t udpReceiveDatagram(Socket *socket, SocketMsg *message, uint_t flags) message->length = netBufferRead(message->data, queueItem->buffer, queueItem->offset, message->size); + //Network interface where the packet was received + message->interface = queueItem->interface; //Save the source IP address message->srcIpAddr = queueItem->srcIpAddr; //Save the source port number diff --git a/core/udp.h b/core/udp.h index ab41f29d..319df9cc 100644 --- a/core/udp.h +++ b/core/udp.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _UDP_H diff --git a/dhcp/dhcp_client.c b/dhcp/dhcp_client.c index 8e58dc33..fb5045db 100644 --- a/dhcp/dhcp_client.c +++ b/dhcp/dhcp_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 4039: Rapid Commit Option for the DHCP version 4 * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -1378,9 +1378,7 @@ void dhcpClientProcessMessage(NetInterface *interface, length = netBufferGetLength(buffer) - offset; //Make sure the DHCP message is valid - if(length < sizeof(DhcpMessage)) - return; - if(length > DHCP_MAX_MSG_SIZE) + if(length < sizeof(DhcpMessage) || length > DHCP_MAX_MSG_SIZE) return; //Point to the beginning of the DHCP message @@ -1399,12 +1397,15 @@ void dhcpClientProcessMessage(NetInterface *interface, //The DHCP server shall respond with a BOOTREPLY opcode if(message->op != DHCP_OPCODE_BOOTREPLY) return; + //Enforce hardware type if(message->htype != DHCP_HARDWARE_TYPE_ETH) return; + //Check the length of the hardware address if(message->hlen != sizeof(MacAddr)) return; + //Check magic cookie if(message->magicCookie != HTONL(DHCP_MAGIC_COOKIE)) return; @@ -1460,9 +1461,11 @@ void dhcpClientParseOffer(DhcpClientContext *context, //Discard any received packet that does not match the transaction ID if(ntohl(message->xid) != context->transactionId) return; + //Make sure the IP address offered to the client is valid if(message->yiaddr == IPV4_UNSPECIFIED_ADDR) return; + //Check MAC address if(!macCompAddr(&message->chaddr, &logicalInterface->macAddr)) return; @@ -1494,7 +1497,6 @@ void dhcpClientParseOffer(DhcpClientContext *context, * @param[in] context Pointer to the DHCP client context * @param[in] message Pointer to the incoming DHCP message * @param[in] length Length of the incoming message to parse - * @return Error code **/ void dhcpClientParseAck(DhcpClientContext *context, @@ -1522,9 +1524,11 @@ void dhcpClientParseAck(DhcpClientContext *context, //Discard any received packet that does not match the transaction ID if(ntohl(message->xid) != context->transactionId) return; + //Make sure the IP address assigned to the client is valid if(message->yiaddr == IPV4_UNSPECIFIED_ADDR) return; + //Check MAC address if(!macCompAddr(&message->chaddr, &logicalInterface->macAddr)) return; @@ -1729,7 +1733,6 @@ void dhcpClientParseAck(DhcpClientContext *context, * @param[in] context Pointer to the DHCP client context * @param[in] message Pointer to the incoming DHCP message * @param[in] length Length of the incoming message to parse - * @return Error code **/ void dhcpClientParseNak(DhcpClientContext *context, @@ -1751,6 +1754,7 @@ void dhcpClientParseNak(DhcpClientContext *context, //Discard any received packet that does not match the transaction ID if(ntohl(message->xid) != context->transactionId) return; + //Check MAC address if(!macCompAddr(&message->chaddr, &logicalInterface->macAddr)) return; diff --git a/dhcp/dhcp_client.h b/dhcp/dhcp_client.h index 0b106420..868fb3b5 100644 --- a/dhcp/dhcp_client.h +++ b/dhcp/dhcp_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DHCP_CLIENT_H diff --git a/dhcp/dhcp_common.c b/dhcp/dhcp_common.c index 3a30b64f..fa7b29e0 100644 --- a/dhcp/dhcp_common.c +++ b/dhcp/dhcp_common.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -67,7 +67,7 @@ void dhcpAddOption(DhcpMessage *message, uint8_t optionCode, if(option->code == DHCP_OPT_END) break; - //Jump to next the next option + //Jump to the next option n += sizeof(DhcpOption) + option->length; } @@ -84,7 +84,7 @@ void dhcpAddOption(DhcpMessage *message, uint8_t optionCode, //Option value osMemcpy(option->value, optionValue, optionLen); - //Jump to next the next option + //Jump to the next option n += sizeof(DhcpOption) + option->length; //Point to the buffer where the option is to be written @@ -108,40 +108,54 @@ void dhcpAddOption(DhcpMessage *message, uint8_t optionCode, DhcpOption *dhcpGetOption(const DhcpMessage *message, size_t length, uint8_t optionCode) { - uint_t i; + size_t i; DhcpOption *option; //Make sure the DHCP header is valid - if(length < sizeof(DhcpMessage)) - return NULL; - //Get the length of the options field - length -= sizeof(DhcpMessage); - - //Parse DHCP options - for(i = 0; i < length; i++) + if(length >= sizeof(DhcpMessage)) { - //Point to the current option - option = (DhcpOption *) (message->options + i); - - //Pad option detected? - if(option->code == DHCP_OPT_PAD) - continue; - //End option detected? - if(option->code == DHCP_OPT_END) - break; - //Check option length - if((i + 1) >= length || (i + 1 + option->length) >= length) - break; - - //Current option code matches the specified one? - if(option->code == optionCode) - return option; - - //Jump to the next option - i += option->length + 1; + //Get the length of the options field + length -= sizeof(DhcpMessage); + + //Loop through the list of options + for(i = 0; i < length; i++) + { + //Point to the current option + option = (DhcpOption *) (message->options + i); + + //Check option code + if(option->code == DHCP_OPT_PAD) + { + //The pad option can be used to cause subsequent fields to align + //on word boundaries + } + else if(option->code == DHCP_OPT_END) + { + //The end option marks the end of valid information in the vendor + //field + break; + } + else + { + //The option code is followed by a one-byte length field + if((i + 1) >= length) + break; + + //Check the length of the option + if((i + sizeof(DhcpOption) + option->length) > length) + break; + + //Matching option code? + if(option->code == optionCode) + return option; + + //Jump to the next option + i += option->length + 1; + } + } } - //Specified option code not found + //The specified option code does not exist return NULL; } diff --git a/dhcp/dhcp_common.h b/dhcp/dhcp_common.h index 8aba2b80..80a9e134 100644 --- a/dhcp/dhcp_common.h +++ b/dhcp/dhcp_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DHCP_COMMON_H diff --git a/dhcp/dhcp_debug.c b/dhcp/dhcp_debug.c index fed461b5..f81f6010 100644 --- a/dhcp/dhcp_debug.c +++ b/dhcp/dhcp_debug.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/dhcp/dhcp_debug.h b/dhcp/dhcp_debug.h index 76db2976..32237043 100644 --- a/dhcp/dhcp_debug.h +++ b/dhcp/dhcp_debug.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DHCP_DEBUG_H diff --git a/dhcp/dhcp_server.c b/dhcp/dhcp_server.c index ecb80cd4..1523d5ca 100644 --- a/dhcp/dhcp_server.c +++ b/dhcp/dhcp_server.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 4039: Rapid Commit Option for the DHCP version 4 * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -456,7 +456,7 @@ void dhcpServerParseDiscover(DhcpServerContext *context, } } - //Sucessful processing + //Successful processing error = NO_ERROR; } else @@ -476,7 +476,7 @@ void dhcpServerParseDiscover(DhcpServerContext *context, { //Record IP address binding->ipAddr = requestedIpAddr; - //Sucessful processing + //Successful processing error = NO_ERROR; } else diff --git a/dhcp/dhcp_server.h b/dhcp/dhcp_server.h index 0e3f910f..f4a09f89 100644 --- a/dhcp/dhcp_server.h +++ b/dhcp/dhcp_server.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DHCP_SERVER_H diff --git a/dhcpv6/dhcpv6_client.c b/dhcpv6/dhcpv6_client.c index 25622100..804fb4ae 100644 --- a/dhcpv6/dhcpv6_client.c +++ b/dhcpv6/dhcpv6_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * with the latter to obtain configuration parameters. Refer to RFC 3315 * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/dhcpv6/dhcpv6_client.h b/dhcpv6/dhcpv6_client.h index 6dee00ba..e2f682fb 100644 --- a/dhcpv6/dhcpv6_client.h +++ b/dhcpv6/dhcpv6_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DHCPV6_CLIENT_H diff --git a/dhcpv6/dhcpv6_common.c b/dhcpv6/dhcpv6_common.c index 1292f36c..dfc3bd86 100644 --- a/dhcpv6/dhcpv6_common.c +++ b/dhcpv6/dhcpv6_common.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * with the latter to obtain configuration parameters. Refer to RFC 3315 * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/dhcpv6/dhcpv6_common.h b/dhcpv6/dhcpv6_common.h index f513df4b..14de78e2 100644 --- a/dhcpv6/dhcpv6_common.h +++ b/dhcpv6/dhcpv6_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DHCPV6_COMMON_H diff --git a/dhcpv6/dhcpv6_debug.c b/dhcpv6/dhcpv6_debug.c index 58981baa..9eac4bbf 100644 --- a/dhcpv6/dhcpv6_debug.c +++ b/dhcpv6/dhcpv6_debug.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/dhcpv6/dhcpv6_debug.h b/dhcpv6/dhcpv6_debug.h index ea1e9f44..4f6f8404 100644 --- a/dhcpv6/dhcpv6_debug.h +++ b/dhcpv6/dhcpv6_debug.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DHCPV6_DEBUG_H diff --git a/dhcpv6/dhcpv6_relay.c b/dhcpv6/dhcpv6_relay.c index 4d751551..124be26c 100644 --- a/dhcpv6/dhcpv6_relay.c +++ b/dhcpv6/dhcpv6_relay.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -31,7 +31,7 @@ * alongside a routing function in a common node. Refer to RFC 3315 * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/dhcpv6/dhcpv6_relay.h b/dhcpv6/dhcpv6_relay.h index fefdcfdc..a91d7857 100644 --- a/dhcpv6/dhcpv6_relay.h +++ b/dhcpv6/dhcpv6_relay.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DHCPV6_RELAY_H diff --git a/dns/dns_cache.c b/dns/dns_cache.c index 2728675f..07f2e95d 100644 --- a/dns/dns_cache.c +++ b/dns/dns_cache.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/dns/dns_cache.h b/dns/dns_cache.h index ca467801..9013fb19 100644 --- a/dns/dns_cache.h +++ b/dns/dns_cache.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DNS_CACHE_H diff --git a/dns/dns_client.c b/dns/dns_client.c index c0ade0fb..5fac519b 100644 --- a/dns/dns_client.c +++ b/dns/dns_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/dns/dns_client.h b/dns/dns_client.h index 04291e9c..6baa88d1 100644 --- a/dns/dns_client.h +++ b/dns/dns_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DNS_CLIENT_H diff --git a/dns/dns_common.c b/dns/dns_common.c index 82407a38..4f9f1446 100644 --- a/dns/dns_common.c +++ b/dns/dns_common.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/dns/dns_common.h b/dns/dns_common.h index 3b5438a0..8130b21d 100644 --- a/dns/dns_common.h +++ b/dns/dns_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DNS_COMMON_H diff --git a/dns/dns_debug.c b/dns/dns_debug.c index d82a92f6..3355eedb 100644 --- a/dns/dns_debug.c +++ b/dns/dns_debug.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/dns/dns_debug.h b/dns/dns_debug.h index 30102b69..d494971b 100644 --- a/dns/dns_debug.h +++ b/dns/dns_debug.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DNS_DEBUG_H diff --git a/dns_sd/dns_sd.c b/dns_sd/dns_sd.c index 3dc3b595..b61eebce 100644 --- a/dns_sd/dns_sd.c +++ b/dns_sd/dns_sd.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 2782: A DNS RR for specifying the location of services (DNS SRV) * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/dns_sd/dns_sd.h b/dns_sd/dns_sd.h index 14bc153c..153d30ab 100644 --- a/dns_sd/dns_sd.h +++ b/dns_sd/dns_sd.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DNS_SD_H diff --git a/drivers/eth/dm9000_driver.c b/drivers/eth/dm9000_driver.c index 851a4260..4cf690f3 100644 --- a/drivers/eth/dm9000_driver.c +++ b/drivers/eth/dm9000_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -74,7 +74,7 @@ error_t dm9000Init(NetInterface *interface) uint_t i; uint16_t vendorId; uint16_t productId; - uint8_t chipRevision; + uint8_t chipRev; Dm9000Context *context; //Debug message @@ -105,9 +105,9 @@ error_t dm9000Init(NetInterface *interface) } //Retrieve vendorID, product ID and chip revision - vendorId = (dm9000ReadReg(DM9000_REG_VIDH) << 8) | dm9000ReadReg(DM9000_REG_VIDL); - productId = (dm9000ReadReg(DM9000_REG_PIDH) << 8) | dm9000ReadReg(DM9000_REG_PIDL); - chipRevision = dm9000ReadReg(DM9000_REG_CHIPR); + vendorId = (dm9000ReadReg(DM9000_VIDH) << 8) | dm9000ReadReg(DM9000_VIDL); + productId = (dm9000ReadReg(DM9000_PIDH) << 8) | dm9000ReadReg(DM9000_PIDL); + chipRev = dm9000ReadReg(DM9000_CHIPR); //Check vendor ID and product ID if(vendorId != DM9000_VID || productId != DM9000_PID) @@ -116,68 +116,80 @@ error_t dm9000Init(NetInterface *interface) } //Check chip revision - if(chipRevision != DM9000A_CHIP_REV && chipRevision != DM9000B_CHIP_REV) + if(chipRev != DM9000_CHIPR_REV_A && chipRev != DM9000_CHIPR_REV_B) { return ERROR_WRONG_IDENTIFIER; } //Power up the internal PHY by clearing PHYPD - dm9000WriteReg(DM9000_REG_GPR, 0x00); + dm9000WriteReg(DM9000_GPR, 0x00); //Wait for the PHY to be ready sleep(10); //Software reset - dm9000WriteReg(DM9000_REG_NCR, NCR_RST); + dm9000WriteReg(DM9000_NCR, DM9000_NCR_RST); //Wait for the reset to complete - while((dm9000ReadReg(DM9000_REG_NCR) & NCR_RST) != 0) + while((dm9000ReadReg(DM9000_NCR) & DM9000_NCR_RST) != 0) { } //PHY software reset - dm9000WritePhyReg(DM9000_PHY_REG_BMCR, BMCR_RST); + dm9000WritePhyReg(DM9000_BMCR, DM9000_BMCR_RST); //Wait for the PHY reset to complete - while((dm9000ReadPhyReg(DM9000_PHY_REG_BMCR) & BMCR_RST) != 0) + while((dm9000ReadPhyReg(DM9000_BMCR) & DM9000_BMCR_RST) != 0) { } //Debug message TRACE_INFO(" VID = 0x%04" PRIX16 "\r\n", vendorId); TRACE_INFO(" PID = 0x%04" PRIX16 "\r\n", productId); - TRACE_INFO(" CHIPR = 0x%02" PRIX8 "\r\n", chipRevision); - TRACE_INFO(" PHYIDR1 = 0x%04" PRIX16 "\r\n", dm9000ReadPhyReg(DM9000_PHY_REG_PHYIDR1)); - TRACE_INFO(" PHYIDR2 = 0x%04" PRIX16 "\r\n", dm9000ReadPhyReg(DM9000_PHY_REG_PHYIDR2)); + TRACE_INFO(" CHIPR = 0x%02" PRIX8 "\r\n", chipRev); + TRACE_INFO(" PHYIDR1 = 0x%04" PRIX16 "\r\n", dm9000ReadPhyReg(DM9000_PHYIDR1)); + TRACE_INFO(" PHYIDR2 = 0x%04" PRIX16 "\r\n", dm9000ReadPhyReg(DM9000_PHYIDR2)); //Enable loopback mode? #if (DM9000_LOOPBACK_MODE == ENABLED) - dm9000WriteReg(DM9000_REG_NCR, DM9000_LBK_PHY); - dm9000WritePhyReg(DM9000_PHY_REG_BMCR, BMCR_LOOPBACK | BMCR_SPEED_SEL | BMCR_AN_EN | BMCR_DUPLEX_MODE); + //Enable loopback mode + dm9000WriteReg(DM9000_NCR, DM9000_NCR_LBK_PHY); + + //Set operation mode + dm9000WritePhyReg(DM9000_BMCR, DM9000_BMCR_LOOPBACK | DM9000_BMCR_SPEED_SEL | + DM9000_BMCR_AN_EN | DM9000_BMCR_DUPLEX_MODE); #endif //Set host MAC address for(i = 0; i < 6; i++) { - dm9000WriteReg(DM9000_REG_PAR0 + i, interface->macAddr.b[i]); + dm9000WriteReg(DM9000_PAR0 + i, interface->macAddr.b[i]); } //Initialize hash table for(i = 0; i < 8; i++) { - dm9000WriteReg(DM9000_REG_MAR0 + i, 0x00); + dm9000WriteReg(DM9000_MAR0 + i, 0x00); } //Always accept broadcast packets - dm9000WriteReg(DM9000_REG_MAR7, 0x80); + dm9000WriteReg(DM9000_MAR7, 0x80); //Enable the Pointer Auto Return function - dm9000WriteReg(DM9000_REG_IMR, IMR_PAR); + dm9000WriteReg(DM9000_IMR, DM9000_IMR_PAR); + //Clear NSR status bits - dm9000WriteReg(DM9000_REG_NSR, NSR_WAKEST | NSR_TX2END | NSR_TX1END); + dm9000WriteReg(DM9000_NSR, DM9000_NSR_WAKEST | DM9000_NSR_TX2END | + DM9000_NSR_TX1END); + //Clear interrupt flags - dm9000WriteReg(DM9000_REG_ISR, ISR_LNKCHG | ISR_UDRUN | ISR_ROO | ISR_ROS | ISR_PT | ISR_PR); + dm9000WriteReg(DM9000_ISR, DM9000_ISR_LNKCHG | DM9000_ISR_UDRUN | + DM9000_ISR_ROO | DM9000_ISR_ROS | DM9000_ISR_PT | DM9000_ISR_PR); + //Enable interrupts - dm9000WriteReg(DM9000_REG_IMR, IMR_PAR | IMR_LNKCHGI | IMR_PTI | IMR_PRI); + dm9000WriteReg(DM9000_IMR, DM9000_IMR_PAR | DM9000_IMR_LNKCHGI | + DM9000_IMR_PTI | DM9000_IMR_PRI); + //Enable the receiver by setting RXEN - dm9000WriteReg(DM9000_REG_RCR, RCR_DIS_LONG | RCR_DIS_CRC | RCR_RXEN); + dm9000WriteReg(DM9000_RCR, DM9000_RCR_DIS_LONG | DM9000_RCR_DIS_CRC | + DM9000_RCR_RXEN); //Accept any packets from the upper layer osSetEvent(&interface->nicTxEvent); @@ -246,15 +258,15 @@ bool_t dm9000IrqHandler(NetInterface *interface) context = (Dm9000Context *) interface->nicContext; //Read interrupt status register - status = dm9000ReadReg(DM9000_REG_ISR); + status = dm9000ReadReg(DM9000_ISR); //Link status change? - if((status & ISR_LNKCHG) != 0) + if((status & DM9000_ISR_LNKCHG) != 0) { //Read interrupt mask register - mask = dm9000ReadReg(DM9000_REG_IMR); + mask = dm9000ReadReg(DM9000_IMR); //Disable LNKCHGI interrupt - dm9000WriteReg(DM9000_REG_IMR, mask & ~IMR_LNKCHGI); + dm9000WriteReg(DM9000_IMR, mask & ~DM9000_IMR_LNKCHGI); //Set event flag interface->nicEvent = TRUE; @@ -263,10 +275,10 @@ bool_t dm9000IrqHandler(NetInterface *interface) } //Packet transmission complete? - if((status & ISR_PT) != 0) + if((status & DM9000_ISR_PT) != 0) { //Check TX complete status bits - if(dm9000ReadReg(DM9000_REG_NSR) & (NSR_TX2END | NSR_TX1END)) + if((dm9000ReadReg(DM9000_NSR) & (DM9000_NSR_TX2END | DM9000_NSR_TX1END)) != 0) { //The transmission of the current packet is complete if(context->queuedPackets > 0) @@ -279,16 +291,16 @@ bool_t dm9000IrqHandler(NetInterface *interface) } //Clear interrupt flag - dm9000WriteReg(DM9000_REG_ISR, ISR_PT); + dm9000WriteReg(DM9000_ISR, DM9000_ISR_PT); } //Packet received? - if((status & ISR_PR) != 0) + if((status & DM9000_ISR_PR) != 0) { //Read interrupt mask register - mask = dm9000ReadReg(DM9000_REG_IMR); + mask = dm9000ReadReg(DM9000_IMR); //Disable PRI interrupt - dm9000WriteReg(DM9000_REG_IMR, mask & ~IMR_PRI); + dm9000WriteReg(DM9000_IMR, mask & ~DM9000_IMR_PRI); //Set event flag interface->nicEvent = TRUE; @@ -312,21 +324,21 @@ void dm9000EventHandler(NetInterface *interface) uint8_t status; //Read interrupt status register - status = dm9000ReadReg(DM9000_REG_ISR); + status = dm9000ReadReg(DM9000_ISR); //Check whether the link status has changed? - if((status & ISR_LNKCHG) != 0) + if((status & DM9000_ISR_LNKCHG) != 0) { //Clear interrupt flag - dm9000WriteReg(DM9000_REG_ISR, ISR_LNKCHG); + dm9000WriteReg(DM9000_ISR, DM9000_ISR_LNKCHG); //Read network status register - status = dm9000ReadReg(DM9000_REG_NSR); + status = dm9000ReadReg(DM9000_NSR); //Check link state - if((status & NSR_LINKST) != 0) + if((status & DM9000_NSR_LINKST) != 0) { //Get current speed - if((status & NSR_SPEED) != 0) + if((status & DM9000_NSR_SPEED) != 0) { interface->linkSpeed = NIC_LINK_SPEED_10MBPS; } @@ -336,10 +348,10 @@ void dm9000EventHandler(NetInterface *interface) } //Read network control register - status = dm9000ReadReg(DM9000_REG_NCR); + status = dm9000ReadReg(DM9000_NCR); //Determine the new duplex mode - if((status & NCR_FDX) != 0) + if((status & DM9000_NCR_FDX) != 0) { interface->duplexMode = NIC_FULL_DUPLEX_MODE; } @@ -362,10 +374,10 @@ void dm9000EventHandler(NetInterface *interface) } //Check whether a packet has been received? - if((status & ISR_PR) != 0) + if((status & DM9000_ISR_PR) != 0) { //Clear interrupt flag - dm9000WriteReg(DM9000_REG_ISR, ISR_PR); + dm9000WriteReg(DM9000_ISR, DM9000_ISR_PR); //Process all pending packets do @@ -378,7 +390,8 @@ void dm9000EventHandler(NetInterface *interface) } //Re-enable LNKCHGI and PRI interrupts - dm9000WriteReg(DM9000_REG_IMR, IMR_PAR | IMR_LNKCHGI | IMR_PTI | IMR_PRI); + dm9000WriteReg(DM9000_IMR, DM9000_IMR_PAR | DM9000_IMR_LNKCHGI | + DM9000_IMR_PTI | DM9000_IMR_PRI); } @@ -419,9 +432,9 @@ error_t dm9000SendPacket(NetInterface *interface, netBufferRead(context->txBuffer, buffer, offset, length); //A dummy write is required before accessing FIFO - dm9000WriteReg(DM9000_REG_MWCMDX, 0); + dm9000WriteReg(DM9000_MWCMDX, 0); //Select MWCMD register - DM9000_INDEX_REG = DM9000_REG_MWCMD; + DM9000_INDEX_REG = DM9000_MWCMD; //Point to the beginning of the buffer p = (uint16_t *) context->txBuffer; @@ -439,13 +452,13 @@ error_t dm9000SendPacket(NetInterface *interface, } //Write the number of bytes to send - dm9000WriteReg(DM9000_REG_TXPLL, LSB(length)); - dm9000WriteReg(DM9000_REG_TXPLH, MSB(length)); + dm9000WriteReg(DM9000_TXPLL, LSB(length)); + dm9000WriteReg(DM9000_TXPLH, MSB(length)); //Clear interrupt flag - dm9000WriteReg(DM9000_REG_ISR, ISR_PT); + dm9000WriteReg(DM9000_ISR, DM9000_ISR_PT); //Start data transfer - dm9000WriteReg(DM9000_REG_TCR, TCR_TXREQ); + dm9000WriteReg(DM9000_TCR, DM9000_TCR_TXREQ); //The packet was successfully written to FIFO context->queuedPackets++; @@ -475,10 +488,10 @@ error_t dm9000ReceivePacket(NetInterface *interface) context = (Dm9000Context *) interface->nicContext; //A dummy read is required before accessing the 4-byte header - data = dm9000ReadReg(DM9000_REG_MRCMDX); + data = dm9000ReadReg(DM9000_MRCMDX); //Select MRCMDX1 register - DM9000_INDEX_REG = DM9000_REG_MRCMDX1; + DM9000_INDEX_REG = DM9000_MRCMDX1; //Read the first byte of the header status = LSB(DM9000_DATA_REG); @@ -486,7 +499,7 @@ error_t dm9000ReceivePacket(NetInterface *interface) if(status == 0x01) { //Select MRCMD register - DM9000_INDEX_REG = DM9000_REG_MRCMD; + DM9000_INDEX_REG = DM9000_MRCMD; //The second byte is the RX status byte status = MSB(DM9000_DATA_REG); @@ -499,7 +512,8 @@ error_t dm9000ReceivePacket(NetInterface *interface) i = 0; //Make sure no error occurred - if((status & (RSR_LCS | RSR_RWTO | RSR_PLE | RSR_AE | RSR_CE | RSR_FOE)) == 0) + if((status & (DM9000_RSR_LCS | DM9000_RSR_RWTO | DM9000_RSR_PLE | + DM9000_RSR_AE | DM9000_RSR_CE | DM9000_RSR_FOE)) == 0) { //Read data from FIFO using 16-bit mode while((i + 1) < n) @@ -600,16 +614,16 @@ error_t dm9000UpdateMacAddrFilter(NetInterface *interface) //Write the hash table to the DM9000 controller for(i = 0; i < 8; i++) { - dm9000WriteReg(DM9000_REG_MAR0 + i, hashTable[i]); + dm9000WriteReg(DM9000_MAR0 + i, hashTable[i]); } //Debug message TRACE_DEBUG(" MAR = %02" PRIX8 " %02" PRIX8 " %02" PRIX8 " %02" PRIX8 " " "%02" PRIX8 " %02" PRIX8 " %02" PRIX8 " %02" PRIX8 "\r\n", - dm9000ReadReg(DM9000_REG_MAR0), dm9000ReadReg(DM9000_REG_MAR1), - dm9000ReadReg(DM9000_REG_MAR2), dm9000ReadReg(DM9000_REG_MAR3), - dm9000ReadReg(DM9000_REG_MAR4), dm9000ReadReg(DM9000_REG_MAR5), - dm9000ReadReg(DM9000_REG_MAR6), dm9000ReadReg(DM9000_REG_MAR7)); + dm9000ReadReg(DM9000_MAR0), dm9000ReadReg(DM9000_MAR1), + dm9000ReadReg(DM9000_MAR2), dm9000ReadReg(DM9000_MAR3), + dm9000ReadReg(DM9000_MAR4), dm9000ReadReg(DM9000_MAR5), + dm9000ReadReg(DM9000_MAR6), dm9000ReadReg(DM9000_MAR7)); //Successful processing return NO_ERROR; @@ -655,22 +669,23 @@ uint8_t dm9000ReadReg(uint8_t address) void dm9000WritePhyReg(uint8_t address, uint16_t data) { //Write PHY register address - dm9000WriteReg(DM9000_REG_EPAR, 0x40 | address); + dm9000WriteReg(DM9000_EPAR, 0x40 | address); //Write register value - dm9000WriteReg(DM9000_REG_EPDRL, LSB(data)); - dm9000WriteReg(DM9000_REG_EPDRH, MSB(data)); + dm9000WriteReg(DM9000_EPDRL, LSB(data)); + dm9000WriteReg(DM9000_EPDRH, MSB(data)); //Start the write operation - dm9000WriteReg(DM9000_REG_EPCR, EPCR_EPOS | EPCR_ERPRW); + dm9000WriteReg(DM9000_EPCR, DM9000_EPCR_EPOS | DM9000_EPCR_ERPRW); + //PHY access is still in progress? - while((dm9000ReadReg(DM9000_REG_EPCR) & EPCR_ERRE) != 0) + while((dm9000ReadReg(DM9000_EPCR) & DM9000_EPCR_ERRE) != 0) { } //Wait 5us minimum usleep(5); //Clear command register - dm9000WriteReg(DM9000_REG_EPCR, EPCR_EPOS); + dm9000WriteReg(DM9000_EPCR, DM9000_EPCR_EPOS); } @@ -683,22 +698,23 @@ void dm9000WritePhyReg(uint8_t address, uint16_t data) uint16_t dm9000ReadPhyReg(uint8_t address) { //Write PHY register address - dm9000WriteReg(DM9000_REG_EPAR, 0x40 | address); + dm9000WriteReg(DM9000_EPAR, 0x40 | address); //Start the read operation - dm9000WriteReg(DM9000_REG_EPCR, EPCR_EPOS | EPCR_ERPRR); + dm9000WriteReg(DM9000_EPCR, DM9000_EPCR_EPOS | DM9000_EPCR_ERPRR); + //PHY access is still in progress? - while((dm9000ReadReg(DM9000_REG_EPCR) & EPCR_ERRE) != 0) + while((dm9000ReadReg(DM9000_EPCR) & DM9000_EPCR_ERRE) != 0) { } //Clear command register - dm9000WriteReg(DM9000_REG_EPCR, EPCR_EPOS); + dm9000WriteReg(DM9000_EPCR, DM9000_EPCR_EPOS); //Wait 5us minimum usleep(5); //Return register value - return (dm9000ReadReg(DM9000_REG_EPDRH) << 8) | dm9000ReadReg(DM9000_REG_EPDRL); + return (dm9000ReadReg(DM9000_EPDRH) << 8) | dm9000ReadReg(DM9000_EPDRL); } diff --git a/drivers/eth/dm9000_driver.h b/drivers/eth/dm9000_driver.h index 441cc2da..fcfa290d 100644 --- a/drivers/eth/dm9000_driver.h +++ b/drivers/eth/dm9000_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DM9000_DRIVER_H @@ -51,308 +51,469 @@ #define DM9000_DATA_REG *((volatile uint16_t *) 0x30001000) #endif -//DM9000 bus timing -#define AT91C_SMC2_NWS_2 (2 << 0) -#define AT91C_SMC2_TDF_2 (2 << 8) -#define AT91C_SMC2_BAT_16 (1 << 12) -#define AT91C_SMC2_DRP_STANDARD (0 << 15) -#define AT91C_SMC2_RWSETUP_1 (1 << 24) -#define AT91C_SMC2_RWHOLD_1 (1 << 28) - //DM9000 identifiers -#define DM9000_VID 0x0A46 -#define DM9000_PID 0x9000 -#define DM9000A_CHIP_REV 0x19 -#define DM9000B_CHIP_REV 0x1A +#define DM9000_VID ((DM9000_VIDH_DEFAULT << 8) | DM9000_VIDL_DEFAULT) +#define DM9000_PID ((DM9000_PIDH_DEFAULT << 8) | DM9000_PIDL_DEFAULT) //DM9000 registers -#define DM9000_REG_NCR 0x00 -#define DM9000_REG_NSR 0x01 -#define DM9000_REG_TCR 0x02 -#define DM9000_REG_TSR1 0x03 -#define DM9000_REG_TSR2 0x04 -#define DM9000_REG_RCR 0x05 -#define DM9000_REG_RSR 0x06 -#define DM9000_REG_ROCR 0x07 -#define DM9000_REG_BPTR 0x08 -#define DM9000_REG_FCTR 0x09 -#define DM9000_REG_FCR 0x0A -#define DM9000_REG_EPCR 0x0B -#define DM9000_REG_EPAR 0x0C -#define DM9000_REG_EPDRL 0x0D -#define DM9000_REG_EPDRH 0x0E -#define DM9000_REG_WCR 0x0F -#define DM9000_REG_PAR0 0x10 -#define DM9000_REG_PAR1 0x11 -#define DM9000_REG_PAR2 0x12 -#define DM9000_REG_PAR3 0x13 -#define DM9000_REG_PAR4 0x14 -#define DM9000_REG_PAR5 0x15 -#define DM9000_REG_MAR0 0x16 -#define DM9000_REG_MAR1 0x17 -#define DM9000_REG_MAR2 0x18 -#define DM9000_REG_MAR3 0x19 -#define DM9000_REG_MAR4 0x1A -#define DM9000_REG_MAR5 0x1B -#define DM9000_REG_MAR6 0x1C -#define DM9000_REG_MAR7 0x1D -#define DM9000_REG_GPCR 0x1E -#define DM9000_REG_GPR 0x1F -#define DM9000_REG_TRPAL 0x22 -#define DM9000_REG_TRPAH 0x23 -#define DM9000_REG_RWPAL 0x24 -#define DM9000_REG_RWPAH 0x25 -#define DM9000_REG_VIDL 0x28 -#define DM9000_REG_VIDH 0x29 -#define DM9000_REG_PIDL 0x2A -#define DM9000_REG_PIDH 0x2B -#define DM9000_REG_CHIPR 0x2C -#define DM9000_REG_TCR2 0x2D -#define DM9000_REG_OCR 0x2E -#define DM9000_REG_SMCR 0x2F -#define DM9000_REG_ETXCSR 0x30 -#define DM9000_REG_TCSCR 0x31 -#define DM9000_REG_RCSCSR 0x32 -#define DM9000_REG_MPAR 0x33 -#define DM9000_REG_LEDCR 0x34 -#define DM9000_REG_BUSCR 0x38 -#define DM9000_REG_INTCR 0x39 -#define DM9000_REG_SCCR 0x50 -#define DM9000_REG_RSCCR 0x51 -#define DM9000_REG_MRCMDX 0xF0 -#define DM9000_REG_MRCMDX1 0xF1 -#define DM9000_REG_MRCMD 0xF2 -#define DM9000_REG_MRRL 0xF4 -#define DM9000_REG_MRRH 0xF5 -#define DM9000_REG_MWCMDX 0xF6 -#define DM9000_REG_MWCMD 0xF8 -#define DM9000_REG_MWRL 0xFA -#define DM9000_REG_MWRH 0xFB -#define DM9000_REG_TXPLL 0xFC -#define DM9000_REG_TXPLH 0xFD -#define DM9000_REG_ISR 0xFE -#define DM9000_REG_IMR 0xFF +#define DM9000_NCR 0x00 +#define DM9000_NSR 0x01 +#define DM9000_TCR 0x02 +#define DM9000_TSR1 0x03 +#define DM9000_TSR2 0x04 +#define DM9000_RCR 0x05 +#define DM9000_RSR 0x06 +#define DM9000_ROCR 0x07 +#define DM9000_BPTR 0x08 +#define DM9000_FCTR 0x09 +#define DM9000_FCR 0x0A +#define DM9000_EPCR 0x0B +#define DM9000_EPAR 0x0C +#define DM9000_EPDRL 0x0D +#define DM9000_EPDRH 0x0E +#define DM9000_WCR 0x0F +#define DM9000_PAR0 0x10 +#define DM9000_PAR1 0x11 +#define DM9000_PAR2 0x12 +#define DM9000_PAR3 0x13 +#define DM9000_PAR4 0x14 +#define DM9000_PAR5 0x15 +#define DM9000_MAR0 0x16 +#define DM9000_MAR1 0x17 +#define DM9000_MAR2 0x18 +#define DM9000_MAR3 0x19 +#define DM9000_MAR4 0x1A +#define DM9000_MAR5 0x1B +#define DM9000_MAR6 0x1C +#define DM9000_MAR7 0x1D +#define DM9000_GPCR 0x1E +#define DM9000_GPR 0x1F +#define DM9000_TRPAL 0x22 +#define DM9000_TRPAH 0x23 +#define DM9000_RWPAL 0x24 +#define DM9000_RWPAH 0x25 +#define DM9000_VIDL 0x28 +#define DM9000_VIDH 0x29 +#define DM9000_PIDL 0x2A +#define DM9000_PIDH 0x2B +#define DM9000_CHIPR 0x2C +#define DM9000_TCR2 0x2D +#define DM9000_OCR 0x2E +#define DM9000_SMCR 0x2F +#define DM9000_ETXCSR 0x30 +#define DM9000_TCSCR 0x31 +#define DM9000_RCSCSR 0x32 +#define DM9000_MPAR 0x33 +#define DM9000_LEDCR 0x34 +#define DM9000_BUSCR 0x38 +#define DM9000_INTCR 0x39 +#define DM9000_SCCR 0x50 +#define DM9000_RSCCR 0x51 +#define DM9000_MRCMDX 0xF0 +#define DM9000_MRCMDX1 0xF1 +#define DM9000_MRCMD 0xF2 +#define DM9000_MRRL 0xF4 +#define DM9000_MRRH 0xF5 +#define DM9000_MWCMDX 0xF6 +#define DM9000_MWCMD 0xF8 +#define DM9000_MWRL 0xFA +#define DM9000_MWRH 0xFB +#define DM9000_TXPLL 0xFC +#define DM9000_TXPLH 0xFD +#define DM9000_ISR 0xFE +#define DM9000_IMR 0xFF //DM9000 PHY registers -#define DM9000_PHY_REG_BMCR 0x00 -#define DM9000_PHY_REG_BMSR 0x01 -#define DM9000_PHY_REG_PHYIDR1 0x02 -#define DM9000_PHY_REG_PHYIDR2 0x03 -#define DM9000_PHY_REG_ANAR 0x04 -#define DM9000_PHY_REG_ANLPAR 0x05 -#define DM9000_PHY_REG_ANER 0x06 -#define DM9000_PHY_REG_DSCR 0x10 -#define DM9000_PHY_REG_DSCSR 0x11 -#define DM9000_PHY_REG_10BTCSR 0x12 -#define DM9000_PHY_REG_PWDOR 0x13 -#define DM9000_PHY_REG_SCR 0x14 -#define DM9000_PHY_REG_DSP 0x1B -#define DM9000_PHY_REG_PSCR 0x1D - -//NCR register -#define NCR_WAKEEN (1 << 6) -#define NCR_FCOL (1 << 4) -#define NCR_FDX (1 << 3) -#define NCR_LBK (3 << 1) -#define NCR_RST (1 << 0) - -//NSR register -#define NSR_SPEED (1 << 7) -#define NSR_LINKST (1 << 6) -#define NSR_WAKEST (1 << 5) -#define NSR_TX2END (1 << 3) -#define NSR_TX1END (1 << 2) -#define NSR_RXOV (1 << 1) - -//TCR register -#define TCR_TJDIS (1 << 6) -#define TCR_EXCECM (1 << 5) -#define TCR_PAD_DIS2 (1 << 4) -#define TCR_CRC_DIS2 (1 << 3) -#define TCR_PAD_DIS1 (1 << 2) -#define TCR_CRC_DIS1 (1 << 1) -#define TCR_TXREQ (1 << 0) - -//TSR1 and TSR2 registers -#define TSR_TJTO (1 << 7) -#define TSR_LC (1 << 6) -#define TSR_NC (1 << 5) -#define TSR_LCOL (1 << 4) -#define TSR_COL (1 << 3) -#define TSR_EC (1 << 2) - -//RCR register -#define RCR_WTDIS (1 << 6) -#define RCR_DIS_LONG (1 << 5) -#define RCR_DIS_CRC (1 << 4) -#define RCR_ALL (1 << 3) -#define RCR_RUNT (1 << 2) -#define RCR_PRMSC (1 << 1) -#define RCR_RXEN (1 << 0) - -//RSR register -#define RSR_RF (1 << 7) -#define RSR_MF (1 << 6) -#define RSR_LCS (1 << 5) -#define RSR_RWTO (1 << 4) -#define RSR_PLE (1 << 3) -#define RSR_AE (1 << 2) -#define RSR_CE (1 << 1) -#define RSR_FOE (1 << 0) - -//ROCR register -#define ROCR_ROC (127 << 0) -#define ROCR_RXFU (1 << 7) - -//BPTR register -#define BPTR_BPHW (15 << 4) -#define BPTR_JPT (15 << 0) - -//FCTR register -#define FCTR_HWOT (15 << 4) -#define FCTR_LWOT (15 << 0) - -//FCR register -#define FCR_TXP0 (1 << 7) -#define FCR_TXPF (1 << 6) -#define FCR_TXPEN (1 << 5) -#define FCR_BKPA (1 << 4) -#define FCR_BKPM (1 << 3) -#define FCR_RXPS (1 << 2) -#define FCR_RXPCS (1 << 1) -#define FCR_FLCE (1 << 0) - -//EPCR register -#define EPCR_REEP (1 << 5) -#define EPCR_WEP (1 << 4) -#define EPCR_EPOS (1 << 3) -#define EPCR_ERPRR (1 << 2) -#define EPCR_ERPRW (1 << 1) -#define EPCR_ERRE (1 << 0) - -//EPAR register -#define EPAR_PHY_ADR (3 << 6) -#define EPAR_EROA (31 << 0) - -//WCR register -#define WCR_LINKEN (1 << 5) -#define WCR_SAMPLEEN (1 << 4) -#define WCR_MAGICEN (1 << 3) -#define WCR_LINKST (1 << 2) -#define WCR_SAMPLEST (1 << 1) -#define WCR_MAGICST (1 << 0) - -//GPCR register -#define GPCR_GPC6 (1 << 6) -#define GPCR_GPC5 (1 << 5) -#define GPCR_GPC4 (1 << 4) -#define GPCR_GPC3 (1 << 3) -#define GPCR_GPC2 (1 << 2) -#define GPCR_GPC1 (1 << 1) - -//GPR register -#define GPR_GPO6 (1 << 6) -#define GPR_GPO5 (1 << 5) -#define GPR_GPO4 (1 << 4) -#define GPR_GPIO3 (1 << 3) -#define GPR_GPIO2 (1 << 2) -#define GPR_GPIO1 (1 << 1) -#define GPR_PHYPD (1 << 0) - -//TCR2 register -#define TCR2_LED (1 << 7) -#define TCR2_RLCP (1 << 6) -#define TCR2_DTU (1 << 5) -#define TCR2_ONEPM (1 << 4) -#define TCR2_IFGS (15 << 0) - -//OCR register -#define OCR_SCC (3 << 6) -#define OCR_SOE (1 << 4) -#define OCR_SCS (1 << 3) -#define OCR_PHYOP (7 << 0) - -//SMCR register -#define SMCR_SM_EN (1 << 7) -#define SMCR_FLC (1 << 2) -#define SMCR_FB1 (1 << 1) -#define SMCR_FB0 (1 << 0) - -//ETXCSR register -#define ETXCSR_ETE (1 << 7) -#define ETXCSR_ETS2 (1 << 6) -#define ETXCSR_ETS1 (1 << 5) -#define ETXCSR_ETT (3 << 0) - -//TCSCR register -#define TCSCR_UDPCSE (1 << 2) -#define TCSCR_TCPCSE (1 << 1) -#define TCSCR_IPCSE (1 << 0) - -//RCSCSR register -#define RCSCSR_UDPS (1 << 7) -#define RCSCSR_TCPS (1 << 6) -#define RCSCSR_IPS (1 << 5) -#define RCSCSR_UDPP (1 << 4) -#define RCSCSR_TCPP (1 << 3) -#define RCSCSR_IPP (1 << 2) -#define RCSCSR_RCSEN (1 << 1) -#define RCSCSR_DCSE (1 << 0) - -//MPAR register -#define MPAR_ADR_EN (1 << 7) -#define MPAR_EPHYADR (31 << 0) - -//LEDC register -#define LEDCR_GPIO (1 << 1) -#define LEDCR_MII (1 << 0) - -//BUSCR register -#define BUSCR_CURR (3 << 5) -#define BUSCR_EST (1 << 3) -#define BUSCR_IOW_SPIKE (1 << 1) -#define BUSCR_IOR_SPIKE (1 << 0) - -//INTCR register -#define INTCR_INT_TYPE (1 << 1) -#define INTCR_INT_POL (1 << 0) - -//SCCR register -#define SCCR_DIS_CLK (1 << 0) - -//ISR register -#define ISR_IOMODE (1 << 7) -#define ISR_LNKCHG (1 << 5) -#define ISR_UDRUN (1 << 4) -#define ISR_ROO (1 << 3) -#define ISR_ROS (1 << 2) -#define ISR_PT (1 << 1) -#define ISR_PR (1 << 0) - -//IMR register -#define IMR_PAR (1 << 7) -#define IMR_LNKCHGI (1 << 5) -#define IMR_UDRUNI (1 << 4) -#define IMR_ROOI (1 << 3) -#define IMR_ROI (1 << 2) -#define IMR_PTI (1 << 1) -#define IMR_PRI (1 << 0) - -//PHY BMCR register -#define BMCR_RST (1 << 15) -#define BMCR_LOOPBACK (1 << 14) -#define BMCR_SPEED_SEL (1 << 13) -#define BMCR_AN_EN (1 << 12) -#define BMCR_PD (1 << 11) -#define BMCR_ISOLATE (1 << 10) -#define BMCR_RESTART_AN (1 << 9) -#define BMCR_DUPLEX_MODE (1 << 8) -#define BMCR_COL_TEST (1 << 7) - -//Loopback mode -#define DM9000_LBK_NORMAL (0 << 1) -#define DM9000_LBK_MAC (1 << 1) -#define DM9000_LBK_PHY (2 << 1) +#define DM9000_BMCR 0x00 +#define DM9000_BMSR 0x01 +#define DM9000_PHYIDR1 0x02 +#define DM9000_PHYIDR2 0x03 +#define DM9000_ANAR 0x04 +#define DM9000_ANLPAR 0x05 +#define DM9000_ANER 0x06 +#define DM9000_DSCR 0x10 +#define DM9000_DSCSR 0x11 +#define DM9000_10BTCSR 0x12 +#define DM9000_PWDOR 0x13 +#define DM9000_SCR 0x14 +#define DM9000_DSPCR 0x1B +#define DM9000_PSCR 0x1D + +//Network Control register +#define DM9000_NCR_WAKEEN 0x40 +#define DM9000_NCR_FCOL 0x10 +#define DM9000_NCR_FDX 0x08 +#define DM9000_NCR_LBK 0x06 +#define DM9000_NCR_LBK_NORMAL 0x00 +#define DM9000_NCR_LBK_MAC 0x02 +#define DM9000_NCR_LBK_PHY 0x04 +#define DM9000_NCR_RST 0x01 + +//Network Status register +#define DM9000_NSR_SPEED 0x80 +#define DM9000_NSR_LINKST 0x40 +#define DM9000_NSR_WAKEST 0x20 +#define DM9000_NSR_TX2END 0x08 +#define DM9000_NSR_TX1END 0x04 +#define DM9000_NSR_RXOV 0x02 + +//TX Control register +#define DM9000_TCR_TJDIS 0x40 +#define DM9000_TCR_EXCECM 0x20 +#define DM9000_TCR_PAD_DIS2 0x10 +#define DM9000_TCR_CRC_DIS2 0x08 +#define DM9000_TCR_PAD_DIS1 0x04 +#define DM9000_TCR_CRC_DIS1 0x02 +#define DM9000_TCR_TXREQ 0x01 + +//TX Status 1 register +#define DM9000_TSR1_TJTO 0x80 +#define DM9000_TSR1_LC 0x40 +#define DM9000_TSR1_NC 0x20 +#define DM9000_TSR1_LCOL 0x10 +#define DM9000_TSR1_COL 0x08 +#define DM9000_TSR1_EC 0x04 + +//TX Status 2 register +#define DM9000_TSR2_TJTO 0x80 +#define DM9000_TSR2_LC 0x40 +#define DM9000_TSR2_NC 0x20 +#define DM9000_TSR2_LCOL 0x10 +#define DM9000_TSR2_COL 0x08 +#define DM9000_TSR2_EC 0x04 + +//RX Control register +#define DM9000_RCR_WTDIS 0x40 +#define DM9000_RCR_DIS_LONG 0x20 +#define DM9000_RCR_DIS_CRC 0x10 +#define DM9000_RCR_ALL 0x08 +#define DM9000_RCR_RUNT 0x04 +#define DM9000_RCR_PRMSC 0x02 +#define DM9000_RCR_RXEN 0x01 + +//RX Status register +#define DM9000_RSR_RF 0x80 +#define DM9000_RSR_MF 0x40 +#define DM9000_RSR_LCS 0x20 +#define DM9000_RSR_RWTO 0x10 +#define DM9000_RSR_PLE 0x08 +#define DM9000_RSR_AE 0x04 +#define DM9000_RSR_CE 0x02 +#define DM9000_RSR_FOE 0x01 + +//Receive Overflow Counter register +#define DM9000_ROCR_RXFU 0x80 +#define DM9000_ROCR_ROC 0x7F + +//Back Pressure Threshold register +#define DM9000_BPTR_BPHW 0xF0 +#define DM9000_BPTR_JPT 0x0F + +//Flow Control Threshold register +#define DM9000_FCTR_HWOT 0xF0 +#define DM9000_FCTR_LWOT 0x0F + +//RX Flow Control register +#define DM9000_FCR_TXP0 0x80 +#define DM9000_FCR_TXPF 0x40 +#define DM9000_FCR_TXPEN 0x20 +#define DM9000_FCR_BKPA 0x10 +#define DM9000_FCR_BKPM 0x08 +#define DM9000_FCR_RXPS 0x04 +#define DM9000_FCR_RXPCS 0x02 +#define DM9000_FCR_FLCE 0x01 + +//EEPROM & PHY Control register +#define DM9000_EPCR_REEP 0x20 +#define DM9000_EPCR_WEP 0x10 +#define DM9000_EPCR_EPOS 0x08 +#define DM9000_EPCR_ERPRR 0x04 +#define DM9000_EPCR_ERPRW 0x02 +#define DM9000_EPCR_ERRE 0x01 + +//EEPROM & PHY Address register +#define DM9000_EPAR_PHY_ADR 0xC0 +#define DM9000_EPAR_EROA 0x3F + +//Wake Up Control register +#define DM9000_WCR_LINKEN 0x20 +#define DM9000_WCR_SAMPLEEN 0x10 +#define DM9000_WCR_MAGICEN 0x08 +#define DM9000_WCR_LINKST 0x04 +#define DM9000_WCR_SAMPLEST 0x02 +#define DM9000_WCR_MAGICST 0x01 + +//General Purpose Control register +#define DM9000_GPCR_GPC6 0x40 +#define DM9000_GPCR_GPC5 0x20 +#define DM9000_GPCR_GPC4 0x10 +#define DM9000_GPCR_GPC3 0x08 +#define DM9000_GPCR_GPC2 0x04 +#define DM9000_GPCR_GPC1 0x02 + +//General Purpose register +#define DM9000_GPR_GPO6 0x40 +#define DM9000_GPR_GPO5 0x20 +#define DM9000_GPR_GPO4 0x10 +#define DM9000_GPR_GPIO3 0x08 +#define DM9000_GPR_GPIO2 0x04 +#define DM9000_GPR_GPIO1 0x02 +#define DM9000_GPR_PHYPD 0x01 + +//Vendor ID Low Byte register +#define DM9000_VIDL_DEFAULT 0x46 + +//Vendor ID High Byte register +#define DM9000_VIDH_DEFAULT 0x0A + +//Product ID Low Byte register +#define DM9000_PIDL_DEFAULT 0x00 + +//Product ID High Byte register +#define DM9000_PIDH_DEFAULT 0x90 + +//Chip Revision register +#define DM9000_CHIPR_REV_A 0x19 +#define DM9000_CHIPR_REV_B 0x1A + +//TX Control 2 register +#define DM9000_TCR2_LED 0x80 +#define DM9000_TCR2_RLCP 0x40 +#define DM9000_TCR2_DTU 0x20 +#define DM9000_TCR2_ONEPM 0x10 +#define DM9000_TCR2_IFGS 0x0F +#define DM9000_TCR2_IFGS_64_BIT 0x08 +#define DM9000_TCR2_IFGS_72_BIT 0x09 +#define DM9000_TCR2_IFGS_80_BIT 0x0A +#define DM9000_TCR2_IFGS_88_BIT 0x0B +#define DM9000_TCR2_IFGS_96_BIT 0x0C +#define DM9000_TCR2_IFGS_104_BIT 0x0D +#define DM9000_TCR2_IFGS_112_BIT 0x0E +#define DM9000_TCR2_IFGS_120_BIT 0x0F + +//Operation Control register +#define DM9000_OCR_SCC 0xC0 +#define DM9000_OCR_SCC_50MHZ 0x00 +#define DM9000_OCR_SCC_20MHZ 0x40 +#define DM9000_OCR_SCC_100MHZ 0x80 +#define DM9000_OCR_SOE 0x10 +#define DM9000_OCR_SCS 0x08 +#define DM9000_OCR_PHYOP 0x07 + +//Special Mode Control register +#define DM9000_SMCR_SM_EN 0x80 +#define DM9000_SMCR_FLC 0x04 +#define DM9000_SMCR_FB1 0x02 +#define DM9000_SMCR_FB0 0x01 + +//Early Transmit Control/Status register +#define DM9000_ETXCSR_ETE 0x80 +#define DM9000_ETXCSR_ETS2 0x40 +#define DM9000_ETXCSR_ETS1 0x20 +#define DM9000_ETXCSR_ETT 0x03 +#define DM9000_ETXCSR_ETT_12_5_PERCENT 0x00 +#define DM9000_ETXCSR_ETT_25_PERCENT 0x01 +#define DM9000_ETXCSR_ETT_50_PERCENT 0x02 +#define DM9000_ETXCSR_ETT_75_PERCENT 0x03 + +//Transmit Check Sum Control register +#define DM9000_TCSCR_UDPCSE 0x04 +#define DM9000_TCSCR_TCPCSE 0x02 +#define DM9000_TCSCR_IPCSE 0x01 + +//Receive Check Sum Control Status register +#define DM9000_RCSCSR_UDPS 0x80 +#define DM9000_RCSCSR_TCPS 0x40 +#define DM9000_RCSCSR_IPS 0x20 +#define DM9000_RCSCSR_UDPP 0x10 +#define DM9000_RCSCSR_TCPP 0x08 +#define DM9000_RCSCSR_IPP 0x04 +#define DM9000_RCSCSR_RCSEN 0x02 +#define DM9000_RCSCSR_DCSE 0x01 + +//MII PHY Address register +#define DM9000_MPAR_ADR_EN 0x80 +#define DM9000_MPAR_EPHYADR 0x1F + +//LED Pin Control register +#define DM9000_LEDCR_GPIO 0x02 +#define DM9000_LEDCR_MII 0x01 + +//Processor Bus Control register +#define DM9000_BUSCR_CURR 0x60 +#define DM9000_BUSCR_CURR_2MA 0x00 +#define DM9000_BUSCR_CURR_4MA 0x20 +#define DM9000_BUSCR_CURR_6MA 0x40 +#define DM9000_BUSCR_CURR_8MA 0x60 +#define DM9000_BUSCR_EST 0x08 +#define DM9000_BUSCR_IOW_SPIKE 0x02 +#define DM9000_BUSCR_IOR_SPIKE 0x01 + +//INT Pin Control register +#define DM9000_INTCR_INT_TYPE 0x02 +#define DM9000_INTCR_INT_TYPE_DIRECT 0x00 +#define DM9000_INTCR_INT_TYPE_OC 0x02 +#define DM9000_INTCR_INT_POL 0x01 +#define DM9000_INTCR_INT_POL_HIGH 0x00 +#define DM9000_INTCR_INT_POL_LOW 0x01 + +//System Clock Turn On Control register +#define DM9000_SCCR_DIS_CLK 0x01 + +//Interrupt Status register +#define DM9000_ISR_IOMODE 0x80 +#define DM9000_ISR_IOMODE_16_BIT 0x00 +#define DM9000_ISR_IOMODE_8_BIT 0x80 +#define DM9000_ISR_LNKCHG 0x20 +#define DM9000_ISR_UDRUN 0x10 +#define DM9000_ISR_ROO 0x08 +#define DM9000_ISR_ROS 0x04 +#define DM9000_ISR_PT 0x02 +#define DM9000_ISR_PR 0x01 + +//Interrupt Mask register +#define DM9000_IMR_PAR 0x80 +#define DM9000_IMR_LNKCHGI 0x20 +#define DM9000_IMR_UDRUNI 0x10 +#define DM9000_IMR_ROOI 0x08 +#define DM9000_IMR_ROI 0x04 +#define DM9000_IMR_PTI 0x02 +#define DM9000_IMR_PRI 0x01 + +//Basic Mode Control register +#define DM9000_BMCR_RST 0x8000 +#define DM9000_BMCR_LOOPBACK 0x4000 +#define DM9000_BMCR_SPEED_SEL 0x2000 +#define DM9000_BMCR_AN_EN 0x1000 +#define DM9000_BMCR_POWER_DOWN 0x0800 +#define DM9000_BMCR_ISOLATE 0x0400 +#define DM9000_BMCR_RESTART_AN 0x0200 +#define DM9000_BMCR_DUPLEX_MODE 0x0100 +#define DM9000_BMCR_COL_TEST 0x0080 + +//Basic Mode Status register +#define DM9000_BMSR_100BT4 0x8000 +#define DM9000_BMSR_100BTX_FD 0x4000 +#define DM9000_BMSR_100BTX_HD 0x2000 +#define DM9000_BMSR_10BT_FD 0x1000 +#define DM9000_BMSR_10BT_HD 0x0800 +#define DM9000_BMSR_MF_PREAMBLE_SUPPR 0x0040 +#define DM9000_BMSR_AN_COMPLETE 0x0020 +#define DM9000_BMSR_REMOTE_FAULT 0x0010 +#define DM9000_BMSR_AN_CAPABLE 0x0008 +#define DM9000_BMSR_LINK_STATUS 0x0004 +#define DM9000_BMSR_JABBER_DETECT 0x0002 +#define DM9000_BMSR_EXTENDED_CAPABLE 0x0001 + +//PHY ID Identifier 1 register +#define DM9000_PHYIDR1_OUI_MSB 0xFFFF +#define DM9000_PHYIDR1_OUI_MSB_DEFAULT 0x0181 + +//PHY ID Identifier 2 register +#define DM9000_PHYIDR2_OUI_LSB 0xFC00 +#define DM9000_PHYIDR2_OUI_LSB_DEFAULT 0xB800 +#define DM9000_PHYIDR2_VNDR_MDL 0x03F0 +#define DM9000_PHYIDR2_VNDR_MDL_DEFAULT 0x0070 +#define DM9000_PHYIDR2_MDL_REV 0x000F +#define DM9000_PHYIDR2_MDL_REV_DEFAULT 0x0000 + +//Auto-Negotiation Advertisement register +#define DM9000_ANAR_NP 0x8000 +#define DM9000_ANAR_ACK 0x4000 +#define DM9000_ANAR_RF 0x2000 +#define DM9000_ANAR_FCS 0x0400 +#define DM9000_ANAR_100BT4 0x0200 +#define DM9000_ANAR_100BTX_FD 0x0100 +#define DM9000_ANAR_100BTX_HD 0x0080 +#define DM9000_ANAR_10BT_FD 0x0040 +#define DM9000_ANAR_10BT_HD 0x0020 +#define DM9000_ANAR_SELECTOR 0x001F +#define DM9000_ANAR_SELECTOR_DEFAULT 0x0001 + +//Auto-Negotiation Link Partner Ability register +#define DM9000_ANLPAR_NP 0x8000 +#define DM9000_ANLPAR_ACK 0x4000 +#define DM9000_ANLPAR_RF 0x2000 +#define DM9000_ANLPAR_FCS 0x0400 +#define DM9000_ANLPAR_100BT4 0x0200 +#define DM9000_ANLPAR_100BTX_FD 0x0100 +#define DM9000_ANLPAR_100BTX_HD 0x0080 +#define DM9000_ANLPAR_10BT_FD 0x0040 +#define DM9000_ANLPAR_10BT_HD 0x0020 +#define DM9000_ANLPAR_SELECTOR 0x001F +#define DM9000_ANLPAR_SELECTOR_DEFAULT 0x0001 + +//Auto-Negotiation Expansion register +#define DM9000_ANER_PDF 0x0010 +#define DM9000_ANER_LP_NP_ABLE 0x0008 +#define DM9000_ANER_NP_ABLE 0x0004 +#define DM9000_ANER_PAGE_RX 0x0002 +#define DM9000_ANER_LP_AN_ABLE 0x0001 + +//Davicom Specified Configuration register +#define DM9000_DSCR_BP_4B5B 0x8000 +#define DM9000_DSCR_BP_SCR 0x4000 +#define DM9000_DSCR_BP_ALIGN 0x2000 +#define DM9000_DSCR_BP_ADPOK 0x1000 +#define DM9000_DSCR_TX_FX 0x0400 +#define DM9000_DSCR_F_LINK_100 0x0080 +#define DM9000_DSCR_SPLED_CTL 0x0040 +#define DM9000_DSCR_COLLED_CTL 0x0020 +#define DM9000_DSCR_RPDCTR_EN 0x0010 +#define DM9000_DSCR_SMRST 0x0008 +#define DM9000_DSCR_MFPSC 0x0004 +#define DM9000_DSCR_SLEEP 0x0002 +#define DM9000_DSCR_RLOUT 0x0001 + +//Davicom Specified Configuration/Status register +#define DM9000_DSCSR_100FDX 0x8000 +#define DM9000_DSCSR_100HDX 0x4000 +#define DM9000_DSCSR_10FDX 0x2000 +#define DM9000_DSCSR_10HDX 0x1000 +#define DM9000_DSCSR_PHYADR 0x01F0 +#define DM9000_DSCSR_ANMB 0x000F + +//10BASE-T Configuration/Status register +#define DM9000_10BTCSR_LP_EN 0x4000 +#define DM9000_10BTCSR_HBE 0x2000 +#define DM9000_10BTCSR_SQUELCH 0x1000 +#define DM9000_10BTCSR_JABEN 0x0800 +#define DM9000_10BTCSR_POLR 0x0001 + +//Power Down Control register +#define DM9000_PWDOR_PD10DRV 0x0100 +#define DM9000_PWDOR_PD100DL 0x0080 +#define DM9000_PWDOR_PDCHIP 0x0040 +#define DM9000_PWDOR_PDCOM 0x0020 +#define DM9000_PWDOR_PDAEQ 0x0010 +#define DM9000_PWDOR_PDDRV 0x0008 +#define DM9000_PWDOR_PDEDI 0x0004 +#define DM9000_PWDOR_PDEDO 0x0002 +#define DM9000_PWDOR_PD10 0x0001 + +//Specified Configuration register +#define DM9000_SCR_TSTSE1 0x8000 +#define DM9000_SCR_TSTSE2 0x4000 +#define DM9000_SCR_FORCE_TXSD 0x2000 +#define DM9000_SCR_FORCE_FEF 0x1000 +#define DM9000_SCR_PREAMBLEX 0x0800 +#define DM9000_SCR_TX10M_PWR 0x0400 +#define DM9000_SCR_NWAY_PWR 0x0200 +#define DM9000_SCR_MDIX_CNTL 0x0080 +#define DM9000_SCR_AUTONEG_LPBK 0x0040 +#define DM9000_SCR_MDIX_FIX 0x0020 +#define DM9000_SCR_MDIX_DOWN 0x0010 +#define DM9000_SCR_MONSEL1 0x0008 +#define DM9000_SCR_MONSEL0 0x0004 +#define DM9000_SCR_PD_VALUE 0x0001 + +//DSP Control register +#define DM9000_DSPCR_DSP 0xFFFF + +//Power Saving Control register +#define DM9000_PSCR_PREAMBLEX 0x0800 +#define DM9000_PSCR_AMPLITUDE 0x0400 +#define DM9000_PSCR_TX_PWR 0x0200 //C++ guard #ifdef __cplusplus diff --git a/drivers/eth/enc28j60_driver.c b/drivers/eth/enc28j60_driver.c index 07e788ab..27c88bcf 100644 --- a/drivers/eth/enc28j60_driver.c +++ b/drivers/eth/enc28j60_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,14 +25,13 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level #define TRACE_LEVEL NIC_TRACE_LEVEL //Dependencies -#include #include "core/net.h" #include "drivers/eth/enc28j60_driver.h" #include "debug.h" @@ -105,113 +104,117 @@ error_t enc28j60Init(NetInterface *interface) } //Read silicon revision ID - revisionId = enc28j60ReadReg(interface, ENC28J60_REG_EREVID); + revisionId = enc28j60ReadReg(interface, ENC28J60_EREVID); //Debug message TRACE_INFO("ENC28J60 revision ID: 0x%02X\r\n", revisionId); //Disable CLKOUT output - enc28j60WriteReg(interface, ENC28J60_REG_ECOCON, 0x00); + enc28j60WriteReg(interface, ENC28J60_ECOCON, ENC28J60_ECOCON_COCON_DISABLED); //Set the MAC address of the station - enc28j60WriteReg(interface, ENC28J60_REG_MAADR1, interface->macAddr.b[0]); - enc28j60WriteReg(interface, ENC28J60_REG_MAADR2, interface->macAddr.b[1]); - enc28j60WriteReg(interface, ENC28J60_REG_MAADR3, interface->macAddr.b[2]); - enc28j60WriteReg(interface, ENC28J60_REG_MAADR4, interface->macAddr.b[3]); - enc28j60WriteReg(interface, ENC28J60_REG_MAADR5, interface->macAddr.b[4]); - enc28j60WriteReg(interface, ENC28J60_REG_MAADR6, interface->macAddr.b[5]); + enc28j60WriteReg(interface, ENC28J60_MAADR5, interface->macAddr.b[0]); + enc28j60WriteReg(interface, ENC28J60_MAADR4, interface->macAddr.b[1]); + enc28j60WriteReg(interface, ENC28J60_MAADR3, interface->macAddr.b[2]); + enc28j60WriteReg(interface, ENC28J60_MAADR2, interface->macAddr.b[3]); + enc28j60WriteReg(interface, ENC28J60_MAADR1, interface->macAddr.b[4]); + enc28j60WriteReg(interface, ENC28J60_MAADR0, interface->macAddr.b[5]); //Set receive buffer location - enc28j60WriteReg(interface, ENC28J60_REG_ERXSTL, LSB(ENC28J60_RX_BUFFER_START)); - enc28j60WriteReg(interface, ENC28J60_REG_ERXSTH, MSB(ENC28J60_RX_BUFFER_START)); - enc28j60WriteReg(interface, ENC28J60_REG_ERXNDL, LSB(ENC28J60_RX_BUFFER_STOP)); - enc28j60WriteReg(interface, ENC28J60_REG_ERXNDH, MSB(ENC28J60_RX_BUFFER_STOP)); + enc28j60WriteReg(interface, ENC28J60_ERXSTL, LSB(ENC28J60_RX_BUFFER_START)); + enc28j60WriteReg(interface, ENC28J60_ERXSTH, MSB(ENC28J60_RX_BUFFER_START)); + enc28j60WriteReg(interface, ENC28J60_ERXNDL, LSB(ENC28J60_RX_BUFFER_STOP)); + enc28j60WriteReg(interface, ENC28J60_ERXNDH, MSB(ENC28J60_RX_BUFFER_STOP)); - //The ERXRDPT register defines a location within the FIFO - //where the receive hardware is forbidden to write to - enc28j60WriteReg(interface, ENC28J60_REG_ERXRDPTL, LSB(ENC28J60_RX_BUFFER_STOP)); - enc28j60WriteReg(interface, ENC28J60_REG_ERXRDPTH, MSB(ENC28J60_RX_BUFFER_STOP)); + //The ERXRDPT register defines a location within the FIFO where the receive + //hardware is forbidden to write to + enc28j60WriteReg(interface, ENC28J60_ERXRDPTL, LSB(ENC28J60_RX_BUFFER_STOP)); + enc28j60WriteReg(interface, ENC28J60_ERXRDPTH, MSB(ENC28J60_RX_BUFFER_STOP)); //Configure the receive filters - enc28j60WriteReg(interface, ENC28J60_REG_ERXFCON, ERXFCON_UCEN | - ERXFCON_CRCEN | ERXFCON_HTEN | ERXFCON_BCEN); + enc28j60WriteReg(interface, ENC28J60_ERXFCON, ENC28J60_ERXFCON_UCEN | + ENC28J60_ERXFCON_CRCEN | ENC28J60_ERXFCON_HTEN | ENC28J60_ERXFCON_BCEN); //Initialize the hash table - enc28j60WriteReg(interface, ENC28J60_REG_EHT0, 0x00); - enc28j60WriteReg(interface, ENC28J60_REG_EHT1, 0x00); - enc28j60WriteReg(interface, ENC28J60_REG_EHT2, 0x00); - enc28j60WriteReg(interface, ENC28J60_REG_EHT3, 0x00); - enc28j60WriteReg(interface, ENC28J60_REG_EHT4, 0x00); - enc28j60WriteReg(interface, ENC28J60_REG_EHT5, 0x00); - enc28j60WriteReg(interface, ENC28J60_REG_EHT6, 0x00); - enc28j60WriteReg(interface, ENC28J60_REG_EHT7, 0x00); + enc28j60WriteReg(interface, ENC28J60_EHT0, 0x00); + enc28j60WriteReg(interface, ENC28J60_EHT1, 0x00); + enc28j60WriteReg(interface, ENC28J60_EHT2, 0x00); + enc28j60WriteReg(interface, ENC28J60_EHT3, 0x00); + enc28j60WriteReg(interface, ENC28J60_EHT4, 0x00); + enc28j60WriteReg(interface, ENC28J60_EHT5, 0x00); + enc28j60WriteReg(interface, ENC28J60_EHT6, 0x00); + enc28j60WriteReg(interface, ENC28J60_EHT7, 0x00); //Pull the MAC out of reset - enc28j60WriteReg(interface, ENC28J60_REG_MACON2, 0x00); + enc28j60WriteReg(interface, ENC28J60_MACON2, 0x00); //Enable the MAC to receive frames - enc28j60WriteReg(interface, ENC28J60_REG_MACON1, - MACON1_TXPAUS | MACON1_RXPAUS | MACON1_MARXEN); + enc28j60WriteReg(interface, ENC28J60_MACON1, ENC28J60_MACON1_TXPAUS | + ENC28J60_MACON1_RXPAUS | ENC28J60_MACON1_MARXEN); - //Enable automatic padding to at least 60 bytes, always append a valid CRC - //and check frame length. MAC can operate in half-duplex or full-duplex mode + //Enable automatic padding, always append a valid CRC and check frame + //length. MAC can operate in half-duplex or full-duplex mode #if (ENC28J60_FULL_DUPLEX_SUPPORT == ENABLED) - enc28j60WriteReg(interface, ENC28J60_REG_MACON3, MACON3_PADCFG(1) | - MACON3_TXCRCEN | MACON3_FRMLNEN | MACON3_FULDPX); + enc28j60WriteReg(interface, ENC28J60_MACON3, ENC28J60_MACON3_PADCFG_AUTO | + ENC28J60_MACON3_TXCRCEN | ENC28J60_MACON3_FRMLNEN | + ENC28J60_MACON3_FULDPX); #else - enc28j60WriteReg(interface, ENC28J60_REG_MACON3, MACON3_PADCFG(1) | - MACON3_TXCRCEN | MACON3_FRMLNEN); + enc28j60WriteReg(interface, ENC28J60_MACON3, ENC28J60_MACON3_PADCFG_AUTO | + ENC28J60_MACON3_TXCRCEN | ENC28J60_MACON3_FRMLNEN); #endif //When the medium is occupied, the MAC will wait indefinitely for it to //become free when attempting to transmit - enc28j60WriteReg(interface, ENC28J60_REG_MACON4, MACON4_DEFER); + enc28j60WriteReg(interface, ENC28J60_MACON4, ENC28J60_MACON4_DEFER); //Maximum frame length that can be received or transmitted - enc28j60WriteReg(interface, ENC28J60_REG_MAMXFLL, LSB(ETH_MAX_FRAME_SIZE)); - enc28j60WriteReg(interface, ENC28J60_REG_MAMXFLH, MSB(ETH_MAX_FRAME_SIZE)); + enc28j60WriteReg(interface, ENC28J60_MAMXFLL, LSB(ETH_MAX_FRAME_SIZE)); + enc28j60WriteReg(interface, ENC28J60_MAMXFLH, MSB(ETH_MAX_FRAME_SIZE)); //Configure the back-to-back inter-packet gap register #if (ENC28J60_FULL_DUPLEX_SUPPORT == ENABLED) - enc28j60WriteReg(interface, ENC28J60_REG_MABBIPG, 0x15); + enc28j60WriteReg(interface, ENC28J60_MABBIPG, ENC28J60_MABBIPG_DEFAULT_FD); #else - enc28j60WriteReg(interface, ENC28J60_REG_MABBIPG, 0x12); + enc28j60WriteReg(interface, ENC28J60_MABBIPG, ENC28J60_MABBIPG_DEFAULT_HD); #endif //Configure the non-back-to-back inter-packet gap register - enc28j60WriteReg(interface, ENC28J60_REG_MAIPGL, 0x12); - enc28j60WriteReg(interface, ENC28J60_REG_MAIPGH, 0x0C); + enc28j60WriteReg(interface, ENC28J60_MAIPGL, ENC28J60_MAIPGL_DEFAULT); + enc28j60WriteReg(interface, ENC28J60_MAIPGH, ENC28J60_MAIPGH_DEFAULT); //Collision window register - enc28j60WriteReg(interface, ENC28J60_REG_MACLCON2, 63); + enc28j60WriteReg(interface, ENC28J60_MACLCON2, + ENC28J60_MACLCON2_COLWIN_DEFAULT); //Set the PHY to the proper duplex mode #if (ENC28J60_FULL_DUPLEX_SUPPORT == ENABLED) - enc28j60WritePhyReg(interface, ENC28J60_PHY_REG_PHCON1, PHCON1_PDPXMD); + enc28j60WritePhyReg(interface, ENC28J60_PHCON1, ENC28J60_PHCON1_PDPXMD); #else - enc28j60WritePhyReg(interface, ENC28J60_PHY_REG_PHCON1, 0x0000); + enc28j60WritePhyReg(interface, ENC28J60_PHCON1, 0x0000); #endif //Disable half-duplex loopback in PHY - enc28j60WritePhyReg(interface, ENC28J60_PHY_REG_PHCON2, PHCON2_HDLDIS); + enc28j60WritePhyReg(interface, ENC28J60_PHCON2, ENC28J60_PHCON2_HDLDIS); //LEDA displays link status and LEDB displays TX/RX activity - enc28j60WritePhyReg(interface, ENC28J60_PHY_REG_PHLCON, - PHLCON_LACFG(4) | PHLCON_LBCFG(7) | PHLCON_LFRQ(0) | PHLCON_STRCH); + enc28j60WritePhyReg(interface, ENC28J60_PHLCON, + ENC28J60_PHLCON_LACFG_LINK | ENC28J60_PHLCON_LBCFG_TX_RX | + ENC28J60_PHLCON_LFRQ_40_MS | ENC28J60_PHLCON_STRCH); //Clear interrupt flags - enc28j60WriteReg(interface, ENC28J60_REG_EIR, 0x00); + enc28j60WriteReg(interface, ENC28J60_EIR, 0x00); //Configure interrupts as desired - enc28j60WriteReg(interface, ENC28J60_REG_EIE, EIE_INTIE | - EIE_PKTIE | EIE_LINKIE | EIE_TXIE | EIE_TXERIE); + enc28j60WriteReg(interface, ENC28J60_EIE, ENC28J60_EIE_INTIE | + ENC28J60_EIE_PKTIE | ENC28J60_EIE_LINKIE | ENC28J60_EIE_TXIE | + ENC28J60_EIE_TXERIE); //Configure PHY interrupts as desired - enc28j60WritePhyReg(interface, ENC28J60_PHY_REG_PHIE, - PHIE_PLNKIE | PHIE_PGEIE); + enc28j60WritePhyReg(interface, ENC28J60_PHIE, ENC28J60_PHIE_PLNKIE | + ENC28J60_PHIE_PGEIE); //Set RXEN to enable reception - enc28j60SetBit(interface, ENC28J60_REG_ECON1, ECON1_RXEN); + enc28j60SetBit(interface, ENC28J60_ECON1, ENC28J60_ECON1_RXEN); //Dump registers for debugging purpose enc28j60DumpReg(interface); @@ -279,16 +282,16 @@ bool_t enc28j60IrqHandler(NetInterface *interface) flag = FALSE; //Clear the INTIE bit, immediately after an interrupt event - enc28j60ClearBit(interface, ENC28J60_REG_EIE, EIE_INTIE); + enc28j60ClearBit(interface, ENC28J60_EIE, ENC28J60_EIE_INTIE); //Read interrupt status register - status = enc28j60ReadReg(interface, ENC28J60_REG_EIR); + status = enc28j60ReadReg(interface, ENC28J60_EIR); //Link status change? - if((status & EIR_LINKIF) != 0) + if((status & ENC28J60_EIR_LINKIF) != 0) { //Disable LINKIE interrupt - enc28j60ClearBit(interface, ENC28J60_REG_EIE, EIE_LINKIE); + enc28j60ClearBit(interface, ENC28J60_EIE, ENC28J60_EIE_LINKIE); //Set event flag interface->nicEvent = TRUE; @@ -297,10 +300,10 @@ bool_t enc28j60IrqHandler(NetInterface *interface) } //Packet received? - if((status & EIR_PKTIF) != 0) + if(enc28j60ReadReg(interface, ENC28J60_EPKTCNT) != 0) { //Disable PKTIE interrupt - enc28j60ClearBit(interface, ENC28J60_REG_EIE, EIE_PKTIE); + enc28j60ClearBit(interface, ENC28J60_EIE, ENC28J60_EIE_PKTIE); //Set event flag interface->nicEvent = TRUE; @@ -309,10 +312,11 @@ bool_t enc28j60IrqHandler(NetInterface *interface) } //Packet transmission complete? - if((status & (EIR_TXIF | EIE_TXERIE)) != 0) + if((status & (ENC28J60_EIR_TXIF | ENC28J60_EIE_TXERIE)) != 0) { //Clear interrupt flags - enc28j60ClearBit(interface, ENC28J60_REG_EIR, EIR_TXIF | EIE_TXERIE); + enc28j60ClearBit(interface, ENC28J60_EIR, ENC28J60_EIR_TXIF | + ENC28J60_EIE_TXERIE); //Notify the TCP/IP stack that the transmitter is ready to send flag |= osSetEventFromIsr(&interface->nicTxEvent); @@ -320,7 +324,7 @@ bool_t enc28j60IrqHandler(NetInterface *interface) //Once the interrupt has been serviced, the INTIE bit //is set again to re-enable interrupts - enc28j60SetBit(interface, ENC28J60_REG_EIE, EIE_INTIE); + enc28j60SetBit(interface, ENC28J60_EIE, ENC28J60_EIE_INTIE); //A higher priority task must be woken? return flag; @@ -339,20 +343,20 @@ void enc28j60EventHandler(NetInterface *interface) uint16_t value; //Read interrupt status register - status = enc28j60ReadReg(interface, ENC28J60_REG_EIR); + status = enc28j60ReadReg(interface, ENC28J60_EIR); //Check whether the link state has changed - if((status & EIR_LINKIF) != 0) + if((status & ENC28J60_EIR_LINKIF) != 0) { //Clear PHY interrupts flags - enc28j60ReadPhyReg(interface, ENC28J60_PHY_REG_PHIR); + enc28j60ReadPhyReg(interface, ENC28J60_PHIR); //Clear interrupt flag - enc28j60ClearBit(interface, ENC28J60_REG_EIR, EIR_LINKIF); + enc28j60ClearBit(interface, ENC28J60_EIR, ENC28J60_EIR_LINKIF); //Read PHY status register - value = enc28j60ReadPhyReg(interface, ENC28J60_PHY_REG_PHSTAT2); + value = enc28j60ReadPhyReg(interface, ENC28J60_PHSTAT2); //Check link state - if((value & PHSTAT2_LSTAT) != 0) + if((value & ENC28J60_PHSTAT2_LSTAT) != 0) { //Link speed interface->linkSpeed = NIC_LINK_SPEED_10MBPS; @@ -378,10 +382,10 @@ void enc28j60EventHandler(NetInterface *interface) } //Check whether a packet has been received? - if((status & EIR_PKTIF) != 0) + if(enc28j60ReadReg(interface, ENC28J60_EPKTCNT) != 0) { //Clear interrupt flag - enc28j60ClearBit(interface, ENC28J60_REG_EIR, EIR_PKTIF); + enc28j60ClearBit(interface, ENC28J60_EIR, ENC28J60_EIR_PKTIF); //Process all pending packets do @@ -394,7 +398,8 @@ void enc28j60EventHandler(NetInterface *interface) } //Re-enable LINKIE and PKTIE interrupts - enc28j60SetBit(interface, ENC28J60_REG_EIE, EIE_LINKIE | EIE_PKTIE); + enc28j60SetBit(interface, ENC28J60_EIE, ENC28J60_EIE_LINKIE | + ENC28J60_EIE_PKTIE); } @@ -436,29 +441,30 @@ error_t enc28j60SendPacket(NetInterface *interface, //It is recommended to reset the transmit logic before //attempting to transmit a packet - enc28j60SetBit(interface, ENC28J60_REG_ECON1, ECON1_TXRST); - enc28j60ClearBit(interface, ENC28J60_REG_ECON1, ECON1_TXRST); + enc28j60SetBit(interface, ENC28J60_ECON1, ENC28J60_ECON1_TXRST); + enc28j60ClearBit(interface, ENC28J60_ECON1, ENC28J60_ECON1_TXRST); //Interrupt flags should be cleared after the reset is completed - enc28j60ClearBit(interface, ENC28J60_REG_EIR, EIR_TXIF | EIR_TXERIF); + enc28j60ClearBit(interface, ENC28J60_EIR, ENC28J60_EIR_TXIF | + ENC28J60_EIR_TXERIF); //Set transmit buffer location - enc28j60WriteReg(interface, ENC28J60_REG_ETXSTL, LSB(ENC28J60_TX_BUFFER_START)); - enc28j60WriteReg(interface, ENC28J60_REG_ETXSTH, MSB(ENC28J60_TX_BUFFER_START)); + enc28j60WriteReg(interface, ENC28J60_ETXSTL, LSB(ENC28J60_TX_BUFFER_START)); + enc28j60WriteReg(interface, ENC28J60_ETXSTH, MSB(ENC28J60_TX_BUFFER_START)); //Point to start of transmit buffer - enc28j60WriteReg(interface, ENC28J60_REG_EWRPTL, LSB(ENC28J60_TX_BUFFER_START)); - enc28j60WriteReg(interface, ENC28J60_REG_EWRPTH, MSB(ENC28J60_TX_BUFFER_START)); + enc28j60WriteReg(interface, ENC28J60_EWRPTL, LSB(ENC28J60_TX_BUFFER_START)); + enc28j60WriteReg(interface, ENC28J60_EWRPTH, MSB(ENC28J60_TX_BUFFER_START)); //Copy the data to the transmit buffer enc28j60WriteBuffer(interface, buffer, offset); //ETXND should point to the last byte in the data payload - enc28j60WriteReg(interface, ENC28J60_REG_ETXNDL, LSB(ENC28J60_TX_BUFFER_START + length)); - enc28j60WriteReg(interface, ENC28J60_REG_ETXNDH, MSB(ENC28J60_TX_BUFFER_START + length)); + enc28j60WriteReg(interface, ENC28J60_ETXNDL, LSB(ENC28J60_TX_BUFFER_START + length)); + enc28j60WriteReg(interface, ENC28J60_ETXNDH, MSB(ENC28J60_TX_BUFFER_START + length)); //Start transmission - enc28j60SetBit(interface, ENC28J60_REG_ECON1, ECON1_TXRTS); + enc28j60SetBit(interface, ENC28J60_ECON1, ENC28J60_ECON1_TXRTS); //Successful processing return NO_ERROR; @@ -474,34 +480,38 @@ error_t enc28j60SendPacket(NetInterface *interface, error_t enc28j60ReceivePacket(NetInterface *interface) { error_t error; - uint16_t n; + uint16_t length; uint16_t status; + uint8_t header[6]; Enc28j60Context *context; //Point to the driver context context = (Enc28j60Context *) interface->nicContext; //Any packet pending in the receive buffer? - if(enc28j60ReadReg(interface, ENC28J60_REG_EPKTCNT)) + if(enc28j60ReadReg(interface, ENC28J60_EPKTCNT) != 0) { //Point to the start of the received packet - enc28j60WriteReg(interface, ENC28J60_REG_ERDPTL, LSB(context->nextPacket)); - enc28j60WriteReg(interface, ENC28J60_REG_ERDPTH, MSB(context->nextPacket)); + enc28j60WriteReg(interface, ENC28J60_ERDPTL, LSB(context->nextPacket)); + enc28j60WriteReg(interface, ENC28J60_ERDPTH, MSB(context->nextPacket)); - //Read the first two bytes, which are the address of the next packet - enc28j60ReadBuffer(interface, (uint8_t *) &context->nextPacket, sizeof(uint16_t)); - //Get the length of the received frame in bytes - enc28j60ReadBuffer(interface, (uint8_t *) &n, sizeof(uint16_t)); - //Read the receive status vector (RSV) - enc28j60ReadBuffer(interface, (uint8_t *) &status, sizeof(uint16_t)); + //The packet is preceded by a 6-byte header + enc28j60ReadBuffer(interface, header, sizeof(header)); + + //The first two bytes are the address of the next packet + context->nextPacket = LOAD16LE(header); + //Get the length of the received packet + length = LOAD16LE(header + 2); + //Get the receive status vector (RSV) + status = LOAD16LE(header + 4); //Make sure no error occurred - if((status & RSV_RECEIVED_OK) != 0) + if((status & ENC28J60_RSV_RECEIVED_OK) != 0) { //Limit the number of data to read - n = MIN(n, ETH_MAX_FRAME_SIZE); + length = MIN(length, ETH_MAX_FRAME_SIZE); //Read the Ethernet frame - enc28j60ReadBuffer(interface, context->rxBuffer, n); + enc28j60ReadBuffer(interface, context->rxBuffer, length); //Valid packet received error = NO_ERROR; } @@ -515,17 +525,17 @@ error_t enc28j60ReceivePacket(NetInterface *interface) //end of the received memory buffer if(context->nextPacket == ENC28J60_RX_BUFFER_START) { - enc28j60WriteReg(interface, ENC28J60_REG_ERXRDPTL, LSB(ENC28J60_RX_BUFFER_STOP)); - enc28j60WriteReg(interface, ENC28J60_REG_ERXRDPTH, MSB(ENC28J60_RX_BUFFER_STOP)); + enc28j60WriteReg(interface, ENC28J60_ERXRDPTL, LSB(ENC28J60_RX_BUFFER_STOP)); + enc28j60WriteReg(interface, ENC28J60_ERXRDPTH, MSB(ENC28J60_RX_BUFFER_STOP)); } else { - enc28j60WriteReg(interface, ENC28J60_REG_ERXRDPTL, LSB(context->nextPacket - 1)); - enc28j60WriteReg(interface, ENC28J60_REG_ERXRDPTH, MSB(context->nextPacket - 1)); + enc28j60WriteReg(interface, ENC28J60_ERXRDPTL, LSB(context->nextPacket - 1)); + enc28j60WriteReg(interface, ENC28J60_ERXRDPTH, MSB(context->nextPacket - 1)); } //Decrement the packet counter - enc28j60SetBit(interface, ENC28J60_REG_ECON2, ECON2_PKTDEC); + enc28j60SetBit(interface, ENC28J60_ECON2, ENC28J60_ECON2_PKTDEC); } else { @@ -542,7 +552,7 @@ error_t enc28j60ReceivePacket(NetInterface *interface) ancillary = NET_DEFAULT_RX_ANCILLARY; //Pass the packet to the upper layer - nicProcessPacket(interface, context->rxBuffer, n, &ancillary); + nicProcessPacket(interface, context->rxBuffer, length, &ancillary); } //Return status code @@ -590,24 +600,24 @@ error_t enc28j60UpdateMacAddrFilter(NetInterface *interface) } //Write the hash table to the ENC28J60 controller - enc28j60WriteReg(interface, ENC28J60_REG_EHT0, hashTable[0]); - enc28j60WriteReg(interface, ENC28J60_REG_EHT1, hashTable[1]); - enc28j60WriteReg(interface, ENC28J60_REG_EHT2, hashTable[2]); - enc28j60WriteReg(interface, ENC28J60_REG_EHT3, hashTable[3]); - enc28j60WriteReg(interface, ENC28J60_REG_EHT4, hashTable[4]); - enc28j60WriteReg(interface, ENC28J60_REG_EHT5, hashTable[5]); - enc28j60WriteReg(interface, ENC28J60_REG_EHT6, hashTable[6]); - enc28j60WriteReg(interface, ENC28J60_REG_EHT7, hashTable[7]); + enc28j60WriteReg(interface, ENC28J60_EHT0, hashTable[0]); + enc28j60WriteReg(interface, ENC28J60_EHT1, hashTable[1]); + enc28j60WriteReg(interface, ENC28J60_EHT2, hashTable[2]); + enc28j60WriteReg(interface, ENC28J60_EHT3, hashTable[3]); + enc28j60WriteReg(interface, ENC28J60_EHT4, hashTable[4]); + enc28j60WriteReg(interface, ENC28J60_EHT5, hashTable[5]); + enc28j60WriteReg(interface, ENC28J60_EHT6, hashTable[6]); + enc28j60WriteReg(interface, ENC28J60_EHT7, hashTable[7]); //Debug message - TRACE_DEBUG(" EHT0 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_REG_EHT0)); - TRACE_DEBUG(" EHT1 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_REG_EHT1)); - TRACE_DEBUG(" EHT2 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_REG_EHT2)); - TRACE_DEBUG(" EHT3 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_REG_EHT3)); - TRACE_DEBUG(" EHT0 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_REG_EHT4)); - TRACE_DEBUG(" EHT1 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_REG_EHT5)); - TRACE_DEBUG(" EHT2 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_REG_EHT6)); - TRACE_DEBUG(" EHT3 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_REG_EHT7)); + TRACE_DEBUG(" EHT0 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_EHT0)); + TRACE_DEBUG(" EHT1 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_EHT1)); + TRACE_DEBUG(" EHT2 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_EHT2)); + TRACE_DEBUG(" EHT3 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_EHT3)); + TRACE_DEBUG(" EHT0 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_EHT4)); + TRACE_DEBUG(" EHT1 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_EHT5)); + TRACE_DEBUG(" EHT2 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_EHT6)); + TRACE_DEBUG(" EHT3 = %02" PRIX8 "\r\n", enc28j60ReadReg(interface, ENC28J60_EHT7)); //Successful processing return NO_ERROR; @@ -652,30 +662,30 @@ void enc28j60SelectBank(NetInterface *interface, uint16_t address) //Rewrite the bank number only if a change is detected if(bank != context->currentBank) { - //Select specified bank - switch(bank) + //Select the relevant bank + if(bank == BANK_0) { - case BANK_0: //Select bank 0 - enc28j60ClearBit(interface, ENC28J60_REG_ECON1, ECON1_BSEL1 | ECON1_BSEL0); - break; - case BANK_1: + enc28j60ClearBit(interface, ENC28J60_ECON1, ENC28J60_ECON1_BSEL1 | + ENC28J60_ECON1_BSEL0); + } + else if(bank == BANK_1) + { //Select bank 1 - enc28j60SetBit(interface, ENC28J60_REG_ECON1, ECON1_BSEL0); - enc28j60ClearBit(interface, ENC28J60_REG_ECON1, ECON1_BSEL1); - break; - case BANK_2: + enc28j60SetBit(interface, ENC28J60_ECON1, ENC28J60_ECON1_BSEL0); + enc28j60ClearBit(interface, ENC28J60_ECON1, ENC28J60_ECON1_BSEL1); + } + else if(bank == BANK_2) + { //Select bank 2 - enc28j60ClearBit(interface, ENC28J60_REG_ECON1, ECON1_BSEL0); - enc28j60SetBit(interface, ENC28J60_REG_ECON1, ECON1_BSEL1); - break; - case BANK_3: + enc28j60ClearBit(interface, ENC28J60_ECON1, ENC28J60_ECON1_BSEL0); + enc28j60SetBit(interface, ENC28J60_ECON1, ENC28J60_ECON1_BSEL1); + } + else + { //Select bank 3 - enc28j60SetBit(interface, ENC28J60_REG_ECON1, ECON1_BSEL1 | ECON1_BSEL0); - break; - default: - //Invalid bank - break; + enc28j60SetBit(interface, ENC28J60_ECON1, ENC28J60_ECON1_BSEL1 | + ENC28J60_ECON1_BSEL0); } //Save bank number @@ -757,15 +767,15 @@ void enc28j60WritePhyReg(NetInterface *interface, uint16_t address, uint16_t data) { //Write register address - enc28j60WriteReg(interface, ENC28J60_REG_MIREGADR, address & REG_ADDR_MASK); + enc28j60WriteReg(interface, ENC28J60_MIREGADR, address & REG_ADDR_MASK); //Write the lower 8 bits - enc28j60WriteReg(interface, ENC28J60_REG_MIWRL, LSB(data)); + enc28j60WriteReg(interface, ENC28J60_MIWRL, LSB(data)); //Write the upper 8 bits - enc28j60WriteReg(interface, ENC28J60_REG_MIWRH, MSB(data)); + enc28j60WriteReg(interface, ENC28J60_MIWRH, MSB(data)); //Wait until the PHY register has been written - while((enc28j60ReadReg(interface, ENC28J60_REG_MISTAT) & MISTAT_BUSY) != 0) + while((enc28j60ReadReg(interface, ENC28J60_MISTAT) & ENC28J60_MISTAT_BUSY) != 0) { } } @@ -783,22 +793,22 @@ uint16_t enc28j60ReadPhyReg(NetInterface *interface, uint16_t address) uint16_t data; //Write register address - enc28j60WriteReg(interface, ENC28J60_REG_MIREGADR, address & REG_ADDR_MASK); + enc28j60WriteReg(interface, ENC28J60_MIREGADR, address & REG_ADDR_MASK); //Start read operation - enc28j60WriteReg(interface, ENC28J60_REG_MICMD, MICMD_MIIRD); + enc28j60WriteReg(interface, ENC28J60_MICMD, ENC28J60_MICMD_MIIRD); //Wait for the read operation to complete - while((enc28j60ReadReg(interface, ENC28J60_REG_MISTAT) & MISTAT_BUSY) != 0) + while((enc28j60ReadReg(interface, ENC28J60_MISTAT) & ENC28J60_MISTAT_BUSY) != 0) { } //Clear command register - enc28j60WriteReg(interface, ENC28J60_REG_MICMD, 0); + enc28j60WriteReg(interface, ENC28J60_MICMD, 0); //Read the lower 8 bits - data = enc28j60ReadReg(interface, ENC28J60_REG_MIRDL); + data = enc28j60ReadReg(interface, ENC28J60_MIRDL); //Read the upper 8 bits - data |= enc28j60ReadReg(interface, ENC28J60_REG_MIRDH) << 8; + data |= enc28j60ReadReg(interface, ENC28J60_MIRDH) << 8; //Return register contents return data; diff --git a/drivers/eth/enc28j60_driver.h b/drivers/eth/enc28j60_driver.h index 01c1f68f..056b3d2a 100644 --- a/drivers/eth/enc28j60_driver.h +++ b/drivers/eth/enc28j60_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ENC28J60_DRIVER_H @@ -38,12 +38,6 @@ #error ENC28J60_FULL_DUPLEX_SUPPORT parameter is not valid #endif -//Silicon revision identifiers -#define ENC28J60_REV_B1 0x02 -#define ENC28J60_REV_B4 0x04 -#define ENC28J60_REV_B5 0x05 -#define ENC28J60_REV_B7 0x06 - //Receive and transmit buffers #define ENC28J60_RX_BUFFER_START 0x0000 #define ENC28J60_RX_BUFFER_STOP 0x17FF @@ -76,306 +70,387 @@ #define REG_BANK_MASK 0x0F00 #define REG_ADDR_MASK 0x001F -//Bank 0 registers -#define ENC28J60_REG_ERDPTL (ETH_REG_TYPE | BANK_0 | 0x00) -#define ENC28J60_REG_ERDPTH (ETH_REG_TYPE | BANK_0 | 0x01) -#define ENC28J60_REG_EWRPTL (ETH_REG_TYPE | BANK_0 | 0x02) -#define ENC28J60_REG_EWRPTH (ETH_REG_TYPE | BANK_0 | 0x03) -#define ENC28J60_REG_ETXSTL (ETH_REG_TYPE | BANK_0 | 0x04) -#define ENC28J60_REG_ETXSTH (ETH_REG_TYPE | BANK_0 | 0x05) -#define ENC28J60_REG_ETXNDL (ETH_REG_TYPE | BANK_0 | 0x06) -#define ENC28J60_REG_ETXNDH (ETH_REG_TYPE | BANK_0 | 0x07) -#define ENC28J60_REG_ERXSTL (ETH_REG_TYPE | BANK_0 | 0x08) -#define ENC28J60_REG_ERXSTH (ETH_REG_TYPE | BANK_0 | 0x09) -#define ENC28J60_REG_ERXNDL (ETH_REG_TYPE | BANK_0 | 0x0A) -#define ENC28J60_REG_ERXNDH (ETH_REG_TYPE | BANK_0 | 0x0B) -#define ENC28J60_REG_ERXRDPTL (ETH_REG_TYPE | BANK_0 | 0x0C) -#define ENC28J60_REG_ERXRDPTH (ETH_REG_TYPE | BANK_0 | 0x0D) -#define ENC28J60_REG_ERXWRPTL (ETH_REG_TYPE | BANK_0 | 0x0E) -#define ENC28J60_REG_ERXWRPTH (ETH_REG_TYPE | BANK_0 | 0x0F) -#define ENC28J60_REG_EDMASTL (ETH_REG_TYPE | BANK_0 | 0x10) -#define ENC28J60_REG_EDMASTH (ETH_REG_TYPE | BANK_0 | 0x11) -#define ENC28J60_REG_EDMANDL (ETH_REG_TYPE | BANK_0 | 0x12) -#define ENC28J60_REG_EDMANDH (ETH_REG_TYPE | BANK_0 | 0x13) -#define ENC28J60_REG_EDMADSTL (ETH_REG_TYPE | BANK_0 | 0x14) -#define ENC28J60_REG_EDMADSTH (ETH_REG_TYPE | BANK_0 | 0x15) -#define ENC28J60_REG_EDMACSL (ETH_REG_TYPE | BANK_0 | 0x16) -#define ENC28J60_REG_EDMACSH (ETH_REG_TYPE | BANK_0 | 0x17) -#define ENC28J60_REG_EIE (ETH_REG_TYPE | BANK_0 | 0x1B) -#define ENC28J60_REG_EIR (ETH_REG_TYPE | BANK_0 | 0x1C) -#define ENC28J60_REG_ESTAT (ETH_REG_TYPE | BANK_0 | 0x1D) -#define ENC28J60_REG_ECON2 (ETH_REG_TYPE | BANK_0 | 0x1E) -#define ENC28J60_REG_ECON1 (ETH_REG_TYPE | BANK_0 | 0x1F) - -//Bank 1 registers -#define ENC28J60_REG_EHT0 (ETH_REG_TYPE | BANK_1 | 0x00) -#define ENC28J60_REG_EHT1 (ETH_REG_TYPE | BANK_1 | 0x01) -#define ENC28J60_REG_EHT2 (ETH_REG_TYPE | BANK_1 | 0x02) -#define ENC28J60_REG_EHT3 (ETH_REG_TYPE | BANK_1 | 0x03) -#define ENC28J60_REG_EHT4 (ETH_REG_TYPE | BANK_1 | 0x04) -#define ENC28J60_REG_EHT5 (ETH_REG_TYPE | BANK_1 | 0x05) -#define ENC28J60_REG_EHT6 (ETH_REG_TYPE | BANK_1 | 0x06) -#define ENC28J60_REG_EHT7 (ETH_REG_TYPE | BANK_1 | 0x07) -#define ENC28J60_REG_EPMM0 (ETH_REG_TYPE | BANK_1 | 0x08) -#define ENC28J60_REG_EPMM1 (ETH_REG_TYPE | BANK_1 | 0x09) -#define ENC28J60_REG_EPMM2 (ETH_REG_TYPE | BANK_1 | 0x0A) -#define ENC28J60_REG_EPMM3 (ETH_REG_TYPE | BANK_1 | 0x0B) -#define ENC28J60_REG_EPMM4 (ETH_REG_TYPE | BANK_1 | 0x0C) -#define ENC28J60_REG_EPMM5 (ETH_REG_TYPE | BANK_1 | 0x0D) -#define ENC28J60_REG_EPMM6 (ETH_REG_TYPE | BANK_1 | 0x0E) -#define ENC28J60_REG_EPMM7 (ETH_REG_TYPE | BANK_1 | 0x0F) -#define ENC28J60_REG_EPMCSL (ETH_REG_TYPE | BANK_1 | 0x10) -#define ENC28J60_REG_EPMCSH (ETH_REG_TYPE | BANK_1 | 0x11) -#define ENC28J60_REG_EPMOL (ETH_REG_TYPE | BANK_1 | 0x14) -#define ENC28J60_REG_EPMOH (ETH_REG_TYPE | BANK_1 | 0x15) -#define ENC28J60_REG_EWOLIE (ETH_REG_TYPE | BANK_1 | 0x16) -#define ENC28J60_REG_EWOLIR (ETH_REG_TYPE | BANK_1 | 0x17) -#define ENC28J60_REG_ERXFCON (ETH_REG_TYPE | BANK_1 | 0x18) -#define ENC28J60_REG_EPKTCNT (ETH_REG_TYPE | BANK_1 | 0x19) - -//Bank 2 registers -#define ENC28J60_REG_MACON1 (MAC_REG_TYPE | BANK_2 | 0x00) -#define ENC28J60_REG_MACON2 (MAC_REG_TYPE | BANK_2 | 0x01) -#define ENC28J60_REG_MACON3 (MAC_REG_TYPE | BANK_2 | 0x02) -#define ENC28J60_REG_MACON4 (MAC_REG_TYPE | BANK_2 | 0x03) -#define ENC28J60_REG_MABBIPG (MAC_REG_TYPE | BANK_2 | 0x04) -#define ENC28J60_REG_MAIPGL (MAC_REG_TYPE | BANK_2 | 0x06) -#define ENC28J60_REG_MAIPGH (MAC_REG_TYPE | BANK_2 | 0x07) -#define ENC28J60_REG_MACLCON1 (MAC_REG_TYPE | BANK_2 | 0x08) -#define ENC28J60_REG_MACLCON2 (MAC_REG_TYPE | BANK_2 | 0x09) -#define ENC28J60_REG_MAMXFLL (MAC_REG_TYPE | BANK_2 | 0x0A) -#define ENC28J60_REG_MAMXFLH (MAC_REG_TYPE | BANK_2 | 0x0B) -#define ENC28J60_REG_MAPHSUP (MAC_REG_TYPE | BANK_2 | 0x0D) -#define ENC28J60_REG_MICON (MII_REG_TYPE | BANK_2 | 0x11) -#define ENC28J60_REG_MICMD (MII_REG_TYPE | BANK_2 | 0x12) -#define ENC28J60_REG_MIREGADR (MII_REG_TYPE | BANK_2 | 0x14) -#define ENC28J60_REG_MIWRL (MII_REG_TYPE | BANK_2 | 0x16) -#define ENC28J60_REG_MIWRH (MII_REG_TYPE | BANK_2 | 0x17) -#define ENC28J60_REG_MIRDL (MII_REG_TYPE | BANK_2 | 0x18) -#define ENC28J60_REG_MIRDH (MII_REG_TYPE | BANK_2 | 0x19) - -//Bank 3 registers -#define ENC28J60_REG_MAADR5 (MAC_REG_TYPE | BANK_3 | 0x00) -#define ENC28J60_REG_MAADR6 (MAC_REG_TYPE | BANK_3 | 0x01) -#define ENC28J60_REG_MAADR3 (MAC_REG_TYPE | BANK_3 | 0x02) -#define ENC28J60_REG_MAADR4 (MAC_REG_TYPE | BANK_3 | 0x03) -#define ENC28J60_REG_MAADR1 (MAC_REG_TYPE | BANK_3 | 0x04) -#define ENC28J60_REG_MAADR2 (MAC_REG_TYPE | BANK_3 | 0x05) -#define ENC28J60_REG_EBSTSD (ETH_REG_TYPE | BANK_3 | 0x06) -#define ENC28J60_REG_EBSTCON (ETH_REG_TYPE | BANK_3 | 0x07) -#define ENC28J60_REG_EBSTCSL (ETH_REG_TYPE | BANK_3 | 0x08) -#define ENC28J60_REG_EBSTCSH (ETH_REG_TYPE | BANK_3 | 0x09) -#define ENC28J60_REG_MISTAT (MII_REG_TYPE | BANK_3 | 0x0A) -#define ENC28J60_REG_EREVID (ETH_REG_TYPE | BANK_3 | 0x12) -#define ENC28J60_REG_ECOCON (ETH_REG_TYPE | BANK_3 | 0x15) -#define ENC28J60_REG_EFLOCON (ETH_REG_TYPE | BANK_3 | 0x17) -#define ENC28J60_REG_EPAUSL (ETH_REG_TYPE | BANK_3 | 0x18) -#define ENC28J60_REG_EPAUSH (ETH_REG_TYPE | BANK_3 | 0x19) - -//PHY registers -#define ENC28J60_PHY_REG_PHCON1 (PHY_REG_TYPE | 0x00) -#define ENC28J60_PHY_REG_PHSTAT1 (PHY_REG_TYPE | 0x01) -#define ENC28J60_PHY_REG_PHID1 (PHY_REG_TYPE | 0x02) -#define ENC28J60_PHY_REG_PHID2 (PHY_REG_TYPE | 0x03) -#define ENC28J60_PHY_REG_PHCON2 (PHY_REG_TYPE | 0x10) -#define ENC28J60_PHY_REG_PHSTAT2 (PHY_REG_TYPE | 0x11) -#define ENC28J60_PHY_REG_PHIE (PHY_REG_TYPE | 0x12) -#define ENC28J60_PHY_REG_PHIR (PHY_REG_TYPE | 0x13) -#define ENC28J60_PHY_REG_PHLCON (PHY_REG_TYPE | 0x14) - -//EIE register -#define EIE_INTIE (1 << 7) -#define EIE_PKTIE (1 << 6) -#define EIE_DMAIE (1 << 5) -#define EIE_LINKIE (1 << 4) -#define EIE_TXIE (1 << 3) -#define EIE_WOLIE (1 << 2) -#define EIE_TXERIE (1 << 1) -#define EIE_RXERIE (1 << 0) - -//EIR register -#define EIR_PKTIF (1 << 6) -#define EIR_DMAIF (1 << 5) -#define EIR_LINKIF (1 << 4) -#define EIR_TXIF (1 << 3) -#define EIR_WOLIF (1 << 2) -#define EIR_TXERIF (1 << 1) -#define EIR_RXERIF (1 << 0) - -//ESTAT register -#define ESTAT_INT (1 << 7) -#define ESTAT_LATECOL (1 << 4) -#define ESTAT_RXBUSY (1 << 2) -#define ESTAT_TXABRT (1 << 1) -#define ESTAT_CLKRDY (1 << 0) - -//ECON2 register -#define ECON2_AUTOINC (1 << 7) -#define ECON2_PKTDEC (1 << 6) -#define ECON2_PWRSV (1 << 5) -#define ECON2_VRPS (1 << 3) - -//ECON1 register -#define ECON1_TXRST (1 << 7) -#define ECON1_RXRST (1 << 6) -#define ECON1_DMAST (1 << 5) -#define ECON1_CSUMEN (1 << 4) -#define ECON1_TXRTS (1 << 3) -#define ECON1_RXEN (1 << 2) -#define ECON1_BSEL1 (1 << 1) -#define ECON1_BSEL0 (1 << 0) - -//ERXFCON register -#define ERXFCON_UCEN (1 << 7) -#define ERXFCON_ANDOR (1 << 6) -#define ERXFCON_CRCEN (1 << 5) -#define ERXFCON_PMEN (1 << 4) -#define ERXFCON_MPEN (1 << 3) -#define ERXFCON_HTEN (1 << 2) -#define ERXFCON_MCEN (1 << 1) -#define ERXFCON_BCEN (1 << 0) - -//MACON1 register -#define MACON1_LOOPBK (1 << 4) -#define MACON1_TXPAUS (1 << 3) -#define MACON1_RXPAUS (1 << 2) -#define MACON1_PASSALL (1 << 1) -#define MACON1_MARXEN (1 << 0) - -//MACON2 register -#define MACON2_MARST (1 << 7) -#define MACON2_RNDRST (1 << 6) -#define MACON2_MARXRST (1 << 3) -#define MACON2_RFUNRST (1 << 2) -#define MACON2_MATXRST (1 << 1) -#define MACON2_TFUNRST (1 << 0) - -//MACON3 register -#define MACON3_PADCFG2 (1 << 7) -#define MACON3_PADCFG1 (1 << 6) -#define MACON3_PADCFG0 (1 << 5) -#define MACON3_TXCRCEN (1 << 4) -#define MACON3_PHDRLEN (1 << 3) -#define MACON3_HFRMLEN (1 << 2) -#define MACON3_FRMLNEN (1 << 1) -#define MACON3_FULDPX (1 << 0) - -#define MACON3_PADCFG(x) ((x) << 5) - -//MACON4 register -#define MACON4_DEFER (1 << 6) -#define MACON4_BPEN (1 << 5) -#define MACON4_NOBKOFF (1 << 4) -#define MACON4_LONGPRE (1 << 1) -#define MACON4_PUREPRE (1 << 0) - -//MAPHSUP register -#define MAPHSUP_RSTINTFC (1 << 7) -#define MAPHSUP_RSTRMII (1 << 3) - -//MICON register -#define MICON_RSTMII (1 << 7) - -//MICMD register -#define MICMD_MIISCAN (1 << 1) -#define MICMD_MIIRD (1 << 0) - -//EBSTCON register -#define EBSTCON_PSV2 (1 << 7) -#define EBSTCON_PSV1 (1 << 6) -#define EBSTCON_PSV0 (1 << 5) -#define EBSTCON_PSEL (1 << 4) -#define EBSTCON_TMSEL1 (1 << 3) -#define EBSTCON_TMSEL0 (1 << 2) -#define EBSTCON_TME (1 << 1) -#define EBSTCON_BISTST (1 << 0) - -//MISTAT register -#define MISTAT_NVALID (1 << 2) -#define MISTAT_SCAN (1 << 1) -#define MISTAT_BUSY (1 << 0) - -//ECOCON register -#define ECOCON_COCON2 (1 << 2) -#define ECOCON_COCON1 (1 << 1) -#define ECOCON_COCON0 (1 << 0) - -//EFLOCON register -#define EFLOCON_FULDPXS (1 << 2) -#define EFLOCON_FCEN1 (1 << 1) -#define EFLOCON_FCEN0 (1 << 0) - -//PHCON1 register -#define PHCON1_PRST (1 << 15) -#define PHCON1_PLOOPBK (1 << 14) -#define PHCON1_PPWRSV (1 << 11) -#define PHCON1_PDPXMD (1 << 8) - -//PHSTAT1 register -#define PHSTAT1_PFDPX (1 << 12) -#define PHSTAT1_PHDPX (1 << 11) -#define PHSTAT1_LLSTAT (1 << 2) -#define PHSTAT1_JBSTAT (1 << 1) - -//PHCON2 register -#define PHCON2_FRCLINK (1 << 14) -#define PHCON2_TXDIS (1 << 13) -#define PHCON2_JABBER (1 << 10) -#define PHCON2_HDLDIS (1 << 8) - -//PHSTAT2 register -#define PHSTAT2_TXSTAT (1 << 13) -#define PHSTAT2_RXSTAT (1 << 12) -#define PHSTAT2_COLSTAT (1 << 11) -#define PHSTAT2_LSTAT (1 << 10) -#define PHSTAT2_DPXSTAT (1 << 9) -#define PHSTAT2_PLRITY (1 << 4) - -//PHIE register -#define PHIE_PLNKIE (1 << 4) -#define PHIE_PGEIE (1 << 1) - -//PHIR register -#define PHIR_PLNKIF (1 << 4) -#define PHIR_PGIF (1 << 2) - -//PHLCON register -#define PHLCON_LACFG3 (1 << 11) -#define PHLCON_LACFG2 (1 << 10) -#define PHLCON_LACFG1 (1 << 9) -#define PHLCON_LACFG0 (1 << 8) -#define PHLCON_LBCFG3 (1 << 7) -#define PHLCON_LBCFG2 (1 << 6) -#define PHLCON_LBCFG1 (1 << 5) -#define PHLCON_LBCFG0 (1 << 4) -#define PHLCON_LFRQ1 (1 << 3) -#define PHLCON_LFRQ0 (1 << 2) -#define PHLCON_STRCH (1 << 1) - -#define PHLCON_LACFG(x) ((x) << 8) -#define PHLCON_LBCFG(x) ((x) << 4) -#define PHLCON_LFRQ(x) ((x) << 2) +//ENC28J60 registers +#define ENC28J60_ERDPTL (ETH_REG_TYPE | BANK_0 | 0x00) +#define ENC28J60_ERDPTH (ETH_REG_TYPE | BANK_0 | 0x01) +#define ENC28J60_EWRPTL (ETH_REG_TYPE | BANK_0 | 0x02) +#define ENC28J60_EWRPTH (ETH_REG_TYPE | BANK_0 | 0x03) +#define ENC28J60_ETXSTL (ETH_REG_TYPE | BANK_0 | 0x04) +#define ENC28J60_ETXSTH (ETH_REG_TYPE | BANK_0 | 0x05) +#define ENC28J60_ETXNDL (ETH_REG_TYPE | BANK_0 | 0x06) +#define ENC28J60_ETXNDH (ETH_REG_TYPE | BANK_0 | 0x07) +#define ENC28J60_ERXSTL (ETH_REG_TYPE | BANK_0 | 0x08) +#define ENC28J60_ERXSTH (ETH_REG_TYPE | BANK_0 | 0x09) +#define ENC28J60_ERXNDL (ETH_REG_TYPE | BANK_0 | 0x0A) +#define ENC28J60_ERXNDH (ETH_REG_TYPE | BANK_0 | 0x0B) +#define ENC28J60_ERXRDPTL (ETH_REG_TYPE | BANK_0 | 0x0C) +#define ENC28J60_ERXRDPTH (ETH_REG_TYPE | BANK_0 | 0x0D) +#define ENC28J60_ERXWRPTL (ETH_REG_TYPE | BANK_0 | 0x0E) +#define ENC28J60_ERXWRPTH (ETH_REG_TYPE | BANK_0 | 0x0F) +#define ENC28J60_EDMASTL (ETH_REG_TYPE | BANK_0 | 0x10) +#define ENC28J60_EDMASTH (ETH_REG_TYPE | BANK_0 | 0x11) +#define ENC28J60_EDMANDL (ETH_REG_TYPE | BANK_0 | 0x12) +#define ENC28J60_EDMANDH (ETH_REG_TYPE | BANK_0 | 0x13) +#define ENC28J60_EDMADSTL (ETH_REG_TYPE | BANK_0 | 0x14) +#define ENC28J60_EDMADSTH (ETH_REG_TYPE | BANK_0 | 0x15) +#define ENC28J60_EDMACSL (ETH_REG_TYPE | BANK_0 | 0x16) +#define ENC28J60_EDMACSH (ETH_REG_TYPE | BANK_0 | 0x17) +#define ENC28J60_EIE (ETH_REG_TYPE | BANK_0 | 0x1B) +#define ENC28J60_EIR (ETH_REG_TYPE | BANK_0 | 0x1C) +#define ENC28J60_ESTAT (ETH_REG_TYPE | BANK_0 | 0x1D) +#define ENC28J60_ECON2 (ETH_REG_TYPE | BANK_0 | 0x1E) +#define ENC28J60_ECON1 (ETH_REG_TYPE | BANK_0 | 0x1F) +#define ENC28J60_EHT0 (ETH_REG_TYPE | BANK_1 | 0x00) +#define ENC28J60_EHT1 (ETH_REG_TYPE | BANK_1 | 0x01) +#define ENC28J60_EHT2 (ETH_REG_TYPE | BANK_1 | 0x02) +#define ENC28J60_EHT3 (ETH_REG_TYPE | BANK_1 | 0x03) +#define ENC28J60_EHT4 (ETH_REG_TYPE | BANK_1 | 0x04) +#define ENC28J60_EHT5 (ETH_REG_TYPE | BANK_1 | 0x05) +#define ENC28J60_EHT6 (ETH_REG_TYPE | BANK_1 | 0x06) +#define ENC28J60_EHT7 (ETH_REG_TYPE | BANK_1 | 0x07) +#define ENC28J60_EPMM0 (ETH_REG_TYPE | BANK_1 | 0x08) +#define ENC28J60_EPMM1 (ETH_REG_TYPE | BANK_1 | 0x09) +#define ENC28J60_EPMM2 (ETH_REG_TYPE | BANK_1 | 0x0A) +#define ENC28J60_EPMM3 (ETH_REG_TYPE | BANK_1 | 0x0B) +#define ENC28J60_EPMM4 (ETH_REG_TYPE | BANK_1 | 0x0C) +#define ENC28J60_EPMM5 (ETH_REG_TYPE | BANK_1 | 0x0D) +#define ENC28J60_EPMM6 (ETH_REG_TYPE | BANK_1 | 0x0E) +#define ENC28J60_EPMM7 (ETH_REG_TYPE | BANK_1 | 0x0F) +#define ENC28J60_EPMCSL (ETH_REG_TYPE | BANK_1 | 0x10) +#define ENC28J60_EPMCSH (ETH_REG_TYPE | BANK_1 | 0x11) +#define ENC28J60_EPMOL (ETH_REG_TYPE | BANK_1 | 0x14) +#define ENC28J60_EPMOH (ETH_REG_TYPE | BANK_1 | 0x15) +#define ENC28J60_EWOLIE (ETH_REG_TYPE | BANK_1 | 0x16) +#define ENC28J60_EWOLIR (ETH_REG_TYPE | BANK_1 | 0x17) +#define ENC28J60_ERXFCON (ETH_REG_TYPE | BANK_1 | 0x18) +#define ENC28J60_EPKTCNT (ETH_REG_TYPE | BANK_1 | 0x19) +#define ENC28J60_MACON1 (MAC_REG_TYPE | BANK_2 | 0x00) +#define ENC28J60_MACON2 (MAC_REG_TYPE | BANK_2 | 0x01) +#define ENC28J60_MACON3 (MAC_REG_TYPE | BANK_2 | 0x02) +#define ENC28J60_MACON4 (MAC_REG_TYPE | BANK_2 | 0x03) +#define ENC28J60_MABBIPG (MAC_REG_TYPE | BANK_2 | 0x04) +#define ENC28J60_MAIPGL (MAC_REG_TYPE | BANK_2 | 0x06) +#define ENC28J60_MAIPGH (MAC_REG_TYPE | BANK_2 | 0x07) +#define ENC28J60_MACLCON1 (MAC_REG_TYPE | BANK_2 | 0x08) +#define ENC28J60_MACLCON2 (MAC_REG_TYPE | BANK_2 | 0x09) +#define ENC28J60_MAMXFLL (MAC_REG_TYPE | BANK_2 | 0x0A) +#define ENC28J60_MAMXFLH (MAC_REG_TYPE | BANK_2 | 0x0B) +#define ENC28J60_MAPHSUP (MAC_REG_TYPE | BANK_2 | 0x0D) +#define ENC28J60_MICON (MII_REG_TYPE | BANK_2 | 0x11) +#define ENC28J60_MICMD (MII_REG_TYPE | BANK_2 | 0x12) +#define ENC28J60_MIREGADR (MII_REG_TYPE | BANK_2 | 0x14) +#define ENC28J60_MIWRL (MII_REG_TYPE | BANK_2 | 0x16) +#define ENC28J60_MIWRH (MII_REG_TYPE | BANK_2 | 0x17) +#define ENC28J60_MIRDL (MII_REG_TYPE | BANK_2 | 0x18) +#define ENC28J60_MIRDH (MII_REG_TYPE | BANK_2 | 0x19) +#define ENC28J60_MAADR1 (MAC_REG_TYPE | BANK_3 | 0x00) +#define ENC28J60_MAADR0 (MAC_REG_TYPE | BANK_3 | 0x01) +#define ENC28J60_MAADR3 (MAC_REG_TYPE | BANK_3 | 0x02) +#define ENC28J60_MAADR2 (MAC_REG_TYPE | BANK_3 | 0x03) +#define ENC28J60_MAADR5 (MAC_REG_TYPE | BANK_3 | 0x04) +#define ENC28J60_MAADR4 (MAC_REG_TYPE | BANK_3 | 0x05) +#define ENC28J60_EBSTSD (ETH_REG_TYPE | BANK_3 | 0x06) +#define ENC28J60_EBSTCON (ETH_REG_TYPE | BANK_3 | 0x07) +#define ENC28J60_EBSTCSL (ETH_REG_TYPE | BANK_3 | 0x08) +#define ENC28J60_EBSTCSH (ETH_REG_TYPE | BANK_3 | 0x09) +#define ENC28J60_MISTAT (MII_REG_TYPE | BANK_3 | 0x0A) +#define ENC28J60_EREVID (ETH_REG_TYPE | BANK_3 | 0x12) +#define ENC28J60_ECOCON (ETH_REG_TYPE | BANK_3 | 0x15) +#define ENC28J60_EFLOCON (ETH_REG_TYPE | BANK_3 | 0x17) +#define ENC28J60_EPAUSL (ETH_REG_TYPE | BANK_3 | 0x18) +#define ENC28J60_EPAUSH (ETH_REG_TYPE | BANK_3 | 0x19) + +//ENC28J60 PHY registers +#define ENC28J60_PHCON1 (PHY_REG_TYPE | 0x00) +#define ENC28J60_PHSTAT1 (PHY_REG_TYPE | 0x01) +#define ENC28J60_PHID1 (PHY_REG_TYPE | 0x02) +#define ENC28J60_PHID2 (PHY_REG_TYPE | 0x03) +#define ENC28J60_PHCON2 (PHY_REG_TYPE | 0x10) +#define ENC28J60_PHSTAT2 (PHY_REG_TYPE | 0x11) +#define ENC28J60_PHIE (PHY_REG_TYPE | 0x12) +#define ENC28J60_PHIR (PHY_REG_TYPE | 0x13) +#define ENC28J60_PHLCON (PHY_REG_TYPE | 0x14) + +//Ethernet Interrupt Enable register +#define ENC28J60_EIE_INTIE 0x80 +#define ENC28J60_EIE_PKTIE 0x40 +#define ENC28J60_EIE_DMAIE 0x20 +#define ENC28J60_EIE_LINKIE 0x10 +#define ENC28J60_EIE_TXIE 0x08 +#define ENC28J60_EIE_WOLIE 0x04 +#define ENC28J60_EIE_TXERIE 0x02 +#define ENC28J60_EIE_RXERIE 0x01 + +//Ethernet Interrupt Request register +#define ENC28J60_EIR_PKTIF 0x40 +#define ENC28J60_EIR_DMAIF 0x20 +#define ENC28J60_EIR_LINKIF 0x10 +#define ENC28J60_EIR_TXIF 0x08 +#define ENC28J60_EIR_WOLIF 0x04 +#define ENC28J60_EIR_TXERIF 0x02 +#define ENC28J60_EIR_RXERIF 0x01 + +//Ethernet Status register +#define ENC28J60_ESTAT_INT 0x80 +#define ENC28J60_ESTAT_R6 0x40 +#define ENC28J60_ESTAT_R5 0x20 +#define ENC28J60_ESTAT_LATECOL 0x10 +#define ENC28J60_ESTAT_RXBUSY 0x04 +#define ENC28J60_ESTAT_TXABRT 0x02 +#define ENC28J60_ESTAT_CLKRDY 0x01 + +//Ethernet Control 2 register +#define ENC28J60_ECON2_AUTOINC 0x80 +#define ENC28J60_ECON2_PKTDEC 0x40 +#define ENC28J60_ECON2_PWRSV 0x20 +#define ENC28J60_ECON2_VRPS 0x08 + +//Ethernet Control 1 register +#define ENC28J60_ECON1_TXRST 0x80 +#define ENC28J60_ECON1_RXRST 0x40 +#define ENC28J60_ECON1_DMAST 0x20 +#define ENC28J60_ECON1_CSUMEN 0x10 +#define ENC28J60_ECON1_TXRTS 0x08 +#define ENC28J60_ECON1_RXEN 0x04 +#define ENC28J60_ECON1_BSEL1 0x02 +#define ENC28J60_ECON1_BSEL0 0x01 + +//Ethernet Wake-Up On LAN Interrupt Enable register +#define ENC28J60_EWOLIE_UCWOLIE 0x80 +#define ENC28J60_EWOLIE_AWOLIE 0x40 +#define ENC28J60_EWOLIE_PMWOLIE 0x10 +#define ENC28J60_EWOLIE_MPWOLIE 0x08 +#define ENC28J60_EWOLIE_HTWOLIE 0x04 +#define ENC28J60_EWOLIE_MCWOLIE 0x02 +#define ENC28J60_EWOLIE_BCWOLIE 0x01 + +//Ethernet Wake-Up On LAN Interrupt Request register +#define ENC28J60_EWOLIR_UCWOLIF 0x80 +#define ENC28J60_EWOLIR_AWOLIF 0x40 +#define ENC28J60_EWOLIR_PMWOLIF 0x10 +#define ENC28J60_EWOLIR_MPWOLIF 0x08 +#define ENC28J60_EWOLIR_HTWOLIF 0x04 +#define ENC28J60_EWOLIR_MCWOLIF 0x02 +#define ENC28J60_EWOLIR_BCWOLIF 0x01 + +//Receive Filter Control register +#define ENC28J60_ERXFCON_UCEN 0x80 +#define ENC28J60_ERXFCON_ANDOR 0x40 +#define ENC28J60_ERXFCON_CRCEN 0x20 +#define ENC28J60_ERXFCON_PMEN 0x10 +#define ENC28J60_ERXFCON_MPEN 0x08 +#define ENC28J60_ERXFCON_HTEN 0x04 +#define ENC28J60_ERXFCON_MCEN 0x02 +#define ENC28J60_ERXFCON_BCEN 0x01 + +//MAC Control 1 register +#define ENC28J60_MACON1_LOOPBK 0x10 +#define ENC28J60_MACON1_TXPAUS 0x08 +#define ENC28J60_MACON1_RXPAUS 0x04 +#define ENC28J60_MACON1_PASSALL 0x02 +#define ENC28J60_MACON1_MARXEN 0x01 + +//MAC Control 2 register +#define ENC28J60_MACON2_MARST 0x80 +#define ENC28J60_MACON2_RNDRST 0x40 +#define ENC28J60_MACON2_MARXRST 0x08 +#define ENC28J60_MACON2_RFUNRST 0x04 +#define ENC28J60_MACON2_MATXRST 0x02 +#define ENC28J60_MACON2_TFUNRST 0x01 + +//MAC Control 3 register +#define ENC28J60_MACON3_PADCFG 0xE0 +#define ENC28J60_MACON3_PADCFG_NO 0x00 +#define ENC28J60_MACON3_PADCFG_60_BYTES 0x20 +#define ENC28J60_MACON3_PADCFG_64_BYTES 0x60 +#define ENC28J60_MACON3_PADCFG_AUTO 0xA0 +#define ENC28J60_MACON3_TXCRCEN 0x10 +#define ENC28J60_MACON3_PHDRLEN 0x08 +#define ENC28J60_MACON3_HFRMEN 0x04 +#define ENC28J60_MACON3_FRMLNEN 0x02 +#define ENC28J60_MACON3_FULDPX 0x01 + +//MAC Control 4 register +#define ENC28J60_MACON4_DEFER 0x40 +#define ENC28J60_MACON4_BPEN 0x20 +#define ENC28J60_MACON4_NOBKOFF 0x10 +#define ENC28J60_MACON4_LONGPRE 0x02 +#define ENC28J60_MACON4_PUREPRE 0x01 + +//Back-to-Back Inter-Packet Gap register +#define ENC28J60_MABBIPG_DEFAULT_HD 0x12 +#define ENC28J60_MABBIPG_DEFAULT_FD 0x15 + +//Non-Back-to-Back Inter-Packet Gap Low Byte register +#define ENC28J60_MAIPGL_DEFAULT 0x12 + +//Non-Back-to-Back Inter-Packet Gap High Byte register +#define ENC28J60_MAIPGH_DEFAULT 0x0C + +//Retransmission Maximum register +#define ENC28J60_MACLCON1_RETMAX 0x0F + +//Collision Window register +#define ENC28J60_MACLCON2_COLWIN 0x3F +#define ENC28J60_MACLCON2_COLWIN_DEFAULT 0x37 + +//MAC-PHY Support register +#define ENC28J60_MAPHSUP_RSTINTFC 0x80 +#define ENC28J60_MAPHSUP_R4 0x10 +#define ENC28J60_MAPHSUP_RSTRMII 0x08 +#define ENC28J60_MAPHSUP_R0 0x01 + +//MII Control register +#define ENC28J60_MICON_RSTMII 0x80 + +//MII Command register +#define ENC28J60_MICMD_MIISCAN 0x02 +#define ENC28J60_MICMD_MIIRD 0x01 + +//MII Register Addres register +#define ENC28J60_MIREGADR_VAL 0x1F + +//Self-Test Control register +#define ENC28J60_EBSTCON_PSV 0xE0 +#define ENC28J60_EBSTCON_PSEL 0x10 +#define ENC28J60_EBSTCON_TMSEL 0x0C +#define ENC28J60_EBSTCON_TMSEL_RANDOM 0x00 +#define ENC28J60_EBSTCON_TMSEL_ADDR 0x04 +#define ENC28J60_EBSTCON_TMSEL_PATTERN_SHIFT 0x08 +#define ENC28J60_EBSTCON_TMSEL_RACE_MODE 0x0C +#define ENC28J60_EBSTCON_TME 0x02 +#define ENC28J60_EBSTCON_BISTST 0x01 + +//MII Status register +#define ENC28J60_MISTAT_R3 0x08 +#define ENC28J60_MISTAT_NVALID 0x04 +#define ENC28J60_MISTAT_SCAN 0x02 +#define ENC28J60_MISTAT_BUSY 0x01 + +//Ethernet Revision ID register +#define ENC28J60_EREVID_REV 0x1F +#define ENC28J60_EREVID_REV_B1 0x02 +#define ENC28J60_EREVID_REV_B4 0x04 +#define ENC28J60_EREVID_REV_B5 0x05 +#define ENC28J60_EREVID_REV_B7 0x06 + +//Clock Output Control register +#define ENC28J60_ECOCON_COCON 0x07 +#define ENC28J60_ECOCON_COCON_DISABLED 0x00 +#define ENC28J60_ECOCON_COCON_DIV1 0x01 +#define ENC28J60_ECOCON_COCON_DIV2 0x02 +#define ENC28J60_ECOCON_COCON_DIV3 0x03 +#define ENC28J60_ECOCON_COCON_DIV4 0x04 +#define ENC28J60_ECOCON_COCON_DIV8 0x05 + +//Ethernet Flow Control register +#define ENC28J60_EFLOCON_FULDPXS 0x04 +#define ENC28J60_EFLOCON_FCEN 0x03 +#define ENC28J60_EFLOCON_FCEN_OFF 0x00 +#define ENC28J60_EFLOCON_FCEN_ON_HD 0x01 +#define ENC28J60_EFLOCON_FCEN_ON_FD 0x02 +#define ENC28J60_EFLOCON_FCEN_SEND_PAUSE 0x03 + +//PHY Control 1 register +#define ENC28J60_PHCON1_PRST 0x8000 +#define ENC28J60_PHCON1_PLOOPBK 0x4000 +#define ENC28J60_PHCON1_PPWRSV 0x0800 +#define ENC28J60_PHCON1_PDPXMD 0x0100 + +//Physical Layer Status 1 register +#define ENC28J60_PHSTAT1_PFDPX 0x1000 +#define ENC28J60_PHSTAT1_PHDPX 0x0800 +#define ENC28J60_PHSTAT1_LLSTAT 0x0004 +#define ENC28J60_PHSTAT1_JBRSTAT 0x0002 + +//PHY Identifier 1 register +#define ENC28J60_PHID1_PIDH 0xFFFF +#define ENC28J60_PHID1_PIDH_DEFAULT 0x0083 + +//PHY Identifier 2 register +#define ENC28J60_PHID2_PIDL 0xFC00 +#define ENC28J60_PHID2_PIDL_DEFAULT 0x1400 +#define ENC28J60_PHID2_PPN 0x03F0 +#define ENC28J60_PHID2_PPN_DEFAULT 0x0000 +#define ENC28J60_PHID2_PREV 0x000F + +//PHY Control 2 register +#define ENC28J60_PHCON2_FRCLNK 0x4000 +#define ENC28J60_PHCON2_TXDIS 0x2000 +#define ENC28J60_PHCON2_JABBER 0x0400 +#define ENC28J60_PHCON2_HDLDIS 0x0100 + +//Physical Layer Status 2 register +#define ENC28J60_PHSTAT2_TXSTAT 0x2000 +#define ENC28J60_PHSTAT2_RXSTAT 0x1000 +#define ENC28J60_PHSTAT2_COLSTAT 0x0800 +#define ENC28J60_PHSTAT2_LSTAT 0x0400 +#define ENC28J60_PHSTAT2_DPXSTAT 0x0200 +#define ENC28J60_PHSTAT2_PLRITY 0x0010 + +//PHY Interrupt Enable register +#define ENC28J60_PHIE_PLNKIE 0x0010 +#define ENC28J60_PHIE_PGEIE 0x0002 + +//PHY Interrupt Request register +#define ENC28J60_PHIR_PLNKIF 0x0010 +#define ENC28J60_PHIR_PGIF 0x0004 + +//PHY Module LED Control register +#define ENC28J60_PHLCON_LACFG 0x0F00 +#define ENC28J60_PHLCON_LACFG_TX 0x0100 +#define ENC28J60_PHLCON_LACFG_RX 0x0200 +#define ENC28J60_PHLCON_LACFG_COL 0x0300 +#define ENC28J60_PHLCON_LACFG_LINK 0x0400 +#define ENC28J60_PHLCON_LACFG_DUPLEX 0x0500 +#define ENC28J60_PHLCON_LACFG_TX_RX 0x0700 +#define ENC28J60_PHLCON_LACFG_ON 0x0800 +#define ENC28J60_PHLCON_LACFG_OFF 0x0900 +#define ENC28J60_PHLCON_LACFG_BLINK_FAST 0x0A00 +#define ENC28J60_PHLCON_LACFG_BLINK_SLOW 0x0B00 +#define ENC28J60_PHLCON_LACFG_LINK_RX 0x0C00 +#define ENC28J60_PHLCON_LACFG_LINK_TX_RX 0x0D00 +#define ENC28J60_PHLCON_LACFG_DUPLEX_COL 0x0E00 +#define ENC28J60_PHLCON_LBCFG 0x00F0 +#define ENC28J60_PHLCON_LBCFG_TX 0x0010 +#define ENC28J60_PHLCON_LBCFG_RX 0x0020 +#define ENC28J60_PHLCON_LBCFG_COL 0x0030 +#define ENC28J60_PHLCON_LBCFG_LINK 0x0040 +#define ENC28J60_PHLCON_LBCFG_DUPLEX 0x0050 +#define ENC28J60_PHLCON_LBCFG_TX_RX 0x0070 +#define ENC28J60_PHLCON_LBCFG_ON 0x0080 +#define ENC28J60_PHLCON_LBCFG_OFF 0x0090 +#define ENC28J60_PHLCON_LBCFG_BLINK_FAST 0x00A0 +#define ENC28J60_PHLCON_LBCFG_BLINK_SLOW 0x00B0 +#define ENC28J60_PHLCON_LBCFG_LINK_RX 0x00C0 +#define ENC28J60_PHLCON_LBCFG_LINK_TX_RX 0x00D0 +#define ENC28J60_PHLCON_LBCFG_DUPLEX_COL 0x00E0 +#define ENC28J60_PHLCON_LFRQ 0x000C +#define ENC28J60_PHLCON_LFRQ_40_MS 0x0000 +#define ENC28J60_PHLCON_LFRQ_73_MS 0x0004 +#define ENC28J60_PHLCON_LFRQ_139_MS 0x0008 +#define ENC28J60_PHLCON_STRCH 0x0002 //Per-packet control byte -#define TX_CTRL_PHUGEEN (1 << 3) -#define TX_CTRL_PPADEN (1 << 2) -#define TX_CTRL_PCRCEN (1 << 1) -#define TX_CTRL_POVERRIDE (1 << 0) +#define ENC28J60_TX_CTRL_PHUGEEN 0x08 +#define ENC28J60_TX_CTRL_PPADEN 0x04 +#define ENC28J60_TX_CTRL_PCRCEN 0x02 +#define ENC28J60_TX_CTRL_POVERRIDE 0x01 //Receive status vector -#define RSV_VLAN_TYPE 0x4000 -#define RSV_UNKNOWN_OPCODE 0x2000 -#define RSV_PAUSE_CONTROL_FRAME 0x1000 -#define RSV_CONTROL_FRAME 0x0800 -#define RSV_DRIBBLE_NIBBLE 0x0400 -#define RSV_BROADCAST_PACKET 0x0200 -#define RSV_MULTICAST_PACKET 0x0100 -#define RSV_RECEIVED_OK 0x0080 -#define RSV_LENGTH_OUT_OF_RANGE 0x0040 -#define RSV_LENGTH_CHECK_ERROR 0x0020 -#define RSV_CRC_ERROR 0x0010 -#define RSV_CARRIER_EVENT 0x0004 -#define RSV_DROP_EVENT 0x0001 +#define ENC28J60_RSV_VLAN_TYPE 0x4000 +#define ENC28J60_RSV_UNKNOWN_OPCODE 0x2000 +#define ENC28J60_RSV_PAUSE_CONTROL_FRAME 0x1000 +#define ENC28J60_RSV_CONTROL_FRAME 0x0800 +#define ENC28J60_RSV_DRIBBLE_NIBBLE 0x0400 +#define ENC28J60_RSV_BROADCAST_PACKET 0x0200 +#define ENC28J60_RSV_MULTICAST_PACKET 0x0100 +#define ENC28J60_RSV_RECEIVED_OK 0x0080 +#define ENC28J60_RSV_LENGTH_OUT_OF_RANGE 0x0040 +#define ENC28J60_RSV_LENGTH_CHECK_ERROR 0x0020 +#define ENC28J60_RSV_CRC_ERROR 0x0010 +#define ENC28J60_RSV_CARRIER_EVENT 0x0004 +#define ENC28J60_RSV_DROP_EVENT 0x0001 //C++ guard #ifdef __cplusplus diff --git a/drivers/eth/enc624j600_driver.c b/drivers/eth/enc624j600_driver.c index 0ee98001..f124adc7 100644 --- a/drivers/eth/enc624j600_driver.c +++ b/drivers/eth/enc624j600_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -99,17 +99,18 @@ error_t enc624j600Init(NetInterface *interface) enc624j600SoftReset(interface); //Disable CLKOUT output - enc624j600WriteReg(interface, ENC624J600_REG_ECON2, ECON2_ETHEN | ECON2_STRCH); + enc624j600WriteReg(interface, ENC624J600_ECON2, ENC624J600_ECON2_ETHEN | + ENC624J600_ECON2_STRCH); //Optionally set the station MAC address if(macCompAddr(&interface->macAddr, &MAC_UNSPECIFIED_ADDR)) { //Use the factory preprogrammed station address - temp = enc624j600ReadReg(interface, ENC624J600_REG_MAADR1); + temp = enc624j600ReadReg(interface, ENC624J600_MAADR1); interface->macAddr.w[0] = letoh16(temp); - temp = enc624j600ReadReg(interface, ENC624J600_REG_MAADR2); + temp = enc624j600ReadReg(interface, ENC624J600_MAADR2); interface->macAddr.w[1] = letoh16(temp); - temp = enc624j600ReadReg(interface, ENC624J600_REG_MAADR3); + temp = enc624j600ReadReg(interface, ENC624J600_MAADR3); interface->macAddr.w[2] = letoh16(temp); //Generate the 64-bit interface identifier @@ -119,48 +120,53 @@ error_t enc624j600Init(NetInterface *interface) { //Override the factory preprogrammed address temp = htole16(interface->macAddr.w[0]); - enc624j600WriteReg(interface, ENC624J600_REG_MAADR1, temp); + enc624j600WriteReg(interface, ENC624J600_MAADR1, temp); temp = htole16(interface->macAddr.w[1]); - enc624j600WriteReg(interface, ENC624J600_REG_MAADR2, temp); + enc624j600WriteReg(interface, ENC624J600_MAADR2, temp); temp = htole16(interface->macAddr.w[2]); - enc624j600WriteReg(interface, ENC624J600_REG_MAADR3, temp); + enc624j600WriteReg(interface, ENC624J600_MAADR3, temp); } //Set receive buffer location - enc624j600WriteReg(interface, ENC624J600_REG_ERXST, ENC624J600_RX_BUFFER_START); + enc624j600WriteReg(interface, ENC624J600_ERXST, ENC624J600_RX_BUFFER_START); //Program the tail pointer ERXTAIL to the last even address of the buffer - enc624j600WriteReg(interface, ENC624J600_REG_ERXTAIL, ENC624J600_RX_BUFFER_STOP); + enc624j600WriteReg(interface, ENC624J600_ERXTAIL, ENC624J600_RX_BUFFER_STOP); //Configure the receive filters - enc624j600WriteReg(interface, ENC624J600_REG_ERXFCON, ERXFCON_HTEN | - ERXFCON_CRCEN | ERXFCON_RUNTEN | ERXFCON_UCEN | ERXFCON_BCEN); + enc624j600WriteReg(interface, ENC624J600_ERXFCON, ENC624J600_ERXFCON_HTEN | + ENC624J600_ERXFCON_CRCEN | ENC624J600_ERXFCON_RUNTEN | + ENC624J600_ERXFCON_UCEN | ENC624J600_ERXFCON_BCEN); //Initialize the hash table - enc624j600WriteReg(interface, ENC624J600_REG_EHT1, 0x0000); - enc624j600WriteReg(interface, ENC624J600_REG_EHT2, 0x0000); - enc624j600WriteReg(interface, ENC624J600_REG_EHT3, 0x0000); - enc624j600WriteReg(interface, ENC624J600_REG_EHT4, 0x0000); + enc624j600WriteReg(interface, ENC624J600_EHT1, 0x0000); + enc624j600WriteReg(interface, ENC624J600_EHT2, 0x0000); + enc624j600WriteReg(interface, ENC624J600_EHT3, 0x0000); + enc624j600WriteReg(interface, ENC624J600_EHT4, 0x0000); - //All short frames will be zero-padded to 60 bytes and a valid CRC is then appended - enc624j600WriteReg(interface, ENC624J600_REG_MACON2, - MACON2_DEFER | MACON2_PADCFG0 | MACON2_TXCRCEN | MACON2_R1); + //All short frames will be zero-padded to 60 bytes and a valid CRC is then + //appended + enc624j600WriteReg(interface, ENC624J600_MACON2, ENC624J600_MACON2_DEFER | + ENC624J600_MACON2_PADCFG_AUTO | ENC624J600_MACON2_TXCRCEN | + ENC624J600_MACON2_R1_DEFAULT); //Program the MAMXFL register with the maximum frame length to be accepted - enc624j600WriteReg(interface, ENC624J600_REG_MAMXFL, ETH_MAX_FRAME_SIZE); + enc624j600WriteReg(interface, ENC624J600_MAMXFL, ETH_MAX_FRAME_SIZE); //PHY initialization - enc624j600WritePhyReg(interface, ENC624J600_PHY_REG_PHANA, PHANA_ADPAUS0 | - PHANA_AD100FD | PHANA_AD100 | PHANA_AD10FD | PHANA_AD10 | PHANA_ADIEEE0); + enc624j600WritePhyReg(interface, ENC624J600_PHANA, ENC624J600_PHANA_ADPAUS0 | + ENC624J600_PHANA_AD100FD | ENC624J600_PHANA_AD100 | ENC624J600_PHANA_AD10FD | + ENC624J600_PHANA_AD10 | ENC624J600_PHANA_ADIEEE_DEFAULT); //Clear interrupt flags - enc624j600WriteReg(interface, ENC624J600_REG_EIR, 0x0000); + enc624j600WriteReg(interface, ENC624J600_EIR, 0x0000); //Configure interrupts as desired - enc624j600WriteReg(interface, ENC624J600_REG_EIE, EIE_INTIE | - EIE_LINKIE | EIE_PKTIE | EIE_TXIE | EIE_TXABTIE); + enc624j600WriteReg(interface, ENC624J600_EIE, ENC624J600_EIE_INTIE | + ENC624J600_EIE_LINKIE | ENC624J600_EIE_PKTIE | ENC624J600_EIE_TXIE | + ENC624J600_EIE_TXABTIE); //Set RXEN to enable reception - enc624j600SetBit(interface, ENC624J600_REG_ECON1, ECON1_RXEN); + enc624j600SetBit(interface, ENC624J600_ECON1, ENC624J600_ECON1_RXEN); //Dump registers for debugging purpose enc624j600DumpReg(interface); @@ -228,16 +234,16 @@ bool_t enc624j600IrqHandler(NetInterface *interface) flag = FALSE; //Clear the INTIE bit, immediately after an interrupt event - enc624j600ClearBit(interface, ENC624J600_REG_EIE, EIE_INTIE); + enc624j600ClearBit(interface, ENC624J600_EIE, ENC624J600_EIE_INTIE); //Read interrupt status register - status = enc624j600ReadReg(interface, ENC624J600_REG_EIR); + status = enc624j600ReadReg(interface, ENC624J600_EIR); //Link status change? - if((status & EIR_LINKIF) != 0) + if((status & ENC624J600_EIR_LINKIF) != 0) { //Disable LINKIE interrupt - enc624j600ClearBit(interface, ENC624J600_REG_EIE, EIE_LINKIE); + enc624j600ClearBit(interface, ENC624J600_EIE, ENC624J600_EIE_LINKIE); //Set event flag interface->nicEvent = TRUE; @@ -246,10 +252,10 @@ bool_t enc624j600IrqHandler(NetInterface *interface) } //Packet received? - if((status & EIR_PKTIF) != 0) + if((status & ENC624J600_EIR_PKTIF) != 0) { //Disable PKTIE interrupt - enc624j600ClearBit(interface, ENC624J600_REG_EIE, EIE_PKTIE); + enc624j600ClearBit(interface, ENC624J600_EIE, ENC624J600_EIE_PKTIE); //Set event flag interface->nicEvent = TRUE; @@ -258,10 +264,11 @@ bool_t enc624j600IrqHandler(NetInterface *interface) } //Packet transmission complete? - if((status & (EIR_TXIF | EIR_TXABTIF)) != 0) + if((status & (ENC624J600_EIR_TXIF | ENC624J600_EIR_TXABTIF)) != 0) { //Clear interrupt flags - enc624j600ClearBit(interface, ENC624J600_REG_EIR, EIR_TXIF | EIR_TXABTIF); + enc624j600ClearBit(interface, ENC624J600_EIR, ENC624J600_EIR_TXIF | + ENC624J600_EIR_TXABTIF); //Notify the TCP/IP stack that the transmitter is ready to send flag |= osSetEventFromIsr(&interface->nicTxEvent); @@ -269,7 +276,7 @@ bool_t enc624j600IrqHandler(NetInterface *interface) //Once the interrupt has been serviced, the INTIE bit //is set again to re-enable interrupts - enc624j600SetBit(interface, ENC624J600_REG_EIE, EIE_INTIE); + enc624j600SetBit(interface, ENC624J600_EIE, ENC624J600_EIE_INTIE); //A higher priority task must be woken? return flag; @@ -288,24 +295,24 @@ void enc624j600EventHandler(NetInterface *interface) uint16_t value; //Read interrupt status register - status = enc624j600ReadReg(interface, ENC624J600_REG_EIR); + status = enc624j600ReadReg(interface, ENC624J600_EIR); //Check whether the link state has changed - if((status & EIR_LINKIF) != 0) + if((status & ENC624J600_EIR_LINKIF) != 0) { //Clear interrupt flag - enc624j600ClearBit(interface, ENC624J600_REG_EIR, EIR_LINKIF); + enc624j600ClearBit(interface, ENC624J600_EIR, ENC624J600_EIR_LINKIF); //Read Ethernet status register - value = enc624j600ReadReg(interface, ENC624J600_REG_ESTAT); + value = enc624j600ReadReg(interface, ENC624J600_ESTAT); //Check link state - if((value & ESTAT_PHYLNK) != 0) + if((value & ENC624J600_ESTAT_PHYLNK) != 0) { //Read PHY status register 3 - value = enc624j600ReadPhyReg(interface, ENC624J600_PHY_REG_PHSTAT3); + value = enc624j600ReadPhyReg(interface, ENC624J600_PHSTAT3); //Get current speed - if((value & PHSTAT3_SPDDPX1) != 0) + if((value & ENC624J600_PHSTAT3_SPDDPX1) != 0) { interface->linkSpeed = NIC_LINK_SPEED_100MBPS; } @@ -315,7 +322,7 @@ void enc624j600EventHandler(NetInterface *interface) } //Determine the new duplex mode - if((value & PHSTAT3_SPDDPX2) != 0) + if((value & ENC624J600_PHSTAT3_SPDDPX2) != 0) { interface->duplexMode = NIC_FULL_DUPLEX_MODE; } @@ -341,10 +348,10 @@ void enc624j600EventHandler(NetInterface *interface) } //Check whether a packet has been received? - if((status & EIR_PKTIF) != 0) + if((status & ENC624J600_EIR_PKTIF) != 0) { //Clear interrupt flag - enc624j600ClearBit(interface, ENC624J600_REG_EIR, EIR_PKTIF); + enc624j600ClearBit(interface, ENC624J600_EIR, ENC624J600_EIR_PKTIF); //Process all pending packets do @@ -357,7 +364,8 @@ void enc624j600EventHandler(NetInterface *interface) } //Re-enable LINKIE and PKTIE interrupts - enc624j600SetBit(interface, ENC624J600_REG_EIE, EIE_LINKIE | EIE_PKTIE); + enc624j600SetBit(interface, ENC624J600_EIE, ENC624J600_EIE_LINKIE | + ENC624J600_EIE_PKTIE); } @@ -398,25 +406,27 @@ error_t enc624j600SendPacket(NetInterface *interface, } //Ensure that the transmitter is ready to send - if(enc624j600ReadReg(interface, ENC624J600_REG_ECON1) & ECON1_TXRTS) + if(enc624j600ReadReg(interface, ENC624J600_ECON1) & ENC624J600_ECON1_TXRTS) { return ERROR_FAILURE; } //Point to the SRAM buffer - enc624j600WriteReg(interface, ENC624J600_REG_EGPWRPT, ENC624J600_TX_BUFFER_START); + enc624j600WriteReg(interface, ENC624J600_EGPWRPT, ENC624J600_TX_BUFFER_START); //Copy the packet to the SRAM buffer enc624j600WriteBuffer(interface, ENC624J600_CMD_WGPDATA, buffer, offset); //Program ETXST to the start address of the packet - enc624j600WriteReg(interface, ENC624J600_REG_ETXST, ENC624J600_TX_BUFFER_START); + enc624j600WriteReg(interface, ENC624J600_ETXST, ENC624J600_TX_BUFFER_START); //Program ETXLEN with the length of data copied to the memory - enc624j600WriteReg(interface, ENC624J600_REG_ETXLEN, length); + enc624j600WriteReg(interface, ENC624J600_ETXLEN, length); //Clear TXIF and TXABTIF interrupt flags - enc624j600ClearBit(interface, ENC624J600_REG_EIR, EIR_TXIF | EIR_TXABTIF); + enc624j600ClearBit(interface, ENC624J600_EIR, ENC624J600_EIR_TXIF | + ENC624J600_EIR_TXABTIF); + //Set the TXRTS bit to initiate transmission - enc624j600SetBit(interface, ENC624J600_REG_ECON1, ECON1_TXRTS); + enc624j600SetBit(interface, ENC624J600_ECON1, ENC624J600_ECON1_TXRTS); //Successful processing return NO_ERROR; @@ -432,47 +442,40 @@ error_t enc624j600SendPacket(NetInterface *interface, error_t enc624j600ReceivePacket(NetInterface *interface) { error_t error; - uint16_t n; + uint16_t length; uint32_t status; + uint8_t header[8]; Enc624j600Context *context; //Point to the driver context context = (Enc624j600Context *) interface->nicContext; //Verify that a packet is waiting by ensuring that PKTCNT is non-zero - if(enc624j600ReadReg(interface, ENC624J600_REG_ESTAT) & ESTAT_PKTCNT) + if(enc624j600ReadReg(interface, ENC624J600_ESTAT) & ENC624J600_ESTAT_PKTCNT) { //Point to the next packet - enc624j600WriteReg(interface, ENC624J600_REG_ERXRDPT, context->nextPacket); - - //Read the first two bytes, which are the address of the next packet - enc624j600ReadBuffer(interface, ENC624J600_CMD_RRXDATA, - (uint8_t *) &context->nextPacket, sizeof(uint16_t)); - - //Convert the value to host byte order - context->nextPacket = letoh16(context->nextPacket); - - //Get the length of the received frame in bytes - enc624j600ReadBuffer(interface, ENC624J600_CMD_RRXDATA, - (uint8_t *) &n, sizeof(uint16_t)); - - //Convert the value to host byte order - n = letoh16(n); + enc624j600WriteReg(interface, ENC624J600_ERXRDPT, context->nextPacket); - //Read the receive status vector (RSV) - enc624j600ReadBuffer(interface, ENC624J600_CMD_RRXDATA, - (uint8_t *) &status, sizeof(uint32_t)); + //The packet is preceded by a 8-byte header + enc624j600ReadBuffer(interface, ENC624J600_CMD_RRXDATA, header, sizeof(header)); - //Convert the value to host byte order - status = letoh32(status); + //The first two bytes are the address of the next packet + context->nextPacket = LOAD16LE(header); + //Get the length of the received packet + length = LOAD16LE(header + 2); + //Get the receive status vector (RSV) + status = LOAD32LE(header + 4); //Make sure no error occurred - if((status & RSV_RECEIVED_OK) != 0) + if((status & ENC624J600_RSV_RECEIVED_OK) != 0) { //Limit the number of data to read - n = MIN(n, ETH_MAX_FRAME_SIZE); + length = MIN(length, ETH_MAX_FRAME_SIZE); + //Read the Ethernet frame - enc624j600ReadBuffer(interface, ENC624J600_CMD_RRXDATA, context->rxBuffer, n); + enc624j600ReadBuffer(interface, ENC624J600_CMD_RRXDATA, + context->rxBuffer, length); + //Valid packet received error = NO_ERROR; } @@ -487,15 +490,17 @@ error_t enc624j600ReceivePacket(NetInterface *interface) //received memory buffer if(context->nextPacket == ENC624J600_RX_BUFFER_START) { - enc624j600WriteReg(interface, ENC624J600_REG_ERXTAIL, ENC624J600_RX_BUFFER_STOP); + enc624j600WriteReg(interface, ENC624J600_ERXTAIL, + ENC624J600_RX_BUFFER_STOP); } else { - enc624j600WriteReg(interface, ENC624J600_REG_ERXTAIL, context->nextPacket - 2); + enc624j600WriteReg(interface, ENC624J600_ERXTAIL, + context->nextPacket - 2); } //Set PKTDEC to decrement the PKTCNT bits - enc624j600SetBit(interface, ENC624J600_REG_ECON1, ECON1_PKTDEC); + enc624j600SetBit(interface, ENC624J600_ECON1, ENC624J600_ECON1_PKTDEC); } else { @@ -512,7 +517,7 @@ error_t enc624j600ReceivePacket(NetInterface *interface) ancillary = NET_DEFAULT_RX_ANCILLARY; //Pass the packet to the upper layer - nicProcessPacket(interface, context->rxBuffer, n, &ancillary); + nicProcessPacket(interface, context->rxBuffer, length, &ancillary); } //Return status code @@ -560,16 +565,16 @@ error_t enc624j600UpdateMacAddrFilter(NetInterface *interface) } //Write the hash table to the ENC624J600 controller - enc624j600WriteReg(interface, ENC624J600_REG_EHT1, hashTable[0]); - enc624j600WriteReg(interface, ENC624J600_REG_EHT2, hashTable[1]); - enc624j600WriteReg(interface, ENC624J600_REG_EHT3, hashTable[2]); - enc624j600WriteReg(interface, ENC624J600_REG_EHT4, hashTable[3]); + enc624j600WriteReg(interface, ENC624J600_EHT1, hashTable[0]); + enc624j600WriteReg(interface, ENC624J600_EHT2, hashTable[1]); + enc624j600WriteReg(interface, ENC624J600_EHT3, hashTable[2]); + enc624j600WriteReg(interface, ENC624J600_EHT4, hashTable[3]); //Debug message - TRACE_DEBUG(" EHT1 = %04" PRIX16 "\r\n", enc624j600ReadReg(interface, ENC624J600_REG_EHT1)); - TRACE_DEBUG(" EHT2 = %04" PRIX16 "\r\n", enc624j600ReadReg(interface, ENC624J600_REG_EHT2)); - TRACE_DEBUG(" EHT3 = %04" PRIX16 "\r\n", enc624j600ReadReg(interface, ENC624J600_REG_EHT3)); - TRACE_DEBUG(" EHT4 = %04" PRIX16 "\r\n", enc624j600ReadReg(interface, ENC624J600_REG_EHT4)); + TRACE_DEBUG(" EHT1 = %04" PRIX16 "\r\n", enc624j600ReadReg(interface, ENC624J600_EHT1)); + TRACE_DEBUG(" EHT2 = %04" PRIX16 "\r\n", enc624j600ReadReg(interface, ENC624J600_EHT2)); + TRACE_DEBUG(" EHT3 = %04" PRIX16 "\r\n", enc624j600ReadReg(interface, ENC624J600_EHT3)); + TRACE_DEBUG(" EHT4 = %04" PRIX16 "\r\n", enc624j600ReadReg(interface, ENC624J600_EHT4)); //Successful processing return NO_ERROR; @@ -586,25 +591,31 @@ void enc624j600UpdateMacConfig(NetInterface *interface) uint16_t duplexMode; //Determine the new duplex mode by reading the PHYDPX bit - duplexMode = enc624j600ReadReg(interface, ENC624J600_REG_ESTAT) & ESTAT_PHYDPX; + duplexMode = enc624j600ReadReg(interface, ENC624J600_ESTAT) & ENC624J600_ESTAT_PHYDPX; //Full-duplex mode? if(duplexMode) { //Configure the FULDPX bit to match the current duplex mode - enc624j600WriteReg(interface, ENC624J600_REG_MACON2, MACON2_DEFER | - MACON2_PADCFG2 | MACON2_PADCFG0 | MACON2_TXCRCEN | MACON2_R1 | MACON2_FULDPX); + enc624j600WriteReg(interface, ENC624J600_MACON2, ENC624J600_MACON2_DEFER | + ENC624J600_MACON2_PADCFG_AUTO | ENC624J600_MACON2_TXCRCEN | + ENC624J600_MACON2_R1_DEFAULT | ENC624J600_MACON2_FULDPX); + //Configure the Back-to-Back Inter-Packet Gap register - enc624j600WriteReg(interface, ENC624J600_REG_MABBIPG, 0x15); + enc624j600WriteReg(interface, ENC624J600_MABBIPG, + ENC624J600_MABBIPG_BBIPG_DEFAULT_FD); } //Half-duplex mode? else { //Configure the FULDPX bit to match the current duplex mode - enc624j600WriteReg(interface, ENC624J600_REG_MACON2, MACON2_DEFER | - MACON2_PADCFG2 | MACON2_PADCFG0 | MACON2_TXCRCEN | MACON2_R1); + enc624j600WriteReg(interface, ENC624J600_MACON2, ENC624J600_MACON2_DEFER | + ENC624J600_MACON2_PADCFG_AUTO | ENC624J600_MACON2_TXCRCEN | + ENC624J600_MACON2_R1_DEFAULT); + //Configure the Back-to-Back Inter-Packet Gap register - enc624j600WriteReg(interface, ENC624J600_REG_MABBIPG, 0x12); + enc624j600WriteReg(interface, ENC624J600_MABBIPG, + ENC624J600_MABBIPG_BBIPG_DEFAULT_HD); } } @@ -621,23 +632,23 @@ error_t enc624j600SoftReset(NetInterface *interface) do { //Write 0x1234 to EUDAST - enc624j600WriteReg(interface, ENC624J600_REG_EUDAST, 0x1234); + enc624j600WriteReg(interface, ENC624J600_EUDAST, 0x1234); //Read back register and check contents - } while(enc624j600ReadReg(interface, ENC624J600_REG_EUDAST) != 0x1234); + } while(enc624j600ReadReg(interface, ENC624J600_EUDAST) != 0x1234); //Poll CLKRDY and wait for it to become set - while((enc624j600ReadReg(interface, ENC624J600_REG_ESTAT) & ESTAT_CLKRDY) == 0) + while((enc624j600ReadReg(interface, ENC624J600_ESTAT) & ENC624J600_ESTAT_CLKRDY) == 0) { } //Issue a system reset command by setting ETHRST - enc624j600SetBit(interface, ENC624J600_REG_ECON2, ECON2_ETHRST); + enc624j600SetBit(interface, ENC624J600_ECON2, ENC624J600_ECON2_ETHRST); //Wait at least 25us for the reset to take place sleep(1); //Read EUDAST to confirm that the system reset took place. //EUDAST should have reverted back to its reset default - if(enc624j600ReadReg(interface, ENC624J600_REG_EUDAST) != 0x0000) + if(enc624j600ReadReg(interface, ENC624J600_EUDAST) != 0x0000) { return ERROR_FAILURE; } @@ -718,15 +729,22 @@ uint16_t enc624j600ReadReg(NetInterface *interface, uint8_t address) void enc624j600WritePhyReg(NetInterface *interface, uint8_t address, uint16_t data) { + uint16_t status; + //Write the address of the PHY register to write to - enc624j600WriteReg(interface, ENC624J600_REG_MIREGADR, MIREGADR_R8 | address); + enc624j600WriteReg(interface, ENC624J600_MIREGADR, + ENC624J600_MIREGADR_R12_8_DEFAULT | address); + //Write the 16 bits of data into the MIWR register - enc624j600WriteReg(interface, ENC624J600_REG_MIWR, data); + enc624j600WriteReg(interface, ENC624J600_MIWR, data); //Wait until the PHY register has been written - while((enc624j600ReadReg(interface, ENC624J600_REG_MISTAT) & MISTAT_BUSY) != 0) + do { - } + //Read MII Management Status register + status = enc624j600ReadReg(interface, ENC624J600_MISTAT); + //Check the value of the busy status bit + } while((status & ENC624J600_MISTAT_BUSY) != 0); } @@ -739,23 +757,31 @@ void enc624j600WritePhyReg(NetInterface *interface, uint8_t address, uint16_t enc624j600ReadPhyReg(NetInterface *interface, uint8_t address) { + uint16_t status; + //Write the address of the PHY register to read from - enc624j600WriteReg(interface, ENC624J600_REG_MIREGADR, MIREGADR_R8 | address); + enc624j600WriteReg(interface, ENC624J600_MIREGADR, + ENC624J600_MIREGADR_R12_8_DEFAULT | address); + //Start read operation - enc624j600WriteReg(interface, ENC624J600_REG_MICMD, MICMD_MIIRD); + enc624j600WriteReg(interface, ENC624J600_MICMD, ENC624J600_MICMD_MIIRD); //Wait at least 25.6us before polling the BUSY bit usleep(100); + //Wait for the read operation to complete - while((enc624j600ReadReg(interface, ENC624J600_REG_MISTAT) & MISTAT_BUSY) != 0) + do { - } + //Read MII Management Status register + status = enc624j600ReadReg(interface, ENC624J600_MISTAT); + //Check the value of the busy status bit + } while((status & ENC624J600_MISTAT_BUSY) != 0); //Clear command register - enc624j600WriteReg(interface, ENC624J600_REG_MICMD, 0x00); + enc624j600WriteReg(interface, ENC624J600_MICMD, 0x00); //Return register contents - return enc624j600ReadReg(interface, ENC624J600_REG_MIRD); + return enc624j600ReadReg(interface, ENC624J600_MIRD); } diff --git a/drivers/eth/enc624j600_driver.h b/drivers/eth/enc624j600_driver.h index 1d719fd0..62a8b0a0 100644 --- a/drivers/eth/enc624j600_driver.h +++ b/drivers/eth/enc624j600_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ENC624J600_DRIVER_H @@ -87,359 +87,451 @@ #define ENC624J600_CMD_WUDADATA 0x32 //Write EUDADATA //ENC624J600 registers -#define ENC624J600_REG_ETXST 0x00 -#define ENC624J600_REG_ETXLEN 0x02 -#define ENC624J600_REG_ERXST 0x04 -#define ENC624J600_REG_ERXTAIL 0x06 -#define ENC624J600_REG_ERXHEAD 0x08 -#define ENC624J600_REG_EDMAST 0x0A -#define ENC624J600_REG_EDMALEN 0x0C -#define ENC624J600_REG_EDMADST 0x0E -#define ENC624J600_REG_EDMACS 0x10 -#define ENC624J600_REG_ETXSTAT 0x12 -#define ENC624J600_REG_ETXWIRE 0x14 -#define ENC624J600_REG_EUDAST 0x16 -#define ENC624J600_REG_EUDAND 0x18 -#define ENC624J600_REG_ESTAT 0x1A -#define ENC624J600_REG_EIR 0x1C -#define ENC624J600_REG_ECON1 0x1E -#define ENC624J600_REG_EHT1 0x20 -#define ENC624J600_REG_EHT2 0x22 -#define ENC624J600_REG_EHT3 0x24 -#define ENC624J600_REG_EHT4 0x26 -#define ENC624J600_REG_EPMM1 0x28 -#define ENC624J600_REG_EPMM2 0x2A -#define ENC624J600_REG_EPMM3 0x2C -#define ENC624J600_REG_EPMM4 0x2E -#define ENC624J600_REG_EPMCS 0x30 -#define ENC624J600_REG_EPMO 0x32 -#define ENC624J600_REG_ERXFCON 0x34 -#define ENC624J600_REG_MACON1 0x40 -#define ENC624J600_REG_MACON2 0x42 -#define ENC624J600_REG_MABBIPG 0x44 -#define ENC624J600_REG_MAIPG 0x46 -#define ENC624J600_REG_MACLCON 0x48 -#define ENC624J600_REG_MAMXFL 0x4A -#define ENC624J600_REG_MICMD 0x52 -#define ENC624J600_REG_MIREGADR 0x54 -#define ENC624J600_REG_MAADR3 0x60 -#define ENC624J600_REG_MAADR2 0x62 -#define ENC624J600_REG_MAADR1 0x64 -#define ENC624J600_REG_MIWR 0x66 -#define ENC624J600_REG_MIRD 0x68 -#define ENC624J600_REG_MISTAT 0x6A -#define ENC624J600_REG_EPAUS 0x6C -#define ENC624J600_REG_ECON2 0x6E -#define ENC624J600_REG_ERXWM 0x70 -#define ENC624J600_REG_EIE 0x72 -#define ENC624J600_REG_EIDLED 0x74 -#define ENC624J600_REG_EGPDATA 0x80 -#define ENC624J600_REG_ERXDATA 0x82 -#define ENC624J600_REG_EUDADATA 0x84 -#define ENC624J600_REG_EGPRDPT 0x86 -#define ENC624J600_REG_EGPWRPT 0x88 -#define ENC624J600_REG_ERXRDPT 0x8A -#define ENC624J600_REG_ERXWRPT 0x8C -#define ENC624J600_REG_EUDARDPT 0x8E -#define ENC624J600_REG_EUDAWRPT 0x90 +#define ENC624J600_ETXST 0x00 +#define ENC624J600_ETXLEN 0x02 +#define ENC624J600_ERXST 0x04 +#define ENC624J600_ERXTAIL 0x06 +#define ENC624J600_ERXHEAD 0x08 +#define ENC624J600_EDMAST 0x0A +#define ENC624J600_EDMALEN 0x0C +#define ENC624J600_EDMADST 0x0E +#define ENC624J600_EDMACS 0x10 +#define ENC624J600_ETXSTAT 0x12 +#define ENC624J600_ETXWIRE 0x14 +#define ENC624J600_EUDAST 0x16 +#define ENC624J600_EUDAND 0x18 +#define ENC624J600_ESTAT 0x1A +#define ENC624J600_EIR 0x1C +#define ENC624J600_ECON1 0x1E +#define ENC624J600_EHT1 0x20 +#define ENC624J600_EHT2 0x22 +#define ENC624J600_EHT3 0x24 +#define ENC624J600_EHT4 0x26 +#define ENC624J600_EPMM1 0x28 +#define ENC624J600_EPMM2 0x2A +#define ENC624J600_EPMM3 0x2C +#define ENC624J600_EPMM4 0x2E +#define ENC624J600_EPMCS 0x30 +#define ENC624J600_EPMO 0x32 +#define ENC624J600_ERXFCON 0x34 +#define ENC624J600_MACON1 0x40 +#define ENC624J600_MACON2 0x42 +#define ENC624J600_MABBIPG 0x44 +#define ENC624J600_MAIPG 0x46 +#define ENC624J600_MACLCON 0x48 +#define ENC624J600_MAMXFL 0x4A +#define ENC624J600_MICMD 0x52 +#define ENC624J600_MIREGADR 0x54 +#define ENC624J600_MAADR3 0x60 +#define ENC624J600_MAADR2 0x62 +#define ENC624J600_MAADR1 0x64 +#define ENC624J600_MIWR 0x66 +#define ENC624J600_MIRD 0x68 +#define ENC624J600_MISTAT 0x6A +#define ENC624J600_EPAUS 0x6C +#define ENC624J600_ECON2 0x6E +#define ENC624J600_ERXWM 0x70 +#define ENC624J600_EIE 0x72 +#define ENC624J600_EIDLED 0x74 +#define ENC624J600_EGPDATA 0x80 +#define ENC624J600_ERXDATA 0x82 +#define ENC624J600_EUDADATA 0x84 +#define ENC624J600_EGPRDPT 0x86 +#define ENC624J600_EGPWRPT 0x88 +#define ENC624J600_ERXRDPT 0x8A +#define ENC624J600_ERXWRPT 0x8C +#define ENC624J600_EUDARDPT 0x8E +#define ENC624J600_EUDAWRPT 0x90 //ENC624J600 PHY registers -#define ENC624J600_PHY_REG_PHCON1 0x00 -#define ENC624J600_PHY_REG_PHSTAT1 0x01 -#define ENC624J600_PHY_REG_PHANA 0x04 -#define ENC624J600_PHY_REG_PHANLPA 0x05 -#define ENC624J600_PHY_REG_PHANE 0x06 -#define ENC624J600_PHY_REG_PHCON2 0x11 -#define ENC624J600_PHY_REG_PHSTAT2 0x1B -#define ENC624J600_PHY_REG_PHSTAT3 0x1F - -//ESTAT register -#define ESTAT_INT 0x8000 -#define ESTAT_FCIDLE 0x4000 -#define ESTAT_RXBUSY 0x2000 -#define ESTAT_CLKRDY 0x1000 -#define ESTAT_R11 0x0800 -#define ESTAT_PHYDPX 0x0400 -#define ESTAT_R9 0x0200 -#define ESTAT_PHYLNK 0x0100 -#define ESTAT_PKTCNT 0x00FF - -//EIR register -#define EIR_CRYPTEN 0x8000 -#define EIR_MODEXIF 0x4000 -#define EIR_HASHIF 0x2000 -#define EIR_AESIF 0x1000 -#define EIR_LINKIF 0x0800 -#define EIR_R10 0x0400 -#define EIR_R9 0x0200 -#define EIR_R8 0x0100 -#define EIR_R7 0x0080 -#define EIR_PKTIF 0x0040 -#define EIR_DMAIF 0x0020 -#define EIR_R4 0x0010 -#define EIR_TXIF 0x0008 -#define EIR_TXABTIF 0x0004 -#define EIR_RXABTIF 0x0002 -#define EIR_PCFULIF 0x0001 - -//ECON1 register -#define ECON1_MODEXST 0x8000 -#define ECON1_HASHEN 0x4000 -#define ECON1_HASHOP 0x2000 -#define ECON1_HASHLST 0x1000 -#define ECON1_AESST 0x0800 -#define ECON1_AESOP1 0x0400 -#define ECON1_AESOP0 0x0200 -#define ECON1_PKTDEC 0x0100 -#define ECON1_FCOP1 0x0080 -#define ECON1_FCOP0 0x0040 -#define ECON1_DMAST 0x0020 -#define ECON1_DMACPY 0x0010 -#define ECON1_DMACSSD 0x0008 -#define ECON1_DMANOCS 0x0004 -#define ECON1_TXRTS 0x0002 -#define ECON1_RXEN 0x0001 - -//ETXSTAT register -#define ETXSTAT_R12 0x1000 -#define ETXSTAT_R11 0x0800 -#define ETXSTAT_LATECOL 0x0400 -#define ETXSTAT_MAXCOL 0x0200 -#define ETXSTAT_EXDEFER 0x0100 -#define ETXSTAT_DEFER 0x0080 -#define ETXSTAT_R6 0x0040 -#define ETXSTAT_R5 0x0020 -#define ETXSTAT_CRCBAD 0x0010 -#define ETXSTAT_COLCNT 0x000F - -//ERXFCON register -#define ERXFCON_HTEN 0x8000 -#define ERXFCON_MPEN 0x4000 -#define ERXFCON_NOTPM 0x1000 -#define ERXFCON_PMEN3 0x0800 -#define ERXFCON_PMEN2 0x0400 -#define ERXFCON_PMEN1 0x0200 -#define ERXFCON_PMEN0 0x0100 -#define ERXFCON_CRCEEN 0x0080 -#define ERXFCON_CRCEN 0x0040 -#define ERXFCON_RUNTEEN 0x0020 -#define ERXFCON_RUNTEN 0x0010 -#define ERXFCON_UCEN 0x0008 -#define ERXFCON_NOTMEEN 0x0004 -#define ERXFCON_MCEN 0x0002 -#define ERXFCON_BCEN 0x0001 - -//MACON1 register -#define MACON1_R15 0x8000 -#define MACON1_R14 0x4000 -#define MACON1_R11 0x0800 -#define MACON1_R10 0x0400 -#define MACON1_R9 0x0200 -#define MACON1_R8 0x0100 -#define MACON1_LOOPBK 0x0010 -#define MACON1_R3 0x0008 -#define MACON1_RXPAUS 0x0004 -#define MACON1_PASSALL 0x0002 -#define MACON1_R0 0x0001 - -//MACON2 register -#define MACON2_DEFER 0x4000 -#define MACON2_BPEN 0x2000 -#define MACON2_NOBKOFF 0x1000 -#define MACON2_R9 0x0200 -#define MACON2_R8 0x0100 -#define MACON2_PADCFG2 0x0080 -#define MACON2_PADCFG1 0x0040 -#define MACON2_PADCFG0 0x0020 -#define MACON2_TXCRCEN 0x0010 -#define MACON2_PHDREN 0x0008 -#define MACON2_HFRMEN 0x0004 -#define MACON2_R1 0x0002 -#define MACON2_FULDPX 0x0001 - -//MABBIPG register -#define MABBIPG_BBIPG 0x007F - -//MAIPG register -#define MAIPG_R14 0x4000 -#define MAIPG_R13 0x2000 -#define MAIPG_R12 0x1000 -#define MAIPG_R11 0x0800 -#define MAIPG_R10 0x0400 -#define MAIPG_R9 0x0200 -#define MAIPG_R8 0x0100 -#define MAIPG_IPG 0x007F - -//MACLCON register -#define MACLCON_R13 0x2000 -#define MACLCON_R12 0x1000 -#define MACLCON_R11 0x0800 -#define MACLCON_R10 0x0400 -#define MACLCON_R9 0x0200 -#define MACLCON_R8 0x0100 -#define MACLCON_MAXRET 0x000F - -//MICMD register -#define MICMD_MIISCAN 0x0002 -#define MICMD_MIIRD 0x0001 - -//MIREGADR register -#define MIREGADR_R12 0x1000 -#define MIREGADR_R11 0x0800 -#define MIREGADR_R10 0x0400 -#define MIREGADR_R9 0x0200 -#define MIREGADR_R8 0x0100 -#define MIREGADR_PHREG 0x001F - -//MISTAT register -#define MISTAT_R3 0x0008 -#define MISTAT_NVALID 0x0004 -#define MISTAT_SCAN 0x0002 -#define MISTAT_BUSY 0x0001 - -//ECON2 register -#define ECON2_ETHEN 0x8000 -#define ECON2_STRCH 0x4000 -#define ECON2_TXMAC 0x2000 -#define ECON2_SHA1MD5 0x1000 -#define ECON2_COCON3 0x0800 -#define ECON2_COCON2 0x0400 -#define ECON2_COCON1 0x0200 -#define ECON2_COCON0 0x0100 -#define ECON2_AUTOFC 0x0080 -#define ECON2_TXRST 0x0040 -#define ECON2_RXRST 0x0020 -#define ECON2_ETHRST 0x0010 -#define ECON2_MODLEN1 0x0008 -#define ECON2_MODLEN0 0x0004 -#define ECON2_AESLEN1 0x0002 -#define ECON2_AESLEN0 0x0001 - -//ERXWM register -#define ERXWM_RXFWM 0xFF00 -#define ERXWM_RXEWM 0x00FF - -//EIE register -#define EIE_INTIE 0x8000 -#define EIE_MODEXIE 0x4000 -#define EIE_HASHIE 0x2000 -#define EIE_AESIE 0x1000 -#define EIE_LINKIE 0x0800 -#define EIE_R10 0x0400 -#define EIE_R9 0x0200 -#define EIE_R8 0x0100 -#define EIE_R7 0x0080 -#define EIE_PKTIE 0x0040 -#define EIE_DMAIE 0x0020 -#define EIE_R4 0x0010 -#define EIE_TXIE 0x0008 -#define EIE_TXABTIE 0x0004 -#define EIE_RXABTIE 0x0002 -#define EIE_PCFULIE 0x0001 - -//EIDLED register -#define EIDLED_LACFG3 0x8000 -#define EIDLED_LACFG2 0x4000 -#define EIDLED_LACFG1 0x2000 -#define EIDLED_LACFG0 0x1000 -#define EIDLED_LBCFG3 0x0800 -#define EIDLED_LBCFG2 0x0400 -#define EIDLED_LBCFG1 0x0200 -#define EIDLED_LBCFG0 0x0100 -#define EIDLED_DEVID 0x00FF - -//PHCON1 register -#define PHCON1_PRST 0x8000 -#define PHCON1_PLOOPBK 0x4000 -#define PHCON1_SPD100 0x2000 -#define PHCON1_ANEN 0x1000 -#define PHCON1_PSLEEP 0x0800 -#define PHCON1_RENEG 0x0200 -#define PHCON1_PFULDPX 0x0100 - -//PHSTAT1 register -#define PHSTAT1_FULL100 0x4000 -#define PHSTAT1_HALF100 0x2000 -#define PHSTAT1_FULL10 0x1000 -#define PHSTAT1_HALF10 0x0800 -#define PHSTAT1_ANDONE 0x0020 -#define PHSTAT1_LRFAULT 0x0010 -#define PHSTAT1_ANABLE 0x0008 -#define PHSTAT1_LLSTAT 0x0004 -#define PHSTAT1_EXTREGS 0x0001 - -//PHANA register -#define PHANA_ADNP 0x8000 -#define PHANA_ADFAULT 0x2000 -#define PHANA_ADPAUS1 0x0800 -#define PHANA_ADPAUS0 0x0400 -#define PHANA_AD100FD 0x0100 -#define PHANA_AD100 0x0080 -#define PHANA_AD10FD 0x0040 -#define PHANA_AD10 0x0020 -#define PHANA_ADIEEE4 0x0010 -#define PHANA_ADIEEE3 0x0008 -#define PHANA_ADIEEE2 0x0004 -#define PHANA_ADIEEE1 0x0002 -#define PHANA_ADIEEE0 0x0001 - -//PHANLPA register -#define PHANLPA_LPNP 0x8000 -#define PHANLPA_LPACK 0x4000 -#define PHANLPA_LPFAULT 0x2000 -#define PHANLPA_LPPAUS1 0x0800 -#define PHANLPA_LPPAUS0 0x0400 -#define PHANLPA_LP100T4 0x0200 -#define PHANLPA_LP100FD 0x0100 -#define PHANLPA_LP100 0x0080 -#define PHANLPA_LP10FD 0x0040 -#define PHANLPA_LP10 0x0020 -#define PHANLPA_LPIEEE 0x001F -#define PHANLPA_LPIEEE4 0x0010 -#define PHANLPA_LPIEEE3 0x0008 -#define PHANLPA_LPIEEE2 0x0004 -#define PHANLPA_LPIEEE1 0x0002 -#define PHANLPA_LPIEEE0 0x0001 - -//PHANE register -#define PHANE_PDFLT 0x0010 -#define PHANE_LPARCD 0x0002 -#define PHANE_LPANABL 0x0001 - -//PHCON2 register -#define PHCON2_EDPWRDN 0x2000 -#define PHCON2_EDTHRES 0x0800 -#define PHCON2_FRCLNK 0x0004 -#define PHCON2_EDSTAT 0x0002 - -//PHSTAT2 register -#define PHSTAT2_PLRITY 0x0010 - -//PHSTAT3 register -#define PHSTAT3_SPDDPX2 0x0010 -#define PHSTAT3_SPDDPX1 0x0008 -#define PHSTAT3_SPDDPX0 0x0004 +#define ENC624J600_PHCON1 0x00 +#define ENC624J600_PHSTAT1 0x01 +#define ENC624J600_PHANA 0x04 +#define ENC624J600_PHANLPA 0x05 +#define ENC624J600_PHANE 0x06 +#define ENC624J600_PHCON2 0x11 +#define ENC624J600_PHSTAT2 0x1B +#define ENC624J600_PHSTAT3 0x1F + +//TX Start Address register +#define ENC624J600_ETXST_VAL 0x7FFF + +//TX Length register +#define ENC624J600_ETXLEN_VAL 0x7FFF + +//RX Buffer Start Address register +#define ENC624J600_ERXST_VAL 0x7FFF + +//RX Tail Pointer register +#define ENC624J600_ERXTAIL_VAL 0x7FFF + +//RX Head Pointer register +#define ENC624J600_ERXHEAD_VAL 0x7FFF + +//DMA Start Address register +#define ENC624J600_EDMAST_VAL 0x7FFF + +//DMA Length register +#define ENC624J600_EDMALEN_VAL 0x7FFF + +//DMA Destination Address register +#define ENC624J600_EDMADST_VAL 0x7FFF + +//Ethernet Transmit Status register +#define ENC624J600_ETXSTAT_R12 0x1000 +#define ENC624J600_ETXSTAT_R11 0x0800 +#define ENC624J600_ETXSTAT_LATECOL 0x0400 +#define ENC624J600_ETXSTAT_MAXCOL 0x0200 +#define ENC624J600_ETXSTAT_EXDEFER 0x0100 +#define ENC624J600_ETXSTAT_DEFER 0x0080 +#define ENC624J600_ETXSTAT_R6 0x0040 +#define ENC624J600_ETXSTAT_R5 0x0020 +#define ENC624J600_ETXSTAT_CRCBAD 0x0010 +#define ENC624J600_ETXSTAT_COLCNT 0x000F + +//User-Defined Area Start Pointer register +#define ENC624J600_EUDAST_VAL 0x7FFF + +//User-Defined Area End Pointer register +#define ENC624J600_EUDAND_VAL 0x7FFF + +//Ethernet Status register +#define ENC624J600_ESTAT_INT 0x8000 +#define ENC624J600_ESTAT_FCIDLE 0x4000 +#define ENC624J600_ESTAT_RXBUSY 0x2000 +#define ENC624J600_ESTAT_CLKRDY 0x1000 +#define ENC624J600_ESTAT_R11 0x0800 +#define ENC624J600_ESTAT_PHYDPX 0x0400 +#define ENC624J600_ESTAT_R9 0x0200 +#define ENC624J600_ESTAT_PHYLNK 0x0100 +#define ENC624J600_ESTAT_PKTCNT 0x00FF + +//Ethernet Interrupt Flag register +#define ENC624J600_EIR_CRYPTEN 0x8000 +#define ENC624J600_EIR_MODEXIF 0x4000 +#define ENC624J600_EIR_HASHIF 0x2000 +#define ENC624J600_EIR_AESIF 0x1000 +#define ENC624J600_EIR_LINKIF 0x0800 +#define ENC624J600_EIR_R10 0x0400 +#define ENC624J600_EIR_R9 0x0200 +#define ENC624J600_EIR_R8 0x0100 +#define ENC624J600_EIR_R7 0x0080 +#define ENC624J600_EIR_PKTIF 0x0040 +#define ENC624J600_EIR_DMAIF 0x0020 +#define ENC624J600_EIR_R4 0x0010 +#define ENC624J600_EIR_TXIF 0x0008 +#define ENC624J600_EIR_TXABTIF 0x0004 +#define ENC624J600_EIR_RXABTIF 0x0002 +#define ENC624J600_EIR_PCFULIF 0x0001 + +//Ethernet Control 1 register +#define ENC624J600_ECON1_MODEXST 0x8000 +#define ENC624J600_ECON1_HASHEN 0x4000 +#define ENC624J600_ECON1_HASHOP 0x2000 +#define ENC624J600_ECON1_HASHLST 0x1000 +#define ENC624J600_ECON1_AESST 0x0800 +#define ENC624J600_ECON1_AESOP1 0x0400 +#define ENC624J600_ECON1_AESOP0 0x0200 +#define ENC624J600_ECON1_PKTDEC 0x0100 +#define ENC624J600_ECON1_FCOP1 0x0080 +#define ENC624J600_ECON1_FCOP0 0x0040 +#define ENC624J600_ECON1_DMAST 0x0020 +#define ENC624J600_ECON1_DMACPY 0x0010 +#define ENC624J600_ECON1_DMACSSD 0x0008 +#define ENC624J600_ECON1_DMANOCS 0x0004 +#define ENC624J600_ECON1_TXRTS 0x0002 +#define ENC624J600_ECON1_RXEN 0x0001 + +//Ethernet RX Filter Control register +#define ENC624J600_ERXFCON_HTEN 0x8000 +#define ENC624J600_ERXFCON_MPEN 0x4000 +#define ENC624J600_ERXFCON_NOTPM 0x1000 +#define ENC624J600_ERXFCON_PMEN 0x0F00 +#define ENC624J600_ERXFCON_PMEN_DISABLED 0x0000 +#define ENC624J600_ERXFCON_PMEN_CHECKSUM 0x0100 +#define ENC624J600_ERXFCON_PMEN_UNICAST 0x0200 +#define ENC624J600_ERXFCON_PMEN_NOT_UNICAST 0x0300 +#define ENC624J600_ERXFCON_PMEN_MULTICAST 0x0400 +#define ENC624J600_ERXFCON_PMEN_NOT_MULTICAST 0x0500 +#define ENC624J600_ERXFCON_PMEN_BROADCAST 0x0600 +#define ENC624J600_ERXFCON_PMEN_NOT_BROADCAST 0x0700 +#define ENC624J600_ERXFCON_PMEN_HASH 0x0800 +#define ENC624J600_ERXFCON_PMEN_MAGIC_PKT 0x0900 +#define ENC624J600_ERXFCON_CRCEEN 0x0080 +#define ENC624J600_ERXFCON_CRCEN 0x0040 +#define ENC624J600_ERXFCON_RUNTEEN 0x0020 +#define ENC624J600_ERXFCON_RUNTEN 0x0010 +#define ENC624J600_ERXFCON_UCEN 0x0008 +#define ENC624J600_ERXFCON_NOTMEEN 0x0004 +#define ENC624J600_ERXFCON_MCEN 0x0002 +#define ENC624J600_ERXFCON_BCEN 0x0001 + +//MAC Control 1 register +#define ENC624J600_MACON1_R15_14 0xC000 +#define ENC624J600_MACON1_R11_8 0x0F00 +#define ENC624J600_MACON1_LOOPBK 0x0010 +#define ENC624J600_MACON1_R3 0x0008 +#define ENC624J600_MACON1_R3_DEFAULT 0x0008 +#define ENC624J600_MACON1_RXPAUS 0x0004 +#define ENC624J600_MACON1_PASSALL 0x0002 +#define ENC624J600_MACON1_R0 0x0001 +#define ENC624J600_MACON1_R0_DEFAULT 0x0001 + +//MAC Control 2 register +#define ENC624J600_MACON2_DEFER 0x4000 +#define ENC624J600_MACON2_BPEN 0x2000 +#define ENC624J600_MACON2_NOBKOFF 0x1000 +#define ENC624J600_MACON2_R9_8 0x0300 +#define ENC624J600_MACON2_PADCFG 0x00E0 +#define ENC624J600_MACON2_PADCFG_NO 0x0000 +#define ENC624J600_MACON2_PADCFG_60_BYTES 0x0020 +#define ENC624J600_MACON2_PADCFG_64_BYTES 0x0060 +#define ENC624J600_MACON2_PADCFG_AUTO 0x00A0 +#define ENC624J600_MACON2_TXCRCEN 0x0010 +#define ENC624J600_MACON2_PHDREN 0x0008 +#define ENC624J600_MACON2_HFRMEN 0x0004 +#define ENC624J600_MACON2_R1 0x0002 +#define ENC624J600_MACON2_R1_DEFAULT 0x0002 +#define ENC624J600_MACON2_FULDPX 0x0001 + +//MAC Back-To-Back Inter-Packet Gap register +#define ENC624J600_MABBIPG_BBIPG 0x007F +#define ENC624J600_MABBIPG_BBIPG_DEFAULT_HD 0x0012 +#define ENC624J600_MABBIPG_BBIPG_DEFAULT_FD 0x0015 + +//MAC Inter-Packet Gap register +#define ENC624J600_MAIPG_R14_8 0x7F00 +#define ENC624J600_MAIPG_R14_8_DEFAULT 0x0C00 +#define ENC624J600_MAIPG_IPG 0x007F +#define ENC624J600_MAIPG_IPG_DEFAULT 0x0012 + +//MAC Collision Control register +#define ENC624J600_MACLCON_R13_8 0x3F00 +#define ENC624J600_MACLCON_R13_8_DEFAULT 0x3700 +#define ENC624J600_MACLCON_MAXRET 0x000F + +//MII Management Command register +#define ENC624J600_MICMD_MIISCAN 0x0002 +#define ENC624J600_MICMD_MIIRD 0x0001 + +//MII Management Address register +#define ENC624J600_MIREGADR_R12_8 0x1F00 +#define ENC624J600_MIREGADR_R12_8_DEFAULT 0x0100 +#define ENC624J600_MIREGADR_PHREG 0x001F + +//MII Management Status register +#define ENC624J600_MISTAT_R3 0x0008 +#define ENC624J600_MISTAT_NVALID 0x0004 +#define ENC624J600_MISTAT_SCAN 0x0002 +#define ENC624J600_MISTAT_BUSY 0x0001 + +//Ethernet Control 2 register +#define ENC624J600_ECON2_ETHEN 0x8000 +#define ENC624J600_ECON2_STRCH 0x4000 +#define ENC624J600_ECON2_TXMAC 0x2000 +#define ENC624J600_ECON2_SHA1MD5 0x1000 +#define ENC624J600_ECON2_COCON 0x0F00 +#define ENC624J600_ECON2_COCON_NONE 0x0000 +#define ENC624J600_ECON2_COCON_33_33_MHZ 0x0100 +#define ENC624J600_ECON2_COCON_25_00_MHZ 0x0200 +#define ENC624J600_ECON2_COCON_20_00_MHZ 0x0300 +#define ENC624J600_ECON2_COCON_16_67_MHZ 0x0400 +#define ENC624J600_ECON2_COCON_12_50_MHZ 0x0500 +#define ENC624J600_ECON2_COCON_10_00_MHZ 0x0600 +#define ENC624J600_ECON2_COCON_8_333_MHZ 0x0700 +#define ENC624J600_ECON2_COCON_8_000_MHZ 0x0800 +#define ENC624J600_ECON2_COCON_6_250_MHZ 0x0900 +#define ENC624J600_ECON2_COCON_5_000_MHZ 0x0A00 +#define ENC624J600_ECON2_COCON_4_000_MHZ 0x0B00 +#define ENC624J600_ECON2_COCON_3_125_MHZ 0x0C00 +#define ENC624J600_ECON2_COCON_100_KHZ 0x0E00 +#define ENC624J600_ECON2_COCON_50_KHZ 0x0F00 +#define ENC624J600_ECON2_AUTOFC 0x0080 +#define ENC624J600_ECON2_TXRST 0x0040 +#define ENC624J600_ECON2_RXRST 0x0020 +#define ENC624J600_ECON2_ETHRST 0x0010 +#define ENC624J600_ECON2_MODLEN 0x000C +#define ENC624J600_ECON2_MODLEN_512_BITS 0x0000 +#define ENC624J600_ECON2_MODLEN_768_BITS 0x0004 +#define ENC624J600_ECON2_MODLEN_1024_BITS 0x0008 +#define ENC624J600_ECON2_AESLEN 0x0003 +#define ENC624J600_ECON2_AESLEN_128_BITS 0x0000 +#define ENC624J600_ECON2_AESLEN_192_BITS 0x0001 +#define ENC624J600_ECON2_AESLEN_256_BITS 0x0002 + +//Receive Watermark register +#define ENC624J600_ERXWM_RXFWM 0xFF00 +#define ENC624J600_ERXWM_RXEWM 0x00FF + +//Ethernet Interrupt Enable register +#define ENC624J600_EIE_INTIE 0x8000 +#define ENC624J600_EIE_MODEXIE 0x4000 +#define ENC624J600_EIE_HASHIE 0x2000 +#define ENC624J600_EIE_AESIE 0x1000 +#define ENC624J600_EIE_LINKIE 0x0800 +#define ENC624J600_EIE_R10_7 0x0780 +#define ENC624J600_EIE_PKTIE 0x0040 +#define ENC624J600_EIE_DMAIE 0x0020 +#define ENC624J600_EIE_R4 0x0010 +#define ENC624J600_EIE_R4_DEFAULT 0x0010 +#define ENC624J600_EIE_TXIE 0x0008 +#define ENC624J600_EIE_TXABTIE 0x0004 +#define ENC624J600_EIE_RXABTIE 0x0002 +#define ENC624J600_EIE_PCFULIE 0x0001 + +//Ethernet ID Status/LED Control register +#define ENC624J600_EIDLED_LACFG 0xF000 +#define ENC624J600_EIDLED_LACFG_OFF 0x0000 +#define ENC624J600_EIDLED_LACFG_ON 0x1000 +#define ENC624J600_EIDLED_LACFG_LINK 0x2000 +#define ENC624J600_EIDLED_LACFG_COL 0x3000 +#define ENC624J600_EIDLED_LACFG_TX 0x4000 +#define ENC624J600_EIDLED_LACFG_RX 0x5000 +#define ENC624J600_EIDLED_LACFG_TX_RX 0x6000 +#define ENC624J600_EIDLED_LACFG_DUPLEX 0x7000 +#define ENC624J600_EIDLED_LACFG_SPEED 0x8000 +#define ENC624J600_EIDLED_LACFG_LINK_TX 0x9000 +#define ENC624J600_EIDLED_LACFG_LINK_RX 0xA000 +#define ENC624J600_EIDLED_LACFG_LINK_TX_RX 0xB000 +#define ENC624J600_EIDLED_LACFG_LINK_COL 0xC000 +#define ENC624J600_EIDLED_LACFG_LINK_DUPLEX_TX_RX 0xE000 +#define ENC624J600_EIDLED_LACFG_LINK_SPEED_TX_RX 0xF000 +#define ENC624J600_EIDLED_LBCFG 0x0F00 +#define ENC624J600_EIDLED_LBCFG_OFF 0x0000 +#define ENC624J600_EIDLED_LBCFG_ON 0x0100 +#define ENC624J600_EIDLED_LBCFG_LINK 0x0200 +#define ENC624J600_EIDLED_LBCFG_COL 0x0300 +#define ENC624J600_EIDLED_LBCFG_TX 0x0400 +#define ENC624J600_EIDLED_LBCFG_RX 0x0500 +#define ENC624J600_EIDLED_LBCFG_TX_RX 0x0600 +#define ENC624J600_EIDLED_LBCFG_DUPLEX 0x0700 +#define ENC624J600_EIDLED_LBCFG_SPEED 0x0800 +#define ENC624J600_EIDLED_LBCFG_LINK_TX 0x0900 +#define ENC624J600_EIDLED_LBCFG_LINK_RX 0x0A00 +#define ENC624J600_EIDLED_LBCFG_LINK_TX_RX 0x0B00 +#define ENC624J600_EIDLED_LBCFG_LINK_COL 0x0C00 +#define ENC624J600_EIDLED_LBCFG_LINK_DUPLEX_TX_RX 0x0E00 +#define ENC624J600_EIDLED_LBCFG_LINK_SPEED_TX_RX 0x0F00 +#define ENC624J600_EIDLED_DEVID 0x00E0 +#define ENC624J600_EIDLED_DEVID_DEFAULT 0x0020 +#define ENC624J600_EIDLED_REVID 0x001F + +//General Purpose Data Window register +#define ENC624J600_EGPDATA_R15_8 0xFF00 +#define ENC624J600_EGPDATA_VAL 0x00FF + +//Ethernet RX Data Window register +#define ENC624J600_ERXDATA_R15_8 0xFF00 +#define ENC624J600_ERXDATA_VAL 0x00FF + +//User-Defined Area Data Window register +#define ENC624J600_EUDADATA_R15_8 0xFF00 +#define ENC624J600_EUDADATA_VAL 0x00FF + +//General Purpose Window Read Pointer register +#define ENC624J600_EGPRDPT_VAL 0x7FFF + +//General Purpose Window Write Pointer register +#define ENC624J600_EGPWRPT_VAL 0x7FFF + +//RX Window Read Pointer register +#define ENC624J600_ERXRDPT_VAL 0x7FFF + +//RX Window Write Pointer register +#define ENC624J600_ERXWRPT_VAL 0x7FFF + +//UDA Window Read Pointer register +#define ENC624J600_EUDARDPT_VAL 0x7FFF + +//UDA Window Write Pointer register +#define ENC624J600_EUDAWRPT_VAL 0x7FFF + +//PHY Control 1 register +#define ENC624J600_PHCON1_PRST 0x8000 +#define ENC624J600_PHCON1_PLOOPBK 0x4000 +#define ENC624J600_PHCON1_SPD100 0x2000 +#define ENC624J600_PHCON1_ANEN 0x1000 +#define ENC624J600_PHCON1_PSLEEP 0x0800 +#define ENC624J600_PHCON1_RENEG 0x0200 +#define ENC624J600_PHCON1_PFULDPX 0x0100 + +//PHY Status 1 register +#define ENC624J600_PHSTAT1_FULL100 0x4000 +#define ENC624J600_PHSTAT1_HALF100 0x2000 +#define ENC624J600_PHSTAT1_FULL10 0x1000 +#define ENC624J600_PHSTAT1_HALF10 0x0800 +#define ENC624J600_PHSTAT1_ANDONE 0x0020 +#define ENC624J600_PHSTAT1_LRFAULT 0x0010 +#define ENC624J600_PHSTAT1_ANABLE 0x0008 +#define ENC624J600_PHSTAT1_LLSTAT 0x0004 +#define ENC624J600_PHSTAT1_EXTREGS 0x0001 + +//PHY Auto-Negotiation Advertisement register +#define ENC624J600_PHANA_ADNP 0x8000 +#define ENC624J600_PHANA_ADFAULT 0x2000 +#define ENC624J600_PHANA_ADPAUS1 0x0800 +#define ENC624J600_PHANA_ADPAUS0 0x0400 +#define ENC624J600_PHANA_AD100FD 0x0100 +#define ENC624J600_PHANA_AD100 0x0080 +#define ENC624J600_PHANA_AD10FD 0x0040 +#define ENC624J600_PHANA_AD10 0x0020 +#define ENC624J600_PHANA_ADIEEE 0x001F +#define ENC624J600_PHANA_ADIEEE_DEFAULT 0x0001 + +//PHY Auto-Negotiation Link Partner Ability register +#define ENC624J600_PHANLPA_LPNP 0x8000 +#define ENC624J600_PHANLPA_LPACK 0x4000 +#define ENC624J600_PHANLPA_LPFAULT 0x2000 +#define ENC624J600_PHANLPA_LPPAUS1 0x0800 +#define ENC624J600_PHANLPA_LPPAUS0 0x0400 +#define ENC624J600_PHANLPA_LP100T4 0x0200 +#define ENC624J600_PHANLPA_LP100FD 0x0100 +#define ENC624J600_PHANLPA_LP100 0x0080 +#define ENC624J600_PHANLPA_LP10FD 0x0040 +#define ENC624J600_PHANLPA_LP10 0x0020 +#define ENC624J600_PHANLPA_LPIEEE 0x001F + +//PHY Auto-Negotiation Expansion register +#define ENC624J600_PHANE_PDFLT 0x0010 +#define ENC624J600_PHANE_LPARCD 0x0002 +#define ENC624J600_PHANE_LPANABL 0x0001 + +//PHY Control 2 register +#define ENC624J600_PHCON2_EDPWRDN 0x2000 +#define ENC624J600_PHCON2_EDTHRES 0x0800 +#define ENC624J600_PHCON2_FRCLNK 0x0004 +#define ENC624J600_PHCON2_EDSTAT 0x0002 + +//PHY Status 2 register +#define ENC624J600_PHSTAT2_PLRITY 0x0010 + +//PHY Status 3 register +#define ENC624J600_PHSTAT3_R6 0x0040 +#define ENC624J600_PHSTAT3_R6_DEFAULT 0x0040 +#define ENC624J600_PHSTAT3_SPDDPX2 0x0010 +#define ENC624J600_PHSTAT3_SPDDPX1 0x0008 +#define ENC624J600_PHSTAT3_SPDDPX0 0x0004 //Receive status vector -#define RSV_UNICAST_FILTER 0x00100000 -#define RSV_PATTERN_MATCH_FILTER 0x00080000 -#define RSV_MAGIC_PACKET_FILTER 0x00040000 -#define RSV_HASH_FILTER 0x00020000 -#define RSV_NOT_ME_FILTER 0x00010000 -#define RSV_RUNT_FILTER 0x00008000 -#define RSV_VLAN_TYPE 0x00004000 -#define RSV_UNKNOWN_OPCODE 0x00002000 -#define RSV_PAUSE_CONTROL_FRAME 0x00001000 -#define RSV_CONTROL_FRAME 0x00000800 -#define RSV_DRIBBLE_NIBBLE 0x00000400 -#define RSV_BROADCAST_PACKET 0x00000200 -#define RSV_MULTICAST_PACKET 0x00000100 -#define RSV_RECEIVED_OK 0x00000080 -#define RSV_LENGTH_OUT_OF_RANGE 0x00000040 -#define RSV_LENGTH_CHECK_ERROR 0x00000020 -#define RSV_CRC_ERROR 0x00000010 -#define RSV_CARRIER_EVENT 0x00000004 -#define RSV_PACKET_IGNORED 0x00000001 +#define ENC624J600_RSV_UNICAST_FILTER 0x00100000 +#define ENC624J600_RSV_PATTERN_MATCH_FILTER 0x00080000 +#define ENC624J600_RSV_MAGIC_PACKET_FILTER 0x00040000 +#define ENC624J600_RSV_HASH_FILTER 0x00020000 +#define ENC624J600_RSV_NOT_ME_FILTER 0x00010000 +#define ENC624J600_RSV_RUNT_FILTER 0x00008000 +#define ENC624J600_RSV_VLAN_TYPE 0x00004000 +#define ENC624J600_RSV_UNKNOWN_OPCODE 0x00002000 +#define ENC624J600_RSV_PAUSE_CONTROL_FRAME 0x00001000 +#define ENC624J600_RSV_CONTROL_FRAME 0x00000800 +#define ENC624J600_RSV_DRIBBLE_NIBBLE 0x00000400 +#define ENC624J600_RSV_BROADCAST_PACKET 0x00000200 +#define ENC624J600_RSV_MULTICAST_PACKET 0x00000100 +#define ENC624J600_RSV_RECEIVED_OK 0x00000080 +#define ENC624J600_RSV_LENGTH_OUT_OF_RANGE 0x00000040 +#define ENC624J600_RSV_LENGTH_CHECK_ERROR 0x00000020 +#define ENC624J600_RSV_CRC_ERROR 0x00000010 +#define ENC624J600_RSV_CARRIER_EVENT 0x00000004 +#define ENC624J600_RSV_PACKET_IGNORED 0x00000001 //C++ guard #ifdef __cplusplus diff --git a/drivers/eth/ksz8851_driver.c b/drivers/eth/ksz8851_driver.c index fdb99a04..5d20c45f 100644 --- a/drivers/eth/ksz8851_driver.c +++ b/drivers/eth/ksz8851_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -87,12 +87,13 @@ error_t ksz8851Init(NetInterface *interface) interface->extIntDriver->init(); //Debug message - TRACE_DEBUG("CIDER=0x%04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_REG_CIDER)); - TRACE_DEBUG("PHY1ILR=0x%04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_REG_PHY1ILR)); - TRACE_DEBUG("PHY1IHR=0x%04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_REG_PHY1IHR)); + TRACE_DEBUG("CIDER=0x%04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_CIDER)); + TRACE_DEBUG("PHY1ILR=0x%04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_PHY1ILR)); + TRACE_DEBUG("PHY1IHR=0x%04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_PHY1IHR)); //Check device ID and revision ID - if(ksz8851ReadReg(interface, KSZ8851_REG_CIDER) != KSZ8851_REV_A3_ID) + if(ksz8851ReadReg(interface, KSZ8851_CIDER) != (KSZ8851_CIDER_FAMILY_ID_DEFAULT | + KSZ8851_CIDER_CHIP_ID_DEFAULT | KSZ8851_CIDER_REV_ID_A3)) { return ERROR_WRONG_IDENTIFIER; } @@ -119,47 +120,56 @@ error_t ksz8851Init(NetInterface *interface) } //Initialize MAC address - ksz8851WriteReg(interface, KSZ8851_REG_MARH, htons(interface->macAddr.w[0])); - ksz8851WriteReg(interface, KSZ8851_REG_MARM, htons(interface->macAddr.w[1])); - ksz8851WriteReg(interface, KSZ8851_REG_MARL, htons(interface->macAddr.w[2])); + ksz8851WriteReg(interface, KSZ8851_MARH, htons(interface->macAddr.w[0])); + ksz8851WriteReg(interface, KSZ8851_MARM, htons(interface->macAddr.w[1])); + ksz8851WriteReg(interface, KSZ8851_MARL, htons(interface->macAddr.w[2])); + + //Packets shorter than 64 bytes are padded and the CRC is automatically + //generated + ksz8851WriteReg(interface, KSZ8851_TXCR, KSZ8851_TXCR_TXFCE | + KSZ8851_TXCR_TXPE | KSZ8851_TXCR_TXCE); - //Packets shorter than 64 bytes are padded and the CRC is automatically generated - ksz8851WriteReg(interface, KSZ8851_REG_TXCR, TXCR_TXFCE | TXCR_TXPE | TXCR_TXCE); //Automatically increment TX data pointer - ksz8851WriteReg(interface, KSZ8851_REG_TXFDPR, TXFDPR_TXFPAI); + ksz8851WriteReg(interface, KSZ8851_TXFDPR, KSZ8851_TXFDPR_TXFPAI); //Configure address filtering - ksz8851WriteReg(interface, KSZ8851_REG_RXCR1, - RXCR1_RXPAFMA | RXCR1_RXFCE | RXCR1_RXBE | RXCR1_RXME | RXCR1_RXUE); + ksz8851WriteReg(interface, KSZ8851_RXCR1, KSZ8851_RXCR1_RXPAFMA | + KSZ8851_RXCR1_RXFCE | KSZ8851_RXCR1_RXBE | KSZ8851_RXCR1_RXME | + KSZ8851_RXCR1_RXUE); //No checksum verification - ksz8851WriteReg(interface, KSZ8851_REG_RXCR2, - RXCR2_SRDBL2 | RXCR2_IUFFP | RXCR2_RXIUFCEZ); + ksz8851WriteReg(interface, KSZ8851_RXCR2, KSZ8851_RXCR2_SRDBL_SINGLE_FRAME | + KSZ8851_RXCR2_IUFFP | KSZ8851_RXCR2_RXIUFCEZ); //Enable automatic RXQ frame buffer dequeue - ksz8851WriteReg(interface, KSZ8851_REG_RXQCR, RXQCR_RXFCTE | RXQCR_ADRFE); + ksz8851WriteReg(interface, KSZ8851_RXQCR, KSZ8851_RXQCR_RXFCTE | + KSZ8851_RXQCR_ADRFE); + //Automatically increment RX data pointer - ksz8851WriteReg(interface, KSZ8851_REG_RXFDPR, RXFDPR_RXFPAI); + ksz8851WriteReg(interface, KSZ8851_RXFDPR, KSZ8851_RXFDPR_RXFPAI); //Configure receive frame count threshold - ksz8851WriteReg(interface, KSZ8851_REG_RXFCTR, 1); + ksz8851WriteReg(interface, KSZ8851_RXFCTR, 1); //Force link in half-duplex if auto-negotiation failed - ksz8851ClearBit(interface, KSZ8851_REG_P1CR, P1CR_FORCE_DUPLEX); + ksz8851ClearBit(interface, KSZ8851_P1CR, KSZ8851_P1CR_FORCE_DUPLEX); //Restart auto-negotiation - ksz8851SetBit(interface, KSZ8851_REG_P1CR, P1CR_RESTART_AN); + ksz8851SetBit(interface, KSZ8851_P1CR, KSZ8851_P1CR_RESTART_AN); //Clear interrupt flags - ksz8851SetBit(interface, KSZ8851_REG_ISR, ISR_LCIS | ISR_TXIS | - ISR_RXIS | ISR_RXOIS | ISR_TXPSIS | ISR_RXPSIS | ISR_TXSAIS | - ISR_RXWFDIS | ISR_RXMPDIS | ISR_LDIS | ISR_EDIS | ISR_SPIBEIS); + ksz8851SetBit(interface, KSZ8851_ISR, KSZ8851_ISR_LCIS | + KSZ8851_ISR_TXIS | KSZ8851_ISR_RXIS | KSZ8851_ISR_RXOIS | + KSZ8851_ISR_TXPSIS | KSZ8851_ISR_RXPSIS | KSZ8851_ISR_TXSAIS | + KSZ8851_ISR_RXWFDIS | KSZ8851_ISR_RXMPDIS | KSZ8851_ISR_LDIS | + KSZ8851_ISR_EDIS | KSZ8851_ISR_SPIBEIS); //Configure interrupts as desired - ksz8851SetBit(interface, KSZ8851_REG_IER, IER_LCIE | IER_TXIE | IER_RXIE); + ksz8851SetBit(interface, KSZ8851_IER, KSZ8851_IER_LCIE | + KSZ8851_IER_TXIE | KSZ8851_IER_RXIE); //Enable TX operation - ksz8851SetBit(interface, KSZ8851_REG_TXCR, TXCR_TXE); + ksz8851SetBit(interface, KSZ8851_TXCR, KSZ8851_TXCR_TXE); //Enable RX operation - ksz8851SetBit(interface, KSZ8851_REG_RXCR1, RXCR1_RXE); + ksz8851SetBit(interface, KSZ8851_RXCR1, KSZ8851_RXCR1_RXE); //Accept any packets from the upper layer osSetEvent(&interface->nicTxEvent); @@ -225,18 +235,18 @@ bool_t ksz8851IrqHandler(NetInterface *interface) flag = FALSE; //Save IER register value - ier = ksz8851ReadReg(interface, KSZ8851_REG_IER); + ier = ksz8851ReadReg(interface, KSZ8851_IER); //Disable interrupts to release the interrupt line - ksz8851WriteReg(interface, KSZ8851_REG_IER, 0); + ksz8851WriteReg(interface, KSZ8851_IER, 0); //Read interrupt status register - isr = ksz8851ReadReg(interface, KSZ8851_REG_ISR); + isr = ksz8851ReadReg(interface, KSZ8851_ISR); //Link status change? - if((isr & ISR_LCIS) != 0) + if((isr & KSZ8851_ISR_LCIS) != 0) { //Disable LCIE interrupt - ier &= ~IER_LCIE; + ier &= ~KSZ8851_IER_LCIE; //Set event flag interface->nicEvent = TRUE; @@ -245,13 +255,13 @@ bool_t ksz8851IrqHandler(NetInterface *interface) } //Packet transmission complete? - if((isr & ISR_TXIS) != 0) + if((isr & KSZ8851_ISR_TXIS) != 0) { //Clear interrupt flag - ksz8851WriteReg(interface, KSZ8851_REG_ISR, ISR_TXIS); + ksz8851WriteReg(interface, KSZ8851_ISR, KSZ8851_ISR_TXIS); //Get the amount of free memory available in the TX FIFO - n = ksz8851ReadReg(interface, KSZ8851_REG_TXMIR) & TXMIR_TXMA_MASK; + n = ksz8851ReadReg(interface, KSZ8851_TXMIR) & KSZ8851_TXMIR_TXMA; //Check whether the TX FIFO is available for writing if(n >= (ETH_MAX_FRAME_SIZE + 8)) @@ -262,10 +272,10 @@ bool_t ksz8851IrqHandler(NetInterface *interface) } //Packet received? - if((isr & ISR_RXIS) != 0) + if((isr & KSZ8851_ISR_RXIS) != 0) { //Disable RXIE interrupt - ier &= ~IER_RXIE; + ier &= ~KSZ8851_IER_RXIE; //Set event flag interface->nicEvent = TRUE; @@ -274,7 +284,7 @@ bool_t ksz8851IrqHandler(NetInterface *interface) } //Re-enable interrupts once the interrupt has been serviced - ksz8851WriteReg(interface, KSZ8851_REG_IER, ier); + ksz8851WriteReg(interface, KSZ8851_IER, ier); //A higher priority task must be woken? return flag; @@ -292,21 +302,21 @@ void ksz8851EventHandler(NetInterface *interface) uint_t frameCount; //Read interrupt status register - status = ksz8851ReadReg(interface, KSZ8851_REG_ISR); + status = ksz8851ReadReg(interface, KSZ8851_ISR); //Check whether the link status has changed? - if((status & ISR_LCIS) != 0) + if((status & KSZ8851_ISR_LCIS) != 0) { //Clear interrupt flag - ksz8851WriteReg(interface, KSZ8851_REG_ISR, ISR_LCIS); + ksz8851WriteReg(interface, KSZ8851_ISR, KSZ8851_ISR_LCIS); //Read PHY status register - status = ksz8851ReadReg(interface, KSZ8851_REG_P1SR); + status = ksz8851ReadReg(interface, KSZ8851_P1SR); //Check link state - if((status & P1SR_LINK_GOOD) != 0) + if((status & KSZ8851_P1SR_LINK_GOOD) != 0) { //Get current speed - if((status & P1SR_OPERATION_SPEED) != 0) + if((status & KSZ8851_P1SR_OPERATION_SPEED) != 0) { interface->linkSpeed = NIC_LINK_SPEED_100MBPS; } @@ -316,7 +326,7 @@ void ksz8851EventHandler(NetInterface *interface) } //Determine the new duplex mode - if((status & P1SR_OPERATION_DUPLEX) != 0) + if((status & KSZ8851_P1SR_OPERATION_DUPLEX) != 0) { interface->duplexMode = NIC_FULL_DUPLEX_MODE; } @@ -339,12 +349,12 @@ void ksz8851EventHandler(NetInterface *interface) } //Check whether a packet has been received? - if((status & ISR_RXIS) != 0) + if((status & KSZ8851_ISR_RXIS) != 0) { //Clear interrupt flag - ksz8851WriteReg(interface, KSZ8851_REG_ISR, ISR_RXIS); + ksz8851WriteReg(interface, KSZ8851_ISR, KSZ8851_ISR_RXIS); //Get the total number of frames that are pending in the buffer - frameCount = MSB(ksz8851ReadReg(interface, KSZ8851_REG_RXFCTR)); + frameCount = MSB(ksz8851ReadReg(interface, KSZ8851_RXFCTR)); //Process all pending packets while(frameCount > 0) @@ -357,7 +367,7 @@ void ksz8851EventHandler(NetInterface *interface) } //Re-enable LCIE and RXIE interrupts - ksz8851SetBit(interface, KSZ8851_REG_IER, IER_LCIE | IER_RXIE); + ksz8851SetBit(interface, KSZ8851_IER, KSZ8851_IER_LCIE | KSZ8851_IER_RXIE); } @@ -395,7 +405,7 @@ error_t ksz8851SendPacket(NetInterface *interface, } //Get the amount of free memory available in the TX FIFO - n = ksz8851ReadReg(interface, KSZ8851_REG_TXMIR) & TXMIR_TXMA_MASK; + n = ksz8851ReadReg(interface, KSZ8851_TXMIR) & KSZ8851_TXMIR_TXMA; //Make sure the TX FIFO is available for writing if(n < (length + 8)) @@ -407,24 +417,26 @@ error_t ksz8851SendPacket(NetInterface *interface, netBufferRead(context->txBuffer, buffer, offset, length); //Format control word - header.controlWord = htole16(TX_CTRL_TXIC | (context->frameId++ & TX_CTRL_TXFID)); + header.controlWord = htole16(KSZ8851_TX_CTRL_TXIC | + (context->frameId++ & KSZ8851_TX_CTRL_TXFID)); + //Total number of bytes to be transmitted header.byteCount = htole16(length); //Enable TXQ write access - ksz8851SetBit(interface, KSZ8851_REG_RXQCR, RXQCR_SDA); + ksz8851SetBit(interface, KSZ8851_RXQCR, KSZ8851_RXQCR_SDA); //Write TX packet header ksz8851WriteFifo(interface, (uint8_t *) &header, sizeof(Ksz8851TxHeader)); //Write data ksz8851WriteFifo(interface, context->txBuffer, length); //End TXQ write access - ksz8851ClearBit(interface, KSZ8851_REG_RXQCR, RXQCR_SDA); + ksz8851ClearBit(interface, KSZ8851_RXQCR, KSZ8851_RXQCR_SDA); //Start transmission - ksz8851SetBit(interface, KSZ8851_REG_TXQCR, TXQCR_METFE); + ksz8851SetBit(interface, KSZ8851_TXQCR, KSZ8851_TXQCR_METFE); //Get the amount of free memory available in the TX FIFO - n = ksz8851ReadReg(interface, KSZ8851_REG_TXMIR) & TXMIR_TXMA_MASK; + n = ksz8851ReadReg(interface, KSZ8851_TXMIR) & KSZ8851_TXMIR_TXMA; //Check whether the TX FIFO is available for writing if(n >= (ETH_MAX_FRAME_SIZE + 8)) @@ -455,28 +467,29 @@ error_t ksz8851ReceivePacket(NetInterface *interface) context = (Ksz8851Context *) interface->nicContext; //Read received frame status from RXFHSR - status = ksz8851ReadReg(interface, KSZ8851_REG_RXFHSR); + status = ksz8851ReadReg(interface, KSZ8851_RXFHSR); //Make sure the frame is valid - if((status & RXFHSR_RXFV) != 0) + if((status & KSZ8851_RXFHSR_RXFV) != 0) { //Check error flags - if((status & (RXFHSR_RXMR | RXFHSR_RXFTL | RXFHSR_RXRF | RXFHSR_RXCE)) == 0) + if((status & (KSZ8851_RXFHSR_RXMR | KSZ8851_RXFHSR_RXFTL | + KSZ8851_RXFHSR_RXRF | KSZ8851_RXFHSR_RXCE)) == 0) { //Read received frame byte size from RXFHBCR - n = ksz8851ReadReg(interface, KSZ8851_REG_RXFHBCR) & RXFHBCR_RXBC_MASK; + n = ksz8851ReadReg(interface, KSZ8851_RXFHBCR) & KSZ8851_RXFHBCR_RXBC; //Ensure the frame size is acceptable if(n > 0 && n <= ETH_MAX_FRAME_SIZE) { //Reset QMU RXQ frame pointer to zero - ksz8851WriteReg(interface, KSZ8851_REG_RXFDPR, RXFDPR_RXFPAI); + ksz8851WriteReg(interface, KSZ8851_RXFDPR, KSZ8851_RXFDPR_RXFPAI); //Enable RXQ read access - ksz8851SetBit(interface, KSZ8851_REG_RXQCR, RXQCR_SDA); + ksz8851SetBit(interface, KSZ8851_RXQCR, KSZ8851_RXQCR_SDA); //Read data ksz8851ReadFifo(interface, context->rxBuffer, n); //End RXQ read access - ksz8851ClearBit(interface, KSZ8851_REG_RXQCR, RXQCR_SDA); + ksz8851ClearBit(interface, KSZ8851_RXQCR, KSZ8851_RXQCR_SDA); //Additional options can be passed to the stack along with the packet ancillary = NET_DEFAULT_RX_ANCILLARY; @@ -490,7 +503,7 @@ error_t ksz8851ReceivePacket(NetInterface *interface) } //Release the current error frame from RXQ - ksz8851SetBit(interface, KSZ8851_REG_RXQCR, RXQCR_RRXEF); + ksz8851SetBit(interface, KSZ8851_RXQCR, KSZ8851_RXQCR_RRXEF); //Report an error return ERROR_INVALID_PACKET; } @@ -536,16 +549,16 @@ error_t ksz8851UpdateMacAddrFilter(NetInterface *interface) } //Write the hash table to the KSZ8851 controller - ksz8851WriteReg(interface, KSZ8851_REG_MAHTR0, hashTable[0]); - ksz8851WriteReg(interface, KSZ8851_REG_MAHTR1, hashTable[1]); - ksz8851WriteReg(interface, KSZ8851_REG_MAHTR2, hashTable[2]); - ksz8851WriteReg(interface, KSZ8851_REG_MAHTR3, hashTable[3]); + ksz8851WriteReg(interface, KSZ8851_MAHTR0, hashTable[0]); + ksz8851WriteReg(interface, KSZ8851_MAHTR1, hashTable[1]); + ksz8851WriteReg(interface, KSZ8851_MAHTR2, hashTable[2]); + ksz8851WriteReg(interface, KSZ8851_MAHTR3, hashTable[3]); //Debug message - TRACE_DEBUG(" MAHTR0 = %04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_REG_MAHTR0)); - TRACE_DEBUG(" MAHTR1 = %04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_REG_MAHTR1)); - TRACE_DEBUG(" MAHTR2 = %04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_REG_MAHTR2)); - TRACE_DEBUG(" MAHTR3 = %04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_REG_MAHTR3)); + TRACE_DEBUG(" MAHTR0 = %04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_MAHTR0)); + TRACE_DEBUG(" MAHTR1 = %04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_MAHTR1)); + TRACE_DEBUG(" MAHTR2 = %04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_MAHTR2)); + TRACE_DEBUG(" MAHTR3 = %04" PRIX16 "\r\n", ksz8851ReadReg(interface, KSZ8851_MAHTR3)); //Successful processing return NO_ERROR; diff --git a/drivers/eth/ksz8851_driver.h b/drivers/eth/ksz8851_driver.h index 860b14c1..1ef370f7 100644 --- a/drivers/eth/ksz8851_driver.h +++ b/drivers/eth/ksz8851_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8851_DRIVER_H @@ -48,391 +48,419 @@ #define KSZ8851_CMD_REG *((volatile uint16_t *) 0x60000004) #endif -//Device ID -#define KSZ8851_REV_A2_ID 0x8870 -#define KSZ8851_REV_A3_ID 0x8872 - //SPI command set -#define KSZ8851_CMD_RD_REG 0x00 -#define KSZ8851_CMD_WR_REG 0x40 -#define KSZ8851_CMD_RD_FIFO 0x80 -#define KSZ8851_CMD_WR_FIFO 0xC0 +#define KSZ8851_CMD_RD_REG 0x00 +#define KSZ8851_CMD_WR_REG 0x40 +#define KSZ8851_CMD_RD_FIFO 0x80 +#define KSZ8851_CMD_WR_FIFO 0xC0 //Byte enable bits #if (KSZ8851_SPI_SUPPORT == ENABLED) - #define KSZ8851_CMD_B0 0x04 - #define KSZ8851_CMD_B1 0x08 - #define KSZ8851_CMD_B2 0x10 - #define KSZ8851_CMD_B3 0x20 + #define KSZ8851_CMD_B0 0x04 + #define KSZ8851_CMD_B1 0x08 + #define KSZ8851_CMD_B2 0x10 + #define KSZ8851_CMD_B3 0x20 #else - #define KSZ8851_CMD_B0 0x1000 - #define KSZ8851_CMD_B1 0x2000 - #define KSZ8851_CMD_B2 0x4000 - #define KSZ8851_CMD_B3 0x8000 + #define KSZ8851_CMD_B0 0x1000 + #define KSZ8851_CMD_B1 0x2000 + #define KSZ8851_CMD_B2 0x4000 + #define KSZ8851_CMD_B3 0x8000 #endif //KSZ8851 registers -#define KSZ8851_REG_CCR 0x08 -#define KSZ8851_REG_MARL 0x10 -#define KSZ8851_REG_MARM 0x12 -#define KSZ8851_REG_MARH 0x14 -#define KSZ8851_REG_OBCR 0x20 -#define KSZ8851_REG_EEPCR 0x22 -#define KSZ8851_REG_MBIR 0x24 -#define KSZ8851_REG_GRR 0x26 -#define KSZ8851_REG_WFCR 0x2A -#define KSZ8851_REG_WF0CRC0 0x30 -#define KSZ8851_REG_WF0CRC1 0x32 -#define KSZ8851_REG_WF0BM0 0x34 -#define KSZ8851_REG_WF0BM1 0x36 -#define KSZ8851_REG_WF0BM2 0x38 -#define KSZ8851_REG_WF0BM3 0x3A -#define KSZ8851_REG_WF1CRC0 0x40 -#define KSZ8851_REG_WF1CRC1 0x42 -#define KSZ8851_REG_WF1BM0 0x44 -#define KSZ8851_REG_WF1BM1 0x46 -#define KSZ8851_REG_WF1BM2 0x48 -#define KSZ8851_REG_WF1BM3 0x4A -#define KSZ8851_REG_WF2CRC0 0x50 -#define KSZ8851_REG_WF2CRC1 0x52 -#define KSZ8851_REG_WF2BM0 0x54 -#define KSZ8851_REG_WF2BM1 0x56 -#define KSZ8851_REG_WF2BM2 0x58 -#define KSZ8851_REG_WF2BM3 0x5A -#define KSZ8851_REG_WF3CRC0 0x60 -#define KSZ8851_REG_WF3CRC1 0x62 -#define KSZ8851_REG_WF3BM0 0x64 -#define KSZ8851_REG_WF3BM1 0x66 -#define KSZ8851_REG_WF3BM2 0x68 -#define KSZ8851_REG_WF3BM3 0x6A -#define KSZ8851_REG_TXCR 0x70 -#define KSZ8851_REG_TXSR 0x72 -#define KSZ8851_REG_RXCR1 0x74 -#define KSZ8851_REG_RXCR2 0x76 -#define KSZ8851_REG_TXMIR 0x78 -#define KSZ8851_REG_RXFHSR 0x7C -#define KSZ8851_REG_RXFHBCR 0x7E -#define KSZ8851_REG_TXQCR 0x80 -#define KSZ8851_REG_RXQCR 0x82 -#define KSZ8851_REG_TXFDPR 0x84 -#define KSZ8851_REG_RXFDPR 0x86 -#define KSZ8851_REG_RXDTTR 0x8C -#define KSZ8851_REG_RXDBCTR 0x8E -#define KSZ8851_REG_IER 0x90 -#define KSZ8851_REG_ISR 0x92 -#define KSZ8851_REG_RXFCTR 0x9C -#define KSZ8851_REG_TXNTFSR 0x9E -#define KSZ8851_REG_MAHTR0 0xA0 -#define KSZ8851_REG_MAHTR1 0xA2 -#define KSZ8851_REG_MAHTR2 0xA4 -#define KSZ8851_REG_MAHTR3 0xA6 -#define KSZ8851_REG_FCLWR 0xB0 -#define KSZ8851_REG_FCHWR 0xB2 -#define KSZ8851_REG_FCOWR 0xB4 -#define KSZ8851_REG_CIDER 0xC0 -#define KSZ8851_REG_CGCR 0xC6 -#define KSZ8851_REG_IACR 0xC8 -#define KSZ8851_REG_IADLR 0xD0 -#define KSZ8851_REG_IADHR 0xD2 -#define KSZ8851_REG_PMECR 0xD4 -#define KSZ8851_REG_GSWUTR 0xD6 -#define KSZ8851_REG_PHYRR 0xD8 -#define KSZ8851_REG_P1MBCR 0xE4 -#define KSZ8851_REG_P1MBSR 0xE6 -#define KSZ8851_REG_PHY1ILR 0xE8 -#define KSZ8851_REG_PHY1IHR 0xEA -#define KSZ8851_REG_P1ANAR 0xEC -#define KSZ8851_REG_P1ANLPR 0xEE -#define KSZ8851_REG_P1SCLMD 0xF4 -#define KSZ8851_REG_P1CR 0xF6 -#define KSZ8851_REG_P1SR 0xF8 - -//CCR register -#define CCR_BUS_ENDIAN_MODE 0x0400 -#define CCR_EEPROM_PRESENCE 0x0200 -#define CCR_SPI_MODE 0x0100 -#define CCR_8_BIT_DATA_BUS 0x0080 -#define CCR_16_BIT_DATA_BUS 0x0040 -#define CCR_32_BIT_DATA_BUS 0x0020 -#define CCR_BUS_SHARED_MODE 0x0010 -#define CCR_128_PIN_PACKAGE 0x0008 -#define CCR_48_PIN_PACKAGE 0x0002 -#define CCR_32_PIN_PACKAGE 0x0001 - -//OBCR register -#define OBCR_OUT_DRIVE_STRENGTH 0x0040 -#define OBCR_SPI_SO_DELAY2 0x0020 -#define OBCR_SPI_SO_DELAY1 0x0010 -#define OBCR_SPI_SO_DELAY0 0x0008 -#define OBCR_BUS_CLOCK_SEL 0x0004 -#define OBCR_BUS_CLOCK_DIV1 0x0002 -#define OBCR_BUS_CLOCK_DIV0 0x0001 - -//EEPCR register -#define EEPCR_EESA 0x0010 -#define EEPCR_EESB 0x0008 -#define EEPCR_EECB2 0x0004 -#define EEPCR_EECB1 0x0002 -#define EEPCR_EECB0 0x0001 - -//MBIR register -#define MBIR_TXMBF 0x1000 -#define MBIR_TXMBFA 0x0800 -#define MBIR_TXMBFC2 0x0400 -#define MBIR_TXMBFC1 0x0200 -#define MBIR_TXMBFC0 0x0100 -#define MBIR_RXMBF 0x0010 -#define MBIR_RXMBFA 0x0008 -#define MBIR_RXMBFC2 0x0004 -#define MBIR_RXMBFC1 0x0002 -#define MBIR_RXMBFC0 0x0001 - -//GRR register -#define GRR_QMU_MODULE_SOFT_RST 0x0002 -#define GRR_GLOBAL_SOFT_RST 0x0001 - -//WFCR register -#define WFCR_MPRXE 0x0080 -#define WFCR_WF3E 0x0008 -#define WFCR_WF2E 0x0004 -#define WFCR_WF1E 0x0002 -#define WFCR_WF0E 0x0001 - -//TXCR register -#define TXCR_TCGICMP 0x0100 -#define TXCR_TCGUDP 0x0080 -#define TXCR_TCGTCP 0x0040 -#define TXCR_TCGIP 0x0020 -#define TXCR_FTXQ 0x0010 -#define TXCR_TXFCE 0x0008 -#define TXCR_TXPE 0x0004 -#define TXCR_TXCE 0x0002 -#define TXCR_TXE 0x0001 - -//TXSR register -#define TXSR_TXLC 0x2000 -#define TXSR_TXMC 0x1000 -#define TXSR_TXFID5 0x0020 -#define TXSR_TXFID4 0x0010 -#define TXSR_TXFID3 0x0008 -#define TXSR_TXFID2 0x0004 -#define TXSR_TXFID1 0x0002 -#define TXSR_TXFID0 0x0001 - -//RXCR1 register -#define RXCR1_FRXQ 0x8000 -#define RXCR1_RXUDPFCC 0x4000 -#define RXCR1_RXTCPFCC 0x2000 -#define RXCR1_RXIPFCC 0x1000 -#define RXCR1_RXPAFMA 0x0800 -#define RXCR1_RXFCE 0x0400 -#define RXCR1_RXEFE 0x0200 -#define RXCR1_RXMAFMA 0x0100 -#define RXCR1_RXBE 0x0080 -#define RXCR1_RXME 0x0040 -#define RXCR1_RXUE 0x0020 -#define RXCR1_RXAE 0x0010 -#define RXCR1_RXINVF 0x0002 -#define RXCR1_RXE 0x0001 - -//RXCR2 register -#define RXCR2_SRDBL2 0x0080 -#define RXCR2_SRDBL1 0x0040 -#define RXCR2_SRDBL0 0x0020 -#define RXCR2_IUFFP 0x0010 -#define RXCR2_RXIUFCEZ 0x0008 -#define RXCR2_UDPLFE 0x0004 -#define RXCR2_RXICMPFCC 0x0002 -#define RXCR2_RXSAF 0x0001 - -//TXMIR register -#define TXMIR_TXMA_MASK 0x1FFF - -//RXFHSR register -#define RXFHSR_RXFV 0x8000 -#define RXFHSR_RXICMPFCS 0x2000 -#define RXFHSR_RXIPFCS 0x1000 -#define RXFHSR_RXTCPFCS 0x0800 -#define RXFHSR_RXUDPFCS 0x0400 -#define RXFHSR_RXBF 0x0080 -#define RXFHSR_RXMF 0x0040 -#define RXFHSR_RXUF 0x0020 -#define RXFHSR_RXMR 0x0010 -#define RXFHSR_RXFT 0x0008 -#define RXFHSR_RXFTL 0x0004 -#define RXFHSR_RXRF 0x0002 -#define RXFHSR_RXCE 0x0001 - -//RXFHBCR register -#define RXFHBCR_RXBC_MASK 0x0FFF - -//TXQCR register -#define TXQCR_AETFE 0x0004 -#define TXQCR_TXQMAM 0x0002 -#define TXQCR_METFE 0x0001 - -//RXQCR register -#define RXQCR_RXDTTS 0x1000 -#define RXQCR_RXDBCTS 0x0800 -#define RXQCR_RXFCTS 0x0400 -#define RXQCR_RXIPHTOE 0x0200 -#define RXQCR_RXDTTE 0x0080 -#define RXQCR_RXDBCTE 0x0040 -#define RXQCR_RXFCTE 0x0020 -#define RXQCR_ADRFE 0x0010 -#define RXQCR_SDA 0x0008 -#define RXQCR_RRXEF 0x0001 - -//TXFDPR register -#define TXFDPR_TXFPAI 0x4000 - -//RXFDPR register -#define RXFDPR_RXFPAI 0x4000 - -//IER register -#define IER_LCIE 0x8000 -#define IER_TXIE 0x4000 -#define IER_RXIE 0x2000 -#define IER_RXOIE 0x0800 -#define IER_TXPSIE 0x0200 -#define IER_RXPSIE 0x0100 -#define IER_TXSAIE 0x0040 -#define IER_RXWFDIE 0x0020 -#define IER_RXMPDIE 0x0010 -#define IER_LDIE 0x0008 -#define IER_EDIE 0x0004 -#define IER_SPIBEIE 0x0002 -#define IER_DEDIE 0x0001 - -//ISR register -#define ISR_LCIS 0x8000 -#define ISR_TXIS 0x4000 -#define ISR_RXIS 0x2000 -#define ISR_RXOIS 0x0800 -#define ISR_TXPSIS 0x0200 -#define ISR_RXPSIS 0x0100 -#define ISR_TXSAIS 0x0040 -#define ISR_RXWFDIS 0x0020 -#define ISR_RXMPDIS 0x0010 -#define ISR_LDIS 0x0008 -#define ISR_EDIS 0x0004 -#define ISR_SPIBEIS 0x0002 - -//CGCR register -#define CGCR_LEDSEL0 0x0200 - -//IACR register -#define IACR_READ_ENABLE 0x1000 -#define IACR_TABLE_SELECT1 0x0800 -#define IACR_TABLE_SELECT0 0x0400 - -//PMECR register -#define PMECR_PME_DELAY_EN 0x4000 -#define PMECR_PME_POLARITY 0x1000 -#define PMECR_PME_WUP_FRAME_EN 0x0800 -#define PMECR_PME_MAGIC_EN 0x0400 -#define PMECR_PME_LINK_UP_EN 0x0200 -#define PMECR_PME_ENERGY_EN 0x0100 -#define PMECR_AUTO_WUP_EN 0x0080 -#define PMECR_WUP_NORMAL_OP_MODE 0x0040 -#define PMECR_WUP_FROM_WUP_FRAME 0x0020 -#define PMECR_WUP_FROM_MAGIC 0x0010 -#define PMECR_WUP_FROM_LINK_UP 0x0008 -#define PMECR_WUP_FROM_ENERGY 0x0004 -#define PMECR_PWR_MODE1 0x0002 -#define PMECR_PWR_MODE0 0x0001 - -//PHYRR register -#define PHYRR_PHY_RESET 0x0001 - -//P1MBCR register -#define P1MBCR_LOCAL_LOOPBACK 0x4000 -#define P1MBCR_FORCE_100 0x2000 -#define P1MBCR_AN_ENABLE 0x1000 -#define P1MBCR_RESTART_AN 0x0200 -#define P1MBCR_FORCE_FULL_DUPLEX 0x0100 -#define P1MBCR_HP_MDIX 0x0020 -#define P1MBCR_FORCE_MDIX 0x0010 -#define P1MBCR_DISABLE_MDIX 0x0008 -#define P1MBCR_DISABLE_TRANSMIT 0x0002 -#define P1MBCR_DISABLE_LED 0x0001 - -//P1MBSR register -#define P1MBSR_T4_CAPABLE 0x8000 -#define P1MBSR_100_FD_CAPABLE 0x4000 -#define P1MBSR_100_CAPABLE 0x2000 -#define P1MBSR_10_FD_CAPABLE 0x1000 -#define P1MBSR_10_CAPABLE 0x0800 -#define P1MBSR_PREAMBLE_SUPPR 0x0040 -#define P1MBSR_AN_COMPLETE 0x0020 -#define P1MBSR_AN_CAPABLE 0x0008 -#define P1MBSR_LINK_STATUS 0x0004 -#define P1MBSR_JABBER_TEST 0x0002 -#define P1MBSR_EXTENDED_CAPABLE 0x0001 - -//P1ANAR register -#define P1ANAR_NEXT_PAGE 0x8000 -#define P1ANAR_REMOTE_FAULT 0x2000 -#define P1ANAR_ADV_PAUSE 0x0400 -#define P1ANAR_ADV_100_FD 0x0100 -#define P1ANAR_ADV_100 0x0080 -#define P1ANAR_ADV_10_FD 0x0040 -#define P1ANAR_ADV_10 0x0020 -#define P1ANAR_SELECTOR_FIELD4 0x0010 -#define P1ANAR_SELECTOR_FIELD3 0x0008 -#define P1ANAR_SELECTOR_FIELD2 0x0004 -#define P1ANAR_SELECTOR_FIELD1 0x0002 -#define P1ANAR_SELECTOR_FIELD0 0x0001 - -//P1ANLPR register -#define P1ANLPR_NEXT_PAGE 0x8000 -#define P1ANLPR_LP_ACK 0x4000 -#define P1ANLPR_REMOTE_FAULT 0x2000 -#define P1ANLPR_ADV_PAUSE 0x0400 -#define P1ANLPR_ADV_100_FD 0x0100 -#define P1ANLPR_ADV_100 0x0080 -#define P1ANLPR_ADV_10_FD 0x0040 -#define P1ANLPR_ADV_10 0x0020 - -//P1SCLMD register -#define P1SCLMD_VCT_RESULT1 0x4000 -#define P1SCLMD_VCT_RESULT0 0x2000 -#define P1SCLMD_VCT_EN 0x1000 -#define P1SCLMD_FORCE_LNK 0x0800 -#define P1SCLMD_REMOTE_LOOPBACK 0x0200 - -//P1CR register -#define P1CR_LED_OFF 0x8000 -#define P1CR_TX_DISABLE 0x4000 -#define P1CR_RESTART_AN 0x2000 -#define P1CR_DISABLE_AUTO_MDIX 0x0400 -#define P1CR_FORCE_MDIX 0x0200 -#define P1CR_AN_ENABLE 0x0080 -#define P1CR_FORCE_SPEED 0x0040 -#define P1CR_FORCE_DUPLEX 0x0020 -#define P1CR_ADV_PAUSE 0x0010 -#define P1CR_ADV_100_FD 0x0008 -#define P1CR_ADV_100 0x0004 -#define P1CR_ADV_10_FD 0x0002 -#define P1CR_ADV_10 0x0001 - -//P1SR register -#define P1SR_HP_MDIX 0x8000 -#define P1SR_REVERSED_POLARITY 0x2000 -#define P1SR_OPERATION_SPEED 0x0400 -#define P1SR_OPERATION_DUPLEX 0x0200 -#define P1SR_MDIX_STATUS 0x0080 -#define P1SR_AN_DONE 0x0040 -#define P1SR_LINK_GOOD 0x0020 -#define P1SR_PARTNER_ADV_PAUSE 0x0010 -#define P1SR_PARTNER_ADV_100_FD 0x0008 -#define P1SR_PARTNER_ADV_100 0x0004 -#define P1SR_PARTNER_ADV_10_FD 0x0002 -#define P1SR_PARTNER_ADV_10 0x0001 +#define KSZ8851_CCR 0x08 +#define KSZ8851_MARL 0x10 +#define KSZ8851_MARM 0x12 +#define KSZ8851_MARH 0x14 +#define KSZ8851_OBCR 0x20 +#define KSZ8851_EEPCR 0x22 +#define KSZ8851_MBIR 0x24 +#define KSZ8851_GRR 0x26 +#define KSZ8851_WFCR 0x2A +#define KSZ8851_WF0CRC0 0x30 +#define KSZ8851_WF0CRC1 0x32 +#define KSZ8851_WF0BM0 0x34 +#define KSZ8851_WF0BM1 0x36 +#define KSZ8851_WF0BM2 0x38 +#define KSZ8851_WF0BM3 0x3A +#define KSZ8851_WF1CRC0 0x40 +#define KSZ8851_WF1CRC1 0x42 +#define KSZ8851_WF1BM0 0x44 +#define KSZ8851_WF1BM1 0x46 +#define KSZ8851_WF1BM2 0x48 +#define KSZ8851_WF1BM3 0x4A +#define KSZ8851_WF2CRC0 0x50 +#define KSZ8851_WF2CRC1 0x52 +#define KSZ8851_WF2BM0 0x54 +#define KSZ8851_WF2BM1 0x56 +#define KSZ8851_WF2BM2 0x58 +#define KSZ8851_WF2BM3 0x5A +#define KSZ8851_WF3CRC0 0x60 +#define KSZ8851_WF3CRC1 0x62 +#define KSZ8851_WF3BM0 0x64 +#define KSZ8851_WF3BM1 0x66 +#define KSZ8851_WF3BM2 0x68 +#define KSZ8851_WF3BM3 0x6A +#define KSZ8851_TXCR 0x70 +#define KSZ8851_TXSR 0x72 +#define KSZ8851_RXCR1 0x74 +#define KSZ8851_RXCR2 0x76 +#define KSZ8851_TXMIR 0x78 +#define KSZ8851_RXFHSR 0x7C +#define KSZ8851_RXFHBCR 0x7E +#define KSZ8851_TXQCR 0x80 +#define KSZ8851_RXQCR 0x82 +#define KSZ8851_TXFDPR 0x84 +#define KSZ8851_RXFDPR 0x86 +#define KSZ8851_RXDTTR 0x8C +#define KSZ8851_RXDBCTR 0x8E +#define KSZ8851_IER 0x90 +#define KSZ8851_ISR 0x92 +#define KSZ8851_RXFCTR 0x9C +#define KSZ8851_TXNTFSR 0x9E +#define KSZ8851_MAHTR0 0xA0 +#define KSZ8851_MAHTR1 0xA2 +#define KSZ8851_MAHTR2 0xA4 +#define KSZ8851_MAHTR3 0xA6 +#define KSZ8851_FCLWR 0xB0 +#define KSZ8851_FCHWR 0xB2 +#define KSZ8851_FCOWR 0xB4 +#define KSZ8851_CIDER 0xC0 +#define KSZ8851_CGCR 0xC6 +#define KSZ8851_IACR 0xC8 +#define KSZ8851_IADLR 0xD0 +#define KSZ8851_IADHR 0xD2 +#define KSZ8851_PMECR 0xD4 +#define KSZ8851_GSWUTR 0xD6 +#define KSZ8851_PHYRR 0xD8 +#define KSZ8851_P1MBCR 0xE4 +#define KSZ8851_P1MBSR 0xE6 +#define KSZ8851_PHY1ILR 0xE8 +#define KSZ8851_PHY1IHR 0xEA +#define KSZ8851_P1ANAR 0xEC +#define KSZ8851_P1ANLPR 0xEE +#define KSZ8851_P1SCLMD 0xF4 +#define KSZ8851_P1CR 0xF6 +#define KSZ8851_P1SR 0xF8 + +//Chip Configuration register +#define KSZ8851_CCR_BUS_ENDIAN_MODE 0x0400 +#define KSZ8851_CCR_EEPROM_PRESENCE 0x0200 +#define KSZ8851_CCR_SPI_BUS_MODE 0x0100 +#define KSZ8851_CCR_8_BIT_DATA_BUS 0x0080 +#define KSZ8851_CCR_16_BIT_DATA_BUS 0x0040 +#define KSZ8851_CCR_32_BIT_DATA_BUS 0x0020 +#define KSZ8851_CCR_SHARED_BUS_MODE 0x0010 +#define KSZ8851_CCR_128_PIN_PACKAGE 0x0008 +#define KSZ8851_CCR_48_PIN_PACKAGE 0x0002 +#define KSZ8851_CCR_32_PIN_PACKAGE 0x0001 + +//On-Chip Bus Control register +#define KSZ8851_OBCR_OUT_PIN_DRIVE_STRENGTH 0x0040 +#define KSZ8851_OBCR_BUS_CLK_SEL 0x0004 +#define KSZ8851_OBCR_BUS_CLK_DIV 0x0003 +#define KSZ8851_OBCR_BUS_CLK_DIV_1 0x0000 +#define KSZ8851_OBCR_BUS_CLK_DIV_2 0x0001 +#define KSZ8851_OBCR_BUS_CLK_DIV_3 0x0002 + +//EEPROM Control register +#define KSZ8851_EEPCR_EESRWA 0x0020 +#define KSZ8851_EEPCR_EESA 0x0010 +#define KSZ8851_EEPCR_EESB 0x0008 +#define KSZ8851_EEPCR_EECB 0x0007 +#define KSZ8851_EEPCR_EECB_EED_IO 0x0004 +#define KSZ8851_EEPCR_EECB_EESK 0x0002 +#define KSZ8851_EEPCR_EECB_EECS 0x0001 + +//Memory BIST Info register +#define KSZ8851_MBIR_TXMBF 0x1000 +#define KSZ8851_MBIR_TXMBFA 0x0800 +#define KSZ8851_MBIR_TXMBFC 0x0700 +#define KSZ8851_MBIR_RXMBF 0x0010 +#define KSZ8851_MBIR_RXMBFA 0x0008 +#define KSZ8851_MBIR_RXMBFC 0x0007 + +//Global Reset register +#define KSZ8851_GRR_QMU_MODULE_SOFT_RESET 0x0002 +#define KSZ8851_GRR_GLOBAL_SOFT_RESET 0x0001 + +//Wakeup Frame Control register +#define KSZ8851_WFCR_MPRXE 0x0080 +#define KSZ8851_WFCR_WF3E 0x0008 +#define KSZ8851_WFCR_WF2E 0x0004 +#define KSZ8851_WFCR_WF1E 0x0002 +#define KSZ8851_WFCR_WF0E 0x0001 + +//Transmit Control register +#define KSZ8851_TXCR_TCGICMP 0x0100 +#define KSZ8851_TXCR_TCGTCP 0x0040 +#define KSZ8851_TXCR_TCGIP 0x0020 +#define KSZ8851_TXCR_FTXQ 0x0010 +#define KSZ8851_TXCR_TXFCE 0x0008 +#define KSZ8851_TXCR_TXPE 0x0004 +#define KSZ8851_TXCR_TXCE 0x0002 +#define KSZ8851_TXCR_TXE 0x0001 + +//Transmit Status register +#define KSZ8851_TXSR_TXLC 0x2000 +#define KSZ8851_TXSR_TXMC 0x1000 +#define KSZ8851_TXSR_TXFID 0x003F + +//Receive Control 1 register +#define KSZ8851_RXCR1_FRXQ 0x8000 +#define KSZ8851_RXCR1_RXUDPFCC 0x4000 +#define KSZ8851_RXCR1_RXTCPFCC 0x2000 +#define KSZ8851_RXCR1_RXIPFCC 0x1000 +#define KSZ8851_RXCR1_RXPAFMA 0x0800 +#define KSZ8851_RXCR1_RXFCE 0x0400 +#define KSZ8851_RXCR1_RXEFE 0x0200 +#define KSZ8851_RXCR1_RXMAFMA 0x0100 +#define KSZ8851_RXCR1_RXBE 0x0080 +#define KSZ8851_RXCR1_RXME 0x0040 +#define KSZ8851_RXCR1_RXUE 0x0020 +#define KSZ8851_RXCR1_RXAE 0x0010 +#define KSZ8851_RXCR1_RXINVF 0x0002 +#define KSZ8851_RXCR1_RXE 0x0001 + +//Receive Control 2 register +#define KSZ8851_RXCR2_SRDBL 0x00E0 +#define KSZ8851_RXCR2_SRDBL_4_BYTES 0x0000 +#define KSZ8851_RXCR2_SRDBL_8_BYTES 0x0020 +#define KSZ8851_RXCR2_SRDBL_16_BYTES 0x0040 +#define KSZ8851_RXCR2_SRDBL_32_BYTES 0x0060 +#define KSZ8851_RXCR2_SRDBL_SINGLE_FRAME 0x0080 +#define KSZ8851_RXCR2_IUFFP 0x0010 +#define KSZ8851_RXCR2_RXIUFCEZ 0x0008 +#define KSZ8851_RXCR2_UDPLFE 0x0004 +#define KSZ8851_RXCR2_RXICMPFCC 0x0002 +#define KSZ8851_RXCR2_RXSAF 0x0001 + +//TXQ Memory Information register +#define KSZ8851_TXMIR_TXMA 0x1FFF + +//Receive Frame Header Status register +#define KSZ8851_RXFHSR_RXFV 0x8000 +#define KSZ8851_RXFHSR_RXICMPFCS 0x2000 +#define KSZ8851_RXFHSR_RXIPFCS 0x1000 +#define KSZ8851_RXFHSR_RXTCPFCS 0x0800 +#define KSZ8851_RXFHSR_RXUDPFCS 0x0400 +#define KSZ8851_RXFHSR_RXBF 0x0080 +#define KSZ8851_RXFHSR_RXMF 0x0040 +#define KSZ8851_RXFHSR_RXUF 0x0020 +#define KSZ8851_RXFHSR_RXMR 0x0010 +#define KSZ8851_RXFHSR_RXFT 0x0008 +#define KSZ8851_RXFHSR_RXFTL 0x0004 +#define KSZ8851_RXFHSR_RXRF 0x0002 +#define KSZ8851_RXFHSR_RXCE 0x0001 + +//Receive Frame Header Byte Count register +#define KSZ8851_RXFHBCR_RXBC 0x0FFF + +//TXQ Command register +#define KSZ8851_TXQCR_AETFE 0x0004 +#define KSZ8851_TXQCR_TXQMAM 0x0002 +#define KSZ8851_TXQCR_METFE 0x0001 + +//RXQ Command register +#define KSZ8851_RXQCR_RXDTTS 0x1000 +#define KSZ8851_RXQCR_RXDBCTS 0x0800 +#define KSZ8851_RXQCR_RXFCTS 0x0400 +#define KSZ8851_RXQCR_RXIPHTOE 0x0200 +#define KSZ8851_RXQCR_RXDTTE 0x0080 +#define KSZ8851_RXQCR_RXDBCTE 0x0040 +#define KSZ8851_RXQCR_RXFCTE 0x0020 +#define KSZ8851_RXQCR_ADRFE 0x0010 +#define KSZ8851_RXQCR_SDA 0x0008 +#define KSZ8851_RXQCR_RRXEF 0x0001 + +//TX Frame Data Pointer register +#define KSZ8851_TXFDPR_TXFPAI 0x4000 +#define KSZ8851_TXFDPR_TXFP 0x07FF + +//RX Frame Data Pointer register +#define KSZ8851_RXFDPR_RXFPAI 0x4000 +#define KSZ8851_RXFDPR_WST 0x1000 +#define KSZ8851_RXFDPR_EMS 0x0800 +#define KSZ8851_RXFDPR_RXFP 0x07FF + +//Interrupt Enable register +#define KSZ8851_IER_LCIE 0x8000 +#define KSZ8851_IER_TXIE 0x4000 +#define KSZ8851_IER_RXIE 0x2000 +#define KSZ8851_IER_RXOIE 0x0800 +#define KSZ8851_IER_TXPSIE 0x0200 +#define KSZ8851_IER_RXPSIE 0x0100 +#define KSZ8851_IER_TXSAIE 0x0040 +#define KSZ8851_IER_RXWFDIE 0x0020 +#define KSZ8851_IER_RXMPDIE 0x0010 +#define KSZ8851_IER_LDIE 0x0008 +#define KSZ8851_IER_EDIE 0x0004 +#define KSZ8851_IER_SPIBEIE 0x0002 +#define KSZ8851_IER_DEDIE 0x0001 + +//Interrupt Status register +#define KSZ8851_ISR_LCIS 0x8000 +#define KSZ8851_ISR_TXIS 0x4000 +#define KSZ8851_ISR_RXIS 0x2000 +#define KSZ8851_ISR_RXOIS 0x0800 +#define KSZ8851_ISR_TXPSIS 0x0200 +#define KSZ8851_ISR_RXPSIS 0x0100 +#define KSZ8851_ISR_TXSAIS 0x0040 +#define KSZ8851_ISR_RXWFDIS 0x0020 +#define KSZ8851_ISR_RXMPDIS 0x0010 +#define KSZ8851_ISR_LDIS 0x0008 +#define KSZ8851_ISR_EDIS 0x0004 +#define KSZ8851_ISR_SPIBEIS 0x0002 + +//RX Frame Count & Threshold register +#define KSZ8851_RXFCTR_RXFC 0xFF00 +#define KSZ8851_RXFCTR_RXFCT 0x00FF + +//Flow Control Low Watermark register +#define KSZ8851_FCLWR_FCLWC 0x0FFF + +//Flow Control High Watermark register +#define KSZ8851_FCHWR_FCHWC 0x0FFF + +//Flow Control Overrun Watermark register +#define KSZ8851_FCOWR_FCLWC 0x0FFF + +//Chip ID and Enable register +#define KSZ8851_CIDER_FAMILY_ID 0xFF00 +#define KSZ8851_CIDER_FAMILY_ID_DEFAULT 0x8800 +#define KSZ8851_CIDER_CHIP_ID 0x00F0 +#define KSZ8851_CIDER_CHIP_ID_DEFAULT 0x0070 +#define KSZ8851_CIDER_REV_ID 0x000E +#define KSZ8851_CIDER_REV_ID_A2 0x0000 +#define KSZ8851_CIDER_REV_ID_A3 0x0002 + +//Chip Global Control register +#define KSZ8851_CGCR_LEDSEL0 0x0200 + +//Indirect Access Control register +#define KSZ8851_IACR_READ_EN 0x1000 +#define KSZ8851_IACR_TABLE_SEL 0x0C00 +#define KSZ8851_IACR_TABLE_SEL_MIB_COUNTER 0x0C00 +#define KSZ8851_IACR_INDIRECT_ADDR 0x001F + +//Power Management Event Control register +#define KSZ8851_PMECR_PME_DELAY_EN 0x4000 +#define KSZ8851_PMECR_PME_OUT_POLARITY 0x1000 +#define KSZ8851_PMECR_WOL_TO_PME_OUT_EN 0x0F00 +#define KSZ8851_PMECR_WOL_TO_PME_OUT_EN_WUP_FRAME 0x0800 +#define KSZ8851_PMECR_WOL_TO_PME_OUT_EN_MAGIC_PKT 0x0400 +#define KSZ8851_PMECR_WOL_TO_PME_OUT_EN_LINK_UP 0x0200 +#define KSZ8851_PMECR_WOL_TO_PME_OUT_EN_ENERGY_DETECT 0x0100 +#define KSZ8851_PMECR_AUTO_WUP_EN 0x0080 +#define KSZ8851_PMECR_WUP_TO_NORMAL_OP_MODE 0x0040 +#define KSZ8851_PMECR_WUP_EVENT 0x003C +#define KSZ8851_PMECR_WUP_EVENT_NONE 0x0000 +#define KSZ8851_PMECR_WUP_EVENT_ENERGY_DETECT 0x0004 +#define KSZ8851_PMECR_WUP_EVENT_LINK_UP 0x0008 +#define KSZ8851_PMECR_WUP_EVENT_MAGIC_PKT 0x0010 +#define KSZ8851_PMECR_WUP_EVENT_WUP_FRAME 0x0020 +#define KSZ8851_PMECR_PWR_MGMT_MODE 0x0003 +#define KSZ8851_PMECR_PWR_MGMT_MODE_NORMAL 0x0000 +#define KSZ8851_PMECR_PWR_MGMT_MODE_ENERGY_DETECT 0x0001 +#define KSZ8851_PMECR_PWR_MGMT_MODE_PWR_SAVING 0x0003 + +//Go-Sleep & Wake-Up Time register +#define KSZ8851_GSWUTR_WUP_TIME 0xFF00 +#define KSZ8851_GSWUTR_GO_SLEEP_TIME 0x00FF + +//PHY Reset register +#define KSZ8851_PHYRR_PHY_RESET 0x0001 + +//PHY 1 MII Basic Control register +#define KSZ8851_P1MBCR_LOCAL_LOOPBACK 0x4000 +#define KSZ8851_P1MBCR_FORCE_100 0x2000 +#define KSZ8851_P1MBCR_AN_ENABLE 0x1000 +#define KSZ8851_P1MBCR_RESTART_AN 0x0200 +#define KSZ8851_P1MBCR_FORCE_FULL_DUPLEX 0x0100 +#define KSZ8851_P1MBCR_HP_MDIX 0x0020 +#define KSZ8851_P1MBCR_FORCE_MDIX 0x0010 +#define KSZ8851_P1MBCR_DISABLE_MDIX 0x0008 +#define KSZ8851_P1MBCR_DISABLE_TRANSMIT 0x0002 +#define KSZ8851_P1MBCR_DISABLE_LED 0x0001 + +//PHY 1 MII Basic Status register +#define KSZ8851_P1MBSR_T4_CAPABLE 0x8000 +#define KSZ8851_P1MBSR_100_FULL_CAPABLE 0x4000 +#define KSZ8851_P1MBSR_100_HALF_CAPABLE 0x2000 +#define KSZ8851_P1MBSR_10_FULL_CAPABLE 0x1000 +#define KSZ8851_P1MBSR_10_HALF_CAPABLE 0x0800 +#define KSZ8851_P1MBSR_PREAMBLE_SUPPR 0x0040 +#define KSZ8851_P1MBSR_AN_COMPLETE 0x0020 +#define KSZ8851_P1MBSR_AN_CAPABLE 0x0008 +#define KSZ8851_P1MBSR_LINK_STATUS 0x0004 +#define KSZ8851_P1MBSR_JABBER_TEST 0x0002 +#define KSZ8851_P1MBSR_EXTENDED_CAPABLE 0x0001 + +//PHY 1 ID Low register +#define KSZ8851_PHY1ILR_DEFAULT 0x1430 + +//PHY 1 ID High register +#define KSZ8851_PHY1IHR_DEFAULT 0x0022 + +//PHY 1 Auto-Negotiation Advertisement register +#define KSZ8851_P1ANAR_NEXT_PAGE 0x8000 +#define KSZ8851_P1ANAR_REMOTE_FAULT 0x2000 +#define KSZ8851_P1ANAR_PAUSE 0x0400 +#define KSZ8851_P1ANAR_ADV_100_FULL 0x0100 +#define KSZ8851_P1ANAR_ADV_100_HALF 0x0080 +#define KSZ8851_P1ANAR_ADV_10_FULL 0x0040 +#define KSZ8851_P1ANAR_ADV_10_HALF 0x0020 +#define KSZ8851_P1ANAR_SELECTOR 0x001F + +//PHY 1 Auto-Negotiation Link Partner Ability register +#define KSZ8851_P1ANLPR_NEXT_PAGE 0x8000 +#define KSZ8851_P1ANLPR_LP_ACK 0x4000 +#define KSZ8851_P1ANLPR_REMOTE_FAULT 0x2000 +#define KSZ8851_P1ANLPR_PAUSE 0x0400 +#define KSZ8851_P1ANLPR_ADV_100_FULL 0x0100 +#define KSZ8851_P1ANLPR_ADV_100_HALF 0x0080 +#define KSZ8851_P1ANLPR_ADV_10_FULL 0x0040 +#define KSZ8851_P1ANLPR_ADV_10_HALF 0x0020 + +//Port 1 PHY Special Control/Status & LinkMD register +#define KSZ8851_P1SCLMD_VCT_RESULT 0x6000 +#define KSZ8851_P1SCLMD_VCT_EN 0x1000 +#define KSZ8851_P1SCLMD_FORCE_LNK 0x0800 +#define KSZ8851_P1SCLMD_REMOTE_LOOPBACK 0x0200 +#define KSZ8851_P1SCLMD_VCT_FAULT_COUNT 0x01FF + +//Port 1 Control register +#define KSZ8851_P1CR_LED_OFF 0x8000 +#define KSZ8851_P1CR_TX_DISABLE 0x4000 +#define KSZ8851_P1CR_RESTART_AN 0x2000 +#define KSZ8851_P1CR_DISABLE_AUTO_MDIX 0x0400 +#define KSZ8851_P1CR_FORCE_MDIX 0x0200 +#define KSZ8851_P1CR_AN_ENABLE 0x0080 +#define KSZ8851_P1CR_FORCE_SPEED 0x0040 +#define KSZ8851_P1CR_FORCE_DUPLEX 0x0020 +#define KSZ8851_P1CR_ADV_PAUSE 0x0010 +#define KSZ8851_P1CR_ADV_100_FULL 0x0008 +#define KSZ8851_P1CR_ADV_100_HALF 0x0004 +#define KSZ8851_P1CR_ADV_10_FULL 0x0002 +#define KSZ8851_P1CR_ADV_10_HALF 0x0001 + +//Port 1 Status register +#define KSZ8851_P1SR_HP_MDIX 0x8000 +#define KSZ8851_P1SR_POLARITY_REVERSE 0x2000 +#define KSZ8851_P1SR_OPERATION_SPEED 0x0400 +#define KSZ8851_P1SR_OPERATION_DUPLEX 0x0200 +#define KSZ8851_P1SR_MDIX_STATUS 0x0080 +#define KSZ8851_P1SR_AN_DONE 0x0040 +#define KSZ8851_P1SR_LINK_GOOD 0x0020 +#define KSZ8851_P1SR_LP_PAUSE 0x0010 +#define KSZ8851_P1SR_LP_100_FULL 0x0008 +#define KSZ8851_P1SR_LP_100_HALF 0x0004 +#define KSZ8851_P1SR_LP_10_FULL 0x0002 +#define KSZ8851_P1SR_LP_10_HALF 0x0001 //Transmit control word -#define TX_CTRL_TXIC 0x8000 -#define TX_CTRL_TXFID 0x003F +#define KSZ8851_TX_CTRL_TXIC 0x8000 +#define KSZ8851_TX_CTRL_TXFID 0x003F //C++ guard #ifdef __cplusplus diff --git a/drivers/loopback/loopback_driver.c b/drivers/loopback/loopback_driver.c index 27fd0eb6..87c697af 100644 --- a/drivers/loopback/loopback_driver.c +++ b/drivers/loopback/loopback_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/loopback/loopback_driver.h b/drivers/loopback/loopback_driver.h index 12c29f1b..ce3afaea 100644 --- a/drivers/loopback/loopback_driver.h +++ b/drivers/loopback/loopback_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LOOPBACK_DRIVER_H diff --git a/drivers/mac/a2fxxxm3_eth_driver.c b/drivers/mac/a2fxxxm3_eth_driver.c index 870265f1..01be2d1c 100644 --- a/drivers/mac/a2fxxxm3_eth_driver.c +++ b/drivers/mac/a2fxxxm3_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/a2fxxxm3_eth_driver.h b/drivers/mac/a2fxxxm3_eth_driver.h index 3b4722a6..64c00784 100644 --- a/drivers/mac/a2fxxxm3_eth_driver.h +++ b/drivers/mac/a2fxxxm3_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _A2FXXXM3_ETH_DRIVER_H diff --git a/drivers/mac/am335x_eth_driver.c b/drivers/mac/am335x_eth_driver.c index 96c8dc26..433156b2 100644 --- a/drivers/mac/am335x_eth_driver.c +++ b/drivers/mac/am335x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -86,7 +86,7 @@ static Am335xTxBufferDesc txBufferDesc2[AM335X_ETH_TX_BUFFER_COUNT]; #pragma location = AM335X_ETH_RAM_CPPI_SECTION static Am335xRxBufferDesc rxBufferDesc[AM335X_ETH_RX_BUFFER_COUNT]; -//Keil MDK-ARM or GCC compiler? +//GCC compiler? #else //Transmit buffer (port 1) @@ -1804,7 +1804,7 @@ error_t am335xEthAddVlanEntry(uint_t port, uint_t vlanId) //Add a new entry to the ALE table am335xEthWriteEntry(index, &entry); - //Sucessful processing + //Successful processing error = NO_ERROR; } else @@ -1875,7 +1875,7 @@ error_t am335xEthAddVlanAddrEntry(uint_t port, uint_t vlanId, MacAddr *macAddr) //Add a new entry to the ALE table am335xEthWriteEntry(index, &entry); - //Sucessful processing + //Successful processing error = NO_ERROR; } else @@ -1917,7 +1917,7 @@ error_t am335xEthDeleteVlanAddrEntry(uint_t port, uint_t vlanId, MacAddr *macAdd //Update the ALE table am335xEthWriteEntry(index, &entry); - //Sucessful processing + //Successful processing error = NO_ERROR; } else diff --git a/drivers/mac/am335x_eth_driver.h b/drivers/mac/am335x_eth_driver.h index 02646fda..e2e121a2 100644 --- a/drivers/mac/am335x_eth_driver.h +++ b/drivers/mac/am335x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _AM335X_ETH_DRIVER_H diff --git a/drivers/mac/aps3_eth_driver.c b/drivers/mac/aps3_eth_driver.c index a9db4c21..b37ed7c6 100644 --- a/drivers/mac/aps3_eth_driver.c +++ b/drivers/mac/aps3_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/aps3_eth_driver.h b/drivers/mac/aps3_eth_driver.h index e31b68da..ed6d5399 100644 --- a/drivers/mac/aps3_eth_driver.h +++ b/drivers/mac/aps3_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _APS3_ETH_DRIVER_H diff --git a/drivers/mac/avr32_eth_driver.c b/drivers/mac/avr32_eth_driver.c index b10be465..1251da21 100644 --- a/drivers/mac/avr32_eth_driver.c +++ b/drivers/mac/avr32_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/avr32_eth_driver.h b/drivers/mac/avr32_eth_driver.h index d15e5765..49b02d6e 100644 --- a/drivers/mac/avr32_eth_driver.h +++ b/drivers/mac/avr32_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _AVR32_ETH_DRIVER_H diff --git a/drivers/mac/efm32gg11_eth_driver.c b/drivers/mac/efm32gg11_eth_driver.c index cfc1fdf3..cc20a2ee 100644 --- a/drivers/mac/efm32gg11_eth_driver.c +++ b/drivers/mac/efm32gg11_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/efm32gg11_eth_driver.h b/drivers/mac/efm32gg11_eth_driver.h index eacc5b4c..c0035328 100644 --- a/drivers/mac/efm32gg11_eth_driver.h +++ b/drivers/mac/efm32gg11_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _EFM32GG11_ETH_DRIVER_H diff --git a/drivers/mac/esp32_eth_driver.c b/drivers/mac/esp32_eth_driver.c index 547bd050..e9c55550 100644 --- a/drivers/mac/esp32_eth_driver.c +++ b/drivers/mac/esp32_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -403,7 +403,6 @@ void esp32EthTick(NetInterface *interface) void esp32EthEnableIrq(NetInterface *interface) { - //Valid Ethernet PHY or switch driver? if(interface->phyDriver != NULL) { @@ -429,7 +428,6 @@ void esp32EthEnableIrq(NetInterface *interface) void esp32EthDisableIrq(NetInterface *interface) { - //Valid Ethernet PHY or switch driver? if(interface->phyDriver != NULL) { diff --git a/drivers/mac/esp32_eth_driver.h b/drivers/mac/esp32_eth_driver.h index ef821485..c483af88 100644 --- a/drivers/mac/esp32_eth_driver.h +++ b/drivers/mac/esp32_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ESP32_ETH_DRIVER_H diff --git a/drivers/mac/f28m35x_eth_driver.c b/drivers/mac/f28m35x_eth_driver.c index 9a6f6980..31e8cb80 100644 --- a/drivers/mac/f28m35x_eth_driver.c +++ b/drivers/mac/f28m35x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -56,7 +56,7 @@ static uint8_t txBuffer[ETH_MAX_FRAME_SIZE + 2]; #pragma data_alignment = 4 static uint8_t rxBuffer[ETH_MAX_FRAME_SIZE]; -//Keil MDK-ARM or GCC compiler? +//GCC compiler? #else //Transmit buffer diff --git a/drivers/mac/f28m35x_eth_driver.h b/drivers/mac/f28m35x_eth_driver.h index b9637c18..6b679687 100644 --- a/drivers/mac/f28m35x_eth_driver.h +++ b/drivers/mac/f28m35x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _F28M35X_ETH_DRIVER_H diff --git a/drivers/mac/fm4_eth_driver.c b/drivers/mac/fm4_eth_driver.c index 3566b0a6..4d8314a0 100644 --- a/drivers/mac/fm4_eth_driver.c +++ b/drivers/mac/fm4_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/fm4_eth_driver.h b/drivers/mac/fm4_eth_driver.h index 10942e16..87a6a397 100644 --- a/drivers/mac/fm4_eth_driver.h +++ b/drivers/mac/fm4_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _FM4_ETH_DRIVER_H diff --git a/drivers/mac/gd32f307_eth_driver.c b/drivers/mac/gd32f307_eth_driver.c index e3dfefe9..fe20707e 100644 --- a/drivers/mac/gd32f307_eth_driver.c +++ b/drivers/mac/gd32f307_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/gd32f307_eth_driver.h b/drivers/mac/gd32f307_eth_driver.h index 61235dd2..c6273e23 100644 --- a/drivers/mac/gd32f307_eth_driver.h +++ b/drivers/mac/gd32f307_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _GD32F307_ETH_DRIVER_H diff --git a/drivers/mac/lm3s_eth_driver.c b/drivers/mac/lm3s_eth_driver.c index 4e6da0db..f8d54e87 100644 --- a/drivers/mac/lm3s_eth_driver.c +++ b/drivers/mac/lm3s_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/lm3s_eth_driver.h b/drivers/mac/lm3s_eth_driver.h index 89c39f82..84cf7468 100644 --- a/drivers/mac/lm3s_eth_driver.h +++ b/drivers/mac/lm3s_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LM3S_ETH_DRIVER_H diff --git a/drivers/mac/lpc175x_eth_driver.c b/drivers/mac/lpc175x_eth_driver.c index 8e9fb3a9..4ac4c538 100644 --- a/drivers/mac/lpc175x_eth_driver.c +++ b/drivers/mac/lpc175x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/lpc175x_eth_driver.h b/drivers/mac/lpc175x_eth_driver.h index 30d943ad..c8fd276c 100644 --- a/drivers/mac/lpc175x_eth_driver.h +++ b/drivers/mac/lpc175x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LPC175X_ETH_DRIVER_H diff --git a/drivers/mac/lpc176x_eth_driver.c b/drivers/mac/lpc176x_eth_driver.c index 0c7d7979..9538fc42 100644 --- a/drivers/mac/lpc176x_eth_driver.c +++ b/drivers/mac/lpc176x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/lpc176x_eth_driver.h b/drivers/mac/lpc176x_eth_driver.h index f82a8050..e9b0a01f 100644 --- a/drivers/mac/lpc176x_eth_driver.h +++ b/drivers/mac/lpc176x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LPC176X_ETH_DRIVER_H diff --git a/drivers/mac/lpc178x_eth_driver.c b/drivers/mac/lpc178x_eth_driver.c index d8832921..dc4e55fa 100644 --- a/drivers/mac/lpc178x_eth_driver.c +++ b/drivers/mac/lpc178x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/lpc178x_eth_driver.h b/drivers/mac/lpc178x_eth_driver.h index f2ee512b..961ef1d6 100644 --- a/drivers/mac/lpc178x_eth_driver.h +++ b/drivers/mac/lpc178x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LPC178X_ETH_DRIVER_H diff --git a/drivers/mac/lpc18xx_eth_driver.c b/drivers/mac/lpc18xx_eth_driver.c index 0fc01b6d..caa3ddb5 100644 --- a/drivers/mac/lpc18xx_eth_driver.c +++ b/drivers/mac/lpc18xx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/lpc18xx_eth_driver.h b/drivers/mac/lpc18xx_eth_driver.h index 5aa9f5fb..c1143935 100644 --- a/drivers/mac/lpc18xx_eth_driver.h +++ b/drivers/mac/lpc18xx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LPC18XX_ETH_DRIVER_H diff --git a/drivers/mac/lpc23xx_eth_driver.c b/drivers/mac/lpc23xx_eth_driver.c index 12a36290..2760d832 100644 --- a/drivers/mac/lpc23xx_eth_driver.c +++ b/drivers/mac/lpc23xx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/lpc23xx_eth_driver.h b/drivers/mac/lpc23xx_eth_driver.h index 9b5aeb18..1678c545 100644 --- a/drivers/mac/lpc23xx_eth_driver.h +++ b/drivers/mac/lpc23xx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LPC23XX_ETH_DRIVER_H diff --git a/drivers/mac/lpc43xx_eth_driver.c b/drivers/mac/lpc43xx_eth_driver.c index aa822d38..6ebbc6a6 100644 --- a/drivers/mac/lpc43xx_eth_driver.c +++ b/drivers/mac/lpc43xx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/lpc43xx_eth_driver.h b/drivers/mac/lpc43xx_eth_driver.h index e4750336..39078c1a 100644 --- a/drivers/mac/lpc43xx_eth_driver.h +++ b/drivers/mac/lpc43xx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LPC43XX_ETH_DRIVER_H diff --git a/drivers/mac/lpc546xx_eth_driver.c b/drivers/mac/lpc54xxx_eth_driver.c similarity index 77% rename from drivers/mac/lpc546xx_eth_driver.c rename to drivers/mac/lpc54xxx_eth_driver.c index 711f1cec..e5adf102 100644 --- a/drivers/mac/lpc546xx_eth_driver.c +++ b/drivers/mac/lpc54xxx_eth_driver.c @@ -1,12 +1,12 @@ /** - * @file lpc546xx_eth_driver.c - * @brief LPC54608/LPC54618/LPC54628 Ethernet MAC driver + * @file lpc54xxx_eth_driver.c + * @brief LPC540xx/LPC546xx Ethernet MAC driver * * @section License * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -39,7 +39,7 @@ #include "fsl_iocon.h" #include "fsl_gpio.h" #include "core/net.h" -#include "drivers/mac/lpc546xx_eth_driver.h" +#include "drivers/mac/lpc54xxx_eth_driver.h" #include "debug.h" //Underlying network interface @@ -50,31 +50,31 @@ static NetInterface *nicDriverInterface; //Transmit buffer #pragma data_alignment = 4 -static uint8_t txBuffer[LPC546XX_ETH_TX_BUFFER_COUNT][LPC546XX_ETH_TX_BUFFER_SIZE]; +static uint8_t txBuffer[LPC54XXX_ETH_TX_BUFFER_COUNT][LPC54XXX_ETH_TX_BUFFER_SIZE]; //Receive buffer #pragma data_alignment = 4 -static uint8_t rxBuffer[LPC546XX_ETH_RX_BUFFER_COUNT][LPC546XX_ETH_RX_BUFFER_SIZE]; +static uint8_t rxBuffer[LPC54XXX_ETH_RX_BUFFER_COUNT][LPC54XXX_ETH_RX_BUFFER_SIZE]; //Transmit DMA descriptors #pragma data_alignment = 4 -static Lpc546xxTxDmaDesc txDmaDesc[LPC546XX_ETH_TX_BUFFER_COUNT]; +static Lpc54xxxTxDmaDesc txDmaDesc[LPC54XXX_ETH_TX_BUFFER_COUNT]; //Receive DMA descriptors #pragma data_alignment = 4 -static Lpc546xxRxDmaDesc rxDmaDesc[LPC546XX_ETH_RX_BUFFER_COUNT]; +static Lpc54xxxRxDmaDesc rxDmaDesc[LPC54XXX_ETH_RX_BUFFER_COUNT]; //Keil MDK-ARM or GCC compiler? #else //Transmit buffer -static uint8_t txBuffer[LPC546XX_ETH_TX_BUFFER_COUNT][LPC546XX_ETH_TX_BUFFER_SIZE] +static uint8_t txBuffer[LPC54XXX_ETH_TX_BUFFER_COUNT][LPC54XXX_ETH_TX_BUFFER_SIZE] __attribute__((aligned(4))); //Receive buffer -static uint8_t rxBuffer[LPC546XX_ETH_RX_BUFFER_COUNT][LPC546XX_ETH_RX_BUFFER_SIZE] +static uint8_t rxBuffer[LPC54XXX_ETH_RX_BUFFER_COUNT][LPC54XXX_ETH_RX_BUFFER_SIZE] __attribute__((aligned(4))); //Transmit DMA descriptors -static Lpc546xxTxDmaDesc txDmaDesc[LPC546XX_ETH_TX_BUFFER_COUNT] +static Lpc54xxxTxDmaDesc txDmaDesc[LPC54XXX_ETH_TX_BUFFER_COUNT] __attribute__((aligned(4))); //Receive DMA descriptors -static Lpc546xxRxDmaDesc rxDmaDesc[LPC546XX_ETH_RX_BUFFER_COUNT] +static Lpc54xxxRxDmaDesc rxDmaDesc[LPC54XXX_ETH_RX_BUFFER_COUNT] __attribute__((aligned(4))); #endif @@ -86,23 +86,23 @@ static uint_t rxIndex; /** - * @brief LPC546xx Ethernet MAC driver + * @brief LPC54xxx Ethernet MAC driver **/ -const NicDriver lpc546xxEthDriver = +const NicDriver lpc54xxxEthDriver = { NIC_TYPE_ETHERNET, ETH_MTU, - lpc546xxEthInit, - lpc546xxEthTick, - lpc546xxEthEnableIrq, - lpc546xxEthDisableIrq, - lpc546xxEthEventHandler, - lpc546xxEthSendPacket, - lpc546xxEthUpdateMacAddrFilter, - lpc546xxEthUpdateMacConfig, - lpc546xxEthWritePhyReg, - lpc546xxEthReadPhyReg, + lpc54xxxEthInit, + lpc54xxxEthTick, + lpc54xxxEthEnableIrq, + lpc54xxxEthDisableIrq, + lpc54xxxEthEventHandler, + lpc54xxxEthSendPacket, + lpc54xxxEthUpdateMacAddrFilter, + lpc54xxxEthUpdateMacConfig, + lpc54xxxEthWritePhyReg, + lpc54xxxEthReadPhyReg, TRUE, TRUE, TRUE, @@ -111,17 +111,17 @@ const NicDriver lpc546xxEthDriver = /** - * @brief LPC546xx Ethernet MAC initialization + * @brief LPC54xxx Ethernet MAC initialization * @param[in] interface Underlying network interface * @return Error code **/ -error_t lpc546xxEthInit(NetInterface *interface) +error_t lpc54xxxEthInit(NetInterface *interface) { error_t error; //Debug message - TRACE_INFO("Initializing LPC546xx Ethernet MAC...\r\n"); + TRACE_INFO("Initializing LPC54xxx Ethernet MAC...\r\n"); //Save underlying network interface nicDriverInterface = interface; @@ -132,7 +132,7 @@ error_t lpc546xxEthInit(NetInterface *interface) RESET_PeripheralReset(kETH_RST_SHIFT_RSTn); //GPIO configuration - lpc546xxEthInitGpio(interface); + lpc54xxxEthInitGpio(interface); //Perform a software reset ENET->DMA_MODE |= ENET_DMA_MODE_SWR_MASK; @@ -196,7 +196,7 @@ error_t lpc546xxEthInit(NetInterface *interface) //Configure RX features ENET->DMA_CH[0].DMA_CHX_RX_CTRL = ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(1) | - ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(LPC546XX_ETH_RX_BUFFER_SIZE / 4); + ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(LPC54XXX_ETH_RX_BUFFER_SIZE / 4); //Enable store and forward mode for transmission ENET->MTL_QUEUE[0].MTL_TXQX_OP_MODE |= ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(7) | @@ -208,7 +208,7 @@ error_t lpc546xxEthInit(NetInterface *interface) ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK; //Initialize DMA descriptor lists - lpc546xxEthInitDmaDesc(interface); + lpc54xxxEthInitDmaDesc(interface); //Disable MAC interrupts ENET->MAC_INTR_EN = 0; @@ -218,11 +218,11 @@ error_t lpc546xxEthInit(NetInterface *interface) ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK | ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK; //Set priority grouping (3 bits for pre-emption priority, no bits for subpriority) - NVIC_SetPriorityGrouping(LPC546XX_ETH_IRQ_PRIORITY_GROUPING); + NVIC_SetPriorityGrouping(LPC54XXX_ETH_IRQ_PRIORITY_GROUPING); //Configure Ethernet interrupt priority - NVIC_SetPriority(ETHERNET_IRQn, NVIC_EncodePriority(LPC546XX_ETH_IRQ_PRIORITY_GROUPING, - LPC546XX_ETH_IRQ_GROUP_PRIORITY, LPC546XX_ETH_IRQ_SUB_PRIORITY)); + NVIC_SetPriority(ETHERNET_IRQn, NVIC_EncodePriority(LPC54XXX_ETH_IRQ_PRIORITY_GROUPING, + LPC54XXX_ETH_IRQ_GROUP_PRIORITY, LPC54XXX_ETH_IRQ_SUB_PRIORITY)); //Enable MAC transmission and reception ENET->MAC_CONFIG |= ENET_MAC_CONFIG_TE_MASK | ENET_MAC_CONFIG_RE_MASK; @@ -239,18 +239,25 @@ error_t lpc546xxEthInit(NetInterface *interface) } -//LPCXpresso54608 evaluation board? -#if defined(USE_LPCXPRESSO_54608) +//LPCXpresso54S018, LPCXpresso54S018M, LPCXpresso54608, LPCXpresso54628 or +//LPC54018-IoT-Module evaluation board? +#if defined(USE_LPCXPRESSO_54S018) || defined(USE_LPCXPRESSO_54S018M) || \ + defined(USE_LPCXPRESSO_54608) || defined(USE_LPCXPRESSO_54628) || \ + defined(USE_LPC54018_IOT_MODULE) /** * @brief GPIO configuration * @param[in] interface Underlying network interface **/ -void lpc546xxEthInitGpio(NetInterface *interface) +void lpc54xxxEthInitGpio(NetInterface *interface) { gpio_pin_config_t pinConfig; +//LPCXpresso54S018, LPCXpresso54608, LPCXpresso54628 or LPC54018-IoT-Module +//evaluation board? +#if defined(USE_LPCXPRESSO_54S018) || defined(USE_LPCXPRESSO_54608) || \ + defined(USE_LPCXPRESSO_54628) || defined(USE_LPC54018_IOT_MODULE) //Select RMII interface mode SYSCON->ETHPHYSEL |= SYSCON_ETHPHYSEL_PHY_SEL_MASK; @@ -259,54 +266,117 @@ void lpc546xxEthInitGpio(NetInterface *interface) //Enable GPIO clocks CLOCK_EnableClock(kCLOCK_Gpio0); + CLOCK_EnableClock(kCLOCK_Gpio2); CLOCK_EnableClock(kCLOCK_Gpio4); - //Configure ENET_TXD1 (PA0_17) + //Configure ENET_TXD1 (P0_17) IOCON_PinMuxSet(IOCON, 0, 17, IOCON_FUNC7 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); - //Configure ENET_TXD0 (PA4_8) + //Configure ENET_TXD0 (P4_8) IOCON_PinMuxSet(IOCON, 4, 8, IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); - //Configure ENET_RX_DV (PA4_10) + //Configure ENET_RX_DV (P4_10) IOCON_PinMuxSet(IOCON, 4, 10, IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); - //Configure ENET_RXD0 (PA4_11) + //Configure ENET_RXD0 (P4_11) IOCON_PinMuxSet(IOCON, 4, 11, IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); - //Configure ENET_RXD1 (PA4_12) + //Configure ENET_RXD1 (P4_12) IOCON_PinMuxSet(IOCON, 4, 12, IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); - //Configure ENET_TX_EN (PA4_13) + //Configure ENET_TX_EN (P4_13) IOCON_PinMuxSet(IOCON, 4, 13, IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); - //Configure ENET_RX_CLK (PA4_14) + //Configure ENET_RX_CLK (P4_14) IOCON_PinMuxSet(IOCON, 4, 14, IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); - //Configure ENET_MDC (PA4_15) + //Configure ENET_MDC (P4_15) IOCON_PinMuxSet(IOCON, 4, 15, IOCON_FUNC1 | IOCON_MODE_INACT | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); - //Configure ENET_MDIO (PA4_16) + //Configure ENET_MDIO (P4_16) IOCON_PinMuxSet(IOCON, 4, 16, IOCON_FUNC1 | IOCON_MODE_PULLUP | IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); - //Configure ENET_RST as an output + //Configure ENET_RST (P2_26) as an output pinConfig.pinDirection = kGPIO_DigitalOutput; pinConfig.outputLogic = 0; GPIO_PinInit(GPIO, 2, 26, &pinConfig); //Reset PHY transceiver (hard reset) - GPIO_WritePinOutput(GPIO, 2, 26, 0); + GPIO_PinWrite(GPIO, 2, 26, 0); sleep(10); - GPIO_WritePinOutput(GPIO, 2, 26, 1); + GPIO_PinWrite(GPIO, 2, 26, 1); sleep(10); + +//LPCXpresso54S018M evaluation board? +#elif defined(USE_LPCXPRESSO_54S018M) + //Select RMII interface mode + SYSCON->ETHPHYSEL |= SYSCON_ETHPHYSEL_PHY_SEL_MASK; + + //Enable IOCON clock + CLOCK_EnableClock(kCLOCK_Iocon); + + //Enable GPIO clocks + CLOCK_EnableClock(kCLOCK_Gpio0); + CLOCK_EnableClock(kCLOCK_Gpio1); + CLOCK_EnableClock(kCLOCK_Gpio2); + CLOCK_EnableClock(kCLOCK_Gpio4); + + //Configure ENET_TXD1 (P0_17) + IOCON_PinMuxSet(IOCON, 0, 17, IOCON_FUNC7 | IOCON_MODE_INACT | + IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + + //Configure ENET_MDC (P1_16) + IOCON_PinMuxSet(IOCON, 1, 16, IOCON_FUNC1 | IOCON_MODE_INACT | + IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + + //Configure ENET_MDIO (P1_23) + IOCON_PinMuxSet(IOCON, 1, 23, IOCON_FUNC4 | IOCON_MODE_PULLUP | + IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + + //Configure ENET_TXD0 (P4_8) + IOCON_PinMuxSet(IOCON, 4, 8, IOCON_FUNC1 | IOCON_MODE_INACT | + IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + + //Configure ENET_RX_DV (P4_10) + IOCON_PinMuxSet(IOCON, 4, 10, IOCON_FUNC1 | IOCON_MODE_INACT | + IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + + //Configure ENET_RXD0 (P4_11) + IOCON_PinMuxSet(IOCON, 4, 11, IOCON_FUNC1 | IOCON_MODE_INACT | + IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + + //Configure ENET_RXD1 (P4_12) + IOCON_PinMuxSet(IOCON, 4, 12, IOCON_FUNC1 | IOCON_MODE_INACT | + IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + + //Configure ENET_TX_EN (P4_13) + IOCON_PinMuxSet(IOCON, 4, 13, IOCON_FUNC1 | IOCON_MODE_INACT | + IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + + //Configure ENET_RX_CLK (P4_14) + IOCON_PinMuxSet(IOCON, 4, 14, IOCON_FUNC1 | IOCON_MODE_INACT | + IOCON_DIGITAL_EN | IOCON_INPFILT_OFF); + + //Configure ENET_RST (P2_26) as an output + pinConfig.pinDirection = kGPIO_DigitalOutput; + pinConfig.outputLogic = 0; + GPIO_PinInit(GPIO, 2, 26, &pinConfig); + + //Reset PHY transceiver (hard reset) + GPIO_PinWrite(GPIO, 2, 26, 0); + sleep(10); + GPIO_PinWrite(GPIO, 2, 26, 1); + sleep(10); +#endif } #endif @@ -317,12 +387,12 @@ void lpc546xxEthInitGpio(NetInterface *interface) * @param[in] interface Underlying network interface **/ -void lpc546xxEthInitDmaDesc(NetInterface *interface) +void lpc54xxxEthInitDmaDesc(NetInterface *interface) { uint_t i; //Initialize TX DMA descriptor list - for(i = 0; i < LPC546XX_ETH_TX_BUFFER_COUNT; i++) + for(i = 0; i < LPC54XXX_ETH_TX_BUFFER_COUNT; i++) { //The descriptor is initially owned by the application txDmaDesc[i].tdes0 = 0; @@ -335,7 +405,7 @@ void lpc546xxEthInitDmaDesc(NetInterface *interface) txIndex = 0; //Initialize RX DMA descriptor list - for(i = 0; i < LPC546XX_ETH_RX_BUFFER_COUNT; i++) + for(i = 0; i < LPC54XXX_ETH_RX_BUFFER_COUNT; i++) { //The descriptor is initially owned by the DMA rxDmaDesc[i].rdes0 = (uint32_t) rxBuffer[i]; @@ -350,17 +420,17 @@ void lpc546xxEthInitDmaDesc(NetInterface *interface) //Start location of the TX descriptor list ENET->DMA_CH[0].DMA_CHX_TXDESC_LIST_ADDR = (uint32_t) &txDmaDesc[0]; //Length of the transmit descriptor ring - ENET->DMA_CH[0].DMA_CHX_TXDESC_RING_LENGTH = LPC546XX_ETH_TX_BUFFER_COUNT - 1; + ENET->DMA_CH[0].DMA_CHX_TXDESC_RING_LENGTH = LPC54XXX_ETH_TX_BUFFER_COUNT - 1; //Start location of the RX descriptor list ENET->DMA_CH[0].DMA_CHX_RXDESC_LIST_ADDR = (uint32_t) &rxDmaDesc[0]; //Length of the receive descriptor ring - ENET->DMA_CH[0].DMA_CHX_RXDESC_RING_LENGTH = LPC546XX_ETH_RX_BUFFER_COUNT - 1; + ENET->DMA_CH[0].DMA_CHX_RXDESC_RING_LENGTH = LPC54XXX_ETH_RX_BUFFER_COUNT - 1; } /** - * @brief LPC546xx Ethernet MAC timer handler + * @brief LPC54xxx Ethernet MAC timer handler * * This routine is periodically called by the TCP/IP stack to handle periodic * operations such as polling the link state @@ -368,7 +438,7 @@ void lpc546xxEthInitDmaDesc(NetInterface *interface) * @param[in] interface Underlying network interface **/ -void lpc546xxEthTick(NetInterface *interface) +void lpc54xxxEthTick(NetInterface *interface) { //Valid Ethernet PHY or switch driver? if(interface->phyDriver != NULL) @@ -393,7 +463,7 @@ void lpc546xxEthTick(NetInterface *interface) * @param[in] interface Underlying network interface **/ -void lpc546xxEthEnableIrq(NetInterface *interface) +void lpc54xxxEthEnableIrq(NetInterface *interface) { //Enable Ethernet MAC interrupts NVIC_EnableIRQ(ETHERNET_IRQn); @@ -421,7 +491,7 @@ void lpc546xxEthEnableIrq(NetInterface *interface) * @param[in] interface Underlying network interface **/ -void lpc546xxEthDisableIrq(NetInterface *interface) +void lpc54xxxEthDisableIrq(NetInterface *interface) { //Disable Ethernet MAC interrupts NVIC_DisableIRQ(ETHERNET_IRQn); @@ -445,7 +515,7 @@ void lpc546xxEthDisableIrq(NetInterface *interface) /** - * @brief LPC546xx Ethernet MAC interrupt service routine + * @brief LPC54xxx Ethernet MAC interrupt service routine **/ void ETHERNET_IRQHandler(void) @@ -497,11 +567,11 @@ void ETHERNET_IRQHandler(void) /** - * @brief LPC546xx Ethernet MAC event handler + * @brief LPC54xxx Ethernet MAC event handler * @param[in] interface Underlying network interface **/ -void lpc546xxEthEventHandler(NetInterface *interface) +void lpc54xxxEthEventHandler(NetInterface *interface) { error_t error; @@ -515,7 +585,7 @@ void lpc546xxEthEventHandler(NetInterface *interface) do { //Read incoming packet - error = lpc546xxEthReceivePacket(interface); + error = lpc54xxxEthReceivePacket(interface); //No more data in the receive buffer? } while(error != ERROR_BUFFER_EMPTY); @@ -537,7 +607,7 @@ void lpc546xxEthEventHandler(NetInterface *interface) * @return Error code **/ -error_t lpc546xxEthSendPacket(NetInterface *interface, +error_t lpc54xxxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary) { size_t length; @@ -546,7 +616,7 @@ error_t lpc546xxEthSendPacket(NetInterface *interface, length = netBufferGetLength(buffer) - offset; //Check the frame length - if(length > LPC546XX_ETH_TX_BUFFER_SIZE) + if(length > LPC54XXX_ETH_TX_BUFFER_SIZE) { //The transmitter can accept another packet osSetEvent(&interface->nicTxEvent); @@ -576,7 +646,7 @@ error_t lpc546xxEthSendPacket(NetInterface *interface, ENET->DMA_CH[0].DMA_CHX_TXDESC_TAIL_PTR = 0; //Increment index and wrap around if necessary - if(++txIndex >= LPC546XX_ETH_TX_BUFFER_COUNT) + if(++txIndex >= LPC54XXX_ETH_TX_BUFFER_COUNT) { txIndex = 0; } @@ -599,7 +669,7 @@ error_t lpc546xxEthSendPacket(NetInterface *interface, * @return Error code **/ -error_t lpc546xxEthReceivePacket(NetInterface *interface) +error_t lpc54xxxEthReceivePacket(NetInterface *interface) { error_t error; size_t n; @@ -618,7 +688,7 @@ error_t lpc546xxEthReceivePacket(NetInterface *interface) //Retrieve the length of the frame n = rxDmaDesc[rxIndex].rdes3 & ENET_RDES3_PL; //Limit the number of data to read - n = MIN(n, LPC546XX_ETH_RX_BUFFER_SIZE); + n = MIN(n, LPC54XXX_ETH_RX_BUFFER_SIZE); //Additional options can be passed to the stack along with the packet ancillary = NET_DEFAULT_RX_ANCILLARY; @@ -647,7 +717,7 @@ error_t lpc546xxEthReceivePacket(NetInterface *interface) rxDmaDesc[rxIndex].rdes3 = ENET_RDES3_OWN | ENET_RDES3_IOC | ENET_RDES3_BUF1V; //Increment index and wrap around if necessary - if(++rxIndex >= LPC546XX_ETH_RX_BUFFER_COUNT) + if(++rxIndex >= LPC54XXX_ETH_RX_BUFFER_COUNT) { rxIndex = 0; } @@ -674,7 +744,7 @@ error_t lpc546xxEthReceivePacket(NetInterface *interface) * @return Error code **/ -error_t lpc546xxEthUpdateMacAddrFilter(NetInterface *interface) +error_t lpc54xxxEthUpdateMacAddrFilter(NetInterface *interface) { uint_t i; bool_t acceptMulticast; @@ -724,7 +794,7 @@ error_t lpc546xxEthUpdateMacAddrFilter(NetInterface *interface) * @return Error code **/ -error_t lpc546xxEthUpdateMacConfig(NetInterface *interface) +error_t lpc54xxxEthUpdateMacConfig(NetInterface *interface) { uint32_t config; @@ -767,7 +837,7 @@ error_t lpc546xxEthUpdateMacConfig(NetInterface *interface) * @param[in] data Register value **/ -void lpc546xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, +void lpc54xxxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data) { uint32_t temp; @@ -809,7 +879,7 @@ void lpc546xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, * @return Register value **/ -uint16_t lpc546xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, +uint16_t lpc54xxxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr) { uint16_t data; diff --git a/drivers/mac/lpc546xx_eth_driver.h b/drivers/mac/lpc54xxx_eth_driver.h similarity index 67% rename from drivers/mac/lpc546xx_eth_driver.h rename to drivers/mac/lpc54xxx_eth_driver.h index da5fcb75..119dbb6c 100644 --- a/drivers/mac/lpc546xx_eth_driver.h +++ b/drivers/mac/lpc54xxx_eth_driver.h @@ -1,12 +1,12 @@ /** - * @file lpc546xx_eth_driver.h - * @brief LPC54608/LPC54618/LPC54628 Ethernet MAC driver + * @file lpc54xxx_eth_driver.h + * @brief LPC540xx/LPC546xx Ethernet MAC driver * * @section License * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,62 +25,62 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ -#ifndef _LPC546XX_ETH_DRIVER_H -#define _LPC546XX_ETH_DRIVER_H +#ifndef _LPC54XXX_ETH_DRIVER_H +#define _LPC54XXX_ETH_DRIVER_H //Dependencies #include "core/nic.h" //Number of TX buffers -#ifndef LPC546XX_ETH_TX_BUFFER_COUNT - #define LPC546XX_ETH_TX_BUFFER_COUNT 3 -#elif (LPC546XX_ETH_TX_BUFFER_COUNT < 1) - #error LPC546XX_ETH_TX_BUFFER_COUNT parameter is not valid +#ifndef LPC54XXX_ETH_TX_BUFFER_COUNT + #define LPC54XXX_ETH_TX_BUFFER_COUNT 3 +#elif (LPC54XXX_ETH_TX_BUFFER_COUNT < 1) + #error LPC54XXX_ETH_TX_BUFFER_COUNT parameter is not valid #endif //TX buffer size -#ifndef LPC546XX_ETH_TX_BUFFER_SIZE - #define LPC546XX_ETH_TX_BUFFER_SIZE 1536 -#elif (LPC546XX_ETH_TX_BUFFER_SIZE != 1536) - #error LPC546XX_ETH_TX_BUFFER_SIZE parameter is not valid +#ifndef LPC54XXX_ETH_TX_BUFFER_SIZE + #define LPC54XXX_ETH_TX_BUFFER_SIZE 1536 +#elif (LPC54XXX_ETH_TX_BUFFER_SIZE != 1536) + #error LPC54XXX_ETH_TX_BUFFER_SIZE parameter is not valid #endif //Number of RX buffers -#ifndef LPC546XX_ETH_RX_BUFFER_COUNT - #define LPC546XX_ETH_RX_BUFFER_COUNT 6 -#elif (LPC546XX_ETH_RX_BUFFER_COUNT < 1) - #error LPC546XX_ETH_RX_BUFFER_COUNT parameter is not valid +#ifndef LPC54XXX_ETH_RX_BUFFER_COUNT + #define LPC54XXX_ETH_RX_BUFFER_COUNT 6 +#elif (LPC54XXX_ETH_RX_BUFFER_COUNT < 1) + #error LPC54XXX_ETH_RX_BUFFER_COUNT parameter is not valid #endif //RX buffer size -#ifndef LPC546XX_ETH_RX_BUFFER_SIZE - #define LPC546XX_ETH_RX_BUFFER_SIZE 1536 -#elif (LPC546XX_ETH_RX_BUFFER_SIZE != 1536) - #error LPC546XX_ETH_RX_BUFFER_SIZE parameter is not valid +#ifndef LPC54XXX_ETH_RX_BUFFER_SIZE + #define LPC54XXX_ETH_RX_BUFFER_SIZE 1536 +#elif (LPC54XXX_ETH_RX_BUFFER_SIZE != 1536) + #error LPC54XXX_ETH_RX_BUFFER_SIZE parameter is not valid #endif //Interrupt priority grouping -#ifndef LPC546XX_ETH_IRQ_PRIORITY_GROUPING - #define LPC546XX_ETH_IRQ_PRIORITY_GROUPING 4 -#elif (LPC546XX_ETH_IRQ_PRIORITY_GROUPING < 0) - #error LPC546XX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid +#ifndef LPC54XXX_ETH_IRQ_PRIORITY_GROUPING + #define LPC54XXX_ETH_IRQ_PRIORITY_GROUPING 4 +#elif (LPC54XXX_ETH_IRQ_PRIORITY_GROUPING < 0) + #error LPC54XXX_ETH_IRQ_PRIORITY_GROUPING parameter is not valid #endif //Ethernet interrupt group priority -#ifndef LPC546XX_ETH_IRQ_GROUP_PRIORITY - #define LPC546XX_ETH_IRQ_GROUP_PRIORITY 6 -#elif (LPC546XX_ETH_IRQ_GROUP_PRIORITY < 0) - #error LPC546XX_ETH_IRQ_GROUP_PRIORITY parameter is not valid +#ifndef LPC54XXX_ETH_IRQ_GROUP_PRIORITY + #define LPC54XXX_ETH_IRQ_GROUP_PRIORITY 6 +#elif (LPC54XXX_ETH_IRQ_GROUP_PRIORITY < 0) + #error LPC54XXX_ETH_IRQ_GROUP_PRIORITY parameter is not valid #endif //Ethernet interrupt subpriority -#ifndef LPC546XX_ETH_IRQ_SUB_PRIORITY - #define LPC546XX_ETH_IRQ_SUB_PRIORITY 0 -#elif (LPC546XX_ETH_IRQ_SUB_PRIORITY < 0) - #error LPC546XX_ETH_IRQ_SUB_PRIORITY parameter is not valid +#ifndef LPC54XXX_ETH_IRQ_SUB_PRIORITY + #define LPC54XXX_ETH_IRQ_SUB_PRIORITY 0 +#elif (LPC54XXX_ETH_IRQ_SUB_PRIORITY < 0) + #error LPC54XXX_ETH_IRQ_SUB_PRIORITY parameter is not valid #endif //Transmit normal descriptor (read format) @@ -178,7 +178,7 @@ typedef struct uint32_t tdes1; uint32_t tdes2; uint32_t tdes3; -} Lpc546xxTxDmaDesc; +} Lpc54xxxTxDmaDesc; /** @@ -191,35 +191,35 @@ typedef struct uint32_t rdes1; uint32_t rdes2; uint32_t rdes3; -} Lpc546xxRxDmaDesc; +} Lpc54xxxRxDmaDesc; -//LPC546xx Ethernet MAC driver -extern const NicDriver lpc546xxEthDriver; +//LPC54xxx Ethernet MAC driver +extern const NicDriver lpc54xxxEthDriver; -//LPC546xx Ethernet MAC related functions -error_t lpc546xxEthInit(NetInterface *interface); -void lpc546xxEthInitGpio(NetInterface *interface); -void lpc546xxEthInitDmaDesc(NetInterface *interface); +//LPC54xxx Ethernet MAC related functions +error_t lpc54xxxEthInit(NetInterface *interface); +void lpc54xxxEthInitGpio(NetInterface *interface); +void lpc54xxxEthInitDmaDesc(NetInterface *interface); -void lpc546xxEthTick(NetInterface *interface); +void lpc54xxxEthTick(NetInterface *interface); -void lpc546xxEthEnableIrq(NetInterface *interface); -void lpc546xxEthDisableIrq(NetInterface *interface); -void lpc546xxEthEventHandler(NetInterface *interface); +void lpc54xxxEthEnableIrq(NetInterface *interface); +void lpc54xxxEthDisableIrq(NetInterface *interface); +void lpc54xxxEthEventHandler(NetInterface *interface); -error_t lpc546xxEthSendPacket(NetInterface *interface, +error_t lpc54xxxEthSendPacket(NetInterface *interface, const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary); -error_t lpc546xxEthReceivePacket(NetInterface *interface); +error_t lpc54xxxEthReceivePacket(NetInterface *interface); -error_t lpc546xxEthUpdateMacAddrFilter(NetInterface *interface); -error_t lpc546xxEthUpdateMacConfig(NetInterface *interface); +error_t lpc54xxxEthUpdateMacAddrFilter(NetInterface *interface); +error_t lpc54xxxEthUpdateMacConfig(NetInterface *interface); -void lpc546xxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, +void lpc54xxxEthWritePhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr, uint16_t data); -uint16_t lpc546xxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, +uint16_t lpc54xxxEthReadPhyReg(uint8_t opcode, uint8_t phyAddr, uint8_t regAddr); //C++ guard diff --git a/drivers/mac/m2sxxx_eth_driver.c b/drivers/mac/m2sxxx_eth_driver.c index e425bbd9..25818ae0 100644 --- a/drivers/mac/m2sxxx_eth_driver.c +++ b/drivers/mac/m2sxxx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/m2sxxx_eth_driver.h b/drivers/mac/m2sxxx_eth_driver.h index 71c7aca8..c34ea5f2 100644 --- a/drivers/mac/m2sxxx_eth_driver.h +++ b/drivers/mac/m2sxxx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _M2SXXX_ETH_DRIVER_H diff --git a/drivers/mac/m487_eth_driver.c b/drivers/mac/m487_eth_driver.c index ca3feefe..4be62f8e 100644 --- a/drivers/mac/m487_eth_driver.c +++ b/drivers/mac/m487_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/m487_eth_driver.h b/drivers/mac/m487_eth_driver.h index ff11158a..14f7a7c4 100644 --- a/drivers/mac/m487_eth_driver.h +++ b/drivers/mac/m487_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _M487_ETH_DRIVER_H diff --git a/drivers/mac/mcf5225x_eth_driver.c b/drivers/mac/mcf5225x_eth_driver.c index cb1a1814..e7858d46 100644 --- a/drivers/mac/mcf5225x_eth_driver.c +++ b/drivers/mac/mcf5225x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mcf5225x_eth_driver.h b/drivers/mac/mcf5225x_eth_driver.h index 51593f81..578d7275 100644 --- a/drivers/mac/mcf5225x_eth_driver.h +++ b/drivers/mac/mcf5225x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MCF5225X_ETH_DRIVER_H diff --git a/drivers/mac/mcimx6ul_eth1_driver.c b/drivers/mac/mcimx6ul_eth1_driver.c index ce95354b..08b9a87f 100644 --- a/drivers/mac/mcimx6ul_eth1_driver.c +++ b/drivers/mac/mcimx6ul_eth1_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mcimx6ul_eth1_driver.h b/drivers/mac/mcimx6ul_eth1_driver.h index 1f8548cf..fa09614f 100644 --- a/drivers/mac/mcimx6ul_eth1_driver.h +++ b/drivers/mac/mcimx6ul_eth1_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MCIMX6UL_ETH1_DRIVER_H diff --git a/drivers/mac/mcimx6ul_eth2_driver.c b/drivers/mac/mcimx6ul_eth2_driver.c index 893a0008..0235d937 100644 --- a/drivers/mac/mcimx6ul_eth2_driver.c +++ b/drivers/mac/mcimx6ul_eth2_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mcimx6ul_eth2_driver.h b/drivers/mac/mcimx6ul_eth2_driver.h index bf47d6fc..53255ba7 100644 --- a/drivers/mac/mcimx6ul_eth2_driver.h +++ b/drivers/mac/mcimx6ul_eth2_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MCIMX6UL_ETH2_DRIVER_H diff --git a/drivers/mac/mimxrt1020_eth_driver.c b/drivers/mac/mimxrt1020_eth_driver.c index bad0f614..9f53e258 100644 --- a/drivers/mac/mimxrt1020_eth_driver.c +++ b/drivers/mac/mimxrt1020_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mimxrt1020_eth_driver.h b/drivers/mac/mimxrt1020_eth_driver.h index cada1eae..4c27722d 100644 --- a/drivers/mac/mimxrt1020_eth_driver.h +++ b/drivers/mac/mimxrt1020_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MIMXRT1020_ETH_DRIVER_H diff --git a/drivers/mac/mimxrt1050_eth_driver.c b/drivers/mac/mimxrt1050_eth_driver.c index 7ba15f5a..e106fc1a 100644 --- a/drivers/mac/mimxrt1050_eth_driver.c +++ b/drivers/mac/mimxrt1050_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mimxrt1050_eth_driver.h b/drivers/mac/mimxrt1050_eth_driver.h index 39165f0a..797a854c 100644 --- a/drivers/mac/mimxrt1050_eth_driver.h +++ b/drivers/mac/mimxrt1050_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MIMXRT1050_ETH_DRIVER_H diff --git a/drivers/mac/mimxrt1060_eth_driver.c b/drivers/mac/mimxrt1060_eth_driver.c index ff0079c1..46026dc7 100644 --- a/drivers/mac/mimxrt1060_eth_driver.c +++ b/drivers/mac/mimxrt1060_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mimxrt1060_eth_driver.h b/drivers/mac/mimxrt1060_eth_driver.h index 81c62ab3..d26c3d5f 100644 --- a/drivers/mac/mimxrt1060_eth_driver.h +++ b/drivers/mac/mimxrt1060_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MIMXRT1060_ETH_DRIVER_H diff --git a/drivers/mac/mk6x_eth_driver.c b/drivers/mac/mk6x_eth_driver.c index 5076d477..0505a2a7 100644 --- a/drivers/mac/mk6x_eth_driver.c +++ b/drivers/mac/mk6x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mk6x_eth_driver.h b/drivers/mac/mk6x_eth_driver.h index 248e298f..60884bef 100644 --- a/drivers/mac/mk6x_eth_driver.h +++ b/drivers/mac/mk6x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MK6X_ETH_DRIVER_H diff --git a/drivers/mac/mk7x_eth_driver.c b/drivers/mac/mk7x_eth_driver.c index 5c0f00bc..5517cd9c 100644 --- a/drivers/mac/mk7x_eth_driver.c +++ b/drivers/mac/mk7x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mk7x_eth_driver.h b/drivers/mac/mk7x_eth_driver.h index abcd4c04..ecac9eb0 100644 --- a/drivers/mac/mk7x_eth_driver.h +++ b/drivers/mac/mk7x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MK7X_ETH_DRIVER_H diff --git a/drivers/mac/mkv5x_eth_driver.c b/drivers/mac/mkv5x_eth_driver.c index 5a024ac7..120bd2e9 100644 --- a/drivers/mac/mkv5x_eth_driver.c +++ b/drivers/mac/mkv5x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mkv5x_eth_driver.h b/drivers/mac/mkv5x_eth_driver.h index d4372681..02062ea8 100644 --- a/drivers/mac/mkv5x_eth_driver.h +++ b/drivers/mac/mkv5x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MKV5X_ETH_DRIVER_H diff --git a/drivers/mac/mpc57xx_eth_driver.c b/drivers/mac/mpc57xx_eth_driver.c index 3e010dd9..d68f2da0 100644 --- a/drivers/mac/mpc57xx_eth_driver.c +++ b/drivers/mac/mpc57xx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mpc57xx_eth_driver.h b/drivers/mac/mpc57xx_eth_driver.h index 594d7306..c97ff16c 100644 --- a/drivers/mac/mpc57xx_eth_driver.h +++ b/drivers/mac/mpc57xx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MPC57XX_ETH_DRIVER_H diff --git a/drivers/mac/mpfsxxx_eth1_driver.c b/drivers/mac/mpfsxxx_eth1_driver.c index bbe86a83..8a85804e 100644 --- a/drivers/mac/mpfsxxx_eth1_driver.c +++ b/drivers/mac/mpfsxxx_eth1_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mpfsxxx_eth1_driver.h b/drivers/mac/mpfsxxx_eth1_driver.h index 287c089b..e56b16e0 100644 --- a/drivers/mac/mpfsxxx_eth1_driver.h +++ b/drivers/mac/mpfsxxx_eth1_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MPFSXXX_ETH1_DRIVER_H diff --git a/drivers/mac/mpfsxxx_eth2_driver.c b/drivers/mac/mpfsxxx_eth2_driver.c index 26e7b58b..e7bdb2fe 100644 --- a/drivers/mac/mpfsxxx_eth2_driver.c +++ b/drivers/mac/mpfsxxx_eth2_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/mpfsxxx_eth2_driver.h b/drivers/mac/mpfsxxx_eth2_driver.h index bb9e83f0..1fd01c56 100644 --- a/drivers/mac/mpfsxxx_eth2_driver.h +++ b/drivers/mac/mpfsxxx_eth2_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MPFSXXX_ETH2_DRIVER_H diff --git a/drivers/mac/msp432e4_eth_driver.c b/drivers/mac/msp432e4_eth_driver.c index 0585f5c5..d39dd258 100644 --- a/drivers/mac/msp432e4_eth_driver.c +++ b/drivers/mac/msp432e4_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/msp432e4_eth_driver.h b/drivers/mac/msp432e4_eth_driver.h index 9a64b91f..ad285166 100644 --- a/drivers/mac/msp432e4_eth_driver.h +++ b/drivers/mac/msp432e4_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MSP432E4_ETH_DRIVER_H diff --git a/drivers/mac/nuc472_eth_driver.c b/drivers/mac/nuc472_eth_driver.c index 24e2cfb7..dbe455bb 100644 --- a/drivers/mac/nuc472_eth_driver.c +++ b/drivers/mac/nuc472_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/nuc472_eth_driver.h b/drivers/mac/nuc472_eth_driver.h index 0af7547e..8a430b8b 100644 --- a/drivers/mac/nuc472_eth_driver.h +++ b/drivers/mac/nuc472_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NUC472_ETH_DRIVER_H diff --git a/drivers/mac/omapl138_eth_driver.c b/drivers/mac/omapl138_eth_driver.c index 4c99b171..cff1a8b5 100644 --- a/drivers/mac/omapl138_eth_driver.c +++ b/drivers/mac/omapl138_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -73,7 +73,7 @@ static Omapl138TxBufferDesc txBufferDesc[OMAPL138_ETH_TX_BUFFER_COUNT]; #pragma location = OMAPL138_ETH_RAM_CPPI_SECTION static Omapl138RxBufferDesc rxBufferDesc[OMAPL138_ETH_RX_BUFFER_COUNT]; -//Keil MDK-ARM or GCC compiler? +//GCC compiler? #else //Transmit buffer diff --git a/drivers/mac/omapl138_eth_driver.h b/drivers/mac/omapl138_eth_driver.h index ceb8cf45..4fa151fe 100644 --- a/drivers/mac/omapl138_eth_driver.h +++ b/drivers/mac/omapl138_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _OMAPL138_ETH_DRIVER_H diff --git a/drivers/mac/pic32mx_eth_driver.c b/drivers/mac/pic32mx_eth_driver.c index e31081a2..179b33aa 100644 --- a/drivers/mac/pic32mx_eth_driver.c +++ b/drivers/mac/pic32mx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/pic32mx_eth_driver.h b/drivers/mac/pic32mx_eth_driver.h index 8c1e8002..78752a68 100644 --- a/drivers/mac/pic32mx_eth_driver.h +++ b/drivers/mac/pic32mx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _PIC32MX_ETH_DRIVER_H diff --git a/drivers/mac/pic32mz_eth_driver.c b/drivers/mac/pic32mz_eth_driver.c index f361c16a..177c253a 100644 --- a/drivers/mac/pic32mz_eth_driver.c +++ b/drivers/mac/pic32mz_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/pic32mz_eth_driver.h b/drivers/mac/pic32mz_eth_driver.h index e84dc45a..786b1ff2 100644 --- a/drivers/mac/pic32mz_eth_driver.h +++ b/drivers/mac/pic32mz_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _PIC32MZ_ETH_DRIVER_H diff --git a/drivers/mac/ra6m3_eth_driver.c b/drivers/mac/ra6m3_eth_driver.c index a5fc3d60..888dee79 100644 --- a/drivers/mac/ra6m3_eth_driver.c +++ b/drivers/mac/ra6m3_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/ra6m3_eth_driver.h b/drivers/mac/ra6m3_eth_driver.h index 24541471..dbcd477f 100644 --- a/drivers/mac/ra6m3_eth_driver.h +++ b/drivers/mac/ra6m3_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _RA6M3_ETH_DRIVER_H diff --git a/drivers/mac/rx62n_eth_driver.c b/drivers/mac/rx62n_eth_driver.c index 7edfad2f..b29abdfd 100644 --- a/drivers/mac/rx62n_eth_driver.c +++ b/drivers/mac/rx62n_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -220,7 +220,7 @@ error_t rx62nEthInit(NetInterface *interface) } -//RDK RX62N evaluation board? +//RDK-RX62N evaluation board? #if defined(USE_RDK_RX62N) /** diff --git a/drivers/mac/rx62n_eth_driver.h b/drivers/mac/rx62n_eth_driver.h index 8580fc4c..6208fe98 100644 --- a/drivers/mac/rx62n_eth_driver.h +++ b/drivers/mac/rx62n_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _RX62N_ETH_DRIVER_H diff --git a/drivers/mac/rx63n_eth_driver.c b/drivers/mac/rx63n_eth_driver.c index 9ebd98b9..63bf93f0 100644 --- a/drivers/mac/rx63n_eth_driver.c +++ b/drivers/mac/rx63n_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -224,8 +224,9 @@ error_t rx63nEthInit(NetInterface *interface) } -//RDK RX63N or RSK RX63N evaluation board? -#if defined(USE_RDK_RX63N) || defined(USE_RSK_RX63N) +//RDK-RX63N, RSK-RX63N or RSK-RX63N-256K evaluation board? +#if defined(USE_RDK_RX63N) || defined(USE_RSK_RX63N) || \ + defined(USE_RSK_RX63N_256K) /** * @brief GPIO configuration @@ -286,7 +287,7 @@ void rx63nEthInitGpio(NetInterface *interface) PORTB.PMR.BIT.B7 = 1; MPC.PB7PFS.BYTE = 0x12; -#elif defined(USE_RSK_RX63N) +#elif defined(USE_RSK_RX63N) || defined(USE_RSK_RX63N_256K) //Select MII interface mode MPC.PFENET.BIT.PHYMODE = 1; diff --git a/drivers/mac/rx63n_eth_driver.h b/drivers/mac/rx63n_eth_driver.h index b8d564ac..27ccd369 100644 --- a/drivers/mac/rx63n_eth_driver.h +++ b/drivers/mac/rx63n_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _RX63N_ETH_DRIVER_H diff --git a/drivers/mac/rza1_eth_driver.c b/drivers/mac/rza1_eth_driver.c index faa857cb..3c4a9518 100644 --- a/drivers/mac/rza1_eth_driver.c +++ b/drivers/mac/rza1_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -47,15 +47,19 @@ static NetInterface *nicDriverInterface; //Transmit buffer #pragma data_alignment = 32 +#pragma location = RZA1_ETH_RAM_SECTION static uint8_t txBuffer[RZA1_ETH_TX_BUFFER_COUNT][RZA1_ETH_TX_BUFFER_SIZE]; //Receive buffer #pragma data_alignment = 32 +#pragma location = RZA1_ETH_RAM_SECTION static uint8_t rxBuffer[RZA1_ETH_RX_BUFFER_COUNT][RZA1_ETH_RX_BUFFER_SIZE]; //Transmit DMA descriptors #pragma data_alignment = 32 +#pragma location = RZA1_ETH_RAM_SECTION static Rza1TxDmaDesc txDmaDesc[RZA1_ETH_TX_BUFFER_COUNT]; //Receive DMA descriptors #pragma data_alignment = 32 +#pragma location = RZA1_ETH_RAM_SECTION static Rza1RxDmaDesc rxDmaDesc[RZA1_ETH_RX_BUFFER_COUNT]; //ARM or GCC compiler? @@ -63,16 +67,16 @@ static Rza1RxDmaDesc rxDmaDesc[RZA1_ETH_RX_BUFFER_COUNT]; //Transmit buffer static uint8_t txBuffer[RZA1_ETH_TX_BUFFER_COUNT][RZA1_ETH_TX_BUFFER_SIZE] - __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32))); + __attribute__((aligned(32), section(RZA1_ETH_RAM_SECTION))); //Receive buffer static uint8_t rxBuffer[RZA1_ETH_RX_BUFFER_COUNT][RZA1_ETH_RX_BUFFER_SIZE] - __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32))); + __attribute__((aligned(32), section(RZA1_ETH_RAM_SECTION))); //Transmit DMA descriptors static Rza1TxDmaDesc txDmaDesc[RZA1_ETH_TX_BUFFER_COUNT] - __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32))); + __attribute__((aligned(32), section(RZA1_ETH_RAM_SECTION))); //Receive DMA descriptors static Rza1RxDmaDesc rxDmaDesc[RZA1_ETH_RX_BUFFER_COUNT] - __attribute__((section(".BSS_DMAC_SAMPLE_INTERNAL_RAM"), aligned(32))); + __attribute__((aligned(32), section(RZA1_ETH_RAM_SECTION))); #endif @@ -219,7 +223,7 @@ error_t rza1EthInit(NetInterface *interface) ETHER.ECSIPR0 = 0; //Enable the desired EDMAC interrupts - ETHER.EESIPR0 = ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP; + ETHER.EESIPR0 = ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP; //Register interrupt handler R_INTC_Regist_Int_Func(INTC_ID_ETHERI, rza1EthIrqHandler); @@ -240,7 +244,7 @@ error_t rza1EthInit(NetInterface *interface) } -//RSK RZ/A1H, Stream it! RZ, Hachiko or VK-RZ/A1H evaluation board? +//RSK-RZ/A1H, Stream it! RZ, Hachiko or VK-RZ/A1H evaluation board? #if defined(USE_RSK_RZA1H) || defined(USE_STREAM_IT_RZ) || \ defined(USE_HACHIKO) || defined(USE_VK_RZA1H) @@ -875,7 +879,7 @@ void rza1EthEventHandler(NetInterface *interface) } //Re-enable EDMAC interrupts - ETHER.EESIPR0 = ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP; + ETHER.EESIPR0 = ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP; } diff --git a/drivers/mac/rza1_eth_driver.h b/drivers/mac/rza1_eth_driver.h index f130c37e..61b933af 100644 --- a/drivers/mac/rza1_eth_driver.h +++ b/drivers/mac/rza1_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _RZA1_ETH_DRIVER_H @@ -69,6 +69,11 @@ #error RZA1_ETH_IRQ_PRIORITY parameter is not valid #endif +//Name of the section where to place DMA buffers +#ifndef RZA1_ETH_RAM_SECTION + #define RZA1_ETH_RAM_SECTION ".BSS_DMAC_SAMPLE_INTERNAL_RAM" +#endif + //ARSTR register #define ETHER_ARSTR_ARST 0x00000001 diff --git a/drivers/mac/s32k148_eth_driver.c b/drivers/mac/s32k148_eth_driver.c index 5444e678..98e2a36f 100644 --- a/drivers/mac/s32k148_eth_driver.c +++ b/drivers/mac/s32k148_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/s32k148_eth_driver.h b/drivers/mac/s32k148_eth_driver.h index 5375edda..63f76167 100644 --- a/drivers/mac/s32k148_eth_driver.h +++ b/drivers/mac/s32k148_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _S32K148_ETH_DRIVER_H diff --git a/drivers/mac/s5d9_eth_driver.c b/drivers/mac/s5d9_eth_driver.c index f82897ef..674bb7d3 100644 --- a/drivers/mac/s5d9_eth_driver.c +++ b/drivers/mac/s5d9_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/s5d9_eth_driver.h b/drivers/mac/s5d9_eth_driver.h index 00c28e13..acc3b313 100644 --- a/drivers/mac/s5d9_eth_driver.h +++ b/drivers/mac/s5d9_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _S5D9_ETH_DRIVER_H diff --git a/drivers/mac/s7g2_eth_driver.c b/drivers/mac/s7g2_eth_driver.c index 2d0d0043..30e046e8 100644 --- a/drivers/mac/s7g2_eth_driver.c +++ b/drivers/mac/s7g2_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/s7g2_eth_driver.h b/drivers/mac/s7g2_eth_driver.h index ad6008c9..7a43ac28 100644 --- a/drivers/mac/s7g2_eth_driver.h +++ b/drivers/mac/s7g2_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _S7G2_ETH_DRIVER_H diff --git a/drivers/mac/sam3x_eth_driver.c b/drivers/mac/sam3x_eth_driver.c index 38bff82a..4597b388 100644 --- a/drivers/mac/sam3x_eth_driver.c +++ b/drivers/mac/sam3x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/sam3x_eth_driver.h b/drivers/mac/sam3x_eth_driver.h index 2d4433d5..6a1ae304 100644 --- a/drivers/mac/sam3x_eth_driver.h +++ b/drivers/mac/sam3x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SAM3X_ETH_DRIVER_H diff --git a/drivers/mac/sam4e_eth_driver.c b/drivers/mac/sam4e_eth_driver.c index c8341be9..f81c4c21 100644 --- a/drivers/mac/sam4e_eth_driver.c +++ b/drivers/mac/sam4e_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/sam4e_eth_driver.h b/drivers/mac/sam4e_eth_driver.h index 6cee4777..4e9d0feb 100644 --- a/drivers/mac/sam4e_eth_driver.h +++ b/drivers/mac/sam4e_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SAM4E_ETH_DRIVER_H diff --git a/drivers/mac/sam7x_eth_driver.c b/drivers/mac/sam7x_eth_driver.c index b24d3fb9..fbb0b801 100644 --- a/drivers/mac/sam7x_eth_driver.c +++ b/drivers/mac/sam7x_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/sam7x_eth_driver.h b/drivers/mac/sam7x_eth_driver.h index 4f8366de..9d855c78 100644 --- a/drivers/mac/sam7x_eth_driver.h +++ b/drivers/mac/sam7x_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SAM7X_ETH_DRIVER_H diff --git a/drivers/mac/sam9263_eth_driver.c b/drivers/mac/sam9263_eth_driver.c index 7e8f7d27..ed76542d 100644 --- a/drivers/mac/sam9263_eth_driver.c +++ b/drivers/mac/sam9263_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/sam9263_eth_driver.h b/drivers/mac/sam9263_eth_driver.h index f3e6a0e2..dc0ce476 100644 --- a/drivers/mac/sam9263_eth_driver.h +++ b/drivers/mac/sam9263_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SAM9263_ETH_DRIVER_H diff --git a/drivers/mac/sama5d2_eth_driver.c b/drivers/mac/sama5d2_eth_driver.c index c4eb8fad..fb982d31 100644 --- a/drivers/mac/sama5d2_eth_driver.c +++ b/drivers/mac/sama5d2_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/sama5d2_eth_driver.h b/drivers/mac/sama5d2_eth_driver.h index 1e9c5966..1c49257c 100644 --- a/drivers/mac/sama5d2_eth_driver.h +++ b/drivers/mac/sama5d2_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SAMA5D2_ETH_DRIVER_H diff --git a/drivers/mac/sama5d3_eth_driver.c b/drivers/mac/sama5d3_eth_driver.c index 66db6719..00267ce0 100644 --- a/drivers/mac/sama5d3_eth_driver.c +++ b/drivers/mac/sama5d3_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/sama5d3_eth_driver.h b/drivers/mac/sama5d3_eth_driver.h index ab918747..5291c41d 100644 --- a/drivers/mac/sama5d3_eth_driver.h +++ b/drivers/mac/sama5d3_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SAMA5D3_ETH_DRIVER_H diff --git a/drivers/mac/sama5d3_geth_driver.c b/drivers/mac/sama5d3_geth_driver.c index 05ff399b..e50edda7 100644 --- a/drivers/mac/sama5d3_geth_driver.c +++ b/drivers/mac/sama5d3_geth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/sama5d3_geth_driver.h b/drivers/mac/sama5d3_geth_driver.h index 44a1ef23..2b7cf94c 100644 --- a/drivers/mac/sama5d3_geth_driver.h +++ b/drivers/mac/sama5d3_geth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SAMA5D3_GETH_DRIVER_H diff --git a/drivers/mac/same54_eth_driver.c b/drivers/mac/same54_eth_driver.c index 31082825..ece969f1 100644 --- a/drivers/mac/same54_eth_driver.c +++ b/drivers/mac/same54_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/same54_eth_driver.h b/drivers/mac/same54_eth_driver.h index 21dc7110..13212eff 100644 --- a/drivers/mac/same54_eth_driver.h +++ b/drivers/mac/same54_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SAME54_ETH_DRIVER_H diff --git a/drivers/mac/same70_eth_driver.c b/drivers/mac/same70_eth_driver.c index c6774b67..dab4840e 100644 --- a/drivers/mac/same70_eth_driver.c +++ b/drivers/mac/same70_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/same70_eth_driver.h b/drivers/mac/same70_eth_driver.h index 13e96de9..789e6527 100644 --- a/drivers/mac/same70_eth_driver.h +++ b/drivers/mac/same70_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SAME70_ETH_DRIVER_H diff --git a/drivers/mac/samv71_eth_driver.c b/drivers/mac/samv71_eth_driver.c index f072b511..5c6a4786 100644 --- a/drivers/mac/samv71_eth_driver.c +++ b/drivers/mac/samv71_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/samv71_eth_driver.h b/drivers/mac/samv71_eth_driver.h index cad53f86..2116b694 100644 --- a/drivers/mac/samv71_eth_driver.h +++ b/drivers/mac/samv71_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SAMV71_ETH_DRIVER_H diff --git a/drivers/mac/stm32f1xx_eth_driver.c b/drivers/mac/stm32f1xx_eth_driver.c index acdf29cd..5ec24f48 100644 --- a/drivers/mac/stm32f1xx_eth_driver.c +++ b/drivers/mac/stm32f1xx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/stm32f1xx_eth_driver.h b/drivers/mac/stm32f1xx_eth_driver.h index dd3e2cff..31003919 100644 --- a/drivers/mac/stm32f1xx_eth_driver.h +++ b/drivers/mac/stm32f1xx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _STM32F1XX_ETH_DRIVER_H diff --git a/drivers/mac/stm32f2xx_eth_driver.c b/drivers/mac/stm32f2xx_eth_driver.c index 2f64f2be..11452614 100644 --- a/drivers/mac/stm32f2xx_eth_driver.c +++ b/drivers/mac/stm32f2xx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/stm32f2xx_eth_driver.h b/drivers/mac/stm32f2xx_eth_driver.h index b0876cb8..4f595dce 100644 --- a/drivers/mac/stm32f2xx_eth_driver.h +++ b/drivers/mac/stm32f2xx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _STM32F2XX_ETH_DRIVER_H diff --git a/drivers/mac/stm32f4xx_eth_driver.c b/drivers/mac/stm32f4xx_eth_driver.c index a195cc40..eed23d2b 100644 --- a/drivers/mac/stm32f4xx_eth_driver.c +++ b/drivers/mac/stm32f4xx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/stm32f4xx_eth_driver.h b/drivers/mac/stm32f4xx_eth_driver.h index 1c76bf4b..1806ad8d 100644 --- a/drivers/mac/stm32f4xx_eth_driver.h +++ b/drivers/mac/stm32f4xx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _STM32F4XX_ETH_DRIVER_H diff --git a/drivers/mac/stm32f7xx_eth_driver.c b/drivers/mac/stm32f7xx_eth_driver.c index fd69d877..0c2aa443 100644 --- a/drivers/mac/stm32f7xx_eth_driver.c +++ b/drivers/mac/stm32f7xx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/stm32f7xx_eth_driver.h b/drivers/mac/stm32f7xx_eth_driver.h index ae39bf26..7fa32821 100644 --- a/drivers/mac/stm32f7xx_eth_driver.h +++ b/drivers/mac/stm32f7xx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _STM32F7XX_ETH_DRIVER_H diff --git a/drivers/mac/stm32h7xx_eth_driver.c b/drivers/mac/stm32h7xx_eth_driver.c index d312f250..13744b50 100644 --- a/drivers/mac/stm32h7xx_eth_driver.c +++ b/drivers/mac/stm32h7xx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -255,13 +255,14 @@ error_t stm32h7xxEthInit(NetInterface *interface) } -//STM32F743I-EVAL, STM32F747I-EVAL, STM32H745I-Discovery, STM32H747I-Discovery, -//STM32H750B-DK, Nucleo-H743ZI, Nucleo-H743ZI2 or Nucleo-H745ZI-Q evaluation board? +//STM32F743I-EVAL, STM32F747I-EVAL, STM32H735G-DK, STM32H745I-Discovery, +//STM32H747I-Discovery, STM32H750B-DK, Nucleo-H723ZG, Nucleo-H743ZI, +//Nucleo-H743ZI2 or Nucleo-H745ZI-Q evaluation board? #if defined(USE_STM32H743I_EVAL) || defined(USE_STM32H747I_EVAL) || \ - defined(USE_STM32H745I_DISCO) || defined(USE_STM32H747I_DISCO) || \ - defined(USE_STM32H750B_DISCO) || defined(USE_STM32H7XX_NUCLEO_144) || \ - defined(USE_STM32H7XX_NUCLEO_144_MB1363) || \ - defined(USE_STM32H7XX_NUCLEO_144_MB1364) + defined(USE_STM32H735G_DK) || defined(USE_STM32H745I_DISCO) || \ + defined(USE_STM32H747I_DISCO) || defined(USE_STM32H750B_DISCO) || \ + defined(USE_NUCLEO_H723ZG) || defined(USE_NUCLEO_H743ZI) || \ + defined(USE_NUCLEO_H743ZI2) || defined(USE_NUCLEO_H745ZI_Q) /** * @brief GPIO configuration @@ -304,6 +305,38 @@ void stm32h7xxEthInitGpio(NetInterface *interface) GPIO_InitStructure.Pin = GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13; HAL_GPIO_Init(GPIOG, &GPIO_InitStructure); +//STM32H735G-DK evaluation board? +#elif defined(USE_STM32H735G_DK) + //Enable SYSCFG clock + __HAL_RCC_SYSCFG_CLK_ENABLE(); + + //Enable GPIO clocks + __HAL_RCC_GPIOA_CLK_ENABLE(); + __HAL_RCC_GPIOB_CLK_ENABLE(); + __HAL_RCC_GPIOC_CLK_ENABLE(); + + //Select RMII interface mode + HAL_SYSCFG_ETHInterfaceSelect(SYSCFG_ETH_RMII); + + //Configure RMII pins + GPIO_InitStructure.Mode = GPIO_MODE_AF_PP; + GPIO_InitStructure.Pull = GPIO_NOPULL; + GPIO_InitStructure.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStructure.Alternate = GPIO_AF11_ETH; + + //Configure ETH_RMII_REF_CLK (PA1), ETH_MDIO (PA2) and ETH_RMII_CRS_DV (PA7) + GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_7; + HAL_GPIO_Init(GPIOA, &GPIO_InitStructure); + + //Configure RMII_RX_ER (PB10), RMII_TX_EN (PB11), ETH_RMII_TXD1 (PB12) + //and ETH_RMII_TXD0 (PB13) + GPIO_InitStructure.Pin = GPIO_PIN_10 | GPIO_PIN_11 | GPIO_PIN_12 | GPIO_PIN_13; + HAL_GPIO_Init(GPIOB, &GPIO_InitStructure); + + //Configure ETH_MDC (PC1), ETH_RMII_RXD0 (PC4) and ETH_RMII_RXD1 (PC5) + GPIO_InitStructure.Pin = GPIO_PIN_1 | GPIO_PIN_4 | GPIO_PIN_5; + HAL_GPIO_Init(GPIOC, &GPIO_InitStructure); + //STM32H745I-Discovery or STM32H750B-DK evaluation board? #elif defined(USE_STM32H745I_DISCO) || defined(USE_STM32H750B_DISCO) //Enable SYSCFG clock @@ -356,9 +389,10 @@ void stm32h7xxEthInitGpio(NetInterface *interface) GPIO_InitStructure.Pin = GPIO_PIN_10; HAL_GPIO_Init(GPIOI, &GPIO_InitStructure); -//Nucleo-H743ZI, Nucleo-H743ZI2 or Nucleo-H745ZI-Q evaluation board? -#elif defined(USE_STM32H7XX_NUCLEO_144) || defined(USE_STM32H7XX_NUCLEO_144_MB1363) || \ - defined(USE_STM32H7XX_NUCLEO_144_MB1364) +//Nucleo-H723ZG, Nucleo-H743ZI, Nucleo-H743ZI2 or Nucleo-H745ZI-Q evaluation +//board? +#elif defined(USE_NUCLEO_H723ZG) || defined(USE_NUCLEO_H743ZI) || \ + defined(USE_NUCLEO_H743ZI2) || defined(USE_NUCLEO_H745ZI_Q) //Enable SYSCFG clock __HAL_RCC_SYSCFG_CLK_ENABLE(); diff --git a/drivers/mac/stm32h7xx_eth_driver.h b/drivers/mac/stm32h7xx_eth_driver.h index d9b0e877..0a9d45ba 100644 --- a/drivers/mac/stm32h7xx_eth_driver.h +++ b/drivers/mac/stm32h7xx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _STM32H7XX_ETH_DRIVER_H diff --git a/drivers/mac/stm32mp1xx_eth_driver.c b/drivers/mac/stm32mp1xx_eth_driver.c index 74b92876..645c1f2c 100644 --- a/drivers/mac/stm32mp1xx_eth_driver.c +++ b/drivers/mac/stm32mp1xx_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/stm32mp1xx_eth_driver.h b/drivers/mac/stm32mp1xx_eth_driver.h index b8274c13..a6275307 100644 --- a/drivers/mac/stm32mp1xx_eth_driver.h +++ b/drivers/mac/stm32mp1xx_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _STM32MP1XX_ETH_DRIVER_H diff --git a/drivers/mac/str912_eth_driver.c b/drivers/mac/str912_eth_driver.c index 9165ec37..4033e1e7 100644 --- a/drivers/mac/str912_eth_driver.c +++ b/drivers/mac/str912_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/str912_eth_driver.h b/drivers/mac/str912_eth_driver.h index 85536d78..45fc4b69 100644 --- a/drivers/mac/str912_eth_driver.h +++ b/drivers/mac/str912_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _STR912_ETH_DRIVER_H diff --git a/drivers/mac/tm4c129_eth_driver.c b/drivers/mac/tm4c129_eth_driver.c index d4263594..308cd43e 100644 --- a/drivers/mac/tm4c129_eth_driver.c +++ b/drivers/mac/tm4c129_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/tm4c129_eth_driver.h b/drivers/mac/tm4c129_eth_driver.h index 1bbff46c..183eb6a9 100644 --- a/drivers/mac/tm4c129_eth_driver.h +++ b/drivers/mac/tm4c129_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TM4C129_ETH_DRIVER_H diff --git a/drivers/mac/tms570_eth_driver.c b/drivers/mac/tms570_eth_driver.c index 8b5a993f..7a6e08f7 100644 --- a/drivers/mac/tms570_eth_driver.c +++ b/drivers/mac/tms570_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -70,7 +70,7 @@ static Tms570TxBufferDesc txBufferDesc[TMS570_ETH_TX_BUFFER_COUNT]; #pragma location = TMS570_ETH_RAM_CPPI_SECTION static Tms570RxBufferDesc rxBufferDesc[TMS570_ETH_RX_BUFFER_COUNT]; -//Keil MDK-ARM or GCC compiler? +//GCC compiler? #else //Transmit buffer diff --git a/drivers/mac/tms570_eth_driver.h b/drivers/mac/tms570_eth_driver.h index b24a3a13..9568852d 100644 --- a/drivers/mac/tms570_eth_driver.h +++ b/drivers/mac/tms570_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TMS570_ETH_DRIVER_H diff --git a/drivers/mac/xmc4400_eth_driver.c b/drivers/mac/xmc4400_eth_driver.c new file mode 100644 index 00000000..e210e75c --- /dev/null +++ b/drivers/mac/xmc4400_eth_driver.c @@ -0,0 +1,956 @@ +/** + * @file xmc4400_eth_driver.c + * @brief Infineon XMC4400 Ethernet MAC driver + * + * @section License + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. + * + * This file is part of CycloneTCP Open. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * @author Oryx Embedded SARL (www.oryx-embedded.com) + * @version 2.0.2 + **/ + +//Switch to the appropriate trace level +#define TRACE_LEVEL NIC_TRACE_LEVEL + +//Dependencies +#include "xmc4400.h" +#include "core/net.h" +#include "drivers/mac/xmc4400_eth_driver.h" +#include "debug.h" + +//Underlying network interface +static NetInterface *nicDriverInterface; + +//IAR EWARM compiler? +#if defined(__ICCARM__) + +//Transmit buffer +#pragma data_alignment = 4 +#pragma location = XMC4400_ETH_RAM_SECTION +static uint8_t txBuffer[XMC4400_ETH_TX_BUFFER_COUNT][XMC4400_ETH_TX_BUFFER_SIZE]; +//Receive buffer +#pragma data_alignment = 4 +#pragma location = XMC4400_ETH_RAM_SECTION +static uint8_t rxBuffer[XMC4400_ETH_RX_BUFFER_COUNT][XMC4400_ETH_RX_BUFFER_SIZE]; +//Transmit DMA descriptors +#pragma data_alignment = 4 +#pragma location = XMC4400_ETH_RAM_SECTION +static Xmc4400TxDmaDesc txDmaDesc[XMC4400_ETH_TX_BUFFER_COUNT]; +//Receive DMA descriptors +#pragma data_alignment = 4 +#pragma location = XMC4400_ETH_RAM_SECTION +static Xmc4400RxDmaDesc rxDmaDesc[XMC4400_ETH_RX_BUFFER_COUNT]; + +//Keil MDK-ARM or GCC compiler? +#else + +//Transmit buffer +static uint8_t txBuffer[XMC4400_ETH_TX_BUFFER_COUNT][XMC4400_ETH_TX_BUFFER_SIZE] + __attribute__((aligned(4), __section__(XMC4400_ETH_RAM_SECTION))); +//Receive buffer +static uint8_t rxBuffer[XMC4400_ETH_RX_BUFFER_COUNT][XMC4400_ETH_RX_BUFFER_SIZE] + __attribute__((aligned(4), __section__(XMC4400_ETH_RAM_SECTION))); +//Transmit DMA descriptors +static Xmc4400TxDmaDesc txDmaDesc[XMC4400_ETH_TX_BUFFER_COUNT] + __attribute__((aligned(4), __section__(XMC4400_ETH_RAM_SECTION))); +//Receive DMA descriptors +static Xmc4400RxDmaDesc rxDmaDesc[XMC4400_ETH_RX_BUFFER_COUNT] + __attribute__((aligned(4), __section__(XMC4400_ETH_RAM_SECTION))); + +#endif + +//Pointer to the current TX DMA descriptor +static Xmc4400TxDmaDesc *txCurDmaDesc; +//Pointer to the current RX DMA descriptor +static Xmc4400RxDmaDesc *rxCurDmaDesc; + + +/** + * @brief XMC4400 Ethernet MAC driver + **/ + +const NicDriver xmc4400EthDriver = +{ + NIC_TYPE_ETHERNET, + ETH_MTU, + xmc4400EthInit, + xmc4400EthTick, + xmc4400EthEnableIrq, + xmc4400EthDisableIrq, + xmc4400EthEventHandler, + xmc4400EthSendPacket, + xmc4400EthUpdateMacAddrFilter, + xmc4400EthUpdateMacConfig, + xmc4400EthWritePhyReg, + xmc4400EthReadPhyReg, + TRUE, + TRUE, + TRUE, + FALSE +}; + + +/** + * @brief XMC4400 Ethernet MAC initialization + * @param[in] interface Underlying network interface + * @return Error code + **/ + +error_t xmc4400EthInit(NetInterface *interface) +{ + error_t error; + + //Debug message + TRACE_INFO("Initializing XMC4400 Ethernet MAC...\r\n"); + + //Save underlying network interface + nicDriverInterface = interface; + + //Disable parity error trap + SCU_PARITY->PETE = 0; + //Disable unaligned access trap + PPB->CCR &= ~PPB_CCR_UNALIGN_TRP_Msk; + + //Enable ETH0 peripheral clock + SCU_CLK->CLKSET = SCU_CLK_CLKSET_ETH0CEN_Msk; + + //GPIO configuration + xmc4400EthInitGpio(interface); + + //Reset ETH0 peripheral + SCU_RESET->PRSET2 = SCU_RESET_PRSET2_ETH0RS_Msk; + SCU_RESET->PRCLR2 = SCU_RESET_PRCLR2_ETH0RS_Msk; + + //Reset DMA controller + ETH0->BUS_MODE |= ETH_BUS_MODE_SWR_Msk; + //Wait for the reset to complete + while((ETH0->BUS_MODE & ETH_BUS_MODE_SWR_Msk) != 0) + { + } + + //Adjust MDC clock range depending on ETH clock frequency + ETH0->GMII_ADDRESS = ETH_GMII_ADDRESS_CR_DIV62; + + //Valid Ethernet PHY or switch driver? + if(interface->phyDriver != NULL) + { + //Ethernet PHY initialization + error = interface->phyDriver->init(interface); + } + else if(interface->switchDriver != NULL) + { + //Ethernet switch initialization + error = interface->switchDriver->init(interface); + } + else + { + //The interface is not properly configured + error = ERROR_FAILURE; + } + + //Any error to report? + if(error) + { + return error; + } + + //Use default MAC configuration + ETH0->MAC_CONFIGURATION = ETH_MAC_CONFIGURATION_RESERVED15_Msk | + ETH_MAC_CONFIGURATION_DO_Msk; + + //Set the MAC address of the station + ETH0->MAC_ADDRESS0_LOW = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16); + ETH0->MAC_ADDRESS0_HIGH = interface->macAddr.w[2]; + + //The MAC supports 3 additional addresses for unicast perfect filtering + ETH0->MAC_ADDRESS1_LOW = 0; + ETH0->MAC_ADDRESS1_HIGH = 0; + ETH0->MAC_ADDRESS2_LOW = 0; + ETH0->MAC_ADDRESS2_HIGH = 0; + ETH0->MAC_ADDRESS3_LOW = 0; + ETH0->MAC_ADDRESS3_HIGH = 0; + + //Initialize hash table + ETH0->HASH_TABLE_LOW = 0; + ETH0->HASH_TABLE_HIGH = 0; + + //Configure the receive filter + ETH0->MAC_FRAME_FILTER = ETH_MAC_FRAME_FILTER_HPF_Msk | ETH_MAC_FRAME_FILTER_HMC_Msk; + //Disable flow control + ETH0->FLOW_CONTROL = 0; + //Enable store and forward mode + ETH0->OPERATION_MODE = ETH_OPERATION_MODE_RSF_Msk | ETH_OPERATION_MODE_TSF_Msk; + + //Configure DMA bus mode + ETH0->BUS_MODE = ETH_BUS_MODE_AAL_Msk | ETH_BUS_MODE_USP_Msk | + ETH_BUS_MODE_RPBL_1 | ETH_BUS_MODE_PR_1_1 | ETH_BUS_MODE_PBL_1; + + //Initialize DMA descriptor lists + xmc4400EthInitDmaDesc(interface); + + //Prevent interrupts from being generated when statistic counters reach + //half their maximum value + ETH0->MMC_TRANSMIT_INTERRUPT_MASK = 0xFFFFFFFF; + ETH0->MMC_RECEIVE_INTERRUPT_MASK = 0xFFFFFFFF; + ETH0->MMC_IPC_RECEIVE_INTERRUPT_MASK = 0xFFFFFFFF; + + //Disable MAC interrupts + ETH0->INTERRUPT_MASK = ETH_INTERRUPT_MASK_TSIM_Msk | ETH_INTERRUPT_MASK_PMTIM_Msk; + + //Enable the desired DMA interrupts + ETH0->INTERRUPT_ENABLE = ETH_INTERRUPT_ENABLE_NIE_Msk | + ETH_INTERRUPT_ENABLE_RIE_Msk | ETH_INTERRUPT_ENABLE_TIE_Msk; + + //Set priority grouping (6 bits for pre-emption priority, no bits for subpriority) + NVIC_SetPriorityGrouping(XMC4400_ETH_IRQ_PRIORITY_GROUPING); + + //Configure Ethernet interrupt priority + NVIC_SetPriority(ETH0_0_IRQn, NVIC_EncodePriority(XMC4400_ETH_IRQ_PRIORITY_GROUPING, + XMC4400_ETH_IRQ_GROUP_PRIORITY, XMC4400_ETH_IRQ_SUB_PRIORITY)); + + //Enable MAC transmission and reception + ETH0->MAC_CONFIGURATION |= ETH_MAC_CONFIGURATION_TE_Msk | ETH_MAC_CONFIGURATION_RE_Msk; + //Enable DMA transmission and reception + ETH0->OPERATION_MODE |= ETH_OPERATION_MODE_ST_Msk | ETH_OPERATION_MODE_SR_Msk; + + //Accept any packets from the upper layer + osSetEvent(&interface->nicTxEvent); + + //Successful initialization + return NO_ERROR; +} + + +//XMC4400 Platform2GO Kit? +#if defined(USE_XMC4400_PLT2GO_KIT) + +/** + * @brief GPIO configuration + * @param[in] interface Underlying network interface + **/ + +void xmc4400EthInitGpio(NetInterface *interface) +{ + uint32_t temp; + + //Configure ETH0.TX_EN (P0.4) + temp = PORT0->IOCR4; + temp &= ~PORT0_IOCR4_PC4_Msk; + temp |= (17UL << PORT0_IOCR4_PC4_Pos); + PORT0->IOCR4 = temp; + + //Configure ETH0.MDIO (P2.0), ETH0.RXD0A (P2.2) and ETH0.RXD1A (P2.3) + temp = PORT2->IOCR0; + temp &= ~(PORT2_IOCR0_PC0_Msk | PORT2_IOCR0_PC2_Msk | PORT2_IOCR0_PC3_Msk); + temp |= (0UL << PORT2_IOCR0_PC0_Pos) | (0UL << PORT2_IOCR0_PC2_Pos) | (0UL << PORT2_IOCR0_PC3_Pos); + PORT2->IOCR0 = temp; + + //Configure ETH0.RXERA (P2.4)and ETH0.MDC (P2.7) + temp = PORT2->IOCR4; + temp &= ~(PORT2_IOCR4_PC4_Msk | PORT2_IOCR4_PC7_Msk); + temp |= (0UL << PORT2_IOCR4_PC4_Pos) | (17UL << PORT2_IOCR4_PC7_Pos); + PORT2->IOCR4 = temp; + + //Configure ETH0.TXD0 (P2.8) and ETH0.TXD1 (P2.9) + temp = PORT2->IOCR8; + temp &= ~(PORT2_IOCR8_PC8_Msk | PORT2_IOCR8_PC9_Msk); + temp |= (17UL << PORT2_IOCR8_PC8_Pos) | (17UL << PORT2_IOCR8_PC9_Pos); + PORT2->IOCR8 = temp; + + //Configure ETH0.CLK_RMIIC (P15.8) and ETH0.CRS_DVC (P15.9) + temp = PORT15->IOCR8; + temp &= ~(PORT15_IOCR8_PC8_Msk | PORT15_IOCR8_PC9_Msk); + temp |= (0UL << PORT15_IOCR8_PC8_Pos) | (0UL << PORT15_IOCR8_PC9_Pos); + PORT15->IOCR8 = temp; + + //Assign ETH_MDIO (P2.0) to HW0 + temp = PORT2->HWSEL & ~PORT2_HWSEL_HW0_Msk; + PORT2->HWSEL = temp | (1UL << PORT2_HWSEL_HW0_Pos); + + //Select output driver strength for ETH0.TX_EN (P2.5) + temp = PORT2->PDR0; + temp &= ~PORT2_PDR0_PD5_Msk; + temp |= (0UL << PORT2_PDR0_PD5_Pos); + PORT2->PDR0 = temp; + + //Select output driver strength for ETH0.TXD0 (P2.8) and ETH0.TXD1 (P2.9) + temp = PORT2->PDR1; + temp &= ~(PORT2_PDR1_PD8_Msk | PORT2_PDR1_PD9_Msk); + temp |= (0UL << PORT2_PDR1_PD8_Pos) | (0UL << PORT2_PDR1_PD9_Pos); + PORT2->PDR1 = temp; + + //Use ETH0.CLK_RMIIC (P15.8) and ETH0.CRS_DVC (P15.9) as digital inputs + PORT15->PDISC &= ~(PORT15_PDISC_PDIS8_Msk | PORT15_PDISC_PDIS9_Msk); + + //Select RMII operation mode + ETH0_CON->CON = ETH_CON_INFSEL_Msk | ETH_CON_MDIO_B | ETH_CON_RXER_A | + ETH_CON_CRS_DV_C | ETH_CON_CLK_RMII_C | ETH_CON_RXD1_A | ETH_CON_RXD0_A; +} + +#endif + + +/** + * @brief Initialize DMA descriptor lists + * @param[in] interface Underlying network interface + **/ + +void xmc4400EthInitDmaDesc(NetInterface *interface) +{ + uint_t i; + + //Initialize TX DMA descriptor list + for(i = 0; i < XMC4400_ETH_TX_BUFFER_COUNT; i++) + { + //Use chain structure rather than ring structure + txDmaDesc[i].tdes0 = ETH_TDES0_IC | ETH_TDES0_TCH; + //Initialize transmit buffer size + txDmaDesc[i].tdes1 = 0; + //Transmit buffer address + txDmaDesc[i].tdes2 = (uint32_t) txBuffer[i]; + //Next descriptor address + txDmaDesc[i].tdes3 = (uint32_t) &txDmaDesc[i + 1]; + } + + //The last descriptor is chained to the first entry + txDmaDesc[i - 1].tdes3 = (uint32_t) &txDmaDesc[0]; + //Point to the very first descriptor + txCurDmaDesc = &txDmaDesc[0]; + + //Initialize RX DMA descriptor list + for(i = 0; i < XMC4400_ETH_RX_BUFFER_COUNT; i++) + { + //The descriptor is initially owned by the DMA + rxDmaDesc[i].rdes0 = ETH_RDES0_OWN; + //Use chain structure rather than ring structure + rxDmaDesc[i].rdes1 = ETH_RDES1_RCH | (XMC4400_ETH_RX_BUFFER_SIZE & ETH_RDES1_RBS1); + //Receive buffer address + rxDmaDesc[i].rdes2 = (uint32_t) rxBuffer[i]; + //Next descriptor address + rxDmaDesc[i].rdes3 = (uint32_t) &rxDmaDesc[i + 1]; + } + + //The last descriptor is chained to the first entry + rxDmaDesc[i - 1].rdes3 = (uint32_t) &rxDmaDesc[0]; + //Point to the very first descriptor + rxCurDmaDesc = &rxDmaDesc[0]; + + //Start location of the TX descriptor list + ETH0->TRANSMIT_DESCRIPTOR_LIST_ADDRESS = (uint32_t) txDmaDesc; + //Start location of the RX descriptor list + ETH0->RECEIVE_DESCRIPTOR_LIST_ADDRESS = (uint32_t) rxDmaDesc; +} + + +/** + * @brief XMC4400 Ethernet MAC timer handler + * + * This routine is periodically called by the TCP/IP stack to handle periodic + * operations such as polling the link state + * + * @param[in] interface Underlying network interface + **/ + +void xmc4400EthTick(NetInterface *interface) +{ + //Valid Ethernet PHY or switch driver? + if(interface->phyDriver != NULL) + { + //Handle periodic operations + interface->phyDriver->tick(interface); + } + else if(interface->switchDriver != NULL) + { + //Handle periodic operations + interface->switchDriver->tick(interface); + } + else + { + //Just for sanity + } +} + + +/** + * @brief Enable interrupts + * @param[in] interface Underlying network interface + **/ + +void xmc4400EthEnableIrq(NetInterface *interface) +{ + //Enable Ethernet MAC interrupts + NVIC_EnableIRQ(ETH0_0_IRQn); + + //Valid Ethernet PHY or switch driver? + if(interface->phyDriver != NULL) + { + //Enable Ethernet PHY interrupts + interface->phyDriver->enableIrq(interface); + } + else if(interface->switchDriver != NULL) + { + //Enable Ethernet switch interrupts + interface->switchDriver->enableIrq(interface); + } + else + { + //Just for sanity + } +} + + +/** + * @brief Disable interrupts + * @param[in] interface Underlying network interface + **/ + +void xmc4400EthDisableIrq(NetInterface *interface) +{ + //Disable Ethernet MAC interrupts + NVIC_DisableIRQ(ETH0_0_IRQn); + + //Valid Ethernet PHY or switch driver? + if(interface->phyDriver != NULL) + { + //Disable Ethernet PHY interrupts + interface->phyDriver->disableIrq(interface); + } + else if(interface->switchDriver != NULL) + { + //Disable Ethernet switch interrupts + interface->switchDriver->disableIrq(interface); + } + else + { + //Just for sanity + } +} + + +/** + * @brief XMC4400 Ethernet MAC interrupt service routine + **/ + +void ETH0_0_IRQHandler(void) +{ + bool_t flag; + uint32_t status; + + //Interrupt service routine prologue + osEnterIsr(); + + //This flag will be set if a higher priority task must be woken + flag = FALSE; + + //Read DMA status register + status = ETH0->STATUS; + + //Packet transmitted? + if((status & ETH_STATUS_TI_Msk) != 0) + { + //Clear TI interrupt flag + ETH0->STATUS = ETH_STATUS_TI_Msk; + + //Check whether the TX buffer is available for writing + if((txCurDmaDesc->tdes0 & ETH_TDES0_OWN) == 0) + { + //Notify the TCP/IP stack that the transmitter is ready to send + flag |= osSetEventFromIsr(&nicDriverInterface->nicTxEvent); + } + } + + //Packet received? + if((status & ETH_STATUS_RI_Msk) != 0) + { + //Disable RIE interrupt + ETH0->INTERRUPT_ENABLE &= ~ETH_INTERRUPT_ENABLE_RIE_Msk; + + //Set event flag + nicDriverInterface->nicEvent = TRUE; + //Notify the TCP/IP stack of the event + flag |= osSetEventFromIsr(&netEvent); + } + + //Clear NIS interrupt flag + ETH0->STATUS = ETH_STATUS_NIS_Msk; + + //Interrupt service routine epilogue + osExitIsr(flag); +} + + +/** + * @brief XMC4400 Ethernet MAC event handler + * @param[in] interface Underlying network interface + **/ + +void xmc4400EthEventHandler(NetInterface *interface) +{ + error_t error; + + //Packet received? + if((ETH0->STATUS & ETH_STATUS_RI_Msk) != 0) + { + //Clear interrupt flag + ETH0->STATUS = ETH_STATUS_RI_Msk; + + //Process all pending packets + do + { + //Read incoming packet + error = xmc4400EthReceivePacket(interface); + + //No more data in the receive buffer? + } while(error != ERROR_BUFFER_EMPTY); + } + + //Re-enable DMA interrupts + ETH0->INTERRUPT_ENABLE = ETH_INTERRUPT_ENABLE_NIE_Msk | + ETH_INTERRUPT_ENABLE_RIE_Msk | ETH_INTERRUPT_ENABLE_TIE_Msk; +} + + +/** + * @brief Send a packet + * @param[in] interface Underlying network interface + * @param[in] buffer Multi-part buffer containing the data to send + * @param[in] offset Offset to the first data byte + * @param[in] ancillary Additional options passed to the stack along with + * the packet + * @return Error code + **/ + +error_t xmc4400EthSendPacket(NetInterface *interface, + const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary) +{ + size_t length; + + //Retrieve the length of the packet + length = netBufferGetLength(buffer) - offset; + + //Check the frame length + if(length > XMC4400_ETH_TX_BUFFER_SIZE) + { + //The transmitter can accept another packet + osSetEvent(&interface->nicTxEvent); + //Report an error + return ERROR_INVALID_LENGTH; + } + + //Make sure the current buffer is available for writing + if((txCurDmaDesc->tdes0 & ETH_TDES0_OWN) != 0) + { + return ERROR_FAILURE; + } + + //Copy user data to the transmit buffer + netBufferRead((uint8_t *) txCurDmaDesc->tdes2, buffer, offset, length); + + //Write the number of bytes to send + txCurDmaDesc->tdes1 = length & ETH_TDES1_TBS1; + //Set LS and FS flags as the data fits in a single buffer + txCurDmaDesc->tdes0 |= ETH_TDES0_LS | ETH_TDES0_FS; + //Give the ownership of the descriptor to the DMA + txCurDmaDesc->tdes0 |= ETH_TDES0_OWN; + + //Clear TU flag to resume processing + ETH0->STATUS = ETH_STATUS_TU_Msk; + //Instruct the DMA to poll the transmit descriptor list + ETH0->TRANSMIT_POLL_DEMAND = 0; + + //Point to the next descriptor in the list + txCurDmaDesc = (Xmc4400TxDmaDesc *) txCurDmaDesc->tdes3; + + //Check whether the next buffer is available for writing + if((txCurDmaDesc->tdes0 & ETH_TDES0_OWN) == 0) + { + //The transmitter can accept another packet + osSetEvent(&interface->nicTxEvent); + } + + //Data successfully written + return NO_ERROR; +} + + +/** + * @brief Receive a packet + * @param[in] interface Underlying network interface + * @return Error code + **/ + +error_t xmc4400EthReceivePacket(NetInterface *interface) +{ + error_t error; + size_t n; + NetRxAncillary ancillary; + + //The current buffer is available for reading? + if((rxCurDmaDesc->rdes0 & ETH_RDES0_OWN) == 0) + { + //FS and LS flags should be set + if((rxCurDmaDesc->rdes0 & ETH_RDES0_FS) != 0 && + (rxCurDmaDesc->rdes0 & ETH_RDES0_LS) != 0) + { + //Make sure no error occurred + if((rxCurDmaDesc->rdes0 & ETH_RDES0_ES) == 0) + { + //Retrieve the length of the frame + n = (rxCurDmaDesc->rdes0 & ETH_RDES0_FL) >> 16; + //Limit the number of data to read + n = MIN(n, XMC4400_ETH_RX_BUFFER_SIZE); + + //Additional options can be passed to the stack along with the packet + ancillary = NET_DEFAULT_RX_ANCILLARY; + + //Pass the packet to the upper layer + nicProcessPacket(interface, (uint8_t *) rxCurDmaDesc->rdes2, n, + &ancillary); + + //Valid packet received + error = NO_ERROR; + } + else + { + //The received packet contains an error + error = ERROR_INVALID_PACKET; + } + } + else + { + //The packet is not valid + error = ERROR_INVALID_PACKET; + } + + //Give the ownership of the descriptor back to the DMA + rxCurDmaDesc->rdes0 = ETH_RDES0_OWN; + //Point to the next descriptor in the list + rxCurDmaDesc = (Xmc4400RxDmaDesc *) rxCurDmaDesc->rdes3; + } + else + { + //No more data in the receive buffer + error = ERROR_BUFFER_EMPTY; + } + + //Clear RU flag to resume processing + ETH0->STATUS = ETH_STATUS_RU_Msk; + //Instruct the DMA to poll the receive descriptor list + ETH0->RECEIVE_POLL_DEMAND = 0; + + //Return status code + return error; +} + + +/** + * @brief Configure MAC address filtering + * @param[in] interface Underlying network interface + * @return Error code + **/ + +error_t xmc4400EthUpdateMacAddrFilter(NetInterface *interface) +{ + uint_t i; + uint_t j; + uint_t k; + uint32_t crc; + uint32_t hashTable[2]; + MacAddr unicastMacAddr[3]; + MacFilterEntry *entry; + + //Debug message + TRACE_DEBUG("Updating MAC filter...\r\n"); + + //Set the MAC address of the station + ETH0->MAC_ADDRESS0_LOW = interface->macAddr.w[0] | (interface->macAddr.w[1] << 16); + ETH0->MAC_ADDRESS0_HIGH = interface->macAddr.w[2]; + + //The MAC supports 3 additional addresses for unicast perfect filtering + unicastMacAddr[0] = MAC_UNSPECIFIED_ADDR; + unicastMacAddr[1] = MAC_UNSPECIFIED_ADDR; + unicastMacAddr[2] = MAC_UNSPECIFIED_ADDR; + + //The hash table is used for multicast address filtering + hashTable[0] = 0; + hashTable[1] = 0; + + //The MAC address filter contains the list of MAC addresses to accept + //when receiving an Ethernet frame + for(i = 0, j = 0; i < MAC_ADDR_FILTER_SIZE; i++) + { + //Point to the current entry + entry = &interface->macAddrFilter[i]; + + //Valid entry? + if(entry->refCount > 0) + { + //Multicast address? + if(macIsMulticastAddr(&entry->addr)) + { + //Compute CRC over the current MAC address + crc = xmc4400EthCalcCrc(&entry->addr, sizeof(MacAddr)); + + //The upper 6 bits in the CRC register are used to index the + //contents of the hash table + k = (crc >> 26) & 0x3F; + + //Update hash table contents + hashTable[k / 32] |= (1 << (k % 32)); + } + else + { + //Up to 3 additional MAC addresses can be specified + if(j < 3) + { + //Save the unicast address + unicastMacAddr[j++] = entry->addr; + } + } + } + } + + //Configure the first unicast address filter + if(j >= 1) + { + //When the AE bit is set, the entry is used for perfect filtering + ETH0->MAC_ADDRESS1_LOW = unicastMacAddr[0].w[0] | (unicastMacAddr[0].w[1] << 16); + ETH0->MAC_ADDRESS1_HIGH = unicastMacAddr[0].w[2] | ETH_MAC_ADDRESS1_HIGH_AE_Msk; + } + else + { + //When the AE bit is cleared, the entry is ignored + ETH0->MAC_ADDRESS1_LOW = 0; + ETH0->MAC_ADDRESS1_HIGH = 0; + } + + //Configure the second unicast address filter + if(j >= 2) + { + //When the AE bit is set, the entry is used for perfect filtering + ETH0->MAC_ADDRESS2_LOW = unicastMacAddr[1].w[0] | (unicastMacAddr[1].w[1] << 16); + ETH0->MAC_ADDRESS2_HIGH = unicastMacAddr[1].w[2] | ETH_MAC_ADDRESS2_HIGH_AE_Msk; + } + else + { + //When the AE bit is cleared, the entry is ignored + ETH0->MAC_ADDRESS2_LOW = 0; + ETH0->MAC_ADDRESS2_HIGH = 0; + } + + //Configure the third unicast address filter + if(j >= 3) + { + //When the AE bit is set, the entry is used for perfect filtering + ETH0->MAC_ADDRESS3_LOW = unicastMacAddr[2].w[0] | (unicastMacAddr[2].w[1] << 16); + ETH0->MAC_ADDRESS3_HIGH = unicastMacAddr[2].w[2] | ETH_MAC_ADDRESS3_HIGH_AE_Msk; + } + else + { + //When the AE bit is cleared, the entry is ignored + ETH0->MAC_ADDRESS3_LOW = 0; + ETH0->MAC_ADDRESS3_HIGH = 0; + } + + //Configure the multicast address filter + ETH0->HASH_TABLE_LOW = hashTable[0]; + ETH0->HASH_TABLE_HIGH = hashTable[1]; + + //Debug message + TRACE_DEBUG(" HASH_TABLE_LOW = %08" PRIX32 "\r\n", ETH0->HASH_TABLE_LOW); + TRACE_DEBUG(" HASH_TABLE_HIGH = %08" PRIX32 "\r\n", ETH0->HASH_TABLE_HIGH); + + //Successful processing + return NO_ERROR; +} + + +/** + * @brief Adjust MAC configuration parameters for proper operation + * @param[in] interface Underlying network interface + * @return Error code + **/ + +error_t xmc4400EthUpdateMacConfig(NetInterface *interface) +{ + uint32_t config; + + //Read current MAC configuration + config = ETH0->MAC_CONFIGURATION; + + //10BASE-T or 100BASE-TX operation mode? + if(interface->linkSpeed == NIC_LINK_SPEED_100MBPS) + { + config |= ETH_MAC_CONFIGURATION_FES_Msk; + } + else + { + config &= ~ETH_MAC_CONFIGURATION_FES_Msk; + } + + //Half-duplex or full-duplex mode? + if(interface->duplexMode == NIC_FULL_DUPLEX_MODE) + { + config |= ETH_MAC_CONFIGURATION_DM_Msk; + } + else + { + config &= ~ETH_MAC_CONFIGURATION_DM_Msk; + } + + //Update MAC configuration register + ETH0->MAC_CONFIGURATION = config; + + //Successful processing + return NO_ERROR; +} + + +/** + * @brief Write PHY register + * @param[in] opcode Access type (2 bits) + * @param[in] phyAddr PHY address (5 bits) + * @param[in] regAddr Register address (5 bits) + * @param[in] data Register value + **/ + +void xmc4400EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, + uint8_t regAddr, uint16_t data) +{ + uint32_t temp; + + //Valid opcode? + if(opcode == SMI_OPCODE_WRITE) + { + //Take care not to alter MDC clock configuration + temp = ETH0->GMII_ADDRESS & ETH_GMII_ADDRESS_CR_Msk; + //Set up a write operation + temp |= ETH_GMII_ADDRESS_MW_Msk | ETH_GMII_ADDRESS_MB_Msk; + //PHY address + temp |= (phyAddr << ETH_GMII_ADDRESS_PA_Pos) & ETH_GMII_ADDRESS_PA_Msk; + //Register address + temp |= (regAddr << ETH_GMII_ADDRESS_MR_Pos) & ETH_GMII_ADDRESS_MR_Msk; + + //Data to be written in the PHY register + ETH0->GMII_DATA = data & ETH_GMII_DATA_MD_Msk; + + //Start a write operation + ETH0->GMII_ADDRESS = temp; + //Wait for the write to complete + while((ETH0->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0) + { + } + } + else + { + //The MAC peripheral only supports standard Clause 22 opcodes + } +} + + +/** + * @brief Read PHY register + * @param[in] opcode Access type (2 bits) + * @param[in] phyAddr PHY address (5 bits) + * @param[in] regAddr Register address (5 bits) + * @return Register value + **/ + +uint16_t xmc4400EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, + uint8_t regAddr) +{ + uint16_t data; + uint32_t temp; + + //Valid opcode? + if(opcode == SMI_OPCODE_READ) + { + //Take care not to alter MDC clock configuration + temp = ETH0->GMII_ADDRESS & ETH_GMII_ADDRESS_CR_Msk; + //Set up a read operation + temp |= ETH_GMII_ADDRESS_MB_Msk; + //PHY address + temp |= (phyAddr << ETH_GMII_ADDRESS_PA_Pos) & ETH_GMII_ADDRESS_PA_Msk; + //Register address + temp |= (regAddr << ETH_GMII_ADDRESS_MR_Pos) & ETH_GMII_ADDRESS_MR_Msk; + + //Start a read operation + ETH0->GMII_ADDRESS = temp; + //Wait for the read to complete + while((ETH0->GMII_ADDRESS & ETH_GMII_ADDRESS_MB_Msk) != 0) + { + } + + //Get register value + data = ETH0->GMII_DATA & ETH_GMII_DATA_MD_Msk; + } + else + { + //The MAC peripheral only supports standard Clause 22 opcodes + data = 0; + } + + //Return the value of the PHY register + return data; +} + + +/** + * @brief CRC calculation + * @param[in] data Pointer to the data over which to calculate the CRC + * @param[in] length Number of bytes to process + * @return Resulting CRC value + **/ + +uint32_t xmc4400EthCalcCrc(const void *data, size_t length) +{ + uint_t i; + uint_t j; + uint32_t crc; + const uint8_t *p; + + //Point to the data over which to calculate the CRC + p = (uint8_t *) data; + //CRC preset value + crc = 0xFFFFFFFF; + + //Loop through data + for(i = 0; i < length; i++) + { + //The message is processed bit by bit + for(j = 0; j < 8; j++) + { + //Update CRC value + if((((crc >> 31) ^ (p[i] >> j)) & 0x01) != 0) + { + crc = (crc << 1) ^ 0x04C11DB7; + } + else + { + crc = crc << 1; + } + } + } + + //Return CRC value + return ~crc; +} diff --git a/drivers/mac/xmc4400_eth_driver.h b/drivers/mac/xmc4400_eth_driver.h new file mode 100644 index 00000000..553fa40e --- /dev/null +++ b/drivers/mac/xmc4400_eth_driver.h @@ -0,0 +1,304 @@ +/** + * @file xmc4400_eth_driver.h + * @brief Infineon XMC4400 Ethernet MAC driver + * + * @section License + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. + * + * This file is part of CycloneTCP Open. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * @author Oryx Embedded SARL (www.oryx-embedded.com) + * @version 2.0.2 + **/ + +#ifndef _XMC4400_ETH_DRIVER_H +#define _XMC4400_ETH_DRIVER_H + +//Dependencies +#include "core/nic.h" + +//Number of TX buffers +#ifndef XMC4400_ETH_TX_BUFFER_COUNT + #define XMC4400_ETH_TX_BUFFER_COUNT 2 +#elif (XMC4400_ETH_TX_BUFFER_COUNT < 1) + #error XMC4400_ETH_TX_BUFFER_COUNT parameter is not valid +#endif + +//TX buffer size +#ifndef XMC4400_ETH_TX_BUFFER_SIZE + #define XMC4400_ETH_TX_BUFFER_SIZE 1536 +#elif (XMC4400_ETH_TX_BUFFER_SIZE != 1536) + #error XMC4400_ETH_TX_BUFFER_SIZE parameter is not valid +#endif + +//Number of RX buffers +#ifndef XMC4400_ETH_RX_BUFFER_COUNT + #define XMC4400_ETH_RX_BUFFER_COUNT 4 +#elif (XMC4400_ETH_RX_BUFFER_COUNT < 1) + #error XMC4400_ETH_RX_BUFFER_COUNT parameter is not valid +#endif + +//RX buffer size +#ifndef XMC4400_ETH_RX_BUFFER_SIZE + #define XMC4400_ETH_RX_BUFFER_SIZE 1536 +#elif (XMC4400_ETH_RX_BUFFER_SIZE != 1536) + #error XMC4400_ETH_RX_BUFFER_SIZE parameter is not valid +#endif + +//Interrupt priority grouping +#ifndef XMC4400_ETH_IRQ_PRIORITY_GROUPING + #define XMC4400_ETH_IRQ_PRIORITY_GROUPING 1 +#elif (XMC4400_ETH_IRQ_PRIORITY_GROUPING < 0) + #error XMC4400_ETH_IRQ_PRIORITY_GROUPING parameter is not valid +#endif + +//Ethernet interrupt group priority +#ifndef XMC4400_ETH_IRQ_GROUP_PRIORITY + #define XMC4400_ETH_IRQ_GROUP_PRIORITY 48 +#elif (XMC4400_ETH_IRQ_GROUP_PRIORITY < 0) + #error XMC4400_ETH_IRQ_GROUP_PRIORITY parameter is not valid +#endif + +//Ethernet interrupt subpriority +#ifndef XMC4400_ETH_IRQ_SUB_PRIORITY + #define XMC4400_ETH_IRQ_SUB_PRIORITY 0 +#elif (XMC4400_ETH_IRQ_SUB_PRIORITY < 0) + #error XMC4400_ETH_IRQ_SUB_PRIORITY parameter is not valid +#endif + +//Name of the section where to place DMA buffers +#ifndef XMC4400_ETH_RAM_SECTION + #define XMC4400_ETH_RAM_SECTION "ETH_RAM" +#endif + +//ETH0_CON register +#define ETH_CON_MDIO_A (0 << ETH_CON_MDIO_Pos) +#define ETH_CON_MDIO_B (1 << ETH_CON_MDIO_Pos) +#define ETH_CON_MDIO_C (2 << ETH_CON_MDIO_Pos) +#define ETH_CON_MDIO_D (3 << ETH_CON_MDIO_Pos) + +#define ETH_CON_CLK_TX_A (0 << ETH_CON_CLK_TX_Pos) +#define ETH_CON_CLK_TX_B (1 << ETH_CON_CLK_TX_Pos) +#define ETH_CON_CLK_TX_C (2 << ETH_CON_CLK_TX_Pos) +#define ETH_CON_CLK_TX_D (3 << ETH_CON_CLK_TX_Pos) + +#define ETH_CON_COL_A (0 << ETH_CON_COL_Pos) +#define ETH_CON_COL_B (1 << ETH_CON_COL_Pos) +#define ETH_CON_COL_C (2 << ETH_CON_COL_Pos) +#define ETH_CON_COL_D (3 << ETH_CON_COL_Pos) + +#define ETH_CON_RXER_A (0 << ETH_CON_RXER_Pos) +#define ETH_CON_RXER_B (1 << ETH_CON_RXER_Pos) +#define ETH_CON_RXER_C (2 << ETH_CON_RXER_Pos) +#define ETH_CON_RXER_D (3 << ETH_CON_RXER_Pos) + +#define ETH_CON_CRS_A (0 << ETH_CON_CRS_Pos) +#define ETH_CON_CRS_B (1 << ETH_CON_CRS_Pos) +#define ETH_CON_CRS_C (2 << ETH_CON_CRS_Pos) +#define ETH_CON_CRS_D (3 << ETH_CON_CRS_Pos) + +#define ETH_CON_CRS_DV_A (0 << ETH_CON_CRS_DV_Pos) +#define ETH_CON_CRS_DV_B (1 << ETH_CON_CRS_DV_Pos) +#define ETH_CON_CRS_DV_C (2 << ETH_CON_CRS_DV_Pos) +#define ETH_CON_CRS_DV_D (3 << ETH_CON_CRS_DV_Pos) + +#define ETH_CON_CLK_RMII_A (0 << ETH_CON_CLK_RMII_Pos) +#define ETH_CON_CLK_RMII_B (1 << ETH_CON_CLK_RMII_Pos) +#define ETH_CON_CLK_RMII_C (2 << ETH_CON_CLK_RMII_Pos) +#define ETH_CON_CLK_RMII_D (3 << ETH_CON_CLK_RMII_Pos) + +#define ETH_CON_RXD3_A (0 << ETH_CON_RXD3_Pos) +#define ETH_CON_RXD3_B (1 << ETH_CON_RXD3_Pos) +#define ETH_CON_RXD3_C (2 << ETH_CON_RXD3_Pos) +#define ETH_CON_RXD3_D (3 << ETH_CON_RXD3_Pos) + +#define ETH_CON_RXD2_A (0 << ETH_CON_RXD2_Pos) +#define ETH_CON_RXD2_B (1 << ETH_CON_RXD2_Pos) +#define ETH_CON_RXD2_C (2 << ETH_CON_RXD2_Pos) +#define ETH_CON_RXD2_D (3 << ETH_CON_RXD2_Pos) + +#define ETH_CON_RXD1_A (0 << ETH_CON_RXD1_Pos) +#define ETH_CON_RXD1_B (1 << ETH_CON_RXD1_Pos) +#define ETH_CON_RXD1_C (2 << ETH_CON_RXD1_Pos) +#define ETH_CON_RXD1_D (3 << ETH_CON_RXD1_Pos) + +#define ETH_CON_RXD0_A (0 << ETH_CON_RXD0_Pos) +#define ETH_CON_RXD0_B (1 << ETH_CON_RXD0_Pos) +#define ETH_CON_RXD0_C (2 << ETH_CON_RXD0_Pos) +#define ETH_CON_RXD0_D (3 << ETH_CON_RXD0_Pos) + +//ETH0_MAC_CONFIGURATION register +#define ETH_MAC_CONFIGURATION_RESERVED15_Msk (1 << 15) + +//ETH0_GMII_ADDRESS register +#define ETH_GMII_ADDRESS_CR_DIV42 (0 << ETH_GMII_ADDRESS_CR_Pos) +#define ETH_GMII_ADDRESS_CR_DIV62 (1 << ETH_GMII_ADDRESS_CR_Pos) +#define ETH_GMII_ADDRESS_CR_DIV16 (2 << ETH_GMII_ADDRESS_CR_Pos) +#define ETH_GMII_ADDRESS_CR_DIV26 (3 << ETH_GMII_ADDRESS_CR_Pos) +#define ETH_GMII_ADDRESS_CR_DIV102 (4 << ETH_GMII_ADDRESS_CR_Pos) +#define ETH_GMII_ADDRESS_CR_DIV124 (5 << ETH_GMII_ADDRESS_CR_Pos) + +//ETH0_BUS_MODE register +#define ETH_BUS_MODE_RPBL_1 (1 << ETH_BUS_MODE_RPBL_Pos) +#define ETH_BUS_MODE_RPBL_2 (2 << ETH_BUS_MODE_RPBL_Pos) +#define ETH_BUS_MODE_RPBL_4 (4 << ETH_BUS_MODE_RPBL_Pos) +#define ETH_BUS_MODE_RPBL_8 (8 << ETH_BUS_MODE_RPBL_Pos) +#define ETH_BUS_MODE_RPBL_16 (16 << ETH_BUS_MODE_RPBL_Pos) +#define ETH_BUS_MODE_RPBL_32 (32 << ETH_BUS_MODE_RPBL_Pos) + +#define ETH_BUS_MODE_PR_1_1 (0 << ETH_BUS_MODE_PR_Pos) +#define ETH_BUS_MODE_PR_2_1 (1 << ETH_BUS_MODE_PR_Pos) +#define ETH_BUS_MODE_PR_3_1 (2 << ETH_BUS_MODE_PR_Pos) +#define ETH_BUS_MODE_PR_4_1 (3 << ETH_BUS_MODE_PR_Pos) + +#define ETH_BUS_MODE_PBL_1 (1 << ETH_BUS_MODE_PBL_Pos) +#define ETH_BUS_MODE_PBL_2 (2 << ETH_BUS_MODE_PBL_Pos) +#define ETH_BUS_MODE_PBL_4 (4 << ETH_BUS_MODE_PBL_Pos) +#define ETH_BUS_MODE_PBL_8 (8 << ETH_BUS_MODE_PBL_Pos) +#define ETH_BUS_MODE_PBL_16 (16 << ETH_BUS_MODE_PBL_Pos) +#define ETH_BUS_MODE_PBL_32 (32 << ETH_BUS_MODE_PBL_Pos) + +//Transmit DMA descriptor flags +#define ETH_TDES0_OWN 0x80000000 +#define ETH_TDES0_IC 0x40000000 +#define ETH_TDES0_LS 0x20000000 +#define ETH_TDES0_FS 0x10000000 +#define ETH_TDES0_DC 0x08000000 +#define ETH_TDES0_DP 0x04000000 +#define ETH_TDES0_TTSE 0x02000000 +#define ETH_TDES0_CIC 0x00C00000 +#define ETH_TDES0_TER 0x00200000 +#define ETH_TDES0_TCH 0x00100000 +#define ETH_TDES0_TTSS 0x00020000 +#define ETH_TDES0_IHE 0x00010000 +#define ETH_TDES0_ES 0x00008000 +#define ETH_TDES0_JT 0x00004000 +#define ETH_TDES0_FF 0x00002000 +#define ETH_TDES0_IPE 0x00001000 +#define ETH_TDES0_LCA 0x00000800 +#define ETH_TDES0_NC 0x00000400 +#define ETH_TDES0_LCO 0x00000200 +#define ETH_TDES0_EC 0x00000100 +#define ETH_TDES0_VF 0x00000080 +#define ETH_TDES0_CC 0x00000078 +#define ETH_TDES0_ED 0x00000004 +#define ETH_TDES0_UF 0x00000002 +#define ETH_TDES0_DB 0x00000001 +#define ETH_TDES1_TBS2 0x1FFF0000 +#define ETH_TDES1_TBS1 0x00001FFF +#define ETH_TDES2_TBAP1 0xFFFFFFFF +#define ETH_TDES3_TBAP2 0xFFFFFFFF + +//Receive DMA descriptor flags +#define ETH_RDES0_OWN 0x80000000 +#define ETH_RDES0_AFM 0x40000000 +#define ETH_RDES0_FL 0x3FFF0000 +#define ETH_RDES0_ES 0x00008000 +#define ETH_RDES0_DE 0x00004000 +#define ETH_RDES0_SAF 0x00002000 +#define ETH_RDES0_LE 0x00001000 +#define ETH_RDES0_OE 0x00000800 +#define ETH_RDES0_VLAN 0x00000400 +#define ETH_RDES0_FS 0x00000200 +#define ETH_RDES0_LS 0x00000100 +#define ETH_RDES0_IPCE_GF 0x00000080 +#define ETH_RDES0_LCO 0x00000040 +#define ETH_RDES0_FT 0x00000020 +#define ETH_RDES0_RWT 0x00000010 +#define ETH_RDES0_RE 0x00000008 +#define ETH_RDES0_DBE 0x00000004 +#define ETH_RDES0_CE 0x00000002 +#define ETH_RDES0_PCE 0x00000001 +#define ETH_RDES1_DIC 0x80000000 +#define ETH_RDES1_RBS2 0x1FFF0000 +#define ETH_RDES1_RER 0x00008000 +#define ETH_RDES1_RCH 0x00004000 +#define ETH_RDES1_RBS1 0x00001FFF +#define ETH_RDES2_RBAP1 0xFFFFFFFF +#define ETH_RDES3_RBAP2 0xFFFFFFFF + +//C++ guard +#ifdef __cplusplus +extern "C" { +#endif + + +/** + * @brief Transmit DMA descriptor + **/ + +typedef struct +{ + uint32_t tdes0; + uint32_t tdes1; + uint32_t tdes2; + uint32_t tdes3; +} Xmc4400TxDmaDesc; + + +/** + * @brief Receive DMA descriptor + **/ + +typedef struct +{ + uint32_t rdes0; + uint32_t rdes1; + uint32_t rdes2; + uint32_t rdes3; +} Xmc4400RxDmaDesc; + + +//XMC4400 Ethernet MAC driver +extern const NicDriver xmc4400EthDriver; + +//XMC4400 Ethernet MAC related functions +error_t xmc4400EthInit(NetInterface *interface); +void xmc4400EthInitGpio(NetInterface *interface); +void xmc4400EthInitDmaDesc(NetInterface *interface); + +void xmc4400EthTick(NetInterface *interface); + +void xmc4400EthEnableIrq(NetInterface *interface); +void xmc4400EthDisableIrq(NetInterface *interface); +void xmc4400EthEventHandler(NetInterface *interface); + +error_t xmc4400EthSendPacket(NetInterface *interface, + const NetBuffer *buffer, size_t offset, NetTxAncillary *ancillary); + +error_t xmc4400EthReceivePacket(NetInterface *interface); + +error_t xmc4400EthUpdateMacAddrFilter(NetInterface *interface); +error_t xmc4400EthUpdateMacConfig(NetInterface *interface); + +void xmc4400EthWritePhyReg(uint8_t opcode, uint8_t phyAddr, + uint8_t regAddr, uint16_t data); + +uint16_t xmc4400EthReadPhyReg(uint8_t opcode, uint8_t phyAddr, + uint8_t regAddr); + +uint32_t xmc4400EthCalcCrc(const void *data, size_t length); + +//C++ guard +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/mac/xmc4500_eth_driver.c b/drivers/mac/xmc4500_eth_driver.c index ad8ecb76..f8aaf2bb 100644 --- a/drivers/mac/xmc4500_eth_driver.c +++ b/drivers/mac/xmc4500_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/xmc4500_eth_driver.h b/drivers/mac/xmc4500_eth_driver.h index 7ed488b1..45f6b687 100644 --- a/drivers/mac/xmc4500_eth_driver.h +++ b/drivers/mac/xmc4500_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _XMC4500_ETH_DRIVER_H diff --git a/drivers/mac/xmc4700_eth_driver.c b/drivers/mac/xmc4700_eth_driver.c index 930b493c..3aa2dff3 100644 --- a/drivers/mac/xmc4700_eth_driver.c +++ b/drivers/mac/xmc4700_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/xmc4700_eth_driver.h b/drivers/mac/xmc4700_eth_driver.h index 79fa0380..2a1a30ea 100644 --- a/drivers/mac/xmc4700_eth_driver.h +++ b/drivers/mac/xmc4700_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _XMC4700_ETH_DRIVER_H diff --git a/drivers/mac/xmc4800_eth_driver.c b/drivers/mac/xmc4800_eth_driver.c index 76c53368..8de48334 100644 --- a/drivers/mac/xmc4800_eth_driver.c +++ b/drivers/mac/xmc4800_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/mac/xmc4800_eth_driver.h b/drivers/mac/xmc4800_eth_driver.h index 702a1f36..bb30e188 100644 --- a/drivers/mac/xmc4800_eth_driver.h +++ b/drivers/mac/xmc4800_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _XMC4800_ETH_DRIVER_H diff --git a/drivers/mac/zynq7000_eth_driver.c b/drivers/mac/zynq7000_eth_driver.c index eebb2986..f1088b50 100644 --- a/drivers/mac/zynq7000_eth_driver.c +++ b/drivers/mac/zynq7000_eth_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -66,7 +66,7 @@ static Zynq7000TxBufferDesc txBufferDesc[ZYNQ7000_ETH_TX_BUFFER_COUNT]; #pragma location = ZYNQ7000_ETH_RAM_SECTION static Zynq7000RxBufferDesc rxBufferDesc[ZYNQ7000_ETH_RX_BUFFER_COUNT]; -//Keil MDK-ARM or GCC compiler? +//GCC compiler? #else //TX buffer diff --git a/drivers/mac/zynq7000_eth_driver.h b/drivers/mac/zynq7000_eth_driver.h index 6bfe1dab..50388fce 100644 --- a/drivers/mac/zynq7000_eth_driver.h +++ b/drivers/mac/zynq7000_eth_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ZYNQ7000_ETH_DRIVER_H diff --git a/drivers/pcap/pcap_driver.c b/drivers/pcap/pcap_driver.c index 73346c86..6f1f8db0 100644 --- a/drivers/pcap/pcap_driver.c +++ b/drivers/pcap/pcap_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/pcap/pcap_driver.h b/drivers/pcap/pcap_driver.h index 72b702c8..fa28e26f 100644 --- a/drivers/pcap/pcap_driver.h +++ b/drivers/pcap/pcap_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _PCAP_DRIVER_H diff --git a/drivers/phy/ar8031_driver.c b/drivers/phy/ar8031_driver.c index 2be38a39..52bf6dc2 100644 --- a/drivers/phy/ar8031_driver.c +++ b/drivers/phy/ar8031_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ar8031_driver.h b/drivers/phy/ar8031_driver.h index 9c68fc0b..e22648bd 100644 --- a/drivers/phy/ar8031_driver.h +++ b/drivers/phy/ar8031_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _AR8031_DRIVER_H diff --git a/drivers/phy/ar8035_driver.c b/drivers/phy/ar8035_driver.c index 462e03dc..04532ab9 100644 --- a/drivers/phy/ar8035_driver.c +++ b/drivers/phy/ar8035_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ar8035_driver.h b/drivers/phy/ar8035_driver.h index edbddcf8..c574ba52 100644 --- a/drivers/phy/ar8035_driver.h +++ b/drivers/phy/ar8035_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _AR8035_DRIVER_H diff --git a/drivers/phy/dm9161_driver.c b/drivers/phy/dm9161_driver.c index 5e6f91f1..61472496 100644 --- a/drivers/phy/dm9161_driver.c +++ b/drivers/phy/dm9161_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/dm9161_driver.h b/drivers/phy/dm9161_driver.h index 6cc2a8a4..680ddbb1 100644 --- a/drivers/phy/dm9161_driver.h +++ b/drivers/phy/dm9161_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DM9161_DRIVER_H diff --git a/drivers/phy/dp83620_driver.c b/drivers/phy/dp83620_driver.c index 78ef3c28..30edc32e 100644 --- a/drivers/phy/dp83620_driver.c +++ b/drivers/phy/dp83620_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/dp83620_driver.h b/drivers/phy/dp83620_driver.h index 3d7005ae..2bfa4244 100644 --- a/drivers/phy/dp83620_driver.h +++ b/drivers/phy/dp83620_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DP83620_DRIVER_H diff --git a/drivers/phy/dp83630_driver.c b/drivers/phy/dp83630_driver.c index e08a7c13..497af6cb 100644 --- a/drivers/phy/dp83630_driver.c +++ b/drivers/phy/dp83630_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/dp83630_driver.h b/drivers/phy/dp83630_driver.h index 3e5a7353..65eb0fd2 100644 --- a/drivers/phy/dp83630_driver.h +++ b/drivers/phy/dp83630_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DP83630_DRIVER_H diff --git a/drivers/phy/dp83640_driver.c b/drivers/phy/dp83640_driver.c index 8d19d477..247835de 100644 --- a/drivers/phy/dp83640_driver.c +++ b/drivers/phy/dp83640_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/dp83640_driver.h b/drivers/phy/dp83640_driver.h index dc1cc8a7..cad1f6fc 100644 --- a/drivers/phy/dp83640_driver.h +++ b/drivers/phy/dp83640_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DP83640_DRIVER_H diff --git a/drivers/phy/dp83822_driver.c b/drivers/phy/dp83822_driver.c index c88370fb..bdcb0ac9 100644 --- a/drivers/phy/dp83822_driver.c +++ b/drivers/phy/dp83822_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/dp83822_driver.h b/drivers/phy/dp83822_driver.h index 07ea55e8..9c4d046c 100644 --- a/drivers/phy/dp83822_driver.h +++ b/drivers/phy/dp83822_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DP83822_DRIVER_H diff --git a/drivers/phy/dp83848_driver.c b/drivers/phy/dp83848_driver.c index 8fb9cf73..aea0b222 100644 --- a/drivers/phy/dp83848_driver.c +++ b/drivers/phy/dp83848_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/dp83848_driver.h b/drivers/phy/dp83848_driver.h index 24f758fe..b4acb874 100644 --- a/drivers/phy/dp83848_driver.h +++ b/drivers/phy/dp83848_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DP83848_DRIVER_H diff --git a/drivers/phy/dp83tc811_driver.c b/drivers/phy/dp83tc811_driver.c index 9d1f3828..c52f8e97 100644 --- a/drivers/phy/dp83tc811_driver.c +++ b/drivers/phy/dp83tc811_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/dp83tc811_driver.h b/drivers/phy/dp83tc811_driver.h index aafb2476..7ff1eddc 100644 --- a/drivers/phy/dp83tc811_driver.h +++ b/drivers/phy/dp83tc811_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DP83TC811_DRIVER_H diff --git a/drivers/phy/ip101_driver.c b/drivers/phy/ip101_driver.c index 2a0fcd90..d7395475 100644 --- a/drivers/phy/ip101_driver.c +++ b/drivers/phy/ip101_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ip101_driver.h b/drivers/phy/ip101_driver.h index 1dd040cc..feb49b20 100644 --- a/drivers/phy/ip101_driver.h +++ b/drivers/phy/ip101_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IP101_DRIVER_H diff --git a/drivers/phy/ksz8031_driver.c b/drivers/phy/ksz8031_driver.c index 2107db86..df4d4a84 100644 --- a/drivers/phy/ksz8031_driver.c +++ b/drivers/phy/ksz8031_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ksz8031_driver.h b/drivers/phy/ksz8031_driver.h index e6e060fc..465feb54 100644 --- a/drivers/phy/ksz8031_driver.h +++ b/drivers/phy/ksz8031_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8031_DRIVER_H diff --git a/drivers/phy/ksz8041_driver.c b/drivers/phy/ksz8041_driver.c index c85a82d5..3e4479d3 100644 --- a/drivers/phy/ksz8041_driver.c +++ b/drivers/phy/ksz8041_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ksz8041_driver.h b/drivers/phy/ksz8041_driver.h index 67d4116a..4c7c7b05 100644 --- a/drivers/phy/ksz8041_driver.h +++ b/drivers/phy/ksz8041_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8041_DRIVER_H diff --git a/drivers/phy/ksz8051_driver.c b/drivers/phy/ksz8051_driver.c index 7821d3e7..24695e01 100644 --- a/drivers/phy/ksz8051_driver.c +++ b/drivers/phy/ksz8051_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ksz8051_driver.h b/drivers/phy/ksz8051_driver.h index 862f4c29..07b8b8c2 100644 --- a/drivers/phy/ksz8051_driver.h +++ b/drivers/phy/ksz8051_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8051_DRIVER_H diff --git a/drivers/phy/ksz8061_driver.c b/drivers/phy/ksz8061_driver.c index 4d6584f9..18268948 100644 --- a/drivers/phy/ksz8061_driver.c +++ b/drivers/phy/ksz8061_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ksz8061_driver.h b/drivers/phy/ksz8061_driver.h index eb914526..97c29e76 100644 --- a/drivers/phy/ksz8061_driver.h +++ b/drivers/phy/ksz8061_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8061_DRIVER_H diff --git a/drivers/phy/ksz8081_driver.c b/drivers/phy/ksz8081_driver.c index 01d41ea3..49fb0f2d 100644 --- a/drivers/phy/ksz8081_driver.c +++ b/drivers/phy/ksz8081_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ksz8081_driver.h b/drivers/phy/ksz8081_driver.h index d2060a9c..a755c915 100644 --- a/drivers/phy/ksz8081_driver.h +++ b/drivers/phy/ksz8081_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8081_DRIVER_H diff --git a/drivers/phy/ksz8091_driver.c b/drivers/phy/ksz8091_driver.c index 927da0d3..3baf51c3 100644 --- a/drivers/phy/ksz8091_driver.c +++ b/drivers/phy/ksz8091_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ksz8091_driver.h b/drivers/phy/ksz8091_driver.h index 4b0f35a4..e914240c 100644 --- a/drivers/phy/ksz8091_driver.h +++ b/drivers/phy/ksz8091_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8091_DRIVER_H diff --git a/drivers/phy/ksz8721_driver.c b/drivers/phy/ksz8721_driver.c index 5e73124c..8b1f19c7 100644 --- a/drivers/phy/ksz8721_driver.c +++ b/drivers/phy/ksz8721_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ksz8721_driver.h b/drivers/phy/ksz8721_driver.h index 330299fe..50d76156 100644 --- a/drivers/phy/ksz8721_driver.h +++ b/drivers/phy/ksz8721_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8721_DRIVER_H diff --git a/drivers/phy/ksz9031_driver.c b/drivers/phy/ksz9031_driver.c index f2dca130..12a58f81 100644 --- a/drivers/phy/ksz9031_driver.c +++ b/drivers/phy/ksz9031_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/ksz9031_driver.h b/drivers/phy/ksz9031_driver.h index 1229e7ff..d5c30222 100644 --- a/drivers/phy/ksz9031_driver.h +++ b/drivers/phy/ksz9031_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ9031_DRIVER_H diff --git a/drivers/phy/ksz9131_driver.c b/drivers/phy/ksz9131_driver.c new file mode 100644 index 00000000..c59a6e24 --- /dev/null +++ b/drivers/phy/ksz9131_driver.c @@ -0,0 +1,324 @@ +/** + * @file ksz9131_driver.c + * @brief KSZ9131 Gigabit Ethernet PHY driver + * + * @section License + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. + * + * This file is part of CycloneTCP Open. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * @author Oryx Embedded SARL (www.oryx-embedded.com) + * @version 2.0.2 + **/ + +//Switch to the appropriate trace level +#define TRACE_LEVEL NIC_TRACE_LEVEL + +//Dependencies +#include "core/net.h" +#include "drivers/phy/ksz9131_driver.h" +#include "debug.h" + + +/** + * @brief KSZ9131 Ethernet PHY driver + **/ + +const PhyDriver ksz9131PhyDriver = +{ + ksz9131Init, + ksz9131Tick, + ksz9131EnableIrq, + ksz9131DisableIrq, + ksz9131EventHandler +}; + + +/** + * @brief KSZ9131 PHY transceiver initialization + * @param[in] interface Underlying network interface + * @return Error code + **/ + +error_t ksz9131Init(NetInterface *interface) +{ + //Debug message + TRACE_INFO("Initializing KSZ9131...\r\n"); + + //Undefined PHY address? + if(interface->phyAddr >= 32) + { + //Use the default address + interface->phyAddr = KSZ9131_PHY_ADDR; + } + + //Initialize serial management interface + if(interface->smiDriver != NULL) + { + interface->smiDriver->init(); + } + + //Initialize external interrupt line driver + if(interface->extIntDriver != NULL) + { + interface->extIntDriver->init(); + } + + //Reset PHY transceiver + ksz9131WritePhyReg(interface, KSZ9131_BMCR, KSZ9131_BMCR_RESET); + + //Wait for the reset to complete + while(ksz9131ReadPhyReg(interface, KSZ9131_BMCR) & KSZ9131_BMCR_RESET) + { + } + + //Dump PHY registers for debugging purpose + ksz9131DumpPhyReg(interface); + + //The PHY will generate interrupts when link status changes are detected + ksz9131WritePhyReg(interface, KSZ9131_ICSR, KSZ9131_ICSR_LINK_DOWN_IE | + KSZ9131_ICSR_LINK_UP_IE); + + //Force the TCP/IP stack to poll the link state at startup + interface->phyEvent = TRUE; + //Notify the TCP/IP stack of the event + osSetEvent(&netEvent); + + //Successful initialization + return NO_ERROR; +} + + +/** + * @brief KSZ9131 timer handler + * @param[in] interface Underlying network interface + **/ + +void ksz9131Tick(NetInterface *interface) +{ + uint16_t value; + bool_t linkState; + + //No external interrupt line driver? + if(interface->extIntDriver == NULL) + { + //Read basic status register + value = ksz9131ReadPhyReg(interface, KSZ9131_BMSR); + //Retrieve current link state + linkState = (value & KSZ9131_BMSR_LINK_STATUS) ? TRUE : FALSE; + + //Link up event? + if(linkState && !interface->linkState) + { + //Set event flag + interface->phyEvent = TRUE; + //Notify the TCP/IP stack of the event + osSetEvent(&netEvent); + } + //Link down event? + else if(!linkState && interface->linkState) + { + //Set event flag + interface->phyEvent = TRUE; + //Notify the TCP/IP stack of the event + osSetEvent(&netEvent); + } + } +} + + +/** + * @brief Enable interrupts + * @param[in] interface Underlying network interface + **/ + +void ksz9131EnableIrq(NetInterface *interface) +{ + //Enable PHY transceiver interrupts + if(interface->extIntDriver != NULL) + { + interface->extIntDriver->enableIrq(); + } +} + + +/** + * @brief Disable interrupts + * @param[in] interface Underlying network interface + **/ + +void ksz9131DisableIrq(NetInterface *interface) +{ + //Disable PHY transceiver interrupts + if(interface->extIntDriver != NULL) + { + interface->extIntDriver->disableIrq(); + } +} + + +/** + * @brief KSZ9131 event handler + * @param[in] interface Underlying network interface + **/ + +void ksz9131EventHandler(NetInterface *interface) +{ + uint16_t value; + + //Read status register to acknowledge the interrupt + value = ksz9131ReadPhyReg(interface, KSZ9131_ICSR); + + //Link status change? + if((value & (KSZ9131_ICSR_LINK_DOWN_IF | KSZ9131_ICSR_LINK_UP_IF)) != 0) + { + //Any link failure condition is latched in the BMSR register. Reading + //the register twice will always return the actual link status + value = ksz9131ReadPhyReg(interface, KSZ9131_BMSR); + value = ksz9131ReadPhyReg(interface, KSZ9131_BMSR); + + //Link is up? + if((value & KSZ9131_BMSR_LINK_STATUS) != 0) + { + //Read PHY control register + value = ksz9131ReadPhyReg(interface, KSZ9131_PHYCON); + + //Check current speed + if((value & KSZ9131_PHYCON_SPEED_1000BT) != 0) + { + //1000BASE-T + interface->linkSpeed = NIC_LINK_SPEED_1GBPS; + } + else if((value & KSZ9131_PHYCON_SPEED_100BTX) != 0) + { + //100BASE-TX + interface->linkSpeed = NIC_LINK_SPEED_100MBPS; + } + else if((value & KSZ9131_PHYCON_SPEED_10BT) != 0) + { + //10BASE-T + interface->linkSpeed = NIC_LINK_SPEED_10MBPS; + } + else + { + //Debug message + TRACE_WARNING("Invalid speed!\r\n"); + } + + //Check current duplex mode + if((value & KSZ9131_PHYCON_DUPLEX_STATUS) != 0) + { + interface->duplexMode = NIC_FULL_DUPLEX_MODE; + } + else + { + interface->duplexMode = NIC_HALF_DUPLEX_MODE; + } + + //Update link state + interface->linkState = TRUE; + + //Adjust MAC configuration parameters for proper operation + interface->nicDriver->updateMacConfig(interface); + } + else + { + //Update link state + interface->linkState = FALSE; + } + + //Process link state change event + nicNotifyLinkChange(interface); + } +} + + +/** + * @brief Write PHY register + * @param[in] interface Underlying network interface + * @param[in] address PHY register address + * @param[in] data Register value + **/ + +void ksz9131WritePhyReg(NetInterface *interface, uint8_t address, + uint16_t data) +{ + //Write the specified PHY register + if(interface->smiDriver != NULL) + { + interface->smiDriver->writePhyReg(SMI_OPCODE_WRITE, + interface->phyAddr, address, data); + } + else + { + interface->nicDriver->writePhyReg(SMI_OPCODE_WRITE, + interface->phyAddr, address, data); + } +} + + +/** + * @brief Read PHY register + * @param[in] interface Underlying network interface + * @param[in] address PHY register address + * @return Register value + **/ + +uint16_t ksz9131ReadPhyReg(NetInterface *interface, uint8_t address) +{ + uint16_t data; + + //Read the specified PHY register + if(interface->smiDriver != NULL) + { + data = interface->smiDriver->readPhyReg(SMI_OPCODE_READ, + interface->phyAddr, address); + } + else + { + data = interface->nicDriver->readPhyReg(SMI_OPCODE_READ, + interface->phyAddr, address); + } + + //Return the value of the PHY register + return data; +} + + +/** + * @brief Dump PHY registers for debugging purpose + * @param[in] interface Underlying network interface + **/ + +void ksz9131DumpPhyReg(NetInterface *interface) +{ + uint8_t i; + + //Loop through PHY registers + for(i = 0; i < 32; i++) + { + //Display current PHY register + TRACE_DEBUG("%02" PRIu8 ": 0x%04" PRIX16 "\r\n", i, + ksz9131ReadPhyReg(interface, i)); + } + + //Terminate with a line feed + TRACE_DEBUG("\r\n"); +} diff --git a/drivers/phy/ksz9131_driver.h b/drivers/phy/ksz9131_driver.h new file mode 100644 index 00000000..7a7a6ee6 --- /dev/null +++ b/drivers/phy/ksz9131_driver.h @@ -0,0 +1,315 @@ +/** + * @file ksz9131_driver.h + * @brief KSZ9131 Gigabit Ethernet PHY driver + * + * @section License + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. + * + * This file is part of CycloneTCP Open. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * @author Oryx Embedded SARL (www.oryx-embedded.com) + * @version 2.0.2 + **/ + +#ifndef _KSZ9131_DRIVER_H +#define _KSZ9131_DRIVER_H + +//Dependencies +#include "core/nic.h" + +//PHY address +#ifndef KSZ9131_PHY_ADDR + #define KSZ9131_PHY_ADDR 7 +#elif (KSZ9131_PHY_ADDR < 0 || KSZ9131_PHY_ADDR > 31) + #error KSZ9131_PHY_ADDR parameter is not valid +#endif + +//KSZ9131 PHY registers +#define KSZ9131_BMCR 0x00 +#define KSZ9131_BMSR 0x01 +#define KSZ9131_PHYID1 0x02 +#define KSZ9131_PHYID2 0x03 +#define KSZ9131_ANAR 0x04 +#define KSZ9131_ANLPAR 0x05 +#define KSZ9131_ANER 0x06 +#define KSZ9131_ANNPR 0x07 +#define KSZ9131_ANLPNPR 0x08 +#define KSZ9131_GBCR 0x09 +#define KSZ9131_GBSR 0x0A +#define KSZ9131_MMDACR 0x0D +#define KSZ9131_MMDAADR 0x0E +#define KSZ9131_GBESR 0x0F +#define KSZ9131_RLB 0x11 +#define KSZ9131_LINKMD 0x12 +#define KSZ9131_DPMAPCSS 0x13 +#define KSZ9131_RXERCTR 0x15 +#define KSZ9131_LED_MODE_SEL 0x16 +#define KSZ9131_LED_BEHAVIOR 0x17 +#define KSZ9131_MDIO_DRIVE 0x19 +#define KSZ9131_LEGACY_LED_MODE 0x1A +#define KSZ9131_ICSR 0x1B +#define KSZ9131_AUTOMDI 0x1C +#define KSZ9131_SPDC 0x1D +#define KSZ9131_EXT_LOOPBACK 0x1E +#define KSZ9131_PHYCON 0x1F + +//Basic Control register +#define KSZ9131_BMCR_RESET 0x8000 +#define KSZ9131_BMCR_LOOPBACK 0x4000 +#define KSZ9131_BMCR_SPEED_SEL_LSB 0x2000 +#define KSZ9131_BMCR_AN_EN 0x1000 +#define KSZ9131_BMCR_POWER_DOWN 0x0800 +#define KSZ9131_BMCR_ISOLATE 0x0400 +#define KSZ9131_BMCR_RESTART_AN 0x0200 +#define KSZ9131_BMCR_DUPLEX_MODE 0x0100 +#define KSZ9131_BMCR_COL_TEST 0x0080 +#define KSZ9131_BMCR_SPEED_SEL_MSB 0x0040 + +//Basic Status register +#define KSZ9131_BMSR_100BT4 0x8000 +#define KSZ9131_BMSR_100BTX_FD 0x4000 +#define KSZ9131_BMSR_100BTX_HD 0x2000 +#define KSZ9131_BMSR_10BT_FD 0x1000 +#define KSZ9131_BMSR_10BT_HD 0x0800 +#define KSZ9131_BMSR_100BT2_FD 0x0400 +#define KSZ9131_BMSR_100BT2_HD 0x0200 +#define KSZ9131_BMSR_EXTENDED_STATUS 0x0100 +#define KSZ9131_BMSR_UNIDIRECTIONAL_ABLE 0x0080 +#define KSZ9131_BMSR_MF_PREAMBLE_SUPPR 0x0040 +#define KSZ9131_BMSR_AN_COMPLETE 0x0020 +#define KSZ9131_BMSR_REMOTE_FAULT 0x0010 +#define KSZ9131_BMSR_AN_CAPABLE 0x0008 +#define KSZ9131_BMSR_LINK_STATUS 0x0004 +#define KSZ9131_BMSR_JABBER_DETECT 0x0002 +#define KSZ9131_BMSR_EXTENDED_CAPABLE 0x0001 + +//PHY Identifier 1 register +#define KSZ9131_PHYID1_PHY_ID_MSB 0xFFFF +#define KSZ9131_PHYID1_PHY_ID_MSB_DEFAULT 0x0022 + +//PHY Identifier 2 register +#define KSZ9131_PHYID2_PHY_ID_LSB 0xFC00 +#define KSZ9131_PHYID2_PHY_ID_LSB_DEFAULT 0x1400 +#define KSZ9131_PHYID2_MODEL_NUM 0x03F0 +#define KSZ9131_PHYID2_MODEL_NUM_DEFAULT 0x0240 +#define KSZ9131_PHYID2_REVISION_NUM 0x000F + +//Auto-Negotiation Advertisement register +#define KSZ9131_ANAR_NEXT_PAGE 0x8000 +#define KSZ9131_ANAR_REMOTE_FAULT 0x2000 +#define KSZ9131_ANAR_EXTENDED_NEXT_PAGE 0x1000 +#define KSZ9131_ANAR_ASYM_PAUSE 0x0800 +#define KSZ9131_ANAR_SYM_PAUSE 0x0400 +#define KSZ9131_ANAR_100BT4 0x0200 +#define KSZ9131_ANAR_100BTX_FD 0x0100 +#define KSZ9131_ANAR_100BTX_HD 0x0080 +#define KSZ9131_ANAR_10BT_FD 0x0040 +#define KSZ9131_ANAR_10BT_HD 0x0020 +#define KSZ9131_ANAR_SELECTOR 0x001F +#define KSZ9131_ANAR_SELECTOR_DEFAULT 0x0001 + +//Auto-Negotiation Link Partner Ability register +#define KSZ9131_ANLPAR_NEXT_PAGE 0x8000 +#define KSZ9131_ANLPAR_ACK 0x4000 +#define KSZ9131_ANLPAR_REMOTE_FAULT 0x2000 +#define KSZ9131_ANLPAR_EXTENDED_NEXT_PAGE 0x1000 +#define KSZ9131_ANLPAR_ASYM_PAUSE 0x0800 +#define KSZ9131_ANLPAR_PAUSE 0x0400 +#define KSZ9131_ANLPAR_100BT4 0x0200 +#define KSZ9131_ANLPAR_100BTX_FD 0x0100 +#define KSZ9131_ANLPAR_100BTX_HD 0x0080 +#define KSZ9131_ANLPAR_10BT_FD 0x0040 +#define KSZ9131_ANLPAR_10BT_HD 0x0020 +#define KSZ9131_ANLPAR_SELECTOR 0x001F +#define KSZ9131_ANLPAR_SELECTOR_DEFAULT 0x0001 + +//Auto-Negotiation Expansion register +#define KSZ9131_ANER_RECEIVE_NP_LOC_ABLE 0x0040 +#define KSZ9131_ANER_RECEIVE_NP_STOR_LOC 0x0020 +#define KSZ9131_ANER_PAR_DETECT_FAULT 0x0010 +#define KSZ9131_ANER_LP_NEXT_PAGE_ABLE 0x0008 +#define KSZ9131_ANER_NEXT_PAGE_ABLE 0x0004 +#define KSZ9131_ANER_PAGE_RECEIVED 0x0002 +#define KSZ9131_ANER_LP_AN_ABLE 0x0001 + +//Auto-Negotiation Next Page TX register +#define KSZ9131_ANNPR_NEXT_PAGE 0x8000 +#define KSZ9131_ANNPR_MSG_PAGE 0x2000 +#define KSZ9131_ANNPR_ACK2 0x1000 +#define KSZ9131_ANNPR_TOGGLE 0x0800 +#define KSZ9131_ANNPR_MESSAGE 0x07FF + +//Auto-Negotiation Next Page RX register +#define KSZ9131_ANLPNPR_NEXT_PAGE 0x8000 +#define KSZ9131_ANLPNPR_ACK 0x4000 +#define KSZ9131_ANLPNPR_MSG_PAGE 0x2000 +#define KSZ9131_ANLPNPR_ACK2 0x1000 +#define KSZ9131_ANLPNPR_TOGGLE 0x0800 +#define KSZ9131_ANLPNPR_MESSAGE 0x07FF + +//Auto-Negotiation Master Slave Control register +#define KSZ9131_GBCR_TEST_MODE 0xE000 +#define KSZ9131_GBCR_MS_MAN_CONF_EN 0x1000 +#define KSZ9131_GBCR_MS_MAN_CONF_VAL 0x0800 +#define KSZ9131_GBCR_PORT_TYPE 0x0400 +#define KSZ9131_GBCR_1000BT_FD 0x0200 +#define KSZ9131_GBCR_1000BT_HD 0x0100 + +//Auto-Negotiation Master Slave Status register +#define KSZ9131_GBSR_MS_CONF_FAULT 0x8000 +#define KSZ9131_GBSR_MS_CONF_RES 0x4000 +#define KSZ9131_GBSR_LOCAL_RECEIVER_STATUS 0x2000 +#define KSZ9131_GBSR_REMOTE_RECEIVER_STATUS 0x1000 +#define KSZ9131_GBSR_LP_1000BT_FD 0x0800 +#define KSZ9131_GBSR_LP_1000BT_HD 0x0400 +#define KSZ9131_GBSR_IDLE_ERR_COUNT 0x00FF + +//MMD Access Control register +#define KSZ9131_MMDACR_FUNC 0xC000 +#define KSZ9131_MMDACR_FUNC_ADDR 0x0000 +#define KSZ9131_MMDACR_FUNC_DATA_NO_POST_INC 0x4000 +#define KSZ9131_MMDACR_FUNC_DATA_POST_INC_RW 0x8000 +#define KSZ9131_MMDACR_FUNC_DATA_POST_INC_W 0xC000 +#define KSZ9131_MMDACR_DEVAD 0x001F + +//Extended Status register +#define KSZ9131_GBESR_1000BX_FD 0x8000 +#define KSZ9131_GBESR_1000BX_HD 0x4000 +#define KSZ9131_GBESR_1000BT_FD 0x2000 +#define KSZ9131_GBESR_1000BT_HD 0x1000 + +//Remote Loopback register +#define KSZ9131_RLB_REMOTE_LOOPBACK 0x0100 + +//LinkMD Cable Diagnostic register +#define KSZ9131_LINKMD_TEST_EN 0x8000 +#define KSZ9131_LINKMD_TX_DIS 0x4000 +#define KSZ9131_LINKMD_PAIR 0x3000 +#define KSZ9131_LINKMD_PAIR_A 0x0000 +#define KSZ9131_LINKMD_PAIR_B 0x1000 +#define KSZ9131_LINKMD_PAIR_C 0x2000 +#define KSZ9131_LINKMD_PAIR_D 0x3000 +#define KSZ9131_LINKMD_SEL 0x0C00 +#define KSZ9131_LINKMD_STATUS 0x0300 +#define KSZ9131_LINKMD_STATUS_NORMAL 0x0000 +#define KSZ9131_LINKMD_STATUS_OPEN 0x0100 +#define KSZ9131_LINKMD_STATUS_SHORT 0x0200 +#define KSZ9131_LINKMD_STATUS_TEST_FAILED 0x0300 +#define KSZ9131_LINKMD_FAULT_DATA 0x00FF + +//Digital PMA/PCS Status register +#define KSZ9131_DPMAPCSS_1000BT_LINK_STATUS 0x0002 +#define KSZ9131_DPMAPCSS_100BTX_LINK_STATUS 0x0001 + +//LED Mode Select register +#define KSZ9131_LED_MODE_SEL_LED2_CONFIG 0x00F0 +#define KSZ9131_LED_MODE_SEL_LED1_CONFIG 0x000F + +//LED Behavior register +#define KSZ9131_LED_BEHAVIOR_LED_ACT_OUT_SEL 0x4000 +#define KSZ9131_LED_BEHAVIOR_LED_PULSING_EN 0x1000 +#define KSZ9131_LED_BEHAVIOR_LED_BLINK_RATE 0x0C00 +#define KSZ9131_LED_BEHAVIOR_LED_BLINK_RATE_2_5HZ 0x0000 +#define KSZ9131_LED_BEHAVIOR_LED_BLINK_RATE_5HZ 0x0400 +#define KSZ9131_LED_BEHAVIOR_LED_BLINK_RATE_10HZ 0x0800 +#define KSZ9131_LED_BEHAVIOR_LED_BLINK_RATE_20HZ 0x0C00 +#define KSZ9131_LED_BEHAVIOR_LED_PULSE_STRECH_EN 0x0060 +#define KSZ9131_LED_BEHAVIOR_LED_COMBINATION 0x0003 + +//MDIO Drive register +#define KSZ9131_MDIO_DRIVE_MDIO_DRIVE 0x0002 + +//KSZ9031 LED Mode register +#define KSZ9131_LEGACY_LED_MODE_KSZ9031_LED_MODE 0x4000 + +//Interrupt Control/Status register +#define KSZ9131_ICSR_JABBER_IE 0x8000 +#define KSZ9131_ICSR_RECEIVE_ERROR_IE 0x4000 +#define KSZ9131_ICSR_PAGE_RECEIVED_IE 0x2000 +#define KSZ9131_ICSR_PAR_DETECT_FAULT_IE 0x1000 +#define KSZ9131_ICSR_LP_ACK_IE 0x0800 +#define KSZ9131_ICSR_LINK_DOWN_IE 0x0400 +#define KSZ9131_ICSR_REMOTE_FAULT_IE 0x0200 +#define KSZ9131_ICSR_LINK_UP_IE 0x0100 +#define KSZ9131_ICSR_JABBER_IF 0x0080 +#define KSZ9131_ICSR_RECEIVE_ERROR_IF 0x0040 +#define KSZ9131_ICSR_PAGE_RECEIVED_IF 0x0020 +#define KSZ9131_ICSR_PAR_DETECT_FAULT_IF 0x0010 +#define KSZ9131_ICSR_LP_ACK_IF 0x0008 +#define KSZ9131_ICSR_LINK_DOWN_IF 0x0004 +#define KSZ9131_ICSR_REMOTE_FAULT_IF 0x0002 +#define KSZ9131_ICSR_LINK_UP_IF 0x0001 + +//Auto MDI/MDI-X register +#define KSZ9131_AUTOMDI_MDI_SET 0x0080 +#define KSZ9131_AUTOMDI_SWAP_OFF 0x0040 + +//Software Power Down Control register +#define KSZ9131_SPDC_CLK_GATE_OVERRIDE 0x0800 +#define KSZ9131_SPDC_PLL_DIS 0x0400 +#define KSZ9131_SPDC_IO_DC_TEST_EN 0x0080 +#define KSZ9131_SPDC_VOH 0x0040 + +//External Loopback register +#define KSZ9131_EXT_LOOPBACK_EXT_LPBK 0x0008 + +//Control register +#define KSZ9131_PHYCON_INT_POL_INVERT 0x4000 +#define KSZ9131_PHYCON_JABBER_EN 0x0200 +#define KSZ9131_PHYCON_SQE_TEST_EN 0x0100 +#define KSZ9131_PHYCON_SPEED_1000BT 0x0040 +#define KSZ9131_PHYCON_SPEED_100BTX 0x0020 +#define KSZ9131_PHYCON_SPEED_10BT 0x0010 +#define KSZ9131_PHYCON_DUPLEX_STATUS 0x0008 +#define KSZ9131_PHYCON_1000BT_MS_STATUS 0x0004 +#define KSZ9131_PHYCON_SOFT_RESET 0x0002 +#define KSZ9131_PHYCON_LINK_STATUS_CHECK_FAIL 0x0001 + +//C++ guard +#ifdef __cplusplus +extern "C" { +#endif + +//KSZ9131 Ethernet PHY driver +extern const PhyDriver ksz9131PhyDriver; + +//KSZ9131 related functions +error_t ksz9131Init(NetInterface *interface); + +void ksz9131Tick(NetInterface *interface); + +void ksz9131EnableIrq(NetInterface *interface); +void ksz9131DisableIrq(NetInterface *interface); + +void ksz9131EventHandler(NetInterface *interface); + +void ksz9131WritePhyReg(NetInterface *interface, uint8_t address, + uint16_t data); + +uint16_t ksz9131ReadPhyReg(NetInterface *interface, uint8_t address); + +void ksz9131DumpPhyReg(NetInterface *interface); + +//C++ guard +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/phy/lan8700_driver.c b/drivers/phy/lan8700_driver.c index 332dcd93..b1b49063 100644 --- a/drivers/phy/lan8700_driver.c +++ b/drivers/phy/lan8700_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/lan8700_driver.h b/drivers/phy/lan8700_driver.h index 749fef8e..f3f44deb 100644 --- a/drivers/phy/lan8700_driver.h +++ b/drivers/phy/lan8700_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LAN8700_DRIVER_H diff --git a/drivers/phy/lan8710_driver.c b/drivers/phy/lan8710_driver.c index 04445023..76b1cc66 100644 --- a/drivers/phy/lan8710_driver.c +++ b/drivers/phy/lan8710_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/lan8710_driver.h b/drivers/phy/lan8710_driver.h index 660a47c3..fc77f430 100644 --- a/drivers/phy/lan8710_driver.h +++ b/drivers/phy/lan8710_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LAN8710_DRIVER_H diff --git a/drivers/phy/lan8720_driver.c b/drivers/phy/lan8720_driver.c index 0056e2cd..34883a26 100644 --- a/drivers/phy/lan8720_driver.c +++ b/drivers/phy/lan8720_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/lan8720_driver.h b/drivers/phy/lan8720_driver.h index e419a8b2..31724565 100644 --- a/drivers/phy/lan8720_driver.h +++ b/drivers/phy/lan8720_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LAN8720_DRIVER_H diff --git a/drivers/phy/lan8740_driver.c b/drivers/phy/lan8740_driver.c index 07614428..6a6b3922 100644 --- a/drivers/phy/lan8740_driver.c +++ b/drivers/phy/lan8740_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/lan8740_driver.h b/drivers/phy/lan8740_driver.h index 26fbe17f..523a6328 100644 --- a/drivers/phy/lan8740_driver.h +++ b/drivers/phy/lan8740_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LAN8740_DRIVER_H diff --git a/drivers/phy/lan8742_driver.c b/drivers/phy/lan8742_driver.c index 4217a60f..831b54bc 100644 --- a/drivers/phy/lan8742_driver.c +++ b/drivers/phy/lan8742_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/lan8742_driver.h b/drivers/phy/lan8742_driver.h index 7ef45bdf..9f538ad8 100644 --- a/drivers/phy/lan8742_driver.h +++ b/drivers/phy/lan8742_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LAN8742_DRIVER_H diff --git a/drivers/phy/lan8770_driver.c b/drivers/phy/lan8770_driver.c index 85233918..04d68b01 100644 --- a/drivers/phy/lan8770_driver.c +++ b/drivers/phy/lan8770_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/lan8770_driver.h b/drivers/phy/lan8770_driver.h index 49e23b2e..7be978f1 100644 --- a/drivers/phy/lan8770_driver.h +++ b/drivers/phy/lan8770_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LAN8770_DRIVER_H diff --git a/drivers/phy/mv88e1512_driver.c b/drivers/phy/mv88e1512_driver.c index c1daaf80..b3f118d7 100644 --- a/drivers/phy/mv88e1512_driver.c +++ b/drivers/phy/mv88e1512_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/mv88e1512_driver.h b/drivers/phy/mv88e1512_driver.h index 904d1aa0..5896401b 100644 --- a/drivers/phy/mv88e1512_driver.h +++ b/drivers/phy/mv88e1512_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MV88E1512_DRIVER_H diff --git a/drivers/phy/pef7071_driver.c b/drivers/phy/pef7071_driver.c new file mode 100644 index 00000000..b366d1aa --- /dev/null +++ b/drivers/phy/pef7071_driver.c @@ -0,0 +1,302 @@ +/** + * @file pef7071_driver.c + * @brief PEF7071 Gigabit Ethernet PHY driver + * + * @section License + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. + * + * This file is part of CycloneTCP Open. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * @author Oryx Embedded SARL (www.oryx-embedded.com) + * @version 2.0.2 + **/ + +//Switch to the appropriate trace level +#define TRACE_LEVEL NIC_TRACE_LEVEL + +//Dependencies +#include "core/net.h" +#include "drivers/phy/pef7071_driver.h" +#include "debug.h" + + +/** + * @brief PEF7071 Ethernet PHY driver + **/ + +const PhyDriver pef7071PhyDriver = +{ + pef7071Init, + pef7071Tick, + pef7071EnableIrq, + pef7071DisableIrq, + pef7071EventHandler +}; + + +/** + * @brief PEF7071 PHY transceiver initialization + * @param[in] interface Underlying network interface + * @return Error code + **/ + +error_t pef7071Init(NetInterface *interface) +{ + //Debug message + TRACE_INFO("Initializing PEF7071...\r\n"); + + //Undefined PHY address? + if(interface->phyAddr >= 32) + { + //Use the default address + interface->phyAddr = PEF7071_PHY_ADDR; + } + + //Initialize serial management interface + if(interface->smiDriver != NULL) + { + interface->smiDriver->init(); + } + + //Reset PHY transceiver + pef7071WritePhyReg(interface, PEF7071_CTRL, PEF7071_CTRL_RST); + + //Wait for the reset to complete + while(pef7071ReadPhyReg(interface, PEF7071_CTRL) & PEF7071_CTRL_RST) + { + } + + //Select RMII mode + pef7071WritePhyReg(interface, PEF7071_MIICTRL, PEF7071_MIICTRL_RXCOFF | + PEF7071_MIICTRL_MODE_RMII); + + //The link speed is forced to 10/100 Mbit/s only + pef7071WritePhyReg(interface, PEF7071_GCTRL, 0); + + //Restart auto-negotiation + pef7071WritePhyReg(interface, PEF7071_CTRL, PEF7071_CTRL_ANEN | + PEF7071_CTRL_ANRS); + + //Dump PHY registers for debugging purpose + pef7071DumpPhyReg(interface); + + //Force the TCP/IP stack to poll the link state at startup + interface->phyEvent = TRUE; + //Notify the TCP/IP stack of the event + osSetEvent(&netEvent); + + //Successful initialization + return NO_ERROR; +} + + +/** + * @brief PEF7071 timer handler + * @param[in] interface Underlying network interface + **/ + +void pef7071Tick(NetInterface *interface) +{ + uint16_t value; + bool_t linkState; + + //Read status register + value = pef7071ReadPhyReg(interface, PEF7071_STAT); + //Retrieve current link state + linkState = (value & PEF7071_STAT_LS) ? TRUE : FALSE; + + //Link up event? + if(linkState && !interface->linkState) + { + //Set event flag + interface->phyEvent = TRUE; + //Notify the TCP/IP stack of the event + osSetEvent(&netEvent); + } + //Link down event? + else if(!linkState && interface->linkState) + { + //Set event flag + interface->phyEvent = TRUE; + //Notify the TCP/IP stack of the event + osSetEvent(&netEvent); + } +} + + +/** + * @brief Enable interrupts + * @param[in] interface Underlying network interface + **/ + +void pef7071EnableIrq(NetInterface *interface) +{ +} + + +/** + * @brief Disable interrupts + * @param[in] interface Underlying network interface + **/ + +void pef7071DisableIrq(NetInterface *interface) +{ +} + + +/** + * @brief PEF7071 event handler + * @param[in] interface Underlying network interface + **/ + +void pef7071EventHandler(NetInterface *interface) +{ + uint16_t status; + + //Read status register + status = pef7071ReadPhyReg(interface, PEF7071_STAT); + + //Link is up? + if((status & PEF7071_STAT_LS) != 0) + { + //Read MII status register + status = pef7071ReadPhyReg(interface, PEF7071_MIISTAT); + + //Check current speed + switch(status & PEF7071_MIISTAT_SPEED) + { + //10BASE-T + case PEF7071_MIISTAT_SPEED_TEN: + interface->linkSpeed = NIC_LINK_SPEED_10MBPS; + break; + //100BASE-TX + case PEF7071_MIISTAT_SPEED_FAST: + interface->linkSpeed = NIC_LINK_SPEED_100MBPS; + break; + //1000BASE-T + case PEF7071_MIISTAT_SPEED_GIGA: + interface->linkSpeed = NIC_LINK_SPEED_1GBPS; + break; + //Unknown speed + default: + //Debug message + TRACE_WARNING("Invalid speed\r\n"); + break; + } + + //Check current duplex mode + if((status & PEF7071_MIISTAT_DPX) != 0) + { + interface->duplexMode = NIC_FULL_DUPLEX_MODE; + } + else + { + interface->duplexMode = NIC_HALF_DUPLEX_MODE; + } + + //Update link state + interface->linkState = TRUE; + + //Adjust MAC configuration parameters for proper operation + interface->nicDriver->updateMacConfig(interface); + } + else + { + //Update link state + interface->linkState = FALSE; + } + + //Process link state change event + nicNotifyLinkChange(interface); +} + + +/** + * @brief Write PHY register + * @param[in] interface Underlying network interface + * @param[in] address PHY register address + * @param[in] data Register value + **/ + +void pef7071WritePhyReg(NetInterface *interface, uint8_t address, + uint16_t data) +{ + //Write the specified PHY register + if(interface->smiDriver != NULL) + { + interface->smiDriver->writePhyReg(SMI_OPCODE_WRITE, + interface->phyAddr, address, data); + } + else + { + interface->nicDriver->writePhyReg(SMI_OPCODE_WRITE, + interface->phyAddr, address, data); + } +} + + +/** + * @brief Read PHY register + * @param[in] interface Underlying network interface + * @param[in] address PHY register address + * @return Register value + **/ + +uint16_t pef7071ReadPhyReg(NetInterface *interface, uint8_t address) +{ + uint16_t data; + + //Read the specified PHY register + if(interface->smiDriver != NULL) + { + data = interface->smiDriver->readPhyReg(SMI_OPCODE_READ, + interface->phyAddr, address); + } + else + { + data = interface->nicDriver->readPhyReg(SMI_OPCODE_READ, + interface->phyAddr, address); + } + + //Return the value of the PHY register + return data; +} + + +/** + * @brief Dump PHY registers for debugging purpose + * @param[in] interface Underlying network interface + **/ + +void pef7071DumpPhyReg(NetInterface *interface) +{ + uint8_t i; + + //Loop through PHY registers + for(i = 0; i < 32; i++) + { + //Display current PHY register + TRACE_DEBUG("%02" PRIu8 ": 0x%04" PRIX16 "\r\n", i, + pef7071ReadPhyReg(interface, i)); + } + + //Terminate with a line feed + TRACE_DEBUG("\r\n"); +} diff --git a/drivers/phy/pef7071_driver.h b/drivers/phy/pef7071_driver.h new file mode 100644 index 00000000..2e42cde9 --- /dev/null +++ b/drivers/phy/pef7071_driver.h @@ -0,0 +1,849 @@ +/** + * @file pef7071_driver.h + * @brief PEF7071 Gigabit Ethernet PHY driver + * + * @section License + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. + * + * This file is part of CycloneTCP Open. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software Foundation, + * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. + * + * @author Oryx Embedded SARL (www.oryx-embedded.com) + * @version 2.0.2 + **/ + +#ifndef _PEF7071_DRIVER_H +#define _PEF7071_DRIVER_H + +//Dependencies +#include "core/nic.h" + +//PHY address +#ifndef PEF7071_PHY_ADDR + #define PEF7071_PHY_ADDR 0 +#elif (PEF7071_PHY_ADDR < 0 || PEF7071_PHY_ADDR > 31) + #error PEF7071_PHY_ADDR parameter is not valid +#endif + +//PEF7071 PHY registers +#define PEF7071_CTRL 0x00 +#define PEF7071_STAT 0x01 +#define PEF7071_PHYID1 0x02 +#define PEF7071_PHYID2 0x03 +#define PEF7071_AN_ADV 0x04 +#define PEF7071_AN_LPA 0x05 +#define PEF7071_AN_EXP 0x06 +#define PEF7071_AN_NPTX 0x07 +#define PEF7071_AN_NPRX 0x08 +#define PEF7071_GCTRL 0x09 +#define PEF7071_GSTAT 0x0A +#define PEF7071_RES11 0x0B +#define PEF7071_RES12 0x0C +#define PEF7071_MMDCTRL 0x0D +#define PEF7071_MMDDATA 0x0E +#define PEF7071_XSTAT 0x0F +#define PEF7071_PHYPHYPERF 0x10 +#define PEF7071_PHYSTAT1 0x11 +#define PEF7071_PHYSTAT2 0x12 +#define PEF7071_PHYCTL1 0x13 +#define PEF7071_PHYCTL2 0x14 +#define PEF7071_ERRCNT 0x15 +#define PEF7071_EECTRL 0x16 +#define PEF7071_MIICTRL 0x17 +#define PEF7071_MIISTAT 0x18 +#define PEF7071_IMASK 0x19 +#define PEF7071_ISTAT 0x1A +#define PEF7071_LED 0x1B +#define PEF7071_TPGCTRL 0x1C +#define PEF7071_TPGDATA 0x1D +#define PEF7071_FWV 0x1E +#define PEF7071_RES1F 0x1F + +//PEF7071 MMD registers +#define PEF7071_EEE_CTRL1 0x03, 0x0000 +#define PEF7071_EEE_STAT1 0x03, 0x0001 +#define PEF7071_EEE_CAP 0x03, 0x0014 +#define PEF7071_EEE_WAKERR 0x03, 0x0016 +#define PEF7071_ANEGEEE_AN_ADV 0x07, 0x003C +#define PEF7071_EEE_AN_LPADV 0x07, 0x003D +#define PEF7071_EEPROM 0x1E, 0x0000 +#define PEF7071_LEDCH 0x1F, 0x01E0 +#define PEF7071_LEDCL 0x1F, 0x01E1 +#define PEF7071_LED0H 0x1F, 0x01E2 +#define PEF7071_LED0L 0x1F, 0x01E3 +#define PEF7071_LED1H 0x1F, 0x01E4 +#define PEF7071_LED1L 0x1F, 0x01E5 +#define PEF7071_LED2H 0x1F, 0x01E6 +#define PEF7071_LED2L 0x1F, 0x01E7 +#define PEF7071_EEE_RXERR_LINK_FAIL_H 0x1F, 0x01EA +#define PEF7071_EEE_RXERR_LINK_FAIL_L 0x1F, 0x01EB +#define PEF7071_MII2CTRL 0x1F, 0x01EC +#define PEF7071_LEG_LPI_CFG0 0x1F, 0x01ED +#define PEF7071_LEG_LPI_CFG1 0x1F, 0x01EE +#define PEF7071_WOLCTRL 0x1F, 0x0781 +#define PEF7071_WOLAD0 0x1F, 0x0783 +#define PEF7071_WOLAD1 0x1F, 0x0784 +#define PEF7071_WOLAD2 0x1F, 0x0785 +#define PEF7071_WOLAD3 0x1F, 0x0786 +#define PEF7071_WOLAD4 0x1F, 0x0787 +#define PEF7071_WOLAD5 0x1F, 0x0788 +#define PEF7071_WOLPW0 0x1F, 0x0789 +#define PEF7071_WOLPW1 0x1F, 0x078A +#define PEF7071_WOLPW2 0x1F, 0x078B +#define PEF7071_WOLPW3 0x1F, 0x078C +#define PEF7071_WOLPW4 0x1F, 0x078D +#define PEF7071_WOLPW5 0x1F, 0x078E +#define PEF7071_LEG_LPI_CFG2 0x1F, 0x0EB5 +#define PEF7071_LEG_LPI_CFG3 0x1F, 0x0EB7 + +//Control register +#define PEF7071_CTRL_RST 0x8000 +#define PEF7071_CTRL_LB 0x4000 +#define PEF7071_CTRL_SSL 0x2000 +#define PEF7071_CTRL_ANEN 0x1000 +#define PEF7071_CTRL_PD 0x0800 +#define PEF7071_CTRL_ISOL 0x0400 +#define PEF7071_CTRL_ANRS 0x0200 +#define PEF7071_CTRL_DPLX 0x0100 +#define PEF7071_CTRL_COL 0x0080 +#define PEF7071_CTRL_SSM 0x0040 + +//Status register +#define PEF7071_STAT_CBT4 0x8000 +#define PEF7071_STAT_CBTXF 0x4000 +#define PEF7071_STAT_CBTXH 0x2000 +#define PEF7071_STAT_XBTF 0x1000 +#define PEF7071_STAT_XBTH 0x0800 +#define PEF7071_STAT_CBT2F 0x0400 +#define PEF7071_STAT_CBT2H 0x0200 +#define PEF7071_STAT_EXT 0x0100 +#define PEF7071_STAT_MFPS 0x0040 +#define PEF7071_STAT_ANOK 0x0020 +#define PEF7071_STAT_RF 0x0010 +#define PEF7071_STAT_ANAB 0x0008 +#define PEF7071_STAT_LS 0x0004 +#define PEF7071_STAT_JD 0x0002 +#define PEF7071_STAT_XCAP 0x0001 + +//PHY Identifier 1 register +#define PEF7071_PHYID1_OUI_MSB 0xFFFF +#define PEF7071_PHYID1_OUI_MSB_DEFAULT 0x0000 + +//PHY Identifier 2 register +#define PEF7071_PHYID2_OUI_LSB 0xFC00 +#define PEF7071_PHYID2_OUI_LSB_DEFAULT 0x0000 +#define PEF7071_PHYID2_LDN 0x03F0 +#define PEF7071_PHYID2_LDN_DEFAULT 0x0000 +#define PEF7071_PHYID2_LDRN 0x000F + +//Auto-Negotiation Advertisement register +#define PEF7071_AN_ADV_NP 0x8000 +#define PEF7071_AN_ADV_RF 0x2000 +#define PEF7071_AN_ADV_TAF 0x1FE0 +#define PEF7071_AN_ADV_TAF_XBT_HDX 0x0020 +#define PEF7071_AN_ADV_TAF_XBT_FDX 0x0040 +#define PEF7071_AN_ADV_TAF_DBT_HDX 0x0080 +#define PEF7071_AN_ADV_TAF_DBT_FDX 0x0100 +#define PEF7071_AN_ADV_TAF_DBT4 0x0200 +#define PEF7071_AN_ADV_TAF_PS_SYM 0x0400 +#define PEF7071_AN_ADV_TAF_PS_ASYM 0x0800 +#define PEF7071_AN_ADV_TAF_RES 0x1000 +#define PEF7071_AN_ADV_SF 0x001F +#define PEF7071_AN_ADV_SF_DEFAULT 0x0001 + +//Auto-Negotiation Link-Partner Ability register +#define PEF7071_AN_LPA_NP 0x8000 +#define PEF7071_AN_LPA_ACK 0x4000 +#define PEF7071_AN_LPA_RF 0x2000 +#define PEF7071_AN_LPA_TAF 0x1FE0 +#define PEF7071_AN_LPA_TAF_XBT_HDX 0x0020 +#define PEF7071_AN_LPA_TAF_XBT_FDX 0x0040 +#define PEF7071_AN_LPA_TAF_DBT_HDX 0x0080 +#define PEF7071_AN_LPA_TAF_DBT_FDX 0x0100 +#define PEF7071_AN_LPA_TAF_DBT4 0x0200 +#define PEF7071_AN_LPA_TAF_PS_SYM 0x0400 +#define PEF7071_AN_LPA_TAF_PS_ASYM 0x0800 +#define PEF7071_AN_LPA_TAF_RES 0x1000 +#define PEF7071_AN_LPA_SF 0x001F +#define PEF7071_AN_LPA_SF_DEFAULT 0x0001 + +//Auto-Negotiation Expansion register +#define PEF7071_AN_EXP_RESD 0xFFE0 +#define PEF7071_AN_EXP_PDF 0x0010 +#define PEF7071_AN_EXP_LPNPC 0x0008 +#define PEF7071_AN_EXP_NPC 0x0004 +#define PEF7071_AN_EXP_PR 0x0002 +#define PEF7071_AN_EXP_LPANC 0x0001 + +//Auto-Negotiation Next-Page Transmit register +#define PEF7071_AN_NPTX_NP 0x8000 +#define PEF7071_AN_NPTX_MP 0x2000 +#define PEF7071_AN_NPTX_ACK2 0x1000 +#define PEF7071_AN_NPTX_TOGG 0x0800 +#define PEF7071_AN_NPTX_MCF 0x07FF + +//Auto-Negotiation Link-Partner Received Next-Page register +#define PEF7071_AN_NPRX_NP 0x8000 +#define PEF7071_AN_NPRX_ACK 0x4000 +#define PEF7071_AN_NPRX_MP 0x2000 +#define PEF7071_AN_NPRX_ACK2 0x1000 +#define PEF7071_AN_NPRX_TOGG 0x0800 +#define PEF7071_AN_NPRX_MCF 0x07FF + +//Gigabit Control register +#define PEF7071_GCTRL_TM 0xE000 +#define PEF7071_GCTRL_MSEN 0x1000 +#define PEF7071_GCTRL_MS 0x0800 +#define PEF7071_GCTRL_MSPT 0x0400 +#define PEF7071_GCTRL_MBTFD 0x0200 +#define PEF7071_GCTRL_MBTHD 0x0100 + +//Gigabit Status register +#define PEF7071_GSTAT_MSFAULT 0x8000 +#define PEF7071_GSTAT_MSRES 0x4000 +#define PEF7071_GSTAT_LRXSTAT 0x2000 +#define PEF7071_GSTAT_RRXSTAT 0x1000 +#define PEF7071_GSTAT_MBTFD 0x0800 +#define PEF7071_GSTAT_MBTHD 0x0400 +#define PEF7071_GSTAT_IEC 0x00FF + +//MMD Access Control register +#define PEF7071_MMDCTRL_ACTYPE 0xC000 +#define PEF7071_MMDCTRL_ACTYPE_ADDRESS 0x0000 +#define PEF7071_MMDCTRL_ACTYPE_DATA 0x4000 +#define PEF7071_MMDCTRL_ACTYPE_DATA_PI 0x8000 +#define PEF7071_MMDCTRL_ACTYPE_DATA_PIWR 0xC000 +#define PEF7071_MMDCTRL_RESH 0x3F00 +#define PEF7071_MMDCTRL_RESL 0x00E0 +#define PEF7071_MMDCTRL_DEVAD 0x001F + +//MMD Access Data register +#define PEF7071_MMDDATA_ADDR_DATA 0xFFFF + +//Extended Status register +#define PEF7071_XSTAT_MBXF 0x8000 +#define PEF7071_XSTAT_MBXH 0x4000 +#define PEF7071_XSTAT_MBTF 0x2000 +#define PEF7071_XSTAT_MBTH 0x1000 +#define PEF7071_XSTAT_RESH 0x0F00 +#define PEF7071_XSTAT_RESL 0x00FF + +//Physical Layer Performance Status register +#define PEF7071_PHYPHYPERF_FREQ 0xFF00 +#define PEF7071_PHYPHYPERF_SNR 0x00F0 +#define PEF7071_PHYPHYPERF_LEN 0x000F + +//Physical Layer Status 1 register +#define PEF7071_PHYSTAT1_RESH 0xFE00 +#define PEF7071_PHYSTAT1_LSADS 0x0100 +#define PEF7071_PHYSTAT1_POLD 0x0080 +#define PEF7071_PHYSTAT1_POLC 0x0040 +#define PEF7071_PHYSTAT1_POLB 0x0020 +#define PEF7071_PHYSTAT1_POLA 0x0010 +#define PEF7071_PHYSTAT1_MDICD 0x0008 +#define PEF7071_PHYSTAT1_MDIAB 0x0004 +#define PEF7071_PHYSTAT1_RESL 0x0003 + +//Physical Layer Status 2 register +#define PEF7071_PHYSTAT2_RESD 0x8000 +#define PEF7071_PHYSTAT2_SKEWD 0x7000 +#define PEF7071_PHYSTAT2_RESC 0x0800 +#define PEF7071_PHYSTAT2_SKEWC 0x0700 +#define PEF7071_PHYSTAT2_RESB 0x0080 +#define PEF7071_PHYSTAT2_SKEWB 0x0070 +#define PEF7071_PHYSTAT2_RESA 0x0008 +#define PEF7071_PHYSTAT2_SKEWA 0x0007 + +//Physical Layer Control 1 register +#define PEF7071_PHYCTL1_TLOOP 0xE000 +#define PEF7071_PHYCTL1_TXOFF 0x1000 +#define PEF7071_PHYCTL1_TXADJ 0x0F00 +#define PEF7071_PHYCTL1_POLD 0x0080 +#define PEF7071_PHYCTL1_POLC 0x0040 +#define PEF7071_PHYCTL1_POLB 0x0020 +#define PEF7071_PHYCTL1_POLA 0x0010 +#define PEF7071_PHYCTL1_MDICD 0x0008 +#define PEF7071_PHYCTL1_MDIAB 0x0004 +#define PEF7071_PHYCTL1_TXEEE10 0x0002 +#define PEF7071_PHYCTL1_AMDIX 0x0001 + +//Physical Layer Control 2 register +#define PEF7071_PHYCTL2_LSADS 0xC000 +#define PEF7071_PHYCTL2_LSADS_OFF 0x0000 +#define PEF7071_PHYCTL2_LSADS_ADS2 0x4000 +#define PEF7071_PHYCTL2_LSADS_ADS3 0x8000 +#define PEF7071_PHYCTL2_LSADS_ADS4 0xC000 +#define PEF7071_PHYCTL2_RESH 0x3800 +#define PEF7071_PHYCTL2_CLKSEL 0x0400 +#define PEF7071_PHYCTL2_CLKSEL_CLK25M 0x0000 +#define PEF7071_PHYCTL2_CLKSEL_CLK125M 0x0400 +#define PEF7071_PHYCTL2_SDETP 0x0200 +#define PEF7071_PHYCTL2_SDETP_LOWACTIVE 0x0000 +#define PEF7071_PHYCTL2_SDETP_HIGHACTIVE 0x0200 +#define PEF7071_PHYCTL2_STICKY 0x0100 +#define PEF7071_PHYCTL2_RESL 0x00F0 +#define PEF7071_PHYCTL2_ADCR 0x0008 +#define PEF7071_PHYCTL2_ADCR_DEFAULT 0x0000 +#define PEF7071_PHYCTL2_ADCR_BOOST 0x0008 +#define PEF7071_PHYCTL2_PSCL 0x0004 +#define PEF7071_PHYCTL2_ANPD 0x0002 +#define PEF7071_PHYCTL2_LPI 0x0001 + +//Error Counter register +#define PEF7071_ERRCNT_SEL 0x0F00 +#define PEF7071_ERRCNT_SEL_RXERR 0x0000 +#define PEF7071_ERRCNT_SEL_RXACT 0x0100 +#define PEF7071_ERRCNT_SEL_ESDERR 0x0200 +#define PEF7071_ERRCNT_SEL_SSDERR 0x0300 +#define PEF7071_ERRCNT_SEL_TXERR 0x0400 +#define PEF7071_ERRCNT_SEL_TXACT 0x0500 +#define PEF7071_ERRCNT_SEL_COL 0x0600 +#define PEF7071_ERRCNT_COUNT 0x00FF + +//EEPROM Control register +#define PEF7071_EECTRL_EESCAN 0x8000 +#define PEF7071_EECTRL_EEAF 0x4000 +#define PEF7071_EECTRL_CSRDET 0x2000 +#define PEF7071_EECTRL_EEDET 0x1000 +#define PEF7071_EECTRL_SIZE 0x0F00 +#define PEF7071_EECTRL_SIZE_SIZE1K 0x0000 +#define PEF7071_EECTRL_SIZE_SIZE2K 0x0100 +#define PEF7071_EECTRL_SIZE_SIZE4K 0x0200 +#define PEF7071_EECTRL_SIZE_SIZE8K 0x0300 +#define PEF7071_EECTRL_SIZE_SIZE16K 0x0400 +#define PEF7071_EECTRL_SIZE_SIZE32K 0x0500 +#define PEF7071_EECTRL_SIZE_SIZE64K 0x0600 +#define PEF7071_EECTRL_SIZE_SIZE128K 0x0700 +#define PEF7071_EECTRL_SIZE_SIZE256K 0x0800 +#define PEF7071_EECTRL_SIZE_SIZE512K 0x0900 +#define PEF7071_EECTRL_SIZE_SIZE1024K 0x0A00 +#define PEF7071_EECTRL_ADRMODE 0x0080 +#define PEF7071_EECTRL_ADRMODE_MODE11 0x0000 +#define PEF7071_EECTRL_ADRMODE_MODE16 0x0080 +#define PEF7071_EECTRL_DADR 0x0070 +#define PEF7071_EECTRL_SPEED 0x000C +#define PEF7071_EECTRL_SPEED_FRQ_100KHZ 0x0000 +#define PEF7071_EECTRL_SPEED_FRQ_400KHZ 0x0004 +#define PEF7071_EECTRL_SPEED_FRQ_1_0MHZ 0x0008 +#define PEF7071_EECTRL_SPEED_FRQ_3_4MHZ 0x000C +#define PEF7071_EECTRL_RDWR 0x0002 +#define PEF7071_EECTRL_EXEC 0x0001 + +//Media-Independent Interface Control register +#define PEF7071_MIICTRL_RXCOFF 0x8000 +#define PEF7071_MIICTRL_RXSKEW 0x7000 +#define PEF7071_MIICTRL_RXSKEW_SKEW_0N0 0x0000 +#define PEF7071_MIICTRL_RXSKEW_SKEW_0N5 0x1000 +#define PEF7071_MIICTRL_RXSKEW_SKEW_1N0 0x2000 +#define PEF7071_MIICTRL_RXSKEW_SKEW_1N5 0x3000 +#define PEF7071_MIICTRL_RXSKEW_SKEW_2N0 0x4000 +#define PEF7071_MIICTRL_RXSKEW_SKEW_2N5 0x5000 +#define PEF7071_MIICTRL_RXSKEW_SKEW_3N0 0x6000 +#define PEF7071_MIICTRL_RXSKEW_SKEW_3N5 0x7000 +#define PEF7071_MIICTRL_V25_33 0x0800 +#define PEF7071_MIICTRL_TXSKEW 0x0700 +#define PEF7071_MIICTRL_TXSKEW_SKEW_0N0 0x0000 +#define PEF7071_MIICTRL_TXSKEW_SKEW_0N5 0x0100 +#define PEF7071_MIICTRL_TXSKEW_SKEW_1N0 0x0200 +#define PEF7071_MIICTRL_TXSKEW_SKEW_1N5 0x0300 +#define PEF7071_MIICTRL_TXSKEW_SKEW_2N0 0x0400 +#define PEF7071_MIICTRL_TXSKEW_SKEW_2N5 0x0500 +#define PEF7071_MIICTRL_TXSKEW_SKEW_3N0 0x0600 +#define PEF7071_MIICTRL_TXSKEW_SKEW_3N5 0x0700 +#define PEF7071_MIICTRL_CRS 0x00C0 +#define PEF7071_MIICTRL_FLOW 0x0030 +#define PEF7071_MIICTRL_FLOW_COPPER 0x0000 +#define PEF7071_MIICTRL_FLOW_CONVERTER 0x0030 +#define PEF7071_MIICTRL_MODE 0x000F +#define PEF7071_MIICTRL_MODE_RGMII 0x0000 +#define PEF7071_MIICTRL_MODE_SGMII 0x0001 +#define PEF7071_MIICTRL_MODE_RMII 0x0002 +#define PEF7071_MIICTRL_MODE_RTBI 0x0003 +#define PEF7071_MIICTRL_MODE_GMII 0x0004 +#define PEF7071_MIICTRL_MODE_TBI 0x0005 +#define PEF7071_MIICTRL_MODE_SGMIINC 0x0006 +#define PEF7071_MIICTRL_MODE_TEST 0x000F +#define PEF7071_MIICTRL_MODE_CONV_X2T1000 0x0000 +#define PEF7071_MIICTRL_MODE_CONV_X2T1000A 0x0001 + +//Media-Independent Interface Status register +#define PEF7071_MIISTAT_RESH 0xFF00 +#define PEF7071_MIISTAT_PHY 0x00C0 +#define PEF7071_MIISTAT_PHY_TP 0x0000 +#define PEF7071_MIISTAT_PHY_FIBER 0x0040 +#define PEF7071_MIISTAT_PHY_MII2 0x0080 +#define PEF7071_MIISTAT_PHY_SGMII 0x00C0 +#define PEF7071_MIISTAT_PS 0x0030 +#define PEF7071_MIISTAT_PS_NONE 0x0000 +#define PEF7071_MIISTAT_PS_TX 0x0010 +#define PEF7071_MIISTAT_PS_RX 0x0020 +#define PEF7071_MIISTAT_PS_TXRX 0x0030 +#define PEF7071_MIISTAT_DPX 0x0008 +#define PEF7071_MIISTAT_EEE 0x0004 +#define PEF7071_MIISTAT_EEE_OFF 0x0000 +#define PEF7071_MIISTAT_EEE_ON 0x0004 +#define PEF7071_MIISTAT_SPEED 0x0003 +#define PEF7071_MIISTAT_SPEED_TEN 0x0000 +#define PEF7071_MIISTAT_SPEED_FAST 0x0001 +#define PEF7071_MIISTAT_SPEED_GIGA 0x0002 +#define PEF7071_MIISTAT_SPEED_RES 0x0003 + +//Interrupt Mask register +#define PEF7071_IMASK_WOL 0x8000 +#define PEF7071_IMASK_MSRE 0x4000 +#define PEF7071_IMASK_NPRX 0x2000 +#define PEF7071_IMASK_NPTX 0x1000 +#define PEF7071_IMASK_ANE 0x0800 +#define PEF7071_IMASK_ANC 0x0400 +#define PEF7071_IMASK_RESH 0x0300 +#define PEF7071_IMASK_RESL 0x00C0 +#define PEF7071_IMASK_ADSC 0x0020 +#define PEF7071_IMASK_MDIPC 0x0010 +#define PEF7071_IMASK_MDIXC 0x0008 +#define PEF7071_IMASK_DXMC 0x0004 +#define PEF7071_IMASK_LSPC 0x0002 +#define PEF7071_IMASK_LSTC 0x0001 + +//Interrupt Status register +#define PEF7071_ISTAT_WOL 0x8000 +#define PEF7071_ISTAT_MSRE 0x4000 +#define PEF7071_ISTAT_NPRX 0x2000 +#define PEF7071_ISTAT_NPTX 0x1000 +#define PEF7071_ISTAT_ANE 0x0800 +#define PEF7071_ISTAT_ANC 0x0400 +#define PEF7071_ISTAT_RESH 0x0300 +#define PEF7071_ISTAT_RESL 0x00C0 +#define PEF7071_ISTAT_ADSC 0x0020 +#define PEF7071_ISTAT_MDIPC 0x0010 +#define PEF7071_ISTAT_MDIXC 0x0008 +#define PEF7071_ISTAT_DXMC 0x0004 +#define PEF7071_ISTAT_LSPC 0x0002 +#define PEF7071_ISTAT_LSTC 0x0001 + +//LED Control register +#define PEF7071_LED_RESH 0xF000 +#define PEF7071_LED_LED3EN 0x0800 +#define PEF7071_LED_LED2EN 0x0400 +#define PEF7071_LED_LED1EN 0x0200 +#define PEF7071_LED_LED0EN 0x0100 +#define PEF7071_LED_RESL 0x00F0 +#define PEF7071_LED_LED3DA 0x0008 +#define PEF7071_LED_LED3DA_OFF 0x0000 +#define PEF7071_LED_LED3DA_ON 0x0008 +#define PEF7071_LED_LED2DA 0x0004 +#define PEF7071_LED_LED2DA_OFF 0x0000 +#define PEF7071_LED_LED2DA_ON 0x0004 +#define PEF7071_LED_LED1DA 0x0002 +#define PEF7071_LED_LED1DA_OFF 0x0000 +#define PEF7071_LED_LED1DA_ON 0x0002 +#define PEF7071_LED_LED0DA 0x0001 +#define PEF7071_LED_LED0DA_OFF 0x0000 +#define PEF7071_LED_LED0DA_ON 0x0001 + +//Test-Packet Generator Control register +#define PEF7071_TPGCTRL_RESH1 0xC000 +#define PEF7071_TPGCTRL_MODE 0x2000 +#define PEF7071_TPGCTRL_MODE_BURST 0x0000 +#define PEF7071_TPGCTRL_MODE_SINGLE 0x2000 +#define PEF7071_TPGCTRL_RESH0 0x1000 +#define PEF7071_TPGCTRL_IPGL 0x0C00 +#define PEF7071_TPGCTRL_IPGL_BT48 0x0000 +#define PEF7071_TPGCTRL_IPGL_BT96 0x0400 +#define PEF7071_TPGCTRL_IPGL_BT960 0x0800 +#define PEF7071_TPGCTRL_IPGL_BT9600 0x0C00 +#define PEF7071_TPGCTRL_TYPE 0x0300 +#define PEF7071_TPGCTRL_TYPE_RANDOM 0x0000 +#define PEF7071_TPGCTRL_TYPE_BYTEINC 0x0100 +#define PEF7071_TPGCTRL_TYPE_PREDEF 0x0200 +#define PEF7071_TPGCTRL_RESL1 0x0080 +#define PEF7071_TPGCTRL_SIZE 0x0070 +#define PEF7071_TPGCTRL_SIZE_B64 0x0000 +#define PEF7071_TPGCTRL_SIZE_B128 0x0010 +#define PEF7071_TPGCTRL_SIZE_B256 0x0020 +#define PEF7071_TPGCTRL_SIZE_B512 0x0030 +#define PEF7071_TPGCTRL_SIZE_B1024 0x0040 +#define PEF7071_TPGCTRL_SIZE_B1518 0x0050 +#define PEF7071_TPGCTRL_SIZE_B9600 0x0060 +#define PEF7071_TPGCTRL_RESL0 0x000C +#define PEF7071_TPGCTRL_START 0x0002 +#define PEF7071_TPGCTRL_EN 0x0001 + +//Test-Packet Generator Data register +#define PEF7071_TPGDATA_DA 0xF000 +#define PEF7071_TPGDATA_SA 0x0F00 +#define PEF7071_TPGDATA_DATA 0x00FF + +//Firmware Version register +#define PEF7071_FWV_REL 0x8000 +#define PEF7071_FWV_REL_TEST 0x0000 +#define PEF7071_FWV_REL_RELEASE 0x8000 +#define PEF7071_FWV_MAJOR 0x7F00 +#define PEF7071_FWV_MINOR 0x00FF + +//EEE Control 1 register +#define PEF7071_EEE_CTRL1_RXCKST 0x0400 + +//EEE Status 1 register +#define PEF7071_EEE_STAT1_TXLPI_RCVD 0x0800 +#define PEF7071_EEE_STAT1_TXLPI_IND 0x0200 +#define PEF7071_EEE_STAT1_RXLPI_IND 0x0100 +#define PEF7071_EEE_STAT1_TXCKST 0x0040 + +//EEE Capability register +#define PEF7071_EEE_CAP_EEE_10GBKR 0x0040 +#define PEF7071_EEE_CAP_EEE_10GBKX4 0x0020 +#define PEF7071_EEE_CAP_EEE_1000BKX 0x0010 +#define PEF7071_EEE_CAP_EEE_10GBT 0x0008 +#define PEF7071_EEE_CAP_EEE_1000BT 0x0004 +#define PEF7071_EEE_CAP_EEE_100BTX 0x0002 + +//EEE Wake Time Fault Count register +#define PEF7071_EEE_WAKERR_ERRCNT 0xFFFF + +//EEE Auto-Negotiation Advertisement register +#define PEF7071_ANEGEEE_AN_ADV_EEE_10GBKR 0x0040 +#define PEF7071_ANEGEEE_AN_ADV_EEE_10GBKX4 0x0020 +#define PEF7071_ANEGEEE_AN_ADV_EEE_1000BKX 0x0010 +#define PEF7071_ANEGEEE_AN_ADV_EEE_10GBT 0x0008 +#define PEF7071_ANEGEEE_AN_ADV_EEE_1000BT 0x0004 +#define PEF7071_ANEGEEE_AN_ADV_EEE_100BTX 0x0002 + +//EEE Auto-Negotiation Link-Partner Advertisement register +#define PEF7071_EEE_AN_LPADV_EEE_10GBKR 0x0040 +#define PEF7071_EEE_AN_LPADV_EEE_10GBKX4 0x0020 +#define PEF7071_EEE_AN_LPADV_EEE_1000BKX 0x0010 +#define PEF7071_EEE_AN_LPADV_EEE_10GBT 0x0008 +#define PEF7071_EEE_AN_LPADV_EEE_1000BT 0x0004 +#define PEF7071_EEE_AN_LPADV_EEE_100BTX 0x0002 + +//EEPROM Content register +#define PEF7071_EEPROM_DATA 0x00FF + +//LED Configuration H register +#define PEF7071_LEDCH_FBF 0x00C0 +#define PEF7071_LEDCH_FBF_F02HZ 0x0000 +#define PEF7071_LEDCH_FBF_F04HZ 0x0040 +#define PEF7071_LEDCH_FBF_F08HZ 0x0080 +#define PEF7071_LEDCH_FBF_F16HZ 0x00C0 +#define PEF7071_LEDCH_SBF 0x0030 +#define PEF7071_LEDCH_SBF_F02HZ 0x0000 +#define PEF7071_LEDCH_SBF_F04HZ 0x0010 +#define PEF7071_LEDCH_SBF_F08HZ 0x0020 +#define PEF7071_LEDCH_SBF_F16HZ 0x0030 +#define PEF7071_LEDCH_NACS 0x0007 +#define PEF7071_LEDCH_NACS_NONE 0x0000 +#define PEF7071_LEDCH_NACS_LINK 0x0001 +#define PEF7071_LEDCH_NACS_PDOWN 0x0002 +#define PEF7071_LEDCH_NACS_EEE 0x0003 +#define PEF7071_LEDCH_NACS_ANEG 0x0004 +#define PEF7071_LEDCH_NACS_ABIST 0x0005 +#define PEF7071_LEDCH_NACS_CDIAG 0x0006 +#define PEF7071_LEDCH_NACS_TEST 0x0007 + +//LED Configuration L register +#define PEF7071_LEDCL_SCAN 0x0070 +#define PEF7071_LEDCL_SCAN_NONE 0x0000 +#define PEF7071_LEDCL_SCAN_LINK 0x0010 +#define PEF7071_LEDCL_SCAN_PDOWN 0x0020 +#define PEF7071_LEDCL_SCAN_EEE 0x0030 +#define PEF7071_LEDCL_SCAN_ANEG 0x0040 +#define PEF7071_LEDCL_SCAN_ABIST 0x0050 +#define PEF7071_LEDCL_SCAN_CDIAG 0x0060 +#define PEF7071_LEDCL_SCAN_TEST 0x0070 +#define PEF7071_LEDCL_CBLINK 0x0007 +#define PEF7071_LEDCL_CBLINK_NONE 0x0000 +#define PEF7071_LEDCL_CBLINK_LINK 0x0001 +#define PEF7071_LEDCL_CBLINK_PDOWN 0x0002 +#define PEF7071_LEDCL_CBLINK_EEE 0x0003 +#define PEF7071_LEDCL_CBLINK_ANEG 0x0004 +#define PEF7071_LEDCL_CBLINK_ABIST 0x0005 +#define PEF7071_LEDCL_CBLINK_CDIAG 0x0006 +#define PEF7071_LEDCL_CBLINK_TEST 0x0007 + +//Configuration for LED Pin 0 H register +#define PEF7071_LED0H_CON 0x00F0 +#define PEF7071_LED0H_CON_NONE 0x0000 +#define PEF7071_LED0H_CON_LINK10 0x0010 +#define PEF7071_LED0H_CON_LINK100 0x0020 +#define PEF7071_LED0H_CON_LINK10X 0x0030 +#define PEF7071_LED0H_CON_LINK1000 0x0040 +#define PEF7071_LED0H_CON_LINK10_0 0x0050 +#define PEF7071_LED0H_CON_LINK100X 0x0060 +#define PEF7071_LED0H_CON_LINK10XX 0x0070 +#define PEF7071_LED0H_CON_PDOWN 0x0080 +#define PEF7071_LED0H_CON_EEE 0x0090 +#define PEF7071_LED0H_CON_ANEG 0x00A0 +#define PEF7071_LED0H_CON_ABIST 0x00B0 +#define PEF7071_LED0H_CON_CDIAG 0x00C0 +#define PEF7071_LED0H_CON_COPPER 0x00D0 +#define PEF7071_LED0H_CON_FIBER 0x00E0 +#define PEF7071_LED0H_BLINKF 0x000F +#define PEF7071_LED0H_BLINKF_NONE 0x0000 +#define PEF7071_LED0H_BLINKF_LINK10 0x0001 +#define PEF7071_LED0H_BLINKF_LINK100 0x0002 +#define PEF7071_LED0H_BLINKF_LINK10X 0x0003 +#define PEF7071_LED0H_BLINKF_LINK1000 0x0004 +#define PEF7071_LED0H_BLINKF_LINK10_0 0x0005 +#define PEF7071_LED0H_BLINKF_LINK100X 0x0006 +#define PEF7071_LED0H_BLINKF_LINK10XX 0x0007 +#define PEF7071_LED0H_BLINKF_PDOWN 0x0008 +#define PEF7071_LED0H_BLINKF_EEE 0x0009 +#define PEF7071_LED0H_BLINKF_ANEG 0x000A +#define PEF7071_LED0H_BLINKF_ABIST 0x000B +#define PEF7071_LED0H_BLINKF_CDIAG 0x000C + +//Configuration for LED Pin 0 L register +#define PEF7071_LED0L_BLINKS 0x00F0 +#define PEF7071_LED0L_BLINKS_NONE 0x0000 +#define PEF7071_LED0L_BLINKS_LINK10 0x0010 +#define PEF7071_LED0L_BLINKS_LINK100 0x0020 +#define PEF7071_LED0L_BLINKS_LINK10X 0x0030 +#define PEF7071_LED0L_BLINKS_LINK1000 0x0040 +#define PEF7071_LED0L_BLINKS_LINK10_0 0x0050 +#define PEF7071_LED0L_BLINKS_LINK100X 0x0060 +#define PEF7071_LED0L_BLINKS_LINK10XX 0x0070 +#define PEF7071_LED0L_BLINKS_PDOWN 0x0080 +#define PEF7071_LED0L_BLINKS_EEE 0x0090 +#define PEF7071_LED0L_BLINKS_ANEG 0x00A0 +#define PEF7071_LED0L_BLINKS_ABIST 0x00B0 +#define PEF7071_LED0L_BLINKS_CDIAG 0x00C0 +#define PEF7071_LED0L_PULSE 0x000F +#define PEF7071_LED0L_PULSE_NONE 0x0000 +#define PEF7071_LED0L_PULSE_TXACT 0x0001 +#define PEF7071_LED0L_PULSE_RXACT 0x0002 +#define PEF7071_LED0L_PULSE_COL 0x0004 + +//Configuration for LED Pin 1 H register +#define PEF7071_LED1H_CON 0x00F0 +#define PEF7071_LED1H_CON_NONE 0x0000 +#define PEF7071_LED1H_CON_LINK10 0x0010 +#define PEF7071_LED1H_CON_LINK100 0x0020 +#define PEF7071_LED1H_CON_LINK10X 0x0030 +#define PEF7071_LED1H_CON_LINK1000 0x0040 +#define PEF7071_LED1H_CON_LINK10_0 0x0050 +#define PEF7071_LED1H_CON_LINK100X 0x0060 +#define PEF7071_LED1H_CON_LINK10XX 0x0070 +#define PEF7071_LED1H_CON_PDOWN 0x0080 +#define PEF7071_LED1H_CON_EEE 0x0090 +#define PEF7071_LED1H_CON_ANEG 0x00A0 +#define PEF7071_LED1H_CON_ABIST 0x00B0 +#define PEF7071_LED1H_CON_CDIAG 0x00C0 +#define PEF7071_LED1H_CON_COPPER 0x00D0 +#define PEF7071_LED1H_CON_FIBER 0x00E0 +#define PEF7071_LED1H_BLINKF 0x000F +#define PEF7071_LED1H_BLINKF_NONE 0x0000 +#define PEF7071_LED1H_BLINKF_LINK10 0x0001 +#define PEF7071_LED1H_BLINKF_LINK100 0x0002 +#define PEF7071_LED1H_BLINKF_LINK10X 0x0003 +#define PEF7071_LED1H_BLINKF_LINK1000 0x0004 +#define PEF7071_LED1H_BLINKF_LINK10_0 0x0005 +#define PEF7071_LED1H_BLINKF_LINK100X 0x0006 +#define PEF7071_LED1H_BLINKF_LINK10XX 0x0007 +#define PEF7071_LED1H_BLINKF_PDOWN 0x0008 +#define PEF7071_LED1H_BLINKF_EEE 0x0009 +#define PEF7071_LED1H_BLINKF_ANEG 0x000A +#define PEF7071_LED1H_BLINKF_ABIST 0x000B +#define PEF7071_LED1H_BLINKF_CDIAG 0x000C + +//Configuration for LED Pin 1 L register +#define PEF7071_LED1L_BLINKS 0x00F0 +#define PEF7071_LED1L_BLINKS_NONE 0x0000 +#define PEF7071_LED1L_BLINKS_LINK10 0x0010 +#define PEF7071_LED1L_BLINKS_LINK100 0x0020 +#define PEF7071_LED1L_BLINKS_LINK10X 0x0030 +#define PEF7071_LED1L_BLINKS_LINK1000 0x0040 +#define PEF7071_LED1L_BLINKS_LINK10_0 0x0050 +#define PEF7071_LED1L_BLINKS_LINK100X 0x0060 +#define PEF7071_LED1L_BLINKS_LINK10XX 0x0070 +#define PEF7071_LED1L_BLINKS_PDOWN 0x0080 +#define PEF7071_LED1L_BLINKS_EEE 0x0090 +#define PEF7071_LED1L_BLINKS_ANEG 0x00A0 +#define PEF7071_LED1L_BLINKS_ABIST 0x00B0 +#define PEF7071_LED1L_BLINKS_CDIAG 0x00C0 +#define PEF7071_LED1L_PULSE 0x000F +#define PEF7071_LED1L_PULSE_NONE 0x0000 +#define PEF7071_LED1L_PULSE_TXACT 0x0001 +#define PEF7071_LED1L_PULSE_RXACT 0x0002 +#define PEF7071_LED1L_PULSE_COL 0x0004 + +//Configuration for LED Pin 2 H register +#define PEF7071_LED2H_CON 0x00F0 +#define PEF7071_LED2H_CON_NONE 0x0000 +#define PEF7071_LED2H_CON_LINK10 0x0010 +#define PEF7071_LED2H_CON_LINK100 0x0020 +#define PEF7071_LED2H_CON_LINK10X 0x0030 +#define PEF7071_LED2H_CON_LINK1000 0x0040 +#define PEF7071_LED2H_CON_LINK10_0 0x0050 +#define PEF7071_LED2H_CON_LINK100X 0x0060 +#define PEF7071_LED2H_CON_LINK10XX 0x0070 +#define PEF7071_LED2H_CON_PDOWN 0x0080 +#define PEF7071_LED2H_CON_EEE 0x0090 +#define PEF7071_LED2H_CON_ANEG 0x00A0 +#define PEF7071_LED2H_CON_ABIST 0x00B0 +#define PEF7071_LED2H_CON_CDIAG 0x00C0 +#define PEF7071_LED2H_CON_COPPER 0x00D0 +#define PEF7071_LED2H_CON_FIBER 0x00E0 +#define PEF7071_LED2H_BLINKF 0x000F +#define PEF7071_LED2H_BLINKF_NONE 0x0000 +#define PEF7071_LED2H_BLINKF_LINK10 0x0001 +#define PEF7071_LED2H_BLINKF_LINK100 0x0002 +#define PEF7071_LED2H_BLINKF_LINK10X 0x0003 +#define PEF7071_LED2H_BLINKF_LINK1000 0x0004 +#define PEF7071_LED2H_BLINKF_LINK10_0 0x0005 +#define PEF7071_LED2H_BLINKF_LINK100X 0x0006 +#define PEF7071_LED2H_BLINKF_LINK10XX 0x0007 +#define PEF7071_LED2H_BLINKF_PDOWN 0x0008 +#define PEF7071_LED2H_BLINKF_EEE 0x0009 +#define PEF7071_LED2H_BLINKF_ANEG 0x000A +#define PEF7071_LED2H_BLINKF_ABIST 0x000B +#define PEF7071_LED2H_BLINKF_CDIAG 0x000C + +//Configuration for LED Pin 2 L register +#define PEF7071_LED2L_BLINKS 0x00F0 +#define PEF7071_LED2L_BLINKS_NONE 0x0000 +#define PEF7071_LED2L_BLINKS_LINK10 0x0010 +#define PEF7071_LED2L_BLINKS_LINK100 0x0020 +#define PEF7071_LED2L_BLINKS_LINK10X 0x0030 +#define PEF7071_LED2L_BLINKS_LINK1000 0x0040 +#define PEF7071_LED2L_BLINKS_LINK10_0 0x0050 +#define PEF7071_LED2L_BLINKS_LINK100X 0x0060 +#define PEF7071_LED2L_BLINKS_LINK10XX 0x0070 +#define PEF7071_LED2L_BLINKS_PDOWN 0x0080 +#define PEF7071_LED2L_BLINKS_EEE 0x0090 +#define PEF7071_LED2L_BLINKS_ANEG 0x00A0 +#define PEF7071_LED2L_BLINKS_ABIST 0x00B0 +#define PEF7071_LED2L_BLINKS_CDIAG 0x00C0 +#define PEF7071_LED2L_PULSE 0x000F +#define PEF7071_LED2L_PULSE_NONE 0x0000 +#define PEF7071_LED2L_PULSE_TXACT 0x0001 +#define PEF7071_LED2L_PULSE_RXACT 0x0002 +#define PEF7071_LED2L_PULSE_COL 0x0004 + +//EEE Link-Fail Counter H register +#define PEF7071_EEE_RXERR_LINK_FAIL_H_VAL 0x00FF + +//EEE Link-Fail Counter L register +#define PEF7071_EEE_RXERR_LINK_FAIL_L_VAL 0x00FF + +//MII2 Control register +#define PEF7071_MII2CTRL_RXSKEW 0x0070 +#define PEF7071_MII2CTRL_RXSKEW_SKEW_0N0 0x0000 +#define PEF7071_MII2CTRL_RXSKEW_SKEW_0N5 0x0010 +#define PEF7071_MII2CTRL_RXSKEW_SKEW_1N0 0x0020 +#define PEF7071_MII2CTRL_RXSKEW_SKEW_1N5 0x0030 +#define PEF7071_MII2CTRL_RXSKEW_SKEW_2N0 0x0040 +#define PEF7071_MII2CTRL_RXSKEW_SKEW_2N5 0x0050 +#define PEF7071_MII2CTRL_RXSKEW_SKEW_3N0 0x0060 +#define PEF7071_MII2CTRL_RXSKEW_SKEW_3N5 0x0070 +#define PEF7071_MII2CTRL_TXSKEW 0x0007 +#define PEF7071_MII2CTRL_TXSKEW_SKEW_0N0 0x0000 +#define PEF7071_MII2CTRL_TXSKEW_SKEW_0N5 0x0001 +#define PEF7071_MII2CTRL_TXSKEW_SKEW_1N0 0x0002 +#define PEF7071_MII2CTRL_TXSKEW_SKEW_1N5 0x0003 +#define PEF7071_MII2CTRL_TXSKEW_SKEW_2N0 0x0004 +#define PEF7071_MII2CTRL_TXSKEW_SKEW_2N5 0x0005 +#define PEF7071_MII2CTRL_TXSKEW_SKEW_3N0 0x0006 +#define PEF7071_MII2CTRL_TXSKEW_SKEW_3N5 0x0007 + +//Legacy LPI Configuration 0 register +#define PEF7071_LEG_LPI_CFG0_HOLDOFF_100BT 0x00FF + +//Legacy LPI Configuration 1 register +#define PEF7071_LEG_LPI_CFG1_HOLDOFF_1000BT 0x00FF + +//Wake-On-LAN Control register +#define PEF7071_WOLCTRL_SPWD_EN 0x0004 +#define PEF7071_WOLCTRL_RES 0x0002 +#define PEF7071_WOLCTRL_EN 0x0001 + +//Wake-On-LAN Address Byte 0 register +#define PEF7071_WOLAD0_VAL 0x00FF + +//Wake-On-LAN Address Byte 1 register +#define PEF7071_WOLAD1_VAL 0x00FF + +//Wake-On-LAN Address Byte 2 register +#define PEF7071_WOLAD2_VAL 0x00FF + +//Wake-On-LAN Address Byte 3 register +#define PEF7071_WOLAD3_VAL 0x00FF + +//Wake-On-LAN Address Byte 4 register +#define PEF7071_WOLAD4_VAL 0x00FF + +//Wake-On-LAN Address Byte 5 register +#define PEF7071_WOLAD5_VAL 0x00FF + +//Wake-On-LAN SecureON Password Byte 0 register +#define PEF7071_WOLPW0_VAL 0x00FF + +//Wake-On-LAN SecureON Password Byte 1 register +#define PEF7071_WOLPW1_VAL 0x00FF + +//Wake-On-LAN SecureON Password Byte 2 register +#define PEF7071_WOLPW2_VAL 0x00FF + +//Wake-On-LAN SecureON Password Byte 3 register +#define PEF7071_WOLPW3_VAL 0x00FF + +//Wake-On-LAN SecureON Password Byte 4 register +#define PEF7071_WOLPW4_VAL 0x00FF + +//Wake-On-LAN SecureON Password Byte 5 register +#define PEF7071_WOLPW5_VAL 0x00FF + +//Legacy LPI Configuration 2 register +#define PEF7071_LEG_LPI_CFG2_IPG 0x00FF +#define PEF7071_LEG_LPI_CFG2_IPG_DEFAULT 0x000E + +//Legacy LPI Configuration 3 register +#define PEF7071_LEG_LPI_CFG3_IDLE 0x00FF +#define PEF7071_LEG_LPI_CFG3_IDLE_DEFAULT 0x0040 + +//C++ guard +#ifdef __cplusplus +extern "C" { +#endif + +//PEF7071 Ethernet PHY driver +extern const PhyDriver pef7071PhyDriver; + +//PEF7071 related functions +error_t pef7071Init(NetInterface *interface); + +void pef7071Tick(NetInterface *interface); + +void pef7071EnableIrq(NetInterface *interface); +void pef7071DisableIrq(NetInterface *interface); + +void pef7071EventHandler(NetInterface *interface); + +void pef7071WritePhyReg(NetInterface *interface, uint8_t address, + uint16_t data); + +uint16_t pef7071ReadPhyReg(NetInterface *interface, uint8_t address); + +void pef7071DumpPhyReg(NetInterface *interface); + +//C++ guard +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/phy/rtl8211e_driver.c b/drivers/phy/rtl8211e_driver.c index 59a68621..0e133b55 100644 --- a/drivers/phy/rtl8211e_driver.c +++ b/drivers/phy/rtl8211e_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/rtl8211e_driver.h b/drivers/phy/rtl8211e_driver.h index 3601cc78..d10d4117 100644 --- a/drivers/phy/rtl8211e_driver.h +++ b/drivers/phy/rtl8211e_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _RTL8211E_DRIVER_H diff --git a/drivers/phy/rtl8211f_driver.c b/drivers/phy/rtl8211f_driver.c index b98d0a1b..506f5d63 100644 --- a/drivers/phy/rtl8211f_driver.c +++ b/drivers/phy/rtl8211f_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/rtl8211f_driver.h b/drivers/phy/rtl8211f_driver.h index 6da39825..2ef3f26e 100644 --- a/drivers/phy/rtl8211f_driver.h +++ b/drivers/phy/rtl8211f_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _RTL8211F_DRIVER_H diff --git a/drivers/phy/st802rt1a_driver.c b/drivers/phy/st802rt1a_driver.c index 7da09688..3c955ac6 100644 --- a/drivers/phy/st802rt1a_driver.c +++ b/drivers/phy/st802rt1a_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/st802rt1a_driver.h b/drivers/phy/st802rt1a_driver.h index cc9b6145..e2d8be61 100644 --- a/drivers/phy/st802rt1a_driver.h +++ b/drivers/phy/st802rt1a_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ST802RT1A_DRIVER_H diff --git a/drivers/phy/tja1100_driver.c b/drivers/phy/tja1100_driver.c index b4a96407..e54ac779 100644 --- a/drivers/phy/tja1100_driver.c +++ b/drivers/phy/tja1100_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -104,7 +104,7 @@ error_t tja1100Init(NetInterface *interface) //Select RMII mode (25MHz XTAL) value = tja1100ReadPhyReg(interface, TJA1100_CONFIG1); value &= ~TJA1100_CONFIG1_MII_MODE; - value |= TJA1100_CONFIG1_MII_MODE_RMII_25MHZ; + value |= TJA1100_CONFIG1_MII_MODE_RMII_25MHZ_XTAL; tja1100WritePhyReg(interface, TJA1100_CONFIG1, value); //The PHY is configured for autonomous operation diff --git a/drivers/phy/tja1100_driver.h b/drivers/phy/tja1100_driver.h index 5640ca70..4e8d3e22 100644 --- a/drivers/phy/tja1100_driver.h +++ b/drivers/phy/tja1100_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TJA1100_DRIVER_H @@ -42,249 +42,251 @@ #endif //TJA1100 PHY registers -#define TJA1100_BASIC_CTRL 0x00 -#define TJA1100_BASIC_STAT 0x01 -#define TJA1100_PHY_ID1 0x02 -#define TJA1100_PHY_ID2 0x03 -#define TJA1100_EXTENDED_STAT 0x0F -#define TJA1100_PHY_ID3 0x10 -#define TJA1100_EXTENDED_CTRL 0x11 -#define TJA1100_CONFIG1 0x12 -#define TJA1100_CONFIG2 0x13 -#define TJA1100_SYM_ERR_COUNTER 0x14 -#define TJA1100_INT_SRC 0x15 -#define TJA1100_INT_EN 0x16 -#define TJA1100_COMM_STAT 0x17 -#define TJA1100_GENERAL_STAT 0x18 -#define TJA1100_EXTERNAL_STAT 0x19 -#define TJA1100_LINK_FAIL_COUNTER 0x1A +#define TJA1100_BASIC_CTRL 0x00 +#define TJA1100_BASIC_STAT 0x01 +#define TJA1100_PHY_ID1 0x02 +#define TJA1100_PHY_ID2 0x03 +#define TJA1100_EXTENDED_STAT 0x0F +#define TJA1100_PHY_ID3 0x10 +#define TJA1100_EXTENDED_CTRL 0x11 +#define TJA1100_CONFIG1 0x12 +#define TJA1100_CONFIG2 0x13 +#define TJA1100_SYM_ERR_COUNTER 0x14 +#define TJA1100_INT_SRC 0x15 +#define TJA1100_INT_EN 0x16 +#define TJA1100_COMM_STAT 0x17 +#define TJA1100_GENERAL_STAT 0x18 +#define TJA1100_EXTERNAL_STAT 0x19 +#define TJA1100_LINK_FAIL_COUNTER 0x1A //Basic control register -#define TJA1100_BASIC_CTRL_RESET 0x8000 -#define TJA1100_BASIC_CTRL_LOOPBACK 0x4000 -#define TJA1100_BASIC_CTRL_SPEED_SEL_LSB 0x2000 -#define TJA1100_BASIC_CTRL_AUTONEG_EN 0x1000 -#define TJA1100_BASIC_CTRL_POWER_DOWN 0x0800 -#define TJA1100_BASIC_CTRL_ISOLATE 0x0400 -#define TJA1100_BASIC_CTRL_RE_AUTONEG 0x0200 -#define TJA1100_BASIC_CTRL_DUPLEX_MODE 0x0100 -#define TJA1100_BASIC_CTRL_COL_TEST 0x0080 -#define TJA1100_BASIC_CTRL_SPEED_SEL_MSB 0x0040 -#define TJA1100_BASIC_CTRL_UNIDIRECT_EN 0x0020 +#define TJA1100_BASIC_CTRL_RESET 0x8000 +#define TJA1100_BASIC_CTRL_LOOPBACK 0x4000 +#define TJA1100_BASIC_CTRL_SPEED_SEL_LSB 0x2000 +#define TJA1100_BASIC_CTRL_AUTONEG_EN 0x1000 +#define TJA1100_BASIC_CTRL_POWER_DOWN 0x0800 +#define TJA1100_BASIC_CTRL_ISOLATE 0x0400 +#define TJA1100_BASIC_CTRL_RE_AUTONEG 0x0200 +#define TJA1100_BASIC_CTRL_DUPLEX_MODE 0x0100 +#define TJA1100_BASIC_CTRL_COL_TEST 0x0080 +#define TJA1100_BASIC_CTRL_SPEED_SEL_MSB 0x0040 +#define TJA1100_BASIC_CTRL_UNIDIRECT_EN 0x0020 //Basic status register -#define TJA1100_BASIC_STAT_100BT4 0x8000 -#define TJA1100_BASIC_STAT_100BTX_FD 0x4000 -#define TJA1100_BASIC_STAT_100BTX_HD 0x2000 -#define TJA1100_BASIC_STAT_10BT_FD 0x1000 -#define TJA1100_BASIC_STAT_10BT_HD 0x0800 -#define TJA1100_BASIC_STAT_100BT2_FD 0x0400 -#define TJA1100_BASIC_STAT_100BT2_HD 0x0200 -#define TJA1100_BASIC_STAT_EXTENDED_STATUS 0x0100 -#define TJA1100_BASIC_STAT_UNIDIRECT_ABILITY 0x0080 -#define TJA1100_BASIC_STAT_MF_PREAMBLE_SUPPR 0x0040 -#define TJA1100_BASIC_STAT_AUTONEG_COMPLETE 0x0020 -#define TJA1100_BASIC_STAT_REMOTE_FAULT 0x0010 -#define TJA1100_BASIC_STAT_AUTONEG_ABILITY 0x0008 -#define TJA1100_BASIC_STAT_LINK_STATUS 0x0004 -#define TJA1100_BASIC_STAT_JABBER_DETECT 0x0002 -#define TJA1100_BASIC_STAT_EXTENDED_CAPABILITY 0x0001 +#define TJA1100_BASIC_STAT_100BT4 0x8000 +#define TJA1100_BASIC_STAT_100BTX_FD 0x4000 +#define TJA1100_BASIC_STAT_100BTX_HD 0x2000 +#define TJA1100_BASIC_STAT_10BT_FD 0x1000 +#define TJA1100_BASIC_STAT_10BT_HD 0x0800 +#define TJA1100_BASIC_STAT_100BT2_FD 0x0400 +#define TJA1100_BASIC_STAT_100BT2_HD 0x0200 +#define TJA1100_BASIC_STAT_EXTENDED_STATUS 0x0100 +#define TJA1100_BASIC_STAT_UNIDIRECT_ABILITY 0x0080 +#define TJA1100_BASIC_STAT_MF_PREAMBLE_SUPPR 0x0040 +#define TJA1100_BASIC_STAT_AUTONEG_COMPLETE 0x0020 +#define TJA1100_BASIC_STAT_REMOTE_FAULT 0x0010 +#define TJA1100_BASIC_STAT_AUTONEG_ABILITY 0x0008 +#define TJA1100_BASIC_STAT_LINK_STATUS 0x0004 +#define TJA1100_BASIC_STAT_JABBER_DETECT 0x0002 +#define TJA1100_BASIC_STAT_EXTENDED_CAPABILITY 0x0001 //PHY identification 1 register -#define TJA1100_PHY_ID1_OUI_MSB 0xFFFF -#define TJA1100_PHY_ID1_OUI_MSB_DEFAULT 0x0180 +#define TJA1100_PHY_ID1_OUI_MSB 0xFFFF +#define TJA1100_PHY_ID1_OUI_MSB_DEFAULT 0x0180 //PHY identification 2 register -#define TJA1100_PHY_ID2_OUI_LSB 0xFC00 -#define TJA1100_PHY_ID2_OUI_LSB_DEFAULT 0xDC00 -#define TJA1100_PHY_ID2_TYPE_NO 0x03F0 -#define TJA1100_PHY_ID2_TYPE_NO_DEFAULT 0x0040 -#define TJA1100_PHY_ID2_REVISION_NO 0x000F +#define TJA1100_PHY_ID2_OUI_LSB 0xFC00 +#define TJA1100_PHY_ID2_OUI_LSB_DEFAULT 0xDC00 +#define TJA1100_PHY_ID2_TYPE_NO 0x03F0 +#define TJA1100_PHY_ID2_TYPE_NO_DEFAULT 0x0040 +#define TJA1100_PHY_ID2_REVISION_NO 0x000F //Extended status register -#define TJA1100_EXTENDED_STAT_1000BX_FD 0x8000 -#define TJA1100_EXTENDED_STAT_1000BX_HD 0x4000 -#define TJA1100_EXTENDED_STAT_1000BT_FD 0x2000 -#define TJA1100_EXTENDED_STAT_1000BT_HD 0x1000 -#define TJA1100_EXTENDED_STAT_100BT1 0x0080 -#define TJA1100_EXTENDED_STAT_1000BT1 0x0040 +#define TJA1100_EXTENDED_STAT_1000BX_FD 0x8000 +#define TJA1100_EXTENDED_STAT_1000BX_HD 0x4000 +#define TJA1100_EXTENDED_STAT_1000BT_FD 0x2000 +#define TJA1100_EXTENDED_STAT_1000BT_HD 0x1000 +#define TJA1100_EXTENDED_STAT_100BT1 0x0080 +#define TJA1100_EXTENDED_STAT_1000BT1 0x0040 //PHY identification 3 register -#define TJA1100_PHY_ID3_VERSION_NO 0x00FF +#define TJA1100_PHY_ID3_VERSION_NO 0x00FF //Extended control register -#define TJA1100_EXTENDED_CTRL_LINK_CONTROL 0x8000 -#define TJA1100_EXTENDED_CTRL_POWER_MODE 0x7800 -#define TJA1100_EXTENDED_CTRL_POWER_MODE_NO_CHANGE 0x0000 -#define TJA1100_EXTENDED_CTRL_POWER_MODE_NORMAL 0x1800 -#define TJA1100_EXTENDED_CTRL_POWER_MODE_SLEEP_REQ 0x5800 -#define TJA1100_EXTENDED_CTRL_POWER_MODE_STANDBY 0x6000 -#define TJA1100_EXTENDED_CTRL_SLAVE_JITTER_TEST 0x0400 -#define TJA1100_EXTENDED_CTRL_TRAINING_RESTART 0x0200 -#define TJA1100_EXTENDED_CTRL_TEST_MODE 0x01C0 -#define TJA1100_EXTENDED_CTRL_TEST_MODE_0 0x0000 -#define TJA1100_EXTENDED_CTRL_TEST_MODE_1 0x0040 -#define TJA1100_EXTENDED_CTRL_TEST_MODE_2 0x0080 -#define TJA1100_EXTENDED_CTRL_TEST_MODE_3 0x00C0 -#define TJA1100_EXTENDED_CTRL_TEST_MODE_4 0x0100 -#define TJA1100_EXTENDED_CTRL_TEST_MODE_5 0x0140 -#define TJA1100_EXTENDED_CTRL_TEST_MODE_6 0x0180 -#define TJA1100_EXTENDED_CTRL_CABLE_TEST 0x0020 -#define TJA1100_EXTENDED_CTRL_LOOPBACK_MODE 0x0018 -#define TJA1100_EXTENDED_CTRL_LOOPBACK_MODE_INTERNAL 0x0000 -#define TJA1100_EXTENDED_CTRL_LOOPBACK_MODE_EXTERNAL 0x0008 -#define TJA1100_EXTENDED_CTRL_LOOPBACK_MODE_REMOTE 0x0018 -#define TJA1100_EXTENDED_CTRL_CONFIG_EN 0x0004 -#define TJA1100_EXTENDED_CTRL_CONFIG_INH 0x0002 -#define TJA1100_EXTENDED_CTRL_WAKE_REQUEST 0x0001 +#define TJA1100_EXTENDED_CTRL_LINK_CONTROL 0x8000 +#define TJA1100_EXTENDED_CTRL_POWER_MODE 0x7800 +#define TJA1100_EXTENDED_CTRL_POWER_MODE_NO_CHANGE 0x0000 +#define TJA1100_EXTENDED_CTRL_POWER_MODE_NORMAL 0x1800 +#define TJA1100_EXTENDED_CTRL_POWER_MODE_SLEEP_REQ 0x5800 +#define TJA1100_EXTENDED_CTRL_POWER_MODE_STANDBY 0x6000 +#define TJA1100_EXTENDED_CTRL_SLAVE_JITTER_TEST 0x0400 +#define TJA1100_EXTENDED_CTRL_TRAINING_RESTART 0x0200 +#define TJA1100_EXTENDED_CTRL_TEST_MODE 0x01C0 +#define TJA1100_EXTENDED_CTRL_TEST_MODE_0 0x0000 +#define TJA1100_EXTENDED_CTRL_TEST_MODE_1 0x0040 +#define TJA1100_EXTENDED_CTRL_TEST_MODE_2 0x0080 +#define TJA1100_EXTENDED_CTRL_TEST_MODE_3 0x00C0 +#define TJA1100_EXTENDED_CTRL_TEST_MODE_4 0x0100 +#define TJA1100_EXTENDED_CTRL_TEST_MODE_5 0x0140 +#define TJA1100_EXTENDED_CTRL_TEST_MODE_6 0x0180 +#define TJA1100_EXTENDED_CTRL_CABLE_TEST 0x0020 +#define TJA1100_EXTENDED_CTRL_LOOPBACK_MODE 0x0018 +#define TJA1100_EXTENDED_CTRL_LOOPBACK_MODE_INTERNAL 0x0000 +#define TJA1100_EXTENDED_CTRL_LOOPBACK_MODE_EXTERNAL 0x0008 +#define TJA1100_EXTENDED_CTRL_LOOPBACK_MODE_REMOTE 0x0018 +#define TJA1100_EXTENDED_CTRL_CONFIG_EN 0x0004 +#define TJA1100_EXTENDED_CTRL_CONFIG_INH 0x0002 +#define TJA1100_EXTENDED_CTRL_WAKE_REQUEST 0x0001 //Configuration 1 register -#define TJA1100_CONFIG1_MASTER_SLAVE 0x8000 -#define TJA1100_CONFIG1_AUTO_OP 0x4000 -#define TJA1100_CONFIG1_LINK_LENGTH 0x2000 -#define TJA1100_CONFIG1_TX_AMPLITUDE 0x0C00 -#define TJA1100_CONFIG1_TX_AMPLITUDE_500MV 0x0000 -#define TJA1100_CONFIG1_TX_AMPLITUDE_750MV 0x0400 -#define TJA1100_CONFIG1_TX_AMPLITUDE_1000MV 0x0800 -#define TJA1100_CONFIG1_TX_AMPLITUDE_1250MV 0x0C00 -#define TJA1100_CONFIG1_MII_MODE 0x0300 -#define TJA1100_CONFIG1_MII_MODE_MII 0x0000 -#define TJA1100_CONFIG1_MII_MODE_RMII_50MHZ 0x0100 -#define TJA1100_CONFIG1_MII_MODE_RMII_25MHZ 0x0200 -#define TJA1100_CONFIG1_MII_MODE_REV_MII 0x0300 -#define TJA1100_CONFIG1_MII_DRIVER 0x0080 -#define TJA1100_CONFIG1_LED_MODE 0x0030 -#define TJA1100_CONFIG1_LED_MODE_LINK_UP 0x0000 -#define TJA1100_CONFIG1_LED_MODE_FRAME_RX 0x0010 -#define TJA1100_CONFIG1_LED_MODE_SYM_ERR 0x0020 -#define TJA1100_CONFIG1_LED_MODE_CRS 0x0030 -#define TJA1100_CONFIG1_LED_ENABLE 0x0008 -#define TJA1100_CONFIG1_CONFIG_WAKE 0x0004 -#define TJA1100_CONFIG1_AUTO_PWD 0x0002 +#define TJA1100_CONFIG1_MASTER_SLAVE 0x8000 +#define TJA1100_CONFIG1_AUTO_OP 0x4000 +#define TJA1100_CONFIG1_LINK_LENGTH 0x2000 +#define TJA1100_CONFIG1_TX_AMPLITUDE 0x0C00 +#define TJA1100_CONFIG1_TX_AMPLITUDE_500MV 0x0000 +#define TJA1100_CONFIG1_TX_AMPLITUDE_750MV 0x0400 +#define TJA1100_CONFIG1_TX_AMPLITUDE_1000MV 0x0800 +#define TJA1100_CONFIG1_TX_AMPLITUDE_1250MV 0x0C00 +#define TJA1100_CONFIG1_MII_MODE 0x0300 +#define TJA1100_CONFIG1_MII_MODE_MII 0x0000 +#define TJA1100_CONFIG1_MII_MODE_RMII_50MHZ_REFCLK_IN 0x0100 +#define TJA1100_CONFIG1_MII_MODE_RMII_25MHZ_XTAL 0x0200 +#define TJA1100_CONFIG1_MII_MODE_REV_MII 0x0300 +#define TJA1100_CONFIG1_MII_DRIVER 0x0080 +#define TJA1100_CONFIG1_MII_DRIVER_STANDARD 0x0000 +#define TJA1100_CONFIG1_MII_DRIVER_REDUCED 0x0080 +#define TJA1100_CONFIG1_LED_MODE 0x0030 +#define TJA1100_CONFIG1_LED_MODE_LINK_UP 0x0000 +#define TJA1100_CONFIG1_LED_MODE_FRAME_RX 0x0010 +#define TJA1100_CONFIG1_LED_MODE_SYM_ERR 0x0020 +#define TJA1100_CONFIG1_LED_MODE_CRS 0x0030 +#define TJA1100_CONFIG1_LED_ENABLE 0x0008 +#define TJA1100_CONFIG1_CONFIG_WAKE 0x0004 +#define TJA1100_CONFIG1_AUTO_PWD 0x0002 //Configuration 2 register -#define TJA1100_CONFIG2_PHYAD 0xF800 -#define TJA1100_CONFIG2_SQI_AVERAGING 0x0600 -#define TJA1100_CONFIG2_SQI_AVERAGING_32_SYMBOLS 0x0000 -#define TJA1100_CONFIG2_SQI_AVERAGING_64_SYMBOLS 0x0200 -#define TJA1100_CONFIG2_SQI_AVERAGING_128_SYMBOLS 0x0400 -#define TJA1100_CONFIG2_SQI_AVERAGING_256_SYMBOLS 0x0600 -#define TJA1100_CONFIG2_SQI_WLIMIT 0x01C0 -#define TJA1100_CONFIG2_SQI_WLIMIT_NONE 0x0000 -#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_A 0x0040 -#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_B 0x0080 -#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_C 0x00C0 -#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_D 0x0100 -#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_E 0x0140 -#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_F 0x0180 -#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_G 0x01C0 -#define TJA1100_CONFIG2_SQI_FAILLIMIT 0x0038 -#define TJA1100_CONFIG2_SQI_FAILLIMIT_NONE 0x0000 -#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_A 0x0008 -#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_B 0x0010 -#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_C 0x0018 -#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_D 0x0020 -#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_E 0x0028 -#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_F 0x0030 -#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_G 0x0038 -#define TJA1100_CONFIG2_JUMBO_ENABLE 0x0004 -#define TJA1100_CONFIG2_SLEEP_REQUEST_TO 0x0003 -#define TJA1100_CONFIG2_SLEEP_REQUEST_TO_0_4MS 0x0000 -#define TJA1100_CONFIG2_SLEEP_REQUEST_TO_1MS 0x0001 -#define TJA1100_CONFIG2_SLEEP_REQUEST_TO_4MS 0x0002 -#define TJA1100_CONFIG2_SLEEP_REQUEST_TO_16MS 0x0003 +#define TJA1100_CONFIG2_PHYAD 0xF800 +#define TJA1100_CONFIG2_SQI_AVERAGING 0x0600 +#define TJA1100_CONFIG2_SQI_AVERAGING_32_SYMBOLS 0x0000 +#define TJA1100_CONFIG2_SQI_AVERAGING_64_SYMBOLS 0x0200 +#define TJA1100_CONFIG2_SQI_AVERAGING_128_SYMBOLS 0x0400 +#define TJA1100_CONFIG2_SQI_AVERAGING_256_SYMBOLS 0x0600 +#define TJA1100_CONFIG2_SQI_WLIMIT 0x01C0 +#define TJA1100_CONFIG2_SQI_WLIMIT_NONE 0x0000 +#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_A 0x0040 +#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_B 0x0080 +#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_C 0x00C0 +#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_D 0x0100 +#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_E 0x0140 +#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_F 0x0180 +#define TJA1100_CONFIG2_SQI_WLIMIT_CLASS_G 0x01C0 +#define TJA1100_CONFIG2_SQI_FAILLIMIT 0x0038 +#define TJA1100_CONFIG2_SQI_FAILLIMIT_NONE 0x0000 +#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_A 0x0008 +#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_B 0x0010 +#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_C 0x0018 +#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_D 0x0020 +#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_E 0x0028 +#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_F 0x0030 +#define TJA1100_CONFIG2_SQI_FAILLIMIT_CLASS_G 0x0038 +#define TJA1100_CONFIG2_JUMBO_ENABLE 0x0004 +#define TJA1100_CONFIG2_SLEEP_REQUEST_TO 0x0003 +#define TJA1100_CONFIG2_SLEEP_REQUEST_TO_0_4MS 0x0000 +#define TJA1100_CONFIG2_SLEEP_REQUEST_TO_1MS 0x0001 +#define TJA1100_CONFIG2_SLEEP_REQUEST_TO_4MS 0x0002 +#define TJA1100_CONFIG2_SLEEP_REQUEST_TO_16MS 0x0003 //Symbol error counter register -#define TJA1100_SYM_ERR_COUNTER_SYM_ERR_CNT 0xFFFF +#define TJA1100_SYM_ERR_COUNTER_SYM_ERR_CNT 0xFFFF //Interrupt source register -#define TJA1100_INT_SRC_PWON 0x8000 -#define TJA1100_INT_SRC_WAKEUP 0x4000 -#define TJA1100_INT_SRC_PHY_INIT_FAIL 0x0800 -#define TJA1100_INT_SRC_LINK_STATUS_FAIL 0x0400 -#define TJA1100_INT_SRC_LINK_STATUS_UP 0x0200 -#define TJA1100_INT_SRC_SYM_ERR 0x0100 -#define TJA1100_INT_SRC_TRAINING_FAILED 0x0080 -#define TJA1100_INT_SRC_SQI_WARNING 0x0040 -#define TJA1100_INT_SRC_CONTROL_ERR 0x0020 -#define TJA1100_INT_SRC_UV_ERR 0x0008 -#define TJA1100_INT_SRC_UV_RECOVERY 0x0004 -#define TJA1100_INT_SRC_TEMP_ERR 0x0002 -#define TJA1100_INT_SRC_SLEEP_ABORT 0x0001 +#define TJA1100_INT_SRC_PWON 0x8000 +#define TJA1100_INT_SRC_WAKEUP 0x4000 +#define TJA1100_INT_SRC_PHY_INIT_FAIL 0x0800 +#define TJA1100_INT_SRC_LINK_STATUS_FAIL 0x0400 +#define TJA1100_INT_SRC_LINK_STATUS_UP 0x0200 +#define TJA1100_INT_SRC_SYM_ERR 0x0100 +#define TJA1100_INT_SRC_TRAINING_FAILED 0x0080 +#define TJA1100_INT_SRC_SQI_WARNING 0x0040 +#define TJA1100_INT_SRC_CONTROL_ERR 0x0020 +#define TJA1100_INT_SRC_UV_ERR 0x0008 +#define TJA1100_INT_SRC_UV_RECOVERY 0x0004 +#define TJA1100_INT_SRC_TEMP_ERR 0x0002 +#define TJA1100_INT_SRC_SLEEP_ABORT 0x0001 //Interrupt enable register -#define TJA1100_INT_EN_PWON 0x8000 -#define TJA1100_INT_EN_WAKEUP 0x4000 -#define TJA1100_INT_EN_PHY_INIT_FAIL 0x0800 -#define TJA1100_INT_EN_LINK_STATUS_FAIL 0x0400 -#define TJA1100_INT_EN_LINK_STATUS_UP 0x0200 -#define TJA1100_INT_EN_SYM_ERR 0x0100 -#define TJA1100_INT_EN_TRAINING_FAILED 0x0080 -#define TJA1100_INT_EN_SQI_WARNING 0x0040 -#define TJA1100_INT_EN_CONTROL_ERR 0x0020 -#define TJA1100_INT_EN_UV_ERR 0x0008 -#define TJA1100_INT_EN_UV_RECOVERY 0x0004 -#define TJA1100_INT_EN_TEMP_ERR 0x0002 -#define TJA1100_INT_EN_SLEEP_ABORT 0x0001 +#define TJA1100_INT_EN_PWON 0x8000 +#define TJA1100_INT_EN_WAKEUP 0x4000 +#define TJA1100_INT_EN_PHY_INIT_FAIL 0x0800 +#define TJA1100_INT_EN_LINK_STATUS_FAIL 0x0400 +#define TJA1100_INT_EN_LINK_STATUS_UP 0x0200 +#define TJA1100_INT_EN_SYM_ERR 0x0100 +#define TJA1100_INT_EN_TRAINING_FAILED 0x0080 +#define TJA1100_INT_EN_SQI_WARNING 0x0040 +#define TJA1100_INT_EN_CONTROL_ERR 0x0020 +#define TJA1100_INT_EN_UV_ERR 0x0008 +#define TJA1100_INT_EN_UV_RECOVERY 0x0004 +#define TJA1100_INT_EN_TEMP_ERR 0x0002 +#define TJA1100_INT_EN_SLEEP_ABORT 0x0001 //Communication status register -#define TJA1100_COMM_STAT_LINK_UP 0x8000 -#define TJA1100_COMM_STAT_TX_MODE 0x6000 -#define TJA1100_COMM_STAT_TX_MODE_DISABLED 0x0000 -#define TJA1100_COMM_STAT_TX_MODE_SEND_N 0x2000 -#define TJA1100_COMM_STAT_TX_MODE_SEND_I 0x4000 -#define TJA1100_COMM_STAT_TX_MODE_SEND_Z 0x6000 -#define TJA1100_COMM_STAT_LOC_RCVR_STATUS 0x1000 -#define TJA1100_COMM_STAT_REM_RCVR_STATUS 0x0800 -#define TJA1100_COMM_STAT_SCR_LOCKED 0x0400 -#define TJA1100_COMM_STAT_SSD_ERR 0x0200 -#define TJA1100_COMM_STAT_ESD_ERR 0x0100 -#define TJA1100_COMM_STAT_SQI 0x00E0 -#define TJA1100_COMM_STAT_SQI_WORSE_THAN_CLASS_A 0x0000 -#define TJA1100_COMM_STAT_SQI_CLASS_A 0x0020 -#define TJA1100_COMM_STAT_SQI_CLASS_B 0x0040 -#define TJA1100_COMM_STAT_SQI_CLASS_C 0x0060 -#define TJA1100_COMM_STAT_SQI_CLASS_D 0x0080 -#define TJA1100_COMM_STAT_SQI_CLASS_E 0x00A0 -#define TJA1100_COMM_STAT_SQI_CLASS_F 0x00C0 -#define TJA1100_COMM_STAT_SQI_CLASS_G 0x00E0 -#define TJA1100_COMM_STAT_RECEIVE_ERR 0x0010 -#define TJA1100_COMM_STAT_TRANSMIT_ERR 0x0008 -#define TJA1100_COMM_STAT_PHY_STATE 0x0007 -#define TJA1100_COMM_STAT_PHY_STATE_IDLE 0x0000 -#define TJA1100_COMM_STAT_PHY_STATE_INITIALIZING 0x0001 -#define TJA1100_COMM_STAT_PHY_STATE_CONFIGURED 0x0002 -#define TJA1100_COMM_STAT_PHY_STATE_OFFLINE 0x0003 -#define TJA1100_COMM_STAT_PHY_STATE_ACTIVE 0x0004 -#define TJA1100_COMM_STAT_PHY_STATE_ISOLATE 0x0005 -#define TJA1100_COMM_STAT_PHY_STATE_CABLE_TEST 0x0006 -#define TJA1100_COMM_STAT_PHY_STATE_TEST_MODE 0x0007 +#define TJA1100_COMM_STAT_LINK_UP 0x8000 +#define TJA1100_COMM_STAT_TX_MODE 0x6000 +#define TJA1100_COMM_STAT_TX_MODE_DISABLED 0x0000 +#define TJA1100_COMM_STAT_TX_MODE_SEND_N 0x2000 +#define TJA1100_COMM_STAT_TX_MODE_SEND_I 0x4000 +#define TJA1100_COMM_STAT_TX_MODE_SEND_Z 0x6000 +#define TJA1100_COMM_STAT_LOC_RCVR_STATUS 0x1000 +#define TJA1100_COMM_STAT_REM_RCVR_STATUS 0x0800 +#define TJA1100_COMM_STAT_SCR_LOCKED 0x0400 +#define TJA1100_COMM_STAT_SSD_ERR 0x0200 +#define TJA1100_COMM_STAT_ESD_ERR 0x0100 +#define TJA1100_COMM_STAT_SQI 0x00E0 +#define TJA1100_COMM_STAT_SQI_WORSE_THAN_CLASS_A 0x0000 +#define TJA1100_COMM_STAT_SQI_CLASS_A 0x0020 +#define TJA1100_COMM_STAT_SQI_CLASS_B 0x0040 +#define TJA1100_COMM_STAT_SQI_CLASS_C 0x0060 +#define TJA1100_COMM_STAT_SQI_CLASS_D 0x0080 +#define TJA1100_COMM_STAT_SQI_CLASS_E 0x00A0 +#define TJA1100_COMM_STAT_SQI_CLASS_F 0x00C0 +#define TJA1100_COMM_STAT_SQI_CLASS_G 0x00E0 +#define TJA1100_COMM_STAT_RECEIVE_ERR 0x0010 +#define TJA1100_COMM_STAT_TRANSMIT_ERR 0x0008 +#define TJA1100_COMM_STAT_PHY_STATE 0x0007 +#define TJA1100_COMM_STAT_PHY_STATE_IDLE 0x0000 +#define TJA1100_COMM_STAT_PHY_STATE_INITIALIZING 0x0001 +#define TJA1100_COMM_STAT_PHY_STATE_CONFIGURED 0x0002 +#define TJA1100_COMM_STAT_PHY_STATE_OFFLINE 0x0003 +#define TJA1100_COMM_STAT_PHY_STATE_ACTIVE 0x0004 +#define TJA1100_COMM_STAT_PHY_STATE_ISOLATE 0x0005 +#define TJA1100_COMM_STAT_PHY_STATE_CABLE_TEST 0x0006 +#define TJA1100_COMM_STAT_PHY_STATE_TEST_MODE 0x0007 //General status register -#define TJA1100_GENERAL_STAT_INT_STATUS 0x8000 -#define TJA1100_GENERAL_STAT_PLL_LOCKED 0x4000 -#define TJA1100_GENERAL_STAT_LOCAL_WU 0x2000 -#define TJA1100_GENERAL_STAT_REMOTE_WU 0x1000 -#define TJA1100_GENERAL_STAT_DATA_DET_WU 0x0800 -#define TJA1100_GENERAL_STAT_EN_STATUS 0x0400 -#define TJA1100_GENERAL_STAT_RESET_STATUS 0x0200 -#define TJA1100_GENERAL_STAT_LINKFAIL_CNT 0x00F8 +#define TJA1100_GENERAL_STAT_INT_STATUS 0x8000 +#define TJA1100_GENERAL_STAT_PLL_LOCKED 0x4000 +#define TJA1100_GENERAL_STAT_LOCAL_WU 0x2000 +#define TJA1100_GENERAL_STAT_REMOTE_WU 0x1000 +#define TJA1100_GENERAL_STAT_DATA_DET_WU 0x0800 +#define TJA1100_GENERAL_STAT_EN_STATUS 0x0400 +#define TJA1100_GENERAL_STAT_RESET_STATUS 0x0200 +#define TJA1100_GENERAL_STAT_LINKFAIL_CNT 0x00F8 //External status register -#define TJA1100_EXTERNAL_STAT_UV_VDDA_3V3 0x4000 -#define TJA1100_EXTERNAL_STAT_UV_VDDD_1V8 0x2000 -#define TJA1100_EXTERNAL_STAT_UV_VDDA_1V8 0x1000 -#define TJA1100_EXTERNAL_STAT_UV_VDDIO 0x0800 -#define TJA1100_EXTERNAL_STAT_TEMP_HIGH 0x0400 -#define TJA1100_EXTERNAL_STAT_TEMP_WARN 0x0200 -#define TJA1100_EXTERNAL_STAT_SHORT_DETECT 0x0100 -#define TJA1100_EXTERNAL_STAT_OPEN_DETECT 0x0080 -#define TJA1100_EXTERNAL_STAT_POLARITY_DETECT 0x0040 -#define TJA1100_EXTERNAL_STAT_INTERLEAVE_DETECT 0x0020 +#define TJA1100_EXTERNAL_STAT_UV_VDDA_3V3 0x4000 +#define TJA1100_EXTERNAL_STAT_UV_VDDD_1V8 0x2000 +#define TJA1100_EXTERNAL_STAT_UV_VDDA_1V8 0x1000 +#define TJA1100_EXTERNAL_STAT_UV_VDDIO 0x0800 +#define TJA1100_EXTERNAL_STAT_TEMP_HIGH 0x0400 +#define TJA1100_EXTERNAL_STAT_TEMP_WARN 0x0200 +#define TJA1100_EXTERNAL_STAT_SHORT_DETECT 0x0100 +#define TJA1100_EXTERNAL_STAT_OPEN_DETECT 0x0080 +#define TJA1100_EXTERNAL_STAT_POLARITY_DETECT 0x0040 +#define TJA1100_EXTERNAL_STAT_INTERLEAVE_DETECT 0x0020 //Link-fail counter register -#define TJA1100_LINK_FAIL_COUNTER_LOC_RCVR_CNT 0xFF00 -#define TJA1100_LINK_FAIL_COUNTER_REM_RCVR_CNT 0x00FF +#define TJA1100_LINK_FAIL_COUNTER_LOC_RCVR_CNT 0xFF00 +#define TJA1100_LINK_FAIL_COUNTER_REM_RCVR_CNT 0x00FF //C++ guard #ifdef __cplusplus diff --git a/drivers/phy/tja1101_driver.c b/drivers/phy/tja1101_driver.c index 90aeafb4..5bb98c6c 100644 --- a/drivers/phy/tja1101_driver.c +++ b/drivers/phy/tja1101_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -101,10 +101,10 @@ error_t tja1101Init(NetInterface *interface) value |= TJA1101_EXTENDED_CTRL_CONFIG_EN; tja1101WritePhyReg(interface, TJA1101_EXTENDED_CTRL, value); - //Select RMII mode (25MHz XTAL) + //Select RMII mode (50MHz output on REF_CLK) value = tja1101ReadPhyReg(interface, TJA1101_CONFIG1); value &= ~TJA1101_CONFIG1_MII_MODE; - value |= TJA1101_CONFIG1_MII_MODE_RMII_25MHZ; + value |= TJA1101_CONFIG1_MII_MODE_RMII_50MHZ_REF_CLK_OUT; tja1101WritePhyReg(interface, TJA1101_CONFIG1, value); //The PHY is configured for autonomous operation diff --git a/drivers/phy/tja1101_driver.h b/drivers/phy/tja1101_driver.h index 2871307e..5fa1e414 100644 --- a/drivers/phy/tja1101_driver.h +++ b/drivers/phy/tja1101_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TJA1101_DRIVER_H @@ -42,256 +42,274 @@ #endif //TJA1101 PHY registers -#define TJA1101_BASIC_CTRL 0x00 -#define TJA1101_BASIC_STAT 0x01 -#define TJA1101_PHY_ID1 0x02 -#define TJA1101_PHY_ID2 0x03 -#define TJA1101_EXTENDED_STAT 0x0F -#define TJA1101_PHY_ID3 0x10 -#define TJA1101_EXTENDED_CTRL 0x11 -#define TJA1101_CONFIG1 0x12 -#define TJA1101_CONFIG2 0x13 -#define TJA1101_SYM_ERR_COUNTER 0x14 -#define TJA1101_INT_SRC 0x15 -#define TJA1101_INT_EN 0x16 -#define TJA1101_COMM_STAT 0x17 -#define TJA1101_GENERAL_STAT 0x18 -#define TJA1101_EXTERNAL_STAT 0x19 -#define TJA1101_LINK_FAIL_COUNTER 0x1A -#define TJA1101_COMM_CTRL 0x1B -#define TJA1101_CONFIG3 0x1C +#define TJA1101_BASIC_CTRL 0x00 +#define TJA1101_BASIC_STAT 0x01 +#define TJA1101_PHY_ID1 0x02 +#define TJA1101_PHY_ID2 0x03 +#define TJA1101_EXTENDED_STAT 0x0F +#define TJA1101_PHY_ID3 0x10 +#define TJA1101_EXTENDED_CTRL 0x11 +#define TJA1101_CONFIG1 0x12 +#define TJA1101_CONFIG2 0x13 +#define TJA1101_SYM_ERR_COUNTER 0x14 +#define TJA1101_INT_SRC 0x15 +#define TJA1101_INT_EN 0x16 +#define TJA1101_COMM_STAT 0x17 +#define TJA1101_GENERAL_STAT 0x18 +#define TJA1101_EXTERNAL_STAT 0x19 +#define TJA1101_LINK_FAIL_COUNTER 0x1A +#define TJA1101_COMM_CTRL 0x1B +#define TJA1101_CONFIG3 0x1C //Basic control register -#define TJA1101_BASIC_CTRL_RESET 0x8000 -#define TJA1101_BASIC_CTRL_LOOPBACK 0x4000 -#define TJA1101_BASIC_CTRL_SPEED_SEL_LSB 0x2000 -#define TJA1101_BASIC_CTRL_AUTONEG_EN 0x1000 -#define TJA1101_BASIC_CTRL_POWER_DOWN 0x0800 -#define TJA1101_BASIC_CTRL_ISOLATE 0x0400 -#define TJA1101_BASIC_CTRL_RE_AUTONEG 0x0200 -#define TJA1101_BASIC_CTRL_DUPLEX_MODE 0x0100 -#define TJA1101_BASIC_CTRL_COL_TEST 0x0080 -#define TJA1101_BASIC_CTRL_SPEED_SEL_MSB 0x0040 -#define TJA1101_BASIC_CTRL_UNIDIRECT_EN 0x0020 +#define TJA1101_BASIC_CTRL_RESET 0x8000 +#define TJA1101_BASIC_CTRL_LOOPBACK 0x4000 +#define TJA1101_BASIC_CTRL_SPEED_SEL_LSB 0x2000 +#define TJA1101_BASIC_CTRL_AUTONEG_EN 0x1000 +#define TJA1101_BASIC_CTRL_POWER_DOWN 0x0800 +#define TJA1101_BASIC_CTRL_ISOLATE 0x0400 +#define TJA1101_BASIC_CTRL_RE_AUTONEG 0x0200 +#define TJA1101_BASIC_CTRL_DUPLEX_MODE 0x0100 +#define TJA1101_BASIC_CTRL_COL_TEST 0x0080 +#define TJA1101_BASIC_CTRL_SPEED_SEL_MSB 0x0040 +#define TJA1101_BASIC_CTRL_UNIDIRECT_EN 0x0020 //Basic status register -#define TJA1101_BASIC_STAT_100BT4 0x8000 -#define TJA1101_BASIC_STAT_100BTX_FD 0x4000 -#define TJA1101_BASIC_STAT_100BTX_HD 0x2000 -#define TJA1101_BASIC_STAT_10BT_FD 0x1000 -#define TJA1101_BASIC_STAT_10BT_HD 0x0800 -#define TJA1101_BASIC_STAT_100BT2_FD 0x0400 -#define TJA1101_BASIC_STAT_100BT2_HD 0x0200 -#define TJA1101_BASIC_STAT_EXTENDED_STATUS 0x0100 -#define TJA1101_BASIC_STAT_UNIDIRECT_ABILITY 0x0080 -#define TJA1101_BASIC_STAT_MF_PREAMBLE_SUPPR 0x0040 -#define TJA1101_BASIC_STAT_AUTONEG_COMPLETE 0x0020 -#define TJA1101_BASIC_STAT_REMOTE_FAULT 0x0010 -#define TJA1101_BASIC_STAT_AUTONEG_ABILITY 0x0008 -#define TJA1101_BASIC_STAT_LINK_STATUS 0x0004 -#define TJA1101_BASIC_STAT_JABBER_DETECT 0x0002 -#define TJA1101_BASIC_STAT_EXTENDED_CAPABILITY 0x0001 +#define TJA1101_BASIC_STAT_100BT4 0x8000 +#define TJA1101_BASIC_STAT_100BTX_FD 0x4000 +#define TJA1101_BASIC_STAT_100BTX_HD 0x2000 +#define TJA1101_BASIC_STAT_10BT_FD 0x1000 +#define TJA1101_BASIC_STAT_10BT_HD 0x0800 +#define TJA1101_BASIC_STAT_100BT2_FD 0x0400 +#define TJA1101_BASIC_STAT_100BT2_HD 0x0200 +#define TJA1101_BASIC_STAT_EXTENDED_STATUS 0x0100 +#define TJA1101_BASIC_STAT_UNIDIRECT_ABILITY 0x0080 +#define TJA1101_BASIC_STAT_MF_PREAMBLE_SUPPR 0x0040 +#define TJA1101_BASIC_STAT_AUTONEG_COMPLETE 0x0020 +#define TJA1101_BASIC_STAT_REMOTE_FAULT 0x0010 +#define TJA1101_BASIC_STAT_AUTONEG_ABILITY 0x0008 +#define TJA1101_BASIC_STAT_LINK_STATUS 0x0004 +#define TJA1101_BASIC_STAT_JABBER_DETECT 0x0002 +#define TJA1101_BASIC_STAT_EXTENDED_CAPABILITY 0x0001 //PHY identification 1 register -#define TJA1101_PHY_ID1_OUI_MSB 0xFFFF -#define TJA1101_PHY_ID1_OUI_MSB_DEFAULT 0x0180 +#define TJA1101_PHY_ID1_OUI_MSB 0xFFFF +#define TJA1101_PHY_ID1_OUI_MSB_DEFAULT 0x0180 //PHY identification 2 register -#define TJA1101_PHY_ID2_OUI_LSB 0xFC00 -#define TJA1101_PHY_ID2_OUI_LSB_DEFAULT 0xDC00 -#define TJA1101_PHY_ID2_TYPE_NO 0x03F0 -#define TJA1101_PHY_ID2_TYPE_NO_DEFAULT 0x0100 -#define TJA1101_PHY_ID2_REVISION_NO 0x000F +#define TJA1101_PHY_ID2_OUI_LSB 0xFC00 +#define TJA1101_PHY_ID2_OUI_LSB_DEFAULT 0xDC00 +#define TJA1101_PHY_ID2_TYPE_NO 0x03F0 +#define TJA1101_PHY_ID2_TYPE_NO_DEFAULT 0x0100 +#define TJA1101_PHY_ID2_REVISION_NO 0x000F //Extended status register -#define TJA1101_EXTENDED_STAT_1000BX_FD 0x8000 -#define TJA1101_EXTENDED_STAT_1000BX_HD 0x4000 -#define TJA1101_EXTENDED_STAT_1000BT_FD 0x2000 -#define TJA1101_EXTENDED_STAT_1000BT_HD 0x1000 -#define TJA1101_EXTENDED_STAT_100BT1 0x0080 -#define TJA1101_EXTENDED_STAT_1000BT1 0x0040 +#define TJA1101_EXTENDED_STAT_1000BX_FD 0x8000 +#define TJA1101_EXTENDED_STAT_1000BX_HD 0x4000 +#define TJA1101_EXTENDED_STAT_1000BT_FD 0x2000 +#define TJA1101_EXTENDED_STAT_1000BT_HD 0x1000 +#define TJA1101_EXTENDED_STAT_100BT1 0x0080 +#define TJA1101_EXTENDED_STAT_RTPGE 0x0040 //PHY identification 3 register -#define TJA1101_PHY_ID3_VERSION_NO 0x00FF +#define TJA1101_PHY_ID3_VERSION_NO 0x00FF //Extended control register -#define TJA1101_EXTENDED_CTRL_LINK_CONTROL 0x8000 -#define TJA1101_EXTENDED_CTRL_POWER_MODE 0x7800 -#define TJA1101_EXTENDED_CTRL_POWER_MODE_NO_CHANGE 0x0000 -#define TJA1101_EXTENDED_CTRL_POWER_MODE_NORMAL 0x1800 -#define TJA1101_EXTENDED_CTRL_POWER_MODE_SLEEP_REQ 0x5800 -#define TJA1101_EXTENDED_CTRL_POWER_MODE_STANDBY 0x6000 -#define TJA1101_EXTENDED_CTRL_SLAVE_JITTER_TEST 0x0400 -#define TJA1101_EXTENDED_CTRL_TRAINING_RESTART 0x0200 -#define TJA1101_EXTENDED_CTRL_TEST_MODE 0x01C0 -#define TJA1101_EXTENDED_CTRL_TEST_MODE_0 0x0000 -#define TJA1101_EXTENDED_CTRL_TEST_MODE_1 0x0040 -#define TJA1101_EXTENDED_CTRL_TEST_MODE_2 0x0080 -#define TJA1101_EXTENDED_CTRL_TEST_MODE_3 0x00C0 -#define TJA1101_EXTENDED_CTRL_TEST_MODE_4 0x0100 -#define TJA1101_EXTENDED_CTRL_TEST_MODE_5 0x0140 -#define TJA1101_EXTENDED_CTRL_TEST_MODE_6 0x0180 -#define TJA1101_EXTENDED_CTRL_CABLE_TEST 0x0020 -#define TJA1101_EXTENDED_CTRL_LOOPBACK_MODE 0x0018 -#define TJA1101_EXTENDED_CTRL_LOOPBACK_MODE_INTERNAL 0x0000 -#define TJA1101_EXTENDED_CTRL_LOOPBACK_MODE_EXTERNAL 0x0008 -#define TJA1101_EXTENDED_CTRL_LOOPBACK_MODE_REMOTE 0x0018 -#define TJA1101_EXTENDED_CTRL_CONFIG_EN 0x0004 -#define TJA1101_EXTENDED_CTRL_CONFIG_INH 0x0002 -#define TJA1101_EXTENDED_CTRL_WAKE_REQUEST 0x0001 +#define TJA1101_EXTENDED_CTRL_LINK_CONTROL 0x8000 +#define TJA1101_EXTENDED_CTRL_POWER_MODE 0x7800 +#define TJA1101_EXTENDED_CTRL_POWER_MODE_NO_CHANGE 0x0000 +#define TJA1101_EXTENDED_CTRL_POWER_MODE_NORMAL 0x1800 +#define TJA1101_EXTENDED_CTRL_POWER_MODE_SILENT 0x4800 +#define TJA1101_EXTENDED_CTRL_POWER_MODE_SLEEP 0x5000 +#define TJA1101_EXTENDED_CTRL_POWER_MODE_SLEEP_REQ 0x5800 +#define TJA1101_EXTENDED_CTRL_POWER_MODE_STANDBY 0x6000 +#define TJA1101_EXTENDED_CTRL_SLAVE_JITTER_TEST 0x0400 +#define TJA1101_EXTENDED_CTRL_TRAINING_RESTART 0x0200 +#define TJA1101_EXTENDED_CTRL_TEST_MODE 0x01C0 +#define TJA1101_EXTENDED_CTRL_TEST_MODE_0 0x0000 +#define TJA1101_EXTENDED_CTRL_TEST_MODE_1 0x0040 +#define TJA1101_EXTENDED_CTRL_TEST_MODE_2 0x0080 +#define TJA1101_EXTENDED_CTRL_TEST_MODE_3 0x00C0 +#define TJA1101_EXTENDED_CTRL_TEST_MODE_4 0x0100 +#define TJA1101_EXTENDED_CTRL_TEST_MODE_5 0x0140 +#define TJA1101_EXTENDED_CTRL_TEST_MODE_6 0x0180 +#define TJA1101_EXTENDED_CTRL_CABLE_TEST 0x0020 +#define TJA1101_EXTENDED_CTRL_LOOPBACK_MODE 0x0018 +#define TJA1101_EXTENDED_CTRL_LOOPBACK_MODE_INTERNAL 0x0000 +#define TJA1101_EXTENDED_CTRL_LOOPBACK_MODE_EXTERNAL 0x0008 +#define TJA1101_EXTENDED_CTRL_LOOPBACK_MODE_REMOTE 0x0018 +#define TJA1101_EXTENDED_CTRL_CONFIG_EN 0x0004 +#define TJA1101_EXTENDED_CTRL_WAKE_REQUEST 0x0001 //Configuration 1 register -#define TJA1101_CONFIG1_MASTER_SLAVE 0x8000 -#define TJA1101_CONFIG1_FWDPHYLOC 0x4000 -#define TJA1101_CONFIG1_LINK_LENGTH 0x2000 -#define TJA1101_CONFIG1_REMWUPHY 0x0800 -#define TJA1101_CONFIG1_LOCWUPHY 0x0400 -#define TJA1101_CONFIG1_MII_MODE 0x0300 -#define TJA1101_CONFIG1_MII_MODE_MII 0x0000 -#define TJA1101_CONFIG1_MII_MODE_RMII_50MHZ 0x0100 -#define TJA1101_CONFIG1_MII_MODE_RMII_25MHZ 0x0200 -#define TJA1101_CONFIG1_MII_MODE_REV_MII 0x0300 -#define TJA1101_CONFIG1_MII_DRIVER 0x0080 -#define TJA1101_CONFIG1_SLEEP_CONFIRM 0x0040 -#define TJA1101_CONFIG1_FWDPHYREM 0x0004 -#define TJA1101_CONFIG1_AUTO_PWD 0x0002 -#define TJA1101_CONFIG1_LPS_ACTIVE 0x0001 +#define TJA1101_CONFIG1_MASTER_SLAVE 0x8000 +#define TJA1101_CONFIG1_FWDPHYLOC 0x4000 +#define TJA1101_CONFIG1_REMWUPHY 0x0800 +#define TJA1101_CONFIG1_LOCWUPHY 0x0400 +#define TJA1101_CONFIG1_MII_MODE 0x0300 +#define TJA1101_CONFIG1_MII_MODE_MII 0x0000 +#define TJA1101_CONFIG1_MII_MODE_RMII_50MHZ_REF_CLK_IN 0x0100 +#define TJA1101_CONFIG1_MII_MODE_RMII_50MHZ_REF_CLK_OUT 0x0200 +#define TJA1101_CONFIG1_MII_MODE_REV_MII 0x0300 +#define TJA1101_CONFIG1_MII_DRIVER 0x0080 +#define TJA1101_CONFIG1_MII_DRIVER_STANDARD 0x0000 +#define TJA1101_CONFIG1_MII_DRIVER_REDUCED 0x0080 +#define TJA1101_CONFIG1_SLEEP_CONFIRM 0x0040 +#define TJA1101_CONFIG1_LPS_WUR_DIS 0x0020 +#define TJA1101_CONFIG1_SLEEP_ACK 0x0010 +#define TJA1101_CONFIG1_FWDPHYREM 0x0004 +#define TJA1101_CONFIG1_AUTO_PWD 0x0002 +#define TJA1101_CONFIG1_LPS_ACTIVE 0x0001 //Configuration 2 register -#define TJA1101_CONFIG2_PHYAD 0xF800 -#define TJA1101_CONFIG2_SQI_AVERAGING 0x0600 -#define TJA1101_CONFIG2_SQI_AVERAGING_32_SYMBOLS 0x0000 -#define TJA1101_CONFIG2_SQI_AVERAGING_64_SYMBOLS 0x0200 -#define TJA1101_CONFIG2_SQI_AVERAGING_128_SYMBOLS 0x0400 -#define TJA1101_CONFIG2_SQI_AVERAGING_256_SYMBOLS 0x0600 -#define TJA1101_CONFIG2_SQI_WLIMIT 0x01C0 -#define TJA1101_CONFIG2_SQI_WLIMIT_NONE 0x0000 -#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_A 0x0040 -#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_B 0x0080 -#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_C 0x00C0 -#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_D 0x0100 -#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_E 0x0140 -#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_F 0x0180 -#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_G 0x01C0 -#define TJA1101_CONFIG2_SQI_FAILLIMIT 0x0038 -#define TJA1101_CONFIG2_SQI_FAILLIMIT_NONE 0x0000 -#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_A 0x0008 -#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_B 0x0010 -#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_C 0x0018 -#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_D 0x0020 -#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_E 0x0028 -#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_F 0x0030 -#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_G 0x0038 -#define TJA1101_CONFIG2_JUMBO_ENABLE 0x0004 -#define TJA1101_CONFIG2_SLEEP_REQUEST_TO 0x0003 -#define TJA1101_CONFIG2_SLEEP_REQUEST_TO_0_4MS 0x0000 -#define TJA1101_CONFIG2_SLEEP_REQUEST_TO_1MS 0x0001 -#define TJA1101_CONFIG2_SLEEP_REQUEST_TO_4MS 0x0002 -#define TJA1101_CONFIG2_SLEEP_REQUEST_TO_16MS 0x0003 +#define TJA1101_CONFIG2_PHYAD 0xF800 +#define TJA1101_CONFIG2_SQI_AVERAGING 0x0600 +#define TJA1101_CONFIG2_SQI_AVERAGING_32_SYMBOLS 0x0000 +#define TJA1101_CONFIG2_SQI_AVERAGING_64_SYMBOLS 0x0200 +#define TJA1101_CONFIG2_SQI_AVERAGING_128_SYMBOLS 0x0400 +#define TJA1101_CONFIG2_SQI_AVERAGING_256_SYMBOLS 0x0600 +#define TJA1101_CONFIG2_SQI_WLIMIT 0x01C0 +#define TJA1101_CONFIG2_SQI_WLIMIT_NONE 0x0000 +#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_A 0x0040 +#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_B 0x0080 +#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_C 0x00C0 +#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_D 0x0100 +#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_E 0x0140 +#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_F 0x0180 +#define TJA1101_CONFIG2_SQI_WLIMIT_CLASS_G 0x01C0 +#define TJA1101_CONFIG2_SQI_FAILLIMIT 0x0038 +#define TJA1101_CONFIG2_SQI_FAILLIMIT_NONE 0x0000 +#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_A 0x0008 +#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_B 0x0010 +#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_C 0x0018 +#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_D 0x0020 +#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_E 0x0028 +#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_F 0x0030 +#define TJA1101_CONFIG2_SQI_FAILLIMIT_CLASS_G 0x0038 +#define TJA1101_CONFIG2_JUMBO_ENABLE 0x0004 +#define TJA1101_CONFIG2_SLEEP_REQUEST_TO 0x0003 +#define TJA1101_CONFIG2_SLEEP_REQUEST_TO_0_4MS 0x0000 +#define TJA1101_CONFIG2_SLEEP_REQUEST_TO_1MS 0x0001 +#define TJA1101_CONFIG2_SLEEP_REQUEST_TO_4MS 0x0002 +#define TJA1101_CONFIG2_SLEEP_REQUEST_TO_16MS 0x0003 //Symbol error counter register -#define TJA1101_SYM_ERR_COUNTER_SYM_ERR_CNT 0xFFFF +#define TJA1101_SYM_ERR_COUNTER_SYM_ERR_CNT 0xFFFF //Interrupt source register -#define TJA1101_INT_SRC_PWON 0x8000 -#define TJA1101_INT_SRC_WAKEUP 0x4000 -#define TJA1101_INT_SRC_WUR_RECEIVED 0x2000 -#define TJA1101_INT_SRC_LPS_RECEIVED 0x1000 -#define TJA1101_INT_SRC_PHY_INIT_FAIL 0x0800 -#define TJA1101_INT_SRC_LINK_STATUS_FAIL 0x0400 -#define TJA1101_INT_SRC_LINK_STATUS_UP 0x0200 -#define TJA1101_INT_SRC_SYM_ERR 0x0100 -#define TJA1101_INT_SRC_TRAINING_FAILED 0x0080 -#define TJA1101_INT_SRC_SQI_WARNING 0x0040 -#define TJA1101_INT_SRC_CONTROL_ERR 0x0020 -#define TJA1101_INT_SRC_UV_ERR 0x0008 -#define TJA1101_INT_SRC_UV_RECOVERY 0x0004 -#define TJA1101_INT_SRC_TEMP_ERR 0x0002 -#define TJA1101_INT_SRC_SLEEP_ABORT 0x0001 +#define TJA1101_INT_SRC_PWON 0x8000 +#define TJA1101_INT_SRC_WAKEUP 0x4000 +#define TJA1101_INT_SRC_WUR_RECEIVED 0x2000 +#define TJA1101_INT_SRC_LPS_RECEIVED 0x1000 +#define TJA1101_INT_SRC_PHY_INIT_FAIL 0x0800 +#define TJA1101_INT_SRC_LINK_STATUS_FAIL 0x0400 +#define TJA1101_INT_SRC_LINK_STATUS_UP 0x0200 +#define TJA1101_INT_SRC_SYM_ERR 0x0100 +#define TJA1101_INT_SRC_TRAINING_FAILED 0x0080 +#define TJA1101_INT_SRC_SQI_WARNING 0x0040 +#define TJA1101_INT_SRC_CONTROL_ERR 0x0020 +#define TJA1101_INT_SRC_UV_ERR 0x0008 +#define TJA1101_INT_SRC_UV_RECOVERY 0x0004 +#define TJA1101_INT_SRC_TEMP_ERR 0x0002 +#define TJA1101_INT_SRC_SLEEP_ABORT 0x0001 //Interrupt enable register -#define TJA1101_INT_EN_PWON 0x8000 -#define TJA1101_INT_EN_WAKEUP 0x4000 -#define TJA1101_INT_EN_WUR_RECEIVED 0x2000 -#define TJA1101_INT_EN_LPS_RECEIVED 0x1000 -#define TJA1101_INT_EN_PHY_INIT_FAIL 0x0800 -#define TJA1101_INT_EN_LINK_STATUS_FAIL 0x0400 -#define TJA1101_INT_EN_LINK_STATUS_UP 0x0200 -#define TJA1101_INT_EN_SYM_ERR 0x0100 -#define TJA1101_INT_EN_TRAINING_FAILED 0x0080 -#define TJA1101_INT_EN_SQI_WARNING 0x0040 -#define TJA1101_INT_EN_CONTROL_ERR 0x0020 -#define TJA1101_INT_EN_TXEN_CLAMPED 0x0010 -#define TJA1101_INT_EN_UV_ERR 0x0008 -#define TJA1101_INT_EN_UV_RECOVERY 0x0004 -#define TJA1101_INT_EN_TEMP_ERR 0x0002 -#define TJA1101_INT_EN_SLEEP_ABORT 0x0001 +#define TJA1101_INT_EN_PWON 0x8000 +#define TJA1101_INT_EN_WAKEUP 0x4000 +#define TJA1101_INT_EN_WUR_RECEIVED 0x2000 +#define TJA1101_INT_EN_LPS_RECEIVED 0x1000 +#define TJA1101_INT_EN_PHY_INIT_FAIL 0x0800 +#define TJA1101_INT_EN_LINK_STATUS_FAIL 0x0400 +#define TJA1101_INT_EN_LINK_STATUS_UP 0x0200 +#define TJA1101_INT_EN_SYM_ERR 0x0100 +#define TJA1101_INT_EN_TRAINING_FAILED 0x0080 +#define TJA1101_INT_EN_SQI_WARNING 0x0040 +#define TJA1101_INT_EN_CONTROL_ERR 0x0020 +#define TJA1101_INT_EN_TXEN_CLAMPED 0x0010 +#define TJA1101_INT_EN_UV_ERR 0x0008 +#define TJA1101_INT_EN_UV_RECOVERY 0x0004 +#define TJA1101_INT_EN_TEMP_ERR 0x0002 +#define TJA1101_INT_EN_SLEEP_ABORT 0x0001 //Communication status register -#define TJA1101_COMM_STAT_LINK_UP 0x8000 -#define TJA1101_COMM_STAT_TX_MODE 0x6000 -#define TJA1101_COMM_STAT_TX_MODE_DISABLED 0x0000 -#define TJA1101_COMM_STAT_TX_MODE_SEND_N 0x2000 -#define TJA1101_COMM_STAT_TX_MODE_SEND_I 0x4000 -#define TJA1101_COMM_STAT_TX_MODE_SEND_Z 0x6000 -#define TJA1101_COMM_STAT_LOC_RCVR_STATUS 0x1000 -#define TJA1101_COMM_STAT_REM_RCVR_STATUS 0x0800 -#define TJA1101_COMM_STAT_SCR_LOCKED 0x0400 -#define TJA1101_COMM_STAT_SSD_ERR 0x0200 -#define TJA1101_COMM_STAT_ESD_ERR 0x0100 -#define TJA1101_COMM_STAT_SQI 0x00E0 -#define TJA1101_COMM_STAT_SQI_WORSE_THAN_CLASS_A 0x0000 -#define TJA1101_COMM_STAT_SQI_CLASS_A 0x0020 -#define TJA1101_COMM_STAT_SQI_CLASS_B 0x0040 -#define TJA1101_COMM_STAT_SQI_CLASS_C 0x0060 -#define TJA1101_COMM_STAT_SQI_CLASS_D 0x0080 -#define TJA1101_COMM_STAT_SQI_CLASS_E 0x00A0 -#define TJA1101_COMM_STAT_SQI_CLASS_F 0x00C0 -#define TJA1101_COMM_STAT_SQI_CLASS_G 0x00E0 -#define TJA1101_COMM_STAT_RECEIVE_ERR 0x0010 -#define TJA1101_COMM_STAT_TRANSMIT_ERR 0x0008 -#define TJA1101_COMM_STAT_PHY_STATE 0x0007 -#define TJA1101_COMM_STAT_PHY_STATE_IDLE 0x0000 -#define TJA1101_COMM_STAT_PHY_STATE_INITIALIZING 0x0001 -#define TJA1101_COMM_STAT_PHY_STATE_CONFIGURED 0x0002 -#define TJA1101_COMM_STAT_PHY_STATE_OFFLINE 0x0003 -#define TJA1101_COMM_STAT_PHY_STATE_ACTIVE 0x0004 -#define TJA1101_COMM_STAT_PHY_STATE_ISOLATE 0x0005 -#define TJA1101_COMM_STAT_PHY_STATE_CABLE_TEST 0x0006 -#define TJA1101_COMM_STAT_PHY_STATE_TEST_MODE 0x0007 +#define TJA1101_COMM_STAT_LINK_UP 0x8000 +#define TJA1101_COMM_STAT_TX_MODE 0x6000 +#define TJA1101_COMM_STAT_TX_MODE_DISABLED 0x0000 +#define TJA1101_COMM_STAT_TX_MODE_SEND_N 0x2000 +#define TJA1101_COMM_STAT_TX_MODE_SEND_I 0x4000 +#define TJA1101_COMM_STAT_TX_MODE_SEND_Z 0x6000 +#define TJA1101_COMM_STAT_LOC_RCVR_STATUS 0x1000 +#define TJA1101_COMM_STAT_REM_RCVR_STATUS 0x0800 +#define TJA1101_COMM_STAT_SCR_LOCKED 0x0400 +#define TJA1101_COMM_STAT_SSD_ERR 0x0200 +#define TJA1101_COMM_STAT_ESD_ERR 0x0100 +#define TJA1101_COMM_STAT_SQI 0x00E0 +#define TJA1101_COMM_STAT_SQI_WORSE_THAN_CLASS_A 0x0000 +#define TJA1101_COMM_STAT_SQI_CLASS_A 0x0020 +#define TJA1101_COMM_STAT_SQI_CLASS_B 0x0040 +#define TJA1101_COMM_STAT_SQI_CLASS_C 0x0060 +#define TJA1101_COMM_STAT_SQI_CLASS_D 0x0080 +#define TJA1101_COMM_STAT_SQI_CLASS_E 0x00A0 +#define TJA1101_COMM_STAT_SQI_CLASS_F 0x00C0 +#define TJA1101_COMM_STAT_SQI_CLASS_G 0x00E0 +#define TJA1101_COMM_STAT_RECEIVE_ERR 0x0010 +#define TJA1101_COMM_STAT_TRANSMIT_ERR 0x0008 +#define TJA1101_COMM_STAT_PHY_STATE 0x0007 +#define TJA1101_COMM_STAT_PHY_STATE_IDLE 0x0000 +#define TJA1101_COMM_STAT_PHY_STATE_INITIALIZING 0x0001 +#define TJA1101_COMM_STAT_PHY_STATE_CONFIGURED 0x0002 +#define TJA1101_COMM_STAT_PHY_STATE_OFFLINE 0x0003 +#define TJA1101_COMM_STAT_PHY_STATE_ACTIVE 0x0004 +#define TJA1101_COMM_STAT_PHY_STATE_ISOLATE 0x0005 +#define TJA1101_COMM_STAT_PHY_STATE_CABLE_TEST 0x0006 +#define TJA1101_COMM_STAT_PHY_STATE_TEST_MODE 0x0007 //General status register -#define TJA1101_GENERAL_STAT_INT_STATUS 0x8000 -#define TJA1101_GENERAL_STAT_PLL_LOCKED 0x4000 -#define TJA1101_GENERAL_STAT_LOCAL_WU 0x2000 -#define TJA1101_GENERAL_STAT_REMOTE_WU 0x1000 -#define TJA1101_GENERAL_STAT_DATA_DET_WU 0x0800 -#define TJA1101_GENERAL_STAT_EN_STATUS 0x0400 -#define TJA1101_GENERAL_STAT_RESET_STATUS 0x0200 -#define TJA1101_GENERAL_STAT_LINKFAIL_CNT 0x00F8 +#define TJA1101_GENERAL_STAT_INT_STATUS 0x8000 +#define TJA1101_GENERAL_STAT_PLL_LOCKED 0x4000 +#define TJA1101_GENERAL_STAT_LOCAL_WU 0x2000 +#define TJA1101_GENERAL_STAT_REMOTE_WU 0x1000 +#define TJA1101_GENERAL_STAT_DATA_DET_WU 0x0800 +#define TJA1101_GENERAL_STAT_EN_STATUS 0x0400 +#define TJA1101_GENERAL_STAT_RESET_STATUS 0x0200 +#define TJA1101_GENERAL_STAT_LINKFAIL_CNT 0x00F8 //External status register -#define TJA1101_EXTERNAL_STAT_UV_VDDA_3V3 0x4000 -#define TJA1101_EXTERNAL_STAT_UV_VDDD_1V8 0x2000 -#define TJA1101_EXTERNAL_STAT_UV_VDDA_1V8 0x1000 -#define TJA1101_EXTERNAL_STAT_UV_VDDIO 0x0800 -#define TJA1101_EXTERNAL_STAT_TEMP_HIGH 0x0400 -#define TJA1101_EXTERNAL_STAT_TEMP_WARN 0x0200 -#define TJA1101_EXTERNAL_STAT_SHORT_DETECT 0x0100 -#define TJA1101_EXTERNAL_STAT_OPEN_DETECT 0x0080 -#define TJA1101_EXTERNAL_STAT_POLARITY_DETECT 0x0040 -#define TJA1101_EXTERNAL_STAT_INTERLEAVE_DETECT 0x0020 +#define TJA1101_EXTERNAL_STAT_UV_VDDA_3V3 0x8000 +#define TJA1101_EXTERNAL_STAT_UV_VDDD_1V8 0x4000 +#define TJA1101_EXTERNAL_STAT_UV_VDDA_1V8 0x2000 +#define TJA1101_EXTERNAL_STAT_UV_VDDIO 0x0800 +#define TJA1101_EXTERNAL_STAT_TEMP_HIGH 0x0400 +#define TJA1101_EXTERNAL_STAT_TEMP_WARN 0x0200 +#define TJA1101_EXTERNAL_STAT_SHORT_DETECT 0x0100 +#define TJA1101_EXTERNAL_STAT_OPEN_DETECT 0x0080 +#define TJA1101_EXTERNAL_STAT_POLARITY_DETECT 0x0040 +#define TJA1101_EXTERNAL_STAT_INTERLEAVE_DETECT 0x0020 //Link-fail counter register -#define TJA1101_LINK_FAIL_COUNTER_LOC_RCVR_CNT 0xFF00 -#define TJA1101_LINK_FAIL_COUNTER_REM_RCVR_CNT 0x00FF +#define TJA1101_LINK_FAIL_COUNTER_LOC_RCVR_CNT 0xFF00 +#define TJA1101_LINK_FAIL_COUNTER_REM_RCVR_CNT 0x00FF //Common configuration register -#define TJA1101_COMM_CTRL_AUTO_OP 0x8000 +#define TJA1101_COMM_CTRL_AUTO_OP 0x8000 +#define TJA1101_COMM_CTRL_CLK_MODE 0x3000 +#define TJA1101_COMM_CTRL_CLK_MODE_25MHZ_XTAL_NO_CLK_OUT 0x0000 +#define TJA1101_COMM_CTRL_CLK_MODE_25MHZ_XTAL_CLK_OUT 0x1000 +#define TJA1101_COMM_CTRL_CLK_MODE_25MHZ_EXT_CLK_IN 0x2000 +#define TJA1101_COMM_CTRL_CLK_MODE_50MHZ_REF_CLK_IN 0x3000 +#define TJA1101_COMM_CTRL_LDO_MODE 0x0800 +#define TJA1101_COMM_CTRL_CLK_DRIVER 0x0400 +#define TJA1101_COMM_CTRL_CLK_HOLD 0x0200 +#define TJA1101_COMM_CTRL_LOC_WU_TIM 0x0180 +#define TJA1101_COMM_CTRL_LOC_WU_TIM_LONGEST 0x0000 +#define TJA1101_COMM_CTRL_LOC_WU_TIM_LONG 0x0080 +#define TJA1101_COMM_CTRL_LOC_WU_TIM_SHORT 0x0100 +#define TJA1101_COMM_CTRL_LOC_WU_TIM_SHORTEST 0x0180 +#define TJA1101_COMM_CTRL_CONFIG_WAKE 0x0040 +#define TJA1101_COMM_CTRL_CONFIG_INH 0x0020 //Configuration 3 register -#define TJA1101_CONFIG3_SHORT_DETECT 0x0100 -#define TJA1101_CONFIG3_OPEN_DETECT 0x0080 +#define TJA1101_CONFIG3_FORCE_SLEEP 0x0002 //C++ guard #ifdef __cplusplus diff --git a/drivers/phy/upd60611_driver.c b/drivers/phy/upd60611_driver.c index 2a5dbd2b..7a4c1b7b 100644 --- a/drivers/phy/upd60611_driver.c +++ b/drivers/phy/upd60611_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/phy/upd60611_driver.h b/drivers/phy/upd60611_driver.h index 38991626..dea8f30e 100644 --- a/drivers/phy/upd60611_driver.h +++ b/drivers/phy/upd60611_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _UPD60611_DRIVER_H diff --git a/drivers/switch/ksz8463_driver.c b/drivers/switch/ksz8463_driver.c index 5468c2e4..6b57bd98 100644 --- a/drivers/switch/ksz8463_driver.c +++ b/drivers/switch/ksz8463_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -611,7 +611,6 @@ NicDuplexMode ksz8463GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz8463SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz8463_driver.h b/drivers/switch/ksz8463_driver.h index 7277ecea..a617402a 100644 --- a/drivers/switch/ksz8463_driver.h +++ b/drivers/switch/ksz8463_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8463_DRIVER_H diff --git a/drivers/switch/ksz8563_driver.c b/drivers/switch/ksz8563_driver.c index 50d6aef4..033c678f 100644 --- a/drivers/switch/ksz8563_driver.c +++ b/drivers/switch/ksz8563_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -731,7 +731,6 @@ NicDuplexMode ksz8563GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz8563SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz8563_driver.h b/drivers/switch/ksz8563_driver.h index f0fb3c31..183aebf7 100644 --- a/drivers/switch/ksz8563_driver.h +++ b/drivers/switch/ksz8563_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8563_DRIVER_H diff --git a/drivers/switch/ksz8775_driver.c b/drivers/switch/ksz8775_driver.c index 35d4bbd7..a3ca6d48 100644 --- a/drivers/switch/ksz8775_driver.c +++ b/drivers/switch/ksz8775_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -741,7 +741,6 @@ NicDuplexMode ksz8775GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz8775SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz8775_driver.h b/drivers/switch/ksz8775_driver.h index 7158936f..4c774d17 100644 --- a/drivers/switch/ksz8775_driver.h +++ b/drivers/switch/ksz8775_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8775_DRIVER_H diff --git a/drivers/switch/ksz8794_driver.c b/drivers/switch/ksz8794_driver.c index e93343ca..532eaeab 100644 --- a/drivers/switch/ksz8794_driver.c +++ b/drivers/switch/ksz8794_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -705,7 +705,6 @@ NicDuplexMode ksz8794GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz8794SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz8794_driver.h b/drivers/switch/ksz8794_driver.h index d02bb7c1..07f2304d 100644 --- a/drivers/switch/ksz8794_driver.h +++ b/drivers/switch/ksz8794_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8794_DRIVER_H diff --git a/drivers/switch/ksz8795_driver.c b/drivers/switch/ksz8795_driver.c index bd767c44..d6cfb2a8 100644 --- a/drivers/switch/ksz8795_driver.c +++ b/drivers/switch/ksz8795_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -707,7 +707,6 @@ NicDuplexMode ksz8795GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz8795SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz8795_driver.h b/drivers/switch/ksz8795_driver.h index 949c333c..a1c538ae 100644 --- a/drivers/switch/ksz8795_driver.h +++ b/drivers/switch/ksz8795_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8795_DRIVER_H diff --git a/drivers/switch/ksz8863_driver.c b/drivers/switch/ksz8863_driver.c index b1674130..82d25dcd 100644 --- a/drivers/switch/ksz8863_driver.c +++ b/drivers/switch/ksz8863_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -598,7 +598,6 @@ NicDuplexMode ksz8863GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz8863SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz8863_driver.h b/drivers/switch/ksz8863_driver.h index 3437e491..9c803926 100644 --- a/drivers/switch/ksz8863_driver.h +++ b/drivers/switch/ksz8863_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8863_DRIVER_H diff --git a/drivers/switch/ksz8864_driver.c b/drivers/switch/ksz8864_driver.c index 4391e3a2..a7f3c855 100644 --- a/drivers/switch/ksz8864_driver.c +++ b/drivers/switch/ksz8864_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -636,7 +636,6 @@ NicDuplexMode ksz8864GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz8864SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz8864_driver.h b/drivers/switch/ksz8864_driver.h index acb8c879..c6ccef96 100644 --- a/drivers/switch/ksz8864_driver.h +++ b/drivers/switch/ksz8864_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8864_DRIVER_H diff --git a/drivers/switch/ksz8873_driver.c b/drivers/switch/ksz8873_driver.c index 001cdc59..e0d4451d 100644 --- a/drivers/switch/ksz8873_driver.c +++ b/drivers/switch/ksz8873_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -598,7 +598,6 @@ NicDuplexMode ksz8873GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz8873SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz8873_driver.h b/drivers/switch/ksz8873_driver.h index a776357e..1841dc6f 100644 --- a/drivers/switch/ksz8873_driver.h +++ b/drivers/switch/ksz8873_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8873_DRIVER_H diff --git a/drivers/switch/ksz8895_driver.c b/drivers/switch/ksz8895_driver.c index fd3202e8..cb08b1c7 100644 --- a/drivers/switch/ksz8895_driver.c +++ b/drivers/switch/ksz8895_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -597,7 +597,6 @@ NicDuplexMode ksz8895GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz8895SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz8895_driver.h b/drivers/switch/ksz8895_driver.h index f2fdf8c5..d16645b6 100644 --- a/drivers/switch/ksz8895_driver.h +++ b/drivers/switch/ksz8895_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ8895_DRIVER_H diff --git a/drivers/switch/ksz9477_driver.c b/drivers/switch/ksz9477_driver.c index 39083f6c..3a5b912e 100644 --- a/drivers/switch/ksz9477_driver.c +++ b/drivers/switch/ksz9477_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -726,7 +726,6 @@ NicDuplexMode ksz9477GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz9477SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz9477_driver.h b/drivers/switch/ksz9477_driver.h index 246c3721..0ff78ec6 100644 --- a/drivers/switch/ksz9477_driver.h +++ b/drivers/switch/ksz9477_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ9477_DRIVER_H diff --git a/drivers/switch/ksz9563_driver.c b/drivers/switch/ksz9563_driver.c index ba5af8ee..a52af399 100644 --- a/drivers/switch/ksz9563_driver.c +++ b/drivers/switch/ksz9563_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -736,7 +736,6 @@ NicDuplexMode ksz9563GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz9563SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz9563_driver.h b/drivers/switch/ksz9563_driver.h index e1b23a91..ed900f6f 100644 --- a/drivers/switch/ksz9563_driver.h +++ b/drivers/switch/ksz9563_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ9563_DRIVER_H diff --git a/drivers/switch/ksz9893_driver.c b/drivers/switch/ksz9893_driver.c index 1d4a2def..e82b326f 100644 --- a/drivers/switch/ksz9893_driver.c +++ b/drivers/switch/ksz9893_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -736,7 +736,6 @@ NicDuplexMode ksz9893GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz9893SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz9893_driver.h b/drivers/switch/ksz9893_driver.h index 1147497d..35841936 100644 --- a/drivers/switch/ksz9893_driver.h +++ b/drivers/switch/ksz9893_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ9893_DRIVER_H diff --git a/drivers/switch/ksz9897_driver.c b/drivers/switch/ksz9897_driver.c index 0a9d0b3e..621f9345 100644 --- a/drivers/switch/ksz9897_driver.c +++ b/drivers/switch/ksz9897_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -726,7 +726,6 @@ NicDuplexMode ksz9897GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void ksz9897SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/ksz9897_driver.h b/drivers/switch/ksz9897_driver.h index e0223d95..abb6cb4e 100644 --- a/drivers/switch/ksz9897_driver.h +++ b/drivers/switch/ksz9897_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _KSZ9897_DRIVER_H diff --git a/drivers/switch/lan9303_driver.c b/drivers/switch/lan9303_driver.c index 96fd05ac..c1d3758e 100644 --- a/drivers/switch/lan9303_driver.c +++ b/drivers/switch/lan9303_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -700,7 +700,6 @@ NicDuplexMode lan9303GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void lan9303SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/lan9303_driver.h b/drivers/switch/lan9303_driver.h index 3294cc93..48ba9ad3 100644 --- a/drivers/switch/lan9303_driver.h +++ b/drivers/switch/lan9303_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LAN9303_DRIVER_H diff --git a/drivers/switch/mv88e6060_driver.c b/drivers/switch/mv88e6060_driver.c index e0d6fee0..f0064add 100644 --- a/drivers/switch/mv88e6060_driver.c +++ b/drivers/switch/mv88e6060_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -613,7 +613,6 @@ NicDuplexMode mv88e6060GetDuplexMode(NetInterface *interface, uint8_t port) * @param[in] interface Underlying network interface * @param[in] port Port number * @param[in] state Port state - * @return Duplex mode **/ void mv88e6060SetPortState(NetInterface *interface, uint8_t port, diff --git a/drivers/switch/mv88e6060_driver.h b/drivers/switch/mv88e6060_driver.h index 1fffd751..13210410 100644 --- a/drivers/switch/mv88e6060_driver.h +++ b/drivers/switch/mv88e6060_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MV88E6060_DRIVER_H diff --git a/drivers/usb_rndis/rndis.c b/drivers/usb_rndis/rndis.c index e94b317e..c2573e5c 100644 --- a/drivers/usb_rndis/rndis.c +++ b/drivers/usb_rndis/rndis.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/usb_rndis/rndis.h b/drivers/usb_rndis/rndis.h index e401caf3..137951b0 100644 --- a/drivers/usb_rndis/rndis.h +++ b/drivers/usb_rndis/rndis.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _RNDIS_H diff --git a/drivers/usb_rndis/rndis_debug.c b/drivers/usb_rndis/rndis_debug.c index 9ba03ffa..05da01db 100644 --- a/drivers/usb_rndis/rndis_debug.c +++ b/drivers/usb_rndis/rndis_debug.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/usb_rndis/rndis_debug.h b/drivers/usb_rndis/rndis_debug.h index 2d57cfec..fefa450e 100644 --- a/drivers/usb_rndis/rndis_debug.h +++ b/drivers/usb_rndis/rndis_debug.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _RNDIS_DEBUG_H diff --git a/drivers/usb_rndis/rndis_driver.c b/drivers/usb_rndis/rndis_driver.c index 411bd5e5..63655176 100644 --- a/drivers/usb_rndis/rndis_driver.c +++ b/drivers/usb_rndis/rndis_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/usb_rndis/rndis_driver.h b/drivers/usb_rndis/rndis_driver.h index 65aa9b52..a1fd766a 100644 --- a/drivers/usb_rndis/rndis_driver.h +++ b/drivers/usb_rndis/rndis_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _RNDIS_DRIVER_H @@ -37,7 +37,7 @@ //Number of TX buffers #ifndef RNDIS_TX_BUFFER_COUNT #define RNDIS_TX_BUFFER_COUNT 2 -#elif (RNDIS_TX_BUFFER_COUNT != 1) +#elif (RNDIS_TX_BUFFER_COUNT < 1) #error RNDIS_TX_BUFFER_COUNT parameter is not valid #endif diff --git a/drivers/usb_rndis/usbd_desc.c b/drivers/usb_rndis/usbd_desc.c index 789323a4..9ccb253b 100644 --- a/drivers/usb_rndis/usbd_desc.c +++ b/drivers/usb_rndis/usbd_desc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Dependencies diff --git a/drivers/usb_rndis/usbd_desc.h b/drivers/usb_rndis/usbd_desc.h index 712e91e4..a6dfd725 100644 --- a/drivers/usb_rndis/usbd_desc.h +++ b/drivers/usb_rndis/usbd_desc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _USBD_DESC_H diff --git a/drivers/usb_rndis/usbd_rndis.c b/drivers/usb_rndis/usbd_rndis.c index fa3a27fc..03b8bf87 100644 --- a/drivers/usb_rndis/usbd_rndis.c +++ b/drivers/usb_rndis/usbd_rndis.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/usb_rndis/usbd_rndis.h b/drivers/usb_rndis/usbd_rndis.h index 8a7b798f..fb486aa7 100644 --- a/drivers/usb_rndis/usbd_rndis.h +++ b/drivers/usb_rndis/usbd_rndis.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _USB_RNDIS_H diff --git a/drivers/wifi/bcm43362_driver.c b/drivers/wifi/bcm43362_driver.c index 9c33545b..3ae1d641 100644 --- a/drivers/wifi/bcm43362_driver.c +++ b/drivers/wifi/bcm43362_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/wifi/bcm43362_driver.h b/drivers/wifi/bcm43362_driver.h index 8d1fed62..42cdc6db 100644 --- a/drivers/wifi/bcm43362_driver.h +++ b/drivers/wifi/bcm43362_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _BCM43362_DRIVER_H diff --git a/drivers/wifi/esp32_wifi_driver.c b/drivers/wifi/esp32_wifi_driver.c index 72c13f4b..4dc5c6ad 100644 --- a/drivers/wifi/esp32_wifi_driver.c +++ b/drivers/wifi/esp32_wifi_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/wifi/esp32_wifi_driver.h b/drivers/wifi/esp32_wifi_driver.h index 24205d36..8a04ff82 100644 --- a/drivers/wifi/esp32_wifi_driver.h +++ b/drivers/wifi/esp32_wifi_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ESP32_WIFI_DRIVER_H diff --git a/drivers/wifi/esp8266_driver.c b/drivers/wifi/esp8266_driver.c index ed09aefb..120660e4 100644 --- a/drivers/wifi/esp8266_driver.c +++ b/drivers/wifi/esp8266_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/wifi/esp8266_driver.h b/drivers/wifi/esp8266_driver.h index d70395c1..0f995ecc 100644 --- a/drivers/wifi/esp8266_driver.h +++ b/drivers/wifi/esp8266_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ESP8266_WIFI_DRIVER_H diff --git a/drivers/wifi/mrf24wg_driver.c b/drivers/wifi/mrf24wg_driver.c index ebf4bc5d..347de97f 100644 --- a/drivers/wifi/mrf24wg_driver.c +++ b/drivers/wifi/mrf24wg_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/wifi/mrf24wg_driver.h b/drivers/wifi/mrf24wg_driver.h index e74f7908..7d44d081 100644 --- a/drivers/wifi/mrf24wg_driver.h +++ b/drivers/wifi/mrf24wg_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MRF24WG_DRIVER_H diff --git a/drivers/wifi/wf200_driver.c b/drivers/wifi/wf200_driver.c index 3769be4c..5ff5dcc0 100644 --- a/drivers/wifi/wf200_driver.c +++ b/drivers/wifi/wf200_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/wifi/wf200_driver.h b/drivers/wifi/wf200_driver.h index d79f1b0c..ff966f19 100644 --- a/drivers/wifi/wf200_driver.h +++ b/drivers/wifi/wf200_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _WF200_DRIVER_H diff --git a/drivers/wifi/wilc1000_driver.c b/drivers/wifi/wilc1000_driver.c index 51813a46..36649577 100644 --- a/drivers/wifi/wilc1000_driver.c +++ b/drivers/wifi/wilc1000_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/wifi/wilc1000_driver.h b/drivers/wifi/wilc1000_driver.h index 38ce85ff..d83625da 100644 --- a/drivers/wifi/wilc1000_driver.h +++ b/drivers/wifi/wilc1000_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _WILC1000_DRIVER_H diff --git a/drivers/wifi/winc1500_driver.c b/drivers/wifi/winc1500_driver.c index 63b84516..457563b8 100644 --- a/drivers/wifi/winc1500_driver.c +++ b/drivers/wifi/winc1500_driver.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/drivers/wifi/winc1500_driver.h b/drivers/wifi/winc1500_driver.h index 33405682..4b8320b7 100644 --- a/drivers/wifi/winc1500_driver.h +++ b/drivers/wifi/winc1500_driver.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _WINC1500_DRIVER_H diff --git a/ftp/ftp_client.c b/ftp/ftp_client.c index 12566be2..14494ff1 100644 --- a/ftp/ftp_client.c +++ b/ftp/ftp_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 2428: FTP Extensions for IPv6 and NATs * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -834,9 +834,13 @@ error_t ftpClientOpenDir(FtpClientContext *context, const char_t *path) { //Format LIST command if(!osStrcmp(path, ".")) + { ftpClientFormatCommand(context, "LIST", NULL); + } else + { ftpClientFormatCommand(context, "LIST", path); + } //Check status code if(!error) diff --git a/ftp/ftp_client.h b/ftp/ftp_client.h index 081700f9..559af6c6 100644 --- a/ftp/ftp_client.h +++ b/ftp/ftp_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _FTP_CLIENT_H diff --git a/ftp/ftp_client_misc.c b/ftp/ftp_client_misc.c index acffec46..7eb63754 100644 --- a/ftp/ftp_client_misc.c +++ b/ftp/ftp_client_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -452,7 +452,7 @@ error_t ftpClientParsePwdReply(FtpClientContext *context, char_t *path, *p = '\0'; //Search for the first double quote - p = strchr(context->buffer, '\"'); + p = osStrchr(context->buffer, '\"'); //Failed to parse the response? if(p == NULL) return ERROR_INVALID_SYNTAX; @@ -548,8 +548,10 @@ error_t ftpClientParseDirEntry(char_t *line, FtpDirEntry *dirEntry) dirEntry->modified.minutes = (uint8_t) osStrtoul(token + 3, NULL, 10); //The PM period covers the 12 hours from noon to midnight - if(strstr(token, "PM") != NULL) + if(osStrstr(token, "PM") != NULL) + { dirEntry->modified.hours += 12; + } } else { @@ -595,10 +597,15 @@ error_t ftpClientParseDirEntry(char_t *line, FtpDirEntry *dirEntry) else { //Check file permissions - if(strchr(token, 'd') != NULL) + if(osStrchr(token, 'd') != NULL) + { dirEntry->attributes |= FTP_FILE_ATTR_DIRECTORY; - if(strchr(token, 'w') == NULL) + } + + if(osStrchr(token, 'w') == NULL) + { dirEntry->attributes |= FTP_FILE_ATTR_READ_ONLY; + } //Read next field token = osStrtok_r(NULL, " ", &p); diff --git a/ftp/ftp_client_misc.h b/ftp/ftp_client_misc.h index 50a237f5..0d892970 100644 --- a/ftp/ftp_client_misc.h +++ b/ftp/ftp_client_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _FTP_CLIENT_MISC_H diff --git a/ftp/ftp_client_transport.c b/ftp/ftp_client_transport.c index 8aa07742..9b5ba881 100644 --- a/ftp/ftp_client_transport.c +++ b/ftp/ftp_client_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ftp/ftp_client_transport.h b/ftp/ftp_client_transport.h index f6a13322..83d3bc19 100644 --- a/ftp/ftp_client_transport.h +++ b/ftp/ftp_client_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _FTP_CLIENT_TRANSPORT_H diff --git a/ftp/ftp_server.c b/ftp/ftp_server.c index fd4d4ccc..f5e2d419 100644 --- a/ftp/ftp_server.c +++ b/ftp/ftp_server.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -34,7 +34,7 @@ * - RFC 2428: FTP Extensions for IPv6 and NATs * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ftp/ftp_server.h b/ftp/ftp_server.h index 086514a3..7b33df14 100644 --- a/ftp/ftp_server.h +++ b/ftp/ftp_server.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _FTP_SERVER_H diff --git a/ftp/ftp_server_commands.c b/ftp/ftp_server_commands.c index f40ecb2a..19247973 100644 --- a/ftp/ftp_server_commands.c +++ b/ftp/ftp_server_commands.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -1670,10 +1670,15 @@ void ftpServerProcessList(FtpClientConnection *connection, char_t *param) { //Skip option flags while(*param != ' ' && *param != '\0') + { param++; + } + //Skip whitespace characters while(*param == ' ') + { param++; + } } //The pathname is optional diff --git a/ftp/ftp_server_commands.h b/ftp/ftp_server_commands.h index e87195ee..fce5dabc 100644 --- a/ftp/ftp_server_commands.h +++ b/ftp/ftp_server_commands.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _FTP_SERVER_COMMANDS_H diff --git a/ftp/ftp_server_control.c b/ftp/ftp_server_control.c index da88d119..99f96e77 100644 --- a/ftp/ftp_server_control.c +++ b/ftp/ftp_server_control.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ftp/ftp_server_control.h b/ftp/ftp_server_control.h index 576cf958..2a7bc1e5 100644 --- a/ftp/ftp_server_control.h +++ b/ftp/ftp_server_control.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _FTP_SERVER_CONTROL_H diff --git a/ftp/ftp_server_data.c b/ftp/ftp_server_data.c index 81b77d7e..21cf7f88 100644 --- a/ftp/ftp_server_data.c +++ b/ftp/ftp_server_data.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ftp/ftp_server_data.h b/ftp/ftp_server_data.h index 5bc1c102..6d067cb3 100644 --- a/ftp/ftp_server_data.h +++ b/ftp/ftp_server_data.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _FTP_SERVER_DATA_H diff --git a/ftp/ftp_server_misc.c b/ftp/ftp_server_misc.c index bcaaa4f2..ce9fbac2 100644 --- a/ftp/ftp_server_misc.c +++ b/ftp/ftp_server_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ftp/ftp_server_misc.h b/ftp/ftp_server_misc.h index 7eb23800..f773cdfe 100644 --- a/ftp/ftp_server_misc.h +++ b/ftp/ftp_server_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _FTP_SERVER_MISC_H diff --git a/ftp/ftp_server_transport.c b/ftp/ftp_server_transport.c index 243a2990..8a08657b 100644 --- a/ftp/ftp_server_transport.c +++ b/ftp/ftp_server_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ftp/ftp_server_transport.h b/ftp/ftp_server_transport.h index 68e41079..b2b2f579 100644 --- a/ftp/ftp_server_transport.h +++ b/ftp/ftp_server_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _FTP_SERVER_TRANSPORT_H diff --git a/http/http_client.c b/http/http_client.c index f3a89199..aa4a3c26 100644 --- a/http/http_client.c +++ b/http/http_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -36,7 +36,7 @@ * - RFC 7231: Hypertext Transfer Protocol (HTTP/1.1): Semantics and Content * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -425,7 +425,7 @@ error_t httpClientSetMethod(HttpClientContext *context, const char_t *method) context->buffer[context->bufferLen] = '\0'; //The Request-Line begins with a method token - p = strchr(context->buffer, ' '); + p = osStrchr(context->buffer, ' '); //Any parsing error? if(p == NULL) return ERROR_INVALID_SYNTAX; @@ -487,7 +487,7 @@ error_t httpClientSetUri(HttpClientContext *context, const char_t *uri) context->buffer[context->bufferLen] = '\0'; //The Request-Line begins with a method token - p = strchr(context->buffer, ' '); + p = osStrchr(context->buffer, ' '); //Any parsing error? if(p == NULL) return ERROR_INVALID_SYNTAX; @@ -616,7 +616,7 @@ error_t httpClientSetQueryString(HttpClientContext *context, context->buffer[context->bufferLen] = '\0'; //The Request-Line begins with a method token - p = strchr(context->buffer, ' '); + p = osStrchr(context->buffer, ' '); //Any parsing error? if(p == NULL) return ERROR_INVALID_SYNTAX; @@ -631,7 +631,7 @@ error_t httpClientSetQueryString(HttpClientContext *context, if(*p == '?') { //Point to the end of the query string - q = strchr(p + 1, ' '); + q = osStrchr(p + 1, ' '); //Any parsing error? if(q == NULL) return ERROR_INVALID_SYNTAX; @@ -717,7 +717,7 @@ error_t httpClientAddQueryParam(HttpClientContext *context, context->buffer[context->bufferLen] = '\0'; //The Request-Line begins with a method token - p = strchr(context->buffer, ' '); + p = osStrchr(context->buffer, ' '); //Any parsing error? if(p == NULL) return ERROR_INVALID_SYNTAX; @@ -732,7 +732,7 @@ error_t httpClientAddQueryParam(HttpClientContext *context, if(*p == '?') { //Point to the end of the query string - p = strchr(p + 1, ' '); + p = osStrchr(p + 1, ' '); //Any parsing error? if(p == NULL) return ERROR_INVALID_SYNTAX; diff --git a/http/http_client.h b/http/http_client.h index b3984595..bc3d55a9 100644 --- a/http/http_client.h +++ b/http/http_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _HTTP_CLIENT_H diff --git a/http/http_client_auth.c b/http/http_client_auth.c index 975e7ccf..a7837584 100644 --- a/http/http_client_auth.c +++ b/http/http_client_auth.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -40,7 +40,7 @@ * - RFC 7617: The Basic HTTP Authentication Scheme * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -164,7 +164,7 @@ error_t httpClientFormatAuthorizationField(HttpClientContext *context) context->buffer[context->bufferLen] = '\0'; //The Request-Line begins with a method token - q = strchr(context->buffer, ' '); + q = osStrchr(context->buffer, ' '); //Any parsing error? if(q == NULL) return ERROR_INVALID_SYNTAX; @@ -173,7 +173,7 @@ error_t httpClientFormatAuthorizationField(HttpClientContext *context) uri = q + 1; //Point to the end of the Request-URI - q = strchr(uri, ' '); + q = osStrchr(uri, ' '); //Any parsing error? if(q == NULL) return ERROR_INVALID_SYNTAX; @@ -504,8 +504,10 @@ void httpClientParseQopParam(const HttpParam *param, for(n = 0; (i + n) < param->valueLen; n++) { //Separator character found? - if(strchr(", \t", param->value[i + n])) + if(osStrchr(", \t", param->value[i + n]) != NULL) + { break; + } } //Check current token diff --git a/http/http_client_auth.h b/http/http_client_auth.h index 049926d1..42d48e46 100644 --- a/http/http_client_auth.h +++ b/http/http_client_auth.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _HTTP_CLIENT_AUTH_H diff --git a/http/http_client_misc.c b/http/http_client_misc.c index b3bcd55b..1721fbd5 100644 --- a/http/http_client_misc.c +++ b/http/http_client_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -347,7 +347,7 @@ error_t httpClientParseHeaderField(HttpClientContext *context, char_t *line, //Each header field consists of a case-insensitive field name followed //by a colon, optional leading whitespace, the field value, and optional //trailing whitespace (refer to RFC 7230, section 3.2) - separator = strchr(line, ':'); + separator = osStrchr(line, ':'); //Any parsing error? if(separator == NULL) diff --git a/http/http_client_misc.h b/http/http_client_misc.h index 1ca8ba1a..2d8015e6 100644 --- a/http/http_client_misc.h +++ b/http/http_client_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _HTTP_CLIENT_MISC_H diff --git a/http/http_client_transport.c b/http/http_client_transport.c index 46257bb0..4bbef81a 100644 --- a/http/http_client_transport.c +++ b/http/http_client_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/http/http_client_transport.h b/http/http_client_transport.h index 5096ea7c..e12caa61 100644 --- a/http/http_client_transport.h +++ b/http/http_client_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _HTTP_CLIENT_TRANSPORT_H diff --git a/http/http_common.c b/http/http_common.c index 0cbcb32d..fe7bd4ab 100644 --- a/http/http_common.c +++ b/http/http_common.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -94,7 +94,7 @@ error_t httpCheckCharset(const char_t *s, size_t length, uint_t charset) m |= HTTP_CHARSET_TEXT | HTTP_CHARSET_OBS_TEXT; //Check if character is a token character - if(strchr("!#$%&'*+-.^_`|~", c)) + if(osStrchr("!#$%&'*+-.^_`|~", c)) m |= HTTP_CHARSET_TCHAR; //Invalid character? @@ -163,7 +163,7 @@ error_t httpParseParam(const char_t **pos, HttpParam *param) { //Discard whitespace and separator characters } - else if(isalnum(c) || strchr("!#$%&'*+-.^_`|~", c) || c >= 128) + else if(isalnum(c) || osStrchr("!#$%&'*+-.^_`|~", c) || c >= 128) { //Point to the first character of the parameter name param->name = p + i; @@ -196,7 +196,7 @@ error_t httpParseParam(const char_t **pos, HttpParam *param) //Save the length of the parameter name param->nameLen = p + i - param->name; } - else if(isalnum(c) || strchr("!#$%&'*+-.^_`|~", c) || c >= 128) + else if(isalnum(c) || osStrchr("!#$%&'*+-.^_`|~", c) || c >= 128) { //Advance data pointer } @@ -230,7 +230,7 @@ error_t httpParseParam(const char_t **pos, HttpParam *param) //Successful processing error = NO_ERROR; } - else if(isalnum(c) || strchr("!#$%&'*+-.^_`|~", c) || c >= 128) + else if(isalnum(c) || osStrchr("!#$%&'*+-.^_`|~", c) || c >= 128) { //Point to the first character that follows the parameter name i = param->name + param->nameLen - p; @@ -261,7 +261,7 @@ error_t httpParseParam(const char_t **pos, HttpParam *param) //using double-quote marks (refer to RFC 7230, section 3.2.6) param->value = p + i; } - else if(isalnum(c) || strchr("!#$%&'*+-.^_`|~", c) || c >= 128) + else if(isalnum(c) || osStrchr("!#$%&'*+-.^_`|~", c) || c >= 128) { //Point to the first character of the parameter value param->value = p + i; @@ -325,7 +325,7 @@ error_t httpParseParam(const char_t **pos, HttpParam *param) //Successful processing error = NO_ERROR; } - else if(isalnum(c) || strchr("!#$%&'*+-.^_`|~", c) || c >= 128) + else if(isalnum(c) || osStrchr("!#$%&'*+-.^_`|~", c) || c >= 128) { //Advance data pointer } @@ -470,7 +470,6 @@ error_t httpCopyParamValue(const HttpParam *param, char_t *value, * @param[in] input Point to the byte array * @param[in] inputLen Length of the byte array * @param[out] output NULL-terminated string resulting from the conversion - * @return Error code **/ void httpEncodeHexString(const uint8_t *input, size_t inputLen, char_t *output) diff --git a/http/http_common.h b/http/http_common.h index a8f46e3e..e86468dc 100644 --- a/http/http_common.h +++ b/http/http_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _HTTP_COMMON_H diff --git a/http/http_server.c b/http/http_server.c index bfc9061e..f2be4f7e 100644 --- a/http/http_server.c +++ b/http/http_server.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -35,7 +35,7 @@ * - RFC 2818: HTTP Over TLS * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/http/http_server.h b/http/http_server.h index 09dd67f6..ff951b1a 100644 --- a/http/http_server.h +++ b/http/http_server.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _HTTP_SERVER_H diff --git a/http/http_server_auth.c b/http/http_server_auth.c index b2c11e5b..c52fe5d3 100644 --- a/http/http_server_auth.c +++ b/http/http_server_auth.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -234,7 +234,7 @@ void httpParseAuthorizationField(HttpConnection *connection, char_t *value) //Properly terminate the string token[n] = '\0'; //Check whether a separator is present - separator = strchr(token, ':'); + separator = osStrchr(token, ':'); //Separator found? if(separator != NULL) @@ -277,7 +277,7 @@ void httpParseAuthorizationField(HttpConnection *connection, char_t *value) while(token != NULL) { //Check whether a separator is present - separator = strchr(token, '='); + separator = osStrchr(token, '='); //Separator found? if(separator != NULL) diff --git a/http/http_server_auth.h b/http/http_server_auth.h index 0a25c57d..c9c1dd63 100644 --- a/http/http_server_auth.h +++ b/http/http_server_auth.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _HTTP_SERVER_AUTH_H diff --git a/http/http_server_misc.c b/http/http_server_misc.c index 279672e3..ddff8092 100644 --- a/http/http_server_misc.c +++ b/http/http_server_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -156,7 +156,7 @@ error_t httpReadRequestHeader(HttpConnection *connection) break; //Check whether a separator is present - separator = strchr(connection->buffer, ':'); + separator = osStrchr(connection->buffer, ':'); //Separator found? if(separator != NULL) @@ -225,7 +225,7 @@ error_t httpParseRequestLine(HttpConnection *connection, char_t *requestLine) return ERROR_INVALID_REQUEST; //Check whether a query string is present - s = strchr(token, '?'); + s = osStrchr(token, '?'); //Query string found? if(s != NULL) @@ -415,7 +415,6 @@ error_t httpReadHeaderField(HttpConnection *connection, * @param[in] connection Structure representing an HTTP connection * @param[in] name Name of the header field * @param[in] value Value of the header field - * @return Error code **/ void httpParseHeaderField(HttpConnection *connection, @@ -1184,7 +1183,6 @@ error_t httpDecodePercentEncodedString(const char_t *input, * @param[in] input Point to the byte array * @param[in] inputLen Length of the byte array * @param[out] output NULL-terminated string resulting from the conversion - * @return Error code **/ void httpConvertArrayToHexString(const uint8_t *input, diff --git a/http/http_server_misc.h b/http/http_server_misc.h index c52cc585..4b251605 100644 --- a/http/http_server_misc.h +++ b/http/http_server_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _HTTP_SERVER_MISC_H diff --git a/http/mime.c b/http/mime.c index c0c9264d..e8581996 100644 --- a/http/mime.c +++ b/http/mime.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/http/mime.h b/http/mime.h index 15dbdef6..c2805c3b 100644 --- a/http/mime.h +++ b/http/mime.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MIME_H diff --git a/http/ssi.c b/http/ssi.c index 044b7f6c..ed99d055 100644 --- a/http/ssi.c +++ b/http/ssi.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * language used to generate dynamic content to web pages * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -439,7 +439,7 @@ error_t ssiProcessIncludeCommand(HttpConnection *connection, connection->buffer[length - 7] = '\0'; //Check whether a separator is present - separator = strchr(connection->buffer, '='); + separator = osStrchr(connection->buffer, '='); //Separator not found? if(!separator) return ERROR_INVALID_TAG; @@ -612,7 +612,7 @@ error_t ssiProcessEchoCommand(HttpConnection *connection, const char_t *tag, siz connection->buffer[length - 4] = '\0'; //Check whether a separator is present - separator = strchr(connection->buffer, '='); + separator = osStrchr(connection->buffer, '='); //Separator not found? if(!separator) return ERROR_INVALID_TAG; @@ -774,7 +774,7 @@ error_t ssiProcessExecCommand(HttpConnection *connection, const char_t *tag, siz connection->buffer[length - 4] = '\0'; //Check whether a separator is present - separator = strchr(connection->buffer, '='); + separator = osStrchr(connection->buffer, '='); //Separator not found? if(!separator) return ERROR_INVALID_TAG; diff --git a/http/ssi.h b/http/ssi.h index 51ce9cbc..538f3d0e 100644 --- a/http/ssi.h +++ b/http/ssi.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SSI_H diff --git a/icecast/icecast_client.c b/icecast/icecast_client.c index c72bfd63..1362347b 100644 --- a/icecast/icecast_client.c +++ b/icecast/icecast_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -551,7 +551,7 @@ error_t icecastClientConnect(IcecastClientContext *context) break; //Check whether a separator is present - separator = strchr(context->buffer, ':'); + separator = osStrchr(context->buffer, ':'); //Separator found? if(separator) diff --git a/icecast/icecast_client.h b/icecast/icecast_client.h index 31716ae4..1b5cc5a5 100644 --- a/icecast/icecast_client.h +++ b/icecast/icecast_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ICECAST_CLIENT_H diff --git a/ipv4/arp.c b/ipv4/arp.c index e6d09d29..bd62d2aa 100644 --- a/ipv4/arp.c +++ b/ipv4/arp.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * a specific host when only its IPv4 address is known. Refer to RFC 826 * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv4/arp.h b/ipv4/arp.h index e2de0146..f8526f43 100644 --- a/ipv4/arp.h +++ b/ipv4/arp.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ARP_H diff --git a/ipv4/auto_ip.c b/ipv4/auto_ip.c index 8f030f90..dac74b8e 100644 --- a/ipv4/auto_ip.c +++ b/ipv4/auto_ip.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -35,7 +35,7 @@ * - RFC 5227: IPv4 Address Conflict Detection * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv4/auto_ip.h b/ipv4/auto_ip.h index aff2c1a0..8814d606 100644 --- a/ipv4/auto_ip.h +++ b/ipv4/auto_ip.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _AUTO_IP_H diff --git a/ipv4/icmp.c b/ipv4/icmp.c index fe12fe90..fb72b395 100644 --- a/ipv4/icmp.c +++ b/ipv4/icmp.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv4/icmp.h b/ipv4/icmp.h index ef358432..259fbc0c 100644 --- a/ipv4/icmp.h +++ b/ipv4/icmp.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ICMP_H diff --git a/ipv4/igmp.c b/ipv4/igmp.c index 59685a3f..408fd3fe 100644 --- a/ipv4/igmp.c +++ b/ipv4/igmp.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 3376: Internet Group Management Protocol, Version 3 * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv4/igmp.h b/ipv4/igmp.h index 8411c377..e7be7151 100644 --- a/ipv4/igmp.h +++ b/ipv4/igmp.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IGMP_H diff --git a/ipv4/ipv4.c b/ipv4/ipv4.c index 1362ca40..5af64852 100644 --- a/ipv4/ipv4.c +++ b/ipv4/ipv4.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -31,7 +31,7 @@ * networks. Refer to RFC 791 for complete details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv4/ipv4.h b/ipv4/ipv4.h index e519089e..b93d662d 100644 --- a/ipv4/ipv4.h +++ b/ipv4/ipv4.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPV4_H diff --git a/ipv4/ipv4_frag.c b/ipv4/ipv4_frag.c index 7437a360..a9006926 100644 --- a/ipv4/ipv4_frag.c +++ b/ipv4/ipv4_frag.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -34,7 +34,7 @@ * - RFC 815: IP datagram reassembly algorithms * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv4/ipv4_frag.h b/ipv4/ipv4_frag.h index 82b8f821..db847de2 100644 --- a/ipv4/ipv4_frag.h +++ b/ipv4/ipv4_frag.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPV4_FRAG_H diff --git a/ipv4/ipv4_misc.c b/ipv4/ipv4_misc.c index a7fed5fb..0ebc4926 100644 --- a/ipv4/ipv4_misc.c +++ b/ipv4/ipv4_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv4/ipv4_misc.h b/ipv4/ipv4_misc.h index 8b3f6230..aaa7321e 100644 --- a/ipv4/ipv4_misc.h +++ b/ipv4/ipv4_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPV4_MISC_H diff --git a/ipv4/ipv4_routing.h b/ipv4/ipv4_routing.h index 5857f85a..43c0efdf 100644 --- a/ipv4/ipv4_routing.h +++ b/ipv4/ipv4_routing.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPV4_ROUTING_H diff --git a/ipv6/icmpv6.c b/ipv6/icmpv6.c index 8a310947..9be0c2c0 100644 --- a/ipv6/icmpv6.c +++ b/ipv6/icmpv6.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -32,7 +32,7 @@ * by every IPv6 node. Refer to the RFC 2463 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv6/icmpv6.h b/ipv6/icmpv6.h index 613f3a90..874d3532 100644 --- a/ipv6/icmpv6.h +++ b/ipv6/icmpv6.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _ICMPV6_H diff --git a/ipv6/ipv6.c b/ipv6/ipv6.c index 54ccb26b..7f28961f 100644 --- a/ipv6/ipv6.c +++ b/ipv6/ipv6.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * as the successor to IP version 4 (IPv4). Refer to RFC 2460 * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv6/ipv6.h b/ipv6/ipv6.h index dc510329..10b46e13 100644 --- a/ipv6/ipv6.h +++ b/ipv6/ipv6.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPV6_H diff --git a/ipv6/ipv6_frag.c b/ipv6/ipv6_frag.c index 1c88f683..4a5ff0c0 100644 --- a/ipv6/ipv6_frag.c +++ b/ipv6/ipv6_frag.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv6/ipv6_frag.h b/ipv6/ipv6_frag.h index aad7d808..2ae7ecd8 100644 --- a/ipv6/ipv6_frag.h +++ b/ipv6/ipv6_frag.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPV6_FRAG_H diff --git a/ipv6/ipv6_misc.c b/ipv6/ipv6_misc.c index 238833e8..a6e42778 100644 --- a/ipv6/ipv6_misc.c +++ b/ipv6/ipv6_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -1391,7 +1391,7 @@ error_t ipv6ComputeSolicitedNodeAddr(const Ipv6Addr *ipAddr, solicitedNodeAddr->b[14] = ipAddr->b[14]; solicitedNodeAddr->b[15] = ipAddr->b[15]; - //Sucessful processing + //Successful processing error = NO_ERROR; } else diff --git a/ipv6/ipv6_misc.h b/ipv6/ipv6_misc.h index 6f6cba9f..828d5b25 100644 --- a/ipv6/ipv6_misc.h +++ b/ipv6/ipv6_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPV6_MISC_H diff --git a/ipv6/ipv6_pmtu.c b/ipv6/ipv6_pmtu.c index bc23d0ec..85199a6e 100644 --- a/ipv6/ipv6_pmtu.c +++ b/ipv6/ipv6_pmtu.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv6/ipv6_pmtu.h b/ipv6/ipv6_pmtu.h index 5eb18c31..80921de6 100644 --- a/ipv6/ipv6_pmtu.h +++ b/ipv6/ipv6_pmtu.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPV6_PMTU_H diff --git a/ipv6/ipv6_routing.c b/ipv6/ipv6_routing.c index fafe0543..088b9071 100644 --- a/ipv6/ipv6_routing.c +++ b/ipv6/ipv6_routing.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -169,7 +169,7 @@ error_t ipv6AddRoute(const Ipv6Addr *prefix, uint_t prefixLen, //The entry is now valid entry->valid = TRUE; - //Sucessful processing + //Successful processing error = NO_ERROR; } else diff --git a/ipv6/ipv6_routing.h b/ipv6/ipv6_routing.h index a71e7d62..233dd70b 100644 --- a/ipv6/ipv6_routing.h +++ b/ipv6/ipv6_routing.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPV6_ROUTING_H diff --git a/ipv6/mld.c b/ipv6/mld.c index 919fe56c..7751cbd9 100644 --- a/ipv6/mld.c +++ b/ipv6/mld.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -34,7 +34,7 @@ * - RFC 3810: Multicast Listener Discovery Version 2 (MLDv2) for IPv6 * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv6/mld.h b/ipv6/mld.h index d21e0d36..ceb22ecc 100644 --- a/ipv6/mld.h +++ b/ipv6/mld.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MLD_H diff --git a/ipv6/ndp.c b/ipv6/ndp.c index 54aa8d57..7aefaa77 100644 --- a/ipv6/ndp.c +++ b/ipv6/ndp.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -32,7 +32,7 @@ * Refer to RFC 4861 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv6/ndp.h b/ipv6/ndp.h index 6a79c498..5e1a653d 100644 --- a/ipv6/ndp.h +++ b/ipv6/ndp.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NDP_H diff --git a/ipv6/ndp_cache.c b/ipv6/ndp_cache.c index 52b299ce..63952e79 100644 --- a/ipv6/ndp_cache.c +++ b/ipv6/ndp_cache.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv6/ndp_cache.h b/ipv6/ndp_cache.h index a3b0d096..bc20416f 100644 --- a/ipv6/ndp_cache.h +++ b/ipv6/ndp_cache.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NDP_CACHE_H diff --git a/ipv6/ndp_misc.c b/ipv6/ndp_misc.c index cdf51492..82107bfa 100644 --- a/ipv6/ndp_misc.c +++ b/ipv6/ndp_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -666,7 +666,7 @@ void *ndpGetOption(uint8_t *options, size_t length, uint8_t type) if(option->type == type || type == NDP_OPT_ANY) return option; - //Jump to next the next option + //Jump to the next option i += option->length * 8; } @@ -701,7 +701,7 @@ error_t ndpCheckOptions(const uint8_t *options, size_t length) if(option->length == 0) return ERROR_INVALID_OPTION; - //Jump to next the next option + //Jump to the next option i += option->length * 8; } diff --git a/ipv6/ndp_misc.h b/ipv6/ndp_misc.h index 23c1c95e..39e0d969 100644 --- a/ipv6/ndp_misc.h +++ b/ipv6/ndp_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NDP_MISC_H diff --git a/ipv6/ndp_router_adv.c b/ipv6/ndp_router_adv.c index 380cc193..0a150a94 100644 --- a/ipv6/ndp_router_adv.c +++ b/ipv6/ndp_router_adv.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv6/ndp_router_adv.h b/ipv6/ndp_router_adv.h index c79afb87..68bb621f 100644 --- a/ipv6/ndp_router_adv.h +++ b/ipv6/ndp_router_adv.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NDP_ROUTER_ADV_H diff --git a/ipv6/slaac.c b/ipv6/slaac.c index b1ee5054..5229852d 100644 --- a/ipv6/slaac.c +++ b/ipv6/slaac.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 6106: IPv6 Router Advertisement Options for DNS Configuration * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ipv6/slaac.h b/ipv6/slaac.h index 7d480aca..86fa7bcc 100644 --- a/ipv6/slaac.h +++ b/ipv6/slaac.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SLAAC_H diff --git a/llmnr/llmnr_client.c b/llmnr/llmnr_client.c index 5e8a91d2..bcc0aefd 100644 --- a/llmnr/llmnr_client.c +++ b/llmnr/llmnr_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/llmnr/llmnr_client.h b/llmnr/llmnr_client.h index 22feb1cf..c7ef3b71 100644 --- a/llmnr/llmnr_client.h +++ b/llmnr/llmnr_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LLMNR_CLIENT_H diff --git a/llmnr/llmnr_common.c b/llmnr/llmnr_common.c index 1bcc99cc..168d281e 100644 --- a/llmnr/llmnr_common.c +++ b/llmnr/llmnr_common.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/llmnr/llmnr_common.h b/llmnr/llmnr_common.h index 842951e0..f5e9bdbe 100644 --- a/llmnr/llmnr_common.h +++ b/llmnr/llmnr_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LLMNR_COMMON_H diff --git a/llmnr/llmnr_responder.c b/llmnr/llmnr_responder.c index 3a0b4368..17ebe450 100644 --- a/llmnr/llmnr_responder.c +++ b/llmnr/llmnr_responder.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/llmnr/llmnr_responder.h b/llmnr/llmnr_responder.h index b668bab0..1b72ef30 100644 --- a/llmnr/llmnr_responder.h +++ b/llmnr/llmnr_responder.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LLMNR_RESPONDER_H diff --git a/mdns/mdns_client.c b/mdns/mdns_client.c index b104d3f8..bfab65f4 100644 --- a/mdns/mdns_client.c +++ b/mdns/mdns_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mdns/mdns_client.h b/mdns/mdns_client.h index 8258c2a6..0eb06864 100644 --- a/mdns/mdns_client.h +++ b/mdns/mdns_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MDNS_CLIENT_H diff --git a/mdns/mdns_common.c b/mdns/mdns_common.c index aac91b6f..5db56407 100644 --- a/mdns/mdns_common.c +++ b/mdns/mdns_common.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 6763: DNS-Based Service Discovery * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mdns/mdns_common.h b/mdns/mdns_common.h index a6234d86..9f173ae1 100644 --- a/mdns/mdns_common.h +++ b/mdns/mdns_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MDNS_COMMON_H diff --git a/mdns/mdns_responder.c b/mdns/mdns_responder.c index b84ee9f1..f4d4b43f 100644 --- a/mdns/mdns_responder.c +++ b/mdns/mdns_responder.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mdns/mdns_responder.h b/mdns/mdns_responder.h index 53f4bc84..0cb3462b 100644 --- a/mdns/mdns_responder.h +++ b/mdns/mdns_responder.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MDNS_RESPONDER_H diff --git a/mibs/if_mib_impl.c b/mibs/if_mib_impl.c index d27ae917..bbbd48dc 100644 --- a/mibs/if_mib_impl.c +++ b/mibs/if_mib_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/if_mib_impl.h b/mibs/if_mib_impl.h index 96a48c64..f82a4411 100644 --- a/mibs/if_mib_impl.h +++ b/mibs/if_mib_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IF_MIB_IMPL_H diff --git a/mibs/if_mib_module.c b/mibs/if_mib_module.c index 243e8f32..8bbe22cb 100644 --- a/mibs/if_mib_module.c +++ b/mibs/if_mib_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -32,7 +32,7 @@ * - RFC 2863: The Interfaces Group MIB * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/if_mib_module.h b/mibs/if_mib_module.h index f69e527a..4d6cc0e7 100644 --- a/mibs/if_mib_module.h +++ b/mibs/if_mib_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IF_MIB_MODULE_H diff --git a/mibs/ip_mib_impl.c b/mibs/ip_mib_impl.c index 3649053c..6682611b 100644 --- a/mibs/ip_mib_impl.c +++ b/mibs/ip_mib_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/ip_mib_impl.h b/mibs/ip_mib_impl.h index 81104432..b6bc1873 100644 --- a/mibs/ip_mib_impl.h +++ b/mibs/ip_mib_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IP_MIB_IMPL_H diff --git a/mibs/ip_mib_module.c b/mibs/ip_mib_module.c index 296f4acd..8ed65860 100644 --- a/mibs/ip_mib_module.c +++ b/mibs/ip_mib_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 4001: Textual Conventions for Internet Network Addresses * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/ip_mib_module.h b/mibs/ip_mib_module.h index f4349571..2edac5cd 100644 --- a/mibs/ip_mib_module.h +++ b/mibs/ip_mib_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IP_MIB_MODULE_H diff --git a/mibs/mib2_impl.c b/mibs/mib2_impl.c index cbbc39f3..aa88a82f 100644 --- a/mibs/mib2_impl.c +++ b/mibs/mib2_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Dependencies diff --git a/mibs/mib2_impl.h b/mibs/mib2_impl.h index b790cb3f..77082b9b 100644 --- a/mibs/mib2_impl.h +++ b/mibs/mib2_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MIB2_IMPL_H diff --git a/mibs/mib2_module.c b/mibs/mib2_module.c index d0a36cff..4b22a49c 100644 --- a/mibs/mib2_module.c +++ b/mibs/mib2_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -32,7 +32,7 @@ * - RFC 1213: MIB for Network Management of TCP/IP-based internets (version 2) * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/mib2_module.h b/mibs/mib2_module.h index 89fe8f02..88cba169 100644 --- a/mibs/mib2_module.h +++ b/mibs/mib2_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MIB2_MODULE_H diff --git a/mibs/mib_common.c b/mibs/mib_common.c index f092f4d8..6c131496 100644 --- a/mibs/mib_common.c +++ b/mibs/mib_common.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Dependencies diff --git a/mibs/mib_common.h b/mibs/mib_common.h index 2ce039a6..619883ff 100644 --- a/mibs/mib_common.h +++ b/mibs/mib_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MIB_COMMON_H diff --git a/mibs/snmp_community_mib_impl.c b/mibs/snmp_community_mib_impl.c index 72647bce..b5586d8e 100644 --- a/mibs/snmp_community_mib_impl.c +++ b/mibs/snmp_community_mib_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * of an SNMP entity. Refer to RFC 3418 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_community_mib_impl.h b/mibs/snmp_community_mib_impl.h index fe8c37e9..dea3ce55 100644 --- a/mibs/snmp_community_mib_impl.h +++ b/mibs/snmp_community_mib_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * of an SNMP entity. Refer to RFC 3418 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_COMMUNITY_MIB_IMPL_H diff --git a/mibs/snmp_community_mib_module.c b/mibs/snmp_community_mib_module.c index 79b0a740..7c743d0f 100644 --- a/mibs/snmp_community_mib_module.c +++ b/mibs/snmp_community_mib_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -31,7 +31,7 @@ * to RFC 3584 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_community_mib_module.h b/mibs/snmp_community_mib_module.h index 00742cfe..420dee29 100644 --- a/mibs/snmp_community_mib_module.h +++ b/mibs/snmp_community_mib_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * of an SNMP entity. Refer to RFC 3418 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_COMMUNITY_MIB_MODULE_H diff --git a/mibs/snmp_framework_mib_impl.c b/mibs/snmp_framework_mib_impl.c index 8853df1b..cbfac8d3 100644 --- a/mibs/snmp_framework_mib_impl.c +++ b/mibs/snmp_framework_mib_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_framework_mib_impl.h b/mibs/snmp_framework_mib_impl.h index 0b61b974..59976e99 100644 --- a/mibs/snmp_framework_mib_impl.h +++ b/mibs/snmp_framework_mib_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_FRAMEWORK_MIB_IMPL_H diff --git a/mibs/snmp_framework_mib_module.c b/mibs/snmp_framework_mib_module.c index 4aa32b60..f77e3989 100644 --- a/mibs/snmp_framework_mib_module.c +++ b/mibs/snmp_framework_mib_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * frameworks. Refer to RFC 3411 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_framework_mib_module.h b/mibs/snmp_framework_mib_module.h index 82ad425d..668d43fb 100644 --- a/mibs/snmp_framework_mib_module.h +++ b/mibs/snmp_framework_mib_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_FRAMEWORK_MIB_MODULE_H diff --git a/mibs/snmp_mib_impl.c b/mibs/snmp_mib_impl.c index d58bb0aa..7316458d 100644 --- a/mibs/snmp_mib_impl.c +++ b/mibs/snmp_mib_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_mib_impl.h b/mibs/snmp_mib_impl.h index 9f99ed27..43acc12a 100644 --- a/mibs/snmp_mib_impl.h +++ b/mibs/snmp_mib_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_MIB_IMPL_H diff --git a/mibs/snmp_mib_module.c b/mibs/snmp_mib_module.c index 95c8f1b5..f1431faf 100644 --- a/mibs/snmp_mib_module.c +++ b/mibs/snmp_mib_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * of an SNMP entity. Refer to RFC 3418 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_mib_module.h b/mibs/snmp_mib_module.h index 4f656619..642d37d5 100644 --- a/mibs/snmp_mib_module.h +++ b/mibs/snmp_mib_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_MIB_MODULE_H diff --git a/mibs/snmp_mpd_mib_impl.c b/mibs/snmp_mpd_mib_impl.c index de3ddd28..3d1d34a1 100644 --- a/mibs/snmp_mpd_mib_impl.c +++ b/mibs/snmp_mpd_mib_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_mpd_mib_impl.h b/mibs/snmp_mpd_mib_impl.h index 1b49a8c0..41ba6654 100644 --- a/mibs/snmp_mpd_mib_impl.h +++ b/mibs/snmp_mpd_mib_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_MPD_MIB_IMPL_H diff --git a/mibs/snmp_mpd_mib_module.c b/mibs/snmp_mpd_mib_module.c index 9c56b178..bb0095dc 100644 --- a/mibs/snmp_mpd_mib_module.c +++ b/mibs/snmp_mpd_mib_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * dispatching. Refer to RFC 3412 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_mpd_mib_module.h b/mibs/snmp_mpd_mib_module.h index 134bec7d..eefb5bf9 100644 --- a/mibs/snmp_mpd_mib_module.h +++ b/mibs/snmp_mpd_mib_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_MPD_MIB_MODULE_H diff --git a/mibs/snmp_usm_mib_impl.c b/mibs/snmp_usm_mib_impl.c index b0797d32..ec330f56 100644 --- a/mibs/snmp_usm_mib_impl.c +++ b/mibs/snmp_usm_mib_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_usm_mib_impl.h b/mibs/snmp_usm_mib_impl.h index f845e3b6..ebe76ef0 100644 --- a/mibs/snmp_usm_mib_impl.h +++ b/mibs/snmp_usm_mib_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_USM_MIB_IMPL_H diff --git a/mibs/snmp_usm_mib_module.c b/mibs/snmp_usm_mib_module.c index f1867030..6d7ee9a4 100644 --- a/mibs/snmp_usm_mib_module.c +++ b/mibs/snmp_usm_mib_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -31,7 +31,7 @@ * Refer to RFC 3414 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_usm_mib_module.h b/mibs/snmp_usm_mib_module.h index 60af9ee5..82ba4da0 100644 --- a/mibs/snmp_usm_mib_module.h +++ b/mibs/snmp_usm_mib_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_USM_MIB_MODULE_H diff --git a/mibs/snmp_vacm_mib_impl.c b/mibs/snmp_vacm_mib_impl.c index e10c8ef7..ade78025 100644 --- a/mibs/snmp_vacm_mib_impl.c +++ b/mibs/snmp_vacm_mib_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_vacm_mib_impl.h b/mibs/snmp_vacm_mib_impl.h index 124d482a..a00a0f80 100644 --- a/mibs/snmp_vacm_mib_impl.h +++ b/mibs/snmp_vacm_mib_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_VACM_MIB_IMPL_H diff --git a/mibs/snmp_vacm_mib_module.c b/mibs/snmp_vacm_mib_module.c index 4d2eb565..2089206d 100644 --- a/mibs/snmp_vacm_mib_module.c +++ b/mibs/snmp_vacm_mib_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -32,7 +32,7 @@ * details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/snmp_vacm_mib_module.h b/mibs/snmp_vacm_mib_module.h index fb7c55d2..a83a5e76 100644 --- a/mibs/snmp_vacm_mib_module.h +++ b/mibs/snmp_vacm_mib_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_VACM_MIB_MODULE_H diff --git a/mibs/tcp_mib_impl.c b/mibs/tcp_mib_impl.c index 48480cd4..df9697dc 100644 --- a/mibs/tcp_mib_impl.c +++ b/mibs/tcp_mib_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/tcp_mib_impl.h b/mibs/tcp_mib_impl.h index f7939ac3..0e05ce4b 100644 --- a/mibs/tcp_mib_impl.h +++ b/mibs/tcp_mib_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TCP_MIB_IMPL_H diff --git a/mibs/tcp_mib_module.c b/mibs/tcp_mib_module.c index 341f4f4a..f587202e 100644 --- a/mibs/tcp_mib_module.c +++ b/mibs/tcp_mib_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 4001: Textual Conventions for Internet Network Addresses * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/tcp_mib_module.h b/mibs/tcp_mib_module.h index aafdfee8..411a385e 100644 --- a/mibs/tcp_mib_module.h +++ b/mibs/tcp_mib_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TCP_MIB_MODULE_H diff --git a/mibs/udp_mib_impl.c b/mibs/udp_mib_impl.c index a86c7fbd..ec3b992b 100644 --- a/mibs/udp_mib_impl.c +++ b/mibs/udp_mib_impl.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/udp_mib_impl.h b/mibs/udp_mib_impl.h index 06f51c30..9c6ae059 100644 --- a/mibs/udp_mib_impl.h +++ b/mibs/udp_mib_impl.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _UDP_MIB_IMPL_H diff --git a/mibs/udp_mib_module.c b/mibs/udp_mib_module.c index 3d33e5b2..f6425302 100644 --- a/mibs/udp_mib_module.c +++ b/mibs/udp_mib_module.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 4001: Textual Conventions for Internet Network Addresses * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mibs/udp_mib_module.h b/mibs/udp_mib_module.h index 3856d3a0..0aa7ad06 100644 --- a/mibs/udp_mib_module.h +++ b/mibs/udp_mib_module.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _UDP_MIB_MODULE_H diff --git a/modbus/modbus_client.c b/modbus/modbus_client.c index 12110e15..884e0c9f 100644 --- a/modbus/modbus_client.c +++ b/modbus/modbus_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/modbus/modbus_client.h b/modbus/modbus_client.h index c918e7d5..732f8fb6 100644 --- a/modbus/modbus_client.h +++ b/modbus/modbus_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_CLIENT_H diff --git a/modbus/modbus_client_misc.c b/modbus/modbus_client_misc.c index 96d1d766..d76d4e81 100644 --- a/modbus/modbus_client_misc.c +++ b/modbus/modbus_client_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/modbus/modbus_client_misc.h b/modbus/modbus_client_misc.h index fb861f21..30a7aecd 100644 --- a/modbus/modbus_client_misc.h +++ b/modbus/modbus_client_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_CLIENT_MISC_H diff --git a/modbus/modbus_client_pdu.c b/modbus/modbus_client_pdu.c index 7f6df185..97870dcb 100644 --- a/modbus/modbus_client_pdu.c +++ b/modbus/modbus_client_pdu.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/modbus/modbus_client_pdu.h b/modbus/modbus_client_pdu.h index 66ab67cf..5a551862 100644 --- a/modbus/modbus_client_pdu.h +++ b/modbus/modbus_client_pdu.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_CLIENT_PDU_H diff --git a/modbus/modbus_client_transport.c b/modbus/modbus_client_transport.c index 62c0e501..75eed490 100644 --- a/modbus/modbus_client_transport.c +++ b/modbus/modbus_client_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/modbus/modbus_client_transport.h b/modbus/modbus_client_transport.h index 9d64fb17..222e065b 100644 --- a/modbus/modbus_client_transport.h +++ b/modbus/modbus_client_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_CLIENT_TRANSPORT_H diff --git a/modbus/modbus_common.h b/modbus/modbus_common.h index fe0985b3..dc0a4969 100644 --- a/modbus/modbus_common.h +++ b/modbus/modbus_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_COMMON_H diff --git a/modbus/modbus_debug.c b/modbus/modbus_debug.c index 9b1792c4..f1b819a4 100644 --- a/modbus/modbus_debug.c +++ b/modbus/modbus_debug.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/modbus/modbus_debug.h b/modbus/modbus_debug.h index 07835277..dedc4f88 100644 --- a/modbus/modbus_debug.h +++ b/modbus/modbus_debug.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_DEBUG_H diff --git a/modbus/modbus_server.c b/modbus/modbus_server.c index 7d5964a5..1286bb9d 100644 --- a/modbus/modbus_server.c +++ b/modbus/modbus_server.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/modbus/modbus_server.h b/modbus/modbus_server.h index 17bc0102..4b000e9a 100644 --- a/modbus/modbus_server.h +++ b/modbus/modbus_server.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_SERVER_H diff --git a/modbus/modbus_server_misc.c b/modbus/modbus_server_misc.c index 4926df10..44b52d7b 100644 --- a/modbus/modbus_server_misc.c +++ b/modbus/modbus_server_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/modbus/modbus_server_misc.h b/modbus/modbus_server_misc.h index 9b86bd25..9c30e7c0 100644 --- a/modbus/modbus_server_misc.h +++ b/modbus/modbus_server_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_SERVER_MISC_H diff --git a/modbus/modbus_server_pdu.c b/modbus/modbus_server_pdu.c index e929d24e..14456dbd 100644 --- a/modbus/modbus_server_pdu.c +++ b/modbus/modbus_server_pdu.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/modbus/modbus_server_pdu.h b/modbus/modbus_server_pdu.h index df3857fa..abe81a14 100644 --- a/modbus/modbus_server_pdu.h +++ b/modbus/modbus_server_pdu.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_SERVER_PDU_H diff --git a/modbus/modbus_server_security.c b/modbus/modbus_server_security.c index 240e6e44..18e25ca3 100644 --- a/modbus/modbus_server_security.c +++ b/modbus/modbus_server_security.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/modbus/modbus_server_security.h b/modbus/modbus_server_security.h index 5f70f43e..8aef611f 100644 --- a/modbus/modbus_server_security.h +++ b/modbus/modbus_server_security.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_SERVER_SECURITY_H diff --git a/modbus/modbus_server_transport.c b/modbus/modbus_server_transport.c index d1088287..5bebdbec 100644 --- a/modbus/modbus_server_transport.c +++ b/modbus/modbus_server_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/modbus/modbus_server_transport.h b/modbus/modbus_server_transport.h index ca96129d..4e78b3cf 100644 --- a/modbus/modbus_server_transport.h +++ b/modbus/modbus_server_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MODBUS_SERVER_TRANSPORT_H diff --git a/mqtt/mqtt_client.c b/mqtt/mqtt_client.c index d46f5af2..8a938071 100644 --- a/mqtt/mqtt_client.c +++ b/mqtt/mqtt_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mqtt/mqtt_client.h b/mqtt/mqtt_client.h index 0d4d949d..41bc201e 100644 --- a/mqtt/mqtt_client.h +++ b/mqtt/mqtt_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_CLIENT_H diff --git a/mqtt/mqtt_client_misc.c b/mqtt/mqtt_client_misc.c index 34eee9f7..19bc04d9 100644 --- a/mqtt/mqtt_client_misc.c +++ b/mqtt/mqtt_client_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mqtt/mqtt_client_misc.h b/mqtt/mqtt_client_misc.h index 4be1e781..10c945c6 100644 --- a/mqtt/mqtt_client_misc.h +++ b/mqtt/mqtt_client_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_CLIENT_MISC_H diff --git a/mqtt/mqtt_client_packet.c b/mqtt/mqtt_client_packet.c index 428f56df..fc49dc8e 100644 --- a/mqtt/mqtt_client_packet.c +++ b/mqtt/mqtt_client_packet.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mqtt/mqtt_client_packet.h b/mqtt/mqtt_client_packet.h index c8765caa..1fa085ea 100644 --- a/mqtt/mqtt_client_packet.h +++ b/mqtt/mqtt_client_packet.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_CLIENT_PACKET_H diff --git a/mqtt/mqtt_client_transport.c b/mqtt/mqtt_client_transport.c index bca418a6..cf6da656 100644 --- a/mqtt/mqtt_client_transport.c +++ b/mqtt/mqtt_client_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mqtt/mqtt_client_transport.h b/mqtt/mqtt_client_transport.h index 99d0e9f2..96a88eeb 100644 --- a/mqtt/mqtt_client_transport.h +++ b/mqtt/mqtt_client_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_CLIENT_TRANSPORT_H diff --git a/mqtt/mqtt_common.h b/mqtt/mqtt_common.h index 5407dc99..15780818 100644 --- a/mqtt/mqtt_common.h +++ b/mqtt/mqtt_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_COMMON_H diff --git a/mqtt_sn/mqtt_sn_client.c b/mqtt_sn/mqtt_sn_client.c index a3433e70..3a4238aa 100644 --- a/mqtt_sn/mqtt_sn_client.c +++ b/mqtt_sn/mqtt_sn_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -936,7 +936,7 @@ error_t mqttSnClientSubscribe(MqttSnClientContext *context, { //The topic ID field is not relevant in case of subscriptions to a //topic name which contains wildcard characters - if(strchr(topicName, '#') == NULL && strchr(topicName, '+') == NULL) + if(osStrchr(topicName, '#') == NULL && osStrchr(topicName, '+') == NULL) { //Save the topic ID assigned by the gateway error = mqttSnClientAddTopic(context, topicName, context->topicId); @@ -1363,10 +1363,12 @@ error_t mqttSnClientTask(MqttSnClientContext *context, systime_t timeout) /** * @brief Disconnect from the MQTT-SN gateway * @param[in] context Pointer to the MQTT-SN client context + * @param[in] duration Sleep duration, in milliseconds * @return Error code **/ -error_t mqttSnClientDisconnect(MqttSnClientContext *context) +error_t mqttSnClientDisconnect(MqttSnClientContext *context, + systime_t duration) { error_t error; systime_t time; @@ -1392,7 +1394,7 @@ error_t mqttSnClientDisconnect(MqttSnClientContext *context) //The DISCONNECT message is sent by a client to indicate that it //wants to close the connection - error = mqttSnClientSendDisconnect(context, 0); + error = mqttSnClientSendDisconnect(context, duration / 1000); } else if(context->state == MQTT_SN_CLIENT_STATE_SENDING_REQ) { @@ -1410,7 +1412,7 @@ error_t mqttSnClientDisconnect(MqttSnClientContext *context) { //If the retry timer times out and the expected gateway's reply //is not received, the client retransmits the message - error = mqttSnClientSendDisconnect(context, 0); + error = mqttSnClientSendDisconnect(context, duration / 1000); } else { diff --git a/mqtt_sn/mqtt_sn_client.h b/mqtt_sn/mqtt_sn_client.h index b3437d4f..70065e82 100644 --- a/mqtt_sn/mqtt_sn_client.h +++ b/mqtt_sn/mqtt_sn_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_SN_CLIENT_H @@ -329,7 +329,9 @@ error_t mqttSnClientGetReturnCode(MqttSnClientContext *context, error_t mqttSnClientTask(MqttSnClientContext *context, systime_t timeout); -error_t mqttSnClientDisconnect(MqttSnClientContext *context); +error_t mqttSnClientDisconnect(MqttSnClientContext *context, + systime_t duration); + void mqttSnClientDeinit(MqttSnClientContext *context); //C++ guard diff --git a/mqtt_sn/mqtt_sn_client_message.c b/mqtt_sn/mqtt_sn_client_message.c index 5c09f38b..bfd59860 100644 --- a/mqtt_sn/mqtt_sn_client_message.c +++ b/mqtt_sn/mqtt_sn_client_message.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -1555,8 +1555,8 @@ error_t mqttSnClientSendUnsubscribe(MqttSnClientContext *context, else { //Short topic name? - if(osStrlen(topicName) == 2 && strchr(topicName, '#') == NULL && - strchr(topicName, '+') == NULL) + if(osStrlen(topicName) == 2 && osStrchr(topicName, '#') == NULL && + osStrchr(topicName, '+') == NULL) { //The UNSUBSCRIBE message contains a short topic name flags.topicIdType = MQTT_SN_SHORT_TOPIC_NAME; diff --git a/mqtt_sn/mqtt_sn_client_message.h b/mqtt_sn/mqtt_sn_client_message.h index 2ebccfa1..6caa91ef 100644 --- a/mqtt_sn/mqtt_sn_client_message.h +++ b/mqtt_sn/mqtt_sn_client_message.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_SN_CLIENT_MESSAGE_H diff --git a/mqtt_sn/mqtt_sn_client_misc.c b/mqtt_sn/mqtt_sn_client_misc.c index 2bb155b5..d594e937 100644 --- a/mqtt_sn/mqtt_sn_client_misc.c +++ b/mqtt_sn/mqtt_sn_client_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -606,7 +606,7 @@ bool_t mqttSnClientIsShortTopicName(const char_t *topicName) if(osStrlen(topicName) == 2) { //Ensure the topic name does not contains wildcard characters - if(strchr(topicName, '#') == NULL && strchr(topicName, '+') == NULL) + if(osStrchr(topicName, '#') == NULL && osStrchr(topicName, '+') == NULL) { //The short topic name is a valid res = TRUE; diff --git a/mqtt_sn/mqtt_sn_client_misc.h b/mqtt_sn/mqtt_sn_client_misc.h index 27df11f1..867b3705 100644 --- a/mqtt_sn/mqtt_sn_client_misc.h +++ b/mqtt_sn/mqtt_sn_client_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_SN_CLIENT_MISC_H diff --git a/mqtt_sn/mqtt_sn_client_transport.c b/mqtt_sn/mqtt_sn_client_transport.c index 6da3266d..7f538062 100644 --- a/mqtt_sn/mqtt_sn_client_transport.c +++ b/mqtt_sn/mqtt_sn_client_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mqtt_sn/mqtt_sn_client_transport.h b/mqtt_sn/mqtt_sn_client_transport.h index 127e362b..7e1344da 100644 --- a/mqtt_sn/mqtt_sn_client_transport.h +++ b/mqtt_sn/mqtt_sn_client_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_SN_CLIENT_TRANSPORT_H diff --git a/mqtt_sn/mqtt_sn_common.h b/mqtt_sn/mqtt_sn_common.h index 70975598..2d0f099f 100644 --- a/mqtt_sn/mqtt_sn_common.h +++ b/mqtt_sn/mqtt_sn_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_SN_COMMON_H diff --git a/mqtt_sn/mqtt_sn_debug.c b/mqtt_sn/mqtt_sn_debug.c index 2fdda860..4bbc85b4 100644 --- a/mqtt_sn/mqtt_sn_debug.c +++ b/mqtt_sn/mqtt_sn_debug.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mqtt_sn/mqtt_sn_debug.h b/mqtt_sn/mqtt_sn_debug.h index 666f660a..86aea4b4 100644 --- a/mqtt_sn/mqtt_sn_debug.h +++ b/mqtt_sn/mqtt_sn_debug.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_SN_DEBUG_H diff --git a/mqtt_sn/mqtt_sn_message.c b/mqtt_sn/mqtt_sn_message.c index dc5f92dc..8229c267 100644 --- a/mqtt_sn/mqtt_sn_message.c +++ b/mqtt_sn/mqtt_sn_message.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/mqtt_sn/mqtt_sn_message.h b/mqtt_sn/mqtt_sn_message.h index baf76977..9a2515d8 100644 --- a/mqtt_sn/mqtt_sn_message.h +++ b/mqtt_sn/mqtt_sn_message.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _MQTT_SN_MESSAGE_H diff --git a/netbios/nbns_client.c b/netbios/nbns_client.c index b35d2b29..e10e7d58 100644 --- a/netbios/nbns_client.c +++ b/netbios/nbns_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/netbios/nbns_client.h b/netbios/nbns_client.h index 56fba41b..d5820217 100644 --- a/netbios/nbns_client.h +++ b/netbios/nbns_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NBNS_CLIENT_H diff --git a/netbios/nbns_common.c b/netbios/nbns_common.c index 89b1fbb7..e22ba2e3 100644 --- a/netbios/nbns_common.c +++ b/netbios/nbns_common.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/netbios/nbns_common.h b/netbios/nbns_common.h index f0e0bcf7..c6b62a7c 100644 --- a/netbios/nbns_common.h +++ b/netbios/nbns_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NBNS_COMMON_H diff --git a/netbios/nbns_responder.c b/netbios/nbns_responder.c index 03d32682..60429f93 100644 --- a/netbios/nbns_responder.c +++ b/netbios/nbns_responder.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/netbios/nbns_responder.h b/netbios/nbns_responder.h index 8a8658ed..b6791e91 100644 --- a/netbios/nbns_responder.h +++ b/netbios/nbns_responder.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NBNS_RESPONDER_H diff --git a/ppp/chap.c b/ppp/chap.c index b0067741..317b012b 100644 --- a/ppp/chap.c +++ b/ppp/chap.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ppp/chap.h b/ppp/chap.h index 6f41c2ce..da130b21 100644 --- a/ppp/chap.h +++ b/ppp/chap.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _CHAP_H diff --git a/ppp/ipcp.c b/ppp/ipcp.c index e473d1fe..a944f85b 100644 --- a/ppp/ipcp.c +++ b/ppp/ipcp.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ppp/ipcp.h b/ppp/ipcp.h index b4b1a63a..ff98fd14 100644 --- a/ppp/ipcp.h +++ b/ppp/ipcp.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPCP_H diff --git a/ppp/ipv6cp.c b/ppp/ipv6cp.c index 80b64c7a..20d4bb67 100644 --- a/ppp/ipv6cp.c +++ b/ppp/ipv6cp.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ppp/ipv6cp.h b/ppp/ipv6cp.h index 0795e594..743c87ec 100644 --- a/ppp/ipv6cp.h +++ b/ppp/ipv6cp.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _IPV6CP_H diff --git a/ppp/lcp.c b/ppp/lcp.c index 6e67d131..9a225329 100644 --- a/ppp/lcp.c +++ b/ppp/lcp.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ppp/lcp.h b/ppp/lcp.h index 167d91b2..a7842cda 100644 --- a/ppp/lcp.h +++ b/ppp/lcp.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _LCP_H diff --git a/ppp/pap.c b/ppp/pap.c index ddbbff9c..b5f9f5ac 100644 --- a/ppp/pap.c +++ b/ppp/pap.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ppp/pap.h b/ppp/pap.h index 493fa76e..c0f4f971 100644 --- a/ppp/pap.h +++ b/ppp/pap.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _PAP_H diff --git a/ppp/ppp.c b/ppp/ppp.c index ff4e84a7..21aeafe7 100644 --- a/ppp/ppp.c +++ b/ppp/ppp.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ppp/ppp.h b/ppp/ppp.h index c96cd559..1312cd5e 100644 --- a/ppp/ppp.h +++ b/ppp/ppp.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _PPP_H diff --git a/ppp/ppp_debug.c b/ppp/ppp_debug.c index 3923cdb9..8edb5029 100644 --- a/ppp/ppp_debug.c +++ b/ppp/ppp_debug.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Dependencies diff --git a/ppp/ppp_debug.h b/ppp/ppp_debug.h index 9d6c91e2..caace4e6 100644 --- a/ppp/ppp_debug.h +++ b/ppp/ppp_debug.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _DHCP_DEBUG_H diff --git a/ppp/ppp_fsm.c b/ppp/ppp_fsm.c index 8bf36fdc..dfed0b21 100644 --- a/ppp/ppp_fsm.c +++ b/ppp/ppp_fsm.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ppp/ppp_fsm.h b/ppp/ppp_fsm.h index 260cb35f..61a04121 100644 --- a/ppp/ppp_fsm.h +++ b/ppp/ppp_fsm.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _PPP_FSM_H diff --git a/ppp/ppp_hdlc.c b/ppp/ppp_hdlc.c index 4f678ee4..d7ac6c35 100644 --- a/ppp/ppp_hdlc.c +++ b/ppp/ppp_hdlc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ppp/ppp_hdlc.h b/ppp/ppp_hdlc.h index 84fa7821..aab17a77 100644 --- a/ppp/ppp_hdlc.h +++ b/ppp/ppp_hdlc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _PPP_HDLC_H diff --git a/ppp/ppp_misc.c b/ppp/ppp_misc.c index 5d52608f..29917b5b 100644 --- a/ppp/ppp_misc.c +++ b/ppp/ppp_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/ppp/ppp_misc.h b/ppp/ppp_misc.h index 9c8d078c..a9d4d365 100644 --- a/ppp/ppp_misc.h +++ b/ppp/ppp_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _PPP_MISC_H diff --git a/smtp/smtp_client.c b/smtp/smtp_client.c index a4a1eeb3..a4caf1b8 100644 --- a/smtp/smtp_client.c +++ b/smtp/smtp_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -33,7 +33,7 @@ * - RFC 3207: SMTP Service Extension for Secure SMTP over TLS * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/smtp/smtp_client.h b/smtp/smtp_client.h index c84e78d2..29878ea5 100644 --- a/smtp/smtp_client.h +++ b/smtp/smtp_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SMTP_CLIENT_H diff --git a/smtp/smtp_client_auth.c b/smtp/smtp_client_auth.c index 5cc97b1b..bae1db64 100644 --- a/smtp/smtp_client_auth.c +++ b/smtp/smtp_client_auth.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/smtp/smtp_client_auth.h b/smtp/smtp_client_auth.h index 660f1154..64f3d42f 100644 --- a/smtp/smtp_client_auth.h +++ b/smtp/smtp_client_auth.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SMTP_CLIENT_AUTH_H diff --git a/smtp/smtp_client_misc.c b/smtp/smtp_client_misc.c index 8ab24115..1a3609f8 100644 --- a/smtp/smtp_client_misc.c +++ b/smtp/smtp_client_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/smtp/smtp_client_misc.h b/smtp/smtp_client_misc.h index 7a1d7b1b..a42a2c40 100644 --- a/smtp/smtp_client_misc.h +++ b/smtp/smtp_client_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SMTP_CLIENT_MISC_H diff --git a/smtp/smtp_client_transport.c b/smtp/smtp_client_transport.c index 7e4c2925..1a044510 100644 --- a/smtp/smtp_client_transport.c +++ b/smtp/smtp_client_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/smtp/smtp_client_transport.h b/smtp/smtp_client_transport.h index 5868d6b8..0b3055d2 100644 --- a/smtp/smtp_client_transport.h +++ b/smtp/smtp_client_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SMTP_CLIENT_TRANSPORT_H diff --git a/snmp/snmp_agent.c b/snmp/snmp_agent.c index a737874f..5102cdd9 100644 --- a/snmp/snmp_agent.c +++ b/snmp/snmp_agent.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -41,7 +41,7 @@ * SNMP Framework * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/snmp/snmp_agent.h b/snmp/snmp_agent.h index ea8446f7..cb0ccdcf 100644 --- a/snmp/snmp_agent.h +++ b/snmp/snmp_agent.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_AGENT_H diff --git a/snmp/snmp_agent_dispatch.c b/snmp/snmp_agent_dispatch.c index 77a69b5d..cd82c637 100644 --- a/snmp/snmp_agent_dispatch.c +++ b/snmp/snmp_agent_dispatch.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/snmp/snmp_agent_dispatch.h b/snmp/snmp_agent_dispatch.h index 0ef0c8c8..7cbbf818 100644 --- a/snmp/snmp_agent_dispatch.h +++ b/snmp/snmp_agent_dispatch.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_AGENT_DISPATCH_H diff --git a/snmp/snmp_agent_inform.c b/snmp/snmp_agent_inform.c index 5401cf52..f681efbd 100644 --- a/snmp/snmp_agent_inform.c +++ b/snmp/snmp_agent_inform.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/snmp/snmp_agent_inform.h b/snmp/snmp_agent_inform.h index d39cdf24..12fee042 100644 --- a/snmp/snmp_agent_inform.h +++ b/snmp/snmp_agent_inform.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_AGENT_INFORM_H diff --git a/snmp/snmp_agent_message.c b/snmp/snmp_agent_message.c index 2bc46585..37da982f 100644 --- a/snmp/snmp_agent_message.c +++ b/snmp/snmp_agent_message.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/snmp/snmp_agent_message.h b/snmp/snmp_agent_message.h index 22698863..00956510 100644 --- a/snmp/snmp_agent_message.h +++ b/snmp/snmp_agent_message.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_AGENT_MESSAGE_H diff --git a/snmp/snmp_agent_misc.c b/snmp/snmp_agent_misc.c index eeba71d9..34a9724e 100644 --- a/snmp/snmp_agent_misc.c +++ b/snmp/snmp_agent_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/snmp/snmp_agent_misc.h b/snmp/snmp_agent_misc.h index bf645217..ed8c68b8 100644 --- a/snmp/snmp_agent_misc.h +++ b/snmp/snmp_agent_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_AGENT_MISC_H diff --git a/snmp/snmp_agent_object.c b/snmp/snmp_agent_object.c index fa036fa0..567415ae 100644 --- a/snmp/snmp_agent_object.c +++ b/snmp/snmp_agent_object.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/snmp/snmp_agent_object.h b/snmp/snmp_agent_object.h index c826a169..65e015f6 100644 --- a/snmp/snmp_agent_object.h +++ b/snmp/snmp_agent_object.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_AGENT_OBJECT_H diff --git a/snmp/snmp_agent_pdu.c b/snmp/snmp_agent_pdu.c index 0dc88f03..cbefa1c7 100644 --- a/snmp/snmp_agent_pdu.c +++ b/snmp/snmp_agent_pdu.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/snmp/snmp_agent_pdu.h b/snmp/snmp_agent_pdu.h index af9c2319..072be90b 100644 --- a/snmp/snmp_agent_pdu.h +++ b/snmp/snmp_agent_pdu.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_AGENT_PDU_H diff --git a/snmp/snmp_agent_trap.c b/snmp/snmp_agent_trap.c index 21ec17fb..32d6a7b0 100644 --- a/snmp/snmp_agent_trap.c +++ b/snmp/snmp_agent_trap.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/snmp/snmp_agent_trap.h b/snmp/snmp_agent_trap.h index 8d60f800..3ecf81f3 100644 --- a/snmp/snmp_agent_trap.h +++ b/snmp/snmp_agent_trap.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_AGENT_TRAP_H diff --git a/snmp/snmp_agent_usm.c b/snmp/snmp_agent_usm.c index 5d26933e..e6e58445 100644 --- a/snmp/snmp_agent_usm.c +++ b/snmp/snmp_agent_usm.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -34,7 +34,7 @@ * - RFC 7860: HMAC-SHA-2 Authentication Protocols in the User-based Security Model * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/snmp/snmp_agent_usm.h b/snmp/snmp_agent_usm.h index e0b36b4c..84ecef6e 100644 --- a/snmp/snmp_agent_usm.h +++ b/snmp/snmp_agent_usm.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_AGENT_USM_H diff --git a/snmp/snmp_agent_vacm.c b/snmp/snmp_agent_vacm.c index cacf5ad3..111332ba 100644 --- a/snmp/snmp_agent_vacm.c +++ b/snmp/snmp_agent_vacm.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * Network Management Protocol (SNMP). Refer to RFC 3415 for complete details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/snmp/snmp_agent_vacm.h b/snmp/snmp_agent_vacm.h index 4d7692e4..c7463325 100644 --- a/snmp/snmp_agent_vacm.h +++ b/snmp/snmp_agent_vacm.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_AGENT_VACM_H diff --git a/snmp/snmp_common.h b/snmp/snmp_common.h index a75105b2..2fec169c 100644 --- a/snmp/snmp_common.h +++ b/snmp/snmp_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNMP_COMMON_H diff --git a/sntp/ntp_common.h b/sntp/ntp_common.h index 59f05938..2f4a2eeb 100644 --- a/sntp/ntp_common.h +++ b/sntp/ntp_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _NTP_COMMON_H diff --git a/sntp/sntp_client.c b/sntp/sntp_client.c index fc03778f..65f2450d 100644 --- a/sntp/sntp_client.c +++ b/sntp/sntp_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * in the Internet. Refer to RFC 4330 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/sntp/sntp_client.h b/sntp/sntp_client.h index 00a2245b..6d708182 100644 --- a/sntp/sntp_client.h +++ b/sntp/sntp_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNTP_CLIENT_H diff --git a/sntp/sntp_client_misc.c b/sntp/sntp_client_misc.c index 3c547eef..a50283f4 100644 --- a/sntp/sntp_client_misc.c +++ b/sntp/sntp_client_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -30,7 +30,7 @@ * in the Internet. Refer to RFC 4330 for more details * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/sntp/sntp_client_misc.h b/sntp/sntp_client_misc.h index c264b862..377032f5 100644 --- a/sntp/sntp_client_misc.h +++ b/sntp/sntp_client_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _SNTP_CLIENT_MISC_H diff --git a/tftp/tftp_client.c b/tftp/tftp_client.c index d92c94df..9282ec21 100644 --- a/tftp/tftp_client.c +++ b/tftp/tftp_client.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -35,7 +35,7 @@ * - RFC 1784: TFTP Timeout Interval and Transfer Size Options * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/tftp/tftp_client.h b/tftp/tftp_client.h index 387f65c9..1c9b4eb5 100644 --- a/tftp/tftp_client.h +++ b/tftp/tftp_client.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TFTP_CLIENT_H diff --git a/tftp/tftp_client_misc.c b/tftp/tftp_client_misc.c index 13dc1d52..fb1e1b94 100644 --- a/tftp/tftp_client_misc.c +++ b/tftp/tftp_client_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/tftp/tftp_client_misc.h b/tftp/tftp_client_misc.h index 0037f738..3cc8f429 100644 --- a/tftp/tftp_client_misc.h +++ b/tftp/tftp_client_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TFTP_CLIENT_MISC_H diff --git a/tftp/tftp_common.h b/tftp/tftp_common.h index f918dc91..bbb82a44 100644 --- a/tftp/tftp_common.h +++ b/tftp/tftp_common.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TFTP_COMMON_H diff --git a/tftp/tftp_server.c b/tftp/tftp_server.c index 737d3919..041e5818 100644 --- a/tftp/tftp_server.c +++ b/tftp/tftp_server.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -35,7 +35,7 @@ * - RFC 1784: TFTP Timeout Interval and Transfer Size Options * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/tftp/tftp_server.h b/tftp/tftp_server.h index 9f66fa9c..34182456 100644 --- a/tftp/tftp_server.h +++ b/tftp/tftp_server.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TFTP_SERVER_H diff --git a/tftp/tftp_server_misc.c b/tftp/tftp_server_misc.c index 82af1419..ded6fdf4 100644 --- a/tftp/tftp_server_misc.c +++ b/tftp/tftp_server_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/tftp/tftp_server_misc.h b/tftp/tftp_server_misc.h index af81488e..26d08799 100644 --- a/tftp/tftp_server_misc.h +++ b/tftp/tftp_server_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _TFTP_SERVER_MISC_H diff --git a/web_socket/web_socket.c b/web_socket/web_socket.c index 21a067d1..43507f6e 100644 --- a/web_socket/web_socket.c +++ b/web_socket/web_socket.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/web_socket/web_socket.h b/web_socket/web_socket.h index 0512e1ed..d24c151b 100644 --- a/web_socket/web_socket.h +++ b/web_socket/web_socket.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _WEB_SOCKET_H diff --git a/web_socket/web_socket_auth.c b/web_socket/web_socket_auth.c index 37c5d5cb..bd5f55d2 100644 --- a/web_socket/web_socket_auth.c +++ b/web_socket/web_socket_auth.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -98,7 +98,7 @@ error_t webSocketParseAuthenticateField(WebSocket *webSocket, char_t *value) while(token != NULL) { //Check whether a separator is present - separator = strchr(token, '='); + separator = osStrchr(token, '='); //Separator found? if(separator != NULL) diff --git a/web_socket/web_socket_auth.h b/web_socket/web_socket_auth.h index 0a88082f..0696088f 100644 --- a/web_socket/web_socket_auth.h +++ b/web_socket/web_socket_auth.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _WEB_SOCKET_AUTH_H diff --git a/web_socket/web_socket_frame.c b/web_socket/web_socket_frame.c index b29650d7..ad064cc1 100644 --- a/web_socket/web_socket_frame.c +++ b/web_socket/web_socket_frame.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/web_socket/web_socket_frame.h b/web_socket/web_socket_frame.h index f8a1ea70..6a9ab0ed 100644 --- a/web_socket/web_socket_frame.h +++ b/web_socket/web_socket_frame.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _WEB_SOCKET_FRAME_H diff --git a/web_socket/web_socket_misc.c b/web_socket/web_socket_misc.c index 99e53ea8..495fc5b6 100644 --- a/web_socket/web_socket_misc.c +++ b/web_socket/web_socket_misc.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level @@ -390,7 +390,7 @@ error_t webSocketParseRequestLine(WebSocket *webSocket, char_t *line) return ERROR_INVALID_REQUEST; //Check whether a query string is present - s = strchr(token, '?'); + s = osStrchr(token, '?'); //Query string found? if(s != NULL) @@ -523,7 +523,7 @@ error_t webSocketParseHeaderField(WebSocket *webSocket, char_t *line) TRACE_DEBUG("%s", line); //Check whether a separator is present - separator = strchr(line, ':'); + separator = osStrchr(line, ':'); //Separator found? if(separator != NULL) diff --git a/web_socket/web_socket_misc.h b/web_socket/web_socket_misc.h index 2182b472..e7d0ae63 100644 --- a/web_socket/web_socket_misc.h +++ b/web_socket/web_socket_misc.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _WEB_SOCKET_MISC_H diff --git a/web_socket/web_socket_transport.c b/web_socket/web_socket_transport.c index 92ef84e4..c9025106 100644 --- a/web_socket/web_socket_transport.c +++ b/web_socket/web_socket_transport.c @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ //Switch to the appropriate trace level diff --git a/web_socket/web_socket_transport.h b/web_socket/web_socket_transport.h index f002cac6..6121f0db 100644 --- a/web_socket/web_socket_transport.h +++ b/web_socket/web_socket_transport.h @@ -6,7 +6,7 @@ * * SPDX-License-Identifier: GPL-2.0-or-later * - * Copyright (C) 2010-2020 Oryx Embedded SARL. All rights reserved. + * Copyright (C) 2010-2021 Oryx Embedded SARL. All rights reserved. * * This file is part of CycloneTCP Open. * @@ -25,7 +25,7 @@ * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. * * @author Oryx Embedded SARL (www.oryx-embedded.com) - * @version 2.0.0 + * @version 2.0.2 **/ #ifndef _WEB_SOCKET_TRANSPORT_H