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dmac: madr msb bit is fixed to 0 in 8/9 channels

Fix another dmac tests :)
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1 parent b2fbbdd commit 5efbf2a8023432d4ff6f9564e77eda7714c4f91d @gregory38 gregory38 committed Jan 28, 2016
Showing with 14 additions and 0 deletions.
  1. +14 −0 pcsx2/ps2/LegacyDmac.cpp
@@ -374,6 +374,20 @@ __fi bool dmacWrite32( u32 mem, mem32_t& value )
return false;
}
+ icase(fromSPR_MADR)
+ {
+ // SPR bit is fixed at 0 for this channel
+ psHu32(mem) = value & 0x7FFFFFFF;
+ return false;
+ }
+
+ icase(toSPR_MADR)
+ {
+ // SPR bit is fixed at 0 for this channel
+ psHu32(mem) = value & 0x7FFFFFFF;
+ return false;
+ }
+
icase(fromSPR_SADR)
{
// Address must be QW aligned and fit in the 16K range of SPR

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