{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":502944312,"defaultBranch":"main","name":"DisplayPort","ownerLogin":"Parretto","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2022-06-13T12:21:02.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/99640102?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1673511596.524363","currentOid":""},"activityList":{"items":[{"before":"227618bba33f6d3dfbfe5a92753a7e47d75f66ac","after":"ddadb15dc3d448780417d302f0155fbb1d70896f","ref":"refs/heads/main","pushedAt":"2024-05-22T17:45:50.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Added training clock recovery callback\nAdded DPRX spread spectrum option\nImproved DPRX link training","shortMessageHtmlLink":"Added training clock recovery callback"}},{"before":"9d03b9832203530fdc3aeee6b13d715ff9f1ec61","after":"227618bba33f6d3dfbfe5a92753a7e47d75f66ac","ref":"refs/heads/main","pushedAt":"2024-04-23T09:10:03.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"DPRX: Increased EDID size to 1024 bytes","shortMessageHtmlLink":"DPRX: Increased EDID size to 1024 bytes"}},{"before":"3f82d8a60162b74239b56c209b78516885da9d08","after":"9d03b9832203530fdc3aeee6b13d715ff9f1ec61","ref":"refs/heads/main","pushedAt":"2024-04-23T09:00:50.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"DPRX: increased EDID size to 1024 bytes","shortMessageHtmlLink":"DPRX: increased EDID size to 1024 bytes"}},{"before":"67a40db1344f4fabc7fbd860c9367413730ac7d3","after":"3f82d8a60162b74239b56c209b78516885da9d08","ref":"refs/heads/main","pushedAt":"2024-03-18T08:45:23.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Updated AMD PHY GTH driver","shortMessageHtmlLink":"Updated AMD PHY GTH driver"}},{"before":"f60b292bb61923582b90eabef3a8bc4bc797a9fd","after":"67a40db1344f4fabc7fbd860c9367413730ac7d3","ref":"refs/heads/main","pushedAt":"2024-03-15T15:59:44.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Updated AMD ZCU102 reference design with 270 MHZ GT reference clock","shortMessageHtmlLink":"Updated AMD ZCU102 reference design with 270 MHZ GT reference clock"}},{"before":"bc377ef19916363136bc98836fc810e808eb0038","after":"f60b292bb61923582b90eabef3a8bc4bc797a9fd","ref":"refs/heads/main","pushedAt":"2024-02-26T19:58:18.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Added video resolution 7680x4320P30\nModified PHY controller with PIO\nImproved performance of DPTX and DPRX video modules","shortMessageHtmlLink":"Added video resolution 7680x4320P30"}},{"before":"43e8cddabf4f7fb555937dfc2d89e4c46c9bd42a","after":"bc377ef19916363136bc98836fc810e808eb0038","ref":"refs/heads/main","pushedAt":"2024-01-28T13:26:37.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Added 10-bits video for DPTX and DPRX\nAdded software folder (DP application and driver)","shortMessageHtmlLink":"Added 10-bits video for DPTX and DPRX"}},{"before":"5986249266b05511db14a1c22d3e53cc04336fee","after":"43e8cddabf4f7fb555937dfc2d89e4c46c9bd42a","ref":"refs/heads/main","pushedAt":"2023-12-21T15:51:44.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Added support for Artix-7 GTP\nAdded TPS4 TX link training","shortMessageHtmlLink":"Added support for Artix-7 GTP"}},{"before":"db44875765558c33078744d7edf9abd9b8735057","after":"5986249266b05511db14a1c22d3e53cc04336fee","ref":"refs/heads/main","pushedAt":"2023-11-30T10:46:47.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Updated AMD DP application","shortMessageHtmlLink":"Updated AMD DP application"}},{"before":"12613d2617bff5545c0460f4faaf434eed0d2de1","after":"db44875765558c33078744d7edf9abd9b8735057","ref":"refs/heads/main","pushedAt":"2023-10-29T19:09:20.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Updated Lattice Local dimming reference design","shortMessageHtmlLink":"Updated Lattice Local dimming reference design"}},{"before":"16c5c644dc5d7d0dff7307c4c9081b1422816dc5","after":"12613d2617bff5545c0460f4faaf434eed0d2de1","ref":"refs/heads/main","pushedAt":"2023-09-20T07:50:45.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Upgraded with latest source files.\nAdded support for Intel Arria 10 GX.\nFixed compilation issue for Lattice with SynplifyPro synthesis.","shortMessageHtmlLink":"Upgraded with latest source files."}},{"before":"1a24f03b02f664051ae309b233bfe08dcddb738a","after":"16c5c644dc5d7d0dff7307c4c9081b1422816dc5","ref":"refs/heads/main","pushedAt":"2023-07-03T20:38:47.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Intel DP reference design: Removed global clock buffer (Quartus Prime Pro 23.2 fix)","shortMessageHtmlLink":"Intel DP reference design: Removed global clock buffer (Quartus Prime…"}},{"before":"36927875c52bff104b96ee65632c542e7d407dea","after":"1a24f03b02f664051ae309b233bfe08dcddb738a","ref":"refs/heads/main","pushedAt":"2023-06-28T08:21:03.519Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Updated README","shortMessageHtmlLink":"Updated README"}},{"before":"a05c07bd128ee4406e42917dd3e8a1b8a9dd82de","after":"36927875c52bff104b96ee65632c542e7d407dea","ref":"refs/heads/main","pushedAt":"2023-06-26T15:09:31.388Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Synchronized Lattice RPI design with latest DP","shortMessageHtmlLink":"Synchronized Lattice RPI design with latest DP"}},{"before":"e2b8d7d4b5a4fe29f6caacda658ba380a3916f1c","after":"a05c07bd128ee4406e42917dd3e8a1b8a9dd82de","ref":"refs/heads/main","pushedAt":"2023-06-22T08:27:39.133Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Released Lattice Raspberry PI with local dimming reference design","shortMessageHtmlLink":"Released Lattice Raspberry PI with local dimming reference design"}},{"before":"fe7f2a953de35b7f7b4d22846f5d534a38f38fdc","after":"e2b8d7d4b5a4fe29f6caacda658ba380a3916f1c","ref":"refs/heads/main","pushedAt":"2023-05-12T18:18:59.984Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Added support for Intel Cyclone 10 GX\nUpdated FPGA vendor names","shortMessageHtmlLink":"Added support for Intel Cyclone 10 GX"}},{"before":"704f78a1662b45ec296675159e282d8f3bf9a4d3","after":"fe7f2a953de35b7f7b4d22846f5d534a38f38fdc","ref":"refs/heads/main","pushedAt":"2023-03-22T10:32:32.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"Parretto","name":"Parretto","path":"/Parretto","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/99640102?s=80&v=4"},"commit":{"message":"Added simulation folder","shortMessageHtmlLink":"Added simulation folder"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEUTl07AA","startCursor":null,"endCursor":null}},"title":"Activity · Parretto/DisplayPort"}