{"payload":{"header_redesign_enabled":false,"results":[{"id":"502944312","archived":false,"color":"#b2b7f8","followers":38,"has_funding_file":false,"hl_name":"Parretto/DisplayPort","hl_trunc_description":"DisplayPort IP-core","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":502944312,"name":"DisplayPort","owner_id":99640102,"owner_login":"Parretto","updated_at":"2024-05-22T17:45:50.519Z","has_issues":false}},"sponsorable":false,"topics":["fpga","xilinx","lattice","ip-core","displayport"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":94,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AParretto%252FDisplayPort%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/Parretto/DisplayPort/star":{"post":"UEg7JQw67VJ1BEsrGx802JUCCC0LincK-uPZUKCFYmh1fi5x8a-SqHZlTq0VzZMoO6LdvMrE0ub_Aa8uMjsMfw"},"/Parretto/DisplayPort/unstar":{"post":"17pjKTIV4Sad4WD55Pjib2hxdqPdX0OfsOVJVbK51W9pV5wLhIS7TqaJdQVBx9ggHdS9S4MhoPmg-7Ye0os3UQ"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"M1gVk6sOCmdQJaVDJqUJwsKUwSaUYS2-4QvABXhDO3QDz145h8ZJ54QZiulCd-esh_1DZKT4hO4CFXWBOJNpqA"}}},"title":"Repository search results"}