I2C EEPROM Emulation for Smart Devicetrees - a Reference Design
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I2C_Devicetree
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README.md

README.md

I2C_Devicetree

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I2C_Devicetree The I2C_Devicetree reference design project uses a programmable System-on-Chip (SoC) with a Cortex-M0 CPU, in a small 28 Pin TSSOP package, to emulate an I2C EEPROM using the FLASH memory of the SoC, which creates an "intelligent memory" device. The I2C_Devicetree reference design project is intended to make it easier for people to create their own custom expansion boards for Beaglebone, Raspberry Pi and other platforms that require the use of a Devicetree EEPROM for automatic product identification, pin mapping, and configuration on the Linux Operating System. The I2C_Devicetree reference design project also includes an I2C I/O Expander to provide extra GPIO pins that are I2C controlled.

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I2C_Devicetree