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T4 async support #45

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merged 2 commits into from Feb 3, 2019

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commented Jan 31, 2019

Asynch SPI.transfer support for Teensy 4.0 beta board.

Includes "hack" that if the tx_buffer address is > 0x20200000 it will call system function to flush the cache.

Likewise if the rx_buffer is > than same address it will call system function to delete the cache for that region...

KurtE added some commits Jan 31, 2019

First pass - Teensy 4 Async transfer support
Still testing and running into memory usage issues, but I think some of the basics are working.  Still need to do more testing, including verifying on larger buffers.
T4 - Async updates - Hack for high memory...
If a buffer is up in the high memory, that is either in the area marked DMARAM or created by malloc and you try to do a SPI transfer using DMA, the code detects the addresses >= 0x20200000 and then calls the system functions to either flush the cache or delete the cache on the read...

@PaulStoffregen PaulStoffregen merged commit 70c832a into PaulStoffregen:master Feb 3, 2019

@KurtE KurtE deleted the KurtE:T4_Async_Support branch Feb 3, 2019

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