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/* Teensyduino Core Library
* http://www.pjrc.com/teensy/
* Copyright (c) 2017 PJRC.COM, LLC.
*
* Permission is hereby granted, free of charge, to any person obtaining
* a copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* 1. The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* 2. If the Software is incorporated into a build system that allows
* selection among a list of target devices, then similar target
* devices manufactured by PJRC.COM must be included in the list of
* target devices and selectable in the same manner.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef _kinetis_h_
#define _kinetis_h_
#include <stdint.h>
// Teensy 3.0
#if defined(__MK20DX128__)
enum IRQ_NUMBER_t {
IRQ_DMA_CH0 = 0,
IRQ_DMA_CH1 = 1,
IRQ_DMA_CH2 = 2,
IRQ_DMA_CH3 = 3,
IRQ_DMA_ERROR = 4,
IRQ_FTFL_COMPLETE = 6,
IRQ_FTFL_COLLISION = 7,
IRQ_LOW_VOLTAGE = 8,
IRQ_LLWU = 9,
IRQ_WDOG = 10,
IRQ_I2C0 = 11,
IRQ_SPI0 = 12,
IRQ_I2S0_TX = 13,
IRQ_I2S0_RX = 14,
IRQ_UART0_LON = 15,
IRQ_UART0_STATUS = 16,
IRQ_UART0_ERROR = 17,
IRQ_UART1_STATUS = 18,
IRQ_UART1_ERROR = 19,
IRQ_UART2_STATUS = 20,
IRQ_UART2_ERROR = 21,
IRQ_ADC0 = 22,
IRQ_CMP0 = 23,
IRQ_CMP1 = 24,
IRQ_FTM0 = 25,
IRQ_FTM1 = 26,
IRQ_CMT = 27,
IRQ_RTC_ALARM = 28,
IRQ_RTC_SECOND = 29,
IRQ_PIT_CH0 = 30,
IRQ_PIT_CH1 = 31,
IRQ_PIT_CH2 = 32,
IRQ_PIT_CH3 = 33,
IRQ_PDB = 34,
IRQ_USBOTG = 35,
IRQ_USBDCD = 36,
IRQ_TSI = 37,
IRQ_MCG = 38,
IRQ_LPTMR = 39,
IRQ_PORTA = 40,
IRQ_PORTB = 41,
IRQ_PORTC = 42,
IRQ_PORTD = 43,
IRQ_PORTE = 44,
IRQ_SOFTWARE = 45
};
#define NVIC_NUM_INTERRUPTS 46
#define DMA_NUM_CHANNELS 4
#define DMAMUX_SOURCE_UART0_RX 2
#define DMAMUX_SOURCE_UART0_TX 3
#define DMAMUX_SOURCE_UART1_RX 4
#define DMAMUX_SOURCE_UART1_TX 5
#define DMAMUX_SOURCE_UART2_RX 6
#define DMAMUX_SOURCE_UART2_TX 7
#define DMAMUX_SOURCE_I2S0_RX 14
#define DMAMUX_SOURCE_I2S0_TX 15
#define DMAMUX_SOURCE_SPI0_RX 16
#define DMAMUX_SOURCE_SPI0_TX 17
#define DMAMUX_SOURCE_I2C0 22
#define DMAMUX_SOURCE_FTM0_CH0 24
#define DMAMUX_SOURCE_FTM0_CH1 25
#define DMAMUX_SOURCE_FTM0_CH2 26
#define DMAMUX_SOURCE_FTM0_CH3 27
#define DMAMUX_SOURCE_FTM0_CH4 28
#define DMAMUX_SOURCE_FTM0_CH5 29
#define DMAMUX_SOURCE_FTM0_CH6 30
#define DMAMUX_SOURCE_FTM0_CH7 31
#define DMAMUX_SOURCE_FTM1_CH0 32
#define DMAMUX_SOURCE_FTM1_CH1 33
#define DMAMUX_SOURCE_ADC0 40
#define DMAMUX_SOURCE_CMP0 42
#define DMAMUX_SOURCE_CMP1 43
#define DMAMUX_SOURCE_DAC0 45
#define DMAMUX_SOURCE_CMT 47
#define DMAMUX_SOURCE_PDB 48
#define DMAMUX_SOURCE_PORTA 49
#define DMAMUX_SOURCE_PORTB 50
#define DMAMUX_SOURCE_PORTC 51
#define DMAMUX_SOURCE_PORTD 52
#define DMAMUX_SOURCE_PORTE 53
#define DMAMUX_SOURCE_ALWAYS0 54
#define DMAMUX_SOURCE_ALWAYS1 55
#define DMAMUX_SOURCE_ALWAYS2 56
#define DMAMUX_SOURCE_ALWAYS3 57
#define DMAMUX_SOURCE_ALWAYS4 58
#define DMAMUX_SOURCE_ALWAYS5 59
#define DMAMUX_SOURCE_ALWAYS6 60
#define DMAMUX_SOURCE_ALWAYS7 61
#define DMAMUX_SOURCE_ALWAYS8 62
#define DMAMUX_SOURCE_ALWAYS9 63
#define DMAMUX_NUM_SOURCE_ALWAYS 10
#define KINETISK
#define HAS_KINETISK_UART0
#define HAS_KINETISK_UART0_FIFO
#define HAS_KINETISK_UART1
#define HAS_KINETISK_UART2
#define HAS_KINETIS_I2C0
#define HAS_KINETIS_LLWU_16CH
#define HAS_KINETIS_ADC0
#define HAS_KINETIS_TSI
#define HAS_KINETIS_FLASH_FTFL
// Teensy 3.1 & 3.2
#elif defined(__MK20DX256__)
enum IRQ_NUMBER_t {
IRQ_DMA_CH0 = 0,
IRQ_DMA_CH1 = 1,
IRQ_DMA_CH2 = 2,
IRQ_DMA_CH3 = 3,
IRQ_DMA_CH4 = 4,
IRQ_DMA_CH5 = 5,
IRQ_DMA_CH6 = 6,
IRQ_DMA_CH7 = 7,
IRQ_DMA_CH8 = 8,
IRQ_DMA_CH9 = 9,
IRQ_DMA_CH10 = 10,
IRQ_DMA_CH11 = 11,
IRQ_DMA_CH12 = 12,
IRQ_DMA_CH13 = 13,
IRQ_DMA_CH14 = 14,
IRQ_DMA_CH15 = 15,
IRQ_DMA_ERROR = 16,
IRQ_FTFL_COMPLETE = 18,
IRQ_FTFL_COLLISION = 19,
IRQ_LOW_VOLTAGE = 20,
IRQ_LLWU = 21,
IRQ_WDOG = 22,
IRQ_I2C0 = 24,
IRQ_I2C1 = 25,
IRQ_SPI0 = 26,
IRQ_SPI1 = 27,
IRQ_CAN_MESSAGE = 29,
IRQ_CAN_BUS_OFF = 30,
IRQ_CAN_ERROR = 31,
IRQ_CAN_TX_WARN = 32,
IRQ_CAN_RX_WARN = 33,
IRQ_CAN_WAKEUP = 34,
IRQ_I2S0_TX = 35,
IRQ_I2S0_RX = 36,
IRQ_UART0_LON = 44,
IRQ_UART0_STATUS = 45,
IRQ_UART0_ERROR = 46,
IRQ_UART1_STATUS = 47,
IRQ_UART1_ERROR = 48,
IRQ_UART2_STATUS = 49,
IRQ_UART2_ERROR = 50,
IRQ_ADC0 = 57,
IRQ_ADC1 = 58,
IRQ_CMP0 = 59,
IRQ_CMP1 = 60,
IRQ_CMP2 = 61,
IRQ_FTM0 = 62,
IRQ_FTM1 = 63,
IRQ_FTM2 = 64,
IRQ_CMT = 65,
IRQ_RTC_ALARM = 66,
IRQ_RTC_SECOND = 67,
IRQ_PIT_CH0 = 68,
IRQ_PIT_CH1 = 69,
IRQ_PIT_CH2 = 70,
IRQ_PIT_CH3 = 71,
IRQ_PDB = 72,
IRQ_USBOTG = 73,
IRQ_USBDCD = 74,
IRQ_DAC0 = 81,
IRQ_TSI = 83,
IRQ_MCG = 84,
IRQ_LPTMR = 85,
IRQ_PORTA = 87,
IRQ_PORTB = 88,
IRQ_PORTC = 89,
IRQ_PORTD = 90,
IRQ_PORTE = 91,
IRQ_SOFTWARE = 94
};
#define NVIC_NUM_INTERRUPTS 95
#define DMA_NUM_CHANNELS 16
#define DMAMUX_SOURCE_UART0_RX 2
#define DMAMUX_SOURCE_UART0_TX 3
#define DMAMUX_SOURCE_UART1_RX 4
#define DMAMUX_SOURCE_UART1_TX 5
#define DMAMUX_SOURCE_UART2_RX 6
#define DMAMUX_SOURCE_UART2_TX 7
#define DMAMUX_SOURCE_I2S0_RX 14
#define DMAMUX_SOURCE_I2S0_TX 15
#define DMAMUX_SOURCE_SPI0_RX 16
#define DMAMUX_SOURCE_SPI0_TX 17
#define DMAMUX_SOURCE_SPI1_RX 18
#define DMAMUX_SOURCE_SPI1_TX 19
#define DMAMUX_SOURCE_I2C0 22
#define DMAMUX_SOURCE_I2C1 23
#define DMAMUX_SOURCE_FTM0_CH0 24
#define DMAMUX_SOURCE_FTM0_CH1 25
#define DMAMUX_SOURCE_FTM0_CH2 26
#define DMAMUX_SOURCE_FTM0_CH3 27
#define DMAMUX_SOURCE_FTM0_CH4 28
#define DMAMUX_SOURCE_FTM0_CH5 29
#define DMAMUX_SOURCE_FTM0_CH6 30
#define DMAMUX_SOURCE_FTM0_CH7 31
#define DMAMUX_SOURCE_FTM1_CH0 32
#define DMAMUX_SOURCE_FTM1_CH1 33
#define DMAMUX_SOURCE_FTM2_CH0 34
#define DMAMUX_SOURCE_FTM2_CH1 35
#define DMAMUX_SOURCE_ADC0 40
#define DMAMUX_SOURCE_ADC1 41
#define DMAMUX_SOURCE_CMP0 42
#define DMAMUX_SOURCE_CMP1 43
#define DMAMUX_SOURCE_CMP2 44
#define DMAMUX_SOURCE_DAC0 45
#define DMAMUX_SOURCE_CMT 47
#define DMAMUX_SOURCE_PDB 48
#define DMAMUX_SOURCE_PORTA 49
#define DMAMUX_SOURCE_PORTB 50
#define DMAMUX_SOURCE_PORTC 51
#define DMAMUX_SOURCE_PORTD 52
#define DMAMUX_SOURCE_PORTE 53
#define DMAMUX_SOURCE_ALWAYS0 54
#define DMAMUX_SOURCE_ALWAYS1 55
#define DMAMUX_SOURCE_ALWAYS2 56
#define DMAMUX_SOURCE_ALWAYS3 57
#define DMAMUX_SOURCE_ALWAYS4 58
#define DMAMUX_SOURCE_ALWAYS5 59
#define DMAMUX_SOURCE_ALWAYS6 60
#define DMAMUX_SOURCE_ALWAYS7 61
#define DMAMUX_SOURCE_ALWAYS8 62
#define DMAMUX_SOURCE_ALWAYS9 63
#define DMAMUX_NUM_SOURCE_ALWAYS 10
#define KINETISK
#define HAS_KINETISK_UART0
#define HAS_KINETISK_UART0_FIFO
#define HAS_KINETISK_UART1
#define HAS_KINETISK_UART1_FIFO
#define HAS_KINETISK_UART2
#define HAS_KINETIS_I2C0
#define HAS_KINETIS_I2C1
#define HAS_KINETIS_LLWU_16CH
#define HAS_KINETIS_ADC0
#define HAS_KINETIS_ADC1
#define HAS_KINETIS_TSI
#define HAS_KINETIS_FLASH_FTFL
// Teensy-LC
#elif defined(__MKL26Z64__)
enum IRQ_NUMBER_t {
IRQ_DMA_CH0 = 0,
IRQ_DMA_CH1 = 1,
IRQ_DMA_CH2 = 2,
IRQ_DMA_CH3 = 3,
IRQ_FTFA = 5,
IRQ_LOW_VOLTAGE = 6,
IRQ_LLWU = 7,
IRQ_I2C0 = 8,
IRQ_I2C1 = 9,
IRQ_SPI0 = 10,
IRQ_SPI1 = 11,
IRQ_UART0_STATUS = 12,
IRQ_UART1_STATUS = 13,
IRQ_UART2_STATUS = 14,
IRQ_ADC0 = 15,
IRQ_CMP0 = 16,
IRQ_FTM0 = 17,
IRQ_FTM1 = 18,
IRQ_FTM2 = 19,
IRQ_RTC_ALARM = 20,
IRQ_RTC_SECOND = 21,
IRQ_PIT = 22,
IRQ_I2S0 = 23,
IRQ_USBOTG = 24,
IRQ_DAC0 = 25,
IRQ_TSI = 26,
IRQ_MCG = 27,
IRQ_LPTMR = 28,
IRQ_SOFTWARE = 29, // TODO: verify this works
IRQ_PORTA = 30,
IRQ_PORTCD = 31
};
#define NVIC_NUM_INTERRUPTS 32
#define DMA_NUM_CHANNELS 4
#define DMAMUX_SOURCE_UART0_RX 2
#define DMAMUX_SOURCE_UART0_TX 3
#define DMAMUX_SOURCE_UART1_RX 4
#define DMAMUX_SOURCE_UART1_TX 5
#define DMAMUX_SOURCE_UART2_RX 6
#define DMAMUX_SOURCE_UART2_TX 7
#define DMAMUX_SOURCE_I2S0_RX 14
#define DMAMUX_SOURCE_I2S0_TX 15
#define DMAMUX_SOURCE_SPI0_RX 16
#define DMAMUX_SOURCE_SPI0_TX 17
#define DMAMUX_SOURCE_SPI1_RX 18
#define DMAMUX_SOURCE_SPI1_TX 19
#define DMAMUX_SOURCE_I2C0 22
#define DMAMUX_SOURCE_I2C1 23
#define DMAMUX_SOURCE_TPM0_CH0 24
#define DMAMUX_SOURCE_TPM0_CH1 25
#define DMAMUX_SOURCE_TPM0_CH2 26
#define DMAMUX_SOURCE_TPM0_CH3 27
#define DMAMUX_SOURCE_TPM0_CH4 28
#define DMAMUX_SOURCE_TPM0_CH5 29
#define DMAMUX_SOURCE_TPM1_CH0 32
#define DMAMUX_SOURCE_TPM1_CH1 33
#define DMAMUX_SOURCE_TPM2_CH0 34
#define DMAMUX_SOURCE_TPM2_CH1 35
#define DMAMUX_SOURCE_ADC0 40
#define DMAMUX_SOURCE_CMP0 42
#define DMAMUX_SOURCE_DAC0 45
#define DMAMUX_SOURCE_PORTA 49
#define DMAMUX_SOURCE_PORTC 51
#define DMAMUX_SOURCE_PORTD 52
#define DMAMUX_SOURCE_FTM0_OV 54
#define DMAMUX_SOURCE_FTM1_OV 55
#define DMAMUX_SOURCE_FTM2_OV 56
#define DMAMUX_SOURCE_TSI 57
#define DMAMUX_SOURCE_ALWAYS0 60
#define DMAMUX_SOURCE_ALWAYS1 61
#define DMAMUX_SOURCE_ALWAYS2 62
#define DMAMUX_SOURCE_ALWAYS3 63
#define DMAMUX_NUM_SOURCE_ALWAYS 4
#define KINETISL
#define HAS_KINETISL_UART0
#define HAS_KINETISL_UART1
#define HAS_KINETISL_UART2
#define HAS_KINETIS_I2C0
#define HAS_KINETIS_I2C0_STOPF
#define HAS_KINETIS_I2C1
#define HAS_KINETIS_I2C1_STOPF
#define HAS_KINETIS_LLWU_16CH
#define HAS_KINETIS_ADC0
#define HAS_KINETIS_TSI_LITE
#define HAS_KINETIS_FLASH_FTFA
#elif defined(__MK64FX512__)
enum IRQ_NUMBER_t {
IRQ_DMA_CH0 = 0,
IRQ_DMA_CH1 = 1,
IRQ_DMA_CH2 = 2,
IRQ_DMA_CH3 = 3,
IRQ_DMA_CH4 = 4,
IRQ_DMA_CH5 = 5,
IRQ_DMA_CH6 = 6,
IRQ_DMA_CH7 = 7,
IRQ_DMA_CH8 = 8,
IRQ_DMA_CH9 = 9,
IRQ_DMA_CH10 = 10,
IRQ_DMA_CH11 = 11,
IRQ_DMA_CH12 = 12,
IRQ_DMA_CH13 = 13,
IRQ_DMA_CH14 = 14,
IRQ_DMA_CH15 = 15,
IRQ_DMA_ERROR = 16,
IRQ_MCM = 17,
IRQ_FTFL_COMPLETE = 18,
IRQ_FTFL_COLLISION = 19,
IRQ_LOW_VOLTAGE = 20,
IRQ_LLWU = 21,
IRQ_WDOG = 22,
IRQ_RNG = 23,
IRQ_I2C0 = 24,
IRQ_I2C1 = 25,
IRQ_SPI0 = 26,
IRQ_SPI1 = 27,
IRQ_I2S0_TX = 28,
IRQ_I2S0_RX = 29,
IRQ_UART0_STATUS = 31,
IRQ_UART0_ERROR = 32,
IRQ_UART1_STATUS = 33,
IRQ_UART1_ERROR = 34,
IRQ_UART2_STATUS = 35,
IRQ_UART2_ERROR = 36,
IRQ_UART3_STATUS = 37,
IRQ_UART3_ERROR = 38,
IRQ_ADC0 = 39,
IRQ_CMP0 = 40,
IRQ_CMP1 = 41,
IRQ_FTM0 = 42,
IRQ_FTM1 = 43,
IRQ_FTM2 = 44,
IRQ_CMT = 45,
IRQ_RTC_ALARM = 46,
IRQ_RTC_SECOND = 47,
IRQ_PIT_CH0 = 48,
IRQ_PIT_CH1 = 49,
IRQ_PIT_CH2 = 50,
IRQ_PIT_CH3 = 51,
IRQ_PDB = 52,
IRQ_USBOTG = 53,
IRQ_USBDCD = 54,
IRQ_DAC0 = 56,
IRQ_MCG = 57,
IRQ_LPTMR = 58,
IRQ_PORTA = 59,
IRQ_PORTB = 60,
IRQ_PORTC = 61,
IRQ_PORTD = 62,
IRQ_PORTE = 63,
IRQ_SOFTWARE = 64,
IRQ_SPI2 = 65,
IRQ_UART4_STATUS = 66,
IRQ_UART4_ERROR = 67,
IRQ_UART5_STATUS = 68,
IRQ_UART5_ERROR = 69,
IRQ_CMP2 = 70,
IRQ_FTM3 = 71,
IRQ_DAC1 = 72,
IRQ_ADC1 = 73,
IRQ_I2C2 = 74,
IRQ_CAN0_MESSAGE = 75,
IRQ_CAN0_BUS_OFF = 76,
IRQ_CAN0_ERROR = 77,
IRQ_CAN0_TX_WARN = 78,
IRQ_CAN0_RX_WARN = 79,
IRQ_CAN0_WAKEUP = 80,
IRQ_SDHC = 81,
IRQ_ENET_TIMER = 82,
IRQ_ENET_TX = 83,
IRQ_ENET_RX = 84,
IRQ_ENET_ERROR = 85
};
#define NVIC_NUM_INTERRUPTS 86
#define DMA_NUM_CHANNELS 16
#define DMAMUX_SOURCE_TSI 1
#define DMAMUX_SOURCE_UART0_RX 2
#define DMAMUX_SOURCE_UART0_TX 3
#define DMAMUX_SOURCE_UART1_RX 4
#define DMAMUX_SOURCE_UART1_TX 5
#define DMAMUX_SOURCE_UART2_RX 6
#define DMAMUX_SOURCE_UART2_TX 7
#define DMAMUX_SOURCE_UART3_RX 8
#define DMAMUX_SOURCE_UART3_TX 9
#define DMAMUX_SOURCE_UART4_RXTX 10
#define DMAMUX_SOURCE_UART5_RXTX 11
#define DMAMUX_SOURCE_I2S0_RX 12
#define DMAMUX_SOURCE_I2S0_TX 13
#define DMAMUX_SOURCE_SPI0_RX 14
#define DMAMUX_SOURCE_SPI0_TX 15
#define DMAMUX_SOURCE_SPI1 16
#define DMAMUX_SOURCE_SPI2 17
#define DMAMUX_SOURCE_I2C0 18
#define DMAMUX_SOURCE_I2C1 19
#define DMAMUX_SOURCE_I2C2 19
#define DMAMUX_SOURCE_FTM0_CH0 20
#define DMAMUX_SOURCE_FTM0_CH1 21
#define DMAMUX_SOURCE_FTM0_CH2 22
#define DMAMUX_SOURCE_FTM0_CH3 23
#define DMAMUX_SOURCE_FTM0_CH4 24
#define DMAMUX_SOURCE_FTM0_CH5 25
#define DMAMUX_SOURCE_FTM0_CH6 26
#define DMAMUX_SOURCE_FTM0_CH7 27
#define DMAMUX_SOURCE_FTM1_CH0 28
#define DMAMUX_SOURCE_FTM1_CH1 29
#define DMAMUX_SOURCE_FTM2_CH0 30
#define DMAMUX_SOURCE_FTM2_CH1 31
#define DMAMUX_SOURCE_FTM3_CH0 32
#define DMAMUX_SOURCE_FTM3_CH1 33
#define DMAMUX_SOURCE_FTM3_CH2 34
#define DMAMUX_SOURCE_FTM3_CH3 35
#define DMAMUX_SOURCE_FTM3_CH4 36
#define DMAMUX_SOURCE_FTM3_CH5 37
#define DMAMUX_SOURCE_FTM3_CH6 38
#define DMAMUX_SOURCE_FTM3_CH7 39
#define DMAMUX_SOURCE_ADC0 40
#define DMAMUX_SOURCE_ADC1 41
#define DMAMUX_SOURCE_CMP0 42
#define DMAMUX_SOURCE_CMP1 43
#define DMAMUX_SOURCE_CMP2 44
#define DMAMUX_SOURCE_DAC0 45
#define DMAMUX_SOURCE_DAC1 46
#define DMAMUX_SOURCE_CMT 47
#define DMAMUX_SOURCE_PDB 48
#define DMAMUX_SOURCE_PORTA 49
#define DMAMUX_SOURCE_PORTB 50
#define DMAMUX_SOURCE_PORTC 51
#define DMAMUX_SOURCE_PORTD 52
#define DMAMUX_SOURCE_PORTE 53
#define DMAMUX_SOURCE_IEEE1588_T0 54
#define DMAMUX_SOURCE_IEEE1588_T1 55
#define DMAMUX_SOURCE_IEEE1588_T2 56
#define DMAMUX_SOURCE_IEEE1588_T3 57
#define DMAMUX_SOURCE_ALWAYS0 58
#define DMAMUX_SOURCE_ALWAYS1 59
#define DMAMUX_SOURCE_ALWAYS2 60
#define DMAMUX_SOURCE_ALWAYS3 61
#define DMAMUX_SOURCE_ALWAYS4 62
#define DMAMUX_SOURCE_ALWAYS5 63
#define DMAMUX_NUM_SOURCE_ALWAYS 6
#define KINETISK
#define HAS_KINETISK_UART0
#define HAS_KINETISK_UART0_FIFO
#define HAS_KINETISK_UART1
#define HAS_KINETISK_UART1_FIFO
#define HAS_KINETISK_UART2
#define HAS_KINETISK_UART3
#define HAS_KINETISK_UART4
#define HAS_KINETISK_UART5
#define HAS_KINETIS_I2C0
#define HAS_KINETIS_I2C0_STOPF
#define HAS_KINETIS_I2C1
#define HAS_KINETIS_I2C1_STOPF
#define HAS_KINETIS_I2C2
#define HAS_KINETIS_I2C2_STOPF
#define HAS_KINETIS_LLWU_16CH
#define HAS_KINETIS_MPU
#define HAS_KINETIS_ADC0
#define HAS_KINETIS_ADC1
#define HAS_KINETIS_FLASH_FTFE
#define HAS_KINETIS_SDHC
#elif defined(__MK66FX1M0__)
// https://forum.pjrc.com/threads/24633-Any-Chance-of-a-Teensy-3-1?p=78655&viewfull=1#post78655
enum IRQ_NUMBER_t {
IRQ_DMA_CH0 = 0,
IRQ_DMA_CH1 = 1,
IRQ_DMA_CH2 = 2,
IRQ_DMA_CH3 = 3,
IRQ_DMA_CH4 = 4,
IRQ_DMA_CH5 = 5,
IRQ_DMA_CH6 = 6,
IRQ_DMA_CH7 = 7,
IRQ_DMA_CH8 = 8,
IRQ_DMA_CH9 = 9,
IRQ_DMA_CH10 = 10,
IRQ_DMA_CH11 = 11,
IRQ_DMA_CH12 = 12,
IRQ_DMA_CH13 = 13,
IRQ_DMA_CH14 = 14,
IRQ_DMA_CH15 = 15,
IRQ_DMA_ERROR = 16,
IRQ_MCM = 17,
IRQ_FTFL_COMPLETE = 18,
IRQ_FTFL_COLLISION = 19,
IRQ_LOW_VOLTAGE = 20,
IRQ_LLWU = 21,
IRQ_WDOG = 22,
IRQ_RNG = 23,
IRQ_I2C0 = 24,
IRQ_I2C1 = 25,
IRQ_SPI0 = 26,
IRQ_SPI1 = 27,
IRQ_I2S0_TX = 28,
IRQ_I2S0_RX = 29,
IRQ_UART0_STATUS = 31,
IRQ_UART0_ERROR = 32,
IRQ_UART1_STATUS = 33,
IRQ_UART1_ERROR = 34,
IRQ_UART2_STATUS = 35,
IRQ_UART2_ERROR = 36,
IRQ_UART3_STATUS = 37,
IRQ_UART3_ERROR = 38,
IRQ_ADC0 = 39,
IRQ_CMP0 = 40,
IRQ_CMP1 = 41,
IRQ_FTM0 = 42,
IRQ_FTM1 = 43,
IRQ_FTM2 = 44,
IRQ_CMT = 45,
IRQ_RTC_ALARM = 46,
IRQ_RTC_SECOND = 47,
IRQ_PIT_CH0 = 48,
IRQ_PIT_CH1 = 49,
IRQ_PIT_CH2 = 50,
IRQ_PIT_CH3 = 51,
IRQ_PDB = 52,
IRQ_USBOTG = 53,
IRQ_USBDCD = 54,
IRQ_DAC0 = 56,
IRQ_MCG = 57,
IRQ_LPTMR = 58,
IRQ_PORTA = 59,
IRQ_PORTB = 60,
IRQ_PORTC = 61,
IRQ_PORTD = 62,
IRQ_PORTE = 63,
IRQ_SOFTWARE = 64,
IRQ_SPI2 = 65,
IRQ_UART4_STATUS = 66,
IRQ_UART4_ERROR = 67,
IRQ_CMP2 = 70,
IRQ_FTM3 = 71,
IRQ_DAC1 = 72,
IRQ_ADC1 = 73,
IRQ_I2C2 = 74,
IRQ_CAN0_MESSAGE = 75,
IRQ_CAN0_BUS_OFF = 76,
IRQ_CAN0_ERROR = 77,
IRQ_CAN0_TX_WARN = 78,
IRQ_CAN0_RX_WARN = 79,
IRQ_CAN0_WAKEUP = 80,
IRQ_SDHC = 81,
IRQ_ENET_TIMER = 82,
IRQ_ENET_TX = 83,
IRQ_ENET_RX = 84,
IRQ_ENET_ERROR = 85,
IRQ_LPUART0 = 86,
IRQ_TSI = 87,
IRQ_TPM1 = 88,
IRQ_TPM2 = 89,
IRQ_USBHS_PHY = 90,
IRQ_I2C3 = 91,
IRQ_CMP3 = 92,
IRQ_USBHS = 93,
IRQ_CAN1_MESSAGE = 94,
IRQ_CAN1_BUS_OFF = 95,
IRQ_CAN1_ERROR = 96,
IRQ_CAN1_TX_WARN = 97,
IRQ_CAN1_RX_WARN = 98,
IRQ_CAN1_WAKEUP = 99
};
#define NVIC_NUM_INTERRUPTS 100
#define DMA_NUM_CHANNELS 32
#define DMAMUX_SOURCE_TSI 1
#define DMAMUX_SOURCE_UART0_RX 2
#define DMAMUX_SOURCE_UART0_TX 3
#define DMAMUX_SOURCE_UART1_RX 4
#define DMAMUX_SOURCE_UART1_TX 5
#define DMAMUX_SOURCE_UART2_RX 6
#define DMAMUX_SOURCE_UART2_TX 7
#define DMAMUX_SOURCE_UART3_RX 8
#define DMAMUX_SOURCE_UART3_TX 9
#define DMAMUX_SOURCE_UART4_RXTX 10
#define DMAMUX_SOURCE_I2S0_RX 12
#define DMAMUX_SOURCE_I2S0_TX 13
#define DMAMUX_SOURCE_SPI0_RX 14
#define DMAMUX_SOURCE_SPI0_TX 15
#define DMAMUX_SOURCE_SPI1_RX 16
#define DMAMUX_SOURCE_SPI1_TX 17
#define DMAMUX_SOURCE_I2C0 18
#define DMAMUX_SOURCE_I2C3 18
#define DMAMUX_SOURCE_I2C1 19
#define DMAMUX_SOURCE_I2C2 19
#define DMAMUX_SOURCE_FTM0_CH0 20
#define DMAMUX_SOURCE_FTM0_CH1 21
#define DMAMUX_SOURCE_FTM0_CH2 22
#define DMAMUX_SOURCE_FTM0_CH3 23
#define DMAMUX_SOURCE_FTM0_CH4 24
#define DMAMUX_SOURCE_FTM0_CH5 25
#define DMAMUX_SOURCE_FTM0_CH6 26
#define DMAMUX_SOURCE_FTM0_CH7 27
#define DMAMUX_SOURCE_FTM1_CH0 28
#define DMAMUX_SOURCE_TPM1_CH0 28
#define DMAMUX_SOURCE_FTM1_CH1 29
#define DMAMUX_SOURCE_TPM1_CH1 29
#define DMAMUX_SOURCE_FTM2_CH0 30
#define DMAMUX_SOURCE_TPM2_CH0 30
#define DMAMUX_SOURCE_FTM2_CH1 31
#define DMAMUX_SOURCE_TPM2_CH1 31
#define DMAMUX_SOURCE_FTM3_CH0 32
#define DMAMUX_SOURCE_FTM3_CH1 33
#define DMAMUX_SOURCE_FTM3_CH2 34
#define DMAMUX_SOURCE_FTM3_CH3 35
#define DMAMUX_SOURCE_FTM3_CH4 36
#define DMAMUX_SOURCE_FTM3_CH5 37
#define DMAMUX_SOURCE_FTM3_CH6 38
#define DMAMUX_SOURCE_SPI2_RX 38
#define DMAMUX_SOURCE_FTM3_CH7 39
#define DMAMUX_SOURCE_SPI2_TX 39
#define DMAMUX_SOURCE_ADC0 40
#define DMAMUX_SOURCE_ADC1 41
#define DMAMUX_SOURCE_CMP0 42
#define DMAMUX_SOURCE_CMP1 43
#define DMAMUX_SOURCE_CMP2 44
#define DMAMUX_SOURCE_CMP3 44
#define DMAMUX_SOURCE_DAC0 45
#define DMAMUX_SOURCE_DAC1 46
#define DMAMUX_SOURCE_CMT 47
#define DMAMUX_SOURCE_PDB 48
#define DMAMUX_SOURCE_PORTA 49
#define DMAMUX_SOURCE_PORTB 50
#define DMAMUX_SOURCE_PORTC 51
#define DMAMUX_SOURCE_PORTD 52
#define DMAMUX_SOURCE_PORTE 53
#define DMAMUX_SOURCE_IEEE1588_T0 54
#define DMAMUX_SOURCE_IEEE1588_T1 55
#define DMAMUX_SOURCE_FTM1_OV 55
#define DMAMUX_SOURCE_IEEE1588_T2 56
#define DMAMUX_SOURCE_FTM2_OV 56
#define DMAMUX_SOURCE_IEEE1588_T3 57
#define DMAMUX_SOURCE_LPUART0_RX 58
#define DMAMUX_SOURCE_LPUART0_TX 59
#define DMAMUX_SOURCE_ALWAYS0 60
#define DMAMUX_SOURCE_ALWAYS1 61
#define DMAMUX_SOURCE_ALWAYS2 62
#define DMAMUX_SOURCE_ALWAYS3 63
#define DMAMUX_NUM_SOURCE_ALWAYS 4
#define KINETISK
#define HAS_KINETISK_UART0
#define HAS_KINETISK_UART0_FIFO
#define HAS_KINETISK_UART1
#define HAS_KINETISK_UART1_FIFO
#define HAS_KINETISK_UART2
#define HAS_KINETISK_UART3
#define HAS_KINETISK_UART4
#define HAS_KINETISK_LPUART0
#define HAS_KINETIS_I2C0
#define HAS_KINETIS_I2C0_STOPF
#define HAS_KINETIS_I2C1
#define HAS_KINETIS_I2C1_STOPF
#define HAS_KINETIS_I2C2
#define HAS_KINETIS_I2C2_STOPF
#define HAS_KINETIS_I2C3
#define HAS_KINETIS_I2C3_STOPF
#define HAS_KINETIS_LLWU_32CH
#define HAS_KINETIS_MPU
#define HAS_KINETIS_ADC0
#define HAS_KINETIS_ADC1
#define HAS_KINETIS_TSI_LITE
#define HAS_KINETIS_FLASH_FTFE
#define HAS_KINETIS_SDHC
#define HAS_KINETIS_HSRUN
#endif // end of board-specific definitions
#if (F_CPU == 240000000)
#define F_PLL 240000000
#ifndef F_BUS
#define F_BUS 60000000
//#define F_BUS 80000000 // uncomment these to try peripheral overclocking
//#define F_BUS 120000000 // all the usual overclocking caveats apply...
#endif
#define F_MEM 30000000
#elif (F_CPU == 216000000)
#define F_PLL 216000000
#ifndef F_BUS
#define F_BUS 54000000
//#define F_BUS 72000000
//#define F_BUS 108000000
#endif
#define F_MEM 27000000
#elif (F_CPU == 192000000)
#define F_PLL 192000000
#ifndef F_BUS
#define F_BUS 48000000
//#define F_BUS 64000000
//#define F_BUS 96000000
#endif
#define F_MEM 27428571
#elif (F_CPU == 180000000)
#define F_PLL 180000000
#ifndef F_BUS
#define F_BUS 60000000
//#define F_BUS 90000000
#endif
#define F_MEM 25714286
#elif (F_CPU == 168000000)
#define F_PLL 168000000
#define F_BUS 56000000
#define F_MEM 28000000
#elif (F_CPU == 144000000)
#define F_PLL 144000000
#ifndef F_BUS
#define F_BUS 48000000
//#define F_BUS 72000000
#endif
#define F_MEM 28800000
#elif (F_CPU == 120000000)
#define F_PLL 120000000
#ifndef F_BUS
#define F_BUS 60000000
//#define F_BUS 120000000
#endif
#define F_MEM 24000000
#elif (F_CPU == 96000000)
#define F_PLL 96000000
#ifndef F_BUS
#define F_BUS 48000000
//#define F_BUS 96000000
#endif
#define F_MEM 24000000
#elif (F_CPU == 72000000)
#define F_PLL 72000000
#ifndef F_BUS
#define F_BUS 36000000
//#define F_BUS 72000000
#endif
#define F_MEM 24000000
#elif (F_CPU == 48000000)
#define F_PLL 96000000
#if defined(KINETISK)
#define F_BUS 48000000
#elif defined(KINETISL)
#define F_BUS 24000000
#endif
#define F_MEM 24000000
#elif (F_CPU == 24000000)
#define F_PLL 96000000
#define F_BUS 24000000
#define F_MEM 24000000
#elif (F_CPU == 16000000)
#define F_PLL 16000000
#define F_BUS 16000000
#define F_MEM 16000000
#elif (F_CPU == 8000000)
#define F_PLL 8000000
#define F_BUS 8000000
#define F_MEM 8000000
#elif (F_CPU == 4000000)
#define F_PLL 4000000
#define F_BUS 4000000
#define F_MEM 4000000
#elif (F_CPU == 2000000)
#define F_PLL 2000000
#define F_BUS 2000000
#define F_MEM 1000000
#endif
#ifndef NULL
#define NULL (0)
#endif
// Port control and interrupts (PORT)
#define PORTA_PCR0 (*(volatile uint32_t *)0x40049000) // Pin Control Register n
#define PORT_PCR_ISF ((uint32_t)0x01000000) // Interrupt Status Flag
#define PORT_PCR_IRQC(n) ((uint32_t)(((n) & 15) << 16)) // Interrupt Configuration
#define PORT_PCR_IRQC_MASK ((uint32_t)0x000F0000)
#define PORT_PCR_LK ((uint32_t)0x00008000) // Lock Register
#define PORT_PCR_MUX(n) ((uint32_t)(((n) & 7) << 8)) // Pin Mux Control
#define PORT_PCR_MUX_MASK ((uint32_t)0x00000700)
#define PORT_PCR_DSE ((uint32_t)0x00000040) // Drive Strength Enable
#define PORT_PCR_ODE ((uint32_t)0x00000020) // Open Drain Enable
#define PORT_PCR_PFE ((uint32_t)0x00000010) // Passive Filter Enable
#define PORT_PCR_SRE ((uint32_t)0x00000004) // Slew Rate Enable
#define PORT_PCR_PE ((uint32_t)0x00000002) // Pull Enable
#define PORT_PCR_PS ((uint32_t)0x00000001) // Pull Select
#define PORTA_PCR1 (*(volatile uint32_t *)0x40049004) // Pin Control Register n
#define PORTA_PCR2 (*(volatile uint32_t *)0x40049008) // Pin Control Register n
#define PORTA_PCR3 (*(volatile uint32_t *)0x4004900C) // Pin Control Register n
#define PORTA_PCR4 (*(volatile uint32_t *)0x40049010) // Pin Control Register n
#define PORTA_PCR5 (*(volatile uint32_t *)0x40049014) // Pin Control Register n
#define PORTA_PCR6 (*(volatile uint32_t *)0x40049018) // Pin Control Register n
#define PORTA_PCR7 (*(volatile uint32_t *)0x4004901C) // Pin Control Register n
#define PORTA_PCR8 (*(volatile uint32_t *)0x40049020) // Pin Control Register n
#define PORTA_PCR9 (*(volatile uint32_t *)0x40049024) // Pin Control Register n
#define PORTA_PCR10 (*(volatile uint32_t *)0x40049028) // Pin Control Register n
#define PORTA_PCR11 (*(volatile uint32_t *)0x4004902C) // Pin Control Register n
#define PORTA_PCR12 (*(volatile uint32_t *)0x40049030) // Pin Control Register n
#define PORTA_PCR13 (*(volatile uint32_t *)0x40049034) // Pin Control Register n
#define PORTA_PCR14 (*(volatile uint32_t *)0x40049038) // Pin Control Register n
#define PORTA_PCR15 (*(volatile uint32_t *)0x4004903C) // Pin Control Register n
#define PORTA_PCR16 (*(volatile uint32_t *)0x40049040) // Pin Control Register n
#define PORTA_PCR17 (*(volatile uint32_t *)0x40049044) // Pin Control Register n
#define PORTA_PCR18 (*(volatile uint32_t *)0x40049048) // Pin Control Register n
#define PORTA_PCR19 (*(volatile uint32_t *)0x4004904C) // Pin Control Register n
#define PORTA_PCR20 (*(volatile uint32_t *)0x40049050) // Pin Control Register n
#define PORTA_PCR21 (*(volatile uint32_t *)0x40049054) // Pin Control Register n
#define PORTA_PCR22 (*(volatile uint32_t *)0x40049058) // Pin Control Register n
#define PORTA_PCR23 (*(volatile uint32_t *)0x4004905C) // Pin Control Register n
#define PORTA_PCR24 (*(volatile uint32_t *)0x40049060) // Pin Control Register n
#define PORTA_PCR25 (*(volatile uint32_t *)0x40049064) // Pin Control Register n
#define PORTA_PCR26 (*(volatile uint32_t *)0x40049068) // Pin Control Register n
#define PORTA_PCR27 (*(volatile uint32_t *)0x4004906C) // Pin Control Register n
#define PORTA_PCR28 (*(volatile uint32_t *)0x40049070) // Pin Control Register n
#define PORTA_PCR29 (*(volatile uint32_t *)0x40049074) // Pin Control Register n
#define PORTA_PCR30 (*(volatile uint32_t *)0x40049078) // Pin Control Register n
#define PORTA_PCR31 (*(volatile uint32_t *)0x4004907C) // Pin Control Register n
#define PORTA_GPCLR (*(volatile uint32_t *)0x40049080) // Global Pin Control Low Register
#define PORTA_GPCHR (*(volatile uint32_t *)0x40049084) // Global Pin Control High Register
#define PORTA_ISFR (*(volatile uint32_t *)0x400490A0) // Interrupt Status Flag Register
#define PORTA_DFER (*(volatile uint32_t *)0x400490C0) // Digital Filter Enable
#define PORTA_DFCR (*(volatile uint32_t *)0x400490C4) // Digital Filter Clock
#define PORTA_DFWR (*(volatile uint32_t *)0x400490C8) // Digital Filter Width
#define PORTB_PCR0 (*(volatile uint32_t *)0x4004A000) // Pin Control Register n
#define PORTB_PCR1 (*(volatile uint32_t *)0x4004A004) // Pin Control Register n
#define PORTB_PCR2 (*(volatile uint32_t *)0x4004A008) // Pin Control Register n
#define PORTB_PCR3 (*(volatile uint32_t *)0x4004A00C) // Pin Control Register n
#define PORTB_PCR4 (*(volatile uint32_t *)0x4004A010) // Pin Control Register n
#define PORTB_PCR5 (*(volatile uint32_t *)0x4004A014) // Pin Control Register n
#define PORTB_PCR6 (*(volatile uint32_t *)0x4004A018) // Pin Control Register n
#define PORTB_PCR7 (*(volatile uint32_t *)0x4004A01C) // Pin Control Register n
#define PORTB_PCR8 (*(volatile uint32_t *)0x4004A020) // Pin Control Register n
#define PORTB_PCR9 (*(volatile uint32_t *)0x4004A024) // Pin Control Register n
#define PORTB_PCR10 (*(volatile uint32_t *)0x4004A028) // Pin Control Register n
#define PORTB_PCR11 (*(volatile uint32_t *)0x4004A02C) // Pin Control Register n
#define PORTB_PCR12 (*(volatile uint32_t *)0x4004A030) // Pin Control Register n
#define PORTB_PCR13 (*(volatile uint32_t *)0x4004A034) // Pin Control Register n
#define PORTB_PCR14 (*(volatile uint32_t *)0x4004A038) // Pin Control Register n
#define PORTB_PCR15 (*(volatile uint32_t *)0x4004A03C) // Pin Control Register n
#define PORTB_PCR16 (*(volatile uint32_t *)0x4004A040) // Pin Control Register n
#define PORTB_PCR17 (*(volatile uint32_t *)0x4004A044) // Pin Control Register n
#define PORTB_PCR18 (*(volatile uint32_t *)0x4004A048) // Pin Control Register n
#define PORTB_PCR19 (*(volatile uint32_t *)0x4004A04C) // Pin Control Register n
#define PORTB_PCR20 (*(volatile uint32_t *)0x4004A050) // Pin Control Register n
#define PORTB_PCR21 (*(volatile uint32_t *)0x4004A054) // Pin Control Register n
#define PORTB_PCR22 (*(volatile uint32_t *)0x4004A058) // Pin Control Register n
#define PORTB_PCR23 (*(volatile uint32_t *)0x4004A05C) // Pin Control Register n
#define PORTB_PCR24 (*(volatile uint32_t *)0x4004A060) // Pin Control Register n
#define PORTB_PCR25 (*(volatile uint32_t *)0x4004A064) // Pin Control Register n
#define PORTB_PCR26 (*(volatile uint32_t *)0x4004A068) // Pin Control Register n
#define PORTB_PCR27 (*(volatile uint32_t *)0x4004A06C) // Pin Control Register n
#define PORTB_PCR28 (*(volatile uint32_t *)0x4004A070) // Pin Control Register n
#define PORTB_PCR29 (*(volatile uint32_t *)0x4004A074) // Pin Control Register n
#define PORTB_PCR30 (*(volatile uint32_t *)0x4004A078) // Pin Control Register n
#define PORTB_PCR31 (*(volatile uint32_t *)0x4004A07C) // Pin Control Register n
#define PORTB_GPCLR (*(volatile uint32_t *)0x4004A080) // Global Pin Control Low Register
#define PORTB_GPCHR (*(volatile uint32_t *)0x4004A084) // Global Pin Control High Register
#define PORTB_ISFR (*(volatile uint32_t *)0x4004A0A0) // Interrupt Status Flag Register
#define PORTB_DFER (*(volatile uint32_t *)0x4004A0C0) // Digital Filter Enable
#define PORTB_DFCR (*(volatile uint32_t *)0x4004A0C4) // Digital Filter Clock
#define PORTB_DFWR (*(volatile uint32_t *)0x4004A0C8) // Digital Filter Width
#define PORTC_PCR0 (*(volatile uint32_t *)0x4004B000) // Pin Control Register n
#define PORTC_PCR1 (*(volatile uint32_t *)0x4004B004) // Pin Control Register n
#define PORTC_PCR2 (*(volatile uint32_t *)0x4004B008) // Pin Control Register n
#define PORTC_PCR3 (*(volatile uint32_t *)0x4004B00C) // Pin Control Register n
#define PORTC_PCR4 (*(volatile uint32_t *)0x4004B010) // Pin Control Register n
#define PORTC_PCR5 (*(volatile uint32_t *)0x4004B014) // Pin Control Register n
#define PORTC_PCR6 (*(volatile uint32_t *)0x4004B018) // Pin Control Register n
#define PORTC_PCR7 (*(volatile uint32_t *)0x4004B01C) // Pin Control Register n
#define PORTC_PCR8 (*(volatile uint32_t *)0x4004B020) // Pin Control Register n
#define PORTC_PCR9 (*(volatile uint32_t *)0x4004B024) // Pin Control Register n
#define PORTC_PCR10 (*(volatile uint32_t *)0x4004B028) // Pin Control Register n
#define PORTC_PCR11 (*(volatile uint32_t *)0x4004B02C) // Pin Control Register n
#define PORTC_PCR12 (*(volatile uint32_t *)0x4004B030) // Pin Control Register n
#define PORTC_PCR13 (*(volatile uint32_t *)0x4004B034) // Pin Control Register n
#define PORTC_PCR14 (*(volatile uint32_t *)0x4004B038) // Pin Control Register n
#define PORTC_PCR15 (*(volatile uint32_t *)0x4004B03C) // Pin Control Register n
#define PORTC_PCR16 (*(volatile uint32_t *)0x4004B040) // Pin Control Register n
#define PORTC_PCR17 (*(volatile uint32_t *)0x4004B044) // Pin Control Register n
#define PORTC_PCR18 (*(volatile uint32_t *)0x4004B048) // Pin Control Register n
#define PORTC_PCR19 (*(volatile uint32_t *)0x4004B04C) // Pin Control Register n
#define PORTC_PCR20 (*(volatile uint32_t *)0x4004B050) // Pin Control Register n
#define PORTC_PCR21 (*(volatile uint32_t *)0x4004B054) // Pin Control Register n
#define PORTC_PCR22 (*(volatile uint32_t *)0x4004B058) // Pin Control Register n
#define PORTC_PCR23 (*(volatile uint32_t *)0x4004B05C) // Pin Control Register n
#define PORTC_PCR24 (*(volatile uint32_t *)0x4004B060) // Pin Control Register n
#define PORTC_PCR25 (*(volatile uint32_t *)0x4004B064) // Pin Control Register n
#define PORTC_PCR26 (*(volatile uint32_t *)0x4004B068) // Pin Control Register n
#define PORTC_PCR27 (*(volatile uint32_t *)0x4004B06C) // Pin Control Register n
#define PORTC_PCR28 (*(volatile uint32_t *)0x4004B070) // Pin Control Register n
#define PORTC_PCR29 (*(volatile uint32_t *)0x4004B074) // Pin Control Register n
#define PORTC_PCR30 (*(volatile uint32_t *)0x4004B078) // Pin Control Register n
#define PORTC_PCR31 (*(volatile uint32_t *)0x4004B07C) // Pin Control Register n
#define PORTC_GPCLR (*(volatile uint32_t *)0x4004B080) // Global Pin Control Low Register
#define PORTC_GPCHR (*(volatile uint32_t *)0x4004B084) // Global Pin Control High Register
#define PORTC_ISFR (*(volatile uint32_t *)0x4004B0A0) // Interrupt Status Flag Register
#define PORTC_DFER (*(volatile uint32_t *)0x4004B0C0) // Digital Filter Enable
#define PORTC_DFCR (*(volatile uint32_t *)0x4004B0C4) // Digital Filter Clock
#define PORTC_DFWR (*(volatile uint32_t *)0x4004B0C8) // Digital Filter Width
#define PORTD_PCR0 (*(volatile uint32_t *)0x4004C000) // Pin Control Register n
#define PORTD_PCR1 (*(volatile uint32_t *)0x4004C004) // Pin Control Register n
#define PORTD_PCR2 (*(volatile uint32_t *)0x4004C008) // Pin Control Register n
#define PORTD_PCR3 (*(volatile uint32_t *)0x4004C00C) // Pin Control Register n
#define PORTD_PCR4 (*(volatile uint32_t *)0x4004C010) // Pin Control Register n
#define PORTD_PCR5 (*(volatile uint32_t *)0x4004C014) // Pin Control Register n
#define PORTD_PCR6 (*(volatile uint32_t *)0x4004C018) // Pin Control Register n
#define PORTD_PCR7 (*(volatile uint32_t *)0x4004C01C) // Pin Control Register n
#define PORTD_PCR8 (*(volatile uint32_t *)0x4004C020) // Pin Control Register n
#define PORTD_PCR9 (*(volatile uint32_t *)0x4004C024) // Pin Control Register n
#define PORTD_PCR10 (*(volatile uint32_t *)0x4004C028) // Pin Control Register n
#define PORTD_PCR11 (*(volatile uint32_t *)0x4004C02C) // Pin Control Register n
#define PORTD_PCR12 (*(volatile uint32_t *)0x4004C030) // Pin Control Register n
#define PORTD_PCR13 (*(volatile uint32_t *)0x4004C034) // Pin Control Register n
#define PORTD_PCR14 (*(volatile uint32_t *)0x4004C038) // Pin Control Register n
#define PORTD_PCR15 (*(volatile uint32_t *)0x4004C03C) // Pin Control Register n
#define PORTD_PCR16 (*(volatile uint32_t *)0x4004C040) // Pin Control Register n
#define PORTD_PCR17 (*(volatile uint32_t *)0x4004C044) // Pin Control Register n
#define PORTD_PCR18 (*(volatile uint32_t *)0x4004C048) // Pin Control Register n
#define PORTD_PCR19 (*(volatile uint32_t *)0x4004C04C) // Pin Control Register n
#define PORTD_PCR20 (*(volatile uint32_t *)0x4004C050) // Pin Control Register n
#define PORTD_PCR21 (*(volatile uint32_t *)0x4004C054) // Pin Control Register n
#define PORTD_PCR22 (*(volatile uint32_t *)0x4004C058) // Pin Control Register n
#define PORTD_PCR23 (*(volatile uint32_t *)0x4004C05C) // Pin Control Register n
#define PORTD_PCR24 (*(volatile uint32_t *)0x4004C060) // Pin Control Register n
#define PORTD_PCR25 (*(volatile uint32_t *)0x4004C064) // Pin Control Register n
#define PORTD_PCR26 (*(volatile uint32_t *)0x4004C068) // Pin Control Register n
#define PORTD_PCR27 (*(volatile uint32_t *)0x4004C06C) // Pin Control Register n
#define PORTD_PCR28 (*(volatile uint32_t *)0x4004C070) // Pin Control Register n
#define PORTD_PCR29 (*(volatile uint32_t *)0x4004C074) // Pin Control Register n
#define PORTD_PCR30 (*(volatile uint32_t *)0x4004C078) // Pin Control Register n
#define PORTD_PCR31 (*(volatile uint32_t *)0x4004C07C) // Pin Control Register n
#define PORTD_GPCLR (*(volatile uint32_t *)0x4004C080) // Global Pin Control Low Register
#define PORTD_GPCHR (*(volatile uint32_t *)0x4004C084) // Global Pin Control High Register
#define PORTD_ISFR (*(volatile uint32_t *)0x4004C0A0) // Interrupt Status Flag Register
#define PORTD_DFER (*(volatile uint32_t *)0x4004C0C0) // Digital Filter Enable
#define PORTD_DFCR (*(volatile uint32_t *)0x4004C0C4) // Digital Filter Clock
#define PORTD_DFWR (*(volatile uint32_t *)0x4004C0C8) // Digital Filter Width
#define PORTE_PCR0 (*(volatile uint32_t *)0x4004D000) // Pin Control Register n
#define PORTE_PCR1 (*(volatile uint32_t *)0x4004D004) // Pin Control Register n
#define PORTE_PCR2 (*(volatile uint32_t *)0x4004D008) // Pin Control Register n
#define PORTE_PCR3 (*(volatile uint32_t *)0x4004D00C) // Pin Control Register n
#define PORTE_PCR4 (*(volatile uint32_t *)0x4004D010) // Pin Control Register n
#define PORTE_PCR5 (*(volatile uint32_t *)0x4004D014) // Pin Control Register n
#define PORTE_PCR6 (*(volatile uint32_t *)0x4004D018) // Pin Control Register n
#define PORTE_PCR7 (*(volatile uint32_t *)0x4004D01C) // Pin Control Register n
#define PORTE_PCR8 (*(volatile uint32_t *)0x4004D020) // Pin Control Register n
#define PORTE_PCR9 (*(volatile uint32_t *)0x4004D024) // Pin Control Register n
#define PORTE_PCR10 (*(volatile uint32_t *)0x4004D028) // Pin Control Register n
#define PORTE_PCR11 (*(volatile uint32_t *)0x4004D02C) // Pin Control Register n
#define PORTE_PCR12 (*(volatile uint32_t *)0x4004D030) // Pin Control Register n
#define PORTE_PCR13 (*(volatile uint32_t *)0x4004D034) // Pin Control Register n
#define PORTE_PCR14 (*(volatile uint32_t *)0x4004D038) // Pin Control Register n
#define PORTE_PCR15 (*(volatile uint32_t *)0x4004D03C) // Pin Control Register n
#define PORTE_PCR16 (*(volatile uint32_t *)0x4004D040) // Pin Control Register n
#define PORTE_PCR17 (*(volatile uint32_t *)0x4004D044) // Pin Control Register n
#define PORTE_PCR18 (*(volatile uint32_t *)0x4004D048) // Pin Control Register n
#define PORTE_PCR19 (*(volatile uint32_t *)0x4004D04C) // Pin Control Register n
#define PORTE_PCR20 (*(volatile uint32_t *)0x4004D050) // Pin Control Register n
#define PORTE_PCR21 (*(volatile uint32_t *)0x4004D054) // Pin Control Register n
#define PORTE_PCR22 (*(volatile uint32_t *)0x4004D058) // Pin Control Register n
#define PORTE_PCR23 (*(volatile uint32_t *)0x4004D05C) // Pin Control Register n
#define PORTE_PCR24 (*(volatile uint32_t *)0x4004D060) // Pin Control Register n
#define PORTE_PCR25 (*(volatile uint32_t *)0x4004D064) // Pin Control Register n
#define PORTE_PCR26 (*(volatile uint32_t *)0x4004D068) // Pin Control Register n
#define PORTE_PCR27 (*(volatile uint32_t *)0x4004D06C) // Pin Control Register n
#define PORTE_PCR28 (*(volatile uint32_t *)0x4004D070) // Pin Control Register n
#define PORTE_PCR29 (*(volatile uint32_t *)0x4004D074) // Pin Control Register n
#define PORTE_PCR30 (*(volatile uint32_t *)0x4004D078) // Pin Control Register n
#define PORTE_PCR31 (*(volatile uint32_t *)0x4004D07C) // Pin Control Register n
#define PORTE_GPCLR (*(volatile uint32_t *)0x4004D080) // Global Pin Control Low Register
#define PORTE_GPCHR (*(volatile uint32_t *)0x4004D084) // Global Pin Control High Register
#define PORTE_ISFR (*(volatile uint32_t *)0x4004D0A0) // Interrupt Status Flag Register
#define PORTE_DFER (*(volatile uint32_t *)0x4004D0C0) // Digital Filter Enable
#define PORTE_DFCR (*(volatile uint32_t *)0x4004D0C4) // Digital Filter Clock
#define PORTE_DFWR (*(volatile uint32_t *)0x4004D0C8) // Digital Filter Width
// System Integration Module (SIM)
#define SIM_SOPT1 (*(volatile uint32_t *)0x40047000) // System Options Register 1
#define SIM_SOPT1_USBREGEN ((uint32_t)0x80000000) // USB regulator enable
#define SIM_SOPT1_USBSSTBY ((uint32_t)0x40000000) // USB regulator standby in Stop, VLPS, LLS and VLLS
#define SIM_SOPT1_USBVSTBY ((uint32_t)0x20000000) // USB regulator standby in VLPR and VLPW
#define SIM_SOPT1_OSC32KSEL(n) ((uint32_t)(((n) & 3) << 18)) // 32K oscillator clock, 0=system osc, 2=rtc osc, 3=lpo
#define SIM_SOPT1CFG (*(volatile uint32_t *)0x40047004) // SOPT1 Configuration Register
#define SIM_SOPT1CFG_USSWE ((uint32_t)0x04000000) // USB voltage regulator stop standby write enable
#define SIM_SOPT1CFG_UVSWE ((uint32_t)0x02000000) // USB voltage regulator VLP standby write enable
#define SIM_SOPT1CFG_URWE ((uint32_t)0x01000000) // USB voltage regulator enable write enable
#define SIM_USBPHYCTL (*(volatile uint32_t *)0x40047008) // USB PHY Control Register
#define SIM_USBPHYCTL_USBDISILIM ((uint32_t)0x00800000) // USB Disable Inrush Current Limit
#define SIM_USBPHYCTL_USB3VOUTTRG(n) ((uint32_t)(((n) & 7) << 20)) // USB 3.3V Output Target
#define SIM_USBPHYCTL_USBVREGPD ((uint32_t)0x00020000) // Enables the pulldown on the output of the USB Regulator.
#define SIM_USBPHYCTL_USBVREGSEL ((uint32_t)0x00010000) // Selects the default input voltage source
#define SIM_SOPT2 (*(volatile uint32_t *)0x40048004) // System Options Register 2
#define SIM_SOPT2_SDHCSRC(n) (uint32_t)(((n) & 3) << 28) // SDHC Clock, 0=system, 1=FLL/PLL, 2=OSCERCLK, 3=external
#define SIM_SOPT2_LPUARTSRC(n) (uint32_t)(((n) & 3) << 26) // LPUART Clock, 0=off, 1=FLL/PLL, 2=OSCERCLK, 3=MCGIRCLK
#define SIM_SOPT2_UART0SRC(n) (uint32_t)(((n) & 3) << 26) // UART0 Clock, 0=off, 1=FLL/PLL, 2=OSCERCLK, 3=MCGIRCLK
#define SIM_SOPT2_TPMSRC(n) (uint32_t)(((n) & 3) << 24) // TPM Clock, 0=off, 1=FLL/PLL, 2=OSCERCLK, 3=MCGIRCLK
#define SIM_SOPT2_TIMESRC(n) (uint32_t)(((n) & 3) << 20) // IEEE 1588 clock, 0=system, 1=FLL/PLL, 2=OSCERCLK, 3=external
#define SIM_SOPT2_RMIISRC ((uint32_t)0x00080000) // 0=external, 1=external 1588
#define SIM_SOPT2_USBSRC ((uint32_t)0x00040000) // 0=USB_CLKIN, 1=FFL/PLL
#define SIM_SOPT2_PLLFLLSEL ((uint32_t)0x00010000) // 0=FLL, 1=PLL
#define SIM_SOPT2_IRC48SEL ((uint32_t)0x00030000) // 0=FLL, 1=PLL
#define SIM_SOPT2_TRACECLKSEL ((uint32_t)0x00001000) // 0=MCGOUTCLK, 1=CPU
#define SIM_SOPT2_PTD7PAD ((uint32_t)0x00000800) // 0=normal, 1=double drive PTD7
#define SIM_SOPT2_FBSL(n) ((uint32_t)(((n) & 3) << 8)) // FlexBus security level
#define SIM_SOPT2_CLKOUTSEL(n) ((uint32_t)(((n) & 7) << 5)) // Selects the clock to output on the CLKOUT pin.
#define SIM_SOPT2_RTCCLKOUTSEL ((uint32_t)0x00000010) // RTC clock out select
#define SIM_SOPT2_USBREGEN ((uint32_t)0x00000002) // USB PHY PLL Regulator Enable
#define SIM_SOPT2_USBSLSRC ((uint32_t)0x00000001) // USB Slow Clock Source
#define SIM_SOPT4 (*(volatile uint32_t *)0x4004800C) // System Options Register 4
#define SIM_SOPT4_FTM3TRG1SRC ((uint32_t)0x80000000) // FlexTimer 3 Hardware Trigger 1 Source Select
#define SIM_SOPT4_FTM3TRG0SRC ((uint32_t)0x40000000) // FlexTimer 3 Hardware Trigger 0 Source Select
#define SIM_SOPT4_FTM0TRG1SRC ((uint32_t)0x20000000) // FlexTimer 0 Hardware Trigger 1 Source Select
#define SIM_SOPT4_FTM0TRG0SRC ((uint32_t)0x10000000) // FlexTimer 0 Hardware Trigger 0 Source Select
#define SIM_SOPT4_FTM3CLKSEL ((uint32_t)0x08000000) // FlexTimer 3 External Clock Pin Select
#define SIM_SOPT4_FTM2CLKSEL ((uint32_t)0x04000000) // FlexTimer 2 External Clock Pin Select
#define SIM_SOPT4_FTM1CLKSEL ((uint32_t)0x02000000) // FTM1 External Clock Pin Select
#define SIM_SOPT4_FTM0CLKSEL ((uint32_t)0x01000000) // FlexTimer 0 External Clock Pin Select
#define SIM_SOPT4_FTM2CH1SRC ((uint32_t)0x00400000) // FTM2 channel 1 input capture source select
#define SIM_SOPT4_FTM2CH0SRC(n) ((uint32_t)(((n) & 3) << 20)) // FTM2 channel 0 input capture source select
#define SIM_SOPT4_FTM1CH0SRC(n) ((uint32_t)(((n) & 3) << 18)) // FTM1 channel 0 input capture source select
#define SIM_SOPT4_FTM3FLT0 ((uint32_t)0x00001000) // FTM3 Fault 0 Select
#define SIM_SOPT4_FTM2FLT0 ((uint32_t)0x00000100) // FTM2 Fault 0 Select
#define SIM_SOPT4_FTM1FLT0 ((uint32_t)0x00000010) // FTM1 Fault 0 Select
#define SIM_SOPT4_FTM0FLT3 ((uint32_t)0x00000008) // FTM0 Fault 3 Select
#define SIM_SOPT4_FTM0FLT2 ((uint32_t)0x00000004) // FTM0 Fault 2 Select
#define SIM_SOPT4_FTM0FLT1 ((uint32_t)0x00000002) // FTM0 Fault 1 Select
#define SIM_SOPT4_FTM0FLT0 ((uint32_t)0x00000001) // FTM0 Fault 0 Select
#define SIM_SOPT5 (*(volatile uint32_t *)0x40048010) // System Options Register 5
#define SIM_SOPT5_LPUART0RXSRC(n) (uint32_t)(((n) & 3) << 18) // LPUART0 receive data source select
#define SIM_SOPT5_LPUART0TXSRC(n) (uint32_t)(((n) & 3) << 16) // LPUART0 transmit data source select
#define SIM_SOPT5_UART1RXSRC(n) (uint32_t)(((n) & 3) << 6) // UART 1 receive data source select
#define SIM_SOPT5_UART1TXSRC(n) (uint32_t)(((n) & 3) << 4) // UART 1 transmit data source select
#define SIM_SOPT5_UART0RXSRC(n) (uint32_t)(((n) & 3) << 2) // UART 0 receive data source select
#define SIM_SOPT5_UART0TXSRC(n) (uint32_t)(((n) & 3) << 0) // UART 0 transmit data source select
#define SIM_SOPT7 (*(volatile uint32_t *)0x40048018) // System Options Register 7
#define SIM_SOPT7_ADC1ALTTRGEN ((uint32_t)0x00008000) // ADC1 alternate trigger enable
#define SIM_SOPT7_ADC1PRETRGSEL ((uint32_t)0x00001000) // ADC1 pre-trigger select
#define SIM_SOPT7_ADC1TRGSEL(n) (uint32_t)(((n) & 15) << 8) // ADC1 trigger select
#define SIM_SOPT7_ADC0ALTTRGEN ((uint32_t)0x00000080) // ADC0 alternate trigger enable
#define SIM_SOPT7_ADC0PRETRGSEL ((uint32_t)0x00000010) // ADC0 pretrigger select
#define SIM_SOPT7_ADC0TRGSEL(n) (uint32_t)(((n) & 15) << 0) // ADC0 trigger select
#define SIM_SOPT8 (*(volatile uint32_t *)0x4004801C) // System Options Register 8
#define SIM_SOPT8_FTM3OCH7SRC ((uint32_t)0x80000000) // FTM3 channel 7 output source
#define SIM_SOPT8_FTM3OCH6SRC ((uint32_t)0x40000000) // FTM3 channel 6 output source
#define SIM_SOPT8_FTM3OCH5SRC ((uint32_t)0x20000000) // FTM3 channel 5 output source
#define SIM_SOPT8_FTM3OCH4SRC ((uint32_t)0x10000000) // FTM3 channel 4 output source
#define SIM_SOPT8_FTM3OCH3SRC ((uint32_t)0x08000000) // FTM3 channel 3 output source
#define SIM_SOPT8_FTM3OCH2SRC ((uint32_t)0x04000000) // FTM3 channel 2 output source
#define SIM_SOPT8_FTM3OCH1SRC ((uint32_t)0x02000000) // FTM3 channel 1 output source
#define SIM_SOPT8_FTM3OCH0SRC ((uint32_t)0x01000000) // FTM3 channel 0 output source
#define SIM_SOPT8_FTM0OCH7SRC ((uint32_t)0x00800000) // FTM0 channel 7 output source
#define SIM_SOPT8_FTM0OCH6SRC ((uint32_t)0x00400000) // FTM0 channel 6 output source
#define SIM_SOPT8_FTM0OCH5SRC ((uint32_t)0x00200000) // FTM0 channel 5 output source
#define SIM_SOPT8_FTM0OCH4SRC ((uint32_t)0x00100000) // FTM0 channel 4 output source
#define SIM_SOPT8_FTM0OCH3SRC ((uint32_t)0x00080000) // FTM0 channel 3 output source
#define SIM_SOPT8_FTM0OCH2SRC ((uint32_t)0x00040000) // FTM0 channel 2 output source
#define SIM_SOPT8_FTM0OCH1SRC ((uint32_t)0x00020000) // FTM0 channel 1 output source
#define SIM_SOPT8_FTM0OCH0SRC ((uint32_t)0x00010000) // FTM0 channel 0 output source
#define SIM_SOPT8_FTM3SYNCBIT ((uint32_t)0x00000008) // FTM3 Hardware Trigger 0 Software Synchronization
#define SIM_SOPT8_FTM2SYNCBIT ((uint32_t)0x00000004) // FTM2 Hardware Trigger 0 Software Synchronization
#define SIM_SOPT8_FTM1SYNCBIT ((uint32_t)0x00000002) // FTM1 Hardware Trigger 0 Software Synchronization
#define SIM_SOPT8_FTM0SYNCBIT ((uint32_t)0x00000001) // FTM0 Hardware Trigger 0 Software Synchronization
#define SIM_SOPT9 (*(volatile uint32_t *)0x40048020) // System Options Register 9
#define SIM_SOPT9_TPM2CLKSEL ((uint32_t)0x02000000) // TPM2 External Clock Pin Select
#define SIM_SOPT9_TPM1CLKSEL ((uint32_t)0x01000000) // TPM1 External Clock Pin Select
#define SIM_SOPT9_TPM2CH0SRC(n) (uint32_t)(((n) & 3) << 20) // TPM2 channel 0 input capture source select
#define SIM_SOPT9_TPM1CH0SRC(n) (uint32_t)(((n) & 3) << 18) // TPM1 channel 0 input capture source select
#define SIM_SDID (*(const uint32_t *)0x40048024) // System Device Identification Register
#define SIM_SCGC1 (*(volatile uint32_t *)0x40048028) // System Clock Gating Control Register 1
#define SIM_SCGC1_UART5 ((uint32_t)0x00000800) // UART5 Clock Gate Control
#define SIM_SCGC1_UART4 ((uint32_t)0x00000400) // UART4 Clock Gate Control
#define SIM_SCGC1_I2C3 ((uint32_t)0x00000080) // I2C3 Clock Gate Control
#define SIM_SCGC1_I2C2 ((uint32_t)0x00000040) // I2C2 Clock Gate Control
#define SIM_SCGC2 (*(volatile uint32_t *)0x4004802C) // System Clock Gating Control Register 2
#if defined(KINETISK)
#define SIM_SCGC2_DAC1 ((uint32_t)0x00002000) // DAC1 Clock Gate Control
#define SIM_SCGC2_DAC0 ((uint32_t)0x00001000) // DAC0 Clock on APIS1 (base addr 400CC000)
#define SIM_SCGC2_TPM2 ((uint32_t)0x00000400) // TPM2 Clock Gate Control
#define SIM_SCGC2_TPM1 ((uint32_t)0x00000200) // TPM1 Clock Gate Control
#define SIM_SCGC2_LPUART0 ((uint32_t)0x00000010) // LPUART0 Clock Gate Control
#define SIM_SCGC2_ENET ((uint32_t)0x00000001) // Ethernet Clock Gate Control
#endif
#define SIM_SCGC3 (*(volatile uint32_t *)0x40048030) // System Clock Gating Control Register 3
#define SIM_SCGC3_ADC1 ((uint32_t)0x08000000) // ADC1 Clock Gate Control
#define SIM_SCGC3_FTM3 ((uint32_t)0x02000000) // FTM3 Clock Gate Control
#define SIM_SCGC3_FTM2 ((uint32_t)0x01000000) // FTM2 Clock on APIS1 (base addr 400B8000)
#define SIM_SCGC3_SDHC ((uint32_t)0x00020000) // SDHC Clock Gate Control
#define SIM_SCGC3_SPI2 ((uint32_t)0x00001000) // SPI2 Clock Gate Control
#define SIM_SCGC3_FLEXCAN1 ((uint32_t)0x00000010) // FLEXCAN1 Clock Gate Control
#define SIM_SCGC3_USBHSDCD ((uint32_t)0x00000008) // USBHSDCD Clock Gate Control
#define SIM_SCGC3_USBHSPHY ((uint32_t)0x00000004) // USBHSPHY Clock Gate Control
#define SIM_SCGC3_USBHS ((uint32_t)0x00000002) // USBHS Clock Gate Control
//#define SIM_SCGC3_RNGA ((uint32_t)0x00000001) // RNGA Clock on APIS1 (base addr 400A0000)
#define SIM_SCGC4 (*(volatile uint32_t *)0x40048034) // System Clock Gating Control Register 4
#define SIM_SCGC4_VREF ((uint32_t)0x00100000) // VREF Clock Gate Control
#define SIM_SCGC4_CMP ((uint32_t)0x00080000) // Comparator Clock Gate Control
#define SIM_SCGC4_USBOTG ((uint32_t)0x00040000) // USB Clock Gate Control
#define SIM_SCGC4_UART3 ((uint32_t)0x00002000) // UART3 Clock Gate Control
#define SIM_SCGC4_UART2 ((uint32_t)0x00001000) // UART2 Clock Gate Control
#define SIM_SCGC4_UART1 ((uint32_t)0x00000800) // UART1 Clock Gate Control
#define SIM_SCGC4_UART0 ((uint32_t)0x00000400) // UART0 Clock Gate Control
#define SIM_SCGC4_I2C1 ((uint32_t)0x00000080) // I2C1 Clock Gate Control
#define SIM_SCGC4_I2C0 ((uint32_t)0x00000040) // I2C0 Clock Gate Control
#define SIM_SCGC4_CMT ((uint32_t)0x00000004) // CMT Clock Gate Control
#define SIM_SCGC4_EWM ((uint32_t)0x00000002) // EWM Clock Gate Control
#ifdef KINETISL
#define SIM_SCGC4_SPI1 ((uint32_t)0x00800000) //
#define SIM_SCGC4_SPI0 ((uint32_t)0x00400000) //
#endif
#define SIM_SCGC5 (*(volatile uint32_t *)0x40048038) // System Clock Gating Control Register 5
#define SIM_SCGC5_PORTE ((uint32_t)0x00002000) // Port E Clock Gate Control
#define SIM_SCGC5_PORTD ((uint32_t)0x00001000) // Port D Clock Gate Control
#define SIM_SCGC5_PORTC ((uint32_t)0x00000800) // Port C Clock Gate Control
#define SIM_SCGC5_PORTB ((uint32_t)0x00000400) // Port B Clock Gate Control
#define SIM_SCGC5_PORTA ((uint32_t)0x00000200) // Port A Clock Gate Control
#define SIM_SCGC5_TSI ((uint32_t)0x00000020) // Touch Sense Input TSI Clock Gate Control
#define SIM_SCGC5_LPTIMER ((uint32_t)0x00000001) // Low Power Timer Access Control
#define SIM_SCGC6 (*(volatile uint32_t *)0x4004803C) // System Clock Gating Control Register 6
#if defined(KINETISL)
#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) // DAC on Kinetis-L
#define SIM_SCGC6_TPM2 ((uint32_t)0x04000000) // FTM2 Clock Gate Control
#define SIM_SCGC6_TPM1 ((uint32_t)0x02000000) // FTM1 Clock Gate Control
#define SIM_SCGC6_TPM0 ((uint32_t)0x01000000) // FTM0 Clock Gate Control
#elif defined(KINETISK)
//#define SIM_SCGC6_DAC0 ((uint32_t)0x80000000) // DAC0 Clock on APIS0 (base addr 4003F000)
//#define SIM_SCGC6_FTM2 ((uint32_t)0x04000000) // FTM2 Clock on APIS0 (base addr 4003A000)
#define SIM_SCGC6_PDB ((uint32_t)0x00400000) // PDB Clock Gate Control
#define SIM_SCGC6_USBDCD ((uint32_t)0x00200000) // USB DCD Clock Gate Control
#define SIM_SCGC6_SPI1 ((uint32_t)0x00002000) // SPI1 Clock Gate Control
#define SIM_SCGC6_SPI0 ((uint32_t)0x00001000) // SPI0 Clock Gate Control
#define SIM_SCGC6_RNGA ((uint32_t)0x00000200) // RNGA Clock on APIS0 (base addr 40029000)
#define SIM_SCGC6_FLEXCAN0 ((uint32_t)0x00000010) // FlexCAN0 Clock Gate Control
#define SIM_SCGC6_CRC ((uint32_t)0x00040000) // CRC Clock Gate Control
#endif
#define SIM_SCGC6_RTC ((uint32_t)0x20000000) // RTC Access
#define SIM_SCGC6_ADC0 ((uint32_t)0x08000000) // ADC0 Clock Gate Control
#define SIM_SCGC6_FTM1 ((uint32_t)0x02000000) // FTM1 Clock Gate Control
#define SIM_SCGC6_FTM0 ((uint32_t)0x01000000) // FTM0 Clock Gate Control
#define SIM_SCGC6_PIT ((uint32_t)0x00800000) // PIT Clock Gate Control
#define SIM_SCGC6_I2S ((uint32_t)0x00008000) // I2S Clock Gate Control
#define SIM_SCGC6_DMAMUX ((uint32_t)0x00000002) // DMA Mux Clock Gate Control
#define SIM_SCGC6_FTFL ((uint32_t)0x00000001) // Flash Memory Clock Gate Control
#define SIM_SCGC7 (*(volatile uint32_t *)0x40048040) // System Clock Gating Control Register 7
#if defined(KINETISK)
#define SIM_SCGC7_SDRAMC ((uint32_t)0x00000008) // SDRAM Clock Gate Control
#define SIM_SCGC7_MPU ((uint32_t)0x00000004) // MPU Clock Gate Control
#define SIM_SCGC7_DMA ((uint32_t)0x00000002) // DMA Clock Gate Control
#define SIM_SCGC7_FLEXBUS ((uint32_t)0x00000001) // FLEXBUS Clock Gate Control
#elif defined(KINETISL)
#define SIM_SCGC7_DMA ((uint32_t)0x00000100) // DMA Clock Gate Control
#endif
#define SIM_CLKDIV1 (*(volatile uint32_t *)0x40048044) // System Clock Divider Register 1
#define SIM_CLKDIV1_OUTDIV1(n) ((uint32_t)(((n) & 0x0F) << 28)) // divide value for the core/system clock
#define SIM_CLKDIV1_OUTDIV2(n) ((uint32_t)(((n) & 0x0F) << 24)) // divide value for the peripheral clock
#define SIM_CLKDIV1_OUTDIV3(n) ((uint32_t)(((n) & 0x0F) << 20)) // divide value for the flexbus clock
#define SIM_CLKDIV1_OUTDIV4(n) ((uint32_t)(((n) & 0x0F) << 16)) // divide value for the flash clock
#define SIM_CLKDIV1_OUTDIVS(n1, n2, n3, n4) \
(SIM_CLKDIV1_OUTDIV1(n1) | SIM_CLKDIV1_OUTDIV2(n2) | \
SIM_CLKDIV1_OUTDIV3(n3) | SIM_CLKDIV1_OUTDIV4(n4))
#define SIM_CLKDIV2 (*(volatile uint32_t *)0x40048048) // System Clock Divider Register 2
#define SIM_CLKDIV2_USBDIV(n) ((uint32_t)(((n) & 0x07) << 1))
#define SIM_CLKDIV2_USBFRAC ((uint32_t)0x01)
#define SIM_FCFG1 (*(const uint32_t *)0x4004804C) // Flash Configuration Register 1
#define SIM_FCFG1_FLASHDOZE ((uint32_t)0x00000002) // Flash Doze (disabled during wait)
#define SIM_FCFG1_FLASHDIS ((uint32_t)0x00000001) // Flash Disable
#define SIM_FCFG2 (*(const uint32_t *)0x40048050) // Flash Configuration Register 2
#define SIM_UIDH (*(const uint32_t *)0x40048054) // Unique Identification Register High
#define SIM_UIDMH (*(const uint32_t *)0x40048058) // Unique Identification Register Mid-High
#define SIM_UIDML (*(const uint32_t *)0x4004805C) // Unique Identification Register Mid Low
#define SIM_UIDL (*(const uint32_t *)0x40048060) // Unique Identification Register Low
#define SIM_CLKDIV3 (*(volatile uint32_t *)0x40048064) // System Clock Divider Register 3 (LPUART & TPM)
#define SIM_CLKDIV3_PLLFLLDIV(n) ((uint32_t)(((n) & 0x07) << 1))
#define SIM_CLKDIV3_PLLFLLFRAC ((uint32_t)0x01)
#define SIM_CLKDIV4 (*(volatile uint32_t *)0x40048068) // System Clock Divider Register 4 (Trace)
#define SIM_CLKDIV4_TRACEDIV(n) ((uint32_t)(((n) & 0x07) << 1))
#define SIM_CLKDIV4_TRACEFRAC ((uint32_t)0x01)
#if defined(KINETISL)
#define SIM_COPC (*(volatile uint32_t *)0x40048100) // COP Control Register (SIM_COPC)
#define SIM_SRVCOP (*(volatile uint32_t *)0x40048104) // Service COP Register (SIM_SRVCOP)
#endif
// Reset Control Module (RCM)
#define RCM_SRS0 (*(volatile uint8_t *)0x4007F000) // System Reset Status Register 0
#define RCM_SRS0_POR ((uint8_t)0x80)
#define RCM_SRS0_PIN ((uint8_t)0x40)
#define RCM_SRS0_WDOG ((uint8_t)0x20)
#define RCM_SRS0_LOL ((uint8_t)0x08)
#define RCM_SRS0_LOC ((uint8_t)0x04)
#define RCM_SRS0_LVD ((uint8_t)0x02)
#define RCM_SRS0_WAKEUP ((uint8_t)0x01)
#define RCM_SRS1 (*(volatile uint8_t *)0x4007F001) // System Reset Status Register 1
#define RCM_SRS1_SACKERR ((uint8_t)0x20)
#define RCM_SRS1_EZPT ((uint8_t)0x10)
#define RCM_SRS1_MDM_AP ((uint8_t)0x08)
#define RCM_SRS1_SW ((uint8_t)0x04)
#define RCM_SRS1_LOCKUP ((uint8_t)0x02)
#define RCM_SRS1_JTAG ((uint8_t)0x01)
#define RCM_RPFC (*(volatile uint8_t *)0x4007F004) // Reset Pin Filter Control Register
#define RCM_RPFW (*(volatile uint8_t *)0x4007F005) // Reset Pin Filter Width Register
#define RCM_MR (*(volatile uint8_t *)0x4007F007) // Mode Register
#define RCM_SSRS0 (*(volatile uint8_t *)0x4007F008) // Sticky System Reset Status Register 0
#define RCM_SSRS1 (*(volatile uint8_t *)0x4007F009) // Sticky System Reset Status Register 0
// System Mode Controller
#define SMC_PMPROT (*(volatile uint8_t *)0x4007E000) // Power Mode Protection Register
#define SMC_PMPROT_AHSRUN ((uint8_t)0x80) // Allow high speed run mode
#define SMC_PMPROT_AVLP ((uint8_t)0x20) // Allow very low power modes
#define SMC_PMPROT_ALLS ((uint8_t)0x08) // Allow low leakage stop mode
#define SMC_PMPROT_AVLLS ((uint8_t)0x02) // Allow very low leakage stop mode
#define SMC_PMCTRL (*(volatile uint8_t *)0x4007E001) // Power Mode Control Register
#define SMC_PMCTRL_LPWUI ((uint8_t)0x80) // Low Power Wake Up on Interrupt
#define SMC_PMCTRL_RUNM(n) ((uint8_t)(((n) & 0x03) << 5)) // Run Mode Control
#define SMC_PMCTRL_STOPA ((uint8_t)0x08) // Stop Aborted
#define SMC_PMCTRL_STOPM(n) ((uint8_t)((n) & 0x07)) // Stop Mode Control
#define SMC_VLLSCTRL (*(volatile uint8_t *)0x4007E002) // VLLS Control Register
#define SMC_VLLSCTRL_PORPO ((uint8_t)0x20) // POR Power Option
#define SMC_VLLSCTRL_VLLSM(n) ((uint8_t)((n) & 0x07)) // VLLS Mode Control
#if defined(__MK66FX1M0__)
#define SMC_STOPCTRL SMC_VLLSCTRL // Stop Control Register (compatible to SMC_VLLSCTRL)
#define SMC_STOPCTRL_PSTOPO(n) ((uint8_t)(((n) & 0x03) << 6)) // Partial Stop Option
#define SMC_STOPCTRL_PORPO SMC_VLLSCTRL_PORPO // POR Power Option
#define SMC_STOPCTRL_RAM2PO ((uint8_t)0x10) // RAM2 Power Option
#define SMC_STOPCTRL_LLSM(n) SMC_VLLSCTRL_VLLSM(n) // VLLS Mode Control
#endif
#define SMC_PMSTAT (*(volatile uint8_t *)0x4007E003) // Power Mode Status Register
#define SMC_PMSTAT_RUN ((uint8_t)0x01) // Current power mode is RUN
#define SMC_PMSTAT_STOP ((uint8_t)0x02) // Current power mode is STOP
#define SMC_PMSTAT_VLPR ((uint8_t)0x04) // Current power mode is VLPR
#define SMC_PMSTAT_VLPW ((uint8_t)0x08) // Current power mode is VLPW
#define SMC_PMSTAT_VLPS ((uint8_t)0x10) // Current power mode is VLPS
#define SMC_PMSTAT_LLS ((uint8_t)0x20) // Current power mode is LLS
#define SMC_PMSTAT_VLLS ((uint8_t)0x40) // Current power mode is VLLS
#define SMC_PMSTAT_HSRUN ((uint8_t)0x80) // Current power mode is HSRUN
// Power Management Controller
#define PMC_LVDSC1 (*(volatile uint8_t *)0x4007D000) // Low Voltage Detect Status And Control 1 register
#define PMC_LVDSC1_LVDF ((uint8_t)0x80) // Low-Voltage Detect Flag
#define PMC_LVDSC1_LVDACK ((uint8_t)0x40) // Low-Voltage Detect Acknowledge
#define PMC_LVDSC1_LVDIE ((uint8_t)0x20) // Low-Voltage Detect Interrupt Enable
#define PMC_LVDSC1_LVDRE ((uint8_t)0x10) // Low-Voltage Detect Reset Enable
#define PMC_LVDSC1_LVDV(n) ((uint8_t)((n) & 0x03)) // Low-Voltage Detect Voltage Select
#define PMC_LVDSC2 (*(volatile uint8_t *)0x4007D001) // Low Voltage Detect Status And Control 2 register
#define PMC_LVDSC2_LVWF ((uint8_t)0x80) // Low-Voltage Warning Flag
#define PMC_LVDSC2_LVWACK ((uint8_t)0x40) // Low-Voltage Warning Acknowledge
#define PMC_LVDSC2_LVWIE ((uint8_t)0x20) // Low-Voltage Warning Interrupt Enable
#define PMC_LVDSC2_LVWV(n) ((uint8_t)((n) & 0x03)) // Low-Voltage Warning Voltage Select
#define PMC_REGSC (*(volatile uint8_t *)0x4007D002) // Regulator Status And Control register
#define PMC_REGSC_BGEN ((uint8_t)0x10) // Bandgap Enable In VLPx Operation
#define PMC_REGSC_ACKISO ((uint8_t)0x08) // Acknowledge Isolation
#define PMC_REGSC_REGONS ((uint8_t)0x04) // Regulator In Run Regulation Status
#define PMC_REGSC_BGBE ((uint8_t)0x01) // Bandgap Buffer Enable
// Low-Leakage Wakeup Unit (LLWU)
#if defined(HAS_KINETIS_LLWU_32CH)
#define LLWU_PE1 (*(volatile uint8_t *)0x4007C000) // LLWU Pin Enable 1 register
#define LLWU_PE_WUPE_PIN_DISABLE ((uint8_t)0x00) // Disable pin as wakeup pin
#define LLWU_PE_WUPE_PIN_RISING ((uint8_t)0x01) // Enable pin rising edge detect
#define LLWU_PE_WUPE_PIN_FALLING ((uint8_t)0x10) // Enable pin falling edge detect
#define LLWU_PE_WUPE_PIN_ANY ((uint8_t)0x11) // Enable pin with any change detect
#define LLWU_PE1_WUPE0(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P0
#define LLWU_PE1_WUPE1(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P1
#define LLWU_PE1_WUPE2(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P2
#define LLWU_PE1_WUPE3(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P3
#define LLWU_PE2 (*(volatile uint8_t *)0x4007C001) // LLWU Pin Enable 2 register
#define LLWU_PE2_WUPE4(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P4
#define LLWU_PE2_WUPE5(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P5
#define LLWU_PE2_WUPE6(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P6
#define LLWU_PE2_WUPE7(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P7
#define LLWU_PE3 (*(volatile uint8_t *)0x4007C002) // LLWU Pin Enable 3 register
#define LLWU_PE3_WUPE8(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P8
#define LLWU_PE3_WUPE9(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P9
#define LLWU_PE3_WUPE10(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P10
#define LLWU_PE3_WUPE11(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P11
#define LLWU_PE4 (*(volatile uint8_t *)0x4007C003) // LLWU Pin Enable 4 register
#define LLWU_PE4_WUPE12(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P12
#define LLWU_PE4_WUPE13(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P13
#define LLWU_PE4_WUPE14(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P14
#define LLWU_PE4_WUPE15(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P15
#define LLWU_PE5 (*(volatile uint8_t *)0x4007C004) // LLWU Pin Enable 5 register
#define LLWU_PE5_WUPE19(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P19
#define LLWU_PE5_WUPE18(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P18
#define LLWU_PE5_WUPE17(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P17
#define LLWU_PE5_WUPE16(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P16
#define LLWU_PE6 (*(volatile uint8_t *)0x4007C005) // LLWU Pin Enable 6 register
#define LLWU_PE6_WUPE23(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P23
#define LLWU_PE6_WUPE22(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P22
#define LLWU_PE6_WUPE21(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P21
#define LLWU_PE6_WUPE20(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P20
#define LLWU_PE7 (*(volatile uint8_t *)0x4007C006) // LLWU Pin Enable 7 register
#define LLWU_PE7_WUPE27(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P27
#define LLWU_PE7_WUPE26(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P26
#define LLWU_PE7_WUPE25(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P25
#define LLWU_PE7_WUPE24(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P24
#define LLWU_PE8 (*(volatile uint8_t *)0x4007C007) // LLWU Pin Enable 8 register
#define LLWU_PE8_WUPE31(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P31
#define LLWU_PE8_WUPE30(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P30
#define LLWU_PE8_WUPE29(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P29
#define LLWU_PE8_WUPE28(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P28
#define LLWU_ME (*(volatile uint8_t *)0x4007C008) // LLWU Module Enable register
#define LLWU_ME_WUME0 ((uint8_t)0x01) // Wakeup Module Enable For Module 0
#define LLWU_ME_WUME1 ((uint8_t)0x02) // Wakeup Module Enable For Module 1
#define LLWU_ME_WUME2 ((uint8_t)0x04) // Wakeup Module Enable For Module 2
#define LLWU_ME_WUME3 ((uint8_t)0x08) // Wakeup Module Enable For Module 3
#define LLWU_ME_WUME4 ((uint8_t)0x10) // Wakeup Module Enable For Module 4
#define LLWU_ME_WUME5 ((uint8_t)0x20) // Wakeup Module Enable For Module 5
#define LLWU_ME_WUME6 ((uint8_t)0x40) // Wakeup Module Enable For Module 6
#define LLWU_ME_WUME7 ((uint8_t)0x80) // Wakeup Module Enable For Module 7
#define LLWU_PF1 (*(volatile uint8_t *)0x4007C009) // LLWU Pin Flag 1 register
#define LLWU_PF1_WUF0 ((uint8_t)0x01) // Wakeup Flag For LLWU_P0
#define LLWU_PF1_WUF1 ((uint8_t)0x02) // Wakeup Flag For LLWU_P1
#define LLWU_PF1_WUF2 ((uint8_t)0x04) // Wakeup Flag For LLWU_P2
#define LLWU_PF1_WUF3 ((uint8_t)0x08) // Wakeup Flag For LLWU_P3
#define LLWU_PF1_WUF4 ((uint8_t)0x10) // Wakeup Flag For LLWU_P4
#define LLWU_PF1_WUF5 ((uint8_t)0x20) // Wakeup Flag For LLWU_P5
#define LLWU_PF1_WUF6 ((uint8_t)0x40) // Wakeup Flag For LLWU_P6
#define LLWU_PF1_WUF7 ((uint8_t)0x80) // Wakeup Flag For LLWU_P7
#define LLWU_PF2 (*(volatile uint8_t *)0x4007C00A) // LLWU Pin Flag 2 register
#define LLWU_PF2_WUF8 ((uint8_t)0x01) // Wakeup Flag For LLWU_P8
#define LLWU_PF2_WUF9 ((uint8_t)0x02) // Wakeup Flag For LLWU_P9
#define LLWU_PF2_WUF10 ((uint8_t)0x04) // Wakeup Flag For LLWU_P10
#define LLWU_PF2_WUF11 ((uint8_t)0x08) // Wakeup Flag For LLWU_P11
#define LLWU_PF2_WUF12 ((uint8_t)0x10) // Wakeup Flag For LLWU_P12
#define LLWU_PF2_WUF13 ((uint8_t)0x20) // Wakeup Flag For LLWU_P13
#define LLWU_PF2_WUF14 ((uint8_t)0x40) // Wakeup Flag For LLWU_P14
#define LLWU_PF2_WUF15 ((uint8_t)0x80) // Wakeup Flag For LLWU_P15
#define LLWU_PF3 (*(volatile uint8_t *)0x4007C00B) // LLWU Pin Flag 3 register
#define LLWU_PF3_WUF16 ((uint8_t)0x01) // Wakeup Flag For LLWU_P16
#define LLWU_PF3_WUF17 ((uint8_t)0x02) // Wakeup Flag For LLWU_P17
#define LLWU_PF3_WUF18 ((uint8_t)0x04) // Wakeup Flag For LLWU_P18
#define LLWU_PF3_WUF19 ((uint8_t)0x08) // Wakeup Flag For LLWU_P19
#define LLWU_PF3_WUF20 ((uint8_t)0x10) // Wakeup Flag For LLWU_P20
#define LLWU_PF3_WUF21 ((uint8_t)0x20) // Wakeup Flag For LLWU_P21
#define LLWU_PF3_WUF22 ((uint8_t)0x40) // Wakeup Flag For LLWU_P22
#define LLWU_PF3_WUF23 ((uint8_t)0x80) // Wakeup Flag For LLWU_P23
#define LLWU_PF4 (*(volatile uint8_t *)0x4007C00C) // LLWU Pin Flag 4 register
#define LLWU_PF4_WUF31 ((uint8_t)0x01) // Wakeup Flag For LLWU_P31
#define LLWU_PF4_WUF30 ((uint8_t)0x02) // Wakeup Flag For LLWU_P30
#define LLWU_PF4_WUF29 ((uint8_t)0x04) // Wakeup Flag For LLWU_P29
#define LLWU_PF4_WUF28 ((uint8_t)0x08) // Wakeup Flag For LLWU_P28
#define LLWU_PF4_WUF27 ((uint8_t)0x10) // Wakeup Flag For LLWU_P27
#define LLWU_PF4_WUF26 ((uint8_t)0x20) // Wakeup Flag For LLWU_P26
#define LLWU_PF4_WUF25 ((uint8_t)0x40) // Wakeup Flag For LLWU_P25
#define LLWU_PF4_WUF24 ((uint8_t)0x80) // Wakeup Flag For LLWU_P24
#define LLWU_MF5 (*(volatile uint8_t *)0x4007C00D) // LLWU Module Flag 5 register
#define LLWU_MF5_MWUF0 ((uint8_t)0x01) // Wakeup flag For module 0
#define LLWU_MF5_MWUF1 ((uint8_t)0x02) // Wakeup flag For module 1
#define LLWU_MF5_MWUF2 ((uint8_t)0x04) // Wakeup flag For module 2
#define LLWU_MF5_MWUF3 ((uint8_t)0x08) // Wakeup flag For module 3
#define LLWU_MF5_MWUF4 ((uint8_t)0x10) // Wakeup flag For module 4
#define LLWU_MF5_MWUF5 ((uint8_t)0x20) // Wakeup flag For module 5
#define LLWU_MF5_MWUF6 ((uint8_t)0x40) // Wakeup flag For module 6
#define LLWU_MF5_MWUF7 ((uint8_t)0x80) // Wakeup flag For module 7
#define LLWU_FILT1 (*(volatile uint8_t *)0x4007C00E) // LLWU Pin Filter 1 register
#define LLWU_FILT2 (*(volatile uint8_t *)0x4007C00F) // LLWU Pin Filter 2 register
#define LLWU_FILT3 (*(volatile uint8_t *)0x4007C010) // LLWU Pin Filter 3 register
#define LLWU_FILT4 (*(volatile uint8_t *)0x4007C011) // LLWU Pin Filter 4 register
#elif defined(HAS_KINETIS_LLWU_16CH)
#define LLWU_PE1 (*(volatile uint8_t *)0x4007C000) // LLWU Pin Enable 1 register
#define LLWU_PE_WUPE_PIN_DISABLE ((uint8_t)0x00) // Disable pin as wakeup pin
#define LLWU_PE_WUPE_PIN_RISING ((uint8_t)0x01) // Enable pin rising edge detect
#define LLWU_PE_WUPE_PIN_FALLING ((uint8_t)0x10) // Enable pin falling edge detect
#define LLWU_PE_WUPE_PIN_ANY ((uint8_t)0x11) // Enable pin with any change detect
#define LLWU_PE1_WUPE0(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P0
#define LLWU_PE1_WUPE1(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P1
#define LLWU_PE1_WUPE2(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P2
#define LLWU_PE1_WUPE3(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P3
#define LLWU_PE2 (*(volatile uint8_t *)0x4007C001) // LLWU Pin Enable 2 register
#define LLWU_PE2_WUPE4(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P4
#define LLWU_PE2_WUPE5(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P5
#define LLWU_PE2_WUPE6(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P6
#define LLWU_PE2_WUPE7(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P7
#define LLWU_PE3 (*(volatile uint8_t *)0x4007C002) // LLWU Pin Enable 3 register
#define LLWU_PE3_WUPE8(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P8
#define LLWU_PE3_WUPE9(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P9
#define LLWU_PE3_WUPE10(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P10
#define LLWU_PE3_WUPE11(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P11
#define LLWU_PE4 (*(volatile uint8_t *)0x4007C003) // LLWU Pin Enable 4 register
#define LLWU_PE4_WUPE12(n) ((uint8_t)((n) & 0x03)) // Wakeup Pin Enable For LLWU_P12
#define LLWU_PE4_WUPE13(n) ((uint8_t)(((n) & 0x03) << 2)) // Wakeup Pin Enable For LLWU_P13
#define LLWU_PE4_WUPE14(n) ((uint8_t)(((n) & 0x03) << 4)) // Wakeup Pin Enable For LLWU_P14
#define LLWU_PE4_WUPE15(n) ((uint8_t)(((n) & 0x03) << 6)) // Wakeup Pin Enable For LLWU_P15
#define LLWU_ME (*(volatile uint8_t *)0x4007C004) // LLWU Module Enable register
#define LLWU_ME_WUME0 ((uint8_t)0x01) // Wakeup Module Enable For Module 0
#define LLWU_ME_WUME1 ((uint8_t)0x02) // Wakeup Module Enable For Module 1
#define LLWU_ME_WUME2 ((uint8_t)0x04) // Wakeup Module Enable For Module 2
#define LLWU_ME_WUME3 ((uint8_t)0x08) // Wakeup Module Enable For Module 3
#define LLWU_ME_WUME4 ((uint8_t)0x10) // Wakeup Module Enable For Module 4
#define LLWU_ME_WUME5 ((uint8_t)0x20) // Wakeup Module Enable For Module 5
#define LLWU_ME_WUME6 ((uint8_t)0x40) // Wakeup Module Enable For Module 6
#define LLWU_ME_WUME7 ((uint8_t)0x80) // Wakeup Module Enable For Module 7
#define LLWU_F1 (*(volatile uint8_t *)0x4007C005) // LLWU Flag 1 register
#define LLWU_F1_WUF0 ((uint8_t)0x01) // Wakeup Flag For LLWU_P0
#define LLWU_F1_WUF1 ((uint8_t)0x02) // Wakeup Flag For LLWU_P1
#define LLWU_F1_WUF2 ((uint8_t)0x04) // Wakeup Flag For LLWU_P2
#define LLWU_F1_WUF3 ((uint8_t)0x08) // Wakeup Flag For LLWU_P3
#define LLWU_F1_WUF4 ((uint8_t)0x10) // Wakeup Flag For LLWU_P4
#define LLWU_F1_WUF5 ((uint8_t)0x20) // Wakeup Flag For LLWU_P5
#define LLWU_F1_WUF6 ((uint8_t)0x40) // Wakeup Flag For LLWU_P6
#define LLWU_F1_WUF7 ((uint8_t)0x80) // Wakeup Flag For LLWU_P7
#define LLWU_F2 (*(volatile uint8_t *)0x4007C006) // LLWU Flag 2 register
#define LLWU_F2_WUF8 ((uint8_t)0x01) // Wakeup Flag For LLWU_P8
#define LLWU_F2_WUF9 ((uint8_t)0x02) // Wakeup Flag For LLWU_P9
#define LLWU_F2_WUF10 ((uint8_t)0x04) // Wakeup Flag For LLWU_P10
#define LLWU_F2_WUF11 ((uint8_t)0x08) // Wakeup Flag For LLWU_P11
#define LLWU_F2_WUF12 ((uint8_t)0x10) // Wakeup Flag For LLWU_P12
#define LLWU_F2_WUF13 ((uint8_t)0x20) // Wakeup Flag For LLWU_P13
#define LLWU_F2_WUF14 ((uint8_t)0x40) // Wakeup Flag For LLWU_P14
#define LLWU_F2_WUF15 ((uint8_t)0x80) // Wakeup Flag For LLWU_P15
#define LLWU_F3 (*(volatile uint8_t *)0x4007C007) // LLWU Flag 3 register
#define LLWU_F3_MWUF0 ((uint8_t)0x01) // Wakeup flag For module 0
#define LLWU_F3_MWUF1 ((uint8_t)0x02) // Wakeup flag For module 1
#define LLWU_F3_MWUF2 ((uint8_t)0x04) // Wakeup flag For module 2
#define LLWU_F3_MWUF3 ((uint8_t)0x08) // Wakeup flag For module 3
#define LLWU_F3_MWUF4 ((uint8_t)0x10) // Wakeup flag For module 4
#define LLWU_F3_MWUF5 ((uint8_t)0x20) // Wakeup flag For module 5
#define LLWU_F3_MWUF6 ((uint8_t)0x40) // Wakeup flag For module 6
#define LLWU_F3_MWUF7 ((uint8_t)0x80) // Wakeup flag For module 7
#define LLWU_FILT1 (*(volatile uint8_t *)0x4007C008) // LLWU Pin Filter 1 register
#define LLWU_FILT2 (*(volatile uint8_t *)0x4007C009) // LLWU Pin Filter 2 register
#define LLWU_RST (*(volatile uint8_t *)0x4007C00A) // LLWU Reset Enable register
#endif
// Miscellaneous Control Module (MCM)
#if defined(KINETISK)
#define MCM_PLASC (*(volatile uint16_t *)0xE0080008) // Crossbar Switch (AXBS) Slave Configuration
#define MCM_PLAMC (*(volatile uint16_t *)0xE008000A) // Crossbar Switch (AXBS) Master Configuration
#define MCM_PLACR (*(volatile uint32_t *)0xE008000C) // Crossbar Switch (AXBS) Control Register (MK20DX128)
#define MCM_PLACR_ARG ((uint32_t)0x00000200) // Arbitration select, 0=fixed, 1=round-robin
#define MCM_CR (*(volatile uint32_t *)0xE008000C) // RAM arbitration control register (MK20DX256)
#define MCM_CR_SRAMLWP ((uint32_t)0x40000000) // SRAM_L write protect
#define MCM_CR_SRAMLAP(n) ((uint32_t)(((n) & 0x03) << 28)) // SRAM_L priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
#define MCM_CR_SRAMUWP ((uint32_t)0x04000000) // SRAM_U write protect
#define MCM_CR_SRAMUAP(n) ((uint32_t)(((n) & 0x03) << 24)) // SRAM_U priority, 0=RR, 1=favor DMA, 2=CPU, 3=DMA
#define MCM_ISCR (*(volatile uint32_t *)0xE0080010) // Interrupt Status Register
#define MCM_ETBCC (*(volatile uint32_t *)0xE0080014) // ETB Counter Control register
#define MCM_ETBRL (*(volatile uint32_t *)0xE0080018) // ETB Reload register
#define MCM_ETBCNT (*(volatile uint32_t *)0xE008001C) // ETB Counter Value register
#define MCM_FADR (*(volatile uint32_t *)0xE0080020) // Fault address register
#define MCM_FATR (*(volatile uint32_t *)0xE0080024) // Fault attributes register
#define MCM_FDR (*(volatile uint32_t *)0xE0080028) // Fault data register
#define MCM_PID (*(volatile uint32_t *)0xE0080030) // Process ID register
#define MCM_CPO (*(volatile uint32_t *)0xE0080040) // Compute Operation Control Register
#elif defined(KINETISL)
#define MCM_PLASC (*(volatile uint16_t *)0xF0003008) // Crossbar Switch (AXBS) Slave Configuration
#define MCM_PLAMC (*(volatile uint16_t *)0xF000300A) // Crossbar Switch (AXBS) Master Configuration
#define MCM_PLACR (*(volatile uint32_t *)0xF000300C) // Platform Control Register
#define MCM_PLACR_ESFC ((uint32_t)0x00010000) // Enable Stalling Flash Controller
#define MCM_PLACR_DFCS ((uint32_t)0x00008000) // Disable Flash Controller Speculation
#define MCM_PLACR_EFDS ((uint32_t)0x00004000) // Enable Flash Data Speculation
#define MCM_PLACR_DFCC ((uint32_t)0x00002000) // Disable Flash Controller Cache
#define MCM_PLACR_DFCIC ((uint32_t)0x00001000) // Disable Flash Controller Instruction Caching
#define MCM_PLACR_DFCDA ((uint32_t)0x00000800) // Disable Flash Controller Data Caching
#define MCM_PLACR_CFCC ((uint32_t)0x00000400) // Clear Flash Controller Cache
#define MCM_PLACR_ARB ((uint32_t)0x00000200) // Arbitration select
#define MCM_CPO (*(volatile uint32_t *)0xF0003040) // Compute Operation Control Register
#endif
// Crossbar Switch (AXBS) - not programmable on MK20DX128 & Kinetis-L
#define AXBS_PRS0 (*(volatile uint32_t *)0x40004000) // Priority Registers Slave 0
#define AXBS_CRS0 (*(volatile uint32_t *)0x40004010) // Control Register 0
#define AXBS_PRS1 (*(volatile uint32_t *)0x40004100) // Priority Registers Slave 1
#define AXBS_CRS1 (*(volatile uint32_t *)0x40004110) // Control Register 1
#define AXBS_PRS2 (*(volatile uint32_t *)0x40004200) // Priority Registers Slave 2
#define AXBS_CRS2 (*(volatile uint32_t *)0x40004210) // Control Register 2
#define AXBS_PRS3 (*(volatile uint32_t *)0x40004300) // Priority Registers Slave 3
#define AXBS_CRS3 (*(volatile uint32_t *)0x40004310) // Control Register 3
#define AXBS_PRS4 (*(volatile uint32_t *)0x40004400) // Priority Registers Slave 4
#define AXBS_CRS4 (*(volatile uint32_t *)0x40004410) // Control Register 4
#define AXBS_PRS5 (*(volatile uint32_t *)0x40004500) // Priority Registers Slave 5
#define AXBS_CRS5 (*(volatile uint32_t *)0x40004510) // Control Register 5
#define AXBS_PRS6 (*(volatile uint32_t *)0x40004600) // Priority Registers Slave 6
#define AXBS_CRS6 (*(volatile uint32_t *)0x40004610) // Control Register 6
#define AXBS_PRS7 (*(volatile uint32_t *)0x40004700) // Priority Registers Slave 7
#define AXBS_CRS7 (*(volatile uint32_t *)0x40004710) // Control Register 7
#define AXBS_MGPCR0 (*(volatile uint32_t *)0x40004800) // Master 0 General Purpose Control Register
#define AXBS_MGPCR1 (*(volatile uint32_t *)0x40004900) // Master 1 General Purpose Control Register
#define AXBS_MGPCR2 (*(volatile uint32_t *)0x40004A00) // Master 2 General Purpose Control Register
#define AXBS_MGPCR3 (*(volatile uint32_t *)0x40004B00) // Master 3 General Purpose Control Register
#define AXBS_MGPCR4 (*(volatile uint32_t *)0x40004C00) // Master 4 General Purpose Control Register
#define AXBS_MGPCR5 (*(volatile uint32_t *)0x40004D00) // Master 5 General Purpose Control Register
#define AXBS_MGPCR6 (*(volatile uint32_t *)0x40004E00) // Master 6 General Purpose Control Register
#define AXBS_MGPCR7 (*(volatile uint32_t *)0x40004F00) // Master 7 General Purpose Control Register
#define AXBS_CRS_READONLY ((uint32_t)0x80000000)
#define AXBS_CRS_HALTLOWPRIORITY ((uint32_t)0x40000000)
#define AXBS_CRS_ARB_FIXED ((uint32_t)0x00000000)
#define AXBS_CRS_ARB_ROUNDROBIN ((uint32_t)0x00010000)
#define AXBS_CRS_PARK_FIXED ((uint32_t)0x00000000)
#define AXBS_CRS_PARK_PREVIOUS ((uint32_t)0x00000010)
#define AXBS_CRS_PARK_NONE ((uint32_t)0x00000020)
#define AXBS_CRS_PARK(n) ((uint32_t)(((n) & 7) << 0))
// Peripheral Bridge (AIPS-Lite)
#define AIPS0_MPRA (*(volatile uint32_t *)0x40000000) // Master Privilege Register A
#define AIPS0_PACRA (*(volatile uint32_t *)0x40000020) // Peripheral Access Control Register
#define AIPS0_PACRB (*(volatile uint32_t *)0x40000024) // Peripheral Access Control Register
#define AIPS0_PACRC (*(volatile uint32_t *)0x40000028) // Peripheral Access Control Register
#define AIPS0_PACRD (*(volatile uint32_t *)0x4000002C) // Peripheral Access Control Register
#define AIPS0_PACRE (*(volatile uint32_t *)0x40000040) // Peripheral Access Control Register
#define AIPS0_PACRF (*(volatile uint32_t *)0x40000044) // Peripheral Access Control Register
#define AIPS0_PACRG (*(volatile uint32_t *)0x40000048) // Peripheral Access Control Register
#define AIPS0_PACRH (*(volatile uint32_t *)0x4000004C) // Peripheral Access Control Register
#define AIPS0_PACRI (*(volatile uint32_t *)0x40000050) // Peripheral Access Control Register
#define AIPS0_PACRJ (*(volatile uint32_t *)0x40000054) // Peripheral Access Control Register
#define AIPS0_PACRK (*(volatile uint32_t *)0x40000058) // Peripheral Access Control Register
#define AIPS0_PACRL (*(volatile uint32_t *)0x4000005C) // Peripheral Access Control Register
#define AIPS0_PACRM (*(volatile uint32_t *)0x40000060) // Peripheral Access Control Register
#define AIPS0_PACRN (*(volatile uint32_t *)0x40000064) // Peripheral Access Control Register
#define AIPS0_PACRO (*(volatile uint32_t *)0x40000068) // Peripheral Access Control Register
#define AIPS0_PACRP (*(volatile uint32_t *)0x4000006C) // Peripheral Access Control Register
#define AIPS1_MPRA (*(volatile uint32_t *)0x40080000) // Master Privilege Register A
#define AIPS1_PACRA (*(volatile uint32_t *)0x40080020) // Peripheral Access Control Register
#define AIPS1_PACRB (*(volatile uint32_t *)0x40080024) // Peripheral Access Control Register
#define AIPS1_PACRC (*(volatile uint32_t *)0x40080028) // Peripheral Access Control Register
#define AIPS1_PACRD (*(volatile uint32_t *)0x4008002C) // Peripheral Access Control Register
#define AIPS1_PACRE (*(volatile uint32_t *)0x40080040) // Peripheral Access Control Register
#define AIPS1_PACRF (*(volatile uint32_t *)0x40080044) // Peripheral Access Control Register
#define AIPS1_PACRG (*(volatile uint32_t *)0x40080048) // Peripheral Access Control Register
#define AIPS1_PACRH (*(volatile uint32_t *)0x4008004C) // Peripheral Access Control Register
#define AIPS1_PACRI (*(volatile uint32_t *)0x40080050) // Peripheral Access Control Register
#define AIPS1_PACRJ (*(volatile uint32_t *)0x40080054) // Peripheral Access Control Register
#define AIPS1_PACRK (*(volatile uint32_t *)0x40080058) // Peripheral Access Control Register
#define AIPS1_PACRL (*(volatile uint32_t *)0x4008005C) // Peripheral Access Control Register
#define AIPS1_PACRM (*(volatile uint32_t *)0x40080060) // Peripheral Access Control Register
#define AIPS1_PACRN (*(volatile uint32_t *)0x40080064) // Peripheral Access Control Register
#define AIPS1_PACRO (*(volatile uint32_t *)0x40080068) // Peripheral Access Control Register
#define AIPS1_PACRP (*(volatile uint32_t *)0x4008006C) // Peripheral Access Control Register
// Memory Protection Unit (MPU)
#if defined(HAS_KINETIS_MPU)
#define MPU_CESR (*(volatile uint32_t *)0x4000D000) // Control/Error Status Register
#define MPU_EAR0 (*(volatile uint32_t *)0x4000D010) // Error Address Register, slave port 0
#define MPU_EDR0 (*(volatile uint32_t *)0x4000D014) // Error Detail Register, slave port 0
#define MPU_EAR1 (*(volatile uint32_t *)0x4000D018) // Error Address Register, slave port 1
#define MPU_EDR1 (*(volatile uint32_t *)0x4000D01C) // Error Detail Register, slave port 1
#define MPU_EAR2 (*(volatile uint32_t *)0x4000D020) // Error Address Register, slave port 2
#define MPU_EDR2 (*(volatile uint32_t *)0x4000D024) // Error Detail Register, slave port 2
#define MPU_EAR3 (*(volatile uint32_t *)0x4000D028) // Error Address Register, slave port 3
#define MPU_EDR3 (*(volatile uint32_t *)0x4000D02C) // Error Detail Register, slave port 3
#define MPU_EAR4 (*(volatile uint32_t *)0x4000D030) // Error Address Register, slave port 4
#define MPU_EDR4 (*(volatile uint32_t *)0x4000D034) // Error Detail Register, slave port 4
#define MPU_RGD0_WORD0 (*(volatile uint32_t *)0x4000D400) // Region Descriptor 0, Word 0
#define MPU_RGD0_WORD1 (*(volatile uint32_t *)0x4000D404) // Region Descriptor 0, Word 1
#define MPU_RGD0_WORD2 (*(volatile uint32_t *)0x4000D408) // Region Descriptor 0, Word 2
#define MPU_RGD0_WORD3 (*(volatile uint32_t *)0x4000D40C) // Region Descriptor 0, Word 3
#define MPU_RGD1_WORD0 (*(volatile uint32_t *)0x4000D410) // Region Descriptor 1, Word 0
#define MPU_RGD1_WORD1 (*(volatile uint32_t *)0x4000D414) // Region Descriptor 1, Word 1
#define MPU_RGD1_WORD2 (*(volatile uint32_t *)0x4000D418) // Region Descriptor 1, Word 2
#define MPU_RGD1_WORD3 (*(volatile uint32_t *)0x4000D41C) // Region Descriptor 1, Word 3
#define MPU_RGD2_WORD0 (*(volatile uint32_t *)0x4000D420) // Region Descriptor 2, Word 0
#define MPU_RGD2_WORD1 (*(volatile uint32_t *)0x4000D424) // Region Descriptor 2, Word 1
#define MPU_RGD2_WORD2 (*(volatile uint32_t *)0x4000D428) // Region Descriptor 2, Word 2
#define MPU_RGD2_WORD3 (*(volatile uint32_t *)0x4000D42C) // Region Descriptor 2, Word 3
#define MPU_RGD3_WORD0 (*(volatile uint32_t *)0x4000D430) // Region Descriptor 3, Word 0
#define MPU_RGD3_WORD1 (*(volatile uint32_t *)0x4000D434) // Region Descriptor 3, Word 1
#define MPU_RGD3_WORD2 (*(volatile uint32_t *)0x4000D438) // Region Descriptor 3, Word 2
#define MPU_RGD3_WORD3 (*(volatile uint32_t *)0x4000D43C) // Region Descriptor 3, Word 3
#define MPU_RGD4_WORD0 (*(volatile uint32_t *)0x4000D440) // Region Descriptor 4, Word 0
#define MPU_RGD4_WORD1 (*(volatile uint32_t *)0x4000D444) // Region Descriptor 4, Word 1
#define MPU_RGD4_WORD2 (*(volatile uint32_t *)0x4000D448) // Region Descriptor 4, Word 2
#define MPU_RGD4_WORD3 (*(volatile uint32_t *)0x4000D44C) // Region Descriptor 4, Word 3
#define MPU_RGD5_WORD0 (*(volatile uint32_t *)0x4000D450) // Region Descriptor 5, Word 0
#define MPU_RGD5_WORD1 (*(volatile uint32_t *)0x4000D454) // Region Descriptor 5, Word 1
#define MPU_RGD5_WORD2 (*(volatile uint32_t *)0x4000D458) // Region Descriptor 5, Word 2
#define MPU_RGD5_WORD3 (*(volatile uint32_t *)0x4000D45C) // Region Descriptor 5, Word 3
#define MPU_RGD6_WORD0 (*(volatile uint32_t *)0x4000D460) // Region Descriptor 6, Word 0
#define MPU_RGD6_WORD1 (*(volatile uint32_t *)0x4000D464) // Region Descriptor 6, Word 1
#define MPU_RGD6_WORD2 (*(volatile uint32_t *)0x4000D468) // Region Descriptor 6, Word 2
#define MPU_RGD6_WORD3 (*(volatile uint32_t *)0x4000D46C) // Region Descriptor 6, Word 3
#define MPU_RGD7_WORD0 (*(volatile uint32_t *)0x4000D470) // Region Descriptor 7, Word 0
#define MPU_RGD7_WORD1 (*(volatile uint32_t *)0x4000D474) // Region Descriptor 7, Word 1
#define MPU_RGD7_WORD2 (*(volatile uint32_t *)0x4000D478) // Region Descriptor 7, Word 2
#define MPU_RGD7_WORD3 (*(volatile uint32_t *)0x4000D47C) // Region Descriptor 7, Word 3
#define MPU_RGD8_WORD0 (*(volatile uint32_t *)0x4000D480) // Region Descriptor 8, Word 0
#define MPU_RGD8_WORD1 (*(volatile uint32_t *)0x4000D484) // Region Descriptor 8, Word 1
#define MPU_RGD8_WORD2 (*(volatile uint32_t *)0x4000D488) // Region Descriptor 8, Word 2
#define MPU_RGD8_WORD3 (*(volatile uint32_t *)0x4000D48C) // Region Descriptor 8, Word 3
#define MPU_RGD9_WORD0 (*(volatile uint32_t *)0x4000D490) // Region Descriptor 9, Word 0
#define MPU_RGD9_WORD1 (*(volatile uint32_t *)0x4000D494) // Region Descriptor 9, Word 1
#define MPU_RGD9_WORD2 (*(volatile uint32_t *)0x4000D498) // Region Descriptor 9, Word 2
#define MPU_RGD9_WORD3 (*(volatile uint32_t *)0x4000D49C) // Region Descriptor 9, Word 3
#define MPU_RGD10_WORD0 (*(volatile uint32_t *)0x4000D4A0) // Region Descriptor 10, Word 0
#define MPU_RGD10_WORD1 (*(volatile uint32_t *)0x4000D4A4) // Region Descriptor 10, Word 1
#define MPU_RGD10_WORD2 (*(volatile uint32_t *)0x4000D4A8) // Region Descriptor 10, Word 2
#define MPU_RGD10_WORD3 (*(volatile uint32_t *)0x4000D4AC) // Region Descriptor 10, Word 3
#define MPU_RGD11_WORD0 (*(volatile uint32_t *)0x4000D4B0) // Region Descriptor 11, Word 0
#define MPU_RGD11_WORD1 (*(volatile uint32_t *)0x4000D4B4) // Region Descriptor 11, Word 1
#define MPU_RGD11_WORD2 (*(volatile uint32_t *)0x4000D4B8) // Region Descriptor 11, Word 2
#define MPU_RGD11_WORD3 (*(volatile uint32_t *)0x4000D4BC) // Region Descriptor 11, Word 3
#define MPU_RGDAAC0 (*(volatile uint32_t *)0x4000D800) // Region Descriptor Alternate Access Control 0
#define MPU_RGDAAC1 (*(volatile uint32_t *)0x4000D804) // Region Descriptor Alternate Access Control 1
#define MPU_RGDAAC2 (*(volatile uint32_t *)0x4000D808) // Region Descriptor Alternate Access Control 2
#define MPU_RGDAAC3 (*(volatile uint32_t *)0x4000D80C) // Region Descriptor Alternate Access Control 3
#define MPU_RGDAAC4 (*(volatile uint32_t *)0x4000D810) // Region Descriptor Alternate Access Control 4
#define MPU_RGDAAC5 (*(volatile uint32_t *)0x4000D814) // Region Descriptor Alternate Access Control 5
#define MPU_RGDAAC6 (*(volatile uint32_t *)0x4000D818) // Region Descriptor Alternate Access Control 6
#define MPU_RGDAAC7 (*(volatile uint32_t *)0x4000D81C) // Region Descriptor Alternate Access Control 7
#define MPU_RGDAAC8 (*(volatile uint32_t *)0x4000D820) // Region Descriptor Alternate Access Control 8
#define MPU_RGDAAC9 (*(volatile uint32_t *)0x4000D824) // Region Descriptor Alternate Access Control 9
#define MPU_RGDAAC10 (*(volatile uint32_t *)0x4000D828) // Region Descriptor Alternate Access Control 10
#define MPU_RGDAAC11 (*(volatile uint32_t *)0x4000D82C) // Region Descriptor Alternate Access Control 11
#endif
// Direct Memory Access Multiplexer (DMAMUX)
#if DMA_NUM_CHANNELS >= 4
#define DMAMUX0_CHCFG0 (*(volatile uint8_t *)0x40021000) // Channel Configuration register
#define DMAMUX0_CHCFG1 (*(volatile uint8_t *)0x40021001) // Channel Configuration register
#define DMAMUX0_CHCFG2 (*(volatile uint8_t *)0x40021002) // Channel Configuration register
#define DMAMUX0_CHCFG3 (*(volatile uint8_t *)0x40021003) // Channel Configuration register
#endif
#if DMA_NUM_CHANNELS >= 16
#define DMAMUX0_CHCFG4 (*(volatile uint8_t *)0x40021004) // Channel Configuration register
#define DMAMUX0_CHCFG5 (*(volatile uint8_t *)0x40021005) // Channel Configuration register
#define DMAMUX0_CHCFG6 (*(volatile uint8_t *)0x40021006) // Channel Configuration register
#define DMAMUX0_CHCFG7 (*(volatile uint8_t *)0x40021007) // Channel Configuration register
#define DMAMUX0_CHCFG8 (*(volatile uint8_t *)0x40021008) // Channel Configuration register
#define DMAMUX0_CHCFG9 (*(volatile uint8_t *)0x40021009) // Channel Configuration register
#define DMAMUX0_CHCFG10 (*(volatile uint8_t *)0x4002100A) // Channel Configuration register
#define DMAMUX0_CHCFG11 (*(volatile uint8_t *)0x4002100B) // Channel Configuration register
#define DMAMUX0_CHCFG12 (*(volatile uint8_t *)0x4002100C) // Channel Configuration register
#define DMAMUX0_CHCFG13 (*(volatile uint8_t *)0x4002100D) // Channel Configuration register
#define DMAMUX0_CHCFG14 (*(volatile uint8_t *)0x4002100E) // Channel Configuration register
#define DMAMUX0_CHCFG15 (*(volatile uint8_t *)0x4002100F) // Channel Configuration register
#endif
#if DMA_NUM_CHANNELS >= 32
#define DMAMUX0_CHCFG16 (*(volatile uint8_t *)0x40021010) // Channel Configuration register
#define DMAMUX0_CHCFG17 (*(volatile uint8_t *)0x40021011) // Channel Configuration register
#define DMAMUX0_CHCFG18 (*(volatile uint8_t *)0x40021012) // Channel Configuration register
#define DMAMUX0_CHCFG19 (*(volatile uint8_t *)0x40021013) // Channel Configuration register
#define DMAMUX0_CHCFG20 (*(volatile uint8_t *)0x40021014) // Channel Configuration register
#define DMAMUX0_CHCFG21 (*(volatile uint8_t *)0x40021015) // Channel Configuration register
#define DMAMUX0_CHCFG22 (*(volatile uint8_t *)0x40021016) // Channel Configuration register
#define DMAMUX0_CHCFG23 (*(volatile uint8_t *)0x40021017) // Channel Configuration register
#define DMAMUX0_CHCFG24 (*(volatile uint8_t *)0x40021018) // Channel Configuration register
#define DMAMUX0_CHCFG25 (*(volatile uint8_t *)0x40021019) // Channel Configuration register
#define DMAMUX0_CHCFG26 (*(volatile uint8_t *)0x4002101A) // Channel Configuration register
#define DMAMUX0_CHCFG27 (*(volatile uint8_t *)0x4002101B) // Channel Configuration register
#define DMAMUX0_CHCFG28 (*(volatile uint8_t *)0x4002101C) // Channel Configuration register
#define DMAMUX0_CHCFG29 (*(volatile uint8_t *)0x4002101D) // Channel Configuration register
#define DMAMUX0_CHCFG30 (*(volatile uint8_t *)0x4002101E) // Channel Configuration register
#define DMAMUX0_CHCFG31 (*(volatile uint8_t *)0x4002101F) // Channel Configuration register
#endif
#define DMAMUX_DISABLE 0
#define DMAMUX_TRIG 64
#define DMAMUX_ENABLE 128
// Direct Memory Access Controller (eDMA)
#if defined(KINETISK)
#define DMA_CR (*(volatile uint32_t *)0x40008000) // Control Register
#define DMA_CR_CX ((uint32_t)(1<<17)) // Cancel Transfer
#define DMA_CR_ECX ((uint32_t)(1<<16)) // Error Cancel Transfer
#define DMA_CR_EMLM ((uint32_t)0x80) // Enable Minor Loop Mapping
#define DMA_CR_CLM ((uint32_t)0x40) // Continuous Link Mode
#define DMA_CR_HALT ((uint32_t)0x20) // Halt DMA Operations
#define DMA_CR_HOE ((uint32_t)0x10) // Halt On Error
#define DMA_CR_ERCA ((uint32_t)0x04) // Enable Round Robin Channel Arbitration
#define DMA_CR_EDBG ((uint32_t)0x02) // Enable Debug
#define DMA_ES (*(volatile uint32_t *)0x40008004) // Error Status Register
#define DMA_ERQ (*(volatile uint32_t *)0x4000800C) // Enable Request Register
#define DMA_EEI (*(volatile uint32_t *)0x40008014) // Enable Error Interrupt Register
#define DMA_CEEI (*(volatile uint8_t *)0x40008018) // Clear Enable Error Interrupt Register
#define DMA_CEEI_CEEI(n) ((uint8_t)(n & 15)<<0) // Clear Enable Error Interrupt
#define DMA_CEEI_CAEE ((uint8_t)1<<6) // Clear All Enable Error Interrupts
#define DMA_CEEI_NOP ((uint8_t)1<<7) // NOP
#define DMA_SEEI (*(volatile uint8_t *)0x40008019) // Set Enable Error Interrupt Register
#define DMA_SEEI_SEEI(n) ((uint8_t)(n & 15)<<0) // Set Enable Error Interrupt
#define DMA_SEEI_SAEE ((uint8_t)1<<6) // Set All Enable Error Interrupts
#define DMA_SEEI_NOP ((uint8_t)1<<7) // NOP
#define DMA_CERQ (*(volatile uint8_t *)0x4000801A) // Clear Enable Request Register
#define DMA_CERQ_CERQ(n) ((uint8_t)(n & 15)<<0) // Clear Enable Request
#define DMA_CERQ_CAER ((uint8_t)1<<6) // Clear All Enable Requests
#define DMA_CERQ_NOP ((uint8_t)1<<7) // NOP
#define DMA_SERQ (*(volatile uint8_t *)0x4000801B) // Set Enable Request Register
#define DMA_SERQ_SERQ(n) ((uint8_t)(n & 15)<<0) // Set Enable Request
#define DMA_SERQ_SAER ((uint8_t)1<<6) // Set All Enable Requests
#define DMA_SERQ_NOP ((uint8_t)1<<7) // NOP
#define DMA_CDNE (*(volatile uint8_t *)0x4000801C) // Clear DONE Status Bit Register
#define DMA_CDNE_CDNE(n) ((uint8_t)(n & 15)<<0) // Clear Done Bit
#define DMA_CDNE_CADN ((uint8_t)1<<6) // Clear All Done Bits
#define DMA_CDNE_NOP ((uint8_t)1<<7) // NOP
#define DMA_SSRT (*(volatile uint8_t *)0x4000801D) // Set START Bit Register
#define DMA_SSRT_SSRT(n) ((uint8_t)(n & 15)<<0) // Set Start Bit
#define DMA_SSRT_SAST ((uint8_t)1<<6) // Set All Start Bits
#define DMA_SSRT_NOP ((uint8_t)1<<7) // NOP
#define DMA_CERR (*(volatile uint8_t *)0x4000801E) // Clear Error Register
#define DMA_CERR_CERR(n) ((uint8_t)(n & 15)<<0) // Clear Error Indicator
#define DMA_CERR_CAEI ((uint8_t)1<<6) // Clear All Error Indicators
#define DMA_CERR_NOP ((uint8_t)1<<7) // NOP
#define DMA_CINT (*(volatile uint8_t *)0x4000801F) // Clear Interrupt Request Register
#define DMA_CINT_CINT(n) ((uint8_t)(n & 15)<<0) // Clear Interrupt Request
#define DMA_CINT_CAIR ((uint8_t)1<<6) // Clear All Interrupt Requests
#define DMA_CINT_NOP ((uint8_t)1<<7) // NOP
#define DMA_INT (*(volatile uint32_t *)0x40008024) // Interrupt Request Register
#define DMA_ERR (*(volatile uint32_t *)0x4000802C) // Error Register
#define DMA_HRS (*(volatile uint32_t *)0x40008034) // Hardware Request Status Register
#if DMA_NUM_CHANNELS >= 4
#define DMA_ERQ_ERQ0 ((uint32_t)1<<0) // Enable DMA Request 0
#define DMA_ERQ_ERQ1 ((uint32_t)1<<1) // Enable DMA Request 1
#define DMA_ERQ_ERQ2 ((uint32_t)1<<2) // Enable DMA Request 2
#define DMA_ERQ_ERQ3 ((uint32_t)1<<3) // Enable DMA Request 3
#define DMA_INT_INT0 ((uint32_t)1<<0) // Interrupt Request 0
#define DMA_INT_INT1 ((uint32_t)1<<1) // Interrupt Request 1
#define DMA_INT_INT2 ((uint32_t)1<<2) // Interrupt Request 2
#define DMA_INT_INT3 ((uint32_t)1<<3) // Interrupt Request 3
#define DMA_ERR_ERR0 ((uint32_t)1<<0) // Error in Channel 0
#define DMA_ERR_ERR1 ((uint32_t)1<<1) // Error in Channel 1
#define DMA_ERR_ERR2 ((uint32_t)1<<2) // Error in Channel 2
#define DMA_ERR_ERR3 ((uint32_t)1<<3) // Error in Channel 3
#define DMA_HRS_HRS0 ((uint32_t)1<<0) // Hardware Request Status Channel 0
#define DMA_HRS_HRS1 ((uint32_t)1<<1) // Hardware Request Status Channel 1
#define DMA_HRS_HRS2 ((uint32_t)1<<2) // Hardware Request Status Channel 2
#define DMA_HRS_HRS3 ((uint32_t)1<<3) // Hardware Request Status Channel 3
#endif
#if DMA_NUM_CHANNELS >= 16
#define DMA_ERQ_ERQ4 ((uint32_t)1<<4) // Enable DMA Request 4
#define DMA_ERQ_ERQ5 ((uint32_t)1<<5) // Enable DMA Request 5
#define DMA_ERQ_ERQ6 ((uint32_t)1<<6) // Enable DMA Request 6
#define DMA_ERQ_ERQ7 ((uint32_t)1<<7) // Enable DMA Request 7
#define DMA_ERQ_ERQ8 ((uint32_t)1<<8) // Enable DMA Request 8
#define DMA_ERQ_ERQ9 ((uint32_t)1<<9) // Enable DMA Request 9
#define DMA_ERQ_ERQ10 ((uint32_t)1<<10) // Enable DMA Request 10
#define DMA_ERQ_ERQ11 ((uint32_t)1<<11) // Enable DMA Request 11
#define DMA_ERQ_ERQ12 ((uint32_t)1<<12) // Enable DMA Request 12
#define DMA_ERQ_ERQ13 ((uint32_t)1<<13) // Enable DMA Request 13
#define DMA_ERQ_ERQ14 ((uint32_t)1<<14) // Enable DMA Request 14
#define DMA_ERQ_ERQ15 ((uint32_t)1<<15) // Enable DMA Request 15
#define DMA_INT_INT4 ((uint32_t)1<<4) // Interrupt Request 4
#define DMA_INT_INT5 ((uint32_t)1<<5) // Interrupt Request 5
#define DMA_INT_INT6 ((uint32_t)1<<6) // Interrupt Request 6
#define DMA_INT_INT7 ((uint32_t)1<<7) // Interrupt Request 7
#define DMA_INT_INT8 ((uint32_t)1<<8) // Interrupt Request 8
#define DMA_INT_INT9 ((uint32_t)1<<9) // Interrupt Request 9
#define DMA_INT_INT10 ((uint32_t)1<<10) // Interrupt Request 10
#define DMA_INT_INT11 ((uint32_t)1<<11) // Interrupt Request 11
#define DMA_INT_INT12 ((uint32_t)1<<12) // Interrupt Request 12
#define DMA_INT_INT13 ((uint32_t)1<<13) // Interrupt Request 13
#define DMA_INT_INT14 ((uint32_t)1<<14) // Interrupt Request 14
#define DMA_INT_INT15 ((uint32_t)1<<15) // Interrupt Request 15
#define DMA_ERR_ERR4 ((uint32_t)1<<4) // Error in Channel 4
#define DMA_ERR_ERR5 ((uint32_t)1<<5) // Error in Channel 5
#define DMA_ERR_ERR6 ((uint32_t)1<<6) // Error in Channel 6
#define DMA_ERR_ERR7 ((uint32_t)1<<7) // Error in Channel 7
#define DMA_ERR_ERR8 ((uint32_t)1<<8) // Error in Channel 8
#define DMA_ERR_ERR9 ((uint32_t)1<<9) // Error in Channel 9
#define DMA_ERR_ERR10 ((uint32_t)1<<10) // Error in Channel 10
#define DMA_ERR_ERR11 ((uint32_t)1<<11) // Error in Channel 11
#define DMA_ERR_ERR12 ((uint32_t)1<<12) // Error in Channel 12
#define DMA_ERR_ERR13 ((uint32_t)1<<13) // Error in Channel 13
#define DMA_ERR_ERR14 ((uint32_t)1<<14) // Error in Channel 14
#define DMA_ERR_ERR15 ((uint32_t)1<<15) // Error in Channel 15
#define DMA_HRS_HRS4 ((uint32_t)1<<4) // Hardware Request Status Channel 4
#define DMA_HRS_HRS5 ((uint32_t)1<<5) // Hardware Request Status Channel 5
#define DMA_HRS_HRS6 ((uint32_t)1<<6) // Hardware Request Status Channel 6
#define DMA_HRS_HRS7 ((uint32_t)1<<7) // Hardware Request Status Channel 7
#define DMA_HRS_HRS8 ((uint32_t)1<<8) // Hardware Request Status Channel 8
#define DMA_HRS_HRS9 ((uint32_t)1<<9) // Hardware Request Status Channel 9
#define DMA_HRS_HRS10 ((uint32_t)1<<10) // Hardware Request Status Channel 10
#define DMA_HRS_HRS11 ((uint32_t)1<<11) // Hardware Request Status Channel 11
#define DMA_HRS_HRS12 ((uint32_t)1<<12) // Hardware Request Status Channel 12
#define DMA_HRS_HRS13 ((uint32_t)1<<13) // Hardware Request Status Channel 13
#define DMA_HRS_HRS14 ((uint32_t)1<<14) // Hardware Request Status Channel 14
#define DMA_HRS_HRS15 ((uint32_t)1<<15) // Hardware Request Status Channel 15
#endif
#if DMA_NUM_CHANNELS >= 32
#define DMA_ERQ_ERQ16 ((uint32_t)1<<16) // Enable DMA Request 16
#define DMA_ERQ_ERQ17 ((uint32_t)1<<17) // Enable DMA Request 17
#define DMA_ERQ_ERQ18 ((uint32_t)1<<18) // Enable DMA Request 18
#define DMA_ERQ_ERQ19 ((uint32_t)1<<19) // Enable DMA Request 19
#define DMA_ERQ_ERQ20 ((uint32_t)1<<20) // Enable DMA Request 20
#define DMA_ERQ_ERQ21 ((uint32_t)1<<21) // Enable DMA Request 21
#define DMA_ERQ_ERQ22 ((uint32_t)1<<22) // Enable DMA Request 22
#define DMA_ERQ_ERQ23 ((uint32_t)1<<23) // Enable DMA Request 23
#define DMA_ERQ_ERQ24 ((uint32_t)1<<24) // Enable DMA Request 24
#define DMA_ERQ_ERQ25 ((uint32_t)1<<25) // Enable DMA Request 25
#define DMA_ERQ_ERQ26 ((uint32_t)1<<26) // Enable DMA Request 26
#define DMA_ERQ_ERQ27 ((uint32_t)1<<27) // Enable DMA Request 27
#define DMA_ERQ_ERQ28 ((uint32_t)1<<28) // Enable DMA Request 28
#define DMA_ERQ_ERQ29 ((uint32_t)1<<29) // Enable DMA Request 29
#define DMA_ERQ_ERQ30 ((uint32_t)1<<30) // Enable DMA Request 30
#define DMA_ERQ_ERQ31 ((uint32_t)1<<31) // Enable DMA Request 31
#define DMA_INT_INT16 ((uint32_t)1<<16) // Interrupt Request 16
#define DMA_INT_INT17 ((uint32_t)1<<17) // Interrupt Request 17
#define DMA_INT_INT18 ((uint32_t)1<<18) // Interrupt Request 18
#define DMA_INT_INT19 ((uint32_t)1<<19) // Interrupt Request 19
#define DMA_INT_INT20 ((uint32_t)1<<20) // Interrupt Request 20
#define DMA_INT_INT21 ((uint32_t)1<<21) // Interrupt Request 21
#define DMA_INT_INT22 ((uint32_t)1<<22) // Interrupt Request 22
#define DMA_INT_INT23 ((uint32_t)1<<23) // Interrupt Request 23
#define DMA_INT_INT24 ((uint32_t)1<<24) // Interrupt Request 24
#define DMA_INT_INT25 ((uint32_t)1<<25) // Interrupt Request 25
#define DMA_INT_INT26 ((uint32_t)1<<26) // Interrupt Request 26
#define DMA_INT_INT27 ((uint32_t)1<<27) // Interrupt Request 27
#define DMA_INT_INT28 ((uint32_t)1<<28) // Interrupt Request 28
#define DMA_INT_INT29 ((uint32_t)1<<29) // Interrupt Request 29
#define DMA_INT_INT30 ((uint32_t)1<<30) // Interrupt Request 30
#define DMA_INT_INT31 ((uint32_t)1<<31) // Interrupt Request 31
#define DMA_ERR_ERR16 ((uint32_t)1<<16) // Error in Channel 16
#define DMA_ERR_ERR17 ((uint32_t)1<<17) // Error in Channel 17
#define DMA_ERR_ERR18 ((uint32_t)1<<18) // Error in Channel 18
#define DMA_ERR_ERR19 ((uint32_t)1<<19) // Error in Channel 19
#define DMA_ERR_ERR20 ((uint32_t)1<<20) // Error in Channel 20
#define DMA_ERR_ERR21 ((uint32_t)1<<21) // Error in Channel 21
#define DMA_ERR_ERR22 ((uint32_t)1<<22) // Error in Channel 22
#define DMA_ERR_ERR23 ((uint32_t)1<<23) // Error in Channel 23
#define DMA_ERR_ERR24 ((uint32_t)1<<24) // Error in Channel 24
#define DMA_ERR_ERR25 ((uint32_t)1<<25) // Error in Channel 25
#define DMA_ERR_ERR26 ((uint32_t)1<<26) // Error in Channel 26
#define DMA_ERR_ERR27 ((uint32_t)1<<27) // Error in Channel 27
#define DMA_ERR_ERR28 ((uint32_t)1<<28) // Error in Channel 28
#define DMA_ERR_ERR29 ((uint32_t)1<<29) // Error in Channel 29
#define DMA_ERR_ERR30 ((uint32_t)1<<30) // Error in Channel 30
#define DMA_ERR_ERR31 ((uint32_t)1<<31) // Error in Channel 31
#define DMA_HRS_HRS16 ((uint32_t)1<<16) // Hardware Request Status Channel 16
#define DMA_HRS_HRS17 ((uint32_t)1<<17) // Hardware Request Status Channel 17
#define DMA_HRS_HRS18 ((uint32_t)1<<18) // Hardware Request Status Channel 18
#define DMA_HRS_HRS19 ((uint32_t)1<<19) // Hardware Request Status Channel 19
#define DMA_HRS_HRS20 ((uint32_t)1<<20) // Hardware Request Status Channel 20
#define DMA_HRS_HRS21 ((uint32_t)1<<21) // Hardware Request Status Channel 21
#define DMA_HRS_HRS22 ((uint32_t)1<<22) // Hardware Request Status Channel 22
#define DMA_HRS_HRS23 ((uint32_t)1<<23) // Hardware Request Status Channel 23
#define DMA_HRS_HRS24 ((uint32_t)1<<24) // Hardware Request Status Channel 24
#define DMA_HRS_HRS25 ((uint32_t)1<<25) // Hardware Request Status Channel 25
#define DMA_HRS_HRS26 ((uint32_t)1<<26) // Hardware Request Status Channel 26
#define DMA_HRS_HRS27 ((uint32_t)1<<27) // Hardware Request Status Channel 27
#define DMA_HRS_HRS28 ((uint32_t)1<<28) // Hardware Request Status Channel 28
#define DMA_HRS_HRS29 ((uint32_t)1<<29) // Hardware Request Status Channel 29
#define DMA_HRS_HRS30 ((uint32_t)1<<30) // Hardware Request Status Channel 30
#define DMA_HRS_HRS31 ((uint32_t)1<<31) // Hardware Request Status Channel 31
#endif
#if DMA_NUM_CHANNELS >= 4
#define DMA_DCHPRI3 (*(volatile uint8_t *)0x40008100) // Channel n Priority Register
#define DMA_DCHPRI2 (*(volatile uint8_t *)0x40008101) // Channel n Priority Register
#define DMA_DCHPRI1 (*(volatile uint8_t *)0x40008102) // Channel n Priority Register
#define DMA_DCHPRI0 (*(volatile uint8_t *)0x40008103) // Channel n Priority Register
#endif
#define DMA_DCHPRI_CHPRI(n) ((uint8_t)(n & 15)<<0) // Channel Arbitration Priority
#define DMA_DCHPRI_DPA ((uint8_t)1<<6) // Disable PreEmpt Ability
#define DMA_DCHPRI_ECP ((uint8_t)1<<7) // Enable PreEmption
#if DMA_NUM_CHANNELS >= 16
#define DMA_DCHPRI7 (*(volatile uint8_t *)0x40008104) // Channel n Priority Register
#define DMA_DCHPRI6 (*(volatile uint8_t *)0x40008105) // Channel n Priority Register
#define DMA_DCHPRI5 (*(volatile uint8_t *)0x40008106) // Channel n Priority Register
#define DMA_DCHPRI4 (*(volatile uint8_t *)0x40008107) // Channel n Priority Register
#define DMA_DCHPRI11 (*(volatile uint8_t *)0x40008108) // Channel n Priority Register
#define DMA_DCHPRI10 (*(volatile uint8_t *)0x40008109) // Channel n Priority Register
#define DMA_DCHPRI9 (*(volatile uint8_t *)0x4000810A) // Channel n Priority Register
#define DMA_DCHPRI8 (*(volatile uint8_t *)0x4000810B) // Channel n Priority Register
#define DMA_DCHPRI15 (*(volatile uint8_t *)0x4000810C) // Channel n Priority Register
#define DMA_DCHPRI14 (*(volatile uint8_t *)0x4000810D) // Channel n Priority Register
#define DMA_DCHPRI13 (*(volatile uint8_t *)0x4000810E) // Channel n Priority Register
#define DMA_DCHPRI12 (*(volatile uint8_t *)0x4000810F) // Channel n Priority Register
#endif
#if DMA_NUM_CHANNELS >= 32
#define DMA_DCHPRI19 (*(volatile uint8_t *)0x40008110) // Channel n Priority Register
#define DMA_DCHPRI18 (*(volatile uint8_t *)0x40008111) // Channel n Priority Register
#define DMA_DCHPRI17 (*(volatile uint8_t *)0x40008112) // Channel n Priority Register
#define DMA_DCHPRI16 (*(volatile uint8_t *)0x40008113) // Channel n Priority Register
#define DMA_DCHPRI23 (*(volatile uint8_t *)0x40008114) // Channel n Priority Register
#define DMA_DCHPRI22 (*(volatile uint8_t *)0x40008115) // Channel n Priority Register
#define DMA_DCHPRI21 (*(volatile uint8_t *)0x40008116) // Channel n Priority Register
#define DMA_DCHPRI20 (*(volatile uint8_t *)0x40008117) // Channel n Priority Register
#define DMA_DCHPRI27 (*(volatile uint8_t *)0x40008118) // Channel n Priority Register
#define DMA_DCHPRI26 (*(volatile uint8_t *)0x40008119) // Channel n Priority Register
#define DMA_DCHPRI25 (*(volatile uint8_t *)0x4000811A) // Channel n Priority Register
#define DMA_DCHPRI24 (*(volatile uint8_t *)0x4000811B) // Channel n Priority Register
#define DMA_DCHPRI31 (*(volatile uint8_t *)0x4000811C) // Channel n Priority Register
#define DMA_DCHPRI30 (*(volatile uint8_t *)0x4000811D) // Channel n Priority Register
#define DMA_DCHPRI29 (*(volatile uint8_t *)0x4000811E) // Channel n Priority Register
#define DMA_DCHPRI28 (*(volatile uint8_t *)0x4000811F) // Channel n Priority Register
#define DMA_CR_GRP0PRI ((uint32_t)0x100)
#define DMA_CR_GRP1PRI ((uint32_t)0x400)
#endif
#define DMA_TCD_ATTR_SMOD(n) (((n) & 0x1F) << 11)
#define DMA_TCD_ATTR_SSIZE(n) (((n) & 0x7) << 8)
#define DMA_TCD_ATTR_DMOD(n) (((n) & 0x1F) << 3)
#define DMA_TCD_ATTR_DSIZE(n) (((n) & 0x7) << 0)
#define DMA_TCD_ATTR_SIZE_8BIT 0
#define DMA_TCD_ATTR_SIZE_16BIT 1
#define DMA_TCD_ATTR_SIZE_32BIT 2
#define DMA_TCD_ATTR_SIZE_16BYTE 4
#define DMA_TCD_ATTR_SIZE_32BYTE 5 // caution: this might not be supported in newer chips?
#define DMA_TCD_CSR_BWC(n) (((n) & 0x3) << 14)
#define DMA_TCD_CSR_BWC_MASK 0xC000
#define DMA_TCD_CSR_MAJORLINKCH(n) (((n) & 0xF) << 8)
#define DMA_TCD_CSR_MAJORLINKCH_MASK 0x0F00
#define DMA_TCD_CSR_DONE 0x0080
#define DMA_TCD_CSR_ACTIVE 0x0040
#define DMA_TCD_CSR_MAJORELINK 0x0020
#define DMA_TCD_CSR_ESG 0x0010
#define DMA_TCD_CSR_DREQ 0x0008
#define DMA_TCD_CSR_INTHALF 0x0004
#define DMA_TCD_CSR_INTMAJOR 0x0002
#define DMA_TCD_CSR_START 0x0001
#define DMA_TCD_CITER_MASK ((uint16_t)0x7FFF) // Loop count mask
#define DMA_TCD_CITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
#define DMA_TCD_BITER_MASK ((uint16_t)0x7FFF) // Loop count mask
#define DMA_TCD_BITER_ELINK ((uint16_t)1<<15) // Enable channel linking on minor-loop complete
#define DMA_TCD_BITER_ELINKYES_ELINK 0x8000
#define DMA_TCD_BITER_ELINKYES_LINKCH(n) (((n) & 0xF) << 9)
#define DMA_TCD_BITER_ELINKYES_LINKCH_MASK 0x1E00
#define DMA_TCD_BITER_ELINKYES_BITER(n) (((n) & 0x1FF) << 0)
#define DMA_TCD_BITER_ELINKYES_BITER_MASK 0x01FF
#define DMA_TCD_CITER_ELINKYES_ELINK 0x8000
#define DMA_TCD_CITER_ELINKYES_LINKCH(n) (((n) & 0xF) << 9)
#define DMA_TCD_CITER_ELINKYES_LINKCH_MASK 0x1E00
#define DMA_TCD_CITER_ELINKYES_CITER(n) (((n) & 0x1FF) << 0)
#define DMA_TCD_CITER_ELINKYES_CITER_MASK 0x01FF
#define DMA_TCD_NBYTES_SMLOE ((uint32_t)1<<31) // Source Minor Loop Offset Enable
#define DMA_TCD_NBYTES_DMLOE ((uint32_t)1<<30) // Destination Minor Loop Offset Enable
#define DMA_TCD_NBYTES_MLOFFNO_NBYTES(n) ((uint32_t)((n) & 0x3FFFFFFF)) // NBytes transfer count when minor loop disabled
#define DMA_TCD_NBYTES_MLOFFYES_NBYTES(n) ((uint32_t)((n) & 0x3FF)) // NBytes transfer count when minor loop enabled
#define DMA_TCD_NBYTES_MLOFFYES_MLOFF(n) ((uint32_t)((n) & 0xFFFFF)<<10) // Minor loop offset
#if DMA_NUM_CHANNELS >= 4
#define DMA_TCD0_SADDR (*(volatile const void * volatile *)0x40009000) // TCD Source Address
#define DMA_TCD0_SOFF (*(volatile int16_t *)0x40009004) // TCD Signed Source Address Offset
#define DMA_TCD0_ATTR (*(volatile uint16_t *)0x40009006) // TCD Transfer Attributes
#define DMA_TCD0_NBYTES_MLNO (*(volatile uint32_t *)0x40009008) // TCD Minor Byte Count (Minor Loop Disabled)
#define DMA_TCD0_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009008) // TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled)
#define DMA_TCD0_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009008) // TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled)
#define DMA_TCD0_SLAST (*(volatile int32_t *)0x4000900C) // TCD Last Source Address Adjustment
#define DMA_TCD0_DADDR (*(volatile void * volatile *)0x40009010) // TCD Destination Address
#define DMA_TCD0_DOFF (*(volatile int16_t *)0x40009014) // TCD Signed Destination Address Offset
#define DMA_TCD0_CITER_ELINKYES (*(volatile uint16_t *)0x40009016) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
#define DMA_TCD0_CITER_ELINKNO (*(volatile uint16_t *)0x40009016) // ??
#define DMA_TCD0_DLASTSGA (*(volatile int32_t *)0x40009018) // TCD Last Destination Address Adjustment/Scatter Gather Address
#define DMA_TCD0_CSR (*(volatile uint16_t *)0x4000901C) // TCD Control and Status
#define DMA_TCD0_BITER_ELINKYES (*(volatile uint16_t *)0x4000901E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
#define DMA_TCD0_BITER_ELINKNO (*(volatile uint16_t *)0x4000901E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
#define DMA_TCD1_SADDR (*(volatile const void * volatile *)0x40009020) // TCD Source Address
#define DMA_TCD1_SOFF (*(volatile int16_t *)0x40009024) // TCD Signed Source Address Offset
#define DMA_TCD1_ATTR (*(volatile uint16_t *)0x40009026) // TCD Transfer Attributes
#define DMA_TCD1_NBYTES_MLNO (*(volatile uint32_t *)0x40009028) // TCD Minor Byte Count, Minor Loop Disabled
#define DMA_TCD1_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009028) // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
#define DMA_TCD1_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009028) // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
#define DMA_TCD1_SLAST (*(volatile int32_t *)0x4000902C) // TCD Last Source Address Adjustment
#define DMA_TCD1_DADDR (*(volatile void * volatile *)0x40009030) // TCD Destination Address
#define DMA_TCD1_DOFF (*(volatile int16_t *)0x40009034) // TCD Signed Destination Address Offset
#define DMA_TCD1_CITER_ELINKYES (*(volatile uint16_t *)0x40009036) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
#define DMA_TCD1_CITER_ELINKNO (*(volatile uint16_t *)0x40009036) // ??
#define DMA_TCD1_DLASTSGA (*(volatile int32_t *)0x40009038) // TCD Last Destination Address Adjustment/Scatter Gather Address
#define DMA_TCD1_CSR (*(volatile uint16_t *)0x4000903C) // TCD Control and Status
#define DMA_TCD1_BITER_ELINKYES (*(volatile uint16_t *)0x4000903E) // TCD Beginning Minor Loop Link, Major Loop Count Channel Linking Enabled
#define DMA_TCD1_BITER_ELINKNO (*(volatile uint16_t *)0x4000903E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
#define DMA_TCD2_SADDR (*(volatile const void * volatile *)0x40009040) // TCD Source Address
#define DMA_TCD2_SOFF (*(volatile int16_t *)0x40009044) // TCD Signed Source Address Offset
#define DMA_TCD2_ATTR (*(volatile uint16_t *)0x40009046) // TCD Transfer Attributes
#define DMA_TCD2_NBYTES_MLNO (*(volatile uint32_t *)0x40009048) // TCD Minor Byte Count, Minor Loop Disabled
#define DMA_TCD2_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009048) // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
#define DMA_TCD2_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009048) // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
#define DMA_TCD2_SLAST (*(volatile int32_t *)0x4000904C) // TCD Last Source Address Adjustment
#define DMA_TCD2_DADDR (*(volatile void * volatile *)0x40009050) // TCD Destination Address
#define DMA_TCD2_DOFF (*(volatile int16_t *)0x40009054) // TCD Signed Destination Address Offset
#define DMA_TCD2_CITER_ELINKYES (*(volatile uint16_t *)0x40009056) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
#define DMA_TCD2_CITER_ELINKNO (*(volatile uint16_t *)0x40009056) // ??
#define DMA_TCD2_DLASTSGA (*(volatile int32_t *)0x40009058) // TCD Last Destination Address Adjustment/Scatter Gather Address
#define DMA_TCD2_CSR (*(volatile uint16_t *)0x4000905C) // TCD Control and Status
#define DMA_TCD2_BITER_ELINKYES (*(volatile uint16_t *)0x4000905E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Enabled
#define DMA_TCD2_BITER_ELINKNO (*(volatile uint16_t *)0x4000905E) // TCD Beginning Minor Loop Link, Major Loop Count, Channel Linking Disabled
#define DMA_TCD3_SADDR (*(volatile const void * volatile *)0x40009060) // TCD Source Address
#define DMA_TCD3_SOFF (*(volatile int16_t *)0x40009064) // TCD Signed Source Address Offset
#define DMA_TCD3_ATTR (*(volatile uint16_t *)0x40009066) // TCD Transfer Attributes
#define DMA_TCD3_NBYTES_MLNO (*(volatile uint32_t *)0x40009068) // TCD Minor Byte Count, Minor Loop Disabled
#define DMA_TCD3_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009068) // TCD Signed Minor Loop Offset, Minor Loop Enabled and Offset Disabled
#define DMA_TCD3_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009068) // TCD Signed Minor Loop Offset, Minor Loop and Offset Enabled
#define DMA_TCD3_SLAST (*(volatile int32_t *)0x4000906C) // TCD Last Source Address Adjustment
#define DMA_TCD3_DADDR (*(volatile void * volatile *)0x40009070) // TCD Destination Address
#define DMA_TCD3_DOFF (*(volatile int16_t *)0x40009074) // TCD Signed Destination Address Offset
#define DMA_TCD3_CITER_ELINKYES (*(volatile uint16_t *)0x40009076) // TCD Current Minor Loop Link, Major Loop Count, Channel Linking Enabled
#define DMA_TCD3_CITER_ELINKNO (*(volatile uint16_t *)0x40009076) // ??
#define DMA_TCD3_DLASTSGA (*(volatile int32_t *)0x40009078) // TCD Last Destination Address Adjustment/Scatter Gather Address
#define DMA_TCD3_CSR (*(volatile uint16_t *)0x4000907C) // TCD Control and Status
#define DMA_TCD3_BITER_ELINKYES (*(volatile uint16_t *)0x4000907E) // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Enabled
#define DMA_TCD3_BITER_ELINKNO (*(volatile uint16_t *)0x4000907E) // TCD Beginning Minor Loop Link, Major Loop Count ,Channel Linking Disabled
#define DMA_TCD4_SADDR (*(volatile const void * volatile *)0x40009080) // TCD Source Addr
#define DMA_TCD4_SOFF (*(volatile int16_t *)0x40009084) // TCD Signed Source Address Offset
#define DMA_TCD4_ATTR (*(volatile uint16_t *)0x40009086) // TCD Transfer Attributes
#define DMA_TCD4_NBYTES_MLNO (*(volatile uint32_t *)0x40009088) // TCD Minor Byte Count
#define DMA_TCD4_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009088) // TCD Signed Minor Loop Offset
#define DMA_TCD4_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009088) // TCD Signed Minor Loop Offset
#define DMA_TCD4_SLAST (*(volatile int32_t *)0x4000908C) // TCD Last Source Addr Adj.
#define DMA_TCD4_DADDR (*(volatile void * volatile *)0x40009090) // TCD Destination Address
#define DMA_TCD4_DOFF (*(volatile int16_t *)0x40009094) // TCD Signed Dest Address Offset
#define DMA_TCD4_CITER_ELINKYES (*(volatile uint16_t *)0x40009096) // TCD Current Minor Loop Link
#define DMA_TCD4_CITER_ELINKNO (*(volatile uint16_t *)0x40009096) // ??
#define DMA_TCD4_DLASTSGA (*(volatile int32_t *)0x40009098) // TCD Last Destination Addr Adj
#define DMA_TCD4_CSR (*(volatile uint16_t *)0x4000909C) // TCD Control and Status
#define DMA_TCD4_BITER_ELINKYES (*(volatile uint16_t *)0x4000909E) // TCD Beginning Minor Loop Link
#define DMA_TCD4_BITER_ELINKNO (*(volatile uint16_t *)0x4000909E) // TCD Beginning Minor Loop Link
#endif
#if DMA_NUM_CHANNELS >= 16
#define DMA_TCD5_SADDR (*(volatile const void * volatile *)0x400090A0) // TCD Source Addr
#define DMA_TCD5_SOFF (*(volatile int16_t *)0x400090A4) // TCD Signed Source Address Offset
#define DMA_TCD5_ATTR (*(volatile uint16_t *)0x400090A6) // TCD Transfer Attributes
#define DMA_TCD5_NBYTES_MLNO (*(volatile uint32_t *)0x400090A8) // TCD Minor Byte Count
#define DMA_TCD5_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400090A8) // TCD Signed Minor Loop Offset
#define DMA_TCD5_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400090A8) // TCD Signed Minor Loop Offset
#define DMA_TCD5_SLAST (*(volatile int32_t *)0x400090AC) // TCD Last Source Addr Adj.
#define DMA_TCD5_DADDR (*(volatile void * volatile *)0x400090B0) // TCD Destination Address
#define DMA_TCD5_DOFF (*(volatile int16_t *)0x400090B4) // TCD Signed Dest Address Offset
#define DMA_TCD5_CITER_ELINKYES (*(volatile uint16_t *)0x400090B6) // TCD Current Minor Loop Link
#define DMA_TCD5_CITER_ELINKNO (*(volatile uint16_t *)0x400090B6) // ??
#define DMA_TCD5_DLASTSGA (*(volatile int32_t *)0x400090B8) // TCD Last Destination Addr Adj
#define DMA_TCD5_CSR (*(volatile uint16_t *)0x400090BC) // TCD Control and Status
#define DMA_TCD5_BITER_ELINKYES (*(volatile uint16_t *)0x400090BE) // TCD Beginning Minor Loop Link
#define DMA_TCD5_BITER_ELINKNO (*(volatile uint16_t *)0x400090BE) // TCD Beginning Minor Loop Link
#define DMA_TCD6_SADDR (*(volatile const void * volatile *)0x400090C0) // TCD Source Addr
#define DMA_TCD6_SOFF (*(volatile int16_t *)0x400090C4) // TCD Signed Source Address Offset
#define DMA_TCD6_ATTR (*(volatile uint16_t *)0x400090C6) // TCD Transfer Attributes
#define DMA_TCD6_NBYTES_MLNO (*(volatile uint32_t *)0x400090C8) // TCD Minor Byte Count
#define DMA_TCD6_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400090C8) // TCD Signed Minor Loop Offset
#define DMA_TCD6_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400090C8) // TCD Signed Minor Loop Offset
#define DMA_TCD6_SLAST (*(volatile int32_t *)0x400090CC) // TCD Last Source Addr Adj.
#define DMA_TCD6_DADDR (*(volatile void * volatile *)0x400090D0) // TCD Destination Address
#define DMA_TCD6_DOFF (*(volatile int16_t *)0x400090D4) // TCD Signed Dest Address Offset
#define DMA_TCD6_CITER_ELINKYES (*(volatile uint16_t *)0x400090D6) // TCD Current Minor Loop Link
#define DMA_TCD6_CITER_ELINKNO (*(volatile uint16_t *)0x400090D6) // ??
#define DMA_TCD6_DLASTSGA (*(volatile int32_t *)0x400090D8) // TCD Last Destination Addr Adj
#define DMA_TCD6_CSR (*(volatile uint16_t *)0x400090DC) // TCD Control and Status
#define DMA_TCD6_BITER_ELINKYES (*(volatile uint16_t *)0x400090DE) // TCD Beginning Minor Loop Link
#define DMA_TCD6_BITER_ELINKNO (*(volatile uint16_t *)0x400090DE) // TCD Beginning Minor Loop Link
#define DMA_TCD7_SADDR (*(volatile const void * volatile *)0x400090E0) // TCD Source Addr
#define DMA_TCD7_SOFF (*(volatile int16_t *)0x400090E4) // TCD Signed Source Address Offset
#define DMA_TCD7_ATTR (*(volatile uint16_t *)0x400090E6) // TCD Transfer Attributes
#define DMA_TCD7_NBYTES_MLNO (*(volatile uint32_t *)0x400090E8) // TCD Minor Byte Count
#define DMA_TCD7_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400090E8) // TCD Signed Minor Loop Offset
#define DMA_TCD7_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400090E8) // TCD Signed Minor Loop Offset
#define DMA_TCD7_SLAST (*(volatile int32_t *)0x400090EC) // TCD Last Source Addr Adj.
#define DMA_TCD7_DADDR (*(volatile void * volatile *)0x400090F0) // TCD Destination Address
#define DMA_TCD7_DOFF (*(volatile int16_t *)0x400090F4) // TCD Signed Dest Address Offset
#define DMA_TCD7_CITER_ELINKYES (*(volatile uint16_t *)0x400090F6) // TCD Current Minor Loop Link
#define DMA_TCD7_CITER_ELINKNO (*(volatile uint16_t *)0x400090F6) // ??
#define DMA_TCD7_DLASTSGA (*(volatile int32_t *)0x400090F8) // TCD Last Destination Addr Adj
#define DMA_TCD7_CSR (*(volatile uint16_t *)0x400090FC) // TCD Control and Status
#define DMA_TCD7_BITER_ELINKYES (*(volatile uint16_t *)0x400090FE) // TCD Beginning Minor Loop Link
#define DMA_TCD7_BITER_ELINKNO (*(volatile uint16_t *)0x400090FE) // TCD Beginning Minor Loop Link
#define DMA_TCD8_SADDR (*(volatile const void * volatile *)0x40009100) // TCD Source Addr
#define DMA_TCD8_SOFF (*(volatile int16_t *)0x40009104) // TCD Signed Source Address Offset
#define DMA_TCD8_ATTR (*(volatile uint16_t *)0x40009106) // TCD Transfer Attributes
#define DMA_TCD8_NBYTES_MLNO (*(volatile uint32_t *)0x40009108) // TCD Minor Byte Count
#define DMA_TCD8_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009108) // TCD Signed Minor Loop Offset
#define DMA_TCD8_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009108) // TCD Signed Minor Loop Offset
#define DMA_TCD8_SLAST (*(volatile int32_t *)0x4000910C) // TCD Last Source Addr Adj.
#define DMA_TCD8_DADDR (*(volatile void * volatile *)0x40009110) // TCD Destination Address
#define DMA_TCD8_DOFF (*(volatile int16_t *)0x40009114) // TCD Signed Dest Address Offset
#define DMA_TCD8_CITER_ELINKYES (*(volatile uint16_t *)0x40009116) // TCD Current Minor Loop Link
#define DMA_TCD8_CITER_ELINKNO (*(volatile uint16_t *)0x40009116) // ??
#define DMA_TCD8_DLASTSGA (*(volatile int32_t *)0x40009118) // TCD Last Destination Addr Adj
#define DMA_TCD8_CSR (*(volatile uint16_t *)0x4000911C) // TCD Control and Status
#define DMA_TCD8_BITER_ELINKYES (*(volatile uint16_t *)0x4000911E) // TCD Beginning Minor Loop Link
#define DMA_TCD8_BITER_ELINKNO (*(volatile uint16_t *)0x4000911E) // TCD Beginning Minor Loop Link
#define DMA_TCD9_SADDR (*(volatile const void * volatile *)0x40009120) // TCD Source Addr
#define DMA_TCD9_SOFF (*(volatile int16_t *)0x40009124) // TCD Signed Source Address Offset
#define DMA_TCD9_ATTR (*(volatile uint16_t *)0x40009126) // TCD Transfer Attributes
#define DMA_TCD9_NBYTES_MLNO (*(volatile uint32_t *)0x40009128) // TCD Minor Byte Count
#define DMA_TCD9_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009128) // TCD Signed Minor Loop Offset
#define DMA_TCD9_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009128) // TCD Signed Minor Loop Offset
#define DMA_TCD9_SLAST (*(volatile int32_t *)0x4000912C) // TCD Last Source Addr Adj.
#define DMA_TCD9_DADDR (*(volatile void * volatile *)0x40009130) // TCD Destination Address
#define DMA_TCD9_DOFF (*(volatile int16_t *)0x40009134) // TCD Signed Dest Address Offset
#define DMA_TCD9_CITER_ELINKYES (*(volatile uint16_t *)0x40009136) // TCD Current Minor Loop Link
#define DMA_TCD9_CITER_ELINKNO (*(volatile uint16_t *)0x40009136) // ??
#define DMA_TCD9_DLASTSGA (*(volatile int32_t *)0x40009138) // TCD Last Destination Addr Adj
#define DMA_TCD9_CSR (*(volatile uint16_t *)0x4000913C) // TCD Control and Status
#define DMA_TCD9_BITER_ELINKYES (*(volatile uint16_t *)0x4000913E) // TCD Beginning Minor Loop Link
#define DMA_TCD9_BITER_ELINKNO (*(volatile uint16_t *)0x4000913E) // TCD Beginning Minor Loop Link
#define DMA_TCD10_SADDR (*(volatile const void * volatile *)0x40009140) // TCD Source Addr
#define DMA_TCD10_SOFF (*(volatile int16_t *)0x40009144) // TCD Signed Source Address Offset
#define DMA_TCD10_ATTR (*(volatile uint16_t *)0x40009146) // TCD Transfer Attributes
#define DMA_TCD10_NBYTES_MLNO (*(volatile uint32_t *)0x40009148) // TCD Minor Byte Count
#define DMA_TCD10_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009148) // TCD Signed Minor Loop Offset
#define DMA_TCD10_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009148) // TCD Signed Minor Loop Offset
#define DMA_TCD10_SLAST (*(volatile int32_t *)0x4000914C) // TCD Last Source Addr Adj.
#define DMA_TCD10_DADDR (*(volatile void * volatile *)0x40009150) // TCD Destination Address
#define DMA_TCD10_DOFF (*(volatile int16_t *)0x40009154) // TCD Signed Dest Address Offset
#define DMA_TCD10_CITER_ELINKYES (*(volatile uint16_t *)0x40009156) // TCD Current Minor Loop Link
#define DMA_TCD10_CITER_ELINKNO (*(volatile uint16_t *)0x40009156) // ??
#define DMA_TCD10_DLASTSGA (*(volatile int32_t *)0x40009158) // TCD Last Destination Addr Adj
#define DMA_TCD10_CSR (*(volatile uint16_t *)0x4000915C) // TCD Control and Status
#define DMA_TCD10_BITER_ELINKYES (*(volatile uint16_t *)0x4000915E) // TCD Beginning Minor Loop Link
#define DMA_TCD10_BITER_ELINKNO (*(volatile uint16_t *)0x4000915E) // TCD Beginning Minor Loop Link
#define DMA_TCD11_SADDR (*(volatile const void * volatile *)0x40009160) // TCD Source Addr
#define DMA_TCD11_SOFF (*(volatile int16_t *)0x40009164) // TCD Signed Source Address Offset
#define DMA_TCD11_ATTR (*(volatile uint16_t *)0x40009166) // TCD Transfer Attributes
#define DMA_TCD11_NBYTES_MLNO (*(volatile uint32_t *)0x40009168) // TCD Minor Byte Count
#define DMA_TCD11_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009168) // TCD Signed Minor Loop Offset
#define DMA_TCD11_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009168) // TCD Signed Minor Loop Offset
#define DMA_TCD11_SLAST (*(volatile int32_t *)0x4000916C) // TCD Last Source Addr Adj.
#define DMA_TCD11_DADDR (*(volatile void * volatile *)0x40009170) // TCD Destination Address
#define DMA_TCD11_DOFF (*(volatile int16_t *)0x40009174) // TCD Signed Dest Address Offset
#define DMA_TCD11_CITER_ELINKYES (*(volatile uint16_t *)0x40009176) // TCD Current Minor Loop Link
#define DMA_TCD11_CITER_ELINKNO (*(volatile uint16_t *)0x40009176) // ??
#define DMA_TCD11_DLASTSGA (*(volatile int32_t *)0x40009178) // TCD Last Destination Addr Adj
#define DMA_TCD11_CSR (*(volatile uint16_t *)0x4000917C) // TCD Control and Status
#define DMA_TCD11_BITER_ELINKYES (*(volatile uint16_t *)0x4000917E) // TCD Beginning Minor Loop Link
#define DMA_TCD11_BITER_ELINKNO (*(volatile uint16_t *)0x4000917E) // TCD Beginning Minor Loop Link
#define DMA_TCD12_SADDR (*(volatile const void * volatile *)0x40009180) // TCD Source Addr
#define DMA_TCD12_SOFF (*(volatile int16_t *)0x40009184) // TCD Signed Source Address Offset
#define DMA_TCD12_ATTR (*(volatile uint16_t *)0x40009186) // TCD Transfer Attributes
#define DMA_TCD12_NBYTES_MLNO (*(volatile uint32_t *)0x40009188) // TCD Minor Byte Count
#define DMA_TCD12_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009188) // TCD Signed Minor Loop Offset
#define DMA_TCD12_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009188) // TCD Signed Minor Loop Offset
#define DMA_TCD12_SLAST (*(volatile int32_t *)0x4000918C) // TCD Last Source Addr Adj.
#define DMA_TCD12_DADDR (*(volatile void * volatile *)0x40009190) // TCD Destination Address
#define DMA_TCD12_DOFF (*(volatile int16_t *)0x40009194) // TCD Signed Dest Address Offset
#define DMA_TCD12_CITER_ELINKYES (*(volatile uint16_t *)0x40009196) // TCD Current Minor Loop Link
#define DMA_TCD12_CITER_ELINKNO (*(volatile uint16_t *)0x40009196) // ??
#define DMA_TCD12_DLASTSGA (*(volatile int32_t *)0x40009198) // TCD Last Destination Addr Adj
#define DMA_TCD12_CSR (*(volatile uint16_t *)0x4000919C) // TCD Control and Status
#define DMA_TCD12_BITER_ELINKYES (*(volatile uint16_t *)0x4000919E) // TCD Beginning Minor Loop Link
#define DMA_TCD12_BITER_ELINKNO (*(volatile uint16_t *)0x4000919E) // TCD Beginning Minor Loop Link
#define DMA_TCD13_SADDR (*(volatile const void * volatile *)0x400091A0) // TCD Source Addr
#define DMA_TCD13_SOFF (*(volatile int16_t *)0x400091A4) // TCD Signed Source Address Offset
#define DMA_TCD13_ATTR (*(volatile uint16_t *)0x400091A6) // TCD Transfer Attributes
#define DMA_TCD13_NBYTES_MLNO (*(volatile uint32_t *)0x400091A8) // TCD Minor Byte Count
#define DMA_TCD13_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400091A8) // TCD Signed Minor Loop Offset
#define DMA_TCD13_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400091A8) // TCD Signed Minor Loop Offset
#define DMA_TCD13_SLAST (*(volatile int32_t *)0x400091AC) // TCD Last Source Addr Adj.
#define DMA_TCD13_DADDR (*(volatile void * volatile *)0x400091B0) // TCD Destination Address
#define DMA_TCD13_DOFF (*(volatile int16_t *)0x400091B4) // TCD Signed Dest Address Offset
#define DMA_TCD13_CITER_ELINKYES (*(volatile uint16_t *)0x400091B6) // TCD Current Minor Loop Link
#define DMA_TCD13_CITER_ELINKNO (*(volatile uint16_t *)0x400091B6) // ??
#define DMA_TCD13_DLASTSGA (*(volatile int32_t *)0x400091B8) // TCD Last Destination Addr Adj
#define DMA_TCD13_CSR (*(volatile uint16_t *)0x400091BC) // TCD Control and Status
#define DMA_TCD13_BITER_ELINKYES (*(volatile uint16_t *)0x400091BE) // TCD Beginning Minor Loop Link
#define DMA_TCD13_BITER_ELINKNO (*(volatile uint16_t *)0x400091BE) // TCD Beginning Minor Loop Link
#define DMA_TCD14_SADDR (*(volatile const void * volatile *)0x400091C0) // TCD Source Addr
#define DMA_TCD14_SOFF (*(volatile int16_t *)0x400091C4) // TCD Signed Source Address Offset
#define DMA_TCD14_ATTR (*(volatile uint16_t *)0x400091C6) // TCD Transfer Attributes
#define DMA_TCD14_NBYTES_MLNO (*(volatile uint32_t *)0x400091C8) // TCD Minor Byte Count
#define DMA_TCD14_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400091C8) // TCD Signed Minor Loop Offset
#define DMA_TCD14_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400091C8) // TCD Signed Minor Loop Offset
#define DMA_TCD14_SLAST (*(volatile int32_t *)0x400091CC) // TCD Last Source Addr Adj.
#define DMA_TCD14_DADDR (*(volatile void * volatile *)0x400091D0) // TCD Destination Address
#define DMA_TCD14_DOFF (*(volatile int16_t *)0x400091D4) // TCD Signed Dest Address Offset
#define DMA_TCD14_CITER_ELINKYES (*(volatile uint16_t *)0x400091D6) // TCD Current Minor Loop Link
#define DMA_TCD14_CITER_ELINKNO (*(volatile uint16_t *)0x400091D6) // ??
#define DMA_TCD14_DLASTSGA (*(volatile int32_t *)0x400091D8) // TCD Last Destination Addr Adj
#define DMA_TCD14_CSR (*(volatile uint16_t *)0x400091DC) // TCD Control and Status
#define DMA_TCD14_BITER_ELINKYES (*(volatile uint16_t *)0x400091DE) // TCD Beginning Minor Loop Link
#define DMA_TCD14_BITER_ELINKNO (*(volatile uint16_t *)0x400091DE) // TCD Beginning Minor Loop Link
#define DMA_TCD15_SADDR (*(volatile const void * volatile *)0x400091E0) // TCD Source Addr
#define DMA_TCD15_SOFF (*(volatile int16_t *)0x400091E4) // TCD Signed Source Address Offset
#define DMA_TCD15_ATTR (*(volatile uint16_t *)0x400091E6) // TCD Transfer Attributes
#define DMA_TCD15_NBYTES_MLNO (*(volatile uint32_t *)0x400091E8) // TCD Minor Byte Count
#define DMA_TCD15_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400091E8) // TCD Signed Minor Loop Offset
#define DMA_TCD15_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400091E8) // TCD Signed Minor Loop Offset
#define DMA_TCD15_SLAST (*(volatile int32_t *)0x400091EC) // TCD Last Source Addr Adj.
#define DMA_TCD15_DADDR (*(volatile void * volatile *)0x400091F0) // TCD Destination Address
#define DMA_TCD15_DOFF (*(volatile int16_t *)0x400091F4) // TCD Signed Dest Address Offset
#define DMA_TCD15_CITER_ELINKYES (*(volatile uint16_t *)0x400091F6) // TCD Current Minor Loop Link
#define DMA_TCD15_CITER_ELINKNO (*(volatile uint16_t *)0x400091F6) // ??
#define DMA_TCD15_DLASTSGA (*(volatile int32_t *)0x400091F8) // TCD Last Destination Addr Adj
#define DMA_TCD15_CSR (*(volatile uint16_t *)0x400091FC) // TCD Control and Status
#define DMA_TCD15_BITER_ELINKYES (*(volatile uint16_t *)0x400091FE) // TCD Beginning Minor Loop Link
#define DMA_TCD15_BITER_ELINKNO (*(volatile uint16_t *)0x400091FE) // TCD Beginning Minor Loop Link
#endif
#if DMA_NUM_CHANNELS >= 32
#define DMA_TCD16_SADDR (*(volatile const void * volatile *)0x40009200) // TCD Source Addr
#define DMA_TCD16_SOFF (*(volatile int16_t *)0x40009204) // TCD Signed Source Address Offset
#define DMA_TCD16_ATTR (*(volatile uint16_t *)0x40009206) // TCD Transfer Attributes
#define DMA_TCD16_NBYTES_MLNO (*(volatile uint32_t *)0x40009208) // TCD Minor Byte Count
#define DMA_TCD16_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009208) // TCD Signed Minor Loop Offset
#define DMA_TCD16_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009208) // TCD Signed Minor Loop Offset
#define DMA_TCD16_SLAST (*(volatile int32_t *)0x4000920C) // TCD Last Source Addr Adj.
#define DMA_TCD16_DADDR (*(volatile void * volatile *)0x40009210) // TCD Destination Address
#define DMA_TCD16_DOFF (*(volatile int16_t *)0x40009214) // TCD Signed Dest Address Offset
#define DMA_TCD16_CITER_ELINKYES (*(volatile uint16_t *)0x40009216) // TCD Current Minor Loop Link
#define DMA_TCD16_CITER_ELINKNO (*(volatile uint16_t *)0x40009216) // ??
#define DMA_TCD16_DLASTSGA (*(volatile int32_t *)0x40009218) // TCD Last Destination Addr Adj
#define DMA_TCD16_CSR (*(volatile uint16_t *)0x4000921C) // TCD Control and Status
#define DMA_TCD16_BITER_ELINKYES (*(volatile uint16_t *)0x4000921E) // TCD Beginning Minor Loop Link
#define DMA_TCD16_BITER_ELINKNO (*(volatile uint16_t *)0x4000921E) // TCD Beginning Minor Loop Link
#define DMA_TCD17_SADDR (*(volatile const void * volatile *)0x40009220) // TCD Source Addr
#define DMA_TCD17_SOFF (*(volatile int16_t *)0x40009224) // TCD Signed Source Address Offset
#define DMA_TCD17_ATTR (*(volatile uint16_t *)0x40009226) // TCD Transfer Attributes
#define DMA_TCD17_NBYTES_MLNO (*(volatile uint32_t *)0x40009228) // TCD Minor Byte Count
#define DMA_TCD17_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009228) // TCD Signed Minor Loop Offset
#define DMA_TCD17_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009228) // TCD Signed Minor Loop Offset
#define DMA_TCD17_SLAST (*(volatile int32_t *)0x4000922C) // TCD Last Source Addr Adj.
#define DMA_TCD17_DADDR (*(volatile void * volatile *)0x40009230) // TCD Destination Address
#define DMA_TCD17_DOFF (*(volatile int16_t *)0x40009234) // TCD Signed Dest Address Offset
#define DMA_TCD17_CITER_ELINKYES (*(volatile uint16_t *)0x40009236) // TCD Current Minor Loop Link
#define DMA_TCD17_CITER_ELINKNO (*(volatile uint16_t *)0x40009236) // ??
#define DMA_TCD17_DLASTSGA (*(volatile int32_t *)0x40009238) // TCD Last Destination Addr Adj
#define DMA_TCD17_CSR (*(volatile uint16_t *)0x4000923C) // TCD Control and Status
#define DMA_TCD17_BITER_ELINKYES (*(volatile uint16_t *)0x4000923E) // TCD Beginning Minor Loop Link
#define DMA_TCD17_BITER_ELINKNO (*(volatile uint16_t *)0x4000923E) // TCD Beginning Minor Loop Link
#define DMA_TCD18_SADDR (*(volatile const void * volatile *)0x40009240) // TCD Source Addr
#define DMA_TCD18_SOFF (*(volatile int16_t *)0x40009244) // TCD Signed Source Address Offset
#define DMA_TCD18_ATTR (*(volatile uint16_t *)0x40009246) // TCD Transfer Attributes
#define DMA_TCD18_NBYTES_MLNO (*(volatile uint32_t *)0x40009248) // TCD Minor Byte Count
#define DMA_TCD18_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009248) // TCD Signed Minor Loop Offset
#define DMA_TCD18_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009248) // TCD Signed Minor Loop Offset
#define DMA_TCD18_SLAST (*(volatile int32_t *)0x4000924C) // TCD Last Source Addr Adj.
#define DMA_TCD18_DADDR (*(volatile void * volatile *)0x40009250) // TCD Destination Address
#define DMA_TCD18_DOFF (*(volatile int16_t *)0x40009254) // TCD Signed Dest Address Offset
#define DMA_TCD18_CITER_ELINKYES (*(volatile uint16_t *)0x40009256) // TCD Current Minor Loop Link
#define DMA_TCD18_CITER_ELINKNO (*(volatile uint16_t *)0x40009256) // ??
#define DMA_TCD18_DLASTSGA (*(volatile int32_t *)0x40009258) // TCD Last Destination Addr Adj
#define DMA_TCD18_CSR (*(volatile uint16_t *)0x4000925C) // TCD Control and Status
#define DMA_TCD18_BITER_ELINKYES (*(volatile uint16_t *)0x4000925E) // TCD Beginning Minor Loop Link
#define DMA_TCD18_BITER_ELINKNO (*(volatile uint16_t *)0x4000925E) // TCD Beginning Minor Loop Link
#define DMA_TCD19_SADDR (*(volatile const void * volatile *)0x40009260) // TCD Source Addr
#define DMA_TCD19_SOFF (*(volatile int16_t *)0x40009264) // TCD Signed Source Address Offset
#define DMA_TCD19_ATTR (*(volatile uint16_t *)0x40009266) // TCD Transfer Attributes
#define DMA_TCD19_NBYTES_MLNO (*(volatile uint32_t *)0x40009268) // TCD Minor Byte Count
#define DMA_TCD19_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009268) // TCD Signed Minor Loop Offset
#define DMA_TCD19_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009268) // TCD Signed Minor Loop Offset
#define DMA_TCD19_SLAST (*(volatile int32_t *)0x4000926C) // TCD Last Source Addr Adj.
#define DMA_TCD19_DADDR (*(volatile void * volatile *)0x40009270) // TCD Destination Address
#define DMA_TCD19_DOFF (*(volatile int16_t *)0x40009274) // TCD Signed Dest Address Offset
#define DMA_TCD19_CITER_ELINKYES (*(volatile uint16_t *)0x40009276) // TCD Current Minor Loop Link
#define DMA_TCD19_CITER_ELINKNO (*(volatile uint16_t *)0x40009276) // ??
#define DMA_TCD19_DLASTSGA (*(volatile int32_t *)0x40009278) // TCD Last Destination Addr Adj
#define DMA_TCD19_CSR (*(volatile uint16_t *)0x4000927C) // TCD Control and Status
#define DMA_TCD19_BITER_ELINKYES (*(volatile uint16_t *)0x4000927E) // TCD Beginning Minor Loop Link
#define DMA_TCD19_BITER_ELINKNO (*(volatile uint16_t *)0x4000927E) // TCD Beginning Minor Loop Link
#define DMA_TCD20_SADDR (*(volatile const void * volatile *)0x40009280) // TCD Source Addr
#define DMA_TCD20_SOFF (*(volatile int16_t *)0x40009284) // TCD Signed Source Address Offset
#define DMA_TCD20_ATTR (*(volatile uint16_t *)0x40009286) // TCD Transfer Attributes
#define DMA_TCD20_NBYTES_MLNO (*(volatile uint32_t *)0x40009288) // TCD Minor Byte Count
#define DMA_TCD20_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009288) // TCD Signed Minor Loop Offset
#define DMA_TCD20_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009288) // TCD Signed Minor Loop Offset
#define DMA_TCD20_SLAST (*(volatile int32_t *)0x4000928C) // TCD Last Source Addr Adj.
#define DMA_TCD20_DADDR (*(volatile void * volatile *)0x40009290) // TCD Destination Address
#define DMA_TCD20_DOFF (*(volatile int16_t *)0x40009294) // TCD Signed Dest Address Offset
#define DMA_TCD20_CITER_ELINKYES (*(volatile uint16_t *)0x40009296) // TCD Current Minor Loop Link
#define DMA_TCD20_CITER_ELINKNO (*(volatile uint16_t *)0x40009296) // ??
#define DMA_TCD20_DLASTSGA (*(volatile int32_t *)0x40009298) // TCD Last Destination Addr Adj
#define DMA_TCD20_CSR (*(volatile uint16_t *)0x4000929C) // TCD Control and Status
#define DMA_TCD20_BITER_ELINKYES (*(volatile uint16_t *)0x4000929E) // TCD Beginning Minor Loop Link
#define DMA_TCD20_BITER_ELINKNO (*(volatile uint16_t *)0x4000929E) // TCD Beginning Minor Loop Link
#define DMA_TCD21_SADDR (*(volatile const void * volatile *)0x400092A0) // TCD Source Addr
#define DMA_TCD21_SOFF (*(volatile int16_t *)0x400092A4) // TCD Signed Source Address Offset
#define DMA_TCD21_ATTR (*(volatile uint16_t *)0x400092A6) // TCD Transfer Attributes
#define DMA_TCD21_NBYTES_MLNO (*(volatile uint32_t *)0x400092A8) // TCD Minor Byte Count
#define DMA_TCD21_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400092A8) // TCD Signed Minor Loop Offset
#define DMA_TCD21_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400092A8) // TCD Signed Minor Loop Offset
#define DMA_TCD21_SLAST (*(volatile int32_t *)0x400092AC) // TCD Last Source Addr Adj.
#define DMA_TCD21_DADDR (*(volatile void * volatile *)0x400092B0) // TCD Destination Address
#define DMA_TCD21_DOFF (*(volatile int16_t *)0x400092B4) // TCD Signed Dest Address Offset
#define DMA_TCD21_CITER_ELINKYES (*(volatile uint16_t *)0x400092B6) // TCD Current Minor Loop Link
#define DMA_TCD21_CITER_ELINKNO (*(volatile uint16_t *)0x400092B6) // ??
#define DMA_TCD21_DLASTSGA (*(volatile int32_t *)0x400092B8) // TCD Last Destination Addr Adj
#define DMA_TCD21_CSR (*(volatile uint16_t *)0x400092BC) // TCD Control and Status
#define DMA_TCD21_BITER_ELINKYES (*(volatile uint16_t *)0x400092BE) // TCD Beginning Minor Loop Link
#define DMA_TCD21_BITER_ELINKNO (*(volatile uint16_t *)0x400092BE) // TCD Beginning Minor Loop Link
#define DMA_TCD22_SADDR (*(volatile const void * volatile *)0x400092C0) // TCD Source Addr
#define DMA_TCD22_SOFF (*(volatile int16_t *)0x400092C4) // TCD Signed Source Address Offset
#define DMA_TCD22_ATTR (*(volatile uint16_t *)0x400092C6) // TCD Transfer Attributes
#define DMA_TCD22_NBYTES_MLNO (*(volatile uint32_t *)0x400092C8) // TCD Minor Byte Count
#define DMA_TCD22_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400092C8) // TCD Signed Minor Loop Offset
#define DMA_TCD22_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400092C8) // TCD Signed Minor Loop Offset
#define DMA_TCD22_SLAST (*(volatile int32_t *)0x400092CC) // TCD Last Source Addr Adj.
#define DMA_TCD22_DADDR (*(volatile void * volatile *)0x400092D0) // TCD Destination Address
#define DMA_TCD22_DOFF (*(volatile int16_t *)0x400092D4) // TCD Signed Dest Address Offset
#define DMA_TCD22_CITER_ELINKYES (*(volatile uint16_t *)0x400092D6) // TCD Current Minor Loop Link
#define DMA_TCD22_CITER_ELINKNO (*(volatile uint16_t *)0x400092D6) // ??
#define DMA_TCD22_DLASTSGA (*(volatile int32_t *)0x400092D8) // TCD Last Destination Addr Adj
#define DMA_TCD22_CSR (*(volatile uint16_t *)0x400092DC) // TCD Control and Status
#define DMA_TCD22_BITER_ELINKYES (*(volatile uint16_t *)0x400092DE) // TCD Beginning Minor Loop Link
#define DMA_TCD22_BITER_ELINKNO (*(volatile uint16_t *)0x400092DE) // TCD Beginning Minor Loop Link
#define DMA_TCD23_SADDR (*(volatile const void * volatile *)0x400092E0) // TCD Source Addr
#define DMA_TCD23_SOFF (*(volatile int16_t *)0x400092E4) // TCD Signed Source Address Offset
#define DMA_TCD23_ATTR (*(volatile uint16_t *)0x400092E6) // TCD Transfer Attributes
#define DMA_TCD23_NBYTES_MLNO (*(volatile uint32_t *)0x400092E8) // TCD Minor Byte Count
#define DMA_TCD23_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400092E8) // TCD Signed Minor Loop Offset
#define DMA_TCD23_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400092E8) // TCD Signed Minor Loop Offset
#define DMA_TCD23_SLAST (*(volatile int32_t *)0x400092EC) // TCD Last Source Addr Adj.
#define DMA_TCD23_DADDR (*(volatile void * volatile *)0x400092F0) // TCD Destination Address
#define DMA_TCD23_DOFF (*(volatile int16_t *)0x400092F4) // TCD Signed Dest Address Offset
#define DMA_TCD23_CITER_ELINKYES (*(volatile uint16_t *)0x400092F6) // TCD Current Minor Loop Link
#define DMA_TCD23_CITER_ELINKNO (*(volatile uint16_t *)0x400092F6) // ??
#define DMA_TCD23_DLASTSGA (*(volatile int32_t *)0x400092F8) // TCD Last Destination Addr Adj
#define DMA_TCD23_CSR (*(volatile uint16_t *)0x400092FC) // TCD Control and Status
#define DMA_TCD23_BITER_ELINKYES (*(volatile uint16_t *)0x400092FE) // TCD Beginning Minor Loop Link
#define DMA_TCD23_BITER_ELINKNO (*(volatile uint16_t *)0x400092FE) // TCD Beginning Minor Loop Link
#define DMA_TCD24_SADDR (*(volatile const void * volatile *)0x40009300) // TCD Source Addr
#define DMA_TCD24_SOFF (*(volatile int16_t *)0x40009304) // TCD Signed Source Address Offset
#define DMA_TCD24_ATTR (*(volatile uint16_t *)0x40009306) // TCD Transfer Attributes
#define DMA_TCD24_NBYTES_MLNO (*(volatile uint32_t *)0x40009308) // TCD Minor Byte Count
#define DMA_TCD24_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009308) // TCD Signed Minor Loop Offset
#define DMA_TCD24_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009308) // TCD Signed Minor Loop Offset
#define DMA_TCD24_SLAST (*(volatile int32_t *)0x4000930C) // TCD Last Source Addr Adj.
#define DMA_TCD24_DADDR (*(volatile void * volatile *)0x40009310) // TCD Destination Address
#define DMA_TCD24_DOFF (*(volatile int16_t *)0x40009314) // TCD Signed Dest Address Offset
#define DMA_TCD24_CITER_ELINKYES (*(volatile uint16_t *)0x40009316) // TCD Current Minor Loop Link
#define DMA_TCD24_CITER_ELINKNO (*(volatile uint16_t *)0x40009316) // ??
#define DMA_TCD24_DLASTSGA (*(volatile int32_t *)0x40009318) // TCD Last Destination Addr Adj
#define DMA_TCD24_CSR (*(volatile uint16_t *)0x4000931C) // TCD Control and Status
#define DMA_TCD24_BITER_ELINKYES (*(volatile uint16_t *)0x4000931E) // TCD Beginning Minor Loop Link
#define DMA_TCD24_BITER_ELINKNO (*(volatile uint16_t *)0x4000931E) // TCD Beginning Minor Loop Link
#define DMA_TCD25_SADDR (*(volatile const void * volatile *)0x40009320) // TCD Source Addr
#define DMA_TCD25_SOFF (*(volatile int16_t *)0x40009324) // TCD Signed Source Address Offset
#define DMA_TCD25_ATTR (*(volatile uint16_t *)0x40009326) // TCD Transfer Attributes
#define DMA_TCD25_NBYTES_MLNO (*(volatile uint32_t *)0x40009328) // TCD Minor Byte Count
#define DMA_TCD25_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009328) // TCD Signed Minor Loop Offset
#define DMA_TCD25_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009328) // TCD Signed Minor Loop Offset
#define DMA_TCD25_SLAST (*(volatile int32_t *)0x4000932C) // TCD Last Source Addr Adj.
#define DMA_TCD25_DADDR (*(volatile void * volatile *)0x40009330) // TCD Destination Address
#define DMA_TCD25_DOFF (*(volatile int16_t *)0x40009334) // TCD Signed Dest Address Offset
#define DMA_TCD25_CITER_ELINKYES (*(volatile uint16_t *)0x40009336) // TCD Current Minor Loop Link
#define DMA_TCD25_CITER_ELINKNO (*(volatile uint16_t *)0x40009336) // ??
#define DMA_TCD25_DLASTSGA (*(volatile int32_t *)0x40009338) // TCD Last Destination Addr Adj
#define DMA_TCD25_CSR (*(volatile uint16_t *)0x4000933C) // TCD Control and Status
#define DMA_TCD25_BITER_ELINKYES (*(volatile uint16_t *)0x4000933E) // TCD Beginning Minor Loop Link
#define DMA_TCD25_BITER_ELINKNO (*(volatile uint16_t *)0x4000933E) // TCD Beginning Minor Loop Link
#define DMA_TCD26_SADDR (*(volatile const void * volatile *)0x40009340) // TCD Source Addr
#define DMA_TCD26_SOFF (*(volatile int16_t *)0x40009344) // TCD Signed Source Address Offset
#define DMA_TCD26_ATTR (*(volatile uint16_t *)0x40009346) // TCD Transfer Attributes
#define DMA_TCD26_NBYTES_MLNO (*(volatile uint32_t *)0x40009348) // TCD Minor Byte Count
#define DMA_TCD26_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009348) // TCD Signed Minor Loop Offset
#define DMA_TCD26_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009348) // TCD Signed Minor Loop Offset
#define DMA_TCD26_SLAST (*(volatile int32_t *)0x4000934C) // TCD Last Source Addr Adj.
#define DMA_TCD26_DADDR (*(volatile void * volatile *)0x40009350) // TCD Destination Address
#define DMA_TCD26_DOFF (*(volatile int16_t *)0x40009354) // TCD Signed Dest Address Offset
#define DMA_TCD26_CITER_ELINKYES (*(volatile uint16_t *)0x40009356) // TCD Current Minor Loop Link
#define DMA_TCD26_CITER_ELINKNO (*(volatile uint16_t *)0x40009356) // ??
#define DMA_TCD26_DLASTSGA (*(volatile int32_t *)0x40009358) // TCD Last Destination Addr Adj
#define DMA_TCD26_CSR (*(volatile uint16_t *)0x4000935C) // TCD Control and Status
#define DMA_TCD26_BITER_ELINKYES (*(volatile uint16_t *)0x4000935E) // TCD Beginning Minor Loop Link
#define DMA_TCD26_BITER_ELINKNO (*(volatile uint16_t *)0x4000935E) // TCD Beginning Minor Loop Link
#define DMA_TCD27_SADDR (*(volatile const void * volatile *)0x40009360) // TCD Source Addr
#define DMA_TCD27_SOFF (*(volatile int16_t *)0x40009364) // TCD Signed Source Address Offset
#define DMA_TCD27_ATTR (*(volatile uint16_t *)0x40009366) // TCD Transfer Attributes
#define DMA_TCD27_NBYTES_MLNO (*(volatile uint32_t *)0x40009368) // TCD Minor Byte Count
#define DMA_TCD27_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009368) // TCD Signed Minor Loop Offset
#define DMA_TCD27_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009368) // TCD Signed Minor Loop Offset
#define DMA_TCD27_SLAST (*(volatile int32_t *)0x4000936C) // TCD Last Source Addr Adj.
#define DMA_TCD27_DADDR (*(volatile void * volatile *)0x40009370) // TCD Destination Address
#define DMA_TCD27_DOFF (*(volatile int16_t *)0x40009374) // TCD Signed Dest Address Offset
#define DMA_TCD27_CITER_ELINKYES (*(volatile uint16_t *)0x40009376) // TCD Current Minor Loop Link
#define DMA_TCD27_CITER_ELINKNO (*(volatile uint16_t *)0x40009376) // ??
#define DMA_TCD27_DLASTSGA (*(volatile int32_t *)0x40009378) // TCD Last Destination Addr Adj
#define DMA_TCD27_CSR (*(volatile uint16_t *)0x4000937C) // TCD Control and Status
#define DMA_TCD27_BITER_ELINKYES (*(volatile uint16_t *)0x4000937E) // TCD Beginning Minor Loop Link
#define DMA_TCD27_BITER_ELINKNO (*(volatile uint16_t *)0x4000937E) // TCD Beginning Minor Loop Link
#define DMA_TCD28_SADDR (*(volatile const void * volatile *)0x40009380) // TCD Source Addr
#define DMA_TCD28_SOFF (*(volatile int16_t *)0x40009384) // TCD Signed Source Address Offset
#define DMA_TCD28_ATTR (*(volatile uint16_t *)0x40009386) // TCD Transfer Attributes
#define DMA_TCD28_NBYTES_MLNO (*(volatile uint32_t *)0x40009388) // TCD Minor Byte Count
#define DMA_TCD28_NBYTES_MLOFFNO (*(volatile uint32_t *)0x40009388) // TCD Signed Minor Loop Offset
#define DMA_TCD28_NBYTES_MLOFFYES (*(volatile uint32_t *)0x40009388) // TCD Signed Minor Loop Offset
#define DMA_TCD28_SLAST (*(volatile int32_t *)0x4000938C) // TCD Last Source Addr Adj.
#define DMA_TCD28_DADDR (*(volatile void * volatile *)0x40009390) // TCD Destination Address
#define DMA_TCD28_DOFF (*(volatile int16_t *)0x40009394) // TCD Signed Dest Address Offset
#define DMA_TCD28_CITER_ELINKYES (*(volatile uint16_t *)0x40009396) // TCD Current Minor Loop Link
#define DMA_TCD28_CITER_ELINKNO (*(volatile uint16_t *)0x40009396) // ??
#define DMA_TCD28_DLASTSGA (*(volatile int32_t *)0x40009398) // TCD Last Destination Addr Adj
#define DMA_TCD28_CSR (*(volatile uint16_t *)0x4000939C) // TCD Control and Status
#define DMA_TCD28_BITER_ELINKYES (*(volatile uint16_t *)0x4000939E) // TCD Beginning Minor Loop Link
#define DMA_TCD28_BITER_ELINKNO (*(volatile uint16_t *)0x4000939E) // TCD Beginning Minor Loop Link
#define DMA_TCD29_SADDR (*(volatile const void * volatile *)0x400093A0) // TCD Source Addr
#define DMA_TCD29_SOFF (*(volatile int16_t *)0x400093A4) // TCD Signed Source Address Offset
#define DMA_TCD29_ATTR (*(volatile uint16_t *)0x400093A6) // TCD Transfer Attributes
#define DMA_TCD29_NBYTES_MLNO (*(volatile uint32_t *)0x400093A8) // TCD Minor Byte Count
#define DMA_TCD29_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400093A8) // TCD Signed Minor Loop Offset
#define DMA_TCD29_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400093A8) // TCD Signed Minor Loop Offset
#define DMA_TCD29_SLAST (*(volatile int32_t *)0x400093AC) // TCD Last Source Addr Adj.
#define DMA_TCD29_DADDR (*(volatile void * volatile *)0x400093B0) // TCD Destination Address
#define DMA_TCD29_DOFF (*(volatile int16_t *)0x400093B4) // TCD Signed Dest Address Offset
#define DMA_TCD29_CITER_ELINKYES (*(volatile uint16_t *)0x400093B6) // TCD Current Minor Loop Link
#define DMA_TCD29_CITER_ELINKNO (*(volatile uint16_t *)0x400093B6) // ??
#define DMA_TCD29_DLASTSGA (*(volatile int32_t *)0x400093B8) // TCD Last Destination Addr Adj
#define DMA_TCD29_CSR (*(volatile uint16_t *)0x400093BC) // TCD Control and Status
#define DMA_TCD29_BITER_ELINKYES (*(volatile uint16_t *)0x400093BE) // TCD Beginning Minor Loop Link
#define DMA_TCD29_BITER_ELINKNO (*(volatile uint16_t *)0x400093BE) // TCD Beginning Minor Loop Link
#define DMA_TCD30_SADDR (*(volatile const void * volatile *)0x400093C0) // TCD Source Addr
#define DMA_TCD30_SOFF (*(volatile int16_t *)0x400093C4) // TCD Signed Source Address Offset
#define DMA_TCD30_ATTR (*(volatile uint16_t *)0x400093C6) // TCD Transfer Attributes
#define DMA_TCD30_NBYTES_MLNO (*(volatile uint32_t *)0x400093C8) // TCD Minor Byte Count
#define DMA_TCD30_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400093C8) // TCD Signed Minor Loop Offset
#define DMA_TCD30_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400093C8) // TCD Signed Minor Loop Offset
#define DMA_TCD30_SLAST (*(volatile int32_t *)0x400093CC) // TCD Last Source Addr Adj.
#define DMA_TCD30_DADDR (*(volatile void * volatile *)0x400093D0) // TCD Destination Address
#define DMA_TCD30_DOFF (*(volatile int16_t *)0x400093D4) // TCD Signed Dest Address Offset
#define DMA_TCD30_CITER_ELINKYES (*(volatile uint16_t *)0x400093D6) // TCD Current Minor Loop Link
#define DMA_TCD30_CITER_ELINKNO (*(volatile uint16_t *)0x400093D6) // ??
#define DMA_TCD30_DLASTSGA (*(volatile int32_t *)0x400093D8) // TCD Last Destination Addr Adj
#define DMA_TCD30_CSR (*(volatile uint16_t *)0x400093DC) // TCD Control and Status
#define DMA_TCD30_BITER_ELINKYES (*(volatile uint16_t *)0x400093DE) // TCD Beginning Minor Loop Link
#define DMA_TCD30_BITER_ELINKNO (*(volatile uint16_t *)0x400093DE) // TCD Beginning Minor Loop Link
#define DMA_TCD31_SADDR (*(volatile const void * volatile *)0x400093E0) // TCD Source Addr
#define DMA_TCD31_SOFF (*(volatile int16_t *)0x400093E4) // TCD Signed Source Address Offset
#define DMA_TCD31_ATTR (*(volatile uint16_t *)0x400093E6) // TCD Transfer Attributes
#define DMA_TCD31_NBYTES_MLNO (*(volatile uint32_t *)0x400093E8) // TCD Minor Byte Count
#define DMA_TCD31_NBYTES_MLOFFNO (*(volatile uint32_t *)0x400093E8) // TCD Signed Minor Loop Offset
#define DMA_TCD31_NBYTES_MLOFFYES (*(volatile uint32_t *)0x400093E8) // TCD Signed Minor Loop Offset
#define DMA_TCD31_SLAST (*(volatile int32_t *)0x400093EC) // TCD Last Source Addr Adj.
#define DMA_TCD31_DADDR (*(volatile void * volatile *)0x400093F0) // TCD Destination Address
#define DMA_TCD31_DOFF (*(volatile int16_t *)0x400093F4) // TCD Signed Dest Address Offset
#define DMA_TCD31_CITER_ELINKYES (*(volatile uint16_t *)0x400093F6) // TCD Current Minor Loop Link
#define DMA_TCD31_CITER_ELINKNO (*(volatile uint16_t *)0x400093F6) // ??
#define DMA_TCD31_DLASTSGA (*(volatile int32_t *)0x400093F8) // TCD Last Destination Addr Adj
#define DMA_TCD31_CSR (*(volatile uint16_t *)0x400093FC) // TCD Control and Status
#define DMA_TCD31_BITER_ELINKYES (*(volatile uint16_t *)0x400093FE) // TCD Beginning Minor Loop Link
#define DMA_TCD31_BITER_ELINKNO (*(volatile uint16_t *)0x400093FE) // TCD Beginning Minor Loop Link
#endif
#elif defined(KINETISL)
#define DMA_SAR0 (*(volatile const void * volatile *)0x40008100) // Source Address
#define DMA_DAR0 (*(volatile void * volatile *)0x40008104) // Destination Address
#define DMA_DSR_BCR0 (*(volatile uint32_t *)0x40008108) // Status / Byte Count
#define DMA_DCR0 (*(volatile uint32_t *)0x4000810C) // Control
#define DMA_SAR1 (*(volatile const void * volatile *)0x40008110) // Source Address
#define DMA_DAR1 (*(volatile void * volatile *)0x40008114) // Destination Address
#define DMA_DSR_BCR1 (*(volatile uint32_t *)0x40008118) // Status / Byte Count
#define DMA_DCR1 (*(volatile uint32_t *)0x4000811C) // Control
#define DMA_SAR2 (*(volatile const void * volatile *)0x40008120) // Source Address
#define DMA_DAR2 (*(volatile void * volatile *)0x40008124) // Destination Address
#define DMA_DSR_BCR2 (*(volatile uint32_t *)0x40008128) // Status / Byte Count
#define DMA_DCR2 (*(volatile uint32_t *)0x4000812C) // Control
#define DMA_SAR3 (*(volatile const void * volatile *)0x40008130) // Source Address
#define DMA_DAR3 (*(volatile void * volatile *)0x40008134) // Destination Address
#define DMA_DSR_BCR3 (*(volatile uint32_t *)0x40008138) // Status / Byte Count
#define DMA_DCR3 (*(volatile uint32_t *)0x4000813C) // Control
#define DMA_DSR_BCR_CE ((uint32_t)0x40000000) // Configuration Error
#define DMA_DSR_BCR_BES ((uint32_t)0x20000000) // Bus Error on Source
#define DMA_DSR_BCR_BED ((uint32_t)0x10000000) // Bus Error on Destination
#define DMA_DSR_BCR_REQ ((uint32_t)0x04000000) // Request
#define DMA_DSR_BCR_BSY ((uint32_t)0x02000000) // Busy
#define DMA_DSR_BCR_DONE ((uint32_t)0x01000000) // Transactions Done
#define DMA_DSR_BCR_BCR(n) ((n) & 0x00FFFFFF) // Byte Count Remaining
#define DMA_DCR_EINT ((uint32_t)0x80000000) // Enable Interrupt on Completion
#define DMA_DCR_ERQ ((uint32_t)0x40000000) // Enable Peripheral Request
#define DMA_DCR_CS ((uint32_t)0x20000000) // Cycle Steal
#define DMA_DCR_AA ((uint32_t)0x10000000) // Auto-align
#define DMA_DCR_EADREQ ((uint32_t)0x00800000) // Enable asynchronous DMA requests
#define DMA_DCR_SINC ((uint32_t)0x00400000) // Source Increment
#define DMA_DCR_SSIZE(n) (((n) & 3) << 20) // Source Size, 0=32, 1=8, 2=16
#define DMA_DCR_DINC ((uint32_t)0x00080000) // Destination Increment
#define DMA_DCR_DSIZE(n) (((n) & 3) << 17) // Dest Size, 0=32, 1=8, 2=16
#define DMA_DCR_START ((uint32_t)0x00010000) // Start Transfer
#define DMA_DCR_SMOD(n) (((n) & 15) << 12) // Source Address Modulo
#define DMA_DCR_DMOD(n) (((n) & 15) << 8) // Destination Address Modulo
#define DMA_DCR_D_REQ ((uint32_t)0x00000080) // Disable Request
#define DMA_DCR_LINKCC(n) (((n) & 3) << 4) // Link Channel Control
#define DMA_DCR_LCH1(n) (((n) & 3) << 2) // Link Channel 1
#define DMA_DCR_LCH2(n) (((n) & 3) << 0) // Link Channel 2
#endif
// External Watchdog Monitor (EWM)
#define EWM_CTRL (*(volatile uint8_t *)0x40061000) // Control Register
#define EWM_SERV (*(volatile uint8_t *)0x40061001) // Service Register
#define EWM_CMPL (*(volatile uint8_t *)0x40061002) // Compare Low Register
#define EWM_CMPH (*(volatile uint8_t *)0x40061003) // Compare High Register
// Watchdog Timer (WDOG)
#define WDOG_STCTRLH (*(volatile uint16_t *)0x40052000) // Watchdog Status and Control Register High
#define WDOG_STCTRLH_DISTESTWDOG ((uint16_t)0x4000) // Allows the WDOG's functional test mode to be disabled permanently.
#define WDOG_STCTRLH_BYTESEL(n) ((uint16_t)(((n) & 3) << 12)) // selects the byte to be tested when the watchdog is in the byte test mode.
#define WDOG_STCTRLH_TESTSEL ((uint16_t)0x0800)
#define WDOG_STCTRLH_TESTWDOG ((uint16_t)0x0400)
#define WDOG_STCTRLH_WAITEN ((uint16_t)0x0080)
#define WDOG_STCTRLH_STOPEN ((uint16_t)0x0040)
#define WDOG_STCTRLH_DBGEN ((uint16_t)0x0020)
#define WDOG_STCTRLH_ALLOWUPDATE ((uint16_t)0x0010)
#define WDOG_STCTRLH_WINEN ((uint16_t)0x0008)
#define WDOG_STCTRLH_IRQRSTEN ((uint16_t)0x0004)
#define WDOG_STCTRLH_CLKSRC ((uint16_t)0x0002)
#define WDOG_STCTRLH_WDOGEN ((uint16_t)0x0001)
#define WDOG_STCTRLL (*(volatile uint16_t *)0x40052002) // Watchdog Status and Control Register Low
#define WDOG_TOVALH (*(volatile uint16_t *)0x40052004) // Watchdog Time-out Value Register High
#define WDOG_TOVALL (*(volatile uint16_t *)0x40052006) // Watchdog Time-out Value Register Low
#define WDOG_WINH (*(volatile uint16_t *)0x40052008) // Watchdog Window Register High
#define WDOG_WINL (*(volatile uint16_t *)0x4005200A) // Watchdog Window Register Low
#define WDOG_REFRESH (*(volatile uint16_t *)0x4005200C) // Watchdog Refresh register
#define WDOG_UNLOCK (*(volatile uint16_t *)0x4005200E) // Watchdog Unlock register
#define WDOG_UNLOCK_SEQ1 ((uint16_t)0xC520)
#define WDOG_UNLOCK_SEQ2 ((uint16_t)0xD928)
#define WDOG_TMROUTH (*(volatile uint16_t *)0x40052010) // Watchdog Timer Output Register High
#define WDOG_TMROUTL (*(volatile uint16_t *)0x40052012) // Watchdog Timer Output Register Low
#define WDOG_RSTCNT (*(volatile uint16_t *)0x40052014) // Watchdog Reset Count register
#define WDOG_PRESC (*(volatile uint16_t *)0x40052016) // Watchdog Prescaler register
// Multipurpose Clock Generator (MCG)
typedef struct {
volatile uint8_t C1;
volatile uint8_t C2;
volatile uint8_t C3;
volatile uint8_t C4;
volatile uint8_t C5;
volatile uint8_t C6;
volatile uint8_t S;
volatile uint8_t unused1;
volatile uint8_t SC;
volatile uint8_t unused2;
volatile uint8_t ATCVH;
volatile uint8_t ATCVL;
volatile uint8_t C7;
volatile uint8_t C8;
volatile uint8_t C9;
volatile uint8_t unused3;
volatile uint8_t C11;
volatile uint8_t C12;
volatile uint8_t S2;
volatile uint8_t T3;
} KINETIS_MCG_t;
#define KINETIS_MCG (*(KINETIS_MCG_t *)0x40064000)
#define MCG_C1 (KINETIS_MCG.C1) // 40064000 MCG Control 1 Register
#define MCG_C1_IREFSTEN (uint8_t)0x01 // Internal Reference Stop Enable, Controls whether or not the internal reference clock remains enabled when the MCG enters Stop mode.
#define MCG_C1_IRCLKEN (uint8_t)0x02 // Internal Reference Clock Enable, Enables the internal reference clock for use as MCGIRCLK.
#define MCG_C1_IREFS (uint8_t)0x04 // Internal Reference Select, Selects the reference clock source for the FLL.
#define MCG_C1_FRDIV(n) (uint8_t)(((n) & 0x07) << 3) // FLL External Reference Divider, Selects the amount to divide down the external reference clock for the FLL
#define MCG_C1_CLKS(n) (uint8_t)(((n) & 0x03) << 6) // Clock Source Select, Selects the clock source for MCGOUTCLK
#define MCG_C2 (KINETIS_MCG.C2) // 40064001 MCG Control 2 Register
#define MCG_C2_IRCS (uint8_t)0x01 // Internal Reference Clock Select, Selects between the fast or slow internal reference clock source.
#define MCG_C2_LP (uint8_t)0x02 // Low Power Select, Controls whether the FLL or PLL is disabled in BLPI and BLPE modes.
#define MCG_C2_EREFS (uint8_t)0x04 // External Reference Select, Selects the source for the external reference clock.
#define MCG_C2_HGO0 (uint8_t)0x08 // High Gain Oscillator Select, Controls the crystal oscillator mode of operation
#define MCG_C2_RANGE0(n) (uint8_t)(((n) & 0x03) << 4) // Frequency Range Select, Selects the frequency range for the crystal oscillator
#define MCG_C2_LOCRE0 (uint8_t)0x80 // Loss of Clock Reset Enable, Determines whether an interrupt or a reset request is made following a loss of OSC0
#define MCG_C3 (KINETIS_MCG.C3) // 40064002 MCG Control 3 Register
#define MCG_C3_SCTRIM(n) (uint8_t)(n) // Slow Internal Reference Clock Trim Setting
#define MCG_C4 (KINETIS_MCG.C4) // 40064003 MCG Control 4 Register
#define MCG_C4_SCFTRIM (uint8_t)0x01 // Slow Internal Reference Clock Fine Trim
#define MCG_C4_FCTRIM(n) (uint8_t)(((n) & 0x0F) << 1) // Fast Internal Reference Clock Trim Setting
#define MCG_C4_DRST_DRS(n) (uint8_t)(((n) & 0x03) << 5) // DCO Range Select
#define MCG_C4_DMX32 (uint8_t)0x80 // DCO Maximum Frequency with 32.768 kHz Reference, controls whether the DCO frequency range is narrowed
#define MCG_C5 (KINETIS_MCG.C5) // 40064004 MCG Control 5 Register
#define MCG_C5_PRDIV0(n) (uint8_t)((n) & 0x1F) // PLL External Reference Divider
#define MCG_C5_PLLSTEN0 (uint8_t)0x20 // PLL Stop Enable
#define MCG_C5_PLLCLKEN0 (uint8_t)0x40 // PLL Clock Enable
#define MCG_C6 (KINETIS_MCG.C6) // 40064005 MCG Control 6 Register
#define MCG_C6_VDIV0(n) (uint8_t)((n) & 0x1F) // VCO 0 Divider
#define MCG_C6_CME0 (uint8_t)0x20 // Clock Monitor Enable
#define MCG_C6_PLLS (uint8_t)0x40 // PLL Select, Controls whether the PLL or FLL output is selected as the MCG source when CLKS[1:0]=00.
#define MCG_C6_LOLIE0 (uint8_t)0x80 // Loss of Lock Interrrupt Enable
#define MCG_S (KINETIS_MCG.S) // 40064006 MCG Status Register
#define MCG_S_IRCST (uint8_t)0x01 // Internal Reference Clock Status
#define MCG_S_OSCINIT0 (uint8_t)0x02 // OSC Initialization, resets to 0, is set to 1 after the initialization cycles of the crystal oscillator
#define MCG_S_CLKST(n) (uint8_t)(((n) & 0x03) << 2) // Clock Mode Status, 0=FLL is selected, 1= Internal ref, 2=External ref, 3=PLL
#define MCG_S_CLKST_MASK (uint8_t)0x0C
#define MCG_S_IREFST (uint8_t)0x10 // Internal Reference Status
#define MCG_S_PLLST (uint8_t)0x20 // PLL Select Status
#define MCG_S_LOCK0 (uint8_t)0x40 // Lock Status, 0=PLL Unlocked, 1=PLL Locked
#define MCG_S_LOLS0 (uint8_t)0x80 // Loss of Lock Status
#define MCG_SC (KINETIS_MCG.SC) // 40064008 MCG Status and Control Register
#define MCG_SC_LOCS0 (uint8_t)0x01 // OSC0 Loss of Clock Status
#define MCG_SC_FCRDIV(n) (uint8_t)(((n) & 0x07) << 1) // Fast Clock Internal Reference Divider
#define MCG_SC_FLTPRSRV (uint8_t)0x10 // FLL Filter Preserve Enable
#define MCG_SC_ATMF (uint8_t)0x20 // Automatic Trim Machine Fail Flag
#define MCG_SC_ATMS (uint8_t)0x40 // Automatic Trim Machine