From a2f723047cecbb3242b6d747469b0edab8710b9e Mon Sep 17 00:00:00 2001
From: Yash Gupta <hpsyash@gmail.com>
Date: Wed, 5 Oct 2022 11:40:19 +0530
Subject: [PATCH] Fix issue 15 counter

---
 .../counter.v                                 | 21 ++++++++++++
 .../counter_tb.v                              | 34 +++++++++++++++++++
 2 files changed, 55 insertions(+)
 create mode 100644 Verilog Codes for Hardware Modelling/counter.v
 create mode 100644 Verilog Codes for Hardware Modelling/counter_tb.v

diff --git a/Verilog Codes for Hardware Modelling/counter.v b/Verilog Codes for Hardware Modelling/counter.v
new file mode 100644
index 0000000..d4a88c8
--- /dev/null
+++ b/Verilog Codes for Hardware Modelling/counter.v	
@@ -0,0 +1,21 @@
+module N_bit_sync_counter(x,ud,clk,clr,q,y);
+
+parameter N = 4;
+
+input x,ud,clk,clr;
+
+output reg [N-1:0] q;
+output reg y;
+
+always @ (negedge clk,posedge clr)
+if (clr==1) 
+  begin
+  q<=0;
+  y<=0;
+  end
+else
+if (x == 1) 
+  if (ud==1) {y,q} <= q + 1'b1;
+  else
+  {y,q} <= q - 1'b1;
+endmodule
\ No newline at end of file
diff --git a/Verilog Codes for Hardware Modelling/counter_tb.v b/Verilog Codes for Hardware Modelling/counter_tb.v
new file mode 100644
index 0000000..0d5f2ec
--- /dev/null
+++ b/Verilog Codes for Hardware Modelling/counter_tb.v	
@@ -0,0 +1,34 @@
+`timescale 1ns / 1ps
+
+module N_bit_sync_counter_tb;
+
+parameter N = 4; 
+
+reg x,ud,clk,clr;
+wire [N-1:0] q;
+wire y;
+
+N_bit_sync_counter UUT(x,ud,clk,clr,q,y);
+
+initial begin
+clk = 0;
+forever 
+#5 clk = ~clk ;
+end
+
+initial begin
+
+#5 clr = 1'b1;
+#5 clr = 1'b0;
+   ud=1'b0;
+
+x = 1'b1; 
+end
+	
+initial  
+begin
+$display("\ttime,\tq,\ty"); 
+$monitor("\t%d,\t%b,\t%b",$time,q,y); 
+end   
+      
+endmodule
\ No newline at end of file