From f7282716cc67180d086f8dc4de974956845437ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Mon, 10 Sep 2012 19:26:29 +0200 Subject: [PATCH 01/18] Prepare architecture to connect kernels with the shared memory --- .../master_v1_00_a/data/master_v2_1_0.mpd | 26 ++--- hw/pcores/master_v1_00_a/hdl/vhdl/master.vhd | 101 ++++------------ .../master_v1_00_a/hdl/vhdl/user_logic.vhd | 110 +++++++++++------- .../data/registers_v2_1_0.mpd | 24 ++-- .../registers_v2_00_a/hdl/vhdl/registers.vhd | 48 +++----- .../registers_v2_00_a/hdl/vhdl/user_logic.vhd | 106 ++++++++--------- src/lib/get_latest_pcore_version.sh | 4 +- src/mhs.tcl | 48 +++----- 8 files changed, 192 insertions(+), 275 deletions(-) diff --git a/hw/pcores/master_v1_00_a/data/master_v2_1_0.mpd b/hw/pcores/master_v1_00_a/data/master_v2_1_0.mpd index 8d63e4d..c729eff 100644 --- a/hw/pcores/master_v1_00_a/data/master_v2_1_0.mpd +++ b/hw/pcores/master_v1_00_a/data/master_v2_1_0.mpd @@ -50,7 +50,7 @@ PORT address_in_2 = "", DIR = I, VEC = [31:0] PORT address_in_3 = "", DIR = I, VEC = [31:0] PORT go = "", DIR = I PORT ready = "", DIR = O -PORT DEBUG_signal_master = "", DIR = O, VEC = [250:0] +PORT chipscope_probe = "", DIR = O, VEC = [255:0] PORT DO_0 = "", DIR = O, VEC = [31:0] PORT DO_1 = "", DIR = O, VEC = [31:0] PORT DO_2 = "", DIR = O, VEC = [31:0] @@ -59,25 +59,17 @@ PORT DI_0 = "", DIR = I, VEC = [31:0] PORT DI_1 = "", DIR = I, VEC = [31:0] PORT DI_2 = "", DIR = I, VEC = [31:0] PORT DI_3 = "", DIR = I, VEC = [31:0] -PORT ADDR_0 = "", DIR = I, VEC = [9:0] -PORT ADDR_1 = "", DIR = I, VEC = [9:0] -PORT ADDR_2 = "", DIR = I, VEC = [9:0] -PORT ADDR_3 = "", DIR = I, VEC = [9:0] +PORT ADDR_0_W = "", DIR = I, VEC = [9:0] +PORT ADDR_1_W = "", DIR = I, VEC = [9:0] +PORT ADDR_2_W = "", DIR = I, VEC = [9:0] +PORT ADDR_3_W = "", DIR = I, VEC = [9:0] +PORT ADDR_0_R = "", DIR = I, VEC = [9:0] +PORT ADDR_1_R = "", DIR = I, VEC = [9:0] +PORT ADDR_2_R = "", DIR = I, VEC = [9:0] +PORT ADDR_3_R = "", DIR = I, VEC = [9:0] PORT BRAM_CLK = "", DIR = I PORT TRIG_CLK = "", DIR = I PORT RST = "", DIR = I -PORT WE_0 = "", DIR = I, VEC = [3:0] -PORT WE_1 = "", DIR = I, VEC = [3:0] -PORT WE_2 = "", DIR = I, VEC = [3:0] -PORT WE_3 = "", DIR = I, VEC = [3:0] -PORT REQ_0 = "", DIR = I -PORT REQ_1 = "", DIR = I -PORT REQ_2 = "", DIR = I -PORT REQ_3 = "", DIR = I -PORT RDY_0 = "", DIR = O -PORT RDY_1 = "", DIR = O -PORT RDY_2 = "", DIR = O -PORT RDY_3 = "", DIR = O PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/master.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/master.vhd index 8aaed9f..e5c318f 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/master.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/master.vhd @@ -185,20 +185,18 @@ entity master is ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here - address_in_0 : in std_logic_vector(31 downto 0); - address_in_1 : in std_logic_vector(31 downto 0); - address_in_2 : in std_logic_vector(31 downto 0); - address_in_3 : in std_logic_vector(31 downto 0); - go : in std_logic; - ready : out std_logic; - DEBUG_signal_master : out std_logic_vector(250 downto 0); - DO_0, DO_1, DO_2, DO_3 : out std_logic_vector(31 downto 0); - DI_0, DI_1, DI_2, DI_3 : in std_logic_vector(31 downto 0); - ADDR_0, ADDR_1, ADDR_2, ADDR_3 : in std_logic_vector(9 downto 0); - BRAM_CLK, TRIG_CLK, RST : in std_logic; - WE_0, WE_1, WE_2, WE_3 : in std_logic_vector(3 downto 0); - REQ_0, REQ_1, REQ_2, REQ_3 : in std_logic; - RDY_0, RDY_1, RDY_2, RDY_3 : out std_logic; + address_in_0 : in std_logic_vector(31 downto 0); + address_in_1 : in std_logic_vector(31 downto 0); + address_in_2 : in std_logic_vector(31 downto 0); + address_in_3 : in std_logic_vector(31 downto 0); + go : in std_logic; + ready : out std_logic; + chipscope_probe : out std_logic_vector(255 downto 0); + DO_0, DO_1, DO_2, DO_3 : out std_logic_vector(31 downto 0); + DI_0, DI_1, DI_2, DI_3 : in std_logic_vector(31 downto 0); + ADDR_0_W, ADDR_1_W, ADDR_2_W, ADDR_3_W : in std_logic_vector(9 downto 0); + ADDR_0_R, ADDR_1_R, ADDR_2_R, ADDR_3_R : in std_logic_vector(9 downto 0); + BRAM_CLK, TRIG_CLK, RST : in std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- @@ -378,55 +376,8 @@ architecture IMP of master is signal user_IP2Bus_RdAck : std_logic; signal user_IP2Bus_WrAck : std_logic; signal user_IP2Bus_Error : std_logic; --- ------------------ --- signal DEBUG_signal : std_logic_vector(153 downto 0); --- signal DEBUG_md_error : std_logic; --- signal DEBUG_m_axi_awvalid : std_logic; --- signal DEBUG_m_axi_awaddr : std_logic_vector(31 downto 0); --- signal DEBUG_m_axi_awlen : std_logic_vector(7 downto 0); --- signal DEBUG_m_axi_awsize : std_logic_vector(2 downto 0); --- signal DEBUG_m_axi_awburst : std_logic_vector(1 downto 0); --- signal DEBUG_m_axi_awprot : std_logic_vector(2 downto 0); --- signal DEBUG_m_axi_wvalid : std_logic; --- signal DEBUG_m_axi_wdata : std_logic_vector(31 downto 0); --- signal DEBUG_m_axi_wstrb : std_logic_vector(3 downto 0); --- signal DEBUG_m_axi_wlast : std_logic; --- signal DEBUG_m_axi_bready : std_logic; --- ------------------ + begin --- ------------------ debug --- md_error <= DEBUG_md_error; --- m_axi_awvalid <= DEBUG_m_axi_awvalid; --- m_axi_awaddr <= DEBUG_m_axi_awaddr; --- m_axi_awlen <= DEBUG_m_axi_awlen; --- m_axi_awsize <= DEBUG_m_axi_awsize; --- m_axi_awburst <= DEBUG_m_axi_awburst; --- m_axi_awprot <= DEBUG_m_axi_awprot; --- m_axi_wvalid <= DEBUG_m_axi_wvalid; --- m_axi_wdata <= DEBUG_m_axi_wdata; --- m_axi_wstrb <= DEBUG_m_axi_wstrb; --- m_axi_wlast <= DEBUG_m_axi_wlast; --- m_axi_bready <= DEBUG_m_axi_bready; --- DEBUG_signal_master <= DEBUG_md_error& --1 --- m_axi_awready& --1 --- DEBUG_m_axi_awvalid& --1 --- DEBUG_m_axi_awaddr& --32 --- DEBUG_m_axi_awlen& --8 --- DEBUG_m_axi_awsize& --3 --- DEBUG_m_axi_awburst& --2 --- DEBUG_m_axi_awprot& --3 --- DEBUG_m_axi_wvalid& --1 --- m_axi_wready& --1 --- DEBUG_m_axi_wdata& --32 --- DEBUG_m_axi_wstrb& --4 --- DEBUG_m_axi_wlast& --1 --- DEBUG_m_axi_bready& --1 --- m_axi_bvalid& --1 --- m_axi_bresp& --2 --- DEBUG_signal; --251 --- -------------- --- --251 bits --- ------------------ ------------------------------------------ -- instantiate axi_lite_ipif ------------------------------------------ @@ -583,7 +534,7 @@ begin address_in_3 => address_in_3, go => go, ready => ready, - DEBUG_signal => DEBUG_signal_master, + chipscope_probe => chipscope_probe, DO_0 => DO_0, DO_1 => DO_1, DO_2 => DO_2, @@ -592,25 +543,17 @@ begin DI_1 => DI_1, DI_2 => DI_2, DI_3 => DI_3, - ADDR_0 => ADDR_0, - ADDR_1 => ADDR_1, - ADDR_2 => ADDR_2, - ADDR_3 => ADDR_3, + ADDR_0_W => ADDR_0_W, + ADDR_1_W => ADDR_1_W, + ADDR_2_W => ADDR_2_W, + ADDR_3_W => ADDR_3_W, + ADDR_0_R => ADDR_0_R, + ADDR_1_R => ADDR_1_R, + ADDR_2_R => ADDR_2_R, + ADDR_3_R => ADDR_3_R, BRAM_CLK => BRAM_CLK, TRIG_CLK => TRIG_CLK, RST => RST, - WE_0 => WE_0, - WE_1 => WE_1, - WE_2 => WE_2, - WE_3 => WE_3, - REQ_0 => REQ_0, - REQ_1 => REQ_1, - REQ_2 => REQ_2, - REQ_3 => REQ_3, - RDY_0 => RDY_0, - RDY_1 => RDY_1, - RDY_2 => RDY_2, - RDY_3 => RDY_3, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => ipif_Bus2IP_Clk, diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/user_logic.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/user_logic.vhd index 9dcaf79..fd9f9b7 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/user_logic.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/user_logic.vhd @@ -134,20 +134,18 @@ entity user_logic is ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here - address_in_0 : in std_logic_vector(31 downto 0); - address_in_1 : in std_logic_vector(31 downto 0); - address_in_2 : in std_logic_vector(31 downto 0); - address_in_3 : in std_logic_vector(31 downto 0); - go : in std_logic; - ready : out std_logic; - DEBUG_signal : out std_logic_vector(250 downto 0); - DO_0, DO_1, DO_2, DO_3 : out std_logic_vector(31 downto 0); - DI_0, DI_1, DI_2, DI_3 : in std_logic_vector(31 downto 0); - ADDR_0, ADDR_1, ADDR_2, ADDR_3 : in std_logic_vector(9 downto 0); - BRAM_CLK, TRIG_CLK, RST : in std_logic; - WE_0, WE_1, WE_2, WE_3 : in std_logic_vector(3 downto 0); - REQ_0, REQ_1, REQ_2, REQ_3 : in std_logic; - RDY_0, RDY_1, RDY_2, RDY_3 : out std_logic; + address_in_0 : in std_logic_vector(31 downto 0); + address_in_1 : in std_logic_vector(31 downto 0); + address_in_2 : in std_logic_vector(31 downto 0); + address_in_3 : in std_logic_vector(31 downto 0); + go : in std_logic; + ready : out std_logic; + chipscope_probe : out std_logic_vector(255 downto 0); + DO_0, DO_1, DO_2, DO_3 : out std_logic_vector(31 downto 0); + DI_0, DI_1, DI_2, DI_3 : in std_logic_vector(31 downto 0); + ADDR_0_W, ADDR_1_W, ADDR_2_W, ADDR_3_W : in std_logic_vector(9 downto 0); + ADDR_0_R, ADDR_1_R, ADDR_2_R, ADDR_3_R : in std_logic_vector(9 downto 0); + BRAM_CLK, TRIG_CLK, RST : in std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- @@ -552,6 +550,17 @@ architecture IMP of user_logic is signal DEBUG_ip2bus_mstwr_sof_n : std_logic; signal DEBUG_ip2bus_mstwr_eof_n : std_logic; + -- Signals for the shared memory + signal smem_DO_0, smem_DO_1, smem_DO_2, smem_DO_3 : std_logic_vector(31 downto 0); + signal smem_DI_0, smem_DI_1, smem_DI_2, smem_DI_3 : std_logic_vector(31 downto 0); + signal smem_ADDR_0, smem_ADDR_1, smem_ADDR_2, smem_ADDR_3 : std_logic_vector(9 downto 0); + signal smem_BRAM_CLK, smem_TRIG_CLK, smem_RST : std_logic; + signal smem_WE_0, smem_WE_1, smem_WE_2, smem_WE_3 : std_logic_vector(3 downto 0); + signal smem_REQ_0, smem_REQ_1, smem_REQ_2, smem_REQ_3 : std_logic; + signal smem_RDY_0, smem_RDY_1, smem_RDY_2, smem_RDY_3 : std_logic; + + -- Chipscope signals + signal chipscope_probe_signal : std_logic_vector(255 downto 0); ------------------------------------------ @@ -588,6 +597,19 @@ begin -- "0001" C_BASEADDR + 0xC -- ------------------------------------------ + + smem_BRAM_CLK <= BRAM_CLK; + smem_TRIG_CLK <= TRIG_CLK; + smem_RST <= RST; + + DO_0 <= smem_DO_0; + DO_1 <= smem_DO_1; + DO_2 <= smem_DO_2; + DO_3 <= smem_DO_3; + + chipscope_probe <= chipscope_probe_signal; + + slv_reg_write_sel <= Bus2IP_WrCE(1 downto 0); slv_reg_read_sel <= Bus2IP_RdCE(1 downto 0); slv_write_ack <= Bus2IP_WrCE(0) or Bus2IP_WrCE(1); @@ -719,33 +741,33 @@ begin shared_mem : smem port map ( - DO_0 => DO_0, - DO_1 => DO_1, - DO_2 => DO_2, - DO_3 => DO_3, - DI_0 => DI_0, - DI_1 => DI_1, - DI_2 => DI_2, - DI_3 => DI_3, - ADDR_0 => ADDR_0, - ADDR_1 => ADDR_1, - ADDR_2 => ADDR_2, - ADDR_3 => ADDR_3, - BRAM_CLK => BRAM_CLK, - TRIG_CLK => TRIG_CLK, - RST => RST, - WE_0 => WE_0, - WE_1 => WE_1, - WE_2 => WE_2, - WE_3 => WE_3, - REQ_0 => REQ_0, - REQ_1 => REQ_1, - REQ_2 => REQ_2, - REQ_3 => REQ_3, - RDY_0 => RDY_0, - RDY_1 => RDY_1, - RDY_2 => RDY_2, - RDY_3 => RDY_3 + DO_0 => smem_DO_0, + DO_1 => smem_DO_1, + DO_2 => smem_DO_2, + DO_3 => smem_DO_3, + DI_0 => smem_DI_0, + DI_1 => smem_DI_1, + DI_2 => smem_DI_2, + DI_3 => smem_DI_3, + ADDR_0 => smem_ADDR_0, + ADDR_1 => smem_ADDR_1, + ADDR_2 => smem_ADDR_2, + ADDR_3 => smem_ADDR_3, + BRAM_CLK => smem_BRAM_CLK, + TRIG_CLK => smem_TRIG_CLK, + RST => smem_RST, + WE_0 => smem_WE_0, + WE_1 => smem_WE_1, + WE_2 => smem_WE_2, + WE_3 => smem_WE_3, + REQ_0 => smem_REQ_0, + REQ_1 => smem_REQ_1, + REQ_2 => smem_REQ_2, + REQ_3 => smem_REQ_3, + RDY_0 => smem_RDY_0, + RDY_1 => smem_RDY_1, + RDY_2 => smem_RDY_2, + RDY_3 => smem_RDY_3 ); @@ -1061,7 +1083,7 @@ begin ip2bus_mstwr_sof_n <= DEBUG_ip2bus_mstwr_sof_n; ip2bus_mstwr_eof_n <= DEBUG_ip2bus_mstwr_eof_n; DEBUG_bus2ip_mst_error <= bus2ip_mst_error; - DEBUG_signal <= ready3& --1 + chipscope_probe_signal <= ready3& --1 ready2& --1 ready1& --1 ready0& --1 @@ -1107,7 +1129,9 @@ begin bus2ip_mst_cmdack& --1 DEBUG_bus2ip_mst_error& --1 DEBUG_ip2bus_mst_length& --12 - DEBUG_ESTADO&'1'; --5+1 + DEBUG_ESTADO& + '1'& --5+1 + (4 downto 0 => '0'); ------------ --251 diff --git a/hw/pcores/registers_v2_00_a/data/registers_v2_1_0.mpd b/hw/pcores/registers_v2_00_a/data/registers_v2_1_0.mpd index db32762..d4b4b3e 100644 --- a/hw/pcores/registers_v2_00_a/data/registers_v2_1_0.mpd +++ b/hw/pcores/registers_v2_00_a/data/registers_v2_1_0.mpd @@ -50,23 +50,15 @@ PORT DI_0 = "", DIR = O, VEC = [31:0] PORT DI_1 = "", DIR = O, VEC = [31:0] PORT DI_2 = "", DIR = O, VEC = [31:0] PORT DI_3 = "", DIR = O, VEC = [31:0] -PORT ADDR_0 = "", DIR = O, VEC = [9:0] -PORT ADDR_1 = "", DIR = O, VEC = [9:0] -PORT ADDR_2 = "", DIR = O, VEC = [9:0] -PORT ADDR_3 = "", DIR = O, VEC = [9:0] +PORT ADDR_0_W = "", DIR = O, VEC = [9:0] +PORT ADDR_1_W = "", DIR = O, VEC = [9:0] +PORT ADDR_2_W = "", DIR = O, VEC = [9:0] +PORT ADDR_3_W = "", DIR = O, VEC = [9:0] +PORT ADDR_0_R = "", DIR = O, VEC = [9:0] +PORT ADDR_1_R = "", DIR = O, VEC = [9:0] +PORT ADDR_2_R = "", DIR = O, VEC = [9:0] +PORT ADDR_3_R = "", DIR = O, VEC = [9:0] PORT RST = "", DIR = O -PORT WE_0 = "", DIR = O, VEC = [3:0] -PORT WE_1 = "", DIR = O, VEC = [3:0] -PORT WE_2 = "", DIR = O, VEC = [3:0] -PORT WE_3 = "", DIR = O, VEC = [3:0] -PORT REQ_0 = "", DIR = O -PORT REQ_1 = "", DIR = O -PORT REQ_2 = "", DIR = O -PORT REQ_3 = "", DIR = O -PORT RDY_0 = "", DIR = I -PORT RDY_1 = "", DIR = I -PORT RDY_2 = "", DIR = I -PORT RDY_3 = "", DIR = I PORT S_AXI_ACLK = "", DIR = I, SIGIS = CLK, BUS = S_AXI PORT S_AXI_ARESETN = ARESETN, DIR = I, SIGIS = RST, BUS = S_AXI diff --git a/hw/pcores/registers_v2_00_a/hdl/vhdl/registers.vhd b/hw/pcores/registers_v2_00_a/hdl/vhdl/registers.vhd index 8465d93..f57d338 100644 --- a/hw/pcores/registers_v2_00_a/hdl/vhdl/registers.vhd +++ b/hw/pcores/registers_v2_00_a/hdl/vhdl/registers.vhd @@ -138,19 +138,17 @@ entity registers is ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here - address_out_0 : out std_logic_vector(31 downto 0); - address_out_1 : out std_logic_vector(31 downto 0); - address_out_2 : out std_logic_vector(31 downto 0); - address_out_3 : out std_logic_vector(31 downto 0); - go : out std_logic; - ready : in std_logic; - DO_0, DO_1, DO_2, DO_3 : in std_logic_vector(31 downto 0); - DI_0, DI_1, DI_2, DI_3 : out std_logic_vector(31 downto 0); - ADDR_0, ADDR_1, ADDR_2, ADDR_3 : out std_logic_vector(9 downto 0); - RST : out std_logic; - WE_0, WE_1, WE_2, WE_3 : out std_logic_vector(3 downto 0); - REQ_0, REQ_1, REQ_2, REQ_3 : out std_logic; - RDY_0, RDY_1, RDY_2, RDY_3 : in std_logic; + address_out_0 : out std_logic_vector(31 downto 0); + address_out_1 : out std_logic_vector(31 downto 0); + address_out_2 : out std_logic_vector(31 downto 0); + address_out_3 : out std_logic_vector(31 downto 0); + go : out std_logic; + ready : in std_logic; + DO_0, DO_1, DO_2, DO_3 : in std_logic_vector(31 downto 0); + DI_0, DI_1, DI_2, DI_3 : out std_logic_vector(31 downto 0); + ADDR_0_W, ADDR_1_W, ADDR_2_W, ADDR_3_W : out std_logic_vector(9 downto 0); + ADDR_0_R, ADDR_1_R, ADDR_2_R, ADDR_3_R : out std_logic_vector(9 downto 0); + RST : out std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- @@ -329,23 +327,15 @@ begin DI_1 => DI_1, DI_2 => DI_2, DI_3 => DI_3, - ADDR_0 => ADDR_0, - ADDR_1 => ADDR_1, - ADDR_2 => ADDR_2, - ADDR_3 => ADDR_3, + ADDR_0_W => ADDR_0_W, + ADDR_1_W => ADDR_1_W, + ADDR_2_W => ADDR_2_W, + ADDR_3_W => ADDR_3_W, + ADDR_0_R => ADDR_0_R, + ADDR_1_R => ADDR_1_R, + ADDR_2_R => ADDR_2_R, + ADDR_3_R => ADDR_3_R, RST => RST, - WE_0 => WE_0, - WE_1 => WE_1, - WE_2 => WE_2, - WE_3 => WE_3, - REQ_0 => REQ_0, - REQ_1 => REQ_1, - REQ_2 => REQ_2, - REQ_3 => REQ_3, - RDY_0 => RDY_0, - RDY_1 => RDY_1, - RDY_2 => RDY_2, - RDY_3 => RDY_3, -- MAP USER PORTS ABOVE THIS LINE ------------------ Bus2IP_Clk => ipif_Bus2IP_Clk, diff --git a/hw/pcores/registers_v2_00_a/hdl/vhdl/user_logic.vhd b/hw/pcores/registers_v2_00_a/hdl/vhdl/user_logic.vhd index c679039..88f070a 100644 --- a/hw/pcores/registers_v2_00_a/hdl/vhdl/user_logic.vhd +++ b/hw/pcores/registers_v2_00_a/hdl/vhdl/user_logic.vhd @@ -98,19 +98,17 @@ entity user_logic is ( -- ADD USER PORTS BELOW THIS LINE ------------------ --USER ports added here - address_out_0 : out std_logic_vector(31 downto 0); - address_out_1 : out std_logic_vector(31 downto 0); - address_out_2 : out std_logic_vector(31 downto 0); - address_out_3 : out std_logic_vector(31 downto 0); - go : out std_logic; - ready : in std_logic; - DO_0, DO_1, DO_2, DO_3 : in std_logic_vector(31 downto 0); - DI_0, DI_1, DI_2, DI_3 : out std_logic_vector(31 downto 0); - ADDR_0, ADDR_1, ADDR_2, ADDR_3 : out std_logic_vector(9 downto 0); - RST : out std_logic; - WE_0, WE_1, WE_2, WE_3 : out std_logic_vector(3 downto 0); - REQ_0, REQ_1, REQ_2, REQ_3 : out std_logic; - RDY_0, RDY_1, RDY_2, RDY_3 : in std_logic; + address_out_0 : out std_logic_vector(31 downto 0); + address_out_1 : out std_logic_vector(31 downto 0); + address_out_2 : out std_logic_vector(31 downto 0); + address_out_3 : out std_logic_vector(31 downto 0); + go : out std_logic; + ready : in std_logic; + DO_0, DO_1, DO_2, DO_3 : in std_logic_vector(31 downto 0); + DI_0, DI_1, DI_2, DI_3 : out std_logic_vector(31 downto 0); + ADDR_0_W, ADDR_1_W, ADDR_2_W, ADDR_3_W : out std_logic_vector(9 downto 0); + ADDR_0_R, ADDR_1_R, ADDR_2_R, ADDR_3_R : out std_logic_vector(9 downto 0); + RST : out std_logic; -- ADD USER PORTS ABOVE THIS LINE ------------------ -- DO NOT EDIT BELOW THIS LINE --------------------- @@ -202,23 +200,15 @@ begin DI_1 <= slv_reg11; DI_2 <= slv_reg12; DI_3 <= slv_reg13; - ADDR_0 <= slv_reg14(9 downto 0); - ADDR_1 <= slv_reg15(9 downto 0); - ADDR_2 <= slv_reg16(9 downto 0); - ADDR_3 <= slv_reg17(9 downto 0); + ADDR_0_W <= slv_reg14(9 downto 0); + ADDR_1_W <= slv_reg15(9 downto 0); + ADDR_2_W <= slv_reg16(9 downto 0); + ADDR_3_W <= slv_reg17(9 downto 0); + ADDR_0_R <= slv_reg14(9 downto 0); + ADDR_1_R <= slv_reg15(9 downto 0); + ADDR_2_R <= slv_reg16(9 downto 0); + ADDR_3_R <= slv_reg17(9 downto 0); RST <= slv_reg18(0); - WE_0 <= slv_reg19(3 downto 0); - WE_1 <= slv_reg20(3 downto 0); - WE_2 <= slv_reg21(3 downto 0); - WE_3 <= slv_reg22(3 downto 0); - REQ_0 <= slv_reg23(0); - REQ_1 <= slv_reg24(0); - REQ_2 <= slv_reg25(0); - REQ_3 <= slv_reg26(0); - slv_reg27(0) <= RDY_0; - slv_reg28(0) <= RDY_1; - slv_reg29(0) <= RDY_2; - slv_reg30(0) <= RDY_3; ------------------------------------------ -- Example code to read/write user logic slave model s/w accessible registers -- @@ -275,10 +265,10 @@ begin slv_reg24 <= (others => '0'); slv_reg25 <= (others => '0'); slv_reg26 <= (others => '0'); --- slv_reg27 <= (others => '0'); --- slv_reg28 <= (others => '0'); --- slv_reg29 <= (others => '0'); --- slv_reg30 <= (others => '0'); + slv_reg27 <= (others => '0'); + slv_reg28 <= (others => '0'); + slv_reg29 <= (others => '0'); + slv_reg30 <= (others => '0'); slv_reg31 <= (others => '0'); else case slv_reg_write_sel is @@ -439,35 +429,35 @@ begin end if; end loop; when "00000000000000000000000000100000" => --- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop --- if ( Bus2IP_BE(byte_index) = '1' ) then --- slv_reg26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); --- end if; --- end loop; + for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop + if ( Bus2IP_BE(byte_index) = '1' ) then + slv_reg26(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); + end if; + end loop; when "00000000000000000000000000010000" => --- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop --- if ( Bus2IP_BE(byte_index) = '1' ) then --- slv_reg27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); --- end if; --- end loop; + for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop + if ( Bus2IP_BE(byte_index) = '1' ) then + slv_reg27(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); + end if; + end loop; when "00000000000000000000000000001000" => --- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop --- if ( Bus2IP_BE(byte_index) = '1' ) then --- slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); --- end if; --- end loop; + for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop + if ( Bus2IP_BE(byte_index) = '1' ) then + slv_reg28(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); + end if; + end loop; when "00000000000000000000000000000100" => --- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop --- if ( Bus2IP_BE(byte_index) = '1' ) then --- slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); --- end if; --- end loop; + for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop + if ( Bus2IP_BE(byte_index) = '1' ) then + slv_reg29(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); + end if; + end loop; when "00000000000000000000000000000010" => --- for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop --- if ( Bus2IP_BE(byte_index) = '1' ) then --- slv_reg30(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); --- end if; --- end loop; + for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop + if ( Bus2IP_BE(byte_index) = '1' ) then + slv_reg30(byte_index*8+7 downto byte_index*8) <= Bus2IP_Data(byte_index*8+7 downto byte_index*8); + end if; + end loop; when "00000000000000000000000000000001" => for byte_index in 0 to (C_SLV_DWIDTH/8)-1 loop if ( Bus2IP_BE(byte_index) = '1' ) then diff --git a/src/lib/get_latest_pcore_version.sh b/src/lib/get_latest_pcore_version.sh index 35ca7f0..ee57aa3 100755 --- a/src/lib/get_latest_pcore_version.sh +++ b/src/lib/get_latest_pcore_version.sh @@ -3,6 +3,8 @@ # # get_latest_pcore_version # -# TODO: normalize path +# TODO: +# - Normalize path +# - Don't take the last 6 characters (read from 'v' the version number) # ls $1/$2* -d | tail -n 1 | sed 's/^.*\(.\{6\}\)$/\1/' | tr '_' '.' diff --git a/src/mhs.tcl b/src/mhs.tcl index b3901f2..5d84eff 100644 --- a/src/mhs.tcl +++ b/src/mhs.tcl @@ -317,23 +317,15 @@ xadd_hw_ipinst_port $registers_0_handle DI_0 smem_DI_0 xadd_hw_ipinst_port $registers_0_handle DI_1 smem_DI_1 xadd_hw_ipinst_port $registers_0_handle DI_2 smem_DI_2 xadd_hw_ipinst_port $registers_0_handle DI_3 smem_DI_3 -xadd_hw_ipinst_port $registers_0_handle ADDR_0 smem_ADDR_0 -xadd_hw_ipinst_port $registers_0_handle ADDR_1 smem_ADDR_1 -xadd_hw_ipinst_port $registers_0_handle ADDR_2 smem_ADDR_2 -xadd_hw_ipinst_port $registers_0_handle ADDR_3 smem_ADDR_3 +xadd_hw_ipinst_port $registers_0_handle ADDR_0_W smem_ADDR_0_W +xadd_hw_ipinst_port $registers_0_handle ADDR_1_W smem_ADDR_1_W +xadd_hw_ipinst_port $registers_0_handle ADDR_2_W smem_ADDR_2_W +xadd_hw_ipinst_port $registers_0_handle ADDR_3_W smem_ADDR_3_W +xadd_hw_ipinst_port $registers_0_handle ADDR_0_R smem_ADDR_0_R +xadd_hw_ipinst_port $registers_0_handle ADDR_1_R smem_ADDR_1_R +xadd_hw_ipinst_port $registers_0_handle ADDR_2_R smem_ADDR_2_R +xadd_hw_ipinst_port $registers_0_handle ADDR_3_R smem_ADDR_3_R xadd_hw_ipinst_port $registers_0_handle RST smem_RST -xadd_hw_ipinst_port $registers_0_handle WE_0 smem_WE_0 -xadd_hw_ipinst_port $registers_0_handle WE_1 smem_WE_1 -xadd_hw_ipinst_port $registers_0_handle WE_2 smem_WE_2 -xadd_hw_ipinst_port $registers_0_handle WE_3 smem_WE_3 -xadd_hw_ipinst_port $registers_0_handle REQ_0 smem_REQ_0 -xadd_hw_ipinst_port $registers_0_handle REQ_1 smem_REQ_1 -xadd_hw_ipinst_port $registers_0_handle REQ_2 smem_REQ_2 -xadd_hw_ipinst_port $registers_0_handle REQ_3 smem_REQ_3 -xadd_hw_ipinst_port $registers_0_handle RDY_0 smem_RDY_0 -xadd_hw_ipinst_port $registers_0_handle RDY_1 smem_RDY_1 -xadd_hw_ipinst_port $registers_0_handle RDY_2 smem_RDY_2 -xadd_hw_ipinst_port $registers_0_handle RDY_3 smem_RDY_3 # # Master @@ -358,25 +350,17 @@ xadd_hw_ipinst_port $master_0_handle DI_0 smem_DI_0 xadd_hw_ipinst_port $master_0_handle DI_1 smem_DI_1 xadd_hw_ipinst_port $master_0_handle DI_2 smem_DI_2 xadd_hw_ipinst_port $master_0_handle DI_3 smem_DI_3 -xadd_hw_ipinst_port $master_0_handle ADDR_0 smem_ADDR_0 -xadd_hw_ipinst_port $master_0_handle ADDR_1 smem_ADDR_1 -xadd_hw_ipinst_port $master_0_handle ADDR_2 smem_ADDR_2 -xadd_hw_ipinst_port $master_0_handle ADDR_3 smem_ADDR_3 +xadd_hw_ipinst_port $master_0_handle ADDR_0_W smem_ADDR_0_W +xadd_hw_ipinst_port $master_0_handle ADDR_1_W smem_ADDR_1_W +xadd_hw_ipinst_port $master_0_handle ADDR_2_W smem_ADDR_2_W +xadd_hw_ipinst_port $master_0_handle ADDR_3_W smem_ADDR_3_W +xadd_hw_ipinst_port $master_0_handle ADDR_0_R smem_ADDR_0_R +xadd_hw_ipinst_port $master_0_handle ADDR_1_R smem_ADDR_1_R +xadd_hw_ipinst_port $master_0_handle ADDR_2_R smem_ADDR_2_R +xadd_hw_ipinst_port $master_0_handle ADDR_3_R smem_ADDR_3_R xadd_hw_ipinst_port $master_0_handle BRAM_CLK clk_100_0000MHz_PLL0_nobuf xadd_hw_ipinst_port $master_0_handle TRIG_CLK clk_100_0000MHz_90_PLL0_nobuf xadd_hw_ipinst_port $master_0_handle RST smem_RST -xadd_hw_ipinst_port $master_0_handle WE_0 smem_WE_0 -xadd_hw_ipinst_port $master_0_handle WE_1 smem_WE_1 -xadd_hw_ipinst_port $master_0_handle WE_2 smem_WE_2 -xadd_hw_ipinst_port $master_0_handle WE_3 smem_WE_3 -xadd_hw_ipinst_port $master_0_handle REQ_0 smem_REQ_0 -xadd_hw_ipinst_port $master_0_handle REQ_1 smem_REQ_1 -xadd_hw_ipinst_port $master_0_handle REQ_2 smem_REQ_2 -xadd_hw_ipinst_port $master_0_handle REQ_3 smem_REQ_3 -xadd_hw_ipinst_port $master_0_handle RDY_0 smem_RDY_0 -xadd_hw_ipinst_port $master_0_handle RDY_1 smem_RDY_1 -xadd_hw_ipinst_port $master_0_handle RDY_2 smem_RDY_2 -xadd_hw_ipinst_port $master_0_handle RDY_3 smem_RDY_3 # # MB_0 debug module From 671ae91774d96f507eeead8d5412e388d907bd6c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Tue, 11 Sep 2012 17:17:25 +0200 Subject: [PATCH 02/18] Shared memory kernel integration still incomplete --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 159 +++++++------ hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd | 238 +++++++++---------- src/lib/get_latest_pcore_version.sh | 22 ++ 3 files changed, 221 insertions(+), 198 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index 8a21bcb..dc4ec4b 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -62,6 +62,8 @@ architecture smem_arch of smem is -- -- Signals -- + -- TODO: update comments bellow! (outdated signals) + -- -- k#_needs_attention Flag which says wether kernel # needs to be attended -- k#_given_port Within a BRAM, this bit sets with port (A|B) kernel # has been assigned -- k#_requested_bram BRAM from/to which we need to read/write (first ADDR_# bits) @@ -103,38 +105,37 @@ architecture smem_arch of smem is signal bram_1_B_input_sel : bit_vector(1 downto 0) := "00"; - signal DO_0_A : std_logic_vector(31 downto 0) := X"00000000"; - signal DO_0_B : std_logic_vector(31 downto 0) := X"00000000"; - signal DI_0_A : std_logic_vector(31 downto 0) := X"00000000"; - signal DI_0_B : std_logic_vector(31 downto 0) := X"00000000"; - signal ADDR_0_A : std_logic_vector(8 downto 0) := "000000000"; - signal ADDR_0_B : std_logic_vector(8 downto 0) := "000000000"; - signal WE_0_A : std_logic_vector(3 downto 0) := "0000"; - signal WE_0_B : std_logic_vector(3 downto 0) := "0000"; - signal EN_0_A : std_logic := '0'; - signal EN_0_B : std_logic := '0'; - - signal DO_1_A : std_logic_vector(31 downto 0) := X"00000000"; - signal DO_1_B : std_logic_vector(31 downto 0) := X"00000000"; - signal DI_1_A : std_logic_vector(31 downto 0) := X"00000000"; - signal DI_1_B : std_logic_vector(31 downto 0) := X"00000000"; - signal ADDR_1_A : std_logic_vector(8 downto 0) := "000000000"; - signal ADDR_1_B : std_logic_vector(8 downto 0) := "000000000"; - signal WE_1_A : std_logic_vector(3 downto 0) := "0000"; - signal WE_1_B : std_logic_vector(3 downto 0) := "0000"; - signal EN_1_A : std_logic := '0'; - signal EN_1_B : std_logic := '0'; + signal do_0_a : std_logic_vector(31 downto 0) := X"00000000"; + signal do_0_b : std_logic_vector(31 downto 0) := X"00000000"; + signal di_0_a : std_logic_vector(31 downto 0) := X"00000000"; + signal di_0_b : std_logic_vector(31 downto 0) := X"00000000"; + signal addr_0_a : std_logic_vector(8 downto 0) := "000000000"; + signal addr_0_b : std_logic_vector(8 downto 0) := "000000000"; + signal we_0_a : std_logic_vector(3 downto 0) := "0000"; + signal we_0_b : std_logic_vector(3 downto 0) := "0000"; + signal en_0_a : std_logic := '0'; + signal en_0_b : std_logic := '0'; + + signal do_1_a : std_logic_vector(31 downto 0) := X"00000000"; + signal do_1_b : std_logic_vector(31 downto 0) := X"00000000"; + signal di_1_a : std_logic_vector(31 downto 0) := X"00000000"; + signal di_1_b : std_logic_vector(31 downto 0) := X"00000000"; + signal addr_1_a : std_logic_vector(8 downto 0) := "000000000"; + signal addr_1_b : std_logic_vector(8 downto 0) := "000000000"; + signal we_1_a : std_logic_vector(3 downto 0) := "0000"; + signal we_1_b : std_logic_vector(3 downto 0) := "0000"; + signal en_1_a : std_logic := '0'; + signal en_1_b : std_logic := '0'; begin - -- TODO: remove the lines bellow (temporary workaround) - EN_0_A <= '1'; - EN_0_B <= '1'; - EN_1_A <= '1'; - EN_1_B <= '1'; - + -- TODO: decide if enable signals should always be set to 1 + en_0_a <= '1'; + en_0_b <= '1'; + en_1_a <= '1'; + en_1_b <= '1'; k0_requested_bram <= ADDR_0(9 downto 9); k1_requested_bram <= ADDR_1(9 downto 9); @@ -395,17 +396,17 @@ begin -- this block implementation bellow: input_controller_0 : block begin with bram_0_A_input_sel select - DI_0_A <= DI_0 when "00", + di_0_a <= DI_0 when "00", DI_1 when "01", DI_2 when "10", DI_3 when "11"; with bram_0_A_input_sel select - ADDR_0_A <= ADDR_0(8 downto 0) when "00", + addr_0_a <= ADDR_0(8 downto 0) when "00", ADDR_1(8 downto 0) when "01", ADDR_2(8 downto 0) when "10", ADDR_3(8 downto 0) when "11"; with bram_0_A_input_sel select - WE_0_A <= WE_0 when "00", + we_0_a <= WE_0 when "00", WE_1 when "01", WE_2 when "10", WE_3 when "11"; @@ -413,17 +414,17 @@ begin input_controller_1 : block begin with bram_0_B_input_sel select - DI_0_B <= DI_0 when "00", + di_0_b <= DI_0 when "00", DI_1 when "01", DI_2 when "10", DI_3 when "11"; with bram_0_B_input_sel select - ADDR_0_B <= ADDR_0(8 downto 0) when "00", + addr_0_b <= ADDR_0(8 downto 0) when "00", ADDR_1(8 downto 0) when "01", ADDR_2(8 downto 0) when "10", ADDR_3(8 downto 0) when "11"; with bram_0_B_input_sel select - WE_0_B <= WE_0 when "00", + we_0_b <= WE_0 when "00", WE_1 when "01", WE_2 when "10", WE_3 when "11"; @@ -431,17 +432,17 @@ begin input_controller_2 : block begin with bram_1_A_input_sel select - DI_1_A <= DI_0 when "00", + di_1_a <= DI_0 when "00", DI_1 when "01", DI_2 when "10", DI_3 when "11"; with bram_1_A_input_sel select - ADDR_1_A <= ADDR_0(8 downto 0) when "00", + addr_1_a <= ADDR_0(8 downto 0) when "00", ADDR_1(8 downto 0) when "01", ADDR_2(8 downto 0) when "10", ADDR_3(8 downto 0) when "11"; with bram_1_A_input_sel select - WE_1_A <= WE_0 when "00", + we_1_a <= WE_0 when "00", WE_1 when "01", WE_2 when "10", WE_3 when "11"; @@ -449,17 +450,17 @@ begin input_controller_3 : block begin with bram_1_B_input_sel select - DI_1_B <= DI_0 when "00", + di_1_b <= DI_0 when "00", DI_1 when "01", DI_2 when "10", DI_3 when "11"; with bram_1_B_input_sel select - ADDR_1_B <= ADDR_0(8 downto 0) when "00", + addr_1_b <= ADDR_0(8 downto 0) when "00", ADDR_1(8 downto 0) when "01", ADDR_2(8 downto 0) when "10", ADDR_3(8 downto 0) when "11"; with bram_1_B_input_sel select - WE_1_B <= WE_0 when "00", + we_1_b <= WE_0 when "00", WE_1 when "01", WE_2 when "10", WE_3 when "11"; @@ -471,43 +472,43 @@ begin -- --output_controller_0 : process (TRIG_CLK) begin -- case k0_output_sel is - -- when "00" => DO_0 <= DO_0_A; - -- when "01" => DO_0 <= DO_0_B; - -- when "10" => DO_0 <= DO_1_A; - -- when "11" => DO_0 <= DO_1_B; + -- when "00" => DO_0 <= do_0_a; + -- when "01" => DO_0 <= do_0_b; + -- when "10" => DO_0 <= do_1_a; + -- when "11" => DO_0 <= do_1_b; -- end case; --end process output_controller_0; -- output_controller_0 : block begin with k0_output_sel select - DO_0 <= DO_0_A when "00", - DO_0_B when "01", - DO_1_A when "10", - DO_1_B when "11"; + DO_0 <= do_0_a when "00", + do_0_b when "01", + do_1_a when "10", + do_1_b when "11"; end block output_controller_0; output_controller_1 : block begin with k1_output_sel select - DO_1 <= DO_0_A when "00", - DO_0_B when "01", - DO_1_A when "10", - DO_1_B when "11"; + DO_1 <= do_0_a when "00", + do_0_b when "01", + do_1_a when "10", + do_1_b when "11"; end block output_controller_1; output_controller_2 : block begin with k2_output_sel select - DO_2 <= DO_0_A when "00", - DO_0_B when "01", - DO_1_A when "10", - DO_1_B when "11"; + DO_2 <= do_0_a when "00", + do_0_b when "01", + do_1_a when "10", + do_1_b when "11"; end block output_controller_2; output_controller_3 : block begin with k3_output_sel select - DO_3 <= DO_0_A when "00", - DO_0_B when "01", - DO_1_A when "10", - DO_1_B when "11"; + DO_3 <= do_0_a when "00", + do_0_b when "01", + do_1_a when "10", + do_1_b when "11"; end block output_controller_3; @@ -630,28 +631,28 @@ begin ) port map ( - DOA => DO_0_A, -- Output port-A data - DOB => DO_0_B, -- Output port-B data + DOA => do_0_a, -- Output port-A data + DOB => do_0_b, -- Output port-B data DOPA => open, -- We are not using parity bits DOPB => open, -- We are not using parity bits - DIA => DI_0_A, -- Input port-A data - DIB => DI_0_B, -- Input port-B data + DIA => di_0_a, -- Input port-A data + DIB => di_0_b, -- Input port-B data DIPA => DIP_value, -- Input parity bits always set to 0 (not using them) DIPB => DIP_value, -- Input parity bits always set to 0 (not using them) - ADDRA(13 downto 5) => ADDR_0_A, -- Input port-A address + ADDRA(13 downto 5) => addr_0_a, -- Input port-A address ADDRA(4 downto 0) => LOWADDR_value, -- Set low adress bits to 0 - ADDRB(13 downto 5) => ADDR_0_B, -- Input port-B address + ADDRB(13 downto 5) => addr_0_b, -- Input port-B address ADDRB(4 downto 0) => LOWADDR_value, -- Set low adress bits to 0 CLKA => BRAM_CLK, -- Input port-A clock CLKB => BRAM_CLK, -- Input port-B clock - ENA => EN_0_A, -- Input port-A enable - ENB => EN_0_B, -- Input port-B enable + ENA => en_0_a, -- Input port-A enable + ENB => en_0_b, -- Input port-B enable REGCEA => REGCE_value, -- Input port-A output register enable REGCEB => REGCE_value, -- Input port-B output register enable RSTA => RST, -- Input port-A reset RSTB => RST, -- Input port-B reset - WEA => WE_0_A, -- Input port-A write enable - WEB => WE_0_B -- Input port-B write enable + WEA => we_0_a, -- Input port-A write enable + WEB => we_0_b -- Input port-B write enable ); @@ -774,28 +775,28 @@ begin ) port map ( - DOA => DO_1_A, -- Output port-A data - DOB => DO_1_B, -- Output port-B data + DOA => do_1_a, -- Output port-A data + DOB => do_1_b, -- Output port-B data DOPA => open, -- We are not using parity bits DOPB => open, -- We are not using parity bits - DIA => DI_1_A, -- Input port-A data - DIB => DI_1_B, -- Input port-B data + DIA => di_1_a, -- Input port-A data + DIB => di_1_b, -- Input port-B data DIPA => DIP_value, -- Input parity bits always set to 0 (not using them) DIPB => DIP_value, -- Input parity bits always set to 0 (not using them) - ADDRA(13 downto 5) => ADDR_1_A, -- Input port-A address + ADDRA(13 downto 5) => addr_1_a, -- Input port-A address ADDRA(4 downto 0) => LOWADDR_value, -- Set low adress bits to 0 - ADDRB(13 downto 5) => ADDR_1_B, -- Input port-B address + ADDRB(13 downto 5) => addr_1_b, -- Input port-B address ADDRB(4 downto 0) => LOWADDR_value, -- Set low adress bits to 0 CLKA => BRAM_CLK, -- Input port-A clock CLKB => BRAM_CLK, -- Input port-B clock - ENA => EN_1_A, -- Input port-A enable - ENB => EN_1_B, -- Input port-B enable + ENA => en_1_a, -- Input port-A enable + ENB => en_1_b, -- Input port-B enable REGCEA => REGCE_value, -- Input port-A output register enable REGCEB => REGCE_value, -- Input port-B output register enable RSTA => RST, -- Input port-A reset RSTB => RST, -- Input port-B reset - WEA => WE_1_A, -- Input port-A write enable - WEB => WE_1_B -- Input port-B write enable + WEA => we_1_a, -- Input port-A write enable + WEB => we_1_b -- Input port-B write enable ); diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd index 554cb98..55b9756 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd @@ -1,171 +1,171 @@ ----------------------------------------------------------------------------------- --- Company: CEI-UPM --- Engineer: Carlos de Frutos Lopez --- --- Create Date: 11:34:39 05/03/2012 --- Design Name: --- Module Name: thread - Behavioral --- Project Name: --- Target Devices: --- Tool versions: --- Description: --- --- Dependencies: --- --- Revision: --- Revision 0.01 - File Created --- Additional Comments: --- ----------------------------------------------------------------------------------- -library IEEE; -use IEEE.STD_LOGIC_1164.ALL; -use IEEE.STD_LOGIC_UNSIGNED.ALL; - --- Uncomment the following library declaration if using --- arithmetic functions with Signed or Unsigned values ---use IEEE.NUMERIC_STD.ALL; - --- Uncomment the following library declaration if instantiating --- any Xilinx primitives in this code. ---library UNISIM; ---use UNISIM.VComponents.all; - -entity thread is - Port ( clk, resetn : in std_logic; - --from/to memory controller - data_in_m : in std_logic_vector (31 downto 0); - data_out_m : out std_logic_vector (31 downto 0); - address_m : out std_logic_vector (31 downto 0); - rd_req_m : out std_logic; - wr_req_m : out std_logic; - ack_m : in std_logic; - --from/to registers - go_r : in std_logic; - ready_r : out std_logic; - address_a_r : in std_logic_vector (31 downto 0); --- address_b_r : in std_logic_vector (31 downto 0) - DATA_DEBUG : out std_logic_vector (31 downto 0) - ); -end thread; - -architecture Behavioral of thread is - -type state_t is ( - IDLE, - READ_A, WAIT_RD_A, - --READ_B, WAIT_RD_B, HAVE_B, - WRITE_C, WAIT_WR, - READ_C, WAIT_RD_C, - DONE - ); -signal state : state_t; -signal aux : std_logic_vector (31 downto 0); ---signal aux2 : std_logic_vector (31 downto 0); - - -begin - +-- +-- thread.vhd +-- +-- Copyright 2012 Miguel Sánchez de León Peque +-- +-- This program is free software; you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation; either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program; if not, write to the Free Software +-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +-- MA 02110-1301, USA. +-- +-- + + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; + + +entity thread is + + port ( + + -- General ports + CLK : in std_logic; + RESETN : in std_logic; + + -- DDR2 + DDR2_DATA_OUT : in std_logic_vector(31 downto 0); + DDR2_DATA_IN : out std_logic_vector(31 downto 0); + DDR2_ADDRESS : out std_logic_vector(31 downto 0); + DDR2_READ_REQ : out std_logic; + DDR2_WRITE_REQ : out std_logic; + DDR2_RDY : in std_logic; + + -- Shared memory + SMEM_DO : in std_logic_vector(31 downto 0); + SMEM_IN : out std_logic_vector(31 downto 0); + SMEM_ADDR : out std_logic_vector(9 downto 0); + SMEM_WE : out std_logic_vector(3 downto 0); + SMEM_REQ : out std_logic_vector; + SMEM_RDY : in std_logic_vector; + + -- Registers + REG_GO : in std_logic; + REG_READY : out std_logic; + REG_DDR2_ADDRESS : in std_logic_vector(31 downto 0); + REG_SMEM_DO : in std_logic_vector(31 downto 0); + REG_SMEM_DI : in std_logic_vector(31 downto 0); + REG_SMEM_ADDR_READ : in std_logic_vector(9 downto 0); + REG_SMEM_ADDR_WRITE : in std_logic_vector(9 downto 0); + + -- Data debug + DATA_DEBUG : out std_logic_vector(31 downto 0) + + ); + +end thread; + + +architecture Behavioral of thread is + + type state_t is ( + IDLE, + READ_DDR2, WAIT_READ_DDR2, + WRITE_C, WAIT_WR, + READ_C, WAIT_RD_C, + DONE + ); + + signal state : state_t; + signal aux : std_logic_vector (31 downto 0); + +begin + thread_SM: process(clk) is begin if ( clk'event and clk = '1' ) then if resetn = '0' then --reset - aux <= (others => '0'); + aux <= (others => '0'); -- aux2 <= (others => '0'); state <= IDLE; data_out_m <= (others => '0'); address_m <= (others => '0'); rd_req_m <= '0'; wr_req_m <= '0'; - ready_r <= '0'; + ready_r <= '0'; DATA_DEBUG <= (others => '0'); - + else - + case state is - - when IDLE => - ready_r <= '0'; - aux <= (others => '0'); --- aux2 <= (others => '0'); + + when IDLE => + ready_r <= '0'; + aux <= (others => '0'); +-- aux2 <= (others => '0'); data_out_m <= (others => '0'); address_m <= (others => '0'); rd_req_m <= '0'; wr_req_m <= '0'; - ready_r <= '0'; - DATA_DEBUG <= (others => '0'); - + ready_r <= '0'; + DATA_DEBUG <= (others => '0'); + if go_r = '1' then state <= READ_A; end if; - + when READ_A => address_m <= address_a_r; rd_req_m <= '1'; state <= WAIT_RD_A; - + when WAIT_RD_A => if ack_m = '1' then --wait for ack - rd_req_m <='0'; - aux <= data_in_m; - DATA_DEBUG <= data_in_m; + rd_req_m <='0'; + aux <= data_in_m; + DATA_DEBUG <= data_in_m; state <= WRITE_C; end if; - - - --- when READ_B => --- address_m <= address_b_r; --- rd_req_m <= '1'; --- state <= WAIT_RD_B; --- --- when WAIT_RD_B => --- if ack_m = '1' then --wait fow ack --- rd_req_m <='0'; --- state <= HAVE_B; --- end if; --- --- when HAVE_B => --- aux2 <= aux + data_in_m; --- state <= WRITE_C; - + when WRITE_C => - address_m <= address_a_r; --in address_a (could change) + address_m <= address_a_r; --in address_a (could change) data_out_m <= address_a_r-x"C0000000"+x"0000009"; --random number wr_req_m <= '1'; state <= WAIT_WR; - + when WAIT_WR => if ack_m = '1' then --wait for ack wr_req_m <= '0'; state <= READ_C; end if; - - + + when READ_C => address_m <= address_a_r; rd_req_m <= '1'; state <= WAIT_RD_C; - + when WAIT_RD_C => if ack_m = '1' then --wait for ack - rd_req_m <='0'; - aux <= data_in_m; - DATA_DEBUG <= data_in_m; + rd_req_m <='0'; + aux <= data_in_m; + DATA_DEBUG <= data_in_m; state <= DONE; end if; - + when DONE => ready_r <= '1'; - state <= DONE; - + state <= DONE; + when others => null; - + end case; --state - + end if; --resetn end if; --clk end process thread_SM; - - -end Behavioral; - + + +end Behavioral; + diff --git a/src/lib/get_latest_pcore_version.sh b/src/lib/get_latest_pcore_version.sh index ee57aa3..f56889f 100755 --- a/src/lib/get_latest_pcore_version.sh +++ b/src/lib/get_latest_pcore_version.sh @@ -1,5 +1,27 @@ #!/bin/bash +# +# get_latest_pcore_version.sh +# +# Copyright 2012 Miguel Sánchez de León Peque +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, +# MA 02110-1301, USA. +# + + # # get_latest_pcore_version # From 718d368121bcd05dc21dea25f702ce03458f4e07 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Wed, 12 Sep 2012 15:42:13 +0200 Subject: [PATCH 03/18] Shared memory integration completed (needs some testing) --- hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd | 199 ++++++++------- .../master_v1_00_a/hdl/vhdl/user_logic.vhd | 228 ++++++++++-------- 2 files changed, 241 insertions(+), 186 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd index 55b9756..1e048fc 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd @@ -47,8 +47,8 @@ entity thread is SMEM_IN : out std_logic_vector(31 downto 0); SMEM_ADDR : out std_logic_vector(9 downto 0); SMEM_WE : out std_logic_vector(3 downto 0); - SMEM_REQ : out std_logic_vector; - SMEM_RDY : in std_logic_vector; + SMEM_REQ : out std_logic; + SMEM_RDY : in std_logic; -- Registers REG_GO : in std_logic; @@ -67,105 +67,120 @@ entity thread is end thread; -architecture Behavioral of thread is +architecture thread_arch of thread is type state_t is ( + IDLE, - READ_DDR2, WAIT_READ_DDR2, + READ_A, WAIT_RD_A, WRITE_C, WAIT_WR, READ_C, WAIT_RD_C, DONE + ); - signal state : state_t; - signal aux : std_logic_vector (31 downto 0); + signal thread_state : state_t; + signal ddr2_data_out_signal : std_logic_vector(31 downto 0); begin -thread_SM: process(clk) is -begin - if ( clk'event and clk = '1' ) then - if resetn = '0' then --reset - aux <= (others => '0'); --- aux2 <= (others => '0'); - state <= IDLE; - data_out_m <= (others => '0'); - address_m <= (others => '0'); - rd_req_m <= '0'; - wr_req_m <= '0'; - ready_r <= '0'; - DATA_DEBUG <= (others => '0'); - - else - - case state is - - when IDLE => - ready_r <= '0'; - aux <= (others => '0'); --- aux2 <= (others => '0'); - data_out_m <= (others => '0'); - address_m <= (others => '0'); - rd_req_m <= '0'; - wr_req_m <= '0'; - ready_r <= '0'; - DATA_DEBUG <= (others => '0'); - - if go_r = '1' then state <= READ_A; - end if; - - when READ_A => - address_m <= address_a_r; - rd_req_m <= '1'; - state <= WAIT_RD_A; - - when WAIT_RD_A => - if ack_m = '1' then --wait for ack - rd_req_m <='0'; - aux <= data_in_m; - DATA_DEBUG <= data_in_m; - state <= WRITE_C; - end if; - - when WRITE_C => - address_m <= address_a_r; --in address_a (could change) - data_out_m <= address_a_r-x"C0000000"+x"0000009"; --random number - wr_req_m <= '1'; - state <= WAIT_WR; - - when WAIT_WR => - if ack_m = '1' then --wait for ack - wr_req_m <= '0'; - state <= READ_C; - end if; - - - when READ_C => - address_m <= address_a_r; - rd_req_m <= '1'; - state <= WAIT_RD_C; - - when WAIT_RD_C => - if ack_m = '1' then --wait for ack - rd_req_m <='0'; - aux <= data_in_m; - DATA_DEBUG <= data_in_m; - state <= DONE; - end if; - - - when DONE => - ready_r <= '1'; - state <= DONE; - - when others => null; - - end case; --state - - end if; --resetn - end if; --clk -end process thread_SM; - - -end Behavioral; + thread_sm : process (CLK) is + + begin + + if ( clk'event and clk = '1' ) then + + if resetn = '0' then + + ddr2_data_out_signal <= X"00000000"; + thread_state <= IDLE; + DDR2_DATA_IN <= X"00000000"; + DDR2_ADDRESS <= X"00000000"; + DDR2_READ_REQ <= '0'; + DDR2_WRITE_REQ <= '0'; + SMEM_IN <= X"00000000"; + SMEM_ADDR <= "0000000000"; + SMEM_WE <= "0000"; + SMEM_REQ <= '0'; + REG_READY <= '0'; + DATA_DEBUG <= X"00000000"; + + else + + case thread_state is + + when IDLE => + + REG_READY <= '0'; + ddr2_data_out_signal <= (others => '0'); + DDR2_DATA_IN <= (others => '0'); + DDR2_ADDRESS <= (others => '0'); + DDR2_READ_REQ <= '0'; + DDR2_WRITE_REQ <= '0'; + REG_READY <= '0'; + DATA_DEBUG <= (others => '0'); + if REG_GO = '1' then thread_state <= READ_A; + end if; + + when READ_A => + + DDR2_ADDRESS <= REG_DDR2_ADDRESS; + DDR2_READ_REQ <= '1'; + thread_state <= WAIT_RD_A; + + when WAIT_RD_A => + + if DDR2_RDY = '1' then + DDR2_READ_REQ <='0'; + ddr2_data_out_signal <= DDR2_DATA_OUT; + DATA_DEBUG <= DDR2_DATA_OUT; + thread_state <= WRITE_C; + end if; + + when WRITE_C => + + DDR2_ADDRESS <= REG_DDR2_ADDRESS; + DDR2_DATA_IN <= REG_DDR2_ADDRESS-x"C0000000"+x"0000009"; + DDR2_WRITE_REQ <= '1'; + thread_state <= WAIT_WR; + + when WAIT_WR => + + if DDR2_RDY = '1' then + DDR2_WRITE_REQ <= '0'; + thread_state <= READ_C; + end if; + + + when READ_C => + + DDR2_ADDRESS <= REG_DDR2_ADDRESS; + DDR2_READ_REQ <= '1'; + thread_state <= WAIT_RD_C; + + when WAIT_RD_C => + + if DDR2_RDY = '1' then + DDR2_READ_REQ <='0'; + ddr2_data_out_signal <= DDR2_DATA_OUT; + DATA_DEBUG <= DDR2_DATA_OUT; + thread_state <= DONE; + end if; + + when DONE => + + REG_READY <= '1'; + thread_state <= DONE; + + when others => null; + + end case; + + end if; + + end if; + + end process thread_sm; + +end thread_arch; diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/user_logic.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/user_logic.vhd index fd9f9b7..bc4d9aa 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/user_logic.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/user_logic.vhd @@ -213,26 +213,6 @@ architecture IMP of user_logic is --ACK_PROC --> genera los ack bis (para mantener la sincronización) --WR_REQ_PROC0, 1, 2 y 3 --> controla los wr req - COMPONENT thread - PORT( - clk : IN std_logic; - resetn : IN std_logic; - -- from/to memory controller - data_in_m : IN std_logic_vector(31 downto 0); - data_out_m : OUT std_logic_vector(31 downto 0); - address_m : OUT std_logic_vector(31 downto 0); - rd_req_m : OUT std_logic; - wr_req_m : OUT std_logic; - ack_m : IN std_logic; - -- from/to registers - go_r : IN std_logic; - ready_r : OUT std_logic; - address_a_r : IN std_logic_vector(31 downto 0); --- address_b_r : IN std_logic_vector(31 downto 0) - DATA_DEBUG : OUT std_logic_vector(31 downto 0) - ); - END COMPONENT; - COMPONENT controller PORT( @@ -418,6 +398,34 @@ architecture IMP of user_logic is END COMPONENT; + component thread + port ( + CLK : in std_logic; + RESETN : in std_logic; + DDR2_DATA_OUT : in std_logic_vector(31 downto 0); + DDR2_DATA_IN : out std_logic_vector(31 downto 0); + DDR2_ADDRESS : out std_logic_vector(31 downto 0); + DDR2_READ_REQ : out std_logic; + DDR2_WRITE_REQ : out std_logic; + DDR2_RDY : in std_logic; + SMEM_DO : in std_logic_vector(31 downto 0); + SMEM_IN : out std_logic_vector(31 downto 0); + SMEM_ADDR : out std_logic_vector(9 downto 0); + SMEM_WE : out std_logic_vector(3 downto 0); + SMEM_REQ : out std_logic; + SMEM_RDY : in std_logic; + REG_GO : in std_logic; + REG_READY : out std_logic; + REG_DDR2_ADDRESS : in std_logic_vector(31 downto 0); + REG_SMEM_DO : in std_logic_vector(31 downto 0); + REG_SMEM_DI : in std_logic_vector(31 downto 0); + REG_SMEM_ADDR_READ : in std_logic_vector(9 downto 0); + REG_SMEM_ADDR_WRITE : in std_logic_vector(9 downto 0); + DATA_DEBUG : out std_logic_vector(31 downto 0) + ); + end component; + + component smem port ( DO_0, DO_1, DO_2, DO_3 : out std_logic_vector(31 downto 0); @@ -559,6 +567,9 @@ architecture IMP of user_logic is signal smem_REQ_0, smem_REQ_1, smem_REQ_2, smem_REQ_3 : std_logic; signal smem_RDY_0, smem_RDY_1, smem_RDY_2, smem_RDY_3 : std_logic; + -- Registers signals + signal reg_do_0, reg_do_1, reg_do_2, reg_do_3 : std_logic_vector(31 downto 0); + -- Chipscope signals signal chipscope_probe_signal : std_logic_vector(255 downto 0); @@ -602,10 +613,10 @@ begin smem_TRIG_CLK <= TRIG_CLK; smem_RST <= RST; - DO_0 <= smem_DO_0; - DO_1 <= smem_DO_1; - DO_2 <= smem_DO_2; - DO_3 <= smem_DO_3; + DO_0 <= reg_do_0; + DO_1 <= reg_do_1; + DO_2 <= reg_do_2; + DO_3 <= reg_do_3; chipscope_probe <= chipscope_probe_signal; @@ -658,81 +669,110 @@ begin - -------------------------------------------------- - -- Threads instantiation + ------------------------------------------ + -- instantiate threads + ------------------------------------------ - thread0: thread PORT MAP ( - clk => Bus2IP_Clk, - resetn => Bus2IP_Resetn, - -- from/to memory controller - data_in_m => s_data_in_m0_bis, - data_out_m => s_data_out_m0, - address_m => s_address_m0, - rd_req_m => s_rd_req_m0_bis, - wr_req_m => s_wr_req_m0_bis, - ack_m => s_ack_t, - -- from/to registers - go_r => go, - ready_r => s_ready_r0, - address_a_r => address_in_0, - DATA_DEBUG => s_data_debug0 - ); + thread0: thread PORT MAP ( + CLK => Bus2IP_Clk, + RESETN => Bus2IP_Resetn, + DDR2_DATA_OUT => s_data_in_m0_bis, + DDR2_DATA_IN => s_data_out_m0, + DDR2_ADDRESS => s_address_m0, + DDR2_READ_REQ => s_rd_req_m0_bis, + DDR2_WRITE_REQ => s_wr_req_m0_bis, + DDR2_RDY => s_ack_t, + SMEM_DO => smem_DO_0, + SMEM_IN => smem_DI_0, + SMEM_ADDR => smem_ADDR_0, + SMEM_WE => smem_WE_0, + SMEM_REQ => smem_REQ_0, + SMEM_RDY => smem_RDY_0, + REG_GO => go, + REG_READY => s_ready_r0, + REG_DDR2_ADDRESS => address_in_0, + REG_SMEM_DO => reg_do_0, + REG_SMEM_DI => DI_0, + REG_SMEM_ADDR_READ => ADDR_0_R, + REG_SMEM_ADDR_WRITE => ADDR_0_W, + DATA_DEBUG => s_data_debug0 + ); - -------------------------------------------------- - thread1: thread PORT MAP ( - clk => Bus2IP_Clk, - resetn => Bus2IP_Resetn, - -- from/to memory controller - data_in_m => s_data_in_m1_bis, - data_out_m => s_data_out_m1, - address_m => s_address_m1, - rd_req_m => s_rd_req_m1_bis, - wr_req_m => s_wr_req_m1_bis, - ack_m => s_ack_t, - -- from/to registers - go_r => go, - ready_r => s_ready_r1, - address_a_r => address_in_1, - DATA_DEBUG => s_data_debug1 - ); + thread1: thread PORT MAP ( + CLK => Bus2IP_Clk, + RESETN => Bus2IP_Resetn, + DDR2_DATA_OUT => s_data_in_m1_bis, + DDR2_DATA_IN => s_data_out_m1, + DDR2_ADDRESS => s_address_m1, + DDR2_READ_REQ => s_rd_req_m1_bis, + DDR2_WRITE_REQ => s_wr_req_m1_bis, + DDR2_RDY => s_ack_t, + SMEM_DO => smem_DO_1, + SMEM_IN => smem_DI_1, + SMEM_ADDR => smem_ADDR_1, + SMEM_WE => smem_WE_1, + SMEM_REQ => smem_REQ_1, + SMEM_RDY => smem_RDY_1, + REG_GO => go, + REG_READY => s_ready_r1, + REG_DDR2_ADDRESS => address_in_1, + REG_SMEM_DO => reg_do_1, + REG_SMEM_DI => DI_1, + REG_SMEM_ADDR_READ => ADDR_1_R, + REG_SMEM_ADDR_WRITE => ADDR_1_W, + DATA_DEBUG => s_data_debug1 + ); - -------------------------------------------------- - thread2: thread PORT MAP ( - clk => Bus2IP_Clk, - resetn => Bus2IP_Resetn, - -- from/to memory controller - data_in_m => s_data_in_m2_bis, - data_out_m => s_data_out_m2, - address_m => s_address_m2, - rd_req_m => s_rd_req_m2_bis, - wr_req_m => s_wr_req_m2_bis, - ack_m => s_ack_t, - -- from/to registers - go_r => go, - ready_r => s_ready_r2, - address_a_r => address_in_2, - DATA_DEBUG => s_data_debug2 - ); + thread2: thread PORT MAP ( + CLK => Bus2IP_Clk, + RESETN => Bus2IP_Resetn, + DDR2_DATA_OUT => s_data_in_m2_bis, + DDR2_DATA_IN => s_data_out_m2, + DDR2_ADDRESS => s_address_m2, + DDR2_READ_REQ => s_rd_req_m2_bis, + DDR2_WRITE_REQ => s_wr_req_m2_bis, + DDR2_RDY => s_ack_t, + SMEM_DO => smem_DO_2, + SMEM_IN => smem_DI_2, + SMEM_ADDR => smem_ADDR_2, + SMEM_WE => smem_WE_2, + SMEM_REQ => smem_REQ_2, + SMEM_RDY => smem_RDY_2, + REG_GO => go, + REG_READY => s_ready_r2, + REG_DDR2_ADDRESS => address_in_2, + REG_SMEM_DO => reg_do_2, + REG_SMEM_DI => DI_2, + REG_SMEM_ADDR_READ => ADDR_2_R, + REG_SMEM_ADDR_WRITE => ADDR_2_W, + DATA_DEBUG => s_data_debug2 + ); - -------------------------------------------------- - thread3: thread PORT MAP ( - clk => Bus2IP_Clk, - resetn => Bus2IP_Resetn, - -- from/to memory controller - data_in_m => s_data_in_m3_bis, - data_out_m => s_data_out_m3, - address_m => s_address_m3, - rd_req_m => s_rd_req_m3_bis, - wr_req_m => s_wr_req_m3_bis, - ack_m => s_ack_t, - -- from/to registers - go_r => go, - ready_r => s_ready_r3, - address_a_r => address_in_3, - DATA_DEBUG => s_data_debug3 - ); + thread3: thread PORT MAP ( + CLK => Bus2IP_Clk, + RESETN => Bus2IP_Resetn, + DDR2_DATA_OUT => s_data_in_m3_bis, + DDR2_DATA_IN => s_data_out_m3, + DDR2_ADDRESS => s_address_m3, + DDR2_READ_REQ => s_rd_req_m3_bis, + DDR2_WRITE_REQ => s_wr_req_m3_bis, + DDR2_RDY => s_ack_t, + SMEM_DO => smem_DO_3, + SMEM_IN => smem_DI_3, + SMEM_ADDR => smem_ADDR_3, + SMEM_WE => smem_WE_3, + SMEM_REQ => smem_REQ_3, + SMEM_RDY => smem_RDY_3, + REG_GO => go, + REG_READY => s_ready_r3, + REG_DDR2_ADDRESS => address_in_3, + REG_SMEM_DO => reg_do_3, + REG_SMEM_DI => DI_3, + REG_SMEM_ADDR_READ => ADDR_3_R, + REG_SMEM_ADDR_WRITE => ADDR_3_W, + DATA_DEBUG => s_data_debug3 + ); - -------------------------------------------------- ------------------------------------------ From 1157786a97904a26915b842d5e93d8e26d040033 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Wed, 12 Sep 2012 19:54:02 +0200 Subject: [PATCH 04/18] Seems that no functionality has been broken with the shared memory integration --- src/sdk/main.c | 78 +++++++++----------------------------------------- 1 file changed, 13 insertions(+), 65 deletions(-) diff --git a/src/sdk/main.c b/src/sdk/main.c index eda72cb..82c177d 100644 --- a/src/sdk/main.c +++ b/src/sdk/main.c @@ -52,23 +52,15 @@ typedef volatile int32_t * pdata_32; #define DI_1 REG_DATA_32(11) #define DI_2 REG_DATA_32(12) #define DI_3 REG_DATA_32(13) -#define ADDR_0 REG_DATA_32(14) -#define ADDR_1 REG_DATA_32(15) -#define ADDR_2 REG_DATA_32(16) -#define ADDR_3 REG_DATA_32(17) -#define RST REG_DATA_32(18) -#define WE_0 REG_DATA_32(19) -#define WE_1 REG_DATA_32(20) -#define WE_2 REG_DATA_32(21) -#define WE_3 REG_DATA_32(22) -#define REQ_0 REG_DATA_32(23) -#define REQ_1 REG_DATA_32(24) -#define REQ_2 REG_DATA_32(25) -#define REQ_3 REG_DATA_32(26) -#define RDY_0 REG_DATA_32(27) -#define RDY_1 REG_DATA_32(28) -#define RDY_2 REG_DATA_32(29) -#define RDY_3 REG_DATA_32(30) +#define ADDR_0_W REG_DATA_32(14) +#define ADDR_1_W REG_DATA_32(15) +#define ADDR_2_W REG_DATA_32(16) +#define ADDR_3_W REG_DATA_32(17) +#define ADDR_0_R REG_DATA_32(18) +#define ADDR_1_R REG_DATA_32(19) +#define ADDR_2_R REG_DATA_32(20) +#define ADDR_3_R REG_DATA_32(21) +#define RST REG_DATA_32(22) // We need this header to avoid compiling errors... void xil_printf(const char *, ...); @@ -112,54 +104,10 @@ int main(void) xil_printf("Threads have finished!\n"); // Display DDR2 data once the threads have finished - //xil_printf("DDR2 data after the threads have finished:\n"); - //for (i = 0; i < 16; i++) xil_printf("%X => %d\n", &DDR2_DATA_32(i), DDR2_DATA_32(i)); - //for (i = 0; i < 16; i++) xil_printf("%X => %d\n", &DDR2_DATA_32(i+100), DDR2_DATA_32(i+100)); - - DI_0 = 0xAAAAAAAA; - DI_1 = 0xBBBBBBBB; - DI_2 = 0xCCCCCCCC; - DI_3 = 0xDDDDDDDD; - - ADDR_0 = 100; - ADDR_1 = 200; - ADDR_2 = 600; - ADDR_3 = 700; - - WE_0 = 0b1111; - WE_1 = 0b1111; - WE_2 = 0b1111; - WE_3 = 0b1111; - - REQ_0 = 1; - while (!RDY_0); - REQ_0 = 0; - REQ_1 = 1; - while (!RDY_1); - REQ_1 = 0; - REQ_2 = 1; - while (!RDY_2); - REQ_2 = 0; - REQ_3 = 1; - while (!RDY_3); - REQ_3 = 0; - - ADDR_0 = 700; - ADDR_1 = 600; - ADDR_2 = 200; - ADDR_3 = 100; - - REQ_0 = 1; - REQ_1 = 1; - REQ_2 = 1; - REQ_3 = 1; - - while (!RDY_3); - - xil_printf("Data read in port 0 => %x\n", DO_0); - xil_printf("Data read in port 1 => %x\n", DO_1); - xil_printf("Data read in port 2 => %x\n", DO_2); - xil_printf("Data read in port 3 => %x\n", DO_3); + xil_printf("DDR2 data after the threads have finished:\n"); + for (i = 0; i < 16; i++) xil_printf("%X => %d\n", &DDR2_DATA_32(i), DDR2_DATA_32(i)); + for (i = 0; i < 16; i++) xil_printf("%X => %d\n", &DDR2_DATA_32(i+100), DDR2_DATA_32(i+100)); + return 0; } From 838e8e30ac9233c10c6a9b6aaf1a05a203f69a2a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Fri, 14 Sep 2012 14:06:26 +0200 Subject: [PATCH 05/18] REG_SMEM_DO is an output port from the thread point of view --- hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd index 1e048fc..d017100 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/thread.vhd @@ -54,7 +54,7 @@ entity thread is REG_GO : in std_logic; REG_READY : out std_logic; REG_DDR2_ADDRESS : in std_logic_vector(31 downto 0); - REG_SMEM_DO : in std_logic_vector(31 downto 0); + REG_SMEM_DO : out std_logic_vector(31 downto 0); REG_SMEM_DI : in std_logic_vector(31 downto 0); REG_SMEM_ADDR_READ : in std_logic_vector(9 downto 0); REG_SMEM_ADDR_WRITE : in std_logic_vector(9 downto 0); From 6df3a253b8b0e292adc49cfd520521300cad5b9f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Mon, 17 Sep 2012 20:43:19 +0200 Subject: [PATCH 06/18] Towards non-sequential implementation --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 391 ++++++--------------- hw/tb/smem_tb.vhd | 281 +++------------ 2 files changed, 153 insertions(+), 519 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index dc4ec4b..f4d213b 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -82,29 +82,16 @@ architecture smem_arch of smem is -- bram_#_controller_we_[A|B] -- - signal k0_ready : std_logic := '1'; - signal k0_requested_bram : std_logic_vector(0 downto 0) := "0"; signal k0_output_sel : bit_vector(1 downto 0) := "00"; - - signal k1_ready : std_logic := '1'; - signal k1_requested_bram : std_logic_vector(0 downto 0) := "0"; signal k1_output_sel : bit_vector(1 downto 0) := "00"; - - signal k2_ready : std_logic := '1'; - signal k2_requested_bram : std_logic_vector(0 downto 0) := "0"; signal k2_output_sel : bit_vector(1 downto 0) := "00"; - - signal k3_ready : std_logic := '1'; - signal k3_requested_bram : std_logic_vector(0 downto 0) := "0"; signal k3_output_sel : bit_vector(1 downto 0) := "00"; - signal bram_0_A_input_sel : bit_vector(1 downto 0) := "00"; signal bram_0_B_input_sel : bit_vector(1 downto 0) := "00"; signal bram_1_A_input_sel : bit_vector(1 downto 0) := "00"; signal bram_1_B_input_sel : bit_vector(1 downto 0) := "00"; - signal do_0_a : std_logic_vector(31 downto 0) := X"00000000"; signal do_0_b : std_logic_vector(31 downto 0) := X"00000000"; signal di_0_a : std_logic_vector(31 downto 0) := X"00000000"; @@ -131,269 +118,118 @@ architecture smem_arch of smem is begin - -- TODO: decide if enable signals should always be set to 1 + -- TODO: decide if enable signals should always be set to 1... en_0_a <= '1'; en_0_b <= '1'; en_1_a <= '1'; en_1_b <= '1'; - k0_requested_bram <= ADDR_0(9 downto 9); - k1_requested_bram <= ADDR_1(9 downto 9); - k2_requested_bram <= ADDR_2(9 downto 9); - k3_requested_bram <= ADDR_3(9 downto 9); - - RDY_0 <= k0_ready; - RDY_1 <= k1_ready; - RDY_2 <= k2_ready; - RDY_3 <= k3_ready; - - - -- TODO: optimize code bellow for the mem_controller process - mem_controller : process (TRIG_CLK) - - variable bram_0_A_busy : std_logic := '0'; - variable bram_0_B_busy : std_logic := '0'; - variable bram_1_A_busy : std_logic := '0'; - variable bram_1_B_busy : std_logic := '0'; - - variable k0_duplicated : std_logic := '0'; - variable k1_duplicated : std_logic := '0'; - variable k2_duplicated : std_logic := '0'; - variable k3_duplicated : std_logic := '0'; - - variable k0_ready_var : std_logic; - variable k1_ready_var : std_logic; - variable k2_ready_var : std_logic; - variable k3_ready_var : std_logic; - - begin - - if (TRIG_CLK = '1') then - - k0_ready_var := k0_ready; - k1_ready_var := k1_ready; - k2_ready_var := k2_ready; - k3_ready_var := k3_ready; - - if (REQ_1 = '1' and REQ_0 = '1' and ADDR_1 = ADDR_0) then - k1_duplicated := '1'; - end if; - - if (REQ_2 = '1' and REQ_0 = '1' and ADDR_2 = ADDR_0) then - k2_duplicated := '1'; - end if; - - if (REQ_2 = '1' and REQ_1 = '1' and ADDR_2 = ADDR_1) then - k2_duplicated := '1'; - end if; - - if (REQ_3 = '1' and REQ_0 = '1' and ADDR_3 = ADDR_0) then - k3_duplicated := '1'; - end if; - - if (REQ_3 = '1' and REQ_1 = '1' and ADDR_3 = ADDR_1) then - k3_duplicated := '1'; - end if; - - if (REQ_3 = '1' and REQ_2 = '1' and ADDR_3 = ADDR_2) then - k3_duplicated := '1'; - end if; - - if (k0_requested_bram = "0" and REQ_0 = '1' and k0_duplicated = '0') then - - if (bram_0_A_busy = '0') then - bram_0_A_input_sel <= "00"; - k0_ready_var := '0'; - k0_output_sel <= "00"; - bram_0_A_busy := '1'; - elsif (bram_0_B_busy = '0') then - bram_0_B_input_sel <= "00"; - k0_ready_var := '0'; - k0_output_sel <= "01"; - bram_0_B_busy := '1'; - else - end if; - - end if; - - if (k1_requested_bram = "0" and REQ_1 = '1' and k1_duplicated = '0') then - - if (bram_0_A_busy = '0') then - bram_0_A_input_sel <= "01"; - k1_ready_var := '0'; - k1_output_sel <= "00"; - bram_0_A_busy := '1'; - elsif (bram_0_B_busy = '0') then - bram_0_B_input_sel <= "01"; - k1_ready_var := '0'; - k1_output_sel <= "01"; - bram_0_B_busy := '1'; - else - end if; - - end if; - - if (k2_requested_bram = "0" and REQ_2 = '1' and k2_duplicated = '0') then - - if (bram_0_A_busy = '0') then - bram_0_A_input_sel <= "10"; - k2_ready_var := '0'; - k2_output_sel <= "00"; - bram_0_A_busy := '1'; - elsif (bram_0_B_busy = '0') then - bram_0_B_input_sel <= "10"; - k2_ready_var := '0'; - k2_output_sel <= "01"; - bram_0_B_busy := '1'; - else - end if; - - end if; - - if (k3_requested_bram = "0" and REQ_3 = '1' and k3_duplicated = '0') then - - if (bram_0_A_busy = '0') then - bram_0_A_input_sel <= "11"; - k3_ready_var := '0'; - k3_output_sel <= "00"; - bram_0_A_busy := '1'; - elsif (bram_0_B_busy = '0') then - bram_0_B_input_sel <= "11"; - k3_ready_var := '0'; - k3_output_sel <= "01"; - bram_0_B_busy := '1'; - else - end if; - - end if; - - if (k0_requested_bram = "1" and REQ_0 = '1' and k0_duplicated = '0') then - - if (bram_1_A_busy = '0') then - bram_1_A_input_sel <= "00"; - k0_ready_var := '0'; - k0_output_sel <= "10"; - bram_1_A_busy := '1'; - elsif (bram_1_B_busy = '0') then - bram_1_B_input_sel <= "00"; - k0_ready_var := '0'; - k0_output_sel <= "11"; - bram_1_B_busy := '1'; - else - end if; - - end if; - - if (k1_requested_bram = "1" and REQ_1 = '1' and k1_duplicated = '0') then - - if (bram_1_A_busy = '0') then - bram_1_A_input_sel <= "01"; - k1_ready_var := '0'; - k1_output_sel <= "10"; - bram_1_A_busy := '1'; - elsif (bram_1_B_busy = '0') then - bram_1_B_input_sel <= "01"; - k1_ready_var := '0'; - k1_output_sel <= "11"; - bram_1_B_busy := '1'; - else - end if; - - end if; - - if (k2_requested_bram = "1" and REQ_2 = '1' and k2_duplicated = '0') then - - if (bram_1_A_busy = '0') then - bram_1_A_input_sel <= "10"; - k2_ready_var := '0'; - k2_output_sel <= "10"; - bram_1_A_busy := '1'; - elsif (bram_1_B_busy = '0') then - bram_1_B_input_sel <= "10"; - k2_ready_var := '0'; - k2_output_sel <= "11"; - bram_1_B_busy := '1'; - else - end if; - - end if; - - if (k3_requested_bram = "1" and REQ_3 = '1' and k3_duplicated = '0') then - - if (bram_1_A_busy = '0') then - bram_1_A_input_sel <= "11"; - k3_ready_var := '0'; - k3_output_sel <= "10"; - bram_1_A_busy := '1'; - elsif (bram_1_B_busy = '0') then - bram_1_B_input_sel <= "11"; - k3_ready_var := '0'; - k3_output_sel <= "11"; - bram_1_B_busy := '1'; - else - end if; - - end if; - - if (REQ_1 = '1' and REQ_0 = '1' and ADDR_1 = ADDR_0) then - k1_ready_var := k0_ready_var; - k1_output_sel <= k0_output_sel; - end if; - - if (REQ_2 = '1' and REQ_0 = '1' and ADDR_2 = ADDR_0) then - k2_ready_var := k0_ready_var; - k2_output_sel <= k0_output_sel; - end if; - - if (REQ_2 = '1' and REQ_1 = '1' and ADDR_2 = ADDR_1) then - k2_ready_var := k1_ready_var; - k2_output_sel <= k1_output_sel; - end if; - - if (REQ_3 = '1' and REQ_0 = '1' and ADDR_3 = ADDR_0) then - k3_ready_var := k0_ready_var; - k3_output_sel <= k0_output_sel; - end if; - - if (REQ_3 = '1' and REQ_1 = '1' and ADDR_3 = ADDR_1) then - k3_ready_var := k1_ready_var; - k3_output_sel <= k1_output_sel; - end if; - - if (REQ_3 = '1' and REQ_2 = '1' and ADDR_3 = ADDR_2) then - k3_ready_var := k2_ready_var; - k3_output_sel <= k2_output_sel; - end if; - - k0_ready <= k0_ready_var; - k1_ready <= k1_ready_var; - k2_ready <= k2_ready_var; - k3_ready <= k3_ready_var; - - else - - if (k0_ready = '0') then k0_ready <= '1'; end if; - if (k1_ready = '0') then k1_ready <= '1'; end if; - if (k2_ready = '0') then k2_ready <= '1'; end if; - if (k3_ready = '0') then k3_ready <= '1'; end if; - - bram_0_A_busy := '0'; - bram_0_B_busy := '0'; - bram_1_A_busy := '0'; - bram_1_B_busy := '0'; - - k0_duplicated := '0'; - k1_duplicated := '0'; - k2_duplicated := '0'; - k3_duplicated := '0'; - - end if; - - end process mem_controller; - - - -- TODO: decide if a process implementation should be used instead of - -- this block implementation bellow: + + -- TODO: implement a decent input and output controller block + bram_0_A_input_sel <= "00"; + bram_0_B_input_sel <= "01"; + bram_1_A_input_sel <= "10"; + bram_1_B_input_sel <= "11"; + + + -- + -- The higher bits of the output selection signal represent the BRAM + -- which may be being used and, therefore, are the higher input port + -- address bits. + -- + k0_output_sel(1 downto 1) <= to_bitvector(ADDR_0(9 downto 9)); + k1_output_sel(1 downto 1) <= to_bitvector(ADDR_1(9 downto 9)); + k2_output_sel(1 downto 1) <= to_bitvector(ADDR_2(9 downto 9)); + k3_output_sel(1 downto 1) <= to_bitvector(ADDR_3(9 downto 9)); + + + -- + -- The lower bit of the output selection signal represent the BRAM + -- port that may be being used: + -- + -- kX_output_sel(0) = (ADDR_0(8 downto 0) == addr_0_b) or (ADDR_0(8 downto 0) == addr_1_b) + -- + k0_output_sel(0) <= ( ( to_bit(ADDR_0(0)) xnor to_bit(addr_0_b(0)) ) and + ( to_bit(ADDR_0(1)) xnor to_bit(addr_0_b(1)) ) and + ( to_bit(ADDR_0(2)) xnor to_bit(addr_0_b(2)) ) and + ( to_bit(ADDR_0(3)) xnor to_bit(addr_0_b(3)) ) and + ( to_bit(ADDR_0(4)) xnor to_bit(addr_0_b(4)) ) and + ( to_bit(ADDR_0(5)) xnor to_bit(addr_0_b(5)) ) and + ( to_bit(ADDR_0(6)) xnor to_bit(addr_0_b(6)) ) and + ( to_bit(ADDR_0(7)) xnor to_bit(addr_0_b(7)) ) and + ( to_bit(ADDR_0(8)) xnor to_bit(addr_0_b(8)) ) ) + or + ( ( to_bit(ADDR_0(0)) xnor to_bit(addr_1_b(0)) ) and + ( to_bit(ADDR_0(1)) xnor to_bit(addr_1_b(1)) ) and + ( to_bit(ADDR_0(2)) xnor to_bit(addr_1_b(2)) ) and + ( to_bit(ADDR_0(3)) xnor to_bit(addr_1_b(3)) ) and + ( to_bit(ADDR_0(4)) xnor to_bit(addr_1_b(4)) ) and + ( to_bit(ADDR_0(5)) xnor to_bit(addr_1_b(5)) ) and + ( to_bit(ADDR_0(6)) xnor to_bit(addr_1_b(6)) ) and + ( to_bit(ADDR_0(7)) xnor to_bit(addr_1_b(7)) ) and + ( to_bit(ADDR_0(8)) xnor to_bit(addr_1_b(8)) ) ); + + k1_output_sel(0) <= ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_0_b(0)) ) and + ( to_bit(ADDR_1(1)) xnor to_bit(addr_0_b(1)) ) and + ( to_bit(ADDR_1(2)) xnor to_bit(addr_0_b(2)) ) and + ( to_bit(ADDR_1(3)) xnor to_bit(addr_0_b(3)) ) and + ( to_bit(ADDR_1(4)) xnor to_bit(addr_0_b(4)) ) and + ( to_bit(ADDR_1(5)) xnor to_bit(addr_0_b(5)) ) and + ( to_bit(ADDR_1(6)) xnor to_bit(addr_0_b(6)) ) and + ( to_bit(ADDR_1(7)) xnor to_bit(addr_0_b(7)) ) and + ( to_bit(ADDR_1(8)) xnor to_bit(addr_0_b(8)) ) ) + or + ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_1_b(0)) ) and + ( to_bit(ADDR_1(1)) xnor to_bit(addr_1_b(1)) ) and + ( to_bit(ADDR_1(2)) xnor to_bit(addr_1_b(2)) ) and + ( to_bit(ADDR_1(3)) xnor to_bit(addr_1_b(3)) ) and + ( to_bit(ADDR_1(4)) xnor to_bit(addr_1_b(4)) ) and + ( to_bit(ADDR_1(5)) xnor to_bit(addr_1_b(5)) ) and + ( to_bit(ADDR_1(6)) xnor to_bit(addr_1_b(6)) ) and + ( to_bit(ADDR_1(7)) xnor to_bit(addr_1_b(7)) ) and + ( to_bit(ADDR_1(8)) xnor to_bit(addr_1_b(8)) ) ); + + k2_output_sel(0) <= ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_0_b(0)) ) and + ( to_bit(ADDR_1(1)) xnor to_bit(addr_0_b(1)) ) and + ( to_bit(ADDR_1(2)) xnor to_bit(addr_0_b(2)) ) and + ( to_bit(ADDR_1(3)) xnor to_bit(addr_0_b(3)) ) and + ( to_bit(ADDR_1(4)) xnor to_bit(addr_0_b(4)) ) and + ( to_bit(ADDR_1(5)) xnor to_bit(addr_0_b(5)) ) and + ( to_bit(ADDR_1(6)) xnor to_bit(addr_0_b(6)) ) and + ( to_bit(ADDR_1(7)) xnor to_bit(addr_0_b(7)) ) and + ( to_bit(ADDR_1(8)) xnor to_bit(addr_0_b(8)) ) ) + or + ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_1_b(0)) ) and + ( to_bit(ADDR_1(1)) xnor to_bit(addr_1_b(1)) ) and + ( to_bit(ADDR_1(2)) xnor to_bit(addr_1_b(2)) ) and + ( to_bit(ADDR_1(3)) xnor to_bit(addr_1_b(3)) ) and + ( to_bit(ADDR_1(4)) xnor to_bit(addr_1_b(4)) ) and + ( to_bit(ADDR_1(5)) xnor to_bit(addr_1_b(5)) ) and + ( to_bit(ADDR_1(6)) xnor to_bit(addr_1_b(6)) ) and + ( to_bit(ADDR_1(7)) xnor to_bit(addr_1_b(7)) ) and + ( to_bit(ADDR_1(8)) xnor to_bit(addr_1_b(8)) ) ); + + k3_output_sel(0) <= ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_0_b(0)) ) and + ( to_bit(ADDR_1(1)) xnor to_bit(addr_0_b(1)) ) and + ( to_bit(ADDR_1(2)) xnor to_bit(addr_0_b(2)) ) and + ( to_bit(ADDR_1(3)) xnor to_bit(addr_0_b(3)) ) and + ( to_bit(ADDR_1(4)) xnor to_bit(addr_0_b(4)) ) and + ( to_bit(ADDR_1(5)) xnor to_bit(addr_0_b(5)) ) and + ( to_bit(ADDR_1(6)) xnor to_bit(addr_0_b(6)) ) and + ( to_bit(ADDR_1(7)) xnor to_bit(addr_0_b(7)) ) and + ( to_bit(ADDR_1(8)) xnor to_bit(addr_0_b(8)) ) ) + or + ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_1_b(0)) ) and + ( to_bit(ADDR_1(1)) xnor to_bit(addr_1_b(1)) ) and + ( to_bit(ADDR_1(2)) xnor to_bit(addr_1_b(2)) ) and + ( to_bit(ADDR_1(3)) xnor to_bit(addr_1_b(3)) ) and + ( to_bit(ADDR_1(4)) xnor to_bit(addr_1_b(4)) ) and + ( to_bit(ADDR_1(5)) xnor to_bit(addr_1_b(5)) ) and + ( to_bit(ADDR_1(6)) xnor to_bit(addr_1_b(6)) ) and + ( to_bit(ADDR_1(7)) xnor to_bit(addr_1_b(7)) ) and + ( to_bit(ADDR_1(8)) xnor to_bit(addr_1_b(8)) ) ); + + input_controller_0 : block begin with bram_0_A_input_sel select di_0_a <= DI_0 when "00", @@ -467,18 +303,6 @@ begin end block input_controller_3; - -- TODO: decide if the block implementation for the output controllers - -- should be replaced by this process implementation: - -- - --output_controller_0 : process (TRIG_CLK) begin - -- case k0_output_sel is - -- when "00" => DO_0 <= do_0_a; - -- when "01" => DO_0 <= do_0_b; - -- when "10" => DO_0 <= do_1_a; - -- when "11" => DO_0 <= do_1_b; - -- end case; - --end process output_controller_0; - -- output_controller_0 : block begin with k0_output_sel select DO_0 <= do_0_a when "00", @@ -656,6 +480,7 @@ begin ); + RAMB16BWER_1 : RAMB16BWER generic map ( diff --git a/hw/tb/smem_tb.vhd b/hw/tb/smem_tb.vhd index 554635d..c451a5a 100644 --- a/hw/tb/smem_tb.vhd +++ b/hw/tb/smem_tb.vhd @@ -37,6 +37,18 @@ end smem_tb; architecture smem_tb_arch of smem_tb is + type state_t is ( + + IDLE, + SMEM_WRITE, + WAIT_SMEM_WRITE, + FOO, + SMEM_READ, + WAIT_SMEM_READ, + DONE + + ); + component smem port ( @@ -61,7 +73,9 @@ architecture smem_tb_arch of smem_tb is signal BRAM_CLK, TRIG_CLK, RST : std_logic := '0'; signal REQ_0, REQ_1, REQ_2, REQ_3 : std_logic := '0'; signal RDY_0, RDY_1, RDY_2, RDY_3 : std_logic := '0'; - signal test_bench_state : std_logic_vector(1 downto 0) := "00"; + signal start_test_bench : std_logic := '0'; + + signal kernel_state : state_t; begin @@ -130,266 +144,61 @@ begin wait for 100 ns; -- Wait until global set/reset completes - test_bench_state <= "01"; - - wait for 50 ns; - - test_bench_state <= "10"; - - wait for 20 ns; - - test_bench_state <= "11"; + start_test_bench <= '1'; end process test_bench; - thread_0 : process begin - - wait until test_bench_state = "01"; - - DI_0 <= x"AAAAAAAA"; - ADDR_0 <= "1000000000"; - WE_0 <= "1111"; - REQ_0 <= '1'; - - wait until RDY_0 = '0'; + thread_0 : process (TRIG_CLK) - REQ_0 <= '0'; + begin - wait until RDY_0 = '1'; + if (TRIG_CLK'event and TRIG_CLK = '1') then - WE_0 <= "0000"; - REQ_0 <= '1'; + case kernel_state is - wait until RDY_0 = '0'; + when IDLE => - REQ_0 <= '0'; + if start_test_bench = '1' then + kernel_state <= SMEM_WRITE; + end if; - wait until RDY_0 = '1'; + when SMEM_WRITE => - wait until test_bench_state = "10"; + DI_0 <= x"AAAAAAAA"; + ADDR_0 <= "0000000000"; + WE_0 <= "1111"; + REQ_0 <= '1'; + kernel_state <= WAIT_SMEM_WRITE; - ADDR_0 <= "1000000000"; - WE_0 <= "0000"; - REQ_0 <= '1'; + when WAIT_SMEM_WRITE => - wait until RDY_0 = '0'; + if (RDY_0 = '1') then + REQ_0 <= '0'; + kernel_state <= FOO; + end if; - REQ_0 <= '0'; + when FOO => - wait until RDY_0 = '1'; + kernel_state <= SMEM_READ; - wait until test_bench_state = "11"; + when SMEM_READ => - DI_0 <= x"11111111"; - ADDR_0 <= "0000000000"; - WE_0 <= "1111"; - REQ_0 <= '1'; + null; - wait until RDY_0 = '0'; + when WAIT_SMEM_READ => - REQ_0 <= '0'; + null; - wait until RDY_0 = '1'; + when DONE => - WE_0 <= "0000"; - REQ_0 <= '1'; + null; - wait until RDY_0 = '0'; + end case; - REQ_0 <= '0'; - - wait until RDY_0 = '1'; - - wait; + end if; end process thread_0; - thread_1 : process begin - - wait until test_bench_state = "01"; - - DI_1 <= x"BBBBBBBB"; - ADDR_1 <= "1000000001"; - WE_1 <= "1111"; - REQ_1 <= '1'; - - wait until RDY_1 = '0'; - - REQ_1 <= '0'; - - wait until RDY_1 = '1'; - - WE_1 <= "0000"; - REQ_1 <= '1'; - - wait until RDY_1 = '0'; - - REQ_1 <= '0'; - - wait until RDY_1 = '1'; - - wait until test_bench_state = "10"; - - ADDR_1 <= "1000000000"; - WE_1 <= "0000"; - REQ_1 <= '1'; - - wait until RDY_1 = '0'; - - REQ_1 <= '0'; - - wait until RDY_1 = '1'; - - wait until test_bench_state = "11"; - - DI_1 <= x"22222222"; - ADDR_1 <= "0000000001"; - WE_1 <= "1111"; - REQ_1 <= '1'; - - wait until RDY_1 = '0'; - - REQ_1 <= '0'; - - wait until RDY_1 = '1'; - - WE_1 <= "0000"; - REQ_1 <= '1'; - - wait until RDY_1 = '0'; - - REQ_1 <= '0'; - - wait until RDY_1 = '1'; - - wait; - - end process thread_1; - - thread_2 : process begin - - wait until test_bench_state = "01"; - - DI_2 <= x"CCCCCCCC"; - ADDR_2 <= "1000000010"; - WE_2 <= "1111"; - REQ_2 <= '1'; - - wait until RDY_2 = '0'; - - REQ_2 <= '0'; - - wait until RDY_2 = '1'; - - WE_2 <= "0000"; - REQ_2 <= '1'; - - wait until RDY_2 = '0'; - - REQ_2 <= '0'; - - wait until RDY_2 = '1'; - - wait until test_bench_state = "10"; - - ADDR_2 <= "1000000000"; - WE_2 <= "0000"; - REQ_2 <= '1'; - - wait until RDY_2 = '0'; - - REQ_2 <= '0'; - - wait until RDY_2 = '1'; - - wait until test_bench_state = "11"; - - DI_2 <= x"33333333"; - ADDR_2 <= "1000000000"; - WE_2 <= "1111"; - REQ_2 <= '1'; - - wait until RDY_2 = '0'; - - REQ_2 <= '0'; - - wait until RDY_2 = '1'; - - WE_2 <= "0000"; - REQ_2 <= '1'; - - wait until RDY_2 = '0'; - - REQ_2 <= '0'; - - wait until RDY_2 = '1'; - - wait; - - end process thread_2; - - thread_3 : process begin - - wait until test_bench_state = "01"; - - DI_3 <= x"DDDDDDDD"; - ADDR_3 <= "1000000011"; - WE_3 <= "1111"; - REQ_3 <= '1'; - - wait until RDY_3 = '0'; - - REQ_3 <= '0'; - - wait until RDY_3 = '1'; - - WE_3 <= "0000"; - REQ_3 <= '1'; - - wait until RDY_3 = '0'; - - REQ_3 <= '0'; - - wait until RDY_3 = '1'; - - wait until test_bench_state = "10"; - - ADDR_3 <= "1000000000"; - WE_3 <= "0000"; - REQ_3 <= '1'; - - wait until RDY_3 = '0'; - - REQ_3 <= '0'; - - wait until RDY_3 = '1'; - - wait until test_bench_state = "11"; - - DI_3 <= x"44444444"; - ADDR_3 <= "1000000001"; - WE_3 <= "1111"; - REQ_3 <= '1'; - - wait until RDY_3 = '0'; - - REQ_3 <= '0'; - - wait until RDY_3 = '1'; - - WE_3 <= "0000"; - REQ_3 <= '1'; - - wait until RDY_3 = '0'; - - REQ_3 <= '0'; - - wait until RDY_3 = '1'; - - wait; - - end process thread_3; - end smem_tb_arch; From 54c5f05569eb578d440c089c9e57e7497ae2e3d4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Tue, 18 Sep 2012 12:44:05 +0200 Subject: [PATCH 07/18] Fixed kX_output_sel(0) assignment --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 74 +++++++++++----------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index f4d213b..f965dcd 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -189,45 +189,45 @@ begin ( to_bit(ADDR_1(7)) xnor to_bit(addr_1_b(7)) ) and ( to_bit(ADDR_1(8)) xnor to_bit(addr_1_b(8)) ) ); - k2_output_sel(0) <= ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_0_b(0)) ) and - ( to_bit(ADDR_1(1)) xnor to_bit(addr_0_b(1)) ) and - ( to_bit(ADDR_1(2)) xnor to_bit(addr_0_b(2)) ) and - ( to_bit(ADDR_1(3)) xnor to_bit(addr_0_b(3)) ) and - ( to_bit(ADDR_1(4)) xnor to_bit(addr_0_b(4)) ) and - ( to_bit(ADDR_1(5)) xnor to_bit(addr_0_b(5)) ) and - ( to_bit(ADDR_1(6)) xnor to_bit(addr_0_b(6)) ) and - ( to_bit(ADDR_1(7)) xnor to_bit(addr_0_b(7)) ) and - ( to_bit(ADDR_1(8)) xnor to_bit(addr_0_b(8)) ) ) + k2_output_sel(0) <= ( ( to_bit(ADDR_2(0)) xnor to_bit(addr_0_b(0)) ) and + ( to_bit(ADDR_2(1)) xnor to_bit(addr_0_b(1)) ) and + ( to_bit(ADDR_2(2)) xnor to_bit(addr_0_b(2)) ) and + ( to_bit(ADDR_2(3)) xnor to_bit(addr_0_b(3)) ) and + ( to_bit(ADDR_2(4)) xnor to_bit(addr_0_b(4)) ) and + ( to_bit(ADDR_2(5)) xnor to_bit(addr_0_b(5)) ) and + ( to_bit(ADDR_2(6)) xnor to_bit(addr_0_b(6)) ) and + ( to_bit(ADDR_2(7)) xnor to_bit(addr_0_b(7)) ) and + ( to_bit(ADDR_2(8)) xnor to_bit(addr_0_b(8)) ) ) or - ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_1_b(0)) ) and - ( to_bit(ADDR_1(1)) xnor to_bit(addr_1_b(1)) ) and - ( to_bit(ADDR_1(2)) xnor to_bit(addr_1_b(2)) ) and - ( to_bit(ADDR_1(3)) xnor to_bit(addr_1_b(3)) ) and - ( to_bit(ADDR_1(4)) xnor to_bit(addr_1_b(4)) ) and - ( to_bit(ADDR_1(5)) xnor to_bit(addr_1_b(5)) ) and - ( to_bit(ADDR_1(6)) xnor to_bit(addr_1_b(6)) ) and - ( to_bit(ADDR_1(7)) xnor to_bit(addr_1_b(7)) ) and - ( to_bit(ADDR_1(8)) xnor to_bit(addr_1_b(8)) ) ); - - k3_output_sel(0) <= ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_0_b(0)) ) and - ( to_bit(ADDR_1(1)) xnor to_bit(addr_0_b(1)) ) and - ( to_bit(ADDR_1(2)) xnor to_bit(addr_0_b(2)) ) and - ( to_bit(ADDR_1(3)) xnor to_bit(addr_0_b(3)) ) and - ( to_bit(ADDR_1(4)) xnor to_bit(addr_0_b(4)) ) and - ( to_bit(ADDR_1(5)) xnor to_bit(addr_0_b(5)) ) and - ( to_bit(ADDR_1(6)) xnor to_bit(addr_0_b(6)) ) and - ( to_bit(ADDR_1(7)) xnor to_bit(addr_0_b(7)) ) and - ( to_bit(ADDR_1(8)) xnor to_bit(addr_0_b(8)) ) ) + ( ( to_bit(ADDR_2(0)) xnor to_bit(addr_1_b(0)) ) and + ( to_bit(ADDR_2(1)) xnor to_bit(addr_1_b(1)) ) and + ( to_bit(ADDR_2(2)) xnor to_bit(addr_1_b(2)) ) and + ( to_bit(ADDR_2(3)) xnor to_bit(addr_1_b(3)) ) and + ( to_bit(ADDR_2(4)) xnor to_bit(addr_1_b(4)) ) and + ( to_bit(ADDR_2(5)) xnor to_bit(addr_1_b(5)) ) and + ( to_bit(ADDR_2(6)) xnor to_bit(addr_1_b(6)) ) and + ( to_bit(ADDR_2(7)) xnor to_bit(addr_1_b(7)) ) and + ( to_bit(ADDR_2(8)) xnor to_bit(addr_1_b(8)) ) ); + + k3_output_sel(0) <= ( ( to_bit(ADDR_3(0)) xnor to_bit(addr_0_b(0)) ) and + ( to_bit(ADDR_3(1)) xnor to_bit(addr_0_b(1)) ) and + ( to_bit(ADDR_3(2)) xnor to_bit(addr_0_b(2)) ) and + ( to_bit(ADDR_3(3)) xnor to_bit(addr_0_b(3)) ) and + ( to_bit(ADDR_3(4)) xnor to_bit(addr_0_b(4)) ) and + ( to_bit(ADDR_3(5)) xnor to_bit(addr_0_b(5)) ) and + ( to_bit(ADDR_3(6)) xnor to_bit(addr_0_b(6)) ) and + ( to_bit(ADDR_3(7)) xnor to_bit(addr_0_b(7)) ) and + ( to_bit(ADDR_3(8)) xnor to_bit(addr_0_b(8)) ) ) or - ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_1_b(0)) ) and - ( to_bit(ADDR_1(1)) xnor to_bit(addr_1_b(1)) ) and - ( to_bit(ADDR_1(2)) xnor to_bit(addr_1_b(2)) ) and - ( to_bit(ADDR_1(3)) xnor to_bit(addr_1_b(3)) ) and - ( to_bit(ADDR_1(4)) xnor to_bit(addr_1_b(4)) ) and - ( to_bit(ADDR_1(5)) xnor to_bit(addr_1_b(5)) ) and - ( to_bit(ADDR_1(6)) xnor to_bit(addr_1_b(6)) ) and - ( to_bit(ADDR_1(7)) xnor to_bit(addr_1_b(7)) ) and - ( to_bit(ADDR_1(8)) xnor to_bit(addr_1_b(8)) ) ); + ( ( to_bit(ADDR_3(0)) xnor to_bit(addr_1_b(0)) ) and + ( to_bit(ADDR_3(1)) xnor to_bit(addr_1_b(1)) ) and + ( to_bit(ADDR_3(2)) xnor to_bit(addr_1_b(2)) ) and + ( to_bit(ADDR_3(3)) xnor to_bit(addr_1_b(3)) ) and + ( to_bit(ADDR_3(4)) xnor to_bit(addr_1_b(4)) ) and + ( to_bit(ADDR_3(5)) xnor to_bit(addr_1_b(5)) ) and + ( to_bit(ADDR_3(6)) xnor to_bit(addr_1_b(6)) ) and + ( to_bit(ADDR_3(7)) xnor to_bit(addr_1_b(7)) ) and + ( to_bit(ADDR_3(8)) xnor to_bit(addr_1_b(8)) ) ); input_controller_0 : block begin From 22bcceb69e9802108e95c603c746964a44eac6c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Tue, 18 Sep 2012 15:37:07 +0200 Subject: [PATCH 08/18] Added kX_being_served signals --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 26 ++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index f965dcd..c47659c 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -87,6 +87,11 @@ architecture smem_arch of smem is signal k2_output_sel : bit_vector(1 downto 0) := "00"; signal k3_output_sel : bit_vector(1 downto 0) := "00"; + signal k0_being_served : bit := '0'; + signal k1_being_served : bit := '0'; + signal k2_being_served : bit := '0'; + signal k3_being_served : bit := '0'; + signal bram_0_A_input_sel : bit_vector(1 downto 0) := "00"; signal bram_0_B_input_sel : bit_vector(1 downto 0) := "00"; signal bram_1_A_input_sel : bit_vector(1 downto 0) := "00"; @@ -132,6 +137,27 @@ begin bram_1_B_input_sel <= "11"; + k0_being_served <= REQ_0 and ( (not bram_0_A_input_sel(1) and not bram_0_A_input_sel(0)) or + (not bram_0_B_input_sel(1) and not bram_0_B_input_sel(0)) or + (not bram_1_A_input_sel(1) and not bram_1_A_input_sel(0)) or + (not bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ); + + k1_being_served <= REQ_1 and ( (not bram_0_A_input_sel(1) and bram_0_A_input_sel(0)) or + (not bram_0_B_input_sel(1) and bram_0_B_input_sel(0)) or + (not bram_1_A_input_sel(1) and bram_1_A_input_sel(0)) or + (not bram_1_B_input_sel(1) and bram_1_B_input_sel(0)) ); + + k2_being_served <= REQ_2 and ( ( bram_0_A_input_sel(1) and not bram_0_A_input_sel(0)) or + ( bram_0_B_input_sel(1) and not bram_0_B_input_sel(0)) or + ( bram_1_A_input_sel(1) and not bram_1_A_input_sel(0)) or + ( bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ); + + k3_being_served <= REQ_3 and ( ( bram_0_A_input_sel(1) and bram_0_A_input_sel(0)) or + ( bram_0_B_input_sel(1) and bram_0_B_input_sel(0)) or + ( bram_1_A_input_sel(1) and bram_1_A_input_sel(0)) or + ( bram_1_B_input_sel(1) and bram_1_B_input_sel(0)) ); + + -- -- The higher bits of the output selection signal represent the BRAM -- which may be being used and, therefore, are the higher input port From e6780d50e6c54bf85d62bc55fb79b6f0fb28ec01 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Tue, 18 Sep 2012 20:24:59 +0200 Subject: [PATCH 09/18] Optimized kX_output_sel(0) signals --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 96 ++++------------------ 1 file changed, 14 insertions(+), 82 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index c47659c..2221dbb 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -171,89 +171,21 @@ begin -- -- The lower bit of the output selection signal represent the BRAM - -- port that may be being used: + -- port that may be being used. For each BRAM (kX_output_sel(1)), we + -- see if the kernel is connected to port B (if not, then we suppose + -- port A: -- - -- kX_output_sel(0) = (ADDR_0(8 downto 0) == addr_0_b) or (ADDR_0(8 downto 0) == addr_1_b) - -- - k0_output_sel(0) <= ( ( to_bit(ADDR_0(0)) xnor to_bit(addr_0_b(0)) ) and - ( to_bit(ADDR_0(1)) xnor to_bit(addr_0_b(1)) ) and - ( to_bit(ADDR_0(2)) xnor to_bit(addr_0_b(2)) ) and - ( to_bit(ADDR_0(3)) xnor to_bit(addr_0_b(3)) ) and - ( to_bit(ADDR_0(4)) xnor to_bit(addr_0_b(4)) ) and - ( to_bit(ADDR_0(5)) xnor to_bit(addr_0_b(5)) ) and - ( to_bit(ADDR_0(6)) xnor to_bit(addr_0_b(6)) ) and - ( to_bit(ADDR_0(7)) xnor to_bit(addr_0_b(7)) ) and - ( to_bit(ADDR_0(8)) xnor to_bit(addr_0_b(8)) ) ) - or - ( ( to_bit(ADDR_0(0)) xnor to_bit(addr_1_b(0)) ) and - ( to_bit(ADDR_0(1)) xnor to_bit(addr_1_b(1)) ) and - ( to_bit(ADDR_0(2)) xnor to_bit(addr_1_b(2)) ) and - ( to_bit(ADDR_0(3)) xnor to_bit(addr_1_b(3)) ) and - ( to_bit(ADDR_0(4)) xnor to_bit(addr_1_b(4)) ) and - ( to_bit(ADDR_0(5)) xnor to_bit(addr_1_b(5)) ) and - ( to_bit(ADDR_0(6)) xnor to_bit(addr_1_b(6)) ) and - ( to_bit(ADDR_0(7)) xnor to_bit(addr_1_b(7)) ) and - ( to_bit(ADDR_0(8)) xnor to_bit(addr_1_b(8)) ) ); - - k1_output_sel(0) <= ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_0_b(0)) ) and - ( to_bit(ADDR_1(1)) xnor to_bit(addr_0_b(1)) ) and - ( to_bit(ADDR_1(2)) xnor to_bit(addr_0_b(2)) ) and - ( to_bit(ADDR_1(3)) xnor to_bit(addr_0_b(3)) ) and - ( to_bit(ADDR_1(4)) xnor to_bit(addr_0_b(4)) ) and - ( to_bit(ADDR_1(5)) xnor to_bit(addr_0_b(5)) ) and - ( to_bit(ADDR_1(6)) xnor to_bit(addr_0_b(6)) ) and - ( to_bit(ADDR_1(7)) xnor to_bit(addr_0_b(7)) ) and - ( to_bit(ADDR_1(8)) xnor to_bit(addr_0_b(8)) ) ) - or - ( ( to_bit(ADDR_1(0)) xnor to_bit(addr_1_b(0)) ) and - ( to_bit(ADDR_1(1)) xnor to_bit(addr_1_b(1)) ) and - ( to_bit(ADDR_1(2)) xnor to_bit(addr_1_b(2)) ) and - ( to_bit(ADDR_1(3)) xnor to_bit(addr_1_b(3)) ) and - ( to_bit(ADDR_1(4)) xnor to_bit(addr_1_b(4)) ) and - ( to_bit(ADDR_1(5)) xnor to_bit(addr_1_b(5)) ) and - ( to_bit(ADDR_1(6)) xnor to_bit(addr_1_b(6)) ) and - ( to_bit(ADDR_1(7)) xnor to_bit(addr_1_b(7)) ) and - ( to_bit(ADDR_1(8)) xnor to_bit(addr_1_b(8)) ) ); - - k2_output_sel(0) <= ( ( to_bit(ADDR_2(0)) xnor to_bit(addr_0_b(0)) ) and - ( to_bit(ADDR_2(1)) xnor to_bit(addr_0_b(1)) ) and - ( to_bit(ADDR_2(2)) xnor to_bit(addr_0_b(2)) ) and - ( to_bit(ADDR_2(3)) xnor to_bit(addr_0_b(3)) ) and - ( to_bit(ADDR_2(4)) xnor to_bit(addr_0_b(4)) ) and - ( to_bit(ADDR_2(5)) xnor to_bit(addr_0_b(5)) ) and - ( to_bit(ADDR_2(6)) xnor to_bit(addr_0_b(6)) ) and - ( to_bit(ADDR_2(7)) xnor to_bit(addr_0_b(7)) ) and - ( to_bit(ADDR_2(8)) xnor to_bit(addr_0_b(8)) ) ) - or - ( ( to_bit(ADDR_2(0)) xnor to_bit(addr_1_b(0)) ) and - ( to_bit(ADDR_2(1)) xnor to_bit(addr_1_b(1)) ) and - ( to_bit(ADDR_2(2)) xnor to_bit(addr_1_b(2)) ) and - ( to_bit(ADDR_2(3)) xnor to_bit(addr_1_b(3)) ) and - ( to_bit(ADDR_2(4)) xnor to_bit(addr_1_b(4)) ) and - ( to_bit(ADDR_2(5)) xnor to_bit(addr_1_b(5)) ) and - ( to_bit(ADDR_2(6)) xnor to_bit(addr_1_b(6)) ) and - ( to_bit(ADDR_2(7)) xnor to_bit(addr_1_b(7)) ) and - ( to_bit(ADDR_2(8)) xnor to_bit(addr_1_b(8)) ) ); - - k3_output_sel(0) <= ( ( to_bit(ADDR_3(0)) xnor to_bit(addr_0_b(0)) ) and - ( to_bit(ADDR_3(1)) xnor to_bit(addr_0_b(1)) ) and - ( to_bit(ADDR_3(2)) xnor to_bit(addr_0_b(2)) ) and - ( to_bit(ADDR_3(3)) xnor to_bit(addr_0_b(3)) ) and - ( to_bit(ADDR_3(4)) xnor to_bit(addr_0_b(4)) ) and - ( to_bit(ADDR_3(5)) xnor to_bit(addr_0_b(5)) ) and - ( to_bit(ADDR_3(6)) xnor to_bit(addr_0_b(6)) ) and - ( to_bit(ADDR_3(7)) xnor to_bit(addr_0_b(7)) ) and - ( to_bit(ADDR_3(8)) xnor to_bit(addr_0_b(8)) ) ) - or - ( ( to_bit(ADDR_3(0)) xnor to_bit(addr_1_b(0)) ) and - ( to_bit(ADDR_3(1)) xnor to_bit(addr_1_b(1)) ) and - ( to_bit(ADDR_3(2)) xnor to_bit(addr_1_b(2)) ) and - ( to_bit(ADDR_3(3)) xnor to_bit(addr_1_b(3)) ) and - ( to_bit(ADDR_3(4)) xnor to_bit(addr_1_b(4)) ) and - ( to_bit(ADDR_3(5)) xnor to_bit(addr_1_b(5)) ) and - ( to_bit(ADDR_3(6)) xnor to_bit(addr_1_b(6)) ) and - ( to_bit(ADDR_3(7)) xnor to_bit(addr_1_b(7)) ) and - ( to_bit(ADDR_3(8)) xnor to_bit(addr_1_b(8)) ) ); + k0_output_sel(0) <= ( not k0_output_sel(1) and not bram_0_B_input_sel(1) and not bram_0_B_input_sel(0) ) or + ( k0_output_sel(1) and not bram_1_B_input_sel(1) and not bram_1_B_input_sel(0) ); + + k1_output_sel(0) <= ( not k1_output_sel(1) and not bram_0_B_input_sel(1) and bram_0_B_input_sel(0) ) or + ( k1_output_sel(1) and not bram_1_B_input_sel(1) and bram_1_B_input_sel(0) ); + + k2_output_sel(0) <= ( not k2_output_sel(1) and bram_0_B_input_sel(1) and not bram_0_B_input_sel(0) ) or + ( k2_output_sel(1) and bram_1_B_input_sel(1) and not bram_1_B_input_sel(0) ); + + k3_output_sel(0) <= ( not k3_output_sel(1) and bram_0_B_input_sel(1) and bram_0_B_input_sel(0) ) or + ( k3_output_sel(1) and bram_1_B_input_sel(1) and bram_1_B_input_sel(0) ); input_controller_0 : block begin From b25568606856688f7d67ee783f9c3b4451604124 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Tue, 18 Sep 2012 21:19:55 +0200 Subject: [PATCH 10/18] Fixed kX_being_served signals --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 46 +++++++++++++--------- 1 file changed, 27 insertions(+), 19 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index 2221dbb..ee4f383 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -137,25 +137,33 @@ begin bram_1_B_input_sel <= "11"; - k0_being_served <= REQ_0 and ( (not bram_0_A_input_sel(1) and not bram_0_A_input_sel(0)) or - (not bram_0_B_input_sel(1) and not bram_0_B_input_sel(0)) or - (not bram_1_A_input_sel(1) and not bram_1_A_input_sel(0)) or - (not bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ); - - k1_being_served <= REQ_1 and ( (not bram_0_A_input_sel(1) and bram_0_A_input_sel(0)) or - (not bram_0_B_input_sel(1) and bram_0_B_input_sel(0)) or - (not bram_1_A_input_sel(1) and bram_1_A_input_sel(0)) or - (not bram_1_B_input_sel(1) and bram_1_B_input_sel(0)) ); - - k2_being_served <= REQ_2 and ( ( bram_0_A_input_sel(1) and not bram_0_A_input_sel(0)) or - ( bram_0_B_input_sel(1) and not bram_0_B_input_sel(0)) or - ( bram_1_A_input_sel(1) and not bram_1_A_input_sel(0)) or - ( bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ); - - k3_being_served <= REQ_3 and ( ( bram_0_A_input_sel(1) and bram_0_A_input_sel(0)) or - ( bram_0_B_input_sel(1) and bram_0_B_input_sel(0)) or - ( bram_1_A_input_sel(1) and bram_1_A_input_sel(0)) or - ( bram_1_B_input_sel(1) and bram_1_B_input_sel(0)) ); + k0_being_served <= to_bit(REQ_0) and ( + ( not k0_output_sel(1) and ( (not bram_0_A_input_sel(1) and not bram_0_A_input_sel(0)) or + (not bram_0_B_input_sel(1) and not bram_0_B_input_sel(0)) ) ) + or + ( k0_output_sel(1) and ( (not bram_1_A_input_sel(1) and not bram_1_A_input_sel(0)) or + (not bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ) ) ); + + k1_being_served <= to_bit(REQ_1) and ( + ( not k1_output_sel(1) and ( (not bram_0_A_input_sel(1) and bram_0_A_input_sel(0)) or + (not bram_0_B_input_sel(1) and bram_0_B_input_sel(0)) ) ) + or + ( k1_output_sel(1) and ( (not bram_1_A_input_sel(1) and bram_1_A_input_sel(0)) or + (not bram_1_B_input_sel(1) and bram_1_B_input_sel(0)) ) ) ); + + k2_being_served <= to_bit(REQ_2) and ( + ( not k2_output_sel(1) and ( ( bram_0_A_input_sel(1) and not bram_0_A_input_sel(0)) or + ( bram_0_B_input_sel(1) and not bram_0_B_input_sel(0)) ) ) + or + ( k2_output_sel(1) and ( ( bram_1_A_input_sel(1) and not bram_1_A_input_sel(0)) or + ( bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ) ) ); + + k3_being_served <= to_bit(REQ_3) and ( + ( not k3_output_sel(1) and ( ( bram_0_A_input_sel(1) and bram_0_A_input_sel(0)) or + ( bram_0_B_input_sel(1) and bram_0_B_input_sel(0)) ) ) + or + ( k3_output_sel(1) and ( ( bram_1_A_input_sel(1) and bram_1_A_input_sel(0)) or + ( bram_1_B_input_sel(1) and bram_1_B_input_sel(0)) ) ) ); -- From eecbd0cdba13160f470a851c1ebb9ea712eab1a7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Thu, 20 Sep 2012 03:23:00 +0200 Subject: [PATCH 11/18] First implementation without processes (needs some testing) --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 231 ++++++++++++++++++--- 1 file changed, 205 insertions(+), 26 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index ee4f383..101232b 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -92,11 +92,32 @@ architecture smem_arch of smem is signal k2_being_served : bit := '0'; signal k3_being_served : bit := '0'; + signal k0_needs_attention : bit := '0'; + signal k1_needs_attention : bit := '0'; + signal k2_needs_attention : bit := '0'; + signal k3_needs_attention : bit := '0'; + + signal addr_0_eq_addr_1 : bit := '0'; + signal addr_0_eq_addr_2 : bit := '0'; + signal addr_0_eq_addr_3 : bit := '0'; + signal addr_1_eq_addr_2 : bit := '0'; + signal addr_1_eq_addr_3 : bit := '0'; + signal addr_2_eq_addr_3 : bit := '0'; + signal bram_0_A_input_sel : bit_vector(1 downto 0) := "00"; signal bram_0_B_input_sel : bit_vector(1 downto 0) := "00"; signal bram_1_A_input_sel : bit_vector(1 downto 0) := "00"; signal bram_1_B_input_sel : bit_vector(1 downto 0) := "00"; + signal k0_needs_bram_0 : bit := '0'; + signal k0_needs_bram_1 : bit := '0'; + signal k1_needs_bram_0 : bit := '0'; + signal k1_needs_bram_1 : bit := '0'; + signal k2_needs_bram_0 : bit := '0'; + signal k2_needs_bram_1 : bit := '0'; + signal k3_needs_bram_0 : bit := '0'; + signal k3_needs_bram_1 : bit := '0'; + signal do_0_a : std_logic_vector(31 downto 0) := X"00000000"; signal do_0_b : std_logic_vector(31 downto 0) := X"00000000"; signal di_0_a : std_logic_vector(31 downto 0) := X"00000000"; @@ -123,18 +144,114 @@ architecture smem_arch of smem is begin - -- TODO: decide if enable signals should always be set to 1... en_0_a <= '1'; en_0_b <= '1'; en_1_a <= '1'; en_1_b <= '1'; - -- TODO: implement a decent input and output controller block - bram_0_A_input_sel <= "00"; - bram_0_B_input_sel <= "01"; - bram_1_A_input_sel <= "10"; - bram_1_B_input_sel <= "11"; + k0_needs_attention <= to_bit(REQ_0); + + k1_needs_attention <= to_bit(REQ_1) and (not (addr_0_eq_addr_1 and k0_needs_attention)); + + k2_needs_attention <= to_bit(REQ_2) and (not (addr_0_eq_addr_2 and k0_needs_attention)) and (not (addr_1_eq_addr_2 and k1_needs_attention)); + + k3_needs_attention <= to_bit(REQ_3) and (not (addr_0_eq_addr_3 and k0_needs_attention)) and (not (addr_1_eq_addr_3 and k1_needs_attention)) and (not (addr_2_eq_addr_3 and k2_needs_attention)); + + + k0_needs_bram_0 <= k0_needs_attention and not to_bit(ADDR_0(9)); + k0_needs_bram_1 <= k0_needs_attention and to_bit(ADDR_0(9)); + + k1_needs_bram_0 <= k1_needs_attention and not to_bit(ADDR_1(9)); + k1_needs_bram_1 <= k1_needs_attention and to_bit(ADDR_1(9)); + + k2_needs_bram_0 <= k2_needs_attention and not to_bit(ADDR_2(9)); + k2_needs_bram_1 <= k2_needs_attention and to_bit(ADDR_2(9)); + + k3_needs_bram_0 <= k3_needs_attention and not to_bit(ADDR_3(9)); + k3_needs_bram_1 <= k3_needs_attention and to_bit(ADDR_3(9)); + + + bram_0_A_input_sel(1) <= not k0_needs_bram_0 and not k2_needs_bram_0; + bram_0_A_input_sel(0) <= not (k0_needs_bram_0 or (k2_needs_bram_0 and not k1_needs_bram_0)); + + bram_1_A_input_sel(1) <= not k0_needs_bram_1 and not k2_needs_bram_1; + bram_1_A_input_sel(0) <= not (k0_needs_bram_1 or (k2_needs_bram_1 and not k1_needs_bram_1)); + + bram_0_B_input_sel(1) <= bram_0_A_input_sel(1) or bram_0_A_input_sel(0) or not k1_needs_bram_0; + bram_0_B_input_sel(0) <= not (k2_needs_bram_0 and ((k0_needs_bram_0 and not k1_needs_bram_0) or + (k1_needs_bram_0 and not k0_needs_bram_0))); + + bram_1_B_input_sel(1) <= bram_1_A_input_sel(1) or bram_1_A_input_sel(0) or not k1_needs_bram_1; + bram_1_B_input_sel(0) <= not (k2_needs_bram_1 and ((k0_needs_bram_1 and not k1_needs_bram_1) or + (k1_needs_bram_1 and not k0_needs_bram_1))); + + + addr_0_eq_addr_1 <= ( (to_bit(ADDR_0(9)) xnor to_bit(ADDR_1(9))) and + (to_bit(ADDR_0(8)) xnor to_bit(ADDR_1(8))) and + (to_bit(ADDR_0(7)) xnor to_bit(ADDR_1(7))) and + (to_bit(ADDR_0(6)) xnor to_bit(ADDR_1(6))) and + (to_bit(ADDR_0(5)) xnor to_bit(ADDR_1(5))) and + (to_bit(ADDR_0(4)) xnor to_bit(ADDR_1(4))) and + (to_bit(ADDR_0(3)) xnor to_bit(ADDR_1(3))) and + (to_bit(ADDR_0(2)) xnor to_bit(ADDR_1(2))) and + (to_bit(ADDR_0(1)) xnor to_bit(ADDR_1(1))) and + (to_bit(ADDR_0(0)) xnor to_bit(ADDR_1(0))) ); + + addr_0_eq_addr_2 <= ( (to_bit(ADDR_0(9)) xnor to_bit(ADDR_2(9))) and + (to_bit(ADDR_0(8)) xnor to_bit(ADDR_2(8))) and + (to_bit(ADDR_0(7)) xnor to_bit(ADDR_2(7))) and + (to_bit(ADDR_0(6)) xnor to_bit(ADDR_2(6))) and + (to_bit(ADDR_0(5)) xnor to_bit(ADDR_2(5))) and + (to_bit(ADDR_0(4)) xnor to_bit(ADDR_2(4))) and + (to_bit(ADDR_0(3)) xnor to_bit(ADDR_2(3))) and + (to_bit(ADDR_0(2)) xnor to_bit(ADDR_2(2))) and + (to_bit(ADDR_0(1)) xnor to_bit(ADDR_2(1))) and + (to_bit(ADDR_0(0)) xnor to_bit(ADDR_2(0))) ); + + addr_0_eq_addr_3 <= ( (to_bit(ADDR_0(9)) xnor to_bit(ADDR_3(9))) and + (to_bit(ADDR_0(8)) xnor to_bit(ADDR_3(8))) and + (to_bit(ADDR_0(7)) xnor to_bit(ADDR_3(7))) and + (to_bit(ADDR_0(6)) xnor to_bit(ADDR_3(6))) and + (to_bit(ADDR_0(5)) xnor to_bit(ADDR_3(5))) and + (to_bit(ADDR_0(4)) xnor to_bit(ADDR_3(4))) and + (to_bit(ADDR_0(3)) xnor to_bit(ADDR_3(3))) and + (to_bit(ADDR_0(2)) xnor to_bit(ADDR_3(2))) and + (to_bit(ADDR_0(1)) xnor to_bit(ADDR_3(1))) and + (to_bit(ADDR_0(0)) xnor to_bit(ADDR_3(0))) ); + + addr_1_eq_addr_2 <= ( (to_bit(ADDR_1(9)) xnor to_bit(ADDR_2(9))) and + (to_bit(ADDR_1(8)) xnor to_bit(ADDR_2(8))) and + (to_bit(ADDR_1(7)) xnor to_bit(ADDR_2(7))) and + (to_bit(ADDR_1(6)) xnor to_bit(ADDR_2(6))) and + (to_bit(ADDR_1(5)) xnor to_bit(ADDR_2(5))) and + (to_bit(ADDR_1(4)) xnor to_bit(ADDR_2(4))) and + (to_bit(ADDR_1(3)) xnor to_bit(ADDR_2(3))) and + (to_bit(ADDR_1(2)) xnor to_bit(ADDR_2(2))) and + (to_bit(ADDR_1(1)) xnor to_bit(ADDR_2(1))) and + (to_bit(ADDR_1(0)) xnor to_bit(ADDR_2(0))) ); + + addr_1_eq_addr_3 <= ( (to_bit(ADDR_1(9)) xnor to_bit(ADDR_3(9))) and + (to_bit(ADDR_1(8)) xnor to_bit(ADDR_3(8))) and + (to_bit(ADDR_1(7)) xnor to_bit(ADDR_3(7))) and + (to_bit(ADDR_1(6)) xnor to_bit(ADDR_3(6))) and + (to_bit(ADDR_1(5)) xnor to_bit(ADDR_3(5))) and + (to_bit(ADDR_1(4)) xnor to_bit(ADDR_3(4))) and + (to_bit(ADDR_1(3)) xnor to_bit(ADDR_3(3))) and + (to_bit(ADDR_1(2)) xnor to_bit(ADDR_3(2))) and + (to_bit(ADDR_1(1)) xnor to_bit(ADDR_3(1))) and + (to_bit(ADDR_1(0)) xnor to_bit(ADDR_3(0))) ); + + addr_2_eq_addr_3 <= ( (to_bit(ADDR_2(9)) xnor to_bit(ADDR_3(9))) and + (to_bit(ADDR_2(8)) xnor to_bit(ADDR_3(8))) and + (to_bit(ADDR_2(7)) xnor to_bit(ADDR_3(7))) and + (to_bit(ADDR_2(6)) xnor to_bit(ADDR_3(6))) and + (to_bit(ADDR_2(5)) xnor to_bit(ADDR_3(5))) and + (to_bit(ADDR_2(4)) xnor to_bit(ADDR_3(4))) and + (to_bit(ADDR_2(3)) xnor to_bit(ADDR_3(3))) and + (to_bit(ADDR_2(2)) xnor to_bit(ADDR_3(2))) and + (to_bit(ADDR_2(1)) xnor to_bit(ADDR_3(1))) and + (to_bit(ADDR_2(0)) xnor to_bit(ADDR_3(0))) ); k0_being_served <= to_bit(REQ_0) and ( @@ -143,21 +260,21 @@ begin or ( k0_output_sel(1) and ( (not bram_1_A_input_sel(1) and not bram_1_A_input_sel(0)) or (not bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ) ) ); - + k1_being_served <= to_bit(REQ_1) and ( ( not k1_output_sel(1) and ( (not bram_0_A_input_sel(1) and bram_0_A_input_sel(0)) or (not bram_0_B_input_sel(1) and bram_0_B_input_sel(0)) ) ) or ( k1_output_sel(1) and ( (not bram_1_A_input_sel(1) and bram_1_A_input_sel(0)) or (not bram_1_B_input_sel(1) and bram_1_B_input_sel(0)) ) ) ); - + k2_being_served <= to_bit(REQ_2) and ( ( not k2_output_sel(1) and ( ( bram_0_A_input_sel(1) and not bram_0_A_input_sel(0)) or ( bram_0_B_input_sel(1) and not bram_0_B_input_sel(0)) ) ) or ( k2_output_sel(1) and ( ( bram_1_A_input_sel(1) and not bram_1_A_input_sel(0)) or ( bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ) ) ); - + k3_being_served <= to_bit(REQ_3) and ( ( not k3_output_sel(1) and ( ( bram_0_A_input_sel(1) and bram_0_A_input_sel(0)) or ( bram_0_B_input_sel(1) and bram_0_B_input_sel(0)) ) ) @@ -177,23 +294,85 @@ begin k3_output_sel(1 downto 1) <= to_bitvector(ADDR_3(9 downto 9)); - -- - -- The lower bit of the output selection signal represent the BRAM - -- port that may be being used. For each BRAM (kX_output_sel(1)), we - -- see if the kernel is connected to port B (if not, then we suppose - -- port A: - -- - k0_output_sel(0) <= ( not k0_output_sel(1) and not bram_0_B_input_sel(1) and not bram_0_B_input_sel(0) ) or - ( k0_output_sel(1) and not bram_1_B_input_sel(1) and not bram_1_B_input_sel(0) ); - - k1_output_sel(0) <= ( not k1_output_sel(1) and not bram_0_B_input_sel(1) and bram_0_B_input_sel(0) ) or - ( k1_output_sel(1) and not bram_1_B_input_sel(1) and bram_1_B_input_sel(0) ); - - k2_output_sel(0) <= ( not k2_output_sel(1) and bram_0_B_input_sel(1) and not bram_0_B_input_sel(0) ) or - ( k2_output_sel(1) and bram_1_B_input_sel(1) and not bram_1_B_input_sel(0) ); - - k3_output_sel(0) <= ( not k3_output_sel(1) and bram_0_B_input_sel(1) and bram_0_B_input_sel(0) ) or - ( k3_output_sel(1) and bram_1_B_input_sel(1) and bram_1_B_input_sel(0) ); + k0_output_sel(0) <= ( not k0_output_sel(1) and ( (to_bit(ADDR_0(8)) xnor to_bit(addr_0_b(8))) and + (to_bit(ADDR_0(7)) xnor to_bit(addr_0_b(7))) and + (to_bit(ADDR_0(6)) xnor to_bit(addr_0_b(6))) and + (to_bit(ADDR_0(5)) xnor to_bit(addr_0_b(5))) and + (to_bit(ADDR_0(4)) xnor to_bit(addr_0_b(4))) and + (to_bit(ADDR_0(3)) xnor to_bit(addr_0_b(3))) and + (to_bit(ADDR_0(2)) xnor to_bit(addr_0_b(2))) and + (to_bit(ADDR_0(1)) xnor to_bit(addr_0_b(1))) and + (to_bit(ADDR_0(0)) xnor to_bit(addr_0_b(0))) ) ) + or + ( k0_output_sel(1) and ( (to_bit(ADDR_0(8)) xnor to_bit(addr_1_b(8))) and + (to_bit(ADDR_0(7)) xnor to_bit(addr_1_b(7))) and + (to_bit(ADDR_0(6)) xnor to_bit(addr_1_b(6))) and + (to_bit(ADDR_0(5)) xnor to_bit(addr_1_b(5))) and + (to_bit(ADDR_0(4)) xnor to_bit(addr_1_b(4))) and + (to_bit(ADDR_0(3)) xnor to_bit(addr_1_b(3))) and + (to_bit(ADDR_0(2)) xnor to_bit(addr_1_b(2))) and + (to_bit(ADDR_0(1)) xnor to_bit(addr_1_b(1))) and + (to_bit(ADDR_0(0)) xnor to_bit(addr_1_b(0))) ) ); + + k1_output_sel(0) <= ( not k1_output_sel(1) and ( (to_bit(ADDR_1(8)) xnor to_bit(addr_0_b(8))) and + (to_bit(ADDR_1(7)) xnor to_bit(addr_0_b(7))) and + (to_bit(ADDR_1(6)) xnor to_bit(addr_0_b(6))) and + (to_bit(ADDR_1(5)) xnor to_bit(addr_0_b(5))) and + (to_bit(ADDR_1(4)) xnor to_bit(addr_0_b(4))) and + (to_bit(ADDR_1(3)) xnor to_bit(addr_0_b(3))) and + (to_bit(ADDR_1(2)) xnor to_bit(addr_0_b(2))) and + (to_bit(ADDR_1(1)) xnor to_bit(addr_0_b(1))) and + (to_bit(ADDR_1(0)) xnor to_bit(addr_0_b(0))) ) ) + or + ( k1_output_sel(1) and ( (to_bit(ADDR_1(8)) xnor to_bit(addr_1_b(8))) and + (to_bit(ADDR_1(7)) xnor to_bit(addr_1_b(7))) and + (to_bit(ADDR_1(6)) xnor to_bit(addr_1_b(6))) and + (to_bit(ADDR_1(5)) xnor to_bit(addr_1_b(5))) and + (to_bit(ADDR_1(4)) xnor to_bit(addr_1_b(4))) and + (to_bit(ADDR_1(3)) xnor to_bit(addr_1_b(3))) and + (to_bit(ADDR_1(2)) xnor to_bit(addr_1_b(2))) and + (to_bit(ADDR_1(1)) xnor to_bit(addr_1_b(1))) and + (to_bit(ADDR_1(0)) xnor to_bit(addr_1_b(0))) ) ); + + k2_output_sel(0) <= ( not k2_output_sel(1) and ( (to_bit(ADDR_2(8)) xnor to_bit(addr_0_b(8))) and + (to_bit(ADDR_2(7)) xnor to_bit(addr_0_b(7))) and + (to_bit(ADDR_2(6)) xnor to_bit(addr_0_b(6))) and + (to_bit(ADDR_2(5)) xnor to_bit(addr_0_b(5))) and + (to_bit(ADDR_2(4)) xnor to_bit(addr_0_b(4))) and + (to_bit(ADDR_2(3)) xnor to_bit(addr_0_b(3))) and + (to_bit(ADDR_2(2)) xnor to_bit(addr_0_b(2))) and + (to_bit(ADDR_2(1)) xnor to_bit(addr_0_b(1))) and + (to_bit(ADDR_2(0)) xnor to_bit(addr_0_b(0))) ) ) + or + ( k2_output_sel(1) and ( (to_bit(ADDR_2(8)) xnor to_bit(addr_1_b(8))) and + (to_bit(ADDR_2(7)) xnor to_bit(addr_1_b(7))) and + (to_bit(ADDR_2(6)) xnor to_bit(addr_1_b(6))) and + (to_bit(ADDR_2(5)) xnor to_bit(addr_1_b(5))) and + (to_bit(ADDR_2(4)) xnor to_bit(addr_1_b(4))) and + (to_bit(ADDR_2(3)) xnor to_bit(addr_1_b(3))) and + (to_bit(ADDR_2(2)) xnor to_bit(addr_1_b(2))) and + (to_bit(ADDR_2(1)) xnor to_bit(addr_1_b(1))) and + (to_bit(ADDR_2(0)) xnor to_bit(addr_1_b(0))) ) ); + + k3_output_sel(0) <= ( not k3_output_sel(1) and ( (to_bit(ADDR_3(8)) xnor to_bit(addr_0_b(8))) and + (to_bit(ADDR_3(7)) xnor to_bit(addr_0_b(7))) and + (to_bit(ADDR_3(6)) xnor to_bit(addr_0_b(6))) and + (to_bit(ADDR_3(5)) xnor to_bit(addr_0_b(5))) and + (to_bit(ADDR_3(4)) xnor to_bit(addr_0_b(4))) and + (to_bit(ADDR_3(3)) xnor to_bit(addr_0_b(3))) and + (to_bit(ADDR_3(2)) xnor to_bit(addr_0_b(2))) and + (to_bit(ADDR_3(1)) xnor to_bit(addr_0_b(1))) and + (to_bit(ADDR_3(0)) xnor to_bit(addr_0_b(0))) ) ) + or + ( k3_output_sel(1) and ( (to_bit(ADDR_3(8)) xnor to_bit(addr_1_b(8))) and + (to_bit(ADDR_3(7)) xnor to_bit(addr_1_b(7))) and + (to_bit(ADDR_3(6)) xnor to_bit(addr_1_b(6))) and + (to_bit(ADDR_3(5)) xnor to_bit(addr_1_b(5))) and + (to_bit(ADDR_3(4)) xnor to_bit(addr_1_b(4))) and + (to_bit(ADDR_3(3)) xnor to_bit(addr_1_b(3))) and + (to_bit(ADDR_3(2)) xnor to_bit(addr_1_b(2))) and + (to_bit(ADDR_3(1)) xnor to_bit(addr_1_b(1))) and + (to_bit(ADDR_3(0)) xnor to_bit(addr_1_b(0))) ) ); input_controller_0 : block begin From 88781f31882f054ecc9d1a543659820997336577 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Thu, 20 Sep 2012 04:17:11 +0200 Subject: [PATCH 12/18] Enabled RDY_X signals --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 32 +++++++++++----------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index 101232b..5efee7b 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -150,6 +150,12 @@ begin en_1_b <= '1'; + RDY_0 <= to_stdulogic(k0_being_served); + RDY_1 <= to_stdulogic(k1_being_served); + RDY_2 <= to_stdulogic(k2_being_served); + RDY_3 <= to_stdulogic(k3_being_served); + + k0_needs_attention <= to_bit(REQ_0); k1_needs_attention <= to_bit(REQ_1) and (not (addr_0_eq_addr_1 and k0_needs_attention)); @@ -168,8 +174,8 @@ begin k2_needs_bram_0 <= k2_needs_attention and not to_bit(ADDR_2(9)); k2_needs_bram_1 <= k2_needs_attention and to_bit(ADDR_2(9)); - k3_needs_bram_0 <= k3_needs_attention and not to_bit(ADDR_3(9)); - k3_needs_bram_1 <= k3_needs_attention and to_bit(ADDR_3(9)); + -- NEVER USED --k3_needs_bram_0 <= k3_needs_attention and not to_bit(ADDR_3(9)); + -- NEVER USED --k3_needs_bram_1 <= k3_needs_attention and to_bit(ADDR_3(9)); bram_0_A_input_sel(1) <= not k0_needs_bram_0 and not k2_needs_bram_0; @@ -254,33 +260,27 @@ begin (to_bit(ADDR_2(0)) xnor to_bit(ADDR_3(0))) ); - k0_being_served <= to_bit(REQ_0) and ( - ( not k0_output_sel(1) and ( (not bram_0_A_input_sel(1) and not bram_0_A_input_sel(0)) or - (not bram_0_B_input_sel(1) and not bram_0_B_input_sel(0)) ) ) - or - ( k0_output_sel(1) and ( (not bram_1_A_input_sel(1) and not bram_1_A_input_sel(0)) or - (not bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ) ) ); + k0_being_served <= to_bit(REQ_0); - k1_being_served <= to_bit(REQ_1) and ( - ( not k1_output_sel(1) and ( (not bram_0_A_input_sel(1) and bram_0_A_input_sel(0)) or - (not bram_0_B_input_sel(1) and bram_0_B_input_sel(0)) ) ) - or - ( k1_output_sel(1) and ( (not bram_1_A_input_sel(1) and bram_1_A_input_sel(0)) or - (not bram_1_B_input_sel(1) and bram_1_B_input_sel(0)) ) ) ); + k1_being_served <= to_bit(REQ_1); k2_being_served <= to_bit(REQ_2) and ( ( not k2_output_sel(1) and ( ( bram_0_A_input_sel(1) and not bram_0_A_input_sel(0)) or ( bram_0_B_input_sel(1) and not bram_0_B_input_sel(0)) ) ) or ( k2_output_sel(1) and ( ( bram_1_A_input_sel(1) and not bram_1_A_input_sel(0)) or - ( bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ) ) ); + ( bram_1_B_input_sel(1) and not bram_1_B_input_sel(0)) ) ) + or + (not k2_needs_attention) ); k3_being_served <= to_bit(REQ_3) and ( ( not k3_output_sel(1) and ( ( bram_0_A_input_sel(1) and bram_0_A_input_sel(0)) or ( bram_0_B_input_sel(1) and bram_0_B_input_sel(0)) ) ) or ( k3_output_sel(1) and ( ( bram_1_A_input_sel(1) and bram_1_A_input_sel(0)) or - ( bram_1_B_input_sel(1) and bram_1_B_input_sel(0)) ) ) ); + ( bram_1_B_input_sel(1) and bram_1_B_input_sel(0)) ) ) + or + (not k3_needs_attention) ); -- From fee51392af155822f243a5c3abc6d5d8bb3953c0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Thu, 20 Sep 2012 21:06:47 +0200 Subject: [PATCH 13/18] Optimized kx_output_sel(0) signals and updated test bench --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 121 ++++++--------- hw/tb/smem_tb.vhd | 171 +++++++++++++++++++-- 2 files changed, 206 insertions(+), 86 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index 5efee7b..28e79f0 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -294,85 +294,56 @@ begin k3_output_sel(1 downto 1) <= to_bitvector(ADDR_3(9 downto 9)); - k0_output_sel(0) <= ( not k0_output_sel(1) and ( (to_bit(ADDR_0(8)) xnor to_bit(addr_0_b(8))) and - (to_bit(ADDR_0(7)) xnor to_bit(addr_0_b(7))) and - (to_bit(ADDR_0(6)) xnor to_bit(addr_0_b(6))) and - (to_bit(ADDR_0(5)) xnor to_bit(addr_0_b(5))) and - (to_bit(ADDR_0(4)) xnor to_bit(addr_0_b(4))) and - (to_bit(ADDR_0(3)) xnor to_bit(addr_0_b(3))) and - (to_bit(ADDR_0(2)) xnor to_bit(addr_0_b(2))) and - (to_bit(ADDR_0(1)) xnor to_bit(addr_0_b(1))) and - (to_bit(ADDR_0(0)) xnor to_bit(addr_0_b(0))) ) ) + k0_output_sel(0) <= ( not k0_output_sel(1) and ( not bram_0_B_input_sel(1) and + not bram_0_B_input_sel(0)) ) or - ( k0_output_sel(1) and ( (to_bit(ADDR_0(8)) xnor to_bit(addr_1_b(8))) and - (to_bit(ADDR_0(7)) xnor to_bit(addr_1_b(7))) and - (to_bit(ADDR_0(6)) xnor to_bit(addr_1_b(6))) and - (to_bit(ADDR_0(5)) xnor to_bit(addr_1_b(5))) and - (to_bit(ADDR_0(4)) xnor to_bit(addr_1_b(4))) and - (to_bit(ADDR_0(3)) xnor to_bit(addr_1_b(3))) and - (to_bit(ADDR_0(2)) xnor to_bit(addr_1_b(2))) and - (to_bit(ADDR_0(1)) xnor to_bit(addr_1_b(1))) and - (to_bit(ADDR_0(0)) xnor to_bit(addr_1_b(0))) ) ); - - k1_output_sel(0) <= ( not k1_output_sel(1) and ( (to_bit(ADDR_1(8)) xnor to_bit(addr_0_b(8))) and - (to_bit(ADDR_1(7)) xnor to_bit(addr_0_b(7))) and - (to_bit(ADDR_1(6)) xnor to_bit(addr_0_b(6))) and - (to_bit(ADDR_1(5)) xnor to_bit(addr_0_b(5))) and - (to_bit(ADDR_1(4)) xnor to_bit(addr_0_b(4))) and - (to_bit(ADDR_1(3)) xnor to_bit(addr_0_b(3))) and - (to_bit(ADDR_1(2)) xnor to_bit(addr_0_b(2))) and - (to_bit(ADDR_1(1)) xnor to_bit(addr_0_b(1))) and - (to_bit(ADDR_1(0)) xnor to_bit(addr_0_b(0))) ) ) + ( k0_output_sel(1) and ( not bram_1_B_input_sel(1) and + not bram_1_B_input_sel(0)) ); + + k1_output_sel(0) <= ( not k1_output_sel(1) and ( not bram_0_B_input_sel(1) and + bram_0_B_input_sel(0)) ) or - ( k1_output_sel(1) and ( (to_bit(ADDR_1(8)) xnor to_bit(addr_1_b(8))) and - (to_bit(ADDR_1(7)) xnor to_bit(addr_1_b(7))) and - (to_bit(ADDR_1(6)) xnor to_bit(addr_1_b(6))) and - (to_bit(ADDR_1(5)) xnor to_bit(addr_1_b(5))) and - (to_bit(ADDR_1(4)) xnor to_bit(addr_1_b(4))) and - (to_bit(ADDR_1(3)) xnor to_bit(addr_1_b(3))) and - (to_bit(ADDR_1(2)) xnor to_bit(addr_1_b(2))) and - (to_bit(ADDR_1(1)) xnor to_bit(addr_1_b(1))) and - (to_bit(ADDR_1(0)) xnor to_bit(addr_1_b(0))) ) ); - - k2_output_sel(0) <= ( not k2_output_sel(1) and ( (to_bit(ADDR_2(8)) xnor to_bit(addr_0_b(8))) and - (to_bit(ADDR_2(7)) xnor to_bit(addr_0_b(7))) and - (to_bit(ADDR_2(6)) xnor to_bit(addr_0_b(6))) and - (to_bit(ADDR_2(5)) xnor to_bit(addr_0_b(5))) and - (to_bit(ADDR_2(4)) xnor to_bit(addr_0_b(4))) and - (to_bit(ADDR_2(3)) xnor to_bit(addr_0_b(3))) and - (to_bit(ADDR_2(2)) xnor to_bit(addr_0_b(2))) and - (to_bit(ADDR_2(1)) xnor to_bit(addr_0_b(1))) and - (to_bit(ADDR_2(0)) xnor to_bit(addr_0_b(0))) ) ) + ( k1_output_sel(1) and ( not bram_1_B_input_sel(1) and + bram_1_B_input_sel(0)) ); + + k2_output_sel(0) <= ( not k2_output_sel(1) and ( bram_0_B_input_sel(1) and + not bram_0_B_input_sel(0)) ) or - ( k2_output_sel(1) and ( (to_bit(ADDR_2(8)) xnor to_bit(addr_1_b(8))) and - (to_bit(ADDR_2(7)) xnor to_bit(addr_1_b(7))) and - (to_bit(ADDR_2(6)) xnor to_bit(addr_1_b(6))) and - (to_bit(ADDR_2(5)) xnor to_bit(addr_1_b(5))) and - (to_bit(ADDR_2(4)) xnor to_bit(addr_1_b(4))) and - (to_bit(ADDR_2(3)) xnor to_bit(addr_1_b(3))) and - (to_bit(ADDR_2(2)) xnor to_bit(addr_1_b(2))) and - (to_bit(ADDR_2(1)) xnor to_bit(addr_1_b(1))) and - (to_bit(ADDR_2(0)) xnor to_bit(addr_1_b(0))) ) ); - - k3_output_sel(0) <= ( not k3_output_sel(1) and ( (to_bit(ADDR_3(8)) xnor to_bit(addr_0_b(8))) and - (to_bit(ADDR_3(7)) xnor to_bit(addr_0_b(7))) and - (to_bit(ADDR_3(6)) xnor to_bit(addr_0_b(6))) and - (to_bit(ADDR_3(5)) xnor to_bit(addr_0_b(5))) and - (to_bit(ADDR_3(4)) xnor to_bit(addr_0_b(4))) and - (to_bit(ADDR_3(3)) xnor to_bit(addr_0_b(3))) and - (to_bit(ADDR_3(2)) xnor to_bit(addr_0_b(2))) and - (to_bit(ADDR_3(1)) xnor to_bit(addr_0_b(1))) and - (to_bit(ADDR_3(0)) xnor to_bit(addr_0_b(0))) ) ) + ( k2_output_sel(1) and ( bram_1_B_input_sel(1) and + not bram_1_B_input_sel(0)) ); + + k3_output_sel(0) <= ( not k3_output_sel(1) and ( bram_0_B_input_sel(1) and + bram_0_B_input_sel(0)) ) or - ( k3_output_sel(1) and ( (to_bit(ADDR_3(8)) xnor to_bit(addr_1_b(8))) and - (to_bit(ADDR_3(7)) xnor to_bit(addr_1_b(7))) and - (to_bit(ADDR_3(6)) xnor to_bit(addr_1_b(6))) and - (to_bit(ADDR_3(5)) xnor to_bit(addr_1_b(5))) and - (to_bit(ADDR_3(4)) xnor to_bit(addr_1_b(4))) and - (to_bit(ADDR_3(3)) xnor to_bit(addr_1_b(3))) and - (to_bit(ADDR_3(2)) xnor to_bit(addr_1_b(2))) and - (to_bit(ADDR_3(1)) xnor to_bit(addr_1_b(1))) and - (to_bit(ADDR_3(0)) xnor to_bit(addr_1_b(0))) ) ); + ( k3_output_sel(1) and ( bram_1_B_input_sel(1) and + bram_1_B_input_sel(0)) ); + + -- + -- A process implementation alternative for the output controller + -- which could be used to update output signals only on BRAM_CLK + -- events or TRIG_CLK events: + -- + -- TODO: decide whether using a process implementation could be better. + -- + --k0_output_sel_controller : process (BRAM_CLK) begin + --if (BRAM_CLK'event and BRAM_CLK = '0') then + --if (ADDR_0(9 downto 9) = "0") then + --k0_output_sel(1 downto 1) <= "0"; + --if (bram_0_B_input_sel = "00") then + --k0_output_sel(0) <= '1'; + --else + --k0_output_sel(0) <= '0'; + --end if; + --else + --k0_output_sel(1 downto 1) <= "1"; + --if (bram_1_B_input_sel = "00") then + --k0_output_sel(0) <= '1'; + --else + --k0_output_sel(0) <= '0'; + --end if; + --end if; + --end if; + --end process k0_output_sel_controller; input_controller_0 : block begin diff --git a/hw/tb/smem_tb.vhd b/hw/tb/smem_tb.vhd index c451a5a..c84572d 100644 --- a/hw/tb/smem_tb.vhd +++ b/hw/tb/smem_tb.vhd @@ -41,10 +41,8 @@ architecture smem_tb_arch of smem_tb is IDLE, SMEM_WRITE, - WAIT_SMEM_WRITE, FOO, SMEM_READ, - WAIT_SMEM_READ, DONE ); @@ -75,7 +73,10 @@ architecture smem_tb_arch of smem_tb is signal RDY_0, RDY_1, RDY_2, RDY_3 : std_logic := '0'; signal start_test_bench : std_logic := '0'; - signal kernel_state : state_t; + signal kernel_0_state : state_t; + signal kernel_1_state : state_t; + signal kernel_2_state : state_t; + signal kernel_3_state : state_t; begin @@ -155,12 +156,12 @@ begin if (TRIG_CLK'event and TRIG_CLK = '1') then - case kernel_state is + case kernel_0_state is when IDLE => if start_test_bench = '1' then - kernel_state <= SMEM_WRITE; + kernel_0_state <= SMEM_WRITE; end if; when SMEM_WRITE => @@ -169,27 +170,175 @@ begin ADDR_0 <= "0000000000"; WE_0 <= "1111"; REQ_0 <= '1'; - kernel_state <= WAIT_SMEM_WRITE; + if (RDY_0 = '1') then + REQ_0 <= '0'; + kernel_0_state <= FOO; + end if; + + when FOO => + + kernel_0_state <= SMEM_READ; - when WAIT_SMEM_WRITE => + when SMEM_READ => + ADDR_0 <= "1000000001"; + WE_0 <= "0000"; + REQ_0 <= '1'; if (RDY_0 = '1') then REQ_0 <= '0'; - kernel_state <= FOO; + kernel_0_state <= DONE; + end if; + + when DONE => + + null; + + end case; + + end if; + + end process thread_0; + + + thread_1 : process (TRIG_CLK) + + begin + + if (TRIG_CLK'event and TRIG_CLK = '1') then + + case kernel_1_state is + + when IDLE => + + if start_test_bench = '1' then + kernel_1_state <= SMEM_WRITE; + end if; + + when SMEM_WRITE => + + DI_1 <= x"BBBBBBBB"; + ADDR_1 <= "0000000001"; + WE_1 <= "1111"; + REQ_1 <= '1'; + if (RDY_1 = '1') then + REQ_1 <= '0'; + kernel_1_state <= FOO; end if; when FOO => - kernel_state <= SMEM_READ; + kernel_1_state <= SMEM_READ; when SMEM_READ => + ADDR_1 <= "1000000001"; + WE_1 <= "0000"; + REQ_1 <= '1'; + if (RDY_1 = '1') then + REQ_1 <= '0'; + kernel_1_state <= DONE; + end if; + + when DONE => + null; - when WAIT_SMEM_READ => + end case; + + end if; + + end process thread_1; + + + thread_2 : process (TRIG_CLK) + + begin + + if (TRIG_CLK'event and TRIG_CLK = '1') then + + case kernel_2_state is + + when IDLE => + + if start_test_bench = '1' then + kernel_2_state <= SMEM_WRITE; + end if; + + when SMEM_WRITE => + + DI_2 <= x"CCCCCCCC"; + ADDR_2 <= "1000000000"; + WE_2 <= "1111"; + REQ_2 <= '1'; + if (RDY_2 = '1') then + REQ_2 <= '0'; + kernel_2_state <= FOO; + end if; + + when FOO => + + kernel_2_state <= SMEM_READ; + + when SMEM_READ => + + ADDR_2 <= "0000000000"; + WE_2 <= "0000"; + REQ_2 <= '1'; + if (RDY_2 = '1') then + REQ_2 <= '0'; + kernel_2_state <= DONE; + end if; + + when DONE => null; + end case; + + end if; + + end process thread_2; + + + thread_3 : process (TRIG_CLK) + + begin + + if (TRIG_CLK'event and TRIG_CLK = '1') then + + case kernel_3_state is + + when IDLE => + + if start_test_bench = '1' then + kernel_3_state <= SMEM_WRITE; + end if; + + when SMEM_WRITE => + + DI_3 <= x"DDDDDDDD"; + ADDR_3 <= "1000000001"; + WE_3 <= "1111"; + REQ_3 <= '1'; + if (RDY_3 = '1') then + REQ_3 <= '0'; + kernel_3_state <= FOO; + end if; + + when FOO => + + kernel_3_state <= SMEM_READ; + + when SMEM_READ => + + ADDR_3 <= "0000000001"; + WE_3 <= "0000"; + REQ_3 <= '1'; + if (RDY_3 = '1') then + REQ_3 <= '0'; + kernel_3_state <= DONE; + end if; + when DONE => null; @@ -198,7 +347,7 @@ begin end if; - end process thread_0; + end process thread_3; end smem_tb_arch; From e3c13e442a8506a9356a470aae8f3e30e70c87a3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Thu, 20 Sep 2012 21:34:04 +0200 Subject: [PATCH 14/18] Fixed bram_x_A_input_sel(1) signals --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index 28e79f0..29d383e 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -178,10 +178,10 @@ begin -- NEVER USED --k3_needs_bram_1 <= k3_needs_attention and to_bit(ADDR_3(9)); - bram_0_A_input_sel(1) <= not k0_needs_bram_0 and not k2_needs_bram_0; + bram_0_A_input_sel(1) <= not k0_needs_bram_0 and not k1_needs_bram_0; bram_0_A_input_sel(0) <= not (k0_needs_bram_0 or (k2_needs_bram_0 and not k1_needs_bram_0)); - bram_1_A_input_sel(1) <= not k0_needs_bram_1 and not k2_needs_bram_1; + bram_1_A_input_sel(1) <= not k0_needs_bram_1 and not k1_needs_bram_1; bram_1_A_input_sel(0) <= not (k0_needs_bram_1 or (k2_needs_bram_1 and not k1_needs_bram_1)); bram_0_B_input_sel(1) <= bram_0_A_input_sel(1) or bram_0_A_input_sel(0) or not k1_needs_bram_0; From a63030598f2daba1425481ed0fa69b7d147d1b2d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Thu, 20 Sep 2012 21:43:27 +0200 Subject: [PATCH 15/18] Supposing the kernels may forgot to change WE_X signal when not writing to the shared memory --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 58 ++++++++++++++++------ 1 file changed, 42 insertions(+), 16 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index 29d383e..db50434 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -104,6 +104,11 @@ architecture smem_arch of smem is signal addr_1_eq_addr_3 : bit := '0'; signal addr_2_eq_addr_3 : bit := '0'; + signal we_0_safe : std_logic_vector(3 downto 0) := "0000"; + signal we_1_safe : std_logic_vector(3 downto 0) := "0000"; + signal we_2_safe : std_logic_vector(3 downto 0) := "0000"; + signal we_3_safe : std_logic_vector(3 downto 0) := "0000"; + signal bram_0_A_input_sel : bit_vector(1 downto 0) := "00"; signal bram_0_B_input_sel : bit_vector(1 downto 0) := "00"; signal bram_1_A_input_sel : bit_vector(1 downto 0) := "00"; @@ -150,6 +155,27 @@ begin en_1_b <= '1'; + we_0_safe(3) <= WE_0(3) and REQ_0; + we_0_safe(2) <= WE_0(2) and REQ_0; + we_0_safe(1) <= WE_0(1) and REQ_0; + we_0_safe(0) <= WE_0(0) and REQ_0; + + we_1_safe(3) <= WE_0(3) and REQ_0; + we_1_safe(2) <= WE_0(2) and REQ_0; + we_1_safe(1) <= WE_0(1) and REQ_0; + we_1_safe(0) <= WE_0(0) and REQ_0; + + we_2_safe(3) <= WE_0(3) and REQ_0; + we_2_safe(2) <= WE_0(2) and REQ_0; + we_2_safe(1) <= WE_0(1) and REQ_0; + we_2_safe(0) <= WE_0(0) and REQ_0; + + we_3_safe(3) <= WE_0(3) and REQ_0; + we_3_safe(2) <= WE_0(2) and REQ_0; + we_3_safe(1) <= WE_0(1) and REQ_0; + we_3_safe(0) <= WE_0(0) and REQ_0; + + RDY_0 <= to_stdulogic(k0_being_served); RDY_1 <= to_stdulogic(k1_being_served); RDY_2 <= to_stdulogic(k2_being_served); @@ -358,10 +384,10 @@ begin ADDR_2(8 downto 0) when "10", ADDR_3(8 downto 0) when "11"; with bram_0_A_input_sel select - we_0_a <= WE_0 when "00", - WE_1 when "01", - WE_2 when "10", - WE_3 when "11"; + we_0_a <= we_0_safe when "00", + we_1_safe when "01", + we_2_safe when "10", + we_3_safe when "11"; end block input_controller_0; input_controller_1 : block begin @@ -376,10 +402,10 @@ begin ADDR_2(8 downto 0) when "10", ADDR_3(8 downto 0) when "11"; with bram_0_B_input_sel select - we_0_b <= WE_0 when "00", - WE_1 when "01", - WE_2 when "10", - WE_3 when "11"; + we_0_b <= we_0_safe when "00", + we_1_safe when "01", + we_2_safe when "10", + we_3_safe when "11"; end block input_controller_1; input_controller_2 : block begin @@ -394,10 +420,10 @@ begin ADDR_2(8 downto 0) when "10", ADDR_3(8 downto 0) when "11"; with bram_1_A_input_sel select - we_1_a <= WE_0 when "00", - WE_1 when "01", - WE_2 when "10", - WE_3 when "11"; + we_1_a <= we_0_safe when "00", + we_1_safe when "01", + we_2_safe when "10", + we_3_safe when "11"; end block input_controller_2; input_controller_3 : block begin @@ -412,10 +438,10 @@ begin ADDR_2(8 downto 0) when "10", ADDR_3(8 downto 0) when "11"; with bram_1_B_input_sel select - we_1_b <= WE_0 when "00", - WE_1 when "01", - WE_2 when "10", - WE_3 when "11"; + we_1_b <= we_0_safe when "00", + we_1_safe when "01", + we_2_safe when "10", + we_3_safe when "11"; end block input_controller_3; From 87606d51d4f07eaeeabe4fa7b93bbf74d918e0fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Thu, 20 Sep 2012 21:48:52 +0200 Subject: [PATCH 16/18] Fixed some signal names from last commit --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 28 +++++++++++----------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index db50434..1c8797d 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -160,20 +160,20 @@ begin we_0_safe(1) <= WE_0(1) and REQ_0; we_0_safe(0) <= WE_0(0) and REQ_0; - we_1_safe(3) <= WE_0(3) and REQ_0; - we_1_safe(2) <= WE_0(2) and REQ_0; - we_1_safe(1) <= WE_0(1) and REQ_0; - we_1_safe(0) <= WE_0(0) and REQ_0; - - we_2_safe(3) <= WE_0(3) and REQ_0; - we_2_safe(2) <= WE_0(2) and REQ_0; - we_2_safe(1) <= WE_0(1) and REQ_0; - we_2_safe(0) <= WE_0(0) and REQ_0; - - we_3_safe(3) <= WE_0(3) and REQ_0; - we_3_safe(2) <= WE_0(2) and REQ_0; - we_3_safe(1) <= WE_0(1) and REQ_0; - we_3_safe(0) <= WE_0(0) and REQ_0; + we_1_safe(3) <= WE_1(3) and REQ_1; + we_1_safe(2) <= WE_1(2) and REQ_1; + we_1_safe(1) <= WE_1(1) and REQ_1; + we_1_safe(0) <= WE_1(0) and REQ_1; + + we_2_safe(3) <= WE_2(3) and REQ_2; + we_2_safe(2) <= WE_2(2) and REQ_2; + we_2_safe(1) <= WE_2(1) and REQ_2; + we_2_safe(0) <= WE_2(0) and REQ_2; + + we_3_safe(3) <= WE_3(3) and REQ_3; + we_3_safe(2) <= WE_3(2) and REQ_3; + we_3_safe(1) <= WE_3(1) and REQ_3; + we_3_safe(0) <= WE_3(0) and REQ_3; RDY_0 <= to_stdulogic(k0_being_served); From 31f3881f3c764d9455e7a2a119ad6f434ac1fa95 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Thu, 20 Sep 2012 23:12:40 +0200 Subject: [PATCH 17/18] Fixed broadcast when various write requests are found --- hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd | 38 +++++++++++----------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd index 1c8797d..352c88d 100644 --- a/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd +++ b/hw/pcores/master_v1_00_a/hdl/vhdl/smem.vhd @@ -155,25 +155,25 @@ begin en_1_b <= '1'; - we_0_safe(3) <= WE_0(3) and REQ_0; - we_0_safe(2) <= WE_0(2) and REQ_0; - we_0_safe(1) <= WE_0(1) and REQ_0; - we_0_safe(0) <= WE_0(0) and REQ_0; - - we_1_safe(3) <= WE_1(3) and REQ_1; - we_1_safe(2) <= WE_1(2) and REQ_1; - we_1_safe(1) <= WE_1(1) and REQ_1; - we_1_safe(0) <= WE_1(0) and REQ_1; - - we_2_safe(3) <= WE_2(3) and REQ_2; - we_2_safe(2) <= WE_2(2) and REQ_2; - we_2_safe(1) <= WE_2(1) and REQ_2; - we_2_safe(0) <= WE_2(0) and REQ_2; - - we_3_safe(3) <= WE_3(3) and REQ_3; - we_3_safe(2) <= WE_3(2) and REQ_3; - we_3_safe(1) <= WE_3(1) and REQ_3; - we_3_safe(0) <= WE_3(0) and REQ_3; + we_0_safe(3) <= WE_0(3) and to_stdulogic(k0_needs_attention); + we_0_safe(2) <= WE_0(2) and to_stdulogic(k0_needs_attention); + we_0_safe(1) <= WE_0(1) and to_stdulogic(k0_needs_attention); + we_0_safe(0) <= WE_0(0) and to_stdulogic(k0_needs_attention); + + we_1_safe(3) <= WE_1(3) and to_stdulogic(k1_needs_attention); + we_1_safe(2) <= WE_1(2) and to_stdulogic(k1_needs_attention); + we_1_safe(1) <= WE_1(1) and to_stdulogic(k1_needs_attention); + we_1_safe(0) <= WE_1(0) and to_stdulogic(k1_needs_attention); + + we_2_safe(3) <= WE_2(3) and to_stdulogic(k2_needs_attention); + we_2_safe(2) <= WE_2(2) and to_stdulogic(k2_needs_attention); + we_2_safe(1) <= WE_2(1) and to_stdulogic(k2_needs_attention); + we_2_safe(0) <= WE_2(0) and to_stdulogic(k2_needs_attention); + + we_3_safe(3) <= WE_3(3) and to_stdulogic(k3_needs_attention); + we_3_safe(2) <= WE_3(2) and to_stdulogic(k3_needs_attention); + we_3_safe(1) <= WE_3(1) and to_stdulogic(k3_needs_attention); + we_3_safe(0) <= WE_3(0) and to_stdulogic(k3_needs_attention); RDY_0 <= to_stdulogic(k0_being_served); From 2f2968141b468166d626121800a3e028c85f54d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miguel=20S=C3=A1nchez=20de=20Le=C3=B3n=20Peque?= Date: Thu, 20 Sep 2012 23:17:11 +0200 Subject: [PATCH 18/18] Updated test bench --- hw/tb/smem_tb.vhd | 300 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 270 insertions(+), 30 deletions(-) diff --git a/hw/tb/smem_tb.vhd b/hw/tb/smem_tb.vhd index c84572d..34cdaad 100644 --- a/hw/tb/smem_tb.vhd +++ b/hw/tb/smem_tb.vhd @@ -40,9 +40,17 @@ architecture smem_tb_arch of smem_tb is type state_t is ( IDLE, - SMEM_WRITE, - FOO, - SMEM_READ, + SMEM_WRITE_0, + FOO_0, + SMEM_READ_0, + FOO_1, + SMEM_WRITE_1, + FOO_2, + SMEM_READ_1, + FOO_3, + SMEM_WRITE_2, + FOO_4, + SMEM_READ_2, DONE ); @@ -161,10 +169,10 @@ begin when IDLE => if start_test_bench = '1' then - kernel_0_state <= SMEM_WRITE; + kernel_0_state <= SMEM_WRITE_0; end if; - when SMEM_WRITE => + when SMEM_WRITE_0 => DI_0 <= x"AAAAAAAA"; ADDR_0 <= "0000000000"; @@ -172,18 +180,76 @@ begin REQ_0 <= '1'; if (RDY_0 = '1') then REQ_0 <= '0'; - kernel_0_state <= FOO; + kernel_0_state <= FOO_0; end if; - when FOO => + when FOO_0 => - kernel_0_state <= SMEM_READ; + kernel_0_state <= SMEM_READ_0; - when SMEM_READ => + when SMEM_READ_0 => + + ADDR_0 <= "0000000000"; + WE_0 <= "0000"; + REQ_0 <= '1'; + if (RDY_0 = '1') then + REQ_0 <= '0'; + kernel_0_state <= FOO_1; + end if; + + when FOO_1 => + + kernel_0_state <= SMEM_WRITE_1; + + when SMEM_WRITE_1 => + + DI_0 <= x"AAAAAAAA"; + ADDR_0 <= "0000000000"; + WE_0 <= "1111"; + REQ_0 <= '1'; + if (RDY_0 = '1') then + REQ_0 <= '0'; + kernel_0_state <= FOO_2; + end if; + + when FOO_2 => + + kernel_0_state <= SMEM_READ_1; + + when SMEM_READ_1 => ADDR_0 <= "1000000001"; WE_0 <= "0000"; REQ_0 <= '1'; + if (RDY_0 = '1') then + REQ_0 <= '0'; + kernel_0_state <= FOO_3; + end if; + + when FOO_3 => + + kernel_0_state <= SMEM_WRITE_2; + + when SMEM_WRITE_2 => + + DI_0 <= x"AAAAAAAA"; + ADDR_0 <= "0000000010"; + WE_0 <= "1111"; + REQ_0 <= '1'; + if (RDY_0 = '1') then + REQ_0 <= '0'; + kernel_0_state <= FOO_4; + end if; + + when FOO_4 => + + kernel_0_state <= SMEM_READ_2; + + when SMEM_READ_2 => + + ADDR_0 <= "0000001110"; + WE_0 <= "0000"; + REQ_0 <= '1'; if (RDY_0 = '1') then REQ_0 <= '0'; kernel_0_state <= DONE; @@ -211,10 +277,39 @@ begin when IDLE => if start_test_bench = '1' then - kernel_1_state <= SMEM_WRITE; + kernel_1_state <= SMEM_WRITE_0; end if; - when SMEM_WRITE => + when SMEM_WRITE_0 => + + DI_1 <= x"BBBBBBBB"; + ADDR_1 <= "0000000000"; + WE_1 <= "1111"; + REQ_1 <= '1'; + if (RDY_1 = '1') then + REQ_1 <= '0'; + kernel_1_state <= FOO_0; + end if; + + when FOO_0 => + + kernel_1_state <= SMEM_READ_0; + + when SMEM_READ_0 => + + ADDR_1 <= "0000000000"; + WE_1 <= "0000"; + REQ_1 <= '1'; + if (RDY_1 = '1') then + REQ_1 <= '0'; + kernel_1_state <= FOO_1; + end if; + + when FOO_1 => + + kernel_1_state <= SMEM_WRITE_1; + + when SMEM_WRITE_1 => DI_1 <= x"BBBBBBBB"; ADDR_1 <= "0000000001"; @@ -222,16 +317,45 @@ begin REQ_1 <= '1'; if (RDY_1 = '1') then REQ_1 <= '0'; - kernel_1_state <= FOO; + kernel_1_state <= FOO_2; end if; - when FOO => + when FOO_2 => - kernel_1_state <= SMEM_READ; + kernel_1_state <= SMEM_READ_1; - when SMEM_READ => + when SMEM_READ_1 => - ADDR_1 <= "1000000001"; + ADDR_1 <= "1000000000"; + WE_1 <= "0000"; + REQ_1 <= '1'; + if (RDY_1 = '1') then + REQ_1 <= '0'; + kernel_1_state <= FOO_3; + end if; + + when FOO_3 => + + kernel_1_state <= SMEM_WRITE_2; + + when SMEM_WRITE_2 => + + DI_1 <= x"BBBBBBBB"; + ADDR_1 <= "0000000110"; + WE_1 <= "1111"; + REQ_1 <= '1'; + if (RDY_1 = '1') then + REQ_1 <= '0'; + kernel_1_state <= FOO_4; + end if; + + when FOO_4 => + + kernel_1_state <= SMEM_READ_2; + + when SMEM_READ_2 => + + ADDR_1 <= "0000001010"; WE_1 <= "0000"; REQ_1 <= '1'; if (RDY_1 = '1') then @@ -261,29 +385,87 @@ begin when IDLE => if start_test_bench = '1' then - kernel_2_state <= SMEM_WRITE; + kernel_2_state <= SMEM_WRITE_0; end if; - when SMEM_WRITE => + when SMEM_WRITE_0 => DI_2 <= x"CCCCCCCC"; - ADDR_2 <= "1000000000"; + ADDR_2 <= "0000000000"; WE_2 <= "1111"; REQ_2 <= '1'; if (RDY_2 = '1') then REQ_2 <= '0'; - kernel_2_state <= FOO; + kernel_2_state <= FOO_0; end if; - when FOO => + when FOO_0 => - kernel_2_state <= SMEM_READ; + kernel_2_state <= SMEM_READ_0; - when SMEM_READ => + when SMEM_READ_0 => ADDR_2 <= "0000000000"; WE_2 <= "0000"; REQ_2 <= '1'; + if (RDY_2 = '1') then + REQ_2 <= '0'; + kernel_2_state <= FOO_1; + end if; + + when FOO_1 => + + kernel_2_state <= SMEM_WRITE_1; + + when SMEM_WRITE_1 => + + DI_2 <= x"CCCCCCCC"; + ADDR_2 <= "1000000000"; + WE_2 <= "1111"; + REQ_2 <= '1'; + if (RDY_2 = '1') then + REQ_2 <= '0'; + kernel_2_state <= FOO_2; + end if; + + when FOO_2 => + + kernel_2_state <= SMEM_READ_1; + + when SMEM_READ_1 => + + ADDR_2 <= "0000000001"; + WE_2 <= "0000"; + REQ_2 <= '1'; + if (RDY_2 = '1') then + REQ_2 <= '0'; + kernel_2_state <= FOO_3; + end if; + + when FOO_3 => + + kernel_2_state <= SMEM_WRITE_2; + + when SMEM_WRITE_2 => + + DI_2 <= x"CCCCCCCC"; + ADDR_2 <= "0000001010"; + WE_2 <= "1111"; + REQ_2 <= '1'; + if (RDY_2 = '1') then + REQ_2 <= '0'; + kernel_2_state <= FOO_4; + end if; + + when FOO_4 => + + kernel_2_state <= SMEM_READ_2; + + when SMEM_READ_2 => + + ADDR_2 <= "0000000110"; + WE_2 <= "0000"; + REQ_2 <= '1'; if (RDY_2 = '1') then REQ_2 <= '0'; kernel_2_state <= DONE; @@ -311,10 +493,39 @@ begin when IDLE => if start_test_bench = '1' then - kernel_3_state <= SMEM_WRITE; + kernel_3_state <= SMEM_WRITE_0; + end if; + + when SMEM_WRITE_0 => + + DI_3 <= x"DDDDDDDD"; + ADDR_3 <= "0000000000"; + WE_3 <= "1111"; + REQ_3 <= '1'; + if (RDY_3 = '1') then + REQ_3 <= '0'; + kernel_3_state <= FOO_0; + end if; + + when FOO_0 => + + kernel_3_state <= SMEM_READ_0; + + when SMEM_READ_0 => + + ADDR_3 <= "0000000000"; + WE_3 <= "0000"; + REQ_3 <= '1'; + if (RDY_3 = '1') then + REQ_3 <= '0'; + kernel_3_state <= FOO_1; end if; - when SMEM_WRITE => + when FOO_1 => + + kernel_3_state <= SMEM_WRITE_1; + + when SMEM_WRITE_1 => DI_3 <= x"DDDDDDDD"; ADDR_3 <= "1000000001"; @@ -322,16 +533,45 @@ begin REQ_3 <= '1'; if (RDY_3 = '1') then REQ_3 <= '0'; - kernel_3_state <= FOO; + kernel_3_state <= FOO_2; + end if; + + when FOO_2 => + + kernel_3_state <= SMEM_READ_1; + + when SMEM_READ_1 => + + ADDR_3 <= "0000000000"; + WE_3 <= "0000"; + REQ_3 <= '1'; + if (RDY_3 = '1') then + REQ_3 <= '0'; + kernel_3_state <= FOO_3; + end if; + + when FOO_3 => + + kernel_3_state <= SMEM_WRITE_2; + + when SMEM_WRITE_2 => + + DI_3 <= x"DDDDDDDD"; + ADDR_3 <= "0000001110"; + WE_3 <= "1111"; + REQ_3 <= '1'; + if (RDY_3 = '1') then + REQ_3 <= '0'; + kernel_3_state <= FOO_4; end if; - when FOO => + when FOO_4 => - kernel_3_state <= SMEM_READ; + kernel_3_state <= SMEM_READ_2; - when SMEM_READ => + when SMEM_READ_2 => - ADDR_3 <= "0000000001"; + ADDR_3 <= "0000000010"; WE_3 <= "0000"; REQ_3 <= '1'; if (RDY_3 = '1') then