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Fixed connection between the clock generator and memory interface (co…

…nnection didn't exist)
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1 parent 00bb3f8 commit 63ad71e175f867404a3f4714dfdd01f0b8fb2f6b @Peque committed Jul 20, 2012
Showing with 1 addition and 1 deletion.
  1. +1 −1 src/edk.tcl
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2 src/edk.tcl
@@ -257,7 +257,7 @@ xadd_hw_ipinst_port $MCB_DDR2_handle mcbx_dram_cke mcbx_dram_cke
xadd_hw_ipinst_port $MCB_DDR2_handle mcbx_dram_cas_n mcbx_dram_cas_n
xadd_hw_ipinst_port $MCB_DDR2_handle mcbx_dram_ba mcbx_dram_ba
xadd_hw_ipinst_port $MCB_DDR2_handle mcbx_dram_addr mcbx_dram_addr
-xadd_hw_ipinst_port $MCB_DDR2_handle sysclk_2x clk_600_0000MHz_PPL0_nobuf
+xadd_hw_ipinst_port $MCB_DDR2_handle sysclk_2x clk_600_0000MHz_PLL0_nobuf
xadd_hw_ipinst_port $MCB_DDR2_handle sysclk_2x_180 clk_600_0000MHz_180_PLL0_nobuf
xadd_hw_ipinst_port $MCB_DDR2_handle SYS_RST psys_reset_0_BUS_STRUCT_RESET
xadd_hw_ipinst_port $MCB_DDR2_handle PLL_LOCK psys_reset_0_Dcm_locked

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