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Allow + or - before ASC_SOP values. (#165)

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jminor committed Oct 5, 2017
1 parent 82e9636 commit c4916c7d6ade79be5db3061b343556576ee07257
Showing with 5 additions and 5 deletions.
  1. +1 −1 opentimelineio/adapters/cmx_3600.py
  2. +2 −2 tests/sample_data/cdl.edl
  3. +2 −2 tests/test_cdl.py
@@ -278,7 +278,7 @@ def make_clip(self, comment_data):
sat = 1.0
if asc_sop:
triple = r'([\d.]+) ([\d.]+) ([\d.]+)'
triple = r'([-+]?[\d.]+) ([-+]?[\d.]+) ([-+]?[\d.]+)'
m = re.match(
r'\('+triple+'\)\s*\('+triple+'\)\s*\('+triple+'\)',
asc_sop
@@ -2,12 +2,12 @@ TITLE: CDL_Example_Formatted_Many_Ways.01
001 AX V C 01:00:04:05 01:00:05:12 00:00:00:00 00:00:01:07
* FROM CLIP NAME: ZZ100_501 (LAY3)
*ASC_SOP (0.1 0.2 0.3) (1.0 0.0122 0.0305) (1.0 0.0 1.0)
*ASC_SOP (0.1 0.2 0.3) (1.0 -0.0122 0.0305) (1.0 0.0 1.0)
*ASC_SAT 0.9
* SOURCE FILE: ZZ100_501.LAY3.01
002 AX V C 01:00:04:05 01:00:05:12 00:00:01:07 00:00:02:14
* FROM CLIP NAME: ZZ100_501 (LAY3)
* ASC_SOP: (0.1 0.2 0.3) (1.0 0.0122 0.0305) (1.0 0.0 1.0)
* ASC_SOP: (0.1 0.2 0.3) (1.0 -0.0122 0.0305) (1.0 0.0 1.0)
* ASC_SAT: 0.9
* SOURCE FILE: ZZ100_501.LAY3.01
View
@@ -62,7 +62,7 @@ def test_cdl_read(self):
)
self.assertEqual(
cdl.get("asc_sop").get("offset"),
[1.0000, 0.0122, 0.0305]
[1.0000, -0.0122, 0.0305]
)
self.assertEqual(
cdl.get("asc_sop").get("power"),
@@ -74,7 +74,7 @@ def test_cdl_round_trip(self):
001 AX V C 01:00:04:05 01:00:05:12 00:00:00:00 00:00:01:07
* FROM CLIP NAME: ZZ100_501 (LAY3)
*ASC_SOP (0.1 0.2 0.3) (1.0 0.0122 0.0305) (1.0 0.0 1.0)
*ASC_SOP (0.1 0.2 0.3) (1.0 -0.0122 0.0305) (1.0 0.0 1.0)
*ASC_SAT 0.9
* SOURCE FILE: ZZ100_501.LAY3.01
"""

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