diff --git a/doc/Makefile b/doc/Makefile
index 98733e8d..247b174d 100644
--- a/doc/Makefile
+++ b/doc/Makefile
@@ -20,7 +20,7 @@ man:
 #---
 
 html:
-	$(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
+	PYTHONPATH=$(shell pwd)/.. $(SPHINXBUILD) -b html $(ALLSPHINXOPTS) $(BUILDDIR)/html
 
 #---
 
diff --git a/doc/conf.py b/doc/conf.py
index ecb9a968..ffead9cc 100644
--- a/doc/conf.py
+++ b/doc/conf.py
@@ -115,12 +115,12 @@
 
 # -- Sphinx.Ext.InterSphinx -----------------------------------------------
 
-intersphinx_mapping = {
-   'python': ('https://docs.python.org/3.8/', None),
-   'ghdl': ('https://ghdl.github.io/ghdl', None),
-   'vunit': ('https://vunit.github.io', None),
-   'matplotlib': ('https://matplotlib.org/', None)
-}
+#intersphinx_mapping = {
+#   'python': ('https://docs.python.org/3.8/', None),
+#   'ghdl': ('https://ghdl.github.io/ghdl', None),
+#   'vunit': ('https://vunit.github.io', None),
+#   'matplotlib': ('https://matplotlib.org/', None)
+#}
 
 # -- Sphinx.Ext.ExtLinks --------------------------------------------------
 extlinks = {
diff --git a/doc/dev.rst b/doc/dev.rst
index 4480fb7c..39486ea3 100644
--- a/doc/dev.rst
+++ b/doc/dev.rst
@@ -43,8 +43,8 @@ solve the complete workflow were encapsulated into procedures
   This file is compliant with Tcl 8.4 because is the oldest used by a
   supported FPGA Tool (Xilinx ISE).
 
-fpga/tool/*.py
-==============
+fpga/tool/<TOOL>.py
+===================
 
 A base class (``__init__.py``) was developed to provides a uniform API to be
 implemented for each supported Tool.