From 75569227472f627a45ea8524d7e03822f9c73956 Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Tue, 16 Feb 2021 22:03:09 -0300 Subject: [PATCH 1/4] doc: added a detailed support table --- doc/intro.rst | 43 +++++++++++++++++++++++++++++++++++++++---- 1 file changed, 39 insertions(+), 4 deletions(-) diff --git a/doc/intro.rst b/doc/intro.rst index b35607c4..3aa2607b 100644 --- a/doc/intro.rst +++ b/doc/intro.rst @@ -3,10 +3,6 @@ Introduction ############ - -Detailed support ----------------- - .. ATTENTION:: PyFPGA assumes that the backend Tool is ready to run. @@ -18,6 +14,45 @@ Detailed support * GNU/Linux: extra packages installed, environment variables assigned and permissions granted on devices (to transfer the bitstream). +Detailed support +---------------- + +| | ISE | Libero | Openflow | Quartus | Vivado | +|--- |:---: |:---: |:---: |:---: |:---: | +| **add_files** +| `vhdl` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | +| `verilog` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | +| `system_verilog` | `TBD` | `TBD` | `TBD` | `TBD` | `TBD` | +| `constraint` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | +| `block_design` | `NY` | `NY` | `NY` | `NY` | `Yes` | +| **set_param** +| `boolean` (*VHDL/Verilog*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | +| `integer` (*VHDL/Verilog*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | +| `string` (*VHDL/Verilog*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | +| `real` (*VHDL/Verilog*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | +| `std_logic` (*VHDL*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | +| `std_logic_vector` (*VHDL*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | +| **add_path** | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | +| **set_define** (*Verilog*) | `TBI` | `TBI` | `TBI` | `TBI` | `TBI` | +| **set_arch** (*VHDL*) | `TBI` | `TBI` | `TBI` | `TBI` | `TBI` | +| **generate** +| `prj` | `Yes` | `Yes` | `No` | `Yes` | `Yes` | +| `syn` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | +| `imp` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | +| `bit` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | +| **transfer** +| `fpga` | `Yes` | `NY` | `Yes` | `Yes` | `Yes` | +| `spi` | `Yes` | `NY` | `NY` | `NY` | `NY` | +| `bpi` | `Yes` | `NY` | `NY` | `NY` | `NY` | +| `detect` | `Yes` | `NY` | `NY` | `Yes` | `Yes` | +| `unlock` | `Yes` | `No` | `No` | `No` | `No` | + +* `Yes`: already supported +* `No`: no plans (or unneeded) +* `NY`: Not yet, but maybe someday +* `TBD`: To Be Defined +* `TBI`: To Be Implemented + Next Steps ---------- From 322abb52205fb9f29bef30e85e126b43c7bf8be4 Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Tue, 16 Feb 2021 22:29:38 -0300 Subject: [PATCH 2/4] fpga: updated add_files description --- fpga/project.py | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/fpga/project.py b/fpga/project.py index 585e276b..fb197c93 100644 --- a/fpga/project.py +++ b/fpga/project.py @@ -1,6 +1,6 @@ # +# Copyright (C) 2019-2021 Rodrigo A. Melo # Copyright (C) 2019-2020 INTI -# Copyright (C) 2019-2020 Rodrigo A. Melo # # This program is free software: you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -169,16 +169,18 @@ def add_files(self, pathname, filetype=None, library=None, options=None): :param pathname: a relative path to a file, which can contain shell-style wildcards (glob compliant) - :param filetype: the valid values are **verilog** or **vhdl**, - **constraint** and **design** (for a graphical block design). It is - automatically discovered (based on the extension) if None provided - (except for **design**). The default (autodiscovery failed) is - **constraint** + :param filetype: specifies the file type :param library: an optional VHDL library name :param options: to be provided to the underlying tool :raises FileNotFoundError: when a file specified as pathname is not found - :raises ValueError: when filetype is unsupported + :raises ValueError: when *filetype* is unsupported + + .. note:: Valid values for *filetype* are ``vhdl``, ``verilog``, + ``system_verilog``, ``constraint`` (default) and ``block_design`` + (only **Vivado** is currently supported). If None provided, this + value is automatically discovered based on the extension ( + ``.vhd`` or ``.vhdl``, ``.v`` and ``.sv``). """ pathname = os.path.join(self._absdir, pathname) pathname = os.path.normpath(pathname) From 8ee85e4cab74799e4b7b2110cc5b8073aace683d Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Tue, 16 Feb 2021 22:54:53 -0300 Subject: [PATCH 3/4] doc: removed the helpers section --- doc/helpers.rst | 4 ---- doc/index.rst | 1 - 2 files changed, 5 deletions(-) delete mode 100644 doc/helpers.rst diff --git a/doc/helpers.rst b/doc/helpers.rst deleted file mode 100644 index c71063cd..00000000 --- a/doc/helpers.rst +++ /dev/null @@ -1,4 +0,0 @@ -.. program:: pyfpga - -Helper tools -############ diff --git a/doc/index.rst b/doc/index.rst index 2d436d05..d68cabdf 100644 --- a/doc/index.rst +++ b/doc/index.rst @@ -24,5 +24,4 @@ PyFPGA Documentation advanced tools api - helpers dev From 5766208b5d8f2d26eb9e7d11b35bba8366488513 Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Tue, 16 Feb 2021 22:55:15 -0300 Subject: [PATCH 4/4] doc: changed the detailed support table from Markdown to reStructuredText --- doc/intro.rst | 101 ++++++++++++++++++++++++++++++++------------------ 1 file changed, 64 insertions(+), 37 deletions(-) diff --git a/doc/intro.rst b/doc/intro.rst index 3aa2607b..db1d89d4 100644 --- a/doc/intro.rst +++ b/doc/intro.rst @@ -17,44 +17,71 @@ Introduction Detailed support ---------------- -| | ISE | Libero | Openflow | Quartus | Vivado | -|--- |:---: |:---: |:---: |:---: |:---: | -| **add_files** -| `vhdl` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | -| `verilog` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | -| `system_verilog` | `TBD` | `TBD` | `TBD` | `TBD` | `TBD` | -| `constraint` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | -| `block_design` | `NY` | `NY` | `NY` | `NY` | `Yes` | -| **set_param** -| `boolean` (*VHDL/Verilog*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | -| `integer` (*VHDL/Verilog*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | -| `string` (*VHDL/Verilog*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | -| `real` (*VHDL/Verilog*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | -| `std_logic` (*VHDL*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | -| `std_logic_vector` (*VHDL*) | `TBD` | `TBD` |`TBD` | `TBD` | `TBD` | -| **add_path** | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | -| **set_define** (*Verilog*) | `TBI` | `TBI` | `TBI` | `TBI` | `TBI` | -| **set_arch** (*VHDL*) | `TBI` | `TBI` | `TBI` | `TBI` | `TBI` | -| **generate** -| `prj` | `Yes` | `Yes` | `No` | `Yes` | `Yes` | -| `syn` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | -| `imp` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | -| `bit` | `Yes` | `Yes` | `Yes` | `Yes` | `Yes` | -| **transfer** -| `fpga` | `Yes` | `NY` | `Yes` | `Yes` | `Yes` | -| `spi` | `Yes` | `NY` | `NY` | `NY` | `NY` | -| `bpi` | `Yes` | `NY` | `NY` | `NY` | `NY` | -| `detect` | `Yes` | `NY` | `NY` | `Yes` | `Yes` | -| `unlock` | `Yes` | `No` | `No` | `No` | `No` | - -* `Yes`: already supported -* `No`: no plans (or unneeded) -* `NY`: Not yet, but maybe someday -* `TBD`: To Be Defined -* `TBI`: To Be Implemented ++------------------------------+---------+----------+------------+-----------+----------+ +| | ISE | Libero | Openflow | Quartus | Vivado | ++==============================+=========+==========+============+===========+==========+ +|**add_files** | | | | | | ++------------------------------+---------+----------+------------+-----------+----------+ +|``vhdl`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``verilog`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``system_verilog`` | ``TBD`` | ``TBD`` | ``TBD`` | ``TBD`` | ``TBD`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``constraint`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``block_design`` | ``NY`` | ``NY`` | ``NY`` | ``NY`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|**set_param** | | | | | | ++------------------------------+---------+----------+------------+-----------+----------+ +|``boolean`` (*VHDL/Verilog*) | ``TBD`` | ``TBD`` |``TBD`` | ``TBD`` | ``TBD`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``integer`` (*VHDL/Verilog*) | ``TBD`` | ``TBD`` |``TBD`` | ``TBD`` | ``TBD`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``string`` (*VHDL/Verilog*) | ``TBD`` | ``TBD`` |``TBD`` | ``TBD`` | ``TBD`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``real`` (*VHDL/Verilog*) | ``TBD`` | ``TBD`` |``TBD`` | ``TBD`` | ``TBD`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``std_logic`` (*VHDL*) | ``TBD`` | ``TBD`` |``TBD`` | ``TBD`` | ``TBD`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``std_logic_vector`` (*VHDL*) | ``TBD`` | ``TBD`` |``TBD`` | ``TBD`` | ``TBD`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|**add_path** | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|**set_define** (*Verilog*) | ``TBI`` | ``TBI`` | ``TBI`` | ``TBI`` | ``TBI`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|**set_arch** (*VHDL*) | ``TBI`` | ``TBI`` | ``TBI`` | ``TBI`` | ``TBI`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|**generate** | | | | | | ++------------------------------+---------+----------+------------+-----------+----------+ +|``prj`` | ``Yes`` | ``Yes`` | ``No`` | ``Yes`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``syn`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``imp`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``bit`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|**transfer** | | | | | | ++------------------------------+---------+----------+------------+-----------+----------+ +|``fpga`` | ``Yes`` | ``NY`` | ``Yes`` | ``Yes`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``spi`` | ``Yes`` | ``NY`` | ``NY`` | ``NY`` | ``NY`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``bpi`` | ``Yes`` | ``NY`` | ``NY`` | ``NY`` | ``NY`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``detect`` | ``Yes`` | ``NY`` | ``NY`` | ``Yes`` | ``Yes`` | ++------------------------------+---------+----------+------------+-----------+----------+ +|``unlock`` | ``Yes`` | ``No`` | ``No`` | ``No`` | ``No`` | ++------------------------------+---------+----------+------------+-----------+----------+ + +* ``Yes``: already supported +* ``No``: no plans (or unneeded) +* ``NY``: Not yet, but maybe someday +* ``TBD``: To Be Defined +* ``TBI``: To Be Implemented Next Steps ---------- -From here, you can read the :ref:`basic` and :ref:`advanced` sections, check -the detailed :ref:`api` or start with the available :repo:`Examples `. +You can read the :ref:`basic` and :ref:`advanced` sections, check the detailed :ref:`api` or start with the available :repo:`Examples `.