From f96bd2b16714ecac4d7005ca06e265fb45c6f0ce Mon Sep 17 00:00:00 2001 From: motty-mio2 Date: Fri, 19 Feb 2021 12:58:10 +0900 Subject: [PATCH 1/2] fix path error on windows --- fpga/project.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/fpga/project.py b/fpga/project.py index 5173d965..ea29f34f 100644 --- a/fpga/project.py +++ b/fpga/project.py @@ -200,7 +200,7 @@ def add_files(self, pathname, filetype=None, library=None, options=None): else: filetype = 'constraint' _log.debug('add_files: %s filetype detected', filetype) - file = os.path.relpath(file, self.outdir) + file = os.path.relpath(file, self.outdir).replace(os.path.sep, "/") self.tool.add_file(file, filetype, library, options) def get_files(self): From 6812029f3092fbdab854b3d129c2901ddbc1d51d Mon Sep 17 00:00:00 2001 From: Rodrigo Alejandro Melo Date: Fri, 19 Feb 2021 18:26:37 -0300 Subject: [PATCH 2/2] fpga: moved fix for Tcl paths in windows from project.py to tools --- fpga/project.py | 2 +- fpga/tool/__init__.py | 21 +++++++++++++-------- 2 files changed, 14 insertions(+), 9 deletions(-) diff --git a/fpga/project.py b/fpga/project.py index ea29f34f..5173d965 100644 --- a/fpga/project.py +++ b/fpga/project.py @@ -200,7 +200,7 @@ def add_files(self, pathname, filetype=None, library=None, options=None): else: filetype = 'constraint' _log.debug('add_files: %s filetype detected', filetype) - file = os.path.relpath(file, self.outdir).replace(os.path.sep, "/") + file = os.path.relpath(file, self.outdir) self.tool.add_file(file, filetype, library, options) def get_files(self): diff --git a/fpga/tool/__init__.py b/fpga/tool/__init__.py index f99130c0..8ff2783f 100644 --- a/fpga/tool/__init__.py +++ b/fpga/tool/__init__.py @@ -54,6 +54,11 @@ def run(command, capture): return result.stdout +def tcl_path(path): + """Returns a Tcl suitable path.""" + return path.replace(os.path.sep, "/") + + class Tool: """Tool interface. @@ -161,20 +166,20 @@ def _create_gen_script(self, tasks): files.append(' fpga_file {}.edif'.format(self.project)) else: for path in self.paths: - files.append(' fpga_include {}'.format(path)) + files.append(' fpga_include {}'.format(tcl_path(path))) for file in self.files['verilog']: - files.append(' fpga_file {}'.format(file[0])) + files.append(' fpga_file {}'.format(tcl_path(file[0]))) for file in self.files['vhdl']: if file[1] is None: - files.append(' fpga_file {}'.format(file[0])) + files.append(' fpga_file {}'.format(tcl_path(file[0]))) else: - files.append( - ' fpga_file {} {}'.format(file[0], file[1]) - ) + files.append(' fpga_file {} {}'.format( + tcl_path(file[0]), file[1] + )) for file in self.files['design']: - files.append(' fpga_design {}'.format(file[0])) + files.append(' fpga_design {}'.format(tcl_path(file[0]))) for file in self.files['constraint']: - files.append(' fpga_file {}'.format(file[0])) + files.append(' fpga_file {}'.format(tcl_path(file[0]))) # Parameters params = [] for param in self.params: