From 45c1c12d6fb7bc45c2deded33161fe3da294643f Mon Sep 17 00:00:00 2001
From: ryosuke fukatani <nannyakannya@gmail.com>
Date: Sat, 22 Aug 2015 17:39:44 +0900
Subject: [PATCH] Change behavior of walkey.makeTree for assign statement using
 partselect, and add test(test_partselect_assign.py). ex.   assign in1[2:1] =
 reg3[6:5];   always @(posedge CLK) begin     reg1 <= in1[2:1];   end

Previous makeTree:
TOP_reg3['d6:'d5]['d2]

However, this output recall the two -dimensional array , it is considered not to be appropriate.
Changed to:
TOP_reg3['d6]
---
 pyverilog/dataflow/dataflow.py                |  2 +
 pyverilog/dataflow/merge.py                   |  3 +
 pyverilog/dataflow/walker.py                  |  4 ++
 testcode/partselect_assign.v                  | 25 ++++++++
 tests/dataflow_test/test_partselect_assign.py | 59 +++++++++++++++++++
 5 files changed, 93 insertions(+)
 create mode 100644 testcode/partselect_assign.v
 create mode 100644 tests/dataflow_test/test_partselect_assign.py

diff --git a/pyverilog/dataflow/dataflow.py b/pyverilog/dataflow/dataflow.py
index 96b9e28..b7e7bdd 100644
--- a/pyverilog/dataflow/dataflow.py
+++ b/pyverilog/dataflow/dataflow.py
@@ -398,6 +398,8 @@ def tocode(self, dest='dest'):
     def children(self):
         nodelist = []
         return tuple(nodelist)
+    def eval(self):
+        return self.value
     def __eq__(self, other):
         if type(self) != type(other): return False
         return self.value == other.value and self.width == other.width and self.isfloat == other.isfloat and self.isstring == other.isstring
diff --git a/pyverilog/dataflow/merge.py b/pyverilog/dataflow/merge.py
index 2bb5e0f..6e9da5a 100644
--- a/pyverilog/dataflow/merge.py
+++ b/pyverilog/dataflow/merge.py
@@ -39,6 +39,9 @@ def __init__(self, topmodule, terms, binddict, resolved_terms, resolved_binddict
 
     ############################################################################
     def getTerm(self, termname):
+        if isinstance(termname, str):
+            for scope in self.terms.keys():
+                if termname == str(scope): return self.terms[scope]
         if not termname in self.terms: return None
         return self.terms[termname]
 
diff --git a/pyverilog/dataflow/walker.py b/pyverilog/dataflow/walker.py
index d25250c..439a6a6 100644
--- a/pyverilog/dataflow/walker.py
+++ b/pyverilog/dataflow/walker.py
@@ -107,6 +107,10 @@ def walkTree(self, tree, visited=set([]), step=0, delay=False, msb=None, lsb=Non
             msb = self.walkTree(tree.msb, visited, step, delay)
             lsb = self.walkTree(tree.lsb, visited, step, delay)
             var = self.walkTree(tree.var, visited, step, delay, msb=msb, lsb=lsb)
+            if isinstance(var, DFPartselect):
+                child_lsb = self.getTerm(str(tree.var)).lsb.eval()
+                return DFPartselect(var.var, DFIntConst(str(msb.eval() + var.lsb.eval() - child_lsb)),
+                                    DFIntConst(str(lsb.eval() + var.lsb.eval() - child_lsb)))
             return DFPartselect(var, msb, lsb)
 
         if isinstance(tree, DFPointer):
diff --git a/testcode/partselect_assign.v b/testcode/partselect_assign.v
new file mode 100644
index 0000000..5579213
--- /dev/null
+++ b/testcode/partselect_assign.v
@@ -0,0 +1,25 @@
+module TOP(CLK, RST, reg1, OUT);
+  input CLK, RST;
+  reg [1:0] reg1;
+  reg [6:4] reg3;
+  wire [2:1] in1;
+  wire [11:10] in2;
+
+
+  assign in1[2:1] = reg3[6:5];
+
+  always @(posedge CLK or negedge RST) begin
+    reg1 <= in1[2:1];
+  end
+
+  always @(posedge CLK or negedge RST) begin
+    if(RST) begin
+      reg3 <= 3'd0;
+    end else begin
+      reg3 <= 3'd1;
+    end
+  end
+
+endmodule
+
+
diff --git a/tests/dataflow_test/test_partselect_assign.py b/tests/dataflow_test/test_partselect_assign.py
new file mode 100644
index 0000000..880abb6
--- /dev/null
+++ b/tests/dataflow_test/test_partselect_assign.py
@@ -0,0 +1,59 @@
+import os
+import sys
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.dirname(os.path.abspath(__file__)))) )
+from pyverilog.dataflow.dataflow_analyzer import VerilogDataflowAnalyzer
+from pyverilog.dataflow.optimizer import VerilogDataflowOptimizer
+from pyverilog.controlflow.controlflow_analyzer import VerilogControlflowAnalyzer
+codedir = '../../testcode/'
+
+expected = """\
+TOP.RST: TOP_RST
+TOP.reg1: TOP_reg3['d6:'d5]
+TOP.in2: TOP_in2
+TOP.CLK: TOP_CLK
+TOP.reg3: ((TOP_RST)? 3'd0 : 3'd1)
+TOP.in1: TOP_reg3['d6:'d5]
+"""
+
+def test():
+    filelist = [codedir + 'partselect_assign.v']
+    topmodule = 'TOP'
+    noreorder = False
+    nobind = False
+    include = None
+    define = None
+
+    analyzer = VerilogDataflowAnalyzer(filelist, topmodule,
+                                       noreorder=noreorder,
+                                       nobind=nobind,
+                                       preprocess_include=include,
+                                       preprocess_define=define)
+    analyzer.generate()
+
+    directives = analyzer.get_directives()
+    instances = analyzer.getInstances()
+    terms = analyzer.getTerms()
+    binddict = analyzer.getBinddict()
+
+    optimizer = VerilogDataflowOptimizer(terms, binddict)
+    optimizer.resolveConstant()
+
+    c_analyzer = VerilogControlflowAnalyzer(topmodule, terms,
+                                            binddict,
+                                            resolved_terms=optimizer.getResolvedTerms(),
+                                            resolved_binddict=optimizer.getResolvedBinddict(),
+                                            constlist=optimizer.getConstlist()
+                                            )
+
+    output = []
+    for tk in sorted(c_analyzer.resolved_terms.keys(), key=lambda x:str(x[0])):
+        tree = c_analyzer.makeTree(tk)
+        output.append(str(tk) + ': ' + tree.tocode())
+
+    rslt = '\n'.join(output) + '\n'
+
+    print(rslt)
+    assert(rslt == expected)
+
+if __name__ == '__main__':
+    test()