From 454704a235f5aeb0502f7b02c1a3ab5de95a2aa9 Mon Sep 17 00:00:00 2001
From: ryosuke fukatani <nannyakannya@gmail.com>
Date: Sun, 5 Apr 2015 21:57:10 +0900
Subject: [PATCH] modify bug: '([0-9]*\'s(d?))?[0-9][0-9_]*'  treat as unsigned
 decimal. (Because 's' is omitted in  this presentation.)

---
 pyverilog/testcode/decimal.v  | 19 +++++++++++++++++++
 pyverilog/testcode/decimal2.v | 18 ++++++++++++++++++
 pyverilog/testcode/test_sd.py | 11 +++++++++++
 pyverilog/vparser/lexer.py    |  2 +-
 4 files changed, 49 insertions(+), 1 deletion(-)
 create mode 100644 pyverilog/testcode/decimal.v
 create mode 100644 pyverilog/testcode/decimal2.v

diff --git a/pyverilog/testcode/decimal.v b/pyverilog/testcode/decimal.v
new file mode 100644
index 0000000..7ee263f
--- /dev/null
+++ b/pyverilog/testcode/decimal.v
@@ -0,0 +1,19 @@
+//`default_nettype none
+
+module TOP(CLK, RST);
+  input CLK, RST;
+  reg [7:0] cnt1;
+
+
+  always @(posedge CLK or negedge RST) begin
+    if(RST) begin
+      cnt1 <= 'd0;
+    end else begin
+      cnt1 <= cnt1 + 8'd1;
+    end
+  end
+
+
+
+endmodule
+
diff --git a/pyverilog/testcode/decimal2.v b/pyverilog/testcode/decimal2.v
new file mode 100644
index 0000000..4924210
--- /dev/null
+++ b/pyverilog/testcode/decimal2.v
@@ -0,0 +1,18 @@
+//`default_nettype none
+
+module TOP(CLK, RST);
+  input CLK, RST;
+  reg [7:0] cnt2;
+
+
+  always @(posedge CLK or negedge RST) begin
+    if(RST) begin
+      cnt2 <= 'd0;
+    end else begin
+      cnt2 <= cnt2 + 'd1;
+    end
+  end
+
+
+endmodule
+
diff --git a/pyverilog/testcode/test_sd.py b/pyverilog/testcode/test_sd.py
index a02b5cf..022c93d 100644
--- a/pyverilog/testcode/test_sd.py
+++ b/pyverilog/testcode/test_sd.py
@@ -40,6 +40,17 @@ def test_signed_task(self):
     def test_casex(self):
         self.dataflow_wrapper("casex.v")
 
+    def test_decimal(self):
+        terms, binddict = self.dataflow_wrapper("decimal.v")
+        self.assertEqual(binddict.values()[0][0].tostr(),
+        "(Bind dest:TOP.cnt1 tree:(Branch Cond:(Terminal TOP.RST) True:(IntConst 'd0) False:(Operator Plus Next:(Terminal TOP.cnt1),(IntConst 8'd1))))")
+
+    def test_decimal2(self):
+        terms, binddict = self.dataflow_wrapper("decimal2.v")
+        self.assertEqual(binddict.values()[0][0].tostr(),
+        "(Bind dest:TOP.cnt2 tree:(Branch Cond:(Terminal TOP.RST) True:(IntConst 'd0) False:(Operator Plus Next:(Terminal TOP.cnt2),(IntConst 'd1))))")
+
+
     def dataflow_wrapper(self,code_file):
 
         from optparse import OptionParser
diff --git a/pyverilog/vparser/lexer.py b/pyverilog/vparser/lexer.py
index 536404a..b7b2f70 100644
--- a/pyverilog/vparser/lexer.py
+++ b/pyverilog/vparser/lexer.py
@@ -181,7 +181,7 @@ def t_COMMENTOUT(self, t):
     signed_hex_number = '[0-9]*\'sh[0-9a-fA-Fxz][0-9a-fA-Fxz_]*'
 
     decimal_number = '[0-9]*\'d[0-9xz][0-9xz_]*' + '|' + '([0-9]*\'d)?[0-9][0-9_]*'
-    signed_decimal_number = '[0-9]*\'s(d?)[0-9xz][0-9xz_]*' + '|' + '([0-9]*\'s(d?))?[0-9][0-9_]*'
+    signed_decimal_number = '[0-9]*\'s(d?)[0-9xz][0-9xz_]*'
 
     exponent_part = r"""([eE][-+]?[0-9]+)"""
     fractional_constant = r"""([0-9]*\.[0-9]+)|([0-9]+\.)"""