From 92ae5efd04ca745d3993345ca3357ab423852437 Mon Sep 17 00:00:00 2001 From: Yasuhiro Nitta Date: Fri, 24 Apr 2020 17:27:42 +0900 Subject: [PATCH 1/6] add interval option to Counter #54 --- veriloggen/stream/stypes.py | 50 ++++++++++++++++++++++++++++++------- 1 file changed, 41 insertions(+), 9 deletions(-) diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py index 0f10575c..393874da 100644 --- a/veriloggen/stream/stypes.py +++ b/veriloggen/stream/stypes.py @@ -2398,7 +2398,7 @@ class _Accumulator(_UnaryOperator): latency = 1 ops = (vtypes.Plus, ) - def __init__(self, right, size=None, initval=None, + def __init__(self, right, size=None, initval=None, interval=None, enable=None, reset=None, width=32, signed=True): self.size = _to_constant(size) if size is not None else None @@ -2408,6 +2408,8 @@ def __init__(self, right, size=None, initval=None, if not isinstance(self.initval, _Constant): raise TypeError("initval must be Constant, not '%s'" % str(type(self.initval))) + + self.interval = interval self.enable = _to_constant(enable) if self.enable is not None: @@ -2442,6 +2444,8 @@ def _implement(self, m, seq, svalid=None, senable=None): (self.latency, 1)) size_data = self.size.sig_data if self.size is not None else None + if self.size is not None and self.interval is not None: + size_data *= self.interval initval_data = self.initval.sig_data width = self.bit_length() @@ -2460,6 +2464,11 @@ def _implement(self, m, seq, svalid=None, senable=None): next_count_value = vtypes.Mux(count >= size_data - 1, 0, count + 1) count_zero = (count == 0) + + if self.interval is not None: + interval_count = m.Reg(self.name('interval_count'), width, initval=0) + next_interval_count = vtypes.Mux(interval_count >= self.interval - 1, 0, interval_count + 1) + interval_enable = (interval_count == 0) self.sig_data = data @@ -2484,7 +2493,9 @@ def _implement(self, m, seq, svalid=None, senable=None): if not self.ops and self.size is not None: value = (count >= (size_data - 1)) - if self.reset is not None or self.size is not None: + reset_value = initval_data + if self.size is not None: + # if self.reset is not None or self.size is not None: reset_value = initval_data for op in self.ops: if not isinstance(op, type): @@ -2502,24 +2513,43 @@ def _implement(self, m, seq, svalid=None, senable=None): reset_value = (count >= (size_data - 1)) if self.enable is not None: - enable_cond = _and_vars(svalid, senable, enabledata) - seq(data(value), cond=enable_cond) + if self.interval is not None: + enable_cond = _and_vars(svalid, senable, enabledata, interval_enable) + seq(data(value), cond = enable_cond) + else: + enable_cond = _and_vars(svalid, senable, enabledata) + seq(data(value), cond = enable_cond) + enable_cond = _and_vars(svalid, senable, enabledata) if self.size is not None: seq(count(next_count_value), cond=enable_cond) + if self.interval is not None: + seq(interval_count(next_interval_count), cond=enable_cond) + else: + if self.interval is not None: + enable_cond = _and_vars(svalid, senable, interval_enable) + seq(data(value), cond = enable_cond) + else: + enable_cond = _and_vars(svalid, senable) + seq(data(value), cond = enable_cond) + enable_cond = _and_vars(svalid, senable) - seq(data(value), cond=enable_cond) if self.size is not None: seq(count(next_count_value), cond=enable_cond) + + if self.interval is not None: + seq(interval_count(next_interval_count), cond=enable_cond) if self.reset is not None: if self.enable is None: reset_cond = _and_vars(svalid, senable, resetdata) seq(data(reset_value), cond=reset_cond) - + + if self.interval is not None: + seq(interval_count(0), cond=reset_cond) if self.size is not None: seq(count(0), cond=reset_cond) reset_cond = _and_vars(svalid, senable, count_zero) @@ -2533,6 +2563,8 @@ def _implement(self, m, seq, svalid=None, senable=None): svalid, senable, enabledata, resetdata) seq(data(reset_value), cond=reset_enable_cond) + if self.interval is not None: + seq(interval_count(0), cond=reset_enable_cond) if self.size is not None: seq(count(0), cond=reset_enable_cond) reset_enable_cond = _and_vars( @@ -2602,7 +2634,7 @@ def __init__(self, ops, right, size=None, initval=0, class Counter(_Accumulator): - def __init__(self, size=None, step=1, initval=0, + def __init__(self, size=None, step=1, initval=0, interval=1, control=None, enable=None, reset=None, width=32, signed=False): self.ops = (lambda x, y: x + step, ) @@ -2612,7 +2644,7 @@ def __init__(self, size=None, step=1, initval=0, initval -= step - _Accumulator.__init__(self, control, size, initval, + _Accumulator.__init__(self, control, size, initval, interval, enable, reset, width, signed) self.graph_label = 'Counter' @@ -2687,7 +2719,7 @@ def ReduceCustomValid(ops, right, size, initval=0, return data, valid -def CounterValid(size, step=1, initval=0, +def CounterValid(size, step=1, initval=None, control=None, enable=None, reset=None, width=32, signed=False): data = Counter(size, step, initval, From 8d4fd791b10b6b8dbf53139c1fd311fe3fba8830 Mon Sep 17 00:00:00 2001 From: Yasuhiro Nitta Date: Fri, 24 Apr 2020 17:30:41 +0900 Subject: [PATCH 2/6] update counter test with interval #54 --- .../stream_counter/thread_stream_counter.py | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/tests/extension/thread_/stream_counter/thread_stream_counter.py b/tests/extension/thread_/stream_counter/thread_stream_counter.py index 48f35795..f0ec4069 100644 --- a/tests/extension/thread_/stream_counter/thread_stream_counter.py +++ b/tests/extension/thread_/stream_counter/thread_stream_counter.py @@ -25,10 +25,15 @@ def mkLed(): ram_c = vthread.RAM(m, 'ram_c', clk, rst, datawidth, addrwidth) strm = vthread.Stream(m, 'mystream', clk, rst) - cnt = strm.Counter() + cnt1 = strm.Counter() + cnt2 = strm.Counter(initval=1) + cnt3 = strm.Counter(initval=2, size=3) + cnt4 = strm.Counter(initval=3, interval=3) + cnt5 = strm.Counter(initval=4, interval=3, size=4) + cnt6 = strm.Counter(initval=4, step=2, interval=2) a = strm.source('a') b = strm.source('b') - c = a + b + cnt + c = a + b - a - b + cnt1 + cnt2 + cnt3 + cnt4 + cnt5 + cnt6 strm.sink(c, 'c') def comp_stream(size, offset): @@ -39,14 +44,19 @@ def comp_stream(size, offset): strm.join() def comp_sequential(size, offset): - sum = 0 cnt = 0 for i in range(size): + cnt1 = cnt + cnt2 = 1 + cnt + cnt3 = cnt%3 + 2 + cnt4 = (cnt//3) + 3 + cnt5 = (cnt//3)%4 + 4 + cnt6 = (cnt//2)*2 + 4 a = ram_a.read(i + offset) b = ram_b.read(i + offset) - cnt += 1 - sum = a + b + cnt + sum = a + b - a - b + cnt1 + cnt2 + cnt3 + cnt4 + cnt5 + cnt6 ram_c.write(i + offset, sum) + cnt += 1 def check(size, offset_stream, offset_seq): all_ok = True From 7c42e1d9b1b9ec174a2b8a92b2420efb1de79de2 Mon Sep 17 00:00:00 2001 From: Yasuhiro Nitta Date: Fri, 24 Apr 2020 18:19:08 +0900 Subject: [PATCH 3/6] expand size*interval product value to reduce bit length #54 --- veriloggen/stream/stypes.py | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py index 393874da..ad426e97 100644 --- a/veriloggen/stream/stypes.py +++ b/veriloggen/stream/stypes.py @@ -2401,15 +2401,15 @@ class _Accumulator(_UnaryOperator): def __init__(self, right, size=None, initval=None, interval=None, enable=None, reset=None, width=32, signed=True): - self.size = _to_constant(size) if size is not None else None + self.interval = _to_constant(interval) if interval is not None else None + self.size = (_to_constant(size * interval) if size is not None and interval is not None + else (_to_constant(size) if size is not None else None)) self.initval = (_to_constant(initval) if initval is not None else _to_constant(0)) if not isinstance(self.initval, _Constant): raise TypeError("initval must be Constant, not '%s'" % str(type(self.initval))) - - self.interval = interval self.enable = _to_constant(enable) if self.enable is not None: @@ -2444,8 +2444,9 @@ def _implement(self, m, seq, svalid=None, senable=None): (self.latency, 1)) size_data = self.size.sig_data if self.size is not None else None - if self.size is not None and self.interval is not None: - size_data *= self.interval + interval_data = self.interval.sig_data if self.interval is not None else None + # if self.size is not None and self.interval is not None: + # size_data *= self.interval initval_data = self.initval.sig_data width = self.bit_length() @@ -2467,7 +2468,7 @@ def _implement(self, m, seq, svalid=None, senable=None): if self.interval is not None: interval_count = m.Reg(self.name('interval_count'), width, initval=0) - next_interval_count = vtypes.Mux(interval_count >= self.interval - 1, 0, interval_count + 1) + next_interval_count = vtypes.Mux(interval_count >= interval_data - 1, 0, interval_count + 1) interval_enable = (interval_count == 0) self.sig_data = data From 7aaed39184abea99d9fd8a03da2ca15bdf521740 Mon Sep 17 00:00:00 2001 From: Yasuhiro Nitta Date: Fri, 24 Apr 2020 18:21:16 +0900 Subject: [PATCH 4/6] remove unnecessary line --- veriloggen/stream/stypes.py | 2 -- 1 file changed, 2 deletions(-) diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py index ad426e97..87ea9b5e 100644 --- a/veriloggen/stream/stypes.py +++ b/veriloggen/stream/stypes.py @@ -2445,8 +2445,6 @@ def _implement(self, m, seq, svalid=None, senable=None): size_data = self.size.sig_data if self.size is not None else None interval_data = self.interval.sig_data if self.interval is not None else None - # if self.size is not None and self.interval is not None: - # size_data *= self.interval initval_data = self.initval.sig_data width = self.bit_length() From a06e16872988ea61c04b985734d67109733bfde1 Mon Sep 17 00:00:00 2001 From: Yasuhiro Nitta Date: Mon, 27 Apr 2020 13:12:25 +0900 Subject: [PATCH 5/6] support interval option in derived class of _Accumulator #54 --- veriloggen/stream/stypes.py | 38 ++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py index 87ea9b5e..b37c9266 100644 --- a/veriloggen/stream/stypes.py +++ b/veriloggen/stream/stypes.py @@ -2583,9 +2583,9 @@ def _implement(self, m, seq, svalid=None, senable=None): class ReduceAdd(_Accumulator): ops = (vtypes.Plus, ) - def __init__(self, right, size=None, initval=0, + def __init__(self, right, size=None, initval=0, interval=None, enable=None, reset=None, width=32, signed=True): - _Accumulator.__init__(self, right, size, initval, + _Accumulator.__init__(self, right, size, initval, interval, enable, reset, width, signed) @@ -2633,7 +2633,7 @@ def __init__(self, ops, right, size=None, initval=0, class Counter(_Accumulator): - def __init__(self, size=None, step=1, initval=0, interval=1, + def __init__(self, size=None, step=1, initval=0, interval=None, control=None, enable=None, reset=None, width=32, signed=False): self.ops = (lambda x, y: x + step, ) @@ -2651,7 +2651,7 @@ def __init__(self, size=None, step=1, initval=0, interval=1, class Pulse(_Accumulator): ops = () - def __init__(self, size, control=None, enable=None, reset=None): + def __init__(self, size, control=None, enable=None, reset=None, interval=None): if control is None: control = 0 @@ -2661,67 +2661,67 @@ def __init__(self, size, control=None, enable=None, reset=None): width = 1 signed = False - _Accumulator.__init__(self, control, size, initval, + _Accumulator.__init__(self, control, size, initval, interval, enable, reset, width, signed) self.graph_label = 'Pulse' -def _ReduceValid(cls, right, size, initval=0, +def _ReduceValid(cls, right, size, initval=0, interval=None, enable=None, reset=None, width=32, signed=True): - data = cls(right, size, initval, + data = cls(right, size, initval, interval, enable, reset, width, signed) valid = Pulse(size, right, enable, reset) return data, valid -def ReduceAddValid(right, size, initval=0, +def ReduceAddValid(right, size, initval=0, interval=None, enable=None, reset=None, width=32, signed=True): cls = ReduceAdd - return _ReduceValid(cls, right, size, initval, + return _ReduceValid(cls, right, size, initval, interval, enable, reset, width, signed) -def ReduceSubValid(right, size, initval=0, +def ReduceSubValid(right, size, initval=0, interval=None, enable=None, reset=None, width=32, signed=True): cls = ReduceSub - return _ReduceValid(cls, right, size, initval, + return _ReduceValid(cls, right, size, initval, interval, enable, reset, width, signed) -def ReduceMulValid(right, size, initval=0, +def ReduceMulValid(right, size, initval=0, interval=None, enable=None, reset=None, width=32, signed=True): cls = ReduceMul - return _ReduceValid(cls, right, size, initval, + return _ReduceValid(cls, right, size, initval, interval, enable, reset, width, signed) -def ReduceDivValid(right, size, initval=0, +def ReduceDivValid(right, size, initval=0, interval=None, enable=None, reset=None, width=32, signed=True): cls = ReduceDiv - return _ReduceValid(cls, right, size, initval, + return _ReduceValid(cls, right, size, initval, interval, enable, reset, width, signed) -def ReduceCustomValid(ops, right, size, initval=0, +def ReduceCustomValid(ops, right, size, initval=0, interval=None, enable=None, reset=None, width=32, signed=True): - data = ReduceCustom(ops, right, size, initval, + data = ReduceCustom(ops, right, size, initval, interval, enable, reset, width, signed) valid = Pulse(size, right, enable, reset) return data, valid -def CounterValid(size, step=1, initval=None, +def CounterValid(size, step=1, initval=0, interval=None, control=None, enable=None, reset=None, width=32, signed=False): - data = Counter(size, step, initval, + data = Counter(size, step, initval, interval, control, enable, reset, width, signed) valid = Pulse(size, control, enable, reset) From c7a4d8a37b26be919acf9f4b238f9f741399517e Mon Sep 17 00:00:00 2001 From: Yasuhiro Nitta Date: Mon, 27 Apr 2020 13:15:11 +0900 Subject: [PATCH 6/6] apply 0-origin counter index to existing test --- .../thread_stream_graph_ringbuffer_multi.py | 2 +- .../thread_stream_graph_scratchpad_multi.py | 4 ++-- .../thread_/stream_ringbuffer/thread_stream_ringbuffer.py | 2 +- .../thread_stream_ringbuffer_multi.py | 2 +- .../thread_stream_ringbuffer_reuse.py | 2 +- .../thread_/stream_scratchpad/thread_stream_scratchpad.py | 6 +++--- .../thread_stream_scratchpad_multi.py | 4 ++-- .../thread_stream_scratchpad_when.py | 6 +++--- .../thread_/stream_write_ram/thread_stream_write_ram.py | 8 ++++---- .../stream_write_ram_dump/thread_stream_write_ram_dump.py | 8 ++++---- 10 files changed, 22 insertions(+), 22 deletions(-) diff --git a/tests/extension/thread_/stream_graph_ringbuffer_multi/thread_stream_graph_ringbuffer_multi.py b/tests/extension/thread_/stream_graph_ringbuffer_multi/thread_stream_graph_ringbuffer_multi.py index 070be5cd..2c4756e1 100644 --- a/tests/extension/thread_/stream_graph_ringbuffer_multi/thread_stream_graph_ringbuffer_multi.py +++ b/tests/extension/thread_/stream_graph_ringbuffer_multi/thread_stream_graph_ringbuffer_multi.py @@ -46,7 +46,7 @@ def mkLed(): #b = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8 b = strm.AddN(a0, a1, a2, a3, a4, a5, a6, a7, a8) - strm.sink(b, 'b', when=counter > img_width + img_width + 2) + strm.sink(b, 'b', when=counter >= img_width + img_width + 2) def comp_stream(size, offset): strm.set_source('a', ram_a, offset, size * 3) diff --git a/tests/extension/thread_/stream_graph_scratchpad_multi/thread_stream_graph_scratchpad_multi.py b/tests/extension/thread_/stream_graph_scratchpad_multi/thread_stream_graph_scratchpad_multi.py index a6112a34..8b1ed62d 100644 --- a/tests/extension/thread_/stream_graph_scratchpad_multi/thread_stream_graph_scratchpad_multi.py +++ b/tests/extension/thread_/stream_graph_scratchpad_multi/thread_stream_graph_scratchpad_multi.py @@ -29,7 +29,7 @@ def mkLed(): counter = strm.Counter() a = strm.source('a') - a_addr = strm.Counter() - 1 + a_addr = strm.Counter() sp = strm.Scratchpad(a, a_addr, length=128) a0 = a @@ -49,7 +49,7 @@ def mkLed(): #b = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8 b = strm.AddN(a0, a1, a2, a3, a4, a5, a6, a7, a8) - strm.sink(b, 'b', when=counter > img_width + img_width + 2) + strm.sink(b, 'b', when=counter >= img_width + img_width + 2) def comp_stream(size, offset): strm.set_source('a', ram_a, offset, size * 3) diff --git a/tests/extension/thread_/stream_ringbuffer/thread_stream_ringbuffer.py b/tests/extension/thread_/stream_ringbuffer/thread_stream_ringbuffer.py index 57869065..e3c3e44c 100644 --- a/tests/extension/thread_/stream_ringbuffer/thread_stream_ringbuffer.py +++ b/tests/extension/thread_/stream_ringbuffer/thread_stream_ringbuffer.py @@ -35,7 +35,7 @@ def mkLed(): b = a + a_old - strm.sink(b, 'b', when=counter > img_width) + strm.sink(b, 'b', when=counter >= img_width) def comp_stream(size, offset): strm.set_source('a', ram_a, offset, size * 2) diff --git a/tests/extension/thread_/stream_ringbuffer_multi/thread_stream_ringbuffer_multi.py b/tests/extension/thread_/stream_ringbuffer_multi/thread_stream_ringbuffer_multi.py index b124aac0..dd0439ce 100644 --- a/tests/extension/thread_/stream_ringbuffer_multi/thread_stream_ringbuffer_multi.py +++ b/tests/extension/thread_/stream_ringbuffer_multi/thread_stream_ringbuffer_multi.py @@ -46,7 +46,7 @@ def mkLed(): #b = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8 b = strm.AddN(a0, a1, a2, a3, a4, a5, a6, a7, a8) - strm.sink(b, 'b', when=counter > img_width + img_width + 2) + strm.sink(b, 'b', when=counter >= img_width + img_width + 2) def comp_stream(size, offset): strm.set_source('a', ram_a, offset, size * 3) diff --git a/tests/extension/thread_/stream_ringbuffer_reuse/thread_stream_ringbuffer_reuse.py b/tests/extension/thread_/stream_ringbuffer_reuse/thread_stream_ringbuffer_reuse.py index 1adeff87..e4acb8f1 100644 --- a/tests/extension/thread_/stream_ringbuffer_reuse/thread_stream_ringbuffer_reuse.py +++ b/tests/extension/thread_/stream_ringbuffer_reuse/thread_stream_ringbuffer_reuse.py @@ -36,7 +36,7 @@ def mkLed(): b = a + a_old - strm.sink(b, 'b', when=counter > wait_num) + strm.sink(b, 'b', when=counter >= wait_num) def comp_stream(size, offset): strm.set_source('a', ram_a, offset, size * 2) diff --git a/tests/extension/thread_/stream_scratchpad/thread_stream_scratchpad.py b/tests/extension/thread_/stream_scratchpad/thread_stream_scratchpad.py index 1b11b7a4..e7b6b7ae 100644 --- a/tests/extension/thread_/stream_scratchpad/thread_stream_scratchpad.py +++ b/tests/extension/thread_/stream_scratchpad/thread_stream_scratchpad.py @@ -29,16 +29,16 @@ def mkLed(): counter = strm.Counter() a = strm.source('a') - a_addr = strm.Counter() - 1 + a_addr = strm.Counter() sp = strm.Scratchpad(a, a_addr, length=128) - a_old_addr = strm.Counter() - img_width - 1 + a_old_addr = strm.Counter() - img_width a_old = sp.read(a_old_addr) b = a + a_old - strm.sink(b, 'b', when=counter > img_width) + strm.sink(b, 'b', when=counter >= img_width) def comp_stream(size, offset): strm.set_source('a', ram_a, offset, size * 2) diff --git a/tests/extension/thread_/stream_scratchpad_multi/thread_stream_scratchpad_multi.py b/tests/extension/thread_/stream_scratchpad_multi/thread_stream_scratchpad_multi.py index ad8e7e2c..83188f6c 100644 --- a/tests/extension/thread_/stream_scratchpad_multi/thread_stream_scratchpad_multi.py +++ b/tests/extension/thread_/stream_scratchpad_multi/thread_stream_scratchpad_multi.py @@ -29,7 +29,7 @@ def mkLed(): counter = strm.Counter() a = strm.source('a') - a_addr = strm.Counter() - 1 + a_addr = strm.Counter() sp = strm.Scratchpad(a, a_addr, length=128) a0 = a @@ -49,7 +49,7 @@ def mkLed(): #b = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7 + a8 b = strm.AddN(a0, a1, a2, a3, a4, a5, a6, a7, a8) - strm.sink(b, 'b', when=counter > img_width + img_width + 2) + strm.sink(b, 'b', when=counter >= img_width + img_width + 2) def comp_stream(size, offset): strm.set_source('a', ram_a, offset, size * 3) diff --git a/tests/extension/thread_/stream_scratchpad_when/thread_stream_scratchpad_when.py b/tests/extension/thread_/stream_scratchpad_when/thread_stream_scratchpad_when.py index 83319f50..348e1a70 100644 --- a/tests/extension/thread_/stream_scratchpad_when/thread_stream_scratchpad_when.py +++ b/tests/extension/thread_/stream_scratchpad_when/thread_stream_scratchpad_when.py @@ -29,16 +29,16 @@ def mkLed(): counter = strm.Counter() a = strm.source('a') - a_addr = strm.Counter() - 1 + a_addr = strm.Counter() sp = strm.Scratchpad(a, a_addr, when=counter <= img_width, length=128) - a_old_addr = strm.Counter() - img_width - 1 + a_old_addr = strm.Counter() - img_width a_old = sp.read(a_old_addr) b = a + a_old - strm.sink(b, 'b', when=counter > img_width) + strm.sink(b, 'b', when=counter >= img_width) def comp_stream(size, offset): strm.set_source('a', ram_a, offset, size * 2) diff --git a/tests/extension/thread_/stream_write_ram/thread_stream_write_ram.py b/tests/extension/thread_/stream_write_ram/thread_stream_write_ram.py index 7395d76c..4aa3bfd5 100644 --- a/tests/extension/thread_/stream_write_ram/thread_stream_write_ram.py +++ b/tests/extension/thread_/stream_write_ram/thread_stream_write_ram.py @@ -31,16 +31,16 @@ def mkLed(): counter = strm.Counter() a = strm.source('a') - a_addr = strm.Counter() - 1 + a_addr = strm.Counter() - strm.write_RAM('write_ext', a_addr, a, when=counter <= img_width) + strm.write_RAM('write_ext', a_addr, a, when=counter < img_width) - a_old_addr = strm.Counter() - img_width - 1 + a_old_addr = strm.Counter() - img_width a_old = strm.read_RAM('read_ext', a_old_addr) b = a + a_old - strm.sink(b, 'b', when=counter > img_width) + strm.sink(b, 'b', when=counter >= img_width) def comp_stream(size, offset): strm.set_source('a', ram_a, offset, size * 2) diff --git a/tests/extension/thread_/stream_write_ram_dump/thread_stream_write_ram_dump.py b/tests/extension/thread_/stream_write_ram_dump/thread_stream_write_ram_dump.py index f380b5e8..f560ac28 100644 --- a/tests/extension/thread_/stream_write_ram_dump/thread_stream_write_ram_dump.py +++ b/tests/extension/thread_/stream_write_ram_dump/thread_stream_write_ram_dump.py @@ -32,16 +32,16 @@ def mkLed(): counter = strm.Counter() a = strm.source('a') - a_addr = strm.Counter() - 1 + a_addr = strm.Counter() - strm.write_RAM('write_ext', a_addr, a, when=counter <= img_width) + strm.write_RAM('write_ext', a_addr, a, when=counter < img_width) - a_old_addr = strm.Counter() - img_width - 1 + a_old_addr = strm.Counter() - img_width a_old = strm.read_RAM('read_ext', a_old_addr) b = a + a_old - strm.sink(b, 'b', when=counter > img_width) + strm.sink(b, 'b', when=counter >= img_width) def comp_stream(size, offset): strm.set_source('a', ram_a, offset, size * 2)