From dc84070c663b8ca6a066207968ef29774052a945 Mon Sep 17 00:00:00 2001 From: Yasuhiro Nitta Date: Thu, 30 Apr 2020 17:56:20 +0900 Subject: [PATCH] modify bug in readRAM when latency = 2 --- veriloggen/stream/stypes.py | 1 + 1 file changed, 1 insertion(+) diff --git a/veriloggen/stream/stypes.py b/veriloggen/stream/stypes.py index b2dc92af..b3e28c32 100644 --- a/veriloggen/stream/stypes.py +++ b/veriloggen/stream/stypes.py @@ -3505,6 +3505,7 @@ def _implement(self, m, seq, svalid=None, senable=None): if self.latency == 2: data = m.Wire(self.name('data'), datawidth, signed=signed) + data.assign(rdata) self.sig_data = data elif self.latency == 3: