diff --git a/cpu/stm32l0/vectors.c b/cpu/stm32l0/vectors.c index 17e1e50c51a8..7b10e35597f9 100644 --- a/cpu/stm32l0/vectors.c +++ b/cpu/stm32l0/vectors.c @@ -20,12 +20,8 @@ * @} */ -#include #include "vectors_cortexm.h" -/* get the start of the ISR stack as defined in the linkerscript */ -extern uint32_t _estack; - /* define a local dummy handler as it needs to be in the same compilation unit * as the alias definition */ void dummy_handler(void) { @@ -33,119 +29,99 @@ void dummy_handler(void) { } /* STM32L0 specific interrupt vectors */ -WEAK_DEFAULT void isr_wwdg(void); -WEAK_DEFAULT void isr_pvd(void); -WEAK_DEFAULT void isr_rtc(void); -WEAK_DEFAULT void isr_flash(void); -WEAK_DEFAULT void isr_rcc(void); -WEAK_DEFAULT void isr_exti(void); -WEAK_DEFAULT void isr_ts(void); -WEAK_DEFAULT void isr_dma1_ch1(void); -WEAK_DEFAULT void isr_dma1_ch2_3(void); -WEAK_DEFAULT void isr_dma1_ch4_5_6_7(void); WEAK_DEFAULT void isr_adc1_comp(void); +WEAK_DEFAULT void isr_dma1_channel1(void); +WEAK_DEFAULT void isr_dma1_channel2_3(void); +WEAK_DEFAULT void isr_dma1_channel4_5_6_7(void); +WEAK_DEFAULT void isr_exti(void); +WEAK_DEFAULT void isr_flash(void); +WEAK_DEFAULT void isr_i2c1(void); +WEAK_DEFAULT void isr_i2c2(void); +WEAK_DEFAULT void isr_i2c3(void); +WEAK_DEFAULT void isr_lcd(void); WEAK_DEFAULT void isr_lptim1(void); -WEAK_DEFAULT void isr_usart4_5(void); +WEAK_DEFAULT void isr_lpuart1(void); +WEAK_DEFAULT void isr_pvd(void); +WEAK_DEFAULT void isr_rcc(void); +WEAK_DEFAULT void isr_rcc_crs(void); +WEAK_DEFAULT void isr_rng_lpuart1(void); +WEAK_DEFAULT void isr_rtc(void); +WEAK_DEFAULT void isr_spi1(void); +WEAK_DEFAULT void isr_spi2(void); WEAK_DEFAULT void isr_tim2(void); +WEAK_DEFAULT void isr_tim21(void); +WEAK_DEFAULT void isr_tim22(void); WEAK_DEFAULT void isr_tim3(void); WEAK_DEFAULT void isr_tim6_dac(void); WEAK_DEFAULT void isr_tim7(void); -WEAK_DEFAULT void isr_tim21(void); -WEAK_DEFAULT void isr_i2c3(void); -WEAK_DEFAULT void isr_tim22(void); -WEAK_DEFAULT void isr_i2c1(void); -WEAK_DEFAULT void isr_i2c2(void); -WEAK_DEFAULT void isr_spi1(void); -WEAK_DEFAULT void isr_spi2(void); +WEAK_DEFAULT void isr_tsc(void); WEAK_DEFAULT void isr_usart1(void); WEAK_DEFAULT void isr_usart2(void); -WEAK_DEFAULT void isr_rng_lpuart1(void); -WEAK_DEFAULT void isr_lpuart1(void); -WEAK_DEFAULT void isr_lcd(void); +WEAK_DEFAULT void isr_usart4_5(void); WEAK_DEFAULT void isr_usb(void); +WEAK_DEFAULT void isr_wwdg(void); /* CPU specific interrupt vector table */ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = { - isr_wwdg, /* [0] windowed watchdog */ - isr_pvd, /* [1] power control */ - isr_rtc, /* [2] real time clock */ - isr_flash, /* [3] flash memory controller */ - isr_rcc, /* [4] reset and clock control */ - isr_exti, /* [5] external interrupt lines 0 and 1 */ - isr_exti, /* [6] external interrupt lines 2 and 3 */ - isr_exti, /* [7] external interrupt lines 4 to 15 */ + /* shared vectors for all family members */ + [ 0] = isr_wwdg, /* [ 0] Window WatchDog Interrupt */ + [ 1] = isr_pvd, /* [ 1] PVD through EXTI Line detect Interrupt */ + [ 2] = isr_rtc, /* [ 2] RTC through EXTI Line Interrupt */ + [ 3] = isr_flash, /* [ 3] FLASH Interrupt */ + [ 5] = isr_exti, /* [ 5] EXTI Line 0 and 1 Interrupts */ + [ 6] = isr_exti, /* [ 6] EXTI Line 2 and 3 Interrupts */ + [ 7] = isr_exti, /* [ 7] EXTI Line 4 to 15 Interrupts */ + [ 9] = isr_dma1_channel1, /* [ 9] DMA1 Channel 1 Interrupt */ + [10] = isr_dma1_channel2_3, /* [10] DMA1 Channel 2 and Channel 3 Interrupts */ + [11] = isr_dma1_channel4_5_6_7, /* [11] DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */ + [12] = isr_adc1_comp, /* [12] ADC1, COMP1 and COMP2 Interrupts */ + [13] = isr_lptim1, /* [13] LPTIM1 Interrupt */ + [15] = isr_tim2, /* [15] TIM2 Interrupt */ + [20] = isr_tim21, /* [20] TIM21 Interrupt */ + [22] = isr_tim22, /* [22] TIM22 Interrupt */ + [23] = isr_i2c1, /* [23] I2C1 Interrupt */ + [25] = isr_spi1, /* [25] SPI1 Interrupt */ + [28] = isr_usart2, /* [28] USART2 Interrupt */ + #if defined(CPU_MODEL_STM32L031K6) - (0UL), /* [8] reserved */ - isr_dma1_ch1, /* [9] direct memory access controller 1, channel 1*/ - isr_dma1_ch2_3, /* [10] direct memory access controller 1, channel 2 and 3*/ - isr_dma1_ch4_5_6_7, /* [11] direct memory access controller 1, channel 4, 5, 6 and 7*/ - isr_adc1_comp, /* [12] analog digital converter */ - isr_lptim1, /* [13] low power timer 1 */ - (0UL), /* [14] reserved */ - isr_tim2, /* [15] timer 2 */ - (0UL), /* [16] reserved */ - (0UL), /* [17] reserved */ - (0UL), /* [18] reserved */ - (0UL), /* [19] reserved */ - isr_tim21, /* [20] timer 21 */ - (0UL), /* [21] reserved */ - isr_tim22, /* [22] timer 22 */ - isr_i2c1, /* [23] I2C 1 */ - (0UL), /* [24] reserved */ - isr_spi1, /* [25] SPI 1 */ - (0UL), /* [26] reserved */ - (0UL), /* [27] reserved */ - isr_usart2, /* [28] USART 2 */ - isr_lpuart1 /* [29] Low power UART 1 */ + [ 4] = isr_rcc, /* [ 4] RCC Interrupt */ + [29] = isr_lpuart1, /* [29] LPUART1 Interrupt */ #elif defined(CPU_MODEL_STM32L053R8) - isr_ts, /* [8] touch sensing input*/ - isr_dma1_ch1, /* [9] direct memory access controller 1, channel 1*/ - isr_dma1_ch2_3, /* [10] direct memory access controller 1, channel 2 and 3*/ - isr_dma1_ch4_5_6_7, /* [11] direct memory access controller 1, channel 4, 5, 6 and 7*/ - isr_adc1_comp, /* [12] analog digital converter */ - isr_lptim1, /* [13] low power timer 1 */ - (0UL), /* [14] reserved */ - isr_tim2, /* [15] timer 2 */ - (0UL), /* [16] reserved */ - isr_tim6_dac, /* [17] timer 6 and digital to analog converter */ - (0UL), /* [18] reserved */ - (0UL), /* [19] reserved */ - isr_tim21, /* [20] timer 21 */ - (0UL), /* [21] reserved */ - isr_tim22, /* [22] timer 22 */ - isr_i2c1, /* [23] I2C 1 */ - isr_i2c2, /* [24] I2C 2 */ - isr_spi1, /* [25] SPI 1 */ - isr_spi2, /* [26] SPI 2 */ - isr_usart1, /* [27] USART 1 */ - isr_usart2, /* [28] USART 2 */ - isr_rng_lpuart1, /* [29] RNG and Low power UART 1 */ - isr_lcd, /* [30] LCD */ - isr_usb /* [31] USB */ -#else /* CPU_MODEL_STM32L073RZ, CPU_MODEL_STM32L072CZ */ - isr_ts, /* [8] touch sensing input*/ - isr_dma1_ch1, /* [9] direct memory access controller 1, channel 1*/ - isr_dma1_ch2_3, /* [10] direct memory access controller 1, channel 2 and 3*/ - isr_dma1_ch4_5_6_7, /* [11] direct memory access controller 1, channel 4, 5, 6 and 7*/ - isr_adc1_comp, /* [12] analog digital converter */ - isr_lptim1, /* [13] low power timer 1 */ - isr_usart4_5, /* [14] usart 4 to 5 */ - isr_tim2, /* [15] timer 2 */ - isr_tim3, /* [16] timer 3 */ - isr_tim6_dac, /* [17] timer 6 and digital to analog converter */ - isr_tim7, /* [18] timer 7 */ - (0UL), /* [19] reserved */ - isr_tim21, /* [20] timer 21 */ - isr_i2c3, /* [21] I2C 3 */ - isr_tim22, /* [22] timer 22 */ - isr_i2c1, /* [23] I2C 1 */ - isr_i2c2, /* [24] I2C 2 */ - isr_spi1, /* [25] SPI 1 */ - isr_spi2, /* [26] SPI 2 */ - isr_usart1, /* [27] USART 1 */ - isr_usart2, /* [28] USART 2 */ - isr_rng_lpuart1, /* [29] RNG and Low power UART 1 */ - isr_lcd, /* [30] LCD */ - isr_usb /* [31] USB */ + [ 4] = isr_rcc_crs, /* [ 4] RCC and CRS Interrupts */ + [ 8] = isr_tsc, /* [ 8] TSC Interrupt */ + [17] = isr_tim6_dac, /* [17] TIM6 and DAC Interrupts */ + [24] = isr_i2c2, /* [24] I2C2 Interrupt */ + [26] = isr_spi2, /* [26] SPI2 Interrupt */ + [27] = isr_usart1, /* [27] USART1 Interrupt */ + [29] = isr_rng_lpuart1, /* [29] RNG and LPUART1 Interrupts */ + [30] = isr_lcd, /* [30] LCD Interrupt */ + [31] = isr_usb, /* [31] USB global Interrupt */ +#elif defined(CPU_MODEL_STM32L072CZ) + [ 4] = isr_rcc_crs, /* [ 4] RCC and CRS Interrupts */ + [ 8] = isr_tsc, /* [ 8] TSC Interrupt */ + [14] = isr_usart4_5, /* [14] USART4 and USART5 Interrupt */ + [16] = isr_tim3, /* [16] TIM3 Interrupt */ + [17] = isr_tim6_dac, /* [17] TIM6 and DAC Interrupts */ + [18] = isr_tim7, /* [18] TIM7 Interrupt */ + [21] = isr_i2c3, /* [21] I2C3 Interrupt */ + [24] = isr_i2c2, /* [24] I2C2 Interrupt */ + [26] = isr_spi2, /* [26] SPI2 Interrupt */ + [27] = isr_usart1, /* [27] USART1 Interrupt */ + [29] = isr_rng_lpuart1, /* [29] RNG and LPUART1 Interrupts */ + [31] = isr_usb, /* [31] USB global Interrupt */ +#elif defined(CPU_MODEL_STM32L073RZ) + [ 4] = isr_rcc_crs, /* [ 4] RCC and CRS Interrupts */ + [ 8] = isr_tsc, /* [ 8] TSC Interrupt */ + [14] = isr_usart4_5, /* [14] USART4 and USART5 Interrupt */ + [16] = isr_tim3, /* [16] TIM3 Interrupt */ + [17] = isr_tim6_dac, /* [17] TIM6 and DAC Interrupts */ + [18] = isr_tim7, /* [18] TIM7 Interrupt */ + [21] = isr_i2c3, /* [21] I2C3 Interrupt */ + [24] = isr_i2c2, /* [24] I2C2 Interrupt */ + [26] = isr_spi2, /* [26] SPI2 Interrupt */ + [27] = isr_usart1, /* [27] USART1 Interrupt */ + [29] = isr_rng_lpuart1, /* [29] RNG and LPUART1 Interrupts */ + [30] = isr_lcd, /* [30] LCD Interrupt */ + [31] = isr_usb, /* [31] USB global Interrupt */ #endif };