From 5750dc02702b379fa003f205f8049b8e313c80d1 Mon Sep 17 00:00:00 2001
From: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
Date: Sun, 5 Sep 2021 20:41:50 +0200
Subject: [PATCH] cpu/cc2538: fix doxygen grouping warnings

Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
---
 cpu/cc2538/include/cc2538.h         | 26 ++++++++++++--------------
 cpu/cc2538/include/cc2538_gptimer.h |  3 +--
 cpu/cc2538/include/cc2538_rf.h      | 29 +++++++++++++++--------------
 cpu/cc2538/include/cc2538_rfcore.h  |  3 ---
 4 files changed, 28 insertions(+), 33 deletions(-)

diff --git a/cpu/cc2538/include/cc2538.h b/cpu/cc2538/include/cc2538.h
index 08b3a3164001..2d69cd16463e 100644
--- a/cpu/cc2538/include/cc2538.h
+++ b/cpu/cc2538/include/cc2538.h
@@ -26,9 +26,10 @@ extern "C" {
 /* ************************************************************************** */
 /*   CMSIS DEFINITIONS FOR CC2538 */
 /* ************************************************************************** */
-/** @addtogroup CC2538_cmsis CMSIS Definitions */
-/*@{*/
-
+/**
+ * @addtogroup CC2538_cmsis CMSIS Definitions
+ * @{
+ */
 /** Interrupt Number Definition */
 typedef enum IRQn
 {
@@ -86,7 +87,8 @@ typedef enum IRQn
     PERIPH_COUNT_IRQn     = (MACTIMER_IRQn + 1) /**< Number of peripheral IDs */
 } IRQn_Type;
 
-/** @name Cortex-M3 core interrupt handlers
+/**
+ * @name Cortex-M3 core interrupt handlers
  * @{
  */
 void Reset_Handler(void);        /**< Reset handler */
@@ -113,26 +115,23 @@ void SysTick_Handler(void);      /**< SysTick handler */
 /**
  * @brief CMSIS includes
  */
-
 #include <core_cm3.h>
-
-/*@}*/
+/** @} */
 
 #define IEEE_ADDR_MSWORD            ( *(const uint32_t*)0x00280028 ) /**< Most-significant 32 bits of the IEEE address */
 #define IEEE_ADDR_LSWORD            ( *(const uint32_t*)0x0028002c ) /**< Least-significant 32 bits of the IEEE address */
 
 typedef volatile uint32_t cc2538_reg_t; /**< Least-significant 32 bits of the IEEE address */
 
-/** @addtogroup cpu_specific_Peripheral_memory_map
-  * @{
-  */
-
+/**
+ * @addtogroup cpu_specific_Peripheral_memory_map
+ * @{
+ */
 #define FLASH_BASE                  0x00200000 /**< FLASH base address */
 #define SRAM_BASE                   0x20000000 /**< SRAM base address */
 #define PERIPH_BASE                 0x40000000 /**< Peripheral base address */
 
 #define SRAM_BB_BASE                0x22000000 /**< SRAM base address in the bit-band region */
-
 /** @} */
 
 /** @name CC2538 Special Function Registers
@@ -811,5 +810,4 @@ typedef volatile uint32_t cc2538_reg_t; /**< Least-significant 32 bits of the IE
 #endif
 
 #endif /* CC2538_H */
-
-/*@}*/
+/** @} */
diff --git a/cpu/cc2538/include/cc2538_gptimer.h b/cpu/cc2538/include/cc2538_gptimer.h
index 15a8f90f6a7c..43e037370bfb 100644
--- a/cpu/cc2538/include/cc2538_gptimer.h
+++ b/cpu/cc2538/include/cc2538_gptimer.h
@@ -89,5 +89,4 @@ typedef struct {
 #endif
 
 #endif /* CC2538_GPTIMER_H */
-
-/* @} */
+/** @} */
diff --git a/cpu/cc2538/include/cc2538_rf.h b/cpu/cc2538/include/cc2538_rf.h
index e5c8d617fc75..81d08ac5760e 100644
--- a/cpu/cc2538/include/cc2538_rf.h
+++ b/cpu/cc2538/include/cc2538_rf.h
@@ -136,7 +136,7 @@ enum {
     FSM_STATE_TX_CALIBRATION = 32,
 };
 
-/*
+/**
  * @brief RFCORE_XREG_RFERRM bits
  */
 enum {
@@ -149,18 +149,18 @@ enum {
     NLOCK      = BIT(0),
 };
 
- /*
-  * @brief RFCORE_XREG_FRMCTRL0 bits
-  */
+/**
+ * @brief RFCORE_XREG_FRMCTRL0 bits
+ */
 enum {
     SET_RXENMASK_ON_TX  = BIT(0),
     IGNORE_TX_UNDERF    = BIT(1),
     PENDING_OR          = BIT(2),
 };
 
- /*
-  * @brief RFCORE_XREG_FRMCTRL1 bits
-  */
+/**
+ * @brief RFCORE_XREG_FRMCTRL1 bits
+ */
 enum {
     ENERGY_SCAN      = BIT(4),
     AUTOACK          = BIT(5),
@@ -168,7 +168,7 @@ enum {
     APPEND_DATA_MODE = BIT(7),
 };
 
-/*
+/**
  * @brief RFCORE_XREG_RFIRQM0 / RFCORE_XREG_RFIRQF0 bits
  */
 enum {
@@ -182,7 +182,7 @@ enum {
     RXMASKZERO       = BIT(7),
 };
 
-/*
+/**
  * @brief RFCORE_XREG_RFIRQM1 / RFCORE_XREG_RFIRQF1 bits
  */
 enum {
@@ -194,14 +194,18 @@ enum {
     CSP_WAIT         = BIT(5),
 };
 
-/* Values for use with CCTEST_OBSSELx registers: */
+/**
+ * @brief Values for use with CCTEST_OBSSELx registers.
+ */
 enum {
     rfc_obs_sig0 = 0,
     rfc_obs_sig1 = 1,
     rfc_obs_sig2 = 2,
 };
 
-/* Values for RFCORE_XREG_RFC_OBS_CTRLx registers: */
+/**
+ * @brief Values for RFCORE_XREG_RFC_OBS_CTRLx registers.
+ */
 enum {
     constant_value_0 = 0x00, /**< Constant value 0 */
     constant_value_1 = 0x01, /**< Constant value 1*/
@@ -248,8 +252,6 @@ enum {
     disabled         = 0xff, /**< disabled */
 };
 
-/** @} */
-
 /**
  * @name    RF CORE observable signals settings
  */
@@ -278,7 +280,6 @@ enum {
      (CONFIG_CC2538_RF_OBS_SIG_0_PCX > 7))
 #error "CONFIG_CC2538_RF_OBS_SIG_X_PCX must be between 0-7 (PC0-PC7)"
 #endif
-/** @} */
 
 /**
  * @brief   Device descriptor for CC2538 transceiver
diff --git a/cpu/cc2538/include/cc2538_rfcore.h b/cpu/cc2538/include/cc2538_rfcore.h
index de547315d83f..2f549a404bc7 100644
--- a/cpu/cc2538/include/cc2538_rfcore.h
+++ b/cpu/cc2538/include/cc2538_rfcore.h
@@ -276,7 +276,4 @@ enum {
 #endif
 
 #endif /* CC2538_RFCORE_H */
-
-/** @} */
-/** @} */
 /** @} */