From cbcd7d58e754a149e021fc50eabbc7202ac57454 Mon Sep 17 00:00:00 2001
From: Jean Pierre Dudey <jeandudey@hotmail.com>
Date: Tue, 14 Apr 2020 17:15:56 -0500
Subject: [PATCH] cc26xx_cc13xx: fix CCFG offset on x2 variants

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
---
 .../include/cc26xx_cc13xx_ccfg.h              | 42 +++++++++++++------
 1 file changed, 30 insertions(+), 12 deletions(-)

diff --git a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ccfg.h b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ccfg.h
index c1d950c41ade..ff78c17bce87 100644
--- a/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ccfg.h
+++ b/cpu/cc26xx_cc13xx/include/cc26xx_cc13xx_ccfg.h
@@ -22,17 +22,8 @@
 extern "C" {
 #endif
 
-/** @ingroup cpu_specific_peripheral_memory_map
- * @{
- */
-#define CCFG_BASE                           0x50003000 /**<  base address of CCFG memory */
-/*@}*/
-
-/* TODO not present in datasheet but explained in cc26x0ware-lds */
-#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM   0x00000004 /**< CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM */
-
 /**
- * CCFG registers
+ * @brief   CCFG registers
  */
 typedef struct {
     reg32_t EXT_LF_CLK; /**< extern LF clock config */
@@ -59,7 +50,34 @@ typedef struct {
     reg32_t CCFG_PROT_127_96; /**< protect sectors 96-127 */
 } ccfg_regs_t;
 
-#define CCFG ((ccfg_regs_t *) (CCFG_BASE + 0xFA8)) /**< CCFG register bank */
+/**
+ * @brief   CCFG register values
+ * @{
+ */
+#define CCFG_SIZE_AND_DIS_FLAGS_DIS_GPRAM 0x00000004
+/** @} */
+
+/**
+ * @ingroup cpu_specific_peripheral_memory_map
+ * @{
+ */
+/**
+ * @brief   CCFG base address
+ */
+#define CCFG_BASE            (0x50003000)
+/** @} */
+
+#ifdef CPU_VARIANT_X0
+/**
+ * @brief   CCFG register bank
+ */
+#define CCFG                 ((ccfg_regs_t *) (CCFG_BASE + 0xFA8))
+#else
+/**
+ * @brief   CCFG register bank
+ */
+#define CCFG                 ((ccfg_regs_t *) (CCFG_BASE + 0x1FA8))
+#endif
 
 #ifdef __cplusplus
 } /* end extern "C" */
@@ -67,4 +85,4 @@ typedef struct {
 
 #endif /* CC26XX_CC13XX_CCFG_H */
 
-/*@}*/
+/** @} */