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Merge branch 'remove_carriage_returns' of github.com:authmillenon/RIO…
…T into authmillenon-remove_carriage_returns Conflicts: sys/net/destiny/in.h sys/net/destiny/socket.h sys/net/destiny/tcp.h sys/net/destiny/tcp_hc.c sys/net/destiny/tcp_hc.h sys/net/destiny/tcp_timer.c sys/net/destiny/udp.c sys/net/destiny/udp.h
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/* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will | ||
This file is part of the Micro-mesh SensorWeb Firmware. | ||
Micro-Mesh is free software; you can redistribute it and/or modify | ||
it under the terms of the GNU General Public License as published by | ||
the Free Software Foundation; either version 3, or (at your option) | ||
any later version. | ||
Micro-Mesh is distributed in the hope that it will be useful, | ||
but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
GNU General Public License for more details. | ||
You should have received a copy of the GNU General Public License | ||
along with Micro-Mesh; see the file COPYING. If not, write to | ||
the Free Software Foundation, 59 Temple Place - Suite 330, | ||
Boston, MA 02111-1307, USA. */ | ||
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#ifndef __ARM_COMMON_H | ||
#define __ARM_COMMON_H | ||
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/** | ||
* @ingroup arm_common | ||
* @{ | ||
*/ | ||
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#define I_Bit 0x80 | ||
#define F_Bit 0x40 | ||
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#define SYS32Mode 0x1F | ||
#define IRQ32Mode 0x12 | ||
#define FIQ32Mode 0x11 | ||
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#define INTMode (FIQ32Mode | IRQ32Mode) | ||
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/** | ||
* @name IRQ Priority Mapping | ||
*/ | ||
//@{ | ||
#define HIGHEST_PRIORITY 0x01 | ||
#define IRQP_RTIMER 1 // FIQ_PRIORITY // TODO: investigate problems with rtimer and FIQ | ||
#define IRQP_TIMER1 1 | ||
#define IRQP_WATCHDOG 1 | ||
#define IRQP_CLOCK 3 | ||
#define IRQP_GPIO 4 | ||
#define IRQP_RTC 8 | ||
#define LOWEST_PRIORITY 0x0F | ||
// @} | ||
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#define WDT_INT 0 | ||
#define SWI_INT 1 | ||
#define ARM_CORE0_INT 2 | ||
#define ARM_CORE1_INT 3 | ||
#define TIMER0_INT 4 | ||
#define TIMER1_INT 5 | ||
#define UART0_INT 6 | ||
#define UART1_INT 7 | ||
#define PWM0_1_INT 8 | ||
#define I2C0_INT 9 | ||
#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */ | ||
#define SSP0_INT 10 | ||
#define SSP1_INT 11 | ||
#define PLL_INT 12 | ||
#define RTC_INT 13 | ||
#define EINT0_INT 14 | ||
#define EINT1_INT 15 | ||
#define EINT2_INT 16 | ||
#define EINT3_INT 17 | ||
#define ADC0_INT 18 | ||
#define I2C1_INT 19 | ||
#define BOD_INT 20 | ||
#define EMAC_INT 21 | ||
#define USB_INT 22 | ||
#define CAN_INT 23 | ||
#define MCI_INT 24 | ||
#define GPDMA_INT 25 | ||
#define TIMER2_INT 26 | ||
#define TIMER3_INT 27 | ||
#define UART2_INT 28 | ||
#define UART3_INT 29 | ||
#define I2C2_INT 30 | ||
#define I2S_INT 31 | ||
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#define VECT_ADDR_INDEX 0x100 | ||
#define VECT_CNTL_INDEX 0x200 | ||
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#include <stdbool.h> | ||
#include "cpu.h" | ||
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bool cpu_install_irq(int IntNumber, void *HandlerAddr, int Priority); | ||
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/** @} */ | ||
#endif /*ARMVIC_H_*/ | ||
/* Copyright (C) 2005, 2006, 2007, 2008 by Thomas Hillebrandt and Heiko Will | ||
This file is part of the Micro-mesh SensorWeb Firmware. | ||
Micro-Mesh is free software; you can redistribute it and/or modify | ||
it under the terms of the GNU General Public License as published by | ||
the Free Software Foundation; either version 3, or (at your option) | ||
any later version. | ||
Micro-Mesh is distributed in the hope that it will be useful, | ||
but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
GNU General Public License for more details. | ||
You should have received a copy of the GNU General Public License | ||
along with Micro-Mesh; see the file COPYING. If not, write to | ||
the Free Software Foundation, 59 Temple Place - Suite 330, | ||
Boston, MA 02111-1307, USA. */ | ||
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#ifndef __ARM_COMMON_H | ||
#define __ARM_COMMON_H | ||
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/** | ||
* @ingroup arm_common | ||
* @{ | ||
*/ | ||
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#define I_Bit 0x80 | ||
#define F_Bit 0x40 | ||
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#define SYS32Mode 0x1F | ||
#define IRQ32Mode 0x12 | ||
#define FIQ32Mode 0x11 | ||
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#define INTMode (FIQ32Mode | IRQ32Mode) | ||
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/** | ||
* @name IRQ Priority Mapping | ||
*/ | ||
//@{ | ||
#define HIGHEST_PRIORITY 0x01 | ||
#define IRQP_RTIMER 1 // FIQ_PRIORITY // TODO: investigate problems with rtimer and FIQ | ||
#define IRQP_TIMER1 1 | ||
#define IRQP_WATCHDOG 1 | ||
#define IRQP_CLOCK 3 | ||
#define IRQP_GPIO 4 | ||
#define IRQP_RTC 8 | ||
#define LOWEST_PRIORITY 0x0F | ||
// @} | ||
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#define WDT_INT 0 | ||
#define SWI_INT 1 | ||
#define ARM_CORE0_INT 2 | ||
#define ARM_CORE1_INT 3 | ||
#define TIMER0_INT 4 | ||
#define TIMER1_INT 5 | ||
#define UART0_INT 6 | ||
#define UART1_INT 7 | ||
#define PWM0_1_INT 8 | ||
#define I2C0_INT 9 | ||
#define SPI0_INT 10 /* SPI and SSP0 share VIC slot */ | ||
#define SSP0_INT 10 | ||
#define SSP1_INT 11 | ||
#define PLL_INT 12 | ||
#define RTC_INT 13 | ||
#define EINT0_INT 14 | ||
#define EINT1_INT 15 | ||
#define EINT2_INT 16 | ||
#define EINT3_INT 17 | ||
#define ADC0_INT 18 | ||
#define I2C1_INT 19 | ||
#define BOD_INT 20 | ||
#define EMAC_INT 21 | ||
#define USB_INT 22 | ||
#define CAN_INT 23 | ||
#define MCI_INT 24 | ||
#define GPDMA_INT 25 | ||
#define TIMER2_INT 26 | ||
#define TIMER3_INT 27 | ||
#define UART2_INT 28 | ||
#define UART3_INT 29 | ||
#define I2C2_INT 30 | ||
#define I2S_INT 31 | ||
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#define VECT_ADDR_INDEX 0x100 | ||
#define VECT_CNTL_INDEX 0x200 | ||
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#include <stdbool.h> | ||
#include "cpu.h" | ||
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bool cpu_install_irq(int IntNumber, void *HandlerAddr, int Priority); | ||
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/** @} */ | ||
#endif /*ARMVIC_H_*/ |
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@@ -1,96 +1,96 @@ | ||
@-----------------------------------------------------------@ | ||
@ Fast Block Copy (declared in diskio.h) | ||
@-----------------------------------------------------------@ | ||
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.global Copy_un2al | ||
.arm | ||
Copy_un2al: | ||
STMFD SP!, {R4-R8} | ||
ANDS IP, R1, #3 | ||
BEQ lb_align | ||
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BIC R1, #3 | ||
MOV IP, IP, LSL #3 | ||
RSB R8, IP, #32 | ||
LDMIA R1!, {R7} | ||
lb_l1: MOV R3, R7 | ||
LDMIA R1!, {R4-R7} | ||
MOV R3, R3, LSR IP | ||
ORR R3, R3, R4, LSL R8 | ||
MOV R4, R4, LSR IP | ||
ORR R4, R4, R5, LSL R8 | ||
MOV R5, R5, LSR IP | ||
ORR R5, R5, R6, LSL R8 | ||
MOV R6, R6, LSR IP | ||
ORR R6, R6, R7, LSL R8 | ||
SUBS R2, R2, #16 | ||
STMIA R0!, {R3-R6} | ||
BNE lb_l1 | ||
LDMFD SP!, {R4-R8} | ||
BX LR | ||
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lb_align: | ||
LDMIA R1!, {R3-R6} | ||
SUBS R2, R2, #16 | ||
STMIA R0!, {R3-R6} | ||
BNE lb_align | ||
LDMFD SP!, {R4-R8} | ||
BX LR | ||
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.global Copy_al2un | ||
.arm | ||
Copy_al2un: | ||
STMFD SP!, {R4-R8} | ||
ANDS IP, R0, #3 | ||
BEQ sb_align | ||
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MOV IP, IP, LSL #3 | ||
RSB R8, IP, #32 | ||
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LDMIA R1!, {R4-R7} | ||
sb_p1: STRB R4, [R0], #1 | ||
MOV R4, R4, LSR #8 | ||
TST R0, #3 | ||
BNE sb_p1 | ||
ORR R4, R4, R5, LSL IP | ||
MOV R5, R5, LSR R8 | ||
ORR R5, R5, R6, LSL IP | ||
MOV R6, R6, LSR R8 | ||
ORR R6, R6, R7, LSL IP | ||
SUBS R2, R2, #16 | ||
STMIA R0!, {R4-R6} | ||
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sb_l1: MOV R3, R7 | ||
LDMIA R1!, {R4-R7} | ||
MOV R3, R3, LSR R8 | ||
ORR R3, R3, R4, LSL IP | ||
MOV R4, R4, LSR R8 | ||
ORR R4, R4, R5, LSL IP | ||
MOV R5, R5, LSR R8 | ||
ORR R5, R5, R6, LSL IP | ||
MOV R6, R6, LSR R8 | ||
ORR R6, R6, R7, LSL IP | ||
SUBS R2, R2, #16 | ||
STMIA R0!, {R3-R6} | ||
BNE sb_l1 | ||
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MOV R7, R7, LSR R8 | ||
sb_p2: SUBS IP, IP, #8 | ||
STRB R7, [R0], #1 | ||
MOV R7, R7, LSR #8 | ||
BNE sb_p2 | ||
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LDMFD SP!, {R4-R8} | ||
BX LR | ||
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sb_align: | ||
LDMIA R1!, {R3-R6} | ||
SUBS R2, #16 | ||
STMIA R0!, {R3-R6} | ||
BNE sb_align | ||
LDMFD SP!, {R4-R8} | ||
BX LR | ||
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.end | ||
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@-----------------------------------------------------------@ | ||
@ Fast Block Copy (declared in diskio.h) | ||
@-----------------------------------------------------------@ | ||
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.global Copy_un2al | ||
.arm | ||
Copy_un2al: | ||
STMFD SP!, {R4-R8} | ||
ANDS IP, R1, #3 | ||
BEQ lb_align | ||
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BIC R1, #3 | ||
MOV IP, IP, LSL #3 | ||
RSB R8, IP, #32 | ||
LDMIA R1!, {R7} | ||
lb_l1: MOV R3, R7 | ||
LDMIA R1!, {R4-R7} | ||
MOV R3, R3, LSR IP | ||
ORR R3, R3, R4, LSL R8 | ||
MOV R4, R4, LSR IP | ||
ORR R4, R4, R5, LSL R8 | ||
MOV R5, R5, LSR IP | ||
ORR R5, R5, R6, LSL R8 | ||
MOV R6, R6, LSR IP | ||
ORR R6, R6, R7, LSL R8 | ||
SUBS R2, R2, #16 | ||
STMIA R0!, {R3-R6} | ||
BNE lb_l1 | ||
LDMFD SP!, {R4-R8} | ||
BX LR | ||
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lb_align: | ||
LDMIA R1!, {R3-R6} | ||
SUBS R2, R2, #16 | ||
STMIA R0!, {R3-R6} | ||
BNE lb_align | ||
LDMFD SP!, {R4-R8} | ||
BX LR | ||
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.global Copy_al2un | ||
.arm | ||
Copy_al2un: | ||
STMFD SP!, {R4-R8} | ||
ANDS IP, R0, #3 | ||
BEQ sb_align | ||
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MOV IP, IP, LSL #3 | ||
RSB R8, IP, #32 | ||
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LDMIA R1!, {R4-R7} | ||
sb_p1: STRB R4, [R0], #1 | ||
MOV R4, R4, LSR #8 | ||
TST R0, #3 | ||
BNE sb_p1 | ||
ORR R4, R4, R5, LSL IP | ||
MOV R5, R5, LSR R8 | ||
ORR R5, R5, R6, LSL IP | ||
MOV R6, R6, LSR R8 | ||
ORR R6, R6, R7, LSL IP | ||
SUBS R2, R2, #16 | ||
STMIA R0!, {R4-R6} | ||
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sb_l1: MOV R3, R7 | ||
LDMIA R1!, {R4-R7} | ||
MOV R3, R3, LSR R8 | ||
ORR R3, R3, R4, LSL IP | ||
MOV R4, R4, LSR R8 | ||
ORR R4, R4, R5, LSL IP | ||
MOV R5, R5, LSR R8 | ||
ORR R5, R5, R6, LSL IP | ||
MOV R6, R6, LSR R8 | ||
ORR R6, R6, R7, LSL IP | ||
SUBS R2, R2, #16 | ||
STMIA R0!, {R3-R6} | ||
BNE sb_l1 | ||
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MOV R7, R7, LSR R8 | ||
sb_p2: SUBS IP, IP, #8 | ||
STRB R7, [R0], #1 | ||
MOV R7, R7, LSR #8 | ||
BNE sb_p2 | ||
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LDMFD SP!, {R4-R8} | ||
BX LR | ||
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sb_align: | ||
LDMIA R1!, {R3-R6} | ||
SUBS R2, #16 | ||
STMIA R0!, {R3-R6} | ||
BNE sb_align | ||
LDMFD SP!, {R4-R8} | ||
BX LR | ||
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.end | ||
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