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CoreRISCV_AXI4_BaseDesign
IGL2_CoreRISCV_AXI4_TickTacToe
IGL2_MIV_RV32IMA_BaseDesign
README.md

README.md

IGLOO2 Creative Development Board RISC-V Sample FPGA Designs

Sample RISC-V Libero projects for the IGLOO2 (M2GL025) Creative Development Board.

This project contains Libero projects containing FPGA designs including a RISC-V RV32IM soft processor. Programming bitstreams are also included so you don't have to run through the full FPGA design flow in order to start developing software for RISC-V.

Design Feature

The FPGA Designs include the following features

  • CoreRISCV_AXI4 RV32IM RISC-V processor
  • RISC-V debug block allowing on-target debug using openocd/GDB
  • On-chip NVM used as boot/execution memory
  • DDR2 memory for code/data
  • User peripherals such as GPIO, Timers, UART

The memory map for each design is available within each Libero project.

Target Hardware

The IGLOO2 Creative Development Board includes a IGLOO2 M2GL025 FPGA. Details of the features available for this development board are available here .

Libero Projects

This folder contains CoreRISCV_AXI4 Libero V11.8 projects.

  • CoreRISCV_AXI4_BaseDesign, contains a simple RISCV design which allows users to use basic peripherals such as GPIO, UART and Timers.
  • IGL2_CoreRISCV_AXI4_TickTackToe, contains the design used along side of the TickTackToe example software found here. To use this deisgn a daughter board is needed from Adafruit, more information on this can be found here

Modifying the Libero projects

Some of the Libero projects use IP packages not directly available from the Microsemi IP Catalog. These IP packages were created to speed up design creation by wrapping simple logic into reusable user IP packages. These user IP packages are available here.

Please note that you may need to uncomment "`define USE_REGISTERS" in file coreriscv_axi4_defines.v in order to reduce RAM blocks usage. You will need to do this anytime you regenerate the top level SmartDesign in Libero.