Skip to content

Commit

Permalink
Fixed some bugs
Browse files Browse the repository at this point in the history
  • Loading branch information
@RKX1209
RKX1209 committed Jun 8, 2018
1 parent e9884aa commit 10933ba
Show file tree
Hide file tree
Showing 11 changed files with 314 additions and 246 deletions.
7 changes: 4 additions & 3 deletions ARMv8/Disassembler.cpp
View file
Expand Up @@ -1065,7 +1065,7 @@ static void DisasLdstRegRoffset(uint32_t insn, DisasCallback *cb,

if (is_vector) {
/* "LDR/STR [base, Xm/Wm] (SIMD&FP)") */
size = (opc & 2) << 1;
size |= (opc & 2) << 1;
is_store = !extract32(opc, 0, 1);
} else {
if (size == 3 && opc == 2) {
Expand All @@ -1082,14 +1082,15 @@ static void DisasLdstRegRoffset(uint32_t insn, DisasCallback *cb,
is_extended = (size < 3); //TODO: treat other case, size = 0, 1(8bit-> or 16bit->)
}
//bool sf = DisasLdstCompute64bit (size, is_signed, opc);
/* TODO: Calculate address here (not in callback) */
bool sf = (opt & 0x1) ? true : false; // XXX: Correct?
cb->ExtendReg (GPR_DUMMY, rm, opt, sf);
cb->ShiftI64 (GPR_DUMMY, GPR_DUMMY, ShiftType_LSL, shift ? size : 0, sf);
if (is_vector) {
if (is_store) {
cb->StoreFpRegI64 (rt, GPR_DUMMY, size);
cb->StoreFpReg (rt, rn, GPR_DUMMY, size, false, sf);
} else {
cb->LoadFpRegI64 (rt, GPR_DUMMY, size);
cb->LoadFpReg (rt, rn, GPR_DUMMY, size, false, sf);
}
} else {
if (is_store) {
Expand Down
69 changes: 60 additions & 9 deletions ARMv8/Interpreter.cpp
View file
Expand Up @@ -21,7 +21,7 @@ static uint64_t counter;
void Interpreter::Run() {
debug_print ("Running with Interpreter\n");

uint64_t estimate = 3350000, mx = 100000;
uint64_t estimate = 3500000, mx = 100000;
//uint64_t estimate = 3000000, mx = 10000;
//uint64_t estimate = 0, mx = 1000000;
while (Cpu::GetState () == Cpu::State::Running) {
Expand Down Expand Up @@ -703,10 +703,8 @@ void IntprCallback::StoreVecReg(unsigned int rd_idx, int element, unsigned int v
}
}

/* Load/Store for FP */
void IntprCallback::LoadFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int size) {
uint64_t addr = X(ad_idx);
debug_print("Load Fp(%d)[%u] = [X(%u)(0x%lx)]\n", size, fd_idx, ad_idx, addr);
static void _LoadFpReg(unsigned int fd_idx, uint64_t addr, int size) {
VREG(fd_idx).d[0] = VREG(fd_idx).d[1] = 0; // 0 clear
if (size == 0) { // 1byte (8B/16B)
B(fd_idx) = ARMv8::ReadU8 (addr);
} else if (size == 1) { // 2byte (4H/8H)
Expand All @@ -722,11 +720,9 @@ void IntprCallback::LoadFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int s
//ns_debug("Read: Q = 0x%lx, 0x%lx\n", VREG(rd_idx).d[0], VREG(rd_idx).d[1]);
}
}
void IntprCallback::StoreFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int size) {
uint64_t addr = X(ad_idx);
debug_print("Store Fp(%d)[%u] => [X(%u)(0x%lx)]\n", size, fd_idx, ad_idx, addr);
static void _StoreFpReg(unsigned int fd_idx, uint64_t addr, int size) {
if (size == 0) {
ARMv8::WriteU8 (addr, B(fd_idx));
ARMv8::WriteU8 (addr, B(fd_idx));
} else if (size == 1) {
ARMv8::WriteU16 (addr, H(fd_idx));
} else if (size == 2) {
Expand All @@ -740,6 +736,60 @@ void IntprCallback::StoreFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int
}
}

/* Load/Store for FP */
void IntprCallback::LoadFpReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size, bool post, bool bit64) {
char regc = bit64? 'X': 'W';
base_idx = ARMv8::HandleAsSP (base_idx);
debug_print ("Load(%d): Fp[%u] <= [X[%u](0x%lx), %c[%u](0x%lx)]\n",
size, rd_idx, base_idx, X(base_idx), regc, rm_idx, X(rm_idx));
uint64_t addr;
if (bit64) {
if (post)
addr = X(base_idx);
else
addr = X(base_idx) + X(rm_idx);
_LoadFpReg (rd_idx, addr, size);
} else {
if (post)
addr = X(base_idx);
else
addr = X(base_idx) + W(rm_idx);
_LoadFpReg (rd_idx, addr, size);
}
}
void IntprCallback::StoreFpReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size, bool post, bool bit64) {
char regc = bit64? 'X': 'W';
base_idx = ARMv8::HandleAsSP (base_idx);
debug_print ("Store(%d): Fp[%u] => [X[%u](0x%lx), %c[%u](0x%lx)]\n",
size, rd_idx, base_idx, X(base_idx), regc, rm_idx, X(rm_idx));
uint64_t addr;
if (bit64) {
if (post)
addr = X(base_idx);
else
addr = X(base_idx) + X(rm_idx);
_StoreFpReg (rd_idx, addr, size);
} else {
if (post)
addr = X(base_idx);
else
addr = X(base_idx) + W(rm_idx);
_StoreFpReg (rd_idx, addr, size);
}
}

/* Load/Store for FP */
void IntprCallback::LoadFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int size) {
uint64_t addr = X(ad_idx);
debug_print("Load Fp(%d)[%u] = [X(%u)(0x%lx)]\n", size, fd_idx, ad_idx, addr);
_LoadFpReg(fd_idx, addr, size);
}
void IntprCallback::StoreFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int size) {
uint64_t addr = X(ad_idx);
debug_print("Store Fp(%d)[%u] => [X(%u)(0x%lx)]\n", size, fd_idx, ad_idx, addr);
_StoreFpReg(fd_idx, addr, size);
}

/* Bitfield Signed/Unsigned Extract... with Immediate value */
/* X(d)<> = X(n)<off:64> */
void IntprCallback::SExtractI64(unsigned int rd_idx, unsigned int rn_idx, unsigned int pos, unsigned int len, bool bit64) {
Expand Down Expand Up @@ -917,6 +967,7 @@ void IntprCallback::BRK(unsigned int memo) {

/* Read Vector register to FP register */
void IntprCallback::ReadVecReg(unsigned int rd_idx, unsigned int vn_idx, unsigned int index, int size) {
VREG(rd_idx).d[0] = VREG(rd_idx).d[1] = 0; // 0 clear
if (size == 0) {
D(rd_idx) = VREG(vn_idx).b[index];
} else if (size == 1) {
Expand Down
4 changes: 2 additions & 2 deletions GenIpcStubs.py
View file
Expand Up @@ -172,12 +172,12 @@ def tempname():
if isPointerType(elem):
params.append('req->GetDataPointer<%s>(%s)' % (retype(elem, noIndex=True), emitInt(inpOffset)))
logFmt.append('%s %s= %%s' % (retype(elem), '%s ' % name if name else ''))
logElems.append('ARMv8::ReadString(req->GetDataPointer<uint64_t>(%s)).c_str()' % (emitInt(inpOffset)))
logElems.append('read_string(req->GetDataPointer<uint8_t *>(%s), %s).c_str()' % (emitInt(inpOffset), emitInt(typeSize(elem))))
else:
params.append('req->GetData<%s>(%s)' % (retype(elem), emitInt(inpOffset)))
if typeSize(elem) == 16:
logFmt.append('%s %s= %%s' % (retype(elem), '%s ' % name if name else ''))
logElems.append('ARMv8::ReadString(req->GetDataPointer<uint64_t>(%s)).c_str()' % (emitInt(inpOffset)))
logElems.append('read_string(req->GetDataPointer<uint8_t *>(%s), %s).c_str()' % (emitInt(inpOffset), emitInt(typeSize(elem))))
else:
type = retype(elem)
ct = '0x%x'
Expand Down
1 change: 0 additions & 1 deletion Ipc.cpp
View file
Expand Up @@ -116,7 +116,6 @@ uint32_t ProcMessage(IpcService *handler, uint8_t buf[]) {
req.ParseMessage();
IpcMessage resp(obuf, is_domainobj);
uint32_t ret = 0xf601;

switch(req.type) {
case 2: //Close
resp.GenBuf(0, 0, 0);
Expand Down
1 change: 1 addition & 0 deletions Svc.cpp
View file
Expand Up @@ -295,6 +295,7 @@ uint64_t SendSyncRequest(uint32_t handle) {
if (!handler) {
ns_abort ("Cannnot find session handler\n");
}
ns_print("ProcMessage(%p)\n", (void *)handler);
IPC::ProcMessage(handler, msgbuf);
return 0;
}
Expand Down
4 changes: 4 additions & 0 deletions Util.cpp
View file
@@ -1,3 +1,7 @@
/* nsemu - LGPL - Copyright 2017 rkx1209<rkx1209dev@gmail.com> */
#include "Nsemu.hpp"
RunLevel curlevel;
string read_string(uint8_t *buf, int size) {
string str((char *)buf, size);
return str;
}
4 changes: 4 additions & 0 deletions include/ARMv8/Disassembler.hpp
View file
Expand Up @@ -117,6 +117,10 @@ virtual void NotVecReg(unsigned int rd_idx, unsigned int rm_idx) = 0;
virtual void LoadVecReg(unsigned int vd_idx, int element, unsigned int rn_idx, int size) = 0;
virtual void StoreVecReg(unsigned int rd_idx, int element, unsigned int vn_idx, int size) = 0;

/* Load/Store for FP */
virtual void LoadFpReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size, bool post, bool bit64) = 0;
virtual void StoreFpReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size, bool post, bool bit64) = 0;

/* Load/Store for FP */
virtual void LoadFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int size) = 0;
virtual void StoreFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int size) = 0;
Expand Down
4 changes: 4 additions & 0 deletions include/ARMv8/Interpreter.hpp
View file
Expand Up @@ -109,6 +109,10 @@ void FMovReg(unsigned int fd_idx, unsigned int fn_idx, int type);
void LoadVecReg(unsigned int vd_idx, int element, unsigned int rn_idx, int size);
void StoreVecReg(unsigned int rd_idx, int element, unsigned int vn_idx, int size);

/* Load/Store for FP */
void LoadFpReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size, bool post, bool bit64);
void StoreFpReg(unsigned int rd_idx, unsigned int base_idx, unsigned int rm_idx, int size, bool post, bool bit64);

/* Load/Store for FP */
void LoadFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int size);
void StoreFpRegI64(unsigned int fd_idx, unsigned int ad_idx, int size);
Expand Down
1 change: 1 addition & 0 deletions include/Ipc.hpp
View file
Expand Up @@ -28,6 +28,7 @@ class IpcMessage {
}
template<typename T>
T GetDataPointer(uint offset) {
ns_print("req.type=%u, raw_ptr:0x%x, payload_off:0x%x\n", type, raw_ptr, payload_off);
return (T) (raw_ptr + payload_off + 8 + offset);
}
uint64_t GetBuffer(int btype, int num, unsigned int& size) {
Expand Down

0 comments on commit 10933ba

Please sign in to comment.