From 1c33b820719cbc506c70e100592b732a991cfd89 Mon Sep 17 00:00:00 2001 From: Shawn K Date: Thu, 23 Oct 2025 07:18:49 -0700 Subject: [PATCH 01/31] [Clang] VectorExprEvaluator::VisitCallExpr / InterpretBuiltin - allow MMX/SSE/AVX2 PSIGN intrinsics to be used in constexpr (#163685) Fix #155812 --- clang/include/clang/Basic/BuiltinsX86.td | 29 ++++++++----- clang/lib/AST/ByteCode/InterpBuiltin.cpp | 15 +++++++ clang/lib/AST/ExprConstant.cpp | 14 +++++++ clang/lib/Headers/avx2intrin.h | 21 ++++------ clang/lib/Headers/tmmintrin.h | 52 ++++++++++-------------- clang/test/CodeGen/X86/avx2-builtins.c | 7 ++++ clang/test/CodeGen/X86/mmx-builtins.c | 5 +++ clang/test/CodeGen/X86/ssse3-builtins.c | 3 ++ 8 files changed, 92 insertions(+), 54 deletions(-) diff --git a/clang/include/clang/Basic/BuiltinsX86.td b/clang/include/clang/Basic/BuiltinsX86.td index 54b3ce08f5625..8332eac2a890c 100644 --- a/clang/include/clang/Basic/BuiltinsX86.td +++ b/clang/include/clang/Basic/BuiltinsX86.td @@ -123,13 +123,13 @@ let Attributes = [Const, NoThrow, RequiredVectorWidth<128>] in { } } - let Features = "ssse3" in { - def psignb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">; - def psignw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; - def psignd128 : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">; - } - let Features = "ssse3", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWidth<128>] in { + def psignb128 + : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">; + def psignw128 + : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; + def psignd128 + : X86Builtin<"_Vector<4, int>(_Vector<4, int>, _Vector<4, int>)">; def pmulhrsw128 : X86Builtin<"_Vector<8, short>(_Vector<8, short>, _Vector<8, short>)">; def pmaddubsw128 : X86Builtin<"_Vector<8, short>(_Vector<16, char>, _Vector<16, char>)">; def pshufb128 : X86Builtin<"_Vector<16, char>(_Vector<16, char>, _Vector<16, char>)">; @@ -603,10 +603,9 @@ let Features = "avx2", Attributes = [NoThrow, Const, RequiredVectorWidth<256>] i def mpsadbw256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32, char>, _Constant char)">; def palignr256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>, " "_Vector<32, char>, _Constant int)">; - def psadbw256 : X86Builtin<"_Vector<4, long long int>(_Vector<32, char>, _Vector<32, char>)">; - def psignb256 : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32, char>)">; - def psignw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Vector<16, short>)">; - def psignd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>)">; + def psadbw256 + : X86Builtin< + "_Vector<4, long long int>(_Vector<32, char>, _Vector<32, char>)">; def psllw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Vector<8, short>)">; def pslldqi256_byteshift : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Constant int)">; def pslld256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<4, int>)">; @@ -677,7 +676,15 @@ let Features = "avx2", Attributes = [NoThrow, Const, Constexpr, RequiredVectorWi def phsubw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Vector<16, short>)">; def phsubd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>)">; def phsubsw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Vector<16, short>)">; - + + def psignb256 + : X86Builtin<"_Vector<32, char>(_Vector<32, char>, _Vector<32, char>)">; + def psignw256 + : X86Builtin< + "_Vector<16, short>(_Vector<16, short>, _Vector<16, short>)">; + def psignd256 + : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Vector<8, int>)">; + def pshuflw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Constant int)">; def pshufhw256 : X86Builtin<"_Vector<16, short>(_Vector<16, short>, _Constant int)">; def pshufd256 : X86Builtin<"_Vector<8, int>(_Vector<8, int>, _Constant int)">; diff --git a/clang/lib/AST/ByteCode/InterpBuiltin.cpp b/clang/lib/AST/ByteCode/InterpBuiltin.cpp index 2d5ad4a7a92cf..d932a49dd2935 100644 --- a/clang/lib/AST/ByteCode/InterpBuiltin.cpp +++ b/clang/lib/AST/ByteCode/InterpBuiltin.cpp @@ -3809,6 +3809,21 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call, return interp__builtin_ia32_movmsk_op(S, OpPC, Call); } + case X86::BI__builtin_ia32_psignb128: + case X86::BI__builtin_ia32_psignb256: + case X86::BI__builtin_ia32_psignw128: + case X86::BI__builtin_ia32_psignw256: + case X86::BI__builtin_ia32_psignd128: + case X86::BI__builtin_ia32_psignd256: + return interp__builtin_elementwise_int_binop( + S, OpPC, Call, [](const APInt &AElem, const APInt &BElem) { + if (BElem.isZero()) + return APInt::getZero(AElem.getBitWidth()); + if (BElem.isNegative()) + return -AElem; + return AElem; + }); + case clang::X86::BI__builtin_ia32_pavgb128: case clang::X86::BI__builtin_ia32_pavgw128: case clang::X86::BI__builtin_ia32_pavgb256: diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index 00aaaab957591..7db7a01998a4a 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -12312,6 +12312,20 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr *E) { return Success(APValue(ResultElements.data(), ResultElements.size()), E); } + case X86::BI__builtin_ia32_psignb128: + case X86::BI__builtin_ia32_psignb256: + case X86::BI__builtin_ia32_psignw128: + case X86::BI__builtin_ia32_psignw256: + case X86::BI__builtin_ia32_psignd128: + case X86::BI__builtin_ia32_psignd256: + return EvaluateBinOpExpr([](const APInt &AElem, const APInt &BElem) { + if (BElem.isZero()) + return APInt::getZero(AElem.getBitWidth()); + if (BElem.isNegative()) + return -AElem; + return AElem; + }); + case X86::BI__builtin_ia32_blendvpd: case X86::BI__builtin_ia32_blendvpd256: case X86::BI__builtin_ia32_blendvps: diff --git a/clang/lib/Headers/avx2intrin.h b/clang/lib/Headers/avx2intrin.h index fdb825fbbd134..3cbaaece7b38e 100644 --- a/clang/lib/Headers/avx2intrin.h +++ b/clang/lib/Headers/avx2intrin.h @@ -1975,10 +1975,9 @@ _mm256_shuffle_epi8(__m256i __a, __m256i __b) { /// \param __b /// A 256-bit integer vector]. /// \returns A 256-bit integer vector containing the result. -static __inline__ __m256i __DEFAULT_FN_ATTRS256 -_mm256_sign_epi8(__m256i __a, __m256i __b) -{ - return (__m256i)__builtin_ia32_psignb256((__v32qi)__a, (__v32qi)__b); +static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR +_mm256_sign_epi8(__m256i __a, __m256i __b) { + return (__m256i)__builtin_ia32_psignb256((__v32qi)__a, (__v32qi)__b); } /// Sets each element of the result to the corresponding element of the @@ -1996,10 +1995,9 @@ _mm256_sign_epi8(__m256i __a, __m256i __b) /// \param __b /// A 256-bit vector of [16 x i16]. /// \returns A 256-bit vector of [16 x i16] containing the result. -static __inline__ __m256i __DEFAULT_FN_ATTRS256 -_mm256_sign_epi16(__m256i __a, __m256i __b) -{ - return (__m256i)__builtin_ia32_psignw256((__v16hi)__a, (__v16hi)__b); +static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR +_mm256_sign_epi16(__m256i __a, __m256i __b) { + return (__m256i)__builtin_ia32_psignw256((__v16hi)__a, (__v16hi)__b); } /// Sets each element of the result to the corresponding element of the @@ -2017,10 +2015,9 @@ _mm256_sign_epi16(__m256i __a, __m256i __b) /// \param __b /// A 256-bit vector of [8 x i32]. /// \returns A 256-bit vector of [8 x i32] containing the result. -static __inline__ __m256i __DEFAULT_FN_ATTRS256 -_mm256_sign_epi32(__m256i __a, __m256i __b) -{ - return (__m256i)__builtin_ia32_psignd256((__v8si)__a, (__v8si)__b); +static __inline__ __m256i __DEFAULT_FN_ATTRS256_CONSTEXPR +_mm256_sign_epi32(__m256i __a, __m256i __b) { + return (__m256i)__builtin_ia32_psignd256((__v8si)__a, (__v8si)__b); } /// Shifts each 128-bit half of the 256-bit integer vector \a a left by diff --git a/clang/lib/Headers/tmmintrin.h b/clang/lib/Headers/tmmintrin.h index 5d0f20f4d527d..cb4b36ea7383c 100644 --- a/clang/lib/Headers/tmmintrin.h +++ b/clang/lib/Headers/tmmintrin.h @@ -26,9 +26,6 @@ #define __zext128(x) \ (__m128i) __builtin_shufflevector((__v2si)(x), __extension__(__v2si){}, 0, \ 1, 2, 3) -#define __anyext128(x) \ - (__m128i) __builtin_shufflevector((__v2si)(x), __extension__(__v2si){}, 0, \ - 1, -1, -1) #if defined(__cplusplus) && (__cplusplus >= 201103L) #define __DEFAULT_FN_ATTRS_CONSTEXPR __DEFAULT_FN_ATTRS constexpr @@ -641,10 +638,9 @@ _mm_shuffle_pi8(__m64 __a, __m64 __b) { /// A 128-bit integer vector containing control bytes corresponding to /// positions in the destination. /// \returns A 128-bit integer vector containing the resultant values. -static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm_sign_epi8(__m128i __a, __m128i __b) -{ - return (__m128i)__builtin_ia32_psignb128((__v16qi)__a, (__v16qi)__b); +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_sign_epi8(__m128i __a, __m128i __b) { + return (__m128i)__builtin_ia32_psignb128((__v16qi)__a, (__v16qi)__b); } /// For each 16-bit integer in the first source operand, perform one of @@ -667,10 +663,9 @@ _mm_sign_epi8(__m128i __a, __m128i __b) /// A 128-bit integer vector containing control words corresponding to /// positions in the destination. /// \returns A 128-bit integer vector containing the resultant values. -static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm_sign_epi16(__m128i __a, __m128i __b) -{ - return (__m128i)__builtin_ia32_psignw128((__v8hi)__a, (__v8hi)__b); +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_sign_epi16(__m128i __a, __m128i __b) { + return (__m128i)__builtin_ia32_psignw128((__v8hi)__a, (__v8hi)__b); } /// For each 32-bit integer in the first source operand, perform one of @@ -693,10 +688,9 @@ _mm_sign_epi16(__m128i __a, __m128i __b) /// A 128-bit integer vector containing control doublewords corresponding to /// positions in the destination. /// \returns A 128-bit integer vector containing the resultant values. -static __inline__ __m128i __DEFAULT_FN_ATTRS -_mm_sign_epi32(__m128i __a, __m128i __b) -{ - return (__m128i)__builtin_ia32_psignd128((__v4si)__a, (__v4si)__b); +static __inline__ __m128i __DEFAULT_FN_ATTRS_CONSTEXPR +_mm_sign_epi32(__m128i __a, __m128i __b) { + return (__m128i)__builtin_ia32_psignd128((__v4si)__a, (__v4si)__b); } /// For each 8-bit integer in the first source operand, perform one of @@ -719,11 +713,10 @@ _mm_sign_epi32(__m128i __a, __m128i __b) /// A 64-bit integer vector containing control bytes corresponding to /// positions in the destination. /// \returns A 64-bit integer vector containing the resultant values. -static __inline__ __m64 __DEFAULT_FN_ATTRS -_mm_sign_pi8(__m64 __a, __m64 __b) -{ - return __trunc64(__builtin_ia32_psignb128((__v16qi)__anyext128(__a), - (__v16qi)__anyext128(__b))); +static __inline__ __m64 __DEFAULT_FN_ATTRS_CONSTEXPR _mm_sign_pi8(__m64 __a, + __m64 __b) { + return __trunc64(__builtin_ia32_psignb128((__v16qi)__zext128(__a), + (__v16qi)__zext128(__b))); } /// For each 16-bit integer in the first source operand, perform one of @@ -746,11 +739,10 @@ _mm_sign_pi8(__m64 __a, __m64 __b) /// A 64-bit integer vector containing control words corresponding to /// positions in the destination. /// \returns A 64-bit integer vector containing the resultant values. -static __inline__ __m64 __DEFAULT_FN_ATTRS -_mm_sign_pi16(__m64 __a, __m64 __b) -{ - return __trunc64(__builtin_ia32_psignw128((__v8hi)__anyext128(__a), - (__v8hi)__anyext128(__b))); +static __inline__ __m64 __DEFAULT_FN_ATTRS_CONSTEXPR _mm_sign_pi16(__m64 __a, + __m64 __b) { + return __trunc64( + __builtin_ia32_psignw128((__v8hi)__zext128(__a), (__v8hi)__zext128(__b))); } /// For each 32-bit integer in the first source operand, perform one of @@ -773,14 +765,12 @@ _mm_sign_pi16(__m64 __a, __m64 __b) /// A 64-bit integer vector containing two control doublewords corresponding /// to positions in the destination. /// \returns A 64-bit integer vector containing the resultant values. -static __inline__ __m64 __DEFAULT_FN_ATTRS -_mm_sign_pi32(__m64 __a, __m64 __b) -{ - return __trunc64(__builtin_ia32_psignd128((__v4si)__anyext128(__a), - (__v4si)__anyext128(__b))); +static __inline__ __m64 __DEFAULT_FN_ATTRS_CONSTEXPR _mm_sign_pi32(__m64 __a, + __m64 __b) { + return __trunc64( + __builtin_ia32_psignd128((__v4si)__zext128(__a), (__v4si)__zext128(__b))); } -#undef __anyext128 #undef __zext128 #undef __trunc64 #undef __DEFAULT_FN_ATTRS diff --git a/clang/test/CodeGen/X86/avx2-builtins.c b/clang/test/CodeGen/X86/avx2-builtins.c index 03b1bdeb55d7c..5c52d84de56f5 100644 --- a/clang/test/CodeGen/X86/avx2-builtins.c +++ b/clang/test/CodeGen/X86/avx2-builtins.c @@ -1155,23 +1155,30 @@ __m256i test_mm256_shufflelo_epi16(__m256i a) { return _mm256_shufflelo_epi16(a, 83); } TEST_CONSTEXPR(match_v16hi(_mm256_shufflelo_epi16(((__m256i)(__v16hi){ 0,1,2,3, 4,5,6,7, 8,9,10,11, 12,13,14,15}), 83), 3,0,1,1, 4,5,6,7, 11,8,9,9, 12,13,14,15) ); + __m256i test_mm256_sign_epi8(__m256i a, __m256i b) { // CHECK-LABEL: test_mm256_sign_epi8 // CHECK: call <32 x i8> @llvm.x86.avx2.psign.b(<32 x i8> %{{.*}}, <32 x i8> %{{.*}}) return _mm256_sign_epi8(a, b); } +TEST_CONSTEXPR(match_v32qi(_mm256_sign_epi8( + (__m256i)(__v32qs){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,1}, + (__m256i)(__v32qs){0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,-1}), + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,-1)); __m256i test_mm256_sign_epi16(__m256i a, __m256i b) { // CHECK-LABEL: test_mm256_sign_epi16 // CHECK: call <16 x i16> @llvm.x86.avx2.psign.w(<16 x i16> %{{.*}}, <16 x i16> %{{.*}}) return _mm256_sign_epi16(a, b); } +TEST_CONSTEXPR(match_v16hi(_mm256_sign_epi16((__m256i)(__v16hi){0x77,0x77,0xbe,0xbe, -0x9,-0x9,-0x8,-0x8, 0,0,0,0, 0,0,0,0}, (__m256i)(__v16hi){-1,-256,1,256, -512,-1028,512,1028, -2048,-4096,0,0, 0,0,0,0}), -0x77,-0x77,0xbe,0xbe, 0x9,0x9,-0x8,-0x8, 0,0,0,0, 0,0,0,0)); __m256i test_mm256_sign_epi32(__m256i a, __m256i b) { // CHECK-LABEL: test_mm256_sign_epi32 // CHECK: call <8 x i32> @llvm.x86.avx2.psign.d(<8 x i32> %{{.*}}, <8 x i32> %{{.*}}) return _mm256_sign_epi32(a, b); } +TEST_CONSTEXPR(match_v8si(_mm256_sign_epi32((__m256i)(__v8si){0xbeef,0xfeed,0xbead,0xdeed, -1,2,-3,4}, (__m256i)(__v8si){0,0,0,0,-1,-1,-1,-1}), 0,0,0,0, 1,-2,3,-4)); __m256i test_mm256_slli_epi16(__m256i a) { // CHECK-LABEL: test_mm256_slli_epi16 diff --git a/clang/test/CodeGen/X86/mmx-builtins.c b/clang/test/CodeGen/X86/mmx-builtins.c index 767425577a130..273138063a1b1 100644 --- a/clang/test/CodeGen/X86/mmx-builtins.c +++ b/clang/test/CodeGen/X86/mmx-builtins.c @@ -602,23 +602,28 @@ __m64 test_mm_shuffle_pi16(__m64 a) { return _mm_shuffle_pi16(a, 3); } TEST_CONSTEXPR(match_v4hi(_mm_shuffle_pi16(((__m64)(__v4hi){0,1,2,3}), 3), 3,0,0,0)); + __m64 test_mm_sign_pi8(__m64 a, __m64 b) { // CHECK-LABEL: test_mm_sign_pi8 // CHECK: call <16 x i8> @llvm.x86.ssse3.psign.b.128( return _mm_sign_pi8(a, b); } +TEST_CONSTEXPR(match_v8qi(_mm_sign_pi8((__m64)(__v8qi){0,0,0,0, 0,0,0,0}, (__m64)(__v8qi){0,0,0,0, 0,0,0,0}), 0,0,0,0, 0,0,0,0)); +TEST_CONSTEXPR(match_v8qi(_mm_sign_pi8((__m64)(__v8qi){6,7,6,7, 6,7,6,7}, (__m64)(__v8qi){1,1,1,1, 0,0,0,0}), 6,7,6,7, 0,0,0,0)); __m64 test_mm_sign_pi16(__m64 a, __m64 b) { // CHECK-LABEL: test_mm_sign_pi16 // CHECK: call <8 x i16> @llvm.x86.ssse3.psign.w.128( return _mm_sign_pi16(a, b); } +TEST_CONSTEXPR(match_v4hi(_mm_sign_pi16((__m64)(__v4hi){-1,0,1,0}, (__m64)(__v4hi){1,0,-1,0}), -1,0,-1,0)); __m64 test_mm_sign_pi32(__m64 a, __m64 b) { // CHECK-LABEL: test_mm_sign_pi32 // CHECK: call <4 x i32> @llvm.x86.ssse3.psign.d.128( return _mm_sign_pi32(a, b); } +TEST_CONSTEXPR(match_v2si(_mm_sign_pi32((__m64)(__v2si){0x7FFF, -1}, (__m64)(__v2si){-1, 0x7FFF}), -0x7FFF, -1)); __m64 test_mm_sll_pi16(__m64 a, __m64 b) { // CHECK-LABEL: test_mm_sll_pi16 diff --git a/clang/test/CodeGen/X86/ssse3-builtins.c b/clang/test/CodeGen/X86/ssse3-builtins.c index f70afc01a1963..b7a4a2fe7ccd7 100644 --- a/clang/test/CodeGen/X86/ssse3-builtins.c +++ b/clang/test/CodeGen/X86/ssse3-builtins.c @@ -125,15 +125,18 @@ __m128i test_mm_sign_epi8(__m128i a, __m128i b) { // CHECK: call <16 x i8> @llvm.x86.ssse3.psign.b.128(<16 x i8> %{{.*}}, <16 x i8> %{{.*}}) return _mm_sign_epi8(a, b); } +TEST_CONSTEXPR(match_v16qi(_mm_sign_epi8((__m128i)(__v16qs){11,0,13,14, 0,16,17,18, 19,20,21,22, 23,24,25,26}, (__m128i)(__v16qs){0,1,0,1, -1,1,0,0, 0,0,1,1, -1,0,-1,0}), 0,0,0,14, 0,16,0,0, 0,0,21,22, -23,0,-25,0)); __m128i test_mm_sign_epi16(__m128i a, __m128i b) { // CHECK-LABEL: test_mm_sign_epi16 // CHECK: call <8 x i16> @llvm.x86.ssse3.psign.w.128(<8 x i16> %{{.*}}, <8 x i16> %{{.*}}) return _mm_sign_epi16(a, b); } +TEST_CONSTEXPR(match_v8hi(_mm_sign_epi16((__m128i)(__v8hi){0,-2,0,-4,0,-6,0,-8}, (__m128i)(__v8hi){-1,-2,-3,-4,-5,-6,7,-8}), 0,2,0,4,0,6,0,8)); __m128i test_mm_sign_epi32(__m128i a, __m128i b) { // CHECK-LABEL: test_mm_sign_epi32 // CHECK: call <4 x i32> @llvm.x86.ssse3.psign.d.128(<4 x i32> %{{.*}}, <4 x i32> %{{.*}}) return _mm_sign_epi32(a, b); } +TEST_CONSTEXPR(match_v4si(_mm_sign_epi32((__m128i)(__v4si){-1,-2,-3,-4}, (__m128i)(__v4si){-4,-3,-2,-1}), 1,2,3,4)); From fedbe384519115b25b193db2882b18b6bf253eaa Mon Sep 17 00:00:00 2001 From: Erich Keane Date: Thu, 23 Oct 2025 07:21:29 -0700 Subject: [PATCH 02/31] [OpenACC][CIR] Implement atomic-write lowering (#164627) This is a slightly more complicated variant of this, which supports 'x = expr', so the right hand side is an r-value. This patch implements that, adds some tests, and does some minor refactoring to the infrastructure added for the 'atomic read' to make it more flexible for 'write'. This is the second of four 'atomic' kinds. --- clang/include/clang/AST/StmtOpenACC.h | 1 + clang/lib/AST/StmtOpenACC.cpp | 44 ++++++++++---- clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp | 57 +++++++++++++------ .../test/CIR/CodeGenOpenACC/atomic-write.cpp | 55 ++++++++++++++++++ 4 files changed, 129 insertions(+), 28 deletions(-) create mode 100644 clang/test/CIR/CodeGenOpenACC/atomic-write.cpp diff --git a/clang/include/clang/AST/StmtOpenACC.h b/clang/include/clang/AST/StmtOpenACC.h index 4d52805033410..f5240251b67af 100644 --- a/clang/include/clang/AST/StmtOpenACC.h +++ b/clang/include/clang/AST/StmtOpenACC.h @@ -821,6 +821,7 @@ class OpenACCAtomicConstruct final struct StmtInfo { const Expr *V; const Expr *X; + const Expr *Expr; // TODO: OpenACC: We should expand this as we're implementing the other // atomic construct kinds. }; diff --git a/clang/lib/AST/StmtOpenACC.cpp b/clang/lib/AST/StmtOpenACC.cpp index 2b56c1eea547c..462a10d45fbf0 100644 --- a/clang/lib/AST/StmtOpenACC.cpp +++ b/clang/lib/AST/StmtOpenACC.cpp @@ -324,6 +324,18 @@ OpenACCAtomicConstruct *OpenACCAtomicConstruct::Create( return Inst; } +static std::pair getBinaryOpArgs(const Expr *Op) { + if (const auto *BO = dyn_cast(Op)) { + assert(BO->getOpcode() == BO_Assign); + return {BO->getLHS(), BO->getRHS()}; + } + + const auto *OO = cast(Op); + assert(OO->getOperator() == OO_Equal); + + return {OO->getArg(0), OO->getArg(1)}; +} + const OpenACCAtomicConstruct::StmtInfo OpenACCAtomicConstruct::getAssociatedStmtInfo() const { // This ends up being a vastly simplified version of SemaOpenACCAtomic, since @@ -333,27 +345,35 @@ OpenACCAtomicConstruct::getAssociatedStmtInfo() const { switch (AtomicKind) { case OpenACCAtomicKind::None: - case OpenACCAtomicKind::Write: case OpenACCAtomicKind::Update: case OpenACCAtomicKind::Capture: - assert(false && "Only 'read' has been implemented here"); + assert(false && "Only 'read'/'write' have been implemented here"); return {}; case OpenACCAtomicKind::Read: { // Read only supports the format 'v = x'; where both sides are a scalar // expression. This can come in 2 forms; BinaryOperator or // CXXOperatorCallExpr (rarely). - const Expr *AssignExpr = cast(getAssociatedStmt()); - if (const auto *BO = dyn_cast(AssignExpr)) { - assert(BO->getOpcode() == BO_Assign); - return {BO->getLHS()->IgnoreImpCasts(), BO->getRHS()->IgnoreImpCasts()}; - } - - const auto *OO = cast(AssignExpr); - assert(OO->getOperator() == OO_Equal); - - return {OO->getArg(0)->IgnoreImpCasts(), OO->getArg(1)->IgnoreImpCasts()}; + std::pair BinaryArgs = + getBinaryOpArgs(cast(getAssociatedStmt())); + // We want the L-value for each side, so we ignore implicit casts. + return {BinaryArgs.first->IgnoreImpCasts(), + BinaryArgs.second->IgnoreImpCasts(), /*expr=*/nullptr}; } + case OpenACCAtomicKind::Write: { + // Write supports only the format 'x = expr', where the expression is scalar + // type, and 'x' is a scalar l value. As above, this can come in 2 forms; + // Binary Operator or CXXOperatorCallExpr. + std::pair BinaryArgs = + getBinaryOpArgs(cast(getAssociatedStmt())); + // We want the L-value for ONLY the X side, so we ignore implicit casts. For + // the right side (the expr), we emit it as an r-value so we need to + // maintain implicit casts. + return {/*v=*/nullptr, BinaryArgs.first->IgnoreImpCasts(), + BinaryArgs.second}; } + } + + llvm_unreachable("unknown OpenACC atomic kind"); } OpenACCCacheConstruct *OpenACCCacheConstruct::CreateEmpty(const ASTContext &C, diff --git a/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp b/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp index 77e6f8389c361..b125330321afd 100644 --- a/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp @@ -306,9 +306,10 @@ CIRGenFunction::emitOpenACCCacheConstruct(const OpenACCCacheConstruct &s) { mlir::LogicalResult CIRGenFunction::emitOpenACCAtomicConstruct(const OpenACCAtomicConstruct &s) { - // For now, we are only support 'read', so diagnose. We can switch on the kind - // later once we start implementing the other 3 forms. - if (s.getAtomicKind() != OpenACCAtomicKind::Read) { + // For now, we are only support 'read'/'write', so diagnose. We can switch on + // the kind later once we start implementing the other 2 forms. While we + if (s.getAtomicKind() != OpenACCAtomicKind::Read && + s.getAtomicKind() != OpenACCAtomicKind::Write) { cgm.errorNYI(s.getSourceRange(), "OpenACC Atomic Construct"); return mlir::failure(); } @@ -318,17 +319,41 @@ CIRGenFunction::emitOpenACCAtomicConstruct(const OpenACCAtomicConstruct &s) { // it has custom emit logic. mlir::Location start = getLoc(s.getSourceRange().getBegin()); OpenACCAtomicConstruct::StmtInfo inf = s.getAssociatedStmtInfo(); - // Atomic 'read' only permits 'v = x', where v and x are both scalar L values. - // The getAssociatedStmtInfo strips off implicit casts, which includes - // implicit conversions and L-to-R-Value conversions, so we can just emit it - // as an L value. The Flang implementation has no problem with different - // types, so it appears that the dialect can handle the conversions. - mlir::Value v = emitLValue(inf.V).getPointer(); - mlir::Value x = emitLValue(inf.X).getPointer(); - mlir::Type resTy = convertType(inf.V->getType()); - auto op = mlir::acc::AtomicReadOp::create(builder, start, x, v, resTy, - /*ifCond=*/{}); - emitOpenACCClauses(op, s.getDirectiveKind(), s.getDirectiveLoc(), - s.clauses()); - return mlir::success(); + + switch (s.getAtomicKind()) { + case OpenACCAtomicKind::None: + case OpenACCAtomicKind::Update: + case OpenACCAtomicKind::Capture: + llvm_unreachable("Unimplemented atomic construct type, should have " + "diagnosed/returned above"); + return mlir::failure(); + case OpenACCAtomicKind::Read: { + + // Atomic 'read' only permits 'v = x', where v and x are both scalar L + // values. The getAssociatedStmtInfo strips off implicit casts, which + // includes implicit conversions and L-to-R-Value conversions, so we can + // just emit it as an L value. The Flang implementation has no problem with + // different types, so it appears that the dialect can handle the + // conversions. + mlir::Value v = emitLValue(inf.V).getPointer(); + mlir::Value x = emitLValue(inf.X).getPointer(); + mlir::Type resTy = convertType(inf.V->getType()); + auto op = mlir::acc::AtomicReadOp::create(builder, start, x, v, resTy, + /*ifCond=*/{}); + emitOpenACCClauses(op, s.getDirectiveKind(), s.getDirectiveLoc(), + s.clauses()); + return mlir::success(); + } + case OpenACCAtomicKind::Write: { + mlir::Value x = emitLValue(inf.X).getPointer(); + mlir::Value expr = emitAnyExpr(inf.Expr).getValue(); + auto op = mlir::acc::AtomicWriteOp::create(builder, start, x, expr, + /*ifCond=*/{}); + emitOpenACCClauses(op, s.getDirectiveKind(), s.getDirectiveLoc(), + s.clauses()); + return mlir::success(); + } + } + + llvm_unreachable("unknown OpenACC atomic kind"); } diff --git a/clang/test/CIR/CodeGenOpenACC/atomic-write.cpp b/clang/test/CIR/CodeGenOpenACC/atomic-write.cpp new file mode 100644 index 0000000000000..16855348cb1f1 --- /dev/null +++ b/clang/test/CIR/CodeGenOpenACC/atomic-write.cpp @@ -0,0 +1,55 @@ +// RUN: %clang_cc1 -fopenacc -triple x86_64-linux-gnu -Wno-openacc-self-if-potential-conflict -emit-cir -fclangir -triple x86_64-linux-pc %s -o - | FileCheck %s + +extern "C" bool condition(int x, unsigned int y, float f); +extern "C" double do_thing(float f); + +struct ConvertsToScalar { + operator float(); +}; + +void use(int x, unsigned int y, float f, ConvertsToScalar cts) { + // CHECK: cir.func{{.*}}(%[[X_ARG:.*]]: !s32i{{.*}}, %[[Y_ARG:.*]]: !u32i{{.*}}, %[[F_ARG:.*]]: !cir.float{{.*}}){{.*}}, %[[CTS_ARG:.*]]: !rec_ConvertsToScalar{{.*}}) { + // CHECK-NEXT: %[[X_ALLOC:.*]] = cir.alloca !s32i, !cir.ptr, ["x", init] + // CHECK-NEXT: %[[Y_ALLOC:.*]] = cir.alloca !u32i, !cir.ptr, ["y", init] + // CHECK-NEXT: %[[F_ALLOC:.*]] = cir.alloca !cir.float, !cir.ptr, ["f", init] + // CHECK-NEXT: %[[CTS_ALLOC:.*]] = cir.alloca !rec_ConvertsToScalar, !cir.ptr, ["cts", init] + // + // CHECK-NEXT: cir.store %[[X_ARG]], %[[X_ALLOC]] : !s32i, !cir.ptr + // CHECK-NEXT: cir.store %[[Y_ARG]], %[[Y_ALLOC]] : !u32i, !cir.ptr + // CHECK-NEXT: cir.store %[[F_ARG]], %[[F_ALLOC]] : !cir.float, !cir.ptr + // CHECK-NEXT: cir.store %[[CTS_ARG]], %[[CTS_ALLOC]] : !rec_ConvertsToScalar, !cir.ptr + + // CHECK-NEXT: %[[Y_LOAD:.*]] = cir.load {{.*}}%[[Y_ALLOC]] : !cir.ptr, !u32i + // CHECK-NEXT: %[[Y_TO_FLOAT:.*]] = cir.cast int_to_float %[[Y_LOAD]] : !u32i -> !cir.float + // CHECK-NEXT: %[[F_LOAD:.*]] = cir.load {{.*}}%[[F_ALLOC]] : !cir.ptr, !cir.float + // CHECK-NEXT: %[[MUL:.*]] = cir.binop(mul, %[[Y_TO_FLOAT]], %[[F_LOAD]]) : !cir.float + // CHECK-NEXT: %[[RHS_CAST:.*]] = cir.cast float_to_int %[[MUL]] : !cir.float -> !s32i + // CHECK-NEXT: acc.atomic.write %[[X_ALLOC]] = %[[RHS_CAST]] : !cir.ptr, !s32i +#pragma acc atomic write + x = y * f; + + // CHECK-NEXT: %[[F_LOAD:.*]] = cir.load {{.*}}%[[F_ALLOC]] : !cir.ptr, !cir.float + // CHECK-NEXT: %[[CALL:.*]] = cir.call @do_thing(%[[F_LOAD]]) : (!cir.float) -> !cir.double + // CHECK-NEXT: %[[CALL_CAST:.*]] = cir.cast float_to_int %[[CALL]] : !cir.double -> !u32i + // CHECK-NEXT: acc.atomic.write %[[Y_ALLOC]] = %[[CALL_CAST]] : !cir.ptr, !u32i +#pragma acc atomic write + y = do_thing(f); + + // CHECK-NEXT: %[[X_LOAD:.*]] = cir.load {{.*}}%[[X_ALLOC]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[X_CAST:.*]] = cir.cast int_to_float %[[X_LOAD]] : !s32i -> !cir.float + // CHECK-NEXT: %[[THING_CALL:.*]] = cir.call @do_thing(%[[X_CAST]]) : (!cir.float) -> !cir.double + // CHECK-NEXT: %[[THING_CAST:.*]] = cir.cast floating %[[THING_CALL]] : !cir.double -> !cir.float + // CHECK-NEXT: %[[X_LOAD:.*]] = cir.load {{.*}}%[[X_ALLOC]] : !cir.ptr, !s32i + // CHECK-NEXT: %[[Y_LOAD:.*]] = cir.load {{.*}}%[[Y_ALLOC]] : !cir.ptr, !u32i + // CHECK-NEXT: %[[F_LOAD:.*]] = cir.load {{.*}}%[[F_ALLOC]] : !cir.ptr, !cir.float + // CHECK-NEXT: %[[COND_CALL:.*]] = cir.call @condition(%[[X_LOAD]], %[[Y_LOAD]], %[[F_LOAD]]) : (!s32i, !u32i, !cir.float) -> !cir.bool + // CHECK-NEXT: %[[COND_CAST:.*]] = builtin.unrealized_conversion_cast %[[COND_CALL]] : !cir.bool to i1 + // CHECK-NEXT: acc.atomic.write if(%[[COND_CAST]]) %[[F_ALLOC]] = %[[THING_CAST]] : !cir.ptr, !cir.float +#pragma acc atomic write if (condition(x, y, f)) + f = do_thing(x); + + // CHECK-NEXT: %[[CTS_CONV_CALL:.*]] = cir.call @{{.*}}(%[[CTS_ALLOC]]) : (!cir.ptr) -> !cir.float + // CHECK-NEXT: acc.atomic.write %[[F_ALLOC]] = %[[CTS_CONV_CALL]] : !cir.ptr, !cir.float +#pragma acc atomic write + f = cts; +} From 5d7da0a5cd0031e4a3e4f685e061a0dc6d599ae9 Mon Sep 17 00:00:00 2001 From: Timur Golubovich Date: Thu, 23 Oct 2025 17:26:14 +0300 Subject: [PATCH 03/31] [lldb] Added a warning in case of instruction decode failure (#164413) While testing baremetal lldb, I came across a situation that if an instruction could not be disassembled, lldb will print nothing as an output which might be a bit strange. I added at least printing warning in this case. --- lldb/source/Core/DumpDataExtractor.cpp | 3 ++- lldb/test/API/commands/memory/read/TestMemoryRead.py | 12 ++++++++++++ lldb/test/API/commands/memory/read/main.c | 3 +++ 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/lldb/source/Core/DumpDataExtractor.cpp b/lldb/source/Core/DumpDataExtractor.cpp index 37dffc72d76ac..a0dc752a3466d 100644 --- a/lldb/source/Core/DumpDataExtractor.cpp +++ b/lldb/source/Core/DumpDataExtractor.cpp @@ -157,7 +157,8 @@ static lldb::offset_t DumpInstructions(const DataExtractor &DE, Stream *s, exe_scope->CalculateExecutionContext(exe_ctx); disassembler_sp->GetInstructionList().Dump( s, show_address, show_bytes, show_control_flow_kind, &exe_ctx); - } + } else if (number_of_instructions) + s->Printf("failed to decode instructions at 0x%" PRIx64 ".", addr); } } else s->Printf("invalid target"); diff --git a/lldb/test/API/commands/memory/read/TestMemoryRead.py b/lldb/test/API/commands/memory/read/TestMemoryRead.py index 67b28ee79067b..dbe6d9e7a62ea 100644 --- a/lldb/test/API/commands/memory/read/TestMemoryRead.py +++ b/lldb/test/API/commands/memory/read/TestMemoryRead.py @@ -41,6 +41,18 @@ def test_memory_read_c_string(self): " Consider increasing the maximum read length.", ) + @skipIf(archs=no_match("^(riscv|aarch64).*")) + def test_memory_read_instruction_decode_failure(self): + """Test the 'memory read' command with instruction format.""" + self.build_run_stop() + + # assume that 0xffffff is invalid instruction in RISC-V and AArch64, + # so decoding it will fail + self.expect( + "memory read --format instruction `&my_insns[0]` `&my_insns[3]`", + substrs=["failed to decode instructions at"], + ) + def test_memory_read(self): """Test the 'memory read' command with plain and vector formats.""" self.build_run_stop() diff --git a/lldb/test/API/commands/memory/read/main.c b/lldb/test/API/commands/memory/read/main.c index 774b47bfeabb0..360f85af919cc 100644 --- a/lldb/test/API/commands/memory/read/main.c +++ b/lldb/test/API/commands/memory/read/main.c @@ -5,5 +5,8 @@ int main(int argc, const char *argv[]) { double my_double = 1234.5678; int my_ints[] = {2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22}; uint64_t my_uint64s[] = {0, 1, 2, 3, 4, 5, 6, 7}; + // assume that 0xffffff is invalid instruction in RISC-V and AArch64, + // so decoding it will fail + char my_insns[] = {0xff, 0xff, 0xff}; return 0; // break here } From 45f97f71aff8c22f1880e817b6f05ae6ae3afa72 Mon Sep 17 00:00:00 2001 From: "A. Jiang" Date: Thu, 23 Oct 2025 22:32:21 +0800 Subject: [PATCH 04/31] [libc++][docs] Add missing column headers for GitHub issues (#164745) We started to list GitHub issues in the status CSV tables/pages due to e0d0b90d52f54f291c1042046ddf22e925408235. However, the changes made existing column header insufficient. We probably need to add new column headers for GitHub issues. --- libcxx/docs/Status/Cxx17Issues.csv | 16 ++++++++-------- libcxx/docs/Status/Cxx17Papers.csv | 16 ++++++++-------- libcxx/docs/Status/Cxx20Issues.csv | 20 ++++++++++---------- libcxx/docs/Status/Cxx20Papers.csv | 22 +++++++++++----------- libcxx/docs/Status/Cxx23Issues.csv | 16 ++++++++-------- libcxx/docs/Status/Cxx23Papers.csv | 16 ++++++++-------- libcxx/docs/Status/Cxx2cIssues.csv | 18 +++++++++--------- libcxx/docs/Status/Cxx2cPapers.csv | 16 ++++++++-------- 8 files changed, 70 insertions(+), 70 deletions(-) diff --git a/libcxx/docs/Status/Cxx17Issues.csv b/libcxx/docs/Status/Cxx17Issues.csv index 4e8cbf9abb893..2fb7f14996be0 100644 --- a/libcxx/docs/Status/Cxx17Issues.csv +++ b/libcxx/docs/Status/Cxx17Issues.csv @@ -1,4 +1,4 @@ -"Issue #","Issue Name","Meeting","Status","First released version","Notes" +"Issue #","Issue Name","Meeting","Status","First released version","GitHub issue","Notes" "`LWG2016 `__","Allocators must be no-throw swappable","2014-11 (Urbana)","|Complete|","","`#103224 `__","" "`LWG2118 `__","``unique_ptr``\ for array does not support cv qualification conversion of actual argument","2014-11 (Urbana)","|Complete|","","`#103225 `__","" "`LWG2170 `__","Aggregates cannot be ``DefaultConstructible``\ ","2014-11 (Urbana)","|Complete|","","`#103226 `__","" @@ -23,7 +23,7 @@ "`LWG2365 `__","Missing noexcept in ``shared_ptr::shared_ptr(nullptr_t)``\ ","2014-11 (Urbana)","|Complete|","","`#103246 `__","" "`LWG2376 `__","``bad_weak_ptr::what()``\ overspecified","2014-11 (Urbana)","|Complete|","","`#103247 `__","" "`LWG2387 `__","More nested types that must be accessible and unambiguous","2014-11 (Urbana)","|Complete|","","`#103248 `__","" -"","","","","","" +"","","","","","","" "`LWG2059 `__","C++0x ambiguity problem with map::erase","2015-05 (Lenexa)","|Complete|","","`#103249 `__","" "`LWG2063 `__","Contradictory requirements for string move assignment","2015-05 (Lenexa)","|Complete|","","`#103250 `__","" "`LWG2076 `__","Bad CopyConstructible requirement in set constructors","2015-05 (Lenexa)","|Complete|","","`#103251 `__","" @@ -59,7 +59,7 @@ "`LWG2470 `__","Allocator's destroy function should be allowed to fail to instantiate","2015-05 (Lenexa)","|Complete|","","`#103283 `__","" "`LWG2482 `__","[c.strings] Table 73 mentions nonexistent functions","2015-05 (Lenexa)","|Complete|","","`#103284 `__","" "`LWG2488 `__","Placeholders should be allowed and encouraged to be constexpr","2015-05 (Lenexa)","|Complete|","","`#103285 `__","" -"","","","","","" +"","","","","","","" "`LWG1169 `__","``num_get``\ not fully compatible with ``strto*``\ ","2015-10 (Kona)","|Complete|","","`#103286 `__","" "`LWG2072 `__","Unclear wording about capacity of temporary buffers","2015-10 (Kona)","|Complete|","","`#103287 `__","" "`LWG2101 `__","Some transformation types can produce impossible types","2015-10 (Kona)","|Complete|","","`#103288 `__","" @@ -98,7 +98,7 @@ "`LWG2489 `__","``mem_fn()``\ should be ``noexcept``\ ","2015-10 (Kona)","|Complete|","","`#103335 `__","" "`LWG2492 `__","Clarify requirements for ``comp``\ ","2015-10 (Kona)","|Complete|","","`#103336 `__","" "`LWG2495 `__","There is no such thing as an Exception Safety element","2015-10 (Kona)","|Complete|","","`#103337 `__","" -"","","","","","" +"","","","","","","" "`LWG2192 `__","Validity and return type of ``std::abs(0u)``\ is unclear","2016-02 (Jacksonville)","|Complete|","","`#103338 `__","" "`LWG2276 `__","Missing requirement on ``std::promise::set_exception``\ ","2016-02 (Jacksonville)","|Complete|","","`#103339 `__","" "`LWG2296 `__","``std::addressof``\ should be ``constexpr``\ ","2016-02 (Jacksonville)","|Complete|","","`#103340 `__","" @@ -128,7 +128,7 @@ "`LWG2585 `__","``forward_list::resize(size_type, const value_type&)``\ effects incorrect","2016-02 (Jacksonville)","|Complete|","","`#103363 `__","" "`LWG2586 `__","Wrong value category used in ``scoped_allocator_adaptor::construct()``\ ","2016-02 (Jacksonville)","|Complete|","","`#103364 `__","" "`LWG2590 `__","Aggregate initialization for ``std::array``\ ","2016-02 (Jacksonville)","|Complete|","","`#103365 `__","" -"","","","","","" +"","","","","","","" "`LWG2181 `__","Exceptions from seed sequence operations","2016-06 (Oulu)","|Complete|","","`#103367 `__","" "`LWG2309 `__","mutex::lock() should not throw device_or_resource_busy","2016-06 (Oulu)","|Complete|","","`#103368 `__","" "`LWG2310 `__","Public exposition only member in std::array","2016-06 (Oulu)","|Complete|","","`#103369 `__","" @@ -179,7 +179,7 @@ "`LWG2726 `__","``[recursive_]directory_iterator::increment(error_code&)`` is underspecified","2016-06 (Oulu)","|Complete|","","`#103429 `__","" "`LWG2727 `__","Parallel algorithms with constexpr specifier","2016-06 (Oulu)","","","`#99968 `__","" "`LWG2728 `__","status(p).permissions() and symlink_status(p).permissions() are not specified","2016-06 (Oulu)","|Complete|","","`#103430 `__","" -"","","","","","" +"","","","","","","" "`LWG2062 `__","Effect contradictions w/o no-throw guarantee of std::function swaps","2016-11 (Issaquah)","|Complete|","","`#103431 `__","" "`LWG2166 `__","Heap property underspecified?","2016-11 (Issaquah)","","","`#99969 `__","" "`LWG2221 `__","No formatted output operator for nullptr","2016-11 (Issaquah)","|Complete|","","`#103432 `__","" @@ -257,7 +257,7 @@ "`LWG2773 `__","Making std::ignore constexpr","2016-11 (Issaquah)","|Complete|","","`#103541 `__","" "`LWG2777 `__","basic_string_view::copy should use char_traits::copy","2016-11 (Issaquah)","|Complete|","","`#103542 `__","" "`LWG2778 `__","basic_string_view is missing constexpr","2016-11 (Issaquah)","|Complete|","","`#103543 `__","" -"","","","","","" +"","","","","","","" "`LWG2260 `__","Missing requirement for Allocator::pointer","2017-02 (Kona)","|Complete|","","`#103544 `__","" "`LWG2676 `__","Provide filesystem::path overloads for File-based streams","2017-02 (Kona)","|Complete|","","`#103545 `__","" "`LWG2768 `__","any_cast and move semantics","2017-02 (Kona)","|Complete|","","`#103546 `__","" @@ -309,7 +309,7 @@ "`LWG2911 `__","An is_aggregate type trait is needed","2017-02 (Kona)","|Complete|","","`#103597 `__","" "`LWG2921 `__","packaged_task and type-erased allocators","2017-02 (Kona)","|Complete|","20","`#103598 `__","Originally implemented in LLVM 6 but reverted later. Old documentation incorrectly said it was implemented." "`LWG2934 `__","optional doesn't compare with T","2017-02 (Kona)","|Complete|","","`#103599 `__","" -"","","","","","" +"","","","","","","" "`LWG2901 `__","Variants cannot properly support allocators","2017-07 (Toronto)","|Complete|","","`#103600 `__","" "`LWG2955 `__","``to_chars / from_chars``\ depend on ``std::string``\ ","2017-07 (Toronto)","|Nothing To Do|","","`#103601 `__","Resolved by `P0682R1 `__" "`LWG2956 `__","``filesystem::canonical()``\ still defined in terms of ``absolute(p, base)``\ ","2017-07 (Toronto)","|Complete|","","`#103602 `__","" diff --git a/libcxx/docs/Status/Cxx17Papers.csv b/libcxx/docs/Status/Cxx17Papers.csv index ac9bb06e33ae0..1a9d3b08f3ec3 100644 --- a/libcxx/docs/Status/Cxx17Papers.csv +++ b/libcxx/docs/Status/Cxx17Papers.csv @@ -1,4 +1,4 @@ -"Paper #","Paper Name","Meeting","Status","First released version","Notes" +"Paper #","Paper Name","Meeting","Status","First released version","GitHub issue","Notes" "`N3911 `__","TransformationTrait Alias ``void_t``\ .","2014-11 (Urbana)","|Complete|","3.6","`#103603 `__","" "`N4089 `__","Safe conversions in ``unique_ptr``\ .","2014-11 (Urbana)","|Complete|","5","`#99936 `__","" "`N4169 `__","A proposal to add invoke function template","2014-11 (Urbana)","|Complete|","3.7","`#103604 `__","" @@ -10,13 +10,13 @@ "`N4280 `__","Non-member size() and more","2014-11 (Urbana)","|Complete|","3.6","`#103610 `__","" "`N4284 `__","Contiguous Iterators.","2014-11 (Urbana)","|Complete|","3.6","`#103611 `__","" "`N4285 `__","Cleanup for exception-specification and throw-expression.","2014-11 (Urbana)","|Complete|","4","`#103612 `__","" -"","","","","","" +"","","","","","","" "`N4387 `__","improving pair and tuple","2015-05 (Lenexa)","|Complete|","4","`#103613 `__","" "`N4389 `__","bool_constant","2015-05 (Lenexa)","|Complete|","3.7","`#103614 `__","" "`N4508 `__","shared_mutex for C++17","2015-05 (Lenexa)","|Complete|","3.7","`#103615 `__","" "`N4366 `__","LWG 2228 missing SFINAE rule","2015-05 (Lenexa)","|Complete|","3.1","`#103616 `__","" "`N4510 `__","Minimal incomplete type support for standard containers, revision 4","2015-05 (Lenexa)","|Complete|","3.6","`#103617 `__","" -"","","","","","" +"","","","","","","" "`P0004R1 `__","Remove Deprecated iostreams aliases.","2015-10 (Kona)","|Complete|","3.8","`#103618 `__","" "`P0006R0 `__","Adopt Type Traits Variable Templates for C++17.","2015-10 (Kona)","|Complete|","3.8","`#103619 `__","" "`P0092R1 `__","Polishing ","2015-10 (Kona)","|Complete|","3.8","`#103620 `__","" @@ -24,7 +24,7 @@ "`P0156R0 `__","Variadic lock_guard(rev 3).","2015-10 (Kona)","|Nothing To Do|","","`#103622 `__","Pulled at the 2017-01 meeting in Kona" "`P0074R0 `__","Making ``std::owner_less``\ more flexible","2015-10 (Kona)","|Complete|","3.8","`#103623 `__","" "`P0013R1 `__","Logical type traits rev 2","2015-10 (Kona)","|Complete|","3.8","`#103624 `__","" -"","","","","","" +"","","","","","","" "`P0024R2 `__","The Parallelism TS Should be Standardized","2016-02 (Jacksonville)","|Partial|","","`#99938 `__","" "`P0226R1 `__","Mathematical Special Functions for C++17","2016-02 (Jacksonville)","|In Progress|","","`#99939 `__","Progress is tracked `here `__" "`P0220R1 `__","Adopt Library Fundamentals V1 TS Components for C++17","2016-02 (Jacksonville)","|Complete|","16","`#103625 `__","" @@ -40,7 +40,7 @@ "`P0031R0 `__","A Proposal to Add Constexpr Modifiers to reverse_iterator, move_iterator, array and Range Access","2016-02 (Jacksonville)","|Complete|","4","`#103636 `__","" "`P0272R1 `__","Give ``std::string``\ a non-const ``.data()``\ member function","2016-02 (Jacksonville)","|Complete|","3.9","`#103637 `__","" "`P0077R2 `__","``is_callable``\ , the missing INVOKE related trait","2016-02 (Jacksonville)","|Complete|","3.9","`#103638 `__","" -"","","","","","" +"","","","","","","" "`P0032R3 `__","Homogeneous interface for variant, any and optional","2016-06 (Oulu)","|Complete|","4","`#103639 `__","" "`P0040R3 `__","Extending memory management tools","2016-06 (Oulu)","|Complete|","4","`#103640 `__","" "`P0063R3 `__","C++17 should refer to C11 instead of C99","2016-06 (Oulu)","|Complete|","7","`#103642 `__","" @@ -69,7 +69,7 @@ "`P0392R0 `__","Adapting string_view by filesystem paths","2016-06 (Oulu)","|Complete|","4","`#103665 `__","" "`P0393R3 `__","Making Variant Greater Equal","2016-06 (Oulu)","|Complete|","4","`#103666 `__","" "`P0394R4 `__","Hotel Parallelifornia: terminate() for Parallel Algorithms Exception Handling","2016-06 (Oulu)","|Complete|","17","`#103667 `__","" -"","","","","","" +"","","","","","","" "`P0003R5 `__","Removing Deprecated Exception Specifications from C++17","2016-11 (Issaquah)","|Complete|","5","`#103668 `__","" "`P0067R5 `__","Elementary string conversions, revision 5","2016-11 (Issaquah)","|Partial|","","`#99940 `__","For integer types, ``std::(to|from)_chars`` has been available since v7; for ``float`` and ``double``, ``std::to_chars`` since v14 and ``std::from_chars`` since v20. Support is complete except for ``long double``." "`P0403R1 `__","Literal suffixes for ``basic_string_view``\ ","2016-11 (Issaquah)","|Complete|","4","`#103669 `__","" @@ -88,7 +88,7 @@ "`P0516R0 `__","Clarify That shared_future's Copy Operations have Wide Contracts","2016-11 (Issaquah)","|Complete|","4","`#103679 `__","" "`P0517R0 `__","Make future_error Constructible","2016-11 (Issaquah)","|Complete|","4","`#103680 `__","" "`P0521R0 `__","Proposed Resolution for CA 14 (shared_ptr use_count/unique)","2016-11 (Issaquah)","|Complete|","18","`#103681 `__","" -"","","","","","" +"","","","","","","" "`P0156R2 `__","Variadic Lock guard(rev 5)","2017-02 (Kona)","|Complete|","5","`#103682 `__","" "`P0270R3 `__","Removing C dependencies from signal handler wording","2017-02 (Kona)","|Nothing To Do|","","`#99946 `__","" "`P0298R3 `__","A byte type definition","2017-02 (Kona)","|Complete|","5","`#103683 `__","" @@ -108,6 +108,6 @@ "`P0607R0 `__","Inline Variables for the Standard Library","2017-02 (Kona)","|In Progress|","6","`#99951 `__","The parts of P0607 that are not done are the ```` bits" "`P0618R0 `__","Deprecating ","2017-02 (Kona)","|Complete|","15","`#103697 `__","" "`P0623R0 `__","Final C++17 Parallel Algorithms Fixes","2017-02 (Kona)","|Nothing To Do|","","`#103698 `__","" -"","","","","","" +"","","","","","","" "`P0682R1 `__","Repairing elementary string conversions","2017-07 (Toronto)","","","`#99952 `__","" "`P0739R0 `__","Some improvements to class template argument deduction integration into the standard library","2017-07 (Toronto)","|Complete|","5","`#103699 `__","" diff --git a/libcxx/docs/Status/Cxx20Issues.csv b/libcxx/docs/Status/Cxx20Issues.csv index 646615b2d8d7f..3d01ff5bbbdfb 100644 --- a/libcxx/docs/Status/Cxx20Issues.csv +++ b/libcxx/docs/Status/Cxx20Issues.csv @@ -1,4 +1,4 @@ -"Issue #","Issue Name","Meeting","Status","First released version","Notes" +"Issue #","Issue Name","Meeting","Status","First released version","GitHub issue","Notes" "`LWG2070 `__","``allocate_shared``\ should use ``allocator_traits::construct``\ ","2017-07 (Toronto)","|Nothing To Do|","","`#103733 `__","Resolved by `P0674R1 `__" "`LWG2444 `__","Inconsistent complexity for ``std::sort_heap``\ ","2017-07 (Toronto)","|Nothing To Do|","","`#103734 `__","" "`LWG2593 `__","Moved-from state of Allocators","2017-07 (Toronto)","|Nothing To Do|","","`#100220 `__","" @@ -12,7 +12,7 @@ "`LWG2961 `__","Bad postcondition for ``set_default_resource``\ ","2017-07 (Toronto)","|Complete|","16","`#103740 `__","" "`LWG2966 `__","Incomplete resolution of US 74","2017-07 (Toronto)","|Nothing To Do|","","`#103741 `__","" "`LWG2974 `__","Diagnose out of bounds ``tuple_element/variant_alternative``\ ","2017-07 (Toronto)","|Complete|","","`#103742 `__","" -"","","","","","" +"","","","","","","" "`LWG2779 `__","[networking.ts] Relax requirements on buffer sequence iterators","2017-11 (Albuquerque)","|Nothing To Do|","","`#100223 `__","" "`LWG2870 `__","Default value of parameter theta of polar should be dependent","2017-11 (Albuquerque)","|Complete|","","`#103743 `__","" "`LWG2935 `__","What should create_directories do when p already exists but is not a directory?","2017-11 (Albuquerque)","|Nothing To Do|","","`#103744 `__","" @@ -39,7 +39,7 @@ "`LWG2998 `__","Requirements on function objects passed to {``forward_``,}list-specific algorithms","2017-11 (Albuquerque)","|Nothing To Do|","","`#103762 `__","" "`LWG3001 `__","weak_ptr::element_type needs remove_extent_t","2017-11 (Albuquerque)","|Complete|","14","`#103763 `__","" "`LWG3024 `__","variant's copies must be deleted instead of disabled via SFINAE","2017-11 (Albuquerque)","|Complete|","","`#103764 `__","" -"","","","","","" +"","","","","","","" "`LWG2164 `__","What are the semantics of ``vector.emplace(vector.begin(), vector.back())``\ ?","2018-03 (Jacksonville)","|Complete|","","`#103765 `__","" "`LWG2243 `__","``istream::putback``\ problem","2018-03 (Jacksonville)","|Complete|","","`#103766 `__","" "`LWG2816 `__","``resize_file``\ has impossible postcondition","2018-03 (Jacksonville)","|Nothing To Do|","","`#103770 `__","" @@ -74,7 +74,7 @@ "`LWG3048 `__","``transform_reduce(exec, first1, last1, first2, init)``\ discards execution policy","2018-03 (Jacksonville)","|Complete|","17","`#103794 `__","" "`LWG3051 `__","Floating point classifications were inadvertently changed in P0175","2018-03 (Jacksonville)","|Nothing To Do|","","`#103795 `__","" "`LWG3075 `__","``basic_string``\ needs deduction guides from ``basic_string_view``\ ","2018-03 (Jacksonville)","|Complete|","","`#103796 `__","" -"","","","","","" +"","","","","","","" "`LWG2139 `__","What is a user-defined type?","2018-06 (Rapperswil)","","","`#100233 `__","" "`LWG2970 `__","Return type of std::visit misspecified","2018-06 (Rapperswil)","|Complete|","11","`#103797 `__","" "`LWG3058 `__","Parallel adjacent_difference shouldn't require creating temporaries","2018-06 (Rapperswil)","","","`#100234 `__","" @@ -90,7 +90,7 @@ "`LWG3100 `__","Unnecessary and confusing ""empty span"" wording","2018-06 (Rapperswil)","|Nothing To Do|","","`#103803 `__","" "`LWG3102 `__","Clarify span iterator and ``const_iterator`` behavior","2018-06 (Rapperswil)","|Complete|","","`#103804 `__","" "`LWG3104 `__","Fixing duration division","2018-06 (Rapperswil)","|Complete|","","`#103805 `__","" -"","","","","","" +"","","","","","","" "`LWG2183 `__","Muddled allocator requirements for ``match_results``\ constructors","2018-11 (San Diego)","|Complete|","","`#103806 `__","" "`LWG2184 `__","Muddled allocator requirements for ``match_results``\ assignments","2018-11 (San Diego)","|Complete|","","`#103807 `__","" "`LWG2412 `__","``promise::set_value()``\ and ``promise::get_future()``\ should not race","2018-11 (San Diego)","","","`#100239 `__","" @@ -128,7 +128,7 @@ "`LWG3148 `__","````\ should be freestanding","2018-11 (San Diego)","","","`#100250 `__","" "`LWG3153 `__","``Common``\ and ``common_type``\ have too little in common","2018-11 (San Diego)","|Complete|","13","`#103831 `__","" "`LWG3154 `__","``Common``\ and ``CommonReference``\ have a common defect","2018-11 (San Diego)","|Nothing To Do|","","`#103832 `__","" -"","","","","","" +"","","","","","","" "`LWG3012 `__","``atomic``\ is unimplementable for non-``is_trivially_copy_constructible T``\ ","2019-02 (Kona)","","","`#100252 `__","" "`LWG3040 `__","``basic_string_view::starts_with``\ *Effects* are incorrect","2019-02 (Kona)","|Complete|","","`#103834 `__","" "`LWG3077 `__","``(push|emplace)_back``\ should invalidate the ``end``\ iterator","2019-02 (Kona)","|Nothing To Do|","","`#103835 `__","" @@ -142,7 +142,7 @@ "`LWG3179 `__","``subrange``\ should always model ``Range``\ ","2019-02 (Kona)","|Nothing To Do|","","`#103842 `__","" "`LWG3180 `__","Inconsistently named return type for ``ranges::minmax_element``\ ","2019-02 (Kona)","|Complete|","15","`#103844 `__","" "`LWG3182 `__","Specification of ``Same``\ could be clearer","2019-02 (Kona)","|Complete|","15","`#103845 `__","" -"","","","","","" +"","","","","","","" "`LWG2899 `__","``is_(nothrow_)move_constructible``\ and ``tuple``\ , ``optional``\ and ``unique_ptr``\ ","2019-07 (Cologne)","","","`#100255 `__","" "`LWG3055 `__","``path::operator+=(*single-character*)``\ misspecified","2019-07 (Cologne)","|Complete|","7","`#103846 `__","" "`LWG3158 `__","``tuple(allocator_arg_t, const Alloc&)``\ should be conditionally explicit","2019-07 (Cologne)","|Complete|","10","`#103847 `__","" @@ -160,7 +160,7 @@ "`LWG3206 `__","``year_month_day``\ conversion to ``sys_days``\ uses not-existing member function","2019-07 (Cologne)","|Complete|","","`#103858 `__","" "`LWG3208 `__","``Boolean``\ 's expression requirements are ordered inconsistently","2019-07 (Cologne)","|Nothing To Do|","","`#103860 `__","" "`LWG3209 `__","Expression in ``year::ok()``\ returns clause is ill-formed","2019-07 (Cologne)","|Complete|","","`#103861 `__","" -"","","","","","" +"","","","","","","" "`LWG3231 `__","``year_month_day_last::day``\ specification does not cover ``!ok()``\ values","2019-11 (Belfast)","|Nothing To Do|","","`#103862 `__","" "`LWG3225 `__","``zoned_time``\ converting constructor shall not be ``noexcept``\ ","2019-11 (Belfast)","|Complete|","19","`#103863 `__","" "`LWG3190 `__","``std::allocator::allocate``\ sometimes returns too little storage","2019-11 (Belfast)","|Complete|","14","`#103864 `__","" @@ -188,7 +188,7 @@ "`LWG3276 `__","Class ``split_view::outer_iterator::value_type``\ should inherit from ``view_interface``\ ","2019-11 (Belfast)","|Complete|","15","`#103881 `__","" "`LWG3277 `__","Pre-increment on prvalues is not a requirement of ``weakly_incrementable``\ ","2019-11 (Belfast)","|Nothing To Do|","","`#103882 `__","" "`LWG3149 `__","``DefaultConstructible``\ should require default initialization","2019-11 (Belfast)","|Complete|","13","`#103883 `__","" -"","","","","","" +"","","","","","","" "`LWG1203 `__","More useful rvalue stream insertion","2020-02 (Prague)","|Complete|","12","`#103884 `__","" "`LWG2859 `__","Definition of *reachable* in [ptr.launder] misses pointer arithmetic from pointer-interconvertible object","2020-02 (Prague)","","","`#100269 `__","" "`LWG3018 `__","``shared_ptr``\ of function type","2020-02 (Prague)","|Nothing To Do|","","`#103885 `__","" @@ -298,5 +298,5 @@ "`LWG3396 `__","Clarify point of reference for ``source_location::current()``\ (DE 169)","2020-02 (Prague)","|Nothing To Do|","16","`#103995 `__","" "`LWG3397 `__","``ranges::basic_istream_view::iterator``\ should not provide ``iterator_category``\ ","2020-02 (Prague)","|Complete|","16","`#103996 `__","" "`LWG3398 `__","``tuple_element_t``\ is also wrong for ``const subrange``\ ","2020-02 (Prague)","|Complete|","14","`#103997 `__","" -"","","","","","" +"","","","","","","" "`LWG3446 `__","``indirectly_readable_traits``\ ambiguity for types with both ``value_type``\ and ``element_type``\ ","2020-11 (Virtual)","|Complete|","13","`#103998 `__","" diff --git a/libcxx/docs/Status/Cxx20Papers.csv b/libcxx/docs/Status/Cxx20Papers.csv index a0c49df0a3f87..7fbccde688009 100644 --- a/libcxx/docs/Status/Cxx20Papers.csv +++ b/libcxx/docs/Status/Cxx20Papers.csv @@ -1,7 +1,7 @@ -"Paper #","Paper Name","Meeting","Status","First released version","Notes" +"Paper #","Paper Name","Meeting","Status","First released version","GitHub issue","Notes" "`P0463R1 `__","Endian just Endian","2017-07 (Toronto)","|Complete|","7","`#103999 `__","" "`P0674R1 `__","Extending make_shared to Support Arrays","2017-07 (Toronto)","|Complete|","15","`#104000 `__","" -"","","","","","" +"","","","","","","" "`P0020R6 `__","Floating Point Atomic","2017-11 (Albuquerque)","|Complete|","18","`#104001 `__","The feature-test macro was not set until LLVM 20." "`P0053R7 `__","C++ Synchronized Buffered Ostream","2017-11 (Albuquerque)","|Complete|","18","`#104002 `__","" "`P0202R3 `__","Add constexpr modifiers to functions in and Headers","2017-11 (Albuquerque)","|Complete|","12","`#104003 `__","" @@ -16,7 +16,7 @@ "`P0767R1 `__","Deprecate POD","2017-11 (Albuquerque)","|Complete|","21","`#104013 `__","It was previously erroneously marked as complete in LLVM 7." "`P0768R1 `__","Library Support for the Spaceship (Comparison) Operator","2017-11 (Albuquerque)","|Complete|","","`#104014 `__","" "`P0777R1 `__","Treating Unnecessary ``decay``\ ","2017-11 (Albuquerque)","|Complete|","7","`#104016 `__","" -"","","","","","" +"","","","","","","" "`P0122R7 `__","","2018-03 (Jacksonville)","|Complete|","7","`#104017 `__","" "`P0355R7 `__","Extending chrono to Calendars and Time Zones","2018-03 (Jacksonville)","|Partial|","","`#99982 `__","See the `Github issue `__ for detailed status" "`P0551R3 `__","Thou Shalt Not Specialize ``std``\ Function Templates!","2018-03 (Jacksonville)","|Complete|","11","`#104018 `__","" @@ -26,7 +26,7 @@ "`P0858R0 `__","Constexpr iterator requirements","2018-03 (Jacksonville)","|Complete|","12","`#104024 `__","" "`P0905R1 `__","Symmetry for spaceship","2018-03 (Jacksonville)","|Complete|","7","`#104025 `__","" "`P0966R1 `__","``string::reserve``\ Should Not Shrink","2018-03 (Jacksonville)","|Complete|","12","`#104026 `__","It was previously erroneously marked as complete in version 8. See `bug 45368 `__" -"","","","","","" +"","","","","","","" "`P0019R8 `__","Atomic Ref","2018-06 (Rapperswil)","|Complete|","19","`#104028 `__","" "`P0458R2 `__","Checking for Existence of an Element in Associative Containers","2018-06 (Rapperswil)","|Complete|","13","`#104029 `__","" "`P0475R1 `__","LWG 2511: guaranteed copy elision for piecewise construction","2018-06 (Rapperswil)","|Complete|","","`#104031 `__","" @@ -50,7 +50,7 @@ "`P1023R0 `__","constexpr comparison operators for std::array","2018-06 (Rapperswil)","|Complete|","8","`#104103 `__","" "`P1025R1 `__","Update The Reference To The Unicode Standard","2018-06 (Rapperswil)","","","`#100598 `__","" "`P1120R0 `__","Consistency improvements for <=> and other comparison operators","2018-06 (Rapperswil)","","","`#99989 `__","" -"","","","","","" +"","","","","","","" "`P0318R1 `__","unwrap_ref_decay and unwrap_reference","2018-11 (San Diego)","|Complete|","8","`#104105 `__","" "`P0356R5 `__","Simplified partial function application","2018-11 (San Diego)","|Complete|","13","`#104106 `__","" "`P0357R3 `__","reference_wrapper for incomplete types","2018-11 (San Diego)","|Complete|","8","`#104107 `__","" @@ -80,7 +80,7 @@ "`P1248R1 `__","Remove CommonReference requirement from StrictWeakOrdering (a.k.a Fixing Relations)","2018-11 (San Diego)","|Complete|","13","`#104131 `__","" "`P1285R0 `__","Improving Completeness Requirements for Type Traits","2018-11 (San Diego)","","","`#99995 `__","" "`P1353R0 `__","Missing feature test macros","2018-11 (San Diego)","|Complete|","19","`#100006 `__","" -"","","","","","" +"","","","","","","" "`P0339R6 `__","polymorphic_allocator<> as a vocabulary type","2019-02 (Kona)","|Complete|","16","`#104132 `__","" "`P0340R3 `__","Making std::underlying_type SFINAE-friendly","2019-02 (Kona)","|Complete|","9","`#104133 `__","" "`P0738R2 `__","I Stream, You Stream, We All Stream for istream_iterator","2019-02 (Kona)","","","`#100007 `__","" @@ -98,7 +98,7 @@ "`P1462R1 `__","Mandating the Standard Library: Clause 20 - Strings library","2019-02 (Kona)","|Complete|","9","`#104145 `__","" "`P1463R1 `__","Mandating the Standard Library: Clause 21 - Containers library","2019-02 (Kona)","","","`#100010 `__","" "`P1464R1 `__","Mandating the Standard Library: Clause 22 - Iterators library","2019-02 (Kona)","|Complete|","9","`#104147 `__","" -"","","","","","" +"","","","","","","" "`P0325R4 `__","to_array from LFTS with updates","2019-07 (Cologne)","|Complete|","10","`#104149 `__","" "`P0408R7 `__","Efficient Access to basic_stringbuf's Buffer","2019-07 (Cologne)","|Complete|","17","`#104150 `__","" "`P0466R5 `__","Layout-compatibility and Pointer-interconvertibility Traits","2019-07 (Cologne)","","","`#100013 `__","" @@ -133,7 +133,7 @@ "`P1652R1 `__","Printf corner cases in std::format","2019-07 (Cologne)","|Complete|","14","`#104177 `__","" "`P1661R1 `__","Remove dedicated precalculated hash lookup interface","2019-07 (Cologne)","|Nothing To Do|","","`#104178 `__","" "`P1754R1 `__","Rename concepts to standard_case for C++20, while we still can","2019-07 (Cologne)","|Complete|","15","`#104179 `__","" -"","","","","","" +"","","","","","","" "`P0883R2 `__","Fixing Atomic Initialization","2019-11 (Belfast)","|Complete|","14","`#104180 `__","shared_ptr and floating-point changes weren't applied as they themselves aren't implemented yet. Also, ``ATOMIC_FLAG_INIT`` was marked deprecated in version 14, but was undeprecated with the implementation of LWG3659 in version 15." "`P1391R4 `__","Range constructor for std::string_view","2019-11 (Belfast)","|Complete|","14","`#104181 `__","" "`P1394R4 `__","Range constructor for std::span","2019-11 (Belfast)","|Complete|","14","`#104182 `__","" @@ -163,7 +163,7 @@ "`P1960R0 `__","NB Comment Changes Reviewed by SG1","2019-11 (Belfast)","","","`#100033 `__","" "`P1961R0 `__","Harmonizing the definitions of total order for pointers","2019-11 (Belfast)","","","`#100611 `__","" "`P1965R0 `__","Blanket Wording for Specifying ""Hidden Friends""","2019-11 (Belfast)","","","`#100034 `__","" -"","","","","","" +"","","","","","","" "`P0586R2 `__","Safe integral comparisons","2020-02 (Prague)","|Complete|","13","`#104199 `__","" "`P0593R6 `__","Implicit creation of objects for low-level object manipulation","2020-02 (Prague)","","","`#100035 `__","" "`P1115R3 `__","Improving the Return Value of Erase-Like Algorithms II: Free erase/erase if","2020-02 (Prague)","|Complete|","11","`#104200 `__","" @@ -191,7 +191,7 @@ "`P2102R0 `__","Make 'implicit expression variations' more explicit (Wording for US185)","2020-02 (Prague)","|Complete|","15","`#100042 `__","" "`P2106R0 `__","Alternative wording for GB315 and GB316","2020-02 (Prague)","|Complete|","15","`#104215 `__","" "`P2116R0 `__","Remove tuple-like protocol support from fixed-extent span","2020-02 (Prague)","|Complete|","11","`#104216 `__","" -"","","","","","" +"","","","","","","" "`P2231R1 `__","Missing constexpr in std::optional and std::variant","2021-06 (Virtual)","|Complete|","19","`#104217 `__","Changes of feature-test macros are completed in LLVM 20." "`P2325R3 `__","Views should not be required to be default constructible","2021-06 (Virtual)","|Complete|","16","`#104218 `__","" "`P2210R2 `__","Superior String Splitting","2021-06 (Virtual)","|Complete|","16","`#104219 `__","" @@ -199,7 +199,7 @@ "`P2281R1 `__","Clarifying range adaptor objects","2021-06 (Virtual)","|Complete|","14","`#104221 `__","" "`P2328R1 `__","join_view should join all views of ranges","2021-06 (Virtual)","|Complete|","15","`#104222 `__","" "`P2367R0 `__","Remove misuses of list-initialization from Clause 24","2021-06 (Virtual)","|Complete|","15","`#104223 `__","" -"","","","","","" +"","","","","","","" "`P2372R3 `__","Fixing locale handling in chrono formatters","2021-10 (Virtual)","|Complete|","21","`#100043 `__","" "`P2415R2 `__","What is a ``view``","2021-10 (Virtual)","|Complete|","14","`#104224 `__","" "`P2418R2 `__","Add support for ``std::generator``-like types to ``std::format``","2021-10 (Virtual)","|Complete|","15","`#104225 `__","" diff --git a/libcxx/docs/Status/Cxx23Issues.csv b/libcxx/docs/Status/Cxx23Issues.csv index 9318176ac964a..5a68b51ec85fb 100644 --- a/libcxx/docs/Status/Cxx23Issues.csv +++ b/libcxx/docs/Status/Cxx23Issues.csv @@ -1,4 +1,4 @@ -"Issue #","Issue Name","Meeting","Status","First released version","Notes" +"Issue #","Issue Name","Meeting","Status","First released version","GitHub issue","Notes" "`LWG2839 `__","Self-move-assignment of library types, again","2020-11 (Virtual)","|Nothing To Do|","","`#104255 `__","" "`LWG3117 `__","Missing ``packaged_task`` deduction guides","2020-11 (Virtual)","|Complete|","16","`#104256 `__","" "`LWG3143 `__","``monotonic_buffer_resource`` growth policy is unclear","2020-11 (Virtual)","","","`#104258 `__","" @@ -49,7 +49,7 @@ "`LWG3477 `__","Simplify constraints for ``semiregular-box``","2020-11 (Virtual)","|Complete|","13","`#104308 `__","" "`LWG3482 `__","``drop_view``'s const begin should additionally require ``sized_range``","2020-11 (Virtual)","|Complete|","14","`#104309 `__","" "`LWG3483 `__","``transform_view::iterator``'s difference is overconstrained","2020-11 (Virtual)","|Complete|","14","`#104310 `__","" -"","","","","","" +"","","","","","","" "`LWG3391 `__","Problems with ``counted_iterator``/``move_iterator::base() const &``","2021-02 (Virtual)","","","`#104311 `__","" "`LWG3433 `__","``subrange::advance(n)`` has UB when ``n < 0``","2021-02 (Virtual)","|Complete|","14","`#104312 `__","" "`LWG3490 `__","``ranges::drop_while_view::begin()`` is missing a precondition","2021-02 (Virtual)","|Nothing To Do|","","`#104313 `__","" @@ -59,7 +59,7 @@ "`LWG3500 `__","``join_view::iterator::operator->()`` is bogus","2021-02 (Virtual)","|Complete|","14","`#104318 `__","" "`LWG3502 `__","``elements_view`` should not be allowed to return dangling reference","2021-02 (Virtual)","|Complete|","16","`#104319 `__","" "`LWG3505 `__","``split_view::outer-iterator::operator++`` misspecified","2021-02 (Virtual)","","","`#104320 `__","" -"","","","","","" +"","","","","","","" "`LWG2774 `__","``std::function`` construction vs assignment","2021-06 (Virtual)","","","`#104321 `__","" "`LWG2818 `__","``::std::`` everywhere rule needs tweaking","2021-06 (Virtual)","|Nothing To Do|","","`#104322 `__","" "`LWG2997 `__","LWG 491 and the specification of ``{forward_,}list::unique``","2021-06 (Virtual)","","","`#104323 `__","" @@ -96,7 +96,7 @@ "`LWG3552 `__","Parallel specialized memory algorithms should require forward iterators","2021-06 (Virtual)","","","`#104357 `__","" "`LWG3553 `__","Useless constraint in ``split_view::outer-iterator::value_type::begin()``","2021-06 (Virtual)","","","`#104358 `__","" "`LWG3555 `__","``{transform,elements}_view::iterator::iterator_concept`` should consider const-qualification of the underlying range","2021-06 (Virtual)","","","`#104359 `__","" -"","","","","","" +"","","","","","","" "`LWG2191 `__","Incorrect specification of ``match_results(match_results&&)``","2021-10 (Virtual)","|Nothing To Do|","","`#104360 `__","" "`LWG2381 `__","Inconsistency in parsing floating point numbers","2021-10 (Virtual)","|Complete|","19","`#104361 `__","" "`LWG2762 `__","``unique_ptr operator*()`` should be ``noexcept``","2021-10 (Virtual)","|Complete|","19","`#104362 `__","" @@ -136,7 +136,7 @@ "`LWG3592 `__","``lazy_split_view`` needs to check the simpleness of Pattern","2021-10 (Virtual)","","","`#104938 `__","" "`LWG3593 `__","Several iterators' ``base() const &`` and ``lazy_split_view::outer-iterator::value_type::end()`` missing ``noexcept``","2021-10 (Virtual)","","","`#104939 `__","" "`LWG3595 `__","Exposition-only classes proxy and postfix-proxy for ``common_iterator`` should be fully ``constexpr``","2021-10 (Virtual)","|Complete|","14","`#104940 `__","" -"","","","","","" +"","","","","","","" "`LWG3088 `__","``forward_list::merge`` behaviour unclear when passed ``*this``","2022-02 (Virtual)","|Complete|","Yes","`#104942 `__","" "`LWG3471 `__","``polymorphic_allocator::allocate`` does not satisfy ``Cpp17Allocator`` requirements","2022-02 (Virtual)","","","`#104943 `__","" "`LWG3525 `__","``uses_allocator_construction_args`` fails to handle types convertible to ``pair``","2022-02 (Virtual)","","","`#104944 `__","" @@ -158,7 +158,7 @@ "`LWG3657 `__","``std::hash`` is not enabled","2022-02 (Virtual)","|Complete|","17","`#104960 `__","" "`LWG3660 `__","``iterator_traits::pointer`` should conform to §[iterator.traits]","2022-02 (Virtual)","|Complete|","14","`#104961 `__","" "`LWG3661 `__","``constinit atomic> a(nullptr);`` should work","2022-02 (Virtual)","","","`#104962 `__","" -"","","","","","" +"","","","","","","" "`LWG3564 `__","``transform_view::iterator::value_type`` and ``iterator_category`` should use ``const F&``","2022-07 (Virtual)","|Complete|","20","`#104963 `__","" "`LWG3617 `__","``function``/``packaged_task`` deduction guides and deducing ``this``","2022-07 (Virtual)","","","`#104965 `__","" "`LWG3656 `__","Inconsistent bit operations returning a count","2022-07 (Virtual)","|Complete|","15","`#104966 `__","" @@ -185,7 +185,7 @@ "`LWG3719 `__","Directory iterators should be usable with default sentinel","2022-07 (Virtual)","|Complete|","17","`#104992 `__","" "`LWG3721 `__","Allow an ``arg-id`` with a value of zero for ``width`` in ``std-format-spec``","2022-07 (Virtual)","|Complete|","16","`#104993 `__","" "`LWG3724 `__","``decay-copy`` should be constrained","2022-07 (Virtual)","|Complete|","14","`#104994 `__","" -"","","","","","" +"","","","","","","" "`LWG3028 `__","Container requirements tables should distinguish ``const`` and non-``const`` variables","2022-11 (Kona)","","","`#104995 `__","" "`LWG3118 `__","``fpos`` equality comparison unspecified","2022-11 (Kona)","","","`#104996 `__","" "`LWG3177 `__","Limit permission to specialize variable templates to program-defined types","2022-11 (Kona)","|Nothing To Do|","","`#104997 `__","" @@ -244,7 +244,7 @@ "`LWG3823 `__","Unnecessary precondition for ``is_aggregate``","2022-11 (Kona)","|Nothing To Do|","","`#105058 `__","" "`LWG3824 `__","Number of ``bind`` placeholders is underspecified","2022-11 (Kona)","|Nothing To Do|","","`#105060 `__","" "`LWG3826 `__","Redundant specification [for overload of yield_value]","2022-11 (Kona)","|Nothing To Do|","","`#105061 `__","" -"","","","","","" +"","","","","","","" "`LWG2195 `__","Missing constructors for ``match_results``","2023-02 (Issaquah)","","","`#105062 `__","" "`LWG2295 `__","Locale name when the provided ``Facet`` is a ``nullptr``","2023-02 (Issaquah)","","","`#105063 `__","" "`LWG3032 `__","``ValueSwappable`` requirement missing for ``push_heap`` and ``make_heap``","2023-02 (Issaquah)","","","`#105064 `__","" diff --git a/libcxx/docs/Status/Cxx23Papers.csv b/libcxx/docs/Status/Cxx23Papers.csv index 3a87e64339e1f..b655384bad7f2 100644 --- a/libcxx/docs/Status/Cxx23Papers.csv +++ b/libcxx/docs/Status/Cxx23Papers.csv @@ -1,16 +1,16 @@ -"Paper #","Paper Name","Meeting","Status","First released version","Notes" +"Paper #","Paper Name","Meeting","Status","First released version","GitHub issue","Notes" "`P0881R7 `__","A Proposal to add stacktrace library","2020-11 (Virtual)","","","`#105131 `__","" "`P0943R6 `__","Support C atomics in C++","2020-11 (Virtual)","|Complete|","15","`#105132 `__","" "`P1048R1 `__","A proposal for a type trait to detect scoped enumerations","2020-11 (Virtual)","|Complete|","12","`#105134 `__","" "`P1679R3 `__","string contains function","2020-11 (Virtual)","|Complete|","12","`#105135 `__","" -"","","","","","" +"","","","","","","" "`P1682R3 `__","std::to_underlying for enumerations","2021-02 (Virtual)","|Complete|","13","`#105136 `__","" "`P2017R1 `__","Conditionally borrowed ranges","2021-02 (Virtual)","|Complete|","16","`#105138 `__","" "`P2160R1 `__","Locks lock lockables","2021-02 (Virtual)","|Nothing To Do|","","`#105139 `__","" "`P2162R2 `__","Inheriting from std::variant","2021-02 (Virtual)","|Complete|","13","`#105140 `__","" "`P2212R2 `__","Relax Requirements for time_point::clock","2021-02 (Virtual)","|Nothing To Do|","","`#105141 `__","" "`P2259R1 `__","Repairing input range adaptors and counted_iterator","2021-02 (Virtual)","","","`#105142 `__","" -"","","","","","" +"","","","","","","" "`P0401R6 `__","Providing size feedback in the Allocator interface","2021-06 (Virtual)","|Complete|","15","`#105144 `__","" "`P0448R4 `__","A strstream replacement using span as buffer","2021-06 (Virtual)","","","`#105145 `__","" "`P1132R8 `__","out_ptr - a scalable output pointer abstraction","2021-06 (Virtual)","|Complete|","19","`#105146 `__","" @@ -22,7 +22,7 @@ "`P1989R2 `__","Range constructor for std::string_view","2021-06 (Virtual)","|Complete|","14","`#105154 `__","" "`P2136R3 `__","invoke_r","2021-06 (Virtual)","|Complete|","17","`#105155 `__","" "`P2166R1 `__","A Proposal to Prohibit std::basic_string and std::basic_string_view construction from nullptr","2021-06 (Virtual)","|Complete|","13","`#105156 `__","" -"","","","","","" +"","","","","","","" "`P0288R9 `__","``any_invocable``","2021-10 (Virtual)","","","`#105157 `__","" "`P0798R8 `__","Monadic operations for ``std::optional``","2021-10 (Virtual)","|Complete|","14","`#105158 `__","" "`P0849R8 `__","``auto(x)``: ``DECAY_COPY`` in the language","2021-10 (Virtual)","|Complete|","14","`#105159 `__","" @@ -37,7 +37,7 @@ "`P2340R1 `__","Clarifying the status of the 'C headers'","2021-10 (Virtual)","|Nothing To Do|","","`#105170 `__","" "`P2393R1 `__","Cleaning up ``integer``-class types","2021-10 (Virtual)","","","`#105171 `__","" "`P2401R0 `__","Add a conditional ``noexcept`` specification to ``std::exchange``","2021-10 (Virtual)","|Complete|","14","`#105172 `__","" -"","","","","","" +"","","","","","","" "`P0323R12 `__","``std::expected``","2022-02 (Virtual)","|Complete|","16","`#105173 `__","" "`P0533R9 `__","``constexpr`` for ```` and ````","2022-02 (Virtual)","|In Progress|","","`#105174 `__","``isfinite``, ``isinf``, ``isnan`` and ``isnormal`` are implemented" "`P0627R6 `__","Function to mark unreachable code","2022-02 (Virtual)","|Complete|","15","`#105175 `__","" @@ -50,7 +50,7 @@ "`P2441R2 `__","``views::join_with``","2022-02 (Virtual)","|Complete|","21","`#105185 `__","" "`P2442R1 `__","Windowing range adaptors: ``views::chunk`` and ``views::slide``","2022-02 (Virtual)","","","`#105187 `__","" "`P2443R1 `__","``views::chunk_by``","2022-02 (Virtual)","|Complete|","18","`#105188 `__","" -"","","","","","" +"","","","","","","" "`P0009R18 `__","mdspan: A Non-Owning Multidimensional Array Reference","2022-07 (Virtual)","|Complete|","18","`#105189 `__","" "`P0429R9 `__","A Standard ``flat_map``","2022-07 (Virtual)","|Complete|","20","`#105190 `__","" "`P1169R4 `__","``static operator()``","2022-07 (Virtual)","|Complete|","16","`#105192 `__","" @@ -91,7 +91,7 @@ "`P2599R2 `__","``mdspan::size_type`` should be ``index_type``","2022-07 (Virtual)","|Complete|","18","`#105235 `__","" "`P2604R0 `__","mdspan: rename pointer and contiguous","2022-07 (Virtual)","|Complete|","18","`#105236 `__","" "`P2613R1 `__","Add the missing ``empty`` to ``mdspan``","2022-07 (Virtual)","|Complete|","18","`#105237 `__","" -"","","","","","" +"","","","","","","" "`P1202R5 `__","Asymmetric Fences","2022-11 (Kona)","","","`#105238 `__","" "`P1264R2 `__","Revising the wording of ``stream`` input operations","2022-11 (Kona)","|Complete|","9","`#105239 `__","" "`P1478R8 `__","``Byte-wise`` ``atomic`` ``memcpy``","2022-11 (Kona)","","","`#105240 `__","" @@ -101,7 +101,7 @@ "`P2539R4 `__","Should the output of ``std::print`` to a terminal be synchronized with the underlying stream?","2022-11 (Kona)","|Complete|","18","`#105245 `__","" "`P2602R2 `__","Poison Pills are Too Toxic","2022-11 (Kona)","|Complete|","19","`#105246 `__","Implemented as a DR in C++20." "`P2708R1 `__","No Further Fundamentals TSes","2022-11 (Kona)","|Nothing To Do|","","`#105247 `__","" -"","","","","","" +"","","","","","","" "`P0290R4 `__","``apply()`` for ``synchronized_value``","2023-02 (Issaquah)","","","`#105249 `__","" "`P2770R0 `__","Stashing stashing ``iterators`` for proper flattening","2023-02 (Issaquah)","|Complete|","21","`#105250 `__","" "`P2164R9 `__","``views::enumerate``","2023-02 (Issaquah)","","","`#105251 `__","" diff --git a/libcxx/docs/Status/Cxx2cIssues.csv b/libcxx/docs/Status/Cxx2cIssues.csv index 237217a31b9ea..859c49af17ec9 100644 --- a/libcxx/docs/Status/Cxx2cIssues.csv +++ b/libcxx/docs/Status/Cxx2cIssues.csv @@ -1,4 +1,4 @@ -"Issue #","Issue Name","Meeting","Status","First released version","Notes" +"Issue #","Issue Name","Meeting","Status","First released version","GitHub issue","Notes" "`LWG2994 `__","Needless UB for ``basic_string`` and ``basic_string_view``","2023-06 (Varna)","|Complete|","5","`#105268 `__","" "`LWG3884 `__","``flat_foo`` is missing allocator-extended copy/move constructors","2023-06 (Varna)","","","`#105269 `__","" "`LWG3885 `__","``op`` should be in [zombie.names]","2023-06 (Varna)","|Nothing To Do|","","`#105270 `__","" @@ -16,7 +16,7 @@ "`LWG3935 `__","``template constexpr complex& operator=(const complex&)`` has no specification","2023-06 (Varna)","|Complete|","3.4","`#105284 `__","" "`LWG3938 `__","Cannot use ``std::expected`` monadic ops with move-only ``error_type``","2023-06 (Varna)","|Complete|","18","`#105285 `__","" "`LWG3940 `__","``std::expected::value()`` also needs ``E`` to be copy constructible","2023-06 (Varna)","|Complete|","18","`#105286 `__","" -"","","","","","" +"","","","","","","" "`LWG2392 `__","""character type"" is used but not defined","2023-11 (Kona)","","","`#105287 `__","" "`LWG3203 `__","``span`` element access invalidation","2023-11 (Kona)","|Nothing To Do|","","`#105288 `__","" "`LWG3305 `__","``any_cast``","2023-11 (Kona)","|Complete|","18","`#105289 `__","" @@ -39,7 +39,7 @@ "`LWG3987 `__","Including `` doesn't provide `std::begin`/`end`","2023-11 (Kona)","|Complete|","","`#105309 `__","" "`LWG3990 `__","Program-defined specializations of ``std::tuple`` and ``std::variant`` can't be properly supported","2023-11 (Kona)","|Complete|","21","`#105310 `__","" "`LWG4001 `__","``iota_view`` should provide ``empty``","2023-11 (Kona)","|Complete|","19","`#105311 `__","" -"","","","","","" +"","","","","","","" "`LWG3767 `__","``codecvt`` incorrectly added to locale","2024-03 (Tokyo)","","","`#105313 `__","" "`LWG3919 `__","``enumerate_view`` may invoke UB for sized common non-forward underlying ranges","2024-03 (Tokyo)","","","`#105315 `__","" "`LWG3950 `__","``std::basic_string_view`` comparison operators are overspecified","2024-03 (Tokyo)","|Complete|","18","`#105316 `__","" @@ -61,7 +61,7 @@ "`LWG4045 `__","``tuple`` can create dangling references from ``tuple-like``","2024-03 (Tokyo)","","","`#105337 `__","" "`LWG4053 `__","Unary call to ``std::views::repeat`` does not decay the argument","2024-03 (Tokyo)","|Complete|","19","`#105338 `__","" "`LWG4054 `__","Repeating a ``repeat_view`` should repeat the view","2024-03 (Tokyo)","|Complete|","19","`#105340 `__","" -"","","","","","" +"","","","","","","" "`LWG3944 `__","Formatters converting sequences of ``char`` to sequences of ``wchar_t``","2024-06 (St. Louis)","|Complete|","21","`#105342 `__","" "`LWG4060 `__","``submdspan`` preconditions do not forbid creating invalid pointer","2024-06 (St. Louis)","","","`#105343 `__","" "`LWG4061 `__","Should ``std::basic_format_context`` be default-constructible/copyable/movable?","2024-06 (St. Louis)","|Complete|","19","`#105344 `__","" @@ -75,7 +75,7 @@ "`LWG4098 `__","``views::adjacent<0>`` should reject non-forward ranges","2024-06 (St. Louis)","","","`#105353 `__","" "`LWG4105 `__","``ranges::ends_with``\`s Returns misses difference casting","2024-06 (St. Louis)","","","`#105354 `__","" "`LWG4106 `__","``basic_format_args`` should not be default-constructible","2024-06 (St. Louis)","|Complete|","19","`#105355 `__","" -"","","","","","" +"","","","","","","" "`LWG3216 `__","Rebinding the allocator before calling ``construct``/``destroy`` in ``allocate_shared``","2024-11 (Wrocław)","","","`#118332 `__","" "`LWG3436 `__","``std::construct_at`` should support arrays","2024-11 (Wrocław)","","","`#118335 `__","" "`LWG3886 `__","Monad mo' problems","2024-11 (Wrocław)","|Complete|","22","`#118336 `__","" @@ -110,7 +110,7 @@ "`LWG4164 `__","Missing guarantees for ``forward_list`` modifiers","2024-11 (Wrocław)","|Complete|","21","`#118366 `__","" "`LWG4169 `__","``std::atomic``'s default constructor should be constrained","2024-11 (Wrocław)","","","`#118367 `__","" "`LWG4170 `__","``contiguous_iterator`` should require ``to_address(I{})``","2024-11 (Wrocław)","","","`#118368 `__","" -"","","","","","" +"","","","","","","" "`LWG3578 `__","Iterator SCARYness in the context of associative container merging","2025-02 (Hagenberg)","","","`#127859 `__","" "`LWG3956 `__","``chrono::parse`` uses ``from_stream`` as a customization point","2025-02 (Hagenberg)","","","`#127860 `__","" "`LWG4172 `__","``unique_lock`` self-move-assignment is broken","2025-02 (Hagenberg)","","","`#127861 `__","" @@ -120,7 +120,7 @@ "`LWG4189 `__","``cache_latest_view`` should be freestanding","2025-02 (Hagenberg)","","","`#127865 `__","" "`LWG4191 `__","P1467 changed the return type of ``pow(complex, int)``","2025-02 (Hagenberg)","","","`#127866 `__","" "`LWG4196 `__","Complexity of ``inplace_merge()`` is incorrect","2025-02 (Hagenberg)","","","`#127867 `__","" -"","","","","","" +"","","","","","","" "`LWG4198 `__","``schedule_from`` isn't starting the schedule sender if decay-copying results throws","2025-06 (Sofia)","","","`#148188 `__","" "`LWG4202 `__","``enable-sender`` should be a variable template","2025-06 (Sofia)","","","`#148189 `__","" "`LWG4203 `__","Constraints on ``get-state`` functions are incorrect","2025-06 (Sofia)","","","`#148190 `__","" @@ -145,9 +145,9 @@ "`LWG4242 `__","``ranges::distance`` does not work with volatile iterators","2025-06 (Sofia)","","","`#148224 `__","" "`LWG4245 `__","Operators that interact with ``counted_iterator`` and ``default_sentinel_t`` should be ``noexcept``","2025-06 (Sofia)","","","`#148226 `__","" "`LWG4247 `__","Header ```` is not yet freestanding","2025-06 (Sofia)","","","`#148227 `__","" -"","","","","","" +"","","","","","","" "`LWG3343 `__","Ordering of calls to ``unlock()`` and ``notify_all()`` in Effects element of ``notify_all_at_thread_exit()`` should be reversed","Not Adopted Yet","|Complete|","16","`#105356 `__","" "`LWG4139 `__","§[time.zone.leap] recursive constraint in ``<=>``","Not Adopted Yet","|Complete|","20","`#118369 `__","" "`LWG3456 `__","Pattern used by ``std::from_chars`` is underspecified (option B)","Not Adopted Yet","|Complete|","20","`#118370 `__","" "`LWG3882 `__","``tuple`` relational operators have confused friendships","Not Adopted Yet","|Complete|","22","The comparsion operators are constrained harder than the proposed resolution. libstdc++ and MSVC STL do the same.","" -"","","","","","" +"","","","","","","" diff --git a/libcxx/docs/Status/Cxx2cPapers.csv b/libcxx/docs/Status/Cxx2cPapers.csv index 0eedc82e3dbf5..a5423acf0d419 100644 --- a/libcxx/docs/Status/Cxx2cPapers.csv +++ b/libcxx/docs/Status/Cxx2cPapers.csv @@ -1,4 +1,4 @@ -"Paper #","Paper Name","Meeting","Status","First released version","Notes" +"Paper #","Paper Name","Meeting","Status","First released version","GitHub issue","Notes" "`P2497R0 `__","Testing for success or failure of ```` functions","2023-06 (Varna)","|Complete|","18","`#105357 `__","" "`P2592R3 `__","Hashing support for ``std::chrono`` value classes","2023-06 (Varna)","","","`#105358 `__","" "`P2587R3 `__","``to_string`` or not ``to_string``","2023-06 (Varna)","","","`#105359 `__","" @@ -26,7 +26,7 @@ "`P2548R6 `__","``copyable_function``","2023-06 (Varna)","","","`#105387 `__","" "`P2714R1 `__","Bind front and back to NTTP callables","2023-06 (Varna)","|Partial|","20","`#105388 `__","" "`P2630R4 `__","``submdspan``","2023-06 (Varna)","","","`#105389 `__","" -"","","","","","" +"","","","","","","" "`P0543R3 `__","Saturation arithmetic","2023-11 (Kona)","|Complete|","18","`#105390 `__","" "`P2407R5 `__","Freestanding Library: Partial Classes","2023-11 (Kona)","","","`#105391 `__","" "`P2546R5 `__","Debugging Support","2023-11 (Kona)","","","`#105392 `__","" @@ -45,7 +45,7 @@ "`P2836R1 `__","``std::basic_const_iterator`` should follow its underlying type's convertibility","2023-11 (Kona)","","","`#105406 `__","" "`P2264R7 `__","Make ``assert()`` macro user friendly for C and C++","2023-11 (Kona)","","","`#105407 `__","" "`P1673R13 `__","A free function linear algebra interface based on the BLAS","2023-11 (Kona)","","","`#105408 `__","" -"","","","","","" +"","","","","","","" "`P2875R4 `__","Undeprecate ``polymorphic_allocator::destroy`` for C++26","2024-03 (Tokyo)","|Complete|","15","`#105410 `__","" "`P2867R2 `__","Remove Deprecated ``strstreams`` From C++26","2024-03 (Tokyo)","|Complete|","19","`#105411 `__","" "`P2869R4 `__","Remove Deprecated ``shared_ptr`` Atomic Access APIs from C++26","2024-03 (Tokyo)","","","`#105412 `__","" @@ -62,7 +62,7 @@ "`P2944R3 `__","Comparisons for ``reference_wrapper``","2024-03 (Tokyo)","|Complete|","22","`#105424 `__","The changes to ``tuple``'s equality overload from P2165R4 are not yet implemented." "`P2642R6 `__","Padded ``mdspan`` layouts","2024-03 (Tokyo)","","","`#105425 `__","" "`P3029R1 `__","Better ``mdspan``'s CTAD","2024-03 (Tokyo)","|Complete|","19","`#105426 `__","" -"","","","","","" +"","","","","","","" "`P2747R2 `__","``constexpr`` placement new","2024-06 (St. Louis)","|Complete|","20","`#105427 `__","" "`P2997R1 `__","Removing the common reference requirement from the indirectly invocable concepts","2024-06 (St. Louis)","|Complete|","19","`#105428 `__","Implemented as a DR against C++20. (MSVC STL and libstdc++ will do the same.)" "`P2389R2 `__","``dextents`` Index Type Parameter","2024-06 (St. Louis)","|Complete|","19","`#105429 `__","" @@ -75,7 +75,7 @@ "`P2075R6 `__","Philox as an extension of the C++ RNG engines","2024-06 (St. Louis)","","","`#105437 `__","" "`P2422R1 `__","Remove ``nodiscard`` annotations from the standard library specification","2024-06 (St. Louis)","|Complete|","19","`#105438 `__","``nodiscard`` attributes were kept as a conforming extension" "`P2300R10 `__","``std::execution``","2024-06 (St. Louis)","","","`#105440 `__","" -"","","","","","" +"","","","","","","" "`P3136R1 `__","Retiring niebloids","2024-11 (Wrocław)","|Complete|","14","`#118133 `__","" "`P3138R5 `__","``views::cache_latest``","2024-11 (Wrocław)","","","`#118134 `__","" "`P3379R0 `__","Constrain ``std::expected`` equality operators","2024-11 (Wrocław)","|Complete|","21","`#118135 `__","" @@ -95,7 +95,7 @@ "`P3325R5 `__","A Utility for Creating Execution Environments","2024-11 (Wrocław)","","","`#118385 `__","" "`P3068R6 `__","Allowing exception throwing in constant-evaluation","2024-11 (Wrocław)","","","`#118386 `__","" "`P3247R2 `__","Deprecate the notion of trivial types","2024-11 (Wrocław)","|Complete|","21","`#118387 `__","" -"","","","","","" +"","","","","","","" "`P3074R7 `__","trivial unions (was ``std::uninitialized``)","2025-02 (Hagenberg)","","","`#127868 `__","" "`P1494R5 `__","Partial program correctness","2025-02 (Hagenberg)","","","`#127869 `__","" "`P2900R14 `__","Contracts for C++","2025-02 (Hagenberg)","","","`#127870 `__","" @@ -116,7 +116,7 @@ "`P3471R4 `__","Standard Library Hardening","2025-02 (Hagenberg)","","","`#127885 `__","" "`P0447R28 `__","Introduction of ``std::hive`` to the standard library","2025-02 (Hagenberg)","","","`#127886 `__","" "`P3019R14 `__","``indirect`` and ``polymorphic``: Vocabulary Types for Composite Class Design","2025-02 (Hagenberg)","","","`#127887 `__","" -"","","","","","" +"","","","","","","" "`P2996R13 `__","Reflection for C++26","2025-06 (Sofia)","","","`#148123 `__","" "`P3394R4 `__","Annotations for Reflection","2025-06 (Sofia)","","","`#148124 `__","" "`P3293R3 `__","Splicing a base class subobject","2025-06 (Sofia)","","","`#148125 `__","" @@ -156,4 +156,4 @@ "`P3697R1 `__","Minor additions to C++26 standard library hardening","2025-06 (Sofia)","","","`#148180 `__","" "`P3552R3 `__","Add a Coroutine Task Type","2025-06 (Sofia)","","","`#148182 `__","" "`P1317R2 `__","Remove return type deduction in ``std::apply``","2025-06 (Sofia)","","","`#148183 `__","" -"","","","","","" +"","","","","","","" From 9a5ae34eb6e90c51e2231ceb1a8cf933341f3222 Mon Sep 17 00:00:00 2001 From: Luke Hutton Date: Thu, 23 Oct 2025 15:35:18 +0100 Subject: [PATCH 05/31] [mlir][tosa] Add support for matmul_t_block_scaled (#163433) This commit adds support for the MATMUL_T_BLOCK_SCALED operation from the EXT_MXFP extension. This includes: - Operation definition in TosaOps.td - Micro-scaling supported types definition - Shape inference and verifiers - Validation pass checks to ensure usage is only valid when the target environment includes ext-mxfp and at least v1.1.draft of the specification. As part of this commit, a notion of EXT_MXFP is also added. The extension can be specified as part of the target environment and can only be used if the specification version is at least 1.1. Note: currently it excludes support for mxint8. This will be added in a later commit. Note: this commit adds support as defined in the spec in https://github.com/arm/tosa-specification/commit/063846a75b9687ab01e58cb3538472bffb3a03b0. EXT_MXFP extension is considered experimental and subject to breaking change. Co-authored-by: Tat Wai Chong --- mlir/include/mlir/Dialect/Tosa/IR/TargetEnv.h | 37 ++- .../Dialect/Tosa/IR/TosaComplianceData.h.inc | 12 + .../mlir/Dialect/Tosa/IR/TosaOpBase.td | 19 +- mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td | 34 +++ .../Dialect/Tosa/IR/TosaProfileCompliance.h | 1 + .../mlir/Dialect/Tosa/IR/TosaTypesBase.td | 13 ++ mlir/lib/Dialect/Tosa/IR/TargetEnv.cpp | 94 +++++++- mlir/lib/Dialect/Tosa/IR/TosaOps.cpp | 218 ++++++++++++++++-- .../Tosa/Transforms/TosaProfileCompliance.cpp | 15 ++ .../Tosa/Transforms/TosaValidation.cpp | 19 +- mlir/test/Dialect/Tosa/invalid_extension.mlir | 8 + mlir/test/Dialect/Tosa/level_check.mlir | 9 + mlir/test/Dialect/Tosa/ops.mlir | 42 ++++ .../Tosa/profile_pro_fp_unsupported.mlir | 9 +- mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir | 54 +++++ .../tosa-validation-version-1p1-valid.mlir | 10 +- mlir/test/Dialect/Tosa/verifier.mlir | 48 ++++ 17 files changed, 597 insertions(+), 45 deletions(-) diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TargetEnv.h b/mlir/include/mlir/Dialect/Tosa/IR/TargetEnv.h index 4ecf03c34c1a5..e088eb31338dc 100644 --- a/mlir/include/mlir/Dialect/Tosa/IR/TargetEnv.h +++ b/mlir/include/mlir/Dialect/Tosa/IR/TargetEnv.h @@ -54,6 +54,8 @@ TargetEnvAttr lookupTargetEnvOrDefault(Operation *op); /// and provide utilities around the TOSA specification version. class TosaSpecificationVersion { public: + TosaSpecificationVersion() = default; + TosaSpecificationVersion(uint32_t major, uint32_t minor) : majorVersion(major), minorVersion(minor) {} TosaSpecificationVersion(SpecificationVersion version) @@ -83,6 +85,10 @@ class TosaSpecificationVersion { } }; +TosaSpecificationVersion getMinVersion(const Profile &profile); +TosaSpecificationVersion getMinVersion(const Extension &extension); +TosaSpecificationVersion getMinVersion(const Level &level); + llvm::SmallString<4> stringifyVersion(TosaSpecificationVersion version); /// This class represents the capability enabled in the target implementation @@ -91,22 +97,19 @@ llvm::SmallString<4> stringifyVersion(TosaSpecificationVersion version); class TargetEnv { public: TargetEnv() {} - explicit TargetEnv(SpecificationVersion specificationVersion, Level level, - const ArrayRef &profiles, - const ArrayRef &extensions) - : specificationVersion(specificationVersion), level(level) { - enabledProfiles.insert_range(profiles); - enabledExtensions.insert_range(extensions); - } - explicit TargetEnv(TargetEnvAttr targetAttr) - : TargetEnv(targetAttr.getSpecificationVersion(), targetAttr.getLevel(), - targetAttr.getProfiles(), targetAttr.getExtensions()) {} + static FailureOr + createTargetEnvFromAttr(TargetEnvAttr targetAttr, Location targetEnvAttrLoc); + + static LogicalResult verifyTargetInformation(TargetEnvAttr targetAttr, + Location targetAttrLoc); void addProfile(Profile p) { enabledProfiles.insert(p); } void addExtension(Extension e) { enabledExtensions.insert(e); } - SpecificationVersion getSpecVersion() const { return specificationVersion; } + TosaSpecificationVersion getSpecVersion() const { + return specificationVersion; + } TosaLevel getLevel() const { if (level == Level::eightK) @@ -140,7 +143,17 @@ class TargetEnv { } private: - SpecificationVersion specificationVersion; + // Require target information is verified before constructing, via the use of + // `createTargetEnvFromAttr`. + explicit TargetEnv(SpecificationVersion specificationVersion, Level level, + const ArrayRef &profiles, + const ArrayRef &extensions) + : specificationVersion(specificationVersion), level(level) { + enabledProfiles.insert_range(profiles); + enabledExtensions.insert_range(extensions); + } + + TosaSpecificationVersion specificationVersion; Level level; llvm::SmallSet enabledProfiles; llvm::SmallSet enabledExtensions; diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc b/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc index c1b5e785bd739..294fb9d99fdb6 100644 --- a/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc +++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc @@ -554,6 +554,18 @@ extensionComplianceMap = { allOf}, {{Extension::bf16}, {{{bf16T, bf16T, bf16T, bf16T, fp32T}, SpecificationVersion::V_1_0}}}}}, + {"tosa.matmul_t_block_scaled", + {{{Extension::mxfp}, + {{{fp4e2m1T, fp8ue8m0T, fp4e2m1T, fp8ue8m0T, fp32T}, + SpecificationVersion::V_1_1_DRAFT}, + {{fp6e2m3T, fp8ue8m0T, fp6e2m3T, fp8ue8m0T, fp32T}, + SpecificationVersion::V_1_1_DRAFT}, + {{fp6e3m2T, fp8ue8m0T, fp6e3m2T, fp8ue8m0T, fp32T}, + SpecificationVersion::V_1_1_DRAFT}, + {{fp8e4m3T, fp8ue8m0T, fp8e4m3T, fp8ue8m0T, fp32T}, + SpecificationVersion::V_1_1_DRAFT}, + {{fp8e5m2T, fp8ue8m0T, fp8e5m2T, fp8ue8m0T, fp32T}, + SpecificationVersion::V_1_1_DRAFT}}}}}, {"tosa.max_pool2d", {{{Extension::int16}, {{{i16T, i16T}, SpecificationVersion::V_1_0}}}, {{Extension::fp8e4m3}, diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td b/mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td index 8376a4c87dbf2..48e0073c76ab6 100644 --- a/mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td +++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaOpBase.td @@ -270,13 +270,14 @@ def Tosa_EXT_CONTROLFLOW : I32EnumAttrCase<"controlflow", 8>; def Tosa_EXT_DOUBLEROUND : I32EnumAttrCase<"doubleround", 9>; def Tosa_EXT_INEXACTROUND : I32EnumAttrCase<"inexactround", 10>; def Tosa_EXT_DYNAMIC : I32EnumAttrCase<"dynamic", 11>; +def Tosa_EXT_MXFP : I32EnumAttrCase<"mxfp", 12>; def Tosa_ExtensionAttr : Tosa_I32EnumAttr<"Extension", "supported TOSA extensions", "ext", [ Tosa_EXT_NONE, Tosa_EXT_INT16, Tosa_EXT_INT4, Tosa_EXT_BF16, Tosa_EXT_FP8E4M3, Tosa_EXT_FP8E5M2, Tosa_EXT_FFT, Tosa_EXT_VARIABLE, Tosa_EXT_CONTROLFLOW, Tosa_EXT_DOUBLEROUND, Tosa_EXT_INEXACTROUND, - Tosa_EXT_DYNAMIC + Tosa_EXT_DYNAMIC, Tosa_EXT_MXFP ]> { let extraClassDeclaration = [{ static llvm::SmallVector getAllValues() { @@ -284,7 +285,7 @@ def Tosa_ExtensionAttr Extension::int16, Extension::int4, Extension::bf16, Extension::fp8e4m3, Extension::fp8e5m2, Extension::fft, Extension::variable, Extension::controlflow, Extension::doubleround, - Extension::inexactround, Extension::dynamic + Extension::inexactround, Extension::dynamic, Extension::mxfp }; } }]; @@ -437,7 +438,7 @@ def Tosa_TargetEnv : Tosa_Attr<"TargetEnv", "target_env"> { } //===----------------------------------------------------------------------===// -// Iterable attributes. +// Enum attributes. //===----------------------------------------------------------------------===// // Defined in `section 3. Enumerations` of the TOSA specification. @@ -463,6 +464,18 @@ def Tosa_RoundingModeAttr : Tosa_I32EnumAttr<"RoundingMode", "Supported rounding modes", "rounding_mode", [Tosa_ROUNDING_SINGLE_ROUND, Tosa_ROUNDING_INEXACT_ROUND, Tosa_ROUNDING_DOUBLE_ROUND]>; +def Tosa_BLOCK_SIZE_32 : I32EnumAttrCase<"BLOCK_SIZE_32", 32>; + +def Tosa_BlockSizeAttr + : Tosa_I32EnumAttr<"BlockSize", "Block size for the block_scaled formats", "block_size", + [Tosa_BLOCK_SIZE_32]> { + let extraClassDeclaration = [{ + static uint32_t getBlockSizeValue(BlockSize blockSize) { + return static_cast(blockSize); + } + }]; +} + //===----------------------------------------------------------------------===// // TOSA Interfaces. diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td b/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td index 137554f49460d..6f07247b478c8 100644 --- a/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td +++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaOps.td @@ -347,6 +347,40 @@ def Tosa_MatMulOp : Tosa_InferShapedTypeOp<"matmul"> { "operands attr-dict `:` functional-type(operands, results)"; } +//===----------------------------------------------------------------------===// +// Operator: matmul_t_block_scaled +//===----------------------------------------------------------------------===// +def Tosa_MatmulTBlockScaledOp : Tosa_InferShapedTypeOp<"matmul_t_block_scaled"> { + let summary = "Performs two dimensional matrix multiplications using block scaled tensors."; + + let description = [{ + Performs two dimensional matrix multiplications using block scaled tensors. The block + dimension is always the the last dimension of the tensor, so the result is effectively + a matrix multiply of A by the transposed B matrix. If the N dimension of input B is of + size 1, the B matrix will be broadcast. + }]; + + let arguments = (ins + Tosa_MXFPDataTensor3D:$a_data, + Tosa_MXFPScaleTensor3D:$a_scale, + Tosa_MXFPDataTensor3D:$b_data, + Tosa_MXFPScaleTensor3D:$b_scale, + Tosa_BlockSizeAttr:$block_size + ); + + let results = (outs + Tosa_Tensor3D:$output_data + ); + + let hasVerifier = 1; + let hasCustomAssemblyFormat = 1; + + list availability = [ + Profile<[Tosa_PRO_FP]>, + Extension<[Tosa_EXT_MXFP]> + ]; +} + //===----------------------------------------------------------------------===// // Operator: max_pool2d //===----------------------------------------------------------------------===// diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h b/mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h index 7b946ad6c6a89..79df1b888b40e 100644 --- a/mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h +++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaProfileCompliance.h @@ -147,6 +147,7 @@ class TosaProfileCompliance { case Extension::fp8e4m3: case Extension::fp8e5m2: case Extension::fft: + case Extension::mxfp: return {Profile::pro_fp}; case Extension::variable: case Extension::controlflow: diff --git a/mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td b/mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td index 93ab120339d55..20bb961482ad8 100644 --- a/mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td +++ b/mlir/include/mlir/Dialect/Tosa/IR/TosaTypesBase.td @@ -84,6 +84,10 @@ def Tosa_QuantizedInt : AnyTypeOf<[Tosa_QuantizedType<"uint8", [8], 0>, def Tosa_AnyNumber : AnyTypeOf<[Tosa_Int, Tosa_QuantizedInt, AnyFloat], "number">; +def Tosa_MXFPNumber : AnyTypeOf<[F8E4M3FN, F8E5M2, F4E2M1FN, F6E2M3FN, F6E3M2FN], + "micro-scaling format number">; +def Tosa_MXFPScaleNumber : AnyTypeOf<[F8E8M0FNU], "micro-scaling format scale number">; + //===----------------------------------------------------------------------===// // TOSA Tensor Conformance //===----------------------------------------------------------------------===// @@ -187,6 +191,15 @@ def Tosa_Int32Tensor2D : AnyTypeOf<[ def Tosa_TensorAtLeast1D : AnyTypeOf<[ Tosa_UnrankedTensor, TosaRankedTensorOf<[Tosa_AnyNumber], [AtLeastRankOne]>], "tosa-conformant tensor of at least rank 1", "::mlir::TensorType">; +def Tosa_MXFPDataTensor3D : AnyTypeOf<[ + TosaUnrankedTensorOf<[Tosa_MXFPNumber]>, + TosaTensorRankOf<[Tosa_MXFPNumber], [3]> +]>; +def Tosa_MXFPScaleTensor3D : AnyTypeOf<[ + TosaUnrankedTensorOf<[Tosa_MXFPScaleNumber]>, + TosaTensorRankOf<[Tosa_MXFPScaleNumber], [3]> +]>; + //===----------------------------------------------------------------------===// // Generic scalar, vector, or tensor of a particular type. //===----------------------------------------------------------------------===// diff --git a/mlir/lib/Dialect/Tosa/IR/TargetEnv.cpp b/mlir/lib/Dialect/Tosa/IR/TargetEnv.cpp index 1cba1bb540c02..32eb286531d28 100644 --- a/mlir/lib/Dialect/Tosa/IR/TargetEnv.cpp +++ b/mlir/lib/Dialect/Tosa/IR/TargetEnv.cpp @@ -12,6 +12,96 @@ namespace mlir { namespace tosa { +llvm::SmallString<4> stringifyVersion(TosaSpecificationVersion version) { + return llvm::formatv("{0}.{1}", version.getMajor(), version.getMinor()); +} + +TosaSpecificationVersion getMinVersion(const Profile &profile) { + switch (profile) { + case Profile::pro_int: + case Profile::pro_fp: + return TosaSpecificationVersion(1, 0); + case Profile::none: + return TosaSpecificationVersion(0, 0); + } + llvm_unreachable("Unknown TOSA profile"); +} + +TosaSpecificationVersion getMinVersion(const Extension &extension) { + switch (extension) { + case Extension::int16: + case Extension::int4: + case Extension::bf16: + case Extension::fp8e4m3: + case Extension::fp8e5m2: + case Extension::fft: + case Extension::variable: + case Extension::controlflow: + case Extension::doubleround: + case Extension::inexactround: + case Extension::dynamic: + return TosaSpecificationVersion(1, 0); + case Extension::mxfp: + return TosaSpecificationVersion(1, 1); + case Extension::none: + return TosaSpecificationVersion(0, 0); + } + llvm_unreachable("Unknown TOSA extension"); +} + +TosaSpecificationVersion getMinVersion(const Level &level) { + switch (level) { + case Level::eightK: + case Level::none: + return TosaSpecificationVersion(1, 0); + } + llvm_unreachable("Unknown TOSA level"); +} + +FailureOr +TargetEnv::createTargetEnvFromAttr(TargetEnvAttr targetAttr, + Location targetEnvAttrLoc) { + if (failed(verifyTargetInformation(targetAttr, targetEnvAttrLoc))) + return failure(); + + return TargetEnv(targetAttr.getSpecificationVersion(), targetAttr.getLevel(), + targetAttr.getProfiles(), targetAttr.getExtensions()); +} + +LogicalResult TargetEnv::verifyTargetInformation(TargetEnvAttr targetAttr, + Location targetAttrLoc) { + TosaSpecificationVersion targetVersion(targetAttr.getSpecificationVersion()); + + const auto isCompatibleWithTargetVersion = + [&](const auto &targetEnum, Location targetAttrLoc, + StringRef enumName) -> LogicalResult { + const TosaSpecificationVersion minRequiredVersion = + getMinVersion(targetEnum); + if (!targetVersion.isBackwardsCompatibleWith(minRequiredVersion)) + return emitError(targetAttrLoc, enumName) + << " '" << stringifyEnum(targetEnum) + << "' is not compatible with the target version " + << stringifyVersion(targetVersion) + << ", minimum required version is " + << stringifyVersion(minRequiredVersion); + return success(); + }; + + for (const auto &profile : targetAttr.getProfiles()) + if (failed( + isCompatibleWithTargetVersion(profile, targetAttrLoc, "profile"))) + return failure(); + for (const auto &extension : targetAttr.getExtensions()) + if (failed(isCompatibleWithTargetVersion(extension, targetAttrLoc, + "extension"))) + return failure(); + if (failed(isCompatibleWithTargetVersion(targetAttr.getLevel(), targetAttrLoc, + "level"))) + return failure(); + + return success(); +} + TargetEnvAttr lookupTargetEnv(Operation *op) { while (op) { op = SymbolTable::getNearestSymbolTable(op); @@ -39,9 +129,5 @@ TargetEnvAttr lookupTargetEnvOrDefault(Operation *op) { return getDefaultTargetEnv(op->getContext()); } -llvm::SmallString<4> stringifyVersion(TosaSpecificationVersion version) { - return llvm::formatv("{0}.{1}", version.getMajor(), version.getMinor()); -} - } // namespace tosa } // namespace mlir diff --git a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp index 00f84bc43f444..6cd0eaea3ce6c 100644 --- a/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp +++ b/mlir/lib/Dialect/Tosa/IR/TosaOps.cpp @@ -321,6 +321,19 @@ ParseResult parseAttrEntryWithEnumHandling(OpAsmParser &parser, } } + // special handling: block_size accepts a *bare* BlockSizeMode enum + if constexpr (std::is_same_v) { + if (name == "block_size" && succeeded(parser.parseOptionalKeyword(&kw))) { + auto sym = symbolizeBlockSize(kw); + if (!sym) + return parser.emitError(parser.getCurrentLocation()) + << "invalid block_size value: " << kw; + auto attr = BlockSizeAttr::get(parser.getContext(), sym.value()); + outAttrs.push_back(NamedAttribute(name, attr)); + return success(); + } + } + // Default path: parse any normal attribute literal, including fully qualified // enum keyword Attribute attr; @@ -373,6 +386,8 @@ void printNamedAttr(OpAsmPrinter &parser, const NamedAttribute namedAttr) { } else if (auto nanPropagationModeAttr = dyn_cast(attr)) { parser << nanPropagationModeAttr.getValue(); + } else if (auto blockSizeAttr = dyn_cast(attr)) { + parser << blockSizeAttr.getValue(); } else { parser.printAttribute(attr); } @@ -508,6 +523,15 @@ void ReduceMinOp::print(OpAsmPrinter &parser) { printWithNanPropagationHandling(parser, *this); } +ParseResult MatmulTBlockScaledOp::parse(OpAsmParser &parser, + OperationState &result) { + return parseWithEnumHandling(parser, result); +} + +void MatmulTBlockScaledOp::print(OpAsmPrinter &parser) { + printWithEnumHandling(parser, *this); +} + //===----------------------------------------------------------------------===// // Tosa utilities. //===----------------------------------------------------------------------===// @@ -933,32 +957,35 @@ static LogicalResult verifyVariableOpErrorIf(T op, Type type, StringRef name) { // verify that inType and outType have same element types template -static LogicalResult verifySameElementTypes(T op, Type inType, Type outType) { - auto inputType = llvm::dyn_cast(inType); - auto outputType = llvm::dyn_cast(outType); - if (!inputType) { - op.emitOpError("expect shaped tensor for input, got ") << inType; +static LogicalResult verifySameElementTypes(T op, Type aType, Type bType, + StringRef aName = "input", + StringRef bName = "output") { + auto aTType = llvm::dyn_cast(aType); + auto bTType = llvm::dyn_cast(bType); + if (!aTType) { + op.emitOpError("expect shaped tensor for") << aName << ", got " << aType; return failure(); } - if (!outputType) { - op.emitOpError("expect shaped tensor for output, got ") << outType; + if (!bTType) { + op.emitOpError("expect shaped tensor for") << bName << ", got" << bType; return failure(); } - auto inputElementType = inputType.getElementType(); - auto outputElementType = outputType.getElementType(); - auto inputQuantType = - llvm::dyn_cast(inputElementType); - auto outputQuantType = - llvm::dyn_cast(outputElementType); - if ((inputElementType.isIntOrIndexOrFloat() || inputQuantType) && - (outputElementType.isIntOrIndexOrFloat() || outputQuantType) && - inputElementType != outputElementType) { + auto aElementType = aTType.getElementType(); + auto bElementType = bTType.getElementType(); + auto aQuantType = + llvm::dyn_cast(aElementType); + auto bQuantType = + llvm::dyn_cast(bElementType); + if ((aElementType.isIntOrIndexOrFloat() || aQuantType) && + (bElementType.isIntOrIndexOrFloat() || bQuantType) && + aElementType != bElementType) { // only check if both element types are int/index/float/UniformQuantized // eg, not sure how to check quant::QuantizedType // this happens in test_conv2d_q_grouped_convolution in // tfl-to-tosa-pipeline.mlir - op.emitOpError("expect input and output to have same element type, got ") - << inputElementType << " and " << outputElementType; + op.emitOpError("expect ") + << aName << " and " << bName << " to have same element type, got " + << aElementType << " and " << bElementType; return failure(); } return success(); @@ -1846,6 +1873,161 @@ LogicalResult MatMulOp::verify() { return success(); } +LogicalResult tosa::MatmulTBlockScaledOp::inferReturnTypeComponents( + MLIRContext *context, ::std::optional location, + MatmulTBlockScaledOp::Adaptor adaptor, + SmallVectorImpl &inferredReturnShapes) { + SmallVector outShape(3, ShapedType::kDynamic); + + const auto aDataShape = cast(adaptor.getAData().getType()); + if (aDataShape.hasRank()) { + outShape[0] = aDataShape.getDimSize(0); + outShape[1] = aDataShape.getDimSize(1); + } + + const auto aScaleShape = cast(adaptor.getAScale().getType()); + if (aScaleShape.hasRank()) { + outShape[0] = ShapedType::isDynamic(outShape[0]) ? aScaleShape.getDimSize(0) + : outShape[0]; + outShape[1] = ShapedType::isDynamic(outShape[1]) ? aScaleShape.getDimSize(1) + : outShape[1]; + } + + // If B batch size is 1, it is broadcast across A's batch size + const auto bDataShape = cast(adaptor.getBData().getType()); + if (bDataShape.hasRank()) { + const int64_t bDataBatchSize = bDataShape.getDimSize(0); + if (bDataBatchSize != 1) + outShape[0] = + ShapedType::isDynamic(outShape[0]) ? bDataBatchSize : outShape[0]; + outShape[2] = bDataShape.getDimSize(1); + } + + const auto bScaleShape = cast(adaptor.getBScale().getType()); + if (bScaleShape.hasRank()) { + const int64_t bScaleBatchSize = bScaleShape.getDimSize(0); + if (bScaleBatchSize != 1) + outShape[0] = + ShapedType::isDynamic(outShape[0]) ? bScaleBatchSize : outShape[0]; + outShape[2] = ShapedType::isDynamic(outShape[2]) ? bScaleShape.getDimSize(1) + : outShape[2]; + } + + inferredReturnShapes.push_back(ShapedTypeComponents(outShape)); + return success(); +} + +LogicalResult MatmulTBlockScaledOp::verify() { + // Verify same input data types + const Type aDataType = getAData().getType(); + const Type bDataType = getBData().getType(); + if (failed(verifySameElementTypes(*this, aDataType, bDataType, "A_data", + "B_data"))) + return failure(); + + auto tryUpdateDimOrFailure = [&](int64_t &currDim, const int64_t newDim, + const StringRef operandName, + const StringRef dimName) -> LogicalResult { + if (ShapedType::isDynamic(currDim)) { + currDim = newDim; + return success(); + } else if (ShapedType::isStatic(newDim) && currDim != newDim) { + return emitOpError("expected ") + << dimName << " of " << operandName << " to match size " << currDim + << ", got " << newDim; + } + return success(); + }; + + // Verify input shape compatibility + int64_t N = ShapedType::kDynamic; + int64_t D = ShapedType::kDynamic; + int64_t H = ShapedType::kDynamic; + int64_t W = ShapedType::kDynamic; + int64_t C = ShapedType::kDynamic; + int64_t multiplesOfC = ShapedType::kDynamic; + + const ShapeAdaptor aDataShape = ShapeAdaptor(aDataType); + if (aDataShape.hasRank()) { + N = aDataShape.getDimSize(0); + H = aDataShape.getDimSize(1); + C = aDataShape.getDimSize(2); + } + + const ShapeAdaptor aScaleShape = ShapeAdaptor(getAScale().getType()); + if (aScaleShape.hasRank()) { + if (failed(tryUpdateDimOrFailure(N, aScaleShape.getDimSize(0), "a_scale", + "batch")) || + failed(tryUpdateDimOrFailure(H, aScaleShape.getDimSize(1), "a_scale", + "height"))) + return failure(); + multiplesOfC = aScaleShape.getDimSize(2); + } + + const ShapeAdaptor bDataShape = ShapeAdaptor(bDataType); + if (bDataShape.hasRank()) { + if (failed(tryUpdateDimOrFailure(D, bDataShape.getDimSize(0), "b_data", + "batch")) || + failed(tryUpdateDimOrFailure(C, bDataShape.getDimSize(2), "b_data", + "channels"))) + return failure(); + W = bDataShape.getDimSize(1); + } + + const ShapeAdaptor bScaleShape = ShapeAdaptor(getBScale().getType()); + if (bScaleShape.hasRank()) { + if (failed(tryUpdateDimOrFailure(D, bScaleShape.getDimSize(0), "b_scale", + "batch")) || + failed(tryUpdateDimOrFailure(W, bScaleShape.getDimSize(1), "b_scale", + "width")) || + failed(tryUpdateDimOrFailure(multiplesOfC, bScaleShape.getDimSize(2), + "b_scale", "C/block_size"))) + return failure(); + } + + // Verify batch size is broadcast compatible + if (ShapedType::isStatic(N) && ShapedType::isStatic(D) && N != D && D != 1) + return emitOpError("expect B matrix batch size to be broadcast compatible " + "with A, got D=") + << D << " vs N=" << N; + + // Verify C is a multiple of block size + const uint32_t blockSize = BlockSizeAttr::getBlockSizeValue(getBlockSize()); + if (ShapedType::isStatic(C) && C % blockSize != 0) + return emitOpError("expect C to be a multiple of block size, got C=") + << C << ", block_size=" << blockSize; + + // Verify multiplesOfC is C / block size + if (ShapedType::isStatic(C) && ShapedType::isStatic(multiplesOfC) && + multiplesOfC != C / blockSize) + return emitOpError( + "expect scale operands dimension 2 to equal C/block_size (") + << C << "/" << blockSize << ")" + << ", got " << multiplesOfC; + + // Verify output shape + N = ShapedType::isDynamic(N) ? D : N; + const SmallVector expectedOutputShape = {N, H, W}; + const auto outputType = cast(getResult().getType()); + if (outputType.hasRank() && + failed( + verifyCompatibleShape(outputType.getShape(), expectedOutputShape))) { + InFlightDiagnostic opError = emitOpError("expected output shape "); + auto stringifyDim = [&](int64_t d) { + if (ShapedType::isDynamic(d)) + opError << "?"; + else + opError << d; + }; + llvm::interleaveComma(outputType.getShape(), opError, stringifyDim); + opError << " to be compatible with expected output shape "; + llvm::interleaveComma(expectedOutputShape, opError, stringifyDim); + return opError; + } + + return success(); +} + LogicalResult tosa::PadOp::inferReturnTypeComponents( MLIRContext *context, ::std::optional location, PadOp::Adaptor adaptor, diff --git a/mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp b/mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp index f072e3eff1975..e965ae0cf9888 100644 --- a/mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp +++ b/mlir/lib/Dialect/Tosa/Transforms/TosaProfileCompliance.cpp @@ -25,6 +25,12 @@ TosaProfileCompliance::TosaProfileCompliance() { const TypeInfo fp8e4m3T = {mlir::Float8E4M3FNType::getTypeID(), 8}; const TypeInfo fp8e5m2T = {mlir::Float8E5M2Type::getTypeID(), 8}; + // micro-scaling formats + const TypeInfo fp6e2m3T = {mlir::Float6E2M3FNType::getTypeID(), 6}; + const TypeInfo fp6e3m2T = {mlir::Float6E3M2FNType::getTypeID(), 6}; + const TypeInfo fp4e2m1T = {mlir::Float4E2M1FNType::getTypeID(), 4}; + const TypeInfo fp8ue8m0T = {mlir::Float8E8M0FNUType::getTypeID(), 8}; + // The profile-based compliance content below is auto-generated by a script // in https://git.mlplatform.org/tosa/specification.git #include "mlir/Dialect/Tosa/IR/TosaComplianceData.h.inc" @@ -269,6 +275,7 @@ LogicalResult ProfileInfoDepot::populatationDispatch(Operation *op) { // For the most of tosa operators, all operands are profile/extension related // and hence are all considered in this profile-based compilance check. + POPULATE_PROFILE_INFO_COMMON(MatmulTBlockScaled) POPULATE_PROFILE_INFO_COMMON(Cast) POPULATE_PROFILE_INFO_COMMON(Const) POPULATE_PROFILE_INFO_COMMON(ArgMax) @@ -623,6 +630,14 @@ TosaProfileCompliance::stringifyTypeInfo(const TypeInfo &typeInfo) { return {"fp8e4m3"}; } else if (typeInfo.typeID == mlir::Float8E5M2Type::getTypeID()) { return {"fp8e5m2"}; + } else if (typeInfo.typeID == mlir::Float6E2M3FNType::getTypeID()) { + return {"fp6e2m3"}; + } else if (typeInfo.typeID == mlir::Float6E3M2FNType::getTypeID()) { + return {"fp6e3m2"}; + } else if (typeInfo.typeID == mlir::Float4E2M1FNType::getTypeID()) { + return {"fp4e2m1"}; + } else if (typeInfo.typeID == mlir::Float8E8M0FNUType::getTypeID()) { + return {"fp8e8m0"}; } llvm_unreachable("unknown type"); } diff --git a/mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp b/mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp index 82f2f7eb17af4..3f874d94ab9be 100644 --- a/mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp +++ b/mlir/lib/Dialect/Tosa/Transforms/TosaValidation.cpp @@ -657,6 +657,7 @@ LogicalResult TosaValidation::levelCheckRanksAndSizes(Operation *op) { CHECK_SIZES(TransposeConv2D); CHECK_SIZES(FFT2d); CHECK_SIZES(MatMul); + CHECK_SIZES(MatmulTBlockScaled); CHECK_SIZES(MaxPool2d); CHECK_SIZES(RFFT2d); // Scatter/Gather Operators @@ -1192,9 +1193,9 @@ LogicalResult TosaValidation::applyErrorIfCheck(Operation *op) { bool TosaValidation::isValidElementType(Type type, const bool allowUnsigned) { if (isa(type)) { return isa(type); - } - if (auto intTy = dyn_cast(type)) { + Float8E5M2Type, Float4E2M1FNType, Float6E2M3FNType, + Float6E3M2FNType, Float8E8M0FNUType>(type); + } else if (auto intTy = dyn_cast(type)) { if (intTy.isSignless()) { switch (intTy.getWidth()) { case 1: @@ -1220,13 +1221,19 @@ bool TosaValidation::isValidElementType(Type type, const bool allowUnsigned) { } void TosaValidation::runOnOperation() { + ModuleOp modOp = getOperation(); + const TargetEnvAttr targetEnvAttr = lookupTargetEnvOrDefault(modOp); + const auto maybeTargetEnv = + tosa::TargetEnv::createTargetEnvFromAttr(targetEnvAttr, modOp.getLoc()); + if (failed(maybeTargetEnv)) + return signalPassFailure(); + targetEnv = *maybeTargetEnv; + TosaDialect *tosaDialect = getContext().getLoadedDialect(); if (!tosaDialect) return; - targetEnv = tosa::TargetEnv(lookupTargetEnvOrDefault(getOperation())); - - getOperation().walk([&](Operation *op) { + modOp.walk([&](Operation *op) { if (op->getDialect() != tosaDialect) return; diff --git a/mlir/test/Dialect/Tosa/invalid_extension.mlir b/mlir/test/Dialect/Tosa/invalid_extension.mlir index e5c9402caaddc..005601d4017b8 100644 --- a/mlir/test/Dialect/Tosa/invalid_extension.mlir +++ b/mlir/test/Dialect/Tosa/invalid_extension.mlir @@ -538,3 +538,11 @@ func.func @test_avg_pool2d_non_const_output_zp(%arg0: tensor<1x32x32x8xf32>, %ou (tensor<1x32x32x8xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<1x32x32x8xf32> return %0 : tensor<1x32x32x8xf32> } + +// ----- + +func.func @test_matmul_t_block_scaled(%arg0: tensor<4x8x32xf8E4M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf8E4M3FN>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + // expected-error@+1 {{'tosa.matmul_t_block_scaled' op illegal: requires [mxfp] but not enabled in target}} + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<4x8x32xf8E4M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf8E4M3FN>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} diff --git a/mlir/test/Dialect/Tosa/level_check.mlir b/mlir/test/Dialect/Tosa/level_check.mlir index 8cc357efa0c77..8771e6e2476e4 100644 --- a/mlir/test/Dialect/Tosa/level_check.mlir +++ b/mlir/test/Dialect/Tosa/level_check.mlir @@ -1622,3 +1622,12 @@ func.func @test_unranked_weight_conv2d(%arg0: tensor<1x4x4x4xf32>, %arg1: tensor %0 = tosa.conv2d %arg0, %arg1, %arg2, %arg3, %arg4 {acc_type = f32, dilation = array, pad = array, stride = array, local_bound = true} : (tensor<1x4x4x4xf32>, tensor<*xf32>, tensor<8xf32>, tensor<1xf32>, tensor<1xf32>) -> tensor<*xf32> return %0 : tensor<*xf32> } + +// ----- + +// CHECK-LABEL: test_matmul_t_block_scaled_invalid_size +func.func @test_matmul_t_block_scaled_invalid_size(%arg0: tensor<4x8x536870912xf4E2M1FN>, %arg1: tensor<4x8x16777216xf8E8M0FNU>, %arg2: tensor<4x16x536870912xf4E2M1FN>, %arg3: tensor<4x16x16777216xf8E8M0FNU>) -> tensor<*xf32> { + // expected-error@+1 {{'tosa.matmul_t_block_scaled' op failed level check: operand tensor size (in bytes) <= (1 << MAX_LOG2_SIZE - 1)}} + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<4x8x536870912xf4E2M1FN>, tensor<4x8x16777216xf8E8M0FNU>, tensor<4x16x536870912xf4E2M1FN>, tensor<4x16x16777216xf8E8M0FNU>) -> tensor<*xf32> + return %0 : tensor<*xf32> +} diff --git a/mlir/test/Dialect/Tosa/ops.mlir b/mlir/test/Dialect/Tosa/ops.mlir index 868b7b7a93335..9bf36b5fd4c7d 100644 --- a/mlir/test/Dialect/Tosa/ops.mlir +++ b/mlir/test/Dialect/Tosa/ops.mlir @@ -1226,3 +1226,45 @@ func.func @test_scatter_f8E4M3FN(%arg0: tensor<13x29x3xf8E4M3FN>, %arg1: tensor< %0 = tosa.scatter %arg0, %arg1, %arg2 : (tensor<13x29x3xf8E4M3FN>, tensor<13x26xi32>, tensor<13x26x3xf8E4M3FN>) -> tensor<13x29x3xf8E4M3FN> return %0 : tensor<13x29x3xf8E4M3FN> } + +// ----- +// CHECK-LABEL: test_matmul_t_block_scaled_static +func.func @test_matmul_t_block_scaled_static(%arg0: tensor<4x8x32xf8E4M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf8E4M3FN>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<4x8x32xf8E4M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf8E4M3FN>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} + +// ----- +// CHECK-LABEL: test_matmul_t_block_scaled_unranked +func.func @test_matmul_t_block_scaled_unranked(%arg0: tensor<*xf8E4M3FN>, %arg1: tensor<*xf8E8M0FNU>, %arg2: tensor<*xf8E4M3FN>, %arg3: tensor<*xf8E8M0FNU>) -> tensor<*xf32> { + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<*xf8E4M3FN>, tensor<*xf8E8M0FNU>, tensor<*xf8E4M3FN>, tensor<*xf8E8M0FNU>) -> tensor<*xf32> + return %0 : tensor<*xf32> +} + +// ----- +// CHECK-LABEL: test_matmul_t_block_scaled_fp6e3m2 +func.func @test_matmul_t_block_scaled_fp6e3m2(%arg0: tensor<4x8x32xf6E3M2FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf6E3M2FN>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<4x8x32xf6E3M2FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf6E3M2FN>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} + +// ----- +// CHECK-LABEL: test_matmul_t_block_scaled_fp6e2m3 +func.func @test_matmul_t_block_scaled_fp6e2m3(%arg0: tensor<4x8x32xf6E2M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf6E2M3FN>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<4x8x32xf6E2M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf6E2M3FN>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} + +// ----- +// CHECK-LABEL: test_matmul_t_block_scaled_fp4e2m1 +func.func @test_matmul_t_block_scaled_fp4e2m1(%arg0: tensor<4x8x32xf4E2M1FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf4E2M1FN>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<4x8x32xf4E2M1FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf4E2M1FN>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} + +// ----- +// CHECK-LABEL: test_matmul_t_block_scaled_broadcast +func.func @test_matmul_t_block_scaled_broadcast(%arg0: tensor, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor, %arg3: tensor<1x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor, tensor<4x8x1xf8E8M0FNU>, tensor, tensor<1x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} diff --git a/mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir b/mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir index 7ff8065ee41fd..0271d71561a52 100644 --- a/mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir +++ b/mlir/test/Dialect/Tosa/profile_pro_fp_unsupported.mlir @@ -2,7 +2,7 @@ // Enable all supported extensions to focus the verification of expected profile requirement errors. //-------------------------------------------------------------------------------------------------- -// RUN: mlir-opt %s -split-input-file -verify-diagnostics -tosa-attach-target="profiles=pro_int extensions=int16,int4,bf16,fp8e4m3,fp8e5m2,fft,variable,controlflow,dynamic,doubleround,inexactround" -tosa-validate="strict-op-spec-alignment" +// RUN: mlir-opt %s -split-input-file -verify-diagnostics -tosa-attach-target="specification_version=1.1.draft profiles=pro_int extensions=int16,int4,bf16,fp8e4m3,fp8e5m2,fft,variable,controlflow,dynamic,doubleround,inexactround,mxfp" -tosa-validate="strict-op-spec-alignment" // ----- func.func @test_const_f16() -> tensor<3x11x11x3xf16> { @@ -325,3 +325,10 @@ func.func @test_resize(%arg0: tensor<1x32x32x8xf32>) -> tensor<1x64x64x8xf32> { %1 = tosa.resize %arg0, %scale, %offset, %border { mode = BILINEAR } : (tensor<1x32x32x8xf32>, !tosa.shape<4>, !tosa.shape<2>, !tosa.shape<2>) -> tensor<1x64x64x8xf32> return %1 : tensor<1x64x64x8xf32> } + +// ----- +func.func @test_matmul_t_block_scaled(%arg0: tensor<4x8x32xf6E3M2FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf6E3M2FN>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + // expected-error@+1 {{'tosa.matmul_t_block_scaled' op illegal: requires [pro_fp] but not enabled in target}} + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<4x8x32xf6E3M2FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf6E3M2FN>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} diff --git a/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir b/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir index 80f06f11fe4ad..72479fe21ade8 100644 --- a/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir +++ b/mlir/test/Dialect/Tosa/tosa-infer-shapes.mlir @@ -1574,3 +1574,57 @@ func.func @test_mul_scalar(%arg0: tensor, %arg1: tensor) -> tensor<*xf %0 = tosa.mul %arg0, %arg1, %shift : (tensor, tensor, tensor<1xi8>) -> tensor<*xf32> return %0 : tensor<*xf32> } + +// ----- + +// CHECK-LABEL: test_matmul_t_block_scaled_static +func.func @test_matmul_t_block_scaled_static(%arg0: tensor<4x8x32xf8E4M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<1x16x32xf8E4M3FN>, %arg3: tensor<1x16x1xf8E8M0FNU>) -> tensor { + // CHECK: -> tensor<4x8x16xf32> + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<4x8x32xf8E4M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<1x16x32xf8E4M3FN>, tensor<1x16x1xf8E8M0FNU>) -> tensor + return %0 : tensor +} + +// ----- + +// CHECK-LABEL: test_matmul_t_block_scaled_unranked_a_data +func.func @test_matmul_t_block_scaled_unranked_a_data(%arg0: tensor<*xf8E4M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf8E4M3FN>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor { + // CHECK: -> tensor<4x8x16xf32> + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<*xf8E4M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf8E4M3FN>, tensor<4x16x1xf8E8M0FNU>) -> tensor + return %0 : tensor +} + +// ----- + +// CHECK-LABEL: test_matmul_t_block_scaled_unranked_b_data_and_scale +func.func @test_matmul_t_block_scaled_unranked_b_data_and_scale(%arg0: tensor<4x8x32xf8E4M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<*xf8E4M3FN>, %arg3: tensor<*xf8E8M0FNU>) -> tensor { + // CHECK: -> tensor<4x8x?xf32> + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<4x8x32xf8E4M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<*xf8E4M3FN>, tensor<*xf8E8M0FNU>) -> tensor + return %0 : tensor +} + +// ----- + +// CHECK-LABEL: test_matmul_t_block_scaled_unranked_all +func.func @test_matmul_t_block_scaled_unranked_all(%arg0: tensor<*xf8E4M3FN>, %arg1: tensor<*xf8E8M0FNU>, %arg2: tensor<*xf8E4M3FN>, %arg3: tensor<*xf8E8M0FNU>) -> tensor { + // CHECK: -> tensor + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<*xf8E4M3FN>, tensor<*xf8E8M0FNU>, tensor<*xf8E4M3FN>, tensor<*xf8E8M0FNU>) -> tensor + return %0 : tensor +} + +// ----- + +// CHECK-LABEL: test_matmul_t_block_scaled_broadcast_b_data +func.func @test_matmul_t_block_scaled_broadcast_b_data(%arg0: tensor<*xf8E4M3FN>, %arg1: tensor<*xf8E8M0FNU>, %arg2: tensor<1x4x32xf8E4M3FN>, %arg3: tensor<1x4x1xf8E8M0FNU>) -> tensor { + // CHECK: -> tensor + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<*xf8E4M3FN>, tensor<*xf8E8M0FNU>, tensor<1x4x32xf8E4M3FN>, tensor<1x4x1xf8E8M0FNU>) -> tensor + return %0 : tensor +} + +// ----- + +// CHECK-LABEL: test_matmul_t_block_scaled_broadcast_b_scale +func.func @test_matmul_t_block_scaled_broadcast_b_scale(%arg0: tensor<*xf8E4M3FN>, %arg1: tensor<*xf8E8M0FNU>, %arg2: tensor<*xf8E4M3FN>, %arg3: tensor<1x4x1xf8E8M0FNU>) -> tensor { + // CHECK: -> tensor + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size} : (tensor<*xf8E4M3FN>, tensor<*xf8E8M0FNU>, tensor<*xf8E4M3FN>, tensor<1x4x1xf8E8M0FNU>) -> tensor + return %0 : tensor +} diff --git a/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir b/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir index 81645092bf195..2040a4bc7e6af 100644 --- a/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir +++ b/mlir/test/Dialect/Tosa/tosa-validation-version-1p1-valid.mlir @@ -1,4 +1,4 @@ -// RUN: mlir-opt %s -split-input-file -verify-diagnostics -tosa-attach-target="specification_version=1.1.draft profiles=pro_int,pro_fp extensions=int16,int4,bf16,fp8e4m3,fp8e5m2,fft,variable,controlflow,doubleround,inexactround" -tosa-validate="strict-op-spec-alignment" | FileCheck %s +// RUN: mlir-opt %s -split-input-file -verify-diagnostics -tosa-attach-target="specification_version=1.1.draft profiles=pro_int,pro_fp extensions=int16,int4,bf16,fp8e4m3,fp8e5m2,fft,variable,controlflow,doubleround,inexactround,mxfp" -tosa-validate="strict-op-spec-alignment" | FileCheck %s // ----- @@ -18,3 +18,11 @@ func.func @test_matmul_fp8_input_fp32_acc_type(%arg0: tensor<1x14x19xf8E4M3FN>, %0 = tosa.matmul %arg0, %arg1, %azp0, %bzp0 : (tensor<1x14x19xf8E4M3FN>, tensor<1x19x28xf8E4M3FN>, tensor<1xf8E4M3FN>, tensor<1xf8E4M3FN>) -> tensor<1x14x28xf32> return %0 : tensor<1x14x28xf32> } + +// ----- + +// CHECK-LABEL: test_matmul_t_block_scaled_fp6e2m3 +func.func @test_matmul_t_block_scaled_fp6e2m3(%arg0: tensor<4x8x32xf6E2M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf6E2M3FN>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = BLOCK_SIZE_32} : (tensor<4x8x32xf6E2M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf6E2M3FN>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} diff --git a/mlir/test/Dialect/Tosa/verifier.mlir b/mlir/test/Dialect/Tosa/verifier.mlir index 430b06ad16c39..4be5d725ad612 100644 --- a/mlir/test/Dialect/Tosa/verifier.mlir +++ b/mlir/test/Dialect/Tosa/verifier.mlir @@ -1102,3 +1102,51 @@ func.func @scatter_invalid_K_W(%arg0 : tensor<2x4x5xi32>, %arg1 : tensor<2x6xi32 %2 = tosa.scatter %arg0, %arg1, %arg2 : (tensor<2x4x5xi32>, tensor<2x6xi32>, tensor<2x6x5xi32>) -> tensor<2x4x5xi32> return } + +// ----- + +func.func @test_matmul_t_block_scaled_data_mismatch(%arg0: tensor<4x8x32xf8E4M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf8E5M2>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + // expected-error@+1 {{'tosa.matmul_t_block_scaled' op expect A_data and B_data to have same element type, got 'f8E4M3FN' and 'f8E5M2'}} + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size : i32} : (tensor<4x8x32xf8E4M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf8E5M2>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} + +// ----- + +func.func @test_matmul_t_block_scaled_output_batch_mismatch(%arg0: tensor<*xf8E4M3FN>, %arg1: tensor, %arg2: tensor<*xf8E4M3FN>, %arg3: tensor<4x?x?xf8E8M0FNU>) -> tensor<5x?x?xf32> { + // expected-error@+1 {{'tosa.matmul_t_block_scaled' op expected output shape 5, ?, ? to be compatible with expected output shape 4, 8, ?}} + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size : i32} : (tensor<*xf8E4M3FN>, tensor, tensor<*xf8E4M3FN>, tensor<4x?x?xf8E8M0FNU>) -> tensor<5x?x?xf32> + return %0 : tensor<5x?x?xf32> +} + +// ----- + +func.func @test_matmul_t_block_scaled_output_height_mismatch(%arg0: tensor<*xf8E4M3FN>, %arg1: tensor, %arg2: tensor<*xf8E4M3FN>, %arg3: tensor<4x?x?xf8E8M0FNU>) -> tensor<4x8x?xf32> { + // expected-error@+1 {{'tosa.matmul_t_block_scaled' op expected output shape 4, 8, ? to be compatible with expected output shape 4, 9, ?}} + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size : i32} : (tensor<*xf8E4M3FN>, tensor, tensor<*xf8E4M3FN>, tensor<4x?x?xf8E8M0FNU>) -> tensor<4x8x?xf32> + return %0 : tensor<4x8x?xf32> +} + +// ----- + +func.func @test_matmul_t_block_scaled_output_width_mismatch(%arg0: tensor<*xf8E4M3FN>, %arg1: tensor, %arg2: tensor, %arg3: tensor<*xf8E8M0FNU>) -> tensor { + // expected-error@+1 {{'tosa.matmul_t_block_scaled' op expected output shape ?, ?, 10 to be compatible with expected output shape ?, ?, 1}} + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size : i32} : (tensor<*xf8E4M3FN>, tensor, tensor, tensor<*xf8E8M0FNU>) -> tensor + return %0 : tensor +} + +// ----- + +func.func @test_matmul_t_block_scaled_channel_not_multiple_of_block_size(%arg0: tensor<4x8x55xf8E4M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<4x16x32xf8E4M3FN>, %arg3: tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + // expected-error@+1 {{'tosa.matmul_t_block_scaled' op expected channels of b_data to match size 55, got 32}} + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size : i32} : (tensor<4x8x55xf8E4M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<4x16x32xf8E4M3FN>, tensor<4x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} + +// ----- + +func.func @test_matmul_t_block_scaled_batch_mismatch(%arg0: tensor<4x8x32xf8E4M3FN>, %arg1: tensor<4x8x1xf8E8M0FNU>, %arg2: tensor<2x16x32xf8E4M3FN>, %arg3: tensor<2x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> { + // expected-error@+1 {{'tosa.matmul_t_block_scaled' op expect B matrix batch size to be broadcast compatible with A, got D=2 vs N=4}} + %0 = tosa.matmul_t_block_scaled %arg0, %arg1, %arg2, %arg3 {block_size = #tosa.block_size : i32} : (tensor<4x8x32xf8E4M3FN>, tensor<4x8x1xf8E8M0FNU>, tensor<2x16x32xf8E4M3FN>, tensor<2x16x1xf8E8M0FNU>) -> tensor<4x8x16xf32> + return %0 : tensor<4x8x16xf32> +} From 917d1f20aecfdbdc9e5a7a0eaf947ff7be6fbe15 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Thu, 23 Oct 2025 11:03:38 -0400 Subject: [PATCH 06/31] Silence "not all control paths return a value" warning; NFC --- clang/lib/Sema/SemaOpenACC.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/lib/Sema/SemaOpenACC.cpp b/clang/lib/Sema/SemaOpenACC.cpp index ee9b2b399e762..f0f3832e160cd 100644 --- a/clang/lib/Sema/SemaOpenACC.cpp +++ b/clang/lib/Sema/SemaOpenACC.cpp @@ -3086,6 +3086,7 @@ bool SemaOpenACC::CreateReductionCombinerRecipe( case OpenACCReductionOperator::Invalid: llvm_unreachable("Invalid should have been caught above"); } + llvm_unreachable("Unhandled case"); }; auto tryCombiner = [&, this](DeclRefExpr *LHSDRE, DeclRefExpr *RHSDRE, From faf7af864f9258768133894764f1fae58d43bb09 Mon Sep 17 00:00:00 2001 From: Chad Smith Date: Thu, 23 Oct 2025 08:04:57 -0700 Subject: [PATCH 07/31] [lldb] update lldb-server platform help parsing (#162730) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The lldb-server platform help text is inconsistent with lldb-server gdbserver help text. This PR modernizes the platform server to use LLVM's [TableGen](https://llvm.org/docs/TableGen/)-based option parsing (matching the existing gdbserver implementation), which auto-generates option parsing code and help text. The changes improve documentation quality by adding comprehensive option descriptions,, adding support for `-h`/`--help` flags, and organizing help output with DESCRIPTION and EXAMPLES sections. Internal-only options (`--child-platform-fd`) and unused legacy options (`--debug`, `--verbose`) are now hidden from help while maintaining backward compatibility. All functional behavior remains unchanged—this is purely a documentation and code modernization improvement. ## before ``` > /opt/llvm/bin/lldb-server p -h p: unrecognized option '-h' Usage: /opt/llvm/bin/lldb-server p [--log-file log-file-name] [--log-channels log-channel-list] [--port-file port-file-path] --server --listen port ``` ## after ``` lldb-server p -h OVERVIEW: lldb-server platform USAGE: lldb-server p [options] --listen <[host]:port> [[--] program args...] CONNECTION OPTIONS: --gdbserver-port Port to use for spawned gdbserver instances. If 0 or unspecified, a port will be chosen automatically. Short form: -P --listen <[host]:port> Host and port to listen on. Format: [host]:port or protocol://[host]:port (e.g., tcp://localhost:1234, unix:///path/to/socket). Short form: -L --socket-file Write listening socket information (port number for TCP or path for Unix domain sockets) to the specified file. Short form: -f GENERAL OPTIONS: --help Display this help message and exit. --log-channels Channels to log. A colon-separated list of entries. Each entry starts with a channel followed by a space-separated list of categories. Common channels: lldb, gdb-remote, platform, process. Short form: -c --log-file Destination file to log to. If empty, log to stderr. Short form: -l --server Run in server mode, accepting multiple client connections sequentially. Without this flag, the server exits after handling the first connection. OPTIONS: -- program args Arguments to pass to launched gdbserver instances. DESCRIPTION Acts as a platform server for remote debugging. When LLDB clients connect, the platform server handles platform operations (file transfers, process launching) and spawns debug server instances (lldb-server gdbserver) to handle actual debugging sessions. By default, the server exits after handling one connection. Use --server to keep running and accept multiple connections sequentially. EXAMPLES # Listen on port 1234, exit after first connection lldb-server platform --listen tcp://0.0.0.0:1234 # Listen on port 5555, accept multiple connections lldb-server platform --server --listen tcp://localhost:5555 # Listen on Unix domain socket lldb-server platform --listen unix:///tmp/lldb-server.sock ``` For comparison, here is the **gdbserver** help text: ``` lldb-server g -h OVERVIEW: lldb-server USAGE: lldb-server g[dbserver] [options] [[host]:port] [[--] program args...] CONNECTION: --fd Communicate over the given file descriptor. --named-pipe Write port lldb-server will listen on to the given named pipe. --pipe Write port lldb-server will listen on to the given file descriptor. --reverse-connect Connect to the client instead of passively waiting for a connection. In this case [host]:port denotes the remote address to connect to. GENERAL OPTIONS: --help Prints out the usage information for lldb-server. --log-channels Channels to log. A colon-separated list of entries. Each entry starts with a channel followed by a space-separated list of categories. --log-file Destination file to log to. If empty, log to stderr. --setsid Run lldb-server in a new session. TARGET SELECTION: --attach Attach to the process given by a (numeric) process id or a name. -- program args Launch program for debugging. DESCRIPTION lldb-server connects to the LLDB client, which drives the debugging session. If no connection options are given, the [host]:port argument must be present and will denote the address that lldb-server will listen on. [host] defaults to "localhost" if empty. Port can be zero, in which case the port number will be chosen dynamically and written to destinations given by --named-pipe and --pipe arguments. If no target is selected at startup, lldb-server can be directed by the LLDB client to launch or attach to a process. ``` --- ...s.test => TestGdbserverErrorMessages.test} | 0 .../TestPlatformErrorMessages.test | 25 ++ .../Shell/lldb-server/TestPlatformHelp.test | 40 +++ .../TestPlatformSuccessfulStartup.test | 35 +++ lldb/tools/lldb-server/CMakeLists.txt | 5 + lldb/tools/lldb-server/PlatformOptions.td | 75 +++++ lldb/tools/lldb-server/lldb-platform.cpp | 265 +++++++++++------- 7 files changed, 336 insertions(+), 109 deletions(-) rename lldb/test/Shell/lldb-server/{TestErrorMessages.test => TestGdbserverErrorMessages.test} (100%) create mode 100644 lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test create mode 100644 lldb/test/Shell/lldb-server/TestPlatformHelp.test create mode 100644 lldb/test/Shell/lldb-server/TestPlatformSuccessfulStartup.test create mode 100644 lldb/tools/lldb-server/PlatformOptions.td diff --git a/lldb/test/Shell/lldb-server/TestErrorMessages.test b/lldb/test/Shell/lldb-server/TestGdbserverErrorMessages.test similarity index 100% rename from lldb/test/Shell/lldb-server/TestErrorMessages.test rename to lldb/test/Shell/lldb-server/TestGdbserverErrorMessages.test diff --git a/lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test b/lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test new file mode 100644 index 0000000000000..d8af31ebaca52 --- /dev/null +++ b/lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test @@ -0,0 +1,25 @@ +RUN: %platformserver 2>&1 | FileCheck --check-prefixes=NO_LISTEN,ALL %s +NO_LISTEN: error: either --listen or --child-platform-fd is required + +RUN: %lldb-server platform --listen 2>&1 | FileCheck --check-prefixes=LISTEN_MISSING,ALL %s +LISTEN_MISSING: error: --listen: missing argument + +RUN: %lldb-server p --bogus 2>&1 | FileCheck --check-prefixes=BOGUS,ALL %s +BOGUS: error: unknown argument '--bogus' + +RUN: %platformserver --gdbserver-port 2>&1 | FileCheck --check-prefixes=GDBPORT_MISSING,ALL %s +GDBPORT_MISSING: error: --gdbserver-port: missing argument + +RUN: %platformserver --gdbserver-port notanumber --listen :1234 2>&1 | FileCheck --check-prefixes=GDBPORT_INVALID %s +GDBPORT_INVALID: error: invalid --gdbserver-port value + +RUN: %platformserver --socket-file 2>&1 | FileCheck --check-prefixes=SOCKETFILE_MISSING,ALL %s +SOCKETFILE_MISSING: error: --socket-file: missing argument + +RUN: %platformserver --log-file 2>&1 | FileCheck --check-prefixes=LOGFILE_MISSING,ALL %s +LOGFILE_MISSING: error: --log-file: missing argument + +RUN: %platformserver --log-channels 2>&1 | FileCheck --check-prefixes=LOGCHANNELS_MISSING,ALL %s +LOGCHANNELS_MISSING: error: --log-channels: missing argument + +ALL: Use 'lldb-server {{p|platform}} --help' for a complete list of options. diff --git a/lldb/test/Shell/lldb-server/TestPlatformHelp.test b/lldb/test/Shell/lldb-server/TestPlatformHelp.test new file mode 100644 index 0000000000000..119bbcaaabf14 --- /dev/null +++ b/lldb/test/Shell/lldb-server/TestPlatformHelp.test @@ -0,0 +1,40 @@ +RUN: %platformserver --help 2>&1 | FileCheck %s +RUN: %platformserver -h 2>&1 | FileCheck %s +RUN: %lldb-server p --help 2>&1 | FileCheck %s +RUN: %lldb-server p -h 2>&1 | FileCheck %s +RUN: %lldb-server platform --help 2>&1 | FileCheck %s +RUN: %lldb-server platform -h 2>&1 | FileCheck %s + +CHECK: OVERVIEW: lldb-server platform + +CHECK: USAGE: lldb-server {{p|platform}} [options] --listen <[host]:port> {{\[}}[--] program args...] + +CHECK: CONNECTION OPTIONS: +CHECK: --gdbserver-port +CHECK-SAME: Short form: -P +CHECK: --listen <[host]:port> +CHECK-SAME: Short form: -L +CHECK: --socket-file +CHECK-SAME: Short form: -f + +CHECK: GENERAL OPTIONS: +CHECK: --help +CHECK: --log-channels +CHECK: Short form: -c +CHECK: --log-file +CHECK-SAME: Short form: -l +CHECK: --server + +CHECK: OPTIONS: +CHECK: -- program args + +CHECK: DESCRIPTION +CHECK: Acts as a platform server for remote debugging + +CHECK: EXAMPLES +CHECK: # Listen on port 1234, exit after first connection +CHECK: lldb-server platform --listen tcp://0.0.0.0:1234 +CHECK: # Listen on port 5555, accept multiple connections +CHECK: lldb-server platform --server --listen tcp://localhost:5555 +CHECK: # Listen on Unix domain socket +CHECK: lldb-server platform --listen unix:///tmp/lldb-server.sock diff --git a/lldb/test/Shell/lldb-server/TestPlatformSuccessfulStartup.test b/lldb/test/Shell/lldb-server/TestPlatformSuccessfulStartup.test new file mode 100644 index 0000000000000..88a2384c31c34 --- /dev/null +++ b/lldb/test/Shell/lldb-server/TestPlatformSuccessfulStartup.test @@ -0,0 +1,35 @@ +# Test successful startup with valid TCP listen address +# The socket file is created immediately when the server is ready to accept connections, +# so we can verify successful startup without arbitrary sleep delays. +RUN: rm -f %t.socket1 +RUN: timeout 0.2s %platformserver --listen tcp://127.0.0.1:0 --socket-file %t.socket1 > %t.out1 2>&1 || true +RUN: test -f %t.socket1 +RUN: FileCheck --allow-empty --check-prefix=NO-ERROR %s < %t.out1 + +# Test successful startup with valid gdbserver-port +RUN: rm -f %t.socket3 +RUN: timeout 0.2s %platformserver --listen tcp://127.0.0.1:0 --gdbserver-port 0 --socket-file %t.socket3 > %t.out3 2>&1 || true +RUN: test -f %t.socket3 +RUN: FileCheck --allow-empty --check-prefix=NO-ERROR %s < %t.out3 + +# Test successful startup with specific valid gdbserver-port number +RUN: rm -f %t.socket4 +RUN: timeout 0.2s %platformserver --listen tcp://127.0.0.1:0 --gdbserver-port 12345 --socket-file %t.socket4 > %t.out4 2>&1 || true +RUN: test -f %t.socket4 +RUN: FileCheck --allow-empty --check-prefix=NO-ERROR %s < %t.out4 + +# Test successful startup with server mode (accepting multiple connections) +RUN: rm -f %t.socket5 +RUN: timeout 0.2s %platformserver --server --listen tcp://127.0.0.1:0 --socket-file %t.socket5 > %t.out5 2>&1 || true +RUN: test -f %t.socket5 +RUN: FileCheck --allow-empty --check-prefix=NO-ERROR %s < %t.out5 + +# Test successful startup with abbreviated 'p' command +RUN: rm -f %t.socket6 +RUN: timeout 0.2s %lldb-server p --listen tcp://127.0.0.1:0 --socket-file %t.socket6 > %t.out6 2>&1 || true +RUN: test -f %t.socket6 +RUN: FileCheck --allow-empty --check-prefix=NO-ERROR %s < %t.out6 + +# Verify no error or warning messages appear in successful startup +NO-ERROR-NOT: error: +NO-ERROR-NOT: warning: diff --git a/lldb/tools/lldb-server/CMakeLists.txt b/lldb/tools/lldb-server/CMakeLists.txt index 1d8dc72a3f872..fb55c64936121 100644 --- a/lldb/tools/lldb-server/CMakeLists.txt +++ b/lldb/tools/lldb-server/CMakeLists.txt @@ -2,6 +2,10 @@ set(LLVM_TARGET_DEFINITIONS LLGSOptions.td) tablegen(LLVM LLGSOptions.inc -gen-opt-parser-defs) add_public_tablegen_target(LLGSOptionsTableGen) +set(LLVM_TARGET_DEFINITIONS PlatformOptions.td) +tablegen(LLVM PlatformOptions.inc -gen-opt-parser-defs) +add_public_tablegen_target(PlatformOptionsTableGen) + set(LLDB_PLUGINS) if(CMAKE_SYSTEM_NAME MATCHES "Linux|Android") @@ -67,6 +71,7 @@ add_lldb_tool(lldb-server add_dependencies(lldb-server LLGSOptionsTableGen + PlatformOptionsTableGen ${tablegen_deps} ) target_include_directories(lldb-server PRIVATE "${LLDB_SOURCE_DIR}/source") diff --git a/lldb/tools/lldb-server/PlatformOptions.td b/lldb/tools/lldb-server/PlatformOptions.td new file mode 100644 index 0000000000000..eedd1d8c35343 --- /dev/null +++ b/lldb/tools/lldb-server/PlatformOptions.td @@ -0,0 +1,75 @@ +include "llvm/Option/OptParser.td" + +class F: Flag<["--", "-"], name>; +class R prefixes, string name> + : Option; + +multiclass SJ { + def NAME: Separate<["--", "-"], name>, + HelpText; + def NAME # _eq: Joined<["--", "-"], name # "=">, + Alias(NAME)>; +} + +def grp_connect : OptionGroup<"connection">, HelpText<"CONNECTION OPTIONS">; + +defm listen: SJ<"listen", "Host and port to listen on. Format: [host]:port or protocol://[host]:port (e.g., tcp://localhost:1234, unix:///path/to/socket). Short form: -L">, + MetaVarName<"<[host]:port>">, + Group; +def: Separate<["-"], "L">, Alias, + Group; + +defm socket_file: SJ<"socket-file", "Write listening socket information (port number for TCP or path for Unix domain sockets) to the specified file. Short form: -f">, + MetaVarName<"">, + Group; +def: Separate<["-"], "f">, Alias, + Group; + +defm gdbserver_port: SJ<"gdbserver-port", "Port to use for spawned gdbserver instances. If 0 or unspecified, a port will be chosen automatically. Short form: -P">, + MetaVarName<"">, + Group; +def: Separate<["-"], "P">, Alias, + Group; + +defm child_platform_fd: SJ<"child-platform-fd", "File descriptor for communication with parent platform process (internal use only).">, + MetaVarName<"">, + Group, + Flags<[HelpHidden]>; + +def grp_general : OptionGroup<"general options">, HelpText<"GENERAL OPTIONS">; + +def server: F<"server">, + HelpText<"Run in server mode, accepting multiple client connections sequentially. Without this flag, the server exits after handling the first connection.">, + Group; + +defm log_channels: SJ<"log-channels", "Channels to log. A colon-separated list of entries. Each entry starts with a channel followed by a space-separated list of categories. Common channels: lldb, gdb-remote, platform, process. Short form: -c">, + MetaVarName<"">, + Group; +def: Separate<["-"], "c">, Alias, + Group; + +defm log_file: SJ<"log-file", "Destination file to log to. If empty, log to stderr. Short form: -l">, + MetaVarName<"">, + Group; +def: Separate<["-"], "l">, Alias, + Group; + +def debug: F<"debug">, + HelpText<"(Unused, kept for backward compatibility)">, + Group, + Flags<[HelpHidden]>; + +def verbose: F<"verbose">, + HelpText<"(Unused, kept for backward compatibility)">, + Group, + Flags<[HelpHidden]>; + +def help: F<"help">, + HelpText<"Display this help message and exit.">, + Group; +def: Flag<["-"], "h">, Alias, + Group; + +def REM : R<["--"], "">, + HelpText<"Arguments to pass to launched gdbserver instances.">, + MetaVarName<"program args">; diff --git a/lldb/tools/lldb-server/lldb-platform.cpp b/lldb/tools/lldb-server/lldb-platform.cpp index 0bd928507ba89..59b1eb419bc2b 100644 --- a/lldb/tools/lldb-server/lldb-platform.cpp +++ b/lldb/tools/lldb-server/lldb-platform.cpp @@ -21,6 +21,9 @@ #include #include +#include "llvm/Option/ArgList.h" +#include "llvm/Option/OptTable.h" +#include "llvm/Option/Option.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/ScopedPrinter.h" #include "llvm/Support/WithColor.h" @@ -56,22 +59,69 @@ using namespace llvm; // of target CPUs. For now, let's just use 100. static const int backlog = 100; static const int socket_error = -1; -static int g_debug = 0; -static int g_verbose = 0; -static int g_server = 0; - -// option descriptors for getopt_long_only() -static struct option g_long_options[] = { - {"debug", no_argument, &g_debug, 1}, - {"verbose", no_argument, &g_verbose, 1}, - {"log-file", required_argument, nullptr, 'l'}, - {"log-channels", required_argument, nullptr, 'c'}, - {"listen", required_argument, nullptr, 'L'}, - {"gdbserver-port", required_argument, nullptr, 'P'}, - {"socket-file", required_argument, nullptr, 'f'}, - {"server", no_argument, &g_server, 1}, - {"child-platform-fd", required_argument, nullptr, 2}, - {nullptr, 0, nullptr, 0}}; + +namespace { +using namespace llvm::opt; + +enum ID { + OPT_INVALID = 0, // This is not an option ID. +#define OPTION(...) LLVM_MAKE_OPT_ID(__VA_ARGS__), +#include "PlatformOptions.inc" +#undef OPTION +}; + +#define OPTTABLE_STR_TABLE_CODE +#include "PlatformOptions.inc" +#undef OPTTABLE_STR_TABLE_CODE + +#define OPTTABLE_PREFIXES_TABLE_CODE +#include "PlatformOptions.inc" +#undef OPTTABLE_PREFIXES_TABLE_CODE + +static constexpr opt::OptTable::Info InfoTable[] = { +#define OPTION(...) LLVM_CONSTRUCT_OPT_INFO(__VA_ARGS__), +#include "PlatformOptions.inc" +#undef OPTION +}; + +class PlatformOptTable : public opt::GenericOptTable { +public: + PlatformOptTable() + : opt::GenericOptTable(OptionStrTable, OptionPrefixesTable, InfoTable) {} + + void PrintHelp(llvm::StringRef Name) { + std::string Usage = + (Name + " [options] --listen <[host]:port> [[--] program args...]") + .str(); + + std::string Title = "lldb-server platform"; + + OptTable::printHelp(llvm::outs(), Usage.c_str(), Title.c_str()); + + llvm::outs() << R"( +DESCRIPTION + Acts as a platform server for remote debugging. When LLDB clients connect, + the platform server handles platform operations (file transfers, process + launching) and spawns debug server instances (lldb-server gdbserver) to + handle actual debugging sessions. + + By default, the server exits after handling one connection. Use --server + to keep running and accept multiple connections sequentially. + +EXAMPLES + # Listen on port 1234, exit after first connection + lldb-server platform --listen tcp://0.0.0.0:1234 + + # Listen on port 5555, accept multiple connections + lldb-server platform --server --listen tcp://localhost:5555 + + # Listen on Unix domain socket + lldb-server platform --listen unix:///tmp/lldb-server.sock + +)"; + } +}; +} // namespace #if defined(__APPLE__) #define LOW_PORT (IPPORT_RESERVED) @@ -97,12 +147,11 @@ static void signal_handler(int signo) { } #endif -static void display_usage(const char *progname, const char *subcommand) { - fprintf(stderr, "Usage:\n %s %s [--log-file log-file-name] [--log-channels " - "log-channel-list] [--port-file port-file-path] --server " - "--listen port\n", - progname, subcommand); - exit(0); +static void display_usage(PlatformOptTable &Opts, const char *progname, + const char *subcommand) { + std::string Name = + (llvm::sys::path::filename(progname) + " " + subcommand).str(); + Opts.PrintHelp(Name); } static Status parse_listen_host_port(Socket::SocketProtocol &protocol, @@ -261,7 +310,8 @@ static Status spawn_process(const char *progname, const FileSpec &prog, const Socket *conn_socket, uint16_t gdb_port, const lldb_private::Args &args, const std::string &log_file, - const StringRef log_channels, MainLoop &main_loop) { + const StringRef log_channels, MainLoop &main_loop, + bool multi_client) { Status error; SharedSocket shared_socket(conn_socket, error); if (error.Fail()) @@ -297,9 +347,12 @@ static Status spawn_process(const char *progname, const FileSpec &prog, launch_info.SetLaunchInSeparateProcessGroup(false); - if (g_server) + // Set up process monitor callback based on whether we're in server mode. + if (multi_client) + // In server mode: empty callback (don't terminate when child exits). launch_info.SetMonitorProcessCallback([](lldb::pid_t, int, int) {}); else + // In single-client mode: terminate main loop when child exits. launch_info.SetMonitorProcessCallback([&main_loop](lldb::pid_t, int, int) { main_loop.AddPendingCallback( [](MainLoopBase &loop) { loop.RequestTermination(); }); @@ -371,107 +424,101 @@ int main_platform(int argc, char *argv[]) { signal(SIGPIPE, SIG_IGN); signal(SIGHUP, signal_handler); #endif - int long_option_index = 0; - Status error; - std::string listen_host_port; - int ch; - std::string log_file; - StringRef - log_channels; // e.g. "lldb process threads:gdb-remote default:linux all" + // Special handling for 'help' as first argument. + if (argc > 0 && strcmp(argv[0], "help") == 0) { + PlatformOptTable Opts; + display_usage(Opts, progname, subcommand); + return EXIT_SUCCESS; + } + Status error; shared_fd_t fd = SharedSocket::kInvalidFD; - uint16_t gdbserver_port = 0; - FileSpec socket_file; - bool show_usage = false; - int option_error = 0; - std::string short_options(OptionParser::GetShortOptionString(g_long_options)); + PlatformOptTable Opts; + BumpPtrAllocator Alloc; + StringSaver Saver(Alloc); + bool HasError = false; -#if __GLIBC__ - optind = 0; -#else - optreset = 1; - optind = 1; -#endif + opt::InputArgList Args = + Opts.parseArgs(argc, argv, OPT_UNKNOWN, Saver, [&](llvm::StringRef Msg) { + WithColor::error() << Msg << "\n"; + HasError = true; + }); - while ((ch = getopt_long_only(argc, argv, short_options.c_str(), - g_long_options, &long_option_index)) != -1) { - switch (ch) { - case 0: // Any optional that auto set themselves will return 0 - break; + std::string Name = + (llvm::sys::path::filename(progname) + " " + subcommand).str(); + std::string HelpText = + "Use '" + Name + " --help' for a complete list of options.\n"; - case 'L': - listen_host_port.append(optarg); - break; + if (HasError) { + llvm::errs() << HelpText; + return EXIT_FAILURE; + } - case 'l': // Set Log File - if (optarg && optarg[0]) - log_file.assign(optarg); - break; + if (Args.hasArg(OPT_help)) { + display_usage(Opts, progname, subcommand); + return EXIT_SUCCESS; + } - case 'c': // Log Channels - if (optarg && optarg[0]) - log_channels = StringRef(optarg); - break; + // Parse arguments. + std::string listen_host_port = Args.getLastArgValue(OPT_listen).str(); + std::string log_file = Args.getLastArgValue(OPT_log_file).str(); + StringRef log_channels = Args.getLastArgValue(OPT_log_channels); + bool multi_client = Args.hasArg(OPT_server); + [[maybe_unused]] bool debug = Args.hasArg(OPT_debug); + [[maybe_unused]] bool verbose = Args.hasArg(OPT_verbose); + + if (Args.hasArg(OPT_socket_file)) { + socket_file.SetFile(Args.getLastArgValue(OPT_socket_file), + FileSpec::Style::native); + } - case 'f': // Socket file - if (optarg && optarg[0]) - socket_file.SetFile(optarg, FileSpec::Style::native); - break; + if (Args.hasArg(OPT_gdbserver_port)) { + if (!llvm::to_integer(Args.getLastArgValue(OPT_gdbserver_port), + gdbserver_port)) { + WithColor::error() << "invalid --gdbserver-port value\n"; + return EXIT_FAILURE; + } + } - case 'P': - case 'm': - case 'M': { - uint16_t portnum; - if (!llvm::to_integer(optarg, portnum)) { - WithColor::error() << "invalid port number string " << optarg << "\n"; - option_error = 2; - break; - } - // Note the condition gdbserver_port > HIGH_PORT is valid in case of using - // --child-platform-fd. Check gdbserver_port later. - if (ch == 'P') - gdbserver_port = portnum; - else if (gdbserver_port == 0) - gdbserver_port = portnum; - } break; - - case 2: { - uint64_t _fd; - if (!llvm::to_integer(optarg, _fd)) { - WithColor::error() << "invalid fd " << optarg << "\n"; - option_error = 6; - } else - fd = (shared_fd_t)_fd; - } break; - - case 'h': /* fall-through is intentional */ - case '?': - show_usage = true; - break; + if (Args.hasArg(OPT_child_platform_fd)) { + uint64_t _fd; + if (!llvm::to_integer(Args.getLastArgValue(OPT_child_platform_fd), _fd)) { + WithColor::error() << "invalid --child-platform-fd value\n"; + return EXIT_FAILURE; } + fd = (shared_fd_t)_fd; } if (!LLDBServerUtilities::SetupLogging(log_file, log_channels, 0)) return -1; // Print usage and exit if no listening port is specified. - if (listen_host_port.empty() && fd == SharedSocket::kInvalidFD) - show_usage = true; + if (listen_host_port.empty() && fd == SharedSocket::kInvalidFD) { + WithColor::error() << "either --listen or --child-platform-fd is required\n" + << HelpText; + return EXIT_FAILURE; + } - if (show_usage || option_error) { - display_usage(progname, subcommand); - exit(option_error); + // Get remaining arguments for inferior. + std::vector Inputs; + for (opt::Arg *Arg : Args.filtered(OPT_INPUT)) + Inputs.push_back(Arg->getValue()); + if (opt::Arg *Arg = Args.getLastArg(OPT_REM)) { + for (const char *Val : Arg->getValues()) + Inputs.push_back(Val); } - // Skip any options we consumed with getopt_long_only. - argc -= optind; - argv += optind; lldb_private::Args inferior_arguments; - inferior_arguments.SetArguments(argc, const_cast(argv)); + if (!Inputs.empty()) { + std::vector args_ptrs; + for (const auto &Input : Inputs) + args_ptrs.push_back(Input.data()); + inferior_arguments.SetArguments(args_ptrs.size(), args_ptrs.data()); + } FileSpec debugserver_path = GetDebugserverPath(); if (!debugserver_path) { @@ -514,7 +561,7 @@ int main_platform(int argc, char *argv[]) { platform.SetConnection( std::make_unique(std::move(socket))); client_handle(platform, inferior_arguments); - return 0; + return EXIT_SUCCESS; } if (gdbserver_port != 0 && @@ -522,7 +569,7 @@ int main_platform(int argc, char *argv[]) { WithColor::error() << llvm::formatv("Port number {0} is not in the " "valid user port range of {1} - {2}\n", gdbserver_port, LOW_PORT, HIGH_PORT); - return 1; + return EXIT_FAILURE; } Socket::SocketProtocol protocol = Socket::ProtocolUnixDomain; @@ -559,7 +606,7 @@ int main_platform(int argc, char *argv[]) { if (error.Fail()) { fprintf(stderr, "failed to write socket id to %s: %s\n", socket_file.GetPath().c_str(), error.AsCString()); - return 1; + return EXIT_FAILURE; } } @@ -577,22 +624,22 @@ int main_platform(int argc, char *argv[]) { llvm::Expected> platform_handles = platform_sock->Accept( main_loop, [progname, gdbserver_port, &inferior_arguments, log_file, - log_channels, &main_loop, + log_channels, &main_loop, multi_client, &platform_handles](std::unique_ptr sock_up) { printf("Connection established.\n"); Status error = spawn_process( progname, HostInfo::GetProgramFileSpec(), sock_up.get(), gdbserver_port, inferior_arguments, log_file, log_channels, - main_loop); + main_loop, multi_client); if (error.Fail()) { Log *log = GetLog(LLDBLog::Platform); LLDB_LOGF(log, "spawn_process failed: %s", error.AsCString()); WithColor::error() << "spawn_process failed: " << error.AsCString() << "\n"; - if (!g_server) + if (!multi_client) main_loop.RequestTermination(); } - if (!g_server) + if (!multi_client) platform_handles->clear(); }); if (!platform_handles) { @@ -616,5 +663,5 @@ int main_platform(int argc, char *argv[]) { fprintf(stderr, "lldb-server exiting...\n"); - return 0; + return EXIT_SUCCESS; } From 536bd7214848a75594bb72ab01e02d13d54fb359 Mon Sep 17 00:00:00 2001 From: Erich Keane Date: Thu, 23 Oct 2025 08:09:32 -0700 Subject: [PATCH 08/31] [NFC] Rename 'Expr' to 'RefExpr' to fix the build warnings (#164828) I used 'expr' since that is what it is in the standard, but that obviously conflicts with our warnings on some build bots. This patch fixes that by renaming it. --- clang/include/clang/AST/StmtOpenACC.h | 4 +++- clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp | 2 +- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/clang/include/clang/AST/StmtOpenACC.h b/clang/include/clang/AST/StmtOpenACC.h index f5240251b67af..ae8029797a36e 100644 --- a/clang/include/clang/AST/StmtOpenACC.h +++ b/clang/include/clang/AST/StmtOpenACC.h @@ -821,7 +821,9 @@ class OpenACCAtomicConstruct final struct StmtInfo { const Expr *V; const Expr *X; - const Expr *Expr; + // Listed as 'expr' in the standard, this is typically a generic expression + // as a component. + const Expr *RefExpr; // TODO: OpenACC: We should expand this as we're implementing the other // atomic construct kinds. }; diff --git a/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp b/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp index b125330321afd..349b111c0d8fd 100644 --- a/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenStmtOpenACC.cpp @@ -346,7 +346,7 @@ CIRGenFunction::emitOpenACCAtomicConstruct(const OpenACCAtomicConstruct &s) { } case OpenACCAtomicKind::Write: { mlir::Value x = emitLValue(inf.X).getPointer(); - mlir::Value expr = emitAnyExpr(inf.Expr).getValue(); + mlir::Value expr = emitAnyExpr(inf.RefExpr).getValue(); auto op = mlir::acc::AtomicWriteOp::create(builder, start, x, expr, /*ifCond=*/{}); emitOpenACCClauses(op, s.getDirectiveKind(), s.getDirectiveLoc(), From 0ac4a715f55ed860268740ad5f5535161b6cb552 Mon Sep 17 00:00:00 2001 From: Jordan Rupprecht Date: Thu, 23 Oct 2025 10:16:48 -0500 Subject: [PATCH 09/31] [bazel][lldb] Port #162730: tablegen for lldb-server platform ops (#164832) --- utils/bazel/llvm-project-overlay/lldb/BUILD.bazel | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel b/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel index 7d62afc982be8..b892ac90668fe 100644 --- a/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/lldb/BUILD.bazel @@ -979,7 +979,7 @@ cc_binary( ) gentbl_cc_library( - name = "lldb_server_opts_gen", + name = "lldb_server_llgs_opts_gen", strip_include_prefix = ".", tbl_outs = {"LLGSOptions.inc": ["-gen-opt-parser-defs"]}, tblgen = "//llvm:llvm-tblgen", @@ -987,6 +987,15 @@ gentbl_cc_library( deps = ["//llvm:OptParserTdFiles"], ) +gentbl_cc_library( + name = "lldb_server_platform_opts_gen", + strip_include_prefix = ".", + tbl_outs = {"PlatformOptions.inc": ["-gen-opt-parser-defs"]}, + tblgen = "//llvm:llvm-tblgen", + td_file = "tools/lldb-server/PlatformOptions.td", + deps = ["//llvm:OptParserTdFiles"], +) + cc_binary( name = "lldb-server", srcs = glob([ @@ -1005,7 +1014,8 @@ cc_binary( ":Interpreter", ":Utility", ":Version", - ":lldb_server_opts_gen", + ":lldb_server_llgs_opts_gen", + ":lldb_server_platform_opts_gen", "//lldb:Target", "//lldb:TargetHeaders", "//lldb/source/Plugins:PluginCPlusPlusLanguage", From d130f402642fba3d065aacb506cb061c899558de Mon Sep 17 00:00:00 2001 From: Kees Cook Date: Thu, 23 Oct 2025 08:27:13 -0700 Subject: [PATCH 10/31] [ARM][KCFI] Add backend support for Kernel Control-Flow Integrity (#163698) Implement KCFI (Kernel Control Flow Integrity) backend support for ARM32, Thumb2, and Thumb1. The Linux kernel has supported ARM KCFI via Clang's generic KCFI implementation, but this has finally started to [cause problems](https://github.com/ClangBuiltLinux/linux/issues/2124) so it's time to get the KCFI operand bundle lowering working on ARM. Supports patchable-function-prefix with adjusted load offsets. Provides an instruction size worst case estimate of how large the KCFI bundle is so that range-limited instructions (e.g. cbz) know how big the indirect calls can become. ARM implementation notes: - Four-instruction EOR sequence builds the 32-bit type ID byte-by-byte to work within ARM's modified immediate encoding constraints. - Scratch register selection: r12 (IP) is preferred, r3 used as fallback when r12 holds the call target. r3 gets spilled/reloaded if it is being used as a call argument. - UDF trap encoding: 0x8000 | (0x1F << 5) | target_reg_index, similar to aarch64's trap encoding. Thumb2 implementation notes: - Logically the same as ARM - UDF trap encoding: 0x80 | target_reg_index Thumb1 implementation notes: - Due to register pressure, 2 scratch registers are needed: r3 and r2, which get spilled/reloaded if they are being used as call args. - Instead of EOR, add/lsl sequence to load immediate, followed by a compare. - No trap encoding. Update tests to validate all three sub targets. --- clang/lib/CodeGen/BackendUtil.cpp | 3 +- llvm/lib/Target/ARM/ARMAsmPrinter.cpp | 435 ++++++++++++++++++ llvm/lib/Target/ARM/ARMAsmPrinter.h | 11 + llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp | 2 + llvm/lib/Target/ARM/ARMISelLowering.cpp | 69 +++ llvm/lib/Target/ARM/ARMISelLowering.h | 6 + llvm/lib/Target/ARM/ARMInstrInfo.td | 30 ++ llvm/lib/Target/ARM/ARMTargetMachine.cpp | 12 +- llvm/test/CodeGen/ARM/O3-pipeline.ll | 1 + llvm/test/CodeGen/ARM/kcfi-arm.ll | 138 ++++++ llvm/test/CodeGen/ARM/kcfi-cbz-range.ll | 81 ++++ .../ARM/kcfi-patchable-function-prefix.ll | 99 ++++ llvm/test/CodeGen/ARM/kcfi-thumb.ll | 215 +++++++++ llvm/test/CodeGen/ARM/kcfi-thumb2.ll | 163 +++++++ llvm/test/CodeGen/ARM/kcfi.ll | 28 -- 15 files changed, 1262 insertions(+), 31 deletions(-) create mode 100644 llvm/test/CodeGen/ARM/kcfi-arm.ll create mode 100644 llvm/test/CodeGen/ARM/kcfi-cbz-range.ll create mode 100644 llvm/test/CodeGen/ARM/kcfi-patchable-function-prefix.ll create mode 100644 llvm/test/CodeGen/ARM/kcfi-thumb.ll create mode 100644 llvm/test/CodeGen/ARM/kcfi-thumb2.ll delete mode 100644 llvm/test/CodeGen/ARM/kcfi.ll diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index c423c4bebcac8..468c930acacbd 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -684,7 +684,8 @@ static void addKCFIPass(const Triple &TargetTriple, const LangOptions &LangOpts, PassBuilder &PB) { // If the back-end supports KCFI operand bundle lowering, skip KCFIPass. if (TargetTriple.getArch() == llvm::Triple::x86_64 || - TargetTriple.isAArch64(64) || TargetTriple.isRISCV()) + TargetTriple.isAArch64(64) || TargetTriple.isRISCV() || + TargetTriple.isARM() || TargetTriple.isThumb()) return; // Ensure we lower KCFI operand bundles with -O0. diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp index 3368a509661ae..8e35cadb75857 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.cpp +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.cpp @@ -1471,6 +1471,436 @@ void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) { // instructions) auto-generated. #include "ARMGenMCPseudoLowering.inc" +// Helper function to check if a register is live (used as an implicit operand) +// in the given call instruction. +static bool isRegisterLiveInCall(const MachineInstr &Call, MCRegister Reg) { + for (const MachineOperand &MO : Call.implicit_operands()) { + if (MO.isReg() && MO.getReg() == Reg && MO.isUse()) { + return true; + } + } + return false; +} + +void ARMAsmPrinter::EmitKCFI_CHECK_ARM32(Register AddrReg, int64_t Type, + const MachineInstr &Call, + int64_t PrefixNops) { + // Choose scratch register: r12 primary, r3 if target is r12. + unsigned ScratchReg = ARM::R12; + if (AddrReg == ARM::R12) { + ScratchReg = ARM::R3; + } + + // Calculate ESR for ARM mode (16-bit): 0x8000 | (scratch_reg << 5) | addr_reg + // Note: scratch_reg is always 0x1F since the EOR sequence clobbers it. + const ARMBaseRegisterInfo *TRI = static_cast( + MF->getSubtarget().getRegisterInfo()); + unsigned AddrIndex = TRI->getEncodingValue(AddrReg); + unsigned ESR = 0x8000 | (31 << 5) | (AddrIndex & 31); + + // Check if r3 is live and needs to be spilled. + bool NeedSpillR3 = + (ScratchReg == ARM::R3) && isRegisterLiveInCall(Call, ARM::R3); + + // If we need to spill r3, push it first. + if (NeedSpillR3) { + // push {r3} + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STMDB_UPD) + .addReg(ARM::SP) + .addReg(ARM::SP) + .addImm(ARMCC::AL) + .addReg(0) + .addReg(ARM::R3)); + } + + // Clear bit 0 of target address to handle Thumb function pointers. + // In 32-bit ARM, function pointers may have the low bit set to indicate + // Thumb state when ARM/Thumb interworking is enabled (ARMv4T and later). + // We need to clear it to avoid an alignment fault when loading. + // bic scratch, target, #1 + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BICri) + .addReg(ScratchReg) + .addReg(AddrReg) + .addImm(1) + .addImm(ARMCC::AL) + .addReg(0) + .addReg(0)); + + // ldr scratch, [scratch, #-(PrefixNops * 4 + 4)] + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12) + .addReg(ScratchReg) + .addReg(ScratchReg) + .addImm(-(PrefixNops * 4 + 4)) + .addImm(ARMCC::AL) + .addReg(0)); + + // Each EOR instruction XORs one byte of the type, shifted to its position. + for (int i = 0; i < 4; i++) { + uint8_t byte = (Type >> (i * 8)) & 0xFF; + uint32_t imm = byte << (i * 8); + bool isLast = (i == 3); + + // Encode as ARM modified immediate. + int SOImmVal = ARM_AM::getSOImmVal(imm); + assert(SOImmVal != -1 && + "Cannot encode immediate as ARM modified immediate"); + + // eor[s] scratch, scratch, #imm (last one sets flags with CPSR) + EmitToStreamer(*OutStreamer, + MCInstBuilder(ARM::EORri) + .addReg(ScratchReg) + .addReg(ScratchReg) + .addImm(SOImmVal) + .addImm(ARMCC::AL) + .addReg(0) + .addReg(isLast ? ARM::CPSR : ARM::NoRegister)); + } + + // If we spilled r3, restore it immediately after the comparison. + // This must happen before the branch so r3 is valid on both paths. + if (NeedSpillR3) { + // pop {r3} + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDMIA_UPD) + .addReg(ARM::SP) + .addReg(ARM::SP) + .addImm(ARMCC::AL) + .addReg(0) + .addReg(ARM::R3)); + } + + // beq .Lpass (branch if types match, i.e., scratch is zero) + MCSymbol *Pass = OutContext.createTempSymbol(); + EmitToStreamer(*OutStreamer, + MCInstBuilder(ARM::Bcc) + .addExpr(MCSymbolRefExpr::create(Pass, OutContext)) + .addImm(ARMCC::EQ) + .addReg(ARM::CPSR)); + + // udf #ESR (trap with encoded diagnostic) + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::UDF).addImm(ESR)); + + OutStreamer->emitLabel(Pass); +} + +void ARMAsmPrinter::EmitKCFI_CHECK_Thumb2(Register AddrReg, int64_t Type, + const MachineInstr &Call, + int64_t PrefixNops) { + // Choose scratch register: r12 primary, r3 if target is r12. + unsigned ScratchReg = ARM::R12; + if (AddrReg == ARM::R12) { + ScratchReg = ARM::R3; + } + + // Calculate ESR for Thumb mode (8-bit): 0x80 | addr_reg + // Bit 7: KCFI trap indicator + // Bits 6-5: Reserved + // Bits 4-0: Address register encoding + const ARMBaseRegisterInfo *TRI = static_cast( + MF->getSubtarget().getRegisterInfo()); + unsigned AddrIndex = TRI->getEncodingValue(AddrReg); + unsigned ESR = 0x80 | (AddrIndex & 0x1F); + + // Check if r3 is live and needs to be spilled. + bool NeedSpillR3 = + (ScratchReg == ARM::R3) && isRegisterLiveInCall(Call, ARM::R3); + + // If we need to spill r3, push it first. + if (NeedSpillR3) { + // push {r3} + EmitToStreamer( + *OutStreamer, + MCInstBuilder(ARM::tPUSH).addImm(ARMCC::AL).addReg(0).addReg(ARM::R3)); + } + + // Clear bit 0 of target address to handle Thumb function pointers. + // In 32-bit ARM, function pointers may have the low bit set to indicate + // Thumb state when ARM/Thumb interworking is enabled (ARMv4T and later). + // We need to clear it to avoid an alignment fault when loading. + // bic scratch, target, #1 + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2BICri) + .addReg(ScratchReg) + .addReg(AddrReg) + .addImm(1) + .addImm(ARMCC::AL) + .addReg(0) + .addReg(0)); + + // ldr scratch, [scratch, #-(PrefixNops * 4 + 4)] + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi8) + .addReg(ScratchReg) + .addReg(ScratchReg) + .addImm(-(PrefixNops * 4 + 4)) + .addImm(ARMCC::AL) + .addReg(0)); + + // Each EOR instruction XORs one byte of the type, shifted to its position. + for (int i = 0; i < 4; i++) { + uint8_t byte = (Type >> (i * 8)) & 0xFF; + uint32_t imm = byte << (i * 8); + bool isLast = (i == 3); + + // Verify the immediate can be encoded as Thumb2 modified immediate. + int T2SOImmVal = ARM_AM::getT2SOImmVal(imm); + assert(T2SOImmVal != -1 && + "Cannot encode immediate as Thumb2 modified immediate"); + + // eor[s] scratch, scratch, #imm (last one sets flags with CPSR) + EmitToStreamer(*OutStreamer, + MCInstBuilder(ARM::t2EORri) + .addReg(ScratchReg) + .addReg(ScratchReg) + .addImm(imm) + .addImm(ARMCC::AL) + .addReg(0) + .addReg(isLast ? ARM::CPSR : ARM::NoRegister)); + } + + // If we spilled r3, restore it immediately after the comparison. + // This must happen before the branch so r3 is valid on both paths. + if (NeedSpillR3) { + // pop {r3} + EmitToStreamer( + *OutStreamer, + MCInstBuilder(ARM::tPOP).addImm(ARMCC::AL).addReg(0).addReg(ARM::R3)); + } + + // beq .Lpass (branch if types match, i.e., scratch is zero) + MCSymbol *Pass = OutContext.createTempSymbol(); + EmitToStreamer(*OutStreamer, + MCInstBuilder(ARM::t2Bcc) + .addExpr(MCSymbolRefExpr::create(Pass, OutContext)) + .addImm(ARMCC::EQ) + .addReg(ARM::CPSR)); + + // udf #ESR (trap with encoded diagnostic) + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tUDF).addImm(ESR)); + + OutStreamer->emitLabel(Pass); +} + +void ARMAsmPrinter::EmitKCFI_CHECK_Thumb1(Register AddrReg, int64_t Type, + const MachineInstr &Call, + int64_t PrefixNops) { + // For Thumb1, use R2 unconditionally as scratch register (a low register + // required for tLDRi). R3 is used for building the type hash. + unsigned ScratchReg = ARM::R2; + unsigned TempReg = ARM::R3; + + // Check if r3 is live and needs to be spilled. + bool NeedSpillR3 = isRegisterLiveInCall(Call, ARM::R3); + + // Spill r3 if needed + if (NeedSpillR3) { + EmitToStreamer( + *OutStreamer, + MCInstBuilder(ARM::tPUSH).addImm(ARMCC::AL).addReg(0).addReg(ARM::R3)); + } + + // Check if r2 is live and needs to be spilled. + bool NeedSpillR2 = isRegisterLiveInCall(Call, ARM::R2); + + // Push R2 if it's live + if (NeedSpillR2) { + EmitToStreamer( + *OutStreamer, + MCInstBuilder(ARM::tPUSH).addImm(ARMCC::AL).addReg(0).addReg(ARM::R2)); + } + + // Clear bit 0 from target address + // TempReg (R3) is used first as helper for BIC, then later for building type + // hash. + + // movs temp, #1 + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8) + .addReg(TempReg) + .addReg(ARM::CPSR) + .addImm(1) + .addImm(ARMCC::AL) + .addReg(0)); + + // mov scratch, target + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr) + .addReg(ScratchReg) + .addReg(AddrReg) + .addImm(ARMCC::AL)); + + // bics scratch, temp (scratch = scratch & ~temp) + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBIC) + .addReg(ScratchReg) + .addReg(ARM::CPSR) + .addReg(ScratchReg) + .addReg(TempReg) + .addImm(ARMCC::AL) + .addReg(0)); + + // Load type hash. Thumb1 doesn't support negative offsets, so subtract. + int offset = PrefixNops * 4 + 4; + + // subs scratch, #offset + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSUBi8) + .addReg(ScratchReg) + .addReg(ARM::CPSR) + .addReg(ScratchReg) + .addImm(offset) + .addImm(ARMCC::AL) + .addReg(0)); + + // ldr scratch, [scratch, #0] + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi) + .addReg(ScratchReg) + .addReg(ScratchReg) + .addImm(0) + .addImm(ARMCC::AL) + .addReg(0)); + + // Load expected type inline (instead of EOR sequence) + // + // This creates the 32-bit value byte-by-byte in the temp register: + // movs temp, #byte3 (high byte) + // lsls temp, temp, #8 + // adds temp, #byte2 + // lsls temp, temp, #8 + // adds temp, #byte1 + // lsls temp, temp, #8 + // adds temp, #byte0 (low byte) + + uint8_t byte0 = (Type >> 0) & 0xFF; + uint8_t byte1 = (Type >> 8) & 0xFF; + uint8_t byte2 = (Type >> 16) & 0xFF; + uint8_t byte3 = (Type >> 24) & 0xFF; + + // movs temp, #byte3 (start with high byte) + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8) + .addReg(TempReg) + .addReg(ARM::CPSR) + .addImm(byte3) + .addImm(ARMCC::AL) + .addReg(0)); + + // lsls temp, temp, #8 + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) + .addReg(TempReg) + .addReg(ARM::CPSR) + .addReg(TempReg) + .addImm(8) + .addImm(ARMCC::AL) + .addReg(0)); + + // adds temp, #byte2 + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi8) + .addReg(TempReg) + .addReg(ARM::CPSR) + .addReg(TempReg) + .addImm(byte2) + .addImm(ARMCC::AL) + .addReg(0)); + + // lsls temp, temp, #8 + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) + .addReg(TempReg) + .addReg(ARM::CPSR) + .addReg(TempReg) + .addImm(8) + .addImm(ARMCC::AL) + .addReg(0)); + + // adds temp, #byte1 + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi8) + .addReg(TempReg) + .addReg(ARM::CPSR) + .addReg(TempReg) + .addImm(byte1) + .addImm(ARMCC::AL) + .addReg(0)); + + // lsls temp, temp, #8 + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri) + .addReg(TempReg) + .addReg(ARM::CPSR) + .addReg(TempReg) + .addImm(8) + .addImm(ARMCC::AL) + .addReg(0)); + + // adds temp, #byte0 (low byte) + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi8) + .addReg(TempReg) + .addReg(ARM::CPSR) + .addReg(TempReg) + .addImm(byte0) + .addImm(ARMCC::AL) + .addReg(0)); + + // cmp scratch, temp + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tCMPr) + .addReg(ScratchReg) + .addReg(TempReg) + .addImm(ARMCC::AL) + .addReg(0)); + + // Restore registers if spilled (pop in reverse order of push: R2, then R3) + if (NeedSpillR2) { + // pop {r2} + EmitToStreamer( + *OutStreamer, + MCInstBuilder(ARM::tPOP).addImm(ARMCC::AL).addReg(0).addReg(ARM::R2)); + } + + // Restore r3 if spilled + if (NeedSpillR3) { + // pop {r3} + EmitToStreamer( + *OutStreamer, + MCInstBuilder(ARM::tPOP).addImm(ARMCC::AL).addReg(0).addReg(ARM::R3)); + } + + // beq .Lpass (branch if types match, i.e., scratch == temp) + MCSymbol *Pass = OutContext.createTempSymbol(); + EmitToStreamer(*OutStreamer, + MCInstBuilder(ARM::tBcc) + .addExpr(MCSymbolRefExpr::create(Pass, OutContext)) + .addImm(ARMCC::EQ) + .addReg(ARM::CPSR)); + + // bkpt #0 (trap with encoded diagnostic) + EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBKPT).addImm(0)); + + OutStreamer->emitLabel(Pass); +} + +void ARMAsmPrinter::LowerKCFI_CHECK(const MachineInstr &MI) { + Register AddrReg = MI.getOperand(0).getReg(); + const int64_t Type = MI.getOperand(1).getImm(); + + // Get the call instruction that follows this KCFI_CHECK. + assert(std::next(MI.getIterator())->isCall() && + "KCFI_CHECK not followed by a call instruction"); + const MachineInstr &Call = *std::next(MI.getIterator()); + + // Adjust the offset for patchable-function-prefix. + int64_t PrefixNops = 0; + MI.getMF() + ->getFunction() + .getFnAttribute("patchable-function-prefix") + .getValueAsString() + .getAsInteger(10, PrefixNops); + + // Emit the appropriate instruction sequence based on the opcode variant. + switch (MI.getOpcode()) { + case ARM::KCFI_CHECK_ARM: + EmitKCFI_CHECK_ARM32(AddrReg, Type, Call, PrefixNops); + break; + case ARM::KCFI_CHECK_Thumb2: + EmitKCFI_CHECK_Thumb2(AddrReg, Type, Call, PrefixNops); + break; + case ARM::KCFI_CHECK_Thumb1: + EmitKCFI_CHECK_Thumb1(AddrReg, Type, Call, PrefixNops); + break; + default: + llvm_unreachable("Unexpected KCFI_CHECK opcode"); + } +} + void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) { ARM_MC::verifyInstructionPredicates(MI->getOpcode(), getSubtargetInfo().getFeatureBits()); @@ -1504,6 +1934,11 @@ void ARMAsmPrinter::emitInstruction(const MachineInstr *MI) { switch (Opc) { case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass"); case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing"); + case ARM::KCFI_CHECK_ARM: + case ARM::KCFI_CHECK_Thumb2: + case ARM::KCFI_CHECK_Thumb1: + LowerKCFI_CHECK(*MI); + return; case ARM::LEApcrel: case ARM::tLEApcrel: case ARM::t2LEApcrel: { diff --git a/llvm/lib/Target/ARM/ARMAsmPrinter.h b/llvm/lib/Target/ARM/ARMAsmPrinter.h index 2b067c753264f..9e92b5a36a672 100644 --- a/llvm/lib/Target/ARM/ARMAsmPrinter.h +++ b/llvm/lib/Target/ARM/ARMAsmPrinter.h @@ -123,9 +123,20 @@ class LLVM_LIBRARY_VISIBILITY ARMAsmPrinter : public AsmPrinter { void LowerPATCHABLE_FUNCTION_EXIT(const MachineInstr &MI); void LowerPATCHABLE_TAIL_CALL(const MachineInstr &MI); + // KCFI check lowering + void LowerKCFI_CHECK(const MachineInstr &MI); + private: void EmitSled(const MachineInstr &MI, SledKind Kind); + // KCFI check emission helpers + void EmitKCFI_CHECK_ARM32(Register AddrReg, int64_t Type, + const MachineInstr &Call, int64_t PrefixNops); + void EmitKCFI_CHECK_Thumb2(Register AddrReg, int64_t Type, + const MachineInstr &Call, int64_t PrefixNops); + void EmitKCFI_CHECK_Thumb1(Register AddrReg, int64_t Type, + const MachineInstr &Call, int64_t PrefixNops); + // Helpers for emitStartOfAsmFile() and emitEndOfAsmFile() void emitAttributes(); diff --git a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 0d7b6d1236442..fffb63738166d 100644 --- a/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -2301,6 +2301,8 @@ bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i) NewMI->addOperand(MBBI->getOperand(i)); + NewMI->setCFIType(*MBB.getParent(), MI.getCFIType()); + // Update call info and delete the pseudo instruction TCRETURN. if (MI.isCandidateForAdditionalCallInfo()) MI.getMF()->moveAdditionalCallInfo(&MI, &*NewMI); diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index b1a668eef608f..8122db27a9f67 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -2849,6 +2849,8 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, if (isTailCall) { MF.getFrameInfo().setHasTailCall(); SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, MVT::Other, Ops); + if (CLI.CFIType) + Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue()); DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge); DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); return Ret; @@ -2856,6 +2858,8 @@ ARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI, // Returns a chain and a flag for retval copy to use. Chain = DAG.getNode(CallOpc, dl, {MVT::Other, MVT::Glue}, Ops); + if (CLI.CFIType) + Chain.getNode()->setCFIType(CLI.CFIType->getZExtValue()); DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); InGlue = Chain.getValue(1); DAG.addCallSiteInfo(Chain.getNode(), std::move(CSInfo)); @@ -12008,6 +12012,71 @@ static void genTPLoopBody(MachineBasicBlock *TpLoopBody, .add(predOps(ARMCC::AL)); } +bool ARMTargetLowering::supportKCFIBundles() const { + // KCFI is supported in all ARM/Thumb modes + return true; +} + +MachineInstr * +ARMTargetLowering::EmitKCFICheck(MachineBasicBlock &MBB, + MachineBasicBlock::instr_iterator &MBBI, + const TargetInstrInfo *TII) const { + assert(MBBI->isCall() && MBBI->getCFIType() && + "Invalid call instruction for a KCFI check"); + + MachineOperand *TargetOp = nullptr; + switch (MBBI->getOpcode()) { + // ARM mode opcodes + case ARM::BLX: + case ARM::BLX_pred: + case ARM::BLX_noip: + case ARM::BLX_pred_noip: + case ARM::BX_CALL: + TargetOp = &MBBI->getOperand(0); + break; + case ARM::TCRETURNri: + case ARM::TCRETURNrinotr12: + case ARM::TAILJMPr: + case ARM::TAILJMPr4: + TargetOp = &MBBI->getOperand(0); + break; + // Thumb mode opcodes (Thumb1 and Thumb2) + // Note: Most Thumb call instructions have predicate operands before the + // target register Format: tBLXr pred, predreg, target_register, ... + case ARM::tBLXr: // Thumb1/Thumb2: BLX register (requires V5T) + case ARM::tBLXr_noip: // Thumb1/Thumb2: BLX register, no IP clobber + case ARM::tBX_CALL: // Thumb1 only: BX call (push LR, BX) + TargetOp = &MBBI->getOperand(2); + break; + // Tail call instructions don't have predicates, target is operand 0 + case ARM::tTAILJMPr: // Thumb1/Thumb2: Tail call via register + TargetOp = &MBBI->getOperand(0); + break; + default: + llvm_unreachable("Unexpected CFI call opcode"); + } + + assert(TargetOp && TargetOp->isReg() && "Invalid target operand"); + TargetOp->setIsRenamable(false); + + // Select the appropriate KCFI_CHECK variant based on the instruction set + unsigned KCFICheckOpcode; + if (Subtarget->isThumb()) { + if (Subtarget->isThumb2()) { + KCFICheckOpcode = ARM::KCFI_CHECK_Thumb2; + } else { + KCFICheckOpcode = ARM::KCFI_CHECK_Thumb1; + } + } else { + KCFICheckOpcode = ARM::KCFI_CHECK_ARM; + } + + return BuildMI(MBB, MBBI, MBBI->getDebugLoc(), TII->get(KCFICheckOpcode)) + .addReg(TargetOp->getReg()) + .addImm(MBBI->getCFIType()) + .getInstr(); +} + MachineBasicBlock * ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, MachineBasicBlock *BB) const { diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h index 70aa001a41885..8c5e0cfbfda1b 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.h +++ b/llvm/lib/Target/ARM/ARMISelLowering.h @@ -447,6 +447,12 @@ class VectorType; void AdjustInstrPostInstrSelection(MachineInstr &MI, SDNode *Node) const override; + bool supportKCFIBundles() const override; + + MachineInstr *EmitKCFICheck(MachineBasicBlock &MBB, + MachineBasicBlock::instr_iterator &MBBI, + const TargetInstrInfo *TII) const override; + SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const; SDValue PerformBRCONDCombine(SDNode *N, SelectionDAG &DAG) const; SDValue PerformCMOVToBFICombine(SDNode *N, SelectionDAG &DAG) const; diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 282ff534fc112..53be1677b96e3 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -6535,6 +6535,36 @@ def CMP_SWAP_64 : PseudoInst<(outs GPRPair:$Rd, GPRPair:$addr_temp_out), def : Pat<(atomic_fence (timm), 0), (MEMBARRIER)>; +//===----------------------------------------------------------------------===// +// KCFI check pseudo-instruction. +//===----------------------------------------------------------------------===// +// KCFI_CHECK pseudo-instruction for Kernel Control-Flow Integrity. +// Expands to a sequence that verifies the function pointer's type hash. +// Different sizes for different architectures due to different expansions. + +def KCFI_CHECK_ARM + : PseudoInst<(outs), (ins GPR:$ptr, i32imm:$type), NoItinerary, []>, + Sched<[]>, + Requires<[IsARM]> { + let Size = 28; // 7 instructions (bic, ldr, 4x eor, beq, udf) +} + +def KCFI_CHECK_Thumb2 + : PseudoInst<(outs), (ins GPR:$ptr, i32imm:$type), NoItinerary, []>, + Sched<[]>, + Requires<[IsThumb2]> { + let Size = + 32; // worst-case 9 instructions (push, bic, ldr, 4x eor, pop, beq.w, udf) +} + +def KCFI_CHECK_Thumb1 + : PseudoInst<(outs), (ins GPR:$ptr, i32imm:$type), NoItinerary, []>, + Sched<[]>, + Requires<[IsThumb1Only]> { + let Size = 50; // worst-case 25 instructions (pushes, bic helper, type + // building, cmp, pops) +} + //===----------------------------------------------------------------------===// // Instructions used for emitting unwind opcodes on Windows. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index 86740a92b32c5..590d4c70592f8 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -111,6 +111,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() { initializeMVELaneInterleavingPass(Registry); initializeARMFixCortexA57AES1742098Pass(Registry); initializeARMDAGToDAGISelLegacyPass(Registry); + initializeKCFIPass(Registry); } static std::unique_ptr createTLOF(const Triple &TT) { @@ -487,6 +488,9 @@ void ARMPassConfig::addPreSched2() { // proper scheduling. addPass(createARMExpandPseudoPass()); + // Emit KCFI checks for indirect calls. + addPass(createKCFIPass()); + if (getOptLevel() != CodeGenOptLevel::None) { // When optimising for size, always run the Thumb2SizeReduction pass before // IfConversion. Otherwise, check whether IT blocks are restricted @@ -517,9 +521,12 @@ void ARMPassConfig::addPreSched2() { void ARMPassConfig::addPreEmitPass() { addPass(createThumb2SizeReductionPass()); - // Constant island pass work on unbundled instructions. + // Unpack bundles for: + // - Thumb2: Constant island pass requires unbundled instructions + // - KCFI: KCFI_CHECK pseudo instructions need to be unbundled for AsmPrinter addPass(createUnpackMachineBundles([](const MachineFunction &MF) { - return MF.getSubtarget().isThumb2(); + return MF.getSubtarget().isThumb2() || + MF.getFunction().getParent()->getModuleFlag("kcfi"); })); // Don't optimize barriers or block placement at -O0. @@ -530,6 +537,7 @@ void ARMPassConfig::addPreEmitPass() { } void ARMPassConfig::addPreEmitPass2() { + // Inserts fixup instructions before unsafe AES operations. Instructions may // be inserted at the start of blocks and at within blocks so this pass has to // come before those below. diff --git a/llvm/test/CodeGen/ARM/O3-pipeline.ll b/llvm/test/CodeGen/ARM/O3-pipeline.ll index 9601a2e4e3d12..273114822ec44 100644 --- a/llvm/test/CodeGen/ARM/O3-pipeline.ll +++ b/llvm/test/CodeGen/ARM/O3-pipeline.ll @@ -166,6 +166,7 @@ ; CHECK-NEXT: ARM Execution Domain Fix ; CHECK-NEXT: BreakFalseDeps ; CHECK-NEXT: ARM pseudo instruction expansion pass +; CHECK-NEXT: Insert KCFI indirect call checks ; CHECK-NEXT: Thumb2 instruction size reduce pass ; CHECK-NEXT: MachineDominator Tree Construction ; CHECK-NEXT: Machine Natural Loop Construction diff --git a/llvm/test/CodeGen/ARM/kcfi-arm.ll b/llvm/test/CodeGen/ARM/kcfi-arm.ll new file mode 100644 index 0000000000000..e3696cf8ea4ea --- /dev/null +++ b/llvm/test/CodeGen/ARM/kcfi-arm.ll @@ -0,0 +1,138 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=ASM +; RUN: llc -mtriple=armv7-linux-gnueabi -verify-machineinstrs -stop-after=finalize-isel < %s | FileCheck %s --check-prefixes=MIR,ISEL +; RUN: llc -mtriple=armv7-linux-gnueabi -verify-machineinstrs -stop-after=kcfi < %s | FileCheck %s --check-prefixes=MIR,KCFI + +; MIR checks for all functions (grouped here to prevent update_llc_test_checks.py from removing them) + +; MIR-LABEL: name: f1 +; MIR: body: + +; ISEL: BLX %0, csr_aapcs,{{.*}} cfi-type 12345678 + +; KCFI: BUNDLE{{.*}} { +; KCFI-NEXT: KCFI_CHECK_ARM $r0, 12345678 +; KCFI-NEXT: BLX killed $r0, csr_aapcs,{{.*}} +; KCFI-NEXT: } + +; MIR-LABEL: name: f2 +; MIR: body: + +; ISEL: TCRETURNri %0, 0, csr_aapcs, implicit $sp, cfi-type 12345678 + +; KCFI: BUNDLE{{.*}} { +; KCFI-NEXT: KCFI_CHECK_ARM $r0, 12345678 +; KCFI-NEXT: TAILJMPr killed $r0, csr_aapcs, implicit $sp, implicit $sp +; KCFI-NEXT: } + +; ASM: .long 12345678 +define void @f1(ptr noundef %x) !kcfi_type !1 { +; ASM-LABEL: f1: +; ASM: @ %bb.0: +; ASM-NEXT: .save {r11, lr} +; ASM-NEXT: push {r11, lr} +; ASM-NEXT: bic r12, r0, #1 +; ASM-NEXT: ldr r12, [r12, #-4] +; ASM-NEXT: eor r12, r12, #78 +; ASM-NEXT: eor r12, r12, #24832 +; ASM-NEXT: eor r12, r12, #12320768 +; ASM-NEXT: eors r12, r12, #0 +; ASM-NEXT: beq .Ltmp0 +; ASM-NEXT: udf #33760 +; ASM-NEXT: .Ltmp0: +; ASM-NEXT: blx r0 +; ASM-NEXT: pop {r11, pc} + + call void %x() [ "kcfi"(i32 12345678) ] + ret void +} + +; Test with tail call +define void @f2(ptr noundef %x) !kcfi_type !1 { +; ASM-LABEL: f2: +; ASM: @ %bb.0: +; ASM-NEXT: bic r12, r0, #1 +; ASM-NEXT: ldr r12, [r12, #-4] +; ASM-NEXT: eor r12, r12, #78 +; ASM-NEXT: eor r12, r12, #24832 +; ASM-NEXT: eor r12, r12, #12320768 +; ASM-NEXT: eors r12, r12, #0 +; ASM-NEXT: beq .Ltmp1 +; ASM-NEXT: udf #33760 +; ASM-NEXT: .Ltmp1: +; ASM-NEXT: bx r0 + + tail call void %x() [ "kcfi"(i32 12345678) ] + ret void +} + +; Test r3 spill/reload when target is r12 and r3 is a call argument. +; With 5+ arguments (target + 4 args), r0-r3 are all used for arguments, +; forcing r3 to be spilled when we need it as scratch register. +define void @f3_r3_spill(ptr noundef %target, i32 %a, i32 %b, i32 %c, i32 %d) !kcfi_type !1 { +; ASM-LABEL: f3_r3_spill: +; ASM: @ %bb.0: +; ASM-NEXT: .save {r11, lr} +; ASM-NEXT: push {r11, lr} +; ASM-NEXT: mov lr, r3 +; ASM-NEXT: ldr r3, [sp, #8] +; ASM-NEXT: mov r12, r0 +; ASM-NEXT: mov r0, r1 +; ASM-NEXT: mov r1, r2 +; ASM-NEXT: mov r2, lr +; ASM-NEXT: stmdb sp!, {r3} +; ASM-NEXT: bic r3, r12, #1 +; ASM-NEXT: ldr r3, [r3, #-4] +; ASM-NEXT: eor r3, r3, #78 +; ASM-NEXT: eor r3, r3, #24832 +; ASM-NEXT: eor r3, r3, #12320768 +; ASM-NEXT: eors r3, r3, #0 +; ASM-NEXT: ldm sp!, {r3} +; ASM-NEXT: beq .Ltmp2 +; ASM-NEXT: udf #33772 +; ASM-NEXT: .Ltmp2: +; ASM-NEXT: blx r12 +; ASM-NEXT: pop {r11, pc} +; Arguments: r0=%target, r1=%a, r2=%b, r3=%c, [sp]=%d +; Call needs: r0=%a, r1=%b, r2=%c, r3=%d, target in r12 +; Compiler shuffles arguments into place, saving r3 (c) in lr, loading d from stack +; r3 is live as 4th argument, so push it before KCFI check +; Restore r3 immediately after comparison, before branch + call void %target(i32 %a, i32 %b, i32 %c, i32 %d) [ "kcfi"(i32 12345678) ] + ret void +} + +; Test with 3 arguments - r3 not live, target in r12, so r3 used as scratch without spilling +define void @f4_r3_unused(ptr noundef %target, i32 %a, i32 %b) !kcfi_type !1 { +; ASM-LABEL: f4_r3_unused: +; ASM: @ %bb.0: +; ASM-NEXT: .save {r11, lr} +; ASM-NEXT: push {r11, lr} +; ASM-NEXT: mov r3, r0 +; ASM-NEXT: mov r0, r1 +; ASM-NEXT: mov r1, r2 +; ASM-NEXT: bic r12, r3, #1 +; ASM-NEXT: ldr r12, [r12, #-4] +; ASM-NEXT: eor r12, r12, #78 +; ASM-NEXT: eor r12, r12, #24832 +; ASM-NEXT: eor r12, r12, #12320768 +; ASM-NEXT: eors r12, r12, #0 +; ASM-NEXT: beq .Ltmp3 +; ASM-NEXT: udf #33763 +; ASM-NEXT: .Ltmp3: +; ASM-NEXT: blx r3 +; ASM-NEXT: pop {r11, pc} +; Only 3 arguments total, so r3 is not used as call argument +; Compiler puts target→r3, a→r0, b→r1 +; r3 is the target, so we use r12 as scratch (no spill needed) + call void %target(i32 %a, i32 %b) [ "kcfi"(i32 12345678) ] + ret void +} + +!llvm.module.flags = !{!0} +!0 = !{i32 4, !"kcfi", i32 1} +!1 = !{i32 12345678} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; ISEL: {{.*}} +; KCFI: {{.*}} +; MIR: {{.*}} diff --git a/llvm/test/CodeGen/ARM/kcfi-cbz-range.ll b/llvm/test/CodeGen/ARM/kcfi-cbz-range.ll new file mode 100644 index 0000000000000..8e71cae3131d4 --- /dev/null +++ b/llvm/test/CodeGen/ARM/kcfi-cbz-range.ll @@ -0,0 +1,81 @@ +; RUN: llc -mtriple=thumbv7-linux-gnueabi -filetype=obj < %s +; RUN: llc -mtriple=thumbv7-linux-gnueabi < %s | FileCheck %s + +; This test verifies that KCFI instrumentation doesn't cause "out of range +; pc-relative fixup value" errors when generating object files. +; +; The test creates a scenario with enough KCFI-instrumented indirect calls +; (~32 bytes each) that would push a cbz/cbnz instruction out of its ±126 byte +; range if the KCFI_CHECK pseudo-instruction size is not properly accounted for. +; +; Without the fix (KCFI_CHECK returns size 0): +; - Backend thinks KCFI checks take no space +; - Generates cbz to branch over the code +; - During assembly, cbz target is >126 bytes away +; - Assembly fails with "error: out of range pc-relative fixup value" +; +; With the fix (KCFI_CHECK returns size 32 for Thumb2): +; - Backend correctly accounts for KCFI check expansion +; - Avoids cbz or uses longer-range branch instructions +; - Assembly succeeds, object file is generated + +declare void @external_function(i32) + +; Test WITHOUT KCFI: should generate cbz since calls are small +; CHECK-LABEL: test_without_kcfi: +; CHECK: cbz +; CHECK-NOT: bic{{.*}}#1 +define i32 @test_without_kcfi(ptr %callback, i32 %x) { +entry: + %cmp = icmp eq i32 %x, 0 + br i1 %cmp, label %if_zero, label %if_nonzero + +if_nonzero: + ; Regular (non-KCFI) indirect calls - much smaller + call void %callback() + call void %callback() + call void %callback() + call void %callback() + call void %callback() + call void %callback() + + call void @external_function(i32 %x) + %add1 = add i32 %x, 1 + ret i32 %add1 + +if_zero: + call void @external_function(i32 0) + ret i32 0 +} + +; Test WITH KCFI: should NOT generate cbz due to large KCFI checks +; CHECK-LABEL: test_with_kcfi: +; CHECK-NOT: cbz +; CHECK: bic{{.*}}#1 +define i32 @test_with_kcfi(ptr %callback, i32 %x) !kcfi_type !1 { +entry: + %cmp = icmp eq i32 %x, 0 + br i1 %cmp, label %if_zero, label %if_nonzero + +if_nonzero: + ; Six KCFI-instrumented indirect calls (~192 bytes total, exceeds cbz range) + call void %callback() [ "kcfi"(i32 12345678) ] + call void %callback() [ "kcfi"(i32 12345678) ] + call void %callback() [ "kcfi"(i32 12345678) ] + call void %callback() [ "kcfi"(i32 12345678) ] + call void %callback() [ "kcfi"(i32 12345678) ] + call void %callback() [ "kcfi"(i32 12345678) ] + + ; Regular call to prevent optimization + call void @external_function(i32 %x) + %add1 = add i32 %x, 1 + ret i32 %add1 + +if_zero: + call void @external_function(i32 0) + ret i32 0 +} + +!llvm.module.flags = !{!0} +!0 = !{i32 4, !"kcfi", i32 1} +!1 = !{i32 12345678} diff --git a/llvm/test/CodeGen/ARM/kcfi-patchable-function-prefix.ll b/llvm/test/CodeGen/ARM/kcfi-patchable-function-prefix.ll new file mode 100644 index 0000000000000..f8e083891eadb --- /dev/null +++ b/llvm/test/CodeGen/ARM/kcfi-patchable-function-prefix.ll @@ -0,0 +1,99 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=armv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s + +; CHECK: .p2align 2 +; CHECK-NOT: nop +; CHECK: .long 12345678 +define void @f1(ptr noundef %x) !kcfi_type !1 { +; CHECK-LABEL: f1: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: bic r12, r0, #1 +; CHECK-NEXT: ldr r12, [r12, #-4] +; CHECK-NEXT: eor r12, r12, #78 +; CHECK-NEXT: eor r12, r12, #24832 +; CHECK-NEXT: eor r12, r12, #12320768 +; CHECK-NEXT: eors r12, r12, #0 +; CHECK-NEXT: beq .Ltmp0 +; CHECK-NEXT: udf #33760 +; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: blx r0 +; CHECK-NEXT: pop {r11, pc} + call void %x() [ "kcfi"(i32 12345678) ] + ret void +} + +; CHECK: .p2align 2 +; CHECK-NOT: .long +; CHECK-NOT: nop +define void @f2(ptr noundef %x) { +; CHECK-LABEL: f2: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: bic r12, r0, #1 +; CHECK-NEXT: ldr r12, [r12, #-4] +; CHECK-NEXT: eor r12, r12, #78 +; CHECK-NEXT: eor r12, r12, #24832 +; CHECK-NEXT: eor r12, r12, #12320768 +; CHECK-NEXT: eors r12, r12, #0 +; CHECK-NEXT: beq .Ltmp1 +; CHECK-NEXT: udf #33760 +; CHECK-NEXT: .Ltmp1: +; CHECK-NEXT: blx r0 +; CHECK-NEXT: pop {r11, pc} + call void %x() [ "kcfi"(i32 12345678) ] + ret void +} + +; CHECK: .p2align 2 +; CHECK: .long 12345678 +; CHECK-COUNT-11: nop +define void @f3(ptr noundef %x) #0 !kcfi_type !1 { +; CHECK-LABEL: f3: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: bic r12, r0, #1 +; CHECK-NEXT: ldr r12, [r12, #-48] +; CHECK-NEXT: eor r12, r12, #78 +; CHECK-NEXT: eor r12, r12, #24832 +; CHECK-NEXT: eor r12, r12, #12320768 +; CHECK-NEXT: eors r12, r12, #0 +; CHECK-NEXT: beq .Ltmp3 +; CHECK-NEXT: udf #33760 +; CHECK-NEXT: .Ltmp3: +; CHECK-NEXT: blx r0 +; CHECK-NEXT: pop {r11, pc} + call void %x() [ "kcfi"(i32 12345678) ] + ret void +} + +; CHECK: .p2align 2 +; CHECK-COUNT-11: nop +define void @f4(ptr noundef %x) #0 { +; CHECK-LABEL: f4: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r11, lr} +; CHECK-NEXT: push {r11, lr} +; CHECK-NEXT: bic r12, r0, #1 +; CHECK-NEXT: ldr r12, [r12, #-48] +; CHECK-NEXT: eor r12, r12, #78 +; CHECK-NEXT: eor r12, r12, #24832 +; CHECK-NEXT: eor r12, r12, #12320768 +; CHECK-NEXT: eors r12, r12, #0 +; CHECK-NEXT: beq .Ltmp5 +; CHECK-NEXT: udf #33760 +; CHECK-NEXT: .Ltmp5: +; CHECK-NEXT: blx r0 +; CHECK-NEXT: pop {r11, pc} + call void %x() [ "kcfi"(i32 12345678) ] + ret void +} + +attributes #0 = { "patchable-function-prefix"="11" } + +!llvm.module.flags = !{!0} +!0 = !{i32 4, !"kcfi", i32 1} +!1 = !{i32 12345678} diff --git a/llvm/test/CodeGen/ARM/kcfi-thumb.ll b/llvm/test/CodeGen/ARM/kcfi-thumb.ll new file mode 100644 index 0000000000000..7c02d83034d60 --- /dev/null +++ b/llvm/test/CodeGen/ARM/kcfi-thumb.ll @@ -0,0 +1,215 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=thumbv6m-none-eabi < %s | FileCheck %s + +; This test verifies that Thumb1 (ARMv6-M) generates correct code for backend KCFI. +; Thumb1 uses the backend KCFI implementation with Thumb1-specific instructions. + +; Test function without KCFI annotation +; CHECK-LABEL: .globl nosan +; CHECK-NEXT: .p2align 1 +; CHECK-NEXT: .type nosan,%function +; CHECK-NEXT: .code 16 +; CHECK-NEXT: .thumb_func +define dso_local void @nosan() nounwind { +; CHECK-LABEL: nosan: +; CHECK: @ %bb.0: +; CHECK-NEXT: bx lr + ret void +} + +; Test function with KCFI annotation - verifies type hash emission +;; The alignment is at least 4 to avoid unaligned type hash loads when this +;; instrumented function is indirectly called. +; CHECK-LABEL: .globl target_func +; CHECK-NEXT: .p2align 2 +; CHECK-NEXT: .type target_func,%function +; CHECK-NEXT: .long 3170468932 +; CHECK-NEXT: .code 16 +; CHECK-NEXT: .thumb_func +define void @target_func() !kcfi_type !1 { +; CHECK-LABEL: target_func: +; CHECK: @ %bb.0: +; CHECK-NEXT: bx lr + ret void +} + +; Test indirect call with KCFI check using operand bundles +; CHECK-LABEL: .globl f1 +; CHECK: .p2align 2 +; CHECK-NEXT: .type f1,%function +; CHECK-NEXT: .long 3170468932 +; CHECK-NEXT: .code 16 +; CHECK-NEXT: .thumb_func +define void @f1(ptr noundef %x) !kcfi_type !1 { +; CHECK-LABEL: f1: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: movs r3, #1 +; CHECK-NEXT: mov r2, r0 +; CHECK-NEXT: bics r2, r3 +; CHECK-NEXT: subs r2, #4 +; CHECK-NEXT: ldr r2, [r2] +; CHECK-NEXT: movs r3, #188 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #249 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #132 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #68 +; CHECK-NEXT: cmp r2, r3 +; CHECK-NEXT: beq .Ltmp0 +; CHECK-NEXT: bkpt #0 +; CHECK-NEXT: .Ltmp0: +; CHECK-NEXT: blx r0 +; CHECK-NEXT: pop {r7, pc} + call void %x() [ "kcfi"(i32 -1124498364) ] + ret void +} + +; Test with tail call - backend KCFI supports tail calls +define void @f2(ptr noundef %x) !kcfi_type !1 { +; CHECK-LABEL: f2: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: movs r3, #1 +; CHECK-NEXT: mov r2, r0 +; CHECK-NEXT: bics r2, r3 +; CHECK-NEXT: subs r2, #4 +; CHECK-NEXT: ldr r2, [r2] +; CHECK-NEXT: movs r3, #188 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #249 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #132 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #68 +; CHECK-NEXT: cmp r2, r3 +; CHECK-NEXT: beq .Ltmp1 +; CHECK-NEXT: bkpt #0 +; CHECK-NEXT: .Ltmp1: +; CHECK-NEXT: blx r0 +; CHECK-NEXT: pop {r7, pc} + tail call void %x() [ "kcfi"(i32 -1124498364) ] + ret void +} + +; Test with R2 live (3 arguments) - compiler shuffles args, no spilling needed +define void @f3_r2_live(ptr noundef %x, i32 %a, i32 %b, i32 %c) !kcfi_type !1 { +; CHECK-LABEL: f3_r2_live: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r4, lr} +; CHECK-NEXT: push {r4, lr} +; CHECK-NEXT: mov r4, r0 +; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: mov r1, r2 +; CHECK-NEXT: mov r2, r3 +; CHECK-NEXT: push {r2} +; CHECK-NEXT: movs r3, #1 +; CHECK-NEXT: mov r2, r4 +; CHECK-NEXT: bics r2, r3 +; CHECK-NEXT: subs r2, #4 +; CHECK-NEXT: ldr r2, [r2] +; CHECK-NEXT: movs r3, #188 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #249 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #132 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #68 +; CHECK-NEXT: cmp r2, r3 +; CHECK-NEXT: pop {r2} +; CHECK-NEXT: beq .Ltmp2 +; CHECK-NEXT: bkpt #0 +; CHECK-NEXT: .Ltmp2: +; CHECK-NEXT: blx r4 +; CHECK-NEXT: pop {r4, pc} +; Compiler shuffles: target→r4, c→r2, a→r0, b→r1 +; R2 is live (3rd arg), so we push it, then uses R3 as temp, R2 as scratch + call void %x(i32 %a, i32 %b, i32 %c) [ "kcfi"(i32 -1124498364) ] + ret void +} + +; Test with both R2 and R3 live (4 arguments) - compiler moves to r5/r4, uses R3 temp and R12 scratch +define void @f4_r2_r3_live(ptr noundef %x, i32 %a, i32 %b, i32 %c, i32 %d) !kcfi_type !1 { +; CHECK-LABEL: f4_r2_r3_live: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r4, r5, r7, lr} +; CHECK-NEXT: push {r4, r5, r7, lr} +; CHECK-NEXT: mov r5, r3 +; CHECK-NEXT: mov r4, r0 +; CHECK-NEXT: ldr r3, [sp, #16] +; CHECK-NEXT: mov r0, r1 +; CHECK-NEXT: mov r1, r2 +; CHECK-NEXT: mov r2, r5 +; CHECK-NEXT: push {r3} +; CHECK-NEXT: push {r2} +; CHECK-NEXT: movs r3, #1 +; CHECK-NEXT: mov r2, r4 +; CHECK-NEXT: bics r2, r3 +; CHECK-NEXT: subs r2, #4 +; CHECK-NEXT: ldr r2, [r2] +; CHECK-NEXT: movs r3, #188 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #249 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #132 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #68 +; CHECK-NEXT: cmp r2, r3 +; CHECK-NEXT: pop {r2} +; CHECK-NEXT: pop {r3} +; CHECK-NEXT: beq .Ltmp3 +; CHECK-NEXT: bkpt #0 +; CHECK-NEXT: .Ltmp3: +; CHECK-NEXT: blx r4 +; CHECK-NEXT: pop {r4, r5, r7, pc} +; Compiler shuffles: r3→r5, target→r4, d→r3 (from stack), a→r0, b→r1, c→r2 +; Then pushes r3 (d value), then r2, uses R3 as temp, R2 as scratch + call void %x(i32 %a, i32 %b, i32 %c, i32 %d) [ "kcfi"(i32 -1124498364) ] + ret void +} + +; Test where target ends up in R12, forcing R2 as scratch, with both R2 and R3 live +; This uses inline asm to force target into R12, with 4 call arguments to make R2/R3 live +define void @f5_r12_target_r2_r3_live(i32 %a, i32 %b, i32 %c, i32 %d) !kcfi_type !1 { +; CHECK-LABEL: f5_r12_target_r2_r3_live: +; CHECK: @ %bb.0: +; CHECK-NEXT: .save {r7, lr} +; CHECK-NEXT: push {r7, lr} +; CHECK-NEXT: @APP +; CHECK-NEXT: @NO_APP +; CHECK-NEXT: push {r3} +; CHECK-NEXT: push {r2} +; CHECK-NEXT: movs r3, #1 +; CHECK-NEXT: mov r2, r12 +; CHECK-NEXT: bics r2, r3 +; CHECK-NEXT: subs r2, #4 +; CHECK-NEXT: ldr r2, [r2] +; CHECK-NEXT: movs r3, #188 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #249 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #132 +; CHECK-NEXT: lsls r3, r3, #8 +; CHECK-NEXT: adds r3, #68 +; CHECK-NEXT: cmp r2, r3 +; CHECK-NEXT: pop {r2} +; CHECK-NEXT: pop {r3} +; CHECK-NEXT: beq .Ltmp4 +; CHECK-NEXT: bkpt #0 +; CHECK-NEXT: .Ltmp4: +; CHECK-NEXT: blx r12 +; CHECK-NEXT: pop {r7, pc} +; Use inline asm to get function pointer into R12 +; With 4 arguments (r0-r3), both R2 and R3 are live +; Target in R12 means R2 is scratch, R3 is temp, and both need spilling + %target = call ptr asm "", "={r12}"() + call void %target(i32 %a, i32 %b, i32 %c, i32 %d) [ "kcfi"(i32 -1124498364) ] + ret void +} + +!llvm.module.flags = !{!0} +!0 = !{i32 4, !"kcfi", i32 1} +!1 = !{i32 -1124498364} diff --git a/llvm/test/CodeGen/ARM/kcfi-thumb2.ll b/llvm/test/CodeGen/ARM/kcfi-thumb2.ll new file mode 100644 index 0000000000000..f319d98b845de --- /dev/null +++ b/llvm/test/CodeGen/ARM/kcfi-thumb2.ll @@ -0,0 +1,163 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs < %s | FileCheck %s --check-prefix=ASM +; RUN: llc -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs -stop-after=finalize-isel < %s | FileCheck %s --check-prefixes=MIR,ISEL +; RUN: llc -mtriple=thumbv7-linux-gnueabi -verify-machineinstrs -stop-after=kcfi < %s | FileCheck %s --check-prefixes=MIR,KCFI + +; MIR checks for all functions (grouped here to prevent update_llc_test_checks.py from removing them) + +; MIR-LABEL: name: f1 +; MIR: body: + +; ISEL: tBLXr 14 /* CC::al */, $noreg, %0, csr_aapcs,{{.*}} cfi-type 12345678 + +; KCFI: BUNDLE{{.*}} { +; KCFI-NEXT: KCFI_CHECK_Thumb2 $r0, 12345678 +; KCFI-NEXT: tBLXr 14 /* CC::al */, $noreg, {{(killed )?}}$r0, csr_aapcs,{{.*}} +; KCFI-NEXT: } + +; MIR-LABEL: name: f2 +; MIR: body: + +; ISEL: TCRETURNri %0, 0, csr_aapcs, implicit $sp, cfi-type 12345678 + +; KCFI: BUNDLE{{.*}} { +; KCFI-NEXT: KCFI_CHECK_Thumb2 $r0, 12345678 +; KCFI-NEXT: tTAILJMPr {{(killed )?}}$r0, csr_aapcs, implicit $sp, implicit $sp +; KCFI-NEXT: } + +; Test function without KCFI annotation +; ASM-LABEL: .globl nosan +; ASM-NEXT: .p2align 1 +; ASM-NEXT: .type nosan,%function +; ASM-NEXT: .code 16 +; ASM-NEXT: .thumb_func +define dso_local void @nosan() nounwind { +; ASM-LABEL: nosan: +; ASM: @ %bb.0: +; ASM-NEXT: bx lr + ret void +} + +; Test function with KCFI annotation - verifies type hash emission +;; The alignment is at least 4 to avoid unaligned type hash loads when this +;; instrumented function is indirectly called. +; ASM-LABEL: .globl target_func +; ASM-NEXT: .p2align 2 +; ASM-NEXT: .type target_func,%function +; ASM-NEXT: .long 12345678 +; ASM-NEXT: .code 16 +; ASM-NEXT: .thumb_func +define void @target_func() !kcfi_type !1 { +; ASM-LABEL: target_func: +; ASM: @ %bb.0: +; ASM-NEXT: bx lr + ret void +} + +; Test indirect call with KCFI check +; ASM: .long 12345678 +define void @f1(ptr noundef %x) !kcfi_type !1 { +; ASM-LABEL: f1: +; ASM: @ %bb.0: +; ASM-NEXT: .save {r7, lr} +; ASM-NEXT: push {r7, lr} +; ASM-NEXT: bic r12, r0, #1 +; ASM-NEXT: ldr r12, [r12, #-4] +; ASM-NEXT: eor r12, r12, #78 +; ASM-NEXT: eor r12, r12, #24832 +; ASM-NEXT: eor r12, r12, #12320768 +; ASM-NEXT: eors r12, r12, #0 +; ASM-NEXT: beq.w .Ltmp0 +; ASM-NEXT: udf #128 +; ASM-NEXT: .Ltmp0: +; ASM-NEXT: blx r0 +; ASM-NEXT: pop {r7, pc} + + call void %x() [ "kcfi"(i32 12345678) ] + ret void +} + +; Test with tail call +define void @f2(ptr noundef %x) !kcfi_type !1 { +; ASM-LABEL: f2: +; ASM: @ %bb.0: +; ASM-NEXT: bic r12, r0, #1 +; ASM-NEXT: ldr r12, [r12, #-4] +; ASM-NEXT: eor r12, r12, #78 +; ASM-NEXT: eor r12, r12, #24832 +; ASM-NEXT: eor r12, r12, #12320768 +; ASM-NEXT: eors r12, r12, #0 +; ASM-NEXT: beq.w .Ltmp1 +; ASM-NEXT: udf #128 +; ASM-NEXT: .Ltmp1: +; ASM-NEXT: bx r0 + + tail call void %x() [ "kcfi"(i32 12345678) ] + ret void +} + +; Test r3 spill/reload when target is r12 and r3 is a call argument (Thumb2) +define void @f3_r3_spill(ptr noundef %target, i32 %a, i32 %b, i32 %c, i32 %d) !kcfi_type !1 { +; ASM-LABEL: f3_r3_spill: +; ASM: @ %bb.0: +; ASM-NEXT: .save {r7, lr} +; ASM-NEXT: push {r7, lr} +; ASM-NEXT: mov lr, r3 +; ASM-NEXT: ldr r3, [sp, #8] +; ASM-NEXT: mov r12, r0 +; ASM-NEXT: mov r0, r1 +; ASM-NEXT: mov r1, r2 +; ASM-NEXT: mov r2, lr +; ASM-NEXT: push {r3} +; ASM-NEXT: bic r3, r12, #1 +; ASM-NEXT: ldr r3, [r3, #-4] +; ASM-NEXT: eor r3, r3, #78 +; ASM-NEXT: eor r3, r3, #24832 +; ASM-NEXT: eor r3, r3, #12320768 +; ASM-NEXT: eors r3, r3, #0 +; ASM-NEXT: pop {r3} +; ASM-NEXT: beq.w .Ltmp2 +; ASM-NEXT: udf #140 +; ASM-NEXT: .Ltmp2: +; ASM-NEXT: blx r12 +; ASM-NEXT: pop {r7, pc} +; Arguments: r0=%target, r1=%a, r2=%b, r3=%c, [sp+8]=%d +; Call needs: r0=%a, r1=%b, r2=%c, r3=%d, target in r12 +; r3 is live as 4th argument, so push it before KCFI check + call void %target(i32 %a, i32 %b, i32 %c, i32 %d) [ "kcfi"(i32 12345678) ] + ret void +} + +; Test with 3 arguments - r3 not live, target in r12 or elsewhere, r12 used as scratch +define void @f4_r3_unused(ptr noundef %target, i32 %a, i32 %b) !kcfi_type !1 { +; ASM-LABEL: f4_r3_unused: +; ASM: @ %bb.0: +; ASM-NEXT: .save {r7, lr} +; ASM-NEXT: push {r7, lr} +; ASM-NEXT: mov r3, r0 +; ASM-NEXT: mov r0, r1 +; ASM-NEXT: mov r1, r2 +; ASM-NEXT: bic r12, r3, #1 +; ASM-NEXT: ldr r12, [r12, #-4] +; ASM-NEXT: eor r12, r12, #78 +; ASM-NEXT: eor r12, r12, #24832 +; ASM-NEXT: eor r12, r12, #12320768 +; ASM-NEXT: eors r12, r12, #0 +; ASM-NEXT: beq.w .Ltmp3 +; ASM-NEXT: udf #131 +; ASM-NEXT: .Ltmp3: +; ASM-NEXT: blx r3 +; ASM-NEXT: pop {r7, pc} +; Only 3 arguments total, so r3 is not used as call argument +; Target might be in r3, using r12 as scratch (no spill needed) + call void %target(i32 %a, i32 %b) [ "kcfi"(i32 12345678) ] + ret void +} + +!llvm.module.flags = !{!0} +!0 = !{i32 4, !"kcfi", i32 1} +!1 = !{i32 12345678} +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; ISEL: {{.*}} +; KCFI: {{.*}} +; MIR: {{.*}} diff --git a/llvm/test/CodeGen/ARM/kcfi.ll b/llvm/test/CodeGen/ARM/kcfi.ll deleted file mode 100644 index 9e16468c9347b..0000000000000 --- a/llvm/test/CodeGen/ARM/kcfi.ll +++ /dev/null @@ -1,28 +0,0 @@ -; RUN: llc -mtriple=thumbv6m-none-eabi < %s | FileCheck %s - -; CHECK-LABEL: .globl nosan -; CHECK-NEXT: .p2align 1 -; CHECK-NEXT: .type nosan,%function -; CHECK-NEXT: .code 16 -; CHECK-NEXT: .thumb_func -; CHECK-NEXT: nosan: -define dso_local void @nosan() nounwind { - ret void -} - -;; The alignment is at least 4 to avoid unaligned type hash loads when this -;; instrumented function is indirectly called. -; CHECK-LABEL: .globl f1 -; CHECK-NEXT: .p2align 2 -; CHECK-NEXT: .type f1,%function -; CHECK-NEXT: .long 3170468932 -; CHECK-NEXT: .code 16 -; CHECK-NEXT: .thumb_func -; CHECK-NEXT: f1: -define void @f1(ptr noundef %x) !kcfi_type !1 { - ret void -} - -!llvm.module.flags = !{!0} -!0 = !{i32 4, !"kcfi", i32 1} -!1 = !{i32 -1124498364} From c6073d72ee23d8cd6aa49c08edde846359e41bde Mon Sep 17 00:00:00 2001 From: Ryotaro Kasuga Date: Fri, 24 Oct 2025 00:32:34 +0900 Subject: [PATCH 11/31] [LoopCacheAnalysis] Drop incorrect nowrap flags from addrec (#164796) This patch stops propagating nowrap flags unconditionally. In the modified part, when we have an addrec `{%a,+,%b}` where `%b` is known to be negative, we create a new addrec `{%a,+,(-1 * %b)}`. When creating it, the nowrap flags are transferred from the original addrec to the new one without any checks, which is generally incorrect. Since the nowrap property is not essential for this analysis, it would be better to drop it to avoid potential bugs. --- llvm/lib/Analysis/LoopCacheAnalysis.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Analysis/LoopCacheAnalysis.cpp b/llvm/lib/Analysis/LoopCacheAnalysis.cpp index 050c32707596a..424a7fe3721bb 100644 --- a/llvm/lib/Analysis/LoopCacheAnalysis.cpp +++ b/llvm/lib/Analysis/LoopCacheAnalysis.cpp @@ -436,10 +436,9 @@ bool IndexedReference::delinearize(const LoopInfo &LI) { const SCEV *StepRec = AccessFnAR ? AccessFnAR->getStepRecurrence(SE) : nullptr; if (StepRec && SE.isKnownNegative(StepRec)) - AccessFn = SE.getAddRecExpr(AccessFnAR->getStart(), - SE.getNegativeSCEV(StepRec), - AccessFnAR->getLoop(), - AccessFnAR->getNoWrapFlags()); + AccessFn = SE.getAddRecExpr( + AccessFnAR->getStart(), SE.getNegativeSCEV(StepRec), + AccessFnAR->getLoop(), SCEV::NoWrapFlags::FlagAnyWrap); const SCEV *Div = SE.getUDivExactExpr(AccessFn, ElemSize); Subscripts.push_back(Div); Sizes.push_back(ElemSize); From 150145486e82c8da581f94cdceceb2652d644825 Mon Sep 17 00:00:00 2001 From: Sang Ik Lee Date: Thu, 23 Oct 2025 08:32:53 -0700 Subject: [PATCH 12/31] [MLIR][GPU] Generalize gpu.printf op lowering to LLVM call pattern. (#164297) Existing pattern for lowering gpu.printf op to LLVM call uses fixed function name and calling convention. Those two should be exposed as pass option to allow supporting Intel Compute Runtime for GPU. Also adds gpu.printf op pattern to GPU to LLVMSPV pass. It may appear out of place, but integration test is added to XeVM integration test as that is the current best folder for testing with Intel Compute Runtime. Test should be moved in the future if a better test folder is added. --- .../Conversion/GPUCommon/GPUOpsLowering.cpp | 6 ++-- .../lib/Conversion/GPUCommon/GPUOpsLowering.h | 21 ++++++++++--- .../Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp | 5 +++- mlir/test/Conversion/GPUToLLVMSPV/printf.mlir | 16 ++++++++++ .../Dialect/XeVM/GPU/gpu_printf.mlir | 30 +++++++++++++++++++ 5 files changed, 71 insertions(+), 7 deletions(-) create mode 100644 mlir/test/Conversion/GPUToLLVMSPV/printf.mlir create mode 100644 mlir/test/Integration/Dialect/XeVM/GPU/gpu_printf.mlir diff --git a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp index 2285d2695db4e..eb662a1b056de 100644 --- a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp +++ b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.cpp @@ -507,7 +507,8 @@ LogicalResult GPUPrintfOpToLLVMCallLowering::matchAndRewrite( LLVM::LLVMFunctionType::get(rewriter.getI32Type(), {ptrType}, /*isVarArg=*/true); LLVM::LLVMFuncOp printfDecl = - getOrDefineFunction(moduleOp, loc, rewriter, "printf", printfType); + getOrDefineFunction(moduleOp, loc, rewriter, funcName, printfType); + printfDecl.setCConv(callingConvention); // Create the global op or find an existing one. LLVM::GlobalOp global = getOrCreateStringConstant( @@ -530,7 +531,8 @@ LogicalResult GPUPrintfOpToLLVMCallLowering::matchAndRewrite( printfArgs.push_back(stringStart); printfArgs.append(argsRange.begin(), argsRange.end()); - LLVM::CallOp::create(rewriter, loc, printfDecl, printfArgs); + auto call = LLVM::CallOp::create(rewriter, loc, printfDecl, printfArgs); + call.setCConv(callingConvention); rewriter.eraseOp(gpuPrintfOp); return success(); } diff --git a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h index 66d3bb40a8f5a..ec74787b2a8ed 100644 --- a/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h +++ b/mlir/lib/Conversion/GPUCommon/GPUOpsLowering.h @@ -10,6 +10,7 @@ #include "mlir/Conversion/LLVMCommon/Pattern.h" #include "mlir/Dialect/GPU/IR/GPUDialect.h" +#include "mlir/Dialect/LLVMIR/LLVMAttrs.h" #include "mlir/Dialect/LLVMIR/LLVMDialect.h" namespace mlir { @@ -142,13 +143,23 @@ struct GPUPrintfOpToHIPLowering : public ConvertOpToLLVMPattern { /// This pass will add a declaration of printf() to the GPUModule if needed /// and separate out the format strings into global constants. For some /// runtimes, such as OpenCL on AMD, this is sufficient setup, as the compiler -/// will lower printf calls to appropriate device-side code +/// will lower printf calls to appropriate device-side code. +/// However not all backends use the same calling convention and function +/// naming. +/// For example, the LLVM SPIRV backend requires calling convention +/// LLVM::cconv::CConv::SPIR_FUNC and function name needs to be +/// mangled as "_Z6printfPU3AS2Kcz". +/// Default callingConvention is LLVM::cconv::CConv::C and +/// funcName is "printf" but they can be customized as needed. struct GPUPrintfOpToLLVMCallLowering : public ConvertOpToLLVMPattern { - GPUPrintfOpToLLVMCallLowering(const LLVMTypeConverter &converter, - int addressSpace = 0) + GPUPrintfOpToLLVMCallLowering( + const LLVMTypeConverter &converter, int addressSpace = 0, + LLVM::cconv::CConv callingConvention = LLVM::cconv::CConv::C, + StringRef funcName = "printf") : ConvertOpToLLVMPattern(converter), - addressSpace(addressSpace) {} + addressSpace(addressSpace), callingConvention(callingConvention), + funcName(funcName) {} LogicalResult matchAndRewrite(gpu::PrintfOp gpuPrintfOp, gpu::PrintfOpAdaptor adaptor, @@ -156,6 +167,8 @@ struct GPUPrintfOpToLLVMCallLowering private: int addressSpace; + LLVM::cconv::CConv callingConvention; + StringRef funcName; }; /// Lowering of gpu.printf to a vprintf standard library. diff --git a/mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp b/mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp index c2363a1a40294..25f1e1b184d61 100644 --- a/mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp +++ b/mlir/lib/Conversion/GPUToLLVMSPV/GPUToLLVMSPV.cpp @@ -470,10 +470,13 @@ struct GPUToLLVMSPVConversionPass final gpu::GPUFuncOp, gpu::GlobalIdOp, gpu::GridDimOp, gpu::LaneIdOp, gpu::NumSubgroupsOp, gpu::ReturnOp, gpu::ShuffleOp, gpu::SubgroupIdOp, gpu::SubgroupSizeOp, - gpu::ThreadIdOp>(); + gpu::ThreadIdOp, gpu::PrintfOp>(); populateGpuToLLVMSPVConversionPatterns(converter, patterns); populateGpuMemorySpaceAttributeConversions(converter); + patterns.add(converter, /*addressSpace=*/2, + LLVM::cconv::CConv::SPIR_FUNC, + "_Z6printfPU3AS2Kcz"); if (failed(applyPartialConversion(getOperation(), target, std::move(patterns)))) diff --git a/mlir/test/Conversion/GPUToLLVMSPV/printf.mlir b/mlir/test/Conversion/GPUToLLVMSPV/printf.mlir new file mode 100644 index 0000000000000..74017e8354cf1 --- /dev/null +++ b/mlir/test/Conversion/GPUToLLVMSPV/printf.mlir @@ -0,0 +1,16 @@ +// RUN: mlir-opt %s -convert-gpu-to-llvm-spv | FileCheck %s + +gpu.module @test_module { + // CHECK: llvm.mlir.global internal constant @[[$PRINT_GLOBAL:[A-Za-z0-9_]+]]("Hello: %d\0A\00") {addr_space = 2 : i32} + // CHECK: llvm.func spir_funccc @_Z6printfPU3AS2Kcz(!llvm.ptr<2>, ...) -> i32 + // CHECK-LABEL: llvm.func spir_funccc @test_printf + // CHECK: (%[[ARG0:.*]]: i32) + gpu.func @test_printf(%arg0: i32) { + // CHECK: %[[IMM0:.*]] = llvm.mlir.addressof @[[$PRINT_GLOBAL]] : !llvm.ptr<2> + // CHECK-NEXT: %[[IMM2:.*]] = llvm.getelementptr %[[IMM0]][0, 0] : (!llvm.ptr<2>) -> !llvm.ptr<2>, !llvm.array<11 x i8> + // CHECK-NEXT: %{{.*}} = llvm.call spir_funccc @_Z6printfPU3AS2Kcz(%[[IMM2]], %[[ARG0]]) vararg(!llvm.func, ...)>) : (!llvm.ptr<2>, i32) -> i32 + gpu.printf "Hello: %d\n", %arg0 : i32 + gpu.return + } +} + diff --git a/mlir/test/Integration/Dialect/XeVM/GPU/gpu_printf.mlir b/mlir/test/Integration/Dialect/XeVM/GPU/gpu_printf.mlir new file mode 100644 index 0000000000000..edf8775c72418 --- /dev/null +++ b/mlir/test/Integration/Dialect/XeVM/GPU/gpu_printf.mlir @@ -0,0 +1,30 @@ +// RUN: mlir-opt %s \ +// RUN: | mlir-opt -pass-pipeline='builtin.module(cse,func.func(gpu-async-region),xevm-attach-target,gpu.module(convert-gpu-to-llvm-spv{use-64bit-index=true},convert-xevm-to-llvm,cse))' \ +// RUN: | mlir-opt -convert-scf-to-cf -convert-cf-to-llvm -convert-vector-to-llvm -convert-arith-to-llvm \ +// RUN: | mlir-opt -gpu-to-llvm -reconcile-unrealized-casts -cse -gpu-module-to-binary \ +// RUN: | mlir-runner \ +// RUN: --shared-libs=%mlir_sycl_runtime \ +// RUN: --shared-libs=%mlir_runner_utils \ +// RUN: --shared-libs=%mlir_c_runner_utils \ +// RUN: --entry-point-result=void \ +// RUN: | FileCheck %s + +module @test attributes {gpu.container_module} { + gpu.module @test_module { + gpu.func @test_printf(%arg0: i32, %arg1: f32) kernel { + gpu.printf "Hello: %d\n", %arg0 : i32 + gpu.printf "Hello: %f\n", %arg1 : f32 + gpu.return + } + } + + func.func @main() attributes {llvm.emit_c_interface} { + %c1 = arith.constant 1 : index + %c11 = arith.constant 11 : i32 + %c4 = arith.constant 4.0 : f32 + // CHECK: Hello: 11 + // CHECK: Hello: 4.000000 + gpu.launch_func @test_module::@test_printf blocks in (%c1, %c1, %c1) threads in (%c1, %c1, %c1) args(%c11 : i32, %c4 : f32) + return + } +} From cf20a2685e1eb062e8c46f091797576e2a270003 Mon Sep 17 00:00:00 2001 From: Andrew Ng Date: Thu, 23 Oct 2025 16:34:28 +0100 Subject: [PATCH 13/31] [DTLTO][Clang][LLD] Fix DTLTO for multi-call LLVM driver toolchain (#162456) Add DTLTO linker option `--thinlto-remote-compiler-prepend-arg` to enable support for the multi-call LLVM driver that requires an additional option to specify the subcommand, e.g. "llvm clang ...". Fixes https://github.com/llvm/llvm-project/issues/159125. --- clang/include/clang/Driver/CommonArgs.h | 3 ++ clang/lib/Driver/ToolChains/CommonArgs.cpp | 29 ++++++++++++------- clang/lib/Driver/ToolChains/PS4CPU.cpp | 11 +------ .../test/Driver/DTLTO/Inputs/dtlto-helper.py | 11 +++++++ clang/test/Driver/DTLTO/dtlto.c | 23 ++++++++------- clang/test/Driver/DTLTO/filename.py | 4 --- clang/test/Driver/DTLTO/lit.local.cfg | 3 ++ clang/test/Driver/DTLTO/ps5-dtlto.c | 18 +++++++----- lld/COFF/Config.h | 3 ++ lld/COFF/Driver.cpp | 4 +++ lld/COFF/LTO.cpp | 4 +-- lld/COFF/Options.td | 3 ++ lld/ELF/Config.h | 1 + lld/ELF/Driver.cpp | 2 ++ lld/ELF/LTO.cpp | 3 +- lld/ELF/Options.td | 3 ++ lld/docs/DTLTO.rst | 18 ++++++++---- llvm/include/llvm/LTO/LTO.h | 3 ++ llvm/lib/LTO/LTO.cpp | 11 ++++++- llvm/test/ThinLTO/X86/dtlto/json.ll | 20 ++++++++++--- llvm/tools/llvm-lto2/llvm-lto2.cpp | 11 ++++++- 21 files changed, 133 insertions(+), 55 deletions(-) create mode 100644 clang/test/Driver/DTLTO/Inputs/dtlto-helper.py delete mode 100644 clang/test/Driver/DTLTO/filename.py create mode 100644 clang/test/Driver/DTLTO/lit.local.cfg diff --git a/clang/include/clang/Driver/CommonArgs.h b/clang/include/clang/Driver/CommonArgs.h index 23426c0a3e02e..ac17d6211d882 100644 --- a/clang/include/clang/Driver/CommonArgs.h +++ b/clang/include/clang/Driver/CommonArgs.h @@ -76,6 +76,9 @@ void SplitDebugInfo(const ToolChain &TC, Compilation &C, const Tool &T, const JobAction &JA, const llvm::opt::ArgList &Args, const InputInfo &Output, const char *OutFile); +void addDTLTOOptions(const ToolChain &ToolChain, const llvm::opt::ArgList &Args, + llvm::opt::ArgStringList &CmdArgs); + void addLTOOptions(const ToolChain &ToolChain, const llvm::opt::ArgList &Args, llvm::opt::ArgStringList &CmdArgs, const InputInfo &Output, const InputInfoList &Inputs, bool IsThinLTO); diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 99400ac701fbe..727af698738d4 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -949,6 +949,24 @@ bool tools::isTLSDESCEnabled(const ToolChain &TC, return EnableTLSDESC; } +void tools::addDTLTOOptions(const ToolChain &ToolChain, const ArgList &Args, + llvm::opt::ArgStringList &CmdArgs) { + if (Arg *A = Args.getLastArg(options::OPT_fthinlto_distributor_EQ)) { + CmdArgs.push_back( + Args.MakeArgString("--thinlto-distributor=" + Twine(A->getValue()))); + const Driver &D = ToolChain.getDriver(); + CmdArgs.push_back(Args.MakeArgString("--thinlto-remote-compiler=" + + Twine(D.getClangProgramPath()))); + if (auto *PA = D.getPrependArg()) + CmdArgs.push_back(Args.MakeArgString( + "--thinlto-remote-compiler-prepend-arg=" + Twine(PA))); + + for (const auto &A : + Args.getAllArgValues(options::OPT_Xthinlto_distributor_EQ)) + CmdArgs.push_back(Args.MakeArgString("--thinlto-distributor-arg=" + A)); + } +} + void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, ArgStringList &CmdArgs, const InputInfo &Output, const InputInfoList &Inputs, bool IsThinLTO) { @@ -1350,16 +1368,7 @@ void tools::addLTOOptions(const ToolChain &ToolChain, const ArgList &Args, CmdArgs.push_back( Args.MakeArgString(Twine(PluginOptPrefix) + "-time-passes")); - if (Arg *A = Args.getLastArg(options::OPT_fthinlto_distributor_EQ)) { - CmdArgs.push_back( - Args.MakeArgString("--thinlto-distributor=" + Twine(A->getValue()))); - CmdArgs.push_back( - Args.MakeArgString("--thinlto-remote-compiler=" + - Twine(ToolChain.getDriver().getClangProgramPath()))); - - for (auto A : Args.getAllArgValues(options::OPT_Xthinlto_distributor_EQ)) - CmdArgs.push_back(Args.MakeArgString("--thinlto-distributor-arg=" + A)); - } + addDTLTOOptions(ToolChain, Args, CmdArgs); } void tools::addOpenMPRuntimeLibraryPath(const ToolChain &TC, diff --git a/clang/lib/Driver/ToolChains/PS4CPU.cpp b/clang/lib/Driver/ToolChains/PS4CPU.cpp index 61afc61a53dfd..34ec65ae59602 100644 --- a/clang/lib/Driver/ToolChains/PS4CPU.cpp +++ b/clang/lib/Driver/ToolChains/PS4CPU.cpp @@ -344,16 +344,7 @@ void tools::PS5cpu::Linker::ConstructJob(Compilation &C, const JobAction &JA, // pass LTO options to ensure proper codegen, metadata production, etc if // LTO indeed occurs. - if (const Arg *A = Args.getLastArg(options::OPT_fthinlto_distributor_EQ)) { - CmdArgs.push_back( - Args.MakeArgString("--thinlto-distributor=" + Twine(A->getValue()))); - CmdArgs.push_back(Args.MakeArgString("--thinlto-remote-compiler=" + - Twine(D.getClangProgramPath()))); - - for (const auto &A : - Args.getAllArgValues(options::OPT_Xthinlto_distributor_EQ)) - CmdArgs.push_back(Args.MakeArgString("--thinlto-distributor-arg=" + A)); - } + tools::addDTLTOOptions(TC, Args, CmdArgs); if (Args.hasFlag(options::OPT_funified_lto, options::OPT_fno_unified_lto, true)) diff --git a/clang/test/Driver/DTLTO/Inputs/dtlto-helper.py b/clang/test/Driver/DTLTO/Inputs/dtlto-helper.py new file mode 100644 index 0000000000000..6eb9f68e43bce --- /dev/null +++ b/clang/test/Driver/DTLTO/Inputs/dtlto-helper.py @@ -0,0 +1,11 @@ +from pathlib import Path +import sys + +# Arg 1: "clang" path. +p = Path(sys.argv[1]) +print(f"clang-name:{p.resolve().name}") +# Arg 2: Non-zero for LLVM driver. +if sys.argv[2] != "0": + print(f'prepend-arg:"--thinlto-remote-compiler-prepend-arg={p.name}"') +else: + print("prepend-arg: ") diff --git a/clang/test/Driver/DTLTO/dtlto.c b/clang/test/Driver/DTLTO/dtlto.c index f31b635feed96..5fbf7889e790b 100644 --- a/clang/test/Driver/DTLTO/dtlto.c +++ b/clang/test/Driver/DTLTO/dtlto.c @@ -3,16 +3,18 @@ /// Check DTLTO options are forwarded to the linker. /// Check that options are forwarded as expected with --thinlto-distributor=. -// RUN: %python %S/filename.py %clang > %t_forward.log +// RUN: %python %S/Inputs/dtlto-helper.py %clang %llvm-driver > %t_forward.log // RUN: %clang -flto=thin %s -### -fuse-ld=lld --target=x86_64-linux-gnu \ // RUN: -Xthinlto-distributor=a1 -Xthinlto-distributor=a2,a3 \ // RUN: -fthinlto-distributor=d.exe -Werror >>%t_forward.log 2>&1 // RUN: FileCheck %s --input-file=%t_forward.log --check-prefix=FORWARD -// FORWARD: filename.py:[[CLANG:.*]] -// FORWARD: ld.lld +// FORWARD: clang-name:[[CLANG:.*]] +// FORWARD-NEXT: prepend-arg:[[PREPEND_ARG:.*]] +// FORWARD: ld.lld // FORWARD-SAME: "--thinlto-distributor=d.exe" // FORWARD-SAME: "--thinlto-remote-compiler={{[^"]*}}[[CLANG]]" +// FORWARD-SAME: [[PREPEND_ARG]] // FORWARD-SAME: "--thinlto-distributor-arg=a1" // FORWARD-SAME: "--thinlto-distributor-arg=a2" // FORWARD-SAME: "--thinlto-distributor-arg=a3" @@ -30,24 +32,25 @@ /// Check the expected arguments are forwarded by default with only /// --thinlto-distributor=. -// RUN: %python %S/filename.py %clang > %t_default.log +// RUN: %python %S/Inputs/dtlto-helper.py %clang %llvm-driver > %t_default.log // RUN: %clang -flto=thin %s -### -fuse-ld=lld --target=x86_64-linux-gnu \ // RUN: -fthinlto-distributor=d.exe -Werror >>%t_default.log 2>&1 // RUN: FileCheck %s --input-file=%t_default.log --check-prefix=DEFAULT \ // RUN: --implicit-check-not=distributor --implicit-check-not=remote-compiler -// DEFAULT: filename.py:[[CLANG:.*]] -// DEFAULT: ld.lld +// DEFAULT: clang-name:[[CLANG:.*]] +// DEFAULT-NEXT: prepend-arg:[[PREPEND_ARG:.*]] +// DEFAULT: ld.lld // DEFAULT-SAME: "--thinlto-distributor=d.exe" // DEFAULT-SAME: "--thinlto-remote-compiler={{[^"]*}}[[CLANG]]" +// DEFAULT-SAME: [[PREPEND_ARG]] /// Check that nothing is forwarded when the compiler is not in LTO mode, and that /// appropriate unused option warnings are issued. -// RUN: %python %S/filename.py %clang > %t_noflto.log // RUN: %clang %s -### -fuse-ld=lld --target=x86_64-linux-gnu \ -// RUN: -fthinlto-distributor=d.exe >>%t_noflto.log 2>&1 -// RUN: FileCheck %s --input-file=%t_noflto.log --check-prefix=NOFLTO \ -// RUN: --implicit-check-not=distributor --implicit-check-not=remote-compiler +// RUN: -fthinlto-distributor=d.exe 2>&1 | \ +// RUN: FileCheck %s --check-prefix=NOFLTO --implicit-check-not=distributor \ +// RUN: --implicit-check-not=remote-compiler // NOFLTO: warning: argument unused during compilation: '-fthinlto-distributor=d.exe' // NOFLTO: ld.lld diff --git a/clang/test/Driver/DTLTO/filename.py b/clang/test/Driver/DTLTO/filename.py deleted file mode 100644 index df1aeb6682543..0000000000000 --- a/clang/test/Driver/DTLTO/filename.py +++ /dev/null @@ -1,4 +0,0 @@ -from pathlib import Path -import sys - -print(f"filename.py:{Path(sys.argv[1]).resolve().name}") diff --git a/clang/test/Driver/DTLTO/lit.local.cfg b/clang/test/Driver/DTLTO/lit.local.cfg new file mode 100644 index 0000000000000..0756c5cfa11ca --- /dev/null +++ b/clang/test/Driver/DTLTO/lit.local.cfg @@ -0,0 +1,3 @@ +from lit.llvm import llvm_config + +config.substitutions.append(("%llvm-driver", "1" if "llvm-driver" in config.available_features else "0")) diff --git a/clang/test/Driver/DTLTO/ps5-dtlto.c b/clang/test/Driver/DTLTO/ps5-dtlto.c index 4c10a026f944b..b59fb48512000 100644 --- a/clang/test/Driver/DTLTO/ps5-dtlto.c +++ b/clang/test/Driver/DTLTO/ps5-dtlto.c @@ -3,16 +3,18 @@ /// Check DTLTO options are forwarded to the linker. /// Check that options are forwarded as expected with --thinlto-distributor=. -// RUN: %python %S/filename.py %clang > %t_forward.log +// RUN: %python %S/Inputs/dtlto-helper.py %clang %llvm-driver > %t_forward.log // RUN: %clang -flto=thin %s -### --target=x86_64-sie-ps5 \ // RUN: -Xthinlto-distributor=a1 -Xthinlto-distributor=a2,a3 \ // RUN: -fthinlto-distributor=d.exe -Werror >>%t_forward.log 2>&1 // RUN: FileCheck %s --input-file=%t_forward.log --check-prefix=FORWARD -// FORWARD: filename.py:[[CLANG:.*]] -// FORWARD: prospero-lld +// FORWARD: clang-name:[[CLANG:.*]] +// FORWARD-NEXT: prepend-arg:[[PREPEND_ARG:.*]] +// FORWARD: prospero-lld // FORWARD-SAME: "--thinlto-distributor=d.exe" // FORWARD-SAME: "--thinlto-remote-compiler={{[^"]*}}[[CLANG]]" +// FORWARD-SAME: [[PREPEND_ARG]] // FORWARD-SAME: "--thinlto-distributor-arg=a1" // FORWARD-SAME: "--thinlto-distributor-arg=a2" // FORWARD-SAME: "--thinlto-distributor-arg=a3" @@ -30,20 +32,22 @@ /// Check the expected arguments are forwarded by default with only /// --thinlto-distributor=. -// RUN: %python %S/filename.py %clang > %t_default.log +// RUN: %python %S/Inputs/dtlto-helper.py %clang %llvm-driver > %t_default.log // RUN: %clang -flto=thin %s -### --target=x86_64-sie-ps5 \ // RUN: -fthinlto-distributor=d.exe -Werror >>%t_default.log 2>&1 // RUN: FileCheck %s --input-file=%t_default.log --check-prefix=DEFAULT \ // RUN: --implicit-check-not=distributor --implicit-check-not=remote-compiler -// DEFAULT: filename.py:[[CLANG:.*]] -// DEFAULT: prospero-lld +// DEFAULT: clang-name:[[CLANG:.*]] +// DEFAULT-NEXT: prepend-arg:[[PREPEND_ARG:.*]] +// DEFAULT: prospero-lld // DEFAULT-SAME: "--thinlto-distributor=d.exe" // DEFAULT-SAME: "--thinlto-remote-compiler={{[^"]*}}[[CLANG]]" +// DEFAULT-SAME: [[PREPEND_ARG]] /// Check that the arguments are forwarded unconditionally even when the /// compiler is not in LTO mode. -// RUN: %python %S/filename.py %clang > %t_noflto.log +// RUN: %python %S/Inputs/dtlto-helper.py %clang %llvm-driver > %t_noflto.log // RUN: %clang %s -### --target=x86_64-sie-ps5 \ // RUN: -fthinlto-distributor=d.exe -Werror >>%t_noflto.log 2>&1 // RUN: FileCheck %s --input-file=%t_noflto.log --check-prefix=DEFAULT \ diff --git a/lld/COFF/Config.h b/lld/COFF/Config.h index 76b7c1f61cd25..16997e4de780e 100644 --- a/lld/COFF/Config.h +++ b/lld/COFF/Config.h @@ -201,6 +201,9 @@ struct Configuration { // Used for /thinlto-remote-compiler: StringRef dtltoCompiler; + // Used for /thinlto-remote-compiler-prepend-arg: + llvm::SmallVector dtltoCompilerPrependArgs; + // Used for /thinlto-remote-compiler-arg: llvm::SmallVector dtltoCompilerArgs; diff --git a/lld/COFF/Driver.cpp b/lld/COFF/Driver.cpp index 3676b8881016b..0e528de9c3652 100644 --- a/lld/COFF/Driver.cpp +++ b/lld/COFF/Driver.cpp @@ -2113,6 +2113,10 @@ void LinkerDriver::linkerMain(ArrayRef argsArr) { Err(ctx) << "A value must be specified for /thinlto-remote-compiler if " "/thinlto-distributor is specified."; + // Handle /thinlto-remote-compiler-prepend-arg: + config->dtltoCompilerPrependArgs = + args::getStrings(args, OPT_thinlto_remote_compiler_prepend_arg); + // Handle /thinlto-remote-compiler-arg: config->dtltoCompilerArgs = args::getStrings(args, OPT_thinlto_remote_compiler_arg); diff --git a/lld/COFF/LTO.cpp b/lld/COFF/LTO.cpp index a988be610864a..b1efb28347f74 100644 --- a/lld/COFF/LTO.cpp +++ b/lld/COFF/LTO.cpp @@ -118,8 +118,8 @@ BitcodeCompiler::BitcodeCompiler(COFFLinkerContext &c) : ctx(c) { /*ShouldEmitIndexFiles=*/false, /*ShouldEmitImportFiles=*/false, ctx.config.outputFile, ctx.config.dtltoDistributor, ctx.config.dtltoDistributorArgs, - ctx.config.dtltoCompiler, ctx.config.dtltoCompilerArgs, - !ctx.config.saveTempsArgs.empty()); + ctx.config.dtltoCompiler, ctx.config.dtltoCompilerPrependArgs, + ctx.config.dtltoCompilerArgs, !ctx.config.saveTempsArgs.empty()); } else if (ctx.config.thinLTOIndexOnly) { auto OnIndexWrite = [&](StringRef S) { thinIndices.erase(S); }; backend = lto::createWriteIndexesThinBackend( diff --git a/lld/COFF/Options.td b/lld/COFF/Options.td index f3d0eb3356200..d77478fc9c987 100644 --- a/lld/COFF/Options.td +++ b/lld/COFF/Options.td @@ -292,6 +292,9 @@ def thinlto_distributor_arg : P<"thinlto-distributor-arg", def thinlto_remote_compiler : P<"thinlto-remote-compiler", "Compiler for the ThinLTO distributor to invoke for ThinLTO backend " "compilations">; +def thinlto_remote_compiler_prepend_arg : P<"thinlto-remote-compiler-prepend-arg", + "Compiler prepend arguments for the ThinLTO distributor to pass for ThinLTO backend " + "compilations">; def thinlto_remote_compiler_arg : P<"thinlto-remote-compiler-arg", "Compiler arguments for the ThinLTO distributor to pass for ThinLTO backend " "compilations">; diff --git a/lld/ELF/Config.h b/lld/ELF/Config.h index fd57967a1d21f..8ec5a2c04e71c 100644 --- a/lld/ELF/Config.h +++ b/lld/ELF/Config.h @@ -278,6 +278,7 @@ struct Config { llvm::StringRef dtltoDistributor; llvm::SmallVector dtltoDistributorArgs; llvm::StringRef dtltoCompiler; + llvm::SmallVector dtltoCompilerPrependArgs; llvm::SmallVector dtltoCompilerArgs; llvm::SmallVector undefined; llvm::SmallVector dynamicList; diff --git a/lld/ELF/Driver.cpp b/lld/ELF/Driver.cpp index 62f7fffce7dbe..e52d3a0e11113 100644 --- a/lld/ELF/Driver.cpp +++ b/lld/ELF/Driver.cpp @@ -1400,6 +1400,8 @@ static void readConfigs(Ctx &ctx, opt::InputArgList &args) { ctx.arg.dtltoDistributorArgs = args::getStrings(args, OPT_thinlto_distributor_arg); ctx.arg.dtltoCompiler = args.getLastArgValue(OPT_thinlto_remote_compiler_eq); + ctx.arg.dtltoCompilerPrependArgs = + args::getStrings(args, OPT_thinlto_remote_compiler_prepend_arg); ctx.arg.dtltoCompilerArgs = args::getStrings(args, OPT_thinlto_remote_compiler_arg); ctx.arg.dwoDir = args.getLastArgValue(OPT_plugin_opt_dwo_dir_eq); diff --git a/lld/ELF/LTO.cpp b/lld/ELF/LTO.cpp index 8d4a6c9e3a81e..80c6d2482f9fa 100644 --- a/lld/ELF/LTO.cpp +++ b/lld/ELF/LTO.cpp @@ -186,7 +186,8 @@ BitcodeCompiler::BitcodeCompiler(Ctx &ctx) : ctx(ctx) { ctx.arg.thinLTOEmitIndexFiles, ctx.arg.thinLTOEmitImportsFiles, ctx.arg.outputFile, ctx.arg.dtltoDistributor, ctx.arg.dtltoDistributorArgs, ctx.arg.dtltoCompiler, - ctx.arg.dtltoCompilerArgs, !ctx.arg.saveTempsArgs.empty()); + ctx.arg.dtltoCompilerPrependArgs, ctx.arg.dtltoCompilerArgs, + !ctx.arg.saveTempsArgs.empty()); } else { backend = lto::createInProcessThinBackend( llvm::heavyweight_hardware_concurrency(ctx.arg.thinLTOJobs), diff --git a/lld/ELF/Options.td b/lld/ELF/Options.td index 0d6dda4b60d3a..75184de496448 100644 --- a/lld/ELF/Options.td +++ b/lld/ELF/Options.td @@ -725,6 +725,9 @@ defm thinlto_distributor_arg: EEq<"thinlto-distributor-arg", "Arguments to " def thinlto_remote_compiler_eq: JJ<"thinlto-remote-compiler=">, HelpText<"Compiler for the ThinLTO distributor to invoke for ThinLTO backend " "compilations">; +defm thinlto_remote_compiler_prepend_arg: EEq<"thinlto-remote-compiler-prepend-arg", + "Compiler prepend arguments for the ThinLTO distributor to pass for ThinLTO backend " + "compilations">; defm thinlto_remote_compiler_arg: EEq<"thinlto-remote-compiler-arg", "Compiler arguments for the ThinLTO distributor to pass for ThinLTO backend " "compilations">; diff --git a/lld/docs/DTLTO.rst b/lld/docs/DTLTO.rst index 54fcc034d1371..bec24e6fab2c6 100644 --- a/lld/docs/DTLTO.rst +++ b/lld/docs/DTLTO.rst @@ -14,19 +14,23 @@ ELF LLD The command-line interface is as follows: -- ``--thinlto-distributor=`` +- ``--thinlto-distributor=`` Specifies the file to execute as the distributor process. If specified, ThinLTO backend compilations will be distributed. -- ``--thinlto-remote-compiler=`` +- ``--thinlto-remote-compiler=`` Specifies the path to the compiler that the distributor process will use for backend compilations. The compiler invoked must match the version of LLD. -- ``--thinlto-distributor-arg=`` +- ``--thinlto-distributor-arg=`` Specifies ```` on the command line when invoking the distributor. Can be specified multiple times. -- ``--thinlto-remote-compiler-arg=`` +- ``--thinlto-remote-compiler-prepend-arg=`` + Prepends ```` to the remote compiler's command line. + Can be specified multiple times. + +- ``--thinlto-remote-compiler-arg=`` Appends ```` to the remote compiler's command line. Can be specified multiple times. @@ -57,6 +61,10 @@ The command-line interface is as follows: Specifies ```` on the command line when invoking the distributor. Can be specified multiple times. +- ``/thinlto-remote-compiler-prepend-arg:`` + Prepends ```` to the remote compiler's command line. + Can be specified multiple times. + - ``/thinlto-remote-compiler-arg:`` Appends ```` to the remote compiler's command line. Can be specified multiple times. @@ -72,4 +80,4 @@ Currently, other options are silently accepted but do not have the intended effect. Support for such options could be expanded in the future. Currently, there is no DTLTO command line interface supplied for ``clang-cl``, -as users are expected to invoke LLD directly. \ No newline at end of file +as users are expected to invoke LLD directly. diff --git a/llvm/include/llvm/LTO/LTO.h b/llvm/include/llvm/LTO/LTO.h index 000472fe9a3c4..a837cdd95960c 100644 --- a/llvm/include/llvm/LTO/LTO.h +++ b/llvm/include/llvm/LTO/LTO.h @@ -317,6 +317,8 @@ LLVM_ABI ThinBackend createInProcessThinBackend( /// distributor. /// RemoteCompiler specifies the path to a Clang executable to be invoked for /// the backend jobs. +/// RemoteCompilerPrependArgs specifies a list of prepend arguments to be +/// applied to the backend compilations. /// RemoteCompilerArgs specifies a list of arguments to be applied to the /// backend compilations. /// SaveTemps is a debugging tool that prevents temporary files created by this @@ -326,6 +328,7 @@ LLVM_ABI ThinBackend createOutOfProcessThinBackend( bool ShouldEmitIndexFiles, bool ShouldEmitImportsFiles, StringRef LinkerOutputFile, StringRef Distributor, ArrayRef DistributorArgs, StringRef RemoteCompiler, + ArrayRef RemoteCompilerPrependArgs, ArrayRef RemoteCompilerArgs, bool SaveTemps); /// This ThinBackend writes individual module indexes to files, instead of diff --git a/llvm/lib/LTO/LTO.cpp b/llvm/lib/LTO/LTO.cpp index 86780e19f22b8..9d0fa116c85bf 100644 --- a/llvm/lib/LTO/LTO.cpp +++ b/llvm/lib/LTO/LTO.cpp @@ -2224,6 +2224,7 @@ class OutOfProcessThinBackend : public CGThinBackend { ArrayRef DistributorArgs; SString RemoteCompiler; + ArrayRef RemoteCompilerPrependArgs; ArrayRef RemoteCompilerArgs; bool SaveTemps; @@ -2260,12 +2261,14 @@ class OutOfProcessThinBackend : public CGThinBackend { bool ShouldEmitIndexFiles, bool ShouldEmitImportsFiles, StringRef LinkerOutputFile, StringRef Distributor, ArrayRef DistributorArgs, StringRef RemoteCompiler, + ArrayRef RemoteCompilerPrependArgs, ArrayRef RemoteCompilerArgs, bool SaveTemps) : CGThinBackend(Conf, CombinedIndex, ModuleToDefinedGVSummaries, AddStream, OnWrite, ShouldEmitIndexFiles, ShouldEmitImportsFiles, ThinLTOParallelism), LinkerOutputFile(LinkerOutputFile), DistributorPath(Distributor), DistributorArgs(DistributorArgs), RemoteCompiler(RemoteCompiler), + RemoteCompilerPrependArgs(RemoteCompilerPrependArgs), RemoteCompilerArgs(RemoteCompilerArgs), SaveTemps(SaveTemps) {} virtual void setup(unsigned ThinLTONumTasks, unsigned ThinLTOTaskOffset, @@ -2387,6 +2390,11 @@ class OutOfProcessThinBackend : public CGThinBackend { JOS.attributeArray("args", [&]() { JOS.value(RemoteCompiler); + // Forward any supplied prepend options. + if (!RemoteCompilerPrependArgs.empty()) + for (auto &A : RemoteCompilerPrependArgs) + JOS.value(A); + JOS.value("-c"); JOS.value(Saver.save("--target=" + Triple.str())); @@ -2517,6 +2525,7 @@ ThinBackend lto::createOutOfProcessThinBackend( bool ShouldEmitIndexFiles, bool ShouldEmitImportsFiles, StringRef LinkerOutputFile, StringRef Distributor, ArrayRef DistributorArgs, StringRef RemoteCompiler, + ArrayRef RemoteCompilerPrependArgs, ArrayRef RemoteCompilerArgs, bool SaveTemps) { auto Func = [=](const Config &Conf, ModuleSummaryIndex &CombinedIndex, @@ -2526,7 +2535,7 @@ ThinBackend lto::createOutOfProcessThinBackend( Conf, CombinedIndex, Parallelism, ModuleToDefinedGVSummaries, AddStream, OnWrite, ShouldEmitIndexFiles, ShouldEmitImportsFiles, LinkerOutputFile, Distributor, DistributorArgs, RemoteCompiler, - RemoteCompilerArgs, SaveTemps); + RemoteCompilerPrependArgs, RemoteCompilerArgs, SaveTemps); }; return ThinBackend(Func, Parallelism); } diff --git a/llvm/test/ThinLTO/X86/dtlto/json.ll b/llvm/test/ThinLTO/X86/dtlto/json.ll index 1a38438e7b791..ee1c428c31c7c 100644 --- a/llvm/test/ThinLTO/X86/dtlto/json.ll +++ b/llvm/test/ThinLTO/X86/dtlto/json.ll @@ -7,21 +7,33 @@ RUN: rm -rf %t && split-file %s %t && cd %t RUN: opt -thinlto-bc t1.ll -o t1.bc RUN: opt -thinlto-bc t2.ll -o t2.bc -; Perform DTLTO. +; Perform DTLTO with clang. RUN: not llvm-lto2 run t1.bc t2.bc -o my.output \ RUN: -r=t1.bc,t1,px -r=t2.bc,t2,px \ RUN: -dtlto-distributor=%python \ RUN: -dtlto-distributor-arg=%llvm_src_root/utils/dtlto/validate.py,--da1=10,--da2=10 \ RUN: -dtlto-compiler=my_clang.exe \ RUN: -dtlto-compiler-arg=--rota1=10,--rota2=20 \ -RUN: 2>&1 | FileCheck %s +RUN: 2>&1 | FileCheck --check-prefixes=CHECK,CLANG %s + +; Perform DTLTO with LLVM driver. +RUN: not llvm-lto2 run t1.bc t2.bc -o my.output \ +RUN: -r=t1.bc,t1,px -r=t2.bc,t2,px \ +RUN: -dtlto-distributor=%python \ +RUN: -dtlto-distributor-arg=%llvm_src_root/utils/dtlto/validate.py,--da1=10,--da2=10 \ +RUN: -dtlto-compiler=llvm \ +RUN: -dtlto-compiler-prepend-arg=clang \ +RUN: -dtlto-compiler-arg=--rota1=10,--rota2=20 \ +RUN: 2>&1 | FileCheck --check-prefixes=CHECK,LLVM %s CHECK: distributor_args=['--da1=10', '--da2=10'] ; Check the common object. CHECK: "linker_output": "my.output" CHECK: "args": -CHECK-NEXT: "my_clang.exe" +CLANG-NEXT: "my_clang.exe" +LLVM-NEXT: "llvm" +LLVM-NEXT: "clang" CHECK-NEXT: "-c" CHECK-NEXT: "--target=x86_64-unknown-linux-gnu" CHECK-NEXT: "-O2" @@ -30,7 +42,7 @@ CHECK-NEXT: "-Wno-unused-command-line-argument" CHECK-NEXT: "--rota1=10" CHECK-NEXT: "--rota2=20" CHECK-NEXT: ] -CHECK: "inputs": [] +CHECK: "inputs": [] ; Check the first job entry. CHECK: "args": diff --git a/llvm/tools/llvm-lto2/llvm-lto2.cpp b/llvm/tools/llvm-lto2/llvm-lto2.cpp index ff75bb564b1e8..399306f39daeb 100644 --- a/llvm/tools/llvm-lto2/llvm-lto2.cpp +++ b/llvm/tools/llvm-lto2/llvm-lto2.cpp @@ -111,6 +111,12 @@ static cl::opt DTLTOCompiler( "dtlto-compiler", cl::desc("Compiler to use for DTLTO ThinLTO backend compilations.")); +static cl::list DTLTOCompilerPrependArgs( + "dtlto-compiler-prepend-arg", cl::CommaSeparated, + cl::desc("Prepend arguments to pass to the remote compiler for backend " + "compilations."), + cl::value_desc("arg")); + static cl::list DTLTOCompilerArgs( "dtlto-compiler-arg", cl::CommaSeparated, cl::desc("Arguments to pass to the remote compiler for backend " @@ -371,6 +377,9 @@ static int run(int argc, char **argv) { "with -dtlto-distributor\n"; auto DTLTODistributorArgsSV = llvm::to_vector<0>(llvm::map_range( DTLTODistributorArgs, [](const std::string &S) { return StringRef(S); })); + auto DTLTOCompilerPrependArgsSV = llvm::to_vector<0>( + llvm::map_range(DTLTOCompilerPrependArgs, + [](const std::string &S) { return StringRef(S); })); auto DTLTOCompilerArgsSV = llvm::to_vector<0>(llvm::map_range( DTLTOCompilerArgs, [](const std::string &S) { return StringRef(S); })); @@ -388,7 +397,7 @@ static int run(int argc, char **argv) { llvm::heavyweight_hardware_concurrency(Threads), /*OnWrite=*/{}, ThinLTOEmitIndexes, ThinLTOEmitImports, OutputFilename, DTLTODistributor, DTLTODistributorArgsSV, DTLTOCompiler, - DTLTOCompilerArgsSV, SaveTemps); + DTLTOCompilerPrependArgsSV, DTLTOCompilerArgsSV, SaveTemps); } else Backend = createInProcessThinBackend( llvm::heavyweight_hardware_concurrency(Threads), From 6058c0cf4383149e4f0f61a6786d2a4dd6bd301a Mon Sep 17 00:00:00 2001 From: Robert Imschweiler Date: Thu, 23 Oct 2025 17:41:05 +0200 Subject: [PATCH 14/31] [NFC][clang][OpenMP] Cleanup leftover unused CodeGen functions (#164767) --- clang/lib/CodeGen/CGOpenMPRuntime.cpp | 15 --------------- clang/lib/CodeGen/CGOpenMPRuntime.h | 4 ---- 2 files changed, 19 deletions(-) diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.cpp b/clang/lib/CodeGen/CGOpenMPRuntime.cpp index 85b2404cdbdeb..66fea920812c2 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.cpp +++ b/clang/lib/CodeGen/CGOpenMPRuntime.cpp @@ -2712,14 +2712,6 @@ llvm::Value *CGOpenMPRuntime::emitMessageClause(CodeGenFunction &CGF, return CGF.EmitScalarExpr(Message); } -llvm::Value * -CGOpenMPRuntime::emitMessageClause(CodeGenFunction &CGF, - const OMPMessageClause *MessageClause) { - return emitMessageClause( - CGF, MessageClause ? MessageClause->getMessageString() : nullptr, - MessageClause->getBeginLoc()); -} - llvm::Value * CGOpenMPRuntime::emitSeverityClause(OpenMPSeverityClauseKind Severity, SourceLocation Loc) { @@ -2729,13 +2721,6 @@ CGOpenMPRuntime::emitSeverityClause(OpenMPSeverityClauseKind Severity, Severity == OMPC_SEVERITY_warning ? 1 : 2); } -llvm::Value * -CGOpenMPRuntime::emitSeverityClause(const OMPSeverityClause *SeverityClause) { - return emitSeverityClause(SeverityClause ? SeverityClause->getSeverityKind() - : OMPC_SEVERITY_unknown, - SeverityClause->getBeginLoc()); -} - void CGOpenMPRuntime::emitNumThreadsClause( CodeGenFunction &CGF, llvm::Value *NumThreads, SourceLocation Loc, OpenMPNumThreadsClauseModifier Modifier, OpenMPSeverityClauseKind Severity, diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.h b/clang/lib/CodeGen/CGOpenMPRuntime.h index ba76ba6b5f523..6bfd7d6a590b9 100644 --- a/clang/lib/CodeGen/CGOpenMPRuntime.h +++ b/clang/lib/CodeGen/CGOpenMPRuntime.h @@ -1051,13 +1051,9 @@ class CGOpenMPRuntime { virtual llvm::Value *emitMessageClause(CodeGenFunction &CGF, const Expr *Message, SourceLocation Loc); - virtual llvm::Value *emitMessageClause(CodeGenFunction &CGF, - const OMPMessageClause *MessageClause); virtual llvm::Value *emitSeverityClause(OpenMPSeverityClauseKind Severity, SourceLocation Loc); - virtual llvm::Value * - emitSeverityClause(const OMPSeverityClause *SeverityClause); /// Emits call to void __kmpc_push_num_threads(ident_t *loc, kmp_int32 /// global_tid, kmp_int32 num_threads) to generate code for 'num_threads' From c13ac9cadf1f9b4fa886b82d1e84a5feb0439023 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Miko=C5=82aj=20Pir=C3=B3g?= Date: Thu, 23 Oct 2025 18:04:41 +0200 Subject: [PATCH 15/31] [Compiler-rt] Fix wrong assignment in compiler_rt (#164713) The `INTEL_CLEARWATERFOREST` belongs to `ProcessorTypes` enum, but it was assigned to `Subtype` value, leading to cpu_specific/cpu_dispatch not recognizing CWF. The type for `Subtype` and `Type` are changed to respective enums to guard against these sort of errors in the future --- compiler-rt/lib/builtins/cpu_model/x86.c | 30 +++++++++++------------- 1 file changed, 14 insertions(+), 16 deletions(-) diff --git a/compiler-rt/lib/builtins/cpu_model/x86.c b/compiler-rt/lib/builtins/cpu_model/x86.c index 7ddfaa3e3ed6c..d9ff116cdc292 100644 --- a/compiler-rt/lib/builtins/cpu_model/x86.c +++ b/compiler-rt/lib/builtins/cpu_model/x86.c @@ -36,14 +36,14 @@ enum VendorSignatures { SIG_AMD = 0x68747541, // Auth }; -enum ProcessorVendors { +enum ProcessorVendors : unsigned int { VENDOR_INTEL = 1, VENDOR_AMD, VENDOR_OTHER, VENDOR_MAX }; -enum ProcessorTypes { +enum ProcessorTypes : unsigned int { INTEL_BONNELL = 1, INTEL_CORE2, INTEL_COREI7, @@ -319,11 +319,9 @@ static void detectX86FamilyModel(unsigned EAX, unsigned *Family, #define testFeature(F) (Features[F / 32] & (1 << (F % 32))) != 0 -static const char *getIntelProcessorTypeAndSubtype(unsigned Family, - unsigned Model, - const unsigned *Features, - unsigned *Type, - unsigned *Subtype) { +static const char *getIntelProcessorTypeAndSubtype( + unsigned Family, unsigned Model, const unsigned *Features, + enum ProcessorTypes *Type, enum ProcessorSubtypes *Subtype) { // We select CPU strings to match the code in Host.cpp, but we don't use them // in compiler-rt. const char *CPU = 0; @@ -616,8 +614,7 @@ static const char *getIntelProcessorTypeAndSubtype(unsigned Family, // Clearwaterforest: case 0xdd: CPU = "clearwaterforest"; - *Type = INTEL_COREI7; - *Subtype = INTEL_CLEARWATERFOREST; + *Type = INTEL_CLEARWATERFOREST; break; case 0x57: @@ -667,11 +664,9 @@ static const char *getIntelProcessorTypeAndSubtype(unsigned Family, return CPU; } -static const char *getAMDProcessorTypeAndSubtype(unsigned Family, - unsigned Model, - const unsigned *Features, - unsigned *Type, - unsigned *Subtype) { +static const char *getAMDProcessorTypeAndSubtype( + unsigned Family, unsigned Model, const unsigned *Features, + enum ProcessorTypes *Type, enum ProcessorSubtypes *Subtype) { const char *CPU = 0; switch (Family) { @@ -1162,11 +1157,14 @@ __attribute__((visibility("hidden"))) #endif struct __processor_model { unsigned int __cpu_vendor; - unsigned int __cpu_type; - unsigned int __cpu_subtype; + enum ProcessorTypes __cpu_type; + enum ProcessorSubtypes __cpu_subtype; unsigned int __cpu_features[1]; } __cpu_model = {0, 0, 0, {0}}; +static_assert(sizeof(__cpu_model) == 16, + "Wrong size of __cpu_model will result in ABI break"); + #ifndef _WIN32 __attribute__((visibility("hidden"))) #endif From 7ca1472df011a3a7c341f7a866e68b2308d12442 Mon Sep 17 00:00:00 2001 From: Marco Elver Date: Thu, 23 Oct 2025 18:14:33 +0200 Subject: [PATCH 16/31] [Clang] Implement constexpr evaluation for __builtin_infer_alloc_token() (#163639) Implement the constexpr evaluation for `__builtin_infer_alloc_token()` in Clang's constant expression evaluators (both in ExprConstant and the new bytecode interpreter). The constant evaluation is only supported for stateless (hash-based) token modes. If a stateful mode like `increment` is used, the evaluation fails, as the token value is not deterministic at compile time. --- .../include/clang/Basic/DiagnosticASTKinds.td | 6 ++ clang/lib/AST/ByteCode/InterpBuiltin.cpp | 44 +++++++++++++++ clang/lib/AST/ExprConstant.cpp | 22 ++++++++ clang/test/SemaCXX/alloc-token.cpp | 56 +++++++++++++++++++ 4 files changed, 128 insertions(+) diff --git a/clang/include/clang/Basic/DiagnosticASTKinds.td b/clang/include/clang/Basic/DiagnosticASTKinds.td index 0be9146f70364..5c462f9646b3b 100644 --- a/clang/include/clang/Basic/DiagnosticASTKinds.td +++ b/clang/include/clang/Basic/DiagnosticASTKinds.td @@ -403,6 +403,12 @@ def note_constexpr_assumption_failed : Note< def note_constexpr_countzeroes_zero : Note< "evaluation of %select{__builtin_elementwise_clzg|__builtin_elementwise_ctzg}0 " "with a zero value is undefined">; +def note_constexpr_infer_alloc_token_type_inference_failed : Note< + "could not infer allocation type for __builtin_infer_alloc_token">; +def note_constexpr_infer_alloc_token_no_metadata : Note< + "could not get token metadata for inferred type">; +def note_constexpr_infer_alloc_token_stateful_mode : Note< + "stateful alloc token mode not supported in constexpr">; def err_experimental_clang_interp_failed : Error< "the experimental clang interpreter failed to evaluate an expression">; diff --git a/clang/lib/AST/ByteCode/InterpBuiltin.cpp b/clang/lib/AST/ByteCode/InterpBuiltin.cpp index d932a49dd2935..ff50e6dbfb44e 100644 --- a/clang/lib/AST/ByteCode/InterpBuiltin.cpp +++ b/clang/lib/AST/ByteCode/InterpBuiltin.cpp @@ -12,12 +12,14 @@ #include "InterpHelpers.h" #include "PrimType.h" #include "Program.h" +#include "clang/AST/InferAlloc.h" #include "clang/AST/OSLog.h" #include "clang/AST/RecordLayout.h" #include "clang/Basic/Builtins.h" #include "clang/Basic/TargetBuiltins.h" #include "clang/Basic/TargetInfo.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/Support/AllocToken.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/SipHash.h" @@ -1307,6 +1309,45 @@ interp__builtin_ptrauth_string_discriminator(InterpState &S, CodePtr OpPC, return true; } +static bool interp__builtin_infer_alloc_token(InterpState &S, CodePtr OpPC, + const InterpFrame *Frame, + const CallExpr *Call) { + const ASTContext &ASTCtx = S.getASTContext(); + uint64_t BitWidth = ASTCtx.getTypeSize(ASTCtx.getSizeType()); + auto Mode = + ASTCtx.getLangOpts().AllocTokenMode.value_or(llvm::DefaultAllocTokenMode); + uint64_t MaxTokens = + ASTCtx.getLangOpts().AllocTokenMax.value_or(~0ULL >> (64 - BitWidth)); + + // We do not read any of the arguments; discard them. + for (int I = Call->getNumArgs() - 1; I >= 0; --I) + discard(S.Stk, *S.getContext().classify(Call->getArg(I))); + + // Note: Type inference from a surrounding cast is not supported in + // constexpr evaluation. + QualType AllocType = infer_alloc::inferPossibleType(Call, ASTCtx, nullptr); + if (AllocType.isNull()) { + S.CCEDiag(Call, + diag::note_constexpr_infer_alloc_token_type_inference_failed); + return false; + } + + auto ATMD = infer_alloc::getAllocTokenMetadata(AllocType, ASTCtx); + if (!ATMD) { + S.CCEDiag(Call, diag::note_constexpr_infer_alloc_token_no_metadata); + return false; + } + + auto MaybeToken = llvm::getAllocToken(Mode, *ATMD, MaxTokens); + if (!MaybeToken) { + S.CCEDiag(Call, diag::note_constexpr_infer_alloc_token_stateful_mode); + return false; + } + + pushInteger(S, llvm::APInt(BitWidth, *MaybeToken), ASTCtx.getSizeType()); + return true; +} + static bool interp__builtin_operator_new(InterpState &S, CodePtr OpPC, const InterpFrame *Frame, const CallExpr *Call) { @@ -3694,6 +3735,9 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const CallExpr *Call, case Builtin::BI__builtin_ptrauth_string_discriminator: return interp__builtin_ptrauth_string_discriminator(S, OpPC, Frame, Call); + case Builtin::BI__builtin_infer_alloc_token: + return interp__builtin_infer_alloc_token(S, OpPC, Frame, Call); + case Builtin::BI__noop: pushInteger(S, 0, Call->getType()); return true; diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index 7db7a01998a4a..2bd4476b6f3a4 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -44,6 +44,7 @@ #include "clang/AST/CharUnits.h" #include "clang/AST/CurrentSourceLocExprScope.h" #include "clang/AST/Expr.h" +#include "clang/AST/InferAlloc.h" #include "clang/AST/OSLog.h" #include "clang/AST/OptionalDiagnostic.h" #include "clang/AST/RecordLayout.h" @@ -14663,6 +14664,27 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const CallExpr *E, return Success(Result, E); } + case Builtin::BI__builtin_infer_alloc_token: { + // If we fail to infer a type, this fails to be a constant expression; this + // can be checked with __builtin_constant_p(...). + QualType AllocType = infer_alloc::inferPossibleType(E, Info.Ctx, nullptr); + if (AllocType.isNull()) + return Error( + E, diag::note_constexpr_infer_alloc_token_type_inference_failed); + auto ATMD = infer_alloc::getAllocTokenMetadata(AllocType, Info.Ctx); + if (!ATMD) + return Error(E, diag::note_constexpr_infer_alloc_token_no_metadata); + auto Mode = + Info.getLangOpts().AllocTokenMode.value_or(llvm::DefaultAllocTokenMode); + uint64_t BitWidth = Info.Ctx.getTypeSize(Info.Ctx.getSizeType()); + uint64_t MaxTokens = + Info.getLangOpts().AllocTokenMax.value_or(~0ULL >> (64 - BitWidth)); + auto MaybeToken = llvm::getAllocToken(Mode, *ATMD, MaxTokens); + if (!MaybeToken) + return Error(E, diag::note_constexpr_infer_alloc_token_stateful_mode); + return Success(llvm::APInt(BitWidth, *MaybeToken), E); + } + case Builtin::BI__builtin_ffs: case Builtin::BI__builtin_ffsl: case Builtin::BI__builtin_ffsll: { diff --git a/clang/test/SemaCXX/alloc-token.cpp b/clang/test/SemaCXX/alloc-token.cpp index a267442409886..be7acb7d42ef2 100644 --- a/clang/test/SemaCXX/alloc-token.cpp +++ b/clang/test/SemaCXX/alloc-token.cpp @@ -1,11 +1,65 @@ // RUN: %clang_cc1 -triple x86_64-linux-gnu -std=c++23 -fsyntax-only -verify %s // RUN: %clang_cc1 -triple x86_64-linux-gnu -std=c++23 -fsyntax-only -verify %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -triple x86_64-linux-gnu -std=c++23 -fsyntax-only -verify %s -falloc-token-mode=typehash -DMODE_TYPEHASH +// RUN: %clang_cc1 -triple x86_64-linux-gnu -std=c++23 -fsyntax-only -verify %s -falloc-token-max=2 -DTOKEN_MAX=2 #if !__has_builtin(__builtin_infer_alloc_token) #error "missing __builtin_infer_alloc_token" #endif +struct NoPtr { + int x; + long y; +}; + +struct WithPtr { + int a; + char *buf; +}; + +// Check specific known values; these are guaranteed to be stable. +#ifdef MODE_TYPEHASH +static_assert(__builtin_infer_alloc_token(sizeof(int)) == 2689373973731826898ULL); +static_assert(__builtin_infer_alloc_token(sizeof(char*)) == 2250492667400517147ULL); +static_assert(__builtin_infer_alloc_token(sizeof(NoPtr)) == 7465259095297095368ULL); +static_assert(__builtin_infer_alloc_token(sizeof(WithPtr)) == 11898882936532569145ULL); +#elif defined(TOKEN_MAX) +# if TOKEN_MAX == 2 +static_assert(__builtin_infer_alloc_token(sizeof(int)) == 0); +static_assert(__builtin_infer_alloc_token(sizeof(char*)) == 1); +static_assert(__builtin_infer_alloc_token(sizeof(NoPtr)) == 0); +static_assert(__builtin_infer_alloc_token(sizeof(WithPtr)) == 1); +# else +# error "unhandled TOKEN_MAX case" +# endif +#else +static_assert(__builtin_infer_alloc_token(sizeof(int)) == 2689373973731826898ULL); +static_assert(__builtin_infer_alloc_token(sizeof(char*)) == 11473864704255292954ULL); +static_assert(__builtin_infer_alloc_token(sizeof(NoPtr)) == 7465259095297095368ULL); +static_assert(__builtin_infer_alloc_token(sizeof(WithPtr)) == 11898882936532569145ULL); +#endif + +// Template function. +template +constexpr unsigned long get_token() { + return __builtin_infer_alloc_token(sizeof(T)); +} +static_assert(__builtin_infer_alloc_token(sizeof(int)) == get_token()); + +// Test complex expressions. +static_assert(__builtin_constant_p(__builtin_infer_alloc_token(sizeof(int)))); +static_assert(__builtin_infer_alloc_token(sizeof(NoPtr) * 2, 1) == get_token()); +static_assert(__builtin_infer_alloc_token(1, 4 + sizeof(NoPtr)) == get_token()); +static_assert(__builtin_infer_alloc_token(sizeof(NoPtr) << 8) == get_token()); + +// Test usable as a template param. +template +struct token_for_type { + static_assert(ID == get_token()); + static constexpr unsigned long value = ID; +}; +static_assert(token_for_type<__builtin_infer_alloc_token(sizeof(int)), int>::value == get_token()); + template void template_test() { __builtin_infer_alloc_token(T()); // no error if not instantiated @@ -20,4 +74,6 @@ void negative_tests() { __builtin_infer_alloc_token(); // expected-error {{too few arguments to function call}} __builtin_infer_alloc_token((void)0); // expected-error {{argument may not have 'void' type}} negative_template_test(); // expected-note {{in instantiation of function template specialization 'negative_template_test' requested here}} + constexpr auto inference_fail = __builtin_infer_alloc_token(123); // expected-error {{must be initialized by a constant expression}} \ + // expected-note {{could not infer allocation type for __builtin_infer_alloc_token}} } From 213b8a9f18742b2327be177b34eba42d4aedcc4c Mon Sep 17 00:00:00 2001 From: Rahul Joshi Date: Thu, 23 Oct 2025 09:15:24 -0700 Subject: [PATCH 17/31] [NFC][LLVM] Namespace cleanup in MergeICmps (#163761) --- llvm/lib/Transforms/Scalar/MergeICmps.cpp | 34 +++++++++++++---------- 1 file changed, 19 insertions(+), 15 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/MergeICmps.cpp b/llvm/lib/Transforms/Scalar/MergeICmps.cpp index a83cbd17a70dc..f273e9d90e71e 100644 --- a/llvm/lib/Transforms/Scalar/MergeICmps.cpp +++ b/llvm/lib/Transforms/Scalar/MergeICmps.cpp @@ -64,10 +64,10 @@ using namespace llvm; -namespace { - #define DEBUG_TYPE "mergeicmps" +namespace { + // A BCE atom "Binary Compare Expression Atom" represents an integer load // that is a constant offset from a base value, e.g. `a` or `o.c` in the example // at the top. @@ -128,11 +128,12 @@ class BaseIdentifier { unsigned Order = 1; DenseMap BaseToIndex; }; +} // namespace // If this value is a load from a constant offset w.r.t. a base address, and // there are no other users of the load or address, returns the base address and // the offset. -BCEAtom visitICmpLoadOperand(Value *const Val, BaseIdentifier &BaseId) { +static BCEAtom visitICmpLoadOperand(Value *const Val, BaseIdentifier &BaseId) { auto *const LoadI = dyn_cast(Val); if (!LoadI) return {}; @@ -175,6 +176,7 @@ BCEAtom visitICmpLoadOperand(Value *const Val, BaseIdentifier &BaseId) { return BCEAtom(GEP, LoadI, BaseId.getBaseId(Base), Offset); } +namespace { // A comparison between two BCE atoms, e.g. `a == o.a` in the example at the // top. // Note: the terminology is misleading: the comparison is symmetric, so there @@ -239,6 +241,7 @@ class BCECmpBlock { private: BCECmp Cmp; }; +} // namespace bool BCECmpBlock::canSinkBCECmpInst(const Instruction *Inst, AliasAnalysis &AA) const { @@ -302,9 +305,9 @@ bool BCECmpBlock::doesOtherWork() const { // Visit the given comparison. If this is a comparison between two valid // BCE atoms, returns the comparison. -std::optional visitICmp(const ICmpInst *const CmpI, - const ICmpInst::Predicate ExpectedPredicate, - BaseIdentifier &BaseId) { +static std::optional +visitICmp(const ICmpInst *const CmpI, + const ICmpInst::Predicate ExpectedPredicate, BaseIdentifier &BaseId) { // The comparison can only be used once: // - For intermediate blocks, as a branch condition. // - For the final block, as an incoming value for the Phi. @@ -332,10 +335,9 @@ std::optional visitICmp(const ICmpInst *const CmpI, // Visit the given comparison block. If this is a comparison between two valid // BCE atoms, returns the comparison. -std::optional visitCmpBlock(Value *const Val, - BasicBlock *const Block, - const BasicBlock *const PhiBlock, - BaseIdentifier &BaseId) { +static std::optional +visitCmpBlock(Value *const Val, BasicBlock *const Block, + const BasicBlock *const PhiBlock, BaseIdentifier &BaseId) { if (Block->empty()) return std::nullopt; auto *const BranchI = dyn_cast(Block->getTerminator()); @@ -397,6 +399,7 @@ static inline void enqueueBlock(std::vector &Comparisons, Comparisons.push_back(std::move(Comparison)); } +namespace { // A chain of comparisons. class BCECmpChain { public: @@ -420,6 +423,7 @@ class BCECmpChain { // The original entry block (before sorting); BasicBlock *EntryBlock_; }; +} // namespace static bool areContiguous(const BCECmpBlock &First, const BCECmpBlock &Second) { return First.Lhs().BaseId == Second.Lhs().BaseId && @@ -742,9 +746,8 @@ bool BCECmpChain::simplify(const TargetLibraryInfo &TLI, AliasAnalysis &AA, return true; } -std::vector getOrderedBlocks(PHINode &Phi, - BasicBlock *const LastBlock, - int NumBlocks) { +static std::vector +getOrderedBlocks(PHINode &Phi, BasicBlock *const LastBlock, int NumBlocks) { // Walk up from the last block to find other blocks. std::vector Blocks(NumBlocks); assert(LastBlock && "invalid last block"); @@ -777,8 +780,8 @@ std::vector getOrderedBlocks(PHINode &Phi, return Blocks; } -bool processPhi(PHINode &Phi, const TargetLibraryInfo &TLI, AliasAnalysis &AA, - DomTreeUpdater &DTU) { +static bool processPhi(PHINode &Phi, const TargetLibraryInfo &TLI, + AliasAnalysis &AA, DomTreeUpdater &DTU) { LLVM_DEBUG(dbgs() << "processPhi()\n"); if (Phi.getNumIncomingValues() <= 1) { LLVM_DEBUG(dbgs() << "skip: only one incoming value in phi\n"); @@ -874,6 +877,7 @@ static bool runImpl(Function &F, const TargetLibraryInfo &TLI, return MadeChange; } +namespace { class MergeICmpsLegacyPass : public FunctionPass { public: static char ID; From 71b21b5391b267f10c8222fbbe73494fbce6dd86 Mon Sep 17 00:00:00 2001 From: Amr Hesham Date: Thu, 23 Oct 2025 18:20:23 +0200 Subject: [PATCH 18/31] [CIR] Move alloca from cir.try to the surrounding cir.scope (#164488) Upstream moving the allocas from cir.try block to the surrounding cir.scope Issue https://github.com/llvm/llvm-project/issues/154992 --- clang/lib/CIR/CodeGen/CIRGenExpr.cpp | 6 +++- clang/test/CIR/CodeGen/try-catch.cpp | 47 ++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenExpr.cpp b/clang/lib/CIR/CodeGen/CIRGenExpr.cpp index 9df88ad320212..df6ee56eac30b 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExpr.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExpr.cpp @@ -2065,7 +2065,11 @@ mlir::Value CIRGenFunction::emitAlloca(StringRef name, mlir::Type ty, // a surrounding cir.scope, make sure the alloca ends up in the surrounding // scope instead. This is necessary in order to guarantee all SSA values are // reachable during cleanups. - assert(!cir::MissingFeatures::tryOp()); + if (auto tryOp = + llvm::dyn_cast_if_present(entryBlock->getParentOp())) { + if (auto scopeOp = llvm::dyn_cast(tryOp->getParentOp())) + entryBlock = &scopeOp.getScopeRegion().front(); + } return emitAlloca(name, ty, loc, alignment, builder.getBestAllocaInsertPoint(entryBlock), arraySize); diff --git a/clang/test/CIR/CodeGen/try-catch.cpp b/clang/test/CIR/CodeGen/try-catch.cpp index 5a503102d13df..1e4d2a63ada01 100644 --- a/clang/test/CIR/CodeGen/try-catch.cpp +++ b/clang/test/CIR/CodeGen/try-catch.cpp @@ -117,3 +117,50 @@ void try_catch_with_empty_catch_all_2() { // OGCG: %[[RESULT:.*]] = add nsw i32 %[[TMP_A]], 1 // OGCG: store i32 %[[RESULT]], ptr %[[A_ADDR]], align 4 // OGCG: ret void + +void try_catch_with_alloca() { + try { + int a; + int b; + int c = a + b; + } catch (...) { + } +} + +// CIR: cir.scope { +// CIR: %[[A_ADDR:.*]] = cir.alloca !s32i, !cir.ptr, ["a"] +// CIR: %[[B_ADDR:.*]] = cir.alloca !s32i, !cir.ptr, ["b"] +// CIR: %[[C_ADDR:.*]] = cir.alloca !s32i, !cir.ptr, ["c", init] +// CIR: cir.try { +// CIR: %[[TMP_A:.*]] = cir.load{{.*}} %[[A_ADDR]] : !cir.ptr, !s32i +// CIR: %[[TMP_B:.*]] = cir.load{{.*}} %[[B_ADDR]] : !cir.ptr, !s32i +// CIR: %[[RESULT:.*]] = cir.binop(add, %[[TMP_A]], %[[TMP_B]]) nsw : !s32i +// CIR: cir.store{{.*}} %[[RESULT]], %[[C_ADDR]] : !s32i, !cir.ptr +// CIR: cir.yield +// CIR: } +// CIR: } + +// LLVM: %[[A_ADDR:.*]] = alloca i32, i64 1, align 4 +// LLVM: %[[B_ADDR:.*]] = alloca i32, i64 1, align 4 +// LLVM: %[[C_ADDR:.*]] = alloca i32, i64 1, align 4 +// LLVM: br label %[[LABEL_1:.*]] +// LLVM: [[LABEL_1]]: +// LLVM: br label %[[LABEL_2:.*]] +// LLVM: [[LABEL_2]]: +// LLVM: %[[TMP_A:.*]] = load i32, ptr %[[A_ADDR]], align 4 +// LLVM: %[[TMP_B:.*]] = load i32, ptr %[[B_ADDR]], align 4 +// LLVM: %[[RESULT:.*]] = add nsw i32 %[[TMP_A]], %[[TMP_B]] +// LLVM: store i32 %[[RESULT]], ptr %[[C_ADDR]], align 4 +// LLVM: br label %[[LABEL_3:.*]] +// LLVM: [[LABEL_3]]: +// LLVM: br label %[[LABEL_4:.*]] +// LLVM: [[LABEL_4]]: +// LLVM: ret void + +// OGCG: %[[A_ADDR:.*]] = alloca i32, align 4 +// OGCG: %[[B_ADDR:.*]] = alloca i32, align 4 +// OGCG: %[[C_ADDR:.*]] = alloca i32, align 4 +// OGCG: %[[TMP_A:.*]] = load i32, ptr %[[A_ADDR]], align 4 +// OGCG: %[[TMP_B:.*]] = load i32, ptr %[[B_ADDR]], align 4 +// OGCG: %[[RESULT:.*]] = add nsw i32 %[[TMP_A]], %[[TMP_B]] +// OGCG: store i32 %[[RESULT]], ptr %[[C_ADDR]], align 4 From 7731156f30c6e7731e08b4ff52d262be10f93b16 Mon Sep 17 00:00:00 2001 From: Matheus Izvekov Date: Thu, 23 Oct 2025 13:37:59 -0300 Subject: [PATCH 19/31] [clang] OpenMP: fix variant template mismatch crash (#164511) This ammends the fix commited in https://reviews.llvm.org/D109770 / 6cf6fa6ef1c28 Comparing the number of template parameter lists with the number of template parameters is obviously wrong. Even then, the number of parameters being the same doesn't mean the templates are compatible. This change compares if the template parameters are actually equivalent. This fixes the crash, but I am not sure what is the design and intention here, this openmp template support looks too fragile. The added test case still doesn't work, but at least we don't crash now. --- clang/lib/Sema/SemaOpenMP.cpp | 4 +++- .../openmp-begin-declare-variant_template.cpp | 12 ++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 clang/test/SemaOpenMP/openmp-begin-declare-variant_template.cpp diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 5b5b1b685e153..6d5cb0fcaea24 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -7246,7 +7246,9 @@ void SemaOpenMP::ActOnStartOfFunctionDefinitionInOpenMPDeclareVariantScope( FunctionDecl *UDecl = nullptr; if (IsTemplated && isa(CandidateDecl)) { auto *FTD = cast(CandidateDecl); - if (FTD->getTemplateParameters()->size() == TemplateParamLists.size()) + // FIXME: Should this compare the template parameter lists on all levels? + if (SemaRef.Context.isSameTemplateParameterList( + FTD->getTemplateParameters(), TemplateParamLists.back())) UDecl = FTD->getTemplatedDecl(); } else if (!IsTemplated) UDecl = dyn_cast(CandidateDecl); diff --git a/clang/test/SemaOpenMP/openmp-begin-declare-variant_template.cpp b/clang/test/SemaOpenMP/openmp-begin-declare-variant_template.cpp new file mode 100644 index 0000000000000..ded8f58253540 --- /dev/null +++ b/clang/test/SemaOpenMP/openmp-begin-declare-variant_template.cpp @@ -0,0 +1,12 @@ +// RUN: %clang_cc1 -triple x86_64 -fopenmp -verify %s + +// FIXME: Is this supposed to work? + +#pragma omp begin declare variant match(implementation={extension(allow_templates)}) +template void f(T) {} +// expected-note@-1 {{explicit instantiation refers here}} +#pragma end +template struct A {}; +template A f() = delete; +template void f(float); +// expected-error@-1 {{explicit instantiation of undefined function template 'f'}} From d8d80b659a2b36cda574733abe5446c9f9773524 Mon Sep 17 00:00:00 2001 From: wdx727 Date: Fri, 24 Oct 2025 00:38:12 +0800 Subject: [PATCH 20/31] Adding Matching and Inference Functionality to Propeller-PR2 (#162963) Adding Matching and Inference Functionality to Propeller. For detailed information, please refer to the following RFC: https://discourse.llvm.org/t/rfc-adding-matching-and-inference-functionality-to-propeller/86238. This is the second PR, which includes the calculation of basic block hashes and their emission to the ELF file. It is associated with the previous PR at https://github.com/llvm/llvm-project/pull/160706. co-authors: lifengxiang1025 [lifengxiang@kuaishou.com](mailto:lifengxiang@kuaishou.com); zcfh [wuminghui03@kuaishou.com](mailto:wuminghui03@kuaishou.com) Co-authored-by: lifengxiang1025 Co-authored-by: zcfh Co-authored-by: Rahman Lavaee --- llvm/docs/Extensions.rst | 31 ++++- .../llvm/CodeGen/MachineBlockHashInfo.h | 114 +++++++++++++++++ llvm/include/llvm/CodeGen/Passes.h | 3 + llvm/include/llvm/InitializePasses.h | 1 + llvm/include/llvm/MC/MCContext.h | 2 +- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp | 21 +++- llvm/lib/CodeGen/CMakeLists.txt | 1 + llvm/lib/CodeGen/MachineBlockHashInfo.cpp | 115 ++++++++++++++++++ llvm/lib/CodeGen/TargetPassConfig.cpp | 8 ++ .../basic-block-address-map-empty-function.ll | 2 +- ...sic-block-address-map-function-sections.ll | 6 +- .../basic-block-address-map-pgo-features.ll | 2 +- ...k-address-map-with-basic-block-sections.ll | 2 +- ...sic-block-address-map-with-emit-bb-hash.ll | 94 ++++++++++++++ .../X86/basic-block-address-map-with-mfs.ll | 2 +- .../CodeGen/X86/basic-block-address-map.ll | 2 +- 16 files changed, 390 insertions(+), 16 deletions(-) create mode 100644 llvm/include/llvm/CodeGen/MachineBlockHashInfo.h create mode 100644 llvm/lib/CodeGen/MachineBlockHashInfo.cpp create mode 100644 llvm/test/CodeGen/X86/basic-block-address-map-with-emit-bb-hash.ll diff --git a/llvm/docs/Extensions.rst b/llvm/docs/Extensions.rst index 214323e4efc02..91a3ac05ef0e5 100644 --- a/llvm/docs/Extensions.rst +++ b/llvm/docs/Extensions.rst @@ -416,7 +416,36 @@ as offsets relative to prior addresses. The following versioning schemes are currently supported (newer versions support features of the older versions). -Version 3 (newest): Capable of encoding callsite offsets. Enabled by the 6th bit +Version 4 (newest): Capable of encoding basic block hashes. This feature is +enabled by the 7th bit of the feature byte. + +Example: + +.. code-block:: gas + + .section ".llvm_bb_addr_map","",@llvm_bb_addr_map + .byte 4 # version number + .byte 96 # feature byte + .quad .Lfunc_begin0 # address of the function + .byte 2 # number of basic blocks + # BB record for BB_0 + .byte 0 # BB_0 ID + .uleb128 .Lfunc_begin0-.Lfunc_begin0 # BB_0 offset relative to function entry (always zero) + .byte 0 # number of callsites in this block + .uleb128 .LBB_END0_0-.Lfunc_begin0 # BB_0 size + .byte x # BB_0 metadata + .quad 9080480745856761856 # BB_0 hash + # BB record for BB_1 + .byte 1 # BB_1 ID + .uleb128 .LBB0_1-.LBB_END0_0 # BB_1 offset relative to the end of last block (BB_0). + .byte 2 # number of callsites in this block + .uleb128 .LBB0_1_CS0-.LBB0_1 # offset of callsite end relative to the previous offset (.LBB0_1) + .uleb128 .LBB0_1_CS1-.LBB0_1_CS0 # offset of callsite end relative to the previous offset (.LBB0_1_CS0) + .uleb128 .LBB_END0_1-.LBB0_1_CS1 # BB_1 size offset (Offset of the block end relative to the previous offset). + .byte y # BB_1 metadata + .quad 2363478788702666771 # BB_1 hash + +Version 3: Capable of encoding callsite offsets. Enabled by the 6th bit of the feature byte. Example: diff --git a/llvm/include/llvm/CodeGen/MachineBlockHashInfo.h b/llvm/include/llvm/CodeGen/MachineBlockHashInfo.h new file mode 100644 index 0000000000000..d044d5f940b75 --- /dev/null +++ b/llvm/include/llvm/CodeGen/MachineBlockHashInfo.h @@ -0,0 +1,114 @@ +//===- llvm/CodeGen/MachineBlockHashInfo.h ----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Compute the hashes of basic blocks. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_MACHINEBLOCKHASHINFO_H +#define LLVM_CODEGEN_MACHINEBLOCKHASHINFO_H + +#include "llvm/CodeGen/MachineFunctionPass.h" + +namespace llvm { + +/// An object wrapping several components of a basic block hash. The combined +/// (blended) hash is represented and stored as one uint64_t, while individual +/// components are of smaller size (e.g., uint16_t or uint8_t). +struct BlendedBlockHash { +public: + explicit BlendedBlockHash(uint16_t Offset, uint16_t OpcodeHash, + uint16_t InstrHash, uint16_t NeighborHash) + : Offset(Offset), OpcodeHash(OpcodeHash), InstrHash(InstrHash), + NeighborHash(NeighborHash) {} + + explicit BlendedBlockHash(uint64_t CombinedHash) { + Offset = CombinedHash & 0xffff; + CombinedHash >>= 16; + OpcodeHash = CombinedHash & 0xffff; + CombinedHash >>= 16; + InstrHash = CombinedHash & 0xffff; + CombinedHash >>= 16; + NeighborHash = CombinedHash & 0xffff; + } + + /// Combine the blended hash into uint64_t. + uint64_t combine() const { + uint64_t Hash = 0; + Hash |= uint64_t(NeighborHash); + Hash <<= 16; + Hash |= uint64_t(InstrHash); + Hash <<= 16; + Hash |= uint64_t(OpcodeHash); + Hash <<= 16; + Hash |= uint64_t(Offset); + return Hash; + } + + /// Compute a distance between two given blended hashes. The smaller the + /// distance, the more similar two blocks are. For identical basic blocks, + /// the distance is zero. + /// Since OpcodeHash is highly stable, we consider a match good only if + /// the OpcodeHashes are identical. Mismatched OpcodeHashes lead to low + /// matching accuracy, and poor matches undermine the quality of final + /// inference. Notably, during inference, we also consider the matching + /// ratio of basic blocks. For MachineFunctions with a low matching + /// ratio, we directly skip optimization to reduce the impact of + /// mismatches. This ensures even very poor profiles won’t cause negative + /// optimization. + /// In the context of matching, we consider NeighborHash to be more + /// important. This is especially true when accounting for inlining + /// scenarios, where the position of a basic block in the control + /// flow graph is more critical. + uint64_t distance(const BlendedBlockHash &BBH) const { + assert(OpcodeHash == BBH.OpcodeHash && + "incorrect blended hash distance computation"); + uint64_t Dist = 0; + // Account for NeighborHash + Dist += NeighborHash == BBH.NeighborHash ? 0 : 1; + Dist <<= 16; + // Account for InstrHash + Dist += InstrHash == BBH.InstrHash ? 0 : 1; + Dist <<= 16; + // Account for Offset + Dist += (Offset >= BBH.Offset ? Offset - BBH.Offset : BBH.Offset - Offset); + return Dist; + } + +private: + /// The offset of the basic block from the function start. + uint16_t Offset{0}; + /// Hash of the basic block instructions, excluding operands. + uint16_t OpcodeHash{0}; + /// Hash of the basic block instructions, including opcodes and + /// operands. + uint16_t InstrHash{0}; + /// OpcodeHash of the basic block together with OpcodeHashes of its + /// successors and predecessors. + uint16_t NeighborHash{0}; +}; + +class MachineBlockHashInfo : public MachineFunctionPass { + DenseMap MBBHashInfo; + +public: + static char ID; + MachineBlockHashInfo(); + + StringRef getPassName() const override { return "Basic Block Hash Compute"; } + + void getAnalysisUsage(AnalysisUsage &AU) const override; + + bool runOnMachineFunction(MachineFunction &F) override; + + uint64_t getMBBHash(const MachineBasicBlock &MBB); +}; + +} // end namespace llvm + +#endif // LLVM_CODEGEN_MACHINEBLOCKHASHINFO_H diff --git a/llvm/include/llvm/CodeGen/Passes.h b/llvm/include/llvm/CodeGen/Passes.h index 7fae550d8d170..9fddd47b18965 100644 --- a/llvm/include/llvm/CodeGen/Passes.h +++ b/llvm/include/llvm/CodeGen/Passes.h @@ -69,6 +69,9 @@ LLVM_ABI MachineFunctionPass *createBasicBlockSectionsPass(); LLVM_ABI MachineFunctionPass *createBasicBlockPathCloningPass(); +/// createMachineBlockHashInfoPass - This pass computes basic block hashes. +LLVM_ABI MachineFunctionPass *createMachineBlockHashInfoPass(); + /// createMachineFunctionSplitterPass - This pass splits machine functions /// using profile information. LLVM_ABI MachineFunctionPass *createMachineFunctionSplitterPass(); diff --git a/llvm/include/llvm/InitializePasses.h b/llvm/include/llvm/InitializePasses.h index d507ba267d791..581b4ad161daa 100644 --- a/llvm/include/llvm/InitializePasses.h +++ b/llvm/include/llvm/InitializePasses.h @@ -62,6 +62,7 @@ LLVM_ABI void initializeBasicBlockSectionsPass(PassRegistry &); LLVM_ABI void initializeBarrierNoopPass(PassRegistry &); LLVM_ABI void initializeBasicAAWrapperPassPass(PassRegistry &); LLVM_ABI void initializeBlockFrequencyInfoWrapperPassPass(PassRegistry &); +LLVM_ABI void initializeMachineBlockHashInfoPass(PassRegistry &); LLVM_ABI void initializeBranchFolderLegacyPass(PassRegistry &); LLVM_ABI void initializeBranchProbabilityInfoWrapperPassPass(PassRegistry &); LLVM_ABI void initializeBranchRelaxationLegacyPass(PassRegistry &); diff --git a/llvm/include/llvm/MC/MCContext.h b/llvm/include/llvm/MC/MCContext.h index 4a528eecfc900..74abe3403bbed 100644 --- a/llvm/include/llvm/MC/MCContext.h +++ b/llvm/include/llvm/MC/MCContext.h @@ -175,7 +175,7 @@ class MCContext { unsigned GetInstance(unsigned LocalLabelVal); /// SHT_LLVM_BB_ADDR_MAP version to emit. - uint8_t BBAddrMapVersion = 3; + uint8_t BBAddrMapVersion = 4; /// The file name of the log file from the environment variable /// AS_SECURE_LOG_FILE. Which must be set before the .secure_log_unique diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp index fefde64fd1806..8aa488f0efd8f 100644 --- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp +++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp @@ -41,6 +41,7 @@ #include "llvm/CodeGen/GCMetadataPrinter.h" #include "llvm/CodeGen/LazyMachineBlockFrequencyInfo.h" #include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/CodeGen/MachineBlockHashInfo.h" #include "llvm/CodeGen/MachineBranchProbabilityInfo.h" #include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineDominators.h" @@ -184,6 +185,8 @@ static cl::opt PrintLatency( cl::desc("Print instruction latencies as verbose asm comments"), cl::Hidden, cl::init(false)); +extern cl::opt EmitBBHash; + STATISTIC(EmittedInsts, "Number of machine instrs printed"); char AsmPrinter::ID = 0; @@ -474,6 +477,8 @@ void AsmPrinter::getAnalysisUsage(AnalysisUsage &AU) const { AU.addRequired(); AU.addRequired(); AU.addRequired(); + if (EmitBBHash) + AU.addRequired(); } bool AsmPrinter::doInitialization(Module &M) { @@ -1434,14 +1439,11 @@ getBBAddrMapFeature(const MachineFunction &MF, int NumMBBSectionRanges, "BB entries info is required for BBFreq and BrProb " "features"); } - return {FuncEntryCountEnabled, - BBFreqEnabled, - BrProbEnabled, + return {FuncEntryCountEnabled, BBFreqEnabled, BrProbEnabled, MF.hasBBSections() && NumMBBSectionRanges > 1, // Use static_cast to avoid breakage of tests on windows. - static_cast(BBAddrMapSkipEmitBBEntries), - HasCalls, - false}; + static_cast(BBAddrMapSkipEmitBBEntries), HasCalls, + static_cast(EmitBBHash)}; } void AsmPrinter::emitBBAddrMapSection(const MachineFunction &MF) { @@ -1500,6 +1502,9 @@ void AsmPrinter::emitBBAddrMapSection(const MachineFunction &MF) { PrevMBBEndSymbol = MBBSymbol; } + auto MBHI = + Features.BBHash ? &getAnalysis() : nullptr; + if (!Features.OmitBBEntries) { OutStreamer->AddComment("BB id"); // Emit the BB ID for this basic block. @@ -1527,6 +1532,10 @@ void AsmPrinter::emitBBAddrMapSection(const MachineFunction &MF) { emitLabelDifferenceAsULEB128(MBB.getEndSymbol(), CurrentLabel); // Emit the Metadata. OutStreamer->emitULEB128IntValue(getBBAddrMapMetadata(MBB)); + // Emit the Hash. + if (MBHI) { + OutStreamer->emitInt64(MBHI->getMBBHash(MBB)); + } } PrevMBBEndSymbol = MBB.getEndSymbol(); } diff --git a/llvm/lib/CodeGen/CMakeLists.txt b/llvm/lib/CodeGen/CMakeLists.txt index b6872605e22aa..4373c5397a3c6 100644 --- a/llvm/lib/CodeGen/CMakeLists.txt +++ b/llvm/lib/CodeGen/CMakeLists.txt @@ -108,6 +108,7 @@ add_llvm_component_library(LLVMCodeGen LowerEmuTLS.cpp MachineBasicBlock.cpp MachineBlockFrequencyInfo.cpp + MachineBlockHashInfo.cpp MachineBlockPlacement.cpp MachineBranchProbabilityInfo.cpp MachineCFGPrinter.cpp diff --git a/llvm/lib/CodeGen/MachineBlockHashInfo.cpp b/llvm/lib/CodeGen/MachineBlockHashInfo.cpp new file mode 100644 index 0000000000000..c4d9c0f27fbf9 --- /dev/null +++ b/llvm/lib/CodeGen/MachineBlockHashInfo.cpp @@ -0,0 +1,115 @@ +//===- llvm/CodeGen/MachineBlockHashInfo.cpp---------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Compute the hashes of basic blocks. +// +//===----------------------------------------------------------------------===// + +#include "llvm/CodeGen/MachineBlockHashInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/InitializePasses.h" +#include "llvm/Target/TargetMachine.h" + +using namespace llvm; + +uint64_t hashBlock(const MachineBasicBlock &MBB, bool HashOperands) { + uint64_t Hash = 0; + for (const MachineInstr &MI : MBB) { + if (MI.isMetaInstruction() || MI.isTerminator()) + continue; + Hash = hashing::detail::hash_16_bytes(Hash, MI.getOpcode()); + if (HashOperands) { + for (unsigned i = 0; i < MI.getNumOperands(); i++) { + Hash = + hashing::detail::hash_16_bytes(Hash, hash_value(MI.getOperand(i))); + } + } + } + return Hash; +} + +/// Fold a 64-bit integer to a 16-bit one. +uint16_t fold_64_to_16(const uint64_t Value) { + uint16_t Res = static_cast(Value); + Res ^= static_cast(Value >> 16); + Res ^= static_cast(Value >> 32); + Res ^= static_cast(Value >> 48); + return Res; +} + +INITIALIZE_PASS(MachineBlockHashInfo, "machine-block-hash", + "Machine Block Hash Analysis", true, true) + +char MachineBlockHashInfo::ID = 0; + +MachineBlockHashInfo::MachineBlockHashInfo() : MachineFunctionPass(ID) { + initializeMachineBlockHashInfoPass(*PassRegistry::getPassRegistry()); +} + +void MachineBlockHashInfo::getAnalysisUsage(AnalysisUsage &AU) const { + AU.setPreservesAll(); + MachineFunctionPass::getAnalysisUsage(AU); +} + +struct CollectHashInfo { + uint64_t Offset; + uint64_t OpcodeHash; + uint64_t InstrHash; + uint64_t NeighborHash; +}; + +bool MachineBlockHashInfo::runOnMachineFunction(MachineFunction &F) { + DenseMap HashInfos; + uint16_t Offset = 0; + // Initialize hash components + for (const MachineBasicBlock &MBB : F) { + // offset of the machine basic block + HashInfos[&MBB].Offset = Offset; + Offset += MBB.size(); + // Hashing opcodes + HashInfos[&MBB].OpcodeHash = hashBlock(MBB, /*HashOperands=*/false); + // Hash complete instructions + HashInfos[&MBB].InstrHash = hashBlock(MBB, /*HashOperands=*/true); + } + + // Initialize neighbor hash + for (const MachineBasicBlock &MBB : F) { + uint64_t Hash = HashInfos[&MBB].OpcodeHash; + // Append hashes of successors + for (const MachineBasicBlock *SuccMBB : MBB.successors()) { + uint64_t SuccHash = HashInfos[SuccMBB].OpcodeHash; + Hash = hashing::detail::hash_16_bytes(Hash, SuccHash); + } + // Append hashes of predecessors + for (const MachineBasicBlock *PredMBB : MBB.predecessors()) { + uint64_t PredHash = HashInfos[PredMBB].OpcodeHash; + Hash = hashing::detail::hash_16_bytes(Hash, PredHash); + } + HashInfos[&MBB].NeighborHash = Hash; + } + + // Assign hashes + for (const MachineBasicBlock &MBB : F) { + const auto &HashInfo = HashInfos[&MBB]; + BlendedBlockHash BlendedHash(fold_64_to_16(HashInfo.Offset), + fold_64_to_16(HashInfo.OpcodeHash), + fold_64_to_16(HashInfo.InstrHash), + fold_64_to_16(HashInfo.NeighborHash)); + MBBHashInfo[&MBB] = BlendedHash.combine(); + } + + return false; +} + +uint64_t MachineBlockHashInfo::getMBBHash(const MachineBasicBlock &MBB) { + return MBBHashInfo[&MBB]; +} + +MachineFunctionPass *llvm::createMachineBlockHashInfoPass() { + return new MachineBlockHashInfo(); +} diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index b6169e6c4dc34..10b723887b21f 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -272,6 +272,12 @@ static cl::opt cl::desc("Split static data sections into hot and cold " "sections using profile information")); +cl::opt EmitBBHash( + "emit-bb-hash", + cl::desc( + "Emit the hash of basic block in the SHT_LLVM_BB_ADDR_MAP section."), + cl::init(false), cl::Optional); + /// Allow standard passes to be disabled by command line options. This supports /// simple binary flags that either suppress the pass or do nothing. /// i.e. -disable-mypass=false has no effect. @@ -1281,6 +1287,8 @@ void TargetPassConfig::addMachinePasses() { // address map (or both). if (TM->getBBSectionsType() != llvm::BasicBlockSection::None || TM->Options.BBAddrMap) { + if (EmitBBHash) + addPass(llvm::createMachineBlockHashInfoPass()); if (TM->getBBSectionsType() == llvm::BasicBlockSection::List) { addPass(llvm::createBasicBlockSectionsProfileReaderWrapperPass( TM->getBBSectionsFuncListBuf())); diff --git a/llvm/test/CodeGen/X86/basic-block-address-map-empty-function.ll b/llvm/test/CodeGen/X86/basic-block-address-map-empty-function.ll index 4e76262156b42..423e31868bc5f 100644 --- a/llvm/test/CodeGen/X86/basic-block-address-map-empty-function.ll +++ b/llvm/test/CodeGen/X86/basic-block-address-map-empty-function.ll @@ -19,7 +19,7 @@ entry: ; CHECK: func: ; CHECK: .Lfunc_begin1: ; CHECK: .section .llvm_bb_addr_map,"o",@llvm_bb_addr_map,.text{{$}} -; CHECK-NEXT: .byte 3 # version +; CHECK-NEXT: .byte 4 # version ; BASIC-NEXT: .byte 0 # feature ; PGO-NEXT: .byte 3 # feature ; CHECK-NEXT: .quad .Lfunc_begin1 # function address diff --git a/llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll b/llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll index f610b043021a7..e32e5222bf016 100644 --- a/llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll +++ b/llvm/test/CodeGen/X86/basic-block-address-map-function-sections.ll @@ -10,7 +10,7 @@ define dso_local i32 @_Z3barv() { ; CHECK-LABEL: _Z3barv: ; CHECK-NEXT: [[BAR_BEGIN:.Lfunc_begin[0-9]+]]: ; CHECK: .section .llvm_bb_addr_map,"o",@llvm_bb_addr_map,.text._Z3barv{{$}} -; CHECK-NEXT: .byte 3 # version +; CHECK-NEXT: .byte 4 # version ; CHECK-NEXT: .byte 0 # feature ; CHECK-NEXT: .quad [[BAR_BEGIN]] # function address @@ -23,7 +23,7 @@ define dso_local i32 @_Z3foov() { ; CHECK-LABEL: _Z3foov: ; CHECK-NEXT: [[FOO_BEGIN:.Lfunc_begin[0-9]+]]: ; CHECK: .section .llvm_bb_addr_map,"o",@llvm_bb_addr_map,.text._Z3foov{{$}} -; CHECK-NEXT: .byte 3 # version +; CHECK-NEXT: .byte 4 # version ; CHECK-NEXT: .byte 32 # feature ; CHECK-NEXT: .quad [[FOO_BEGIN]] # function address @@ -36,6 +36,6 @@ define linkonce_odr dso_local i32 @_Z4fooTIiET_v() comdat { ; CHECK-LABEL: _Z4fooTIiET_v: ; CHECK-NEXT: [[FOOCOMDAT_BEGIN:.Lfunc_begin[0-9]+]]: ; CHECK: .section .llvm_bb_addr_map,"oG",@llvm_bb_addr_map,.text._Z4fooTIiET_v,_Z4fooTIiET_v,comdat{{$}} -; CHECK-NEXT: .byte 3 # version +; CHECK-NEXT: .byte 4 # version ; CHECK-NEXT: .byte 0 # feature ; CHECK-NEXT: .quad [[FOOCOMDAT_BEGIN]] # function address diff --git a/llvm/test/CodeGen/X86/basic-block-address-map-pgo-features.ll b/llvm/test/CodeGen/X86/basic-block-address-map-pgo-features.ll index ba76f3eab6134..12b1297ba97ce 100644 --- a/llvm/test/CodeGen/X86/basic-block-address-map-pgo-features.ll +++ b/llvm/test/CodeGen/X86/basic-block-address-map-pgo-features.ll @@ -69,7 +69,7 @@ declare i32 @__gxx_personality_v0(...) ; CHECK-LABEL: .Lfunc_end0: ; CHECK: .section .llvm_bb_addr_map,"o",@llvm_bb_addr_map,.text._Z3bazb{{$}} -; CHECK-NEXT: .byte 3 # version +; CHECK-NEXT: .byte 4 # version ; BASIC-NEXT: .byte 32 # feature ; PGO-ALL-NEXT: .byte 39 # feature ; FEC-ONLY-NEXT:.byte 33 # feature diff --git a/llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll b/llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll index 6157f1a727ab5..aeb6dc95e32f3 100644 --- a/llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll +++ b/llvm/test/CodeGen/X86/basic-block-address-map-with-basic-block-sections.ll @@ -47,7 +47,7 @@ declare i32 @__gxx_personality_v0(...) ; CHECK-LABEL: .Lfunc_end0: ; CHECK: .section .llvm_bb_addr_map,"o",@llvm_bb_addr_map,.text.hot._Z3bazb -; CHECK-NEXT: .byte 3 # version +; CHECK-NEXT: .byte 4 # version ; CHECK-NEXT: .byte 40 # feature ; CHECK-NEXT: .byte 2 # number of basic block ranges ; CHECK-NEXT: .quad .Lfunc_begin0 # base address diff --git a/llvm/test/CodeGen/X86/basic-block-address-map-with-emit-bb-hash.ll b/llvm/test/CodeGen/X86/basic-block-address-map-with-emit-bb-hash.ll new file mode 100644 index 0000000000000..a567887753245 --- /dev/null +++ b/llvm/test/CodeGen/X86/basic-block-address-map-with-emit-bb-hash.ll @@ -0,0 +1,94 @@ +; Check the basic block sections labels option works when used along with -emit-bb-hash. +; RUN: llc < %s -mtriple=x86_64 -function-sections -unique-section-names=true -basic-block-address-map -emit-bb-hash | FileCheck %s --check-prefixes=CHECK,UNIQ + +define void @_Z3bazb(i1 zeroext, i1 zeroext) personality ptr @__gxx_personality_v0 { + br i1 %0, label %3, label %8 + +3: + %4 = invoke i32 @_Z3barv() + to label %8 unwind label %6 + br label %10 + +6: + landingpad { ptr, i32 } + catch ptr null + br label %12 + +8: + %9 = call i32 @_Z3foov() + br i1 %1, label %12, label %10 + +10: + %11 = select i1 %1, ptr blockaddress(@_Z3bazb, %3), ptr blockaddress(@_Z3bazb, %12) ; [#uses=1] + indirectbr ptr %11, [label %3, label %12] + +12: + ret void +} + +declare i32 @_Z3barv() #1 + +declare i32 @_Z3foov() #1 + +declare i32 @__gxx_personality_v0(...) + +; UNIQ: .section .text._Z3bazb,"ax",@progbits{{$}} +; NOUNIQ: .section .text,"ax",@progbits,unique,1 +; CHECK-LABEL: _Z3bazb: +; CHECK-LABEL: .Lfunc_begin0: +; CHECK-LABEL: .LBB_END0_0: +; CHECK-LABEL: .LBB0_1: +; CHECK-LABEL: .LBB0_1_CS0: +; CHECK-LABEL: .LBB_END0_1: +; CHECK-LABEL: .LBB0_2: +; CHECK-LABEL: .LBB0_2_CS0: +; CHECK-LABEL: .LBB_END0_2: +; CHECK-LABEL: .LBB0_3: +; CHECK-LABEL: .LBB_END0_3: +; CHECK-LABEL: .Lfunc_end0: + +; UNIQ: .section .llvm_bb_addr_map,"o",@llvm_bb_addr_map,.text._Z3bazb{{$}} +;; Verify that with -unique-section-names=false, the unique id of the text section gets assigned to the llvm_bb_addr_map section. +; NOUNIQ: .section .llvm_bb_addr_map,"o",@llvm_bb_addr_map,.text,unique,1 +; CHECK-NEXT: .byte 4 # version +; CHECK-NEXT: .byte 96 # feature +; CHECK-NEXT: .quad .Lfunc_begin0 # function address +; CHECK-NEXT: .byte 6 # number of basic blocks +; CHECK-NEXT: .byte 0 # BB id +; CHECK-NEXT: .uleb128 .Lfunc_begin0-.Lfunc_begin0 +; CHECK-NEXT: .byte 0 # number of callsites +; CHECK-NEXT: .uleb128 .LBB_END0_0-.Lfunc_begin0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .quad {{-?[0-9]+}} +; CHECK-NEXT: .byte 1 # BB id +; CHECK-NEXT: .uleb128 .LBB0_1-.LBB_END0_0 +; CHECK-NEXT: .byte 1 # number of callsites +; CHECK-NEXT: .uleb128 .LBB0_1_CS0-.LBB0_1 +; CHECK-NEXT: .uleb128 .LBB_END0_1-.LBB0_1_CS0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .quad {{-?[0-9]+}} +; CHECK-NEXT: .byte 3 # BB id +; CHECK-NEXT: .uleb128 .LBB0_2-.LBB_END0_1 +; CHECK-NEXT: .byte 1 # number of callsites +; CHECK-NEXT: .uleb128 .LBB0_2_CS0-.LBB0_2 +; CHECK-NEXT: .uleb128 .LBB_END0_2-.LBB0_2_CS0 +; CHECK-NEXT: .byte 8 +; CHECK-NEXT: .quad {{-?[0-9]+}} +; CHECK-NEXT: .byte 4 # BB id +; CHECK-NEXT: .uleb128 .LBB0_3-.LBB_END0_2 +; CHECK-NEXT: .byte 0 # number of callsites +; CHECK-NEXT: .uleb128 .LBB_END0_3-.LBB0_3 +; CHECK-NEXT: .byte 16 +; CHECK-NEXT: .quad {{-?[0-9]+}} +; CHECK-NEXT: .byte 5 # BB id +; CHECK-NEXT: .uleb128 .LBB0_4-.LBB_END0_3 +; CHECK-NEXT: .byte 0 # number of callsites +; CHECK-NEXT: .uleb128 .LBB_END0_4-.LBB0_4 +; CHECK-NEXT: .byte 1 +; CHECK-NEXT: .quad {{-?[0-9]+}} +; CHECK-NEXT: .byte 2 # BB id +; CHECK-NEXT: .uleb128 .LBB0_5-.LBB_END0_4 +; CHECK-NEXT: .byte 0 # number of callsites +; CHECK-NEXT: .uleb128 .LBB_END0_5-.LBB0_5 +; CHECK-NEXT: .byte 5 +; CHECK-NEXT: .quad {{-?[0-9]+}} diff --git a/llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll b/llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll index 1e8cee4dc8b65..d49b313679628 100644 --- a/llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll +++ b/llvm/test/CodeGen/X86/basic-block-address-map-with-mfs.ll @@ -58,7 +58,7 @@ declare i32 @qux() ; CHECK-LABEL: .Lfunc_end0: ; CHECK: .section .llvm_bb_addr_map,"o",@llvm_bb_addr_map,.text.hot.foo -; CHECK-NEXT: .byte 3 # version +; CHECK-NEXT: .byte 4 # version ; BASIC-NEXT: .byte 40 # feature ; PGO-NEXT: .byte 47 # feature ; CHECK-NEXT: .byte 2 # number of basic block ranges diff --git a/llvm/test/CodeGen/X86/basic-block-address-map.ll b/llvm/test/CodeGen/X86/basic-block-address-map.ll index 5c8f3a645c34a..64cf2c709f3df 100644 --- a/llvm/test/CodeGen/X86/basic-block-address-map.ll +++ b/llvm/test/CodeGen/X86/basic-block-address-map.ll @@ -52,7 +52,7 @@ declare i32 @__gxx_personality_v0(...) ; UNIQ: .section .llvm_bb_addr_map,"o",@llvm_bb_addr_map,.text._Z3bazb{{$}} ;; Verify that with -unique-section-names=false, the unique id of the text section gets assigned to the llvm_bb_addr_map section. ; NOUNIQ: .section .llvm_bb_addr_map,"o",@llvm_bb_addr_map,.text,unique,1 -; CHECK-NEXT: .byte 3 # version +; CHECK-NEXT: .byte 4 # version ; CHECK-NEXT: .byte 32 # feature ; CHECK-NEXT: .quad .Lfunc_begin0 # function address ; CHECK-NEXT: .byte 6 # number of basic blocks From 01498648143c6de409e9c3672ef373189ba97e35 Mon Sep 17 00:00:00 2001 From: NohHyeon Kwon <96061253+swote-git@users.noreply.github.com> Date: Fri, 24 Oct 2025 01:41:48 +0900 Subject: [PATCH 21/31] [clang][test] Add test for comma operator rejection in preprocessor conditionals (#155570) Add test coverage to ensure comma operators remain properly rejected in `#if` directives. Per CWG 1436, comma is not among the permitted operators in preprocessor conditional expressions. This test prevents regressions and clarifies the intended behavior. Fixes #132822 --- clang/test/Preprocessor/cxx_oper_comma.cpp | 45 ++++++++++++++++++++++ 1 file changed, 45 insertions(+) create mode 100644 clang/test/Preprocessor/cxx_oper_comma.cpp diff --git a/clang/test/Preprocessor/cxx_oper_comma.cpp b/clang/test/Preprocessor/cxx_oper_comma.cpp new file mode 100644 index 0000000000000..5db803ae41f32 --- /dev/null +++ b/clang/test/Preprocessor/cxx_oper_comma.cpp @@ -0,0 +1,45 @@ +// RUN: %clang_cc1 -E -pedantic-errors %s -verify -std=c++98 +// RUN: %clang_cc1 -E -pedantic-errors %s -verify -std=c++11 +// RUN: %clang_cc1 -E -pedantic-errors %s -verify -std=c++14 +// RUN: %clang_cc1 -E -pedantic-errors %s -verify -std=c++17 +// RUN: %clang_cc1 -E -pedantic-errors %s -verify -std=c++20 +// RUN: %clang_cc1 -E -pedantic-errors %s -verify=expected,since-cxx23 -std=c++23 -Wno-c23-extensions +// RUN: %clang_cc1 -E -pedantic-errors %s -verify=expected,since-cxx23 -std=c++2c -Wno-c23-extensions + +// Test 1: Top-level comma +// expected-error@+1 {{expected end of line in preprocessor expression}} +#if 1, 2 +#endif + +// Test 2: Comma in conditional expression(CWG3017) +// Per CWG 3017, this exact case highlights the specification gap +// where C++ lacks explicit prohibition of comma operators in #if +// expected-error@+1 {{comma operator in operand of #if}} +#if 1 ? 1, 0 : 3 +#endif + +// Test 3: Parenthesized comma +// expected-error@+1 {{comma operator in operand of #if}} +#if (1, 2) +#endif + +// Test 4: Multiple commas +// expected-error@+1 {{expected end of line in preprocessor expression}} +#if 1, 2, 3 +#endif + +// Test 5: Comma in #elif +#if 0 +#elif (1, 2) // expected-error {{comma operator in operand of #if}} +#endif + +// Test 6: Leading comma (syntax error) +// expected-error@+1 {{invalid token at start of a preprocessor expression}} +#if , +#endif + +// Test 7: Comma in #embed limit parameter (C++23+) +#if __cplusplus >= 202302L +// since-cxx23-error@+1 {{expected ')'}} +#embed "jk.txt" limit(1, 2) +#endif From 930b36cfbbc873fe6c329b95e1c56c6ae1ea1d94 Mon Sep 17 00:00:00 2001 From: Chad Smith Date: Thu, 23 Oct 2025 09:53:43 -0700 Subject: [PATCH 22/31] [lldb] fix lldb-server test failures on windows (#164843) Fix windows test failures from https://github.com/llvm/llvm-project/pull/162730 by including and optional .exe on the lldb-server name. Still passes on linux, but should pass on windows now. ``` > bin/llvm-lit -v tools/lldb/test/Shell/lldb-server/ llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/config.py:531: note: using clang: llvm-project/build/bin/clang llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/config.py:531: note: using ld.lld: /usr/bin/ld.lld llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/config.py:531: note: using lld-link: /usr/bin/lld-link llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/config.py:531: note: using ld64.lld: /usr/bin/ld64.lld llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/config.py:531: note: using wasm-ld: /usr/bin/wasm-ld llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/subst.py:126: note: Did not find obj2yaml in llvm-project/build/./bin:llvm-project/build/./bin llvm-lit: llvm-project/llvm/utils/lit/lit/llvm/subst.py:126: note: Did not find llvm-objdump in llvm-project/build/./bin:llvm-project/build/./bin llvm-lit: llvm-project/lldb/test/Shell/lit.cfg.py:125: warning: Could not set a default per-test timeout. Requires the Python psutil module but it could not be found. Try installing it via pip or via your operating system's package manager. -- Testing: 4 tests, 4 workers -- PASS: lldb-shell :: lldb-server/TestGdbserverErrorMessages.test (1 of 4) PASS: lldb-shell :: lldb-server/TestPlatformHelp.test (2 of 4) PASS: lldb-shell :: lldb-server/TestPlatformErrorMessages.test (3 of 4) PASS: lldb-shell :: lldb-server/TestPlatformSuccessfulStartup.test (4 of 4) Testing Time: 1.10s Total Discovered Tests: 4 Passed: 4 (100.00%) 1 warning(s) in tests ``` --- .../Shell/lldb-server/TestPlatformErrorMessages.test | 2 +- lldb/test/Shell/lldb-server/TestPlatformHelp.test | 10 +++++----- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test b/lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test index d8af31ebaca52..7d3b37aa5fc39 100644 --- a/lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test +++ b/lldb/test/Shell/lldb-server/TestPlatformErrorMessages.test @@ -22,4 +22,4 @@ LOGFILE_MISSING: error: --log-file: missing argument RUN: %platformserver --log-channels 2>&1 | FileCheck --check-prefixes=LOGCHANNELS_MISSING,ALL %s LOGCHANNELS_MISSING: error: --log-channels: missing argument -ALL: Use 'lldb-server {{p|platform}} --help' for a complete list of options. +ALL: Use 'lldb-server{{(\.exe)?}} {{p|platform}} --help' for a complete list of options. diff --git a/lldb/test/Shell/lldb-server/TestPlatformHelp.test b/lldb/test/Shell/lldb-server/TestPlatformHelp.test index 119bbcaaabf14..c5ced8a318100 100644 --- a/lldb/test/Shell/lldb-server/TestPlatformHelp.test +++ b/lldb/test/Shell/lldb-server/TestPlatformHelp.test @@ -5,9 +5,9 @@ RUN: %lldb-server p -h 2>&1 | FileCheck %s RUN: %lldb-server platform --help 2>&1 | FileCheck %s RUN: %lldb-server platform -h 2>&1 | FileCheck %s -CHECK: OVERVIEW: lldb-server platform +CHECK: OVERVIEW: lldb-server{{(\.exe)?}} platform -CHECK: USAGE: lldb-server {{p|platform}} [options] --listen <[host]:port> {{\[}}[--] program args...] +CHECK: USAGE: lldb-server{{(\.exe)?}} {{p|platform}} [options] --listen <[host]:port> {{\[}}[--] program args...] CHECK: CONNECTION OPTIONS: CHECK: --gdbserver-port @@ -33,8 +33,8 @@ CHECK: Acts as a platform server for remote debugging CHECK: EXAMPLES CHECK: # Listen on port 1234, exit after first connection -CHECK: lldb-server platform --listen tcp://0.0.0.0:1234 +CHECK: lldb-server{{(\.exe)?}} platform --listen tcp://0.0.0.0:1234 CHECK: # Listen on port 5555, accept multiple connections -CHECK: lldb-server platform --server --listen tcp://localhost:5555 +CHECK: lldb-server{{(\.exe)?}} platform --server --listen tcp://localhost:5555 CHECK: # Listen on Unix domain socket -CHECK: lldb-server platform --listen unix:///tmp/lldb-server.sock +CHECK: lldb-server{{(\.exe)?}} platform --listen unix:///tmp/lldb-server.sock From 1031f1b293cad13465888722470966ea4b641386 Mon Sep 17 00:00:00 2001 From: Anchu Rajendran S Date: Thu, 23 Oct 2025 09:56:15 -0700 Subject: [PATCH 23/31] [Flang][Driver] Emit module summary for Full LTO (#164302) This PR enables module summary for Full LTO. Module summaries are enabled by default for Full LTO in clang, this change makes the flang behaviour consistent. Reference PR: https://reviews.llvm.org/D34156 --- flang/lib/Frontend/FrontendActions.cpp | 36 +++++++++++++++++++------- flang/test/CMakeLists.txt | 1 + flang/test/Driver/lto-bc.f90 | 36 ++++++++++++++++++-------- 3 files changed, 52 insertions(+), 21 deletions(-) diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp index 0c630d2ba876d..159d08a2797b3 100644 --- a/flang/lib/Frontend/FrontendActions.cpp +++ b/flang/lib/Frontend/FrontendActions.cpp @@ -1019,24 +1019,40 @@ void CodeGenAction::runOptimizationPipeline(llvm::raw_pwrite_stream &os) { // Create the pass manager. llvm::ModulePassManager mpm; - if (opts.PrepareForFatLTO) { - // The module summary should be emitted by default for regular LTO - // except for ld64 targets. - bool emitSummary = opts.PrepareForThinLTO || opts.PrepareForFullLTO || - triple.getVendor() != llvm::Triple::Apple; + // The module summary should be emitted by default for regular LTO + // except for ld64 targets. + bool emitSummary = + opts.PrepareForFullLTO && (triple.getVendor() != llvm::Triple::Apple); + if (opts.PrepareForFatLTO) mpm = pb.buildFatLTODefaultPipeline(level, opts.PrepareForThinLTO, emitSummary); - } else if (opts.PrepareForFullLTO) + else if (opts.PrepareForFullLTO) mpm = pb.buildLTOPreLinkDefaultPipeline(level); else if (opts.PrepareForThinLTO) mpm = pb.buildThinLTOPreLinkDefaultPipeline(level); else mpm = pb.buildPerModuleDefaultPipeline(level); - if (action == BackendActionTy::Backend_EmitBC) - mpm.addPass(llvm::BitcodeWriterPass(os)); - else if (action == BackendActionTy::Backend_EmitLL) - mpm.addPass(llvm::PrintModulePass(os)); + if (action == BackendActionTy::Backend_EmitBC || + action == BackendActionTy::Backend_EmitLL || opts.PrepareForFatLTO) { + if (opts.PrepareForThinLTO) { + // TODO: ThinLTO module summary support is yet to be enabled. + if (action == BackendActionTy::Backend_EmitBC) + mpm.addPass(llvm::BitcodeWriterPass(os)); + else if (action == BackendActionTy::Backend_EmitLL) + mpm.addPass(llvm::PrintModulePass(os)); + } else { + if (emitSummary && !llvmModule->getModuleFlag("ThinLTO")) + llvmModule->addModuleFlag(llvm::Module::Error, "ThinLTO", uint32_t(0)); + if (action == BackendActionTy::Backend_EmitBC) + mpm.addPass(llvm::BitcodeWriterPass( + os, /*ShouldPreserveUseListOrder=*/false, emitSummary)); + else if (action == BackendActionTy::Backend_EmitLL) + mpm.addPass(llvm::PrintModulePass(os, /*Banner=*/"", + /*ShouldPreserveUseListOrder=*/false, + emitSummary)); + } + } // FIXME: This should eventually be replaced by a first-class driver option. // This should be done for both flang and clang simultaneously. diff --git a/flang/test/CMakeLists.txt b/flang/test/CMakeLists.txt index da557f9ec3443..8c8e92faa787a 100644 --- a/flang/test/CMakeLists.txt +++ b/flang/test/CMakeLists.txt @@ -72,6 +72,7 @@ if (NOT FLANG_STANDALONE_BUILD) FileCheck count not + llvm-bcanalyzer llvm-dis llvm-objcopy llvm-objdump diff --git a/flang/test/Driver/lto-bc.f90 b/flang/test/Driver/lto-bc.f90 index 5e34cdb87c5b1..5705fe0cbb929 100644 --- a/flang/test/Driver/lto-bc.f90 +++ b/flang/test/Driver/lto-bc.f90 @@ -1,21 +1,35 @@ ! Test that the output is LLVM bitcode for LTO and not a native objectfile by -! disassembling it to LLVM IR. -! Right now there is nothing special about it and it is similar to non-lto IR, -! more work is needed to add things like module summaries. +! disassembling it to LLVM IR. Also tests that module summaries are emitted for LTO ! RUN: %flang %s -c -o - | not llvm-dis -o %t ! RUN: %flang_fc1 %s -emit-llvm-bc -o - | llvm-dis -o - | FileCheck %s - -! RUN: %flang -flto %s -c -o - | llvm-dis -o - | FileCheck %s -! RUN: %flang -flto=thin %s -c -o - | llvm-dis -o - | FileCheck %s - ! CHECK: define void @_QQmain() ! CHECK-NEXT: ret void ! CHECK-NEXT: } +! CHECK-NOT: !{{.*}} = !{i32 1, !"ThinLTO", i32 0} +! CHECK-NOT: ^{{.*}} = module: +! CHECK-NOT: ^{{.*}} = gv: (name: +! CHECK-NOT: ^{{.*}} = blockcount: + +! RUN: %flang -flto=thin %s -c -o - | llvm-dis -o - | FileCheck %s --check-prefix=THIN +! THIN: define void @_QQmain() +! THIN-NEXT: ret void +! THIN-NEXT: } +! THIN-NOT: !{{.*}} = !{i32 1, !"ThinLTO", i32 0} +! THIN-NOT: ^{{.*}} = module: +! THIN-NOT: ^{{.*}} = gv: (name: +! THIN-NOT: ^{{.*}} = blockcount: -! CHECK-NOT: ^0 = module: -! CHECK-NOT: ^1 = gv: (name: -! CHECK-NOT: ^2 = flags: -! CHECK-NOT: ^3 = blockcount: +! RUN: %flang -flto %s -c -o - | llvm-dis -o - | FileCheck %s --check-prefix=FULL +! FULL: define void @_QQmain() +! FULL-NEXT: ret void +! FULL-NEXT: } +! FULL: !{{.*}} = !{i32 1, !"ThinLTO", i32 0} +! FULL: ^{{.*}} = module: +! FULL: ^{{.*}} = gv: (name: +! FULL: ^{{.*}} = blockcount: +! RUN: %flang_fc1 -flto -emit-llvm-bc %s -o - | llvm-bcanalyzer -dump| FileCheck --check-prefix=MOD-SUMM %s +! MOD-SUMM: FULL_LTO_GLOBALVAL_SUMMARY_BLOCK +program main end program From ede9dd3951e29632a29e13b2fd8c4b6b9d185643 Mon Sep 17 00:00:00 2001 From: Andy Kaylor Date: Thu, 23 Oct 2025 10:01:08 -0700 Subject: [PATCH 24/31] [CIR] Handle dynamic cast to null (#164732) This adds support for handling dynamic casts that are known at compile time to always result in a null pointer. For pointer casts, this emits a null pointer value. For reference casts, it calls the __bad_cast function. --- clang/lib/CIR/CodeGen/CIRGenCXXABI.h | 2 ++ clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp | 26 +++++++++++--- clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp | 7 ++++ clang/test/CIR/CodeGen/dynamic-cast-exact.cpp | 34 +++++++++++++++++++ 4 files changed, 65 insertions(+), 4 deletions(-) diff --git a/clang/lib/CIR/CodeGen/CIRGenCXXABI.h b/clang/lib/CIR/CodeGen/CIRGenCXXABI.h index c78f9b0ea8a26..d3c7dac04dc67 100644 --- a/clang/lib/CIR/CodeGen/CIRGenCXXABI.h +++ b/clang/lib/CIR/CodeGen/CIRGenCXXABI.h @@ -124,6 +124,8 @@ class CIRGenCXXABI { virtual void emitRethrow(CIRGenFunction &cgf, bool isNoReturn) = 0; virtual void emitThrow(CIRGenFunction &cgf, const CXXThrowExpr *e) = 0; + virtual void emitBadCastCall(CIRGenFunction &cgf, mlir::Location loc) = 0; + virtual mlir::Attribute getAddrOfRTTIDescriptor(mlir::Location loc, QualType ty) = 0; diff --git a/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp b/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp index fe9e21064263b..a3cdf192bf9b8 100644 --- a/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenExprCXX.cpp @@ -801,6 +801,26 @@ void CIRGenFunction::emitDeleteCall(const FunctionDecl *deleteFD, emitNewDeleteCall(*this, deleteFD, deleteFTy, deleteArgs); } +static mlir::Value emitDynamicCastToNull(CIRGenFunction &cgf, + mlir::Location loc, QualType destTy) { + mlir::Type destCIRTy = cgf.convertType(destTy); + assert(mlir::isa(destCIRTy) && + "result of dynamic_cast should be a ptr"); + + if (!destTy->isPointerType()) { + mlir::Region *currentRegion = cgf.getBuilder().getBlock()->getParent(); + /// C++ [expr.dynamic.cast]p9: + /// A failed cast to reference type throws std::bad_cast + cgf.cgm.getCXXABI().emitBadCastCall(cgf, loc); + + // The call to bad_cast will terminate the current block. Create a new block + // to hold any follow up code. + cgf.getBuilder().createBlock(currentRegion, currentRegion->end()); + } + + return cgf.getBuilder().getNullPtr(destCIRTy, loc); +} + mlir::Value CIRGenFunction::emitDynamicCast(Address thisAddr, const CXXDynamicCastExpr *dce) { mlir::Location loc = getLoc(dce->getSourceRange()); @@ -831,10 +851,8 @@ mlir::Value CIRGenFunction::emitDynamicCast(Address thisAddr, assert(srcRecordTy->isRecordType() && "source type must be a record type!"); assert(!cir::MissingFeatures::emitTypeCheck()); - if (dce->isAlwaysNull()) { - cgm.errorNYI(dce->getSourceRange(), "emitDynamicCastToNull"); - return {}; - } + if (dce->isAlwaysNull()) + return emitDynamicCastToNull(*this, loc, destTy); auto destCirTy = mlir::cast(convertType(destTy)); return cgm.getCXXABI().emitDynamicCast(*this, loc, srcRecordTy, destRecordTy, diff --git a/clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp b/clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp index f7c4d181cba66..2dce0b16e3043 100644 --- a/clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenItaniumCXXABI.cpp @@ -120,6 +120,8 @@ class CIRGenItaniumCXXABI : public CIRGenCXXABI { return true; } + void emitBadCastCall(CIRGenFunction &cgf, mlir::Location loc) override; + mlir::Value getVirtualBaseClassOffset(mlir::Location loc, CIRGenFunction &cgf, Address thisAddr, const CXXRecordDecl *classDecl, @@ -1883,6 +1885,11 @@ static void emitCallToBadCast(CIRGenFunction &cgf, mlir::Location loc) { cgf.getBuilder().clearInsertionPoint(); } +void CIRGenItaniumCXXABI::emitBadCastCall(CIRGenFunction &cgf, + mlir::Location loc) { + emitCallToBadCast(cgf, loc); +} + // TODO(cir): This could be shared with classic codegen. static CharUnits computeOffsetHint(ASTContext &astContext, const CXXRecordDecl *src, diff --git a/clang/test/CIR/CodeGen/dynamic-cast-exact.cpp b/clang/test/CIR/CodeGen/dynamic-cast-exact.cpp index e3b853321ac7d..9ddb68fbf7355 100644 --- a/clang/test/CIR/CodeGen/dynamic-cast-exact.cpp +++ b/clang/test/CIR/CodeGen/dynamic-cast-exact.cpp @@ -172,3 +172,37 @@ B *offset_cast(A *a) { // OGCG-NEXT: br label %[[LABEL_END]] // OGCG: [[LABEL_END]]: // OGCG-NEXT: phi ptr [ %[[RESULT]], %[[LABEL_NOTNULL]] ], [ null, %[[LABEL_NULL]] ] + +Derived *ptr_cast_always_fail(Base2 *ptr) { + return dynamic_cast(ptr); + } + +// CIR: cir.func {{.*}} @_Z20ptr_cast_always_failP5Base2 +// CIR: %{{.+}} = cir.load{{.*}} %{{.+}} : !cir.ptr>, !cir.ptr +// CIR-NEXT: %[[RESULT:.*]] = cir.const #cir.ptr : !cir.ptr +// CIR-NEXT: cir.store %[[RESULT]], %{{.*}} : !cir.ptr, !cir.ptr> + +// LLVM: define {{.*}} ptr @_Z20ptr_cast_always_failP5Base2 +// LLVM-NEXT: ret ptr null + +// OGCG: define {{.*}} ptr @_Z20ptr_cast_always_failP5Base2 +// OGCG-NEXT: entry: +// OGCG-NEXT: ret ptr null + +Derived &ref_cast_always_fail(Base2 &ref) { + return dynamic_cast(ref); +} + +// CIR: cir.func {{.*}} @_Z20ref_cast_always_failR5Base2 +// CIR: %{{.+}} = cir.load{{.*}} %{{.+}} : !cir.ptr>, !cir.ptr +// CIR-NEXT: cir.call @__cxa_bad_cast() : () -> () +// CIR-NEXT: cir.unreachable + +// LLVM: define {{.*}} ptr @_Z20ref_cast_always_failR5Base2 +// LLVM-NEXT: tail call void @__cxa_bad_cast() +// LLVM-NEXT: unreachable + +// OGCG: define {{.*}} ptr @_Z20ref_cast_always_failR5Base2 +// OGCG-NEXT: entry: +// OGCG-NEXT: tail call void @__cxa_bad_cast() +// OGCG-NEXT: unreachable From 1ab6c0d60c52539b77e1cbfdc7f1ba47ad140b8d Mon Sep 17 00:00:00 2001 From: Jan Svoboda Date: Thu, 23 Oct 2025 10:09:50 -0700 Subject: [PATCH 25/31] [clang] Make explicitly-built modules independent of the CWD (#164840) PR https://github.com/llvm/llvm-project/pull/150123 changed how we normalize the modules cache path. Unfortunately, empty path would get normalized to the current working directory. This means that even explicitly-built PCMs that don't rely on the CWD now embed it, leading to surprising behavior. This PR fixes that by normalizing an empty modules cache path to an empty string. --- clang/lib/Frontend/CompilerInstance.cpp | 5 +---- clang/lib/Lex/HeaderSearch.cpp | 6 ++++-- .../DependencyScannerImpl.cpp | 11 +++++------ clang/test/Modules/explicit-build-cwd.c | 17 +++++++++++++++++ 4 files changed, 27 insertions(+), 12 deletions(-) create mode 100644 clang/test/Modules/explicit-build-cwd.c diff --git a/clang/lib/Frontend/CompilerInstance.cpp b/clang/lib/Frontend/CompilerInstance.cpp index 374138fe4cf8f..e3bf0eaa3c391 100644 --- a/clang/lib/Frontend/CompilerInstance.cpp +++ b/clang/lib/Frontend/CompilerInstance.cpp @@ -546,14 +546,11 @@ void CompilerInstance::createPreprocessor(TranslationUnitKind TUKind) { std::string CompilerInstance::getSpecificModuleCachePath(StringRef ModuleHash) { assert(FileMgr && "Specific module cache path requires a FileManager"); - if (getHeaderSearchOpts().ModuleCachePath.empty()) - return ""; - // Set up the module path, including the hash for the module-creation options. SmallString<256> SpecificModuleCache; normalizeModuleCachePath(*FileMgr, getHeaderSearchOpts().ModuleCachePath, SpecificModuleCache); - if (!getHeaderSearchOpts().DisableModuleHash) + if (!SpecificModuleCache.empty() && !getHeaderSearchOpts().DisableModuleHash) llvm::sys::path::append(SpecificModuleCache, ModuleHash); return std::string(SpecificModuleCache); } diff --git a/clang/lib/Lex/HeaderSearch.cpp b/clang/lib/Lex/HeaderSearch.cpp index 238c5e2f2d9a5..65c324c10ca5d 100644 --- a/clang/lib/Lex/HeaderSearch.cpp +++ b/clang/lib/Lex/HeaderSearch.cpp @@ -2186,6 +2186,8 @@ std::string HeaderSearch::suggestPathToFileForDiagnostics( void clang::normalizeModuleCachePath(FileManager &FileMgr, StringRef Path, SmallVectorImpl &NormalizedPath) { NormalizedPath.assign(Path.begin(), Path.end()); - FileMgr.makeAbsolutePath(NormalizedPath); - llvm::sys::path::remove_dots(NormalizedPath); + if (!NormalizedPath.empty()) { + FileMgr.makeAbsolutePath(NormalizedPath); + llvm::sys::path::remove_dots(NormalizedPath); + } } diff --git a/clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp b/clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp index 05d566922a441..42f52d0ff6241 100644 --- a/clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp +++ b/clang/lib/Tooling/DependencyScanning/DependencyScannerImpl.cpp @@ -524,13 +524,12 @@ bool initializeScanCompilerInstance( // Use the dependency scanning optimized file system if requested to do so. if (DepFS) { DepFS->resetBypassedPathPrefix(); - if (!ScanInstance.getHeaderSearchOpts().ModuleCachePath.empty()) { - SmallString<256> ModulesCachePath; - normalizeModuleCachePath( - ScanInstance.getFileManager(), - ScanInstance.getHeaderSearchOpts().ModuleCachePath, ModulesCachePath); + SmallString<256> ModulesCachePath; + normalizeModuleCachePath(ScanInstance.getFileManager(), + ScanInstance.getHeaderSearchOpts().ModuleCachePath, + ModulesCachePath); + if (!ModulesCachePath.empty()) DepFS->setBypassedPathPrefix(ModulesCachePath); - } ScanInstance.setDependencyDirectivesGetter( std::make_unique( diff --git a/clang/test/Modules/explicit-build-cwd.c b/clang/test/Modules/explicit-build-cwd.c new file mode 100644 index 0000000000000..af8b74361d685 --- /dev/null +++ b/clang/test/Modules/explicit-build-cwd.c @@ -0,0 +1,17 @@ +// This test checks that explicitly building the same module from different +// working directories results in the same PCM contents. + +// RUN: rm -rf %t +// RUN: split-file %s %t +// RUN: mkdir %t/one +// RUN: mkdir %t/two + +//--- module.modulemap +module M { header "M.h" } + +//--- M.h + +// RUN: cd %t/one && %clang_cc1 -fmodules -emit-module %t/module.modulemap -fmodule-name=M -o %t/M_one.pcm +// RUN: cd %t/two && %clang_cc1 -fmodules -emit-module %t/module.modulemap -fmodule-name=M -o %t/M_two.pcm + +// RUN: diff %t/M_one.pcm %t/M_two.pcm From 38473c5d351d6b2ae21b5eb1ce66c2bcc2f7c6f7 Mon Sep 17 00:00:00 2001 From: Ian Anderson Date: Thu, 23 Oct 2025 10:15:00 -0700 Subject: [PATCH 26/31] [clang][headers] Need a way for math.h to share the definitions of INIFINITY and NAN with float.h (#164348) In C23 mode, both float.h and math.h are required to define INIFINITY and NAN. However, with clang modules, there needs to be a single owner for the declarations. Let that be float.h since that's the suggested true owner in Annex F.2.2 of ISO/IEC 9899:2024, and introduce `__need_infinity_nan` so that math.h can pick up the compiler definitions. --- .../find-all-symbols/STLPostfixHeaderMap.cpp | 3 + .../clangd/index/CanonicalIncludes.cpp | 3 + clang/lib/Headers/CMakeLists.txt | 3 + clang/lib/Headers/__float_float.h | 176 +++++++++++++++++ clang/lib/Headers/__float_header_macro.h | 12 ++ clang/lib/Headers/__float_infinity_nan.h | 20 ++ clang/lib/Headers/float.h | 180 ++---------------- clang/lib/Headers/module.modulemap | 18 +- clang/test/Headers/floatneeds.c | 41 ++++ clang/test/Modules/relative-resource-dir.m | 1 + .../gn/secondary/clang/lib/Headers/BUILD.gn | 3 + 11 files changed, 294 insertions(+), 166 deletions(-) create mode 100644 clang/lib/Headers/__float_float.h create mode 100644 clang/lib/Headers/__float_header_macro.h create mode 100644 clang/lib/Headers/__float_infinity_nan.h create mode 100644 clang/test/Headers/floatneeds.c diff --git a/clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp b/clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp index 410df1288b1cc..d43a3ea327a39 100644 --- a/clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp +++ b/clang-tools-extra/clang-include-fixer/find-all-symbols/STLPostfixHeaderMap.cpp @@ -13,6 +13,9 @@ namespace find_all_symbols { const HeaderMapCollector::RegexHeaderMap *getSTLPostfixHeaderMap() { static const HeaderMapCollector::RegexHeaderMap STLPostfixHeaderMap = { + {"include/__float_float.h$", ""}, + {"include/__float_header_macro.h$", ""}, + {"include/__float_infinity_nan.h$", ""}, {"include/__stdarg___gnuc_va_list.h$", ""}, {"include/__stdarg___va_copy.h$", ""}, {"include/__stdarg_header_macro.h$", ""}, diff --git a/clang-tools-extra/clangd/index/CanonicalIncludes.cpp b/clang-tools-extra/clangd/index/CanonicalIncludes.cpp index 1f7b525c8c2b2..cbef64f351341 100644 --- a/clang-tools-extra/clangd/index/CanonicalIncludes.cpp +++ b/clang-tools-extra/clangd/index/CanonicalIncludes.cpp @@ -16,6 +16,9 @@ namespace clang { namespace clangd { namespace { const std::pair IncludeMappings[] = { + {"include/__float_float.h", ""}, + {"include/__float_header_macro.h", ""}, + {"include/__float_infinity_nan.h", ""}, {"include/__stdarg___gnuc_va_list.h", ""}, {"include/__stdarg___va_copy.h", ""}, {"include/__stdarg_header_macro.h", ""}, diff --git a/clang/lib/Headers/CMakeLists.txt b/clang/lib/Headers/CMakeLists.txt index 32a6be88abc20..18589125697b0 100644 --- a/clang/lib/Headers/CMakeLists.txt +++ b/clang/lib/Headers/CMakeLists.txt @@ -4,6 +4,9 @@ set(core_files builtins.h float.h + __float_float.h + __float_header_macro.h + __float_infinity_nan.h inttypes.h iso646.h limits.h diff --git a/clang/lib/Headers/__float_float.h b/clang/lib/Headers/__float_float.h new file mode 100644 index 0000000000000..267c0721a7ee4 --- /dev/null +++ b/clang/lib/Headers/__float_float.h @@ -0,0 +1,176 @@ +/*===---- __float_float.h --------------------------------------------------=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + */ + +#ifndef __CLANG_FLOAT_FLOAT_H +#define __CLANG_FLOAT_FLOAT_H + +#if (defined(__MINGW32__) || defined(_MSC_VER) || defined(_AIX)) && \ + __STDC_HOSTED__ + +/* Undefine anything that we'll be redefining below. */ +# undef FLT_EVAL_METHOD +# undef FLT_ROUNDS +# undef FLT_RADIX +# undef FLT_MANT_DIG +# undef DBL_MANT_DIG +# undef LDBL_MANT_DIG +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \ + !defined(__STRICT_ANSI__) || \ + (defined(__cplusplus) && __cplusplus >= 201103L) || \ + (__STDC_HOSTED__ && defined(_AIX) && defined(_ALL_SOURCE)) +# undef DECIMAL_DIG +# endif +# undef FLT_DIG +# undef DBL_DIG +# undef LDBL_DIG +# undef FLT_MIN_EXP +# undef DBL_MIN_EXP +# undef LDBL_MIN_EXP +# undef FLT_MIN_10_EXP +# undef DBL_MIN_10_EXP +# undef LDBL_MIN_10_EXP +# undef FLT_MAX_EXP +# undef DBL_MAX_EXP +# undef LDBL_MAX_EXP +# undef FLT_MAX_10_EXP +# undef DBL_MAX_10_EXP +# undef LDBL_MAX_10_EXP +# undef FLT_MAX +# undef DBL_MAX +# undef LDBL_MAX +# undef FLT_EPSILON +# undef DBL_EPSILON +# undef LDBL_EPSILON +# undef FLT_MIN +# undef DBL_MIN +# undef LDBL_MIN +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || \ + !defined(__STRICT_ANSI__) || \ + (defined(__cplusplus) && __cplusplus >= 201703L) || \ + (__STDC_HOSTED__ && defined(_AIX) && defined(_ALL_SOURCE)) +# undef FLT_TRUE_MIN +# undef DBL_TRUE_MIN +# undef LDBL_TRUE_MIN +# undef FLT_DECIMAL_DIG +# undef DBL_DECIMAL_DIG +# undef LDBL_DECIMAL_DIG +# undef FLT_HAS_SUBNORM +# undef DBL_HAS_SUBNORM +# undef LDBL_HAS_SUBNORM +# endif +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L) || \ + !defined(__STRICT_ANSI__) +# undef FLT_NORM_MAX +# undef DBL_NORM_MAX +# undef LDBL_NORM_MAX +#endif +#endif + +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L) || \ + !defined(__STRICT_ANSI__) +# undef FLT_SNAN +# undef DBL_SNAN +# undef LDBL_SNAN +#endif + +/* Characteristics of floating point types, C99 5.2.4.2.2 */ + +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \ + (defined(__cplusplus) && __cplusplus >= 201103L) +#define FLT_EVAL_METHOD __FLT_EVAL_METHOD__ +#endif +#define FLT_ROUNDS (__builtin_flt_rounds()) +#define FLT_RADIX __FLT_RADIX__ + +#define FLT_MANT_DIG __FLT_MANT_DIG__ +#define DBL_MANT_DIG __DBL_MANT_DIG__ +#define LDBL_MANT_DIG __LDBL_MANT_DIG__ + +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \ + !defined(__STRICT_ANSI__) || \ + (defined(__cplusplus) && __cplusplus >= 201103L) || \ + (__STDC_HOSTED__ && defined(_AIX) && defined(_ALL_SOURCE)) +# define DECIMAL_DIG __DECIMAL_DIG__ +#endif + +#define FLT_DIG __FLT_DIG__ +#define DBL_DIG __DBL_DIG__ +#define LDBL_DIG __LDBL_DIG__ + +#define FLT_MIN_EXP __FLT_MIN_EXP__ +#define DBL_MIN_EXP __DBL_MIN_EXP__ +#define LDBL_MIN_EXP __LDBL_MIN_EXP__ + +#define FLT_MIN_10_EXP __FLT_MIN_10_EXP__ +#define DBL_MIN_10_EXP __DBL_MIN_10_EXP__ +#define LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__ + +#define FLT_MAX_EXP __FLT_MAX_EXP__ +#define DBL_MAX_EXP __DBL_MAX_EXP__ +#define LDBL_MAX_EXP __LDBL_MAX_EXP__ + +#define FLT_MAX_10_EXP __FLT_MAX_10_EXP__ +#define DBL_MAX_10_EXP __DBL_MAX_10_EXP__ +#define LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__ + +#define FLT_MAX __FLT_MAX__ +#define DBL_MAX __DBL_MAX__ +#define LDBL_MAX __LDBL_MAX__ + +#define FLT_EPSILON __FLT_EPSILON__ +#define DBL_EPSILON __DBL_EPSILON__ +#define LDBL_EPSILON __LDBL_EPSILON__ + +#define FLT_MIN __FLT_MIN__ +#define DBL_MIN __DBL_MIN__ +#define LDBL_MIN __LDBL_MIN__ + +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || \ + !defined(__STRICT_ANSI__) || \ + (defined(__cplusplus) && __cplusplus >= 201703L) || \ + (__STDC_HOSTED__ && defined(_AIX) && defined(_ALL_SOURCE)) +# define FLT_TRUE_MIN __FLT_DENORM_MIN__ +# define DBL_TRUE_MIN __DBL_DENORM_MIN__ +# define LDBL_TRUE_MIN __LDBL_DENORM_MIN__ +# define FLT_DECIMAL_DIG __FLT_DECIMAL_DIG__ +# define DBL_DECIMAL_DIG __DBL_DECIMAL_DIG__ +# define LDBL_DECIMAL_DIG __LDBL_DECIMAL_DIG__ +# define FLT_HAS_SUBNORM __FLT_HAS_DENORM__ +# define DBL_HAS_SUBNORM __DBL_HAS_DENORM__ +# define LDBL_HAS_SUBNORM __LDBL_HAS_DENORM__ +#endif + +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L) || \ + !defined(__STRICT_ANSI__) + /* C23 5.2.5.3.2p28 */ +# define FLT_SNAN (__builtin_nansf("")) +# define DBL_SNAN (__builtin_nans("")) +# define LDBL_SNAN (__builtin_nansl("")) + + /* C23 5.2.5.3.3p32 */ +# define FLT_NORM_MAX __FLT_NORM_MAX__ +# define DBL_NORM_MAX __DBL_NORM_MAX__ +# define LDBL_NORM_MAX __LDBL_NORM_MAX__ +#endif + +#ifdef __STDC_WANT_IEC_60559_TYPES_EXT__ +# define FLT16_MANT_DIG __FLT16_MANT_DIG__ +# define FLT16_DECIMAL_DIG __FLT16_DECIMAL_DIG__ +# define FLT16_DIG __FLT16_DIG__ +# define FLT16_MIN_EXP __FLT16_MIN_EXP__ +# define FLT16_MIN_10_EXP __FLT16_MIN_10_EXP__ +# define FLT16_MAX_EXP __FLT16_MAX_EXP__ +# define FLT16_MAX_10_EXP __FLT16_MAX_10_EXP__ +# define FLT16_MAX __FLT16_MAX__ +# define FLT16_EPSILON __FLT16_EPSILON__ +# define FLT16_MIN __FLT16_MIN__ +# define FLT16_TRUE_MIN __FLT16_TRUE_MIN__ +#endif /* __STDC_WANT_IEC_60559_TYPES_EXT__ */ + +#endif /* __CLANG_FLOAT_FLOAT_H */ diff --git a/clang/lib/Headers/__float_header_macro.h b/clang/lib/Headers/__float_header_macro.h new file mode 100644 index 0000000000000..11b270e90deb9 --- /dev/null +++ b/clang/lib/Headers/__float_header_macro.h @@ -0,0 +1,12 @@ +/*===---- __float_header_macro.h -------------------------------------------=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + */ + +#ifndef __CLANG_FLOAT_H +#define __CLANG_FLOAT_H +#endif /* __CLANG_FLOAT_H */ diff --git a/clang/lib/Headers/__float_infinity_nan.h b/clang/lib/Headers/__float_infinity_nan.h new file mode 100644 index 0000000000000..7e253d0bc59b9 --- /dev/null +++ b/clang/lib/Headers/__float_infinity_nan.h @@ -0,0 +1,20 @@ +/*===---- __float_infinity_nan.h -------------------------------------------=== + * + * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. + * See https://llvm.org/LICENSE.txt for license information. + * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + * + *===-----------------------------------------------------------------------=== + */ + +#ifndef __CLANG_FLOAT_INFINITY_NAN_H +#define __CLANG_FLOAT_INFINITY_NAN_H + +/* C23 5.2.5.3.3p29-30 */ +#undef INFINITY +#undef NAN + +#define INFINITY (__builtin_inff()) +#define NAN (__builtin_nanf("")) + +#endif /* __CLANG_FLOAT_INFINITY_NAN_H */ diff --git a/clang/lib/Headers/float.h b/clang/lib/Headers/float.h index 30427c29dcdbd..82974f60048c9 100644 --- a/clang/lib/Headers/float.h +++ b/clang/lib/Headers/float.h @@ -7,13 +7,21 @@ *===-----------------------------------------------------------------------=== */ -#ifndef __CLANG_FLOAT_H -#define __CLANG_FLOAT_H - #if defined(__MVS__) && __has_include_next() +#include <__float_header_macro.h> #include_next #else +#if !defined(__need_infinity_nan) +#define __need_float_float +#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L) || \ + !defined(__STRICT_ANSI__) +#define __need_infinity_nan +#endif +#include <__float_header_macro.h> +#endif + +#ifdef __need_float_float /* If we're on MinGW, fall back to the system's float.h, which might have * additional definitions provided for Windows. * For more details see http://msdn.microsoft.com/en-us/library/y0ybw9fy.aspx @@ -26,171 +34,15 @@ # include_next -/* Undefine anything that we'll be redefining below. */ -# undef FLT_EVAL_METHOD -# undef FLT_ROUNDS -# undef FLT_RADIX -# undef FLT_MANT_DIG -# undef DBL_MANT_DIG -# undef LDBL_MANT_DIG -#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \ - !defined(__STRICT_ANSI__) || \ - (defined(__cplusplus) && __cplusplus >= 201103L) || \ - (__STDC_HOSTED__ && defined(_AIX) && defined(_ALL_SOURCE)) -# undef DECIMAL_DIG -# endif -# undef FLT_DIG -# undef DBL_DIG -# undef LDBL_DIG -# undef FLT_MIN_EXP -# undef DBL_MIN_EXP -# undef LDBL_MIN_EXP -# undef FLT_MIN_10_EXP -# undef DBL_MIN_10_EXP -# undef LDBL_MIN_10_EXP -# undef FLT_MAX_EXP -# undef DBL_MAX_EXP -# undef LDBL_MAX_EXP -# undef FLT_MAX_10_EXP -# undef DBL_MAX_10_EXP -# undef LDBL_MAX_10_EXP -# undef FLT_MAX -# undef DBL_MAX -# undef LDBL_MAX -# undef FLT_EPSILON -# undef DBL_EPSILON -# undef LDBL_EPSILON -# undef FLT_MIN -# undef DBL_MIN -# undef LDBL_MIN -#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || \ - !defined(__STRICT_ANSI__) || \ - (defined(__cplusplus) && __cplusplus >= 201703L) || \ - (__STDC_HOSTED__ && defined(_AIX) && defined(_ALL_SOURCE)) -# undef FLT_TRUE_MIN -# undef DBL_TRUE_MIN -# undef LDBL_TRUE_MIN -# undef FLT_DECIMAL_DIG -# undef DBL_DECIMAL_DIG -# undef LDBL_DECIMAL_DIG -# undef FLT_HAS_SUBNORM -# undef DBL_HAS_SUBNORM -# undef LDBL_HAS_SUBNORM -# endif -#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L) || \ - !defined(__STRICT_ANSI__) -# undef FLT_NORM_MAX -# undef DBL_NORM_MAX -# undef LDBL_NORM_MAX -#endif -#endif - -#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L) || \ - !defined(__STRICT_ANSI__) -# undef INFINITY -# undef NAN -# undef FLT_SNAN -# undef DBL_SNAN -# undef LDBL_SNAN -#endif - -/* Characteristics of floating point types, C99 5.2.4.2.2 */ - -#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \ - (defined(__cplusplus) && __cplusplus >= 201103L) -#define FLT_EVAL_METHOD __FLT_EVAL_METHOD__ #endif -#define FLT_ROUNDS (__builtin_flt_rounds()) -#define FLT_RADIX __FLT_RADIX__ -#define FLT_MANT_DIG __FLT_MANT_DIG__ -#define DBL_MANT_DIG __DBL_MANT_DIG__ -#define LDBL_MANT_DIG __LDBL_MANT_DIG__ - -#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 199901L) || \ - !defined(__STRICT_ANSI__) || \ - (defined(__cplusplus) && __cplusplus >= 201103L) || \ - (__STDC_HOSTED__ && defined(_AIX) && defined(_ALL_SOURCE)) -# define DECIMAL_DIG __DECIMAL_DIG__ -#endif - -#define FLT_DIG __FLT_DIG__ -#define DBL_DIG __DBL_DIG__ -#define LDBL_DIG __LDBL_DIG__ - -#define FLT_MIN_EXP __FLT_MIN_EXP__ -#define DBL_MIN_EXP __DBL_MIN_EXP__ -#define LDBL_MIN_EXP __LDBL_MIN_EXP__ - -#define FLT_MIN_10_EXP __FLT_MIN_10_EXP__ -#define DBL_MIN_10_EXP __DBL_MIN_10_EXP__ -#define LDBL_MIN_10_EXP __LDBL_MIN_10_EXP__ - -#define FLT_MAX_EXP __FLT_MAX_EXP__ -#define DBL_MAX_EXP __DBL_MAX_EXP__ -#define LDBL_MAX_EXP __LDBL_MAX_EXP__ - -#define FLT_MAX_10_EXP __FLT_MAX_10_EXP__ -#define DBL_MAX_10_EXP __DBL_MAX_10_EXP__ -#define LDBL_MAX_10_EXP __LDBL_MAX_10_EXP__ - -#define FLT_MAX __FLT_MAX__ -#define DBL_MAX __DBL_MAX__ -#define LDBL_MAX __LDBL_MAX__ - -#define FLT_EPSILON __FLT_EPSILON__ -#define DBL_EPSILON __DBL_EPSILON__ -#define LDBL_EPSILON __LDBL_EPSILON__ - -#define FLT_MIN __FLT_MIN__ -#define DBL_MIN __DBL_MIN__ -#define LDBL_MIN __LDBL_MIN__ - -#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 201112L) || \ - !defined(__STRICT_ANSI__) || \ - (defined(__cplusplus) && __cplusplus >= 201703L) || \ - (__STDC_HOSTED__ && defined(_AIX) && defined(_ALL_SOURCE)) -# define FLT_TRUE_MIN __FLT_DENORM_MIN__ -# define DBL_TRUE_MIN __DBL_DENORM_MIN__ -# define LDBL_TRUE_MIN __LDBL_DENORM_MIN__ -# define FLT_DECIMAL_DIG __FLT_DECIMAL_DIG__ -# define DBL_DECIMAL_DIG __DBL_DECIMAL_DIG__ -# define LDBL_DECIMAL_DIG __LDBL_DECIMAL_DIG__ -# define FLT_HAS_SUBNORM __FLT_HAS_DENORM__ -# define DBL_HAS_SUBNORM __DBL_HAS_DENORM__ -# define LDBL_HAS_SUBNORM __LDBL_HAS_DENORM__ +#include <__float_float.h> +#undef __need_float_float #endif -#if (defined(__STDC_VERSION__) && __STDC_VERSION__ >= 202311L) || \ - !defined(__STRICT_ANSI__) - /* C23 5.2.5.3.2p28 */ -# define FLT_SNAN (__builtin_nansf("")) -# define DBL_SNAN (__builtin_nans("")) -# define LDBL_SNAN (__builtin_nansl("")) - - /* C23 5.2.5.3.3p29-30 */ -# define INFINITY (__builtin_inff()) -# define NAN (__builtin_nanf("")) - - /* C23 5.2.5.3.3p32 */ -# define FLT_NORM_MAX __FLT_NORM_MAX__ -# define DBL_NORM_MAX __DBL_NORM_MAX__ -# define LDBL_NORM_MAX __LDBL_NORM_MAX__ +#ifdef __need_infinity_nan +#include <__float_infinity_nan.h> +#undef __need_infinity_nan #endif -#ifdef __STDC_WANT_IEC_60559_TYPES_EXT__ -# define FLT16_MANT_DIG __FLT16_MANT_DIG__ -# define FLT16_DECIMAL_DIG __FLT16_DECIMAL_DIG__ -# define FLT16_DIG __FLT16_DIG__ -# define FLT16_MIN_EXP __FLT16_MIN_EXP__ -# define FLT16_MIN_10_EXP __FLT16_MIN_10_EXP__ -# define FLT16_MAX_EXP __FLT16_MAX_EXP__ -# define FLT16_MAX_10_EXP __FLT16_MAX_10_EXP__ -# define FLT16_MAX __FLT16_MAX__ -# define FLT16_EPSILON __FLT16_EPSILON__ -# define FLT16_MIN __FLT16_MIN__ -# define FLT16_TRUE_MIN __FLT16_TRUE_MIN__ -#endif /* __STDC_WANT_IEC_60559_TYPES_EXT__ */ - #endif /* __MVS__ */ -#endif /* __CLANG_FLOAT_H */ diff --git a/clang/lib/Headers/module.modulemap b/clang/lib/Headers/module.modulemap index bdf5119ba4607..2e4d533356569 100644 --- a/clang/lib/Headers/module.modulemap +++ b/clang/lib/Headers/module.modulemap @@ -171,8 +171,22 @@ module _Builtin_intrinsics [system] [extern_c] { // that module. The system float.h (if present) will be treated // as a textual header in the sytem module. module _Builtin_float [system] { - header "float.h" - export * + textual header "float.h" + + explicit module float { + header "__float_float.h" + export * + } + + explicit module header_macro { + header "__float_header_macro.h" + export * + } + + explicit module infinity_nan { + header "__float_infinity_nan.h" + export * + } } module _Builtin_inttypes [system] { diff --git a/clang/test/Headers/floatneeds.c b/clang/test/Headers/floatneeds.c new file mode 100644 index 0000000000000..e544b41009908 --- /dev/null +++ b/clang/test/Headers/floatneeds.c @@ -0,0 +1,41 @@ +// RUN: rm -fR %t +// RUN: split-file %s %t +// RUN: %clang_cc1 -fsyntax-only -verify=c99 -std=c99 %t/floatneeds0.c +// RUN: %clang_cc1 -fsyntax-only -verify=c99 -std=c99 %t/floatneeds1.c +// RUN: %clang_cc1 -fsyntax-only -verify=c23 -std=c23 %t/floatneeds0.c +// RUN: %clang_cc1 -fsyntax-only -verify=c23 -std=c23 %t/floatneeds1.c +// RUN: %clang_cc1 -fsyntax-only -verify=c99-modules -fmodules -fimplicit-module-maps -fmodules-cache-path=%t -std=c99 %t/floatneeds0.c +// RUN: %clang_cc1 -fsyntax-only -verify=c99-modules -fmodules -fimplicit-module-maps -fmodules-cache-path=%t -std=c99 %t/floatneeds1.c +// RUN: %clang_cc1 -fsyntax-only -verify=c23-modules -fmodules -fimplicit-module-maps -fmodules-cache-path=%t -std=c23 %t/floatneeds0.c +// RUN: %clang_cc1 -fsyntax-only -verify=c23-modules -fmodules -fimplicit-module-maps -fmodules-cache-path=%t -std=c23 %t/floatneeds1.c + +// Use C99 to verify that __need_ can be used to get types that wouldn't normally be available. + +//--- floatneeds0.c +float infinity0 = INFINITY; // c99-error{{undeclared identifier 'INFINITY'}} c23-error{{undeclared identifier 'INFINITY'}} \ + c99-modules-error{{undeclared identifier 'INFINITY'}} c23-modules-error{{undeclared identifier 'INFINITY'}} +float nan0 = NAN; // c99-error{{undeclared identifier 'NAN'}} c23-error{{undeclared identifier 'NAN'}} \ + c99-modules-error{{undeclared identifier 'NAN'}} c23-modules-error{{undeclared identifier 'NAN'}} +float max0 = FLT_MAX; // c99-error{{undeclared identifier 'FLT_MAX'}} c23-error{{undeclared identifier 'FLT_MAX'}} \ + c99-modules-error{{undeclared identifier 'FLT_MAX'}} c23-modules-error{{undeclared identifier 'FLT_MAX'}} + +#define __need_infinity_nan +#include +float infinity1 = INFINITY; +float nan1 = NAN; +float max1 = FLT_MAX; // c99-error{{undeclared identifier}} c23-error{{undeclared identifier}} \ + c99-modules-error{{undeclared identifier}} c23-modules-error{{undeclared identifier}} + +#include +float infinity2 = INFINITY; +float nan2 = NAN; +float max2 = FLT_MAX; + +//--- floatneeds1.c +// c23-no-diagnostics +// c23-modules-no-diagnostics + +#include +float infinity0 = INFINITY; // c99-error{{undeclared identifier}} c99-modules-error{{undeclared identifier}} +float nan0 = NAN; // c99-error{{undeclared identifier}} c99-modules-error{{undeclared identifier}} +float max0 = FLT_MAX; diff --git a/clang/test/Modules/relative-resource-dir.m b/clang/test/Modules/relative-resource-dir.m index 96f2d8efc7860..1183184796d1e 100644 --- a/clang/test/Modules/relative-resource-dir.m +++ b/clang/test/Modules/relative-resource-dir.m @@ -8,5 +8,6 @@ // RUN: -fimplicit-module-maps -fmodules-cache-path=%t.mcp \ // RUN: -fbuiltin-headers-in-system-modules \ // RUN: -resource-dir resource-dir \ +// RUN: -internal-isystem resource-dir/include \ // RUN: -emit-module %S/Inputs/builtin-headers/module.modulemap \ // RUN: -fmodule-name=ModuleWithBuiltinHeader -o %t.pcm diff --git a/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn b/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn index 29c617881dc4c..3c523aeada6cb 100644 --- a/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn +++ b/llvm/utils/gn/secondary/clang/lib/Headers/BUILD.gn @@ -104,6 +104,9 @@ copy("Headers") { "__clang_hip_runtime_wrapper.h", "__clang_hip_stdlib.h", "__clang_spirv_builtins.h", + "__float_float.h", + "__float_header_macro.h", + "__float_infinity_nan.h", "__stdarg___gnuc_va_list.h", "__stdarg___va_copy.h", "__stdarg_header_macro.h", From 1c53bfc635b1138a549d7ff82425af91aa9db512 Mon Sep 17 00:00:00 2001 From: Zack Johnson Date: Thu, 23 Oct 2025 13:16:13 -0400 Subject: [PATCH 27/31] [compiler-rt][ASan] Define SANITIZER_INTERCEPT_WCSNLEN (#164845) Follow up to #162028 `SANITIZER_INTERCEPT_WCSNLEN` is not defined, so `internal_wcsnlen` is always used instead of using `REAL(wcsnlen)` if intercepted. --- .../lib/sanitizer_common/sanitizer_platform_interceptors.h | 1 + 1 file changed, 1 insertion(+) diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h b/compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h index 88ecd7e16306a..ed60671014d5a 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h +++ b/compiler-rt/lib/sanitizer_common/sanitizer_platform_interceptors.h @@ -551,6 +551,7 @@ SANITIZER_WEAK_IMPORT void *aligned_alloc(__sanitizer::usize __alignment, #define SANITIZER_INTERCEPT_MALLOC_USABLE_SIZE (!SI_MAC && !SI_NETBSD) #define SANITIZER_INTERCEPT_MCHECK_MPROBE SI_LINUX_NOT_ANDROID #define SANITIZER_INTERCEPT_WCSLEN 1 +#define SANITIZER_INTERCEPT_WCSNLEN 1 #define SANITIZER_INTERCEPT_WCSCAT (SI_POSIX || SI_WINDOWS) #define SANITIZER_INTERCEPT_WCSDUP SI_POSIX #define SANITIZER_INTERCEPT_SIGNAL_AND_SIGACTION (!SI_WINDOWS && SI_NOT_FUCHSIA) From 2b42c6c163f8520e5a279d6b995907ab606c8600 Mon Sep 17 00:00:00 2001 From: Justin Bogner Date: Thu, 23 Oct 2025 10:19:17 -0700 Subject: [PATCH 28/31] [DirectX] Use a well-formed cbuffer in the unused cbuffer test (#164844) CBuffers still need a layout type for now. Fix the crash when looking up the cbuffer info. --- llvm/test/CodeGen/DirectX/CBufferAccess/unused.ll | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/test/CodeGen/DirectX/CBufferAccess/unused.ll b/llvm/test/CodeGen/DirectX/CBufferAccess/unused.ll index 8c0d82e43b4b1..6f1bbd050bd7c 100644 --- a/llvm/test/CodeGen/DirectX/CBufferAccess/unused.ll +++ b/llvm/test/CodeGen/DirectX/CBufferAccess/unused.ll @@ -2,7 +2,7 @@ ; Check that we correctly ignore cbuffers that were nulled out by optimizations. %__cblayout_CB = type <{ float }> -@CB.cb = local_unnamed_addr global target("dx.CBuffer", %__cblayout_CB) poison +@CB.cb = local_unnamed_addr global target("dx.CBuffer", target("dx.Layout", %__cblayout_CB, 4, 0)) poison @x = external local_unnamed_addr addrspace(2) global float, align 4 ; CHECK-NOT: !hlsl.cbs = From 2b6686f2cd4424d22905a67afee7b0c514fa9042 Mon Sep 17 00:00:00 2001 From: jofrn Date: Thu, 23 Oct 2025 13:50:10 -0400 Subject: [PATCH 29/31] [X86] Manage atomic load of fp -> int promotion in DAG (#148895) When lowering atomic <1 x T> vector types with floats, selection can fail since this pattern is unsupported. To support this, floats can be casted to an integer type of the same size. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 4 + llvm/test/CodeGen/X86/atomic-load-store.ll | 117 +++++++++++++++++++++ 2 files changed, 121 insertions(+) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index d49f25a950e3a..4dfc400fbbb6c 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -2632,6 +2632,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM, setOperationAction(Op, MVT::f32, Promote); } + setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16); + setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32); + setOperationPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64); + // We have target-specific dag combine patterns for the following nodes: setTargetDAGCombine({ISD::VECTOR_SHUFFLE, ISD::SCALAR_TO_VECTOR, diff --git a/llvm/test/CodeGen/X86/atomic-load-store.ll b/llvm/test/CodeGen/X86/atomic-load-store.ll index 4f5cb5a4e9247..9fab8b98b4af0 100644 --- a/llvm/test/CodeGen/X86/atomic-load-store.ll +++ b/llvm/test/CodeGen/X86/atomic-load-store.ll @@ -269,3 +269,120 @@ define <1 x i64> @atomic_vec1_i64_align(ptr %x) nounwind { %ret = load atomic <1 x i64>, ptr %x acquire, align 8 ret <1 x i64> %ret } + +define <1 x half> @atomic_vec1_half(ptr %x) { +; CHECK-O3-LABEL: atomic_vec1_half: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movzwl (%rdi), %eax +; CHECK-O3-NEXT: pinsrw $0, %eax, %xmm0 +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec1_half: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: movzwl (%rdi), %eax +; CHECK-SSE-O3-NEXT: pinsrw $0, %eax, %xmm0 +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-AVX-O3-LABEL: atomic_vec1_half: +; CHECK-AVX-O3: # %bb.0: +; CHECK-AVX-O3-NEXT: movzwl (%rdi), %eax +; CHECK-AVX-O3-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0 +; CHECK-AVX-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec1_half: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: movw (%rdi), %cx +; CHECK-O0-NEXT: # implicit-def: $eax +; CHECK-O0-NEXT: movw %cx, %ax +; CHECK-O0-NEXT: # implicit-def: $xmm0 +; CHECK-O0-NEXT: pinsrw $0, %eax, %xmm0 +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec1_half: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: movw (%rdi), %cx +; CHECK-SSE-O0-NEXT: # implicit-def: $eax +; CHECK-SSE-O0-NEXT: movw %cx, %ax +; CHECK-SSE-O0-NEXT: # implicit-def: $xmm0 +; CHECK-SSE-O0-NEXT: pinsrw $0, %eax, %xmm0 +; CHECK-SSE-O0-NEXT: retq +; +; CHECK-AVX-O0-LABEL: atomic_vec1_half: +; CHECK-AVX-O0: # %bb.0: +; CHECK-AVX-O0-NEXT: movw (%rdi), %cx +; CHECK-AVX-O0-NEXT: # implicit-def: $eax +; CHECK-AVX-O0-NEXT: movw %cx, %ax +; CHECK-AVX-O0-NEXT: # implicit-def: $xmm0 +; CHECK-AVX-O0-NEXT: vpinsrw $0, %eax, %xmm0, %xmm0 +; CHECK-AVX-O0-NEXT: retq + %ret = load atomic <1 x half>, ptr %x acquire, align 2 + ret <1 x half> %ret +} + +define <1 x float> @atomic_vec1_float(ptr %x) { +; CHECK-O3-LABEL: atomic_vec1_float: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec1_float: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-AVX-O3-LABEL: atomic_vec1_float: +; CHECK-AVX-O3: # %bb.0: +; CHECK-AVX-O3-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-AVX-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec1_float: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec1_float: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-SSE-O0-NEXT: retq +; +; CHECK-AVX-O0-LABEL: atomic_vec1_float: +; CHECK-AVX-O0: # %bb.0: +; CHECK-AVX-O0-NEXT: vmovss {{.*#+}} xmm0 = mem[0],zero,zero,zero +; CHECK-AVX-O0-NEXT: retq + %ret = load atomic <1 x float>, ptr %x acquire, align 4 + ret <1 x float> %ret +} + +define <1 x double> @atomic_vec1_double_align(ptr %x) nounwind { +; CHECK-O3-LABEL: atomic_vec1_double_align: +; CHECK-O3: # %bb.0: +; CHECK-O3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-O3-NEXT: retq +; +; CHECK-SSE-O3-LABEL: atomic_vec1_double_align: +; CHECK-SSE-O3: # %bb.0: +; CHECK-SSE-O3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-SSE-O3-NEXT: retq +; +; CHECK-AVX-O3-LABEL: atomic_vec1_double_align: +; CHECK-AVX-O3: # %bb.0: +; CHECK-AVX-O3-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-AVX-O3-NEXT: retq +; +; CHECK-O0-LABEL: atomic_vec1_double_align: +; CHECK-O0: # %bb.0: +; CHECK-O0-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-O0-NEXT: retq +; +; CHECK-SSE-O0-LABEL: atomic_vec1_double_align: +; CHECK-SSE-O0: # %bb.0: +; CHECK-SSE-O0-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-SSE-O0-NEXT: retq +; +; CHECK-AVX-O0-LABEL: atomic_vec1_double_align: +; CHECK-AVX-O0: # %bb.0: +; CHECK-AVX-O0-NEXT: vmovsd {{.*#+}} xmm0 = mem[0],zero +; CHECK-AVX-O0-NEXT: retq + %ret = load atomic <1 x double>, ptr %x acquire, align 8 + ret <1 x double> %ret +} From 10bec2cd9dab796d5685fa8aadf47b912e3558fe Mon Sep 17 00:00:00 2001 From: "S. VenkataKeerthy" <31350914+svkeerthy@users.noreply.github.com> Date: Thu, 23 Oct 2025 10:51:24 -0700 Subject: [PATCH 30/31] [llvm-ir2vec][MIR2Vec] Supporting MIR mode in triplet and entity generation (#164329) Add support for Machine IR (MIR) triplet and entity generation in llvm-ir2vec. This change extends llvm-ir2vec to support Machine IR (MIR) in addition to LLVM IR, enabling the generation of training data for MIR2Vec embeddings. MIR2Vec provides machine-level code embeddings that capture target-specific instruction semantics, complementing the target-independent IR2Vec embeddings. - Extended llvm-ir2vec to support triplet and entity generation for Machine IR (MIR) - Added `--mode=mir` option to specify MIR mode (vs LLVM IR mode) - Implemented MIR triplet generation with Next and Arg relationships - Added entity mapping generation for MIR vocabulary - Updated documentation to explain MIR-specific features and usage (Partially addresses #162200 ; Tracking issue - #141817) --- llvm/docs/CommandGuide/llvm-ir2vec.rst | 88 +- llvm/include/llvm/CodeGen/MIR2Vec.h | 38 + llvm/test/tools/llvm-ir2vec/entities.mir | 28 + .../tools/llvm-ir2vec/output/lit.local.cfg | 3 + .../llvm-ir2vec/output/reference_triplets.txt | 33 + .../output/reference_x86_entities.txt | 7174 +++++++++++++++++ llvm/test/tools/llvm-ir2vec/triplets.mir | 61 + llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp | 244 +- 8 files changed, 7621 insertions(+), 48 deletions(-) create mode 100644 llvm/test/tools/llvm-ir2vec/entities.mir create mode 100644 llvm/test/tools/llvm-ir2vec/output/lit.local.cfg create mode 100644 llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt create mode 100644 llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt create mode 100644 llvm/test/tools/llvm-ir2vec/triplets.mir diff --git a/llvm/docs/CommandGuide/llvm-ir2vec.rst b/llvm/docs/CommandGuide/llvm-ir2vec.rst index 55fe75d2084b1..f51da065b43d8 100644 --- a/llvm/docs/CommandGuide/llvm-ir2vec.rst +++ b/llvm/docs/CommandGuide/llvm-ir2vec.rst @@ -68,32 +68,52 @@ these two modes are used to generate the triplets and entity mappings. Triplet Generation ~~~~~~~~~~~~~~~~~~ -With the `triplets` subcommand, :program:`llvm-ir2vec` analyzes LLVM IR and extracts -numeric triplets consisting of opcode IDs, type IDs, and operand IDs. These triplets +With the `triplets` subcommand, :program:`llvm-ir2vec` analyzes LLVM IR or Machine IR +and extracts numeric triplets consisting of opcode IDs and operand IDs. These triplets are generated in the standard format used for knowledge graph embedding training. -The tool outputs numeric IDs directly using the ir2vec::Vocabulary mapping -infrastructure, eliminating the need for string-to-ID preprocessing. +The tool outputs numeric IDs directly using the vocabulary mapping infrastructure, +eliminating the need for string-to-ID preprocessing. -Usage: +Usage for LLVM IR: .. code-block:: bash - llvm-ir2vec triplets input.bc -o triplets_train2id.txt + llvm-ir2vec triplets --mode=llvm input.bc -o triplets_train2id.txt + +Usage for Machine IR: + +.. code-block:: bash + + llvm-ir2vec triplets --mode=mir input.mir -o triplets_train2id.txt Entity Mapping Generation ~~~~~~~~~~~~~~~~~~~~~~~~~ With the `entities` subcommand, :program:`llvm-ir2vec` generates the entity mappings -supported by IR2Vec in the standard format used for knowledge graph embedding -training. This subcommand outputs all supported entities (opcodes, types, and -operands) with their corresponding numeric IDs, and is not specific for an -LLVM IR file. +supported by IR2Vec or MIR2Vec in the standard format used for knowledge graph embedding +training. This subcommand outputs all supported entities with their corresponding numeric IDs. + +For LLVM IR, entities include opcodes, types, and operands. For Machine IR, entities include +machine opcodes, common operands, and register classes (both physical and virtual). + +Usage for LLVM IR: -Usage: +.. code-block:: bash + + llvm-ir2vec entities --mode=llvm -o entity2id.txt + +Usage for Machine IR: .. code-block:: bash - llvm-ir2vec entities -o entity2id.txt + llvm-ir2vec entities --mode=mir input.mir -o entity2id.txt + +.. note:: + + For LLVM IR mode, the entity mapping is target-independent and does not require an input file. + For Machine IR mode, an input .mir file is required to determine the target architecture, + as entity mappings vary by target (different architectures have different instruction sets + and register classes). Embedding Generation ~~~~~~~~~~~~~~~~~~~~ @@ -222,12 +242,17 @@ Subcommand-specific options: .. option:: - The input LLVM IR or bitcode file to process. This positional argument is - required for the `triplets` subcommand. + The input LLVM IR/bitcode file (.ll/.bc) or Machine IR file (.mir) to process. + This positional argument is required for the `triplets` subcommand. **entities** subcommand: - No subcommand-specific options. +.. option:: + + The input Machine IR file (.mir) to process. This positional argument is required + for the `entities` subcommand when using ``--mode=mir``, as the entity mappings + are target-specific. For ``--mode=llvm``, no input file is required as IR2Vec + entity mappings are target-independent. OUTPUT FORMAT ------------- @@ -240,19 +265,37 @@ metadata headers. The format includes: .. code-block:: text - MAX_RELATIONS= + MAX_RELATION= ... Each line after the metadata header represents one instruction relationship, -with numeric IDs for head entity, relation, and tail entity. The metadata -header (MAX_RELATIONS) provides counts for post-processing and training setup. +with numeric IDs for head entity, tail entity, and relation type. The metadata +header (MAX_RELATION) indicates the maximum relation ID used. + +**Relation Types:** + +For LLVM IR (IR2Vec): + * **0** = Type relationship (instruction to its type) + * **1** = Next relationship (sequential instructions) + * **2+** = Argument relationships (Arg0, Arg1, Arg2, ...) + +For Machine IR (MIR2Vec): + * **0** = Next relationship (sequential instructions) + * **1+** = Argument relationships (Arg0, Arg1, Arg2, ...) + +**Entity IDs:** + +For LLVM IR: Entity IDs represent opcodes, types, and operands as defined by the IR2Vec vocabulary. + +For Machine IR: Entity IDs represent machine opcodes, common operands (immediate, frame index, etc.), +physical register classes, and virtual register classes as defined by the MIR2Vec vocabulary. The entity layout is target-specific. Entity Mode Output ~~~~~~~~~~~~~~~~~~ -In entity mode, the output consists of entity mapping in the format: +In entity mode, the output consists of entity mappings in the format: .. code-block:: text @@ -264,6 +307,13 @@ In entity mode, the output consists of entity mapping in the format: The first line contains the total number of entities, followed by one entity mapping per line with tab-separated entity string and numeric ID. +For LLVM IR, entities include instruction opcodes (e.g., "Add", "Ret"), types +(e.g., "INT", "PTR"), and operand kinds. + +For Machine IR, entities include machine opcodes (e.g., "COPY", "ADD"), +common operands (e.g., "Immediate", "FrameIndex"), physical register classes +(e.g., "PhyReg_GR32"), and virtual register classes (e.g., "VirtReg_GR32"). + Embedding Mode Output ~~~~~~~~~~~~~~~~~~~~~ diff --git a/llvm/include/llvm/CodeGen/MIR2Vec.h b/llvm/include/llvm/CodeGen/MIR2Vec.h index 48bb0a5f2fed9..44f009cd7790e 100644 --- a/llvm/include/llvm/CodeGen/MIR2Vec.h +++ b/llvm/include/llvm/CodeGen/MIR2Vec.h @@ -111,6 +111,11 @@ class MIRVocabulary { size_t TotalEntries = 0; } Layout; + // TODO: See if we can have only one reg classes section instead of physical + // and virtual separate sections in the vocabulary. This would reduce the + // number of vocabulary entities significantly. + // We can potentially distinguish physical and virtual registers by + // considering them as a separate feature. enum class Section : unsigned { Opcodes = 0, CommonOperands = 1, @@ -185,6 +190,25 @@ class MIRVocabulary { return Storage[static_cast(SectionID)][LocalIndex]; } + /// Get entity ID (flat index) for a common operand type + /// This is used for triplet generation + unsigned getEntityIDForCommonOperand( + MachineOperand::MachineOperandType OperandType) const { + return Layout.CommonOperandBase + getCommonOperandIndex(OperandType); + } + + /// Get entity ID (flat index) for a register + /// This is used for triplet generation + unsigned getEntityIDForRegister(Register Reg) const { + if (!Reg.isValid() || Reg.isStack()) + return Layout + .VirtRegBase; // Return VirtRegBase for invalid/stack registers + unsigned LocalIndex = getRegisterOperandIndex(Reg); + size_t BaseOffset = + Reg.isPhysical() ? Layout.PhyRegBase : Layout.VirtRegBase; + return BaseOffset + LocalIndex; + } + public: /// Static method for extracting base opcode names (public for testing) static std::string extractBaseOpcodeName(StringRef InstrName); @@ -201,6 +225,20 @@ class MIRVocabulary { unsigned getDimension() const { return Storage.getDimension(); } + /// Get entity ID (flat index) for an opcode + /// This is used for triplet generation + unsigned getEntityIDForOpcode(unsigned Opcode) const { + return Layout.OpcodeBase + getCanonicalOpcodeIndex(Opcode); + } + + /// Get entity ID (flat index) for a machine operand + /// This is used for triplet generation + unsigned getEntityIDForMachineOperand(const MachineOperand &MO) const { + if (MO.getType() == MachineOperand::MO_Register) + return getEntityIDForRegister(MO.getReg()); + return getEntityIDForCommonOperand(MO.getType()); + } + // Accessor methods const Embedding &operator[](unsigned Opcode) const { unsigned LocalIndex = getCanonicalOpcodeIndex(Opcode); diff --git a/llvm/test/tools/llvm-ir2vec/entities.mir b/llvm/test/tools/llvm-ir2vec/entities.mir new file mode 100644 index 0000000000000..60d9c7a783c4c --- /dev/null +++ b/llvm/test/tools/llvm-ir2vec/entities.mir @@ -0,0 +1,28 @@ +# REQUIRES: x86_64-linux +# RUN: llvm-ir2vec entities --mode=mir %s -o 2>&1 %t1.log +# RUN: diff %S/output/reference_x86_entities.txt %t1.log + +--- | + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" + target triple = "x86_64-unknown-linux-gnu" + + define dso_local noundef i32 @test_function(i32 noundef %a) { + entry: + ret i32 %a + } +... +--- +name: test_function +alignment: 16 +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } +liveins: + - { reg: '$edi', virtual-reg: '%0' } +body: | + bb.0.entry: + liveins: $edi + + %0:gr32 = COPY $edi + $eax = COPY %0 + RET 0, $eax diff --git a/llvm/test/tools/llvm-ir2vec/output/lit.local.cfg b/llvm/test/tools/llvm-ir2vec/output/lit.local.cfg new file mode 100644 index 0000000000000..2406f19eebcdd --- /dev/null +++ b/llvm/test/tools/llvm-ir2vec/output/lit.local.cfg @@ -0,0 +1,3 @@ +# Don't treat files in this directory as tests +# These are reference data files, not test scripts +config.suffixes = [] diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt new file mode 100644 index 0000000000000..dfbac4ce0c4d3 --- /dev/null +++ b/llvm/test/tools/llvm-ir2vec/output/reference_triplets.txt @@ -0,0 +1,33 @@ +MAX_RELATION=4 +187 7072 1 +187 6968 2 +187 187 0 +187 7072 1 +187 6969 2 +187 10 0 +10 7072 1 +10 7072 2 +10 7072 3 +10 6961 4 +10 187 0 +187 6952 1 +187 7072 2 +187 1555 0 +1555 6882 1 +1555 6952 2 +187 7072 1 +187 6968 2 +187 187 0 +187 7072 1 +187 6969 2 +187 601 0 +601 7072 1 +601 7072 2 +601 7072 3 +601 6961 4 +601 187 0 +187 6952 1 +187 7072 2 +187 1555 0 +1555 6882 1 +1555 6952 2 diff --git a/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt new file mode 100644 index 0000000000000..dc436d123fd35 --- /dev/null +++ b/llvm/test/tools/llvm-ir2vec/output/reference_x86_entities.txt @@ -0,0 +1,7174 @@ +7173 +AAA 0 +AAD 1 +AADD 2 +AAM 3 +AAND 4 +AAS 5 +ABS_F 6 +ABS_Fp 7 +ADC 8 +ADCX 9 +ADD 10 +ADDPDrm 11 +ADDPDrr 12 +ADDPSrm 13 +ADDPSrr 14 +ADDR 15 +ADDSDrm 16 +ADDSDrm_Int 17 +ADDSDrr 18 +ADDSDrr_Int 19 +ADDSSrm 20 +ADDSSrm_Int 21 +ADDSSrr 22 +ADDSSrr_Int 23 +ADDSUBPDrm 24 +ADDSUBPDrr 25 +ADDSUBPSrm 26 +ADDSUBPSrr 27 +ADD_F 28 +ADD_FI 29 +ADD_FPrST 30 +ADD_FST 31 +ADD_Fp 32 +ADD_FpI 33 +ADD_FrST 34 +ADJCALLSTACKDOWN 35 +ADJCALLSTACKUP 36 +ADOX 37 +AESDEC 38 +AESDECLASTrm 39 +AESDECLASTrr 40 +AESDECWIDE 41 +AESDECrm 42 +AESDECrr 43 +AESENC 44 +AESENCLASTrm 45 +AESENCLASTrr 46 +AESENCWIDE 47 +AESENCrm 48 +AESENCrr 49 +AESIMCrm 50 +AESIMCrr 51 +AESKEYGENASSISTrmi 52 +AESKEYGENASSISTrri 53 +AND 54 +ANDN 55 +ANDNPDrm 56 +ANDNPDrr 57 +ANDNPSrm 58 +ANDNPSrr 59 +ANDPDrm 60 +ANDPDrr 61 +ANDPSrm 62 +ANDPSrr 63 +ANNOTATION_LABEL 64 +AOR 65 +ARITH_FENCE 66 +ARPL 67 +ASAN_CHECK_MEMACCESS 68 +AVX 69 +AVX_SET 70 +AXOR 71 +BEXTR 72 +BEXTRI 73 +BLCFILL 74 +BLCI 75 +BLCIC 76 +BLCMSK 77 +BLCS 78 +BLENDPDrmi 79 +BLENDPDrri 80 +BLENDPSrmi 81 +BLENDPSrri 82 +BLENDVPDrm 83 +BLENDVPDrr 84 +BLENDVPSrm 85 +BLENDVPSrr 86 +BLSFILL 87 +BLSI 88 +BLSIC 89 +BLSMSK 90 +BLSR 91 +BOUNDS 92 +BSF 93 +BSR 94 +BSWAP 95 +BT 96 +BTC 97 +BTR 98 +BTS 99 +BUNDLE 100 +BZHI 101 +CALL 102 +CALLpcrel 103 +CATCHRET 104 +CBW 105 +CCMP 106 +CDQ 107 +CDQE 108 +CFCMOV 109 +CFI_INSTRUCTION 110 +CHS_F 111 +CHS_Fp 112 +CLAC 113 +CLC 114 +CLD 115 +CLDEMOTE 116 +CLEANUPRET 117 +CLFLUSH 118 +CLFLUSHOPT 119 +CLGI 120 +CLI 121 +CLRSSBSY 122 +CLTS 123 +CLUI 124 +CLWB 125 +CLZERO 126 +CMC 127 +CMOV 128 +CMOVBE_F 129 +CMOVBE_Fp 130 +CMOVB_F 131 +CMOVB_Fp 132 +CMOVE_F 133 +CMOVE_Fp 134 +CMOVNBE_F 135 +CMOVNBE_Fp 136 +CMOVNB_F 137 +CMOVNB_Fp 138 +CMOVNE_F 139 +CMOVNE_Fp 140 +CMOVNP_F 141 +CMOVNP_Fp 142 +CMOVP_F 143 +CMOVP_Fp 144 +CMOV_FR 145 +CMOV_GR 146 +CMOV_RFP 147 +CMOV_VK 148 +CMOV_VR 149 +CMP 150 +CMPCCXADDmr 151 +CMPPDrmi 152 +CMPPDrri 153 +CMPPSrmi 154 +CMPPSrri 155 +CMPSB 156 +CMPSDrmi 157 +CMPSDrmi_Int 158 +CMPSDrri 159 +CMPSDrri_Int 160 +CMPSL 161 +CMPSQ 162 +CMPSSrmi 163 +CMPSSrmi_Int 164 +CMPSSrri 165 +CMPSSrri_Int 166 +CMPSW 167 +CMPXCHG 168 +COMISDrm 169 +COMISDrm_Int 170 +COMISDrr 171 +COMISDrr_Int 172 +COMISSrm 173 +COMISSrm_Int 174 +COMISSrr 175 +COMISSrr_Int 176 +COMP_FST 177 +COM_FIPr 178 +COM_FIr 179 +COM_FST 180 +COM_FpIr 181 +COM_Fpr 182 +CONVERGENCECTRL_ANCHOR 183 +CONVERGENCECTRL_ENTRY 184 +CONVERGENCECTRL_GLUE 185 +CONVERGENCECTRL_LOOP 186 +COPY 187 +COPY_TO_REGCLASS 188 +CPUID 189 +CQO 190 +CRC 191 +CS_PREFIX 192 +CTEST 193 +CVTDQ 194 +CVTPD 195 +CVTPS 196 +CVTSD 197 +CVTSI 198 +CVTSS 199 +CVTTPD 200 +CVTTPS 201 +CVTTSD 202 +CVTTSS 203 +CWD 204 +CWDE 205 +DAA 206 +DAS 207 +DATA 208 +DBG_INSTR_REF 209 +DBG_LABEL 210 +DBG_PHI 211 +DBG_VALUE 212 +DBG_VALUE_LIST 213 +DEC 214 +DIV 215 +DIVPDrm 216 +DIVPDrr 217 +DIVPSrm 218 +DIVPSrr 219 +DIVR_F 220 +DIVR_FI 221 +DIVR_FPrST 222 +DIVR_FST 223 +DIVR_Fp 224 +DIVR_FpI 225 +DIVR_FrST 226 +DIVSDrm 227 +DIVSDrm_Int 228 +DIVSDrr 229 +DIVSDrr_Int 230 +DIVSSrm 231 +DIVSSrm_Int 232 +DIVSSrr 233 +DIVSSrr_Int 234 +DIV_F 235 +DIV_FI 236 +DIV_FPrST 237 +DIV_FST 238 +DIV_Fp 239 +DIV_FpI 240 +DIV_FrST 241 +DPPDrmi 242 +DPPDrri 243 +DPPSrmi 244 +DPPSrri 245 +DS_PREFIX 246 +DYN_ALLOCA 247 +EH_LABEL 248 +EH_RETURN 249 +EH_SjLj_LongJmp 250 +EH_SjLj_SetJmp 251 +EH_SjLj_Setup 252 +ENCLS 253 +ENCLU 254 +ENCLV 255 +ENCODEKEY 256 +ENDBR 257 +ENQCMD 258 +ENQCMDS 259 +ENTER 260 +ERETS 261 +ERETU 262 +ES_PREFIX 263 +EXTRACTPSmri 264 +EXTRACTPSrri 265 +EXTRACT_SUBREG 266 +EXTRQ 267 +EXTRQI 268 +F 269 +FAKE_USE 270 +FARCALL 271 +FARJMP 272 +FAULTING_OP 273 +FBLDm 274 +FBSTPm 275 +FCOM 276 +FCOMP 277 +FCOMPP 278 +FCOS 279 +FDECSTP 280 +FEMMS 281 +FENTRY_CALL 282 +FFREE 283 +FFREEP 284 +FICOM 285 +FICOMP 286 +FINCSTP 287 +FLDCW 288 +FLDENVm 289 +FLDL 290 +FLDLG 291 +FLDLN 292 +FLDPI 293 +FNCLEX 294 +FNINIT 295 +FNOP 296 +FNSTCW 297 +FNSTSW 298 +FNSTSWm 299 +FP 300 +FPATAN 301 +FPREM 302 +FPTAN 303 +FRNDINT 304 +FRSTORm 305 +FSAVEm 306 +FSCALE 307 +FSIN 308 +FSINCOS 309 +FSTENVm 310 +FS_PREFIX 311 +FXRSTOR 312 +FXSAVE 313 +FXTRACT 314 +FYL 315 +FsFLD 316 +GC_LABEL 317 +GETSEC 318 +GF 319 +GS_PREFIX 320 +G_ABDS 321 +G_ABDU 322 +G_ABS 323 +G_ADD 324 +G_ADDRSPACE_CAST 325 +G_AND 326 +G_ANYEXT 327 +G_ASHR 328 +G_ASSERT_ALIGN 329 +G_ASSERT_SEXT 330 +G_ASSERT_ZEXT 331 +G_ATOMICRMW_ADD 332 +G_ATOMICRMW_AND 333 +G_ATOMICRMW_FADD 334 +G_ATOMICRMW_FMAX 335 +G_ATOMICRMW_FMAXIMUM 336 +G_ATOMICRMW_FMIN 337 +G_ATOMICRMW_FMINIMUM 338 +G_ATOMICRMW_FSUB 339 +G_ATOMICRMW_MAX 340 +G_ATOMICRMW_MIN 341 +G_ATOMICRMW_NAND 342 +G_ATOMICRMW_OR 343 +G_ATOMICRMW_SUB 344 +G_ATOMICRMW_UDEC_WRAP 345 +G_ATOMICRMW_UINC_WRAP 346 +G_ATOMICRMW_UMAX 347 +G_ATOMICRMW_UMIN 348 +G_ATOMICRMW_USUB_COND 349 +G_ATOMICRMW_USUB_SAT 350 +G_ATOMICRMW_XCHG 351 +G_ATOMICRMW_XOR 352 +G_ATOMIC_CMPXCHG 353 +G_ATOMIC_CMPXCHG_WITH_SUCCESS 354 +G_BITCAST 355 +G_BITREVERSE 356 +G_BLOCK_ADDR 357 +G_BR 358 +G_BRCOND 359 +G_BRINDIRECT 360 +G_BRJT 361 +G_BSWAP 362 +G_BUILD_VECTOR 363 +G_BUILD_VECTOR_TRUNC 364 +G_BZERO 365 +G_CONCAT_VECTORS 366 +G_CONSTANT 367 +G_CONSTANT_FOLD_BARRIER 368 +G_CONSTANT_POOL 369 +G_CTLZ 370 +G_CTLZ_ZERO_UNDEF 371 +G_CTPOP 372 +G_CTTZ 373 +G_CTTZ_ZERO_UNDEF 374 +G_DEBUGTRAP 375 +G_DYN_STACKALLOC 376 +G_EXTRACT 377 +G_EXTRACT_SUBVECTOR 378 +G_EXTRACT_VECTOR_ELT 379 +G_FABS 380 +G_FACOS 381 +G_FADD 382 +G_FASIN 383 +G_FATAN 384 +G_FCANONICALIZE 385 +G_FCEIL 386 +G_FCMP 387 +G_FCONSTANT 388 +G_FCOPYSIGN 389 +G_FCOS 390 +G_FCOSH 391 +G_FDIV 392 +G_FENCE 393 +G_FEXP 394 +G_FFLOOR 395 +G_FFREXP 396 +G_FILD 397 +G_FIST 398 +G_FLDCW 399 +G_FLDEXP 400 +G_FLOG 401 +G_FMA 402 +G_FMAD 403 +G_FMAXIMUM 404 +G_FMAXIMUMNUM 405 +G_FMAXNUM 406 +G_FMAXNUM_IEEE 407 +G_FMINIMUM 408 +G_FMINIMUMNUM 409 +G_FMINNUM 410 +G_FMINNUM_IEEE 411 +G_FMODF 412 +G_FMUL 413 +G_FNEARBYINT 414 +G_FNEG 415 +G_FNSTCW 416 +G_FPEXT 417 +G_FPOW 418 +G_FPOWI 419 +G_FPTOSI 420 +G_FPTOSI_SAT 421 +G_FPTOUI 422 +G_FPTOUI_SAT 423 +G_FPTRUNC 424 +G_FRAME_INDEX 425 +G_FREEZE 426 +G_FREM 427 +G_FRINT 428 +G_FSHL 429 +G_FSHR 430 +G_FSIN 431 +G_FSINCOS 432 +G_FSINH 433 +G_FSQRT 434 +G_FSUB 435 +G_FTAN 436 +G_FTANH 437 +G_GET_FPENV 438 +G_GET_FPMODE 439 +G_GET_ROUNDING 440 +G_GLOBAL_VALUE 441 +G_ICMP 442 +G_IMPLICIT_DEF 443 +G_INDEXED_LOAD 444 +G_INDEXED_SEXTLOAD 445 +G_INDEXED_STORE 446 +G_INDEXED_ZEXTLOAD 447 +G_INSERT 448 +G_INSERT_SUBVECTOR 449 +G_INSERT_VECTOR_ELT 450 +G_INTRINSIC 451 +G_INTRINSIC_CONVERGENT 452 +G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS 453 +G_INTRINSIC_FPTRUNC_ROUND 454 +G_INTRINSIC_LLRINT 455 +G_INTRINSIC_LRINT 456 +G_INTRINSIC_ROUND 457 +G_INTRINSIC_ROUNDEVEN 458 +G_INTRINSIC_TRUNC 459 +G_INTRINSIC_W_SIDE_EFFECTS 460 +G_INTTOPTR 461 +G_INVOKE_REGION_START 462 +G_IS_FPCLASS 463 +G_JUMP_TABLE 464 +G_LLROUND 465 +G_LOAD 466 +G_LROUND 467 +G_LSHR 468 +G_MEMCPY 469 +G_MEMCPY_INLINE 470 +G_MEMMOVE 471 +G_MEMSET 472 +G_MERGE_VALUES 473 +G_MUL 474 +G_OR 475 +G_PHI 476 +G_PREFETCH 477 +G_PTRAUTH_GLOBAL_VALUE 478 +G_PTRMASK 479 +G_PTRTOINT 480 +G_PTR_ADD 481 +G_READCYCLECOUNTER 482 +G_READSTEADYCOUNTER 483 +G_READ_REGISTER 484 +G_RESET_FPENV 485 +G_RESET_FPMODE 486 +G_ROTL 487 +G_ROTR 488 +G_SADDE 489 +G_SADDO 490 +G_SADDSAT 491 +G_SBFX 492 +G_SCMP 493 +G_SDIV 494 +G_SDIVFIX 495 +G_SDIVFIXSAT 496 +G_SDIVREM 497 +G_SELECT 498 +G_SET_FPENV 499 +G_SET_FPMODE 500 +G_SET_ROUNDING 501 +G_SEXT 502 +G_SEXTLOAD 503 +G_SEXT_INREG 504 +G_SHL 505 +G_SHUFFLE_VECTOR 506 +G_SITOFP 507 +G_SMAX 508 +G_SMIN 509 +G_SMULFIX 510 +G_SMULFIXSAT 511 +G_SMULH 512 +G_SMULO 513 +G_SPLAT_VECTOR 514 +G_SREM 515 +G_SSHLSAT 516 +G_SSUBE 517 +G_SSUBO 518 +G_SSUBSAT 519 +G_STACKRESTORE 520 +G_STACKSAVE 521 +G_STEP_VECTOR 522 +G_STORE 523 +G_STRICT_FADD 524 +G_STRICT_FDIV 525 +G_STRICT_FLDEXP 526 +G_STRICT_FMA 527 +G_STRICT_FMUL 528 +G_STRICT_FREM 529 +G_STRICT_FSQRT 530 +G_STRICT_FSUB 531 +G_SUB 532 +G_TRAP 533 +G_TRUNC 534 +G_TRUNC_SSAT_S 535 +G_TRUNC_SSAT_U 536 +G_TRUNC_USAT_U 537 +G_UADDE 538 +G_UADDO 539 +G_UADDSAT 540 +G_UBFX 541 +G_UBSANTRAP 542 +G_UCMP 543 +G_UDIV 544 +G_UDIVFIX 545 +G_UDIVFIXSAT 546 +G_UDIVREM 547 +G_UITOFP 548 +G_UMAX 549 +G_UMIN 550 +G_UMULFIX 551 +G_UMULFIXSAT 552 +G_UMULH 553 +G_UMULO 554 +G_UNMERGE_VALUES 555 +G_UREM 556 +G_USHLSAT 557 +G_USUBE 558 +G_USUBO 559 +G_USUBSAT 560 +G_VAARG 561 +G_VASTART 562 +G_VECREDUCE_ADD 563 +G_VECREDUCE_AND 564 +G_VECREDUCE_FADD 565 +G_VECREDUCE_FMAX 566 +G_VECREDUCE_FMAXIMUM 567 +G_VECREDUCE_FMIN 568 +G_VECREDUCE_FMINIMUM 569 +G_VECREDUCE_FMUL 570 +G_VECREDUCE_MUL 571 +G_VECREDUCE_OR 572 +G_VECREDUCE_SEQ_FADD 573 +G_VECREDUCE_SEQ_FMUL 574 +G_VECREDUCE_SMAX 575 +G_VECREDUCE_SMIN 576 +G_VECREDUCE_UMAX 577 +G_VECREDUCE_UMIN 578 +G_VECREDUCE_XOR 579 +G_VECTOR_COMPRESS 580 +G_VSCALE 581 +G_WRITE_REGISTER 582 +G_XOR 583 +G_ZEXT 584 +G_ZEXTLOAD 585 +HADDPDrm 586 +HADDPDrr 587 +HADDPSrm 588 +HADDPSrr 589 +HLT 590 +HRESET 591 +HSUBPDrm 592 +HSUBPDrr 593 +HSUBPSrm 594 +HSUBPSrr 595 +ICALL_BRANCH_FUNNEL 596 +IDIV 597 +ILD_F 598 +ILD_Fp 599 +IMPLICIT_DEF 600 +IMUL 601 +IMULZU 602 +IN 603 +INC 604 +INCSSPD 605 +INCSSPQ 606 +INDIRECT_THUNK_CALL 607 +INDIRECT_THUNK_TCRETURN 608 +INIT_UNDEF 609 +INLINEASM 610 +INLINEASM_BR 611 +INSB 612 +INSERTPSrmi 613 +INSERTPSrri 614 +INSERTQ 615 +INSERTQI 616 +INSERT_SUBREG 617 +INSL 618 +INSW 619 +INT 620 +INTO 621 +INVD 622 +INVEPT 623 +INVLPG 624 +INVLPGA 625 +INVLPGB 626 +INVPCID 627 +INVVPID 628 +IRET 629 +ISTT_FP 630 +ISTT_Fp 631 +IST_F 632 +IST_FP 633 +IST_Fp 634 +Int_eh_sjlj_setup_dispatch 635 +JCC 636 +JCXZ 637 +JECXZ 638 +JMP 639 +JMPABS 640 +JRCXZ 641 +JUMP_TABLE_DEBUG_INFO 642 +KADDBkk 643 +KADDDkk 644 +KADDQkk 645 +KADDWkk 646 +KANDBkk 647 +KANDDkk 648 +KANDNBkk 649 +KANDNDkk 650 +KANDNQkk 651 +KANDNWkk 652 +KANDQkk 653 +KANDWkk 654 +KCFI_CHECK 655 +KILL 656 +KMOVBkk 657 +KMOVBkk_EVEX 658 +KMOVBkm 659 +KMOVBkm_EVEX 660 +KMOVBkr 661 +KMOVBkr_EVEX 662 +KMOVBmk 663 +KMOVBmk_EVEX 664 +KMOVBrk 665 +KMOVBrk_EVEX 666 +KMOVDkk 667 +KMOVDkk_EVEX 668 +KMOVDkm 669 +KMOVDkm_EVEX 670 +KMOVDkr 671 +KMOVDkr_EVEX 672 +KMOVDmk 673 +KMOVDmk_EVEX 674 +KMOVDrk 675 +KMOVDrk_EVEX 676 +KMOVQkk 677 +KMOVQkk_EVEX 678 +KMOVQkm 679 +KMOVQkm_EVEX 680 +KMOVQkr 681 +KMOVQkr_EVEX 682 +KMOVQmk 683 +KMOVQmk_EVEX 684 +KMOVQrk 685 +KMOVQrk_EVEX 686 +KMOVWkk 687 +KMOVWkk_EVEX 688 +KMOVWkm 689 +KMOVWkm_EVEX 690 +KMOVWkr 691 +KMOVWkr_EVEX 692 +KMOVWmk 693 +KMOVWmk_EVEX 694 +KMOVWrk 695 +KMOVWrk_EVEX 696 +KNOTBkk 697 +KNOTDkk 698 +KNOTQkk 699 +KNOTWkk 700 +KORBkk 701 +KORDkk 702 +KORQkk 703 +KORTESTBkk 704 +KORTESTDkk 705 +KORTESTQkk 706 +KORTESTWkk 707 +KORWkk 708 +KSET 709 +KSHIFTLBki 710 +KSHIFTLDki 711 +KSHIFTLQki 712 +KSHIFTLWki 713 +KSHIFTRBki 714 +KSHIFTRDki 715 +KSHIFTRQki 716 +KSHIFTRWki 717 +KTESTBkk 718 +KTESTDkk 719 +KTESTQkk 720 +KTESTWkk 721 +KUNPCKBWkk 722 +KUNPCKDQkk 723 +KUNPCKWDkk 724 +KXNORBkk 725 +KXNORDkk 726 +KXNORQkk 727 +KXNORWkk 728 +KXORBkk 729 +KXORDkk 730 +KXORQkk 731 +KXORWkk 732 +LAHF 733 +LAR 734 +LCMPXCHG 735 +LDDQUrm 736 +LDMXCSR 737 +LDS 738 +LDTILECFG 739 +LDTILECFG_EVEX 740 +LD_F 741 +LD_Fp 742 +LD_Frr 743 +LEA 744 +LEAVE 745 +LES 746 +LFENCE 747 +LFS 748 +LGDT 749 +LGS 750 +LIDT 751 +LIFETIME_END 752 +LIFETIME_START 753 +LKGS 754 +LLDT 755 +LLWPCB 756 +LMSW 757 +LOADIWKEY 758 +LOAD_STACK_GUARD 759 +LOCAL_ESCAPE 760 +LOCK_ADD 761 +LOCK_AND 762 +LOCK_BTC 763 +LOCK_BTC_RM 764 +LOCK_BTR 765 +LOCK_BTR_RM 766 +LOCK_BTS 767 +LOCK_BTS_RM 768 +LOCK_DEC 769 +LOCK_INC 770 +LOCK_OR 771 +LOCK_PREFIX 772 +LOCK_SUB 773 +LOCK_XOR 774 +LODSB 775 +LODSL 776 +LODSQ 777 +LODSW 778 +LOOP 779 +LOOPE 780 +LOOPNE 781 +LRET 782 +LRETI 783 +LSL 784 +LSS 785 +LTRm 786 +LTRr 787 +LWPINS 788 +LWPVAL 789 +LXADD 790 +LZCNT 791 +MASKMOVDQU 792 +MASKPAIR 793 +MAXCPDrm 794 +MAXCPDrr 795 +MAXCPSrm 796 +MAXCPSrr 797 +MAXCSDrm 798 +MAXCSDrr 799 +MAXCSSrm 800 +MAXCSSrr 801 +MAXPDrm 802 +MAXPDrr 803 +MAXPSrm 804 +MAXPSrr 805 +MAXSDrm 806 +MAXSDrm_Int 807 +MAXSDrr 808 +MAXSDrr_Int 809 +MAXSSrm 810 +MAXSSrm_Int 811 +MAXSSrr 812 +MAXSSrr_Int 813 +MEMBARRIER 814 +MFENCE 815 +MINCPDrm 816 +MINCPDrr 817 +MINCPSrm 818 +MINCPSrr 819 +MINCSDrm 820 +MINCSDrr 821 +MINCSSrm 822 +MINCSSrr 823 +MINPDrm 824 +MINPDrr 825 +MINPSrm 826 +MINPSrr 827 +MINSDrm 828 +MINSDrm_Int 829 +MINSDrr 830 +MINSDrr_Int 831 +MINSSrm 832 +MINSSrm_Int 833 +MINSSrr 834 +MINSSrr_Int 835 +MMX_CVTPD 836 +MMX_CVTPI 837 +MMX_CVTPS 838 +MMX_CVTTPD 839 +MMX_CVTTPS 840 +MMX_EMMS 841 +MMX_MASKMOVQ 842 +MMX_MOVD 843 +MMX_MOVDQ 844 +MMX_MOVFR 845 +MMX_MOVNTQmr 846 +MMX_MOVQ 847 +MMX_PABSBrm 848 +MMX_PABSBrr 849 +MMX_PABSDrm 850 +MMX_PABSDrr 851 +MMX_PABSWrm 852 +MMX_PABSWrr 853 +MMX_PACKSSDWrm 854 +MMX_PACKSSDWrr 855 +MMX_PACKSSWBrm 856 +MMX_PACKSSWBrr 857 +MMX_PACKUSWBrm 858 +MMX_PACKUSWBrr 859 +MMX_PADDBrm 860 +MMX_PADDBrr 861 +MMX_PADDDrm 862 +MMX_PADDDrr 863 +MMX_PADDQrm 864 +MMX_PADDQrr 865 +MMX_PADDSBrm 866 +MMX_PADDSBrr 867 +MMX_PADDSWrm 868 +MMX_PADDSWrr 869 +MMX_PADDUSBrm 870 +MMX_PADDUSBrr 871 +MMX_PADDUSWrm 872 +MMX_PADDUSWrr 873 +MMX_PADDWrm 874 +MMX_PADDWrr 875 +MMX_PALIGNRrmi 876 +MMX_PALIGNRrri 877 +MMX_PANDNrm 878 +MMX_PANDNrr 879 +MMX_PANDrm 880 +MMX_PANDrr 881 +MMX_PAVGBrm 882 +MMX_PAVGBrr 883 +MMX_PAVGWrm 884 +MMX_PAVGWrr 885 +MMX_PCMPEQBrm 886 +MMX_PCMPEQBrr 887 +MMX_PCMPEQDrm 888 +MMX_PCMPEQDrr 889 +MMX_PCMPEQWrm 890 +MMX_PCMPEQWrr 891 +MMX_PCMPGTBrm 892 +MMX_PCMPGTBrr 893 +MMX_PCMPGTDrm 894 +MMX_PCMPGTDrr 895 +MMX_PCMPGTWrm 896 +MMX_PCMPGTWrr 897 +MMX_PEXTRWrri 898 +MMX_PHADDDrm 899 +MMX_PHADDDrr 900 +MMX_PHADDSWrm 901 +MMX_PHADDSWrr 902 +MMX_PHADDWrm 903 +MMX_PHADDWrr 904 +MMX_PHSUBDrm 905 +MMX_PHSUBDrr 906 +MMX_PHSUBSWrm 907 +MMX_PHSUBSWrr 908 +MMX_PHSUBWrm 909 +MMX_PHSUBWrr 910 +MMX_PINSRWrmi 911 +MMX_PINSRWrri 912 +MMX_PMADDUBSWrm 913 +MMX_PMADDUBSWrr 914 +MMX_PMADDWDrm 915 +MMX_PMADDWDrr 916 +MMX_PMAXSWrm 917 +MMX_PMAXSWrr 918 +MMX_PMAXUBrm 919 +MMX_PMAXUBrr 920 +MMX_PMINSWrm 921 +MMX_PMINSWrr 922 +MMX_PMINUBrm 923 +MMX_PMINUBrr 924 +MMX_PMOVMSKBrr 925 +MMX_PMULHRSWrm 926 +MMX_PMULHRSWrr 927 +MMX_PMULHUWrm 928 +MMX_PMULHUWrr 929 +MMX_PMULHWrm 930 +MMX_PMULHWrr 931 +MMX_PMULLWrm 932 +MMX_PMULLWrr 933 +MMX_PMULUDQrm 934 +MMX_PMULUDQrr 935 +MMX_PORrm 936 +MMX_PORrr 937 +MMX_PSADBWrm 938 +MMX_PSADBWrr 939 +MMX_PSHUFBrm 940 +MMX_PSHUFBrr 941 +MMX_PSHUFWmi 942 +MMX_PSHUFWri 943 +MMX_PSIGNBrm 944 +MMX_PSIGNBrr 945 +MMX_PSIGNDrm 946 +MMX_PSIGNDrr 947 +MMX_PSIGNWrm 948 +MMX_PSIGNWrr 949 +MMX_PSLLDri 950 +MMX_PSLLDrm 951 +MMX_PSLLDrr 952 +MMX_PSLLQri 953 +MMX_PSLLQrm 954 +MMX_PSLLQrr 955 +MMX_PSLLWri 956 +MMX_PSLLWrm 957 +MMX_PSLLWrr 958 +MMX_PSRADri 959 +MMX_PSRADrm 960 +MMX_PSRADrr 961 +MMX_PSRAWri 962 +MMX_PSRAWrm 963 +MMX_PSRAWrr 964 +MMX_PSRLDri 965 +MMX_PSRLDrm 966 +MMX_PSRLDrr 967 +MMX_PSRLQri 968 +MMX_PSRLQrm 969 +MMX_PSRLQrr 970 +MMX_PSRLWri 971 +MMX_PSRLWrm 972 +MMX_PSRLWrr 973 +MMX_PSUBBrm 974 +MMX_PSUBBrr 975 +MMX_PSUBDrm 976 +MMX_PSUBDrr 977 +MMX_PSUBQrm 978 +MMX_PSUBQrr 979 +MMX_PSUBSBrm 980 +MMX_PSUBSBrr 981 +MMX_PSUBSWrm 982 +MMX_PSUBSWrr 983 +MMX_PSUBUSBrm 984 +MMX_PSUBUSBrr 985 +MMX_PSUBUSWrm 986 +MMX_PSUBUSWrr 987 +MMX_PSUBWrm 988 +MMX_PSUBWrr 989 +MMX_PUNPCKHBWrm 990 +MMX_PUNPCKHBWrr 991 +MMX_PUNPCKHDQrm 992 +MMX_PUNPCKHDQrr 993 +MMX_PUNPCKHWDrm 994 +MMX_PUNPCKHWDrr 995 +MMX_PUNPCKLBWrm 996 +MMX_PUNPCKLBWrr 997 +MMX_PUNPCKLDQrm 998 +MMX_PUNPCKLDQrr 999 +MMX_PUNPCKLWDrm 1000 +MMX_PUNPCKLWDrr 1001 +MMX_PXORrm 1002 +MMX_PXORrr 1003 +MMX_SET 1004 +MONITOR 1005 +MONITORX 1006 +MONTMUL 1007 +MORESTACK_RET 1008 +MORESTACK_RET_RESTORE_R 1009 +MOV 1010 +MOVAPDmr 1011 +MOVAPDrm 1012 +MOVAPDrr 1013 +MOVAPDrr_REV 1014 +MOVAPSmr 1015 +MOVAPSrm 1016 +MOVAPSrr 1017 +MOVAPSrr_REV 1018 +MOVBE 1019 +MOVDDUPrm 1020 +MOVDDUPrr 1021 +MOVDI 1022 +MOVDIR 1023 +MOVDIRI 1024 +MOVDQAmr 1025 +MOVDQArm 1026 +MOVDQArr 1027 +MOVDQArr_REV 1028 +MOVDQUmr 1029 +MOVDQUrm 1030 +MOVDQUrr 1031 +MOVDQUrr_REV 1032 +MOVHLPSrr 1033 +MOVHPDmr 1034 +MOVHPDrm 1035 +MOVHPSmr 1036 +MOVHPSrm 1037 +MOVLHPSrr 1038 +MOVLPDmr 1039 +MOVLPDrm 1040 +MOVLPSmr 1041 +MOVLPSrm 1042 +MOVMSKPDrr 1043 +MOVMSKPSrr 1044 +MOVNTDQArm 1045 +MOVNTDQmr 1046 +MOVNTI 1047 +MOVNTImr 1048 +MOVNTPDmr 1049 +MOVNTPSmr 1050 +MOVNTSD 1051 +MOVNTSS 1052 +MOVPC 1053 +MOVPDI 1054 +MOVPQI 1055 +MOVPQIto 1056 +MOVQI 1057 +MOVRS 1058 +MOVSB 1059 +MOVSDmr 1060 +MOVSDrm 1061 +MOVSDrm_alt 1062 +MOVSDrr 1063 +MOVSDrr_REV 1064 +MOVSDto 1065 +MOVSHDUPrm 1066 +MOVSHDUPrr 1067 +MOVSHPmr 1068 +MOVSHPrm 1069 +MOVSL 1070 +MOVSLDUPrm 1071 +MOVSLDUPrr 1072 +MOVSQ 1073 +MOVSS 1074 +MOVSSmr 1075 +MOVSSrm 1076 +MOVSSrm_alt 1077 +MOVSSrr 1078 +MOVSSrr_REV 1079 +MOVSW 1080 +MOVSX 1081 +MOVUPDmr 1082 +MOVUPDrm 1083 +MOVUPDrr 1084 +MOVUPDrr_REV 1085 +MOVUPSmr 1086 +MOVUPSrm 1087 +MOVUPSrr 1088 +MOVUPSrr_REV 1089 +MOVZPQILo 1090 +MOVZX 1091 +MPSADBWrmi 1092 +MPSADBWrri 1093 +MUL 1094 +MULPDrm 1095 +MULPDrr 1096 +MULPSrm 1097 +MULPSrr 1098 +MULSDrm 1099 +MULSDrm_Int 1100 +MULSDrr 1101 +MULSDrr_Int 1102 +MULSSrm 1103 +MULSSrm_Int 1104 +MULSSrr 1105 +MULSSrr_Int 1106 +MULX 1107 +MUL_F 1108 +MUL_FI 1109 +MUL_FPrST 1110 +MUL_FST 1111 +MUL_Fp 1112 +MUL_FpI 1113 +MUL_FrST 1114 +MWAITX 1115 +MWAITX_SAVE_RBX 1116 +MWAITXrrr 1117 +MWAITrr 1118 +NEG 1119 +NOOP 1120 +NOOPL 1121 +NOOPLr 1122 +NOOPQ 1123 +NOOPQr 1124 +NOOPW 1125 +NOOPWr 1126 +NOT 1127 +OR 1128 +ORPDrm 1129 +ORPDrr 1130 +ORPSrm 1131 +ORPSrr 1132 +OUT 1133 +OUTSB 1134 +OUTSL 1135 +OUTSW 1136 +PABSBrm 1137 +PABSBrr 1138 +PABSDrm 1139 +PABSDrr 1140 +PABSWrm 1141 +PABSWrr 1142 +PACKSSDWrm 1143 +PACKSSDWrr 1144 +PACKSSWBrm 1145 +PACKSSWBrr 1146 +PACKUSDWrm 1147 +PACKUSDWrr 1148 +PACKUSWBrm 1149 +PACKUSWBrr 1150 +PADDBrm 1151 +PADDBrr 1152 +PADDDrm 1153 +PADDDrr 1154 +PADDQrm 1155 +PADDQrr 1156 +PADDSBrm 1157 +PADDSBrr 1158 +PADDSWrm 1159 +PADDSWrr 1160 +PADDUSBrm 1161 +PADDUSBrr 1162 +PADDUSWrm 1163 +PADDUSWrr 1164 +PADDWrm 1165 +PADDWrr 1166 +PALIGNRrmi 1167 +PALIGNRrri 1168 +PANDNrm 1169 +PANDNrr 1170 +PANDrm 1171 +PANDrr 1172 +PATCHABLE_EVENT_CALL 1173 +PATCHABLE_FUNCTION_ENTER 1174 +PATCHABLE_FUNCTION_EXIT 1175 +PATCHABLE_OP 1176 +PATCHABLE_RET 1177 +PATCHABLE_TAIL_CALL 1178 +PATCHABLE_TYPED_EVENT_CALL 1179 +PATCHPOINT 1180 +PAUSE 1181 +PAVGBrm 1182 +PAVGBrr 1183 +PAVGUSBrm 1184 +PAVGUSBrr 1185 +PAVGWrm 1186 +PAVGWrr 1187 +PBLENDVBrm 1188 +PBLENDVBrr 1189 +PBLENDWrmi 1190 +PBLENDWrri 1191 +PBNDKB 1192 +PCLMULQDQrmi 1193 +PCLMULQDQrri 1194 +PCMPEQBrm 1195 +PCMPEQBrr 1196 +PCMPEQDrm 1197 +PCMPEQDrr 1198 +PCMPEQQrm 1199 +PCMPEQQrr 1200 +PCMPEQWrm 1201 +PCMPEQWrr 1202 +PCMPESTRIrmi 1203 +PCMPESTRIrri 1204 +PCMPESTRMrmi 1205 +PCMPESTRMrri 1206 +PCMPGTBrm 1207 +PCMPGTBrr 1208 +PCMPGTDrm 1209 +PCMPGTDrr 1210 +PCMPGTQrm 1211 +PCMPGTQrr 1212 +PCMPGTWrm 1213 +PCMPGTWrr 1214 +PCMPISTRIrmi 1215 +PCMPISTRIrri 1216 +PCMPISTRMrmi 1217 +PCMPISTRMrri 1218 +PCONFIG 1219 +PDEP 1220 +PEXT 1221 +PEXTRBmri 1222 +PEXTRBrri 1223 +PEXTRDmri 1224 +PEXTRDrri 1225 +PEXTRQmri 1226 +PEXTRQrri 1227 +PEXTRWmri 1228 +PEXTRWrri 1229 +PEXTRWrri_REV 1230 +PF 1231 +PFACCrm 1232 +PFACCrr 1233 +PFADDrm 1234 +PFADDrr 1235 +PFCMPEQrm 1236 +PFCMPEQrr 1237 +PFCMPGErm 1238 +PFCMPGErr 1239 +PFCMPGTrm 1240 +PFCMPGTrr 1241 +PFMAXrm 1242 +PFMAXrr 1243 +PFMINrm 1244 +PFMINrr 1245 +PFMULrm 1246 +PFMULrr 1247 +PFNACCrm 1248 +PFNACCrr 1249 +PFPNACCrm 1250 +PFPNACCrr 1251 +PFRCPIT 1252 +PFRCPrm 1253 +PFRCPrr 1254 +PFRSQIT 1255 +PFRSQRTrm 1256 +PFRSQRTrr 1257 +PFSUBRrm 1258 +PFSUBRrr 1259 +PFSUBrm 1260 +PFSUBrr 1261 +PHADDDrm 1262 +PHADDDrr 1263 +PHADDSWrm 1264 +PHADDSWrr 1265 +PHADDWrm 1266 +PHADDWrr 1267 +PHI 1268 +PHMINPOSUWrm 1269 +PHMINPOSUWrr 1270 +PHSUBDrm 1271 +PHSUBDrr 1272 +PHSUBSWrm 1273 +PHSUBSWrr 1274 +PHSUBWrm 1275 +PHSUBWrr 1276 +PI 1277 +PINSRBrmi 1278 +PINSRBrri 1279 +PINSRDrmi 1280 +PINSRDrri 1281 +PINSRQrmi 1282 +PINSRQrri 1283 +PINSRWrmi 1284 +PINSRWrri 1285 +PLDTILECFGV 1286 +PLEA 1287 +PMADDUBSWrm 1288 +PMADDUBSWrr 1289 +PMADDWDrm 1290 +PMADDWDrr 1291 +PMAXSBrm 1292 +PMAXSBrr 1293 +PMAXSDrm 1294 +PMAXSDrr 1295 +PMAXSWrm 1296 +PMAXSWrr 1297 +PMAXUBrm 1298 +PMAXUBrr 1299 +PMAXUDrm 1300 +PMAXUDrr 1301 +PMAXUWrm 1302 +PMAXUWrr 1303 +PMINSBrm 1304 +PMINSBrr 1305 +PMINSDrm 1306 +PMINSDrr 1307 +PMINSWrm 1308 +PMINSWrr 1309 +PMINUBrm 1310 +PMINUBrr 1311 +PMINUDrm 1312 +PMINUDrr 1313 +PMINUWrm 1314 +PMINUWrr 1315 +PMOVMSKBrr 1316 +PMOVSXBDrm 1317 +PMOVSXBDrr 1318 +PMOVSXBQrm 1319 +PMOVSXBQrr 1320 +PMOVSXBWrm 1321 +PMOVSXBWrr 1322 +PMOVSXDQrm 1323 +PMOVSXDQrr 1324 +PMOVSXWDrm 1325 +PMOVSXWDrr 1326 +PMOVSXWQrm 1327 +PMOVSXWQrr 1328 +PMOVZXBDrm 1329 +PMOVZXBDrr 1330 +PMOVZXBQrm 1331 +PMOVZXBQrr 1332 +PMOVZXBWrm 1333 +PMOVZXBWrr 1334 +PMOVZXDQrm 1335 +PMOVZXDQrr 1336 +PMOVZXWDrm 1337 +PMOVZXWDrr 1338 +PMOVZXWQrm 1339 +PMOVZXWQrr 1340 +PMULDQrm 1341 +PMULDQrr 1342 +PMULHRSWrm 1343 +PMULHRSWrr 1344 +PMULHRWrm 1345 +PMULHRWrr 1346 +PMULHUWrm 1347 +PMULHUWrr 1348 +PMULHWrm 1349 +PMULHWrr 1350 +PMULLDrm 1351 +PMULLDrr 1352 +PMULLWrm 1353 +PMULLWrr 1354 +PMULUDQrm 1355 +PMULUDQrr 1356 +POP 1357 +POPA 1358 +POPCNT 1359 +POPDS 1360 +POPES 1361 +POPF 1362 +POPFS 1363 +POPGS 1364 +POPP 1365 +POPSS 1366 +PORrm 1367 +PORrr 1368 +PREALLOCATED_ARG 1369 +PREALLOCATED_SETUP 1370 +PREFETCH 1371 +PREFETCHIT 1372 +PREFETCHNTA 1373 +PREFETCHRST 1374 +PREFETCHT 1375 +PREFETCHW 1376 +PREFETCHWT 1377 +PROBED_ALLOCA 1378 +PSADBWrm 1379 +PSADBWrr 1380 +PSEUDO_PROBE 1381 +PSHUFBrm 1382 +PSHUFBrr 1383 +PSHUFDmi 1384 +PSHUFDri 1385 +PSHUFHWmi 1386 +PSHUFHWri 1387 +PSHUFLWmi 1388 +PSHUFLWri 1389 +PSIGNBrm 1390 +PSIGNBrr 1391 +PSIGNDrm 1392 +PSIGNDrr 1393 +PSIGNWrm 1394 +PSIGNWrr 1395 +PSLLDQri 1396 +PSLLDri 1397 +PSLLDrm 1398 +PSLLDrr 1399 +PSLLQri 1400 +PSLLQrm 1401 +PSLLQrr 1402 +PSLLWri 1403 +PSLLWrm 1404 +PSLLWrr 1405 +PSMASH 1406 +PSRADri 1407 +PSRADrm 1408 +PSRADrr 1409 +PSRAWri 1410 +PSRAWrm 1411 +PSRAWrr 1412 +PSRLDQri 1413 +PSRLDri 1414 +PSRLDrm 1415 +PSRLDrr 1416 +PSRLQri 1417 +PSRLQrm 1418 +PSRLQrr 1419 +PSRLWri 1420 +PSRLWrm 1421 +PSRLWrr 1422 +PSUBBrm 1423 +PSUBBrr 1424 +PSUBDrm 1425 +PSUBDrr 1426 +PSUBQrm 1427 +PSUBQrr 1428 +PSUBSBrm 1429 +PSUBSBrr 1430 +PSUBSWrm 1431 +PSUBSWrr 1432 +PSUBUSBrm 1433 +PSUBUSBrr 1434 +PSUBUSWrm 1435 +PSUBUSWrr 1436 +PSUBWrm 1437 +PSUBWrr 1438 +PSWAPDrm 1439 +PSWAPDrr 1440 +PT 1441 +PTCMMIMFP 1442 +PTCMMRLFP 1443 +PTCONJTCMMIMFP 1444 +PTCONJTFP 1445 +PTCVTROWD 1446 +PTCVTROWPS 1447 +PTDPBF 1448 +PTDPBHF 1449 +PTDPBSSD 1450 +PTDPBSSDV 1451 +PTDPBSUD 1452 +PTDPBSUDV 1453 +PTDPBUSD 1454 +PTDPBUSDV 1455 +PTDPBUUD 1456 +PTDPBUUDV 1457 +PTDPFP 1458 +PTDPHBF 1459 +PTDPHF 1460 +PTESTrm 1461 +PTESTrr 1462 +PTILELOADD 1463 +PTILELOADDRS 1464 +PTILELOADDRST 1465 +PTILELOADDRSV 1466 +PTILELOADDT 1467 +PTILELOADDV 1468 +PTILEMOVROWrre 1469 +PTILEMOVROWrreV 1470 +PTILEMOVROWrri 1471 +PTILEMOVROWrriV 1472 +PTILEPAIRLOAD 1473 +PTILEPAIRSTORE 1474 +PTILESTORED 1475 +PTILESTOREDV 1476 +PTILEZERO 1477 +PTILEZEROV 1478 +PTMMULTF 1479 +PTTCMMIMFP 1480 +PTTCMMRLFP 1481 +PTTDPBF 1482 +PTTDPFP 1483 +PTTMMULTF 1484 +PTTRANSPOSED 1485 +PTTRANSPOSEDV 1486 +PTWRITE 1487 +PTWRITEm 1488 +PTWRITEr 1489 +PUNPCKHBWrm 1490 +PUNPCKHBWrr 1491 +PUNPCKHDQrm 1492 +PUNPCKHDQrr 1493 +PUNPCKHQDQrm 1494 +PUNPCKHQDQrr 1495 +PUNPCKHWDrm 1496 +PUNPCKHWDrr 1497 +PUNPCKLBWrm 1498 +PUNPCKLBWrr 1499 +PUNPCKLDQrm 1500 +PUNPCKLDQrr 1501 +PUNPCKLQDQrm 1502 +PUNPCKLQDQrr 1503 +PUNPCKLWDrm 1504 +PUNPCKLWDrr 1505 +PUSH 1506 +PUSHA 1507 +PUSHCS 1508 +PUSHDS 1509 +PUSHES 1510 +PUSHF 1511 +PUSHFS 1512 +PUSHGS 1513 +PUSHP 1514 +PUSHSS 1515 +PVALIDATE 1516 +PXORrm 1517 +PXORrr 1518 +RCL 1519 +RCPPSm 1520 +RCPPSr 1521 +RCPSSm 1522 +RCPSSm_Int 1523 +RCPSSr 1524 +RCPSSr_Int 1525 +RCR 1526 +RDFLAGS 1527 +RDFSBASE 1528 +RDGSBASE 1529 +RDMSR 1530 +RDMSRLIST 1531 +RDMSRri 1532 +RDMSRri_EVEX 1533 +RDPID 1534 +RDPKRUr 1535 +RDPMC 1536 +RDPRU 1537 +RDRAND 1538 +RDSEED 1539 +RDSSPD 1540 +RDSSPQ 1541 +RDTSC 1542 +RDTSCP 1543 +REG_SEQUENCE 1544 +REPNE_PREFIX 1545 +REP_MOVSB 1546 +REP_MOVSD 1547 +REP_MOVSQ 1548 +REP_MOVSW 1549 +REP_PREFIX 1550 +REP_STOSB 1551 +REP_STOSD 1552 +REP_STOSQ 1553 +REP_STOSW 1554 +RET 1555 +RETI 1556 +REX 1557 +RMPADJUST 1558 +RMPQUERY 1559 +RMPUPDATE 1560 +ROL 1561 +ROR 1562 +RORX 1563 +ROUNDPDmi 1564 +ROUNDPDri 1565 +ROUNDPSmi 1566 +ROUNDPSri 1567 +ROUNDSDmi 1568 +ROUNDSDmi_Int 1569 +ROUNDSDri 1570 +ROUNDSDri_Int 1571 +ROUNDSSmi 1572 +ROUNDSSmi_Int 1573 +ROUNDSSri 1574 +ROUNDSSri_Int 1575 +RSM 1576 +RSQRTPSm 1577 +RSQRTPSr 1578 +RSQRTSSm 1579 +RSQRTSSm_Int 1580 +RSQRTSSr 1581 +RSQRTSSr_Int 1582 +RSTORSSP 1583 +SAHF 1584 +SALC 1585 +SAR 1586 +SARX 1587 +SAVEPREVSSP 1588 +SBB 1589 +SCASB 1590 +SCASL 1591 +SCASQ 1592 +SCASW 1593 +SEAMCALL 1594 +SEAMOPS 1595 +SEAMRET 1596 +SEG_ALLOCA 1597 +SEH_BeginEpilogue 1598 +SEH_EndEpilogue 1599 +SEH_EndPrologue 1600 +SEH_PushFrame 1601 +SEH_PushReg 1602 +SEH_SaveReg 1603 +SEH_SaveXMM 1604 +SEH_SetFrame 1605 +SEH_StackAlign 1606 +SEH_StackAlloc 1607 +SEH_UnwindV 1608 +SEH_UnwindVersion 1609 +SENDUIPI 1610 +SERIALIZE 1611 +SETB_C 1612 +SETCCm 1613 +SETCCm_EVEX 1614 +SETCCr 1615 +SETCCr_EVEX 1616 +SETSSBSY 1617 +SETZUCCm 1618 +SETZUCCr 1619 +SFENCE 1620 +SGDT 1621 +SHA 1622 +SHL 1623 +SHLD 1624 +SHLDROT 1625 +SHLX 1626 +SHR 1627 +SHRD 1628 +SHRDROT 1629 +SHRX 1630 +SHUFPDrmi 1631 +SHUFPDrri 1632 +SHUFPSrmi 1633 +SHUFPSrri 1634 +SIDT 1635 +SKINIT 1636 +SLDT 1637 +SLWPCB 1638 +SMSW 1639 +SQRTPDm 1640 +SQRTPDr 1641 +SQRTPSm 1642 +SQRTPSr 1643 +SQRTSDm 1644 +SQRTSDm_Int 1645 +SQRTSDr 1646 +SQRTSDr_Int 1647 +SQRTSSm 1648 +SQRTSSm_Int 1649 +SQRTSSr 1650 +SQRTSSr_Int 1651 +SQRT_F 1652 +SQRT_Fp 1653 +SS_PREFIX 1654 +STAC 1655 +STACKALLOC_W_PROBING 1656 +STACKMAP 1657 +STATEPOINT 1658 +STC 1659 +STD 1660 +STGI 1661 +STI 1662 +STMXCSR 1663 +STOSB 1664 +STOSL 1665 +STOSQ 1666 +STOSW 1667 +STR 1668 +STRm 1669 +STTILECFG 1670 +STTILECFG_EVEX 1671 +STUI 1672 +ST_F 1673 +ST_FP 1674 +ST_FPrr 1675 +ST_Fp 1676 +ST_FpP 1677 +ST_Frr 1678 +SUB 1679 +SUBPDrm 1680 +SUBPDrr 1681 +SUBPSrm 1682 +SUBPSrr 1683 +SUBREG_TO_REG 1684 +SUBR_F 1685 +SUBR_FI 1686 +SUBR_FPrST 1687 +SUBR_FST 1688 +SUBR_Fp 1689 +SUBR_FpI 1690 +SUBR_FrST 1691 +SUBSDrm 1692 +SUBSDrm_Int 1693 +SUBSDrr 1694 +SUBSDrr_Int 1695 +SUBSSrm 1696 +SUBSSrm_Int 1697 +SUBSSrr 1698 +SUBSSrr_Int 1699 +SUB_F 1700 +SUB_FI 1701 +SUB_FPrST 1702 +SUB_FST 1703 +SUB_Fp 1704 +SUB_FpI 1705 +SUB_FrST 1706 +SWAPGS 1707 +SYSCALL 1708 +SYSENTER 1709 +SYSEXIT 1710 +SYSRET 1711 +T 1712 +TAILJMPd 1713 +TAILJMPd_CC 1714 +TAILJMPm 1715 +TAILJMPr 1716 +TCMMIMFP 1717 +TCMMRLFP 1718 +TCONJTCMMIMFP 1719 +TCONJTFP 1720 +TCRETURN_HIPE 1721 +TCRETURN_WIN 1722 +TCRETURN_WINmi 1723 +TCRETURNdi 1724 +TCRETURNdicc 1725 +TCRETURNmi 1726 +TCRETURNri 1727 +TCVTROWD 1728 +TCVTROWPS 1729 +TDCALL 1730 +TDPBF 1731 +TDPBHF 1732 +TDPBSSD 1733 +TDPBSUD 1734 +TDPBUSD 1735 +TDPBUUD 1736 +TDPFP 1737 +TDPHBF 1738 +TDPHF 1739 +TEST 1740 +TESTUI 1741 +TILELOADD 1742 +TILELOADDRS 1743 +TILELOADDRST 1744 +TILELOADDRS_EVEX 1745 +TILELOADDT 1746 +TILELOADD_EVEX 1747 +TILEMOVROWrre 1748 +TILEMOVROWrri 1749 +TILERELEASE 1750 +TILESTORED 1751 +TILESTORED_EVEX 1752 +TILEZERO 1753 +TLBSYNC 1754 +TLSCall 1755 +TLS_addr 1756 +TLS_addrX 1757 +TLS_base_addr 1758 +TLS_base_addrX 1759 +TLS_desc 1760 +TMMULTF 1761 +TPAUSE 1762 +TRAP 1763 +TST_F 1764 +TST_Fp 1765 +TTCMMIMFP 1766 +TTCMMRLFP 1767 +TTDPBF 1768 +TTDPFP 1769 +TTMMULTF 1770 +TTRANSPOSED 1771 +TZCNT 1772 +TZMSK 1773 +UBSAN_UD 1774 +UCOMISDrm 1775 +UCOMISDrm_Int 1776 +UCOMISDrr 1777 +UCOMISDrr_Int 1778 +UCOMISSrm 1779 +UCOMISSrm_Int 1780 +UCOMISSrr 1781 +UCOMISSrr_Int 1782 +UCOM_FIPr 1783 +UCOM_FIr 1784 +UCOM_FPPr 1785 +UCOM_FPr 1786 +UCOM_FpIr 1787 +UCOM_Fpr 1788 +UCOM_Fr 1789 +UD 1790 +UIRET 1791 +UMONITOR 1792 +UMWAIT 1793 +UNPCKHPDrm 1794 +UNPCKHPDrr 1795 +UNPCKHPSrm 1796 +UNPCKHPSrr 1797 +UNPCKLPDrm 1798 +UNPCKLPDrr 1799 +UNPCKLPSrm 1800 +UNPCKLPSrr 1801 +URDMSRri 1802 +URDMSRri_EVEX 1803 +URDMSRrr 1804 +URDMSRrr_EVEX 1805 +UWRMSRir 1806 +UWRMSRir_EVEX 1807 +UWRMSRrr 1808 +UWRMSRrr_EVEX 1809 +V 1810 +VAARG 1811 +VAARG_X 1812 +VADDBF 1813 +VADDPDYrm 1814 +VADDPDYrr 1815 +VADDPDZ 1816 +VADDPDZrm 1817 +VADDPDZrmb 1818 +VADDPDZrmbk 1819 +VADDPDZrmbkz 1820 +VADDPDZrmk 1821 +VADDPDZrmkz 1822 +VADDPDZrr 1823 +VADDPDZrrb 1824 +VADDPDZrrbk 1825 +VADDPDZrrbkz 1826 +VADDPDZrrk 1827 +VADDPDZrrkz 1828 +VADDPDrm 1829 +VADDPDrr 1830 +VADDPHZ 1831 +VADDPHZrm 1832 +VADDPHZrmb 1833 +VADDPHZrmbk 1834 +VADDPHZrmbkz 1835 +VADDPHZrmk 1836 +VADDPHZrmkz 1837 +VADDPHZrr 1838 +VADDPHZrrb 1839 +VADDPHZrrbk 1840 +VADDPHZrrbkz 1841 +VADDPHZrrk 1842 +VADDPHZrrkz 1843 +VADDPSYrm 1844 +VADDPSYrr 1845 +VADDPSZ 1846 +VADDPSZrm 1847 +VADDPSZrmb 1848 +VADDPSZrmbk 1849 +VADDPSZrmbkz 1850 +VADDPSZrmk 1851 +VADDPSZrmkz 1852 +VADDPSZrr 1853 +VADDPSZrrb 1854 +VADDPSZrrbk 1855 +VADDPSZrrbkz 1856 +VADDPSZrrk 1857 +VADDPSZrrkz 1858 +VADDPSrm 1859 +VADDPSrr 1860 +VADDSDZrm 1861 +VADDSDZrm_Int 1862 +VADDSDZrmk_Int 1863 +VADDSDZrmkz_Int 1864 +VADDSDZrr 1865 +VADDSDZrr_Int 1866 +VADDSDZrrb_Int 1867 +VADDSDZrrbk_Int 1868 +VADDSDZrrbkz_Int 1869 +VADDSDZrrk_Int 1870 +VADDSDZrrkz_Int 1871 +VADDSDrm 1872 +VADDSDrm_Int 1873 +VADDSDrr 1874 +VADDSDrr_Int 1875 +VADDSHZrm 1876 +VADDSHZrm_Int 1877 +VADDSHZrmk_Int 1878 +VADDSHZrmkz_Int 1879 +VADDSHZrr 1880 +VADDSHZrr_Int 1881 +VADDSHZrrb_Int 1882 +VADDSHZrrbk_Int 1883 +VADDSHZrrbkz_Int 1884 +VADDSHZrrk_Int 1885 +VADDSHZrrkz_Int 1886 +VADDSSZrm 1887 +VADDSSZrm_Int 1888 +VADDSSZrmk_Int 1889 +VADDSSZrmkz_Int 1890 +VADDSSZrr 1891 +VADDSSZrr_Int 1892 +VADDSSZrrb_Int 1893 +VADDSSZrrbk_Int 1894 +VADDSSZrrbkz_Int 1895 +VADDSSZrrk_Int 1896 +VADDSSZrrkz_Int 1897 +VADDSSrm 1898 +VADDSSrm_Int 1899 +VADDSSrr 1900 +VADDSSrr_Int 1901 +VADDSUBPDYrm 1902 +VADDSUBPDYrr 1903 +VADDSUBPDrm 1904 +VADDSUBPDrr 1905 +VADDSUBPSYrm 1906 +VADDSUBPSYrr 1907 +VADDSUBPSrm 1908 +VADDSUBPSrr 1909 +VAESDECLASTYrm 1910 +VAESDECLASTYrr 1911 +VAESDECLASTZ 1912 +VAESDECLASTZrm 1913 +VAESDECLASTZrr 1914 +VAESDECLASTrm 1915 +VAESDECLASTrr 1916 +VAESDECYrm 1917 +VAESDECYrr 1918 +VAESDECZ 1919 +VAESDECZrm 1920 +VAESDECZrr 1921 +VAESDECrm 1922 +VAESDECrr 1923 +VAESENCLASTYrm 1924 +VAESENCLASTYrr 1925 +VAESENCLASTZ 1926 +VAESENCLASTZrm 1927 +VAESENCLASTZrr 1928 +VAESENCLASTrm 1929 +VAESENCLASTrr 1930 +VAESENCYrm 1931 +VAESENCYrr 1932 +VAESENCZ 1933 +VAESENCZrm 1934 +VAESENCZrr 1935 +VAESENCrm 1936 +VAESENCrr 1937 +VAESIMCrm 1938 +VAESIMCrr 1939 +VAESKEYGENASSISTrmi 1940 +VAESKEYGENASSISTrri 1941 +VALIGNDZ 1942 +VALIGNDZrmbi 1943 +VALIGNDZrmbik 1944 +VALIGNDZrmbikz 1945 +VALIGNDZrmi 1946 +VALIGNDZrmik 1947 +VALIGNDZrmikz 1948 +VALIGNDZrri 1949 +VALIGNDZrrik 1950 +VALIGNDZrrikz 1951 +VALIGNQZ 1952 +VALIGNQZrmbi 1953 +VALIGNQZrmbik 1954 +VALIGNQZrmbikz 1955 +VALIGNQZrmi 1956 +VALIGNQZrmik 1957 +VALIGNQZrmikz 1958 +VALIGNQZrri 1959 +VALIGNQZrrik 1960 +VALIGNQZrrikz 1961 +VANDNPDYrm 1962 +VANDNPDYrr 1963 +VANDNPDZ 1964 +VANDNPDZrm 1965 +VANDNPDZrmb 1966 +VANDNPDZrmbk 1967 +VANDNPDZrmbkz 1968 +VANDNPDZrmk 1969 +VANDNPDZrmkz 1970 +VANDNPDZrr 1971 +VANDNPDZrrk 1972 +VANDNPDZrrkz 1973 +VANDNPDrm 1974 +VANDNPDrr 1975 +VANDNPSYrm 1976 +VANDNPSYrr 1977 +VANDNPSZ 1978 +VANDNPSZrm 1979 +VANDNPSZrmb 1980 +VANDNPSZrmbk 1981 +VANDNPSZrmbkz 1982 +VANDNPSZrmk 1983 +VANDNPSZrmkz 1984 +VANDNPSZrr 1985 +VANDNPSZrrk 1986 +VANDNPSZrrkz 1987 +VANDNPSrm 1988 +VANDNPSrr 1989 +VANDPDYrm 1990 +VANDPDYrr 1991 +VANDPDZ 1992 +VANDPDZrm 1993 +VANDPDZrmb 1994 +VANDPDZrmbk 1995 +VANDPDZrmbkz 1996 +VANDPDZrmk 1997 +VANDPDZrmkz 1998 +VANDPDZrr 1999 +VANDPDZrrk 2000 +VANDPDZrrkz 2001 +VANDPDrm 2002 +VANDPDrr 2003 +VANDPSYrm 2004 +VANDPSYrr 2005 +VANDPSZ 2006 +VANDPSZrm 2007 +VANDPSZrmb 2008 +VANDPSZrmbk 2009 +VANDPSZrmbkz 2010 +VANDPSZrmk 2011 +VANDPSZrmkz 2012 +VANDPSZrr 2013 +VANDPSZrrk 2014 +VANDPSZrrkz 2015 +VANDPSrm 2016 +VANDPSrr 2017 +VASTART_SAVE_XMM_REGS 2018 +VBCSTNEBF 2019 +VBCSTNESH 2020 +VBLENDMPDZ 2021 +VBLENDMPDZrm 2022 +VBLENDMPDZrmb 2023 +VBLENDMPDZrmbk 2024 +VBLENDMPDZrmbkz 2025 +VBLENDMPDZrmk 2026 +VBLENDMPDZrmkz 2027 +VBLENDMPDZrr 2028 +VBLENDMPDZrrk 2029 +VBLENDMPDZrrkz 2030 +VBLENDMPSZ 2031 +VBLENDMPSZrm 2032 +VBLENDMPSZrmb 2033 +VBLENDMPSZrmbk 2034 +VBLENDMPSZrmbkz 2035 +VBLENDMPSZrmk 2036 +VBLENDMPSZrmkz 2037 +VBLENDMPSZrr 2038 +VBLENDMPSZrrk 2039 +VBLENDMPSZrrkz 2040 +VBLENDPDYrmi 2041 +VBLENDPDYrri 2042 +VBLENDPDrmi 2043 +VBLENDPDrri 2044 +VBLENDPSYrmi 2045 +VBLENDPSYrri 2046 +VBLENDPSrmi 2047 +VBLENDPSrri 2048 +VBLENDVPDYrmr 2049 +VBLENDVPDYrrr 2050 +VBLENDVPDrmr 2051 +VBLENDVPDrrr 2052 +VBLENDVPSYrmr 2053 +VBLENDVPSYrrr 2054 +VBLENDVPSrmr 2055 +VBLENDVPSrrr 2056 +VBROADCASTF 2057 +VBROADCASTI 2058 +VBROADCASTSDYrm 2059 +VBROADCASTSDYrr 2060 +VBROADCASTSDZ 2061 +VBROADCASTSDZrm 2062 +VBROADCASTSDZrmk 2063 +VBROADCASTSDZrmkz 2064 +VBROADCASTSDZrr 2065 +VBROADCASTSDZrrk 2066 +VBROADCASTSDZrrkz 2067 +VBROADCASTSSYrm 2068 +VBROADCASTSSYrr 2069 +VBROADCASTSSZ 2070 +VBROADCASTSSZrm 2071 +VBROADCASTSSZrmk 2072 +VBROADCASTSSZrmkz 2073 +VBROADCASTSSZrr 2074 +VBROADCASTSSZrrk 2075 +VBROADCASTSSZrrkz 2076 +VBROADCASTSSrm 2077 +VBROADCASTSSrr 2078 +VCMPBF 2079 +VCMPPDYrmi 2080 +VCMPPDYrri 2081 +VCMPPDZ 2082 +VCMPPDZrmbi 2083 +VCMPPDZrmbik 2084 +VCMPPDZrmi 2085 +VCMPPDZrmik 2086 +VCMPPDZrri 2087 +VCMPPDZrrib 2088 +VCMPPDZrribk 2089 +VCMPPDZrrik 2090 +VCMPPDrmi 2091 +VCMPPDrri 2092 +VCMPPHZ 2093 +VCMPPHZrmbi 2094 +VCMPPHZrmbik 2095 +VCMPPHZrmi 2096 +VCMPPHZrmik 2097 +VCMPPHZrri 2098 +VCMPPHZrrib 2099 +VCMPPHZrribk 2100 +VCMPPHZrrik 2101 +VCMPPSYrmi 2102 +VCMPPSYrri 2103 +VCMPPSZ 2104 +VCMPPSZrmbi 2105 +VCMPPSZrmbik 2106 +VCMPPSZrmi 2107 +VCMPPSZrmik 2108 +VCMPPSZrri 2109 +VCMPPSZrrib 2110 +VCMPPSZrribk 2111 +VCMPPSZrrik 2112 +VCMPPSrmi 2113 +VCMPPSrri 2114 +VCMPSDZrmi 2115 +VCMPSDZrmi_Int 2116 +VCMPSDZrmik_Int 2117 +VCMPSDZrri 2118 +VCMPSDZrri_Int 2119 +VCMPSDZrrib_Int 2120 +VCMPSDZrribk_Int 2121 +VCMPSDZrrik_Int 2122 +VCMPSDrmi 2123 +VCMPSDrmi_Int 2124 +VCMPSDrri 2125 +VCMPSDrri_Int 2126 +VCMPSHZrmi 2127 +VCMPSHZrmi_Int 2128 +VCMPSHZrmik_Int 2129 +VCMPSHZrri 2130 +VCMPSHZrri_Int 2131 +VCMPSHZrrib_Int 2132 +VCMPSHZrribk_Int 2133 +VCMPSHZrrik_Int 2134 +VCMPSSZrmi 2135 +VCMPSSZrmi_Int 2136 +VCMPSSZrmik_Int 2137 +VCMPSSZrri 2138 +VCMPSSZrri_Int 2139 +VCMPSSZrrib_Int 2140 +VCMPSSZrribk_Int 2141 +VCMPSSZrrik_Int 2142 +VCMPSSrmi 2143 +VCMPSSrmi_Int 2144 +VCMPSSrri 2145 +VCMPSSrri_Int 2146 +VCOMISBF 2147 +VCOMISDZrm 2148 +VCOMISDZrm_Int 2149 +VCOMISDZrr 2150 +VCOMISDZrr_Int 2151 +VCOMISDZrrb 2152 +VCOMISDrm 2153 +VCOMISDrm_Int 2154 +VCOMISDrr 2155 +VCOMISDrr_Int 2156 +VCOMISHZrm 2157 +VCOMISHZrm_Int 2158 +VCOMISHZrr 2159 +VCOMISHZrr_Int 2160 +VCOMISHZrrb 2161 +VCOMISSZrm 2162 +VCOMISSZrm_Int 2163 +VCOMISSZrr 2164 +VCOMISSZrr_Int 2165 +VCOMISSZrrb 2166 +VCOMISSrm 2167 +VCOMISSrm_Int 2168 +VCOMISSrr 2169 +VCOMISSrr_Int 2170 +VCOMPRESSPDZ 2171 +VCOMPRESSPDZmr 2172 +VCOMPRESSPDZmrk 2173 +VCOMPRESSPDZrr 2174 +VCOMPRESSPDZrrk 2175 +VCOMPRESSPDZrrkz 2176 +VCOMPRESSPSZ 2177 +VCOMPRESSPSZmr 2178 +VCOMPRESSPSZmrk 2179 +VCOMPRESSPSZrr 2180 +VCOMPRESSPSZrrk 2181 +VCOMPRESSPSZrrkz 2182 +VCOMXSDZrm_Int 2183 +VCOMXSDZrr_Int 2184 +VCOMXSDZrrb_Int 2185 +VCOMXSHZrm_Int 2186 +VCOMXSHZrr_Int 2187 +VCOMXSHZrrb_Int 2188 +VCOMXSSZrm_Int 2189 +VCOMXSSZrr_Int 2190 +VCOMXSSZrrb_Int 2191 +VCVT 2192 +VCVTBF 2193 +VCVTBIASPH 2194 +VCVTDQ 2195 +VCVTHF 2196 +VCVTNE 2197 +VCVTNEEBF 2198 +VCVTNEEPH 2199 +VCVTNEOBF 2200 +VCVTNEOPH 2201 +VCVTNEPS 2202 +VCVTPD 2203 +VCVTPH 2204 +VCVTPS 2205 +VCVTQQ 2206 +VCVTSD 2207 +VCVTSH 2208 +VCVTSI 2209 +VCVTSS 2210 +VCVTTBF 2211 +VCVTTPD 2212 +VCVTTPH 2213 +VCVTTPS 2214 +VCVTTSD 2215 +VCVTTSH 2216 +VCVTTSS 2217 +VCVTUDQ 2218 +VCVTUQQ 2219 +VCVTUSI 2220 +VCVTUW 2221 +VCVTW 2222 +VDBPSADBWZ 2223 +VDBPSADBWZrmi 2224 +VDBPSADBWZrmik 2225 +VDBPSADBWZrmikz 2226 +VDBPSADBWZrri 2227 +VDBPSADBWZrrik 2228 +VDBPSADBWZrrikz 2229 +VDIVBF 2230 +VDIVPDYrm 2231 +VDIVPDYrr 2232 +VDIVPDZ 2233 +VDIVPDZrm 2234 +VDIVPDZrmb 2235 +VDIVPDZrmbk 2236 +VDIVPDZrmbkz 2237 +VDIVPDZrmk 2238 +VDIVPDZrmkz 2239 +VDIVPDZrr 2240 +VDIVPDZrrb 2241 +VDIVPDZrrbk 2242 +VDIVPDZrrbkz 2243 +VDIVPDZrrk 2244 +VDIVPDZrrkz 2245 +VDIVPDrm 2246 +VDIVPDrr 2247 +VDIVPHZ 2248 +VDIVPHZrm 2249 +VDIVPHZrmb 2250 +VDIVPHZrmbk 2251 +VDIVPHZrmbkz 2252 +VDIVPHZrmk 2253 +VDIVPHZrmkz 2254 +VDIVPHZrr 2255 +VDIVPHZrrb 2256 +VDIVPHZrrbk 2257 +VDIVPHZrrbkz 2258 +VDIVPHZrrk 2259 +VDIVPHZrrkz 2260 +VDIVPSYrm 2261 +VDIVPSYrr 2262 +VDIVPSZ 2263 +VDIVPSZrm 2264 +VDIVPSZrmb 2265 +VDIVPSZrmbk 2266 +VDIVPSZrmbkz 2267 +VDIVPSZrmk 2268 +VDIVPSZrmkz 2269 +VDIVPSZrr 2270 +VDIVPSZrrb 2271 +VDIVPSZrrbk 2272 +VDIVPSZrrbkz 2273 +VDIVPSZrrk 2274 +VDIVPSZrrkz 2275 +VDIVPSrm 2276 +VDIVPSrr 2277 +VDIVSDZrm 2278 +VDIVSDZrm_Int 2279 +VDIVSDZrmk_Int 2280 +VDIVSDZrmkz_Int 2281 +VDIVSDZrr 2282 +VDIVSDZrr_Int 2283 +VDIVSDZrrb_Int 2284 +VDIVSDZrrbk_Int 2285 +VDIVSDZrrbkz_Int 2286 +VDIVSDZrrk_Int 2287 +VDIVSDZrrkz_Int 2288 +VDIVSDrm 2289 +VDIVSDrm_Int 2290 +VDIVSDrr 2291 +VDIVSDrr_Int 2292 +VDIVSHZrm 2293 +VDIVSHZrm_Int 2294 +VDIVSHZrmk_Int 2295 +VDIVSHZrmkz_Int 2296 +VDIVSHZrr 2297 +VDIVSHZrr_Int 2298 +VDIVSHZrrb_Int 2299 +VDIVSHZrrbk_Int 2300 +VDIVSHZrrbkz_Int 2301 +VDIVSHZrrk_Int 2302 +VDIVSHZrrkz_Int 2303 +VDIVSSZrm 2304 +VDIVSSZrm_Int 2305 +VDIVSSZrmk_Int 2306 +VDIVSSZrmkz_Int 2307 +VDIVSSZrr 2308 +VDIVSSZrr_Int 2309 +VDIVSSZrrb_Int 2310 +VDIVSSZrrbk_Int 2311 +VDIVSSZrrbkz_Int 2312 +VDIVSSZrrk_Int 2313 +VDIVSSZrrkz_Int 2314 +VDIVSSrm 2315 +VDIVSSrm_Int 2316 +VDIVSSrr 2317 +VDIVSSrr_Int 2318 +VDPBF 2319 +VDPPDrmi 2320 +VDPPDrri 2321 +VDPPHPSZ 2322 +VDPPHPSZm 2323 +VDPPHPSZmb 2324 +VDPPHPSZmbk 2325 +VDPPHPSZmbkz 2326 +VDPPHPSZmk 2327 +VDPPHPSZmkz 2328 +VDPPHPSZr 2329 +VDPPHPSZrk 2330 +VDPPHPSZrkz 2331 +VDPPSYrmi 2332 +VDPPSYrri 2333 +VDPPSrmi 2334 +VDPPSrri 2335 +VERRm 2336 +VERRr 2337 +VERWm 2338 +VERWr 2339 +VEXP 2340 +VEXPANDPDZ 2341 +VEXPANDPDZrm 2342 +VEXPANDPDZrmk 2343 +VEXPANDPDZrmkz 2344 +VEXPANDPDZrr 2345 +VEXPANDPDZrrk 2346 +VEXPANDPDZrrkz 2347 +VEXPANDPSZ 2348 +VEXPANDPSZrm 2349 +VEXPANDPSZrmk 2350 +VEXPANDPSZrmkz 2351 +VEXPANDPSZrr 2352 +VEXPANDPSZrrk 2353 +VEXPANDPSZrrkz 2354 +VEXTRACTF 2355 +VEXTRACTI 2356 +VEXTRACTPSZmri 2357 +VEXTRACTPSZrri 2358 +VEXTRACTPSmri 2359 +VEXTRACTPSrri 2360 +VFCMADDCPHZ 2361 +VFCMADDCPHZm 2362 +VFCMADDCPHZmb 2363 +VFCMADDCPHZmbk 2364 +VFCMADDCPHZmbkz 2365 +VFCMADDCPHZmk 2366 +VFCMADDCPHZmkz 2367 +VFCMADDCPHZr 2368 +VFCMADDCPHZrb 2369 +VFCMADDCPHZrbk 2370 +VFCMADDCPHZrbkz 2371 +VFCMADDCPHZrk 2372 +VFCMADDCPHZrkz 2373 +VFCMADDCSHZm 2374 +VFCMADDCSHZmk 2375 +VFCMADDCSHZmkz 2376 +VFCMADDCSHZr 2377 +VFCMADDCSHZrb 2378 +VFCMADDCSHZrbk 2379 +VFCMADDCSHZrbkz 2380 +VFCMADDCSHZrk 2381 +VFCMADDCSHZrkz 2382 +VFCMULCPHZ 2383 +VFCMULCPHZrm 2384 +VFCMULCPHZrmb 2385 +VFCMULCPHZrmbk 2386 +VFCMULCPHZrmbkz 2387 +VFCMULCPHZrmk 2388 +VFCMULCPHZrmkz 2389 +VFCMULCPHZrr 2390 +VFCMULCPHZrrb 2391 +VFCMULCPHZrrbk 2392 +VFCMULCPHZrrbkz 2393 +VFCMULCPHZrrk 2394 +VFCMULCPHZrrkz 2395 +VFCMULCSHZrm 2396 +VFCMULCSHZrmk 2397 +VFCMULCSHZrmkz 2398 +VFCMULCSHZrr 2399 +VFCMULCSHZrrb 2400 +VFCMULCSHZrrbk 2401 +VFCMULCSHZrrbkz 2402 +VFCMULCSHZrrk 2403 +VFCMULCSHZrrkz 2404 +VFIXUPIMMPDZ 2405 +VFIXUPIMMPDZrmbi 2406 +VFIXUPIMMPDZrmbik 2407 +VFIXUPIMMPDZrmbikz 2408 +VFIXUPIMMPDZrmi 2409 +VFIXUPIMMPDZrmik 2410 +VFIXUPIMMPDZrmikz 2411 +VFIXUPIMMPDZrri 2412 +VFIXUPIMMPDZrrib 2413 +VFIXUPIMMPDZrribk 2414 +VFIXUPIMMPDZrribkz 2415 +VFIXUPIMMPDZrrik 2416 +VFIXUPIMMPDZrrikz 2417 +VFIXUPIMMPSZ 2418 +VFIXUPIMMPSZrmbi 2419 +VFIXUPIMMPSZrmbik 2420 +VFIXUPIMMPSZrmbikz 2421 +VFIXUPIMMPSZrmi 2422 +VFIXUPIMMPSZrmik 2423 +VFIXUPIMMPSZrmikz 2424 +VFIXUPIMMPSZrri 2425 +VFIXUPIMMPSZrrib 2426 +VFIXUPIMMPSZrribk 2427 +VFIXUPIMMPSZrribkz 2428 +VFIXUPIMMPSZrrik 2429 +VFIXUPIMMPSZrrikz 2430 +VFIXUPIMMSDZrmi 2431 +VFIXUPIMMSDZrmik 2432 +VFIXUPIMMSDZrmikz 2433 +VFIXUPIMMSDZrri 2434 +VFIXUPIMMSDZrrib 2435 +VFIXUPIMMSDZrribk 2436 +VFIXUPIMMSDZrribkz 2437 +VFIXUPIMMSDZrrik 2438 +VFIXUPIMMSDZrrikz 2439 +VFIXUPIMMSSZrmi 2440 +VFIXUPIMMSSZrmik 2441 +VFIXUPIMMSSZrmikz 2442 +VFIXUPIMMSSZrri 2443 +VFIXUPIMMSSZrrib 2444 +VFIXUPIMMSSZrribk 2445 +VFIXUPIMMSSZrribkz 2446 +VFIXUPIMMSSZrrik 2447 +VFIXUPIMMSSZrrikz 2448 +VFMADD 2449 +VFMADDCPHZ 2450 +VFMADDCPHZm 2451 +VFMADDCPHZmb 2452 +VFMADDCPHZmbk 2453 +VFMADDCPHZmbkz 2454 +VFMADDCPHZmk 2455 +VFMADDCPHZmkz 2456 +VFMADDCPHZr 2457 +VFMADDCPHZrb 2458 +VFMADDCPHZrbk 2459 +VFMADDCPHZrbkz 2460 +VFMADDCPHZrk 2461 +VFMADDCPHZrkz 2462 +VFMADDCSHZm 2463 +VFMADDCSHZmk 2464 +VFMADDCSHZmkz 2465 +VFMADDCSHZr 2466 +VFMADDCSHZrb 2467 +VFMADDCSHZrbk 2468 +VFMADDCSHZrbkz 2469 +VFMADDCSHZrk 2470 +VFMADDCSHZrkz 2471 +VFMADDPD 2472 +VFMADDPS 2473 +VFMADDSD 2474 +VFMADDSS 2475 +VFMADDSUB 2476 +VFMADDSUBPD 2477 +VFMADDSUBPS 2478 +VFMSUB 2479 +VFMSUBADD 2480 +VFMSUBADDPD 2481 +VFMSUBADDPS 2482 +VFMSUBPD 2483 +VFMSUBPS 2484 +VFMSUBSD 2485 +VFMSUBSS 2486 +VFMULCPHZ 2487 +VFMULCPHZrm 2488 +VFMULCPHZrmb 2489 +VFMULCPHZrmbk 2490 +VFMULCPHZrmbkz 2491 +VFMULCPHZrmk 2492 +VFMULCPHZrmkz 2493 +VFMULCPHZrr 2494 +VFMULCPHZrrb 2495 +VFMULCPHZrrbk 2496 +VFMULCPHZrrbkz 2497 +VFMULCPHZrrk 2498 +VFMULCPHZrrkz 2499 +VFMULCSHZrm 2500 +VFMULCSHZrmk 2501 +VFMULCSHZrmkz 2502 +VFMULCSHZrr 2503 +VFMULCSHZrrb 2504 +VFMULCSHZrrbk 2505 +VFMULCSHZrrbkz 2506 +VFMULCSHZrrk 2507 +VFMULCSHZrrkz 2508 +VFNMADD 2509 +VFNMADDPD 2510 +VFNMADDPS 2511 +VFNMADDSD 2512 +VFNMADDSS 2513 +VFNMSUB 2514 +VFNMSUBPD 2515 +VFNMSUBPS 2516 +VFNMSUBSD 2517 +VFNMSUBSS 2518 +VFPCLASSBF 2519 +VFPCLASSPDZ 2520 +VFPCLASSPDZmbi 2521 +VFPCLASSPDZmbik 2522 +VFPCLASSPDZmi 2523 +VFPCLASSPDZmik 2524 +VFPCLASSPDZri 2525 +VFPCLASSPDZrik 2526 +VFPCLASSPHZ 2527 +VFPCLASSPHZmbi 2528 +VFPCLASSPHZmbik 2529 +VFPCLASSPHZmi 2530 +VFPCLASSPHZmik 2531 +VFPCLASSPHZri 2532 +VFPCLASSPHZrik 2533 +VFPCLASSPSZ 2534 +VFPCLASSPSZmbi 2535 +VFPCLASSPSZmbik 2536 +VFPCLASSPSZmi 2537 +VFPCLASSPSZmik 2538 +VFPCLASSPSZri 2539 +VFPCLASSPSZrik 2540 +VFPCLASSSDZmi 2541 +VFPCLASSSDZmik 2542 +VFPCLASSSDZri 2543 +VFPCLASSSDZrik 2544 +VFPCLASSSHZmi 2545 +VFPCLASSSHZmik 2546 +VFPCLASSSHZri 2547 +VFPCLASSSHZrik 2548 +VFPCLASSSSZmi 2549 +VFPCLASSSSZmik 2550 +VFPCLASSSSZri 2551 +VFPCLASSSSZrik 2552 +VFRCZPDYrm 2553 +VFRCZPDYrr 2554 +VFRCZPDrm 2555 +VFRCZPDrr 2556 +VFRCZPSYrm 2557 +VFRCZPSYrr 2558 +VFRCZPSrm 2559 +VFRCZPSrr 2560 +VFRCZSDrm 2561 +VFRCZSDrr 2562 +VFRCZSSrm 2563 +VFRCZSSrr 2564 +VGATHERDPDYrm 2565 +VGATHERDPDZ 2566 +VGATHERDPDZrm 2567 +VGATHERDPDrm 2568 +VGATHERDPSYrm 2569 +VGATHERDPSZ 2570 +VGATHERDPSZrm 2571 +VGATHERDPSrm 2572 +VGATHERPF 2573 +VGATHERQPDYrm 2574 +VGATHERQPDZ 2575 +VGATHERQPDZrm 2576 +VGATHERQPDrm 2577 +VGATHERQPSYrm 2578 +VGATHERQPSZ 2579 +VGATHERQPSZrm 2580 +VGATHERQPSrm 2581 +VGETEXPBF 2582 +VGETEXPPDZ 2583 +VGETEXPPDZm 2584 +VGETEXPPDZmb 2585 +VGETEXPPDZmbk 2586 +VGETEXPPDZmbkz 2587 +VGETEXPPDZmk 2588 +VGETEXPPDZmkz 2589 +VGETEXPPDZr 2590 +VGETEXPPDZrb 2591 +VGETEXPPDZrbk 2592 +VGETEXPPDZrbkz 2593 +VGETEXPPDZrk 2594 +VGETEXPPDZrkz 2595 +VGETEXPPHZ 2596 +VGETEXPPHZm 2597 +VGETEXPPHZmb 2598 +VGETEXPPHZmbk 2599 +VGETEXPPHZmbkz 2600 +VGETEXPPHZmk 2601 +VGETEXPPHZmkz 2602 +VGETEXPPHZr 2603 +VGETEXPPHZrb 2604 +VGETEXPPHZrbk 2605 +VGETEXPPHZrbkz 2606 +VGETEXPPHZrk 2607 +VGETEXPPHZrkz 2608 +VGETEXPPSZ 2609 +VGETEXPPSZm 2610 +VGETEXPPSZmb 2611 +VGETEXPPSZmbk 2612 +VGETEXPPSZmbkz 2613 +VGETEXPPSZmk 2614 +VGETEXPPSZmkz 2615 +VGETEXPPSZr 2616 +VGETEXPPSZrb 2617 +VGETEXPPSZrbk 2618 +VGETEXPPSZrbkz 2619 +VGETEXPPSZrk 2620 +VGETEXPPSZrkz 2621 +VGETEXPSDZm 2622 +VGETEXPSDZmk 2623 +VGETEXPSDZmkz 2624 +VGETEXPSDZr 2625 +VGETEXPSDZrb 2626 +VGETEXPSDZrbk 2627 +VGETEXPSDZrbkz 2628 +VGETEXPSDZrk 2629 +VGETEXPSDZrkz 2630 +VGETEXPSHZm 2631 +VGETEXPSHZmk 2632 +VGETEXPSHZmkz 2633 +VGETEXPSHZr 2634 +VGETEXPSHZrb 2635 +VGETEXPSHZrbk 2636 +VGETEXPSHZrbkz 2637 +VGETEXPSHZrk 2638 +VGETEXPSHZrkz 2639 +VGETEXPSSZm 2640 +VGETEXPSSZmk 2641 +VGETEXPSSZmkz 2642 +VGETEXPSSZr 2643 +VGETEXPSSZrb 2644 +VGETEXPSSZrbk 2645 +VGETEXPSSZrbkz 2646 +VGETEXPSSZrk 2647 +VGETEXPSSZrkz 2648 +VGETMANTBF 2649 +VGETMANTPDZ 2650 +VGETMANTPDZrmbi 2651 +VGETMANTPDZrmbik 2652 +VGETMANTPDZrmbikz 2653 +VGETMANTPDZrmi 2654 +VGETMANTPDZrmik 2655 +VGETMANTPDZrmikz 2656 +VGETMANTPDZrri 2657 +VGETMANTPDZrrib 2658 +VGETMANTPDZrribk 2659 +VGETMANTPDZrribkz 2660 +VGETMANTPDZrrik 2661 +VGETMANTPDZrrikz 2662 +VGETMANTPHZ 2663 +VGETMANTPHZrmbi 2664 +VGETMANTPHZrmbik 2665 +VGETMANTPHZrmbikz 2666 +VGETMANTPHZrmi 2667 +VGETMANTPHZrmik 2668 +VGETMANTPHZrmikz 2669 +VGETMANTPHZrri 2670 +VGETMANTPHZrrib 2671 +VGETMANTPHZrribk 2672 +VGETMANTPHZrribkz 2673 +VGETMANTPHZrrik 2674 +VGETMANTPHZrrikz 2675 +VGETMANTPSZ 2676 +VGETMANTPSZrmbi 2677 +VGETMANTPSZrmbik 2678 +VGETMANTPSZrmbikz 2679 +VGETMANTPSZrmi 2680 +VGETMANTPSZrmik 2681 +VGETMANTPSZrmikz 2682 +VGETMANTPSZrri 2683 +VGETMANTPSZrrib 2684 +VGETMANTPSZrribk 2685 +VGETMANTPSZrribkz 2686 +VGETMANTPSZrrik 2687 +VGETMANTPSZrrikz 2688 +VGETMANTSDZrmi 2689 +VGETMANTSDZrmik 2690 +VGETMANTSDZrmikz 2691 +VGETMANTSDZrri 2692 +VGETMANTSDZrrib 2693 +VGETMANTSDZrribk 2694 +VGETMANTSDZrribkz 2695 +VGETMANTSDZrrik 2696 +VGETMANTSDZrrikz 2697 +VGETMANTSHZrmi 2698 +VGETMANTSHZrmik 2699 +VGETMANTSHZrmikz 2700 +VGETMANTSHZrri 2701 +VGETMANTSHZrrib 2702 +VGETMANTSHZrribk 2703 +VGETMANTSHZrribkz 2704 +VGETMANTSHZrrik 2705 +VGETMANTSHZrrikz 2706 +VGETMANTSSZrmi 2707 +VGETMANTSSZrmik 2708 +VGETMANTSSZrmikz 2709 +VGETMANTSSZrri 2710 +VGETMANTSSZrrib 2711 +VGETMANTSSZrribk 2712 +VGETMANTSSZrribkz 2713 +VGETMANTSSZrrik 2714 +VGETMANTSSZrrikz 2715 +VGF 2716 +VHADDPDYrm 2717 +VHADDPDYrr 2718 +VHADDPDrm 2719 +VHADDPDrr 2720 +VHADDPSYrm 2721 +VHADDPSYrr 2722 +VHADDPSrm 2723 +VHADDPSrr 2724 +VHSUBPDYrm 2725 +VHSUBPDYrr 2726 +VHSUBPDrm 2727 +VHSUBPDrr 2728 +VHSUBPSYrm 2729 +VHSUBPSYrr 2730 +VHSUBPSrm 2731 +VHSUBPSrr 2732 +VINSERTF 2733 +VINSERTI 2734 +VINSERTPSZrmi 2735 +VINSERTPSZrri 2736 +VINSERTPSrmi 2737 +VINSERTPSrri 2738 +VLDDQUYrm 2739 +VLDDQUrm 2740 +VLDMXCSR 2741 +VMASKMOVDQU 2742 +VMASKMOVPDYmr 2743 +VMASKMOVPDYrm 2744 +VMASKMOVPDmr 2745 +VMASKMOVPDrm 2746 +VMASKMOVPSYmr 2747 +VMASKMOVPSYrm 2748 +VMASKMOVPSmr 2749 +VMASKMOVPSrm 2750 +VMAXBF 2751 +VMAXCPDYrm 2752 +VMAXCPDYrr 2753 +VMAXCPDZ 2754 +VMAXCPDZrm 2755 +VMAXCPDZrmb 2756 +VMAXCPDZrmbk 2757 +VMAXCPDZrmbkz 2758 +VMAXCPDZrmk 2759 +VMAXCPDZrmkz 2760 +VMAXCPDZrr 2761 +VMAXCPDZrrk 2762 +VMAXCPDZrrkz 2763 +VMAXCPDrm 2764 +VMAXCPDrr 2765 +VMAXCPHZ 2766 +VMAXCPHZrm 2767 +VMAXCPHZrmb 2768 +VMAXCPHZrmbk 2769 +VMAXCPHZrmbkz 2770 +VMAXCPHZrmk 2771 +VMAXCPHZrmkz 2772 +VMAXCPHZrr 2773 +VMAXCPHZrrk 2774 +VMAXCPHZrrkz 2775 +VMAXCPSYrm 2776 +VMAXCPSYrr 2777 +VMAXCPSZ 2778 +VMAXCPSZrm 2779 +VMAXCPSZrmb 2780 +VMAXCPSZrmbk 2781 +VMAXCPSZrmbkz 2782 +VMAXCPSZrmk 2783 +VMAXCPSZrmkz 2784 +VMAXCPSZrr 2785 +VMAXCPSZrrk 2786 +VMAXCPSZrrkz 2787 +VMAXCPSrm 2788 +VMAXCPSrr 2789 +VMAXCSDZrm 2790 +VMAXCSDZrr 2791 +VMAXCSDrm 2792 +VMAXCSDrr 2793 +VMAXCSHZrm 2794 +VMAXCSHZrr 2795 +VMAXCSSZrm 2796 +VMAXCSSZrr 2797 +VMAXCSSrm 2798 +VMAXCSSrr 2799 +VMAXPDYrm 2800 +VMAXPDYrr 2801 +VMAXPDZ 2802 +VMAXPDZrm 2803 +VMAXPDZrmb 2804 +VMAXPDZrmbk 2805 +VMAXPDZrmbkz 2806 +VMAXPDZrmk 2807 +VMAXPDZrmkz 2808 +VMAXPDZrr 2809 +VMAXPDZrrb 2810 +VMAXPDZrrbk 2811 +VMAXPDZrrbkz 2812 +VMAXPDZrrk 2813 +VMAXPDZrrkz 2814 +VMAXPDrm 2815 +VMAXPDrr 2816 +VMAXPHZ 2817 +VMAXPHZrm 2818 +VMAXPHZrmb 2819 +VMAXPHZrmbk 2820 +VMAXPHZrmbkz 2821 +VMAXPHZrmk 2822 +VMAXPHZrmkz 2823 +VMAXPHZrr 2824 +VMAXPHZrrb 2825 +VMAXPHZrrbk 2826 +VMAXPHZrrbkz 2827 +VMAXPHZrrk 2828 +VMAXPHZrrkz 2829 +VMAXPSYrm 2830 +VMAXPSYrr 2831 +VMAXPSZ 2832 +VMAXPSZrm 2833 +VMAXPSZrmb 2834 +VMAXPSZrmbk 2835 +VMAXPSZrmbkz 2836 +VMAXPSZrmk 2837 +VMAXPSZrmkz 2838 +VMAXPSZrr 2839 +VMAXPSZrrb 2840 +VMAXPSZrrbk 2841 +VMAXPSZrrbkz 2842 +VMAXPSZrrk 2843 +VMAXPSZrrkz 2844 +VMAXPSrm 2845 +VMAXPSrr 2846 +VMAXSDZrm 2847 +VMAXSDZrm_Int 2848 +VMAXSDZrmk_Int 2849 +VMAXSDZrmkz_Int 2850 +VMAXSDZrr 2851 +VMAXSDZrr_Int 2852 +VMAXSDZrrb_Int 2853 +VMAXSDZrrbk_Int 2854 +VMAXSDZrrbkz_Int 2855 +VMAXSDZrrk_Int 2856 +VMAXSDZrrkz_Int 2857 +VMAXSDrm 2858 +VMAXSDrm_Int 2859 +VMAXSDrr 2860 +VMAXSDrr_Int 2861 +VMAXSHZrm 2862 +VMAXSHZrm_Int 2863 +VMAXSHZrmk_Int 2864 +VMAXSHZrmkz_Int 2865 +VMAXSHZrr 2866 +VMAXSHZrr_Int 2867 +VMAXSHZrrb_Int 2868 +VMAXSHZrrbk_Int 2869 +VMAXSHZrrbkz_Int 2870 +VMAXSHZrrk_Int 2871 +VMAXSHZrrkz_Int 2872 +VMAXSSZrm 2873 +VMAXSSZrm_Int 2874 +VMAXSSZrmk_Int 2875 +VMAXSSZrmkz_Int 2876 +VMAXSSZrr 2877 +VMAXSSZrr_Int 2878 +VMAXSSZrrb_Int 2879 +VMAXSSZrrbk_Int 2880 +VMAXSSZrrbkz_Int 2881 +VMAXSSZrrk_Int 2882 +VMAXSSZrrkz_Int 2883 +VMAXSSrm 2884 +VMAXSSrm_Int 2885 +VMAXSSrr 2886 +VMAXSSrr_Int 2887 +VMCALL 2888 +VMCLEARm 2889 +VMFUNC 2890 +VMINBF 2891 +VMINCPDYrm 2892 +VMINCPDYrr 2893 +VMINCPDZ 2894 +VMINCPDZrm 2895 +VMINCPDZrmb 2896 +VMINCPDZrmbk 2897 +VMINCPDZrmbkz 2898 +VMINCPDZrmk 2899 +VMINCPDZrmkz 2900 +VMINCPDZrr 2901 +VMINCPDZrrk 2902 +VMINCPDZrrkz 2903 +VMINCPDrm 2904 +VMINCPDrr 2905 +VMINCPHZ 2906 +VMINCPHZrm 2907 +VMINCPHZrmb 2908 +VMINCPHZrmbk 2909 +VMINCPHZrmbkz 2910 +VMINCPHZrmk 2911 +VMINCPHZrmkz 2912 +VMINCPHZrr 2913 +VMINCPHZrrk 2914 +VMINCPHZrrkz 2915 +VMINCPSYrm 2916 +VMINCPSYrr 2917 +VMINCPSZ 2918 +VMINCPSZrm 2919 +VMINCPSZrmb 2920 +VMINCPSZrmbk 2921 +VMINCPSZrmbkz 2922 +VMINCPSZrmk 2923 +VMINCPSZrmkz 2924 +VMINCPSZrr 2925 +VMINCPSZrrk 2926 +VMINCPSZrrkz 2927 +VMINCPSrm 2928 +VMINCPSrr 2929 +VMINCSDZrm 2930 +VMINCSDZrr 2931 +VMINCSDrm 2932 +VMINCSDrr 2933 +VMINCSHZrm 2934 +VMINCSHZrr 2935 +VMINCSSZrm 2936 +VMINCSSZrr 2937 +VMINCSSrm 2938 +VMINCSSrr 2939 +VMINMAXBF 2940 +VMINMAXPDZ 2941 +VMINMAXPDZrmbi 2942 +VMINMAXPDZrmbik 2943 +VMINMAXPDZrmbikz 2944 +VMINMAXPDZrmi 2945 +VMINMAXPDZrmik 2946 +VMINMAXPDZrmikz 2947 +VMINMAXPDZrri 2948 +VMINMAXPDZrrib 2949 +VMINMAXPDZrribk 2950 +VMINMAXPDZrribkz 2951 +VMINMAXPDZrrik 2952 +VMINMAXPDZrrikz 2953 +VMINMAXPHZ 2954 +VMINMAXPHZrmbi 2955 +VMINMAXPHZrmbik 2956 +VMINMAXPHZrmbikz 2957 +VMINMAXPHZrmi 2958 +VMINMAXPHZrmik 2959 +VMINMAXPHZrmikz 2960 +VMINMAXPHZrri 2961 +VMINMAXPHZrrib 2962 +VMINMAXPHZrribk 2963 +VMINMAXPHZrribkz 2964 +VMINMAXPHZrrik 2965 +VMINMAXPHZrrikz 2966 +VMINMAXPSZ 2967 +VMINMAXPSZrmbi 2968 +VMINMAXPSZrmbik 2969 +VMINMAXPSZrmbikz 2970 +VMINMAXPSZrmi 2971 +VMINMAXPSZrmik 2972 +VMINMAXPSZrmikz 2973 +VMINMAXPSZrri 2974 +VMINMAXPSZrrib 2975 +VMINMAXPSZrribk 2976 +VMINMAXPSZrribkz 2977 +VMINMAXPSZrrik 2978 +VMINMAXPSZrrikz 2979 +VMINMAXSDrmi 2980 +VMINMAXSDrmi_Int 2981 +VMINMAXSDrmik_Int 2982 +VMINMAXSDrmikz_Int 2983 +VMINMAXSDrri 2984 +VMINMAXSDrri_Int 2985 +VMINMAXSDrrib_Int 2986 +VMINMAXSDrribk_Int 2987 +VMINMAXSDrribkz_Int 2988 +VMINMAXSDrrik_Int 2989 +VMINMAXSDrrikz_Int 2990 +VMINMAXSHrmi 2991 +VMINMAXSHrmi_Int 2992 +VMINMAXSHrmik_Int 2993 +VMINMAXSHrmikz_Int 2994 +VMINMAXSHrri 2995 +VMINMAXSHrri_Int 2996 +VMINMAXSHrrib_Int 2997 +VMINMAXSHrribk_Int 2998 +VMINMAXSHrribkz_Int 2999 +VMINMAXSHrrik_Int 3000 +VMINMAXSHrrikz_Int 3001 +VMINMAXSSrmi 3002 +VMINMAXSSrmi_Int 3003 +VMINMAXSSrmik_Int 3004 +VMINMAXSSrmikz_Int 3005 +VMINMAXSSrri 3006 +VMINMAXSSrri_Int 3007 +VMINMAXSSrrib_Int 3008 +VMINMAXSSrribk_Int 3009 +VMINMAXSSrribkz_Int 3010 +VMINMAXSSrrik_Int 3011 +VMINMAXSSrrikz_Int 3012 +VMINPDYrm 3013 +VMINPDYrr 3014 +VMINPDZ 3015 +VMINPDZrm 3016 +VMINPDZrmb 3017 +VMINPDZrmbk 3018 +VMINPDZrmbkz 3019 +VMINPDZrmk 3020 +VMINPDZrmkz 3021 +VMINPDZrr 3022 +VMINPDZrrb 3023 +VMINPDZrrbk 3024 +VMINPDZrrbkz 3025 +VMINPDZrrk 3026 +VMINPDZrrkz 3027 +VMINPDrm 3028 +VMINPDrr 3029 +VMINPHZ 3030 +VMINPHZrm 3031 +VMINPHZrmb 3032 +VMINPHZrmbk 3033 +VMINPHZrmbkz 3034 +VMINPHZrmk 3035 +VMINPHZrmkz 3036 +VMINPHZrr 3037 +VMINPHZrrb 3038 +VMINPHZrrbk 3039 +VMINPHZrrbkz 3040 +VMINPHZrrk 3041 +VMINPHZrrkz 3042 +VMINPSYrm 3043 +VMINPSYrr 3044 +VMINPSZ 3045 +VMINPSZrm 3046 +VMINPSZrmb 3047 +VMINPSZrmbk 3048 +VMINPSZrmbkz 3049 +VMINPSZrmk 3050 +VMINPSZrmkz 3051 +VMINPSZrr 3052 +VMINPSZrrb 3053 +VMINPSZrrbk 3054 +VMINPSZrrbkz 3055 +VMINPSZrrk 3056 +VMINPSZrrkz 3057 +VMINPSrm 3058 +VMINPSrr 3059 +VMINSDZrm 3060 +VMINSDZrm_Int 3061 +VMINSDZrmk_Int 3062 +VMINSDZrmkz_Int 3063 +VMINSDZrr 3064 +VMINSDZrr_Int 3065 +VMINSDZrrb_Int 3066 +VMINSDZrrbk_Int 3067 +VMINSDZrrbkz_Int 3068 +VMINSDZrrk_Int 3069 +VMINSDZrrkz_Int 3070 +VMINSDrm 3071 +VMINSDrm_Int 3072 +VMINSDrr 3073 +VMINSDrr_Int 3074 +VMINSHZrm 3075 +VMINSHZrm_Int 3076 +VMINSHZrmk_Int 3077 +VMINSHZrmkz_Int 3078 +VMINSHZrr 3079 +VMINSHZrr_Int 3080 +VMINSHZrrb_Int 3081 +VMINSHZrrbk_Int 3082 +VMINSHZrrbkz_Int 3083 +VMINSHZrrk_Int 3084 +VMINSHZrrkz_Int 3085 +VMINSSZrm 3086 +VMINSSZrm_Int 3087 +VMINSSZrmk_Int 3088 +VMINSSZrmkz_Int 3089 +VMINSSZrr 3090 +VMINSSZrr_Int 3091 +VMINSSZrrb_Int 3092 +VMINSSZrrbk_Int 3093 +VMINSSZrrbkz_Int 3094 +VMINSSZrrk_Int 3095 +VMINSSZrrkz_Int 3096 +VMINSSrm 3097 +VMINSSrm_Int 3098 +VMINSSrr 3099 +VMINSSrr_Int 3100 +VMLAUNCH 3101 +VMLOAD 3102 +VMMCALL 3103 +VMOV 3104 +VMOVAPDYmr 3105 +VMOVAPDYrm 3106 +VMOVAPDYrr 3107 +VMOVAPDYrr_REV 3108 +VMOVAPDZ 3109 +VMOVAPDZmr 3110 +VMOVAPDZmrk 3111 +VMOVAPDZrm 3112 +VMOVAPDZrmk 3113 +VMOVAPDZrmkz 3114 +VMOVAPDZrr 3115 +VMOVAPDZrr_REV 3116 +VMOVAPDZrrk 3117 +VMOVAPDZrrk_REV 3118 +VMOVAPDZrrkz 3119 +VMOVAPDZrrkz_REV 3120 +VMOVAPDmr 3121 +VMOVAPDrm 3122 +VMOVAPDrr 3123 +VMOVAPDrr_REV 3124 +VMOVAPSYmr 3125 +VMOVAPSYrm 3126 +VMOVAPSYrr 3127 +VMOVAPSYrr_REV 3128 +VMOVAPSZ 3129 +VMOVAPSZmr 3130 +VMOVAPSZmrk 3131 +VMOVAPSZrm 3132 +VMOVAPSZrmk 3133 +VMOVAPSZrmkz 3134 +VMOVAPSZrr 3135 +VMOVAPSZrr_REV 3136 +VMOVAPSZrrk 3137 +VMOVAPSZrrk_REV 3138 +VMOVAPSZrrkz 3139 +VMOVAPSZrrkz_REV 3140 +VMOVAPSmr 3141 +VMOVAPSrm 3142 +VMOVAPSrr 3143 +VMOVAPSrr_REV 3144 +VMOVDDUPYrm 3145 +VMOVDDUPYrr 3146 +VMOVDDUPZ 3147 +VMOVDDUPZrm 3148 +VMOVDDUPZrmk 3149 +VMOVDDUPZrmkz 3150 +VMOVDDUPZrr 3151 +VMOVDDUPZrrk 3152 +VMOVDDUPZrrkz 3153 +VMOVDDUPrm 3154 +VMOVDDUPrr 3155 +VMOVDI 3156 +VMOVDQA 3157 +VMOVDQAYmr 3158 +VMOVDQAYrm 3159 +VMOVDQAYrr 3160 +VMOVDQAYrr_REV 3161 +VMOVDQAmr 3162 +VMOVDQArm 3163 +VMOVDQArr 3164 +VMOVDQArr_REV 3165 +VMOVDQU 3166 +VMOVDQUYmr 3167 +VMOVDQUYrm 3168 +VMOVDQUYrr 3169 +VMOVDQUYrr_REV 3170 +VMOVDQUmr 3171 +VMOVDQUrm 3172 +VMOVDQUrr 3173 +VMOVDQUrr_REV 3174 +VMOVHLPSZrr 3175 +VMOVHLPSrr 3176 +VMOVHPDZ 3177 +VMOVHPDmr 3178 +VMOVHPDrm 3179 +VMOVHPSZ 3180 +VMOVHPSmr 3181 +VMOVHPSrm 3182 +VMOVLHPSZrr 3183 +VMOVLHPSrr 3184 +VMOVLPDZ 3185 +VMOVLPDmr 3186 +VMOVLPDrm 3187 +VMOVLPSZ 3188 +VMOVLPSmr 3189 +VMOVLPSrm 3190 +VMOVMSKPDYrr 3191 +VMOVMSKPDrr 3192 +VMOVMSKPSYrr 3193 +VMOVMSKPSrr 3194 +VMOVNTDQAYrm 3195 +VMOVNTDQAZ 3196 +VMOVNTDQAZrm 3197 +VMOVNTDQArm 3198 +VMOVNTDQYmr 3199 +VMOVNTDQZ 3200 +VMOVNTDQZmr 3201 +VMOVNTDQmr 3202 +VMOVNTPDYmr 3203 +VMOVNTPDZ 3204 +VMOVNTPDZmr 3205 +VMOVNTPDmr 3206 +VMOVNTPSYmr 3207 +VMOVNTPSZ 3208 +VMOVNTPSZmr 3209 +VMOVNTPSmr 3210 +VMOVPDI 3211 +VMOVPQI 3212 +VMOVPQIto 3213 +VMOVQI 3214 +VMOVRSBZ 3215 +VMOVRSBZm 3216 +VMOVRSBZmk 3217 +VMOVRSBZmkz 3218 +VMOVRSDZ 3219 +VMOVRSDZm 3220 +VMOVRSDZmk 3221 +VMOVRSDZmkz 3222 +VMOVRSQZ 3223 +VMOVRSQZm 3224 +VMOVRSQZmk 3225 +VMOVRSQZmkz 3226 +VMOVRSWZ 3227 +VMOVRSWZm 3228 +VMOVRSWZmk 3229 +VMOVRSWZmkz 3230 +VMOVSDZmr 3231 +VMOVSDZmrk 3232 +VMOVSDZrm 3233 +VMOVSDZrm_alt 3234 +VMOVSDZrmk 3235 +VMOVSDZrmkz 3236 +VMOVSDZrr 3237 +VMOVSDZrr_REV 3238 +VMOVSDZrrk 3239 +VMOVSDZrrk_REV 3240 +VMOVSDZrrkz 3241 +VMOVSDZrrkz_REV 3242 +VMOVSDmr 3243 +VMOVSDrm 3244 +VMOVSDrm_alt 3245 +VMOVSDrr 3246 +VMOVSDrr_REV 3247 +VMOVSDto 3248 +VMOVSH 3249 +VMOVSHDUPYrm 3250 +VMOVSHDUPYrr 3251 +VMOVSHDUPZ 3252 +VMOVSHDUPZrm 3253 +VMOVSHDUPZrmk 3254 +VMOVSHDUPZrmkz 3255 +VMOVSHDUPZrr 3256 +VMOVSHDUPZrrk 3257 +VMOVSHDUPZrrkz 3258 +VMOVSHDUPrm 3259 +VMOVSHDUPrr 3260 +VMOVSHZmr 3261 +VMOVSHZmrk 3262 +VMOVSHZrm 3263 +VMOVSHZrm_alt 3264 +VMOVSHZrmk 3265 +VMOVSHZrmkz 3266 +VMOVSHZrr 3267 +VMOVSHZrr_REV 3268 +VMOVSHZrrk 3269 +VMOVSHZrrk_REV 3270 +VMOVSHZrrkz 3271 +VMOVSHZrrkz_REV 3272 +VMOVSHtoW 3273 +VMOVSLDUPYrm 3274 +VMOVSLDUPYrr 3275 +VMOVSLDUPZ 3276 +VMOVSLDUPZrm 3277 +VMOVSLDUPZrmk 3278 +VMOVSLDUPZrmkz 3279 +VMOVSLDUPZrr 3280 +VMOVSLDUPZrrk 3281 +VMOVSLDUPZrrkz 3282 +VMOVSLDUPrm 3283 +VMOVSLDUPrr 3284 +VMOVSS 3285 +VMOVSSZmr 3286 +VMOVSSZmrk 3287 +VMOVSSZrm 3288 +VMOVSSZrm_alt 3289 +VMOVSSZrmk 3290 +VMOVSSZrmkz 3291 +VMOVSSZrr 3292 +VMOVSSZrr_REV 3293 +VMOVSSZrrk 3294 +VMOVSSZrrk_REV 3295 +VMOVSSZrrkz 3296 +VMOVSSZrrkz_REV 3297 +VMOVSSmr 3298 +VMOVSSrm 3299 +VMOVSSrm_alt 3300 +VMOVSSrr 3301 +VMOVSSrr_REV 3302 +VMOVUPDYmr 3303 +VMOVUPDYrm 3304 +VMOVUPDYrr 3305 +VMOVUPDYrr_REV 3306 +VMOVUPDZ 3307 +VMOVUPDZmr 3308 +VMOVUPDZmrk 3309 +VMOVUPDZrm 3310 +VMOVUPDZrmk 3311 +VMOVUPDZrmkz 3312 +VMOVUPDZrr 3313 +VMOVUPDZrr_REV 3314 +VMOVUPDZrrk 3315 +VMOVUPDZrrk_REV 3316 +VMOVUPDZrrkz 3317 +VMOVUPDZrrkz_REV 3318 +VMOVUPDmr 3319 +VMOVUPDrm 3320 +VMOVUPDrr 3321 +VMOVUPDrr_REV 3322 +VMOVUPSYmr 3323 +VMOVUPSYrm 3324 +VMOVUPSYrr 3325 +VMOVUPSYrr_REV 3326 +VMOVUPSZ 3327 +VMOVUPSZmr 3328 +VMOVUPSZmrk 3329 +VMOVUPSZrm 3330 +VMOVUPSZrmk 3331 +VMOVUPSZrmkz 3332 +VMOVUPSZrr 3333 +VMOVUPSZrr_REV 3334 +VMOVUPSZrrk 3335 +VMOVUPSZrrk_REV 3336 +VMOVUPSZrrkz 3337 +VMOVUPSZrrkz_REV 3338 +VMOVUPSmr 3339 +VMOVUPSrm 3340 +VMOVUPSrr 3341 +VMOVUPSrr_REV 3342 +VMOVW 3343 +VMOVWmr 3344 +VMOVWrm 3345 +VMOVZPDILo 3346 +VMOVZPQILo 3347 +VMOVZPWILo 3348 +VMPSADBWYrmi 3349 +VMPSADBWYrri 3350 +VMPSADBWZ 3351 +VMPSADBWZrmi 3352 +VMPSADBWZrmik 3353 +VMPSADBWZrmikz 3354 +VMPSADBWZrri 3355 +VMPSADBWZrrik 3356 +VMPSADBWZrrikz 3357 +VMPSADBWrmi 3358 +VMPSADBWrri 3359 +VMPTRLDm 3360 +VMPTRSTm 3361 +VMREAD 3362 +VMRESUME 3363 +VMRUN 3364 +VMSAVE 3365 +VMULBF 3366 +VMULPDYrm 3367 +VMULPDYrr 3368 +VMULPDZ 3369 +VMULPDZrm 3370 +VMULPDZrmb 3371 +VMULPDZrmbk 3372 +VMULPDZrmbkz 3373 +VMULPDZrmk 3374 +VMULPDZrmkz 3375 +VMULPDZrr 3376 +VMULPDZrrb 3377 +VMULPDZrrbk 3378 +VMULPDZrrbkz 3379 +VMULPDZrrk 3380 +VMULPDZrrkz 3381 +VMULPDrm 3382 +VMULPDrr 3383 +VMULPHZ 3384 +VMULPHZrm 3385 +VMULPHZrmb 3386 +VMULPHZrmbk 3387 +VMULPHZrmbkz 3388 +VMULPHZrmk 3389 +VMULPHZrmkz 3390 +VMULPHZrr 3391 +VMULPHZrrb 3392 +VMULPHZrrbk 3393 +VMULPHZrrbkz 3394 +VMULPHZrrk 3395 +VMULPHZrrkz 3396 +VMULPSYrm 3397 +VMULPSYrr 3398 +VMULPSZ 3399 +VMULPSZrm 3400 +VMULPSZrmb 3401 +VMULPSZrmbk 3402 +VMULPSZrmbkz 3403 +VMULPSZrmk 3404 +VMULPSZrmkz 3405 +VMULPSZrr 3406 +VMULPSZrrb 3407 +VMULPSZrrbk 3408 +VMULPSZrrbkz 3409 +VMULPSZrrk 3410 +VMULPSZrrkz 3411 +VMULPSrm 3412 +VMULPSrr 3413 +VMULSDZrm 3414 +VMULSDZrm_Int 3415 +VMULSDZrmk_Int 3416 +VMULSDZrmkz_Int 3417 +VMULSDZrr 3418 +VMULSDZrr_Int 3419 +VMULSDZrrb_Int 3420 +VMULSDZrrbk_Int 3421 +VMULSDZrrbkz_Int 3422 +VMULSDZrrk_Int 3423 +VMULSDZrrkz_Int 3424 +VMULSDrm 3425 +VMULSDrm_Int 3426 +VMULSDrr 3427 +VMULSDrr_Int 3428 +VMULSHZrm 3429 +VMULSHZrm_Int 3430 +VMULSHZrmk_Int 3431 +VMULSHZrmkz_Int 3432 +VMULSHZrr 3433 +VMULSHZrr_Int 3434 +VMULSHZrrb_Int 3435 +VMULSHZrrbk_Int 3436 +VMULSHZrrbkz_Int 3437 +VMULSHZrrk_Int 3438 +VMULSHZrrkz_Int 3439 +VMULSSZrm 3440 +VMULSSZrm_Int 3441 +VMULSSZrmk_Int 3442 +VMULSSZrmkz_Int 3443 +VMULSSZrr 3444 +VMULSSZrr_Int 3445 +VMULSSZrrb_Int 3446 +VMULSSZrrbk_Int 3447 +VMULSSZrrbkz_Int 3448 +VMULSSZrrk_Int 3449 +VMULSSZrrkz_Int 3450 +VMULSSrm 3451 +VMULSSrm_Int 3452 +VMULSSrr 3453 +VMULSSrr_Int 3454 +VMWRITE 3455 +VMXOFF 3456 +VMXON 3457 +VORPDYrm 3458 +VORPDYrr 3459 +VORPDZ 3460 +VORPDZrm 3461 +VORPDZrmb 3462 +VORPDZrmbk 3463 +VORPDZrmbkz 3464 +VORPDZrmk 3465 +VORPDZrmkz 3466 +VORPDZrr 3467 +VORPDZrrk 3468 +VORPDZrrkz 3469 +VORPDrm 3470 +VORPDrr 3471 +VORPSYrm 3472 +VORPSYrr 3473 +VORPSZ 3474 +VORPSZrm 3475 +VORPSZrmb 3476 +VORPSZrmbk 3477 +VORPSZrmbkz 3478 +VORPSZrmk 3479 +VORPSZrmkz 3480 +VORPSZrr 3481 +VORPSZrrk 3482 +VORPSZrrkz 3483 +VORPSrm 3484 +VORPSrr 3485 +VP 3486 +VPABSBYrm 3487 +VPABSBYrr 3488 +VPABSBZ 3489 +VPABSBZrm 3490 +VPABSBZrmk 3491 +VPABSBZrmkz 3492 +VPABSBZrr 3493 +VPABSBZrrk 3494 +VPABSBZrrkz 3495 +VPABSBrm 3496 +VPABSBrr 3497 +VPABSDYrm 3498 +VPABSDYrr 3499 +VPABSDZ 3500 +VPABSDZrm 3501 +VPABSDZrmb 3502 +VPABSDZrmbk 3503 +VPABSDZrmbkz 3504 +VPABSDZrmk 3505 +VPABSDZrmkz 3506 +VPABSDZrr 3507 +VPABSDZrrk 3508 +VPABSDZrrkz 3509 +VPABSDrm 3510 +VPABSDrr 3511 +VPABSQZ 3512 +VPABSQZrm 3513 +VPABSQZrmb 3514 +VPABSQZrmbk 3515 +VPABSQZrmbkz 3516 +VPABSQZrmk 3517 +VPABSQZrmkz 3518 +VPABSQZrr 3519 +VPABSQZrrk 3520 +VPABSQZrrkz 3521 +VPABSWYrm 3522 +VPABSWYrr 3523 +VPABSWZ 3524 +VPABSWZrm 3525 +VPABSWZrmk 3526 +VPABSWZrmkz 3527 +VPABSWZrr 3528 +VPABSWZrrk 3529 +VPABSWZrrkz 3530 +VPABSWrm 3531 +VPABSWrr 3532 +VPACKSSDWYrm 3533 +VPACKSSDWYrr 3534 +VPACKSSDWZ 3535 +VPACKSSDWZrm 3536 +VPACKSSDWZrmb 3537 +VPACKSSDWZrmbk 3538 +VPACKSSDWZrmbkz 3539 +VPACKSSDWZrmk 3540 +VPACKSSDWZrmkz 3541 +VPACKSSDWZrr 3542 +VPACKSSDWZrrk 3543 +VPACKSSDWZrrkz 3544 +VPACKSSDWrm 3545 +VPACKSSDWrr 3546 +VPACKSSWBYrm 3547 +VPACKSSWBYrr 3548 +VPACKSSWBZ 3549 +VPACKSSWBZrm 3550 +VPACKSSWBZrmk 3551 +VPACKSSWBZrmkz 3552 +VPACKSSWBZrr 3553 +VPACKSSWBZrrk 3554 +VPACKSSWBZrrkz 3555 +VPACKSSWBrm 3556 +VPACKSSWBrr 3557 +VPACKUSDWYrm 3558 +VPACKUSDWYrr 3559 +VPACKUSDWZ 3560 +VPACKUSDWZrm 3561 +VPACKUSDWZrmb 3562 +VPACKUSDWZrmbk 3563 +VPACKUSDWZrmbkz 3564 +VPACKUSDWZrmk 3565 +VPACKUSDWZrmkz 3566 +VPACKUSDWZrr 3567 +VPACKUSDWZrrk 3568 +VPACKUSDWZrrkz 3569 +VPACKUSDWrm 3570 +VPACKUSDWrr 3571 +VPACKUSWBYrm 3572 +VPACKUSWBYrr 3573 +VPACKUSWBZ 3574 +VPACKUSWBZrm 3575 +VPACKUSWBZrmk 3576 +VPACKUSWBZrmkz 3577 +VPACKUSWBZrr 3578 +VPACKUSWBZrrk 3579 +VPACKUSWBZrrkz 3580 +VPACKUSWBrm 3581 +VPACKUSWBrr 3582 +VPADDBYrm 3583 +VPADDBYrr 3584 +VPADDBZ 3585 +VPADDBZrm 3586 +VPADDBZrmk 3587 +VPADDBZrmkz 3588 +VPADDBZrr 3589 +VPADDBZrrk 3590 +VPADDBZrrkz 3591 +VPADDBrm 3592 +VPADDBrr 3593 +VPADDDYrm 3594 +VPADDDYrr 3595 +VPADDDZ 3596 +VPADDDZrm 3597 +VPADDDZrmb 3598 +VPADDDZrmbk 3599 +VPADDDZrmbkz 3600 +VPADDDZrmk 3601 +VPADDDZrmkz 3602 +VPADDDZrr 3603 +VPADDDZrrk 3604 +VPADDDZrrkz 3605 +VPADDDrm 3606 +VPADDDrr 3607 +VPADDQYrm 3608 +VPADDQYrr 3609 +VPADDQZ 3610 +VPADDQZrm 3611 +VPADDQZrmb 3612 +VPADDQZrmbk 3613 +VPADDQZrmbkz 3614 +VPADDQZrmk 3615 +VPADDQZrmkz 3616 +VPADDQZrr 3617 +VPADDQZrrk 3618 +VPADDQZrrkz 3619 +VPADDQrm 3620 +VPADDQrr 3621 +VPADDSBYrm 3622 +VPADDSBYrr 3623 +VPADDSBZ 3624 +VPADDSBZrm 3625 +VPADDSBZrmk 3626 +VPADDSBZrmkz 3627 +VPADDSBZrr 3628 +VPADDSBZrrk 3629 +VPADDSBZrrkz 3630 +VPADDSBrm 3631 +VPADDSBrr 3632 +VPADDSWYrm 3633 +VPADDSWYrr 3634 +VPADDSWZ 3635 +VPADDSWZrm 3636 +VPADDSWZrmk 3637 +VPADDSWZrmkz 3638 +VPADDSWZrr 3639 +VPADDSWZrrk 3640 +VPADDSWZrrkz 3641 +VPADDSWrm 3642 +VPADDSWrr 3643 +VPADDUSBYrm 3644 +VPADDUSBYrr 3645 +VPADDUSBZ 3646 +VPADDUSBZrm 3647 +VPADDUSBZrmk 3648 +VPADDUSBZrmkz 3649 +VPADDUSBZrr 3650 +VPADDUSBZrrk 3651 +VPADDUSBZrrkz 3652 +VPADDUSBrm 3653 +VPADDUSBrr 3654 +VPADDUSWYrm 3655 +VPADDUSWYrr 3656 +VPADDUSWZ 3657 +VPADDUSWZrm 3658 +VPADDUSWZrmk 3659 +VPADDUSWZrmkz 3660 +VPADDUSWZrr 3661 +VPADDUSWZrrk 3662 +VPADDUSWZrrkz 3663 +VPADDUSWrm 3664 +VPADDUSWrr 3665 +VPADDWYrm 3666 +VPADDWYrr 3667 +VPADDWZ 3668 +VPADDWZrm 3669 +VPADDWZrmk 3670 +VPADDWZrmkz 3671 +VPADDWZrr 3672 +VPADDWZrrk 3673 +VPADDWZrrkz 3674 +VPADDWrm 3675 +VPADDWrr 3676 +VPALIGNRYrmi 3677 +VPALIGNRYrri 3678 +VPALIGNRZ 3679 +VPALIGNRZrmi 3680 +VPALIGNRZrmik 3681 +VPALIGNRZrmikz 3682 +VPALIGNRZrri 3683 +VPALIGNRZrrik 3684 +VPALIGNRZrrikz 3685 +VPALIGNRrmi 3686 +VPALIGNRrri 3687 +VPANDDZ 3688 +VPANDDZrm 3689 +VPANDDZrmb 3690 +VPANDDZrmbk 3691 +VPANDDZrmbkz 3692 +VPANDDZrmk 3693 +VPANDDZrmkz 3694 +VPANDDZrr 3695 +VPANDDZrrk 3696 +VPANDDZrrkz 3697 +VPANDNDZ 3698 +VPANDNDZrm 3699 +VPANDNDZrmb 3700 +VPANDNDZrmbk 3701 +VPANDNDZrmbkz 3702 +VPANDNDZrmk 3703 +VPANDNDZrmkz 3704 +VPANDNDZrr 3705 +VPANDNDZrrk 3706 +VPANDNDZrrkz 3707 +VPANDNQZ 3708 +VPANDNQZrm 3709 +VPANDNQZrmb 3710 +VPANDNQZrmbk 3711 +VPANDNQZrmbkz 3712 +VPANDNQZrmk 3713 +VPANDNQZrmkz 3714 +VPANDNQZrr 3715 +VPANDNQZrrk 3716 +VPANDNQZrrkz 3717 +VPANDNYrm 3718 +VPANDNYrr 3719 +VPANDNrm 3720 +VPANDNrr 3721 +VPANDQZ 3722 +VPANDQZrm 3723 +VPANDQZrmb 3724 +VPANDQZrmbk 3725 +VPANDQZrmbkz 3726 +VPANDQZrmk 3727 +VPANDQZrmkz 3728 +VPANDQZrr 3729 +VPANDQZrrk 3730 +VPANDQZrrkz 3731 +VPANDYrm 3732 +VPANDYrr 3733 +VPANDrm 3734 +VPANDrr 3735 +VPAVGBYrm 3736 +VPAVGBYrr 3737 +VPAVGBZ 3738 +VPAVGBZrm 3739 +VPAVGBZrmk 3740 +VPAVGBZrmkz 3741 +VPAVGBZrr 3742 +VPAVGBZrrk 3743 +VPAVGBZrrkz 3744 +VPAVGBrm 3745 +VPAVGBrr 3746 +VPAVGWYrm 3747 +VPAVGWYrr 3748 +VPAVGWZ 3749 +VPAVGWZrm 3750 +VPAVGWZrmk 3751 +VPAVGWZrmkz 3752 +VPAVGWZrr 3753 +VPAVGWZrrk 3754 +VPAVGWZrrkz 3755 +VPAVGWrm 3756 +VPAVGWrr 3757 +VPBLENDDYrmi 3758 +VPBLENDDYrri 3759 +VPBLENDDrmi 3760 +VPBLENDDrri 3761 +VPBLENDMBZ 3762 +VPBLENDMBZrm 3763 +VPBLENDMBZrmk 3764 +VPBLENDMBZrmkz 3765 +VPBLENDMBZrr 3766 +VPBLENDMBZrrk 3767 +VPBLENDMBZrrkz 3768 +VPBLENDMDZ 3769 +VPBLENDMDZrm 3770 +VPBLENDMDZrmb 3771 +VPBLENDMDZrmbk 3772 +VPBLENDMDZrmbkz 3773 +VPBLENDMDZrmk 3774 +VPBLENDMDZrmkz 3775 +VPBLENDMDZrr 3776 +VPBLENDMDZrrk 3777 +VPBLENDMDZrrkz 3778 +VPBLENDMQZ 3779 +VPBLENDMQZrm 3780 +VPBLENDMQZrmb 3781 +VPBLENDMQZrmbk 3782 +VPBLENDMQZrmbkz 3783 +VPBLENDMQZrmk 3784 +VPBLENDMQZrmkz 3785 +VPBLENDMQZrr 3786 +VPBLENDMQZrrk 3787 +VPBLENDMQZrrkz 3788 +VPBLENDMWZ 3789 +VPBLENDMWZrm 3790 +VPBLENDMWZrmk 3791 +VPBLENDMWZrmkz 3792 +VPBLENDMWZrr 3793 +VPBLENDMWZrrk 3794 +VPBLENDMWZrrkz 3795 +VPBLENDVBYrmr 3796 +VPBLENDVBYrrr 3797 +VPBLENDVBrmr 3798 +VPBLENDVBrrr 3799 +VPBLENDWYrmi 3800 +VPBLENDWYrri 3801 +VPBLENDWrmi 3802 +VPBLENDWrri 3803 +VPBROADCASTBYrm 3804 +VPBROADCASTBYrr 3805 +VPBROADCASTBZ 3806 +VPBROADCASTBZrm 3807 +VPBROADCASTBZrmk 3808 +VPBROADCASTBZrmkz 3809 +VPBROADCASTBZrr 3810 +VPBROADCASTBZrrk 3811 +VPBROADCASTBZrrkz 3812 +VPBROADCASTBrZ 3813 +VPBROADCASTBrZrr 3814 +VPBROADCASTBrZrrk 3815 +VPBROADCASTBrZrrkz 3816 +VPBROADCASTBrm 3817 +VPBROADCASTBrr 3818 +VPBROADCASTDYrm 3819 +VPBROADCASTDYrr 3820 +VPBROADCASTDZ 3821 +VPBROADCASTDZrm 3822 +VPBROADCASTDZrmk 3823 +VPBROADCASTDZrmkz 3824 +VPBROADCASTDZrr 3825 +VPBROADCASTDZrrk 3826 +VPBROADCASTDZrrkz 3827 +VPBROADCASTDrZ 3828 +VPBROADCASTDrZrr 3829 +VPBROADCASTDrZrrk 3830 +VPBROADCASTDrZrrkz 3831 +VPBROADCASTDrm 3832 +VPBROADCASTDrr 3833 +VPBROADCASTMB 3834 +VPBROADCASTMW 3835 +VPBROADCASTQYrm 3836 +VPBROADCASTQYrr 3837 +VPBROADCASTQZ 3838 +VPBROADCASTQZrm 3839 +VPBROADCASTQZrmk 3840 +VPBROADCASTQZrmkz 3841 +VPBROADCASTQZrr 3842 +VPBROADCASTQZrrk 3843 +VPBROADCASTQZrrkz 3844 +VPBROADCASTQrZ 3845 +VPBROADCASTQrZrr 3846 +VPBROADCASTQrZrrk 3847 +VPBROADCASTQrZrrkz 3848 +VPBROADCASTQrm 3849 +VPBROADCASTQrr 3850 +VPBROADCASTWYrm 3851 +VPBROADCASTWYrr 3852 +VPBROADCASTWZ 3853 +VPBROADCASTWZrm 3854 +VPBROADCASTWZrmk 3855 +VPBROADCASTWZrmkz 3856 +VPBROADCASTWZrr 3857 +VPBROADCASTWZrrk 3858 +VPBROADCASTWZrrkz 3859 +VPBROADCASTWrZ 3860 +VPBROADCASTWrZrr 3861 +VPBROADCASTWrZrrk 3862 +VPBROADCASTWrZrrkz 3863 +VPBROADCASTWrm 3864 +VPBROADCASTWrr 3865 +VPCLMULQDQYrmi 3866 +VPCLMULQDQYrri 3867 +VPCLMULQDQZ 3868 +VPCLMULQDQZrmi 3869 +VPCLMULQDQZrri 3870 +VPCLMULQDQrmi 3871 +VPCLMULQDQrri 3872 +VPCMOVYrmr 3873 +VPCMOVYrrm 3874 +VPCMOVYrrr 3875 +VPCMOVYrrr_REV 3876 +VPCMOVrmr 3877 +VPCMOVrrm 3878 +VPCMOVrrr 3879 +VPCMOVrrr_REV 3880 +VPCMPBZ 3881 +VPCMPBZrmi 3882 +VPCMPBZrmik 3883 +VPCMPBZrri 3884 +VPCMPBZrrik 3885 +VPCMPDZ 3886 +VPCMPDZrmbi 3887 +VPCMPDZrmbik 3888 +VPCMPDZrmi 3889 +VPCMPDZrmik 3890 +VPCMPDZrri 3891 +VPCMPDZrrik 3892 +VPCMPEQBYrm 3893 +VPCMPEQBYrr 3894 +VPCMPEQBZ 3895 +VPCMPEQBZrm 3896 +VPCMPEQBZrmk 3897 +VPCMPEQBZrr 3898 +VPCMPEQBZrrk 3899 +VPCMPEQBrm 3900 +VPCMPEQBrr 3901 +VPCMPEQDYrm 3902 +VPCMPEQDYrr 3903 +VPCMPEQDZ 3904 +VPCMPEQDZrm 3905 +VPCMPEQDZrmb 3906 +VPCMPEQDZrmbk 3907 +VPCMPEQDZrmk 3908 +VPCMPEQDZrr 3909 +VPCMPEQDZrrk 3910 +VPCMPEQDrm 3911 +VPCMPEQDrr 3912 +VPCMPEQQYrm 3913 +VPCMPEQQYrr 3914 +VPCMPEQQZ 3915 +VPCMPEQQZrm 3916 +VPCMPEQQZrmb 3917 +VPCMPEQQZrmbk 3918 +VPCMPEQQZrmk 3919 +VPCMPEQQZrr 3920 +VPCMPEQQZrrk 3921 +VPCMPEQQrm 3922 +VPCMPEQQrr 3923 +VPCMPEQWYrm 3924 +VPCMPEQWYrr 3925 +VPCMPEQWZ 3926 +VPCMPEQWZrm 3927 +VPCMPEQWZrmk 3928 +VPCMPEQWZrr 3929 +VPCMPEQWZrrk 3930 +VPCMPEQWrm 3931 +VPCMPEQWrr 3932 +VPCMPESTRIrmi 3933 +VPCMPESTRIrri 3934 +VPCMPESTRMrmi 3935 +VPCMPESTRMrri 3936 +VPCMPGTBYrm 3937 +VPCMPGTBYrr 3938 +VPCMPGTBZ 3939 +VPCMPGTBZrm 3940 +VPCMPGTBZrmk 3941 +VPCMPGTBZrr 3942 +VPCMPGTBZrrk 3943 +VPCMPGTBrm 3944 +VPCMPGTBrr 3945 +VPCMPGTDYrm 3946 +VPCMPGTDYrr 3947 +VPCMPGTDZ 3948 +VPCMPGTDZrm 3949 +VPCMPGTDZrmb 3950 +VPCMPGTDZrmbk 3951 +VPCMPGTDZrmk 3952 +VPCMPGTDZrr 3953 +VPCMPGTDZrrk 3954 +VPCMPGTDrm 3955 +VPCMPGTDrr 3956 +VPCMPGTQYrm 3957 +VPCMPGTQYrr 3958 +VPCMPGTQZ 3959 +VPCMPGTQZrm 3960 +VPCMPGTQZrmb 3961 +VPCMPGTQZrmbk 3962 +VPCMPGTQZrmk 3963 +VPCMPGTQZrr 3964 +VPCMPGTQZrrk 3965 +VPCMPGTQrm 3966 +VPCMPGTQrr 3967 +VPCMPGTWYrm 3968 +VPCMPGTWYrr 3969 +VPCMPGTWZ 3970 +VPCMPGTWZrm 3971 +VPCMPGTWZrmk 3972 +VPCMPGTWZrr 3973 +VPCMPGTWZrrk 3974 +VPCMPGTWrm 3975 +VPCMPGTWrr 3976 +VPCMPISTRIrmi 3977 +VPCMPISTRIrri 3978 +VPCMPISTRMrmi 3979 +VPCMPISTRMrri 3980 +VPCMPQZ 3981 +VPCMPQZrmbi 3982 +VPCMPQZrmbik 3983 +VPCMPQZrmi 3984 +VPCMPQZrmik 3985 +VPCMPQZrri 3986 +VPCMPQZrrik 3987 +VPCMPUBZ 3988 +VPCMPUBZrmi 3989 +VPCMPUBZrmik 3990 +VPCMPUBZrri 3991 +VPCMPUBZrrik 3992 +VPCMPUDZ 3993 +VPCMPUDZrmbi 3994 +VPCMPUDZrmbik 3995 +VPCMPUDZrmi 3996 +VPCMPUDZrmik 3997 +VPCMPUDZrri 3998 +VPCMPUDZrrik 3999 +VPCMPUQZ 4000 +VPCMPUQZrmbi 4001 +VPCMPUQZrmbik 4002 +VPCMPUQZrmi 4003 +VPCMPUQZrmik 4004 +VPCMPUQZrri 4005 +VPCMPUQZrrik 4006 +VPCMPUWZ 4007 +VPCMPUWZrmi 4008 +VPCMPUWZrmik 4009 +VPCMPUWZrri 4010 +VPCMPUWZrrik 4011 +VPCMPWZ 4012 +VPCMPWZrmi 4013 +VPCMPWZrmik 4014 +VPCMPWZrri 4015 +VPCMPWZrrik 4016 +VPCOMBmi 4017 +VPCOMBri 4018 +VPCOMDmi 4019 +VPCOMDri 4020 +VPCOMPRESSBZ 4021 +VPCOMPRESSBZmr 4022 +VPCOMPRESSBZmrk 4023 +VPCOMPRESSBZrr 4024 +VPCOMPRESSBZrrk 4025 +VPCOMPRESSBZrrkz 4026 +VPCOMPRESSDZ 4027 +VPCOMPRESSDZmr 4028 +VPCOMPRESSDZmrk 4029 +VPCOMPRESSDZrr 4030 +VPCOMPRESSDZrrk 4031 +VPCOMPRESSDZrrkz 4032 +VPCOMPRESSQZ 4033 +VPCOMPRESSQZmr 4034 +VPCOMPRESSQZmrk 4035 +VPCOMPRESSQZrr 4036 +VPCOMPRESSQZrrk 4037 +VPCOMPRESSQZrrkz 4038 +VPCOMPRESSWZ 4039 +VPCOMPRESSWZmr 4040 +VPCOMPRESSWZmrk 4041 +VPCOMPRESSWZrr 4042 +VPCOMPRESSWZrrk 4043 +VPCOMPRESSWZrrkz 4044 +VPCOMQmi 4045 +VPCOMQri 4046 +VPCOMUBmi 4047 +VPCOMUBri 4048 +VPCOMUDmi 4049 +VPCOMUDri 4050 +VPCOMUQmi 4051 +VPCOMUQri 4052 +VPCOMUWmi 4053 +VPCOMUWri 4054 +VPCOMWmi 4055 +VPCOMWri 4056 +VPCONFLICTDZ 4057 +VPCONFLICTDZrm 4058 +VPCONFLICTDZrmb 4059 +VPCONFLICTDZrmbk 4060 +VPCONFLICTDZrmbkz 4061 +VPCONFLICTDZrmk 4062 +VPCONFLICTDZrmkz 4063 +VPCONFLICTDZrr 4064 +VPCONFLICTDZrrk 4065 +VPCONFLICTDZrrkz 4066 +VPCONFLICTQZ 4067 +VPCONFLICTQZrm 4068 +VPCONFLICTQZrmb 4069 +VPCONFLICTQZrmbk 4070 +VPCONFLICTQZrmbkz 4071 +VPCONFLICTQZrmk 4072 +VPCONFLICTQZrmkz 4073 +VPCONFLICTQZrr 4074 +VPCONFLICTQZrrk 4075 +VPCONFLICTQZrrkz 4076 +VPDPBSSDSYrm 4077 +VPDPBSSDSYrr 4078 +VPDPBSSDSZ 4079 +VPDPBSSDSZrm 4080 +VPDPBSSDSZrmb 4081 +VPDPBSSDSZrmbk 4082 +VPDPBSSDSZrmbkz 4083 +VPDPBSSDSZrmk 4084 +VPDPBSSDSZrmkz 4085 +VPDPBSSDSZrr 4086 +VPDPBSSDSZrrk 4087 +VPDPBSSDSZrrkz 4088 +VPDPBSSDSrm 4089 +VPDPBSSDSrr 4090 +VPDPBSSDYrm 4091 +VPDPBSSDYrr 4092 +VPDPBSSDZ 4093 +VPDPBSSDZrm 4094 +VPDPBSSDZrmb 4095 +VPDPBSSDZrmbk 4096 +VPDPBSSDZrmbkz 4097 +VPDPBSSDZrmk 4098 +VPDPBSSDZrmkz 4099 +VPDPBSSDZrr 4100 +VPDPBSSDZrrk 4101 +VPDPBSSDZrrkz 4102 +VPDPBSSDrm 4103 +VPDPBSSDrr 4104 +VPDPBSUDSYrm 4105 +VPDPBSUDSYrr 4106 +VPDPBSUDSZ 4107 +VPDPBSUDSZrm 4108 +VPDPBSUDSZrmb 4109 +VPDPBSUDSZrmbk 4110 +VPDPBSUDSZrmbkz 4111 +VPDPBSUDSZrmk 4112 +VPDPBSUDSZrmkz 4113 +VPDPBSUDSZrr 4114 +VPDPBSUDSZrrk 4115 +VPDPBSUDSZrrkz 4116 +VPDPBSUDSrm 4117 +VPDPBSUDSrr 4118 +VPDPBSUDYrm 4119 +VPDPBSUDYrr 4120 +VPDPBSUDZ 4121 +VPDPBSUDZrm 4122 +VPDPBSUDZrmb 4123 +VPDPBSUDZrmbk 4124 +VPDPBSUDZrmbkz 4125 +VPDPBSUDZrmk 4126 +VPDPBSUDZrmkz 4127 +VPDPBSUDZrr 4128 +VPDPBSUDZrrk 4129 +VPDPBSUDZrrkz 4130 +VPDPBSUDrm 4131 +VPDPBSUDrr 4132 +VPDPBUSDSYrm 4133 +VPDPBUSDSYrr 4134 +VPDPBUSDSZ 4135 +VPDPBUSDSZrm 4136 +VPDPBUSDSZrmb 4137 +VPDPBUSDSZrmbk 4138 +VPDPBUSDSZrmbkz 4139 +VPDPBUSDSZrmk 4140 +VPDPBUSDSZrmkz 4141 +VPDPBUSDSZrr 4142 +VPDPBUSDSZrrk 4143 +VPDPBUSDSZrrkz 4144 +VPDPBUSDSrm 4145 +VPDPBUSDSrr 4146 +VPDPBUSDYrm 4147 +VPDPBUSDYrr 4148 +VPDPBUSDZ 4149 +VPDPBUSDZrm 4150 +VPDPBUSDZrmb 4151 +VPDPBUSDZrmbk 4152 +VPDPBUSDZrmbkz 4153 +VPDPBUSDZrmk 4154 +VPDPBUSDZrmkz 4155 +VPDPBUSDZrr 4156 +VPDPBUSDZrrk 4157 +VPDPBUSDZrrkz 4158 +VPDPBUSDrm 4159 +VPDPBUSDrr 4160 +VPDPBUUDSYrm 4161 +VPDPBUUDSYrr 4162 +VPDPBUUDSZ 4163 +VPDPBUUDSZrm 4164 +VPDPBUUDSZrmb 4165 +VPDPBUUDSZrmbk 4166 +VPDPBUUDSZrmbkz 4167 +VPDPBUUDSZrmk 4168 +VPDPBUUDSZrmkz 4169 +VPDPBUUDSZrr 4170 +VPDPBUUDSZrrk 4171 +VPDPBUUDSZrrkz 4172 +VPDPBUUDSrm 4173 +VPDPBUUDSrr 4174 +VPDPBUUDYrm 4175 +VPDPBUUDYrr 4176 +VPDPBUUDZ 4177 +VPDPBUUDZrm 4178 +VPDPBUUDZrmb 4179 +VPDPBUUDZrmbk 4180 +VPDPBUUDZrmbkz 4181 +VPDPBUUDZrmk 4182 +VPDPBUUDZrmkz 4183 +VPDPBUUDZrr 4184 +VPDPBUUDZrrk 4185 +VPDPBUUDZrrkz 4186 +VPDPBUUDrm 4187 +VPDPBUUDrr 4188 +VPDPWSSDSYrm 4189 +VPDPWSSDSYrr 4190 +VPDPWSSDSZ 4191 +VPDPWSSDSZrm 4192 +VPDPWSSDSZrmb 4193 +VPDPWSSDSZrmbk 4194 +VPDPWSSDSZrmbkz 4195 +VPDPWSSDSZrmk 4196 +VPDPWSSDSZrmkz 4197 +VPDPWSSDSZrr 4198 +VPDPWSSDSZrrk 4199 +VPDPWSSDSZrrkz 4200 +VPDPWSSDSrm 4201 +VPDPWSSDSrr 4202 +VPDPWSSDYrm 4203 +VPDPWSSDYrr 4204 +VPDPWSSDZ 4205 +VPDPWSSDZrm 4206 +VPDPWSSDZrmb 4207 +VPDPWSSDZrmbk 4208 +VPDPWSSDZrmbkz 4209 +VPDPWSSDZrmk 4210 +VPDPWSSDZrmkz 4211 +VPDPWSSDZrr 4212 +VPDPWSSDZrrk 4213 +VPDPWSSDZrrkz 4214 +VPDPWSSDrm 4215 +VPDPWSSDrr 4216 +VPDPWSUDSYrm 4217 +VPDPWSUDSYrr 4218 +VPDPWSUDSZ 4219 +VPDPWSUDSZrm 4220 +VPDPWSUDSZrmb 4221 +VPDPWSUDSZrmbk 4222 +VPDPWSUDSZrmbkz 4223 +VPDPWSUDSZrmk 4224 +VPDPWSUDSZrmkz 4225 +VPDPWSUDSZrr 4226 +VPDPWSUDSZrrk 4227 +VPDPWSUDSZrrkz 4228 +VPDPWSUDSrm 4229 +VPDPWSUDSrr 4230 +VPDPWSUDYrm 4231 +VPDPWSUDYrr 4232 +VPDPWSUDZ 4233 +VPDPWSUDZrm 4234 +VPDPWSUDZrmb 4235 +VPDPWSUDZrmbk 4236 +VPDPWSUDZrmbkz 4237 +VPDPWSUDZrmk 4238 +VPDPWSUDZrmkz 4239 +VPDPWSUDZrr 4240 +VPDPWSUDZrrk 4241 +VPDPWSUDZrrkz 4242 +VPDPWSUDrm 4243 +VPDPWSUDrr 4244 +VPDPWUSDSYrm 4245 +VPDPWUSDSYrr 4246 +VPDPWUSDSZ 4247 +VPDPWUSDSZrm 4248 +VPDPWUSDSZrmb 4249 +VPDPWUSDSZrmbk 4250 +VPDPWUSDSZrmbkz 4251 +VPDPWUSDSZrmk 4252 +VPDPWUSDSZrmkz 4253 +VPDPWUSDSZrr 4254 +VPDPWUSDSZrrk 4255 +VPDPWUSDSZrrkz 4256 +VPDPWUSDSrm 4257 +VPDPWUSDSrr 4258 +VPDPWUSDYrm 4259 +VPDPWUSDYrr 4260 +VPDPWUSDZ 4261 +VPDPWUSDZrm 4262 +VPDPWUSDZrmb 4263 +VPDPWUSDZrmbk 4264 +VPDPWUSDZrmbkz 4265 +VPDPWUSDZrmk 4266 +VPDPWUSDZrmkz 4267 +VPDPWUSDZrr 4268 +VPDPWUSDZrrk 4269 +VPDPWUSDZrrkz 4270 +VPDPWUSDrm 4271 +VPDPWUSDrr 4272 +VPDPWUUDSYrm 4273 +VPDPWUUDSYrr 4274 +VPDPWUUDSZ 4275 +VPDPWUUDSZrm 4276 +VPDPWUUDSZrmb 4277 +VPDPWUUDSZrmbk 4278 +VPDPWUUDSZrmbkz 4279 +VPDPWUUDSZrmk 4280 +VPDPWUUDSZrmkz 4281 +VPDPWUUDSZrr 4282 +VPDPWUUDSZrrk 4283 +VPDPWUUDSZrrkz 4284 +VPDPWUUDSrm 4285 +VPDPWUUDSrr 4286 +VPDPWUUDYrm 4287 +VPDPWUUDYrr 4288 +VPDPWUUDZ 4289 +VPDPWUUDZrm 4290 +VPDPWUUDZrmb 4291 +VPDPWUUDZrmbk 4292 +VPDPWUUDZrmbkz 4293 +VPDPWUUDZrmk 4294 +VPDPWUUDZrmkz 4295 +VPDPWUUDZrr 4296 +VPDPWUUDZrrk 4297 +VPDPWUUDZrrkz 4298 +VPDPWUUDrm 4299 +VPDPWUUDrr 4300 +VPERM 4301 +VPERMBZ 4302 +VPERMBZrm 4303 +VPERMBZrmk 4304 +VPERMBZrmkz 4305 +VPERMBZrr 4306 +VPERMBZrrk 4307 +VPERMBZrrkz 4308 +VPERMDYrm 4309 +VPERMDYrr 4310 +VPERMDZ 4311 +VPERMDZrm 4312 +VPERMDZrmb 4313 +VPERMDZrmbk 4314 +VPERMDZrmbkz 4315 +VPERMDZrmk 4316 +VPERMDZrmkz 4317 +VPERMDZrr 4318 +VPERMDZrrk 4319 +VPERMDZrrkz 4320 +VPERMI 4321 +VPERMIL 4322 +VPERMILPDYmi 4323 +VPERMILPDYri 4324 +VPERMILPDYrm 4325 +VPERMILPDYrr 4326 +VPERMILPDZ 4327 +VPERMILPDZmbi 4328 +VPERMILPDZmbik 4329 +VPERMILPDZmbikz 4330 +VPERMILPDZmi 4331 +VPERMILPDZmik 4332 +VPERMILPDZmikz 4333 +VPERMILPDZri 4334 +VPERMILPDZrik 4335 +VPERMILPDZrikz 4336 +VPERMILPDZrm 4337 +VPERMILPDZrmb 4338 +VPERMILPDZrmbk 4339 +VPERMILPDZrmbkz 4340 +VPERMILPDZrmk 4341 +VPERMILPDZrmkz 4342 +VPERMILPDZrr 4343 +VPERMILPDZrrk 4344 +VPERMILPDZrrkz 4345 +VPERMILPDmi 4346 +VPERMILPDri 4347 +VPERMILPDrm 4348 +VPERMILPDrr 4349 +VPERMILPSYmi 4350 +VPERMILPSYri 4351 +VPERMILPSYrm 4352 +VPERMILPSYrr 4353 +VPERMILPSZ 4354 +VPERMILPSZmbi 4355 +VPERMILPSZmbik 4356 +VPERMILPSZmbikz 4357 +VPERMILPSZmi 4358 +VPERMILPSZmik 4359 +VPERMILPSZmikz 4360 +VPERMILPSZri 4361 +VPERMILPSZrik 4362 +VPERMILPSZrikz 4363 +VPERMILPSZrm 4364 +VPERMILPSZrmb 4365 +VPERMILPSZrmbk 4366 +VPERMILPSZrmbkz 4367 +VPERMILPSZrmk 4368 +VPERMILPSZrmkz 4369 +VPERMILPSZrr 4370 +VPERMILPSZrrk 4371 +VPERMILPSZrrkz 4372 +VPERMILPSmi 4373 +VPERMILPSri 4374 +VPERMILPSrm 4375 +VPERMILPSrr 4376 +VPERMPDYmi 4377 +VPERMPDYri 4378 +VPERMPDZ 4379 +VPERMPDZmbi 4380 +VPERMPDZmbik 4381 +VPERMPDZmbikz 4382 +VPERMPDZmi 4383 +VPERMPDZmik 4384 +VPERMPDZmikz 4385 +VPERMPDZri 4386 +VPERMPDZrik 4387 +VPERMPDZrikz 4388 +VPERMPDZrm 4389 +VPERMPDZrmb 4390 +VPERMPDZrmbk 4391 +VPERMPDZrmbkz 4392 +VPERMPDZrmk 4393 +VPERMPDZrmkz 4394 +VPERMPDZrr 4395 +VPERMPDZrrk 4396 +VPERMPDZrrkz 4397 +VPERMPSYrm 4398 +VPERMPSYrr 4399 +VPERMPSZ 4400 +VPERMPSZrm 4401 +VPERMPSZrmb 4402 +VPERMPSZrmbk 4403 +VPERMPSZrmbkz 4404 +VPERMPSZrmk 4405 +VPERMPSZrmkz 4406 +VPERMPSZrr 4407 +VPERMPSZrrk 4408 +VPERMPSZrrkz 4409 +VPERMQYmi 4410 +VPERMQYri 4411 +VPERMQZ 4412 +VPERMQZmbi 4413 +VPERMQZmbik 4414 +VPERMQZmbikz 4415 +VPERMQZmi 4416 +VPERMQZmik 4417 +VPERMQZmikz 4418 +VPERMQZri 4419 +VPERMQZrik 4420 +VPERMQZrikz 4421 +VPERMQZrm 4422 +VPERMQZrmb 4423 +VPERMQZrmbk 4424 +VPERMQZrmbkz 4425 +VPERMQZrmk 4426 +VPERMQZrmkz 4427 +VPERMQZrr 4428 +VPERMQZrrk 4429 +VPERMQZrrkz 4430 +VPERMT 4431 +VPERMWZ 4432 +VPERMWZrm 4433 +VPERMWZrmk 4434 +VPERMWZrmkz 4435 +VPERMWZrr 4436 +VPERMWZrrk 4437 +VPERMWZrrkz 4438 +VPEXPANDBZ 4439 +VPEXPANDBZrm 4440 +VPEXPANDBZrmk 4441 +VPEXPANDBZrmkz 4442 +VPEXPANDBZrr 4443 +VPEXPANDBZrrk 4444 +VPEXPANDBZrrkz 4445 +VPEXPANDDZ 4446 +VPEXPANDDZrm 4447 +VPEXPANDDZrmk 4448 +VPEXPANDDZrmkz 4449 +VPEXPANDDZrr 4450 +VPEXPANDDZrrk 4451 +VPEXPANDDZrrkz 4452 +VPEXPANDQZ 4453 +VPEXPANDQZrm 4454 +VPEXPANDQZrmk 4455 +VPEXPANDQZrmkz 4456 +VPEXPANDQZrr 4457 +VPEXPANDQZrrk 4458 +VPEXPANDQZrrkz 4459 +VPEXPANDWZ 4460 +VPEXPANDWZrm 4461 +VPEXPANDWZrmk 4462 +VPEXPANDWZrmkz 4463 +VPEXPANDWZrr 4464 +VPEXPANDWZrrk 4465 +VPEXPANDWZrrkz 4466 +VPEXTRBZmri 4467 +VPEXTRBZrri 4468 +VPEXTRBmri 4469 +VPEXTRBrri 4470 +VPEXTRDZmri 4471 +VPEXTRDZrri 4472 +VPEXTRDmri 4473 +VPEXTRDrri 4474 +VPEXTRQZmri 4475 +VPEXTRQZrri 4476 +VPEXTRQmri 4477 +VPEXTRQrri 4478 +VPEXTRWZmri 4479 +VPEXTRWZrri 4480 +VPEXTRWZrri_REV 4481 +VPEXTRWmri 4482 +VPEXTRWrri 4483 +VPEXTRWrri_REV 4484 +VPGATHERDDYrm 4485 +VPGATHERDDZ 4486 +VPGATHERDDZrm 4487 +VPGATHERDDrm 4488 +VPGATHERDQYrm 4489 +VPGATHERDQZ 4490 +VPGATHERDQZrm 4491 +VPGATHERDQrm 4492 +VPGATHERQDYrm 4493 +VPGATHERQDZ 4494 +VPGATHERQDZrm 4495 +VPGATHERQDrm 4496 +VPGATHERQQYrm 4497 +VPGATHERQQZ 4498 +VPGATHERQQZrm 4499 +VPGATHERQQrm 4500 +VPHADDBDrm 4501 +VPHADDBDrr 4502 +VPHADDBQrm 4503 +VPHADDBQrr 4504 +VPHADDBWrm 4505 +VPHADDBWrr 4506 +VPHADDDQrm 4507 +VPHADDDQrr 4508 +VPHADDDYrm 4509 +VPHADDDYrr 4510 +VPHADDDrm 4511 +VPHADDDrr 4512 +VPHADDSWYrm 4513 +VPHADDSWYrr 4514 +VPHADDSWrm 4515 +VPHADDSWrr 4516 +VPHADDUBDrm 4517 +VPHADDUBDrr 4518 +VPHADDUBQrm 4519 +VPHADDUBQrr 4520 +VPHADDUBWrm 4521 +VPHADDUBWrr 4522 +VPHADDUDQrm 4523 +VPHADDUDQrr 4524 +VPHADDUWDrm 4525 +VPHADDUWDrr 4526 +VPHADDUWQrm 4527 +VPHADDUWQrr 4528 +VPHADDWDrm 4529 +VPHADDWDrr 4530 +VPHADDWQrm 4531 +VPHADDWQrr 4532 +VPHADDWYrm 4533 +VPHADDWYrr 4534 +VPHADDWrm 4535 +VPHADDWrr 4536 +VPHMINPOSUWrm 4537 +VPHMINPOSUWrr 4538 +VPHSUBBWrm 4539 +VPHSUBBWrr 4540 +VPHSUBDQrm 4541 +VPHSUBDQrr 4542 +VPHSUBDYrm 4543 +VPHSUBDYrr 4544 +VPHSUBDrm 4545 +VPHSUBDrr 4546 +VPHSUBSWYrm 4547 +VPHSUBSWYrr 4548 +VPHSUBSWrm 4549 +VPHSUBSWrr 4550 +VPHSUBWDrm 4551 +VPHSUBWDrr 4552 +VPHSUBWYrm 4553 +VPHSUBWYrr 4554 +VPHSUBWrm 4555 +VPHSUBWrr 4556 +VPINSRBZrmi 4557 +VPINSRBZrri 4558 +VPINSRBrmi 4559 +VPINSRBrri 4560 +VPINSRDZrmi 4561 +VPINSRDZrri 4562 +VPINSRDrmi 4563 +VPINSRDrri 4564 +VPINSRQZrmi 4565 +VPINSRQZrri 4566 +VPINSRQrmi 4567 +VPINSRQrri 4568 +VPINSRWZrmi 4569 +VPINSRWZrri 4570 +VPINSRWrmi 4571 +VPINSRWrri 4572 +VPLZCNTDZ 4573 +VPLZCNTDZrm 4574 +VPLZCNTDZrmb 4575 +VPLZCNTDZrmbk 4576 +VPLZCNTDZrmbkz 4577 +VPLZCNTDZrmk 4578 +VPLZCNTDZrmkz 4579 +VPLZCNTDZrr 4580 +VPLZCNTDZrrk 4581 +VPLZCNTDZrrkz 4582 +VPLZCNTQZ 4583 +VPLZCNTQZrm 4584 +VPLZCNTQZrmb 4585 +VPLZCNTQZrmbk 4586 +VPLZCNTQZrmbkz 4587 +VPLZCNTQZrmk 4588 +VPLZCNTQZrmkz 4589 +VPLZCNTQZrr 4590 +VPLZCNTQZrrk 4591 +VPLZCNTQZrrkz 4592 +VPMACSDDrm 4593 +VPMACSDDrr 4594 +VPMACSDQHrm 4595 +VPMACSDQHrr 4596 +VPMACSDQLrm 4597 +VPMACSDQLrr 4598 +VPMACSSDDrm 4599 +VPMACSSDDrr 4600 +VPMACSSDQHrm 4601 +VPMACSSDQHrr 4602 +VPMACSSDQLrm 4603 +VPMACSSDQLrr 4604 +VPMACSSWDrm 4605 +VPMACSSWDrr 4606 +VPMACSSWWrm 4607 +VPMACSSWWrr 4608 +VPMACSWDrm 4609 +VPMACSWDrr 4610 +VPMACSWWrm 4611 +VPMACSWWrr 4612 +VPMADCSSWDrm 4613 +VPMADCSSWDrr 4614 +VPMADCSWDrm 4615 +VPMADCSWDrr 4616 +VPMADD 4617 +VPMADDUBSWYrm 4618 +VPMADDUBSWYrr 4619 +VPMADDUBSWZ 4620 +VPMADDUBSWZrm 4621 +VPMADDUBSWZrmk 4622 +VPMADDUBSWZrmkz 4623 +VPMADDUBSWZrr 4624 +VPMADDUBSWZrrk 4625 +VPMADDUBSWZrrkz 4626 +VPMADDUBSWrm 4627 +VPMADDUBSWrr 4628 +VPMADDWDYrm 4629 +VPMADDWDYrr 4630 +VPMADDWDZ 4631 +VPMADDWDZrm 4632 +VPMADDWDZrmk 4633 +VPMADDWDZrmkz 4634 +VPMADDWDZrr 4635 +VPMADDWDZrrk 4636 +VPMADDWDZrrkz 4637 +VPMADDWDrm 4638 +VPMADDWDrr 4639 +VPMASKMOVDYmr 4640 +VPMASKMOVDYrm 4641 +VPMASKMOVDmr 4642 +VPMASKMOVDrm 4643 +VPMASKMOVQYmr 4644 +VPMASKMOVQYrm 4645 +VPMASKMOVQmr 4646 +VPMASKMOVQrm 4647 +VPMAXSBYrm 4648 +VPMAXSBYrr 4649 +VPMAXSBZ 4650 +VPMAXSBZrm 4651 +VPMAXSBZrmk 4652 +VPMAXSBZrmkz 4653 +VPMAXSBZrr 4654 +VPMAXSBZrrk 4655 +VPMAXSBZrrkz 4656 +VPMAXSBrm 4657 +VPMAXSBrr 4658 +VPMAXSDYrm 4659 +VPMAXSDYrr 4660 +VPMAXSDZ 4661 +VPMAXSDZrm 4662 +VPMAXSDZrmb 4663 +VPMAXSDZrmbk 4664 +VPMAXSDZrmbkz 4665 +VPMAXSDZrmk 4666 +VPMAXSDZrmkz 4667 +VPMAXSDZrr 4668 +VPMAXSDZrrk 4669 +VPMAXSDZrrkz 4670 +VPMAXSDrm 4671 +VPMAXSDrr 4672 +VPMAXSQZ 4673 +VPMAXSQZrm 4674 +VPMAXSQZrmb 4675 +VPMAXSQZrmbk 4676 +VPMAXSQZrmbkz 4677 +VPMAXSQZrmk 4678 +VPMAXSQZrmkz 4679 +VPMAXSQZrr 4680 +VPMAXSQZrrk 4681 +VPMAXSQZrrkz 4682 +VPMAXSWYrm 4683 +VPMAXSWYrr 4684 +VPMAXSWZ 4685 +VPMAXSWZrm 4686 +VPMAXSWZrmk 4687 +VPMAXSWZrmkz 4688 +VPMAXSWZrr 4689 +VPMAXSWZrrk 4690 +VPMAXSWZrrkz 4691 +VPMAXSWrm 4692 +VPMAXSWrr 4693 +VPMAXUBYrm 4694 +VPMAXUBYrr 4695 +VPMAXUBZ 4696 +VPMAXUBZrm 4697 +VPMAXUBZrmk 4698 +VPMAXUBZrmkz 4699 +VPMAXUBZrr 4700 +VPMAXUBZrrk 4701 +VPMAXUBZrrkz 4702 +VPMAXUBrm 4703 +VPMAXUBrr 4704 +VPMAXUDYrm 4705 +VPMAXUDYrr 4706 +VPMAXUDZ 4707 +VPMAXUDZrm 4708 +VPMAXUDZrmb 4709 +VPMAXUDZrmbk 4710 +VPMAXUDZrmbkz 4711 +VPMAXUDZrmk 4712 +VPMAXUDZrmkz 4713 +VPMAXUDZrr 4714 +VPMAXUDZrrk 4715 +VPMAXUDZrrkz 4716 +VPMAXUDrm 4717 +VPMAXUDrr 4718 +VPMAXUQZ 4719 +VPMAXUQZrm 4720 +VPMAXUQZrmb 4721 +VPMAXUQZrmbk 4722 +VPMAXUQZrmbkz 4723 +VPMAXUQZrmk 4724 +VPMAXUQZrmkz 4725 +VPMAXUQZrr 4726 +VPMAXUQZrrk 4727 +VPMAXUQZrrkz 4728 +VPMAXUWYrm 4729 +VPMAXUWYrr 4730 +VPMAXUWZ 4731 +VPMAXUWZrm 4732 +VPMAXUWZrmk 4733 +VPMAXUWZrmkz 4734 +VPMAXUWZrr 4735 +VPMAXUWZrrk 4736 +VPMAXUWZrrkz 4737 +VPMAXUWrm 4738 +VPMAXUWrr 4739 +VPMINSBYrm 4740 +VPMINSBYrr 4741 +VPMINSBZ 4742 +VPMINSBZrm 4743 +VPMINSBZrmk 4744 +VPMINSBZrmkz 4745 +VPMINSBZrr 4746 +VPMINSBZrrk 4747 +VPMINSBZrrkz 4748 +VPMINSBrm 4749 +VPMINSBrr 4750 +VPMINSDYrm 4751 +VPMINSDYrr 4752 +VPMINSDZ 4753 +VPMINSDZrm 4754 +VPMINSDZrmb 4755 +VPMINSDZrmbk 4756 +VPMINSDZrmbkz 4757 +VPMINSDZrmk 4758 +VPMINSDZrmkz 4759 +VPMINSDZrr 4760 +VPMINSDZrrk 4761 +VPMINSDZrrkz 4762 +VPMINSDrm 4763 +VPMINSDrr 4764 +VPMINSQZ 4765 +VPMINSQZrm 4766 +VPMINSQZrmb 4767 +VPMINSQZrmbk 4768 +VPMINSQZrmbkz 4769 +VPMINSQZrmk 4770 +VPMINSQZrmkz 4771 +VPMINSQZrr 4772 +VPMINSQZrrk 4773 +VPMINSQZrrkz 4774 +VPMINSWYrm 4775 +VPMINSWYrr 4776 +VPMINSWZ 4777 +VPMINSWZrm 4778 +VPMINSWZrmk 4779 +VPMINSWZrmkz 4780 +VPMINSWZrr 4781 +VPMINSWZrrk 4782 +VPMINSWZrrkz 4783 +VPMINSWrm 4784 +VPMINSWrr 4785 +VPMINUBYrm 4786 +VPMINUBYrr 4787 +VPMINUBZ 4788 +VPMINUBZrm 4789 +VPMINUBZrmk 4790 +VPMINUBZrmkz 4791 +VPMINUBZrr 4792 +VPMINUBZrrk 4793 +VPMINUBZrrkz 4794 +VPMINUBrm 4795 +VPMINUBrr 4796 +VPMINUDYrm 4797 +VPMINUDYrr 4798 +VPMINUDZ 4799 +VPMINUDZrm 4800 +VPMINUDZrmb 4801 +VPMINUDZrmbk 4802 +VPMINUDZrmbkz 4803 +VPMINUDZrmk 4804 +VPMINUDZrmkz 4805 +VPMINUDZrr 4806 +VPMINUDZrrk 4807 +VPMINUDZrrkz 4808 +VPMINUDrm 4809 +VPMINUDrr 4810 +VPMINUQZ 4811 +VPMINUQZrm 4812 +VPMINUQZrmb 4813 +VPMINUQZrmbk 4814 +VPMINUQZrmbkz 4815 +VPMINUQZrmk 4816 +VPMINUQZrmkz 4817 +VPMINUQZrr 4818 +VPMINUQZrrk 4819 +VPMINUQZrrkz 4820 +VPMINUWYrm 4821 +VPMINUWYrr 4822 +VPMINUWZ 4823 +VPMINUWZrm 4824 +VPMINUWZrmk 4825 +VPMINUWZrmkz 4826 +VPMINUWZrr 4827 +VPMINUWZrrk 4828 +VPMINUWZrrkz 4829 +VPMINUWrm 4830 +VPMINUWrr 4831 +VPMOVB 4832 +VPMOVD 4833 +VPMOVDBZ 4834 +VPMOVDBZmr 4835 +VPMOVDBZmrk 4836 +VPMOVDBZrr 4837 +VPMOVDBZrrk 4838 +VPMOVDBZrrkz 4839 +VPMOVDWZ 4840 +VPMOVDWZmr 4841 +VPMOVDWZmrk 4842 +VPMOVDWZrr 4843 +VPMOVDWZrrk 4844 +VPMOVDWZrrkz 4845 +VPMOVM 4846 +VPMOVMSKBYrr 4847 +VPMOVMSKBrr 4848 +VPMOVQ 4849 +VPMOVQBZ 4850 +VPMOVQBZmr 4851 +VPMOVQBZmrk 4852 +VPMOVQBZrr 4853 +VPMOVQBZrrk 4854 +VPMOVQBZrrkz 4855 +VPMOVQDZ 4856 +VPMOVQDZmr 4857 +VPMOVQDZmrk 4858 +VPMOVQDZrr 4859 +VPMOVQDZrrk 4860 +VPMOVQDZrrkz 4861 +VPMOVQWZ 4862 +VPMOVQWZmr 4863 +VPMOVQWZmrk 4864 +VPMOVQWZrr 4865 +VPMOVQWZrrk 4866 +VPMOVQWZrrkz 4867 +VPMOVSDBZ 4868 +VPMOVSDBZmr 4869 +VPMOVSDBZmrk 4870 +VPMOVSDBZrr 4871 +VPMOVSDBZrrk 4872 +VPMOVSDBZrrkz 4873 +VPMOVSDWZ 4874 +VPMOVSDWZmr 4875 +VPMOVSDWZmrk 4876 +VPMOVSDWZrr 4877 +VPMOVSDWZrrk 4878 +VPMOVSDWZrrkz 4879 +VPMOVSQBZ 4880 +VPMOVSQBZmr 4881 +VPMOVSQBZmrk 4882 +VPMOVSQBZrr 4883 +VPMOVSQBZrrk 4884 +VPMOVSQBZrrkz 4885 +VPMOVSQDZ 4886 +VPMOVSQDZmr 4887 +VPMOVSQDZmrk 4888 +VPMOVSQDZrr 4889 +VPMOVSQDZrrk 4890 +VPMOVSQDZrrkz 4891 +VPMOVSQWZ 4892 +VPMOVSQWZmr 4893 +VPMOVSQWZmrk 4894 +VPMOVSQWZrr 4895 +VPMOVSQWZrrk 4896 +VPMOVSQWZrrkz 4897 +VPMOVSWBZ 4898 +VPMOVSWBZmr 4899 +VPMOVSWBZmrk 4900 +VPMOVSWBZrr 4901 +VPMOVSWBZrrk 4902 +VPMOVSWBZrrkz 4903 +VPMOVSXBDYrm 4904 +VPMOVSXBDYrr 4905 +VPMOVSXBDZ 4906 +VPMOVSXBDZrm 4907 +VPMOVSXBDZrmk 4908 +VPMOVSXBDZrmkz 4909 +VPMOVSXBDZrr 4910 +VPMOVSXBDZrrk 4911 +VPMOVSXBDZrrkz 4912 +VPMOVSXBDrm 4913 +VPMOVSXBDrr 4914 +VPMOVSXBQYrm 4915 +VPMOVSXBQYrr 4916 +VPMOVSXBQZ 4917 +VPMOVSXBQZrm 4918 +VPMOVSXBQZrmk 4919 +VPMOVSXBQZrmkz 4920 +VPMOVSXBQZrr 4921 +VPMOVSXBQZrrk 4922 +VPMOVSXBQZrrkz 4923 +VPMOVSXBQrm 4924 +VPMOVSXBQrr 4925 +VPMOVSXBWYrm 4926 +VPMOVSXBWYrr 4927 +VPMOVSXBWZ 4928 +VPMOVSXBWZrm 4929 +VPMOVSXBWZrmk 4930 +VPMOVSXBWZrmkz 4931 +VPMOVSXBWZrr 4932 +VPMOVSXBWZrrk 4933 +VPMOVSXBWZrrkz 4934 +VPMOVSXBWrm 4935 +VPMOVSXBWrr 4936 +VPMOVSXDQYrm 4937 +VPMOVSXDQYrr 4938 +VPMOVSXDQZ 4939 +VPMOVSXDQZrm 4940 +VPMOVSXDQZrmk 4941 +VPMOVSXDQZrmkz 4942 +VPMOVSXDQZrr 4943 +VPMOVSXDQZrrk 4944 +VPMOVSXDQZrrkz 4945 +VPMOVSXDQrm 4946 +VPMOVSXDQrr 4947 +VPMOVSXWDYrm 4948 +VPMOVSXWDYrr 4949 +VPMOVSXWDZ 4950 +VPMOVSXWDZrm 4951 +VPMOVSXWDZrmk 4952 +VPMOVSXWDZrmkz 4953 +VPMOVSXWDZrr 4954 +VPMOVSXWDZrrk 4955 +VPMOVSXWDZrrkz 4956 +VPMOVSXWDrm 4957 +VPMOVSXWDrr 4958 +VPMOVSXWQYrm 4959 +VPMOVSXWQYrr 4960 +VPMOVSXWQZ 4961 +VPMOVSXWQZrm 4962 +VPMOVSXWQZrmk 4963 +VPMOVSXWQZrmkz 4964 +VPMOVSXWQZrr 4965 +VPMOVSXWQZrrk 4966 +VPMOVSXWQZrrkz 4967 +VPMOVSXWQrm 4968 +VPMOVSXWQrr 4969 +VPMOVUSDBZ 4970 +VPMOVUSDBZmr 4971 +VPMOVUSDBZmrk 4972 +VPMOVUSDBZrr 4973 +VPMOVUSDBZrrk 4974 +VPMOVUSDBZrrkz 4975 +VPMOVUSDWZ 4976 +VPMOVUSDWZmr 4977 +VPMOVUSDWZmrk 4978 +VPMOVUSDWZrr 4979 +VPMOVUSDWZrrk 4980 +VPMOVUSDWZrrkz 4981 +VPMOVUSQBZ 4982 +VPMOVUSQBZmr 4983 +VPMOVUSQBZmrk 4984 +VPMOVUSQBZrr 4985 +VPMOVUSQBZrrk 4986 +VPMOVUSQBZrrkz 4987 +VPMOVUSQDZ 4988 +VPMOVUSQDZmr 4989 +VPMOVUSQDZmrk 4990 +VPMOVUSQDZrr 4991 +VPMOVUSQDZrrk 4992 +VPMOVUSQDZrrkz 4993 +VPMOVUSQWZ 4994 +VPMOVUSQWZmr 4995 +VPMOVUSQWZmrk 4996 +VPMOVUSQWZrr 4997 +VPMOVUSQWZrrk 4998 +VPMOVUSQWZrrkz 4999 +VPMOVUSWBZ 5000 +VPMOVUSWBZmr 5001 +VPMOVUSWBZmrk 5002 +VPMOVUSWBZrr 5003 +VPMOVUSWBZrrk 5004 +VPMOVUSWBZrrkz 5005 +VPMOVW 5006 +VPMOVWBZ 5007 +VPMOVWBZmr 5008 +VPMOVWBZmrk 5009 +VPMOVWBZrr 5010 +VPMOVWBZrrk 5011 +VPMOVWBZrrkz 5012 +VPMOVZXBDYrm 5013 +VPMOVZXBDYrr 5014 +VPMOVZXBDZ 5015 +VPMOVZXBDZrm 5016 +VPMOVZXBDZrmk 5017 +VPMOVZXBDZrmkz 5018 +VPMOVZXBDZrr 5019 +VPMOVZXBDZrrk 5020 +VPMOVZXBDZrrkz 5021 +VPMOVZXBDrm 5022 +VPMOVZXBDrr 5023 +VPMOVZXBQYrm 5024 +VPMOVZXBQYrr 5025 +VPMOVZXBQZ 5026 +VPMOVZXBQZrm 5027 +VPMOVZXBQZrmk 5028 +VPMOVZXBQZrmkz 5029 +VPMOVZXBQZrr 5030 +VPMOVZXBQZrrk 5031 +VPMOVZXBQZrrkz 5032 +VPMOVZXBQrm 5033 +VPMOVZXBQrr 5034 +VPMOVZXBWYrm 5035 +VPMOVZXBWYrr 5036 +VPMOVZXBWZ 5037 +VPMOVZXBWZrm 5038 +VPMOVZXBWZrmk 5039 +VPMOVZXBWZrmkz 5040 +VPMOVZXBWZrr 5041 +VPMOVZXBWZrrk 5042 +VPMOVZXBWZrrkz 5043 +VPMOVZXBWrm 5044 +VPMOVZXBWrr 5045 +VPMOVZXDQYrm 5046 +VPMOVZXDQYrr 5047 +VPMOVZXDQZ 5048 +VPMOVZXDQZrm 5049 +VPMOVZXDQZrmk 5050 +VPMOVZXDQZrmkz 5051 +VPMOVZXDQZrr 5052 +VPMOVZXDQZrrk 5053 +VPMOVZXDQZrrkz 5054 +VPMOVZXDQrm 5055 +VPMOVZXDQrr 5056 +VPMOVZXWDYrm 5057 +VPMOVZXWDYrr 5058 +VPMOVZXWDZ 5059 +VPMOVZXWDZrm 5060 +VPMOVZXWDZrmk 5061 +VPMOVZXWDZrmkz 5062 +VPMOVZXWDZrr 5063 +VPMOVZXWDZrrk 5064 +VPMOVZXWDZrrkz 5065 +VPMOVZXWDrm 5066 +VPMOVZXWDrr 5067 +VPMOVZXWQYrm 5068 +VPMOVZXWQYrr 5069 +VPMOVZXWQZ 5070 +VPMOVZXWQZrm 5071 +VPMOVZXWQZrmk 5072 +VPMOVZXWQZrmkz 5073 +VPMOVZXWQZrr 5074 +VPMOVZXWQZrrk 5075 +VPMOVZXWQZrrkz 5076 +VPMOVZXWQrm 5077 +VPMOVZXWQrr 5078 +VPMULDQYrm 5079 +VPMULDQYrr 5080 +VPMULDQZ 5081 +VPMULDQZrm 5082 +VPMULDQZrmb 5083 +VPMULDQZrmbk 5084 +VPMULDQZrmbkz 5085 +VPMULDQZrmk 5086 +VPMULDQZrmkz 5087 +VPMULDQZrr 5088 +VPMULDQZrrk 5089 +VPMULDQZrrkz 5090 +VPMULDQrm 5091 +VPMULDQrr 5092 +VPMULHRSWYrm 5093 +VPMULHRSWYrr 5094 +VPMULHRSWZ 5095 +VPMULHRSWZrm 5096 +VPMULHRSWZrmk 5097 +VPMULHRSWZrmkz 5098 +VPMULHRSWZrr 5099 +VPMULHRSWZrrk 5100 +VPMULHRSWZrrkz 5101 +VPMULHRSWrm 5102 +VPMULHRSWrr 5103 +VPMULHUWYrm 5104 +VPMULHUWYrr 5105 +VPMULHUWZ 5106 +VPMULHUWZrm 5107 +VPMULHUWZrmk 5108 +VPMULHUWZrmkz 5109 +VPMULHUWZrr 5110 +VPMULHUWZrrk 5111 +VPMULHUWZrrkz 5112 +VPMULHUWrm 5113 +VPMULHUWrr 5114 +VPMULHWYrm 5115 +VPMULHWYrr 5116 +VPMULHWZ 5117 +VPMULHWZrm 5118 +VPMULHWZrmk 5119 +VPMULHWZrmkz 5120 +VPMULHWZrr 5121 +VPMULHWZrrk 5122 +VPMULHWZrrkz 5123 +VPMULHWrm 5124 +VPMULHWrr 5125 +VPMULLDYrm 5126 +VPMULLDYrr 5127 +VPMULLDZ 5128 +VPMULLDZrm 5129 +VPMULLDZrmb 5130 +VPMULLDZrmbk 5131 +VPMULLDZrmbkz 5132 +VPMULLDZrmk 5133 +VPMULLDZrmkz 5134 +VPMULLDZrr 5135 +VPMULLDZrrk 5136 +VPMULLDZrrkz 5137 +VPMULLDrm 5138 +VPMULLDrr 5139 +VPMULLQZ 5140 +VPMULLQZrm 5141 +VPMULLQZrmb 5142 +VPMULLQZrmbk 5143 +VPMULLQZrmbkz 5144 +VPMULLQZrmk 5145 +VPMULLQZrmkz 5146 +VPMULLQZrr 5147 +VPMULLQZrrk 5148 +VPMULLQZrrkz 5149 +VPMULLWYrm 5150 +VPMULLWYrr 5151 +VPMULLWZ 5152 +VPMULLWZrm 5153 +VPMULLWZrmk 5154 +VPMULLWZrmkz 5155 +VPMULLWZrr 5156 +VPMULLWZrrk 5157 +VPMULLWZrrkz 5158 +VPMULLWrm 5159 +VPMULLWrr 5160 +VPMULTISHIFTQBZ 5161 +VPMULTISHIFTQBZrm 5162 +VPMULTISHIFTQBZrmb 5163 +VPMULTISHIFTQBZrmbk 5164 +VPMULTISHIFTQBZrmbkz 5165 +VPMULTISHIFTQBZrmk 5166 +VPMULTISHIFTQBZrmkz 5167 +VPMULTISHIFTQBZrr 5168 +VPMULTISHIFTQBZrrk 5169 +VPMULTISHIFTQBZrrkz 5170 +VPMULUDQYrm 5171 +VPMULUDQYrr 5172 +VPMULUDQZ 5173 +VPMULUDQZrm 5174 +VPMULUDQZrmb 5175 +VPMULUDQZrmbk 5176 +VPMULUDQZrmbkz 5177 +VPMULUDQZrmk 5178 +VPMULUDQZrmkz 5179 +VPMULUDQZrr 5180 +VPMULUDQZrrk 5181 +VPMULUDQZrrkz 5182 +VPMULUDQrm 5183 +VPMULUDQrr 5184 +VPOPCNTBZ 5185 +VPOPCNTBZrm 5186 +VPOPCNTBZrmk 5187 +VPOPCNTBZrmkz 5188 +VPOPCNTBZrr 5189 +VPOPCNTBZrrk 5190 +VPOPCNTBZrrkz 5191 +VPOPCNTDZ 5192 +VPOPCNTDZrm 5193 +VPOPCNTDZrmb 5194 +VPOPCNTDZrmbk 5195 +VPOPCNTDZrmbkz 5196 +VPOPCNTDZrmk 5197 +VPOPCNTDZrmkz 5198 +VPOPCNTDZrr 5199 +VPOPCNTDZrrk 5200 +VPOPCNTDZrrkz 5201 +VPOPCNTQZ 5202 +VPOPCNTQZrm 5203 +VPOPCNTQZrmb 5204 +VPOPCNTQZrmbk 5205 +VPOPCNTQZrmbkz 5206 +VPOPCNTQZrmk 5207 +VPOPCNTQZrmkz 5208 +VPOPCNTQZrr 5209 +VPOPCNTQZrrk 5210 +VPOPCNTQZrrkz 5211 +VPOPCNTWZ 5212 +VPOPCNTWZrm 5213 +VPOPCNTWZrmk 5214 +VPOPCNTWZrmkz 5215 +VPOPCNTWZrr 5216 +VPOPCNTWZrrk 5217 +VPOPCNTWZrrkz 5218 +VPORDZ 5219 +VPORDZrm 5220 +VPORDZrmb 5221 +VPORDZrmbk 5222 +VPORDZrmbkz 5223 +VPORDZrmk 5224 +VPORDZrmkz 5225 +VPORDZrr 5226 +VPORDZrrk 5227 +VPORDZrrkz 5228 +VPORQZ 5229 +VPORQZrm 5230 +VPORQZrmb 5231 +VPORQZrmbk 5232 +VPORQZrmbkz 5233 +VPORQZrmk 5234 +VPORQZrmkz 5235 +VPORQZrr 5236 +VPORQZrrk 5237 +VPORQZrrkz 5238 +VPORYrm 5239 +VPORYrr 5240 +VPORrm 5241 +VPORrr 5242 +VPPERMrmr 5243 +VPPERMrrm 5244 +VPPERMrrr 5245 +VPPERMrrr_REV 5246 +VPROLDZ 5247 +VPROLDZmbi 5248 +VPROLDZmbik 5249 +VPROLDZmbikz 5250 +VPROLDZmi 5251 +VPROLDZmik 5252 +VPROLDZmikz 5253 +VPROLDZri 5254 +VPROLDZrik 5255 +VPROLDZrikz 5256 +VPROLQZ 5257 +VPROLQZmbi 5258 +VPROLQZmbik 5259 +VPROLQZmbikz 5260 +VPROLQZmi 5261 +VPROLQZmik 5262 +VPROLQZmikz 5263 +VPROLQZri 5264 +VPROLQZrik 5265 +VPROLQZrikz 5266 +VPROLVDZ 5267 +VPROLVDZrm 5268 +VPROLVDZrmb 5269 +VPROLVDZrmbk 5270 +VPROLVDZrmbkz 5271 +VPROLVDZrmk 5272 +VPROLVDZrmkz 5273 +VPROLVDZrr 5274 +VPROLVDZrrk 5275 +VPROLVDZrrkz 5276 +VPROLVQZ 5277 +VPROLVQZrm 5278 +VPROLVQZrmb 5279 +VPROLVQZrmbk 5280 +VPROLVQZrmbkz 5281 +VPROLVQZrmk 5282 +VPROLVQZrmkz 5283 +VPROLVQZrr 5284 +VPROLVQZrrk 5285 +VPROLVQZrrkz 5286 +VPRORDZ 5287 +VPRORDZmbi 5288 +VPRORDZmbik 5289 +VPRORDZmbikz 5290 +VPRORDZmi 5291 +VPRORDZmik 5292 +VPRORDZmikz 5293 +VPRORDZri 5294 +VPRORDZrik 5295 +VPRORDZrikz 5296 +VPRORQZ 5297 +VPRORQZmbi 5298 +VPRORQZmbik 5299 +VPRORQZmbikz 5300 +VPRORQZmi 5301 +VPRORQZmik 5302 +VPRORQZmikz 5303 +VPRORQZri 5304 +VPRORQZrik 5305 +VPRORQZrikz 5306 +VPRORVDZ 5307 +VPRORVDZrm 5308 +VPRORVDZrmb 5309 +VPRORVDZrmbk 5310 +VPRORVDZrmbkz 5311 +VPRORVDZrmk 5312 +VPRORVDZrmkz 5313 +VPRORVDZrr 5314 +VPRORVDZrrk 5315 +VPRORVDZrrkz 5316 +VPRORVQZ 5317 +VPRORVQZrm 5318 +VPRORVQZrmb 5319 +VPRORVQZrmbk 5320 +VPRORVQZrmbkz 5321 +VPRORVQZrmk 5322 +VPRORVQZrmkz 5323 +VPRORVQZrr 5324 +VPRORVQZrrk 5325 +VPRORVQZrrkz 5326 +VPROTBmi 5327 +VPROTBmr 5328 +VPROTBri 5329 +VPROTBrm 5330 +VPROTBrr 5331 +VPROTBrr_REV 5332 +VPROTDmi 5333 +VPROTDmr 5334 +VPROTDri 5335 +VPROTDrm 5336 +VPROTDrr 5337 +VPROTDrr_REV 5338 +VPROTQmi 5339 +VPROTQmr 5340 +VPROTQri 5341 +VPROTQrm 5342 +VPROTQrr 5343 +VPROTQrr_REV 5344 +VPROTWmi 5345 +VPROTWmr 5346 +VPROTWri 5347 +VPROTWrm 5348 +VPROTWrr 5349 +VPROTWrr_REV 5350 +VPSADBWYrm 5351 +VPSADBWYrr 5352 +VPSADBWZ 5353 +VPSADBWZrm 5354 +VPSADBWZrr 5355 +VPSADBWrm 5356 +VPSADBWrr 5357 +VPSCATTERDDZ 5358 +VPSCATTERDDZmr 5359 +VPSCATTERDQZ 5360 +VPSCATTERDQZmr 5361 +VPSCATTERQDZ 5362 +VPSCATTERQDZmr 5363 +VPSCATTERQQZ 5364 +VPSCATTERQQZmr 5365 +VPSHABmr 5366 +VPSHABrm 5367 +VPSHABrr 5368 +VPSHABrr_REV 5369 +VPSHADmr 5370 +VPSHADrm 5371 +VPSHADrr 5372 +VPSHADrr_REV 5373 +VPSHAQmr 5374 +VPSHAQrm 5375 +VPSHAQrr 5376 +VPSHAQrr_REV 5377 +VPSHAWmr 5378 +VPSHAWrm 5379 +VPSHAWrr 5380 +VPSHAWrr_REV 5381 +VPSHLBmr 5382 +VPSHLBrm 5383 +VPSHLBrr 5384 +VPSHLBrr_REV 5385 +VPSHLDDZ 5386 +VPSHLDDZrmbi 5387 +VPSHLDDZrmbik 5388 +VPSHLDDZrmbikz 5389 +VPSHLDDZrmi 5390 +VPSHLDDZrmik 5391 +VPSHLDDZrmikz 5392 +VPSHLDDZrri 5393 +VPSHLDDZrrik 5394 +VPSHLDDZrrikz 5395 +VPSHLDQZ 5396 +VPSHLDQZrmbi 5397 +VPSHLDQZrmbik 5398 +VPSHLDQZrmbikz 5399 +VPSHLDQZrmi 5400 +VPSHLDQZrmik 5401 +VPSHLDQZrmikz 5402 +VPSHLDQZrri 5403 +VPSHLDQZrrik 5404 +VPSHLDQZrrikz 5405 +VPSHLDVDZ 5406 +VPSHLDVDZm 5407 +VPSHLDVDZmb 5408 +VPSHLDVDZmbk 5409 +VPSHLDVDZmbkz 5410 +VPSHLDVDZmk 5411 +VPSHLDVDZmkz 5412 +VPSHLDVDZr 5413 +VPSHLDVDZrk 5414 +VPSHLDVDZrkz 5415 +VPSHLDVQZ 5416 +VPSHLDVQZm 5417 +VPSHLDVQZmb 5418 +VPSHLDVQZmbk 5419 +VPSHLDVQZmbkz 5420 +VPSHLDVQZmk 5421 +VPSHLDVQZmkz 5422 +VPSHLDVQZr 5423 +VPSHLDVQZrk 5424 +VPSHLDVQZrkz 5425 +VPSHLDVWZ 5426 +VPSHLDVWZm 5427 +VPSHLDVWZmk 5428 +VPSHLDVWZmkz 5429 +VPSHLDVWZr 5430 +VPSHLDVWZrk 5431 +VPSHLDVWZrkz 5432 +VPSHLDWZ 5433 +VPSHLDWZrmi 5434 +VPSHLDWZrmik 5435 +VPSHLDWZrmikz 5436 +VPSHLDWZrri 5437 +VPSHLDWZrrik 5438 +VPSHLDWZrrikz 5439 +VPSHLDmr 5440 +VPSHLDrm 5441 +VPSHLDrr 5442 +VPSHLDrr_REV 5443 +VPSHLQmr 5444 +VPSHLQrm 5445 +VPSHLQrr 5446 +VPSHLQrr_REV 5447 +VPSHLWmr 5448 +VPSHLWrm 5449 +VPSHLWrr 5450 +VPSHLWrr_REV 5451 +VPSHRDDZ 5452 +VPSHRDDZrmbi 5453 +VPSHRDDZrmbik 5454 +VPSHRDDZrmbikz 5455 +VPSHRDDZrmi 5456 +VPSHRDDZrmik 5457 +VPSHRDDZrmikz 5458 +VPSHRDDZrri 5459 +VPSHRDDZrrik 5460 +VPSHRDDZrrikz 5461 +VPSHRDQZ 5462 +VPSHRDQZrmbi 5463 +VPSHRDQZrmbik 5464 +VPSHRDQZrmbikz 5465 +VPSHRDQZrmi 5466 +VPSHRDQZrmik 5467 +VPSHRDQZrmikz 5468 +VPSHRDQZrri 5469 +VPSHRDQZrrik 5470 +VPSHRDQZrrikz 5471 +VPSHRDVDZ 5472 +VPSHRDVDZm 5473 +VPSHRDVDZmb 5474 +VPSHRDVDZmbk 5475 +VPSHRDVDZmbkz 5476 +VPSHRDVDZmk 5477 +VPSHRDVDZmkz 5478 +VPSHRDVDZr 5479 +VPSHRDVDZrk 5480 +VPSHRDVDZrkz 5481 +VPSHRDVQZ 5482 +VPSHRDVQZm 5483 +VPSHRDVQZmb 5484 +VPSHRDVQZmbk 5485 +VPSHRDVQZmbkz 5486 +VPSHRDVQZmk 5487 +VPSHRDVQZmkz 5488 +VPSHRDVQZr 5489 +VPSHRDVQZrk 5490 +VPSHRDVQZrkz 5491 +VPSHRDVWZ 5492 +VPSHRDVWZm 5493 +VPSHRDVWZmk 5494 +VPSHRDVWZmkz 5495 +VPSHRDVWZr 5496 +VPSHRDVWZrk 5497 +VPSHRDVWZrkz 5498 +VPSHRDWZ 5499 +VPSHRDWZrmi 5500 +VPSHRDWZrmik 5501 +VPSHRDWZrmikz 5502 +VPSHRDWZrri 5503 +VPSHRDWZrrik 5504 +VPSHRDWZrrikz 5505 +VPSHUFBITQMBZ 5506 +VPSHUFBITQMBZrm 5507 +VPSHUFBITQMBZrmk 5508 +VPSHUFBITQMBZrr 5509 +VPSHUFBITQMBZrrk 5510 +VPSHUFBYrm 5511 +VPSHUFBYrr 5512 +VPSHUFBZ 5513 +VPSHUFBZrm 5514 +VPSHUFBZrmk 5515 +VPSHUFBZrmkz 5516 +VPSHUFBZrr 5517 +VPSHUFBZrrk 5518 +VPSHUFBZrrkz 5519 +VPSHUFBrm 5520 +VPSHUFBrr 5521 +VPSHUFDYmi 5522 +VPSHUFDYri 5523 +VPSHUFDZ 5524 +VPSHUFDZmbi 5525 +VPSHUFDZmbik 5526 +VPSHUFDZmbikz 5527 +VPSHUFDZmi 5528 +VPSHUFDZmik 5529 +VPSHUFDZmikz 5530 +VPSHUFDZri 5531 +VPSHUFDZrik 5532 +VPSHUFDZrikz 5533 +VPSHUFDmi 5534 +VPSHUFDri 5535 +VPSHUFHWYmi 5536 +VPSHUFHWYri 5537 +VPSHUFHWZ 5538 +VPSHUFHWZmi 5539 +VPSHUFHWZmik 5540 +VPSHUFHWZmikz 5541 +VPSHUFHWZri 5542 +VPSHUFHWZrik 5543 +VPSHUFHWZrikz 5544 +VPSHUFHWmi 5545 +VPSHUFHWri 5546 +VPSHUFLWYmi 5547 +VPSHUFLWYri 5548 +VPSHUFLWZ 5549 +VPSHUFLWZmi 5550 +VPSHUFLWZmik 5551 +VPSHUFLWZmikz 5552 +VPSHUFLWZri 5553 +VPSHUFLWZrik 5554 +VPSHUFLWZrikz 5555 +VPSHUFLWmi 5556 +VPSHUFLWri 5557 +VPSIGNBYrm 5558 +VPSIGNBYrr 5559 +VPSIGNBrm 5560 +VPSIGNBrr 5561 +VPSIGNDYrm 5562 +VPSIGNDYrr 5563 +VPSIGNDrm 5564 +VPSIGNDrr 5565 +VPSIGNWYrm 5566 +VPSIGNWYrr 5567 +VPSIGNWrm 5568 +VPSIGNWrr 5569 +VPSLLDQYri 5570 +VPSLLDQZ 5571 +VPSLLDQZmi 5572 +VPSLLDQZri 5573 +VPSLLDQri 5574 +VPSLLDYri 5575 +VPSLLDYrm 5576 +VPSLLDYrr 5577 +VPSLLDZ 5578 +VPSLLDZmbi 5579 +VPSLLDZmbik 5580 +VPSLLDZmbikz 5581 +VPSLLDZmi 5582 +VPSLLDZmik 5583 +VPSLLDZmikz 5584 +VPSLLDZri 5585 +VPSLLDZrik 5586 +VPSLLDZrikz 5587 +VPSLLDZrm 5588 +VPSLLDZrmk 5589 +VPSLLDZrmkz 5590 +VPSLLDZrr 5591 +VPSLLDZrrk 5592 +VPSLLDZrrkz 5593 +VPSLLDri 5594 +VPSLLDrm 5595 +VPSLLDrr 5596 +VPSLLQYri 5597 +VPSLLQYrm 5598 +VPSLLQYrr 5599 +VPSLLQZ 5600 +VPSLLQZmbi 5601 +VPSLLQZmbik 5602 +VPSLLQZmbikz 5603 +VPSLLQZmi 5604 +VPSLLQZmik 5605 +VPSLLQZmikz 5606 +VPSLLQZri 5607 +VPSLLQZrik 5608 +VPSLLQZrikz 5609 +VPSLLQZrm 5610 +VPSLLQZrmk 5611 +VPSLLQZrmkz 5612 +VPSLLQZrr 5613 +VPSLLQZrrk 5614 +VPSLLQZrrkz 5615 +VPSLLQri 5616 +VPSLLQrm 5617 +VPSLLQrr 5618 +VPSLLVDYrm 5619 +VPSLLVDYrr 5620 +VPSLLVDZ 5621 +VPSLLVDZrm 5622 +VPSLLVDZrmb 5623 +VPSLLVDZrmbk 5624 +VPSLLVDZrmbkz 5625 +VPSLLVDZrmk 5626 +VPSLLVDZrmkz 5627 +VPSLLVDZrr 5628 +VPSLLVDZrrk 5629 +VPSLLVDZrrkz 5630 +VPSLLVDrm 5631 +VPSLLVDrr 5632 +VPSLLVQYrm 5633 +VPSLLVQYrr 5634 +VPSLLVQZ 5635 +VPSLLVQZrm 5636 +VPSLLVQZrmb 5637 +VPSLLVQZrmbk 5638 +VPSLLVQZrmbkz 5639 +VPSLLVQZrmk 5640 +VPSLLVQZrmkz 5641 +VPSLLVQZrr 5642 +VPSLLVQZrrk 5643 +VPSLLVQZrrkz 5644 +VPSLLVQrm 5645 +VPSLLVQrr 5646 +VPSLLVWZ 5647 +VPSLLVWZrm 5648 +VPSLLVWZrmk 5649 +VPSLLVWZrmkz 5650 +VPSLLVWZrr 5651 +VPSLLVWZrrk 5652 +VPSLLVWZrrkz 5653 +VPSLLWYri 5654 +VPSLLWYrm 5655 +VPSLLWYrr 5656 +VPSLLWZ 5657 +VPSLLWZmi 5658 +VPSLLWZmik 5659 +VPSLLWZmikz 5660 +VPSLLWZri 5661 +VPSLLWZrik 5662 +VPSLLWZrikz 5663 +VPSLLWZrm 5664 +VPSLLWZrmk 5665 +VPSLLWZrmkz 5666 +VPSLLWZrr 5667 +VPSLLWZrrk 5668 +VPSLLWZrrkz 5669 +VPSLLWri 5670 +VPSLLWrm 5671 +VPSLLWrr 5672 +VPSRADYri 5673 +VPSRADYrm 5674 +VPSRADYrr 5675 +VPSRADZ 5676 +VPSRADZmbi 5677 +VPSRADZmbik 5678 +VPSRADZmbikz 5679 +VPSRADZmi 5680 +VPSRADZmik 5681 +VPSRADZmikz 5682 +VPSRADZri 5683 +VPSRADZrik 5684 +VPSRADZrikz 5685 +VPSRADZrm 5686 +VPSRADZrmk 5687 +VPSRADZrmkz 5688 +VPSRADZrr 5689 +VPSRADZrrk 5690 +VPSRADZrrkz 5691 +VPSRADri 5692 +VPSRADrm 5693 +VPSRADrr 5694 +VPSRAQZ 5695 +VPSRAQZmbi 5696 +VPSRAQZmbik 5697 +VPSRAQZmbikz 5698 +VPSRAQZmi 5699 +VPSRAQZmik 5700 +VPSRAQZmikz 5701 +VPSRAQZri 5702 +VPSRAQZrik 5703 +VPSRAQZrikz 5704 +VPSRAQZrm 5705 +VPSRAQZrmk 5706 +VPSRAQZrmkz 5707 +VPSRAQZrr 5708 +VPSRAQZrrk 5709 +VPSRAQZrrkz 5710 +VPSRAVDYrm 5711 +VPSRAVDYrr 5712 +VPSRAVDZ 5713 +VPSRAVDZrm 5714 +VPSRAVDZrmb 5715 +VPSRAVDZrmbk 5716 +VPSRAVDZrmbkz 5717 +VPSRAVDZrmk 5718 +VPSRAVDZrmkz 5719 +VPSRAVDZrr 5720 +VPSRAVDZrrk 5721 +VPSRAVDZrrkz 5722 +VPSRAVDrm 5723 +VPSRAVDrr 5724 +VPSRAVQZ 5725 +VPSRAVQZrm 5726 +VPSRAVQZrmb 5727 +VPSRAVQZrmbk 5728 +VPSRAVQZrmbkz 5729 +VPSRAVQZrmk 5730 +VPSRAVQZrmkz 5731 +VPSRAVQZrr 5732 +VPSRAVQZrrk 5733 +VPSRAVQZrrkz 5734 +VPSRAVWZ 5735 +VPSRAVWZrm 5736 +VPSRAVWZrmk 5737 +VPSRAVWZrmkz 5738 +VPSRAVWZrr 5739 +VPSRAVWZrrk 5740 +VPSRAVWZrrkz 5741 +VPSRAWYri 5742 +VPSRAWYrm 5743 +VPSRAWYrr 5744 +VPSRAWZ 5745 +VPSRAWZmi 5746 +VPSRAWZmik 5747 +VPSRAWZmikz 5748 +VPSRAWZri 5749 +VPSRAWZrik 5750 +VPSRAWZrikz 5751 +VPSRAWZrm 5752 +VPSRAWZrmk 5753 +VPSRAWZrmkz 5754 +VPSRAWZrr 5755 +VPSRAWZrrk 5756 +VPSRAWZrrkz 5757 +VPSRAWri 5758 +VPSRAWrm 5759 +VPSRAWrr 5760 +VPSRLDQYri 5761 +VPSRLDQZ 5762 +VPSRLDQZmi 5763 +VPSRLDQZri 5764 +VPSRLDQri 5765 +VPSRLDYri 5766 +VPSRLDYrm 5767 +VPSRLDYrr 5768 +VPSRLDZ 5769 +VPSRLDZmbi 5770 +VPSRLDZmbik 5771 +VPSRLDZmbikz 5772 +VPSRLDZmi 5773 +VPSRLDZmik 5774 +VPSRLDZmikz 5775 +VPSRLDZri 5776 +VPSRLDZrik 5777 +VPSRLDZrikz 5778 +VPSRLDZrm 5779 +VPSRLDZrmk 5780 +VPSRLDZrmkz 5781 +VPSRLDZrr 5782 +VPSRLDZrrk 5783 +VPSRLDZrrkz 5784 +VPSRLDri 5785 +VPSRLDrm 5786 +VPSRLDrr 5787 +VPSRLQYri 5788 +VPSRLQYrm 5789 +VPSRLQYrr 5790 +VPSRLQZ 5791 +VPSRLQZmbi 5792 +VPSRLQZmbik 5793 +VPSRLQZmbikz 5794 +VPSRLQZmi 5795 +VPSRLQZmik 5796 +VPSRLQZmikz 5797 +VPSRLQZri 5798 +VPSRLQZrik 5799 +VPSRLQZrikz 5800 +VPSRLQZrm 5801 +VPSRLQZrmk 5802 +VPSRLQZrmkz 5803 +VPSRLQZrr 5804 +VPSRLQZrrk 5805 +VPSRLQZrrkz 5806 +VPSRLQri 5807 +VPSRLQrm 5808 +VPSRLQrr 5809 +VPSRLVDYrm 5810 +VPSRLVDYrr 5811 +VPSRLVDZ 5812 +VPSRLVDZrm 5813 +VPSRLVDZrmb 5814 +VPSRLVDZrmbk 5815 +VPSRLVDZrmbkz 5816 +VPSRLVDZrmk 5817 +VPSRLVDZrmkz 5818 +VPSRLVDZrr 5819 +VPSRLVDZrrk 5820 +VPSRLVDZrrkz 5821 +VPSRLVDrm 5822 +VPSRLVDrr 5823 +VPSRLVQYrm 5824 +VPSRLVQYrr 5825 +VPSRLVQZ 5826 +VPSRLVQZrm 5827 +VPSRLVQZrmb 5828 +VPSRLVQZrmbk 5829 +VPSRLVQZrmbkz 5830 +VPSRLVQZrmk 5831 +VPSRLVQZrmkz 5832 +VPSRLVQZrr 5833 +VPSRLVQZrrk 5834 +VPSRLVQZrrkz 5835 +VPSRLVQrm 5836 +VPSRLVQrr 5837 +VPSRLVWZ 5838 +VPSRLVWZrm 5839 +VPSRLVWZrmk 5840 +VPSRLVWZrmkz 5841 +VPSRLVWZrr 5842 +VPSRLVWZrrk 5843 +VPSRLVWZrrkz 5844 +VPSRLWYri 5845 +VPSRLWYrm 5846 +VPSRLWYrr 5847 +VPSRLWZ 5848 +VPSRLWZmi 5849 +VPSRLWZmik 5850 +VPSRLWZmikz 5851 +VPSRLWZri 5852 +VPSRLWZrik 5853 +VPSRLWZrikz 5854 +VPSRLWZrm 5855 +VPSRLWZrmk 5856 +VPSRLWZrmkz 5857 +VPSRLWZrr 5858 +VPSRLWZrrk 5859 +VPSRLWZrrkz 5860 +VPSRLWri 5861 +VPSRLWrm 5862 +VPSRLWrr 5863 +VPSUBBYrm 5864 +VPSUBBYrr 5865 +VPSUBBZ 5866 +VPSUBBZrm 5867 +VPSUBBZrmk 5868 +VPSUBBZrmkz 5869 +VPSUBBZrr 5870 +VPSUBBZrrk 5871 +VPSUBBZrrkz 5872 +VPSUBBrm 5873 +VPSUBBrr 5874 +VPSUBDYrm 5875 +VPSUBDYrr 5876 +VPSUBDZ 5877 +VPSUBDZrm 5878 +VPSUBDZrmb 5879 +VPSUBDZrmbk 5880 +VPSUBDZrmbkz 5881 +VPSUBDZrmk 5882 +VPSUBDZrmkz 5883 +VPSUBDZrr 5884 +VPSUBDZrrk 5885 +VPSUBDZrrkz 5886 +VPSUBDrm 5887 +VPSUBDrr 5888 +VPSUBQYrm 5889 +VPSUBQYrr 5890 +VPSUBQZ 5891 +VPSUBQZrm 5892 +VPSUBQZrmb 5893 +VPSUBQZrmbk 5894 +VPSUBQZrmbkz 5895 +VPSUBQZrmk 5896 +VPSUBQZrmkz 5897 +VPSUBQZrr 5898 +VPSUBQZrrk 5899 +VPSUBQZrrkz 5900 +VPSUBQrm 5901 +VPSUBQrr 5902 +VPSUBSBYrm 5903 +VPSUBSBYrr 5904 +VPSUBSBZ 5905 +VPSUBSBZrm 5906 +VPSUBSBZrmk 5907 +VPSUBSBZrmkz 5908 +VPSUBSBZrr 5909 +VPSUBSBZrrk 5910 +VPSUBSBZrrkz 5911 +VPSUBSBrm 5912 +VPSUBSBrr 5913 +VPSUBSWYrm 5914 +VPSUBSWYrr 5915 +VPSUBSWZ 5916 +VPSUBSWZrm 5917 +VPSUBSWZrmk 5918 +VPSUBSWZrmkz 5919 +VPSUBSWZrr 5920 +VPSUBSWZrrk 5921 +VPSUBSWZrrkz 5922 +VPSUBSWrm 5923 +VPSUBSWrr 5924 +VPSUBUSBYrm 5925 +VPSUBUSBYrr 5926 +VPSUBUSBZ 5927 +VPSUBUSBZrm 5928 +VPSUBUSBZrmk 5929 +VPSUBUSBZrmkz 5930 +VPSUBUSBZrr 5931 +VPSUBUSBZrrk 5932 +VPSUBUSBZrrkz 5933 +VPSUBUSBrm 5934 +VPSUBUSBrr 5935 +VPSUBUSWYrm 5936 +VPSUBUSWYrr 5937 +VPSUBUSWZ 5938 +VPSUBUSWZrm 5939 +VPSUBUSWZrmk 5940 +VPSUBUSWZrmkz 5941 +VPSUBUSWZrr 5942 +VPSUBUSWZrrk 5943 +VPSUBUSWZrrkz 5944 +VPSUBUSWrm 5945 +VPSUBUSWrr 5946 +VPSUBWYrm 5947 +VPSUBWYrr 5948 +VPSUBWZ 5949 +VPSUBWZrm 5950 +VPSUBWZrmk 5951 +VPSUBWZrmkz 5952 +VPSUBWZrr 5953 +VPSUBWZrrk 5954 +VPSUBWZrrkz 5955 +VPSUBWrm 5956 +VPSUBWrr 5957 +VPTERNLOGDZ 5958 +VPTERNLOGDZrmbi 5959 +VPTERNLOGDZrmbik 5960 +VPTERNLOGDZrmbikz 5961 +VPTERNLOGDZrmi 5962 +VPTERNLOGDZrmik 5963 +VPTERNLOGDZrmikz 5964 +VPTERNLOGDZrri 5965 +VPTERNLOGDZrrik 5966 +VPTERNLOGDZrrikz 5967 +VPTERNLOGQZ 5968 +VPTERNLOGQZrmbi 5969 +VPTERNLOGQZrmbik 5970 +VPTERNLOGQZrmbikz 5971 +VPTERNLOGQZrmi 5972 +VPTERNLOGQZrmik 5973 +VPTERNLOGQZrmikz 5974 +VPTERNLOGQZrri 5975 +VPTERNLOGQZrrik 5976 +VPTERNLOGQZrrikz 5977 +VPTESTMBZ 5978 +VPTESTMBZrm 5979 +VPTESTMBZrmk 5980 +VPTESTMBZrr 5981 +VPTESTMBZrrk 5982 +VPTESTMDZ 5983 +VPTESTMDZrm 5984 +VPTESTMDZrmb 5985 +VPTESTMDZrmbk 5986 +VPTESTMDZrmk 5987 +VPTESTMDZrr 5988 +VPTESTMDZrrk 5989 +VPTESTMQZ 5990 +VPTESTMQZrm 5991 +VPTESTMQZrmb 5992 +VPTESTMQZrmbk 5993 +VPTESTMQZrmk 5994 +VPTESTMQZrr 5995 +VPTESTMQZrrk 5996 +VPTESTMWZ 5997 +VPTESTMWZrm 5998 +VPTESTMWZrmk 5999 +VPTESTMWZrr 6000 +VPTESTMWZrrk 6001 +VPTESTNMBZ 6002 +VPTESTNMBZrm 6003 +VPTESTNMBZrmk 6004 +VPTESTNMBZrr 6005 +VPTESTNMBZrrk 6006 +VPTESTNMDZ 6007 +VPTESTNMDZrm 6008 +VPTESTNMDZrmb 6009 +VPTESTNMDZrmbk 6010 +VPTESTNMDZrmk 6011 +VPTESTNMDZrr 6012 +VPTESTNMDZrrk 6013 +VPTESTNMQZ 6014 +VPTESTNMQZrm 6015 +VPTESTNMQZrmb 6016 +VPTESTNMQZrmbk 6017 +VPTESTNMQZrmk 6018 +VPTESTNMQZrr 6019 +VPTESTNMQZrrk 6020 +VPTESTNMWZ 6021 +VPTESTNMWZrm 6022 +VPTESTNMWZrmk 6023 +VPTESTNMWZrr 6024 +VPTESTNMWZrrk 6025 +VPTESTYrm 6026 +VPTESTYrr 6027 +VPTESTrm 6028 +VPTESTrr 6029 +VPUNPCKHBWYrm 6030 +VPUNPCKHBWYrr 6031 +VPUNPCKHBWZ 6032 +VPUNPCKHBWZrm 6033 +VPUNPCKHBWZrmk 6034 +VPUNPCKHBWZrmkz 6035 +VPUNPCKHBWZrr 6036 +VPUNPCKHBWZrrk 6037 +VPUNPCKHBWZrrkz 6038 +VPUNPCKHBWrm 6039 +VPUNPCKHBWrr 6040 +VPUNPCKHDQYrm 6041 +VPUNPCKHDQYrr 6042 +VPUNPCKHDQZ 6043 +VPUNPCKHDQZrm 6044 +VPUNPCKHDQZrmb 6045 +VPUNPCKHDQZrmbk 6046 +VPUNPCKHDQZrmbkz 6047 +VPUNPCKHDQZrmk 6048 +VPUNPCKHDQZrmkz 6049 +VPUNPCKHDQZrr 6050 +VPUNPCKHDQZrrk 6051 +VPUNPCKHDQZrrkz 6052 +VPUNPCKHDQrm 6053 +VPUNPCKHDQrr 6054 +VPUNPCKHQDQYrm 6055 +VPUNPCKHQDQYrr 6056 +VPUNPCKHQDQZ 6057 +VPUNPCKHQDQZrm 6058 +VPUNPCKHQDQZrmb 6059 +VPUNPCKHQDQZrmbk 6060 +VPUNPCKHQDQZrmbkz 6061 +VPUNPCKHQDQZrmk 6062 +VPUNPCKHQDQZrmkz 6063 +VPUNPCKHQDQZrr 6064 +VPUNPCKHQDQZrrk 6065 +VPUNPCKHQDQZrrkz 6066 +VPUNPCKHQDQrm 6067 +VPUNPCKHQDQrr 6068 +VPUNPCKHWDYrm 6069 +VPUNPCKHWDYrr 6070 +VPUNPCKHWDZ 6071 +VPUNPCKHWDZrm 6072 +VPUNPCKHWDZrmk 6073 +VPUNPCKHWDZrmkz 6074 +VPUNPCKHWDZrr 6075 +VPUNPCKHWDZrrk 6076 +VPUNPCKHWDZrrkz 6077 +VPUNPCKHWDrm 6078 +VPUNPCKHWDrr 6079 +VPUNPCKLBWYrm 6080 +VPUNPCKLBWYrr 6081 +VPUNPCKLBWZ 6082 +VPUNPCKLBWZrm 6083 +VPUNPCKLBWZrmk 6084 +VPUNPCKLBWZrmkz 6085 +VPUNPCKLBWZrr 6086 +VPUNPCKLBWZrrk 6087 +VPUNPCKLBWZrrkz 6088 +VPUNPCKLBWrm 6089 +VPUNPCKLBWrr 6090 +VPUNPCKLDQYrm 6091 +VPUNPCKLDQYrr 6092 +VPUNPCKLDQZ 6093 +VPUNPCKLDQZrm 6094 +VPUNPCKLDQZrmb 6095 +VPUNPCKLDQZrmbk 6096 +VPUNPCKLDQZrmbkz 6097 +VPUNPCKLDQZrmk 6098 +VPUNPCKLDQZrmkz 6099 +VPUNPCKLDQZrr 6100 +VPUNPCKLDQZrrk 6101 +VPUNPCKLDQZrrkz 6102 +VPUNPCKLDQrm 6103 +VPUNPCKLDQrr 6104 +VPUNPCKLQDQYrm 6105 +VPUNPCKLQDQYrr 6106 +VPUNPCKLQDQZ 6107 +VPUNPCKLQDQZrm 6108 +VPUNPCKLQDQZrmb 6109 +VPUNPCKLQDQZrmbk 6110 +VPUNPCKLQDQZrmbkz 6111 +VPUNPCKLQDQZrmk 6112 +VPUNPCKLQDQZrmkz 6113 +VPUNPCKLQDQZrr 6114 +VPUNPCKLQDQZrrk 6115 +VPUNPCKLQDQZrrkz 6116 +VPUNPCKLQDQrm 6117 +VPUNPCKLQDQrr 6118 +VPUNPCKLWDYrm 6119 +VPUNPCKLWDYrr 6120 +VPUNPCKLWDZ 6121 +VPUNPCKLWDZrm 6122 +VPUNPCKLWDZrmk 6123 +VPUNPCKLWDZrmkz 6124 +VPUNPCKLWDZrr 6125 +VPUNPCKLWDZrrk 6126 +VPUNPCKLWDZrrkz 6127 +VPUNPCKLWDrm 6128 +VPUNPCKLWDrr 6129 +VPXORDZ 6130 +VPXORDZrm 6131 +VPXORDZrmb 6132 +VPXORDZrmbk 6133 +VPXORDZrmbkz 6134 +VPXORDZrmk 6135 +VPXORDZrmkz 6136 +VPXORDZrr 6137 +VPXORDZrrk 6138 +VPXORDZrrkz 6139 +VPXORQZ 6140 +VPXORQZrm 6141 +VPXORQZrmb 6142 +VPXORQZrmbk 6143 +VPXORQZrmbkz 6144 +VPXORQZrmk 6145 +VPXORQZrmkz 6146 +VPXORQZrr 6147 +VPXORQZrrk 6148 +VPXORQZrrkz 6149 +VPXORYrm 6150 +VPXORYrr 6151 +VPXORrm 6152 +VPXORrr 6153 +VRANGEPDZ 6154 +VRANGEPDZrmbi 6155 +VRANGEPDZrmbik 6156 +VRANGEPDZrmbikz 6157 +VRANGEPDZrmi 6158 +VRANGEPDZrmik 6159 +VRANGEPDZrmikz 6160 +VRANGEPDZrri 6161 +VRANGEPDZrrib 6162 +VRANGEPDZrribk 6163 +VRANGEPDZrribkz 6164 +VRANGEPDZrrik 6165 +VRANGEPDZrrikz 6166 +VRANGEPSZ 6167 +VRANGEPSZrmbi 6168 +VRANGEPSZrmbik 6169 +VRANGEPSZrmbikz 6170 +VRANGEPSZrmi 6171 +VRANGEPSZrmik 6172 +VRANGEPSZrmikz 6173 +VRANGEPSZrri 6174 +VRANGEPSZrrib 6175 +VRANGEPSZrribk 6176 +VRANGEPSZrribkz 6177 +VRANGEPSZrrik 6178 +VRANGEPSZrrikz 6179 +VRANGESDZrmi 6180 +VRANGESDZrmik 6181 +VRANGESDZrmikz 6182 +VRANGESDZrri 6183 +VRANGESDZrrib 6184 +VRANGESDZrribk 6185 +VRANGESDZrribkz 6186 +VRANGESDZrrik 6187 +VRANGESDZrrikz 6188 +VRANGESSZrmi 6189 +VRANGESSZrmik 6190 +VRANGESSZrmikz 6191 +VRANGESSZrri 6192 +VRANGESSZrrib 6193 +VRANGESSZrribk 6194 +VRANGESSZrribkz 6195 +VRANGESSZrrik 6196 +VRANGESSZrrikz 6197 +VRCP 6198 +VRCPBF 6199 +VRCPPHZ 6200 +VRCPPHZm 6201 +VRCPPHZmb 6202 +VRCPPHZmbk 6203 +VRCPPHZmbkz 6204 +VRCPPHZmk 6205 +VRCPPHZmkz 6206 +VRCPPHZr 6207 +VRCPPHZrk 6208 +VRCPPHZrkz 6209 +VRCPPSYm 6210 +VRCPPSYr 6211 +VRCPPSm 6212 +VRCPPSr 6213 +VRCPSHZrm 6214 +VRCPSHZrmk 6215 +VRCPSHZrmkz 6216 +VRCPSHZrr 6217 +VRCPSHZrrk 6218 +VRCPSHZrrkz 6219 +VRCPSSm 6220 +VRCPSSm_Int 6221 +VRCPSSr 6222 +VRCPSSr_Int 6223 +VREDUCEBF 6224 +VREDUCEPDZ 6225 +VREDUCEPDZrmbi 6226 +VREDUCEPDZrmbik 6227 +VREDUCEPDZrmbikz 6228 +VREDUCEPDZrmi 6229 +VREDUCEPDZrmik 6230 +VREDUCEPDZrmikz 6231 +VREDUCEPDZrri 6232 +VREDUCEPDZrrib 6233 +VREDUCEPDZrribk 6234 +VREDUCEPDZrribkz 6235 +VREDUCEPDZrrik 6236 +VREDUCEPDZrrikz 6237 +VREDUCEPHZ 6238 +VREDUCEPHZrmbi 6239 +VREDUCEPHZrmbik 6240 +VREDUCEPHZrmbikz 6241 +VREDUCEPHZrmi 6242 +VREDUCEPHZrmik 6243 +VREDUCEPHZrmikz 6244 +VREDUCEPHZrri 6245 +VREDUCEPHZrrib 6246 +VREDUCEPHZrribk 6247 +VREDUCEPHZrribkz 6248 +VREDUCEPHZrrik 6249 +VREDUCEPHZrrikz 6250 +VREDUCEPSZ 6251 +VREDUCEPSZrmbi 6252 +VREDUCEPSZrmbik 6253 +VREDUCEPSZrmbikz 6254 +VREDUCEPSZrmi 6255 +VREDUCEPSZrmik 6256 +VREDUCEPSZrmikz 6257 +VREDUCEPSZrri 6258 +VREDUCEPSZrrib 6259 +VREDUCEPSZrribk 6260 +VREDUCEPSZrribkz 6261 +VREDUCEPSZrrik 6262 +VREDUCEPSZrrikz 6263 +VREDUCESDZrmi 6264 +VREDUCESDZrmik 6265 +VREDUCESDZrmikz 6266 +VREDUCESDZrri 6267 +VREDUCESDZrrib 6268 +VREDUCESDZrribk 6269 +VREDUCESDZrribkz 6270 +VREDUCESDZrrik 6271 +VREDUCESDZrrikz 6272 +VREDUCESHZrmi 6273 +VREDUCESHZrmik 6274 +VREDUCESHZrmikz 6275 +VREDUCESHZrri 6276 +VREDUCESHZrrib 6277 +VREDUCESHZrribk 6278 +VREDUCESHZrribkz 6279 +VREDUCESHZrrik 6280 +VREDUCESHZrrikz 6281 +VREDUCESSZrmi 6282 +VREDUCESSZrmik 6283 +VREDUCESSZrmikz 6284 +VREDUCESSZrri 6285 +VREDUCESSZrrib 6286 +VREDUCESSZrribk 6287 +VREDUCESSZrribkz 6288 +VREDUCESSZrrik 6289 +VREDUCESSZrrikz 6290 +VRNDSCALEBF 6291 +VRNDSCALEPDZ 6292 +VRNDSCALEPDZrmbi 6293 +VRNDSCALEPDZrmbik 6294 +VRNDSCALEPDZrmbikz 6295 +VRNDSCALEPDZrmi 6296 +VRNDSCALEPDZrmik 6297 +VRNDSCALEPDZrmikz 6298 +VRNDSCALEPDZrri 6299 +VRNDSCALEPDZrrib 6300 +VRNDSCALEPDZrribk 6301 +VRNDSCALEPDZrribkz 6302 +VRNDSCALEPDZrrik 6303 +VRNDSCALEPDZrrikz 6304 +VRNDSCALEPHZ 6305 +VRNDSCALEPHZrmbi 6306 +VRNDSCALEPHZrmbik 6307 +VRNDSCALEPHZrmbikz 6308 +VRNDSCALEPHZrmi 6309 +VRNDSCALEPHZrmik 6310 +VRNDSCALEPHZrmikz 6311 +VRNDSCALEPHZrri 6312 +VRNDSCALEPHZrrib 6313 +VRNDSCALEPHZrribk 6314 +VRNDSCALEPHZrribkz 6315 +VRNDSCALEPHZrrik 6316 +VRNDSCALEPHZrrikz 6317 +VRNDSCALEPSZ 6318 +VRNDSCALEPSZrmbi 6319 +VRNDSCALEPSZrmbik 6320 +VRNDSCALEPSZrmbikz 6321 +VRNDSCALEPSZrmi 6322 +VRNDSCALEPSZrmik 6323 +VRNDSCALEPSZrmikz 6324 +VRNDSCALEPSZrri 6325 +VRNDSCALEPSZrrib 6326 +VRNDSCALEPSZrribk 6327 +VRNDSCALEPSZrribkz 6328 +VRNDSCALEPSZrrik 6329 +VRNDSCALEPSZrrikz 6330 +VRNDSCALESDZrmi 6331 +VRNDSCALESDZrmi_Int 6332 +VRNDSCALESDZrmik_Int 6333 +VRNDSCALESDZrmikz_Int 6334 +VRNDSCALESDZrri 6335 +VRNDSCALESDZrri_Int 6336 +VRNDSCALESDZrrib_Int 6337 +VRNDSCALESDZrribk_Int 6338 +VRNDSCALESDZrribkz_Int 6339 +VRNDSCALESDZrrik_Int 6340 +VRNDSCALESDZrrikz_Int 6341 +VRNDSCALESHZrmi 6342 +VRNDSCALESHZrmi_Int 6343 +VRNDSCALESHZrmik_Int 6344 +VRNDSCALESHZrmikz_Int 6345 +VRNDSCALESHZrri 6346 +VRNDSCALESHZrri_Int 6347 +VRNDSCALESHZrrib_Int 6348 +VRNDSCALESHZrribk_Int 6349 +VRNDSCALESHZrribkz_Int 6350 +VRNDSCALESHZrrik_Int 6351 +VRNDSCALESHZrrikz_Int 6352 +VRNDSCALESSZrmi 6353 +VRNDSCALESSZrmi_Int 6354 +VRNDSCALESSZrmik_Int 6355 +VRNDSCALESSZrmikz_Int 6356 +VRNDSCALESSZrri 6357 +VRNDSCALESSZrri_Int 6358 +VRNDSCALESSZrrib_Int 6359 +VRNDSCALESSZrribk_Int 6360 +VRNDSCALESSZrribkz_Int 6361 +VRNDSCALESSZrrik_Int 6362 +VRNDSCALESSZrrikz_Int 6363 +VROUNDPDYmi 6364 +VROUNDPDYri 6365 +VROUNDPDmi 6366 +VROUNDPDri 6367 +VROUNDPSYmi 6368 +VROUNDPSYri 6369 +VROUNDPSmi 6370 +VROUNDPSri 6371 +VROUNDSDmi 6372 +VROUNDSDmi_Int 6373 +VROUNDSDri 6374 +VROUNDSDri_Int 6375 +VROUNDSSmi 6376 +VROUNDSSmi_Int 6377 +VROUNDSSri 6378 +VROUNDSSri_Int 6379 +VRSQRT 6380 +VRSQRTBF 6381 +VRSQRTPHZ 6382 +VRSQRTPHZm 6383 +VRSQRTPHZmb 6384 +VRSQRTPHZmbk 6385 +VRSQRTPHZmbkz 6386 +VRSQRTPHZmk 6387 +VRSQRTPHZmkz 6388 +VRSQRTPHZr 6389 +VRSQRTPHZrk 6390 +VRSQRTPHZrkz 6391 +VRSQRTPSYm 6392 +VRSQRTPSYr 6393 +VRSQRTPSm 6394 +VRSQRTPSr 6395 +VRSQRTSHZrm 6396 +VRSQRTSHZrmk 6397 +VRSQRTSHZrmkz 6398 +VRSQRTSHZrr 6399 +VRSQRTSHZrrk 6400 +VRSQRTSHZrrkz 6401 +VRSQRTSSm 6402 +VRSQRTSSm_Int 6403 +VRSQRTSSr 6404 +VRSQRTSSr_Int 6405 +VSCALEFBF 6406 +VSCALEFPDZ 6407 +VSCALEFPDZrm 6408 +VSCALEFPDZrmb 6409 +VSCALEFPDZrmbk 6410 +VSCALEFPDZrmbkz 6411 +VSCALEFPDZrmk 6412 +VSCALEFPDZrmkz 6413 +VSCALEFPDZrr 6414 +VSCALEFPDZrrb 6415 +VSCALEFPDZrrbk 6416 +VSCALEFPDZrrbkz 6417 +VSCALEFPDZrrk 6418 +VSCALEFPDZrrkz 6419 +VSCALEFPHZ 6420 +VSCALEFPHZrm 6421 +VSCALEFPHZrmb 6422 +VSCALEFPHZrmbk 6423 +VSCALEFPHZrmbkz 6424 +VSCALEFPHZrmk 6425 +VSCALEFPHZrmkz 6426 +VSCALEFPHZrr 6427 +VSCALEFPHZrrb 6428 +VSCALEFPHZrrbk 6429 +VSCALEFPHZrrbkz 6430 +VSCALEFPHZrrk 6431 +VSCALEFPHZrrkz 6432 +VSCALEFPSZ 6433 +VSCALEFPSZrm 6434 +VSCALEFPSZrmb 6435 +VSCALEFPSZrmbk 6436 +VSCALEFPSZrmbkz 6437 +VSCALEFPSZrmk 6438 +VSCALEFPSZrmkz 6439 +VSCALEFPSZrr 6440 +VSCALEFPSZrrb 6441 +VSCALEFPSZrrbk 6442 +VSCALEFPSZrrbkz 6443 +VSCALEFPSZrrk 6444 +VSCALEFPSZrrkz 6445 +VSCALEFSDZrm 6446 +VSCALEFSDZrmk 6447 +VSCALEFSDZrmkz 6448 +VSCALEFSDZrr 6449 +VSCALEFSDZrrb_Int 6450 +VSCALEFSDZrrbk_Int 6451 +VSCALEFSDZrrbkz_Int 6452 +VSCALEFSDZrrk 6453 +VSCALEFSDZrrkz 6454 +VSCALEFSHZrm 6455 +VSCALEFSHZrmk 6456 +VSCALEFSHZrmkz 6457 +VSCALEFSHZrr 6458 +VSCALEFSHZrrb_Int 6459 +VSCALEFSHZrrbk_Int 6460 +VSCALEFSHZrrbkz_Int 6461 +VSCALEFSHZrrk 6462 +VSCALEFSHZrrkz 6463 +VSCALEFSSZrm 6464 +VSCALEFSSZrmk 6465 +VSCALEFSSZrmkz 6466 +VSCALEFSSZrr 6467 +VSCALEFSSZrrb_Int 6468 +VSCALEFSSZrrbk_Int 6469 +VSCALEFSSZrrbkz_Int 6470 +VSCALEFSSZrrk 6471 +VSCALEFSSZrrkz 6472 +VSCATTERDPDZ 6473 +VSCATTERDPDZmr 6474 +VSCATTERDPSZ 6475 +VSCATTERDPSZmr 6476 +VSCATTERPF 6477 +VSCATTERQPDZ 6478 +VSCATTERQPDZmr 6479 +VSCATTERQPSZ 6480 +VSCATTERQPSZmr 6481 +VSHA 6482 +VSHUFF 6483 +VSHUFI 6484 +VSHUFPDYrmi 6485 +VSHUFPDYrri 6486 +VSHUFPDZ 6487 +VSHUFPDZrmbi 6488 +VSHUFPDZrmbik 6489 +VSHUFPDZrmbikz 6490 +VSHUFPDZrmi 6491 +VSHUFPDZrmik 6492 +VSHUFPDZrmikz 6493 +VSHUFPDZrri 6494 +VSHUFPDZrrik 6495 +VSHUFPDZrrikz 6496 +VSHUFPDrmi 6497 +VSHUFPDrri 6498 +VSHUFPSYrmi 6499 +VSHUFPSYrri 6500 +VSHUFPSZ 6501 +VSHUFPSZrmbi 6502 +VSHUFPSZrmbik 6503 +VSHUFPSZrmbikz 6504 +VSHUFPSZrmi 6505 +VSHUFPSZrmik 6506 +VSHUFPSZrmikz 6507 +VSHUFPSZrri 6508 +VSHUFPSZrrik 6509 +VSHUFPSZrrikz 6510 +VSHUFPSrmi 6511 +VSHUFPSrri 6512 +VSM 6513 +VSQRTBF 6514 +VSQRTPDYm 6515 +VSQRTPDYr 6516 +VSQRTPDZ 6517 +VSQRTPDZm 6518 +VSQRTPDZmb 6519 +VSQRTPDZmbk 6520 +VSQRTPDZmbkz 6521 +VSQRTPDZmk 6522 +VSQRTPDZmkz 6523 +VSQRTPDZr 6524 +VSQRTPDZrb 6525 +VSQRTPDZrbk 6526 +VSQRTPDZrbkz 6527 +VSQRTPDZrk 6528 +VSQRTPDZrkz 6529 +VSQRTPDm 6530 +VSQRTPDr 6531 +VSQRTPHZ 6532 +VSQRTPHZm 6533 +VSQRTPHZmb 6534 +VSQRTPHZmbk 6535 +VSQRTPHZmbkz 6536 +VSQRTPHZmk 6537 +VSQRTPHZmkz 6538 +VSQRTPHZr 6539 +VSQRTPHZrb 6540 +VSQRTPHZrbk 6541 +VSQRTPHZrbkz 6542 +VSQRTPHZrk 6543 +VSQRTPHZrkz 6544 +VSQRTPSYm 6545 +VSQRTPSYr 6546 +VSQRTPSZ 6547 +VSQRTPSZm 6548 +VSQRTPSZmb 6549 +VSQRTPSZmbk 6550 +VSQRTPSZmbkz 6551 +VSQRTPSZmk 6552 +VSQRTPSZmkz 6553 +VSQRTPSZr 6554 +VSQRTPSZrb 6555 +VSQRTPSZrbk 6556 +VSQRTPSZrbkz 6557 +VSQRTPSZrk 6558 +VSQRTPSZrkz 6559 +VSQRTPSm 6560 +VSQRTPSr 6561 +VSQRTSDZm 6562 +VSQRTSDZm_Int 6563 +VSQRTSDZmk_Int 6564 +VSQRTSDZmkz_Int 6565 +VSQRTSDZr 6566 +VSQRTSDZr_Int 6567 +VSQRTSDZrb_Int 6568 +VSQRTSDZrbk_Int 6569 +VSQRTSDZrbkz_Int 6570 +VSQRTSDZrk_Int 6571 +VSQRTSDZrkz_Int 6572 +VSQRTSDm 6573 +VSQRTSDm_Int 6574 +VSQRTSDr 6575 +VSQRTSDr_Int 6576 +VSQRTSHZm 6577 +VSQRTSHZm_Int 6578 +VSQRTSHZmk_Int 6579 +VSQRTSHZmkz_Int 6580 +VSQRTSHZr 6581 +VSQRTSHZr_Int 6582 +VSQRTSHZrb_Int 6583 +VSQRTSHZrbk_Int 6584 +VSQRTSHZrbkz_Int 6585 +VSQRTSHZrk_Int 6586 +VSQRTSHZrkz_Int 6587 +VSQRTSSZm 6588 +VSQRTSSZm_Int 6589 +VSQRTSSZmk_Int 6590 +VSQRTSSZmkz_Int 6591 +VSQRTSSZr 6592 +VSQRTSSZr_Int 6593 +VSQRTSSZrb_Int 6594 +VSQRTSSZrbk_Int 6595 +VSQRTSSZrbkz_Int 6596 +VSQRTSSZrk_Int 6597 +VSQRTSSZrkz_Int 6598 +VSQRTSSm 6599 +VSQRTSSm_Int 6600 +VSQRTSSr 6601 +VSQRTSSr_Int 6602 +VSTMXCSR 6603 +VSUBBF 6604 +VSUBPDYrm 6605 +VSUBPDYrr 6606 +VSUBPDZ 6607 +VSUBPDZrm 6608 +VSUBPDZrmb 6609 +VSUBPDZrmbk 6610 +VSUBPDZrmbkz 6611 +VSUBPDZrmk 6612 +VSUBPDZrmkz 6613 +VSUBPDZrr 6614 +VSUBPDZrrb 6615 +VSUBPDZrrbk 6616 +VSUBPDZrrbkz 6617 +VSUBPDZrrk 6618 +VSUBPDZrrkz 6619 +VSUBPDrm 6620 +VSUBPDrr 6621 +VSUBPHZ 6622 +VSUBPHZrm 6623 +VSUBPHZrmb 6624 +VSUBPHZrmbk 6625 +VSUBPHZrmbkz 6626 +VSUBPHZrmk 6627 +VSUBPHZrmkz 6628 +VSUBPHZrr 6629 +VSUBPHZrrb 6630 +VSUBPHZrrbk 6631 +VSUBPHZrrbkz 6632 +VSUBPHZrrk 6633 +VSUBPHZrrkz 6634 +VSUBPSYrm 6635 +VSUBPSYrr 6636 +VSUBPSZ 6637 +VSUBPSZrm 6638 +VSUBPSZrmb 6639 +VSUBPSZrmbk 6640 +VSUBPSZrmbkz 6641 +VSUBPSZrmk 6642 +VSUBPSZrmkz 6643 +VSUBPSZrr 6644 +VSUBPSZrrb 6645 +VSUBPSZrrbk 6646 +VSUBPSZrrbkz 6647 +VSUBPSZrrk 6648 +VSUBPSZrrkz 6649 +VSUBPSrm 6650 +VSUBPSrr 6651 +VSUBSDZrm 6652 +VSUBSDZrm_Int 6653 +VSUBSDZrmk_Int 6654 +VSUBSDZrmkz_Int 6655 +VSUBSDZrr 6656 +VSUBSDZrr_Int 6657 +VSUBSDZrrb_Int 6658 +VSUBSDZrrbk_Int 6659 +VSUBSDZrrbkz_Int 6660 +VSUBSDZrrk_Int 6661 +VSUBSDZrrkz_Int 6662 +VSUBSDrm 6663 +VSUBSDrm_Int 6664 +VSUBSDrr 6665 +VSUBSDrr_Int 6666 +VSUBSHZrm 6667 +VSUBSHZrm_Int 6668 +VSUBSHZrmk_Int 6669 +VSUBSHZrmkz_Int 6670 +VSUBSHZrr 6671 +VSUBSHZrr_Int 6672 +VSUBSHZrrb_Int 6673 +VSUBSHZrrbk_Int 6674 +VSUBSHZrrbkz_Int 6675 +VSUBSHZrrk_Int 6676 +VSUBSHZrrkz_Int 6677 +VSUBSSZrm 6678 +VSUBSSZrm_Int 6679 +VSUBSSZrmk_Int 6680 +VSUBSSZrmkz_Int 6681 +VSUBSSZrr 6682 +VSUBSSZrr_Int 6683 +VSUBSSZrrb_Int 6684 +VSUBSSZrrbk_Int 6685 +VSUBSSZrrbkz_Int 6686 +VSUBSSZrrk_Int 6687 +VSUBSSZrrkz_Int 6688 +VSUBSSrm 6689 +VSUBSSrm_Int 6690 +VSUBSSrr 6691 +VSUBSSrr_Int 6692 +VTESTPDYrm 6693 +VTESTPDYrr 6694 +VTESTPDrm 6695 +VTESTPDrr 6696 +VTESTPSYrm 6697 +VTESTPSYrr 6698 +VTESTPSrm 6699 +VTESTPSrr 6700 +VUCOMISDZrm 6701 +VUCOMISDZrm_Int 6702 +VUCOMISDZrr 6703 +VUCOMISDZrr_Int 6704 +VUCOMISDZrrb 6705 +VUCOMISDrm 6706 +VUCOMISDrm_Int 6707 +VUCOMISDrr 6708 +VUCOMISDrr_Int 6709 +VUCOMISHZrm 6710 +VUCOMISHZrm_Int 6711 +VUCOMISHZrr 6712 +VUCOMISHZrr_Int 6713 +VUCOMISHZrrb 6714 +VUCOMISSZrm 6715 +VUCOMISSZrm_Int 6716 +VUCOMISSZrr 6717 +VUCOMISSZrr_Int 6718 +VUCOMISSZrrb 6719 +VUCOMISSrm 6720 +VUCOMISSrm_Int 6721 +VUCOMISSrr 6722 +VUCOMISSrr_Int 6723 +VUCOMXSDZrm 6724 +VUCOMXSDZrm_Int 6725 +VUCOMXSDZrr 6726 +VUCOMXSDZrr_Int 6727 +VUCOMXSDZrrb_Int 6728 +VUCOMXSHZrm 6729 +VUCOMXSHZrm_Int 6730 +VUCOMXSHZrr 6731 +VUCOMXSHZrr_Int 6732 +VUCOMXSHZrrb_Int 6733 +VUCOMXSSZrm 6734 +VUCOMXSSZrm_Int 6735 +VUCOMXSSZrr 6736 +VUCOMXSSZrr_Int 6737 +VUCOMXSSZrrb_Int 6738 +VUNPCKHPDYrm 6739 +VUNPCKHPDYrr 6740 +VUNPCKHPDZ 6741 +VUNPCKHPDZrm 6742 +VUNPCKHPDZrmb 6743 +VUNPCKHPDZrmbk 6744 +VUNPCKHPDZrmbkz 6745 +VUNPCKHPDZrmk 6746 +VUNPCKHPDZrmkz 6747 +VUNPCKHPDZrr 6748 +VUNPCKHPDZrrk 6749 +VUNPCKHPDZrrkz 6750 +VUNPCKHPDrm 6751 +VUNPCKHPDrr 6752 +VUNPCKHPSYrm 6753 +VUNPCKHPSYrr 6754 +VUNPCKHPSZ 6755 +VUNPCKHPSZrm 6756 +VUNPCKHPSZrmb 6757 +VUNPCKHPSZrmbk 6758 +VUNPCKHPSZrmbkz 6759 +VUNPCKHPSZrmk 6760 +VUNPCKHPSZrmkz 6761 +VUNPCKHPSZrr 6762 +VUNPCKHPSZrrk 6763 +VUNPCKHPSZrrkz 6764 +VUNPCKHPSrm 6765 +VUNPCKHPSrr 6766 +VUNPCKLPDYrm 6767 +VUNPCKLPDYrr 6768 +VUNPCKLPDZ 6769 +VUNPCKLPDZrm 6770 +VUNPCKLPDZrmb 6771 +VUNPCKLPDZrmbk 6772 +VUNPCKLPDZrmbkz 6773 +VUNPCKLPDZrmk 6774 +VUNPCKLPDZrmkz 6775 +VUNPCKLPDZrr 6776 +VUNPCKLPDZrrk 6777 +VUNPCKLPDZrrkz 6778 +VUNPCKLPDrm 6779 +VUNPCKLPDrr 6780 +VUNPCKLPSYrm 6781 +VUNPCKLPSYrr 6782 +VUNPCKLPSZ 6783 +VUNPCKLPSZrm 6784 +VUNPCKLPSZrmb 6785 +VUNPCKLPSZrmbk 6786 +VUNPCKLPSZrmbkz 6787 +VUNPCKLPSZrmk 6788 +VUNPCKLPSZrmkz 6789 +VUNPCKLPSZrr 6790 +VUNPCKLPSZrrk 6791 +VUNPCKLPSZrrkz 6792 +VUNPCKLPSrm 6793 +VUNPCKLPSrr 6794 +VXORPDYrm 6795 +VXORPDYrr 6796 +VXORPDZ 6797 +VXORPDZrm 6798 +VXORPDZrmb 6799 +VXORPDZrmbk 6800 +VXORPDZrmbkz 6801 +VXORPDZrmk 6802 +VXORPDZrmkz 6803 +VXORPDZrr 6804 +VXORPDZrrk 6805 +VXORPDZrrkz 6806 +VXORPDrm 6807 +VXORPDrr 6808 +VXORPSYrm 6809 +VXORPSYrr 6810 +VXORPSZ 6811 +VXORPSZrm 6812 +VXORPSZrmb 6813 +VXORPSZrmbk 6814 +VXORPSZrmbkz 6815 +VXORPSZrmk 6816 +VXORPSZrmkz 6817 +VXORPSZrr 6818 +VXORPSZrrk 6819 +VXORPSZrrkz 6820 +VXORPSrm 6821 +VXORPSrr 6822 +VZEROALL 6823 +VZEROUPPER 6824 +V_SET 6825 +V_SETALLONES 6826 +WAIT 6827 +WBINVD 6828 +WBNOINVD 6829 +WRFLAGS 6830 +WRFSBASE 6831 +WRGSBASE 6832 +WRMSR 6833 +WRMSRLIST 6834 +WRMSRNS 6835 +WRMSRNSir 6836 +WRMSRNSir_EVEX 6837 +WRPKRUr 6838 +WRSSD 6839 +WRSSD_EVEX 6840 +WRSSQ 6841 +WRSSQ_EVEX 6842 +WRUSSD 6843 +WRUSSD_EVEX 6844 +WRUSSQ 6845 +WRUSSQ_EVEX 6846 +XABORT 6847 +XABORT_DEF 6848 +XACQUIRE_PREFIX 6849 +XADD 6850 +XAM_F 6851 +XAM_Fp 6852 +XBEGIN 6853 +XCHG 6854 +XCH_F 6855 +XCRYPTCBC 6856 +XCRYPTCFB 6857 +XCRYPTCTR 6858 +XCRYPTECB 6859 +XCRYPTOFB 6860 +XEND 6861 +XGETBV 6862 +XLAT 6863 +XOR 6864 +XORPDrm 6865 +XORPDrr 6866 +XORPSrm 6867 +XORPSrr 6868 +XRELEASE_PREFIX 6869 +XRESLDTRK 6870 +XRSTOR 6871 +XRSTORS 6872 +XSAVE 6873 +XSAVEC 6874 +XSAVEOPT 6875 +XSAVES 6876 +XSETBV 6877 +XSHA 6878 +XSTORE 6879 +XSUSLDTRK 6880 +XTEST 6881 +Immediate 6882 +CImmediate 6883 +FPImmediate 6884 +MBB 6885 +FrameIndex 6886 +ConstantPoolIndex 6887 +TargetIndex 6888 +JumpTableIndex 6889 +ExternalSymbol 6890 +GlobalAddress 6891 +BlockAddress 6892 +RegisterMask 6893 +RegisterLiveOut 6894 +Metadata 6895 +MCSymbol 6896 +CFIIndex 6897 +IntrinsicID 6898 +Predicate 6899 +ShuffleMask 6900 +PhyReg_GR8 6901 +PhyReg_GRH8 6902 +PhyReg_GR8_NOREX2 6903 +PhyReg_GR8_NOREX 6904 +PhyReg_GR8_ABCD_H 6905 +PhyReg_GR8_ABCD_L 6906 +PhyReg_GRH16 6907 +PhyReg_GR16 6908 +PhyReg_GR16_NOREX2 6909 +PhyReg_GR16_NOREX 6910 +PhyReg_VK1 6911 +PhyReg_VK16 6912 +PhyReg_VK2 6913 +PhyReg_VK4 6914 +PhyReg_VK8 6915 +PhyReg_VK16WM 6916 +PhyReg_VK1WM 6917 +PhyReg_VK2WM 6918 +PhyReg_VK4WM 6919 +PhyReg_VK8WM 6920 +PhyReg_SEGMENT_REG 6921 +PhyReg_GR16_ABCD 6922 +PhyReg_FPCCR 6923 +PhyReg_FR16X 6924 +PhyReg_FR16 6925 +PhyReg_VK16PAIR 6926 +PhyReg_VK1PAIR 6927 +PhyReg_VK2PAIR 6928 +PhyReg_VK4PAIR 6929 +PhyReg_VK8PAIR 6930 +PhyReg_VK1PAIR_with_sub_mask_0_in_VK1WM 6931 +PhyReg_LOW32_ADDR_ACCESS_RBP 6932 +PhyReg_LOW32_ADDR_ACCESS 6933 +PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 6934 +PhyReg_FR32X 6935 +PhyReg_GR32 6936 +PhyReg_GR32_NOSP 6937 +PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 6938 +PhyReg_DEBUG_REG 6939 +PhyReg_FR32 6940 +PhyReg_GR32_NOREX2 6941 +PhyReg_GR32_NOREX2_NOSP 6942 +PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 6943 +PhyReg_GR32_NOREX 6944 +PhyReg_VK32 6945 +PhyReg_GR32_NOREX_NOSP 6946 +PhyReg_RFP32 6947 +PhyReg_VK32WM 6948 +PhyReg_GR32_ABCD 6949 +PhyReg_GR32_TC 6950 +PhyReg_GR32_ABCD_and_GR32_TC 6951 +PhyReg_GR32_AD 6952 +PhyReg_GR32_ArgRef 6953 +PhyReg_GR32_BPSP 6954 +PhyReg_GR32_BSI 6955 +PhyReg_GR32_CB 6956 +PhyReg_GR32_DC 6957 +PhyReg_GR32_DIBP 6958 +PhyReg_GR32_SIDI 6959 +PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 6960 +PhyReg_CCR 6961 +PhyReg_DFCCR 6962 +PhyReg_GR32_ABCD_and_GR32_BSI 6963 +PhyReg_GR32_AD_and_GR32_ArgRef 6964 +PhyReg_GR32_ArgRef_and_GR32_CB 6965 +PhyReg_GR32_BPSP_and_GR32_DIBP 6966 +PhyReg_GR32_BPSP_and_GR32_TC 6967 +PhyReg_GR32_BSI_and_GR32_SIDI 6968 +PhyReg_GR32_DIBP_and_GR32_SIDI 6969 +PhyReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 6970 +PhyReg_LOW32_ADDR_ACCESS_with_sub_32bit 6971 +PhyReg_RFP64 6972 +PhyReg_GR64 6973 +PhyReg_FR64X 6974 +PhyReg_GR64_with_sub_8bit 6975 +PhyReg_GR64_NOSP 6976 +PhyReg_GR64_NOREX2 6977 +PhyReg_CONTROL_REG 6978 +PhyReg_FR64 6979 +PhyReg_GR64_with_sub_16bit_in_GR16_NOREX2 6980 +PhyReg_GR64_NOREX2_NOSP 6981 +PhyReg_GR64PLTSafe 6982 +PhyReg_GR64_TC 6983 +PhyReg_GR64_NOREX 6984 +PhyReg_GR64_TCW64 6985 +PhyReg_GR64_TC_with_sub_8bit 6986 +PhyReg_GR64_NOREX2_NOSP_and_GR64_TC 6987 +PhyReg_GR64_TCW64_with_sub_8bit 6988 +PhyReg_GR64_TC_and_GR64_TCW64 6989 +PhyReg_GR64_with_sub_16bit_in_GR16_NOREX 6990 +PhyReg_VK64 6991 +PhyReg_VR64 6992 +PhyReg_GR64PLTSafe_and_GR64_TC 6993 +PhyReg_GR64_NOREX2_NOSP_and_GR64_TCW64 6994 +PhyReg_GR64_NOREX_NOSP 6995 +PhyReg_GR64_NOREX_and_GR64_TC 6996 +PhyReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 6997 +PhyReg_VK64WM 6998 +PhyReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 6999 +PhyReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7000 +PhyReg_GR64PLTSafe_and_GR64_TCW64 7001 +PhyReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7002 +PhyReg_GR64_NOREX_and_GR64_TCW64 7003 +PhyReg_GR64_ABCD 7004 +PhyReg_GR64_with_sub_32bit_in_GR32_TC 7005 +PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7006 +PhyReg_GR64_AD 7007 +PhyReg_GR64_ArgRef 7008 +PhyReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7009 +PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef 7010 +PhyReg_GR64_with_sub_32bit_in_GR32_BPSP 7011 +PhyReg_GR64_with_sub_32bit_in_GR32_BSI 7012 +PhyReg_GR64_with_sub_32bit_in_GR32_CB 7013 +PhyReg_GR64_with_sub_32bit_in_GR32_DIBP 7014 +PhyReg_GR64_with_sub_32bit_in_GR32_SIDI 7015 +PhyReg_GR64_A 7016 +PhyReg_GR64_ArgRef_and_GR64_TC 7017 +PhyReg_GR64_and_LOW32_ADDR_ACCESS 7018 +PhyReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7019 +PhyReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7020 +PhyReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7021 +PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7022 +PhyReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7023 +PhyReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7024 +PhyReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7025 +PhyReg_RST 7026 +PhyReg_RFP80 7027 +PhyReg_RFP80_7 7028 +PhyReg_VR128X 7029 +PhyReg_VR128 7030 +PhyReg_VR256X 7031 +PhyReg_VR256 7032 +PhyReg_VR512 7033 +PhyReg_VR512_0_15 7034 +PhyReg_TILE 7035 +PhyReg_TILEPAIR 7036 +VirtReg_GR8 7037 +VirtReg_GRH8 7038 +VirtReg_GR8_NOREX2 7039 +VirtReg_GR8_NOREX 7040 +VirtReg_GR8_ABCD_H 7041 +VirtReg_GR8_ABCD_L 7042 +VirtReg_GRH16 7043 +VirtReg_GR16 7044 +VirtReg_GR16_NOREX2 7045 +VirtReg_GR16_NOREX 7046 +VirtReg_VK1 7047 +VirtReg_VK16 7048 +VirtReg_VK2 7049 +VirtReg_VK4 7050 +VirtReg_VK8 7051 +VirtReg_VK16WM 7052 +VirtReg_VK1WM 7053 +VirtReg_VK2WM 7054 +VirtReg_VK4WM 7055 +VirtReg_VK8WM 7056 +VirtReg_SEGMENT_REG 7057 +VirtReg_GR16_ABCD 7058 +VirtReg_FPCCR 7059 +VirtReg_FR16X 7060 +VirtReg_FR16 7061 +VirtReg_VK16PAIR 7062 +VirtReg_VK1PAIR 7063 +VirtReg_VK2PAIR 7064 +VirtReg_VK4PAIR 7065 +VirtReg_VK8PAIR 7066 +VirtReg_VK1PAIR_with_sub_mask_0_in_VK1WM 7067 +VirtReg_LOW32_ADDR_ACCESS_RBP 7068 +VirtReg_LOW32_ADDR_ACCESS 7069 +VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit 7070 +VirtReg_FR32X 7071 +VirtReg_GR32 7072 +VirtReg_GR32_NOSP 7073 +VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX2 7074 +VirtReg_DEBUG_REG 7075 +VirtReg_FR32 7076 +VirtReg_GR32_NOREX2 7077 +VirtReg_GR32_NOREX2_NOSP 7078 +VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_16bit_in_GR16_NOREX 7079 +VirtReg_GR32_NOREX 7080 +VirtReg_VK32 7081 +VirtReg_GR32_NOREX_NOSP 7082 +VirtReg_RFP32 7083 +VirtReg_VK32WM 7084 +VirtReg_GR32_ABCD 7085 +VirtReg_GR32_TC 7086 +VirtReg_GR32_ABCD_and_GR32_TC 7087 +VirtReg_GR32_AD 7088 +VirtReg_GR32_ArgRef 7089 +VirtReg_GR32_BPSP 7090 +VirtReg_GR32_BSI 7091 +VirtReg_GR32_CB 7092 +VirtReg_GR32_DC 7093 +VirtReg_GR32_DIBP 7094 +VirtReg_GR32_SIDI 7095 +VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_32bit 7096 +VirtReg_CCR 7097 +VirtReg_DFCCR 7098 +VirtReg_GR32_ABCD_and_GR32_BSI 7099 +VirtReg_GR32_AD_and_GR32_ArgRef 7100 +VirtReg_GR32_ArgRef_and_GR32_CB 7101 +VirtReg_GR32_BPSP_and_GR32_DIBP 7102 +VirtReg_GR32_BPSP_and_GR32_TC 7103 +VirtReg_GR32_BSI_and_GR32_SIDI 7104 +VirtReg_GR32_DIBP_and_GR32_SIDI 7105 +VirtReg_LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit 7106 +VirtReg_LOW32_ADDR_ACCESS_with_sub_32bit 7107 +VirtReg_RFP64 7108 +VirtReg_GR64 7109 +VirtReg_FR64X 7110 +VirtReg_GR64_with_sub_8bit 7111 +VirtReg_GR64_NOSP 7112 +VirtReg_GR64_NOREX2 7113 +VirtReg_CONTROL_REG 7114 +VirtReg_FR64 7115 +VirtReg_GR64_with_sub_16bit_in_GR16_NOREX2 7116 +VirtReg_GR64_NOREX2_NOSP 7117 +VirtReg_GR64PLTSafe 7118 +VirtReg_GR64_TC 7119 +VirtReg_GR64_NOREX 7120 +VirtReg_GR64_TCW64 7121 +VirtReg_GR64_TC_with_sub_8bit 7122 +VirtReg_GR64_NOREX2_NOSP_and_GR64_TC 7123 +VirtReg_GR64_TCW64_with_sub_8bit 7124 +VirtReg_GR64_TC_and_GR64_TCW64 7125 +VirtReg_GR64_with_sub_16bit_in_GR16_NOREX 7126 +VirtReg_VK64 7127 +VirtReg_VR64 7128 +VirtReg_GR64PLTSafe_and_GR64_TC 7129 +VirtReg_GR64_NOREX2_NOSP_and_GR64_TCW64 7130 +VirtReg_GR64_NOREX_NOSP 7131 +VirtReg_GR64_NOREX_and_GR64_TC 7132 +VirtReg_GR64_TCW64_and_GR64_TC_with_sub_8bit 7133 +VirtReg_VK64WM 7134 +VirtReg_GR64_TC_and_GR64_NOREX2_NOSP_and_GR64_TCW64 7135 +VirtReg_GR64_TC_and_GR64_with_sub_16bit_in_GR16_NOREX 7136 +VirtReg_GR64PLTSafe_and_GR64_TCW64 7137 +VirtReg_GR64_NOREX_and_GR64PLTSafe_and_GR64_TC 7138 +VirtReg_GR64_NOREX_and_GR64_TCW64 7139 +VirtReg_GR64_ABCD 7140 +VirtReg_GR64_with_sub_32bit_in_GR32_TC 7141 +VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_TC 7142 +VirtReg_GR64_AD 7143 +VirtReg_GR64_ArgRef 7144 +VirtReg_GR64_and_LOW32_ADDR_ACCESS_RBP 7145 +VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef 7146 +VirtReg_GR64_with_sub_32bit_in_GR32_BPSP 7147 +VirtReg_GR64_with_sub_32bit_in_GR32_BSI 7148 +VirtReg_GR64_with_sub_32bit_in_GR32_CB 7149 +VirtReg_GR64_with_sub_32bit_in_GR32_DIBP 7150 +VirtReg_GR64_with_sub_32bit_in_GR32_SIDI 7151 +VirtReg_GR64_A 7152 +VirtReg_GR64_ArgRef_and_GR64_TC 7153 +VirtReg_GR64_and_LOW32_ADDR_ACCESS 7154 +VirtReg_GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_BSI 7155 +VirtReg_GR64_with_sub_32bit_in_GR32_AD_and_GR32_ArgRef 7156 +VirtReg_GR64_with_sub_32bit_in_GR32_ArgRef_and_GR32_CB 7157 +VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_DIBP 7158 +VirtReg_GR64_with_sub_32bit_in_GR32_BPSP_and_GR32_TC 7159 +VirtReg_GR64_with_sub_32bit_in_GR32_BSI_and_GR32_SIDI 7160 +VirtReg_GR64_with_sub_32bit_in_GR32_DIBP_and_GR32_SIDI 7161 +VirtReg_RST 7162 +VirtReg_RFP80 7163 +VirtReg_RFP80_7 7164 +VirtReg_VR128X 7165 +VirtReg_VR128 7166 +VirtReg_VR256X 7167 +VirtReg_VR256 7168 +VirtReg_VR512 7169 +VirtReg_VR512_0_15 7170 +VirtReg_TILE 7171 +VirtReg_TILEPAIR 7172 diff --git a/llvm/test/tools/llvm-ir2vec/triplets.mir b/llvm/test/tools/llvm-ir2vec/triplets.mir new file mode 100644 index 0000000000000..274984ae9e91d --- /dev/null +++ b/llvm/test/tools/llvm-ir2vec/triplets.mir @@ -0,0 +1,61 @@ +# REQUIRES: x86_64-linux +# RUN: llvm-ir2vec triplets --mode=mir %s -o 2>&1 %t1.log +# RUN: diff %S/output/reference_triplets.txt %t1.log + +--- | + target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" + target triple = "x86_64-unknown-linux-gnu" + + define dso_local noundef i32 @add_function(i32 noundef %a, i32 noundef %b) { + entry: + %sum = add nsw i32 %a, %b + ret i32 %sum + } + + define dso_local noundef i32 @mul_function(i32 noundef %x, i32 noundef %y) { + entry: + %product = mul nsw i32 %x, %y + ret i32 %product + } +... +--- +name: add_function +alignment: 16 +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr32 } + - { id: 2, class: gr32 } +liveins: + - { reg: '$edi', virtual-reg: '%0' } + - { reg: '$esi', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $edi, $esi + + %1:gr32 = COPY $esi + %0:gr32 = COPY $edi + %2:gr32 = nsw ADD32rr %0, %1, implicit-def dead $eflags + $eax = COPY %2 + RET 0, $eax + +--- +name: mul_function +alignment: 16 +tracksRegLiveness: true +registers: + - { id: 0, class: gr32 } + - { id: 1, class: gr32 } + - { id: 2, class: gr32 } +liveins: + - { reg: '$edi', virtual-reg: '%0' } + - { reg: '$esi', virtual-reg: '%1' } +body: | + bb.0.entry: + liveins: $edi, $esi + + %1:gr32 = COPY $esi + %0:gr32 = COPY $edi + %2:gr32 = nsw IMUL32rr %0, %1, implicit-def dead $eflags + $eax = COPY %2 + RET 0, $eax diff --git a/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp b/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp index a723d379129e6..7402782bfd404 100644 --- a/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp +++ b/llvm/tools/llvm-ir2vec/llvm-ir2vec.cpp @@ -19,12 +19,22 @@ /// Generates numeric triplets (head, tail, relation) for vocabulary /// training. Output format: MAX_RELATION=N header followed by /// head\ttail\trelation lines. Relations: 0=Type, 1=Next, 2+=Arg0,Arg1,... -/// Usage: llvm-ir2vec triplets input.bc -o train2id.txt +/// +/// For LLVM IR: +/// llvm-ir2vec triplets input.bc -o train2id.txt +/// +/// For Machine IR: +/// llvm-ir2vec triplets -mode=mir input.mir -o train2id.txt /// /// 2. Entity Mappings (entities): /// Generates entity mappings for vocabulary training. /// Output format: header followed by entity\tid lines. -/// Usage: llvm-ir2vec entities input.bc -o entity2id.txt +/// +/// For LLVM IR: +/// llvm-ir2vec entities input.bc -o entity2id.txt +/// +/// For Machine IR: +/// llvm-ir2vec entities -mode=mir input.mir -o entity2id.txt /// /// 3. Embedding Generation (embeddings): /// Generates IR2Vec/MIR2Vec embeddings using a trained vocabulary. @@ -67,6 +77,8 @@ #include "llvm/CodeGen/MIRParser/MIRParser.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineModuleInfo.h" +#include "llvm/CodeGen/TargetInstrInfo.h" +#include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/TargetSelect.h" #include "llvm/Support/WithColor.h" @@ -106,11 +118,10 @@ static cl::SubCommand "Generate embeddings using trained vocabulary"); // Common options -static cl::opt - InputFilename(cl::Positional, - cl::desc(""), - cl::init("-"), cl::sub(TripletsSubCmd), - cl::sub(EmbeddingsSubCmd), cl::cat(CommonCategory)); +static cl::opt InputFilename( + cl::Positional, cl::desc(""), + cl::init("-"), cl::sub(TripletsSubCmd), cl::sub(EntitiesSubCmd), + cl::sub(EmbeddingsSubCmd), cl::cat(CommonCategory)); static cl::opt OutputFilename("o", cl::desc("Output filename"), cl::value_desc("filename"), @@ -345,6 +356,12 @@ Error processModule(Module &M, raw_ostream &OS) { namespace mir2vec { +/// Relation types for MIR2Vec triplet generation +enum MIRRelationType { + MIRNextRelation = 0, ///< Sequential instruction relationship + MIRArgRelation = 1 ///< Instruction to operand relationship (ArgRelation + N) +}; + /// Helper class for MIR2Vec embedding generation class MIR2VecTool { private: @@ -354,7 +371,7 @@ class MIR2VecTool { public: explicit MIR2VecTool(MachineModuleInfo &MMI) : MMI(MMI) {} - /// Initialize MIR2Vec vocabulary + /// Initialize MIR2Vec vocabulary from file (for embeddings generation) bool initializeVocabulary(const Module &M) { MIR2VecVocabProvider Provider(MMI); auto VocabOrErr = Provider.getVocabulary(M); @@ -368,6 +385,146 @@ class MIR2VecTool { return true; } + /// Initialize vocabulary with layout information only. + /// This creates a minimal vocabulary with correct layout but no actual + /// embeddings. Sufficient for generating training data and entity mappings. + /// + /// Note: Requires target-specific information from the first machine function + /// to determine the vocabulary layout (number of opcodes, register classes). + /// + /// FIXME: Use --target option to get target info directly, avoiding the need + /// to parse machine functions for pre-training operations. + bool initializeVocabularyForLayout(const Module &M) { + for (const Function &F : M) { + if (F.isDeclaration()) + continue; + + MachineFunction *MF = MMI.getMachineFunction(F); + if (!MF) + continue; + + const TargetInstrInfo &TII = *MF->getSubtarget().getInstrInfo(); + const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo(); + const MachineRegisterInfo &MRI = MF->getRegInfo(); + + auto VocabOrErr = + MIRVocabulary::createDummyVocabForTest(TII, TRI, MRI, 1); + if (!VocabOrErr) { + WithColor::error(errs(), ToolName) + << "Failed to create dummy vocabulary - " + << toString(VocabOrErr.takeError()) << "\n"; + return false; + } + Vocab = std::make_unique(std::move(*VocabOrErr)); + return true; + } + + WithColor::error(errs(), ToolName) + << "No machine functions found to initialize vocabulary\n"; + return false; + } + + /// Generate triplets for the module + /// Output format: MAX_RELATION=N header followed by relationships + void generateTriplets(const Module &M, raw_ostream &OS) const { + unsigned MaxRelation = MIRNextRelation; // Track maximum relation ID + std::string Relationships; + raw_string_ostream RelOS(Relationships); + + for (const Function &F : M) { + if (F.isDeclaration()) + continue; + + MachineFunction *MF = MMI.getMachineFunction(F); + if (!MF) { + WithColor::warning(errs(), ToolName) + << "No MachineFunction for " << F.getName() << "\n"; + continue; + } + + unsigned FuncMaxRelation = generateTriplets(*MF, RelOS); + MaxRelation = std::max(MaxRelation, FuncMaxRelation); + } + + RelOS.flush(); + + // Write metadata header followed by relationships + OS << "MAX_RELATION=" << MaxRelation << '\n'; + OS << Relationships; + } + + /// Generate triplets for a single machine function + /// Returns the maximum relation ID used in this function + unsigned generateTriplets(const MachineFunction &MF, raw_ostream &OS) const { + unsigned MaxRelation = MIRNextRelation; + unsigned PrevOpcode = 0; + bool HasPrevOpcode = false; + + if (!Vocab) { + WithColor::error(errs(), ToolName) + << "MIR Vocabulary must be initialized for triplet generation.\n"; + return MaxRelation; + } + + for (const MachineBasicBlock &MBB : MF) { + for (const MachineInstr &MI : MBB) { + // Skip debug instructions + if (MI.isDebugInstr()) + continue; + + // Get opcode entity ID + unsigned OpcodeID = Vocab->getEntityIDForOpcode(MI.getOpcode()); + + // Add "Next" relationship with previous instruction + if (HasPrevOpcode) { + OS << PrevOpcode << '\t' << OpcodeID << '\t' << MIRNextRelation + << '\n'; + LLVM_DEBUG(dbgs() + << Vocab->getStringKey(PrevOpcode) << '\t' + << Vocab->getStringKey(OpcodeID) << '\t' << "Next\n"); + } + + // Add "Arg" relationships for operands + unsigned ArgIndex = 0; + for (const MachineOperand &MO : MI.operands()) { + auto OperandID = Vocab->getEntityIDForMachineOperand(MO); + unsigned RelationID = MIRArgRelation + ArgIndex; + OS << OpcodeID << '\t' << OperandID << '\t' << RelationID << '\n'; + LLVM_DEBUG({ + std::string OperandStr = Vocab->getStringKey(OperandID); + dbgs() << Vocab->getStringKey(OpcodeID) << '\t' << OperandStr + << '\t' << "Arg" << ArgIndex << '\n'; + }); + + ++ArgIndex; + } + + // Update MaxRelation if there were operands + if (ArgIndex > 0) + MaxRelation = std::max(MaxRelation, MIRArgRelation + ArgIndex - 1); + + PrevOpcode = OpcodeID; + HasPrevOpcode = true; + } + } + + return MaxRelation; + } + + /// Generate entity mappings with vocabulary + void generateEntityMappings(raw_ostream &OS) const { + if (!Vocab) { + WithColor::error(errs(), ToolName) + << "Vocabulary must be initialized for entity mappings.\n"; + return; + } + + const unsigned EntityCount = Vocab->getCanonicalSize(); + OS << EntityCount << "\n"; + for (unsigned EntityID = 0; EntityID < EntityCount; ++EntityID) + OS << Vocab->getStringKey(EntityID) << '\t' << EntityID << '\n'; + } + /// Generate embeddings for all machine functions in the module void generateEmbeddings(const Module &M, raw_ostream &OS) const { if (!Vocab) { @@ -538,38 +695,67 @@ int main(int argc, char **argv) { return 1; } - // Create MIR2Vec tool and initialize vocabulary + // Create MIR2Vec tool MIR2VecTool Tool(*MMI); - if (!Tool.initializeVocabulary(*M)) - return 1; + // Initialize vocabulary. For triplet/entity generation, only layout is + // needed For embedding generation, the full vocabulary is needed. + // + // Note: Unlike IR2Vec, MIR2Vec vocabulary initialization requires + // target-specific information for generating the vocabulary layout. So, we + // always initialize the vocabulary in this case. + if (TripletsSubCmd || EntitiesSubCmd) { + if (!Tool.initializeVocabularyForLayout(*M)) { + WithColor::error(errs(), ToolName) + << "Failed to initialize MIR2Vec vocabulary for layout.\n"; + return 1; + } + } else { + if (!Tool.initializeVocabulary(*M)) { + WithColor::error(errs(), ToolName) + << "Failed to initialize MIR2Vec vocabulary.\n"; + return 1; + } + } + assert(Tool.getVocabulary() && + "MIR2Vec vocabulary should be initialized at this point"); LLVM_DEBUG(dbgs() << "MIR2Vec vocabulary loaded successfully.\n" << "Vocabulary dimension: " << Tool.getVocabulary()->getDimension() << "\n" << "Vocabulary size: " << Tool.getVocabulary()->getCanonicalSize() << "\n"); - // Generate embeddings based on subcommand - if (!FunctionName.empty()) { - // Process single function - Function *F = M->getFunction(FunctionName); - if (!F) { - WithColor::error(errs(), ToolName) - << "Function '" << FunctionName << "' not found\n"; - return 1; - } + // Handle subcommands + if (TripletsSubCmd) { + Tool.generateTriplets(*M, OS); + } else if (EntitiesSubCmd) { + Tool.generateEntityMappings(OS); + } else if (EmbeddingsSubCmd) { + if (!FunctionName.empty()) { + // Process single function + Function *F = M->getFunction(FunctionName); + if (!F) { + WithColor::error(errs(), ToolName) + << "Function '" << FunctionName << "' not found\n"; + return 1; + } - MachineFunction *MF = MMI->getMachineFunction(*F); - if (!MF) { - WithColor::error(errs(), ToolName) - << "No MachineFunction for " << FunctionName << "\n"; - return 1; - } + MachineFunction *MF = MMI->getMachineFunction(*F); + if (!MF) { + WithColor::error(errs(), ToolName) + << "No MachineFunction for " << FunctionName << "\n"; + return 1; + } - Tool.generateEmbeddings(*MF, OS); + Tool.generateEmbeddings(*MF, OS); + } else { + // Process all functions + Tool.generateEmbeddings(*M, OS); + } } else { - // Process all functions - Tool.generateEmbeddings(*M, OS); + WithColor::error(errs(), ToolName) + << "Please specify a subcommand: triplets, entities, or embeddings\n"; + return 1; } return 0; From 83f751a001fa57dd8eaa60f08ed420e90170e11d Mon Sep 17 00:00:00 2001 From: Florian Mayer Date: Thu, 23 Oct 2025 10:59:55 -0700 Subject: [PATCH 31/31] [FlowSensitive] [StatusOr] [6/N] support pointer comparison (#164856) --- .../Models/UncheckedStatusOrAccessModel.cpp | 75 +++++++++++++++++++ ...ncheckedStatusOrAccessModelTestFixture.cpp | 57 ++++++++++++++ 2 files changed, 132 insertions(+) diff --git a/clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp b/clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp index 598d33a14f968..22465e664cdd3 100644 --- a/clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp +++ b/clang/lib/Analysis/FlowSensitive/Models/UncheckedStatusOrAccessModel.cpp @@ -168,6 +168,15 @@ static auto isNotOkStatusCall() { "::absl::UnimplementedError", "::absl::UnknownError")))); } +static auto isPointerComparisonOperatorCall(std::string operator_name) { + using namespace ::clang::ast_matchers; // NOLINT: Too many names + return binaryOperator(hasOperatorName(operator_name), + hasLHS(hasType(hasCanonicalType(pointerType( + pointee(anyOf(statusOrType(), statusType())))))), + hasRHS(hasType(hasCanonicalType(pointerType( + pointee(anyOf(statusOrType(), statusType()))))))); +} + static auto buildDiagnoseMatchSwitch(const UncheckedStatusOrAccessModelOptions &Options) { return CFGMatchSwitchBuilder(Expr)) + return dyn_cast(&PointerVal->getPointeeLoc()); + return nullptr; +} + +static BoolValue *evaluatePointerEquality(const Expr *LhsExpr, + const Expr *RhsExpr, + Environment &Env) { + assert(LhsExpr->getType()->isPointerType()); + assert(RhsExpr->getType()->isPointerType()); + RecordStorageLocation *LhsStatusLoc = nullptr; + RecordStorageLocation *RhsStatusLoc = nullptr; + if (isStatusOrType(LhsExpr->getType()->getPointeeType()) && + isStatusOrType(RhsExpr->getType()->getPointeeType())) { + auto *LhsStatusOrLoc = getPointeeLocation(*LhsExpr, Env); + auto *RhsStatusOrLoc = getPointeeLocation(*RhsExpr, Env); + if (LhsStatusOrLoc == nullptr || RhsStatusOrLoc == nullptr) + return nullptr; + LhsStatusLoc = &locForStatus(*LhsStatusOrLoc); + RhsStatusLoc = &locForStatus(*RhsStatusOrLoc); + } else if (isStatusType(LhsExpr->getType()->getPointeeType()) && + isStatusType(RhsExpr->getType()->getPointeeType())) { + LhsStatusLoc = getPointeeLocation(*LhsExpr, Env); + RhsStatusLoc = getPointeeLocation(*RhsExpr, Env); + } + if (LhsStatusLoc == nullptr || RhsStatusLoc == nullptr) + return nullptr; + auto &LhsOkVal = valForOk(*LhsStatusLoc, Env); + auto &RhsOkVal = valForOk(*RhsStatusLoc, Env); + auto &Res = Env.makeAtomicBoolValue(); + auto &A = Env.arena(); + Env.assume(A.makeImplies( + Res.formula(), A.makeEquals(LhsOkVal.formula(), RhsOkVal.formula()))); + return &Res; +} + +static void transferPointerComparisonOperator(const BinaryOperator *Expr, + LatticeTransferState &State, + bool IsNegative) { + auto *LhsAndRhsVal = + evaluatePointerEquality(Expr->getLHS(), Expr->getRHS(), State.Env); + if (LhsAndRhsVal == nullptr) + return; + + if (IsNegative) + State.Env.setValue(*Expr, State.Env.makeNot(*LhsAndRhsVal)); + else + State.Env.setValue(*Expr, *LhsAndRhsVal); +} + static void transferOkStatusCall(const CallExpr *Expr, const MatchFinder::MatchResult &, LatticeTransferState &State) { @@ -482,6 +543,20 @@ buildTransferMatchSwitch(ASTContext &Ctx, transferComparisonOperator(Expr, State, /*IsNegative=*/true); }) + .CaseOfCFGStmt( + isPointerComparisonOperatorCall("=="), + [](const BinaryOperator *Expr, const MatchFinder::MatchResult &, + LatticeTransferState &State) { + transferPointerComparisonOperator(Expr, State, + /*IsNegative=*/false); + }) + .CaseOfCFGStmt( + isPointerComparisonOperatorCall("!="), + [](const BinaryOperator *Expr, const MatchFinder::MatchResult &, + LatticeTransferState &State) { + transferPointerComparisonOperator(Expr, State, + /*IsNegative=*/true); + }) .CaseOfCFGStmt(isOkStatusCall(), transferOkStatusCall) .CaseOfCFGStmt(isNotOkStatusCall(), transferNotOkStatusCall) .Build(); diff --git a/clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp b/clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp index 4bb09d3ebaae8..fff79e52e0aaa 100644 --- a/clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp +++ b/clang/unittests/Analysis/FlowSensitive/UncheckedStatusOrAccessModelTestFixture.cpp @@ -2871,6 +2871,63 @@ TEST_P(UncheckedStatusOrAccessModelTest, EqualityCheck) { )cc"); } +TEST_P(UncheckedStatusOrAccessModelTest, PointerEqualityCheck) { + ExpectDiagnosticsFor( + R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target(STATUSOR_INT* x, STATUSOR_INT* y) { + if (x->ok()) { + if (x == y) + y->value(); + else + y->value(); // [[unsafe]] + } + } + )cc"); + ExpectDiagnosticsFor( + R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target(STATUSOR_INT* x, STATUSOR_INT* y) { + if (x->ok()) { + if (x != y) + y->value(); // [[unsafe]] + else + y->value(); + } + } + )cc"); + ExpectDiagnosticsFor( + R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target(STATUS* x, STATUS* y) { + auto sor = Make(); + if (x->ok()) { + if (x == y && sor.status() == *y) + sor.value(); + else + sor.value(); // [[unsafe]] + } + } + )cc"); + ExpectDiagnosticsFor( + R"cc( +#include "unchecked_statusor_access_test_defs.h" + + void target(STATUS* x, STATUS* y) { + auto sor = Make(); + if (x->ok()) { + if (x != y) + sor.value(); // [[unsafe]] + else if (sor.status() == *y) + sor.value(); + } + } + )cc"); +} + } // namespace std::string