merge main into amd-staging #387
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…164863) This patch extends VPTERNLOG pattern matching to handle cases where an outer NOT wraps a pure logical tree, such as `~(A | B | C)`. By recognizing these negated logic trees, the instruction selector can now emit a single vpternlog instruction. The change preserves the match for patterns like `(x != C1) & (x != C2)`, which also have the xor-with-all-ones pattern outside. The patch conservatively peels the outer XOR-with-all-ones only when it directly wraps a foldable logical operator (AND, OR, XOR, or ANDNP). Resolves llvm#163738
So that we do not have to worry about synchronizing data between the two clusters. This also enables this script to work on AArch64, although we'll look at enabling that later. Reviewers: cmtice Reviewed By: cmtice Pull Request: llvm#165058
…4917) The KCFI_CHECK pseudo-instruction size for ARM got miscalculated. These should represent worst-case expansion to ensure correct branch range calculations and code layout. Update the Size field for each ARM sub-architecture: - ARM: 28 → 40 bytes (10 instructions @ 4 bytes when r3 spill needed) - Thumb2: 32 → 34 bytes (mixed 16/32-bit instructions with r3 spill) - Thumb1: 50 → 38 bytes (19 instructions @ 2 bytes with r2+r3 spills) The ARM and Thumb2 sizes were underestimating the case where the target register is r12, requiring r3 to be used as scratch and spilled/restored. The Thumb1 size was overestimated and has been corrected to the actual worst-case of 19 instructions.
Added in llvm#164524. Fails when using libc++ in a mode that prunes transitive headers.
ranapratap55
approved these changes
Oct 25, 2025
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