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In preparation to strip VPUnrollPartAccessor and unroll recipes directly, strip unnecessary complication in getGEPIndexTy, as the unroll part will no longer be available in follow-ups (see llvm#168886 for instance). The patch also helps by doing a mass test update up-front. Narrowing the GEP index type conditionally does not yield any benefit, and the change is non-functional in terms of emitted assembly. While at it, avoid hard-coding address-space 0, and use the pointer operand's address space to get the GEP index type.
This adds a default enabled flag to control attachment of call site debug info. `-gno-call-site-info` can be used to disable this feature when needed. This should help those concerned about debug info size in llvm#168851.
…rontend and flangFrontend" (llvm#169599) This relands llvm#165277 by reverting llvm#169397. This also relands the corresponding Bazel port by reverting llvm#169410. The original revert was due to a report of a broken build, which was later resolved by fully clearing the build directory.
…m#164813) This patch makes DWARF fission compatible with RISC-V relaxations by using indirect addressing for the DW_AT_high_pc attribute. This eliminates the remaining relocations in .dwo files.
… HIP" (llvm#169637) This relands "[clang][Driver] Support for the SPIR-V backend when compiling HIP" llvm#167543. The only new change is a small fix for the multicall driver. For HIP, the SPIR-V backend can be optionally activated with the -use-spirv-backend flag. This option uses the SPIR-V BE instead of the SPIR-V translator. These changes also ensure that -use-spirv-backend does not require external dependencies, such as spirv-as and spirv-link
`tryDelinearizeFixedSizeImpl` is a heuristic function relying on GEP's type information. Using these information to drive an optimization heuristic is not allowed, so this function should be removed. As llvm#161822 and llvm#164798 have eliminated all calls to this, this patch removes the function itself.
…-vector-to-llvm`. (llvm#169573) `convert-vector-to-llvm` pass applies a set of vector transformation patterns that are not included in the standard `convert-to-llvm` pass interface. These additional transformations are required to properly lower MLIR vector operations. Since not all vector ops have direct `llvm` dialect lowering, many of them must first be progressively rewritten into simpler or more canonical vector ops, which are then lowered to `llvm`. Therefore, running `convert-vector-to-llvm` is necessary to ensure a complete and correct lowering of vector operations to the `llvm` dialect. Original PR: llvm#166204 + post-commit failure fixes.
…da-is-device (llvm#165387) When compiling HIP device code, we add implicit casts for the pointer arguments passed to built-in calls. When compiling for the host, apply the same casts, since the device side of the source (device functions and kernels) should still pass type checks.
This patch adds a new VPlan transformation to hoist predicated loads, if we can prove they execute unconditionally, i.e. there are 2 predicated loads to the same address with complementary masks. Then we are guaranteed to execute one of them on each iteration, allowing us to remove the mask. The transform groups masked replicating loads by their address SCEV, then checks if there are 2 loads with complementary mask. If that is the case, we check if there are any writes that may alias the load address in the blocks between the first and last load with the same address. The transforms operates after linearizing the CFG, but before introducing replicate regions, which means this is just checking a chain of consecutive blocks. Currently this only uses noalias metadata to check for no-alias (using the helpers added in llvm#166247). Then we create an unpredicated VPReplicateRecipe at the position of the first load, then replace all users of the grouped loads with it. Small Alive2 proof for hoisting with complementary masks: https://alive2.llvm.org/ce/z/kUx742 PR: llvm#168373
Add a helper function getAllocTokenModeAsString() to convert AllocTokenMode values to their string representation. NFC.
This adds a combine for add(trunc(ashr(A, C)), trunc(lshr(A, BW-1))), with C >= BW -> X = trunc(ashr(A, C)); add(x, lshr(X, BW-1) The original converts into ashr+lshr+xtn+xtn+add. The second becomes ashr+xtn+usra. The first form has less total latency due to more parallelism, but more micro-ops and seems to be slower in practice.
…n emitAtomicOp (llvm#169610) Fix build error: enumeration values 'AO__scoped_atomic_udec_wrap' and 'AO__scoped_atomic_uinc_wrap' not handled in switch [-Werror,-Wswitch] The two builtins were added in 5d38cdd.
The AArch64_BTI MCPlusBuilder unittest was failing in no assertion builds. Add `#ifndef NDEBUG` to exclude the assertion test from no assertion builds.
Adding documentation following the merge of llvm#168905.
Mips seems kind of broken with these options. n32 seems to override the 64-bit arch with 32-bit pointers, and trying to use any 32-bit mips triple also just errors with any options.
…8428) The instruction selection pass for SPIR-V now performs dead code elimination (DCE). This change removes unused instructions, leading to more optimized SPIR-V output. As a consequence of this, several tests were updated to ensure their continued correctness and to prevent previously tested code from being optimized away. Specifically: - Many tests now store computed values into global variables to ensure they are not eliminated by DCE, allowing their code generation to be verified. - The test `keep-tracked-const.ll` was removed because it no longer tested its original intent. The check statements in this test were for constants generated when expanding a G_TRUNC instruction, which is now removed by DCE instead of being expanded. - A new test, `remove-dead-type-intrinsics.ll`, was added to confirm that dead struct types are correctly removed by the compiler. These updates improve the SPIR-V backends optimization capabilities and maintain the robustness of the test suite. --------- Co-authored-by: Nathan Gauër <github@keenuts.net>
This eliminates the need to have PointerLikeRegClass handling in codegen.
This commit adds support for 'peeled arrays' in HLSL constant buffers.
HLSL CBuffers may have padding between array elements but not after the
last element. This is represented in LLVM IR as {[N-1 x {T, pad}], T}.
Changes include:
- Recognition of the peeled array pattern.
- Logic to reconstitute these into SPIR-V compatible arrays.
- Support for spirv.Padding type in GlobalRegistry and Builtins.
- Updates to SPIRVCBufferAccess to correctly calculate member offsets
in these padded structures.
Depends on llvm#169076
This commit modifies the SPIRV instruction selector to emit `OpCopyMemory` instead of `OpCopyMemorySized` when generating SPIRV for logical addressing. Previously, `G_MEMCPY` was translated to `OpCopyMemorySized`, which requires an explicit size operand. However, for logical SPIRV, the size of the pointee type is implicitly known. This change ensures that `OpCopyMemory` is used, which is more appropriate for logical SPIRV and aligns with the SPIR-V specification for logical addressing.
…#159882) Most targets should now use the convenience multiclass to fixup the operand definitions of pointer-using pseudoinstructions: defm : RemapAllTargetPseudoPointerOperands<target_ptr_regclass>;
All uses have been migrated to RegClassByHwMode. This is now an implementation detail of InstrInfoEmitter for pseudoinstructions.
Calloc was already here, but not the others. Also add manual type information.
…vm#167082) Script scraped dump of most functions in TargetLibraryInfo.def, with existing entries and a few special cases removed. This only adds the definitions, and doesn't add them to any system yet. Adding them in the correct places is the hard part, since it's all written as opt-out with manually written exemptions in TargetLibraryInfo.
…7083) This is one of the easier cases to comprehend in TargetLibraryInfo's setup.
Type Sanitizer support for SystemZ. Co-authored-by: anoopkg6 <anoopkg6@github.com>
Add Support for scudo_standalone for SystemZ without enabling gwp_asan. Co-authored-by: anoopkg6 <anoopkg6@github.com>
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ronlieb
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Nov 26, 2025
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