From 7238b053e2b650993799f86887692378da9af6bd Mon Sep 17 00:00:00 2001 From: sakumisu <1203593632@qq.com> Date: Sat, 13 Apr 2024 22:17:55 +0800 Subject: [PATCH] refactor(drivers/usb):replace rtt usb stack with cherryusb --- bsp/bouffalo_lab/bl61x/.config | 171 +- bsp/bouffalo_lab/bl61x/Kconfig | 7 +- bsp/bouffalo_lab/bl61x/board/Kconfig | 1 + bsp/bouffalo_lab/bl61x/board/cherryusb_port.c | 14 + bsp/bouffalo_lab/bl61x/board/usb_config.h | 265 + bsp/bouffalo_lab/bl61x/rtconfig.h | 99 +- bsp/bouffalo_lab/libraries/Kconfig | 1519 +- bsp/bouffalo_lab/libraries/rt_drivers/Kconfig | 1519 - bsp/hpmicro/hpm6750evk2/.config | 293 +- .../hpm6750evk2/board/cherryusb_port.c | 14 + .../board/linker_scripts/flash_rtt.ld | 6 + bsp/hpmicro/hpm6750evk2/board/usb_config.h | 267 + bsp/hpmicro/hpm6750evk2/rtconfig.h | 172 +- bsp/hpmicro/libraries/hpm_sdk/SConscript | 2 +- components/Kconfig | 3 + components/drivers/Kconfig | 201 +- components/drivers/usb/.ignore_format.yml | 6 + components/drivers/usb/SConscript | 10 +- .../drivers/usb/cherryusb/.clang-format | 171 + .../drivers/usb/cherryusb/.gitattributes | 47 + components/drivers/usb/cherryusb/.gitignore | 23 + .../drivers/usb/cherryusb/.readthedocs.yaml | 35 + .../drivers/usb/cherryusb/CherryUSB.svg | 3 + components/drivers/usb/cherryusb/Kconfig | 310 + .../drivers/usb/cherryusb/Kconfig.cherryusb | 304 + components/drivers/usb/cherryusb/LICENSE | 201 + components/drivers/usb/cherryusb/README.md | 196 + components/drivers/usb/cherryusb/README_zh.md | 198 + components/drivers/usb/cherryusb/SConscript | 210 + components/drivers/usb/cherryusb/VERSION | 5 + .../drivers/usb/cherryusb/cherryusb.cmake | 241 + .../usb/cherryusb/cherryusb_config_template.h | 261 + .../usb/cherryusb/class/audio/usb_audio.h | 1165 + .../usb/cherryusb/class/audio/usbd_audio.c | 344 + .../usb/cherryusb/class/audio/usbd_audio.h | 43 + .../usb/cherryusb/class/audio/usbh_audio.c | 483 + .../usb/cherryusb/class/audio/usbh_audio.h | 76 + .../drivers/usb/cherryusb/class/cdc/usb_cdc.h | 698 + .../usb/cherryusb/class/cdc/usbd_cdc.c | 118 + .../usb/cherryusb/class/cdc/usbd_cdc.h | 29 + .../usb/cherryusb/class/cdc/usbd_cdc_ecm.c | 247 + .../usb/cherryusb/class/cdc/usbd_cdc_ecm.h | 42 + .../usb/cherryusb/class/cdc/usbh_cdc_acm.c | 263 + .../usb/cherryusb/class/cdc/usbh_cdc_acm.h | 50 + .../usb/cherryusb/class/cdc/usbh_cdc_ecm.c | 319 + .../usb/cherryusb/class/cdc/usbh_cdc_ecm.h | 49 + .../usb/cherryusb/class/cdc/usbh_cdc_ncm.c | 388 + .../usb/cherryusb/class/cdc/usbh_cdc_ncm.h | 53 + .../drivers/usb/cherryusb/class/dfu/usb_dfu.h | 137 + .../usb/cherryusb/class/dfu/usbd_dfu.c | 505 + .../usb/cherryusb/class/dfu/usbd_dfu.h | 27 + .../drivers/usb/cherryusb/class/hid/usb_hid.h | 585 + .../usb/cherryusb/class/hid/usbd_hid.c | 89 + .../usb/cherryusb/class/hid/usbd_hid.h | 34 + .../usb/cherryusb/class/hid/usbh_hid.c | 231 + .../usb/cherryusb/class/hid/usbh_hid.h | 41 + .../drivers/usb/cherryusb/class/hub/usb_hub.h | 121 + .../usb/cherryusb/class/hub/usbh_hub.c | 711 + .../usb/cherryusb/class/hub/usbh_hub.h | 33 + .../usb/cherryusb/class/midi/usb_midi.h | 240 + .../drivers/usb/cherryusb/class/msc/usb_msc.h | 89 + .../usb/cherryusb/class/msc/usb_scsi.h | 972 + .../usb/cherryusb/class/msc/usbd_msc.c | 938 + .../usb/cherryusb/class/msc/usbd_msc.h | 32 + .../usb/cherryusb/class/msc/usbh_msc.c | 436 + .../usb/cherryusb/class/msc/usbh_msc.h | 49 + .../usb/cherryusb/class/template/usb_xxx.h | 4 + .../usb/cherryusb/class/template/usbd_xxx.c | 39 + .../usb/cherryusb/class/template/usbd_xxx.h | 16 + .../usb/cherryusb/class/template/usbh_xxx.c | 97 + .../usb/cherryusb/class/template/usbh_xxx.h | 22 + .../cherryusb/class/vendor/net/usbh_asix.c | 774 + .../cherryusb/class/vendor/net/usbh_asix.h | 176 + .../cherryusb/class/vendor/net/usbh_rtl8152.c | 2249 + .../cherryusb/class/vendor/net/usbh_rtl8152.h | 67 + .../class/vendor/serial/usbh_ch34x.c | 356 + .../class/vendor/serial/usbh_ch34x.h | 76 + .../class/vendor/serial/usbh_cp210x.c | 295 + .../class/vendor/serial/usbh_cp210x.h | 73 + .../cherryusb/class/vendor/serial/usbh_ftdi.c | 363 + .../cherryusb/class/vendor/serial/usbh_ftdi.h | 76 + .../class/vendor/serial/usbh_pl2303.c | 426 + .../class/vendor/serial/usbh_pl2303.h | 62 + .../usb/cherryusb/class/video/usb_video.h | 1198 + .../usb/cherryusb/class/video/usbd_video.c | 789 + .../usb/cherryusb/class/video/usbd_video.h | 29 + .../usb/cherryusb/class/video/usbh_video.c | 522 + .../usb/cherryusb/class/video/usbh_video.h | 85 + .../usb/cherryusb/class/wireless/ndis.h | 270 + .../cherryusb/class/wireless/rndis_protocol.h | 302 + .../usb/cherryusb/class/wireless/usbd_rndis.c | 566 + .../usb/cherryusb/class/wireless/usbd_rndis.h | 32 + .../cherryusb/class/wireless/usbh_bluetooth.c | 402 + .../cherryusb/class/wireless/usbh_bluetooth.h | 56 + .../usb/cherryusb/class/wireless/usbh_rndis.c | 561 + .../usb/cherryusb/class/wireless/usbh_rndis.h | 51 + .../drivers/usb/cherryusb/common/usb_dc.h | 194 + .../drivers/usb/cherryusb/common/usb_def.h | 724 + .../drivers/usb/cherryusb/common/usb_errno.h | 24 + .../drivers/usb/cherryusb/common/usb_hc.h | 114 + .../drivers/usb/cherryusb/common/usb_list.h | 459 + .../drivers/usb/cherryusb/common/usb_log.h | 85 + .../drivers/usb/cherryusb/common/usb_osal.h | 61 + .../drivers/usb/cherryusb/common/usb_util.h | 210 + .../drivers/usb/cherryusb/core/usbd_core.c | 1306 + .../drivers/usb/cherryusb/core/usbd_core.h | 111 + .../drivers/usb/cherryusb/core/usbh_core.c | 878 + .../drivers/usb/cherryusb/core/usbh_core.h | 278 + .../demo/audio_v1_mic_multichan_template.c | 241 + .../audio_v1_mic_speaker_multichan_template.c | 265 + .../demo/audio_v2_mic_multichan_template.c | 246 + .../audio_v2_mic_speaker_multichan_template.c | 367 + .../audio_v2_speaker_multichan_template.c | 264 + .../cherryusb/demo/cdc_acm_hid_msc_template.c | 396 + .../usb/cherryusb/demo/cdc_acm_msc_template.c | 315 + .../cherryusb/demo/cdc_acm_multi_template.c | 251 + .../usb/cherryusb/demo/cdc_acm_template.c | 211 + .../usb/cherryusb/demo/cdc_ecm_template.c | 279 + .../usb/cherryusb/demo/cdc_rndis_template.c | 313 + .../usb/cherryusb/demo/dfu_st_cubemx_main.c | 372 + .../demo/dfu_with_st_tool_template.c | 177 + .../demo/hid_custom_inout_template.c | 278 + .../cherryusb/demo/hid_keyboard_template.c | 247 + .../usb/cherryusb/demo/hid_mouse_template.c | 281 + .../usb/cherryusb/demo/midi_template.c | 214 + .../usb/cherryusb/demo/msc_ram_template.c | 165 + .../usb/cherryusb/demo/msc_storage_template.c | 172 + .../usb/cherryusb/demo/music_16k_ac1.h | 109183 +++++++++++++++ .../usb/cherryusb/demo/music_16k_ac2.h | 78605 +++++++++++ .../drivers/usb/cherryusb/demo/pic_data.h | 1146 + .../drivers/usb/cherryusb/demo/usb_host.c | 1100 + .../demo/video_static_mjpeg_template.c | 258 + .../usb/cherryusb/demo/webusb_template.c | 76 + .../usb/cherryusb/demo/winusb1.0_template.c | 462 + .../cherryusb/demo/winusb2.0_cdc_template.c | 339 + .../cherryusb/demo/winusb2.0_hid_template.c | 440 + .../usb/cherryusb/osal/usb_osal_rtthread.c | 169 + .../drivers/usb/cherryusb/platform/README.md | 14 + .../cherryusb/platform/rtthread/usb_check.c | 17 + .../usb/cherryusb/platform/rtthread/usb_msh.c | 47 + .../cherryusb/platform/rtthread/usbh_dfs.c | 241 + .../cherryusb/platform/rtthread/usbh_lwip.c | 415 + .../usb/cherryusb/port/bouffalolab/README.md | 5 + .../cherryusb/port/bouffalolab/usb_dc_bl.c | 1108 + .../drivers/usb/cherryusb/port/ch32/README.md | 5 + .../cherryusb/port/ch32/usb_ch32_usbfs_reg.h | 409 + .../cherryusb/port/ch32/usb_ch32_usbhs_reg.h | 564 + .../usb/cherryusb/port/ch32/usb_dc_usbfs.c | 404 + .../usb/cherryusb/port/ch32/usb_dc_usbhs.c | 382 + .../drivers/usb/cherryusb/port/dwc2/README.md | 31 + .../usb/cherryusb/port/dwc2/usb_dc_dwc2.c | 1191 + .../usb/cherryusb/port/dwc2/usb_dwc2_reg.h | 1721 + .../usb/cherryusb/port/dwc2/usb_glue_at.c | 52 + .../usb/cherryusb/port/dwc2/usb_glue_esp.c | 120 + .../usb/cherryusb/port/dwc2/usb_glue_gd.c | 32 + .../usb/cherryusb/port/dwc2/usb_glue_st.c | 203 + .../usb/cherryusb/port/dwc2/usb_hc_dwc2.c | 1094 + .../drivers/usb/cherryusb/port/ehci/README.md | 27 + .../usb/cherryusb/port/ehci/usb_ehci_priv.h | 76 + .../usb/cherryusb/port/ehci/usb_glue_aic.c | 181 + .../cherryusb/port/ehci/usb_glue_bouffalo.c | 143 + .../usb/cherryusb/port/ehci/usb_glue_hpm.c | 99 + .../usb/cherryusb/port/ehci/usb_glue_intel.c | 55 + .../usb/cherryusb/port/ehci/usb_glue_ma35d0.c | 117 + .../usb/cherryusb/port/ehci/usb_glue_nuc980.c | 62 + .../usb/cherryusb/port/ehci/usb_hc_ehci.c | 1371 + .../usb/cherryusb/port/ehci/usb_hc_ehci.h | 375 + .../usb/cherryusb/port/fsdev/README.md | 33 + .../usb/cherryusb/port/fsdev/usb_dc_fsdev.c | 540 + .../usb/cherryusb/port/fsdev/usb_fsdev_reg.h | 1684 + .../usb/cherryusb/port/hpm/usb_dc_hpm.c | 350 + .../drivers/usb/cherryusb/port/musb/README.md | 19 + .../usb/cherryusb/port/musb/usb_dc_musb.c | 886 + .../usb/cherryusb/port/musb/usb_glue_sunxi.c | 5 + .../usb/cherryusb/port/musb/usb_hc_musb.c | 1018 + .../usb/cherryusb/port/musb/usb_musb_reg.h | 3871 + .../drivers/usb/cherryusb/port/ohci/README.md | 18 + .../usb/cherryusb/port/ohci/usb_hc_ohci.c | 240 + .../usb/cherryusb/port/ohci/usb_hc_ohci.h | 484 + .../usb/cherryusb/port/ohci/usb_ohci_priv.h | 24 + components/legacy/Kconfig | 200 + components/legacy/usb/SConscript | 13 + .../usb/usbdevice/SConscript | 0 .../usb/usbdevice/class/audio_mic.c | 0 .../usb/usbdevice/class/audio_speaker.c | 0 .../usb/usbdevice/class/cdc.h | 0 .../usb/usbdevice/class/cdc_vcom.c | 0 .../usb/usbdevice/class/ecm.c | 0 .../usb/usbdevice/class/hid.c | 0 .../usb/usbdevice/class/hid.h | 0 .../usb/usbdevice/class/mstorage.c | 0 .../usb/usbdevice/class/mstorage.h | 0 .../usb/usbdevice/class/ndis.h | 0 .../usb/usbdevice/class/rndis.c | 0 .../usb/usbdevice/class/rndis.h | 0 .../usb/usbdevice/class/uaudioreg.h | 0 .../usb/usbdevice/class/winusb.c | 0 .../usb/usbdevice/class/winusb.h | 0 .../usb/usbdevice/core/usbdevice.c | 0 .../usb/usbdevice/core/usbdevice_core.c | 0 .../usb/usbhost/SConscript | 0 .../usb/usbhost/class/adk.c | 0 .../usb/usbhost/class/adk.h | 0 .../usb/usbhost/class/hid.c | 0 .../usb/usbhost/class/hid.h | 0 .../usb/usbhost/class/mass.c | 0 .../usb/usbhost/class/mass.h | 0 .../usb/usbhost/class/udisk.c | 0 .../usb/usbhost/class/ukbd.c | 0 .../usb/usbhost/class/umouse.c | 0 .../usb/usbhost/core/driver.c | 0 .../usb/usbhost/core/hub.c | 0 .../usb/usbhost/core/usbhost.c | 0 .../usb/usbhost/core/usbhost_core.c | 0 214 files changed, 245858 insertions(+), 1809 deletions(-) create mode 100644 bsp/bouffalo_lab/bl61x/board/cherryusb_port.c create mode 100644 bsp/bouffalo_lab/bl61x/board/usb_config.h delete mode 100755 bsp/bouffalo_lab/libraries/rt_drivers/Kconfig create mode 100644 bsp/hpmicro/hpm6750evk2/board/cherryusb_port.c create mode 100644 bsp/hpmicro/hpm6750evk2/board/usb_config.h create mode 100755 components/drivers/usb/.ignore_format.yml create mode 100644 components/drivers/usb/cherryusb/.clang-format create mode 100644 components/drivers/usb/cherryusb/.gitattributes create mode 100644 components/drivers/usb/cherryusb/.gitignore create mode 100644 components/drivers/usb/cherryusb/.readthedocs.yaml create mode 100644 components/drivers/usb/cherryusb/CherryUSB.svg create mode 100644 components/drivers/usb/cherryusb/Kconfig create mode 100644 components/drivers/usb/cherryusb/Kconfig.cherryusb create mode 100644 components/drivers/usb/cherryusb/LICENSE create mode 100644 components/drivers/usb/cherryusb/README.md create mode 100644 components/drivers/usb/cherryusb/README_zh.md create mode 100644 components/drivers/usb/cherryusb/SConscript create mode 100644 components/drivers/usb/cherryusb/VERSION create mode 100644 components/drivers/usb/cherryusb/cherryusb.cmake create mode 100644 components/drivers/usb/cherryusb/cherryusb_config_template.h create mode 100644 components/drivers/usb/cherryusb/class/audio/usb_audio.h create mode 100644 components/drivers/usb/cherryusb/class/audio/usbd_audio.c create mode 100644 components/drivers/usb/cherryusb/class/audio/usbd_audio.h create mode 100644 components/drivers/usb/cherryusb/class/audio/usbh_audio.c create mode 100644 components/drivers/usb/cherryusb/class/audio/usbh_audio.h create mode 100644 components/drivers/usb/cherryusb/class/cdc/usb_cdc.h create mode 100644 components/drivers/usb/cherryusb/class/cdc/usbd_cdc.c create mode 100644 components/drivers/usb/cherryusb/class/cdc/usbd_cdc.h create mode 100644 components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.c create mode 100644 components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.h create mode 100644 components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c create mode 100644 components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.h create mode 100644 components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c create mode 100644 components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.h create mode 100644 components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c create mode 100644 components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.h create mode 100644 components/drivers/usb/cherryusb/class/dfu/usb_dfu.h create mode 100644 components/drivers/usb/cherryusb/class/dfu/usbd_dfu.c create mode 100644 components/drivers/usb/cherryusb/class/dfu/usbd_dfu.h create mode 100644 components/drivers/usb/cherryusb/class/hid/usb_hid.h create mode 100644 components/drivers/usb/cherryusb/class/hid/usbd_hid.c create mode 100644 components/drivers/usb/cherryusb/class/hid/usbd_hid.h create mode 100644 components/drivers/usb/cherryusb/class/hid/usbh_hid.c create mode 100644 components/drivers/usb/cherryusb/class/hid/usbh_hid.h create mode 100644 components/drivers/usb/cherryusb/class/hub/usb_hub.h create mode 100644 components/drivers/usb/cherryusb/class/hub/usbh_hub.c create mode 100644 components/drivers/usb/cherryusb/class/hub/usbh_hub.h create mode 100644 components/drivers/usb/cherryusb/class/midi/usb_midi.h create mode 100644 components/drivers/usb/cherryusb/class/msc/usb_msc.h create mode 100644 components/drivers/usb/cherryusb/class/msc/usb_scsi.h create mode 100644 components/drivers/usb/cherryusb/class/msc/usbd_msc.c create mode 100644 components/drivers/usb/cherryusb/class/msc/usbd_msc.h create mode 100644 components/drivers/usb/cherryusb/class/msc/usbh_msc.c create mode 100644 components/drivers/usb/cherryusb/class/msc/usbh_msc.h create mode 100644 components/drivers/usb/cherryusb/class/template/usb_xxx.h create mode 100644 components/drivers/usb/cherryusb/class/template/usbd_xxx.c create mode 100644 components/drivers/usb/cherryusb/class/template/usbd_xxx.h create mode 100644 components/drivers/usb/cherryusb/class/template/usbh_xxx.c create mode 100644 components/drivers/usb/cherryusb/class/template/usbh_xxx.h create mode 100644 components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c create mode 100644 components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.h create mode 100644 components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c create mode 100644 components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.h create mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c create mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.h create mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c create mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.h create mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c create mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.h create mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c create mode 100644 components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.h create mode 100644 components/drivers/usb/cherryusb/class/video/usb_video.h create mode 100644 components/drivers/usb/cherryusb/class/video/usbd_video.c create mode 100644 components/drivers/usb/cherryusb/class/video/usbd_video.h create mode 100644 components/drivers/usb/cherryusb/class/video/usbh_video.c create mode 100644 components/drivers/usb/cherryusb/class/video/usbh_video.h create mode 100644 components/drivers/usb/cherryusb/class/wireless/ndis.h create mode 100644 components/drivers/usb/cherryusb/class/wireless/rndis_protocol.h create mode 100644 components/drivers/usb/cherryusb/class/wireless/usbd_rndis.c create mode 100644 components/drivers/usb/cherryusb/class/wireless/usbd_rndis.h create mode 100644 components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.c create mode 100644 components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.h create mode 100644 components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c create mode 100644 components/drivers/usb/cherryusb/class/wireless/usbh_rndis.h create mode 100644 components/drivers/usb/cherryusb/common/usb_dc.h create mode 100644 components/drivers/usb/cherryusb/common/usb_def.h create mode 100644 components/drivers/usb/cherryusb/common/usb_errno.h create mode 100644 components/drivers/usb/cherryusb/common/usb_hc.h create mode 100644 components/drivers/usb/cherryusb/common/usb_list.h create mode 100644 components/drivers/usb/cherryusb/common/usb_log.h create mode 100644 components/drivers/usb/cherryusb/common/usb_osal.h create mode 100644 components/drivers/usb/cherryusb/common/usb_util.h create mode 100644 components/drivers/usb/cherryusb/core/usbd_core.c create mode 100644 components/drivers/usb/cherryusb/core/usbd_core.h create mode 100644 components/drivers/usb/cherryusb/core/usbh_core.c create mode 100644 components/drivers/usb/cherryusb/core/usbh_core.h create mode 100644 components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c create mode 100644 components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c create mode 100644 components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c create mode 100644 components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c create mode 100644 components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c create mode 100644 components/drivers/usb/cherryusb/demo/cdc_acm_hid_msc_template.c create mode 100644 components/drivers/usb/cherryusb/demo/cdc_acm_msc_template.c create mode 100644 components/drivers/usb/cherryusb/demo/cdc_acm_multi_template.c create mode 100644 components/drivers/usb/cherryusb/demo/cdc_acm_template.c create mode 100644 components/drivers/usb/cherryusb/demo/cdc_ecm_template.c create mode 100644 components/drivers/usb/cherryusb/demo/cdc_rndis_template.c create mode 100644 components/drivers/usb/cherryusb/demo/dfu_st_cubemx_main.c create mode 100644 components/drivers/usb/cherryusb/demo/dfu_with_st_tool_template.c create mode 100644 components/drivers/usb/cherryusb/demo/hid_custom_inout_template.c create mode 100644 components/drivers/usb/cherryusb/demo/hid_keyboard_template.c create mode 100644 components/drivers/usb/cherryusb/demo/hid_mouse_template.c create mode 100644 components/drivers/usb/cherryusb/demo/midi_template.c create mode 100644 components/drivers/usb/cherryusb/demo/msc_ram_template.c create mode 100644 components/drivers/usb/cherryusb/demo/msc_storage_template.c create mode 100644 components/drivers/usb/cherryusb/demo/music_16k_ac1.h create mode 100644 components/drivers/usb/cherryusb/demo/music_16k_ac2.h create mode 100644 components/drivers/usb/cherryusb/demo/pic_data.h create mode 100644 components/drivers/usb/cherryusb/demo/usb_host.c create mode 100644 components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c create mode 100644 components/drivers/usb/cherryusb/demo/webusb_template.c create mode 100644 components/drivers/usb/cherryusb/demo/winusb1.0_template.c create mode 100644 components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c create mode 100644 components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c create mode 100644 components/drivers/usb/cherryusb/osal/usb_osal_rtthread.c create mode 100644 components/drivers/usb/cherryusb/platform/README.md create mode 100644 components/drivers/usb/cherryusb/platform/rtthread/usb_check.c create mode 100644 components/drivers/usb/cherryusb/platform/rtthread/usb_msh.c create mode 100644 components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c create mode 100644 components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c create mode 100644 components/drivers/usb/cherryusb/port/bouffalolab/README.md create mode 100644 components/drivers/usb/cherryusb/port/bouffalolab/usb_dc_bl.c create mode 100644 components/drivers/usb/cherryusb/port/ch32/README.md create mode 100644 components/drivers/usb/cherryusb/port/ch32/usb_ch32_usbfs_reg.h create mode 100644 components/drivers/usb/cherryusb/port/ch32/usb_ch32_usbhs_reg.h create mode 100644 components/drivers/usb/cherryusb/port/ch32/usb_dc_usbfs.c create mode 100644 components/drivers/usb/cherryusb/port/ch32/usb_dc_usbhs.c create mode 100644 components/drivers/usb/cherryusb/port/dwc2/README.md create mode 100644 components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c create mode 100644 components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h create mode 100644 components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c create mode 100644 components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c create mode 100644 components/drivers/usb/cherryusb/port/dwc2/usb_glue_gd.c create mode 100644 components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c create mode 100644 components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c create mode 100644 components/drivers/usb/cherryusb/port/ehci/README.md create mode 100644 components/drivers/usb/cherryusb/port/ehci/usb_ehci_priv.h create mode 100644 components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c create mode 100644 components/drivers/usb/cherryusb/port/ehci/usb_glue_bouffalo.c create mode 100644 components/drivers/usb/cherryusb/port/ehci/usb_glue_hpm.c create mode 100644 components/drivers/usb/cherryusb/port/ehci/usb_glue_intel.c create mode 100644 components/drivers/usb/cherryusb/port/ehci/usb_glue_ma35d0.c create mode 100644 components/drivers/usb/cherryusb/port/ehci/usb_glue_nuc980.c create mode 100644 components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c create mode 100644 components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.h create mode 100644 components/drivers/usb/cherryusb/port/fsdev/README.md create mode 100644 components/drivers/usb/cherryusb/port/fsdev/usb_dc_fsdev.c create mode 100644 components/drivers/usb/cherryusb/port/fsdev/usb_fsdev_reg.h create mode 100644 components/drivers/usb/cherryusb/port/hpm/usb_dc_hpm.c create mode 100644 components/drivers/usb/cherryusb/port/musb/README.md create mode 100644 components/drivers/usb/cherryusb/port/musb/usb_dc_musb.c create mode 100644 components/drivers/usb/cherryusb/port/musb/usb_glue_sunxi.c create mode 100644 components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c create mode 100644 components/drivers/usb/cherryusb/port/musb/usb_musb_reg.h create mode 100644 components/drivers/usb/cherryusb/port/ohci/README.md create mode 100644 components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.c create mode 100644 components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.h create mode 100644 components/drivers/usb/cherryusb/port/ohci/usb_ohci_priv.h create mode 100644 components/legacy/Kconfig create mode 100644 components/legacy/usb/SConscript rename components/{drivers => legacy}/usb/usbdevice/SConscript (100%) rename components/{drivers => legacy}/usb/usbdevice/class/audio_mic.c (100%) rename components/{drivers => legacy}/usb/usbdevice/class/audio_speaker.c (100%) rename components/{drivers => legacy}/usb/usbdevice/class/cdc.h (100%) rename components/{drivers => legacy}/usb/usbdevice/class/cdc_vcom.c (100%) rename components/{drivers => legacy}/usb/usbdevice/class/ecm.c (100%) rename components/{drivers => legacy}/usb/usbdevice/class/hid.c (100%) rename components/{drivers => legacy}/usb/usbdevice/class/hid.h (100%) rename components/{drivers => legacy}/usb/usbdevice/class/mstorage.c (100%) rename components/{drivers => legacy}/usb/usbdevice/class/mstorage.h (100%) rename components/{drivers => legacy}/usb/usbdevice/class/ndis.h (100%) rename components/{drivers => legacy}/usb/usbdevice/class/rndis.c (100%) rename components/{drivers => legacy}/usb/usbdevice/class/rndis.h (100%) rename components/{drivers => legacy}/usb/usbdevice/class/uaudioreg.h (100%) rename components/{drivers => legacy}/usb/usbdevice/class/winusb.c (100%) rename components/{drivers => legacy}/usb/usbdevice/class/winusb.h (100%) rename components/{drivers => legacy}/usb/usbdevice/core/usbdevice.c (100%) rename components/{drivers => legacy}/usb/usbdevice/core/usbdevice_core.c (100%) rename components/{drivers => legacy}/usb/usbhost/SConscript (100%) rename components/{drivers => legacy}/usb/usbhost/class/adk.c (100%) rename components/{drivers => legacy}/usb/usbhost/class/adk.h (100%) rename components/{drivers => legacy}/usb/usbhost/class/hid.c (100%) rename components/{drivers => legacy}/usb/usbhost/class/hid.h (100%) rename components/{drivers => legacy}/usb/usbhost/class/mass.c (100%) rename components/{drivers => legacy}/usb/usbhost/class/mass.h (100%) rename components/{drivers => legacy}/usb/usbhost/class/udisk.c (100%) rename components/{drivers => legacy}/usb/usbhost/class/ukbd.c (100%) rename components/{drivers => legacy}/usb/usbhost/class/umouse.c (100%) rename components/{drivers => legacy}/usb/usbhost/core/driver.c (100%) rename components/{drivers => legacy}/usb/usbhost/core/hub.c (100%) rename components/{drivers => legacy}/usb/usbhost/core/usbhost.c (100%) rename components/{drivers => legacy}/usb/usbhost/core/usbhost_core.c (100%) diff --git a/bsp/bouffalo_lab/bl61x/.config b/bsp/bouffalo_lab/bl61x/.config index c4eed2346dc..309a0e5da42 100644 --- a/bsp/bouffalo_lab/bl61x/.config +++ b/bsp/bouffalo_lab/bl61x/.config @@ -1,7 +1,3 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Project Configuration -# # # RT-Thread Kernel @@ -12,7 +8,7 @@ CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_CPUS_NR=1 -CONFIG_RT_ALIGN_SIZE=8 +CONFIG_RT_ALIGN_SIZE=32 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y # CONFIG_RT_THREAD_PRIORITY_256 is not set @@ -24,20 +20,27 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_IDLE_THREAD_STACK_SIZE=2048 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 # # kservice optimization # -CONFIG_RT_KSERVICE_USING_STDLIB=y -# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# end of kservice optimization + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# end of klibc optimization + CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y CONFIG_RT_DEBUGING_COLOR=y CONFIG_RT_DEBUGING_CONTEXT=y # CONFIG_RT_DEBUGING_AUTO_INIT is not set @@ -52,6 +55,7 @@ CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication # # Memory Management @@ -68,6 +72,8 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y # CONFIG_RT_USING_MEMTRACE is not set # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y +# end of Memory Management + CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set @@ -76,14 +82,12 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50100 +CONFIG_RT_VER_NUM=0x50200 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 -# CONFIG_RT_USING_CACHE is not set -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set +# end of RT-Thread Kernel + +CONFIG_RT_USING_CACHE=y CONFIG_ARCH_RISCV=y CONFIG_ARCH_RISCV_FPU=y CONFIG_ARCH_RISCV_FPU_S=y @@ -150,6 +154,8 @@ CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 CONFIG_RT_DFS_ELM_REENTRANT=y CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 # CONFIG_RT_DFS_ELM_USE_EXFAT is not set +# end of elm-chan's FatFs, Generic FAT Filesystem Module + CONFIG_RT_USING_DFS_DEVFS=y CONFIG_RT_USING_DFS_ROMFS=y # CONFIG_RT_USING_DFS_ROMFS_USER_ROOT is not set @@ -157,6 +163,8 @@ CONFIG_RT_USING_DFS_ROMFS=y # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set # CONFIG_RT_USING_DFS_MQUEUE is not set +# end of DFS: device virtual file system + # CONFIG_RT_USING_FAL is not set # @@ -207,13 +215,44 @@ CONFIG_RT_MMCSD_MAX_PARTITION=16 CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_KTIME is not set # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set +CONFIG_RT_USING_CHERRYUSB=y +# CONFIG_RT_CHERRYUSB_DEVICE is not set +CONFIG_RT_CHERRYUSB_HOST=y +# CONFIG_RT_CHERRYUSB_HOST_CUSTOM is not set +CONFIG_RT_CHERRYUSB_HOST_EHCI_BL=y +# CONFIG_RT_CHERRYUSB_HOST_EHCI_HPM is not set +# CONFIG_RT_CHERRYUSB_HOST_EHCI_AIC is not set +# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 is not set +# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 is not set +# CONFIG_RT_CHERRYUSB_HOST_EHCI_CUSTOM is not set +# CONFIG_RT_CHERRYUSB_HOST_DWC2_ST is not set +# CONFIG_RT_CHERRYUSB_HOST_DWC2_ESP is not set +# CONFIG_RT_CHERRYUSB_HOST_DWC2_CUSTOM is not set +# CONFIG_RT_CHERRYUSB_HOST_MUSB_STANDARD is not set +# CONFIG_RT_CHERRYUSB_HOST_MUSB_SUNXI is not set +# CONFIG_RT_CHERRYUSB_HOST_MUSB_CUSTOM is not set +# CONFIG_RT_CHERRYUSB_HOST_PUSB2 is not set +# CONFIG_RT_CHERRYUSB_HOST_XHCI is not set +CONFIG_RT_CHERRYUSB_HOST_CDC_ACM=y +CONFIG_RT_CHERRYUSB_HOST_HID=y +CONFIG_RT_CHERRYUSB_HOST_MSC=y +# CONFIG_RT_CHERRYUSB_HOST_CDC_RNDIS is not set +# CONFIG_RT_CHERRYUSB_HOST_CDC_ECM is not set +# CONFIG_RT_CHERRYUSB_HOST_CDC_NCM is not set +# CONFIG_RT_CHERRYUSB_HOST_VIDEO is not set +# CONFIG_RT_CHERRYUSB_HOST_AUDIO is not set +# CONFIG_RT_CHERRYUSB_HOST_BLUETOOTH is not set +# CONFIG_RT_CHERRYUSB_HOST_ASIX is not set +# CONFIG_RT_CHERRYUSB_HOST_RTL8152 is not set +# CONFIG_RT_CHERRYUSB_HOST_FTDI is not set +# CONFIG_RT_CHERRYUSB_HOST_CH34X is not set +# CONFIG_RT_CHERRYUSB_HOST_CP210X is not set +# CONFIG_RT_CHERRYUSB_HOST_PL2303 is not set +CONFIG_RT_CHERRYUSB_HOST_TEMPLATE=y +CONFIG_TEST_USBH_CDC_ACM=1 +CONFIG_TEST_USBH_HID=1 +CONFIG_TEST_USBH_MSC=0 +# end of Device Drivers # # C/C++ and POSIX layer @@ -231,6 +270,8 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer # # POSIX (Portable Operating System Interface) layer @@ -252,7 +293,11 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # Socket is in the 'Network' category # +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + # CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer # # Network @@ -261,12 +306,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_NETDEV is not set # CONFIG_RT_USING_LWIP is not set # CONFIG_RT_USING_AT is not set +# end of Network # # Memory protection # # CONFIG_RT_USING_MEM_PROTECTION is not set # CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection # # Utilities @@ -278,12 +325,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + # CONFIG_RT_USING_VBUS is not set +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version +# end of RT-Thread Components + # # RT-Thread Utestcases # # CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases # # RT-Thread online packages @@ -292,7 +350,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # IoT - internet of things # -# CONFIG_PKG_USING_LWIP is not set # CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_UMQTT is not set @@ -314,27 +371,35 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # Marvell WiFi # # CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi # # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + # CONFIG_PKG_USING_RW007 is not set # # CYW43012 WiFi # # CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi # # BL808 WiFi # # CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi # # CYW43439 WiFi # # CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set # CONFIG_PKG_USING_NETUTILS is not set @@ -357,6 +422,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set @@ -399,6 +466,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things # # security packages @@ -409,6 +478,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set # CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages # # language packages @@ -424,18 +494,22 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PARSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format # # XML: Extensible Markup Language # # CONFIG_PKG_USING_SIMPLE_XML is not set # CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + # CONFIG_PKG_USING_LUATOS_SOC is not set # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set # CONFIG_PKG_USING_PIKASCRIPT is not set # CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages # # multimedia packages @@ -447,12 +521,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library # # u8g2: a monochrome graphic library # # CONFIG_PKG_USING_U8G2_OFFICIAL is not set # CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -472,6 +549,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages # # tools packages @@ -520,6 +598,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set # CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages # # system packages @@ -531,6 +610,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT_MEMCPY_CM is not set # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services # # acceleration: Assembly language or algorithmic acceleration packages @@ -538,6 +618,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages # # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard @@ -548,6 +629,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # Micrium: Micrium software products porting for RT-Thread @@ -558,6 +640,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_LITEOS_SDK is not set # CONFIG_PKG_USING_TZ_DATABASE is not set @@ -605,6 +689,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RTP is not set # CONFIG_PKG_USING_REB is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages # # peripheral libraries and drivers @@ -617,9 +702,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # STM32 HAL & SDK Drivers # -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -629,10 +717,13 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_K210_SDK is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_NUCLEI_SDK is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers # # sensors drivers @@ -702,6 +793,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers # # touch drivers @@ -716,6 +808,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_XPT2046_TOUCH is not set # CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -788,6 +882,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_BT_MX01 is not set # CONFIG_PKG_USING_RGPOWER is not set # CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers # # AI packages @@ -802,6 +897,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages # # Signal Processing and Control Algorithm Packages @@ -811,6 +907,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages # # miscellaneous packages @@ -819,6 +916,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # project laboratory # +# end of project laboratory # # samples: kernel and components samples @@ -827,6 +925,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples # # entertainment: terminal games and other interesting software packages @@ -842,6 +941,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set @@ -875,6 +976,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages # # Arduino libraries @@ -890,6 +992,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos # # Sensors @@ -1029,6 +1132,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors # # Display @@ -1040,6 +1145,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display # # Timing @@ -1048,6 +1154,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set # CONFIG_PKG_USING_ARDUINO_TICKER is not set # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing # # Data Processing @@ -1055,6 +1162,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set # CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing # # Data Storage @@ -1065,6 +1174,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication # # Device Control @@ -1076,12 +1186,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control # # Other # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other # # Signal IO @@ -1094,10 +1206,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO # # Uncategorized # +# end of Arduino libraries +# end of RT-Thread online packages + CONFIG_BSP_USING_BL61X=y CONFIG_BSP_USING_ROMAPI=y # CONFIG_BSP_USING_PSRAM is not set @@ -1184,6 +1300,8 @@ CONFIG_UART0_RX_USING_GPIO22=y # CONFIG_UART0_RX_USING_GPIO33 is not set # CONFIG_UART0_RX_USING_GPIO34 is not set # CONFIG_BSP_USING_UART1 is not set +# end of General Purpose UARTs + # CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_RTC is not set @@ -1194,3 +1312,4 @@ CONFIG_UART0_RX_USING_GPIO22=y # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_ON_CHIP_FLASH is not set # CONFIG_BSP_USING_SDH is not set +# end of General Drivers Configuration diff --git a/bsp/bouffalo_lab/bl61x/Kconfig b/bsp/bouffalo_lab/bl61x/Kconfig index c6ee6e58f8d..b8b9123c841 100755 --- a/bsp/bouffalo_lab/bl61x/Kconfig +++ b/bsp/bouffalo_lab/bl61x/Kconfig @@ -15,12 +15,7 @@ config PKGS_DIR option env="PKGS_ROOT" default "packages" -config LIBRARIES_DIR - string - option env="LIBRARIES_DIR" - default "../libraries" - source "$RTT_DIR/Kconfig" source "$PKGS_DIR/Kconfig" source "board/Kconfig" -source "$LIBRARIES_DIR/Kconfig" +source "../libraries/Kconfig" diff --git a/bsp/bouffalo_lab/bl61x/board/Kconfig b/bsp/bouffalo_lab/bl61x/board/Kconfig index 3adc4223830..408952e8ed5 100755 --- a/bsp/bouffalo_lab/bl61x/board/Kconfig +++ b/bsp/bouffalo_lab/bl61x/board/Kconfig @@ -5,6 +5,7 @@ config BSP_USING_BL61X select ARCH_RISCV32 select ARCH_RISCV_FPU_S select BSP_USING_ROMAPI + select RT_USING_CACHE default y config BSP_USING_ROMAPI diff --git a/bsp/bouffalo_lab/bl61x/board/cherryusb_port.c b/bsp/bouffalo_lab/bl61x/board/cherryusb_port.c new file mode 100644 index 00000000000..ecba0e65622 --- /dev/null +++ b/bsp/bouffalo_lab/bl61x/board/cherryusb_port.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/04/23 sakumisu first version + */ +#include + +/* low level init here, this has implemented in cherryusb */ + +/* low level deinit here, this has implemented in cherryusb */ diff --git a/bsp/bouffalo_lab/bl61x/board/usb_config.h b/bsp/bouffalo_lab/bl61x/board/usb_config.h new file mode 100644 index 00000000000..1ecbb4dcca6 --- /dev/null +++ b/bsp/bouffalo_lab/bl61x/board/usb_config.h @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#define CHERRYUSB_VERSION 0x010300 +#define CHERRYUSB_VERSION_STR "v1.3.0" + +/* ================ USB common Configuration ================ */ + +#include + +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) + +#define usb_malloc(size) rt_malloc(size) +#define usb_free(ptr) rt_free(ptr) + +#define memcpy rt_memcpy + +#ifndef CONFIG_USB_DBG_LEVEL +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#ifndef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 4 +#endif + +/* ---------------- FSDEV Configuration ---------------- */ +//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference + +/* ---------------- DWC2 Configuration ---------------- */ +// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) +// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* ---------------- EHCI Configuration ---------------- */ + +#define CONFIG_USB_EHCI_HCCR_OFFSET (0x0) +#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 +#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USB_EHCI_QTD_NUM 3 +#define CONFIG_USB_EHCI_ITD_NUM 20 +#define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE +// #define CONFIG_USB_EHCI_CONFIGFLAG +// #define CONFIG_USB_EHCI_ISO +// #define CONFIG_USB_EHCI_WITH_OHCI + +/* ---------------- OHCI Configuration ---------------- */ +#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0) + +/* ---------------- XHCI Configuration ---------------- */ +#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0) + +/* ---------------- DWC2 Configuration ---------------- */ +/* largest non-periodic USB packet used / 4 */ +// #define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4) +/* largest periodic USB packet used / 4 */ +// #define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4) +/* + * (largest USB packet used / 4) + 1 for status information + 1 transfer complete + + * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario + */ +// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +#endif diff --git a/bsp/bouffalo_lab/bl61x/rtconfig.h b/bsp/bouffalo_lab/bl61x/rtconfig.h index b64a029ab4a..b2cbd54593d 100644 --- a/bsp/bouffalo_lab/bl61x/rtconfig.h +++ b/bsp/bouffalo_lab/bl61x/rtconfig.h @@ -1,14 +1,11 @@ #ifndef RT_CONFIG_H__ #define RT_CONFIG_H__ -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Project Configuration */ - /* RT-Thread Kernel */ #define RT_NAME_MAX 8 #define RT_CPUS_NR 1 -#define RT_ALIGN_SIZE 8 +#define RT_ALIGN_SIZE 32 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 #define RT_TICK_PER_SECOND 1000 @@ -17,15 +14,20 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 512 +#define IDLE_THREAD_STACK_SIZE 2048 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 2048 /* kservice optimization */ -#define RT_KSERVICE_USING_STDLIB +/* end of kservice optimization */ + +/* klibc optimization */ + +/* end of klibc optimization */ #define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT #define RT_DEBUGING_COLOR #define RT_DEBUGING_CONTEXT @@ -36,6 +38,7 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ /* Memory Management */ @@ -43,12 +46,15 @@ #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP +/* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50100 +#define RT_VER_NUM 0x50200 #define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_CACHE #define ARCH_RISCV #define ARCH_RISCV_FPU #define ARCH_RISCV_FPU_S @@ -99,8 +105,10 @@ #define RT_DFS_ELM_MAX_SECTOR_SIZE 512 #define RT_DFS_ELM_REENTRANT #define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +/* end of elm-chan's FatFs, Generic FAT Filesystem Module */ #define RT_USING_DFS_DEVFS #define RT_USING_DFS_ROMFS +/* end of DFS: device virtual file system */ /* Device Drivers */ @@ -117,9 +125,17 @@ #define RT_MMCSD_THREAD_PREORITY 22 #define RT_MMCSD_MAX_PARTITION 16 #define RT_USING_PIN - -/* Using USB */ - +#define RT_USING_CHERRYUSB +#define RT_CHERRYUSB_HOST +#define RT_CHERRYUSB_HOST_EHCI_BL +#define RT_CHERRYUSB_HOST_CDC_ACM +#define RT_CHERRYUSB_HOST_HID +#define RT_CHERRYUSB_HOST_MSC +#define RT_CHERRYUSB_HOST_TEMPLATE +#define TEST_USBH_CDC_ACM 1 +#define TEST_USBH_HID 1 +#define TEST_USBH_MSC 0 +/* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -131,6 +147,8 @@ #define RT_LIBC_TZ_DEFAULT_HOUR 8 #define RT_LIBC_TZ_DEFAULT_MIN 0 #define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ @@ -140,18 +158,30 @@ /* Socket is in the 'Network' category */ +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ /* Network */ +/* end of Network */ /* Memory protection */ +/* end of Memory protection */ /* Utilities */ +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ /* RT-Thread Utestcases */ +/* end of RT-Thread Utestcases */ /* RT-Thread online packages */ @@ -162,57 +192,78 @@ /* Marvell WiFi */ +/* end of Marvell WiFi */ /* Wiced WiFi */ +/* end of Wiced WiFi */ /* CYW43012 WiFi */ +/* end of CYW43012 WiFi */ /* BL808 WiFi */ +/* end of BL808 WiFi */ /* CYW43439 WiFi */ +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ /* IoT Cloud */ +/* end of IoT Cloud */ +/* end of IoT - internet of things */ /* security packages */ +/* end of security packages */ /* language packages */ /* JSON: JavaScript Object Notation, a lightweight data-interchange format */ +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ /* XML: Extensible Markup Language */ +/* end of XML: Extensible Markup Language */ +/* end of language packages */ /* multimedia packages */ /* LVGL: powerful and easy-to-use embedded GUI library */ +/* end of LVGL: powerful and easy-to-use embedded GUI library */ /* u8g2: a monochrome graphic library */ +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ /* tools packages */ +/* end of tools packages */ /* system packages */ /* enhanced kernel services */ +/* end of enhanced kernel services */ /* acceleration: Assembly language or algorithmic acceleration packages */ +/* end of acceleration: Assembly language or algorithmic acceleration packages */ /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ /* Micrium: Micrium software products porting for RT-Thread */ +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ /* peripheral libraries and drivers */ @@ -220,66 +271,90 @@ /* STM32 HAL & SDK Drivers */ +/* end of STM32 HAL & SDK Drivers */ /* Kendryte SDK */ +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ /* sensors drivers */ +/* end of sensors drivers */ /* touch drivers */ +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ /* AI packages */ +/* end of AI packages */ /* Signal Processing and Control Algorithm Packages */ +/* end of Signal Processing and Control Algorithm Packages */ /* miscellaneous packages */ /* project laboratory */ +/* end of project laboratory */ + /* samples: kernel and components samples */ +/* end of samples: kernel and components samples */ /* entertainment: terminal games and other interesting software packages */ +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ /* Arduino libraries */ /* Projects and Demos */ +/* end of Projects and Demos */ /* Sensors */ +/* end of Sensors */ /* Display */ +/* end of Display */ /* Timing */ +/* end of Timing */ /* Data Processing */ +/* end of Data Processing */ /* Data Storage */ /* Communication */ +/* end of Communication */ /* Device Control */ +/* end of Device Control */ /* Other */ +/* end of Other */ /* Signal IO */ +/* end of Signal IO */ /* Uncategorized */ +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ #define BSP_USING_BL61X #define BSP_USING_ROMAPI #define BSP_USING_BL61X_MODULE_DEFAULT @@ -292,5 +367,7 @@ #define BSP_USING_UART0 #define UART0_TX_USING_GPIO21 #define UART0_RX_USING_GPIO22 +/* end of General Purpose UARTs */ +/* end of General Drivers Configuration */ #endif diff --git a/bsp/bouffalo_lab/libraries/Kconfig b/bsp/bouffalo_lab/libraries/Kconfig index f9c6d3e44c6..62737d7920c 100755 --- a/bsp/bouffalo_lab/libraries/Kconfig +++ b/bsp/bouffalo_lab/libraries/Kconfig @@ -1,2 +1,1519 @@ -source "$BSP_DIR/$LIBRARIES_DIR/rt_drivers/Kconfig" +menu "General Drivers Configuration" + config BSP_DRIVER_DEBUG + bool "Enable Driver Debug Log Output" + default n + + menu "General Purpose UARTs" + menuconfig BSP_USING_UART0 + bool "Enable UART0" + default y + if BSP_USING_UART0 + choice + prompt "UART0 TX PIN" + default UART0_TX_USING_GPIO16 if BSP_USING_BL60X + default UART0_TX_USING_GPIO21 if BSP_USING_BL61X + default UART0_TX_USING_GPIO14 if BSP_USING_BL70X + default UART0_TX_USING_GPIO14 if BSP_USING_BL808 + + config UART0_TX_USING_GPIO0 + bool "GPIO_0" + config UART0_TX_USING_GPIO1 + bool "GPIO_1" + config UART0_TX_USING_GPIO2 + bool "GPIO_2" + config UART0_TX_USING_GPIO3 + bool "GPIO_3" + config UART0_TX_USING_GPIO4 + bool "GPIO_4" + config UART0_TX_USING_GPIO5 + bool "GPIO_5" + config UART0_TX_USING_GPIO6 + bool "GPIO_6" + config UART0_TX_USING_GPIO7 + bool "GPIO_7" + config UART0_TX_USING_GPIO8 + bool "GPIO_8" + config UART0_TX_USING_GPIO9 + bool "GPIO_9" + config UART0_TX_USING_GPIO10 + bool "GPIO_10" + config UART0_TX_USING_GPIO11 + bool "GPIO_11" + config UART0_TX_USING_GPIO12 + bool "GPIO_12" + config UART0_TX_USING_GPIO13 + bool "GPIO_13" + config UART0_TX_USING_GPIO13 + bool "GPIO_13" + config UART0_TX_USING_GPIO14 + bool "GPIO_14" + config UART0_TX_USING_GPIO15 + bool "GPIO_15" + config UART0_TX_USING_GPIO16 + bool "GPIO_16" + config UART0_TX_USING_GPIO17 + bool "GPIO_17" + config UART0_TX_USING_GPIO18 + bool "GPIO_18" + config UART0_TX_USING_GPIO19 + bool "GPIO_19" + config UART0_TX_USING_GPIO20 + bool "GPIO_20" + config UART0_TX_USING_GPIO21 + bool "GPIO_21" + config UART0_TX_USING_GPIO22 + bool "GPIO_22" + config UART0_TX_USING_GPIO23 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_23" + config UART0_TX_USING_GPIO24 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_24" + config UART0_TX_USING_GPIO25 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_25" + config UART0_TX_USING_GPIO26 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_26" + config UART0_TX_USING_GPIO27 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_27" + config UART0_TX_USING_GPIO28 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_28" + config UART0_TX_USING_GPIO29 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_29" + config UART0_TX_USING_GPIO30 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_30" + config UART0_TX_USING_GPIO31 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_31" + config UART0_TX_USING_GPIO32 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_32" + config UART0_TX_USING_GPIO33 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_33" + config UART0_TX_USING_GPIO34 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_34" + config UART0_TX_USING_GPIO35 + depends on BSP_USING_BL808 + bool "GPIO_35" + config UART0_TX_USING_GPIO36 + depends on BSP_USING_BL808 + bool "GPIO_36" + config UART0_TX_USING_GPIO37 + depends on BSP_USING_BL808 + bool "GPIO_37" + config UART0_TX_USING_GPIO38 + depends on BSP_USING_BL808 + bool "GPIO_38" + config UART0_TX_USING_GPIO39 + depends on BSP_USING_BL808 + bool "GPIO_39" + config UART0_TX_USING_GPIO44 + depends on BSP_USING_BL808 + bool "GPIO_44" + config UART0_TX_USING_GPIO45 + depends on BSP_USING_BL808 + bool "GPIO_45" + endchoice + + choice + prompt "UART0 RX PIN" + default UART0_RX_USING_GPIO7 if BSP_USING_BL60X + default UART0_RX_USING_GPIO22 if BSP_USING_BL61X + default UART0_RX_USING_GPIO23 if BSP_USING_BL70X + default UART0_RX_USING_GPIO15 if BSP_USING_BL808 + + config UART0_RX_USING_GPIO0 + bool "GPIO_0" + config UART0_RX_USING_GPIO1 + bool "GPIO_1" + config UART0_RX_USING_GPIO2 + bool "GPIO_2" + config UART0_RX_USING_GPIO3 + bool "GPIO_3" + config UART0_RX_USING_GPIO4 + bool "GPIO_4" + config UART0_RX_USING_GPIO5 + bool "GPIO_5" + config UART0_RX_USING_GPIO6 + bool "GPIO_6" + config UART0_RX_USING_GPIO7 + bool "GPIO_7" + config UART0_RX_USING_GPIO8 + bool "GPIO_8" + config UART0_RX_USING_GPIO9 + bool "GPIO_9" + config UART0_RX_USING_GPIO10 + bool "GPIO_10" + config UART0_RX_USING_GPIO11 + bool "GPIO_11" + config UART0_RX_USING_GPIO12 + bool "GPIO_12" + config UART0_RX_USING_GPIO13 + bool "GPIO_13" + config UART0_RX_USING_GPIO14 + bool "GPIO_14" + config UART0_RX_USING_GPIO15 + bool "GPIO_15" + config UART0_RX_USING_GPIO16 + bool "GPIO_16" + config UART0_RX_USING_GPIO17 + bool "GPIO_17" + config UART0_RX_USING_GPIO18 + bool "GPIO_18" + config UART0_RX_USING_GPIO19 + bool "GPIO_19" + config UART0_RX_USING_GPIO20 + bool "GPIO_20" + config UART0_RX_USING_GPIO21 + bool "GPIO_21" + config UART0_RX_USING_GPIO22 + bool "GPIO_22" + config UART0_RX_USING_GPIO23 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_23" + config UART0_RX_USING_GPIO24 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_24" + config UART0_RX_USING_GPIO25 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_25" + config UART0_RX_USING_GPIO26 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_26" + config UART0_RX_USING_GPIO27 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_27" + config UART0_RX_USING_GPIO28 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_28" + config UART0_RX_USING_GPIO29 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_29" + config UART0_RX_USING_GPIO30 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_30" + config UART0_RX_USING_GPIO31 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_31" + config UART0_RX_USING_GPIO32 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_32" + config UART0_RX_USING_GPIO33 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_33" + config UART0_RX_USING_GPIO34 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_34" + config UART0_RX_USING_GPIO35 + depends on BSP_USING_BL808 + bool "GPIO_35" + config UART0_RX_USING_GPIO36 + depends on BSP_USING_BL808 + bool "GPIO_36" + config UART0_RX_USING_GPIO37 + depends on BSP_USING_BL808 + bool "GPIO_37" + config UART0_RX_USING_GPIO38 + depends on BSP_USING_BL808 + bool "GPIO_38" + config UART0_RX_USING_GPIO39 + depends on BSP_USING_BL808 + bool "GPIO_39" + config UART0_RX_USING_GPIO44 + depends on BSP_USING_BL808 + bool "GPIO_44" + config UART0_RX_USING_GPIO45 + depends on BSP_USING_BL808 + bool "GPIO_45" + + endchoice + endif + + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + choice + prompt "UART1 TX PIN" + default UART1_TX_USING_GPIO4 if BSP_USING_BL60X + default UART1_TX_USING_GPIO16 if BSP_USING_BL61X + default UART1_TX_USING_GPIO26 if BSP_USING_BL70X + default UART1_TX_USING_GPIO18 if BSP_USING_BL808 + + config UART1_TX_USING_GPIO0 + bool "GPIO_0" + config UART1_TX_USING_GPIO1 + bool "GPIO_1" + config UART1_TX_USING_GPIO2 + bool "GPIO_2" + config UART1_TX_USING_GPIO3 + bool "GPIO_3" + config UART1_TX_USING_GPIO4 + bool "GPIO_4" + config UART1_TX_USING_GPIO5 + bool "GPIO_5" + config UART1_TX_USING_GPIO6 + bool "GPIO_6" + config UART1_TX_USING_GPIO7 + bool "GPIO_7" + config UART1_TX_USING_GPIO8 + bool "GPIO_8" + config UART1_TX_USING_GPIO9 + bool "GPIO_9" + config UART1_TX_USING_GPIO10 + bool "GPIO_10" + config UART1_TX_USING_GPIO11 + bool "GPIO_11" + config UART1_TX_USING_GPIO12 + bool "GPIO_12" + config UART1_TX_USING_GPIO13 + bool "GPIO_13" + config UART1_TX_USING_GPIO14 + bool "GPIO_14" + config UART1_TX_USING_GPIO15 + bool "GPIO_15" + config UART1_TX_USING_GPIO16 + bool "GPIO_16" + config UART1_TX_USING_GPIO17 + bool "GPIO_17" + config UART1_TX_USING_GPIO18 + bool "GPIO_18" + config UART1_TX_USING_GPIO19 + bool "GPIO_19" + config UART1_TX_USING_GPIO20 + bool "GPIO_20" + config UART1_TX_USING_GPIO21 + bool "GPIO_21" + config UART1_TX_USING_GPIO22 + bool "GPIO_22" + config UART1_TX_USING_GPIO23 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_23" + config UART1_TX_USING_GPIO24 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_24" + config UART1_TX_USING_GPIO25 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_25" + config UART1_TX_USING_GPIO26 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_26" + config UART1_TX_USING_GPIO27 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_27" + config UART1_TX_USING_GPIO28 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_28" + config UART1_TX_USING_GPIO29 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_29" + config UART1_TX_USING_GPIO30 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_30" + config UART1_TX_USING_GPIO31 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_31" + config UART1_TX_USING_GPIO32 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_32" + config UART1_TX_USING_GPIO33 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_33" + config UART1_TX_USING_GPIO34 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_34" + config UART1_TX_USING_GPIO35 + depends on BSP_USING_BL808 + bool "GPIO_35" + config UART1_TX_USING_GPIO36 + depends on BSP_USING_BL808 + bool "GPIO_36" + config UART1_TX_USING_GPIO37 + depends on BSP_USING_BL808 + bool "GPIO_37" + config UART1_TX_USING_GPIO38 + depends on BSP_USING_BL808 + bool "GPIO_38" + config UART1_TX_USING_GPIO39 + depends on BSP_USING_BL808 + bool "GPIO_39" + config UART1_TX_USING_GPIO44 + depends on BSP_USING_BL808 + bool "GPIO_44" + config UART1_TX_USING_GPIO45 + depends on BSP_USING_BL808 + bool "GPIO_45" + endchoice + + choice + prompt "UART1 RX PIN" + default UART1_RX_USING_GPIO3 if BSP_USING_BL60X + default UART1_RX_USING_GPIO17 if BSP_USING_BL61X + default UART1_RX_USING_GPIO27 if BSP_USING_BL70X + default UART1_RX_USING_GPIO19 if BSP_USING_BL808 + + config UART1_RX_USING_GPIO0 + bool "GPIO_0" + config UART1_RX_USING_GPIO1 + bool "GPIO_1" + config UART1_RX_USING_GPIO2 + bool "GPIO_2" + config UART1_RX_USING_GPIO3 + bool "GPIO_3" + config UART1_RX_USING_GPIO4 + bool "GPIO_4" + config UART1_RX_USING_GPIO5 + bool "GPIO_5" + config UART1_RX_USING_GPIO6 + bool "GPIO_6" + config UART1_RX_USING_GPIO7 + bool "GPIO_7" + config UART1_RX_USING_GPIO8 + bool "GPIO_8" + config UART1_RX_USING_GPIO9 + bool "GPIO_9" + config UART1_RX_USING_GPIO10 + bool "GPIO_10" + config UART1_RX_USING_GPIO11 + bool "GPIO_11" + config UART1_RX_USING_GPIO12 + bool "GPIO_12" + config UART1_RX_USING_GPIO13 + bool "GPIO_13" + config UART1_RX_USING_GPIO14 + bool "GPIO_14" + config UART1_RX_USING_GPIO15 + bool "GPIO_15" + config UART1_RX_USING_GPIO16 + bool "GPIO_16" + config UART1_RX_USING_GPIO17 + bool "GPIO_17" + config UART1_RX_USING_GPIO18 + bool "GPIO_18" + config UART1_RX_USING_GPIO19 + bool "GPIO_19" + config UART1_RX_USING_GPIO20 + bool "GPIO_20" + config UART1_RX_USING_GPIO21 + bool "GPIO_21" + config UART1_RX_USING_GPIO22 + bool "GPIO_22" + config UART1_RX_USING_GPIO23 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_23" + config UART1_RX_USING_GPIO24 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_24" + config UART1_RX_USING_GPIO25 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_25" + config UART1_RX_USING_GPIO26 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_26" + config UART1_RX_USING_GPIO27 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_27" + config UART1_RX_USING_GPIO28 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_28" + config UART1_RX_USING_GPIO29 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_29" + config UART1_RX_USING_GPIO30 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_30" + config UART1_RX_USING_GPIO31 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_31" + config UART1_RX_USING_GPIO32 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_32" + config UART1_RX_USING_GPIO33 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_33" + config UART1_RX_USING_GPIO34 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_34" + config UART1_RX_USING_GPIO35 + depends on BSP_USING_BL808 + bool "GPIO_35" + config UART1_RX_USING_GPIO36 + depends on BSP_USING_BL808 + bool "GPIO_36" + config UART1_RX_USING_GPIO37 + depends on BSP_USING_BL808 + bool "GPIO_37" + config UART1_RX_USING_GPIO38 + depends on BSP_USING_BL808 + bool "GPIO_38" + config UART1_RX_USING_GPIO39 + depends on BSP_USING_BL808 + bool "GPIO_39" + config UART1_RX_USING_GPIO44 + depends on BSP_USING_BL808 + bool "GPIO_44" + config UART1_RX_USING_GPIO45 + depends on BSP_USING_BL808 + bool "GPIO_45" + endchoice + endif + + if BSP_USING_BL808 + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + choice + prompt "UART2 TX PIN" + default UART2_TX_USING_GPIO20 + + config UART2_TX_USING_GPIO0 + bool "GPIO_0" + config UART2_TX_USING_GPIO1 + bool "GPIO_1" + config UART2_TX_USING_GPIO2 + bool "GPIO_2" + config UART2_TX_USING_GPIO3 + bool "GPIO_3" + config UART2_TX_USING_GPIO4 + bool "GPIO_4" + config UART2_TX_USING_GPIO5 + bool "GPIO_5" + config UART2_TX_USING_GPIO6 + bool "GPIO_6" + config UART2_TX_USING_GPIO7 + bool "GPIO_7" + config UART2_TX_USING_GPIO8 + bool "GPIO_8" + config UART2_TX_USING_GPIO9 + bool "GPIO_9" + config UART2_TX_USING_GPIO10 + bool "GPIO_10" + config UART2_TX_USING_GPIO11 + bool "GPIO_11" + config UART2_TX_USING_GPIO12 + bool "GPIO_12" + config UART2_TX_USING_GPIO13 + bool "GPIO_13" + config UART2_TX_USING_GPIO14 + bool "GPIO_14" + config UART2_TX_USING_GPIO15 + bool "GPIO_15" + config UART2_TX_USING_GPIO16 + bool "GPIO_16" + config UART2_TX_USING_GPIO17 + bool "GPIO_17" + config UART2_TX_USING_GPIO18 + bool "GPIO_18" + config UART2_TX_USING_GPIO19 + bool "GPIO_19" + config UART2_TX_USING_GPIO20 + bool "GPIO_20" + config UART2_TX_USING_GPIO21 + bool "GPIO_21" + config UART2_TX_USING_GPIO22 + bool "GPIO_22" + config UART2_TX_USING_GPIO23 + bool "GPIO_23" + config UART2_TX_USING_GPIO24 + bool "GPIO_24" + config UART2_TX_USING_GPIO25 + bool "GPIO_25" + config UART2_TX_USING_GPIO26 + bool "GPIO_26" + config UART2_TX_USING_GPIO27 + bool "GPIO_27" + config UART2_TX_USING_GPIO28 + bool "GPIO_28" + config UART2_TX_USING_GPIO29 + bool "GPIO_29" + config UART2_TX_USING_GPIO30 + bool "GPIO_30" + config UART2_TX_USING_GPIO31 + bool "GPIO_31" + config UART2_TX_USING_GPIO32 + bool "GPIO_32" + config UART2_TX_USING_GPIO33 + bool "GPIO_33" + config UART2_TX_USING_GPIO34 + bool "GPIO_34" + config UART2_TX_USING_GPIO35 + bool "GPIO_35" + config UART2_TX_USING_GPIO36 + bool "GPIO_36" + config UART2_TX_USING_GPIO37 + bool "GPIO_37" + config UART2_TX_USING_GPIO38 + bool "GPIO_38" + config UART2_TX_USING_GPIO39 + bool "GPIO_39" + config UART2_TX_USING_GPIO44 + bool "GPIO_44" + config UART2_TX_USING_GPIO45 + bool "GPIO_45" + endchoice + choice + prompt "UART2 RX PIN" + default UART2_RX_USING_GPIO21 + + config UART2_RX_USING_GPIO0 + bool "GPIO_0" + config UART2_RX_USING_GPIO1 + bool "GPIO_1" + config UART2_RX_USING_GPIO2 + bool "GPIO_2" + config UART2_RX_USING_GPIO3 + bool "GPIO_3" + config UART2_RX_USING_GPIO4 + bool "GPIO_4" + config UART2_RX_USING_GPIO5 + bool "GPIO_5" + config UART2_RX_USING_GPIO6 + bool "GPIO_6" + config UART2_RX_USING_GPIO7 + bool "GPIO_7" + config UART2_RX_USING_GPIO8 + bool "GPIO_8" + config UART2_RX_USING_GPIO9 + bool "GPIO_9" + config UART2_RX_USING_GPIO10 + bool "GPIO_10" + config UART2_RX_USING_GPIO11 + bool "GPIO_11" + config UART2_RX_USING_GPIO12 + bool "GPIO_12" + config UART2_RX_USING_GPIO13 + bool "GPIO_13" + config UART2_RX_USING_GPIO13 + bool "GPIO_13" + config UART2_RX_USING_GPIO14 + bool "GPIO_14" + config UART2_RX_USING_GPIO15 + bool "GPIO_15" + config UART2_RX_USING_GPIO16 + bool "GPIO_16" + config UART2_RX_USING_GPIO17 + bool "GPIO_17" + config UART2_RX_USING_GPIO18 + bool "GPIO_18" + config UART2_RX_USING_GPIO19 + bool "GPIO_19" + config UART2_RX_USING_GPIO20 + bool "GPIO_20" + config UART2_RX_USING_GPIO21 + bool "GPIO_21" + config UART2_RX_USING_GPIO22 + bool "GPIO_22" + config UART2_RX_USING_GPIO23 + bool "GPIO_23" + config UART2_RX_USING_GPIO24 + bool "GPIO_24" + config UART2_RX_USING_GPIO25 + bool "GPIO_25" + config UART2_RX_USING_GPIO26 + bool "GPIO_26" + config UART2_RX_USING_GPIO27 + bool "GPIO_27" + config UART2_RX_USING_GPIO28 + bool "GPIO_28" + config UART2_RX_USING_GPIO29 + bool "GPIO_29" + config UART2_RX_USING_GPIO30 + bool "GPIO_30" + config UART2_RX_USING_GPIO31 + bool "GPIO_31" + config UART2_RX_USING_GPIO32 + bool "GPIO_32" + config UART2_RX_USING_GPIO33 + bool "GPIO_33" + config UART2_RX_USING_GPIO34 + bool "GPIO_34" + config UART2_RX_USING_GPIO35 + bool "GPIO_35" + config UART2_RX_USING_GPIO36 + bool "GPIO_36" + config UART2_RX_USING_GPIO37 + bool "GPIO_37" + config UART2_RX_USING_GPIO38 + bool "GPIO_38" + config UART2_RX_USING_GPIO39 + bool "GPIO_39" + config UART2_RX_USING_GPIO44 + bool "GPIO_44" + config UART2_RX_USING_GPIO45 + bool "GPIO_45" + endchoice + endif + endif + + endmenu + + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default n + + config BSP_USING_ADC + bool "Enable ADC" + select RT_USING_ADC + default n + if BSP_USING_ADC + config BSP_ADC_DMA_CHANNEL + string "ADC DMA Channel Name" + default "dma0_ch2" + config BSP_USING_ADC_CH0 + bool "USING ADC CH0" + default n + if BSP_USING_ADC_CH0 + config BSP_ADC_CH0_PIN + int "ADC CH0 Pin Num (GPIO_X)" + default 17 + endif + config BSP_USING_ADC_CH1 + bool "USING ADC CH1" + default n + if BSP_USING_ADC_CH1 + config BSP_ADC_CH1_PIN + int "ADC CH1 Pin Num (GPIO_X)" + default 5 + endif + config BSP_USING_ADC_CH2 + bool "USING ADC CH2" + default n + if BSP_USING_ADC_CH2 + config BSP_ADC_CH2_PIN + int "ADC CH2 Pin Num (GPIO_X)" + default 4 + endif + config BSP_USING_ADC_CH3 + bool "USING ADC CH3" + default n + if BSP_USING_ADC_CH3 + config BSP_ADC_CH3_PIN + int "ADC CH3 Pin Num (GPIO_X)" + default 11 + endif + config BSP_USING_ADC_CH4 + bool "USING ADC CH4" + default n + if BSP_USING_ADC_CH4 + config BSP_ADC_CH4_PIN + int "ADC CH4 Pin Num (GPIO_X)" + default 6 + endif + config BSP_USING_ADC_CH5 + bool "USING ADC CH5" + default n + if BSP_USING_ADC_CH5 + config BSP_ADC_CH5_PIN + int "ADC CH5 Pin Num (GPIO_X)" + default 40 + endif + config BSP_USING_ADC_CH6 + bool "USING ADC CH6" + default n + if BSP_USING_ADC_CH6 + config BSP_ADC_CH6_PIN + int "ADC CH6 Pin Num (GPIO_X)" + default 12 + endif + config BSP_USING_ADC_CH7 + bool "USING ADC CH7" + default n + if BSP_USING_ADC_CH7 + config BSP_ADC_CH7_PIN + int "ADC CH7 Pin Num (GPIO_X)" + default 13 + endif + config BSP_USING_ADC_CH8 + bool "USING ADC CH8" + default n + if BSP_USING_ADC_CH8 + config BSP_ADC_CH8_PIN + int "ADC CH8 Pin Num (GPIO_X)" + default 16 + endif + config BSP_USING_ADC_CH9 + bool "USING ADC CH9" + default n + if BSP_USING_ADC_CH9 + config BSP_ADC_CH9_PIN + int "ADC CH9 Pin Num (GPIO_X)" + default 18 + endif + config BSP_USING_ADC_CH10 + bool "USING ADC CH10" + default n + if BSP_USING_ADC_CH10 + config BSP_ADC_CH10_PIN + int "ADC CH10 Pin Num (GPIO_X)" + default 19 + endif + endif + + config BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + + config BSP_USING_WDT + bool "Enable Watchdog Timer" + select RT_USING_WDT + default n + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + config BSP_USING_PWM0 + bool "Enable PWM0" + default n + + config BSP_USING_PWM1 + bool "Enable PWM1" + default n + + config BSP_USING_PWM2 + bool "Enable PWM2" + default n + + config BSP_USING_PWM3 + bool "Enable PWM3" + default n + endif + + menuconfig BSP_USING_HWTIMER + bool "Enable HWTIMER" + default n + select RT_USING_HWTIMER + if BSP_USING_HWTIMER + config BSP_USING_TIMER0 + bool "Enable TIMER0" + default n + config BSP_USING_TIMER1 + bool "Enable TIMER1" + default n + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + default n + select RT_USING_I2C + if BSP_USING_I2C + config BSP_USING_HW_I2C + bool "Enable Hardware I2C BUS" + default n + if BSP_USING_HW_I2C + menuconfig BSP_USING_I2C0 + bool "Enable I2C0 (hardware)" + default n + if BSP_USING_I2C0 + choice + prompt "I2C0 SCL" + default I2C0_SCL_USING_GPIO14 + + config I2C0_SCL_USING_GPIO0 + bool "GPIO_0" + config I2C0_SCL_USING_GPIO2 + bool "GPIO_2" + config I2C0_SCL_USING_GPIO4 + bool "GPIO_4" + config I2C0_SCL_USING_GPIO6 + bool "GPIO_6" + config I2C0_SCL_USING_GPIO8 + bool "GPIO_8" + config I2C0_SCL_USING_GPIO10 + bool "GPIO_10" + config I2C0_SCL_USING_GPIO12 + bool "GPIO_12" + config I2C0_SCL_USING_GPIO14 + bool "GPIO_14" + config I2C0_SCL_USING_GPIO16 + bool "GPIO_16" + config I2C0_SCL_USING_GPIO18 + bool "GPIO_18" + config I2C0_SCL_USING_GPIO20 + bool "GPIO_20" + config I2C0_SCL_USING_GPIO22 + bool "GPIO_22" + config I2C0_SCL_USING_GPIO24 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_8" + config I2C0_SCL_USING_GPIO26 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_26" + config I2C0_SCL_USING_GPIO28 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_28" + config I2C0_SCL_USING_GPIO30 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_30" + config I2C0_SCL_USING_GPIO32 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_32" + config I2C0_SCL_USING_GPIO34 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_34" + config I2C0_SDA_USING_GPIO36 + depends on BSP_USING_BL808 + bool "GPIO_36" + config I2C0_SDA_USING_GPIO38 + depends on BSP_USING_BL808 + bool "GPIO_38" + config I2C0_SDA_USING_GPIO40 + depends on BSP_USING_BL808 + bool "GPIO_40" + config I2C1_SDA_USING_GPIO42 + depends on BSP_USING_BL808 + bool "GPIO_42" + config I2C0_SDA_USING_GPIO44 + depends on BSP_USING_BL808 + bool "GPIO_44" + endchoice + + choice + prompt "I2C0 SDA" + default I2C0_SDA_USING_GPIO15 + + config I2C0_SDA_USING_GPIO1 + bool "GPIO_1" + config I2C0_SDA_USING_GPIO3 + bool "GPIO_3" + config I2C0_SDA_USING_GPIO5 + bool "GPIO_5" + config I2C0_SDA_USING_GPIO7 + bool "GPIO_7" + config I2C0_SDA_USING_GPIO9 + bool "GPIO_9" + config I2C0_SDA_USING_GPIO11 + bool "GPIO_11" + config I2C0_SDA_USING_GPIO13 + bool "GPIO_13" + config I2C0_SDA_USING_GPIO15 + bool "GPIO_15" + config I2C0_SDA_USING_GPIO17 + bool "GPIO_17" + config I2C0_SDA_USING_GPIO19 + bool "GPIO_19" + config I2C0_SDA_USING_GPIO21 + bool "GPIO_21" + config I2C0_SDA_USING_GPIO23 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_23" + config I2C0_SDA_USING_GPIO25 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_25" + config I2C0_SDA_USING_GPIO27 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_27" + config I2C0_SDA_USING_GPIO29 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_29" + config I2C0_SDA_USING_GPIO31 + depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_31" + config I2C0_SDA_USING_GPIO33 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_33" + config I2C0_SDA_USING_GPIO35 + depends on BSP_USING_BL808 + bool "GPIO_35" + config I2C0_SDA_USING_GPIO37 + depends on BSP_USING_BL808 + bool "GPIO_37" + config I2C0_SDA_USING_GPIO39 + depends on BSP_USING_BL808 + bool "GPIO_39" + config I2C0_SDA_USING_GPIO41 + depends on BSP_USING_BL808 + bool "GPIO_41" + config I2C0_SDA_USING_GPIO43 + depends on BSP_USING_BL808 + bool "GPIO_43" + config I2C0_SDA_USING_GPIO45 + depends on BSP_USING_BL808 + bool "GPIO_45" + endchoice + + config I2C0_FREQUENCY + int "I2C0 Frequency" + default 400000 + endif + + + menuconfig BSP_USING_I2C1 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "Enable I2C1 (hardware)" + default n + if BSP_USING_I2C1 + choice + prompt "I2C1 SCL" + default I2C1_SCL_USING_GPIO0 + + config I2C1_SCL_USING_GPIO0 + bool "GPIO_0" + config I2C1_SCL_USING_GPIO2 + bool "GPIO_2" + config I2C1_SCL_USING_GPIO4 + bool "GPIO_4" + config I2C1_SCL_USING_GPIO6 + bool "GPIO_6" + config I2C1_SCL_USING_GPIO8 + bool "GPIO_8" + config I2C1_SCL_USING_GPIO10 + bool "GPIO_10" + config I2C1_SCL_USING_GPIO12 + bool "GPIO_12" + config I2C1_SCL_USING_GPIO14 + bool "GPIO_14" + config I2C1_SCL_USING_GPIO16 + bool "GPIO_16" + config I2C1_SCL_USING_GPIO18 + bool "GPIO_18" + config I2C1_SCL_USING_GPIO20 + bool "GPIO_20" + config I2C1_SCL_USING_GPIO22 + bool "GPIO_22" + config I2C1_SCL_USING_GPIO24 + bool "GPIO_24" + config I2C1_SCL_USING_GPIO26 + bool "GPIO_26" + config I2C1_SCL_USING_GPIO28 + bool "GPIO_28" + config I2C1_SCL_USING_GPIO30 + bool "GPIO_30" + config I2C1_SCL_USING_GPIO32 + bool "GPIO_32" + config I2C1_SCL_USING_GPIO34 + bool "GPIO_34" + config I2C1_SDA_USING_GPIO36 + depends on BSP_USING_BL808 + bool "GPIO_36" + config I2C1_SDA_USING_GPIO38 + depends on BSP_USING_BL808 + bool "GPIO_38" + config I2C1_SDA_USING_GPIO40 + depends on BSP_USING_BL808 + bool "GPIO_40" + config I2C1_SDA_USING_GPIO42 + depends on BSP_USING_BL808 + bool "GPIO_42" + config I2C1_SDA_USING_GPIO44 + depends on BSP_USING_BL808 + bool "GPIO_44" + endchoice + + choice + prompt "I2C1 SDA" + default I2C1_SDA_USING_GPIO1 + + config I2C1_SDA_USING_GPIO1 + bool "GPIO_1" + config I2C1_SDA_USING_GPIO3 + bool "GPIO_3" + config I2C1_SDA_USING_GPIO5 + bool "GPIO_5" + config I2C1_SDA_USING_GPIO7 + bool "GPIO_7" + config I2C1_SDA_USING_GPIO9 + bool "GPIO_9" + config I2C1_SDA_USING_GPIO11 + bool "GPIO_11" + config I2C1_SDA_USING_GPIO13 + bool "GPIO_13" + config I2C1_SDA_USING_GPIO15 + bool "GPIO_15" + config I2C1_SDA_USING_GPIO17 + bool "GPIO_17" + config I2C1_SDA_USING_GPIO19 + bool "GPIO_19" + config I2C1_SDA_USING_GPIO21 + bool "GPIO_21" + config I2C1_SDA_USING_GPIO23 + bool "GPIO_23" + config I2C1_SDA_USING_GPIO25 + bool "GPIO_25" + config I2C1_SDA_USING_GPIO27 + bool "GPIO_27" + config I2C1_SDA_USING_GPIO29 + bool "GPIO_29" + config I2C1_SDA_USING_GPIO31 + bool "GPIO_31" + config I2C1_SDA_USING_GPIO33 + bool "GPIO_33" + config I2C1_SDA_USING_GPIO35 + depends on BSP_USING_BL808 + bool "GPIO_35" + config I2C1_SDA_USING_GPIO37 + depends on BSP_USING_BL808 + bool "GPIO_37" + config I2C1_SDA_USING_GPIO39 + depends on BSP_USING_BL808 + bool "GPIO_39" + config I2C1_SDA_USING_GPIO41 + depends on BSP_USING_BL808 + bool "GPIO_41" + config I2C1_SDA_USING_GPIO43 + depends on BSP_USING_BL808 + bool "GPIO_43" + config I2C1_SDA_USING_GPIO45 + depends on BSP_USING_BL808 + bool "GPIO_45" + endchoice + + config I2C1_FREQUENCY + int "I2C1 Frequency" + default 400000 + endif + + endif + if !BSP_USING_HW_I2C + menuconfig BSP_USING_SOFT_I2C1 + bool "Enable I2C1 BUS (software simulation)" + select RT_USING_I2C_BITOPS + select BSP_USING_GPIO + default n + if BSP_USING_SOFT_I2C1 + choice + prompt "I2C1 SCL" + default SOFT_I2C1_SCL_USING_GPIO0 + + config SOFT_I2C1_SCL_USING_GPIO0 + bool "GPIO_0" + config SOFT_I2C1_SCL_USING_GPIO2 + bool "GPIO_2" + config SOFT_I2C1_SCL_USING_GPIO4 + bool "GPIO_4" + config SOFT_I2C1_SCL_USING_GPIO6 + bool "GPIO_6" + config SOFT_I2C1_SCL_USING_GPIO8 + bool "GPIO_8" + config SOFT_I2C1_SCL_USING_GPIO10 + bool "GPIO_10" + config SOFT_I2C1_SCL_USING_GPIO12 + bool "GPIO_12" + config SOFT_I2C1_SCL_USING_GPIO14 + bool "GPIO_14" + config SOFT_I2C1_SCL_USING_GPIO16 + bool "GPIO_16" + config SOFT_I2C1_SCL_USING_GPIO18 + bool "GPIO_18" + config SOFT_I2C1_SCL_USING_GPIO20 + bool "GPIO_20" + config SOFT_I2C1_SCL_USING_GPIO22 + bool "GPIO_22" + config SOFT_I2C1_SCL_USING_GPIO24 + bool "GPIO_8" + config SOFT_I2C1_SCL_USING_GPIO26 + bool "GPIO_26" + config SOFT_I2C1_SCL_USING_GPIO28 + bool "GPIO_28" + config SOFT_I2C1_SCL_USING_GPIO30 + bool "GPIO_30" + config SOFT_I2C1_SCL_USING_GPIO32 + bool "GPIO_32" + config SOFT_I2C1_SCL_USING_GPIO34 + bool "GPIO_34" + config SOFT_I2C1_SDA_USING_GPIO36 + depends on BSP_USING_BL808 + bool "GPIO_36" + config SOFT_I2C1_SDA_USING_GPIO38 + depends on BSP_USING_BL808 + bool "GPIO_38" + config SOFT_I2C1_SDA_USING_GPIO40 + depends on BSP_USING_BL808 + bool "GPIO_40" + config SOFT_I2C1_SDA_USING_GPIO42 + depends on BSP_USING_BL808 + bool "GPIO_42" + config SOFT_I2C1_SDA_USING_GPIO44 + depends on BSP_USING_BL808 + bool "GPIO_44" + endchoice + + choice + prompt "I2C1 SDA" + default SOFT_I2C1_SDA_USING_GPIO1 + + config SOFT_I2C1_SDA_USING_GPIO1 + bool "GPIO_1" + config SOFT_I2C1_SDA_USING_GPIO3 + bool "GPIO_3" + config SOFT_I2C1_SDA_USING_GPIO5 + bool "GPIO_5" + config SOFT_I2C1_SDA_USING_GPIO7 + bool "GPIO_7" + config SOFT_I2C1_SDA_USING_GPIO9 + bool "GPIO_9" + config SOFT_I2C1_SDA_USING_GPIO11 + bool "GPIO_11" + config SOFT_I2C1_SDA_USING_GPIO13 + bool "GPIO_13" + config SOFT_I2C1_SDA_USING_GPIO15 + bool "GPIO_15" + config SOFT_I2C1_SDA_USING_GPIO17 + bool "GPIO_17" + config SOFT_I2C1_SDA_USING_GPIO19 + bool "GPIO_19" + config SOFT_I2C1_SDA_USING_GPIO21 + bool "GPIO_21" + config SOFT_I2C1_SDA_USING_GPIO23 + bool "GPIO_23" + config SOFT_I2C1_SDA_USING_GPIO25 + bool "GPIO_25" + config SOFT_I2C1_SDA_USING_GPIO27 + bool "GPIO_27" + config SOFT_I2C1_SDA_USING_GPIO29 + bool "GPIO_29" + config SOFT_I2C1_SDA_USING_GPIO31 + bool "GPIO_31" + config SOFT_I2C1_SDA_USING_GPIO33 + bool "GPIO_33" + config SOFT_I2C1_SDA_USING_GPIO35 + depends on BSP_USING_BL808 + bool "GPIO_35" + config SOFT_I2C1_SDA_USING_GPIO37 + depends on BSP_USING_BL808 + bool "GPIO_37" + config SOFT_I2C1_SDA_USING_GPIO39 + depends on BSP_USING_BL808 + bool "GPIO_39" + config SOFT_I2C1_SDA_USING_GPIO41 + depends on BSP_USING_BL808 + bool "GPIO_41" + config SOFT_I2C1_SDA_USING_GPIO43 + depends on BSP_USING_BL808 + bool "GPIO_43" + config SOFT_I2C1_SDA_USING_GPIO45 + depends on BSP_USING_BL808 + bool "GPIO_45" + endchoice + endif + endif + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI" + select RT_USING_SPI + select RT_USING_PIN + default n + + if BSP_USING_SPI + choice + prompt "SPI SCK PIN" + default SPI_SCK_USING_GPIO3 if BSP_USING_BL60X + default SPI_SCK_USING_GPIO13 if BSP_USING_BL61X + default SPI_SCK_USING_GPIO15 if BSP_USING_BL70X + default SPI_SCK_USING_GPIO19 if BSP_USING_BL808 + + config SPI_SCK_USING_GPIO1 + depends on BSP_USING_BL61X + bool "GPIO_1" + config SPI_SCK_USING_GPIO3 + depends on BSP_USING_BL60X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_3" + config SPI_SCK_USING_GPIO5 + depends on BSP_USING_BL61X + bool "GPIO_5" + config SPI_SCK_USING_GPIO7 + depends on BSP_USING_BL60X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_7" + config SPI_SCK_USING_GPIO9 + depends on BSP_USING_BL61X + bool "GPIO_9" + config SPI_SCK_USING_GPIO11 + depends on BSP_USING_BL60X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_11" + config SPI_SCK_USING_GPIO13 + depends on BSP_USING_BL61X + bool "GPIO_13" + config SPI_SCK_USING_GPIO15 + depends on BSP_USING_BL60X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_15" + config SPI_SCK_USING_GPIO17 + depends on BSP_USING_BL61X + bool "GPIO_17" + config SPI_SCK_USING_GPIO19 + depends on BSP_USING_BL60X || BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_19" + config SPI_SCK_USING_GPIO21 + depends on BSP_USING_BL61X + bool "GPIO_21" + config SPI_SCK_USING_GPIO23 + depends on BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_23" + config SPI_SCK_USING_GPIO25 + depends on BSP_USING_BL61X + bool "GPIO_25" + config SPI_SCK_USING_GPIO27 + depends on BSP_USING_BL70X || BSP_USING_BL808 + bool "GPIO_27" + config SPI_SCK_USING_GPIO29 + depends on BSP_USING_BL61X + bool "GPIO_29" + config SPI_SCK_USING_GPIO31 + depends on BSP_USING_BL808 + bool "GPIO_31" + config SPI_SCK_USING_GPIO33 + depends on BSP_USING_BL61X + bool "GPIO_33" + config SPI_SCK_USING_GPIO35 + depends on BSP_USING_BL808 + bool "GPIO_35" + config SPI_SCK_USING_GPIO39 + depends on BSP_USING_BL808 + bool "GPIO_39" + config SPI_SCK_USING_GPIO43 + depends on BSP_USING_BL808 + bool "GPIO_43" + endchoice + + choice + prompt "SPI MISO PIN" + default SPI_MISO_USING_GPIO0 if BSP_USING_BL60X + default SPI_MISO_USING_GPIO10 if BSP_USING_BL61X + default SPI_MISO_USING_GPIO17 if BSP_USING_BL70X + default SPI_MISO_USING_GPIO22 if BSP_USING_BL808 + + config SPI_MISO_USING_GPIO0 + depends on BSP_USING_BL60X + bool "GPIO_0" + config SPI_MISO_USING_GPIO1 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_1" + config SPI_MISO_USING_GPIO2 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_2" + config SPI_MISO_USING_GPIO4 + depends on BSP_USING_BL60X + bool "GPIO_4" + config SPI_MISO_USING_GPIO5 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_5" + config SPI_MISO_USING_GPIO6 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_6" + config SPI_MISO_USING_GPIO8 + depends on BSP_USING_BL60X + bool "GPIO_8" + config SPI_MISO_USING_GPIO9 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_9" + config SPI_MISO_USING_GPIO10 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_10" + config SPI_MISO_USING_GPIO12 + depends on BSP_USING_BL60X + bool "GPIO_12" + config SPI_MISO_USING_GPIO13 + depends on BSP_USING_BL60X || BSP_USING_BL60X + bool "GPIO_13" + config SPI_MISO_USING_GPIO14 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_14" + config SPI_MISO_USING_GPIO16 + depends on BSP_USING_BL60X + bool "GPIO_16" + config SPI_MISO_USING_GPIO17 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_17" + config SPI_MISO_USING_GPIO18 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_18" + config SPI_MISO_USING_GPIO20 + depends on BSP_USING_BL60X + bool "GPIO_20" + config SPI_MISO_USING_GPIO21 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_21" + config SPI_MISO_USING_GPIO22 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_22" + config SPI_MISO_USING_GPIO25 + depends on BSP_USING_BL70X + bool "GPIO_25" + config SPI_MISO_USING_GPIO26 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_26" + config SPI_MISO_USING_GPIO29 + depends on BSP_USING_BL70X + bool "GPIO_29" + config SPI_MISO_USING_GPIO30 + depends on BSP_USING_BL61X || BSP_USING_BL808 + bool "GPIO_30" + config SPI_MISO_USING_GPIO34 + depends on BSP_USING_BL808 + bool "GPIO_34" + config SPI_MISO_USING_GPIO38 + depends on BSP_USING_BL808 + bool "GPIO_38" + config SPI_MISO_USING_GPIO42 + depends on BSP_USING_BL808 + bool "GPIO_42" + endchoice + + choice + prompt "SPI MOSI PIN" + default SPI_MOSI_USING_GPIO1 if BSP_USING_BL60X + default SPI_MOSI_USING_GPIO11 if BSP_USING_BL61X + default SPI_MOSI_USING_GPIO16 if BSP_USING_BL70X + default SPI_MOSI_USING_GPIO21 if BSP_USING_BL808 + + config SPI_MOSI_USING_GPIO0 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_0" + config SPI_MOSI_USING_GPIO1 + depends on BSP_USING_BL60X || BSP_USING_BL808 + bool "GPIO_1" + config SPI_MOSI_USING_GPIO3 + depends on BSP_USING_BL61X + bool "GPIO_3" + config SPI_MOSI_USING_GPIO4 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_4" + config SPI_MOSI_USING_GPIO5 + depends on BSP_USING_BL60X || BSP_USING_BL808 + bool "GPIO_5" + config SPI_MOSI_USING_GPIO7 + depends on BSP_USING_BL61X + bool "GPIO_7" + config SPI_MOSI_USING_GPIO8 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_8" + config SPI_MOSI_USING_GPIO9 + depends on BSP_USING_BL60X || BSP_USING_BL808 + bool "GPIO_9" + config SPI_MOSI_USING_GPIO11 + depends on BSP_USING_BL61X + bool "GPIO_11" + config SPI_MOSI_USING_GPIO12 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_12" + config SPI_MOSI_USING_GPIO13 + depends on BSP_USING_BL60X || BSP_USING_BL808 + bool "GPIO_13" + config SPI_MOSI_USING_GPIO15 + depends on BSP_USING_BL61X + bool "GPIO_15" + config SPI_MOSI_USING_GPIO16 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_16" + config SPI_MOSI_USING_GPIO17 + depends on BSP_USING_BL60X || BSP_USING_BL808 + bool "GPIO_17" + config SPI_MOSI_USING_GPIO19 + depends on BSP_USING_BL61X + bool "GPIO_19" + config SPI_MOSI_USING_GPIO20 + depends on BSP_USING_BL60X || BSP_USING_BL70X + bool "GPIO_20" + config SPI_MOSI_USING_GPIO21 + depends on BSP_USING_BL60X || BSP_USING_BL808 + bool "GPIO_21" + config SPI_MOSI_USING_GPIO23 + depends on BSP_USING_BL61X + bool "GPIO_23" + config SPI_MOSI_USING_GPIO24 + depends on BSP_USING_BL70X + bool "GPIO_24" + config SPI_MOSI_USING_GPIO25 + depends on BSP_USING_BL808 + bool "GPIO_25" + config SPI_MOSI_USING_GPIO27 + depends on BSP_USING_BL61X + bool "GPIO_27" + config SPI_MOSI_USING_GPIO28 + depends on BSP_USING_BL70X + bool "GPIO_28" + config SPI_MOSI_USING_GPIO29 + depends on BSP_USING_BL808 + bool "GPIO_29" + config SPI_MOSI_USING_GPIO31 + depends on BSP_USING_BL61X + bool "GPIO_31" + config SPI_MOSI_USING_GPIO33 + depends on BSP_USING_BL808 + bool "GPIO_33" + config SPI_MOSI_USING_GPIO37 + depends on BSP_USING_BL808 + bool "GPIO_37" + config SPI_MOSI_USING_GPIO41 + depends on BSP_USING_BL808 + bool "GPIO_41" + config SPI_MOSI_USING_GPIO45 + depends on BSP_USING_BL808 + bool "GPIO_45" + endchoice + + config BSP_SPI_TX_USING_DMA + bool "Enable SPI TX DMA" + default n + if BSP_SPI_TX_USING_DMA + config BSP_SPI_TX_DMA_CHANNEL + string "SPI TX DMA Channel Name" + default "dma0_ch0" + + config BSP_SPI_TX_DMA_TIMEOUT + int "SPI TX DMA Timeout(ms)" + default 10 + range 5 100 + + config BSP_SPI_TX_DMA_NOCACHE_BUFSIZE + depends on BSP_USING_BL61X || BSP_USING_BL808 + int "SPI TX DMA Nocache Buffer Size" + default 512 + range 0 4095 + endif + + config BSP_SPI_RX_USING_DMA + bool "Enable SPI RX DMA" + default n + if BSP_SPI_RX_USING_DMA + config BSP_SPI_RX_DMA_CHANNEL + string "SPI RX DMA Channel Name" + default "dma0_ch1" + + config BSP_SPI_RX_DMA_TIMEOUT + int "SPI RX DMA Timeout(ms)" + default 10 + range 5 100 + + config BSP_SPI_RX_DMA_NOCACHE_BUFSIZE + depends on BSP_USING_BL61X || BSP_USING_BL808 + int "SPI RX DMA Nocache Buffer Size" + default 512 + range 0 4095 + endif + endif + + menuconfig BSP_USING_ON_CHIP_FLASH + bool "Enable On-Chip FLASH" + select FAL_DEBUG_CONFIG + select FAL_PART_HAS_TABLE_CFG + default n + if BSP_USING_ON_CHIP_FLASH + config BSP_USING_ON_CHIP_FLASH_FS + bool "Enable On-Chip FLASH File System" + select PKG_USING_LITTLEFS + default n + endif + + config BSP_USING_SDH + depends on BSP_USING_BL61X || BSP_USING_BL808 + select RT_USING_SDIO + select RT_USING_DFS + select RT_USING_DFS_ELMFAT + select RT_USING_DFS_ROMFS + bool "Enable Secure Digital Host Controller(SDH)" + default n + +endmenu diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/Kconfig b/bsp/bouffalo_lab/libraries/rt_drivers/Kconfig deleted file mode 100755 index 707d98d2012..00000000000 --- a/bsp/bouffalo_lab/libraries/rt_drivers/Kconfig +++ /dev/null @@ -1,1519 +0,0 @@ -menu "General Drivers Configuration" - - config BSP_DRIVER_DEBUG - bool "Enable Driver Debug Log Output" - default n - - menu "General Purpose UARTs" - menuconfig BSP_USING_UART0 - bool "Enable UART0" - default y - if BSP_USING_UART0 - choice - prompt "UART0 TX PIN" - default UART0_TX_USING_GPIO16 if BSP_USING_BL60X - default UART0_TX_USING_GPIO21 if BSP_USING_BL61X - default UART0_TX_USING_GPIO14 if BSP_USING_BL70X - default UART0_TX_USING_GPIO14 if BSP_USING_BL808 - - config UART0_TX_USING_GPIO0 - bool "GPIO_0" - config UART0_TX_USING_GPIO1 - bool "GPIO_1" - config UART0_TX_USING_GPIO2 - bool "GPIO_2" - config UART0_TX_USING_GPIO3 - bool "GPIO_3" - config UART0_TX_USING_GPIO4 - bool "GPIO_4" - config UART0_TX_USING_GPIO5 - bool "GPIO_5" - config UART0_TX_USING_GPIO6 - bool "GPIO_6" - config UART0_TX_USING_GPIO7 - bool "GPIO_7" - config UART0_TX_USING_GPIO8 - bool "GPIO_8" - config UART0_TX_USING_GPIO9 - bool "GPIO_9" - config UART0_TX_USING_GPIO10 - bool "GPIO_10" - config UART0_TX_USING_GPIO11 - bool "GPIO_11" - config UART0_TX_USING_GPIO12 - bool "GPIO_12" - config UART0_TX_USING_GPIO13 - bool "GPIO_13" - config UART0_TX_USING_GPIO13 - bool "GPIO_13" - config UART0_TX_USING_GPIO14 - bool "GPIO_14" - config UART0_TX_USING_GPIO15 - bool "GPIO_15" - config UART0_TX_USING_GPIO16 - bool "GPIO_16" - config UART0_TX_USING_GPIO17 - bool "GPIO_17" - config UART0_TX_USING_GPIO18 - bool "GPIO_18" - config UART0_TX_USING_GPIO19 - bool "GPIO_19" - config UART0_TX_USING_GPIO20 - bool "GPIO_20" - config UART0_TX_USING_GPIO21 - bool "GPIO_21" - config UART0_TX_USING_GPIO22 - bool "GPIO_22" - config UART0_TX_USING_GPIO23 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_23" - config UART0_TX_USING_GPIO24 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_24" - config UART0_TX_USING_GPIO25 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_25" - config UART0_TX_USING_GPIO26 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_26" - config UART0_TX_USING_GPIO27 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_27" - config UART0_TX_USING_GPIO28 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_28" - config UART0_TX_USING_GPIO29 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_29" - config UART0_TX_USING_GPIO30 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_30" - config UART0_TX_USING_GPIO31 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_31" - config UART0_TX_USING_GPIO32 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_32" - config UART0_TX_USING_GPIO33 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_33" - config UART0_TX_USING_GPIO34 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_34" - config UART0_TX_USING_GPIO35 - depends on BSP_USING_BL808 - bool "GPIO_35" - config UART0_TX_USING_GPIO36 - depends on BSP_USING_BL808 - bool "GPIO_36" - config UART0_TX_USING_GPIO37 - depends on BSP_USING_BL808 - bool "GPIO_37" - config UART0_TX_USING_GPIO38 - depends on BSP_USING_BL808 - bool "GPIO_38" - config UART0_TX_USING_GPIO39 - depends on BSP_USING_BL808 - bool "GPIO_39" - config UART0_TX_USING_GPIO44 - depends on BSP_USING_BL808 - bool "GPIO_44" - config UART0_TX_USING_GPIO45 - depends on BSP_USING_BL808 - bool "GPIO_45" - endchoice - - choice - prompt "UART0 RX PIN" - default UART0_RX_USING_GPIO7 if BSP_USING_BL60X - default UART0_RX_USING_GPIO22 if BSP_USING_BL61X - default UART0_RX_USING_GPIO23 if BSP_USING_BL70X - default UART0_RX_USING_GPIO15 if BSP_USING_BL808 - - config UART0_RX_USING_GPIO0 - bool "GPIO_0" - config UART0_RX_USING_GPIO1 - bool "GPIO_1" - config UART0_RX_USING_GPIO2 - bool "GPIO_2" - config UART0_RX_USING_GPIO3 - bool "GPIO_3" - config UART0_RX_USING_GPIO4 - bool "GPIO_4" - config UART0_RX_USING_GPIO5 - bool "GPIO_5" - config UART0_RX_USING_GPIO6 - bool "GPIO_6" - config UART0_RX_USING_GPIO7 - bool "GPIO_7" - config UART0_RX_USING_GPIO8 - bool "GPIO_8" - config UART0_RX_USING_GPIO9 - bool "GPIO_9" - config UART0_RX_USING_GPIO10 - bool "GPIO_10" - config UART0_RX_USING_GPIO11 - bool "GPIO_11" - config UART0_RX_USING_GPIO12 - bool "GPIO_12" - config UART0_RX_USING_GPIO13 - bool "GPIO_13" - config UART0_RX_USING_GPIO14 - bool "GPIO_14" - config UART0_RX_USING_GPIO15 - bool "GPIO_15" - config UART0_RX_USING_GPIO16 - bool "GPIO_16" - config UART0_RX_USING_GPIO17 - bool "GPIO_17" - config UART0_RX_USING_GPIO18 - bool "GPIO_18" - config UART0_RX_USING_GPIO19 - bool "GPIO_19" - config UART0_RX_USING_GPIO20 - bool "GPIO_20" - config UART0_RX_USING_GPIO21 - bool "GPIO_21" - config UART0_RX_USING_GPIO22 - bool "GPIO_22" - config UART0_RX_USING_GPIO23 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_23" - config UART0_RX_USING_GPIO24 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_24" - config UART0_RX_USING_GPIO25 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_25" - config UART0_RX_USING_GPIO26 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_26" - config UART0_RX_USING_GPIO27 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_27" - config UART0_RX_USING_GPIO28 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_28" - config UART0_RX_USING_GPIO29 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_29" - config UART0_RX_USING_GPIO30 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_30" - config UART0_RX_USING_GPIO31 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_31" - config UART0_RX_USING_GPIO32 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_32" - config UART0_RX_USING_GPIO33 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_33" - config UART0_RX_USING_GPIO34 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_34" - config UART0_RX_USING_GPIO35 - depends on BSP_USING_BL808 - bool "GPIO_35" - config UART0_RX_USING_GPIO36 - depends on BSP_USING_BL808 - bool "GPIO_36" - config UART0_RX_USING_GPIO37 - depends on BSP_USING_BL808 - bool "GPIO_37" - config UART0_RX_USING_GPIO38 - depends on BSP_USING_BL808 - bool "GPIO_38" - config UART0_RX_USING_GPIO39 - depends on BSP_USING_BL808 - bool "GPIO_39" - config UART0_RX_USING_GPIO44 - depends on BSP_USING_BL808 - bool "GPIO_44" - config UART0_RX_USING_GPIO45 - depends on BSP_USING_BL808 - bool "GPIO_45" - - endchoice - endif - - menuconfig BSP_USING_UART1 - bool "Enable UART1" - default n - if BSP_USING_UART1 - choice - prompt "UART1 TX PIN" - default UART1_TX_USING_GPIO4 if BSP_USING_BL60X - default UART1_TX_USING_GPIO16 if BSP_USING_BL61X - default UART1_TX_USING_GPIO26 if BSP_USING_BL70X - default UART1_TX_USING_GPIO18 if BSP_USING_BL808 - - config UART1_TX_USING_GPIO0 - bool "GPIO_0" - config UART1_TX_USING_GPIO1 - bool "GPIO_1" - config UART1_TX_USING_GPIO2 - bool "GPIO_2" - config UART1_TX_USING_GPIO3 - bool "GPIO_3" - config UART1_TX_USING_GPIO4 - bool "GPIO_4" - config UART1_TX_USING_GPIO5 - bool "GPIO_5" - config UART1_TX_USING_GPIO6 - bool "GPIO_6" - config UART1_TX_USING_GPIO7 - bool "GPIO_7" - config UART1_TX_USING_GPIO8 - bool "GPIO_8" - config UART1_TX_USING_GPIO9 - bool "GPIO_9" - config UART1_TX_USING_GPIO10 - bool "GPIO_10" - config UART1_TX_USING_GPIO11 - bool "GPIO_11" - config UART1_TX_USING_GPIO12 - bool "GPIO_12" - config UART1_TX_USING_GPIO13 - bool "GPIO_13" - config UART1_TX_USING_GPIO14 - bool "GPIO_14" - config UART1_TX_USING_GPIO15 - bool "GPIO_15" - config UART1_TX_USING_GPIO16 - bool "GPIO_16" - config UART1_TX_USING_GPIO17 - bool "GPIO_17" - config UART1_TX_USING_GPIO18 - bool "GPIO_18" - config UART1_TX_USING_GPIO19 - bool "GPIO_19" - config UART1_TX_USING_GPIO20 - bool "GPIO_20" - config UART1_TX_USING_GPIO21 - bool "GPIO_21" - config UART1_TX_USING_GPIO22 - bool "GPIO_22" - config UART1_TX_USING_GPIO23 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_23" - config UART1_TX_USING_GPIO24 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_24" - config UART1_TX_USING_GPIO25 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_25" - config UART1_TX_USING_GPIO26 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_26" - config UART1_TX_USING_GPIO27 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_27" - config UART1_TX_USING_GPIO28 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_28" - config UART1_TX_USING_GPIO29 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_29" - config UART1_TX_USING_GPIO30 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_30" - config UART1_TX_USING_GPIO31 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_31" - config UART1_TX_USING_GPIO32 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_32" - config UART1_TX_USING_GPIO33 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_33" - config UART1_TX_USING_GPIO34 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_34" - config UART1_TX_USING_GPIO35 - depends on BSP_USING_BL808 - bool "GPIO_35" - config UART1_TX_USING_GPIO36 - depends on BSP_USING_BL808 - bool "GPIO_36" - config UART1_TX_USING_GPIO37 - depends on BSP_USING_BL808 - bool "GPIO_37" - config UART1_TX_USING_GPIO38 - depends on BSP_USING_BL808 - bool "GPIO_38" - config UART1_TX_USING_GPIO39 - depends on BSP_USING_BL808 - bool "GPIO_39" - config UART1_TX_USING_GPIO44 - depends on BSP_USING_BL808 - bool "GPIO_44" - config UART1_TX_USING_GPIO45 - depends on BSP_USING_BL808 - bool "GPIO_45" - endchoice - - choice - prompt "UART1 RX PIN" - default UART1_RX_USING_GPIO3 if BSP_USING_BL60X - default UART1_RX_USING_GPIO17 if BSP_USING_BL61X - default UART1_RX_USING_GPIO27 if BSP_USING_BL70X - default UART1_RX_USING_GPIO19 if BSP_USING_BL808 - - config UART1_RX_USING_GPIO0 - bool "GPIO_0" - config UART1_RX_USING_GPIO1 - bool "GPIO_1" - config UART1_RX_USING_GPIO2 - bool "GPIO_2" - config UART1_RX_USING_GPIO3 - bool "GPIO_3" - config UART1_RX_USING_GPIO4 - bool "GPIO_4" - config UART1_RX_USING_GPIO5 - bool "GPIO_5" - config UART1_RX_USING_GPIO6 - bool "GPIO_6" - config UART1_RX_USING_GPIO7 - bool "GPIO_7" - config UART1_RX_USING_GPIO8 - bool "GPIO_8" - config UART1_RX_USING_GPIO9 - bool "GPIO_9" - config UART1_RX_USING_GPIO10 - bool "GPIO_10" - config UART1_RX_USING_GPIO11 - bool "GPIO_11" - config UART1_RX_USING_GPIO12 - bool "GPIO_12" - config UART1_RX_USING_GPIO13 - bool "GPIO_13" - config UART1_RX_USING_GPIO14 - bool "GPIO_14" - config UART1_RX_USING_GPIO15 - bool "GPIO_15" - config UART1_RX_USING_GPIO16 - bool "GPIO_16" - config UART1_RX_USING_GPIO17 - bool "GPIO_17" - config UART1_RX_USING_GPIO18 - bool "GPIO_18" - config UART1_RX_USING_GPIO19 - bool "GPIO_19" - config UART1_RX_USING_GPIO20 - bool "GPIO_20" - config UART1_RX_USING_GPIO21 - bool "GPIO_21" - config UART1_RX_USING_GPIO22 - bool "GPIO_22" - config UART1_RX_USING_GPIO23 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_23" - config UART1_RX_USING_GPIO24 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_24" - config UART1_RX_USING_GPIO25 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_25" - config UART1_RX_USING_GPIO26 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_26" - config UART1_RX_USING_GPIO27 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_27" - config UART1_RX_USING_GPIO28 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_28" - config UART1_RX_USING_GPIO29 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_29" - config UART1_RX_USING_GPIO30 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_30" - config UART1_RX_USING_GPIO31 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_31" - config UART1_RX_USING_GPIO32 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_32" - config UART1_RX_USING_GPIO33 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_33" - config UART1_RX_USING_GPIO34 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_34" - config UART1_RX_USING_GPIO35 - depends on BSP_USING_BL808 - bool "GPIO_35" - config UART1_RX_USING_GPIO36 - depends on BSP_USING_BL808 - bool "GPIO_36" - config UART1_RX_USING_GPIO37 - depends on BSP_USING_BL808 - bool "GPIO_37" - config UART1_RX_USING_GPIO38 - depends on BSP_USING_BL808 - bool "GPIO_38" - config UART1_RX_USING_GPIO39 - depends on BSP_USING_BL808 - bool "GPIO_39" - config UART1_RX_USING_GPIO44 - depends on BSP_USING_BL808 - bool "GPIO_44" - config UART1_RX_USING_GPIO45 - depends on BSP_USING_BL808 - bool "GPIO_45" - endchoice - endif - - if BSP_USING_BL808 - menuconfig BSP_USING_UART2 - bool "Enable UART2" - default n - if BSP_USING_UART2 - choice - prompt "UART2 TX PIN" - default UART2_TX_USING_GPIO20 - - config UART2_TX_USING_GPIO0 - bool "GPIO_0" - config UART2_TX_USING_GPIO1 - bool "GPIO_1" - config UART2_TX_USING_GPIO2 - bool "GPIO_2" - config UART2_TX_USING_GPIO3 - bool "GPIO_3" - config UART2_TX_USING_GPIO4 - bool "GPIO_4" - config UART2_TX_USING_GPIO5 - bool "GPIO_5" - config UART2_TX_USING_GPIO6 - bool "GPIO_6" - config UART2_TX_USING_GPIO7 - bool "GPIO_7" - config UART2_TX_USING_GPIO8 - bool "GPIO_8" - config UART2_TX_USING_GPIO9 - bool "GPIO_9" - config UART2_TX_USING_GPIO10 - bool "GPIO_10" - config UART2_TX_USING_GPIO11 - bool "GPIO_11" - config UART2_TX_USING_GPIO12 - bool "GPIO_12" - config UART2_TX_USING_GPIO13 - bool "GPIO_13" - config UART2_TX_USING_GPIO14 - bool "GPIO_14" - config UART2_TX_USING_GPIO15 - bool "GPIO_15" - config UART2_TX_USING_GPIO16 - bool "GPIO_16" - config UART2_TX_USING_GPIO17 - bool "GPIO_17" - config UART2_TX_USING_GPIO18 - bool "GPIO_18" - config UART2_TX_USING_GPIO19 - bool "GPIO_19" - config UART2_TX_USING_GPIO20 - bool "GPIO_20" - config UART2_TX_USING_GPIO21 - bool "GPIO_21" - config UART2_TX_USING_GPIO22 - bool "GPIO_22" - config UART2_TX_USING_GPIO23 - bool "GPIO_23" - config UART2_TX_USING_GPIO24 - bool "GPIO_24" - config UART2_TX_USING_GPIO25 - bool "GPIO_25" - config UART2_TX_USING_GPIO26 - bool "GPIO_26" - config UART2_TX_USING_GPIO27 - bool "GPIO_27" - config UART2_TX_USING_GPIO28 - bool "GPIO_28" - config UART2_TX_USING_GPIO29 - bool "GPIO_29" - config UART2_TX_USING_GPIO30 - bool "GPIO_30" - config UART2_TX_USING_GPIO31 - bool "GPIO_31" - config UART2_TX_USING_GPIO32 - bool "GPIO_32" - config UART2_TX_USING_GPIO33 - bool "GPIO_33" - config UART2_TX_USING_GPIO34 - bool "GPIO_34" - config UART2_TX_USING_GPIO35 - bool "GPIO_35" - config UART2_TX_USING_GPIO36 - bool "GPIO_36" - config UART2_TX_USING_GPIO37 - bool "GPIO_37" - config UART2_TX_USING_GPIO38 - bool "GPIO_38" - config UART2_TX_USING_GPIO39 - bool "GPIO_39" - config UART2_TX_USING_GPIO44 - bool "GPIO_44" - config UART2_TX_USING_GPIO45 - bool "GPIO_45" - endchoice - choice - prompt "UART2 RX PIN" - default UART2_RX_USING_GPIO21 - - config UART2_RX_USING_GPIO0 - bool "GPIO_0" - config UART2_RX_USING_GPIO1 - bool "GPIO_1" - config UART2_RX_USING_GPIO2 - bool "GPIO_2" - config UART2_RX_USING_GPIO3 - bool "GPIO_3" - config UART2_RX_USING_GPIO4 - bool "GPIO_4" - config UART2_RX_USING_GPIO5 - bool "GPIO_5" - config UART2_RX_USING_GPIO6 - bool "GPIO_6" - config UART2_RX_USING_GPIO7 - bool "GPIO_7" - config UART2_RX_USING_GPIO8 - bool "GPIO_8" - config UART2_RX_USING_GPIO9 - bool "GPIO_9" - config UART2_RX_USING_GPIO10 - bool "GPIO_10" - config UART2_RX_USING_GPIO11 - bool "GPIO_11" - config UART2_RX_USING_GPIO12 - bool "GPIO_12" - config UART2_RX_USING_GPIO13 - bool "GPIO_13" - config UART2_RX_USING_GPIO13 - bool "GPIO_13" - config UART2_RX_USING_GPIO14 - bool "GPIO_14" - config UART2_RX_USING_GPIO15 - bool "GPIO_15" - config UART2_RX_USING_GPIO16 - bool "GPIO_16" - config UART2_RX_USING_GPIO17 - bool "GPIO_17" - config UART2_RX_USING_GPIO18 - bool "GPIO_18" - config UART2_RX_USING_GPIO19 - bool "GPIO_19" - config UART2_RX_USING_GPIO20 - bool "GPIO_20" - config UART2_RX_USING_GPIO21 - bool "GPIO_21" - config UART2_RX_USING_GPIO22 - bool "GPIO_22" - config UART2_RX_USING_GPIO23 - bool "GPIO_23" - config UART2_RX_USING_GPIO24 - bool "GPIO_24" - config UART2_RX_USING_GPIO25 - bool "GPIO_25" - config UART2_RX_USING_GPIO26 - bool "GPIO_26" - config UART2_RX_USING_GPIO27 - bool "GPIO_27" - config UART2_RX_USING_GPIO28 - bool "GPIO_28" - config UART2_RX_USING_GPIO29 - bool "GPIO_29" - config UART2_RX_USING_GPIO30 - bool "GPIO_30" - config UART2_RX_USING_GPIO31 - bool "GPIO_31" - config UART2_RX_USING_GPIO32 - bool "GPIO_32" - config UART2_RX_USING_GPIO33 - bool "GPIO_33" - config UART2_RX_USING_GPIO34 - bool "GPIO_34" - config UART2_RX_USING_GPIO35 - bool "GPIO_35" - config UART2_RX_USING_GPIO36 - bool "GPIO_36" - config UART2_RX_USING_GPIO37 - bool "GPIO_37" - config UART2_RX_USING_GPIO38 - bool "GPIO_38" - config UART2_RX_USING_GPIO39 - bool "GPIO_39" - config UART2_RX_USING_GPIO44 - bool "GPIO_44" - config UART2_RX_USING_GPIO45 - bool "GPIO_45" - endchoice - endif - endif - - endmenu - - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default n - - config BSP_USING_ADC - bool "Enable ADC" - select RT_USING_ADC - default n - if BSP_USING_ADC - config BSP_ADC_DMA_CHANNEL - string "ADC DMA Channel Name" - default "dma0_ch2" - config BSP_USING_ADC_CH0 - bool "USING ADC CH0" - default n - if BSP_USING_ADC_CH0 - config BSP_ADC_CH0_PIN - int "ADC CH0 Pin Num (GPIO_X)" - default 17 - endif - config BSP_USING_ADC_CH1 - bool "USING ADC CH1" - default n - if BSP_USING_ADC_CH1 - config BSP_ADC_CH1_PIN - int "ADC CH1 Pin Num (GPIO_X)" - default 5 - endif - config BSP_USING_ADC_CH2 - bool "USING ADC CH2" - default n - if BSP_USING_ADC_CH2 - config BSP_ADC_CH2_PIN - int "ADC CH2 Pin Num (GPIO_X)" - default 4 - endif - config BSP_USING_ADC_CH3 - bool "USING ADC CH3" - default n - if BSP_USING_ADC_CH3 - config BSP_ADC_CH3_PIN - int "ADC CH3 Pin Num (GPIO_X)" - default 11 - endif - config BSP_USING_ADC_CH4 - bool "USING ADC CH4" - default n - if BSP_USING_ADC_CH4 - config BSP_ADC_CH4_PIN - int "ADC CH4 Pin Num (GPIO_X)" - default 6 - endif - config BSP_USING_ADC_CH5 - bool "USING ADC CH5" - default n - if BSP_USING_ADC_CH5 - config BSP_ADC_CH5_PIN - int "ADC CH5 Pin Num (GPIO_X)" - default 40 - endif - config BSP_USING_ADC_CH6 - bool "USING ADC CH6" - default n - if BSP_USING_ADC_CH6 - config BSP_ADC_CH6_PIN - int "ADC CH6 Pin Num (GPIO_X)" - default 12 - endif - config BSP_USING_ADC_CH7 - bool "USING ADC CH7" - default n - if BSP_USING_ADC_CH7 - config BSP_ADC_CH7_PIN - int "ADC CH7 Pin Num (GPIO_X)" - default 13 - endif - config BSP_USING_ADC_CH8 - bool "USING ADC CH8" - default n - if BSP_USING_ADC_CH8 - config BSP_ADC_CH8_PIN - int "ADC CH8 Pin Num (GPIO_X)" - default 16 - endif - config BSP_USING_ADC_CH9 - bool "USING ADC CH9" - default n - if BSP_USING_ADC_CH9 - config BSP_ADC_CH9_PIN - int "ADC CH9 Pin Num (GPIO_X)" - default 18 - endif - config BSP_USING_ADC_CH10 - bool "USING ADC CH10" - default n - if BSP_USING_ADC_CH10 - config BSP_ADC_CH10_PIN - int "ADC CH10 Pin Num (GPIO_X)" - default 19 - endif - endif - - config BSP_USING_RTC - bool "Enable RTC" - select RT_USING_RTC - default n - - config BSP_USING_WDT - bool "Enable Watchdog Timer" - select RT_USING_WDT - default n - - menuconfig BSP_USING_PWM - bool "Enable PWM" - default n - select RT_USING_PWM - if BSP_USING_PWM - config BSP_USING_PWM0 - bool "Enable PWM0" - default n - - config BSP_USING_PWM1 - bool "Enable PWM1" - default n - - config BSP_USING_PWM2 - bool "Enable PWM2" - default n - - config BSP_USING_PWM3 - bool "Enable PWM3" - default n - endif - - menuconfig BSP_USING_HWTIMER - bool "Enable HWTIMER" - default n - select RT_USING_HWTIMER - if BSP_USING_HWTIMER - config BSP_USING_TIMER0 - bool "Enable TIMER0" - default n - config BSP_USING_TIMER1 - bool "Enable TIMER1" - default n - endif - - menuconfig BSP_USING_I2C - bool "Enable I2C BUS" - default n - select RT_USING_I2C - if BSP_USING_I2C - config BSP_USING_HW_I2C - bool "Enable Hardware I2C BUS" - default n - if BSP_USING_HW_I2C - menuconfig BSP_USING_I2C0 - bool "Enable I2C0 (hardware)" - default n - if BSP_USING_I2C0 - choice - prompt "I2C0 SCL" - default I2C0_SCL_USING_GPIO14 - - config I2C0_SCL_USING_GPIO0 - bool "GPIO_0" - config I2C0_SCL_USING_GPIO2 - bool "GPIO_2" - config I2C0_SCL_USING_GPIO4 - bool "GPIO_4" - config I2C0_SCL_USING_GPIO6 - bool "GPIO_6" - config I2C0_SCL_USING_GPIO8 - bool "GPIO_8" - config I2C0_SCL_USING_GPIO10 - bool "GPIO_10" - config I2C0_SCL_USING_GPIO12 - bool "GPIO_12" - config I2C0_SCL_USING_GPIO14 - bool "GPIO_14" - config I2C0_SCL_USING_GPIO16 - bool "GPIO_16" - config I2C0_SCL_USING_GPIO18 - bool "GPIO_18" - config I2C0_SCL_USING_GPIO20 - bool "GPIO_20" - config I2C0_SCL_USING_GPIO22 - bool "GPIO_22" - config I2C0_SCL_USING_GPIO24 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_8" - config I2C0_SCL_USING_GPIO26 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_26" - config I2C0_SCL_USING_GPIO28 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_28" - config I2C0_SCL_USING_GPIO30 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_30" - config I2C0_SCL_USING_GPIO32 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_32" - config I2C0_SCL_USING_GPIO34 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_34" - config I2C0_SDA_USING_GPIO36 - depends on BSP_USING_BL808 - bool "GPIO_36" - config I2C0_SDA_USING_GPIO38 - depends on BSP_USING_BL808 - bool "GPIO_38" - config I2C0_SDA_USING_GPIO40 - depends on BSP_USING_BL808 - bool "GPIO_40" - config I2C1_SDA_USING_GPIO42 - depends on BSP_USING_BL808 - bool "GPIO_42" - config I2C0_SDA_USING_GPIO44 - depends on BSP_USING_BL808 - bool "GPIO_44" - endchoice - - choice - prompt "I2C0 SDA" - default I2C0_SDA_USING_GPIO15 - - config I2C0_SDA_USING_GPIO1 - bool "GPIO_1" - config I2C0_SDA_USING_GPIO3 - bool "GPIO_3" - config I2C0_SDA_USING_GPIO5 - bool "GPIO_5" - config I2C0_SDA_USING_GPIO7 - bool "GPIO_7" - config I2C0_SDA_USING_GPIO9 - bool "GPIO_9" - config I2C0_SDA_USING_GPIO11 - bool "GPIO_11" - config I2C0_SDA_USING_GPIO13 - bool "GPIO_13" - config I2C0_SDA_USING_GPIO15 - bool "GPIO_15" - config I2C0_SDA_USING_GPIO17 - bool "GPIO_17" - config I2C0_SDA_USING_GPIO19 - bool "GPIO_19" - config I2C0_SDA_USING_GPIO21 - bool "GPIO_21" - config I2C0_SDA_USING_GPIO23 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_23" - config I2C0_SDA_USING_GPIO25 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_25" - config I2C0_SDA_USING_GPIO27 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_27" - config I2C0_SDA_USING_GPIO29 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_29" - config I2C0_SDA_USING_GPIO31 - depends on BSP_USING_BL61X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_31" - config I2C0_SDA_USING_GPIO33 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_33" - config I2C0_SDA_USING_GPIO35 - depends on BSP_USING_BL808 - bool "GPIO_35" - config I2C0_SDA_USING_GPIO37 - depends on BSP_USING_BL808 - bool "GPIO_37" - config I2C0_SDA_USING_GPIO39 - depends on BSP_USING_BL808 - bool "GPIO_39" - config I2C0_SDA_USING_GPIO41 - depends on BSP_USING_BL808 - bool "GPIO_41" - config I2C0_SDA_USING_GPIO43 - depends on BSP_USING_BL808 - bool "GPIO_43" - config I2C0_SDA_USING_GPIO45 - depends on BSP_USING_BL808 - bool "GPIO_45" - endchoice - - config I2C0_FREQUENCY - int "I2C0 Frequency" - default 400000 - endif - - - menuconfig BSP_USING_I2C1 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "Enable I2C1 (hardware)" - default n - if BSP_USING_I2C1 - choice - prompt "I2C1 SCL" - default I2C1_SCL_USING_GPIO0 - - config I2C1_SCL_USING_GPIO0 - bool "GPIO_0" - config I2C1_SCL_USING_GPIO2 - bool "GPIO_2" - config I2C1_SCL_USING_GPIO4 - bool "GPIO_4" - config I2C1_SCL_USING_GPIO6 - bool "GPIO_6" - config I2C1_SCL_USING_GPIO8 - bool "GPIO_8" - config I2C1_SCL_USING_GPIO10 - bool "GPIO_10" - config I2C1_SCL_USING_GPIO12 - bool "GPIO_12" - config I2C1_SCL_USING_GPIO14 - bool "GPIO_14" - config I2C1_SCL_USING_GPIO16 - bool "GPIO_16" - config I2C1_SCL_USING_GPIO18 - bool "GPIO_18" - config I2C1_SCL_USING_GPIO20 - bool "GPIO_20" - config I2C1_SCL_USING_GPIO22 - bool "GPIO_22" - config I2C1_SCL_USING_GPIO24 - bool "GPIO_24" - config I2C1_SCL_USING_GPIO26 - bool "GPIO_26" - config I2C1_SCL_USING_GPIO28 - bool "GPIO_28" - config I2C1_SCL_USING_GPIO30 - bool "GPIO_30" - config I2C1_SCL_USING_GPIO32 - bool "GPIO_32" - config I2C1_SCL_USING_GPIO34 - bool "GPIO_34" - config I2C1_SDA_USING_GPIO36 - depends on BSP_USING_BL808 - bool "GPIO_36" - config I2C1_SDA_USING_GPIO38 - depends on BSP_USING_BL808 - bool "GPIO_38" - config I2C1_SDA_USING_GPIO40 - depends on BSP_USING_BL808 - bool "GPIO_40" - config I2C1_SDA_USING_GPIO42 - depends on BSP_USING_BL808 - bool "GPIO_42" - config I2C1_SDA_USING_GPIO44 - depends on BSP_USING_BL808 - bool "GPIO_44" - endchoice - - choice - prompt "I2C1 SDA" - default I2C1_SDA_USING_GPIO1 - - config I2C1_SDA_USING_GPIO1 - bool "GPIO_1" - config I2C1_SDA_USING_GPIO3 - bool "GPIO_3" - config I2C1_SDA_USING_GPIO5 - bool "GPIO_5" - config I2C1_SDA_USING_GPIO7 - bool "GPIO_7" - config I2C1_SDA_USING_GPIO9 - bool "GPIO_9" - config I2C1_SDA_USING_GPIO11 - bool "GPIO_11" - config I2C1_SDA_USING_GPIO13 - bool "GPIO_13" - config I2C1_SDA_USING_GPIO15 - bool "GPIO_15" - config I2C1_SDA_USING_GPIO17 - bool "GPIO_17" - config I2C1_SDA_USING_GPIO19 - bool "GPIO_19" - config I2C1_SDA_USING_GPIO21 - bool "GPIO_21" - config I2C1_SDA_USING_GPIO23 - bool "GPIO_23" - config I2C1_SDA_USING_GPIO25 - bool "GPIO_25" - config I2C1_SDA_USING_GPIO27 - bool "GPIO_27" - config I2C1_SDA_USING_GPIO29 - bool "GPIO_29" - config I2C1_SDA_USING_GPIO31 - bool "GPIO_31" - config I2C1_SDA_USING_GPIO33 - bool "GPIO_33" - config I2C1_SDA_USING_GPIO35 - depends on BSP_USING_BL808 - bool "GPIO_35" - config I2C1_SDA_USING_GPIO37 - depends on BSP_USING_BL808 - bool "GPIO_37" - config I2C1_SDA_USING_GPIO39 - depends on BSP_USING_BL808 - bool "GPIO_39" - config I2C1_SDA_USING_GPIO41 - depends on BSP_USING_BL808 - bool "GPIO_41" - config I2C1_SDA_USING_GPIO43 - depends on BSP_USING_BL808 - bool "GPIO_43" - config I2C1_SDA_USING_GPIO45 - depends on BSP_USING_BL808 - bool "GPIO_45" - endchoice - - config I2C1_FREQUENCY - int "I2C1 Frequency" - default 400000 - endif - - endif - if !BSP_USING_HW_I2C - menuconfig BSP_USING_SOFT_I2C1 - bool "Enable I2C1 BUS (software simulation)" - select RT_USING_I2C_BITOPS - select BSP_USING_GPIO - default n - if BSP_USING_SOFT_I2C1 - choice - prompt "I2C1 SCL" - default SOFT_I2C1_SCL_USING_GPIO0 - - config SOFT_I2C1_SCL_USING_GPIO0 - bool "GPIO_0" - config SOFT_I2C1_SCL_USING_GPIO2 - bool "GPIO_2" - config SOFT_I2C1_SCL_USING_GPIO4 - bool "GPIO_4" - config SOFT_I2C1_SCL_USING_GPIO6 - bool "GPIO_6" - config SOFT_I2C1_SCL_USING_GPIO8 - bool "GPIO_8" - config SOFT_I2C1_SCL_USING_GPIO10 - bool "GPIO_10" - config SOFT_I2C1_SCL_USING_GPIO12 - bool "GPIO_12" - config SOFT_I2C1_SCL_USING_GPIO14 - bool "GPIO_14" - config SOFT_I2C1_SCL_USING_GPIO16 - bool "GPIO_16" - config SOFT_I2C1_SCL_USING_GPIO18 - bool "GPIO_18" - config SOFT_I2C1_SCL_USING_GPIO20 - bool "GPIO_20" - config SOFT_I2C1_SCL_USING_GPIO22 - bool "GPIO_22" - config SOFT_I2C1_SCL_USING_GPIO24 - bool "GPIO_8" - config SOFT_I2C1_SCL_USING_GPIO26 - bool "GPIO_26" - config SOFT_I2C1_SCL_USING_GPIO28 - bool "GPIO_28" - config SOFT_I2C1_SCL_USING_GPIO30 - bool "GPIO_30" - config SOFT_I2C1_SCL_USING_GPIO32 - bool "GPIO_32" - config SOFT_I2C1_SCL_USING_GPIO34 - bool "GPIO_34" - config SOFT_I2C1_SDA_USING_GPIO36 - depends on BSP_USING_BL808 - bool "GPIO_36" - config SOFT_I2C1_SDA_USING_GPIO38 - depends on BSP_USING_BL808 - bool "GPIO_38" - config SOFT_I2C1_SDA_USING_GPIO40 - depends on BSP_USING_BL808 - bool "GPIO_40" - config SOFT_I2C1_SDA_USING_GPIO42 - depends on BSP_USING_BL808 - bool "GPIO_42" - config SOFT_I2C1_SDA_USING_GPIO44 - depends on BSP_USING_BL808 - bool "GPIO_44" - endchoice - - choice - prompt "I2C1 SDA" - default SOFT_I2C1_SDA_USING_GPIO1 - - config SOFT_I2C1_SDA_USING_GPIO1 - bool "GPIO_1" - config SOFT_I2C1_SDA_USING_GPIO3 - bool "GPIO_3" - config SOFT_I2C1_SDA_USING_GPIO5 - bool "GPIO_5" - config SOFT_I2C1_SDA_USING_GPIO7 - bool "GPIO_7" - config SOFT_I2C1_SDA_USING_GPIO9 - bool "GPIO_9" - config SOFT_I2C1_SDA_USING_GPIO11 - bool "GPIO_11" - config SOFT_I2C1_SDA_USING_GPIO13 - bool "GPIO_13" - config SOFT_I2C1_SDA_USING_GPIO15 - bool "GPIO_15" - config SOFT_I2C1_SDA_USING_GPIO17 - bool "GPIO_17" - config SOFT_I2C1_SDA_USING_GPIO19 - bool "GPIO_19" - config SOFT_I2C1_SDA_USING_GPIO21 - bool "GPIO_21" - config SOFT_I2C1_SDA_USING_GPIO23 - bool "GPIO_23" - config SOFT_I2C1_SDA_USING_GPIO25 - bool "GPIO_25" - config SOFT_I2C1_SDA_USING_GPIO27 - bool "GPIO_27" - config SOFT_I2C1_SDA_USING_GPIO29 - bool "GPIO_29" - config SOFT_I2C1_SDA_USING_GPIO31 - bool "GPIO_31" - config SOFT_I2C1_SDA_USING_GPIO33 - bool "GPIO_33" - config SOFT_I2C1_SDA_USING_GPIO35 - depends on BSP_USING_BL808 - bool "GPIO_35" - config SOFT_I2C1_SDA_USING_GPIO37 - depends on BSP_USING_BL808 - bool "GPIO_37" - config SOFT_I2C1_SDA_USING_GPIO39 - depends on BSP_USING_BL808 - bool "GPIO_39" - config SOFT_I2C1_SDA_USING_GPIO41 - depends on BSP_USING_BL808 - bool "GPIO_41" - config SOFT_I2C1_SDA_USING_GPIO43 - depends on BSP_USING_BL808 - bool "GPIO_43" - config SOFT_I2C1_SDA_USING_GPIO45 - depends on BSP_USING_BL808 - bool "GPIO_45" - endchoice - endif - endif - endif - - menuconfig BSP_USING_SPI - bool "Enable SPI" - select RT_USING_SPI - select RT_USING_PIN - default n - - if BSP_USING_SPI - choice - prompt "SPI SCK PIN" - default SPI_SCK_USING_GPIO3 if BSP_USING_BL60X - default SPI_SCK_USING_GPIO13 if BSP_USING_BL61X - default SPI_SCK_USING_GPIO15 if BSP_USING_BL70X - default SPI_SCK_USING_GPIO19 if BSP_USING_BL808 - - config SPI_SCK_USING_GPIO1 - depends on BSP_USING_BL61X - bool "GPIO_1" - config SPI_SCK_USING_GPIO3 - depends on BSP_USING_BL60X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_3" - config SPI_SCK_USING_GPIO5 - depends on BSP_USING_BL61X - bool "GPIO_5" - config SPI_SCK_USING_GPIO7 - depends on BSP_USING_BL60X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_7" - config SPI_SCK_USING_GPIO9 - depends on BSP_USING_BL61X - bool "GPIO_9" - config SPI_SCK_USING_GPIO11 - depends on BSP_USING_BL60X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_11" - config SPI_SCK_USING_GPIO13 - depends on BSP_USING_BL61X - bool "GPIO_13" - config SPI_SCK_USING_GPIO15 - depends on BSP_USING_BL60X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_15" - config SPI_SCK_USING_GPIO17 - depends on BSP_USING_BL61X - bool "GPIO_17" - config SPI_SCK_USING_GPIO19 - depends on BSP_USING_BL60X || BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_19" - config SPI_SCK_USING_GPIO21 - depends on BSP_USING_BL61X - bool "GPIO_21" - config SPI_SCK_USING_GPIO23 - depends on BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_23" - config SPI_SCK_USING_GPIO25 - depends on BSP_USING_BL61X - bool "GPIO_25" - config SPI_SCK_USING_GPIO27 - depends on BSP_USING_BL70X || BSP_USING_BL808 - bool "GPIO_27" - config SPI_SCK_USING_GPIO29 - depends on BSP_USING_BL61X - bool "GPIO_29" - config SPI_SCK_USING_GPIO31 - depends on BSP_USING_BL808 - bool "GPIO_31" - config SPI_SCK_USING_GPIO33 - depends on BSP_USING_BL61X - bool "GPIO_33" - config SPI_SCK_USING_GPIO35 - depends on BSP_USING_BL808 - bool "GPIO_35" - config SPI_SCK_USING_GPIO39 - depends on BSP_USING_BL808 - bool "GPIO_39" - config SPI_SCK_USING_GPIO43 - depends on BSP_USING_BL808 - bool "GPIO_43" - endchoice - - choice - prompt "SPI MISO PIN" - default SPI_MISO_USING_GPIO0 if BSP_USING_BL60X - default SPI_MISO_USING_GPIO10 if BSP_USING_BL61X - default SPI_MISO_USING_GPIO17 if BSP_USING_BL70X - default SPI_MISO_USING_GPIO22 if BSP_USING_BL808 - - config SPI_MISO_USING_GPIO0 - depends on BSP_USING_BL60X - bool "GPIO_0" - config SPI_MISO_USING_GPIO1 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_1" - config SPI_MISO_USING_GPIO2 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_2" - config SPI_MISO_USING_GPIO4 - depends on BSP_USING_BL60X - bool "GPIO_4" - config SPI_MISO_USING_GPIO5 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_5" - config SPI_MISO_USING_GPIO6 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_6" - config SPI_MISO_USING_GPIO8 - depends on BSP_USING_BL60X - bool "GPIO_8" - config SPI_MISO_USING_GPIO9 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_9" - config SPI_MISO_USING_GPIO10 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_10" - config SPI_MISO_USING_GPIO12 - depends on BSP_USING_BL60X - bool "GPIO_12" - config SPI_MISO_USING_GPIO13 - depends on BSP_USING_BL60X || BSP_USING_BL60X - bool "GPIO_13" - config SPI_MISO_USING_GPIO14 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_14" - config SPI_MISO_USING_GPIO16 - depends on BSP_USING_BL60X - bool "GPIO_16" - config SPI_MISO_USING_GPIO17 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_17" - config SPI_MISO_USING_GPIO18 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_18" - config SPI_MISO_USING_GPIO20 - depends on BSP_USING_BL60X - bool "GPIO_20" - config SPI_MISO_USING_GPIO21 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_21" - config SPI_MISO_USING_GPIO22 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_22" - config SPI_MISO_USING_GPIO25 - depends on BSP_USING_BL70X - bool "GPIO_25" - config SPI_MISO_USING_GPIO26 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_26" - config SPI_MISO_USING_GPIO29 - depends on BSP_USING_BL70X - bool "GPIO_29" - config SPI_MISO_USING_GPIO30 - depends on BSP_USING_BL61X || BSP_USING_BL808 - bool "GPIO_30" - config SPI_MISO_USING_GPIO34 - depends on BSP_USING_BL808 - bool "GPIO_34" - config SPI_MISO_USING_GPIO38 - depends on BSP_USING_BL808 - bool "GPIO_38" - config SPI_MISO_USING_GPIO42 - depends on BSP_USING_BL808 - bool "GPIO_42" - endchoice - - choice - prompt "SPI MOSI PIN" - default SPI_MOSI_USING_GPIO1 if BSP_USING_BL60X - default SPI_MOSI_USING_GPIO11 if BSP_USING_BL61X - default SPI_MOSI_USING_GPIO16 if BSP_USING_BL70X - default SPI_MOSI_USING_GPIO21 if BSP_USING_BL808 - - config SPI_MOSI_USING_GPIO0 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_0" - config SPI_MOSI_USING_GPIO1 - depends on BSP_USING_BL60X || BSP_USING_BL808 - bool "GPIO_1" - config SPI_MOSI_USING_GPIO3 - depends on BSP_USING_BL61X - bool "GPIO_3" - config SPI_MOSI_USING_GPIO4 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_4" - config SPI_MOSI_USING_GPIO5 - depends on BSP_USING_BL60X || BSP_USING_BL808 - bool "GPIO_5" - config SPI_MOSI_USING_GPIO7 - depends on BSP_USING_BL61X - bool "GPIO_7" - config SPI_MOSI_USING_GPIO8 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_8" - config SPI_MOSI_USING_GPIO9 - depends on BSP_USING_BL60X || BSP_USING_BL808 - bool "GPIO_9" - config SPI_MOSI_USING_GPIO11 - depends on BSP_USING_BL61X - bool "GPIO_11" - config SPI_MOSI_USING_GPIO12 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_12" - config SPI_MOSI_USING_GPIO13 - depends on BSP_USING_BL60X || BSP_USING_BL808 - bool "GPIO_13" - config SPI_MOSI_USING_GPIO15 - depends on BSP_USING_BL61X - bool "GPIO_15" - config SPI_MOSI_USING_GPIO16 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_16" - config SPI_MOSI_USING_GPIO17 - depends on BSP_USING_BL60X || BSP_USING_BL808 - bool "GPIO_17" - config SPI_MOSI_USING_GPIO19 - depends on BSP_USING_BL61X - bool "GPIO_19" - config SPI_MOSI_USING_GPIO20 - depends on BSP_USING_BL60X || BSP_USING_BL70X - bool "GPIO_20" - config SPI_MOSI_USING_GPIO21 - depends on BSP_USING_BL60X || BSP_USING_BL808 - bool "GPIO_21" - config SPI_MOSI_USING_GPIO23 - depends on BSP_USING_BL61X - bool "GPIO_23" - config SPI_MOSI_USING_GPIO24 - depends on BSP_USING_BL70X - bool "GPIO_24" - config SPI_MOSI_USING_GPIO25 - depends on BSP_USING_BL808 - bool "GPIO_25" - config SPI_MOSI_USING_GPIO27 - depends on BSP_USING_BL61X - bool "GPIO_27" - config SPI_MOSI_USING_GPIO28 - depends on BSP_USING_BL70X - bool "GPIO_28" - config SPI_MOSI_USING_GPIO29 - depends on BSP_USING_BL808 - bool "GPIO_29" - config SPI_MOSI_USING_GPIO31 - depends on BSP_USING_BL61X - bool "GPIO_31" - config SPI_MOSI_USING_GPIO33 - depends on BSP_USING_BL808 - bool "GPIO_33" - config SPI_MOSI_USING_GPIO37 - depends on BSP_USING_BL808 - bool "GPIO_37" - config SPI_MOSI_USING_GPIO41 - depends on BSP_USING_BL808 - bool "GPIO_41" - config SPI_MOSI_USING_GPIO45 - depends on BSP_USING_BL808 - bool "GPIO_45" - endchoice - - config BSP_SPI_TX_USING_DMA - bool "Enable SPI TX DMA" - default n - if BSP_SPI_TX_USING_DMA - config BSP_SPI_TX_DMA_CHANNEL - string "SPI TX DMA Channel Name" - default "dma0_ch0" - - config BSP_SPI_TX_DMA_TIMEOUT - int "SPI TX DMA Timeout(ms)" - default 10 - range 5 100 - - config BSP_SPI_TX_DMA_NOCACHE_BUFSIZE - depends on BSP_USING_BL61X || BSP_USING_BL808 - int "SPI TX DMA Nocache Buffer Size" - default 512 - range 0 4095 - endif - - config BSP_SPI_RX_USING_DMA - bool "Enable SPI RX DMA" - default n - if BSP_SPI_RX_USING_DMA - config BSP_SPI_RX_DMA_CHANNEL - string "SPI RX DMA Channel Name" - default "dma0_ch1" - - config BSP_SPI_RX_DMA_TIMEOUT - int "SPI RX DMA Timeout(ms)" - default 10 - range 5 100 - - config BSP_SPI_RX_DMA_NOCACHE_BUFSIZE - depends on BSP_USING_BL61X || BSP_USING_BL808 - int "SPI RX DMA Nocache Buffer Size" - default 512 - range 0 4095 - endif - endif - - menuconfig BSP_USING_ON_CHIP_FLASH - bool "Enable On-Chip FLASH" - select FAL_DEBUG_CONFIG - select FAL_PART_HAS_TABLE_CFG - default n - if BSP_USING_ON_CHIP_FLASH - config BSP_USING_ON_CHIP_FLASH_FS - bool "Enable On-Chip FLASH File System" - select PKG_USING_LITTLEFS - default n - endif - - config BSP_USING_SDH - depends on BSP_USING_BL61X || BSP_USING_BL808 - select RT_USING_SDIO - select RT_USING_DFS - select RT_USING_DFS_ELMFAT - select RT_USING_DFS_ROMFS - bool "Enable Secure Digital Host Controller(SDH)" - default n - -endmenu diff --git a/bsp/hpmicro/hpm6750evk2/.config b/bsp/hpmicro/hpm6750evk2/.config index 46c9a13d832..2e986e98db9 100644 --- a/bsp/hpmicro/hpm6750evk2/.config +++ b/bsp/hpmicro/hpm6750evk2/.config @@ -1,7 +1,3 @@ -# -# Automatically generated file; DO NOT EDIT. -# RT-Thread Configuration -# # # RT-Thread Kernel @@ -24,18 +20,25 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_IDLE_THREAD_STACK_SIZE=2048 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=2048 # # kservice optimization # -# CONFIG_RT_KSERVICE_USING_STDLIB is not set -# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set -# CONFIG_RT_KPRINTF_USING_LONGLONG is not set +# end of kservice optimization + +# +# klibc optimization +# +# CONFIG_RT_KLIBC_USING_STDLIB is not set +# CONFIG_RT_KLIBC_USING_TINY_SIZE is not set +# CONFIG_RT_KLIBC_USING_PRINTF_LONGLONG is not set +# end of klibc optimization + # CONFIG_RT_USING_DEBUG is not set # @@ -48,6 +51,7 @@ CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y # CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication # # Memory Management @@ -64,6 +68,8 @@ CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y # CONFIG_RT_USING_MEMTRACE is not set # CONFIG_RT_USING_HEAP_ISR is not set CONFIG_RT_USING_HEAP=y +# end of Memory Management + CONFIG_RT_USING_DEVICE=y # CONFIG_RT_USING_DEVICE_OPS is not set # CONFIG_RT_USING_INTERRUPT_INFO is not set @@ -72,14 +78,10 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart0" -CONFIG_RT_VER_NUM=0x50100 +CONFIG_RT_VER_NUM=0x50200 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 -# CONFIG_RT_USING_CACHE is not set -# CONFIG_RT_USING_HW_ATOMIC is not set -# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set -# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set -# CONFIG_RT_USING_CPU_FFS is not set +# end of RT-Thread Kernel # # RT-Thread Components @@ -109,7 +111,25 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # # DFS: device virtual file system # -# CONFIG_RT_USING_DFS is not set +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# CONFIG_RT_USING_DFS_NFS is not set +# end of DFS: device virtual file system + # CONFIG_RT_USING_FAL is not set # @@ -118,7 +138,9 @@ CONFIG_FINSH_USING_OPTION_COMPLETION=y # CONFIG_RT_USING_DM is not set CONFIG_RT_USING_DEVICE_IPC=y CONFIG_RT_UNAMED_PIPE_NUMBER=64 -# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 CONFIG_RT_USING_SERIAL=y CONFIG_RT_USING_SERIAL_V1=y # CONFIG_RT_USING_SERIAL_V2 is not set @@ -156,13 +178,43 @@ CONFIG_RT_USING_RTC=y CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_KTIME is not set # CONFIG_RT_USING_HWTIMER is not set - -# -# Using USB -# -# CONFIG_RT_USING_USB is not set -# CONFIG_RT_USING_USB_HOST is not set -# CONFIG_RT_USING_USB_DEVICE is not set +CONFIG_RT_USING_CHERRYUSB=y +# CONFIG_RT_CHERRYUSB_DEVICE is not set +CONFIG_RT_CHERRYUSB_HOST=y +# CONFIG_RT_CHERRYUSB_HOST_CUSTOM is not set +# CONFIG_RT_CHERRYUSB_HOST_EHCI_BL is not set +CONFIG_RT_CHERRYUSB_HOST_EHCI_HPM=y +# CONFIG_RT_CHERRYUSB_HOST_EHCI_AIC is not set +# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 is not set +# CONFIG_RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 is not set +# CONFIG_RT_CHERRYUSB_HOST_EHCI_CUSTOM is not set +# CONFIG_RT_CHERRYUSB_HOST_DWC2_ST is not set +# CONFIG_RT_CHERRYUSB_HOST_DWC2_ESP is not set +# CONFIG_RT_CHERRYUSB_HOST_DWC2_CUSTOM is not set +# CONFIG_RT_CHERRYUSB_HOST_MUSB_STANDARD is not set +# CONFIG_RT_CHERRYUSB_HOST_MUSB_SUNXI is not set +# CONFIG_RT_CHERRYUSB_HOST_MUSB_CUSTOM is not set +# CONFIG_RT_CHERRYUSB_HOST_PUSB2 is not set +# CONFIG_RT_CHERRYUSB_HOST_XHCI is not set +CONFIG_RT_CHERRYUSB_HOST_CDC_ACM=y +CONFIG_RT_CHERRYUSB_HOST_HID=y +# CONFIG_RT_CHERRYUSB_HOST_MSC is not set +# CONFIG_RT_CHERRYUSB_HOST_CDC_RNDIS is not set +# CONFIG_RT_CHERRYUSB_HOST_CDC_ECM is not set +# CONFIG_RT_CHERRYUSB_HOST_CDC_NCM is not set +# CONFIG_RT_CHERRYUSB_HOST_VIDEO is not set +# CONFIG_RT_CHERRYUSB_HOST_AUDIO is not set +# CONFIG_RT_CHERRYUSB_HOST_BLUETOOTH is not set +# CONFIG_RT_CHERRYUSB_HOST_ASIX is not set +# CONFIG_RT_CHERRYUSB_HOST_RTL8152 is not set +# CONFIG_RT_CHERRYUSB_HOST_FTDI is not set +# CONFIG_RT_CHERRYUSB_HOST_CH34X is not set +# CONFIG_RT_CHERRYUSB_HOST_CP210X is not set +# CONFIG_RT_CHERRYUSB_HOST_PL2303 is not set +CONFIG_RT_CHERRYUSB_HOST_TEMPLATE=y +CONFIG_TEST_USBH_CDC_ACM=1 +CONFIG_TEST_USBH_HID=1 +# end of Device Drivers # # C/C++ and POSIX layer @@ -180,11 +232,23 @@ CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer # # POSIX (Portable Operating System Interface) layer # -# CONFIG_RT_USING_POSIX_FS is not set +CONFIG_RT_USING_POSIX_FS=y +# CONFIG_RT_USING_POSIX_DEVIO is not set +# CONFIG_RT_USING_POSIX_STDIO is not set +CONFIG_RT_USING_POSIX_POLL=y +CONFIG_RT_USING_POSIX_SELECT=y +# CONFIG_RT_USING_POSIX_EVENTFD is not set +# CONFIG_RT_USING_POSIX_TIMERFD is not set +CONFIG_RT_USING_POSIX_SOCKET=y +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set # CONFIG_RT_USING_POSIX_DELAY is not set # CONFIG_RT_USING_POSIX_CLOCK is not set # CONFIG_RT_USING_POSIX_TIMER is not set @@ -201,21 +265,105 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # Socket is in the 'Network' category # +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + # CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +# end of Docking with protocol stacks + +CONFIG_SAL_USING_POSIX=y +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=4 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +CONFIG_RT_LWIP_DHCP=y +CONFIG_IP_SOF_BROADCAST=1 +CONFIG_IP_SOF_BROADCAST_RECV=1 + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.1.30" +CONFIG_RT_LWIP_GWADDR="192.168.1.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +# end of Static IPv4 Address + +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=16 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=10 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=1024 +CONFIG_LWIP_NO_RX_THREAD=y +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=1024 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_RT_LWIP_NETIF_NAMESIZE=6 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_DEBUG is not set # CONFIG_RT_USING_AT is not set +# end of Network # # Memory protection # # CONFIG_RT_USING_MEM_PROTECTION is not set # CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection # # Utilities @@ -227,12 +375,23 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + # CONFIG_RT_USING_VBUS is not set +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version +# end of RT-Thread Components + # # RT-Thread Utestcases # # CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases # # RT-Thread online packages @@ -241,7 +400,6 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # IoT - internet of things # -# CONFIG_PKG_USING_LWIP is not set # CONFIG_PKG_USING_LORAWAN_DRIVER is not set # CONFIG_PKG_USING_PAHOMQTT is not set # CONFIG_PKG_USING_UMQTT is not set @@ -263,30 +421,50 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # Marvell WiFi # # CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi # # Wiced WiFi # # CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + # CONFIG_PKG_USING_RW007 is not set # # CYW43012 WiFi # # CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi # # BL808 WiFi # # CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi # # CYW43439 WiFi # # CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + # CONFIG_PKG_USING_COAP is not set # CONFIG_PKG_USING_NOPOLL is not set -# CONFIG_PKG_USING_NETUTILS is not set +CONFIG_PKG_USING_NETUTILS=y +CONFIG_PKG_NETUTILS_PATH="/packages/iot/netutils" +# CONFIG_PKG_NETUTILS_TFTP is not set +CONFIG_PKG_NETUTILS_IPERF=y +CONFIG_IPERF_THREAD_STACK_SIZE=2048 +# CONFIG_PKG_NETUTILS_NETIO is not set +# CONFIG_PKG_NETUTILS_NTP is not set +# CONFIG_PKG_NETUTILS_TELNET is not set +# CONFIG_PKG_NETUTILS_TCPDUMP is not set +CONFIG_PKG_USING_NETUTILS_LATEST_VERSION=y +# CONFIG_PKG_USING_NETUTILS_V133 is not set +CONFIG_PKG_NETUTILS_VER="latest" +CONFIG_PKG_NETUTILS_VER_NUM=0x99999 # CONFIG_PKG_USING_CMUX is not set # CONFIG_PKG_USING_PPP_DEVICE is not set # CONFIG_PKG_USING_AT_DEVICE is not set @@ -306,6 +484,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set # CONFIG_PKG_USING_JOYLINK is not set # CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + # CONFIG_PKG_USING_NIMBLE is not set # CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set # CONFIG_PKG_USING_OTA_DOWNLOADER is not set @@ -348,6 +528,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ZEPHYR_POLLING is not set # CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set # CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# end of IoT - internet of things # # security packages @@ -358,6 +540,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_TINYCRYPT is not set # CONFIG_PKG_USING_TFM is not set # CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages # # language packages @@ -373,18 +556,22 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_JSMN is not set # CONFIG_PKG_USING_AGILE_JSMN is not set # CONFIG_PKG_USING_PARSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format # # XML: Extensible Markup Language # # CONFIG_PKG_USING_SIMPLE_XML is not set # CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + # CONFIG_PKG_USING_LUATOS_SOC is not set # CONFIG_PKG_USING_LUA is not set # CONFIG_PKG_USING_JERRYSCRIPT is not set # CONFIG_PKG_USING_MICROPYTHON is not set # CONFIG_PKG_USING_PIKASCRIPT is not set # CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages # # multimedia packages @@ -396,12 +583,15 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_LVGL is not set # CONFIG_PKG_USING_LV_MUSIC_DEMO is not set # CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library # # u8g2: a monochrome graphic library # # CONFIG_PKG_USING_U8G2_OFFICIAL is not set # CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + # CONFIG_PKG_USING_OPENMV is not set # CONFIG_PKG_USING_MUPDF is not set # CONFIG_PKG_USING_STEMWIN is not set @@ -421,6 +611,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QRCODE is not set # CONFIG_PKG_USING_GUIENGINE is not set # CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages # # tools packages @@ -469,6 +660,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set # CONFIG_PKG_USING_ZDEBUG is not set +# end of tools packages # # system packages @@ -480,6 +672,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RT_MEMCPY_CM is not set # CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set # CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set +# end of enhanced kernel services # # acceleration: Assembly language or algorithmic acceleration packages @@ -487,6 +680,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QFPLIB_M0_FULL is not set # CONFIG_PKG_USING_QFPLIB_M0_TINY is not set # CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages # # CMSIS: ARM Cortex-M Microcontroller Software Interface Standard @@ -497,6 +691,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_CMSIS_NN is not set # CONFIG_PKG_USING_CMSIS_RTOS1 is not set # CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard # # Micrium: Micrium software products porting for RT-Thread @@ -507,6 +702,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UC_CLK is not set # CONFIG_PKG_USING_UC_COMMON is not set # CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + # CONFIG_PKG_USING_FREERTOS_WRAPPER is not set # CONFIG_PKG_USING_LITEOS_SDK is not set # CONFIG_PKG_USING_TZ_DATABASE is not set @@ -554,6 +751,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_RTP is not set # CONFIG_PKG_USING_REB is not set # CONFIG_PKG_USING_R_RHEALSTONE is not set +# end of system packages # # peripheral libraries and drivers @@ -566,9 +764,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # STM32 HAL & SDK Drivers # -# CONFIG_PKG_USING_STM32L4XX_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set # CONFIG_PKG_USING_STM32WB55_SDK is not set # CONFIG_PKG_USING_STM32_SDIO is not set +# end of STM32 HAL & SDK Drivers + # CONFIG_PKG_USING_BLUETRUM_SDK is not set # CONFIG_PKG_USING_EMBARC_BSP is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -578,9 +779,12 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_K210_SDK is not set # CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# end of HAL & SDK Drivers # # sensors drivers @@ -650,6 +854,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_STHS34PF80 is not set +# end of sensors drivers # # touch drivers @@ -664,6 +869,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_XPT2046_TOUCH is not set # CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_BUTTON is not set # CONFIG_PKG_USING_PCF8574 is not set @@ -736,6 +943,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_BT_MX01 is not set # CONFIG_PKG_USING_RGPOWER is not set # CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers # # AI packages @@ -750,6 +958,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_QUEST is not set # CONFIG_PKG_USING_NAXOS is not set # CONFIG_PKG_USING_R_TINYMAIX is not set +# end of AI packages # # Signal Processing and Control Algorithm Packages @@ -759,6 +968,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_UKAL is not set # CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_KISSFFT is not set +# end of Signal Processing and Control Algorithm Packages # # miscellaneous packages @@ -767,6 +977,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # project laboratory # +# end of project laboratory # # samples: kernel and components samples @@ -775,6 +986,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set # CONFIG_PKG_USING_NETWORK_SAMPLES is not set # CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples # # entertainment: terminal games and other interesting software packages @@ -790,6 +1002,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_MORSE is not set +# end of entertainment: terminal games and other interesting software packages + # CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_FASTLZ is not set @@ -823,6 +1037,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_SOEM is not set # CONFIG_PKG_USING_QPARAM is not set # CONFIG_PKG_USING_CorevMCU_CLI is not set +# end of miscellaneous packages # # Arduino libraries @@ -838,6 +1053,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos # # Sensors @@ -977,6 +1193,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set # CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors # # Display @@ -988,6 +1206,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display # # Timing @@ -996,6 +1215,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set # CONFIG_PKG_USING_ARDUINO_TICKER is not set # CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing # # Data Processing @@ -1003,6 +1223,8 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set # CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set # CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing # # Data Storage @@ -1013,6 +1235,7 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication # # Device Control @@ -1024,12 +1247,14 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control # # Other # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other # # Signal IO @@ -1042,16 +1267,18 @@ CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO # # Uncategorized # +# end of Arduino libraries +# end of RT-Thread online packages # # Hardware Drivers Config # CONFIG_SOC_HPM6000=y -# CONFIG_BSP_USING_ENET_PHY_RTL8201 is not set # # On-chip Peripheral Drivers @@ -1083,3 +1310,5 @@ CONFIG_BSP_USING_RTC=y # CONFIG_BSP_USING_WDG is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_ADC is not set +# end of On-chip Peripheral Drivers +# end of Hardware Drivers Config diff --git a/bsp/hpmicro/hpm6750evk2/board/cherryusb_port.c b/bsp/hpmicro/hpm6750evk2/board/cherryusb_port.c new file mode 100644 index 00000000000..ecba0e65622 --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/cherryusb_port.c @@ -0,0 +1,14 @@ +/* + * Copyright (c) 2006-2024, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2024/04/23 sakumisu first version + */ +#include + +/* low level init here, this has implemented in cherryusb */ + +/* low level deinit here, this has implemented in cherryusb */ diff --git a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld index 0d29b2257e5..c993127eb1d 100644 --- a/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld +++ b/bsp/hpmicro/hpm6750evk2/board/linker_scripts/flash_rtt.ld @@ -111,6 +111,12 @@ SECTIONS KEEP (*(.fini)) . = ALIGN(8); + /* section information for usbh class */ + . = ALIGN(8); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + /********************************************* * * RT-Thread related sections - Start diff --git a/bsp/hpmicro/hpm6750evk2/board/usb_config.h b/bsp/hpmicro/hpm6750evk2/board/usb_config.h new file mode 100644 index 00000000000..bcc4e3e72ad --- /dev/null +++ b/bsp/hpmicro/hpm6750evk2/board/usb_config.h @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#define CHERRYUSB_VERSION 0x010300 +#define CHERRYUSB_VERSION_STR "v1.3.0" + +/* ================ USB common Configuration ================ */ + +#include +#include "hpm_soc_feature.h" + +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) + +#define usb_malloc(size) rt_malloc(size) +#define usb_free(ptr) rt_free(ptr) + +#define memcpy rt_memcpy + +#ifndef CONFIG_USB_DBG_LEVEL +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#ifndef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS USB_SOC_MAX_COUNT // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM USB_SOC_DCD_MAX_ENDPOINT_COUNT +#endif + +/* ---------------- FSDEV Configuration ---------------- */ +//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference + +/* ---------------- DWC2 Configuration ---------------- */ +// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) +// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS USB_SOC_MAX_COUNT +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* ---------------- EHCI Configuration ---------------- */ + +#define CONFIG_USB_EHCI_HCCR_OFFSET (0x100) +#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 +#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USB_EHCI_QTD_NUM 3 +#define CONFIG_USB_EHCI_ITD_NUM 20 +// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE +// #define CONFIG_USB_EHCI_CONFIGFLAG +// #define CONFIG_USB_EHCI_ISO +// #define CONFIG_USB_EHCI_WITH_OHCI + +/* ---------------- OHCI Configuration ---------------- */ +#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0) + +/* ---------------- XHCI Configuration ---------------- */ +#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0) + +/* ---------------- DWC2 Configuration ---------------- */ +/* largest non-periodic USB packet used / 4 */ +// #define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4) +/* largest periodic USB packet used / 4 */ +// #define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4) +/* + * (largest USB packet used / 4) + 1 for status information + 1 transfer complete + + * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario + */ +// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +#define CONFIG_USB_EHCI_HPMICRO (1) +#endif diff --git a/bsp/hpmicro/hpm6750evk2/rtconfig.h b/bsp/hpmicro/hpm6750evk2/rtconfig.h index e581610a7bf..c24f3616a8d 100644 --- a/bsp/hpmicro/hpm6750evk2/rtconfig.h +++ b/bsp/hpmicro/hpm6750evk2/rtconfig.h @@ -1,9 +1,6 @@ #ifndef RT_CONFIG_H__ #define RT_CONFIG_H__ -/* Automatically generated file; DO NOT EDIT. */ -/* RT-Thread Configuration */ - /* RT-Thread Kernel */ #define RT_NAME_MAX 8 @@ -17,13 +14,18 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 512 +#define IDLE_THREAD_STACK_SIZE 2048 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_TIMER_THREAD_STACK_SIZE 2048 /* kservice optimization */ +/* end of kservice optimization */ + +/* klibc optimization */ + +/* end of klibc optimization */ /* Inter-Thread communication */ @@ -32,6 +34,7 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ /* Memory Management */ @@ -39,12 +42,14 @@ #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP +/* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart0" -#define RT_VER_NUM 0x50100 +#define RT_VER_NUM 0x50200 #define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ /* RT-Thread Components */ @@ -70,19 +75,37 @@ /* DFS: device virtual file system */ +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_DEVFS +/* end of DFS: device virtual file system */ /* Device Drivers */ #define RT_USING_DEVICE_IPC #define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_RB_BUFSZ 64 #define RT_USING_RTC #define RT_USING_PIN - -/* Using USB */ - +#define RT_USING_CHERRYUSB +#define RT_CHERRYUSB_HOST +#define RT_CHERRYUSB_HOST_EHCI_HPM +#define RT_CHERRYUSB_HOST_CDC_ACM +#define RT_CHERRYUSB_HOST_HID +#define RT_CHERRYUSB_HOST_TEMPLATE +#define TEST_USBH_CDC_ACM 1 +#define TEST_USBH_HID 1 +/* end of Device Drivers */ /* C/C++ and POSIX layer */ @@ -94,27 +117,105 @@ #define RT_LIBC_TZ_DEFAULT_HOUR 8 #define RT_LIBC_TZ_DEFAULT_MIN 0 #define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ /* POSIX (Portable Operating System Interface) layer */ +#define RT_USING_POSIX_FS +#define RT_USING_POSIX_POLL +#define RT_USING_POSIX_SELECT +#define RT_USING_POSIX_SOCKET /* Interprocess Communication (IPC) */ /* Socket is in the 'Network' category */ +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +/* end of Docking with protocol stacks */ +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 4 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS +#define RT_LWIP_DHCP +#define IP_SOF_BROADCAST 1 +#define IP_SOF_BROADCAST_RECV 1 + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.1.30" +#define RT_LWIP_GWADDR "192.168.1.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +/* end of Static IPv4 Address */ +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 16 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 10 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 1024 +#define LWIP_NO_RX_THREAD +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 1024 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define RT_LWIP_NETIF_NAMESIZE 6 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +/* end of Network */ /* Memory protection */ +/* end of Memory protection */ /* Utilities */ +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ /* RT-Thread Utestcases */ +/* end of RT-Thread Utestcases */ /* RT-Thread online packages */ @@ -125,57 +226,83 @@ /* Marvell WiFi */ +/* end of Marvell WiFi */ /* Wiced WiFi */ +/* end of Wiced WiFi */ /* CYW43012 WiFi */ +/* end of CYW43012 WiFi */ /* BL808 WiFi */ +/* end of BL808 WiFi */ /* CYW43439 WiFi */ +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ +#define PKG_USING_NETUTILS +#define PKG_NETUTILS_IPERF +#define IPERF_THREAD_STACK_SIZE 2048 +#define PKG_USING_NETUTILS_LATEST_VERSION +#define PKG_NETUTILS_VER_NUM 0x99999 /* IoT Cloud */ +/* end of IoT Cloud */ +/* end of IoT - internet of things */ /* security packages */ +/* end of security packages */ /* language packages */ /* JSON: JavaScript Object Notation, a lightweight data-interchange format */ +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ /* XML: Extensible Markup Language */ +/* end of XML: Extensible Markup Language */ +/* end of language packages */ /* multimedia packages */ /* LVGL: powerful and easy-to-use embedded GUI library */ +/* end of LVGL: powerful and easy-to-use embedded GUI library */ /* u8g2: a monochrome graphic library */ +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ /* tools packages */ +/* end of tools packages */ /* system packages */ /* enhanced kernel services */ +/* end of enhanced kernel services */ /* acceleration: Assembly language or algorithmic acceleration packages */ +/* end of acceleration: Assembly language or algorithmic acceleration packages */ /* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ /* Micrium: Micrium software products porting for RT-Thread */ +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ /* peripheral libraries and drivers */ @@ -183,66 +310,91 @@ /* STM32 HAL & SDK Drivers */ +/* end of STM32 HAL & SDK Drivers */ /* Kendryte SDK */ +/* end of Kendryte SDK */ +/* end of HAL & SDK Drivers */ /* sensors drivers */ +/* end of sensors drivers */ /* touch drivers */ +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ /* AI packages */ +/* end of AI packages */ /* Signal Processing and Control Algorithm Packages */ +/* end of Signal Processing and Control Algorithm Packages */ /* miscellaneous packages */ /* project laboratory */ +/* end of project laboratory */ + /* samples: kernel and components samples */ +/* end of samples: kernel and components samples */ /* entertainment: terminal games and other interesting software packages */ +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ /* Arduino libraries */ /* Projects and Demos */ +/* end of Projects and Demos */ /* Sensors */ +/* end of Sensors */ /* Display */ +/* end of Display */ /* Timing */ +/* end of Timing */ /* Data Processing */ +/* end of Data Processing */ /* Data Storage */ /* Communication */ +/* end of Communication */ /* Device Control */ +/* end of Device Control */ /* Other */ +/* end of Other */ /* Signal IO */ +/* end of Signal IO */ /* Uncategorized */ +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ + /* Hardware Drivers Config */ #define SOC_HPM6000 @@ -253,5 +405,7 @@ #define BSP_USING_UART #define BSP_USING_UART0 #define BSP_USING_RTC +/* end of On-chip Peripheral Drivers */ +/* end of Hardware Drivers Config */ #endif diff --git a/bsp/hpmicro/libraries/hpm_sdk/SConscript b/bsp/hpmicro/libraries/hpm_sdk/SConscript index 008c4f6dacf..978f6501413 100644 --- a/bsp/hpmicro/libraries/hpm_sdk/SConscript +++ b/bsp/hpmicro/libraries/hpm_sdk/SConscript @@ -68,7 +68,7 @@ if GetDepend(['BSP_USING_FEMC']): if GetDepend(['BSP_USING_PWM']): src += ['drivers/src/hpm_pwm_drv.c'] -if GetDepend(['BSP_USING_USB']): +if GetDepend(['BSP_USING_USB']) or GetDepend(['RT_USING_CHERRYUSB']): src += ['drivers/src/hpm_usb_drv.c'] if GetDepend(['BSP_USING_I2S']): diff --git a/components/Kconfig b/components/Kconfig index cef29589c96..d3f2eef7796 100644 --- a/components/Kconfig +++ b/components/Kconfig @@ -44,4 +44,7 @@ if RT_USING_SMART source "$RTT_DIR/components/lwp/Kconfig" source "$RTT_DIR/components/mm/Kconfig" endif + +source "$RTT_DIR/components/legacy/Kconfig" + endmenu diff --git a/components/drivers/Kconfig b/components/drivers/Kconfig index 55be53624b9..cfb01728534 100755 --- a/components/drivers/Kconfig +++ b/components/drivers/Kconfig @@ -937,205 +937,6 @@ source "$RTT_DIR/components/drivers/pinctrl/Kconfig" source "$RTT_DIR/components/drivers/ktime/Kconfig" source "$RTT_DIR/components/drivers/clk/Kconfig" source "$RTT_DIR/components/drivers/hwtimer/Kconfig" +source "$RTT_DIR/components/drivers/usb/cherryusb/Kconfig" -menu "Using USB" - config RT_USING_USB - bool - default n - - config RT_USING_USB_HOST - bool "Using USB host" - default n - select RT_USING_USB - - if RT_USING_USB_HOST - config RT_USBH_MSTORAGE - bool "Enable Udisk Drivers" - default n - if RT_USBH_MSTORAGE - config UDISK_MOUNTPOINT - string "Udisk mount dir" - default "/" - endif - config RT_USBH_HID - bool "Enable HID Drivers" - default n - if RT_USBH_HID - config RT_USBH_HID_MOUSE - bool "Enable HID mouse protocol" - default n - config RT_USBH_HID_KEYBOARD - bool "Enable HID keyboard protocol" - default n - endif - endif - config RT_USING_USB_DEVICE - bool "Using USB device" - default n - select RT_USING_USB - - if RT_USING_USB_DEVICE || RT_USING_USB_HOST - config RT_USBD_THREAD_STACK_SZ - int "usb thread stack size" - default 4096 - endif - if RT_USING_USB_DEVICE - config USB_VENDOR_ID - hex "USB Vendor ID" - default 0x0FFE - config USB_PRODUCT_ID - hex "USB Product ID" - default 0x0001 - - config RT_USB_DEVICE_COMPOSITE - bool "Enable composite device" - default n - choice - prompt "Device type" - default _RT_USB_DEVICE_NONE - depends on !RT_USB_DEVICE_COMPOSITE - config _RT_USB_DEVICE_NONE - bool "Using custom class by register interface" - select RT_USB_DEVICE_NONE - config _RT_USB_DEVICE_CDC - bool "Enable to use device as CDC device" - select RT_USB_DEVICE_CDC - config _RT_USB_DEVICE_MSTORAGE - bool "Enable to use device as Mass Storage device" - select RT_USB_DEVICE_MSTORAGE - config _RT_USB_DEVICE_HID - bool "Enable to use device as HID device" - select RT_USB_DEVICE_HID - config _RT_USB_DEVICE_RNDIS - bool "Enable to use device as rndis device" - select RT_USB_DEVICE_RNDIS - depends on RT_USING_LWIP - config _RT_USB_DEVICE_ECM - bool "Enable to use device as ecm device" - select RT_USB_DEVICE_ECM - depends on RT_USING_LWIP - config _RT_USB_DEVICE_WINUSB - bool "Enable to use device as winusb device" - select RT_USB_DEVICE_WINUSB - config _RT_USB_DEVICE_AUDIO - bool "Enable to use device as audio device" - select RT_USB_DEVICE_AUDIO - endchoice - if RT_USB_DEVICE_COMPOSITE - config RT_USB_DEVICE_CDC - bool "Enable to use device as CDC device" - default n - config RT_USB_DEVICE_NONE - bool - default y - config RT_USB_DEVICE_MSTORAGE - bool "Enable to use device as Mass Storage device" - default n - config RT_USB_DEVICE_HID - bool "Enable to use device as HID device" - default n - config RT_USB_DEVICE_RNDIS - bool "Enable to use device as rndis device" - default n - depends on RT_USING_LWIP - config RT_USB_DEVICE_ECM - bool "Enable to use device as ecm device" - default n - depends on RT_USING_LWIP - config RT_USB_DEVICE_WINUSB - bool "Enable to use device as winusb device" - default n - config RT_USB_DEVICE_AUDIO - bool "Enable to use device as audio device" - default n - endif - if RT_USB_DEVICE_CDC - config RT_VCOM_TASK_STK_SIZE - int "virtual com thread stack size" - default 512 - config RT_CDC_RX_BUFSIZE - int "virtual com rx buffer size" - default 128 - config RT_VCOM_TX_USE_DMA - bool "Enable to use dma for vcom tx" - default n - config RT_VCOM_SERNO - string "serial number of virtual com" - default "32021919830108" - config RT_VCOM_SER_LEN - int "serial number length of virtual com" - default 14 - config RT_VCOM_TX_TIMEOUT - int "tx timeout(ticks) of virtual com" - default 1000 - endif - if RT_USB_DEVICE_WINUSB - config RT_WINUSB_GUID - string "Guid for winusb" - default "{6860DC3C-C05F-4807-8807-1CA861CC1D66}" - endif - if RT_USB_DEVICE_MSTORAGE - config RT_USB_MSTORAGE_DISK_NAME - string "msc class disk name" - default "flash0" - endif - - if RT_USB_DEVICE_RNDIS - config RNDIS_DELAY_LINK_UP - bool "Delay linkup media connection" - select RT_USING_TIMER_SOFT - default n - endif - - if RT_USB_DEVICE_HID - config RT_USB_DEVICE_HID_KEYBOARD - bool "Use to HID device as Keyboard" - default n - if RT_USB_DEVICE_HID_KEYBOARD - config RT_USB_DEVICE_HID_KEYBOARD_NUMBER - int "Number of Keyboard(max 3)" - default 1 - range 1 3 - endif - config RT_USB_DEVICE_HID_MOUSE - bool "Use to HID device as Mouse" - default n - config RT_USB_DEVICE_HID_GENERAL - bool "Use to HID device as General HID device" - default y - if RT_USB_DEVICE_HID_GENERAL - config RT_USB_DEVICE_HID_GENERAL_OUT_REPORT_LENGTH - int "General HID device out report length" - default 63 - range 0 63 - - config RT_USB_DEVICE_HID_GENERAL_IN_REPORT_LENGTH - int "General HID device in report length" - default 63 - range 0 63 - endif - config RT_USB_DEVICE_HID_MEDIA - bool "Use to HID device as media keyboard" - default y - endif - if RT_USB_DEVICE_AUDIO - config RT_USB_DEVICE_AUDIO_MIC - bool "Use usb mic device as audio device" - default n - if RT_USB_DEVICE_AUDIO_MIC - config RT_USBD_MIC_DEVICE_NAME - string "audio mic device name" - default "mic0" - endif - config RT_USB_DEVICE_AUDIO_SPEAKER - bool "Use usb speaker device as audio device" - default n - if RT_USB_DEVICE_AUDIO_SPEAKER - config RT_USBD_SPEAKER_DEVICE_NAME - string "audio speaker device name" - default "sound0" - endif - endif - endif - endmenu endmenu diff --git a/components/drivers/usb/.ignore_format.yml b/components/drivers/usb/.ignore_format.yml new file mode 100755 index 00000000000..799e138c9d0 --- /dev/null +++ b/components/drivers/usb/.ignore_format.yml @@ -0,0 +1,6 @@ +# files format check exclude path, please follow the instructions below to modify; +# If you need to exclude an entire folder, add the folder path in dir_path; +# If you need to exclude a file, add the path to the file in file_path. + +dir_path: +- cherryusb \ No newline at end of file diff --git a/components/drivers/usb/SConscript b/components/drivers/usb/SConscript index 3e148cefe23..4c815c49b83 100644 --- a/components/drivers/usb/SConscript +++ b/components/drivers/usb/SConscript @@ -1,13 +1,15 @@ -# for module compiling +# RT-Thread building script for bridge + import os from building import * -cwd = GetCurrentDir() -objs = [] -list = os.listdir(cwd) +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) for d in list: path = os.path.join(cwd, d) if os.path.isfile(os.path.join(path, 'SConscript')): objs = objs + SConscript(os.path.join(d, 'SConscript')) + Return('objs') diff --git a/components/drivers/usb/cherryusb/.clang-format b/components/drivers/usb/cherryusb/.clang-format new file mode 100644 index 00000000000..336989ded69 --- /dev/null +++ b/components/drivers/usb/cherryusb/.clang-format @@ -0,0 +1,171 @@ +# clang-format configuration file. Intended for clang-format >= 11.0 +# +# For more information, see: +# +# https://clang.llvm.org/docs/ClangFormat.html +# https://clang.llvm.org/docs/ClangFormatStyleOptions.html +# +--- +# 语言: None, Cpp, Java, JavaScript, ObjC, Proto, TableGen, TextProto +Language: Cpp +# BasedOnStyle: LLVM +# 访问说明符(public、private等)的偏移 +AccessModifierOffset: -4 +# 开括号(开圆括号、开尖括号、开方括号)后的对齐: Align, DontAlign, AlwaysBreak(总是在开括号后换行) +AlignAfterOpenBracket: Align +# 连续赋值时，对齐所有等号 +AlignConsecutiveAssignments: false +# 对齐位域 +AlignConsecutiveBitFields: true +# 连续声明时，对齐所有声明的变量名 +AlignConsecutiveDeclarations: false +# 连续宏时，进行对齐 +AlignConsecutiveMacros: true +# 左对齐逃脱换行(使用反斜杠换行)的反斜杠 +AlignEscapedNewlines: Left +# 水平对齐二元和三元表达式的操作数 +AlignOperands: true +# 对齐连续的尾随的注释 +AlignTrailingComments: true +# 允许函数声明的所有参数在放在下一行 +AllowAllParametersOfDeclarationOnNextLine: false +# 允许短的块放在同一行 +AllowShortBlocksOnASingleLine: false +# 允许短的case标签放在同一行 +AllowShortCaseLabelsOnASingleLine: false +# 允许短的函数放在同一行: None, InlineOnly(定义在类中), Empty(空函数), Inline(定义在类中，空函数), All +AllowShortFunctionsOnASingleLine: None +# 允许短的if语句保持在同一行 +AllowShortIfStatementsOnASingleLine: false +# 允许短的循环保持在同一行 +AllowShortLoopsOnASingleLine: false +# 总是在定义返回类型后换行(deprecated) +AlwaysBreakAfterDefinitionReturnType: None +# 总是在返回类型后换行: None, All, TopLevel(顶级函数，不包括在类中的函数), +# AllDefinitions(所有的定义，不包括声明), TopLevelDefinitions(所有的顶级函数的定义) +AlwaysBreakAfterReturnType: None +# 总是在多行string字面量前换行 +AlwaysBreakBeforeMultilineStrings: false +# 总是在template声明后换行 +AlwaysBreakTemplateDeclarations: false +# false表示函数实参要么都在同一行，要么都各自一行 +BinPackArguments: true +# false表示所有形参要么都在同一行，要么都各自一行 +BinPackParameters: true +# 大括号换行，只有当BreakBeforeBraces设置为Custom时才有效 +BraceWrapping: + AfterClass: false + AfterControlStatement: false + AfterEnum: false + AfterFunction: true + AfterNamespace: false + AfterObjCDeclaration: false + AfterStruct: false + AfterUnion: false + AfterExternBlock: false # Unknown to clang-format-5.0 + BeforeCatch: false + BeforeElse: false + IndentBraces: false + SplitEmptyFunction: true # Unknown to clang-format-4.0 + SplitEmptyRecord: true # Unknown to clang-format-4.0 + SplitEmptyNamespace: true # Unknown to clang-format-4.0 +# 在二元运算符前换行: None(在操作符后换行), NonAssignment(在非赋值的操作符前换行), All(在操作符前换行) +BreakBeforeBinaryOperators: None +BreakBeforeBraces: Custom +#BreakBeforeInheritanceComma: false # Unknown to clang-format-4.0 +# 在三元运算符前换行 +BreakBeforeTernaryOperators: false +# 在构造函数的初始化列表的逗号前换行 +BreakConstructorInitializersBeforeComma: false +BreakAfterJavaFieldAnnotations: false +BreakStringLiterals: false +# 每行字符的限制，0表示没有限制 +ColumnLimit: 0 +# 描述具有特殊意义的注释的正则表达式，它不应该被分割为多行或以其它方式改变 +CommentPragmas: '^ IWYU pragma:' +CompactNamespaces: false # Unknown to clang-format-4.0 +# 构造函数的初始化列表要么都在同一行，要么都各自一行 +ConstructorInitializerAllOnOneLineOrOnePerLine: false +# 构造函数的初始化列表的缩进宽度 +ConstructorInitializerIndentWidth: 4 +# 延续的行的缩进宽度 +ContinuationIndentWidth: 4 +# 去除C++11的列表初始化的大括号{后和}前的空格 +Cpp11BracedListStyle: false +# 继承最常用的指针和引用的对齐方式 +DerivePointerAlignment: false +# 关闭格式化 +DisableFormat: false +ForEachMacros: + - 'SHELL_EXPORT_CMD' + +# 自动检测函数的调用和定义是否被格式为每行一个参数(Experimental) +ExperimentalAutoDetectBinPacking: false +# 缩进case标签 +IndentCaseLabels: true +# 缩进宽度 +IndentWidth: 4 +# 函数返回类型换行时，缩进函数声明或函数定义的函数名 +IndentWrappedFunctionNames: false +# 保留在块开始处的空行 +KeepEmptyLinesAtTheStartOfBlocks: false +# 开始一个块的宏的正则表达式 +MacroBlockBegin: '' +# 结束一个块的宏的正则表达式 +MacroBlockEnd: '' +# 连续空行的最大数量 +MaxEmptyLinesToKeep: 1 +# 命名空间的缩进: None, Inner(缩进嵌套的命名空间中的内容), All +NamespaceIndentation: None +# 使用ObjC块时缩进宽度 +ObjCBlockIndentWidth: 4 +# 在ObjC的@property后添加一个空格 +ObjCSpaceAfterProperty: false +# 在ObjC的protocol列表前添加一个空格 +ObjCSpaceBeforeProtocolList: true +# 在call(后对函数调用换行的penalty +PenaltyBreakBeforeFirstCallParameter: 30 +# 在一个注释中引入换行的penalty +PenaltyBreakComment: 10 +# 第一次在<<前换行的penalty +PenaltyBreakFirstLessLess: 0 +# 在一个字符串字面量中引入换行的penalty +PenaltyBreakString: 10 +# 对于每个在行字符数限制之外的字符的penalty +PenaltyExcessCharacter: 100 +# 将函数的返回类型放到它自己的行的penalty +PenaltyReturnTypeOnItsOwnLine: 60 +# 指针和引用的对齐: Left, Right, Middle +PointerAlignment: Right +# 允许重新排版注释 +ReflowComments: false +# 允许排序#include +SortIncludes: false +# 在C风格类型转换后添加空格 +SpaceAfterCStyleCast: false +# 在赋值运算符之前添加空格 +SpaceBeforeAssignmentOperators: true +# 开圆括号之前添加一个空格: Never, ControlStatements, Always +SpaceBeforeParens: ControlStatements +# 在空的圆括号中添加空格 +SpaceInEmptyParentheses: false +# 在尾随的评论前添加的空格数(只适用于//) +SpacesBeforeTrailingComments: 1 +# 在尖括号的<后和>前添加空格 +SpacesInAngles: false +# 在容器(ObjC和JavaScript的数组和字典等)字面量中添加空格 +SpacesInContainerLiterals: false +# 在C风格类型转换的括号中添加空格 +SpacesInCStyleCastParentheses: false +# 在圆括号的(后和)前添加空格 +SpacesInParentheses: false +# 在方括号的[后和]前添加空格，lamda表达式和未指明大小的数组的声明不受影响 +SpacesInSquareBrackets: false +# 标准: Cpp03, Cpp11, Auto +Standard: Cpp03 +# tab宽度 +TabWidth: 4 +# 使用tab字符: Never, ForIndentation, ForContinuationAndIndentation, Always +UseTab: Never +... + diff --git a/components/drivers/usb/cherryusb/.gitattributes b/components/drivers/usb/cherryusb/.gitattributes new file mode 100644 index 00000000000..74d8c6b212c --- /dev/null +++ b/components/drivers/usb/cherryusb/.gitattributes @@ -0,0 +1,47 @@ +*.c linguist-language=C +*.C linguist-language=C +*.h linguist-language=C +*.H linguist-language=C + +* text=auto + +*.S text +*.asm text +*.c text +*.cc text +*.cpp text +*.cxx text +*.h text +*.htm text +*.html text +*.in text +*.ld text +*.m4 text +*.mak text +*.mk text +*.py text +*.rb text +*.s text +*.sct text +*.sh text +*.txt text +*.xml text +SConscript text +Makefile text +AUTHORS text +COPYING text + +*.LZO -text +*.Opt -text +*.Uv2 -text +*.ewp -text +*.eww -text +*.vcproj -text +*.bat -text +*.dos -text +*.icf -text +*.inf -text +*.ini -text +*.sct -text +*.xsd -text +Jamfile -text \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/.gitignore b/components/drivers/usb/cherryusb/.gitignore new file mode 100644 index 00000000000..22b1a7fa274 --- /dev/null +++ b/components/drivers/usb/cherryusb/.gitignore @@ -0,0 +1,23 @@ +.vscode +**/Drivers/** +**/MDK-ARM/DebugConfig/** +**/MDK-ARM/RTE/** +**/obj/** +**/RET/** +**/Listings/** +**/Objects/** +*.map +*.o +*.d +*.htm +*.dep +*.lnp +*.iex +*.lst +*.axf +*.crf +*.hex +*.Bak +*.uvguix.* +*.scvd +*.usb.tmp \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/.readthedocs.yaml b/components/drivers/usb/cherryusb/.readthedocs.yaml new file mode 100644 index 00000000000..ed14f4de230 --- /dev/null +++ b/components/drivers/usb/cherryusb/.readthedocs.yaml @@ -0,0 +1,35 @@ +# Read the Docs configuration file for Sphinx projects +# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details + +# Required +version: 2 + +# Set the OS, Python version and other tools you might need +build: + os: ubuntu-22.04 + tools: + python: "3.11" + # You can also specify other tool versions: + # nodejs: "20" + # rust: "1.70" + # golang: "1.20" + +# Build documentation in the "docs/" directory with Sphinx +sphinx: + configuration: docs/source/conf.py + # You can configure Sphinx to use a different builder, for instance use the dirhtml builder for simpler URLs + # builder: "dirhtml" + # Fail on all warnings to avoid broken references + # fail_on_warning: true + +# Optionally build your docs in additional formats such as PDF and ePub +# formats: +# - pdf +# - epub + +# Optional but recommended, declare the Python requirements required +# to build your documentation +# See https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html +python: + install: + - requirements: docs/requirements.txt \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/CherryUSB.svg b/components/drivers/usb/cherryusb/CherryUSB.svg new file mode 100644 index 00000000000..c1ed4782122 --- /dev/null +++ b/components/drivers/usb/cherryusb/CherryUSB.svg @@ -0,0 +1,3 @@ + + +
CherryUSB
CherryUSB
Hardware
Hardware
BL
BL
DWC2
DWC2
OHCI
OHCI
EHCI
EHCI
XHCI
XHCI
MUSB
MUSB
FSDEV
FSDEV
HPM
HPM
Device Controller Driver (DCD)
Device Controller Driver (DCD)
Host Controller Driver (HCD)
Host Controller Driver (HCD)
OS Abstraction Layer (OSAL)
OS Abstraction Layer (OSAL)
USB Host
USB Host
USB Host Core
USB Host Core
HID
HID
MSC
MSC
CDC
CDC
UAC
UAC
UVC
UVC
RNDIS
RNDIS
VENDOR
VENDOR
HUB
HUB
USB Device
USB Device
USB Device Core
USB Device Core
HID
HID
MSC
MSC
CDC
CDC
UAC
UAC
UVC
UVC
RNDIS
RNDIS
VENDOR
VENDOR
DFU
DFU
optional
optional
required
requiredText is not SVG - cannot display \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/Kconfig b/components/drivers/usb/cherryusb/Kconfig new file mode 100644 index 00000000000..fdd5bbc7e8e --- /dev/null +++ b/components/drivers/usb/cherryusb/Kconfig @@ -0,0 +1,310 @@ +# Kconfig file for package CherryUSB +menuconfig RT_USING_CHERRYUSB + bool "Using USB with CherryUSB" + default n + +if RT_USING_CHERRYUSB + + menuconfig RT_CHERRYUSB_DEVICE + bool "Enable usb device mode" + default n + + if RT_CHERRYUSB_DEVICE + choice + prompt "Select usb device speed" + default RT_CHERRYUSB_DEVICE_SPEED_FS + config RT_CHERRYUSB_DEVICE_SPEED_FS + bool "FS" + config RT_CHERRYUSB_DEVICE_SPEED_HS + bool "HS" + config RT_CHERRYUSB_DEVICE_SPEED_AUTO + bool "AUTO" + endchoice + + choice + prompt "Select usb device ip, and some ip need config in usb_config.h, please check" + default RT_CHERRYUSB_DEVICE_CUSTOM + config RT_CHERRYUSB_DEVICE_CUSTOM + bool "CUSTOM (Implement it yourself)" + config RT_CHERRYUSB_DEVICE_FSDEV + bool "fsdev" + config RT_CHERRYUSB_DEVICE_DWC2_ST + bool "dwc2_st" + config RT_CHERRYUSB_DEVICE_DWC2_ESP + bool "dwc2_esp" + config RT_CHERRYUSB_DEVICE_DWC2_AT + bool "dwc2_at" + config RT_CHERRYUSB_DEVICE_DWC2_GD + bool "dwc2_gd" + config RT_CHERRYUSB_DEVICE_DWC2_CUSTOM + bool "dwc2_custom" + config RT_CHERRYUSB_DEVICE_MUSB_STANDARD + bool "musb_standard" + config RT_CHERRYUSB_DEVICE_MUSB_SUNXI + bool "musb_sunxi" + config RT_CHERRYUSB_DEVICE_MUSB_CUSTOM + bool "musb_custom" + config RT_CHERRYUSB_DEVICE_BL + bool "bouffalo" + config RT_CHERRYUSB_DEVICE_CH32 + bool "ch32" + config RT_CHERRYUSB_DEVICE_HPM + bool "hpm" + config RT_CHERRYUSB_DEVICE_AIC + bool "aic" + config RT_CHERRYUSB_DEVICE_PUSB2 + bool "pusb2" + endchoice + + config RT_CHERRYUSB_DEVICE_CDC_ACM + bool + prompt "Enable usb cdc acm device" + default n + + config RT_CHERRYUSB_DEVICE_HID + bool + prompt "Enable usb hid device" + default n + + config RT_CHERRYUSB_DEVICE_MSC + bool + prompt "Enable usb msc device" + default n + + config RT_CHERRYUSB_DEVICE_AUDIO + bool + prompt "Enable usb audio device" + default n + + config RT_CHERRYUSB_DEVICE_VIDEO + bool + prompt "Enable usb video device" + default n + + config RT_CHERRYUSB_DEVICE_CDC_RNDIS + bool + prompt "Enable usb cdc rndis device" + default n + + config RT_CHERRYUSB_DEVICE_CDC_ECM + bool + prompt "Enable usb cdc ecm device" + default n + + config RT_CHERRYUSB_DEVICE_CDC_NCM + bool + prompt "Enable usb cdc ncm device" + default n + + config RT_CHERRYUSB_DEVICE_DFU + bool + prompt "Enable usb dfu device" + default n + + choice + prompt "Select usb device template" + default RT_CHERRYUSB_DEVICE_TEMPLATE + config RT_CHERRYUSB_DEVICE_TEMPLATE_NONE + bool "none (Implement it yourself)" + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM + bool "cdc_acm" + config RT_CHERRYUSB_DEVICE_TEMPLATE_MSC + bool "msc" + config RT_CHERRYUSB_DEVICE_TEMPLATE_HID_KEYBOARD + bool "hid_keyboard" + config RT_CHERRYUSB_DEVICE_TEMPLATE_HID_MOUSE + bool "hid_mouse" + config RT_CHERRYUSB_DEVICE_TEMPLATE_HID_CUSTOM + bool "hid_custom" + config RT_CHERRYUSB_DEVICE_TEMPLATE_VIDEO + bool "video" + config RT_CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V1_MIC_SPEAKER + bool "audio_v1_mic_speaker_multichan" + config RT_CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V2_MIC_SPEAKER + bool "audio_v2_mic_speaker_multichan" + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_RNDIS + bool "cdc_rndis" + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ECM + bool "cdc_ecm" + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_NCM + bool "cdc_ncm" + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC + bool "cdc_acm_msc" + config RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC_HID + bool "cdc_acm_msc_hid" + config RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV1 + bool "winusbv1" + config RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_CDC + bool "winusbv2_cdc" + config RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_HID + bool "winusbv2_hid" + endchoice + + endif + + menuconfig RT_CHERRYUSB_HOST + bool "Enable usb host mode" + default n + + if RT_CHERRYUSB_HOST + choice + prompt "Select usb host ip, and some ip need config in usb_config.h, please check" + default RT_CHERRYUSB_HOST_CUSTOM + config RT_CHERRYUSB_HOST_CUSTOM + bool "CUSTOM (Implement it yourself)" + config RT_CHERRYUSB_HOST_EHCI_BL + bool "ehci_bouffalo" + config RT_CHERRYUSB_HOST_EHCI_HPM + bool "ehci_hpm" + config RT_CHERRYUSB_HOST_EHCI_AIC + bool "ehci_aic" + config RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 + bool "ehci_nuvoton_nuc980" + config RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 + bool "ehci_nuvoton_ma35d0" + config RT_CHERRYUSB_HOST_EHCI_CUSTOM + bool "ehci_custom" + config RT_CHERRYUSB_HOST_DWC2_ST + bool "dwc2_st" + config RT_CHERRYUSB_HOST_DWC2_ESP + bool "dwc2_esp" + config RT_CHERRYUSB_HOST_DWC2_CUSTOM + bool "dwc2_custom" + config RT_CHERRYUSB_HOST_MUSB_STANDARD + bool "musb_standard" + config RT_CHERRYUSB_HOST_MUSB_SUNXI + bool "musb_sunxi" + config RT_CHERRYUSB_HOST_MUSB_CUSTOM + bool "musb_custom" + config RT_CHERRYUSB_HOST_PUSB2 + bool "pusb2" + config RT_CHERRYUSB_HOST_XHCI + bool "xhci" + endchoice + + config RT_CHERRYUSB_HOST_CDC_ACM + bool + prompt "Enable usb cdc acm driver" + default n + + config RT_CHERRYUSB_HOST_HID + bool + prompt "Enable usb hid driver" + default n + + config RT_CHERRYUSB_HOST_MSC + bool + prompt "Enable usb msc driver" + default n + select RT_USING_DFS + + config RT_CHERRYUSB_HOST_CDC_ECM + bool + prompt "Enable usb cdc ecm driver" + select RT_USING_LWIP + select RT_USING_LWIP212 + select CONFIG_USBHOST_PLATFORM_CDC_ECM + default n + + config RT_CHERRYUSB_HOST_CDC_RNDIS + bool + prompt "Enable usb rndis driver" + select RT_USING_LWIP + select RT_USING_LWIP212 + select CONFIG_USBHOST_PLATFORM_CDC_RNDIS + default n + + config RT_CHERRYUSB_HOST_CDC_NCM + bool + prompt "Enable usb cdc ncm driver" + select RT_USING_LWIP + select RT_USING_LWIP212 + select CONFIG_USBHOST_PLATFORM_CDC_NCM + default n + + config RT_CHERRYUSB_HOST_VIDEO + bool + prompt "Enable usb video driver, it is commercial charge" + default n + + config RT_CHERRYUSB_HOST_AUDIO + bool + prompt "Enable usb audio driver, it is commercial charge" + default n + + config RT_CHERRYUSB_HOST_BLUETOOTH + bool + prompt "Enable usb bluetooth driver" + default n + + config RT_CHERRYUSB_HOST_ASIX + bool + prompt "Enable usb asix driver" + select RT_USING_LWIP + select RT_USING_LWIP212 + select CONFIG_USBHOST_PLATFORM_CDC_ASIX + default n + + config RT_CHERRYUSB_HOST_RTL8152 + bool + prompt "Enable usb rtl8152 driver" + select RT_USING_LWIP + select RT_USING_LWIP212 + select CONFIG_USBHOST_PLATFORM_CDC_RTL8152 + default n + + config RT_CHERRYUSB_HOST_FTDI + bool + prompt "Enable usb ftdi driver" + default n + + config RT_CHERRYUSB_HOST_CH34X + bool + prompt "Enable usb ch34x driver" + default n + + config RT_CHERRYUSB_HOST_CP210X + bool + prompt "Enable usb cp210x driver" + default n + + config RT_CHERRYUSB_HOST_PL2303 + bool + prompt "Enable usb pl2303 driver" + default n + + config CONFIG_USBHOST_PLATFORM_CDC_ECM + bool + + config CONFIG_USBHOST_PLATFORM_CDC_RNDIS + bool + + config CONFIG_USBHOST_PLATFORM_CDC_NCM + bool + + config CONFIG_USBHOST_PLATFORM_ASIX + bool + + config CONFIG_USBHOST_PLATFORM_RTL152 + bool + + config CHERRYUSB_HOST_TEMPLATE + bool + prompt "Use usb host template" + default n + + if RT_CHERRYUSB_HOST_TEMPLATE + config TEST_USBH_CDC_ACM + int + prompt "demo for test cdc acm" + default 0 + depends on CHERRYUSB_HOST_CDC_ACM + config TEST_USBH_HID + int + prompt "demo for test hid" + default 0 + depends on CHERRYUSB_HOST_HID + endif + endif + +endif diff --git a/components/drivers/usb/cherryusb/Kconfig.cherryusb b/components/drivers/usb/cherryusb/Kconfig.cherryusb new file mode 100644 index 00000000000..1f667e733a0 --- /dev/null +++ b/components/drivers/usb/cherryusb/Kconfig.cherryusb @@ -0,0 +1,304 @@ +# Kconfig file for CherryUSB +menuconfig CHERRYUSB + bool "Using CherryUSB" + default n + +if CHERRYUSB + + menuconfig CHERRYUSB_DEVICE + bool "Enable usb device mode" + default n + + if CHERRYUSB_DEVICE + choice + prompt "Select usb device speed" + default CHERRYUSB_DEVICE_SPEED_FS + config CHERRYUSB_DEVICE_SPEED_FS + bool "FS" + config CHERRYUSB_DEVICE_SPEED_HS + bool "HS" + config CHERRYUSB_DEVICE_SPEED_AUTO + bool "AUTO" + endchoice + + choice + prompt "Select usb device ip, and some ip need config in usb_config.h, please check" + default CHERRYUSB_DEVICE_CUSTOM + config CHERRYUSB_DEVICE_CUSTOM + bool "CUSTOM (Implement it yourself)" + config CHERRYUSB_DEVICE_FSDEV + bool "fsdev" + config CHERRYUSB_DEVICE_DWC2_ST + bool "dwc2_st" + config CHERRYUSB_DEVICE_DWC2_ESP + bool "dwc2_esp" + config CHERRYUSB_DEVICE_DWC2_AT + bool "dwc2_at" + config CHERRYUSB_DEVICE_DWC2_GD + bool "dwc2_gd" + config CHERRYUSB_DEVICE_DWC2_CUSTOM + bool "dwc2_custom" + config CHERRYUSB_DEVICE_MUSB_STANDARD + bool "musb_standard" + config CHERRYUSB_DEVICE_MUSB_SUNXI + bool "musb_sunxi" + config CHERRYUSB_DEVICE_MUSB_CUSTOM + bool "musb_custom" + config CHERRYUSB_DEVICE_BL + bool "bouffalo" + config CHERRYUSB_DEVICE_HPM + bool "hpm" + config CHERRYUSB_DEVICE_AIC + bool "aic" + config CHERRYUSB_DEVICE_CH32 + bool "ch32" + config CHERRYUSB_DEVICE_PUSB2 + bool "pusb2" + endchoice + + config CHERRYUSB_DEVICE_CDC_ACM + bool + prompt "Enable usb cdc acm device" + default n + + config CHERRYUSB_DEVICE_HID + bool + prompt "Enable usb hid device" + default n + + config CHERRYUSB_DEVICE_MSC + bool + prompt "Enable usb msc device" + default n + + config CHERRYUSB_DEVICE_AUDIO + bool + prompt "Enable usb audio device" + default n + + config CHERRYUSB_DEVICE_VIDEO + bool + prompt "Enable usb video device" + default n + + config CHERRYUSB_DEVICE_CDC_RNDIS + bool + prompt "Enable usb cdc rndis device" + default n + + config CHERRYUSB_DEVICE_CDC_ECM + bool + prompt "Enable usb cdc ecm device" + default n + + config CHERRYUSB_DEVICE_CDC_NCM + bool + prompt "Enable usb cdc ncm device" + default n + + config CHERRYUSB_DEVICE_DFU + bool + prompt "Enable usb dfu device" + default n + + choice + prompt "Select usb device template" + default CHERRYUSB_DEVICE_TEMPLATE + config CHERRYUSB_DEVICE_TEMPLATE_NONE + bool "none (Implement it yourself)" + config CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM + bool "cdc_acm" + config CHERRYUSB_DEVICE_TEMPLATE_MSC + bool "msc" + config CHERRYUSB_DEVICE_TEMPLATE_HID_KEYBOARD + bool "hid_keyboard" + config CHERRYUSB_DEVICE_TEMPLATE_HID_MOUSE + bool "hid_mouse" + config CHERRYUSB_DEVICE_TEMPLATE_HID_CUSTOM + bool "hid_custom" + config CHERRYUSB_DEVICE_TEMPLATE_VIDEO + bool "video" + config CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V1_MIC_SPEAKER + bool "audio_v1_mic_speaker_multichan" + config CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V2_MIC_SPEAKER + bool "audio_v2_mic_speaker_multichan" + config CHERRYUSB_DEVICE_TEMPLATE_CDC_RNDIS + bool "cdc_rndis" + config CHERRYUSB_DEVICE_TEMPLATE_CDC_ECM + bool "cdc_ecm" + config CHERRYUSB_DEVICE_TEMPLATE_CDC_NCM + bool "cdc_ncm" + config CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC + bool "cdc_acm_msc" + config CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC_HID + bool "cdc_acm_msc_hid" + config CHERRYUSB_DEVICE_TEMPLATE_WINUSBV1 + bool "winusbv1" + config CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_CDC + bool "winusbv2_cdc" + config CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_HID + bool "winusbv2_hid" + endchoice + + endif + + menuconfig CHERRYUSB_HOST + bool "Enable usb host mode" + default n + + if CHERRYUSB_HOST + choice + prompt "Select usb host ip, and some ip need config in usb_config.h, please check" + default CHERRYUSB_HOST_CUSTOM + config CHERRYUSB_HOST_CUSTOM + bool "CUSTOM (Implement it yourself)" + config CHERRYUSB_HOST_EHCI_BL + bool "ehci_bouffalo" + config CHERRYUSB_HOST_EHCI_HPM + bool "ehci_hpm" + config CHERRYUSB_HOST_EHCI_AIC + bool "ehci_aic" + config CHERRYUSB_HOST_EHCI_NUVOTON_NUC980 + bool "ehci_nuvoton_nuc980" + config CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0 + bool "ehci_nuvoton_ma35d0" + config CHERRYUSB_HOST_EHCI_CUSTOM + bool "ehci_custom" + config CHERRYUSB_HOST_DWC2_ST + bool "dwc2_st" + config CHERRYUSB_HOST_DWC2_ESP + bool "dwc2_esp" + config CHERRYUSB_HOST_DWC2_CUSTOM + bool "dwc2_custom" + config CHERRYUSB_HOST_MUSB_STANDARD + bool "musb_standard" + config CHERRYUSB_HOST_MUSB_SUNXI + bool "musb_sunxi" + config CHERRYUSB_HOST_MUSB_CUSTOM + bool "musb_custom" + config CHERRYUSB_HOST_PUSB2 + bool "pusb2" + config CHERRYUSB_HOST_XHCI + bool "xhci" + endchoice + + config CHERRYUSB_HOST_CDC_ACM + bool + prompt "Enable usb cdc acm driver" + default n + + config CHERRYUSB_HOST_HID + bool + prompt "Enable usb hid driver" + default n + + config CHERRYUSB_HOST_MSC + bool + prompt "Enable usb msc driver" + default n + + config CHERRYUSB_HOST_CDC_ECM + bool + prompt "Enable usb cdc ecm driver" + select USBHOST_PLATFORM_CDC_ECM + default n + + config CHERRYUSB_HOST_CDC_RNDIS + bool + prompt "Enable usb rndis driver" + select USBHOST_PLATFORM_CDC_RNDIS + default n + + config CHERRYUSB_HOST_CDC_NCM + bool + prompt "Enable usb cdc ncm driver" + select USBHOST_PLATFORM_CDC_NCM + default n + + config CHERRYUSB_HOST_VIDEO + bool + prompt "Enable usb video driver, it is commercial charge" + default n + + config CHERRYUSB_HOST_AUDIO + bool + prompt "Enable usb audio driver, it is commercial charge" + default n + + config CHERRYUSB_HOST_BLUETOOTH + bool + prompt "Enable usb bluetooth driver" + default n + + config CHERRYUSB_HOST_ASIX + bool + prompt "Enable usb asix driver" + select USBHOST_PLATFORM_ASIX + default n + + config CHERRYUSB_HOST_RTL8152 + bool + prompt "Enable usb rtl8152 driver" + select USBHOST_PLATFORM_RTL8152 + default n + + config CHERRYUSB_HOST_FTDI + bool + prompt "Enable usb ftdi driver" + default n + + config CHERRYUSB_HOST_CH34X + bool + prompt "Enable usb ch34x driver" + default n + + config CHERRYUSB_HOST_CP210X + bool + prompt "Enable usb cp210x driver" + default n + + config CHERRYUSB_HOST_PL2303 + bool + prompt "Enable usb pl2303 driver" + default n + + config USBHOST_PLATFORM_CDC_ECM + bool + + config USBHOST_PLATFORM_CDC_RNDIS + bool + + config USBHOST_PLATFORM_CDC_NCM + bool + + config USBHOST_PLATFORM_ASIX + bool + + config USBHOST_PLATFORM_RTL152 + bool + + config CHERRYUSB_HOST_TEMPLATE + bool + prompt "Use usb host template" + default n + + if CHERRYUSB_HOST_TEMPLATE + config TEST_USBH_CDC_ACM + int + prompt "demo for test cdc acm" + default 0 + depends on CHERRYUSB_HOST_CDC_ACM + config TEST_USBH_HID + int + prompt "demo for test hid" + default 0 + depends on CHERRYUSB_HOST_HID + config TEST_USBH_MSC + int + prompt "demo for test msc, do not enable because it has used dfs instead" + default 0 + depends on CHERRYUSB_HOST_MSC + endif + endif + +endif diff --git a/components/drivers/usb/cherryusb/LICENSE b/components/drivers/usb/cherryusb/LICENSE new file mode 100644 index 00000000000..261eeb9e9f8 --- /dev/null +++ b/components/drivers/usb/cherryusb/LICENSE @@ -0,0 +1,201 @@ + Apache License + Version 2.0, January 2004 + http://www.apache.org/licenses/ + + TERMS AND CONDITIONS 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The object-oriented and chained approach allows the user to quickly get started with composite devices without having to worry about the underlying logic. At the same time, a standard dcd porting interface has been standardised for adapting different USB IPs to achieve ip-oriented programming. + +CherryUSB Device Stack has the following functions： + +- Support USB2.0 full and high speed, USB3.0 super speed +- Support endpoint irq callback register by users, let users do whatever they wants in endpoint irq callback. +- Support Composite Device +- Support Communication Device Class (CDC_ACM, CDC_ECM) +- Support Human Interface Device (HID) +- Support Mass Storage Class (MSC) +- Support USB VIDEO CLASS (UVC1.0、UVC1.5) +- Support USB AUDIO CLASS (UAC1.0、UAC2.0) +- Support Device Firmware Upgrade CLASS (DFU) +- Support USB MIDI CLASS (MIDI) +- Support Remote NDIS (RNDIS) +- Support WINUSB1.0、WINUSB2.0(with BOS) +- Support Vendor class +- Support multi device with the same USB IP + +CherryUSB Device Stack resource usage (GCC 10.2 with -O2): + +| file | FLASH (Byte) | No Cache RAM (Byte) | RAM (Byte) | Heap (Byte) | +|:-------------:|:--------------:|:-------------------------:|:-------------:|:----------------:| +|usbd_core.c | 3516 | 256(default) + 320 | 0 | 0 | +|usbd_cdc.c | 392 | 0 | 0 | 0 | +|usbd_msc.c | 2839 | 128 + 512(default) | 16 | 0 | +|usbd_hid.c | 364 | 0 | 0 | 0 | +|usbd_audio.c | 1455 | 0 | 0 | 0 | +|usbd_video.c | 2494 | 0 | 84 | 0 | +|usbd_rndis.c | 2109 | 3340 | 76 | 0 | + +## Host Stack Overview + +The CherryUSB Host Stack has a standard enumeration implementation for devices mounted on roothubs and external hubs, and a standard interface for different Classes to indicate what the Class driver needs to do after enumeration and after disconnection. A standard hcd porting interface has also been standardised for adapting different USB IPs for IP-oriented programming. Finally, the host stack is managed using os, and provides osal to make a adaptation for different os. + +CherryUSB Host Stack has the following functions： + +- Automatic loading of supported Class drivers +- Support blocking transfers and asynchronous transfers +- Support Composite Device +- Multi-level HUB support, expandable up to 7 levels(Testing hub with 10 ports works well,only support dwc2 and ehci now) +- Support Communication Device Class (CDC_ACM, CDC_ECM) +- Support Human Interface Device (HID) +- Support Mass Storage Class (MSC) +- Support USB Video CLASS (commercial charge) +- Support USB Audio CLASS (commercial charge) +- Support Remote NDIS (RNDIS) +- Support USB Bluetooth class (support nimble and zephyr bluetooth stack, support **CLASS:0xE0** or vendor class like cdc acm) +- Support Vendor class +- Support USB modeswitch +- Support multi host with the same USB IP + +The CherryUSB Host stack also provides the lsusb function, which allows you to view information about all mounted devices, including those on external hubs, with the help of a shell plugin. + +CherryUSB Host Stack resource usage (GCC 10.2 with -O2): + +| file | FLASH (Byte) | No Cache RAM (Byte) | RAM (Byte) | Heap (Byte) | +|:-------------:|:--------------:|:-------------------------------:|:---------------------------:|:------------:| +|usbh_core.c | ~7700 | 512 + 8 * (1+x) *n | 28 | 0 | +|usbh_hub.c | ~5600 | 32 + 4* (1+x) | 12 + sizeof(struct usbh_hub) * (1+x) | 0 | +|usbh_cdc_acm.c | ~1200 | 7 | 4 + sizeof(struct usbh_cdc_acm) * x | 0 | +|usbh_msc.c | ~2500 | 32 | 4 + sizeof(struct usbh_msc) * x | 0 | +|usbh_hid.c | ~1000 | 128 | 4 + sizeof(struct usbh_hid) * x | 0 | +|usbh_video.c | ~3700 | 128 | 4 + sizeof(struct usbh_video) * x | 0 | +|usbh_audio.c | ~3100 | 128 | 4 + sizeof(struct usbh_audio) * x | 0 | +|usbh_rndis.c | ~3900 | 4096 + 2 * 2048 | sizeof(struct usbh_rndis) * 1 | 0 | +|usbh_cdc_ecm.c | ~2500 | 2 * 1514 | sizeof(struct usbh_cdc_ecm) * 1 | 0 | +|usbh_bluetooth.c | ~2300 | 2 * 2048(default) | sizeof(struct usbh_bluetooth) * 1 | 0 | + +Among them, `sizeof(struct usbh_hub)` and `sizeof(struct usbh_hubport)` are affected by the following macros： + +``` +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 +``` + +x is affected by the following macros： + +``` +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 +``` + +## USB IP Support + +Only standard and commercial USB IP are listed. + +| IP | device | host | Support status | +|:----------------:|:----------:|:--------:|:--------------:| +| OHCI(intel) | none | OHCI | × | +| EHCI(intel) | none | EHCI | √ | +| XHCI(intel) | none | XHCI | √ | +| UHCI(intel) | none | UHCI | × | +| DWC2(synopsys) | DWC2 | DWC2 | √ | +| MUSB(mentor) | MUSB | MUSB | √ | +| FOTG210(faraday)| FOTG210 | EHCI | √ | +| CDNS2(cadence) | CDNS2 | CDNS2 | √ | +| CDNS3(cadence) | CDNS3 | XHCI | × | +| DWC3(synopsys) | DWC3 | XHCI | × | + +## Documentation Tutorial + +Quickly start, USB basic concepts, API manual, Class basic concepts and examples, see [CherryUSB Documentation Tutorial](https://cherryusb.readthedocs.io/) + +## Video Tutorial + +USB basic concepts and how the CherryUSB Device stack is implemented, see [CherryUSB Device Stack Tutorial](https://www.bilibili.com/video/BV1Ef4y1t73d). + +## Graphical Config Tool + +[chryusb_configurator](https://github.com/Egahp/chryusb_configurator) is written in **electron + vite2 + ts** framework，currently used to automate the generation of descriptor arrays, with additional functionality to be added later. + +## Demo Repo + +| Manufacturer | CHIP or Series | USB IP| Repo Url | Support version | Support status | +|:--------------------:|:------------------:|:-----:|:--------:|:------------------:|:-------------:| +|Bouffalolab | BL702/BL616/BL808 | bouffalolab/ehci|[bouffalo_sdk](https://github.com/CherryUSB/bouffalo_sdk)|<= latest | Long-term | +|ST | STM32F1x | fsdev |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term | +|ST | STM32F4/STM32H7 | dwc2 |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term | +|HPMicro | HPM6750 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/hpm_sdk)|<= latest | Long-term | +|Essemi | ES32F36xx | musb |[es32f369_repo](https://github.com/CherryUSB/cherryusb_es32)|<= latest | Long-term | +|Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|v0.10.2 | Long-term | +|artinchip | d12x/d13x/d21x | aic/ehci/ohci |[luban-lite](https://gitee.com/artinchip/luban-lite)|<= latest | Long-term | +|Espressif | esp32s2/esp32s3 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|<= latest | the same with ST | +|AllwinnerTech | F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with Essemi | +|WCH | CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2 | TBD | +|Nordicsemi | Nrf52840 | nrf5x |[nrf5x_repo](https://github.com/CherryUSB/cherryusb_nrf5x)|<= v0.10.2 | No more updated | +|Raspberry pi | rp2040 | rp2040 |[pico-examples](https://github.com/CherryUSB/pico-examples)|<= v0.10.2 | No more updated | + +## Contact + +CherryUSB discord: https://discord.com/invite/wFfvrSAey8. + +## Company Support + +Thanks to the following companies for their support (in no particular order). + + \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/README_zh.md b/components/drivers/usb/cherryusb/README_zh.md new file mode 100644 index 00000000000..a59649e0bb3 --- /dev/null +++ b/components/drivers/usb/cherryusb/README_zh.md @@ -0,0 +1,198 @@ +# CherryUSB + +[English](./README.md) + +CherryUSB 是一个小而美的、可移植性高的、用于嵌入式系统(带 USB IP)的 USB 主从协议栈。 + +![CherryUSB](CherryUSB.svg) + +## 为什么选择 + +### 易于学习 USB + +为了方便用户学习 USB 基本知识、枚举、驱动加载、IP 驱动，因此，编写的代码具备以下优点： + +- 代码精简，逻辑简单，无复杂 C 语言语法 +- 树状化编程，代码层层递进 +- Class 驱动和 porting 驱动模板化、精简化 +- API 分类清晰（从机：初始化、注册类、命令回调类、数据收发类；主机：初始化、查找类、数据收发类） + +### 易于使用 USB + +为了方便用户使用 USB 接口，考虑到用户学习过 uart 和 dma，因此，设计的数据收发类接口具备以下优点： + +- 等价于使用 uart tx dma/uart rx dma +- 收发长度没有限制，用户不需要关心 USB 分包过程（porting 驱动做分包过程） + +### 易于发挥 USB 性能 + +考虑到 USB 性能问题，尽量达到 USB 硬件理论带宽，因此，设计的数据收发类接口具备以下优点： + +- Porting 驱动直接对接寄存器，无抽象层封装 +- Memory zero copy +- IP 如果带 DMA 则使用 DMA 模式（DMA 带硬件分包功能） +- 长度无限制，方便对接硬件 DMA 并且发挥 DMA 的优势 +- 分包功能在中断中处理 + +## 目录结构 + +| 目录名 | 描述 | +|:-------------:|:-------------------------------:| +|class | usb class 类主从驱动 | +|common | usb spec 定义、常用宏、标准接口定义 | +|core | usb 主从协议栈核心实现 | +|demo | 主从 class demo | +|docs | 文档 | +|osal | os 封装层 | +|platform | 其他 os 全家桶适配 | +|port | usb 主从需要实现的 porting 接口 | +|tools | 工具链接 | + +## Device 协议栈简介 + +CherryUSB Device 协议栈对标准设备请求、CLASS 请求、VENDOR 请求以及 custom 特殊请求规范了一套统一的函数框架，采用面向对象和链表的方式，能够使得用户快速上手复合设备，不用管底层的逻辑。同时，规范了一套标准的 dcd porting 接口，用于适配不同的 USB IP，达到面向 ip 编程。 + +CherryUSB Device 协议栈当前实现以下功能： + +- 支持 USB2.0 全速和高速设备，USB3.0 超速设备 +- 支持端点中断注册功能，porting 给用户自己处理中断里的数据 +- 支持复合设备 +- 支持 Communication Device Class (CDC_ACM, CDC_ECM) +- 支持 Human Interface Device (HID) +- 支持 Mass Storage Class (MSC) +- 支持 USB VIDEO CLASS (UVC1.0、UVC1.5) +- 支持 USB AUDIO CLASS (UAC1.0、UAC2.0) +- 支持 Device Firmware Upgrade CLASS (DFU) +- 支持 USB MIDI CLASS (MIDI) +- 支持 Remote NDIS (RNDIS) +- 支持 WINUSB1.0、WINUSB2.0(带 BOS ) +- 支持 Vendor 类 class +- 支持相同 USB IP 的多从机 + +CherryUSB Device 协议栈资源占用说明（GCC 10.2 with -O2）： + +| file | FLASH (Byte) | No Cache RAM (Byte) | RAM (Byte) | Heap (Byte) | +|:-------------:|:--------------:|:-------------------------:|:-------------:|:----------------:| +|usbd_core.c | 3516 | 256(default) + 320 | 0 | 0 | +|usbd_cdc.c | 392 | 0 | 0 | 0 | +|usbd_msc.c | 2839 | 128 + 512(default) | 16 | 0 | +|usbd_hid.c | 364 | 0 | 0 | 0 | +|usbd_audio.c | 1455 | 0 | 0 | 0 | +|usbd_video.c | 2494 | 0 | 84 | 0 | +|usbd_rndis.c | 2109 | 3340 | 76 | 0 | + +## Host 协议栈简介 + +CherryUSB Host 协议栈对挂载在 roothub、外部 hub 上的设备规范了一套标准的枚举实现，对不同的 Class 类也规范了一套标准接口，用来指示在枚举后和断开连接后该 Class 驱动需要做的事情。同时，规范了一套标准的 hcd porting 接口，用于适配不同的 USB IP，达到面向 IP 编程。最后，协议栈使用 OS 管理，并提供了 osal 用来适配不同的 os。 + +CherryUSB Host 协议栈当前实现以下功能： + +- 自动加载支持的Class 驱动 +- 支持阻塞式传输和异步传输 +- 支持复合设备 +- 支持多级 HUB,最高可拓展到 7 级(目前测试 1拖 10 没有问题，当前仅支持 dwc2 和 ehci) +- 支持 Communication Device Class (CDC_ACM, CDC_ECM) +- 支持 Human Interface Device (HID) +- 支持 Mass Storage Class (MSC) +- Support USB Video CLASS（商业收费） +- Support USB Audio CLASS（商业收费） +- 支持 Remote NDIS (RNDIS) +- 支持 USB Bluetooth (支持 nimble and zephyr bluetooth 协议栈，支持 **CLASS: 0xE0** 或者厂家自定义类，类似于 cdc acm 功能) +- 支持 Vendor 类 class +- 支持 USB modeswitch +- 支持相同 USB IP 的多主机 + +同时，CherryUSB Host 协议栈还提供了 lsusb 的功能，借助 shell 插件可以查看所有挂载设备的信息，包括外部 hub 上的设备的信息。 + +CherryUSB Host 协议栈资源占用说明（GCC 10.2 with -O2）： + +| file | FLASH (Byte) | No Cache RAM (Byte) | RAM (Byte) | Heap (Byte) | +|:-------------:|:--------------:|:-------------------------------:|:---------------------------:|:------------:| +|usbh_core.c | ~7700 | 512 + 8 * (1+x) *n | 28 | 0 | +|usbh_hub.c | ~5600 | 32 + 4* (1+x) | 12 + sizeof(struct usbh_hub) * (1+x) | 0 | +|usbh_cdc_acm.c | ~1200 | 7 | 4 + sizeof(struct usbh_cdc_acm) * x | 0 | +|usbh_msc.c | ~2500 | 32 | 4 + sizeof(struct usbh_msc) * x | 0 | +|usbh_hid.c | ~1000 | 128 | 4 + sizeof(struct usbh_hid) * x | 0 | +|usbh_video.c | ~3700 | 128 | 4 + sizeof(struct usbh_video) * x | 0 | +|usbh_audio.c | ~3100 | 128 | 4 + sizeof(struct usbh_audio) * x | 0 | +|usbh_rndis.c | ~3900 | 4096 + 2 * 2048 | sizeof(struct usbh_rndis) * 1 | 0 | +|usbh_cdc_ecm.c | ~2500 | 2 * 1514 | sizeof(struct usbh_cdc_ecm) * 1 | 0 | +|usbh_bluetooth.c | ~2300 | 2 * 2048(default) | sizeof(struct usbh_bluetooth) * 1 | 0 | + +其中，`sizeof(struct usbh_hub)` 和 `sizeof(struct usbh_hubport)` 受以下宏影响： + +``` +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 +``` + +x 受以下宏影响： + +``` +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 +``` + +## USB IP 支持情况 + +仅列举标准 USB IP 和商业性 USB IP + +| IP | device | host | Support status | +|:----------------:|:----------:|:--------:|:--------------:| +| OHCI(intel) | none | OHCI | × | +| EHCI(intel) | none | EHCI | √ | +| XHCI(intel) | none | XHCI | √ | +| UHCI(intel) | none | UHCI | × | +| DWC2(synopsys) | DWC2 | DWC2 | √ | +| MUSB(mentor) | MUSB | MUSB | √ | +| FOTG210(faraday)| FOTG210 | EHCI | √ | +| CDNS2(cadence) | CDNS2 | CDNS2 | √ | +| CDNS3(cadence) | CDNS3 | XHCI | × | +| DWC3(synopsys) | DWC3 | XHCI | × | + +## 文档教程 + +CherryUSB 快速入门、USB 基本概念，API 手册，Class 基本概念和例程，参考 [CherryUSB Documentation Tutorial](https://cherryusb.readthedocs.io/) + +## 视频教程 + +- USB 基本知识点与 CherryUSB Device 协议栈是如何编写的（使用v0.4.1 版本），参考 https://www.bilibili.com/video/BV1Ef4y1t73d. +- CherryUSB 腾讯会议（使用v1.1.0 版本），参考 https://www.bilibili.com/video/BV16x421y7mM. + +## 图形化界面配置工具 + +[chryusb_configurator](https://github.com/Egahp/chryusb_configurator) 采用 **electron + vite2 + ts** 框架编写，当前用于自动化生成描述符数组，后续会增加其他功能。 + +## 示例仓库 + +| Manufacturer | CHIP or Series | USB IP| Repo Url | Support version | Support status | +|:--------------------:|:------------------:|:-----:|:--------:|:------------------:|:-------------:| +|Bouffalolab | BL702/BL616/BL808 | bouffalolab/ehci|[bouffalo_sdk](https://github.com/CherryUSB/bouffalo_sdk)|<= latest | Long-term | +|ST | STM32F1x | fsdev |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term | +|ST | STM32F4/STM32H7 | dwc2 |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term | +|HPMicro | HPM6750 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/hpm_sdk)|<= latest | Long-term | +|Essemi | ES32F36xx | musb |[es32f369_repo](https://github.com/CherryUSB/cherryusb_es32)|<= latest | Long-term | +|Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|v0.10.2 | Long-term | +|artinchip | d12x/d13x/d21x | aic/ehci/ohci |[luban-lite](https://gitee.com/artinchip/luban-lite)|<= latest | Long-term | +|Espressif | esp32s2/esp32s3 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|<= latest | the same with ST | +|AllwinnerTech | F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with Essemi | +|WCH | CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2 | TBD | +|Nordicsemi | Nrf52840 | nrf5x |[nrf5x_repo](https://github.com/CherryUSB/cherryusb_nrf5x)|<= v0.10.2 | No more updated | +|Raspberry pi | rp2040 | rp2040 |[pico-examples](https://github.com/CherryUSB/pico-examples)|<= v0.10.2 | No more updated | + +## Contact + +CherryUSB QQ 群:642693751 +CherryUSB 微信群：与我联系后邀请加入 + +## 支持企业 + +感谢以下企业支持（顺序不分先后）。 + + diff --git a/components/drivers/usb/cherryusb/SConscript b/components/drivers/usb/cherryusb/SConscript new file mode 100644 index 00000000000..1bdb16d503c --- /dev/null +++ b/components/drivers/usb/cherryusb/SConscript @@ -0,0 +1,210 @@ +from building import * + +cwd = GetCurrentDir() +path = [cwd + '/common'] +path += [cwd + '/core'] +path += [cwd + '/class/cdc'] +path += [cwd + '/class/msc'] +path += [cwd + '/class/hid'] +path += [cwd + '/class/audio'] +path += [cwd + '/class/video'] +path += [cwd + '/class/wireless'] +path += [cwd + '/class/dfu'] +path += [cwd + '/class/midi'] +path += [cwd + '/class/vendor/net'] +path += [cwd + '/class/vendor/serial'] +src = [] + +CPPDEFINES = [] + +# USB DEVICE +if GetDepend(['RT_CHERRYUSB_DEVICE']): + path += [cwd + '/osal'] + src += Glob('core/usbd_core.c') + src += Glob('osal/usb_osal_rtthread.c') + + if GetDepend(['RT_CHERRYUSB_DEVICE_SPEED_HS']): + CPPDEFINES+=['CONFIG_USB_HS'] + + if GetDepend(['RT_CHERRYUSB_DEVICE_FSDEV']): + src += Glob('port/fsdev/usb_dc_fsdev.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_ST']): + src += Glob('port/dwc2/usb_dc_dwc2.c') + src += Glob('port/dwc2/usb_glue_st.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_ESP']): + src += Glob('port/dwc2/usb_dc_dwc2.c') + src += Glob('port/dwc2/usb_glue_esp.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_AT']): + src += Glob('port/dwc2/usb_dc_dwc2.c') + src += Glob('port/dwc2/usb_glue_at.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_GD']): + src += Glob('port/dwc2/usb_dc_dwc2.c') + src += Glob('port/dwc2/usb_glue_gd.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_DWC2_CUSTOM']): + src += Glob('port/dwc2/usb_dc_dwc2.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_MUSB_STANDARD']): + src += Glob('port/musb/usb_dc_musb.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_MUSB_SUNXI']): + src += Glob('port/musb/usb_dc_musb.c') + src += Glob('port/musb/usb_glue_sunxi.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_MUSB_CUSTOM']): + src += Glob('port/musb/usb_dc_musb.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_BL']): + src += Glob('port/bouffalolab/usb_dc_bl.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_HPM']): + src += Glob('port/hpm/usb_dc_hpm.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_AIC']): + src += Glob('port/aic/usb_dc_aic.c') + src += Glob('port/aic/usb_dc_aic_ll.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_CH32']): + if GetDepend(['RT_CHERRYUSB_DEVICE_SPEED_HS']): + src += Glob('port/ch32/usb_dc_usbhs.c') + else: + src += Glob('port/ch32/usb_dc_usbfs.c') + + if GetDepend(['RT_CHERRYUSB_DEVICE_CDC_ACM']): + src += Glob('class/cdc/usbd_cdc.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_HID']): + src += Glob('class/hid/usbd_hid.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_MSC']): + src += Glob('class/msc/usbd_msc.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_AUDIO']): + src += Glob('class/audio/usbd_audio.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_VIDEO']): + src += Glob('class/video/usbd_video.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_CDC_RNDIS']): + src += Glob('class/wireless/usbd_rndis.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_CDC_ECM']): + src += Glob('class/cdc/usbd_cdc_ecm.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_CDC_NCM']): + src += Glob('class/cdc/usbd_cdc_ncm.c') + if GetDepend(['RT_CHERRYUSB_USING_DFU']): + src += Glob('class/dfu/usbd_dfu.c') + + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM']): + src += Glob('demo/cdc_acm_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_MSC']): + src += Glob('demo/msc_ram_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_HID_MOUSE']): + src += Glob('demo/hid_mouse_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_HID_KEYBOARD']): + src += Glob('demo/hid_keyboard_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_HID_CUSTOM']): + src += Glob('demo/hid_custom_inout_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_VIDEO']): + src += Glob('demo/video_static_mjpeg_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V1_MIC_SPEAKER']): + src += Glob('demo/audio_v1_mic_speaker_multichan_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_AUDIO_V2_MIC_SPEAKER']): + src += Glob('demo/audio_v2_mic_speaker_multichan_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_RNDIS']): + src += Glob('demo/cdc_rndis_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ECM']): + src += Glob('demo/cdc_ecm_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_NCM']): + src += Glob('demo/cdc_ncm_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC']): + src += Glob('demo/cdc_acm_msc_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM_MSC_HID']): + src += Glob('demo/cdc_acm_hid_msc_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV1']): + src += Glob('demo/winusb1.0_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_CDC']): + src += Glob('demo/winusb2.0_cdc_template.c') + if GetDepend(['RT_CHERRYUSB_DEVICE_TEMPLATE_WINUSBV2_HID']): + src += Glob('demo/winusb2.0_hid_template.c') + +# USB HOST +if GetDepend(['RT_CHERRYUSB_HOST']): + path += [cwd + '/class/hub'] + src += Glob('core/usbh_core.c') + src += Glob('class/hub/usbh_hub.c') + src += Glob('osal/usb_osal_rtthread.c') + + if GetDepend(['RT_CHERRYUSB_HOST_EHCI_BL']): + src += Glob('port/ehci/usb_hc_ehci.c') + src += Glob('port/ehci/usb_glue_bouffalo.c') + if GetDepend(['RT_CHERRYUSB_HOST_EHCI_HPM']): + src += Glob('port/ehci/usb_hc_ehci.c') + src += Glob('port/ehci/usb_glue_hpm.c') + if GetDepend(['RT_CHERRYUSB_HOST_EHCI_AIC']): + path += [cwd + '/port/ehci'] + path += [cwd + '/port/ohci'] + src += Glob('port/ehci/usb_hc_ehci.c') + src += Glob('port/ehci/usb_glue_aic.c') + src += Glob('port/ohci/usb_hc_ohci.c') + if GetDepend(['RT_CHERRYUSB_HOST_EHCI_NUVOTON_NUC980']): + src += Glob('port/ehci/usb_hc_ehci.c') + src += Glob('port/ehci/usb_glue_nuc980.c') + if GetDepend(['RT_CHERRYUSB_HOST_EHCI_NUVOTON_MA35D0']): + src += Glob('port/ehci/usb_hc_ehci.c') + src += Glob('port/ehci/usb_glue_ma35d0.c') + if GetDepend(['RT_CHERRYUSB_HOST_EHCI_CUSTOM']): + src += Glob('port/ehci/usb_hc_ehci.c') + if GetDepend(['RT_CHERRYUSB_HOST_DWC2_ST']): + src += Glob('port/dwc2/usb_hc_dwc2.c') + src += Glob('port/dwc2/usb_glue_st.c') + if GetDepend(['RT_CHERRYUSB_HOST_DWC2_ESP']): + src += Glob('port/dwc2/usb_hc_dwc2.c') + src += Glob('port/dwc2/usb_glue_esp.c') + if GetDepend(['RT_CHERRYUSB_HOST_DWC2_CUSTOM']): + src += Glob('port/dwc2/usb_hc_dwc2.c') + if GetDepend(['RT_CHERRYUSB_HOST_MUSB_STANDARD']): + src += Glob('port/musb/usb_hc_musb.c') + if GetDepend(['RT_CHERRYUSB_HOST_MUSB_SUNXI']): + src += Glob('port/musb/usb_hc_musb.c') + src += Glob('port/musb/usb_glue_sunxi.c') + if GetDepend(['RT_CHERRYUSB_HOST_MUSB_CUSTOM']): + src += Glob('port/musb/usb_hc_musb.c') + + if GetDepend(['RT_CHERRYUSB_HOST_CDC_ACM']): + src += Glob('class/cdc/usbh_cdc_acm.c') + if GetDepend(['RT_CHERRYUSB_HOST_HID']): + src += Glob('class/hid/usbh_hid.c') + if GetDepend(['RT_CHERRYUSB_HOST_MSC']): + src += Glob('class/msc/usbh_msc.c') + if GetDepend(['RT_CHERRYUSB_HOST_CDC_RNDIS']): + src += Glob('class/wireless/usbh_rndis.c') + if GetDepend(['RT_CHERRYUSB_HOST_CDC_ECM']): + src += Glob('class/cdc/usbh_cdc_ecm.c') + if GetDepend(['RT_CHERRYUSB_HOST_CDC_NCM']): + src += Glob('class/cdc/usbh_cdc_ncm.c') + if GetDepend(['RT_CHERRYUSB_HOST_VIDEO']): + src += Glob('class/video/usbh_video.c') + if GetDepend(['RT_CHERRYUSB_HOST_AUDIO']): + src += Glob('class/audio/usbh_audio.c') + if GetDepend(['RT_CHERRYUSB_HOST_BLUETOOTH']): + src += Glob('class/wireless/usbh_bluetooth.c') + if GetDepend(['RT_CHERRYUSB_HOST_ASIX']): + src += Glob('class/vendor/net/usbh_asix.c') + if GetDepend(['RT_CHERRYUSB_HOST_RTL8152']): + src += Glob('class/vendor/net/usbh_rtl8152.c') + if GetDepend(['RT_CHERRYUSB_HOST_FTDI']): + src += Glob('class/vendor/serial/usbh_ftdi.c') + if GetDepend(['RT_CHERRYUSB_HOST_CH34X']): + src += Glob('class/vendor/serial/usbh_ch34x.c') + if GetDepend(['RT_CHERRYUSB_HOST_CP210X']): + src += Glob('class/vendor/serial/usbh_cp210x.c') + if GetDepend(['RT_CHERRYUSB_HOST_PL2303']): + src += Glob('class/vendor/serial/usbh_pl2303.c') + + if GetDepend(['RT_CHERRYUSB_HOST_TEMPLATE']): + src += Glob('demo/usb_host.c') + + if GetDepend('RT_USING_DFS') and GetDepend(['RT_CHERRYUSB_HOST_MSC']): + src += Glob('platform/rtthread/usbh_dfs.c') + + if GetDepend('RT_CHERRYUSB_HOST_CDC_ECM') \ + or GetDepend('RT_CHERRYUSB_HOST_CDC_RNDIS') \ + or GetDepend('RT_CHERRYUSB_HOST_CDC_NCM') \ + or GetDepend('RT_CHERRYUSB_HOST_CDC_ASIX') \ + or GetDepend('RT_CHERRYUSB_HOST_CDC_RTL8152'): + src += Glob('platform/rtthread/usbh_lwip.c') + +src += Glob('platform/rtthread/usb_msh.c') +src += Glob('platform/rtthread/usb_check.c') + +group = DefineGroup('CherryUSB', src, depend = ['RT_USING_CHERRYUSB'], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') + diff --git a/components/drivers/usb/cherryusb/VERSION b/components/drivers/usb/cherryusb/VERSION new file mode 100644 index 00000000000..f976d5d979e --- /dev/null +++ b/components/drivers/usb/cherryusb/VERSION @@ -0,0 +1,5 @@ +VERSION_MAJOR = 1 +VERSION_MINOR = 3 +PATCHLEVEL = 0 +VERSION_TWEAK = 0 +EXTRAVERSION = 0 diff --git a/components/drivers/usb/cherryusb/cherryusb.cmake b/components/drivers/usb/cherryusb/cherryusb.cmake new file mode 100644 index 00000000000..6a78e9dc476 --- /dev/null +++ b/components/drivers/usb/cherryusb/cherryusb.cmake @@ -0,0 +1,241 @@ +# +# Copyright (c) 2024, sakumisu +# +# SPDX-License-Identifier: Apache-2.0 +# + +# set(CONFIG_CHERRYUSB_DEVICE 1) +# set(CONFIG_CHERRYUSB_DEVICE_CDC 1) +# set(CONFIG_CHERRYUSB_DEVICE_HID 1) +# set(CONFIG_CHERRYUSB_DEVICE_MSC 1) +# set(CONFIG_CHERRYUSB_DEVICE_DCD "dwc2_st") + +# set(CONFIG_CHERRYUSB_HOST 1) +# set(CONFIG_CHERRYUSB_HOST_CDC_ACM 1) +# set(CONFIG_CHERRYUSB_HOST_CDC_ECM 1) +# set(CONFIG_CHERRYUSB_HOST_CDC_NCM 1) +# set(CONFIG_CHERRYUSB_HOST_HID 1) +# set(CONFIG_CHERRYUSB_HOST_MSC 1) +# set(CONFIG_CHERRYUSB_HOST_VIDEO 1) +# set(CONFIG_CHERRYUSB_HOST_AUDIO 1) +# set(CONFIG_CHERRYUSB_HOST_CDC_RNDIS 1) +# set(CONFIG_CHERRYUSB_HOST_BLUETOOTH 1) +# set(CONFIG_CHERRYUSB_HOST_ASIX 1) +# set(CONFIG_CHERRYUSB_HOST_RTL8152 1) +# set(CONFIG_CHERRYUSB_OSAL "freertos") +# set(CONFIG_CHERRYUSB_HOST_HCD "ehci_xxx") + +list(APPEND cherryusb_incs +${CMAKE_CURRENT_LIST_DIR}/common +${CMAKE_CURRENT_LIST_DIR}/core +${CMAKE_CURRENT_LIST_DIR}/class/hub +${CMAKE_CURRENT_LIST_DIR}/class/cdc +${CMAKE_CURRENT_LIST_DIR}/class/hid +${CMAKE_CURRENT_LIST_DIR}/class/msc +${CMAKE_CURRENT_LIST_DIR}/class/audio +${CMAKE_CURRENT_LIST_DIR}/class/video +${CMAKE_CURRENT_LIST_DIR}/class/wireless +${CMAKE_CURRENT_LIST_DIR}/class/midi +${CMAKE_CURRENT_LIST_DIR}/class/vendor/net +${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial +) + +if(CONFIG_CHERRYUSB_DEVICE) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/core/usbd_core.c) + if(CONFIG_CHERRYUSB_DEVICE_CDC) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbd_cdc.c) + endif() + if(CONFIG_CHERRYUSB_DEVICE_HID) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/hid/usbd_hid.c) + endif() + if(CONFIG_CHERRYUSB_DEVICE_MSC) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/msc/usbd_msc.c) + endif() + if(CONFIG_CHERRYUSB_DEVICE_AUDIO) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/audio/usbd_audio.c) + endif() + if(CONFIG_CHERRYUSB_DEVICE_VIDEO) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/video/usbd_video.c) + endif() + if(CONFIG_CHERRYUSB_DEVICE_CDC_ECM) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbd_cdc_ecm.c) + endif() + if(CONFIG_CHERRYUSB_DEVICE_CDC_NCM) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbd_cdc_ncm.c) + endif() + if(CONFIG_CHERRYUSB_DEVICE_CDC_RNDIS) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/wireless/usbd_rndis.c) + endif() + if(CONFIG_CHERRYUSB_DEVICE_DFU) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/dfu/usbd_dfu.c) + endif() + + if(DEFINED CONFIG_CHERRYUSB_DEVICE_DCD) + if("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_st") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_dc_dwc2.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_st.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_esp") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_dc_dwc2.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_esp.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_aic") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_dc_dwc2.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_aic.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "dwc2_at") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_dc_dwc2.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_at.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "fsdev") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/fsdev/usb_dc_fsdev.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "hpm") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/hpm/usb_dc_hpm.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "bl") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/bouffalolab/usb_dc_bl.c) + elseif("${CONFIG_CHERRYUSB_DEVICE_DCD}" STREQUAL "musb") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_dc_musb.c) + endif() + endif() + +endif() + +if(CONFIG_CHERRYUSB_HOST) + list(APPEND cherryusb_srcs + ${CMAKE_CURRENT_LIST_DIR}/core/usbh_core.c + ${CMAKE_CURRENT_LIST_DIR}/class/hub/usbh_hub.c + ) + + if(CONFIG_CHERRYUSB_HOST_CDC_ACM) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbh_cdc_acm.c) + endif() + if(CONFIG_CHERRYUSB_HOST_CDC_ECM) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbh_cdc_ecm.c) + endif() + if(CONFIG_CHERRYUSB_HOST_CDC_NCM) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/cdc/usbh_cdc_ncm.c) + endif() + if(CONFIG_CHERRYUSB_HOST_HID) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/hid/usbh_hid.c) + endif() + if(CONFIG_CHERRYUSB_HOST_MSC) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/msc/usbh_msc.c) + + if(CONFIG_CHERRYUSB_HOST_MSC_FATFS) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/fatfs-0.14/source/port/fatfs_usbh.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/fatfs-0.14/source/diskio.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/fatfs-0.14/source/ff.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/fatfs-0.14/source/ffsystem.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/fatfs-0.14/source/ffunicode.c) + + list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/third_party/fatfs-0.14/source) + endif() + endif() + if(CONFIG_CHERRYUSB_HOST_VIDEO) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/video/usbh_video.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherryrb/chry_ringbuffer.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherrypool/chry_pool.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherrypool/usbh_uvc_queue.c) + list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherryrb) + list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/third_party/cherrypool) + endif() + if(CONFIG_CHERRYUSB_HOST_AUDIO) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/audio/usbh_audio.c) + endif() + if(CONFIG_CHERRYUSB_HOST_CDC_RNDIS) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/wireless/usbh_rndis.c) + endif() + if(CONFIG_CHERRYUSB_HOST_BLUETOOTH) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/wireless/usbh_bluetooth.c) + + set(BLUETOOTH_PATH ${CMAKE_CURRENT_LIST_DIR}/third_party/zephyr_bluetooth-2.7.5) + + list(APPEND cherryusb_srcs + ${BLUETOOTH_PATH}/ble_hci_usbh.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/beacon/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/central/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/central_hr/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/central_ht/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/central_multilink/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/central_multilink/src/central_multilink.c + # ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/handsfree/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/ibeacon/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral/src/cts.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_csc/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_dis/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_esp/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_hids/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_hids/src/hog.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_hr/src/main.c + # ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_ht/src/main.c + # ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_ht/src/hts.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_identity/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_identity/src/peripheral_identity.c + # ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_ots/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/peripheral_sc_only/src/main.c + ${BLUETOOTH_PATH}/zephyr_bluetooth/examples/scan_adv/src/main.c + ) + + include(${BLUETOOTH_PATH}/zephyr_bluetooth/zephyr_bluetooth.cmake) + list(APPEND cherryusb_srcs ${zephyr_bluetooth_srcs}) + list(APPEND cherryusb_incs ${zephyr_bluetooth_incs}) + endif() + + if(CONFIG_CHERRYUSB_HOST_ASIX) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/net/usbh_asix.c) + endif() + if(CONFIG_CHERRYUSB_HOST_RTL8152) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/net/usbh_rtl8152.c) + endif() + if(CONFIG_CHERRYUSB_HOST_CH34X) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial/usbh_ch34x.c) + endif() + if(CONFIG_CHERRYUSB_HOST_CP210X) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial/usbh_cp210x.c) + endif() + if(CONFIG_CHERRYUSB_HOST_FTDI) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial/usbh_ftdi.c) + endif() + if(CONFIG_CHERRYUSB_HOST_PL2303) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/class/vendor/serial/usbh_pl2303.c) + endif() + + if(DEFINED CONFIG_CHERRYUSB_HOST_HCD) + if("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "ehci_bouffalo") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci.c) + #list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci_iso.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_glue_bouffalo.c) + list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/port/ehci) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "ehci_hpm") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci.c) + #list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci_iso.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_glue_hpm.c) + list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/port/ehci) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "ehci_aic") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci.c) + #list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci_iso.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_glue_aic.c) + list(APPEND cherryusb_incs ${CMAKE_CURRENT_LIST_DIR}/port/ehci) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "ehci_nuvoton") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci.c) + #list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_hc_ehci_iso.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/ehci/usb_glue_nuvoton.c) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "dwc2_st") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_hc_dwc2.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_st.c) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "dwc2_esp") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_hc_dwc2.c) + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/dwc2/usb_glue_esp.c) + elseif("${CONFIG_CHERRYUSB_HOST_HCD}" STREQUAL "musb") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/port/musb/usb_hc_musb.c) + endif() + endif() + +endif() + +if(DEFINED CONFIG_CHERRYUSB_OSAL) + if("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "freertos") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/usb_osal_freertos.c) + elseif("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "rtthread") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/usb_osal_rtthread.c) + elseif("${CONFIG_CHERRYUSB_OSAL}" STREQUAL "yoc") + list(APPEND cherryusb_srcs ${CMAKE_CURRENT_LIST_DIR}/osal/usb_osal_yoc.c) + endif() +endif() \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/cherryusb_config_template.h b/components/drivers/usb/cherryusb/cherryusb_config_template.h new file mode 100644 index 00000000000..cba9fc4dbfd --- /dev/null +++ b/components/drivers/usb/cherryusb/cherryusb_config_template.h @@ -0,0 +1,261 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +#define CHERRYUSB_VERSION 0x010300 +#define CHERRYUSB_VERSION_STR "v1.3.0" + +/* ================ USB common Configuration ================ */ + +#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) + +#define usb_malloc(size) malloc(size) +#define usb_free(ptr) free(ptr) + +#ifndef CONFIG_USB_DBG_LEVEL +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +/* data align size when use dma */ +#ifndef CONFIG_USB_ALIGN_SIZE +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Setup packet log for debug */ +// #define CONFIG_USBDEV_SETUP_LOG_PRINT + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +/* ---------------- FSDEV Configuration ---------------- */ +//#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2 // maybe 1 or 2, many chips may have a difference + +/* ---------------- DWC2 Configuration ---------------- */ +// #define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) +// #define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +// #define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) +// #define CONFIG_USB_DWC2_TX4_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX5_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) +// #define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +/* ---------------- EHCI Configuration ---------------- */ + +#define CONFIG_USB_EHCI_HCCR_OFFSET (0x0) +#define CONFIG_USB_EHCI_FRAME_LIST_SIZE 1024 +#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USB_EHCI_QTD_NUM 3 +#define CONFIG_USB_EHCI_ITD_NUM 20 +// #define CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE +// #define CONFIG_USB_EHCI_CONFIGFLAG +// #define CONFIG_USB_EHCI_ISO +// #define CONFIG_USB_EHCI_WITH_OHCI + +/* ---------------- OHCI Configuration ---------------- */ +#define CONFIG_USB_OHCI_HCOR_OFFSET (0x0) + +/* ---------------- XHCI Configuration ---------------- */ +#define CONFIG_USB_XHCI_HCCR_OFFSET (0x0) + +/* ---------------- DWC2 Configuration ---------------- */ +/* largest non-periodic USB packet used / 4 */ +// #define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4) +/* largest periodic USB packet used / 4 */ +// #define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4) +/* + * (largest USB packet used / 4) + 1 for status information + 1 transfer complete + + * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario + */ +// #define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4) + +/* ---------------- MUSB Configuration ---------------- */ +// #define CONFIG_USB_MUSB_SUNXI + +#endif diff --git a/components/drivers/usb/cherryusb/class/audio/usb_audio.h b/components/drivers/usb/cherryusb/class/audio/usb_audio.h new file mode 100644 index 00000000000..2b3cdaffa8a --- /dev/null +++ b/components/drivers/usb/cherryusb/class/audio/usb_audio.h @@ -0,0 +1,1165 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_AUDIO_H +#define USB_AUDIO_H + +/** Audio Interface Subclass Codes + * Refer to Table A-2 from audio10.pdf + */ +#define AUDIO_SUBCLASS_UNDEFINED 0x00 +#define AUDIO_SUBCLASS_AUDIOCONTROL 0x01 +#define AUDIO_SUBCLASS_AUDIOSTREAMING 0x02 +#define AUDIO_SUBCLASS_MIDISTREAMING 0x03 + +#define AUDIO_PROTOCOL_UNDEFINED 0x00 +#define AUDIO_PROTOCOLv20 0x20 /* IP version 2.0 */ + +/** Audio Class-Specific Request Codes + * Refer to Table A-9 from audio10.pdf + */ +#define AUDIO_REQUEST_UNDEFINED 0x00 +#define AUDIO_REQUEST_SET_CUR 0x01 +#define AUDIO_REQUEST_GET_CUR 0x81 +#define AUDIO_REQUEST_SET_MIN 0x02 +#define AUDIO_REQUEST_GET_MIN 0x82 +#define AUDIO_REQUEST_SET_MAX 0x03 +#define AUDIO_REQUEST_GET_MAX 0x83 +#define AUDIO_REQUEST_SET_RES 0x04 +#define AUDIO_REQUEST_GET_RES 0x84 +#define AUDIO_REQUEST_SET_MEM 0x05 +#define AUDIO_REQUEST_GET_MEM 0x85 +#define AUDIO_REQUEST_GET_STAT 0xFF + +/** Audio Class-Specific Request Codes + * Refer from audio20_final.pdf + */ +#define AUDIO_REQUEST_CUR 0x01 +#define AUDIO_REQUEST_RANGE 0x02 +/** Audio Class-Specific Control Interface Descriptor Subtypes + * Refer to Table A-5 from audio10.pdf + */ +#define AUDIO_CONTROL_UNDEF 0x01U +#define AUDIO_CONTROL_HEADER 0x01U +#define AUDIO_CONTROL_INPUT_TERMINAL 0x02U +#define AUDIO_CONTROL_OUTPUT_TERMINAL 0x03U +#define AUDIO_CONTROL_MIXER_UNIT 0x04U +#define AUDIO_CONTROL_SELECTOR_UNIT 0x05U +#define AUDIO_CONTROL_FEATURE_UNIT 0x06U +#define AUDIO_CONTROL_EFFECT_UNIT 0x07U +#define AUDIO_CONTROL_PROCESSING_UNIT 0x08U +#define AUDIO_CONTROL_EXTENSION_UNIT 0x09U +#define AUDIO_CONTROL_CLOCK_SOURCE 0x0aU +#define AUDIO_CONTROL_CLOCK_SELECTOR 0x0bU +#define AUDIO_CONTROL_CLOCK_MULTIPLIER 0x0cU +#define AUDIO_CONTROL_SAMPLERATE_CONVERTER 0x0dU + +/** Audio Class-Specific AS Interface Descriptor Subtypes + * Refer to Table A-6 from audio10.pdf + */ +#define AUDIO_STREAMING_UNDEFINED 0x00U +#define AUDIO_STREAMING_GENERAL 0x01U +#define AUDIO_STREAMING_FORMAT_TYPE 0x02U +#define AUDIO_STREAMING_ENCODER 0x03U +#define AUDIO_STREAMING_DECODER 0x04U + +/* Clock Source Descriptor Clock Types */ +#define AUDIO_CLKSRC_EXTERNAL 0x00 /* External clock */ +#define AUDIO_CLKSRC_INTERNAL_FIXED 0x01 /* Internal fixed clock */ +#define AUDIO_CLKSRC_INTERNAL_VAR 0x02 /* Internal variable clock */ +#define AUDIO_CLKSRC_INTERNAL_PROG 0x03 /* Internal programmable clock */ + +/* Effect Unit Effect Types */ +#define AUDIO_EFFECT_UNDEF 0x00 +#define AUDIO_EFFECT_PARAM_EQ_SECTION 0x01 +#define AUDIO_EFFECT_REVERBERATION 0x02 +#define AUDIO_EFFECT_MOD_DELAY 0x03 +#define AUDIO_EFFECT_DYN_RANGE_COMP 0x04 + +/* Processing Unit Process Types */ +#define AUDIO_PROCESS_UNDEFINED 0x00 +#define AUDIO_PROCESS_UPDOWNMIX 0x01 +#define AUDIO_PROCESS_DOLBY_PROLOGIC 0x02 +#define AUDIO_PROCESS_STEREO_EXTENDER 0x03 + +/* Audio Class-Specific Endpoint Descriptor Subtypes */ +#define AUDIO_ENDPOINT_UNDEFINED 0x00U +#define AUDIO_ENDPOINT_GENERAL 0x01U + +/* Feature Unit Control Bits */ +#define AUDIO_CONTROL_MUTE 0x0001 +#define AUDIO_CONTROL_VOLUME 0x0002 +#define AUDIO_CONTROL_BASS 0x0004 +#define AUDIO_CONTROL_MID 0x0008 +#define AUDIO_CONTROL_TREBLE 0x0010 +#define AUDIO_CONTROL_GRAPHIC_EQUALIZER 0x0020 +#define AUDIO_CONTROL_AUTOMATIC_GAIN 0x0040 +#define AUDIO_CONTROL_DEALY 0x0080 +#define AUDIO_CONTROL_BASS_BOOST 0x0100 +#define AUDIO_CONTROL_LOUDNESS 0x0200 + +/* Encoder Type Codes */ +#define AUDIO_ENCODER_UNDEF 0x00 +#define AUDIO_ENCODER_OTHER 0x01 +#define AUDIO_ENCODER_MPEG 0x02 +#define AUDIO_ENCODER_AC3 0x03 +#define AUDIO_ENCODER_WMA 0x04 +#define AUDIO_ENCODER_DTS 0x05 + +/* Decoder Type Codes */ +#define AUDIO_DECODER_UNDEF 0x00 +#define AUDIO_DECODER_OTHER 0x01 +#define AUDIO_DECODER_MPEG 0x02 +#define AUDIO_DECODER_AC3 0x03 +#define AUDIO_DECODER_WMA 0x04 +#define AUDIO_DECODER_DTS 0x05 + +/* Audio Descriptor Types */ +#define AUDIO_UNDEFINED_DESCRIPTOR_TYPE 0x20 +#define AUDIO_DEVICE_DESCRIPTOR_TYPE 0x21 +#define AUDIO_CONFIGURATION_DESCRIPTOR_TYPE 0x22 +#define AUDIO_STRING_DESCRIPTOR_TYPE 0x23 +#define AUDIO_INTERFACE_DESCRIPTOR_TYPE 0x24 +#define AUDIO_ENDPOINT_DESCRIPTOR_TYPE 0x25 + +/* Audio Data Format Type I Codes */ +#define AUDIO_FORMAT_TYPE_I_UNDEFINED 0x0000 +#define AUDIO_FORMAT_PCM 0x0001 +#define AUDIO_FORMAT_PCM8 0x0002 +#define AUDIO_FORMAT_IEEE_FLOAT 0x0003 +#define AUDIO_FORMAT_ALAW 0x0004 +#define AUDIO_FORMAT_MULAW 0x0005 + +#define AUDIO_V2_FORMAT_PCM 0x00000001 +#define AUDIO_V2_FORMAT_PCM8 0x00000002 +#define AUDIO_V2_FORMAT_IEEE_FLOAT 0x00000004 +#define AUDIO_V2_FORMAT_ALAW 0x00000008 +#define AUDIO_V2_FORMAT_MULAW 0x00000010 + +/* bmChannelConfig: a bitmap field that indicates which spatial locations + * are occupied by the channels present in the cluster. The bit allocations + * are as follows: + */ +#define AUDIO_CHANNEL_M 0 /* Mono */ +#define AUDIO_CHANNEL_FL (1 << 0) /* Front Left */ +#define AUDIO_CHANNEL_FR (1 << 1) /* Front Right */ +#define AUDIO_CHANNEL_FC (1 << 2) /* Front Center */ +#define AUDIO_CHANNEL_LFE (1 << 3) /* Low Frequency Effects */ +#define AUDIO_CHANNEL_BL (1 << 4) /* Back Left */ +#define AUDIO_CHANNEL_BR (1 << 5) /* Back Right */ +#define AUDIO_CHANNEL_FLC (1 << 6) /* Front Left of Center */ +#define AUDIO_CHANNEL_FRC (1 << 7) /* Front Right of Center */ +#define AUDIO_CHANNEL_BC (1 << 8) /* Back Center */ +#define AUDIO_CHANNEL_SL (1 << 9) /* Side Left */ +#define AUDIO_CHANNEL_SR (1 << 10) /* Side Right */ +#define AUDIO_CHANNEL_TC (1 << 11) /* Top Center */ +#define AUDIO_CHANNEL_TFL (1 << 12) /* Top Front Left */ +#define AUDIO_CHANNEL_TFC (1 << 13) /* Top Front Center */ +#define AUDIO_CHANNEL_TFR (1 << 14) /* Top Front Right */ +#define AUDIO_CHANNEL_TBL (1 << 15) /* Top Back Left */ +#define AUDIO_CHANNEL_TBC (1 << 16) /* Top Back Center */ +#define AUDIO_CHANNEL_TBR (1 << 17) /* Top Back Right */ +#define AUDIO_CHANNEL_TFLC (1 << 18) /* Top Front Left of Center */ +#define AUDIO_CHANNEL_TFRC (1 << 19) /* Top Front Right of Center */ +#define AUDIO_CHANNEL_LLFE (1 << 20) /* Left Low Frequency Effects */ +#define AUDIO_CHANNEL_RLFE (1 << 21) /* Right Low Frequency Effects */ +#define AUDIO_CHANNEL_TSL (1 << 22) /* Top Side Left */ +#define AUDIO_CHANNEL_TSR (1 << 23) /* Top Side Right */ +#define AUDIO_CHANNEL_BOC (1 << 24) /* Bottom Center */ +#define AUDIO_CHANNEL_BLC (1 << 25) /* Back Left of Center */ +#define AUDIO_CHANNEL_BRC (1 << 26) /* Back Right of Center */ + /* Bits 27-30: Reserved */ +#define AUDIO_CHANNEL_RD (1 << 31) /* Raw Data */ + +/* Audio Function Category Codes */ +#define AUDIO_CATEGORY_UNDEF 0x00 /* Undefined */ +#define AUDIO_CATEGORY_SPEAKER 0x01 /* Desktop speaker */ +#define AUDIO_CATEGORY_THEATER 0x02 /* Home theater */ +#define AUDIO_CATEGORY_MICROPHONE 0x03 /* Microphone */ +#define AUDIO_CATEGORY_HEADSET 0x04 /* Headset */ +#define AUDIO_CATEGORY_TELEPHONE 0x05 /* Telephone */ +#define AUDIO_CATEGORY_CONVERTER 0x06 /* Converter */ +#define AUDIO_CATEGORY_RECORDER 0x07 /* Voice/Sound recorder */ +#define AUDIO_CATEGORY_IO_BOX 0x08 /* I/O box */ +#define AUDIO_CATEGORY_INSTRUMENT 0x09 /* Musical instrument */ +#define AUDIO_CATEGORY_PROAUDIO 0x0a /* Pro-audio */ +#define AUDIO_CATEGORY_AV 0x0b /* Audio/video */ +#define AUDIO_CATEGORY_CONTROL 0x0c /* Control panel */ +#define AUDIO_CATEGORY_OTHER 0xff + +/* Clock Source Control Selectors */ +#define AUDIO_CS_CONTROL_UNDEF 0x00 +#define AUDIO_CS_CONTROL_SAM_FREQ 0x01 +#define AUDIO_CS_CONTROL_CLOCK_VALID 0x02 + +/* Clock Selector Control Selectors */ +#define AUDIO_CX_CONTROL_UNDEF 0x00 +#define AUDIO_CX_CONTROL_CLOCKSEL 0x01 + +/* Clock Multiplier Control Selectors */ +#define AUDIO_CM_CONTROL_UNDEF 0x00 +#define AUDIO_CM_CONTROL_NUMERATOR 0x01 +#define AUDIO_CM_CONTROL_DENOMINATOR 0x02 + +/* Terminal Control Selectors */ +#define AUDIO_TE_CONTROL_UNDEF 0x00 +#define AUDIO_TE_CONTROL_COPY_PROTECT 0x01 +#define AUDIO_TE_CONTROL_CONNECTOR 0x02 +#define AUDIO_TE_CONTROL_OVERLOAD 0x03 +#define AUDIO_TE_CONTROL_CLUSTER 0x04 +#define AUDIO_TE_CONTROL_UNDERFLOW 0x05 +#define AUDIO_TE_CONTROL_OVERFLOW 0x06 +#define AUDIO_TE_CONTROL_LATENCY 0x07 + +/* Mixer Control Selectors */ +#define AUDIO_MU_CONTROL_UNDEF 0x00 +#define AUDIO_MU_CONTROL_MIXER 0x01 +#define AUDIO_MU_CONTROL_CLUSTER 0x02 +#define AUDIO_MU_CONTROL_UNDERFLOW 0x03 +#define AUDIO_MU_CONTROL_OVERFLOW 0x04 +#define AUDIO_MU_CONTROL_LATENCY 0x05 + +/* Selector Control Selectors */ +#define AUDIO_SU_CONTROL_UNDEFINE 0x00 +#define AUDIO_SU_CONTROL_SELECTOR 0x01 +#define AUDIO_SU_CONTROL_LATENCY 0x02 + +/* Feature Unit Control Selectors */ +#define AUDIO_FU_CONTROL_UNDEF 0x00 +#define AUDIO_FU_CONTROL_MUTE 0x01 +#define AUDIO_FU_CONTROL_VOLUME 0x02 +#define AUDIO_FU_CONTROL_BASS 0x03 +#define AUDIO_FU_CONTROL_MID 0x04 +#define AUDIO_FU_CONTROL_TREBLE 0x05 +#define AUDIO_FU_CONTROL_EQUALIZER 0x06 +#define AUDIO_FU_CONTROL_AGC 0x07 +#define AUDIO_FU_CONTROL_DELAY 0x08 +#define AUDIO_FU_CONTROL_BASS_BOOST 0x09 +#define AUDIO_FU_CONTROL_LOUDNESS 0x0a +#define AUDIO_FU_CONTROL_INP_GAIN 0x0b +#define AUDIO_FU_CONTROL_INP_GAIN_PAD 0x0c +#define AUDIO_FU_CONTROL_PHASE_INVERT 0x0d +#define AUDIO_FU_CONTROL_UNDERFLOW 0x0e +#define AUDIO_FU_CONTROL_OVERFLOW 0x0f +#define AUDIO_FU_CONTROL_LATENCY 0x10 + +#define AUDIO_V2_FU_CONTROL_UNDEF 0x00 +#define AUDIO_V2_FU_CONTROL_MUTE (0x03 << 0) +#define AUDIO_V2_FU_CONTROL_VOLUME (0x03 << 2) +#define AUDIO_V2_FU_CONTROL_BASS (0x03 << 4) +#define AUDIO_V2_FU_CONTROL_MID (0x03 << 6) +#define AUDIO_V2_FU_CONTROL_TREBLE (0x03 << 8) +#define AUDIO_V2_FU_CONTROL_EQUALIZER (0x03 << 10) +#define AUDIO_V2_FU_CONTROL_AGC (0x03 << 12) +#define AUDIO_V2_FU_CONTROL_DELAY (0x03 << 14) +#define AUDIO_V2_FU_CONTROL_BASS_BOOST (0x03 << 16) +#define AUDIO_V2_FU_CONTROL_LOUDNESS (0x03 << 18) +#define AUDIO_V2_FU_CONTROL_INP_GAIN (0x03 << 20) +#define AUDIO_V2_FU_CONTROL_INP_GAIN_PAD (0x03 << 22) +#define AUDIO_V2_FU_CONTROL_PHASE_INVERT (0x03 << 24) +#define AUDIO_V2_FU_CONTROL_UNDERFLOW (0x03 << 26) +#define AUDIO_V2_FU_CONTROL_OVERFLOW (0x03 << 28) + +/* Parametric Equalizer Section Effect Unit Control Selectors */ +#define AUDIO_PE_CONTROL_UNDEF 0x00 +#define AUDIO_PE_CONTROL_ENABLE 0x01 +#define AUDIO_PE_CONTROL_CENTERFREQ 0x02 +#define AUDIO_PE_CONTROL_QFACTOR 0x03 +#define AUDIO_PE_CONTROL_GAIN 0x04 +#define AUDIO_PE_CONTROL_UNDERFLOW 0x05 +#define AUDIO_PE_CONTROL_OVERFLOW 0x06 +#define AUDIO_PE_CONTROL_LATENCY 0x07 + +/* Reverberation Effect Unit Control Selectors */ +#define AUDIO_RV_CONTROL_UNDEF 0x00 +#define AUDIO_RV_CONTROL_ENABLE 0x01 +#define AUDIO_RV_CONTROL_TYPE 0x02 +#define AUDIO_RV_CONTROL_LEVEL 0x03 +#define AUDIO_RV_CONTROL_TIME 0x04 +#define AUDIO_RV_CONTROL_FEEDBACK 0x05 +#define AUDIO_RV_CONTROL_PREDELAY 0x06 +#define AUDIO_RV_CONTROL_DENSITY 0x07 +#define AUDIO_RV_CONTROL_HF_ROLLOFF 0x08 +#define AUDIO_RV_CONTROL_UNDERFLOW 0x09 +#define AUDIO_RV_CONTROL_OVERFLOW 0x0a +#define AUDIO_RV_CONTROL_LATENCY 0x0b + +/* Modulation Delay Effect Unit Control Selectors */ +#define AUDIO_MD_CONTROL_UNDEF 0x00 +#define AUDIO_MD_CONTROL_ENABLE 0x01 +#define AUDIO_MD_CONTROL_BALANCE 0x02 +#define AUDIO_MD_CONTROL_RATE 0x03 +#define AUDIO_MD_CONTROL_DEPTH 0x04 +#define AUDIO_MD_CONTROL_TIME 0x05 +#define AUDIO_MD_CONTROL_FEEDBACK 0x06 +#define AUDIO_MD_CONTROL_UNDERFLOW 0x07 +#define AUDIO_MD_CONTROL_OVERFLOW 0x08 +#define AUDIO_MD_CONTROL_LATENCY 0x09 + +/* Dynamic Range Compressor Effect Unit Control Selectors */ +#define AUDIO_DR_CONTROL_UNDEF 0x00 +#define AUDIO_DR_CONTROL_ENABLE 0x01 +#define AUDIO_DR_CONTROL_COMP_RATE 0x02 +#define AUDIO_DR_CONTROL_MAXAMPL 0x03 +#define AUDIO_DR_CONTROL_THRESHOLD 0x04 +#define AUDIO_DR_CONTROL_ATTACK_TIME 0x05 +#define AUDIO_DR_CONTROL_RELEASE_TIME 0x06 +#define AUDIO_DR_CONTROL_UNDERFLOW 0x07 +#define AUDIO_DR_CONTROL_OVERFLOW 0x08 +#define AUDIO_DR_CONTROL_LATENCY 0x09 + +/* Up/Down-mix Processing Unit Control Selectors */ +#define AUDIO_UD_CONTROL_UNDEF 0x00 +#define AUDIO_UD_CONTROL_ENABLE 0x01 +#define AUDIO_UD_CONTROL_MODE_SELECT 0x02 +#define AUDIO_UD_CONTROL_CLUSTER 0x03 +#define AUDIO_UD_CONTROL_UNDERFLOW 0x04 +#define AUDIO_UD_CONTROL_OVERFLOW 0x05 +#define AUDIO_UD_CONTROL_LATENCY 0x06 + +/* Dolby Prologic?Processing Unit Control Selectors */ +#define AUDIO_DP_CONTROL_UNDEF 0x00 +#define AUDIO_DP_CONTROL_ENABLE 0x01 +#define AUDIO_DP_CONTROL_MODE_SELECT 0x02 +#define AUDIO_DP_CONTROL_CLUSTER 0x03 +#define AUDIO_DP_CONTROL_UNDERFLOW 0x04 +#define AUDIO_DP_CONTROL_OVERFLOW 0x05 +#define AUDIO_DP_CONTROL_LATENCY 0x06 + +/* Stereo Extender Processing Unit Control Selectors */ +#define AUDIO_STEXT_CONTROL_UNDEF 0x00 +#define AUDIO_STEXT_CONTROL_ENABLE 0x01 +#define AUDIO_STEXT_CONTROL_WIDTH 0x02 +#define AUDIO_STEXT_CONTROL_UNDERFLOW 0x03 +#define AUDIO_STEXT_CONTROL_OVERFLOW 0x04 +#define AUDIO_STEXT_CONTROL_LATENCY 0x05 + +/* Extension Unit Control Selectors */ + +#define AUDIO_XU_CONTROL_UNDEF 0x00 +#define AUDIO_XU_CONTROL_ENABLE 0x01 +#define AUDIO_XU_CONTROL_CLUSTER 0x02 +#define AUDIO_XU_CONTROL_UNDERFLOW 0x03 +#define AUDIO_XU_CONTROL_OVERFLOW 0x04 +#define AUDIO_XU_CONTROL_LATENCY 0x05 + +/* AudioStreaming Interface Control Selectors */ + +#define AUDIO_AS_CONTROL_UNDEF 0x00 +#define AUDIO_AS_CONTROL_ACT_ALT 0x01 +#define AUDIO_AS_CONTROL_VAL_ALT 0x02 +#define AUDIO_AS_CONTROL_AUDIO_FORMAT 0x03 + +/* Encoder Control Selectors */ + +#define AUDIO_EN_CONTROL_UNDEF 0x00 +#define AUDIO_EN_CONTROL_BIT_RATE 0x01 +#define AUDIO_EN_CONTROL_QUALITY 0x02 +#define AUDIO_EN_CONTROL_VBR 0x03 +#define AUDIO_EN_CONTROL_TYPE 0x04 +#define AUDIO_EN_CONTROL_UNDERFLOW 0x05 +#define AUDIO_EN_CONTROL_OVERFLOW 0x06 +#define AUDIO_EN_CONTROL_ENCODER_ERR 0x07 +#define AUDIO_EN_CONTROL_PARAM1 0x08 +#define AUDIO_EN_CONTROL_PARAM2 0x09 +#define AUDIO_EN_CONTROL_PARAM3 0x0a +#define AUDIO_EN_CONTROL_PARAM4 0x0b +#define AUDIO_EN_CONTROL_PARAM5 0x0c +#define AUDIO_EN_CONTROL_PARAM6 0x0d +#define AUDIO_EN_CONTROL_PARAM7 0x0e +#define AUDIO_EN_CONTROL_PARAM8 0x0f + +/* MPEG Decoder Control Selectors */ + +#define AUDIO_MPGD_CONTROL_UNDEF 0x00 +#define AUDIO_MPGD_CONTROL_DUAL_CHAN 0x01 +#define AUDIO_MPGD_CONTROL_2ND_STEREO 0x02 +#define AUDIO_MPGD_CONTROL_MULTILING 0x03 +#define AUDIO_MPGD_CONTROL_DYN_RANGE 0x04 +#define AUDIO_MPGD_CONTROL_SCALING 0x05 +#define AUDIO_MPGD_CONTROL_HILO_SCALE 0x06 +#define AUDIO_MPGD_CONTROL_UNDERFLOW 0x07 +#define AUDIO_MPGD_CONTROL_OVERFLOW 0x08 +#define AUDIO_MPGD_CONTROL_DECODE_ERR 0x09 + +/* AC-3 Decoder Control Selectors */ + +#define AUDIO_AC3D_CONTROL_UNDEF 0x00 +#define AUDIO_AC3D_CONTROL_MODE 0x01 +#define AUDIO_AC3D_CONTROL_DYN_RANGE 0x02 +#define AUDIO_AC3D_CONTROL_SCALING 0x03 +#define AUDIO_AC3D_CONTROL_HILO_SCALE 0x04 +#define AUDIO_AC3D_CONTROL_UNDERFLOW 0x05 +#define AUDIO_AC3D_CONTROL_OVERFLOW 0x06 +#define AUDIO_AC3D_CONTROL_DECODE_ERR 0x07 + +/* WMA Decoder Control Selectors */ + +#define AUDIO_WMAD_CONTROL_UNDEF 0x00 +#define AUDIO_WMAD_CONTROL_UNDERFLOW 0x01 +#define AUDIO_WMAD_CONTROL_OVERFLOW 0x02 +#define AUDIO_WMAD_CONTROL_DECODE_ERR 0x03 + +/* DTS Decoder Control Selectors */ + +#define AUDIO_DTSD_CONTROL_UNDEF 0x00 +#define AUDIO_DTSD_CONTROL_UNDERFLOW 0x01 +#define AUDIO_DTSD_CONTROL_OVERFLOW 0x02 +#define AUDIO_DTSD_CONTROL_DECODE_ERR 0x03 + +/* Endpoint Control Selectors */ +#define AUDIO_EP_CONTROL_UNDEF 0x00 +#define AUDIO_EP_CONTROL_SAMPLING_FEQ 0x01 +#define AUDIO_EP_CONTROL_PITCH 0x02 + +/* Encoder Error Codes */ + +/* <0: Reserved for vendor extensions */ + +#define AUDIO_ENCODER_SUCCESS 0 /* No Error */ +#define AUDIO_ENCODER_ERROR_NOMEM 1 /* Out of Memory */ +#define AUDIO_ENCODER_ERROR_BW 2 /* Out of Bandwidth */ +#define AUDIO_ENCODER_ERROR_CYCLE 3 /* Out of Processing Cycles */ +#define AUDIO_ENCODER_ERROR_FRAME 4 /* General Format Frame Error */ +#define AUDIO_ENCODER_ERROR_TOOSMALL 5 /* Format Frame Too Small */ +#define AUDIO_ENCODER_ERROR_TOOBIG 6 /* Format Frame Too Large */ +#define AUDIO_ENCODER_ERROR_BADFORMAT 7 /* Bad Data Format */ +#define AUDIO_ENCODER_ERROR_NCHAN 8 /* Incorrect Number of Channels */ +#define AUDIO_ENCODER_ERROR_RATE 9 /* Incorrect Sampling Rate */ +#define AUDIO_ENCODER_ERROR_BITRATE 10 /* Unable to Meet Target Bitrate */ +#define AUDIO_ENCODER_ERROR_PARMS 11 /* Inconsistent Set of Parameters */ +#define AUDIO_ENCODER_ERROR_NOTREADY 12 /* Not Ready */ +#define AUDIO_ENCODER_ERROR_BUSY 13 /* Busy */ + /* >13: Reserved */ + +/* Format Type Codes */ + +#define AUDIO_FORMAT_TYPE_UNDEF 0x00 +#define AUDIO_FORMAT_TYPEI 0x01 +#define AUDIO_FORMAT_TYPEII 0x02 +#define AUDIO_FORMAT_TYPEIII 0x03 +#define AUDIO_FORMAT_TYPEIV 0x04 +#define AUDIO_FORMAT_EXT_TYPEI 0x81 +#define AUDIO_FORMAT_EXT_TYPEII 0x82 +#define AUDIO_FORMAT_EXT_TYPEIII 0x83 + +/* Audio Data Format Type I Bit Allocations */ + +#define AUDIO_FORMAT_TYPEI_PCM (1 << 0) +#define AUDIO_FORMAT_TYPEI_PCM8 (1 << 1) +#define AUDIO_FORMAT_TYPEI_IEEEFLOAT (1 << 2) +#define AUDIO_FORMAT_TYPEI_ALAW (1 << 3) +#define AUDIO_FORMAT_TYPEI_MULAW (1 << 4) +#define AUDIO_FORMAT_TYPEI_RAWDATA (1 << 31) + +/* Audio Data Format Type II Bit Allocations */ + +#define AUDIO_FORMAT_TYPEII_MPEG (1 << 0) +#define AUDIO_FORMAT_TYPEII_AC3 (1 << 1) +#define AUDIO_FORMAT_TYPEII_WMA (1 << 2) +#define AUDIO_FORMAT_TYPEII_DTS (1 << 3) +#define AUDIO_FORMAT_TYPEII_RAWDATA (1 << 31) + +/* Audio Data Format Type III Bit Allocations */ + +#define AUDIO_FORMAT_TYPEIII_IEC61937_AC3 (1 << 0) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG1_L1 (1 << 1) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG1_L2_3 (1 << 1) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG2_NOEXT (1 << 2) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG2_EXT (1 << 3) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG2_AAC_ADTS (1 << 4) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG2_L1_LS (1 << 5) +#define AUDIO_FORMAT_TYPEIII_IEC61937_MPEG2_L2_3_LS (1 << 6) +#define AUDIO_FORMAT_TYPEIII_IEC61937_DTS_I (1 << 7) +#define AUDIO_FORMAT_TYPEIII_IEC61937_DTS_II (1 << 8) +#define AUDIO_FORMAT_TYPEIII_IEC61937_DTS_III (1 << 9) +#define AUDIO_FORMAT_TYPEIII_IEC61937_ATRAC (1 << 10) +#define AUDIO_FORMAT_TYPEIII_IEC61937_ATRAC2_3 (1 << 11) +#define AUDIO_FORMAT_TYPEIII_WMA (1 << 12) + +/* Audio Data Format Type IV Bit Allocations */ + +#define AUDIO_FORMAT_TYPEIV_PCM (1 << 0) +#define AUDIO_FORMAT_TYPEIV_PCM8 (1 << 1) +#define AUDIO_FORMAT_TYPEIV_IEEE_FLOAT (1 << 2) +#define AUDIO_FORMAT_TYPEIV_ALAW (1 << 3) +#define AUDIO_FORMAT_TYPEIV_MULAW (1 << 4) +#define AUDIO_FORMAT_TYPEIV_MPEG (1 << 5) +#define AUDIO_FORMAT_TYPEIV_AC3 (1 << 6) +#define AUDIO_FORMAT_TYPEIV_WMA (1 << 7) +#define AUDIO_FORMAT_TYPEIV_IEC61937_AC3 (1 << 8) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG1_L1 (1 << 9) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG1_L2_3 (1 << 10) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG2_NOEXT (1 << 10) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG2_EXT (1 << 11) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG2_AAC_ADTS (1 << 12) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG2_L1_LS (1 << 13) +#define AUDIO_FORMAT_TYPEIV_IEC61937_MPEG2_L2_3_LS (1 << 14) +#define AUDIO_FORMAT_TYPEIV_IEC61937_DTS_I (1 << 15) +#define AUDIO_FORMAT_TYPEIV_IEC61937_DTS_II (1 << 16) +#define AUDIO_FORMAT_TYPEIV_IEC61937_DTS_III (1 << 17) +#define AUDIO_FORMAT_TYPEIV_IEC61937_ATRAC (1 << 18) +#define AUDIO_FORMAT_TYPEIV_IEC61937_ATRAC2_3 (1 << 19) +#define AUDIO_FORMAT_TYPEIV_TYPE_III_WMA (1 << 20) +#define AUDIO_FORMAT_TYPEIV_IEC60958_PCM (1 << 21) + +/* Side Band Protocol Codes */ +#define AUDIO_SIDEBAND_PROTOCOL_UNDEF 0x00 +#define AUDIO_PRES_TIMESTAMP_PROTOCOL 0x01 + +/** USB Terminal Types + * Refer to Table 2-1 - Table 2-4 from termt10.pdf + */ + +/* USB Terminal Types */ +#define AUDIO_TERMINAL_UNDEF 0x0100 +#define AUDIO_TERMINAL_STREAMING 0x0101 +#define AUDIO_TERMINAL_VENDOR 0x01ff + +/* Input Terminal Types */ +#define AUDIO_INTERM_UNDEF 0x0200 /* Undefined Type */ +#define AUDIO_INTERM_MIC 0x0201 /* A generic microhpone */ +#define AUDIO_INTERM_DESKTOP_MIC 0x0202 /* A desktop microphone */ +#define AUDIO_INTERM_PERSONAL_MIC 0x0203 /* Head-mounted or clip-on microphone */ +#define AUDIO_INTERM_OMNI_MIC 0x0204 /* Omni-directional microphone */ +#define AUDIO_INTERM_MIC_ARRAY 0x0205 /* Microphone array */ +#define AUDIO_INTERM_PROC_MIC_ARRAY 0x0206 /* Microphone array with signal processor */ + +/* Output Terminal Types */ +#define AUDIO_OUTTERM_UNDEF 0x0300 /* Undefined Type */ +#define AUDIO_OUTTERM_SPEAKER 0x0301 /* Generic speakers */ +#define AUDIO_OUTTERM_HEADPHONES 0x0302 /* A head-mounted audio output device */ +#define AUDIO_OUTTERM_HEADDISPLAY 0x0303 /* Head Mounted Display Audio */ +#define AUDIO_OUTTERM_DESKTOP 0x0304 /* Desktop speaker */ +#define AUDIO_OUTTERM_ROOM 0x0305 /* Room speaker */ +#define AUDIO_OUTTERM_COMMS 0x0306 /* Communication speaker */ +#define AUDIO_OUTTERM_LOFREQ 0x0307 /* Low frequency effects speaker */ + +/* Bi-directional Terminal Types */ +#define AUDIO_BIDITERM_UNDEF 0x0400 /* Undefined Type */ +#define AUDIO_BIDITERM_HANDSET 0x0401 /* Hand-held bi-directional audio device */ +#define AUDIO_BIDITERM_HEADSET 0x0402 /* Head-mounted bi-directional audio device */ +#define AUDIO_BIDITERM_SPEAKERPHONE 0x0403 /* Speakerphone, no echo reduction */ +#define AUDIO_BIDITERM_ECHOSUPPRESS 0x0404 /* Echo-suppressing speakerphone */ +#define AUDIO_BIDITERM_ECHOCANCEL 0x0405 /* Echo-canceling speakerphone */ + +/* Telephony Terminal Types */ +#define AUDIO_TELETERM_UNDEF 0x0500 /* Undefined Type */ +#define AUDIO_TELETERM_PHONELINE 0x0501 /* Analog telephone line jack, an ISDN line, + * a proprietary PBX interface, or a wireless link */ +#define AUDIO_TELETERM_TELEPHONE 0x0502 /* Device can be used as a telephone */ +#define AUDIO_TELETERM_DOWNLINE 0x0503 /* Down Line Phone */ + +/* External Terminal Types */ +#define AUDIO_EXTTERM_UNDEF 0x0600 /* Undefined Type */ +#define AUDIO_EXTTERM_ANALOG 0x0601 /* Generic analog connector */ +#define AUDIO_EXTTERM_DIGITAL 0x0602 /* Generic digital audio interface */ +#define AUDIO_EXTTERM_LINE 0x0603 /* Analog connector at standard line levels */ +#define AUDIO_EXTTERM_LEGACY 0x0604 /* Legacy audio line out connector */ +#define AUDIO_EXTTERM_SPDIF 0x0605 /* SPDIF interface */ +#define AUDIO_EXTTERM_1394DA 0x0606 /* 1394 DA stream */ +#define AUDIO_EXTTERM_1394DV 0x0607 /* 1394 DV stream soundtrack */ +#define AUDIO_EXTTERM_ADAT 0x0608 /* ADAT Lightpipe */ +#define AUDIO_EXTTERM_TDIF 0x0609 /* TDIF - Tascam Digital Interface */ +#define AUDIO_EXTTERM_MADI 0x060a /* MADI - Multi-channel Audio Digital Interface (AES) */ + +/* Embedded Function Terminal Types */ +#define AUDIO_EMBEDTERM_UNDEF 0x0700 /* Undefined Type */ +#define AUDIO_EMBEDTERM_CALIBRATION 0x0701 /* Level Calibration Noise Source */ +#define AUDIO_EMBEDTERM_EQUALIZATION 0x0702 /* Equalization Noise */ +#define AUDIO_EMBEDTERM_CD 0x0703 /* CD player */ +#define AUDIO_EMBEDTERM_DAT 0x0704 /* Digital Audio Tape */ +#define AUDIO_EMBEDTERM_DCC 0x0705 /* Digital Compact Cassette */ +#define AUDIO_EMBEDTERM_COMPRESSED 0x0706 /* Compressed Audio Player */ +#define AUDIO_EMBEDTERM_TAPE 0x0707 /* Analog Audio Tape */ +#define AUDIO_EMBEDTERM_PHONOGRAPH 0x0708 /* Analog vinyl record player */ +#define AUDIO_EMBEDTERM_VCR 0x0709 /* Audio track of VCR */ +#define AUDIO_EMBEDTERM_VIDDISC 0x070a /* Audio track of VideoDisc player */ +#define AUDIO_EMBEDTERM_DVD 0x070b /* Audio track of DVD player */ +#define AUDIO_EMBEDTERM_TVTUNER 0x070c /* Audio track of TV tuner */ +#define AUDIO_EMBEDTERM_SATELLITE 0x070d /* Audio track of satellite receiver */ +#define AUDIO_EMBEDTERM_CABLETUNER 0x070e /* Audio track of cable tuner */ +#define AUDIO_EMBEDTERM_DSS 0x070f /* Audio track of DSS receiver */ +#define AUDIO_EMBEDTERM_RADIO 0x0710 /* AM/FM radio receiver */ +#define AUDIO_EMBEDTERM_TRANSMITTER 0x0711 /* AM/FM radio transmitter */ +#define AUDIO_EMBEDTERM_MULTITRACK 0x0712 /* A multi-track recording system */ +#define AUDIO_EMBEDTERM_SYNTHESIZER 0x0713 /* Synthesizer */ +#define AUDIO_EMBEDTERM_PIANO 0x0714 /* Piano */ +#define AUDIO_EMBEDTERM_GUITAR 0x0715 /* Guitar */ +#define AUDIO_EMBEDTERM_PERCUSSON 0x0716 /* Percussion Instrument */ +#define AUDIO_EMBEDTERM_INSTRUMENT 0x0717 /* Other Musical Instrument */ + +#define AUDIO_FORMAT_TYPE_I 0x01 +#define AUDIO_FORMAT_TYPE_II 0x02 +#define AUDIO_FORMAT_TYPE_III 0x03 + +struct audio_cs_if_ac_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdADC; + uint16_t wTotalLength; + uint8_t bInCollection; + uint8_t baInterfaceNr[]; +} __PACKED; + +#define AUDIO_SIZEOF_AC_HEADER_DESC(n) (8 + n) + +struct audio_cs_if_ac_input_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bNrChannels; + uint16_t wChannelConfig; + uint8_t iChannelNames; + uint8_t iTerminal; +} __PACKED; + +#define AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC (12) + +struct audio_cs_if_ac_output_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bSourceID; + uint8_t iTerminal; +} __PACKED; + +#define AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC (9) + +struct audio_cs_if_ac_feature_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bUnitID; + uint8_t bSourceID; + uint8_t bControlSize; + uint8_t bmaControls[1]; + uint8_t iFeature; +} __PACKED; + +#define AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(ch, n) (7 + (ch + 1) * n) + +struct audio_cs_if_as_general_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalLink; + uint8_t bDelay; + uint16_t wFormatTag; +} __PACKED; + +#define AUDIO_SIZEOF_AS_GENERAL_DESC (7) + +struct audio_cs_if_as_format_type_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bFormatType; + uint8_t bNrChannels; + uint8_t bSubframeSize; + uint8_t bBitResolution; + uint8_t bSamFreqType; + uint8_t tSamFreq[3]; +} __PACKED; + +#define AUDIO_SIZEOF_FORMAT_TYPE_DESC(n) (8 + 3 * n) + +struct audio_ep_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bEndpointAddress; + uint8_t bmAttributes; + uint16_t wMaxPacketSize; + uint8_t bInterval; + uint8_t bRefresh; + uint8_t bSynchAddress; +} __PACKED; + +#define AUDIO_SIZEOF_EP_DESC (9) + +struct audio_cs_ep_ep_general_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bmAttributes; + uint8_t bLockDelayUnits; + uint16_t wLockDelay; +} __PACKED; + +#define AUDIO_SIZEOF_CS_EP_GENERAL_DESC (7) + +// clang-format off +#define AUDIO_AC_DESCRIPTOR_INIT(bFirstInterface, bInterfaceCount, wTotalLength, stridx, ...) \ + /* Interface Association Descriptor */ \ + 0x08, \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, \ + bFirstInterface, \ + bInterfaceCount, \ + USB_DEVICE_CLASS_AUDIO, \ + AUDIO_SUBCLASS_AUDIOCONTROL, \ + AUDIO_PROTOCOL_UNDEFINED, \ + 0x00, \ + /* ------------------ AudioControl Interface ------------------ */\ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + stridx, /* iInterface */ \ + 0x08 + PP_NARG(__VA_ARGS__), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */ \ + WBVAL(0x0100), /* bcdADC */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + PP_NARG(__VA_ARGS__), /* bInCollection */ \ + __VA_ARGS__ /* baInterfaceNr */ + +#define AUDIO_AC_DESCRIPTOR_INIT_LEN(n) (0x08 + 0x09 + 0x08 + n) + +#define AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(bTerminalID, wTerminalType, bNrChannels, wChannelConfig) \ + 0x0C, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */ \ + bTerminalID, /* bTerminalID */ \ + WBVAL(wTerminalType), /* wTerminalType : Microphone 0x0201 */ \ + 0x00, /* bAssocTerminal */ \ + bNrChannels, /* bNrChannels */ \ + WBVAL(wChannelConfig), /* wChannelConfig : Mono sets no position bits */ \ + 0x00, /* iChannelNames */ \ + 0x00 /* iTerminal */ + +#define AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(bTerminalID, wTerminalType, bSourceID) \ + 0x09, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */ \ + bTerminalID, /* bTerminalID */ \ + WBVAL(wTerminalType), /* wTerminalType : USB Streaming */ \ + 0x00, /* bAssocTerminal */ \ + bSourceID, /* bSourceID */ \ + 0x00 /* iTerminal */ + +#define AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(bUnitID, bSourceID, bControlSize, ...) \ + 0x07 + PP_NARG(__VA_ARGS__), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */ \ + bUnitID, /* bUnitID */ \ + bSourceID, /* bSourceID */ \ + bControlSize, /* bControlSize */ \ + __VA_ARGS__, /* bmaControls(0) Mute */ \ + 0x00 /* iTerminal */ + +#define AUDIO_AS_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bSubFrameSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval, ...) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x01, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output Terminal*/ \ + 0x01, /* bDelay */ \ + WBVAL(AUDIO_FORMAT_PCM), /* wFormatTag : AUDIO_FORMAT_PCM */ \ + 0x08 + PP_NARG(__VA_ARGS__), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bNrChannels, /* bNrChannels */ \ + bSubFrameSize, /* bSubFrameSize : Bytes per audio subframe */ \ + bBitResolution, /* bBitResolution : bits per sample */ \ + (PP_NARG(__VA_ARGS__)/3), /* bSamFreqType : only one frequency supported */ \ + __VA_ARGS__, /* tSamFreq : Audio sampling frequency coded on 3 bytes */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress : IN endpoint 1 */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + bInterval, /* bInterval : one packet per frame */ \ + 0x00, /* bRefresh */ \ + 0x00, /* bSynchAddress */ \ + 0x07, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + AUDIO_EP_CONTROL_SAMPLING_FEQ, /* bmAttributes AUDIO_SAMPLING_FREQ_CONTROL */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00 + +#define AUDIO_AS_DESCRIPTOR_INIT_LEN(n) (0x09 + 0x09 + 0x07 + 0x08 + 3 * n + 0x09 + 0x07) + +#define AUDIO_MS_STANDARD_DESCRIPTOR_INIT(bInterfaceNumber, bNumEndpoints) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + bNumEndpoints, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_MIDISTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */ \ + 0x00 /* iInterface */ + +#define AUDIO_MS_STANDARD_DESCRIPTOR_INIT_LEN 0x09 + +struct audio_v2_channel_cluster_descriptor { + uint8_t bNrChannels; + uint32_t bmChannelConfig; + uint8_t iChannelNames; +} __PACKED; + +#define AUDIO_V2_SIZEOF_CHANNEL_CLUSTER_DESC (6) + +struct audio_v2_cs_if_ac_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint16_t bcdADC; + uint8_t bCategory; + uint16_t wTotalLength; + uint8_t bmControls; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AC_HEADER_DESC (9) + +struct audio_v2_cs_if_ac_clock_source_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bClockID; + uint8_t bmAttributes; + uint8_t bmControls; + uint8_t bAssocTerminal; + uint8_t iClockSource; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC (8) + +struct audio_v2_cs_if_ac_clock_selector_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bClockID; + uint8_t bNrInPins; + uint8_t baCSourceID[1]; + uint8_t iClockSelector; +} __PACKED; + +#define AUDIO_SIZEOF_AC_CLOCK_SELECTOR_DESC(n) (7 + n) + +struct audio_v2_cs_if_ac_clock_multiplier_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bClockID; + uint8_t bCSourceID; + uint8_t bmControls; + uint8_t iClockMultiplier; +} __PACKED; + +#define AUDIO_SIZEOF_AC_CLOCK_MULTIPLIER_DESC() (7) + +struct audio_v2_cs_if_ac_input_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bCSourceID; + uint8_t bNrChannels; + uint32_t wChannelConfig; + uint8_t iChannelNames; + uint16_t bmControls; + uint8_t iTerminal; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC (17) + +struct audio_v2_cs_if_ac_output_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bSourceID; + uint8_t bCSourceID; + uint16_t bmControls; + uint8_t iTerminal; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC (12) + +struct audio_v2_cs_if_ac_feature_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bUnitID; + uint8_t bSourceID; + uint32_t bmaControls[1]; + uint8_t iFeature; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(ch) (6 + (ch + 1) * 4) + +struct audio_v2_cs_if_as_general_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bTerminalLink; + uint8_t bmControls; + uint8_t bFormatType; + uint32_t bmFormats; + uint8_t bNrChannels; + uint32_t bmChannelConfig; + uint8_t iChannelNames; +} __PACKED; + +#define AUDIO_V2_SIZEOF_AS_GENERAL_DESC (16) + +struct audio_v2_control_range1_param_block { + uint16_t wNumSubRanges; + struct + { + uint8_t bMin; + uint8_t bMax; + uint8_t bRes; + }subrange[]; +} __PACKED; + +struct audio_v2_control_range2_param_block { + uint16_t wNumSubRanges; + struct + { + uint16_t wMin; + uint16_t wMax; + uint16_t wRes; + }subrange[]; +} __PACKED; + +struct audio_v2_control_range3_param_block { + uint16_t wNumSubRanges; + struct + { + uint32_t dMin; + uint32_t dMax; + uint32_t dRes; + }subrange[]; +} __PACKED; + +#define AUDIO_V2_AC_DESCRIPTOR_INIT(bFirstInterface, bInterfaceCount, wTotalLength, bCategory, bmControls, stridx) \ + /* Interface Association Descriptor */ \ + 0x08, \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, \ + bFirstInterface, \ + bInterfaceCount, \ + USB_DEVICE_CLASS_AUDIO, \ + AUDIO_SUBCLASS_UNDEFINED, \ + AUDIO_PROTOCOLv20, \ + 0x00, \ + /* ------------------ AudioControl Interface ------------------ */\ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + stridx, /* iInterface */ \ + 0x09, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */ \ + WBVAL(0x0200), /* bcdADC */ \ + bCategory, /* bCategory */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + bmControls /* bmControls */ \ + +#define AUDIO_V2_AC_DESCRIPTOR_INIT_LEN (0x08 + 0x09 + 0x09) + +#define AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(bClockID, bmAttributes, bmControls) \ + 0x08, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_CLOCK_SOURCE, /* bDescriptorSubtype */ \ + bClockID, /* bClockID */ \ + bmAttributes, /* bmAttributes */ \ + bmControls, /* bmControls */ \ + 0x00, /* bAssocTerminal */ \ + 0x00 /* iClockSource */ + +#define AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(bTerminalID, wTerminalType, bCSourceID, bNrChannels, wChannelConfig, bmControls) \ + 0x11, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */ \ + bTerminalID, /* bTerminalID */ \ + WBVAL(wTerminalType), /* wTerminalType : Microphone 0x0201 */ \ + 0x00, /* bAssocTerminal */ \ + bCSourceID, /* bCSourceID */ \ + bNrChannels, /* bNrChannels */ \ + DBVAL(wChannelConfig), /* wChannelConfig : Mono sets no position bits */ \ + 0x00, /* iChannelNames */ \ + WBVAL(bmControls), /* bmControls */ \ + 0x00 /* iTerminal */ + +#define AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(bTerminalID, wTerminalType, bSourceID, bCSourceID, bmControls) \ + 0x0c, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */ \ + bTerminalID, /* bTerminalID */ \ + WBVAL(wTerminalType), /* wTerminalType : USB Streaming */ \ + 0x00, /* bAssocTerminal */ \ + bSourceID, /* bSourceID */ \ + bCSourceID, /* bCSourceID */ \ + WBVAL(bmControls), /* bmControls */ \ + 0x00 /* iTerminal */ + +#define AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(bUnitID, bSourceID, ...) \ + 0x06 + (PP_NARG(__VA_ARGS__)), /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */ \ + bUnitID, /* bUnitID */ \ + bSourceID, /* bSourceID */ \ + __VA_ARGS__, /* bmaControls(0) Mute */ \ + 0x00 /* iTerminal */ + +#define AUDIO_V2_AS_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bmChannelConfig, bSubslotSize, bBitResolution, bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x01, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x10, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output or Input Terminal*/ \ + 0x00, /* bmControls */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType : AUDIO_FORMAT_TYPE_I */ \ + DBVAL(AUDIO_V2_FORMAT_PCM), /* bmFormats PCM */ \ + bNrChannels, /* bNrChannels */ \ + DBVAL(bmChannelConfig), /* bmChannelConfig */ \ + 0x00, /* iChannelNames */ \ + 0x06, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bSubslotSize, /* bSubslotSize */ \ + bBitResolution, /* bBitResolution */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress 3 out endpoint for Audio */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* XXXX wMaxPacketSize in Bytes (SampleRate * SlotByteSize * NumChannels) */ \ + bInterval, /* bInterval */ \ + 0x08, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + 0x00, /* bmAttributes */ \ + 0x00, /* bmControls */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00 + +#define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT(bInterfaceNumber, bTerminalLink, bNrChannels, bmChannelConfig, bSubslotSize, bBitResolution, bEndpointAddress, wMaxPacketSize, bInterval, bFeedbackEndpointAddress) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + 0x01, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */ \ + AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */ \ + AUDIO_PROTOCOLv20, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x10, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */ \ + bTerminalLink, /* bTerminalLink : Unit ID of the Output or Input Terminal*/ \ + 0x00, /* bmControls */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType : AUDIO_FORMAT_TYPE_I */ \ + DBVAL(AUDIO_V2_FORMAT_PCM), /* bmFormats PCM */ \ + bNrChannels, /* bNrChannels */ \ + DBVAL(bmChannelConfig), /* bmChannelConfig */ \ + 0x00, /* iChannelNames */ \ + 0x06, /* bLength */ \ + AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */ \ + AUDIO_FORMAT_TYPE_I, /* bFormatType */ \ + bSubslotSize, /* bSubslotSize */ \ + bBitResolution, /* bBitResolution */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress 3 out endpoint for Audio */ \ + 0x05, /* bmAttributes: TransferType=Isochronous SyncType=Asynchronous EndpointType=Data*/ \ + WBVAL(wMaxPacketSize), /* XXXX wMaxPacketSize in Bytes (SampleRate * SlotByteSize * NumChannels) */ \ + bInterval, /* bInterval */ \ + 0x08, /* bLength */ \ + AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */ \ + AUDIO_ENDPOINT_GENERAL, /* bDescriptor */ \ + 0x00, /* bmAttributes */ \ + 0x00, /* bmControls */ \ + 0x00, /* bLockDelayUnits */ \ + 0x00, /* wLockDelay */ \ + 0x00, \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bFeedbackEndpointAddress, /* bFeedbackEndpointAddress Revise Dir to bEndpointAddress */ \ + 0x11, /* bmAttributes: TransferType=Isochronous SyncType=None EndpointType=Feedback */ \ + WBVAL(4), /* XXXX wMaxPacketSize in Bytes */ \ + bInterval /* bInterval */ \ + +// clang-format on + +#define AUDIO_V2_AS_DESCRIPTOR_INIT_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08) +#define AUDIO_V2_AS_FEEDBACK_DESCRIPTOR_INIT_LEN (0x09 + 0x09 + 0x10 + 0x06 + 0x07 + 0x08 + 0x07) + +#define AUDIO_SAMPLE_FREQ_NUM(num) (uint8_t)(num), (uint8_t)((num >> 8)) +#define AUDIO_SAMPLE_FREQ_3B(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16)) +#define AUDIO_SAMPLE_FREQ_4B(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), \ + (uint8_t)((frq >> 16)), (uint8_t)((frq >> 24)) + +#endif /* USB_AUDIO_H */ diff --git a/components/drivers/usb/cherryusb/class/audio/usbd_audio.c b/components/drivers/usb/cherryusb/class/audio/usbd_audio.c new file mode 100644 index 00000000000..c78c8ed751c --- /dev/null +++ b/components/drivers/usb/cherryusb/class/audio/usbd_audio.c @@ -0,0 +1,344 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_audio.h" + +struct audio_entity_param { + uint32_t wCur; + uint32_t wMin; + uint32_t wMax; + uint32_t wRes; +}; + +struct usbd_audio_priv { + struct audio_entity_info *table; + uint8_t num; + uint16_t uac_version; +} g_usbd_audio[CONFIG_USBDEV_MAX_BUS]; + +static int audio_class_endpoint_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t control_selector; + uint32_t sampling_freq = 0; + uint8_t ep; + + control_selector = HI_BYTE(setup->wValue); + ep = LO_BYTE(setup->wIndex); + + switch (control_selector) { + case AUDIO_EP_CONTROL_SAMPLING_FEQ: + switch (setup->bRequest) { + case AUDIO_REQUEST_SET_CUR: + memcpy((uint8_t *)&sampling_freq, *data, *len); + USB_LOG_DBG("Set ep:0x%02x %d Hz\r\n", ep, (int)sampling_freq); + usbd_audio_set_sampling_freq(busid, ep, sampling_freq); + break; + case AUDIO_REQUEST_GET_CUR: + case AUDIO_REQUEST_GET_MIN: + case AUDIO_REQUEST_GET_MAX: + case AUDIO_REQUEST_GET_RES: + sampling_freq = usbd_audio_get_sampling_freq(busid, ep); + memcpy(*data, &sampling_freq, 3); + USB_LOG_DBG("Get ep:0x%02x %d Hz\r\n", ep, (int)sampling_freq); + *len = 3; + break; + } + + break; + default: + USB_LOG_WRN("Unhandled Audio Class control selector 0x%02x\r\n", control_selector); + return -1; + } + return 0; +} + +static int audio_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("Audio Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + uint8_t entity_id; + uint8_t ep; + uint8_t subtype = 0x01; + uint8_t control_selector; + uint8_t ch; + uint8_t mute; + uint16_t volume; + int volume_db = 0; + uint32_t sampling_freq = 0; + + const char *mute_string[2] = { "off", "on" }; + + entity_id = HI_BYTE(setup->wIndex); + control_selector = HI_BYTE(setup->wValue); + ch = LO_BYTE(setup->wValue); + + ARG_UNUSED(mute_string); + + for (uint8_t i = 0; i < g_usbd_audio[busid].num; i++) { + if (g_usbd_audio[busid].table[i].bEntityId == entity_id) { + subtype = g_usbd_audio[busid].table[i].bDescriptorSubtype; + ep = g_usbd_audio[busid].table[i].ep; + break; + } + } + + if (subtype == 0x01) { + USB_LOG_ERR("Do not find subtype for 0x%02x\r\n", entity_id); + return -1; + } + + USB_LOG_DBG("Audio entity_id:%02x, subtype:%02x, cs:%02x\r\n", entity_id, subtype, control_selector); + + switch (subtype) { + case AUDIO_CONTROL_FEATURE_UNIT: + switch (control_selector) { + case AUDIO_FU_CONTROL_MUTE: + if (g_usbd_audio[busid].uac_version < 0x0200) { + switch (setup->bRequest) { + case AUDIO_REQUEST_SET_CUR: + mute = (*data)[0]; + usbd_audio_set_mute(busid, ep, ch, mute); + break; + case AUDIO_REQUEST_GET_CUR: + (*data)[0] = usbd_audio_get_mute(busid, ep, ch); + *len = 1; + break; + default: + USB_LOG_WRN("Unhandled Audio Class bRequest 0x%02x in cs 0x%02x\r\n", setup->bRequest, control_selector); + return -1; + } + } else { + switch (setup->bRequest) { + case AUDIO_REQUEST_CUR: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + (*data)[0] = usbd_audio_get_mute(busid, ep, ch); + *len = 1; + } else { + mute = (*data)[0]; + usbd_audio_set_mute(busid, ep, ch, mute); + } + break; + default: + //USB_LOG_WRN("Unhandled Audio Class bRequest 0x%02x in cs 0x%02x\r\n", setup->bRequest, control_selector); + return -1; + } + } + break; + case AUDIO_FU_CONTROL_VOLUME: + if (g_usbd_audio[busid].uac_version < 0x0200) { + switch (setup->bRequest) { + case AUDIO_REQUEST_SET_CUR: + memcpy(&volume, *data, *len); + if (volume < 0x8000) { + volume_db = volume / 256; + } else if (volume > 0x8000) { + volume_db = (0xffff - volume + 1) / -256; + } + volume_db += 128; /* 0 ~ 255 */ + USB_LOG_DBG("Set ep:0x%02x ch:%d volume:0x%04x\r\n", ep, ch, volume); + usbd_audio_set_volume(busid, ep, ch, volume_db); + break; + case AUDIO_REQUEST_GET_CUR: + volume_db = usbd_audio_get_volume(busid, ep, ch); + volume_db -= 128; + if (volume_db >= 0) { + volume = volume_db * 256; + } else { + volume = volume_db * 256 + 0xffff + 1; + } + memcpy(*data, &volume, 2); + *len = 2; + break; + case AUDIO_REQUEST_GET_MIN: + (*data)[0] = 0x00; /* -2560/256 dB */ + (*data)[1] = 0xdb; + *len = 2; + break; + case AUDIO_REQUEST_GET_MAX: + (*data)[0] = 0x00; /* 0 dB */ + (*data)[1] = 0x00; + *len = 2; + break; + case AUDIO_REQUEST_GET_RES: + (*data)[0] = 0x00; /* -256/256 dB */ + (*data)[1] = 0x01; + *len = 2; + break; + default: + USB_LOG_WRN("Unhandled Audio Class bRequest 0x%02x in cs 0x%02x\r\n", setup->bRequest, control_selector); + return -1; + } + } else { + switch (setup->bRequest) { + case AUDIO_REQUEST_CUR: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + volume_db = usbd_audio_get_volume(busid, ep, ch); + volume = volume_db; + memcpy(*data, &volume, 2); + *len = 2; + } else { + memcpy(&volume, *data, *len); + volume_db = volume; + USB_LOG_DBG("Set ep:0x%02x ch:%d volume:0x%02x\r\n", ep, ch, volume); + usbd_audio_set_volume(busid, ep, ch, volume_db); + } + break; + case AUDIO_REQUEST_RANGE: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + *((uint16_t *)(*data + 0)) = 1; + *((uint16_t *)(*data + 2)) = 0; + *((uint16_t *)(*data + 4)) = 100; + *((uint16_t *)(*data + 6)) = 1; + *len = 8; + } else { + } + break; + default: + //USB_LOG_WRN("Unhandled Audio Class bRequest 0x%02x in cs 0x%02x\r\n", setup->bRequest, control_selector); + return -1; + } + } + break; + + default: + USB_LOG_WRN("Unhandled Audio Class cs 0x%02x \r\n", control_selector); + return -1; + } + break; + case AUDIO_CONTROL_CLOCK_SOURCE: + switch (control_selector) { + case AUDIO_CS_CONTROL_SAM_FREQ: + switch (setup->bRequest) { + case AUDIO_REQUEST_CUR: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + sampling_freq = usbd_audio_get_sampling_freq(busid, ep); + memcpy(*data, &sampling_freq, 4); + USB_LOG_DBG("Get ep:0x%02x %d Hz\r\n", ep, (int)sampling_freq); + *len = 4; + } else { + memcpy(&sampling_freq, *data, setup->wLength); + USB_LOG_DBG("Set ep:0x%02x %d Hz\r\n", ep, (int)sampling_freq); + usbd_audio_set_sampling_freq(busid, ep, sampling_freq); + } + break; + case AUDIO_REQUEST_RANGE: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + uint8_t *sampling_freq_table = NULL; + uint16_t num; + + usbd_audio_get_sampling_freq_table(busid, ep, &sampling_freq_table); + num = (uint16_t)((uint16_t)(sampling_freq_table[1] << 8) | ((uint16_t)sampling_freq_table[0])); + memcpy(*data, sampling_freq_table, (12 * num + 2)); + *len = (12 * num + 2); + } else { + } + break; + default: + //USB_LOG_WRN("Unhandled Audio Class bRequest 0x%02x in cs 0x%02x\r\n", setup->bRequest, control_selector); + return -1; + } + break; + case AUDIO_CS_CONTROL_CLOCK_VALID: + if (setup->bmRequestType & USB_REQUEST_DIR_MASK) { + (*data)[0] = 1; + *len = 1; + } else { + return -1; + } + break; + + default: + //USB_LOG_WRN("Unhandled Audio Class cs 0x%02x \r\n", control_selector); + return -1; + } + break; + + default: + break; + } + return 0; +} + +static void audio_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + + break; + + case USBD_EVENT_SET_INTERFACE: { + struct usb_interface_descriptor *intf = (struct usb_interface_descriptor *)arg; + if (intf->bAlternateSetting) { + usbd_audio_open(busid, intf->bInterfaceNumber); + } else { + usbd_audio_close(busid, intf->bInterfaceNumber); + } + } + + break; + + default: + break; + } +} + +struct usbd_interface *usbd_audio_init_intf(uint8_t busid, + struct usbd_interface *intf, + uint16_t uac_version, + struct audio_entity_info *table, + uint8_t num) +{ + if (uac_version < 0x0200) { + intf->class_interface_handler = audio_class_interface_request_handler; + intf->class_endpoint_handler = audio_class_endpoint_request_handler; + intf->vendor_handler = NULL; + intf->notify_handler = audio_notify_handler; + } else { + intf->class_interface_handler = audio_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = audio_notify_handler; + } + + g_usbd_audio[busid].uac_version = uac_version; + g_usbd_audio[busid].table = table; + g_usbd_audio[busid].num = num; + + return intf; +} + +__WEAK void usbd_audio_set_volume(uint8_t busid, uint8_t ep, uint8_t ch, int volume) +{ +} + +__WEAK int usbd_audio_get_volume(uint8_t busid, uint8_t ep, uint8_t ch) +{ + return 0; +} + +__WEAK void usbd_audio_set_mute(uint8_t busid, uint8_t ep, uint8_t ch, bool mute) +{ +} + +__WEAK bool usbd_audio_get_mute(uint8_t busid, uint8_t ep, uint8_t ch) +{ + return 0; +} + +__WEAK void usbd_audio_set_sampling_freq(uint8_t busid, uint8_t ep, uint32_t sampling_freq) +{ +} + +__WEAK uint32_t usbd_audio_get_sampling_freq(uint8_t busid, uint8_t ep) +{ + return 0; +} + +__WEAK void usbd_audio_get_sampling_freq_table(uint8_t busid, uint8_t ep, uint8_t **sampling_freq_table) +{ +} diff --git a/components/drivers/usb/cherryusb/class/audio/usbd_audio.h b/components/drivers/usb/cherryusb/class/audio/usbd_audio.h new file mode 100644 index 00000000000..442405a2f97 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/audio/usbd_audio.h @@ -0,0 +1,43 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_AUDIO_H +#define USBD_AUDIO_H + +#include "usb_audio.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct audio_entity_info { + uint8_t bDescriptorSubtype; + uint8_t bEntityId; + uint8_t ep; +}; + +/* Init audio interface driver */ +struct usbd_interface *usbd_audio_init_intf(uint8_t busid, struct usbd_interface *intf, + uint16_t uac_version, + struct audio_entity_info *table, + uint8_t num); + +void usbd_audio_open(uint8_t busid, uint8_t intf); +void usbd_audio_close(uint8_t busid, uint8_t intf); + +void usbd_audio_set_volume(uint8_t busid, uint8_t ep, uint8_t ch, int volume); +int usbd_audio_get_volume(uint8_t busid, uint8_t ep, uint8_t ch); +void usbd_audio_set_mute(uint8_t busid, uint8_t ep, uint8_t ch, bool mute); +bool usbd_audio_get_mute(uint8_t busid, uint8_t ep, uint8_t ch); +void usbd_audio_set_sampling_freq(uint8_t busid, uint8_t ep, uint32_t sampling_freq); +uint32_t usbd_audio_get_sampling_freq(uint8_t busid, uint8_t ep); + +void usbd_audio_get_sampling_freq_table(uint8_t busid, uint8_t ep, uint8_t **sampling_freq_table); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_AUDIO_H */ diff --git a/components/drivers/usb/cherryusb/class/audio/usbh_audio.c b/components/drivers/usb/cherryusb/class/audio/usbh_audio.c new file mode 100644 index 00000000000..8687e9a4a67 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/audio/usbh_audio.c @@ -0,0 +1,483 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_audio.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_audio" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/audio%d" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ +#define DESC_bDescriptorSubType 2 /** Descriptor subtype offset */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +#ifndef CONFIG_USBHOST_MAX_AUDIO_CLASS +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 4 +#endif + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_audio_buf[128]; + +static struct usbh_audio g_audio_class[CONFIG_USBHOST_MAX_AUDIO_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_audio *usbh_audio_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_AUDIO_CLASS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_audio_class[devno], 0, sizeof(struct usbh_audio)); + g_audio_class[devno].minor = devno; + return &g_audio_class[devno]; + } + } + return NULL; +} + +static void usbh_audio_class_free(struct usbh_audio *audio_class) +{ + int devno = audio_class->minor; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(audio_class, 0, sizeof(struct usbh_audio)); +} + +int usbh_audio_open(struct usbh_audio *audio_class, const char *name, uint32_t samp_freq) +{ + struct usb_setup_packet *setup = audio_class->hport->setup; + struct usb_endpoint_descriptor *ep_desc; + uint8_t mult; + uint16_t mps; + int ret; + uint8_t intf = 0xff; + uint8_t altsetting = 1; + + if (audio_class->is_opened) { + return 0; + } + + for (uint8_t i = 0; i < audio_class->module_num; i++) { + if (strcmp(name, audio_class->module[i].name) == 0) { + for (uint8_t j = 0; j < audio_class->num_of_intf_altsettings; j++) { + for (uint8_t k = 0; k < audio_class->module[i].altsetting[j].sampfreq_num; k++) { + if (audio_class->module[i].altsetting[j].sampfreq[k] == samp_freq) { + intf = audio_class->module[i].data_intf; + altsetting = j; + goto freq_found; + } + } + } + } + } + + return -USB_ERR_NODEV; + +freq_found: + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = altsetting; + setup->wIndex = intf; + setup->wLength = 0; + + ret = usbh_control_transfer(audio_class->hport, setup, NULL); + if (ret < 0) { + return ret; + } + + ep_desc = &audio_class->hport->config.intf[intf].altsetting[altsetting].ep[0].ep_desc; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_ENDPOINT; + setup->bRequest = AUDIO_REQUEST_SET_CUR; + setup->wValue = (AUDIO_EP_CONTROL_SAMPLING_FEQ << 8) | 0x00; + setup->wIndex = ep_desc->bEndpointAddress; + setup->wLength = 3; + + memcpy(g_audio_buf, &samp_freq, 3); + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + if (ret < 0) { + return ret; + } + + mult = (ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT; + mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK; + if (ep_desc->bEndpointAddress & 0x80) { + audio_class->isoin_mps = mps * (mult + 1); + USBH_EP_INIT(audio_class->isoin, ep_desc); + } else { + audio_class->isoout_mps = mps * (mult + 1); + USBH_EP_INIT(audio_class->isoout, ep_desc); + } + + USB_LOG_INFO("Open audio module :%s, altsetting: %u\r\n", name, altsetting); + audio_class->is_opened = true; + return ret; +} + +int usbh_audio_close(struct usbh_audio *audio_class, const char *name) +{ + struct usb_setup_packet *setup = audio_class->hport->setup; + struct usb_endpoint_descriptor *ep_desc; + int ret; + uint8_t intf = 0xff; + uint8_t altsetting = 1; + + for (size_t i = 0; i < audio_class->module_num; i++) { + if (strcmp(name, audio_class->module[i].name) == 0) { + intf = audio_class->module[i].data_intf; + } + } + + if (intf == 0xff) { + return -USB_ERR_NODEV; + } + + USB_LOG_INFO("Close audio module :%s\r\n", name); + audio_class->is_opened = false; + + ep_desc = &audio_class->hport->config.intf[intf].altsetting[altsetting].ep[0].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + if (audio_class->isoin) { + audio_class->isoin = NULL; + } + } else { + if (audio_class->isoout) { + audio_class->isoout = NULL; + } + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = 0; + setup->wIndex = intf; + setup->wLength = 0; + + ret = usbh_control_transfer(audio_class->hport, setup, NULL); + + return ret; +} + +int usbh_audio_set_volume(struct usbh_audio *audio_class, const char *name, uint8_t ch, uint8_t volume) +{ + struct usb_setup_packet *setup = audio_class->hport->setup; + int ret; + uint8_t intf = 0xff; + uint8_t feature_id = 0xff; + uint16_t volume_hex; + + for (size_t i = 0; i < audio_class->module_num; i++) { + if (strcmp(name, audio_class->module[i].name) == 0) { + intf = audio_class->ctrl_intf; + feature_id = audio_class->module[i].feature_unit_id; + } + } + + if (intf == 0xff) { + return -USB_ERR_NODEV; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_SET_CUR; + setup->wValue = (AUDIO_FU_CONTROL_VOLUME << 8) | ch; + setup->wIndex = (feature_id << 8) | intf; + setup->wLength = 2; + + volume_hex = -0xDB00 / 100 * volume + 0xdb00; + + memcpy(g_audio_buf, &volume_hex, 2); + ret = usbh_control_transfer(audio_class->hport, setup, NULL); + + return ret; +} + +int usbh_audio_set_mute(struct usbh_audio *audio_class, const char *name, uint8_t ch, bool mute) +{ + struct usb_setup_packet *setup = audio_class->hport->setup; + int ret; + uint8_t intf = 0xff; + uint8_t feature_id = 0xff; + + for (size_t i = 0; i < audio_class->module_num; i++) { + if (strcmp(name, audio_class->module[i].name) == 0) { + intf = audio_class->ctrl_intf; + feature_id = audio_class->module[i].feature_unit_id; + } + } + + if (intf == 0xff) { + return -USB_ERR_NODEV; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = AUDIO_REQUEST_SET_CUR; + setup->wValue = (AUDIO_FU_CONTROL_MUTE << 8) | ch; + setup->wIndex = (feature_id << 8) | intf; + setup->wLength = 1; + + memcpy(g_audio_buf, &mute, 1); + ret = usbh_control_transfer(audio_class->hport, setup, g_audio_buf); + + return ret; +} + +void usbh_audio_list_module(struct usbh_audio *audio_class) +{ + USB_LOG_INFO("============= Audio module information ===================\r\n"); + USB_LOG_RAW("bcdADC :%04x\r\n", audio_class->bcdADC); + USB_LOG_RAW("Num of modules :%u\r\n", audio_class->module_num); + USB_LOG_RAW("Num of altsettings:%u\r\n", audio_class->num_of_intf_altsettings); + + for (uint8_t i = 0; i < audio_class->module_num; i++) { + USB_LOG_RAW(" module name :%s\r\n", audio_class->module[i].name); + USB_LOG_RAW(" module feature unit id :%d\r\n", audio_class->module[i].feature_unit_id); + + for (uint8_t j = 0; j < audio_class->num_of_intf_altsettings; j++) { + if (j == 0) { + USB_LOG_RAW(" Ingore altsetting 0\r\n"); + continue; + } + USB_LOG_RAW(" Altsetting %u\r\n", j); + USB_LOG_RAW(" module channels :%u\r\n", audio_class->module[i].altsetting[j].channels); + //USB_LOG_RAW(" module format_type :%u\r\n",audio_class->module[i].altsetting[j].format_type); + USB_LOG_RAW(" module bitresolution :%u\r\n", audio_class->module[i].altsetting[j].bitresolution); + USB_LOG_RAW(" module sampfreq num :%u\r\n", audio_class->module[i].altsetting[j].sampfreq_num); + + for (uint8_t k = 0; k < audio_class->module[i].altsetting[j].sampfreq_num; k++) { + USB_LOG_RAW(" module sampfreq :%d hz\r\n", audio_class->module[i].altsetting[j].sampfreq[k]); + } + } + } + + USB_LOG_INFO("============= Audio module information ===================\r\n"); +} + +static int usbh_audio_ctrl_connect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret; + uint8_t cur_iface = 0xff; + uint8_t cur_iface_count = 0xff; + uint8_t cur_alt_setting = 0xff; + uint8_t input_offset = 0; + uint8_t output_offset = 0; + uint8_t feature_unit_offset = 0; + uint8_t format_offset = 0; + uint8_t *p; + + struct usbh_audio *audio_class = usbh_audio_class_alloc(); + if (audio_class == NULL) { + USB_LOG_ERR("Fail to alloc audio_class\r\n"); + return -USB_ERR_NOMEM; + } + + audio_class->hport = hport; + audio_class->ctrl_intf = intf; + audio_class->num_of_intf_altsettings = hport->config.intf[intf + 1].altsetting_num; + + hport->config.intf[intf].priv = audio_class; + + p = hport->raw_config_desc; + while (p[DESC_bLength]) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION: + cur_iface_count = p[3]; + break; + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + break; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + break; + case AUDIO_INTERFACE_DESCRIPTOR_TYPE: + if (cur_iface == audio_class->ctrl_intf) { + switch (p[DESC_bDescriptorSubType]) { + case AUDIO_CONTROL_HEADER: { + struct audio_cs_if_ac_header_descriptor *desc = (struct audio_cs_if_ac_header_descriptor *)p; + audio_class->bcdADC = desc->bcdADC; + audio_class->bInCollection = desc->bInCollection; + } break; + case AUDIO_CONTROL_INPUT_TERMINAL: { + struct audio_cs_if_ac_input_terminal_descriptor *desc = (struct audio_cs_if_ac_input_terminal_descriptor *)p; + + audio_class->module[input_offset].input_terminal_id = desc->bTerminalID; + audio_class->module[input_offset].input_terminal_type = desc->wTerminalType; + audio_class->module[input_offset].input_channel_config = desc->wChannelConfig; + + if (desc->wTerminalType == AUDIO_TERMINAL_STREAMING) { + audio_class->module[input_offset].terminal_link_id = desc->bTerminalID; + } + if (desc->wTerminalType == AUDIO_INTERM_MIC) { + audio_class->module[input_offset].name = "mic"; + } + input_offset++; + } break; + break; + case AUDIO_CONTROL_OUTPUT_TERMINAL: { + struct audio_cs_if_ac_output_terminal_descriptor *desc = (struct audio_cs_if_ac_output_terminal_descriptor *)p; + audio_class->module[output_offset].output_terminal_id = desc->bTerminalID; + audio_class->module[output_offset].output_terminal_type = desc->wTerminalType; + if (desc->wTerminalType == AUDIO_TERMINAL_STREAMING) { + audio_class->module[output_offset].terminal_link_id = desc->bTerminalID; + } + if (desc->wTerminalType == AUDIO_OUTTERM_SPEAKER) { + audio_class->module[output_offset].name = "speaker"; + } + output_offset++; + } break; + case AUDIO_CONTROL_FEATURE_UNIT: { + struct audio_cs_if_ac_feature_unit_descriptor *desc = (struct audio_cs_if_ac_feature_unit_descriptor *)p; + audio_class->module[feature_unit_offset].feature_unit_id = desc->bUnitID; + audio_class->module[feature_unit_offset].feature_unit_controlsize = desc->bControlSize; + + for (uint8_t j = 0; j < desc->bControlSize; j++) { + audio_class->module[feature_unit_offset].feature_unit_controls[j] = p[6 + j]; + } + feature_unit_offset++; + } break; + case AUDIO_CONTROL_PROCESSING_UNIT: + + break; + default: + break; + } + } else if ((cur_iface < (audio_class->ctrl_intf + cur_iface_count)) && (cur_iface > audio_class->ctrl_intf)) { + switch (p[DESC_bDescriptorSubType]) { + case AUDIO_STREAMING_GENERAL: + + break; + case AUDIO_STREAMING_FORMAT_TYPE: { + struct audio_cs_if_as_format_type_descriptor *desc = (struct audio_cs_if_as_format_type_descriptor *)p; + + audio_class->module[format_offset].data_intf = cur_iface; + audio_class->module[format_offset].altsetting[cur_alt_setting].channels = desc->bNrChannels; + audio_class->module[format_offset].altsetting[cur_alt_setting].format_type = desc->bFormatType; + audio_class->module[format_offset].altsetting[cur_alt_setting].bitresolution = desc->bBitResolution; + audio_class->module[format_offset].altsetting[cur_alt_setting].sampfreq_num = desc->bSamFreqType; + + for (uint8_t j = 0; j < desc->bSamFreqType; j++) { + audio_class->module[format_offset].altsetting[cur_alt_setting].sampfreq[j] = (uint32_t)(p[10 + j] << 16) | + (uint32_t)(p[9 + j] << 8) | + (uint32_t)(p[8 + j] << 0); + } + if (cur_alt_setting == (hport->config.intf[intf + 1].altsetting_num - 1)) { + format_offset++; + } + } break; + default: + break; + } + } + break; + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + + if ((input_offset != output_offset) && (input_offset != feature_unit_offset) && (input_offset != format_offset)) { + return -USB_ERR_INVAL; + } + + audio_class->module_num = input_offset; + + for (size_t i = 0; i < audio_class->module_num; i++) { + ret = usbh_audio_close(audio_class, audio_class->module[i].name); + if (ret < 0) { + USB_LOG_ERR("Fail to close audio module :%s\r\n", audio_class->module[i].name); + return ret; + } + } + + usbh_audio_list_module(audio_class); + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, audio_class->minor); + USB_LOG_INFO("Register Audio Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_audio_run(audio_class); + return 0; +} + +static int usbh_audio_ctrl_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_audio *audio_class = (struct usbh_audio *)hport->config.intf[intf].priv; + + if (audio_class) { + if (audio_class->isoin) { + } + + if (audio_class->isoout) { + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister Audio Class:%s\r\n", hport->config.intf[intf].devname); + usbh_audio_stop(audio_class); + } + + usbh_audio_class_free(audio_class); + } + + return ret; +} + +static int usbh_audio_data_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return 0; +} + +static int usbh_audio_data_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + return 0; +} + +__WEAK void usbh_audio_run(struct usbh_audio *audio_class) +{ +} + +__WEAK void usbh_audio_stop(struct usbh_audio *audio_class) +{ +} + +const struct usbh_class_driver audio_ctrl_class_driver = { + .driver_name = "audio_ctrl", + .connect = usbh_audio_ctrl_connect, + .disconnect = usbh_audio_ctrl_disconnect +}; + +const struct usbh_class_driver audio_streaming_class_driver = { + .driver_name = "audio_streaming", + .connect = usbh_audio_data_connect, + .disconnect = usbh_audio_data_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info audio_ctrl_intf_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS, + .class = USB_DEVICE_CLASS_AUDIO, + .subclass = AUDIO_SUBCLASS_AUDIOCONTROL, + .protocol = 0x00, + .id_table = NULL, + .class_driver = &audio_ctrl_class_driver +}; + +CLASS_INFO_DEFINE const struct usbh_class_info audio_streaming_intf_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS, + .class = USB_DEVICE_CLASS_AUDIO, + .subclass = AUDIO_SUBCLASS_AUDIOSTREAMING, + .protocol = 0x00, + .id_table = NULL, + .class_driver = &audio_streaming_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/audio/usbh_audio.h b/components/drivers/usb/cherryusb/class/audio/usbh_audio.h new file mode 100644 index 00000000000..038a8f7e935 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/audio/usbh_audio.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_AUDIO_H +#define USBH_AUDIO_H + +#include "usb_audio.h" + +struct usbh_audio_format_type { + uint8_t channels; + uint8_t format_type; + uint8_t bitresolution; + uint8_t sampfreq_num; + uint32_t sampfreq[3]; +}; + +/** + * bSourceID in feature_unit = input_terminal_id + * bSourceID in output_terminal = feature_unit_id + * terminal_link_id = input_terminal_id or output_terminal_id (if input_terminal_type or output_terminal_type is 0x0101) + * + * +*/ +struct usbh_audio_module { + const char *name; + uint8_t data_intf; + uint8_t input_terminal_id; + uint16_t input_terminal_type; + uint16_t input_channel_config; + uint8_t output_terminal_id; + uint16_t output_terminal_type; + uint8_t feature_unit_id; + uint8_t feature_unit_controlsize; + uint8_t feature_unit_controls[8]; + uint8_t terminal_link_id; + struct usbh_audio_format_type altsetting[CONFIG_USBHOST_MAX_INTF_ALTSETTINGS]; +}; + +struct usbh_audio { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *isoin; /* ISO IN endpoint */ + struct usb_endpoint_descriptor *isoout; /* ISO OUT endpoint */ + + uint8_t ctrl_intf; /* interface number */ + uint8_t minor; + uint16_t isoin_mps; + uint16_t isoout_mps; + bool is_opened; + uint16_t bcdADC; + uint8_t bInCollection; + uint8_t num_of_intf_altsettings; + struct usbh_audio_module module[2]; + uint8_t module_num; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_audio_open(struct usbh_audio *audio_class, const char *name, uint32_t samp_freq); +int usbh_audio_close(struct usbh_audio *audio_class, const char *name); +int usbh_audio_set_volume(struct usbh_audio *audio_class, const char *name, uint8_t ch, uint8_t volume); +int usbh_audio_set_mute(struct usbh_audio *audio_class, const char *name, uint8_t ch, bool mute); + +void usbh_audio_run(struct usbh_audio *audio_class); +void usbh_audio_stop(struct usbh_audio *audio_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_AUDIO_H */ diff --git a/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h b/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h new file mode 100644 index 00000000000..b8a544f3f3e --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usb_cdc.h @@ -0,0 +1,698 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_CDC_H +#define USB_CDC_H + +/*------------------------------------------------------------------------------ + * Definitions based on usbcdc11.pdf (www.usb.org) + *----------------------------------------------------------------------------*/ +/* Communication device class specification version 1.10 */ +#define CDC_V1_10 0x0110U +// Communication device class specification version 1.2 +#define CDC_V1_2_0 0x0120U + +/* Communication interface class code */ +/* (usbcdc11.pdf, 4.2, Table 15) */ +#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02U + +/* Communication interface class subclass codes */ +/* (usbcdc11.pdf, 4.3, Table 16) */ +#define CDC_SUBCLASS_NONE 0x00 /* Reserved */ +#define CDC_SUBCLASS_DLC 0x01 /* Direct Line Control Model */ +#define CDC_SUBCLASS_ACM 0x02 /* Abstract Control Model */ +#define CDC_SUBCLASS_TCM 0x03 /* Telephone Control Model */ +#define CDC_SUBCLASS_MCM 0x04 /* Multi-Channel Control Model */ +#define CDC_SUBCLASS_CAPI 0x05 /* CAPI Control Model */ +#define CDC_SUBCLASS_ECM 0x06 /* Ethernet Networking Control Model */ +#define CDC_SUBCLASS_ATM 0x07 /* ATM Networking Control Model */ + /* 0x08-0x0d Reserved (future use) */ +#define CDC_SUBCLASS_MBIM 0x0e /* MBIM Control Model */ + /* 0x0f-0x7f Reserved (future use) */ + /* 0x80-0xfe Reserved (vendor specific) */ + +#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01U +#define CDC_ABSTRACT_CONTROL_MODEL 0x02U +#define CDC_TELEPHONE_CONTROL_MODEL 0x03U +#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04U +#define CDC_CAPI_CONTROL_MODEL 0x05U +#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06U +#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07U +#define CDC_WIRELESS_HANDSET_CONTROL_MODEL 0x08U +#define CDC_DEVICE_MANAGEMENT 0x09U +#define CDC_MOBILE_DIRECT_LINE_MODEL 0x0AU +#define CDC_OBEX 0x0BU +#define CDC_ETHERNET_EMULATION_MODEL 0x0CU +#define CDC_NETWORK_CONTROL_MODEL 0x0DU + +/* Communication interface class control protocol codes */ +/* (usbcdc11.pdf, 4.4, Table 17) */ +#define CDC_COMMON_PROTOCOL_NONE 0x00U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS 0x01U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101 0x02U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO 0x03U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_GSM_707 0x04U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_3GPP_27007 0x05U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_CDMA 0x06U +#define CDC_COMMON_PROTOCOL_ETHERNET_EMULATION_MODEL 0x07U +// NCM Communication Interface Protocol Codes +// (usbncm10.pdf, 4.2, Table 4-2) +#define CDC_NCM_PROTOCOL_NONE 0x00U +#define CDC_NCM_PROTOCOL_OEM 0xFEU + +/* Data interface class code */ +/* (usbcdc11.pdf, 4.5, Table 18) */ +#define CDC_DATA_INTERFACE_CLASS 0x0A + +/* Data Interface Sub-Class Codes ********************************************/ +#define CDC_DATA_SUBCLASS_NONE 0x00 + +/* Data interface class protocol codes */ +/* (usbcdc11.pdf, 4.7, Table 19) */ +#define CDC_DATA_PROTOCOL_ISDN_BRI 0x30 +#define CDC_DATA_PROTOCOL_HDLC 0x31 +#define CDC_DATA_PROTOCOL_TRANSPARENT 0x32 +#define CDC_DATA_PROTOCOL_Q921_MANAGEMENT 0x50 +#define CDC_DATA_PROTOCOL_Q921_DATA_LINK 0x51 +#define CDC_DATA_PROTOCOL_Q921_MULTIPLEXOR 0x52 +#define CDC_DATA_PROTOCOL_V42 0x90 +#define CDC_DATA_PROTOCOL_EURO_ISDN 0x91 +#define CDC_DATA_PROTOCOL_V24_RATE_ADAPTATION 0x92 +#define CDC_DATA_PROTOCOL_CAPI 0x93 +#define CDC_DATA_PROTOCOL_HOST_BASED_DRIVER 0xFD +#define CDC_DATA_PROTOCOL_DESCRIBED_IN_PUFD 0xFE + +/* Type values for bDescriptorType field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 24) */ +#define CDC_CS_INTERFACE 0x24 +#define CDC_CS_ENDPOINT 0x25 + +/* Type values for bDescriptorSubtype field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 25) */ +#define CDC_FUNC_DESC_HEADER 0x00 +#define CDC_FUNC_DESC_CALL_MANAGEMENT 0x01 +#define CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT 0x02 +#define CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT 0x03 +#define CDC_FUNC_DESC_TELEPHONE_RINGER 0x04 +#define CDC_FUNC_DESC_REPORTING_CAPABILITIES 0x05 +#define CDC_FUNC_DESC_UNION 0x06 +#define CDC_FUNC_DESC_COUNTRY_SELECTION 0x07 +#define CDC_FUNC_DESC_TELEPHONE_OPERATIONAL_MODES 0x08 +#define CDC_FUNC_DESC_USB_TERMINAL 0x09 +#define CDC_FUNC_DESC_NETWORK_CHANNEL 0x0A +#define CDC_FUNC_DESC_PROTOCOL_UNIT 0x0B +#define CDC_FUNC_DESC_EXTENSION_UNIT 0x0C +#define CDC_FUNC_DESC_MULTI_CHANNEL_MANAGEMENT 0x0D +#define CDC_FUNC_DESC_CAPI_CONTROL_MANAGEMENT 0x0E +#define CDC_FUNC_DESC_ETHERNET_NETWORKING 0x0F +#define CDC_FUNC_DESC_ATM_NETWORKING 0x10 +#define CDC_FUNC_DESC_WIRELESS_HANDSET_CONTROL_MODEL 0x11 +#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL 0x12 +#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL_DETAIL 0x13 +#define CDC_FUNC_DESC_DEVICE_MANAGEMENT_MODEL 0x14 +#define CDC_FUNC_DESC_OBEX 0x15 +#define CDC_FUNC_DESC_COMMAND_SET 0x16 +#define CDC_FUNC_DESC_COMMAND_SET_DETAIL 0x17 +#define CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL 0x18 +#define CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER 0x19 +#define CDC_FUNC_DESC_NCM 0x1A + +/* CDC class-specific request codes */ +/* (usbcdc11.pdf, 6.2, Table 46) */ +/* see Table 45 for info about the specific requests. */ +#define CDC_REQUEST_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_REQUEST_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_REQUEST_SET_COMM_FEATURE 0x02 +#define CDC_REQUEST_GET_COMM_FEATURE 0x03 +#define CDC_REQUEST_CLEAR_COMM_FEATURE 0x04 +#define CDC_REQUEST_SET_AUX_LINE_STATE 0x10 +#define CDC_REQUEST_SET_HOOK_STATE 0x11 +#define CDC_REQUEST_PULSE_SETUP 0x12 +#define CDC_REQUEST_SEND_PULSE 0x13 +#define CDC_REQUEST_SET_PULSE_TIME 0x14 +#define CDC_REQUEST_RING_AUX_JACK 0x15 +#define CDC_REQUEST_SET_LINE_CODING 0x20 +#define CDC_REQUEST_GET_LINE_CODING 0x21 +#define CDC_REQUEST_SET_CONTROL_LINE_STATE 0x22 +#define CDC_REQUEST_SEND_BREAK 0x23 +#define CDC_REQUEST_SET_RINGER_PARMS 0x30 +#define CDC_REQUEST_GET_RINGER_PARMS 0x31 +#define CDC_REQUEST_SET_OPERATION_PARMS 0x32 +#define CDC_REQUEST_GET_OPERATION_PARMS 0x33 +#define CDC_REQUEST_SET_LINE_PARMS 0x34 +#define CDC_REQUEST_GET_LINE_PARMS 0x35 +#define CDC_REQUEST_DIAL_DIGITS 0x36 +#define CDC_REQUEST_SET_UNIT_PARAMETER 0x37 +#define CDC_REQUEST_GET_UNIT_PARAMETER 0x38 +#define CDC_REQUEST_CLEAR_UNIT_PARAMETER 0x39 +#define CDC_REQUEST_GET_PROFILE 0x3A +#define CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define CDC_REQUEST_SET_ETHERNET_PMP_FILTER 0x41 +#define CDC_REQUEST_GET_ETHERNET_PMP_FILTER 0x42 +#define CDC_REQUEST_SET_ETHERNET_PACKET_FILTER 0x43 +#define CDC_REQUEST_GET_ETHERNET_STATISTIC 0x44 +#define CDC_REQUEST_SET_ATM_DATA_FORMAT 0x50 +#define CDC_REQUEST_GET_ATM_DEVICE_STATISTICS 0x51 +#define CDC_REQUEST_SET_ATM_DEFAULT_VC 0x52 +#define CDC_REQUEST_GET_ATM_VC_STATISTICS 0x53 +#define CDC_REQUEST_GET_NTB_PARAMETERS 0x80 +#define CDC_REQUEST_GET_NET_ADDRESS 0x81 +#define CDC_REQUEST_SET_NET_ADDRESS 0x82 +#define CDC_REQUEST_GET_NTB_FORMAT 0x83 +#define CDC_REQUEST_SET_NTB_FORMAT 0x84 +#define CDC_REQUEST_GET_NTB_INPUT_SIZE 0x85 +#define CDC_REQUEST_SET_NTB_INPUT_SIZE 0x86 +#define CDC_REQUEST_GET_MAX_DATAGRAM_SIZE 0x87 +#define CDC_REQUEST_SET_MAX_DATAGRAM_SIZE 0x88 +#define CDC_REQUEST_GET_CRC_MODE 0x89 +#define CDC_REQUEST_SET_CRC_MODE 0x90 + +/* Communication feature selector codes */ +/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */ +#define CDC_ABSTRACT_STATE 0x01 +#define CDC_COUNTRY_SETTING 0x02 + +/** Control Signal Bitmap Values for SetControlLineState */ +#define SET_CONTROL_LINE_STATE_RTS 0x02 +#define SET_CONTROL_LINE_STATE_DTR 0x01 + +/* Feature Status returned for ABSTRACT_STATE Selector */ +/* (usbcdc11.pdf, 6.2.3, Table 48) */ +#define CDC_IDLE_SETTING (1 << 0) +#define CDC_DATA_MULTPLEXED_STATE (1 << 1) + +/* Control signal bitmap values for the SetControlLineState request */ +/* (usbcdc11.pdf, 6.2.14, Table 51) */ +#define CDC_DTE_PRESENT (1 << 0) +#define CDC_ACTIVATE_CARRIER (1 << 1) + +/* CDC class-specific notification codes */ +/* (usbcdc11.pdf, 6.3, Table 68) */ +/* see Table 67 for Info about class-specific notifications */ +#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00 +#define CDC_RESPONSE_AVAILABLE 0x01 +#define CDC_AUX_JACK_HOOK_STATE 0x08 +#define CDC_RING_DETECT 0x09 +#define CDC_NOTIFICATION_SERIAL_STATE 0x20 +#define CDC_CALL_STATE_CHANGE 0x28 +#define CDC_LINE_STATE_CHANGE 0x29 +#define CDC_CONNECTION_SPEED_CHANGE 0x2A + +/* UART state bitmap values (Serial state notification). */ +/* (usbcdc11.pdf, 6.3.5, Table 69) */ +#define CDC_SERIAL_STATE_OVERRUN (1 << 6) /* receive data overrun error has occurred */ +#define CDC_SERIAL_STATE_OVERRUN_Pos (6) +#define CDC_SERIAL_STATE_OVERRUN_Msk (1 << CDC_SERIAL_STATE_OVERRUN_Pos) +#define CDC_SERIAL_STATE_PARITY (1 << 5) /* parity error has occurred */ +#define CDC_SERIAL_STATE_PARITY_Pos (5) +#define CDC_SERIAL_STATE_PARITY_Msk (1 << CDC_SERIAL_STATE_PARITY_Pos) +#define CDC_SERIAL_STATE_FRAMING (1 << 4) /* framing error has occurred */ +#define CDC_SERIAL_STATE_FRAMING_Pos (4) +#define CDC_SERIAL_STATE_FRAMING_Msk (1 << CDC_SERIAL_STATE_FRAMING_Pos) +#define CDC_SERIAL_STATE_RING (1 << 3) /* state of ring signal detection */ +#define CDC_SERIAL_STATE_RING_Pos (3) +#define CDC_SERIAL_STATE_RING_Msk (1 << CDC_SERIAL_STATE_RING_Pos) +#define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */ +#define CDC_SERIAL_STATE_BREAK_Pos (2) +#define CDC_SERIAL_STATE_BREAK_Msk (1 << CDC_SERIAL_STATE_BREAK_Pos) +#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) /* state of transmission carrier */ +#define CDC_SERIAL_STATE_TX_CARRIER_Pos (1) +#define CDC_SERIAL_STATE_TX_CARRIER_Msk (1 << CDC_SERIAL_STATE_TX_CARRIER_Pos) +#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) /* state of receiver carrier */ +#define CDC_SERIAL_STATE_RX_CARRIER_Pos (0) +#define CDC_SERIAL_STATE_RX_CARRIER_Msk (1 << CDC_SERIAL_STATE_RX_CARRIER_Pos) + +#define CDC_ECM_XMIT_OK (1 << 0) +#define CDC_ECM_RVC_OK (1 << 1) +#define CDC_ECM_XMIT_ERROR (1 << 2) +#define CDC_ECM_RCV_ERROR (1 << 3) +#define CDC_ECM_RCV_NO_BUFFER (1 << 4) +#define CDC_ECM_DIRECTED_BYTES_XMIT (1 << 5) +#define CDC_ECM_DIRECTED_FRAMES_XMIT (1 << 6) +#define CDC_ECM_MULTICAST_BYTES_XMIT (1 << 7) +#define CDC_ECM_MULTICAST_FRAMES_XMIT (1 << 8) +#define CDC_ECM_BROADCAST_BYTES_XMIT (1 << 9) +#define CDC_ECM_BROADCAST_FRAMES_XMIT (1 << 10) +#define CDC_ECM_DIRECTED_BYTES_RCV (1 << 11) +#define CDC_ECM_DIRECTED_FRAMES_RCV (1 << 12) +#define CDC_ECM_MULTICAST_BYTES_RCV (1 << 13) +#define CDC_ECM_MULTICAST_FRAMES_RCV (1 << 14) +#define CDC_ECM_BROADCAST_BYTES_RCV (1 << 15) +#define CDC_ECM_BROADCAST_FRAMES_RCV (1 << 16) +#define CDC_ECM_RCV_CRC_ERROR (1 << 17) +#define CDC_ECM_TRANSMIT_QUEUE_LENGTH (1 << 18) +#define CDC_ECM_RCV_ERROR_ALIGNMENT (1 << 19) +#define CDC_ECM_XMIT_ONE_COLLISION (1 << 20) +#define CDC_ECM_XMIT_MORE_COLLISIONS (1 << 21) +#define CDC_ECM_XMIT_DEFERRED (1 << 22) +#define CDC_ECM_XMIT_MAX_COLLISIONS (1 << 23) +#define CDC_ECM_RCV_OVERRUN (1 << 24) +#define CDC_ECM_XMIT_UNDERRUN (1 << 25) +#define CDC_ECM_XMIT_HEARTBEAT_FAILURE (1 << 26) +#define CDC_ECM_XMIT_TIMES_CRS_LOST (1 << 27) +#define CDC_ECM_XMIT_LATE_COLLISIONS (1 << 28) + +#define CDC_ECM_MAC_STR_DESC (uint8_t *)"010202030000" +#define CDC_ECM_MAC_ADDR0 0x00U /* 01 */ +#define CDC_ECM_MAC_ADDR1 0x02U /* 02 */ +#define CDC_ECM_MAC_ADDR2 0x02U /* 03 */ +#define CDC_ECM_MAC_ADDR3 0x03U /* 00 */ +#define CDC_ECM_MAC_ADDR4 0x00U /* 00 */ +#define CDC_ECM_MAC_ADDR5 0x00U /* 00 */ + +#define CDC_ECM_NET_DISCONNECTED 0x00U +#define CDC_ECM_NET_CONNECTED 0x01U + +#define CDC_ECM_ETH_STATS_RESERVED 0xE0U +#define CDC_ECM_BMREQUEST_TYPE_ECM 0xA1U + +#define CDC_ECM_CONNECT_SPEED_UPSTREAM 0x004C4B40U /* 5Mbps */ +#define CDC_ECM_CONNECT_SPEED_DOWNSTREAM 0x004C4B40U /* 5Mbps */ + +#define CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION 0x00 +#define CDC_ECM_NOTIFY_CODE_RESPONSE_AVAILABLE 0x01 +#define CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE 0x2A + +#define CDC_NCM_NTH16_SIGNATURE 0x484D434E +#define CDC_NCM_NDP16_SIGNATURE_NCM0 0x304D434E +#define CDC_NCM_NDP16_SIGNATURE_NCM1 0x314D434E + +/*------------------------------------------------------------------------------ + * Structures based on usbcdc11.pdf (www.usb.org) + *----------------------------------------------------------------------------*/ + +/* Header functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.1) */ +/* This header must precede any list of class-specific descriptors. */ +struct cdc_header_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */ + uint16_t bcdCDC; /* USB CDC specification release version */ +} __PACKED; + +/* Call management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.2) */ +/* Describes the processing of calls for the communication class interface. */ +struct cdc_call_management_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities that this configuration supports */ + uint8_t bDataInterface; /* interface number of the data class interface used for call management (optional) */ +} __PACKED; + +/* Abstract control management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.3) */ +/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */ +struct cdc_abstract_control_management_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities supported by this configuration */ +} __PACKED; + +/* Union functional descriptors */ +/* (usbcdc11.pdf, 5.2.3.8) */ +/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */ +struct cdc_union_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* union functional descriptor subtype */ + uint8_t bMasterInterface; /* interface number designated as master */ +} __PACKED; + +/* Union functional descriptors with one slave interface */ +/* (usbcdc11.pdf, 5.2.3.8) */ +struct cdc_union_1slave_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bControlInterface; + uint8_t bSubordinateInterface0; +} __PACKED; + +/* Line coding structure for GET_LINE_CODING / SET_LINE_CODING class requests*/ +/* Format of the data returned when a GetLineCoding request is received */ +/* (usbcdc11.pdf, 6.2.13) */ +struct cdc_line_coding { + uint32_t dwDTERate; /* Data terminal rate in bits per second */ + uint8_t bCharFormat; /* Number of stop bits */ + uint8_t bParityType; /* Parity bit type */ + uint8_t bDataBits; /* Number of data bits */ +} __PACKED; + +/** Data structure for the notification about SerialState */ +struct cdc_acm_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint16_t data; +} __PACKED; + +/** Ethernet Networking Functional Descriptor */ +struct cdc_eth_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t iMACAddress; + uint32_t bmEthernetStatistics; + uint16_t wMaxSegmentSize; + uint16_t wNumberMCFilters; + uint8_t bNumberPowerFilters; +} __PACKED; + +struct cdc_eth_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint8_t data[8]; +} __PACKED; + +struct cdc_ncm_ntb_parameters { + uint16_t wLength; + uint16_t bmNtbFormatsSupported; + uint32_t dwNtbInMaxSize; + uint16_t wNdbInDivisor; + uint16_t wNdbInPayloadRemainder; + uint16_t wNdbInAlignment; + uint16_t wReserved; + uint32_t dwNtbOutMaxSize; + uint16_t wNdbOutDivisor; + uint16_t wNdbOutPayloadRemainder; + uint16_t wNdbOutAlignment; + uint16_t wNtbOutMaxDatagrams; +}; + +struct cdc_ncm_nth16 { + uint32_t dwSignature; + uint16_t wHeaderLength; + uint16_t wSequence; + uint16_t wBlockLength; + uint16_t wNdpIndex; +}; + +struct cdc_ncm_ndp16_datagram { + uint16_t wDatagramIndex; + uint16_t wDatagramLength; +}; + +struct cdc_ncm_ndp16 { + uint32_t dwSignature; + uint16_t wLength; + uint16_t wNextNdpIndex; + struct cdc_ncm_ndp16_datagram datagram[]; +}; + +/*Length of template descriptor: 66 bytes*/ +#define CDC_ACM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_ACM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_ABSTRACT_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_CALL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + (uint8_t)(bFirstInterface + 1), /* bDataInterface */ \ + 0x04, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x02, /* bmCapabilities */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x08, 0x00, /* wMaxPacketSize */ \ + 0x0a, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +/*Length of template descriptor: 66 bytes*/ +#define CDC_RNDIS_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_RNDIS_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_WIRELESS, /* bFunctionClass */ \ + CDC_DIRECT_LINE_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_WIRELESS, /* bInterfaceClass */ \ + CDC_DIRECT_LINE_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_CALL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + (uint8_t)(bFirstInterface + 1), /* bDataInterface */ \ + 0x04, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x08, 0x00, /* wMaxPacketSize */ \ + 0x10, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#define DBVAL_BE(x) ((x >> 24) & 0xFF), ((x >> 16) & 0xFF), ((x >> 8) & 0xFF), (x & 0xFF) + +/*Length of template descriptor: 71 bytes*/ +#define CDC_ECM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_ECM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, \ +eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_ETHERNET_NETWORKING_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_ETHERNET_NETWORKING_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + /* CDC_ECM Functional Descriptor */ \ + 0x0D, /* bFunctionLength */\ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ + CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ + str_idx, /* Device's MAC string index */\ + DBVAL_BE(eth_statistics), /* Ethernet statistics (bitmap) */\ + WBVAL(wMaxPacketSize),/* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(wNumberMCFilters), /* wNumberMCFilters: the number of multicast filters */\ + bNumberPowerFilters, /* bNumberPowerFilters: the number of wakeup power filters */\ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x10, 0x00, /* wMaxPacketSize */ \ + 0x10, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +/*Length of template descriptor: 77 bytes*/ +#define CDC_NCM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 6 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_NCM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, \ +eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_NETWORK_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_NETWORK_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + /* CDC ETH Functional Descriptor */ \ + 0x0D, /* bFunctionLength */\ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ + CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ + str_idx, /* Device's MAC string index */\ + DBVAL_BE(eth_statistics), /* Ethernet statistics (bitmap) */\ + WBVAL(wMaxPacketSize),/* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(wNumberMCFilters), /* wNumberMCFilters: the number of multicast filters */\ + bNumberPowerFilters, /* bNumberPowerFilters: the number of wakeup power filters */\ + 0x06, \ + CDC_CS_INTERFACE, \ + CDC_FUNC_DESC_NCM, \ + 0x00, 0x01, \ + 0x23, \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x10, 0x00, /* wMaxPacketSize */ \ + 0x10, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#endif /* USB_CDC_H */ diff --git a/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.c b/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.c new file mode 100644 index 00000000000..50d13d7d53c --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.c @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc.h" + +const char *stop_name[] = { "1", "1.5", "2" }; +const char *parity_name[] = { "N", "O", "E", "M", "S" }; + +static int cdc_acm_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("CDC Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + struct cdc_line_coding line_coding; + bool dtr, rts; + uint8_t intf_num = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case CDC_REQUEST_SET_LINE_CODING: + + /*******************************************************************************/ + /* Line Coding Structure */ + /*-----------------------------------------------------------------------------*/ + /* Offset | Field | Size | Value | Description */ + /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ + /* 4 | bCharFormat | 1 | Number | Stop bits */ + /* 0 - 1 Stop bit */ + /* 1 - 1.5 Stop bits */ + /* 2 - 2 Stop bits */ + /* 5 | bParityType | 1 | Number | Parity */ + /* 0 - None */ + /* 1 - Odd */ + /* 2 - Even */ + /* 3 - Mark */ + /* 4 - Space */ + /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ + /*******************************************************************************/ + memcpy(&line_coding, *data, setup->wLength); + USB_LOG_DBG("Set intf:%d linecoding <%d %d %s %s>\r\n", + intf_num, + line_coding.dwDTERate, + line_coding.bDataBits, + parity_name[line_coding.bParityType], + stop_name[line_coding.bCharFormat]); + + usbd_cdc_acm_set_line_coding(busid, intf_num, &line_coding); + break; + + case CDC_REQUEST_SET_CONTROL_LINE_STATE: + dtr = (setup->wValue & 0x0001); + rts = (setup->wValue & 0x0002); + USB_LOG_DBG("Set intf:%d DTR 0x%x,RTS 0x%x\r\n", + intf_num, + dtr, + rts); + usbd_cdc_acm_set_dtr(busid, intf_num, dtr); + usbd_cdc_acm_set_rts(busid, intf_num, rts); + break; + + case CDC_REQUEST_GET_LINE_CODING: + usbd_cdc_acm_get_line_coding(busid, intf_num, &line_coding); + memcpy(*data, &line_coding, 7); + *len = 7; + USB_LOG_DBG("Get intf:%d linecoding %d %d %d %d\r\n", + intf_num, + line_coding.dwDTERate, + line_coding.bCharFormat, + line_coding.bParityType, + line_coding.bDataBits); + break; + case CDC_REQUEST_SEND_BREAK: + usbd_cdc_acm_send_break(busid, intf_num); + break; + default: + USB_LOG_WRN("Unhandled CDC Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf) +{ + intf->class_interface_handler = cdc_acm_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = NULL; + + return intf; +} + +__WEAK void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) +{ +} + +__WEAK void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) +{ + line_coding->dwDTERate = 2000000; + line_coding->bDataBits = 8; + line_coding->bParityType = 0; + line_coding->bCharFormat = 0; +} + +__WEAK void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr) +{ +} + +__WEAK void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts) +{ +} + +__WEAK void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf) +{ +} diff --git a/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.h b/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.h new file mode 100644 index 00000000000..ebf3d029e6f --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usbd_cdc.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CDC_H +#define USBD_CDC_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init cdc acm interface driver */ +struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf); + +/* Setup request command callback api */ +void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); +void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); +void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr); +void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts); +void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CDC_H */ diff --git a/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.c b/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.c new file mode 100644 index 00000000000..1fca9cadce2 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc_ecm.h" + +#define CDC_ECM_OUT_EP_IDX 0 +#define CDC_ECM_IN_EP_IDX 1 +#define CDC_ECM_INT_EP_IDX 2 + +/* Describe EndPoints configuration */ +static struct usbd_endpoint cdc_ecm_ep_data[3]; + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_rx_buffer[CONFIG_CDC_ECM_ETH_MAX_SEGSZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_tx_buffer[CONFIG_CDC_ECM_ETH_MAX_SEGSZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_notify_buf[16]; + +volatile uint8_t *g_cdc_ecm_rx_data_buffer = NULL; +volatile uint32_t g_cdc_ecm_rx_data_length = 0; +volatile uint32_t g_cdc_ecm_tx_data_length = 0; + +static volatile uint8_t g_current_net_status = 0; +static volatile uint8_t g_cmd_intf = 0; + +static uint32_t g_connect_speed_table[2] = { CDC_ECM_CONNECT_SPEED_UPSTREAM, + CDC_ECM_CONNECT_SPEED_DOWNSTREAM }; + +void usbd_cdc_ecm_send_notify(uint8_t notifycode, uint8_t value, uint32_t *speed) +{ + struct cdc_eth_notification *notify = (struct cdc_eth_notification *)g_cdc_ecm_notify_buf; + uint8_t bytes2send = 0; + + notify->bmRequestType = CDC_ECM_BMREQUEST_TYPE_ECM; + notify->bNotificationType = notifycode; + + switch (notifycode) { + case CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION: + notify->wValue = value; + notify->wIndex = g_cmd_intf; + notify->wLength = 0U; + + for (uint8_t i = 0U; i < 8U; i++) { + notify->data[i] = 0U; + } + bytes2send = 8U; + break; + case CDC_ECM_NOTIFY_CODE_RESPONSE_AVAILABLE: + notify->wValue = 0U; + notify->wIndex = g_cmd_intf; + notify->wLength = 0U; + for (uint8_t i = 0U; i < 8U; i++) { + notify->data[i] = 0U; + } + bytes2send = 8U; + break; + case CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE: + notify->wValue = 0U; + notify->wIndex = g_cmd_intf; + notify->wLength = 0x0008U; + bytes2send = 16U; + + memcpy(notify->data, speed, 8); + break; + + default: + break; + } + + if (bytes2send) { + usbd_ep_start_write(0, cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_addr, g_cdc_ecm_notify_buf, bytes2send); + } +} + +static int cdc_ecm_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("CDC ECM Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + g_cmd_intf = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case CDC_REQUEST_SET_ETHERNET_PACKET_FILTER: + /* bit0 Promiscuous + * bit1 ALL Multicast + * bit2 Directed + * bit3 Broadcast + * bit4 Multicast + */ + if (g_current_net_status == 0) { + g_current_net_status = 1; + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION, CDC_ECM_NET_CONNECTED, NULL); + } + + break; + default: + USB_LOG_WRN("Unhandled CDC ECM Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +void cdc_ecm_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + g_current_net_status = 0; + g_cdc_ecm_rx_data_length = 0; + g_cdc_ecm_tx_data_length = 0; + g_cdc_ecm_rx_data_buffer = NULL; + break; + case USBD_EVENT_CONFIGURED: + usbd_ep_start_read(0, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr, &g_cdc_ecm_rx_buffer[g_cdc_ecm_rx_data_length], usbd_get_ep_mps(busid, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr)); + break; + + default: + break; + } +} + +void cdc_ecm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + g_cdc_ecm_rx_data_length += nbytes; + + if (nbytes < usbd_get_ep_mps(busid, ep)) { + g_cdc_ecm_rx_data_buffer = g_cdc_ecm_rx_buffer; + usbd_cdc_ecm_data_recv_done(g_cdc_ecm_rx_buffer, g_cdc_ecm_rx_data_length); + } else { + usbd_ep_start_read(0, ep, &g_cdc_ecm_rx_buffer[g_cdc_ecm_rx_data_length], usbd_get_ep_mps(busid, ep)); + } +} + +void cdc_ecm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(0, ep, NULL, 0); + } else { + g_cdc_ecm_tx_data_length = 0; + } +} + +void cdc_ecm_int_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (g_current_net_status == 1) { + g_current_net_status = 2; + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION, CDC_ECM_NET_CONNECTED, g_connect_speed_table); + } +} + +int usbd_cdc_ecm_start_write(uint8_t *buf, uint32_t len) +{ + if (g_cdc_ecm_tx_data_length > 0) { + return -USB_ERR_BUSY; + } + + g_cdc_ecm_tx_data_length = len; + + USB_LOG_DBG("txlen:%d\r\n", g_cdc_ecm_tx_data_length); + return usbd_ep_start_write(0, cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_addr, buf, g_cdc_ecm_tx_data_length); +} + +void usbd_cdc_ecm_start_read_next(void) +{ + g_cdc_ecm_rx_data_length = 0; + g_cdc_ecm_rx_data_buffer = NULL; + usbd_ep_start_read(0, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr, g_cdc_ecm_rx_buffer, usbd_get_ep_mps(busid, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr)); +} + +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP +struct pbuf *usbd_cdc_ecm_eth_rx(void) +{ + struct pbuf *p; + + if (g_cdc_ecm_rx_data_buffer == NULL) { + return NULL; + } + p = pbuf_alloc(PBUF_RAW, g_cdc_ecm_rx_data_length, PBUF_POOL); + if (p == NULL) { + usbd_cdc_ecm_start_read_next(); + return NULL; + } + memcpy(p->payload, (uint8_t *)g_cdc_ecm_rx_buffer, g_cdc_ecm_rx_data_length); + p->len = g_cdc_ecm_rx_data_length; + + USB_LOG_DBG("rxlen:%d\r\n", g_cdc_ecm_rx_data_length); + usbd_cdc_ecm_start_read_next(); + return p; +} + +int usbd_cdc_ecm_eth_tx(struct pbuf *p) +{ + struct pbuf *q; + uint8_t *buffer; + + if (g_cdc_ecm_tx_data_length > 0) { + return -USB_ERR_BUSY; + } + + if (p->tot_len > sizeof(g_cdc_ecm_tx_buffer)) { + p->tot_len = sizeof(g_cdc_ecm_tx_buffer); + } + + buffer = g_cdc_ecm_tx_buffer; + for (q = p; q != NULL; q = q->next) { + memcpy(buffer, q->payload, q->len); + buffer += q->len; + } + + g_cdc_ecm_tx_data_length = p->tot_len; + + return usbd_cdc_ecm_start_write(g_cdc_ecm_tx_buffer, g_cdc_ecm_tx_data_length); +} +#endif + +struct usbd_interface *usbd_cdc_ecm_init_intf(struct usbd_interface *intf, const uint8_t int_ep, const uint8_t out_ep, const uint8_t in_ep) +{ + intf->class_interface_handler = cdc_ecm_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = cdc_ecm_notify_handler; + + cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr = out_ep; + cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_cb = cdc_ecm_bulk_out; + cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_addr = in_ep; + cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_cb = cdc_ecm_bulk_in; + cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_addr = int_ep; + cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_cb = cdc_ecm_int_in; + + usbd_add_endpoint(0, &cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX]); + usbd_add_endpoint(0, &cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX]); + usbd_add_endpoint(0, &cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX]); + + return intf; +} + +void usbd_cdc_ecm_set_connect_speed(uint32_t speed[2]) +{ + memcpy(g_connect_speed_table, speed, 8); +} + +__WEAK void usbd_cdc_ecm_data_recv_done(uint8_t *buf, uint32_t len) +{ +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.h b/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.h new file mode 100644 index 00000000000..8d9e5c9fe00 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usbd_cdc_ecm.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CDC_ECM_H +#define USBD_CDC_ECM_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Ethernet Maximum Segment size, typically 1514 bytes */ +#define CONFIG_CDC_ECM_ETH_MAX_SEGSZE 1514U + +/* Init cdc ecm interface driver */ +struct usbd_interface *usbd_cdc_ecm_init_intf(struct usbd_interface *intf, const uint8_t int_ep, const uint8_t out_ep, const uint8_t in_ep); + +/* Setup request command callback api */ +void usbd_cdc_ecm_set_connect_speed(uint32_t speed[2]); + +/* Api for eth only without any net stack */ +uint8_t *usbd_cdc_ecm_get_tx_buffer(void); +void usbd_cdc_ecm_send_done(void); +int usbd_cdc_ecm_start_write(uint8_t *buf, uint32_t len); +void usbd_cdc_ecm_data_recv_done(uint8_t *buf, uint32_t len); +void usbd_cdc_ecm_start_read_next(void); + +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP +#include "lwip/netif.h" +#include "lwip/pbuf.h" +struct pbuf *usbd_cdc_ecm_eth_rx(void); +int usbd_cdc_ecm_eth_tx(struct pbuf *p); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CDC_ECM_H */ diff --git a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c new file mode 100644 index 00000000000..05184af81cb --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.c @@ -0,0 +1,263 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_cdc_acm.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_cdc_acm" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/ttyACM%d" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_acm_buf[64]; + +static struct usbh_cdc_acm g_cdc_acm_class[CONFIG_USBHOST_MAX_CDC_ACM_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_cdc_acm *usbh_cdc_acm_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_CDC_ACM_CLASS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_cdc_acm_class[devno], 0, sizeof(struct usbh_cdc_acm)); + g_cdc_acm_class[devno].minor = devno; + return &g_cdc_acm_class[devno]; + } + } + return NULL; +} + +static void usbh_cdc_acm_class_free(struct usbh_cdc_acm *cdc_acm_class) +{ + int devno = cdc_acm_class->minor; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(cdc_acm_class, 0, sizeof(struct usbh_cdc_acm)); +} + +int usbh_cdc_acm_set_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup = cdc_acm_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = cdc_acm_class->intf; + setup->wLength = 7; + + memcpy(g_cdc_acm_buf, line_coding, sizeof(struct cdc_line_coding)); + + return usbh_control_transfer(cdc_acm_class->hport, setup, g_cdc_acm_buf); +} + +int usbh_cdc_acm_get_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup = cdc_acm_class->hport->setup; + int ret; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = cdc_acm_class->intf; + setup->wLength = 7; + + ret = usbh_control_transfer(cdc_acm_class->hport, setup, g_cdc_acm_buf); + if (ret < 0) { + return ret; + } + memcpy(line_coding, g_cdc_acm_buf, sizeof(struct cdc_line_coding)); + return ret; +} + +int usbh_cdc_acm_set_line_state(struct usbh_cdc_acm *cdc_acm_class, bool dtr, bool rts) +{ + struct usb_setup_packet *setup = cdc_acm_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE; + setup->wValue = (dtr << 0) | (rts << 1); + setup->wIndex = cdc_acm_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(cdc_acm_class->hport, setup, NULL); +} + +static int usbh_cdc_acm_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret = 0; + + struct usbh_cdc_acm *cdc_acm_class = usbh_cdc_acm_class_alloc(); + if (cdc_acm_class == NULL) { + USB_LOG_ERR("Fail to alloc cdc_acm_class\r\n"); + return -USB_ERR_NOMEM; + } + + cdc_acm_class->hport = hport; + cdc_acm_class->intf = intf; + + hport->config.intf[intf].priv = cdc_acm_class; + hport->config.intf[intf + 1].priv = NULL; + +#ifdef CONFIG_USBHOST_CDC_ACM_NOTIFY + ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + USBH_EP_INIT(cdc_acm_class->intin, ep_desc); +#endif + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_acm_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(cdc_acm_class->bulkout, ep_desc); + } + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, cdc_acm_class->minor); + + USB_LOG_INFO("Register CDC ACM Class:%s\r\n", hport->config.intf[intf].devname); + +#if 0 + USB_LOG_INFO("Test cdc acm rx and tx and rx for 5 times, baudrate is 115200\r\n"); + + struct cdc_line_coding linecoding; + uint8_t count = 5; + + linecoding.dwDTERate = 115200; + linecoding.bDataBits = 8; + linecoding.bParityType = 0; + linecoding.bCharFormat = 0; + usbh_cdc_acm_set_line_coding(cdc_acm_class, &linecoding); + usbh_cdc_acm_set_line_state(cdc_acm_class, true, false); + + memset(g_cdc_acm_buf, 'a', sizeof(g_cdc_acm_buf)); + ret = usbh_cdc_acm_bulk_out_transfer(cdc_acm_class, g_cdc_acm_buf, sizeof(g_cdc_acm_buf), 0xfffffff); + USB_LOG_RAW("out ret:%d\r\n", ret); + while (count--) { + ret = usbh_cdc_acm_bulk_in_transfer(cdc_acm_class, g_cdc_acm_buf, sizeof(g_cdc_acm_buf), 0xfffffff); + USB_LOG_RAW("in ret:%d\r\n", ret); + if (ret > 0) { + for (uint32_t i = 0; i < ret; i++) { + USB_LOG_RAW("%02x ", g_cdc_acm_buf[i]); + } + } + USB_LOG_RAW("\r\n"); + } +#endif + + usbh_cdc_acm_run(cdc_acm_class); + return ret; +} + +static int usbh_cdc_acm_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_cdc_acm *cdc_acm_class = (struct usbh_cdc_acm *)hport->config.intf[intf].priv; + + if (cdc_acm_class) { + if (cdc_acm_class->bulkin) { + usbh_kill_urb(&cdc_acm_class->bulkin_urb); + } + + if (cdc_acm_class->bulkout) { + usbh_kill_urb(&cdc_acm_class->bulkout_urb); + } + +#ifdef CONFIG_USBHOST_CDC_ACM_NOTIFY + if (cdc_acm_class->intin) { + usbh_kill_urb(&cdc_acm_class->intin_urb); + } +#endif + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister CDC ACM Class:%s\r\n", hport->config.intf[intf].devname); + usbh_cdc_acm_stop(cdc_acm_class); + } + + usbh_cdc_acm_class_free(cdc_acm_class); + } + + return ret; +} + +int usbh_cdc_acm_bulk_in_transfer(struct usbh_cdc_acm *cdc_acm_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &cdc_acm_class->bulkin_urb; + + usbh_bulk_urb_fill(urb, cdc_acm_class->hport, cdc_acm_class->bulkin, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +int usbh_cdc_acm_bulk_out_transfer(struct usbh_cdc_acm *cdc_acm_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &cdc_acm_class->bulkout_urb; + + usbh_bulk_urb_fill(urb, cdc_acm_class->hport, cdc_acm_class->bulkout, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +static int usbh_cdc_data_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return 0; +} + +static int usbh_cdc_data_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + return 0; +} + +__WEAK void usbh_cdc_acm_run(struct usbh_cdc_acm *cdc_acm_class) +{ +} + +__WEAK void usbh_cdc_acm_stop(struct usbh_cdc_acm *cdc_acm_class) +{ +} + +const struct usbh_class_driver cdc_acm_class_driver = { + .driver_name = "cdc_acm", + .connect = usbh_cdc_acm_connect, + .disconnect = usbh_cdc_acm_disconnect +}; + +const struct usbh_class_driver cdc_data_class_driver = { + .driver_name = "cdc_data", + .connect = usbh_cdc_data_connect, + .disconnect = usbh_cdc_data_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_acm_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .class = USB_DEVICE_CLASS_CDC, + .subclass = CDC_ABSTRACT_CONTROL_MODEL, + .protocol = CDC_COMMON_PROTOCOL_AT_COMMANDS, + .id_table = NULL, + .class_driver = &cdc_acm_class_driver +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_data_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS, + .class = USB_DEVICE_CLASS_CDC_DATA, + .subclass = 0x00, + .protocol = 0x00, + .id_table = NULL, + .class_driver = &cdc_data_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.h b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.h new file mode 100644 index 00000000000..80800bf9f22 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_acm.h @@ -0,0 +1,50 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CDC_ACM_H +#define USBH_CDC_ACM_H + +#include "usb_cdc.h" + +struct usbh_cdc_acm { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ +#ifdef CONFIG_USBHOST_CDC_ACM_NOTIFY + struct usb_endpoint_descriptor *intin; /* INTR IN endpoint (optional) */ +#endif + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; +#ifdef CONFIG_USBHOST_CDC_ACM_NOTIFY + struct usbh_urb intin_urb; +#endif + + struct cdc_line_coding linecoding; + + uint8_t intf; + uint8_t minor; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_cdc_acm_set_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_line_coding *line_coding); +int usbh_cdc_acm_get_line_coding(struct usbh_cdc_acm *cdc_acm_class, struct cdc_line_coding *line_coding); +int usbh_cdc_acm_set_line_state(struct usbh_cdc_acm *cdc_acm_class, bool dtr, bool rts); + +int usbh_cdc_acm_bulk_in_transfer(struct usbh_cdc_acm *cdc_acm_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); +int usbh_cdc_acm_bulk_out_transfer(struct usbh_cdc_acm *cdc_acm_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); + +void usbh_cdc_acm_run(struct usbh_cdc_acm *cdc_acm_class); +void usbh_cdc_acm_stop(struct usbh_cdc_acm *cdc_acm_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CDC_ACM_H */ diff --git a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c new file mode 100644 index 00000000000..5e3ae7bc71c --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.c @@ -0,0 +1,319 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_cdc_ecm.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_cdc_ecm" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/cdc_ether" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ +#define DESC_bDescriptorSubType 2 /** Descriptor subtype offset */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +#define CONFIG_USBHOST_CDC_ECM_PKT_FILTER 0x000C +#define CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE 1514U + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_rx_buffer[CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_tx_buffer[CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_inttx_buffer[16]; + +static struct usbh_cdc_ecm g_cdc_ecm_class; + +static int usbh_cdc_ecm_set_eth_packet_filter(struct usbh_cdc_ecm *cdc_ecm_class, uint16_t filter_value) +{ + struct usb_setup_packet *setup = cdc_ecm_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_ETHERNET_PACKET_FILTER; + setup->wValue = filter_value; + setup->wIndex = cdc_ecm_class->ctrl_intf; + setup->wLength = 0; + + return usbh_control_transfer(cdc_ecm_class->hport, setup, NULL); +} + +int usbh_cdc_ecm_get_connect_status(struct usbh_cdc_ecm *cdc_ecm_class) +{ + int ret; + + usbh_int_urb_fill(&cdc_ecm_class->intin_urb, cdc_ecm_class->hport, cdc_ecm_class->intin, g_cdc_ecm_inttx_buffer, 16, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&cdc_ecm_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (g_cdc_ecm_inttx_buffer[1] == CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION) { + if (g_cdc_ecm_inttx_buffer[2] == CDC_ECM_NET_CONNECTED) { + cdc_ecm_class->connect_status = true; + } else { + cdc_ecm_class->connect_status = false; + } + } else if (g_cdc_ecm_inttx_buffer[1] == CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE) { + memcpy(cdc_ecm_class->speed, &g_cdc_ecm_inttx_buffer[8], 8); + } + return 0; +} + +static int usbh_cdc_ecm_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + uint8_t altsetting = 0; + char mac_buffer[12]; + uint8_t *p; + uint8_t cur_iface = 0xff; + uint8_t mac_str_idx = 0xff; + + struct usbh_cdc_ecm *cdc_ecm_class = &g_cdc_ecm_class; + + memset(cdc_ecm_class, 0, sizeof(struct usbh_cdc_ecm)); + + cdc_ecm_class->hport = hport; + cdc_ecm_class->ctrl_intf = intf; + cdc_ecm_class->data_intf = intf + 1; + + hport->config.intf[intf].priv = cdc_ecm_class; + hport->config.intf[intf + 1].priv = NULL; + + p = hport->raw_config_desc; + while (p[DESC_bLength]) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + //cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + break; + case CDC_CS_INTERFACE: + if ((cur_iface == cdc_ecm_class->ctrl_intf) && p[DESC_bDescriptorSubType] == CDC_FUNC_DESC_ETHERNET_NETWORKING) { + struct cdc_eth_descriptor *desc = (struct cdc_eth_descriptor *)p; + mac_str_idx = desc->iMACAddress; + cdc_ecm_class->max_segment_size = desc->wMaxSegmentSize; + goto get_mac; + } + break; + + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + +get_mac: + if (mac_str_idx == 0xff) { + USB_LOG_ERR("Do not find cdc ecm mac string\r\n"); + return -1; + } + + memset(mac_buffer, 0, 12); + ret = usbh_get_string_desc(cdc_ecm_class->hport, mac_str_idx, (uint8_t *)mac_buffer); + if (ret < 0) { + return ret; + } + + for (int i = 0, j = 0; i < 12; i += 2, j++) { + char byte_str[3]; + byte_str[0] = mac_buffer[i]; + byte_str[1] = mac_buffer[i + 1]; + byte_str[2] = '\0'; + + uint32_t byte = strtoul(byte_str, NULL, 16); + cdc_ecm_class->mac[j] = (unsigned char)byte; + } + + USB_LOG_INFO("CDC ECM MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + cdc_ecm_class->mac[0], + cdc_ecm_class->mac[1], + cdc_ecm_class->mac[2], + cdc_ecm_class->mac[3], + cdc_ecm_class->mac[4], + cdc_ecm_class->mac[5]); + + if (cdc_ecm_class->max_segment_size > CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE) { + USB_LOG_ERR("CDC ECM Max Segment Size is overflow, default is %u, but now %u\r\n", CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE, cdc_ecm_class->max_segment_size); + } else { + USB_LOG_INFO("CDC ECM Max Segment Size:%u\r\n", cdc_ecm_class->max_segment_size); + } + + /* enable int ep */ + ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + USBH_EP_INIT(cdc_ecm_class->intin, ep_desc); + + if (hport->config.intf[intf + 1].altsetting_num > 1) { + altsetting = hport->config.intf[intf + 1].altsetting_num - 1; + + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[altsetting].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[altsetting].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_ecm_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(cdc_ecm_class->bulkout, ep_desc); + } + } + + USB_LOG_INFO("Select cdc ecm altsetting: %d\r\n", altsetting); + usbh_set_interface(cdc_ecm_class->hport, cdc_ecm_class->data_intf, altsetting); + } else { + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_ecm_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(cdc_ecm_class->bulkout, ep_desc); + } + } + } + + /* bit0 Promiscuous + * bit1 ALL Multicast + * bit2 Directed + * bit3 Broadcast + * bit4 Multicast + */ + ret = usbh_cdc_ecm_set_eth_packet_filter(cdc_ecm_class, CONFIG_USBHOST_CDC_ECM_PKT_FILTER); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("Set CDC ECM packet filter:%04x\r\n", CONFIG_USBHOST_CDC_ECM_PKT_FILTER); + + memcpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register CDC ECM Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_cdc_ecm_run(cdc_ecm_class); + return ret; +} + +static int usbh_cdc_ecm_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_cdc_ecm *cdc_ecm_class = (struct usbh_cdc_ecm *)hport->config.intf[intf].priv; + + if (cdc_ecm_class) { + if (cdc_ecm_class->bulkin) { + usbh_kill_urb(&cdc_ecm_class->bulkin_urb); + } + + if (cdc_ecm_class->bulkout) { + usbh_kill_urb(&cdc_ecm_class->bulkout_urb); + } + + if (cdc_ecm_class->intin) { + usbh_kill_urb(&cdc_ecm_class->intin_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister CDC ECM Class:%s\r\n", hport->config.intf[intf].devname); + usbh_cdc_ecm_stop(cdc_ecm_class); + } + + memset(cdc_ecm_class, 0, sizeof(struct usbh_cdc_ecm)); + } + + return ret; +} + +void usbh_cdc_ecm_rx_thread(void *argument) +{ + uint32_t g_cdc_ecm_rx_length; + int ret; + + USB_LOG_INFO("Create cdc ecm rx thread\r\n"); + // clang-format off +find_class: + // clang-format on + g_cdc_ecm_class.connect_status = false; + if (usbh_find_class_instance("/dev/cdc_ether") == NULL) { + goto delete; + } + + while (g_cdc_ecm_class.connect_status == false) { + ret = usbh_cdc_ecm_get_connect_status(&g_cdc_ecm_class); + if (ret < 0) { + usb_osal_msleep(100); + goto find_class; + } + } + + g_cdc_ecm_rx_length = 0; + while (1) { + usbh_bulk_urb_fill(&g_cdc_ecm_class.bulkin_urb, g_cdc_ecm_class.hport, g_cdc_ecm_class.bulkin, &g_cdc_ecm_rx_buffer[g_cdc_ecm_rx_length], CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_cdc_ecm_class.bulkin_urb); + if (ret < 0) { + goto find_class; + } + + g_cdc_ecm_rx_length += g_cdc_ecm_class.bulkin_urb.actual_length; + + if (g_cdc_ecm_rx_length % USB_GET_MAXPACKETSIZE(g_cdc_ecm_class.bulkin->wMaxPacketSize)) { + USB_LOG_DBG("rxlen:%d\r\n", g_cdc_ecm_rx_length); + + usbh_cdc_ecm_eth_input(g_cdc_ecm_rx_buffer, g_cdc_ecm_rx_length); + + g_cdc_ecm_rx_length = 0; + } else { + /* read continue util read short packet */ + if (g_cdc_ecm_rx_length > CONFIG_USBHOST_CDC_ECM_ETH_MAX_SIZE) { + USB_LOG_ERR("Rx packet is overflow\r\n"); + g_cdc_ecm_rx_length = 0; + } + } + } + // clang-format off +delete: + USB_LOG_INFO("Delete cdc ecm rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +int usbh_cdc_ecm_eth_output(uint8_t *buf, uint32_t buflen) +{ + uint8_t *buffer = g_cdc_ecm_tx_buffer; + + if (g_cdc_ecm_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + memcpy(buffer, buf, buflen); + + USB_LOG_DBG("txlen:%d\r\n", buflen); + + usbh_bulk_urb_fill(&g_cdc_ecm_class.bulkout_urb, g_cdc_ecm_class.hport, g_cdc_ecm_class.bulkout, g_cdc_ecm_tx_buffer, buflen, USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_cdc_ecm_class.bulkout_urb); +} + +__WEAK void usbh_cdc_ecm_run(struct usbh_cdc_ecm *cdc_ecm_class) +{ +} + +__WEAK void usbh_cdc_ecm_stop(struct usbh_cdc_ecm *cdc_ecm_class) +{ +} + +const struct usbh_class_driver cdc_ecm_class_driver = { + .driver_name = "cdc_ecm", + .connect = usbh_cdc_ecm_connect, + .disconnect = usbh_cdc_ecm_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_ecm_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .class = USB_DEVICE_CLASS_CDC, + .subclass = CDC_ETHERNET_NETWORKING_CONTROL_MODEL, + .protocol = CDC_COMMON_PROTOCOL_NONE, + .id_table = NULL, + .class_driver = &cdc_ecm_class_driver +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.h b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.h new file mode 100644 index 00000000000..d965ac88a5d --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ecm.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CDC_ECM_H +#define USBH_CDC_ECM_H + +#include "usb_cdc.h" + +struct usbh_cdc_ecm { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usb_endpoint_descriptor *intin; /* Interrupt IN endpoint */ + struct usbh_urb bulkout_urb; /* Bulk out endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN endpoint */ + struct usbh_urb intin_urb; /* Interrupt IN endpoint */ + + uint8_t ctrl_intf; /* Control interface number */ + uint8_t data_intf; /* Data interface number */ + uint8_t minor; + + uint8_t mac[6]; + bool connect_status; + uint16_t max_segment_size; + uint32_t speed[2]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_cdc_ecm_get_connect_status(struct usbh_cdc_ecm *cdc_ecm_class); + +void usbh_cdc_ecm_run(struct usbh_cdc_ecm *cdc_ecm_class); +void usbh_cdc_ecm_stop(struct usbh_cdc_ecm *cdc_ecm_class); + +int usbh_cdc_ecm_eth_output(uint8_t *buf, uint32_t buflen); +void usbh_cdc_ecm_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_cdc_ecm_rx_thread(void *argument); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CDC_ECM_H */ diff --git a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c new file mode 100644 index 00000000000..4f13f791ea3 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.c @@ -0,0 +1,388 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_cdc_ncm.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_cdc_ncm" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/cdc_ncm" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ +#define DESC_bDescriptorSubType 2 /** Descriptor subtype offset */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_SEGSZE 1514U + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ncm_rx_buffer[CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ncm_tx_buffer[CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ncm_inttx_buffer[16]; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ncm_buf[32]; + +static struct usbh_cdc_ncm g_cdc_ncm_class; + +static int usbh_cdc_ncm_get_ntb_parameters(struct usbh_cdc_ncm *cdc_ncm_class, struct cdc_ncm_ntb_parameters *param) +{ + struct usb_setup_packet *setup = cdc_ncm_class->hport->setup; + int ret; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_NTB_PARAMETERS; + setup->wValue = 0; + setup->wIndex = cdc_ncm_class->ctrl_intf; + setup->wLength = 28; + + ret = usbh_control_transfer(cdc_ncm_class->hport, setup, g_cdc_ncm_buf); + if (ret < 0) { + return ret; + } + + memcpy((uint8_t *)param, g_cdc_ncm_buf, ret - 8); + return 0; +} + +static void print_ntb_parameters(struct cdc_ncm_ntb_parameters *param) +{ + USB_LOG_RAW("CDC NCM ntb parameters:\r\n"); + USB_LOG_RAW("wLength: 0x%02x \r\n", param->wLength); + USB_LOG_RAW("bmNtbFormatsSupported: %s \r\n", param->bmNtbFormatsSupported ? "NTB16" : "NTB32"); + + USB_LOG_RAW("dwNtbInMaxSize: 0x%04x \r\n", param->dwNtbInMaxSize); + USB_LOG_RAW("wNdbInDivisor: 0x%02x \r\n", param->wNdbInDivisor); + USB_LOG_RAW("wNdbInPayloadRemainder: 0x%02x \r\n", param->wNdbInPayloadRemainder); + USB_LOG_RAW("wNdbInAlignment: 0x%02x \r\n", param->wNdbInAlignment); + + USB_LOG_RAW("dwNtbOutMaxSize: 0x%04x \r\n", param->dwNtbOutMaxSize); + USB_LOG_RAW("wNdbOutDivisor: 0x%02x \r\n", param->wNdbOutDivisor); + USB_LOG_RAW("wNdbOutPayloadRemainder: 0x%02x \r\n", param->wNdbOutPayloadRemainder); + USB_LOG_RAW("wNdbOutAlignment: 0x%02x \r\n", param->wNdbOutAlignment); + + USB_LOG_RAW("wNtbOutMaxDatagrams: 0x%02x \r\n", param->wNtbOutMaxDatagrams); +} + +int usbh_cdc_ncm_get_connect_status(struct usbh_cdc_ncm *cdc_ncm_class) +{ + int ret; + + usbh_int_urb_fill(&cdc_ncm_class->intin_urb, cdc_ncm_class->hport, cdc_ncm_class->intin, g_cdc_ncm_inttx_buffer, 16, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&cdc_ncm_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (g_cdc_ncm_inttx_buffer[1] == CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION) { + if (g_cdc_ncm_inttx_buffer[2] == CDC_ECM_NET_CONNECTED) { + cdc_ncm_class->connect_status = true; + } else { + cdc_ncm_class->connect_status = false; + } + } else if (g_cdc_ncm_inttx_buffer[1] == CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE) { + memcpy(cdc_ncm_class->speed, &g_cdc_ncm_inttx_buffer[8], 8); + } + return 0; +} + +static int usbh_cdc_ncm_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + uint8_t altsetting = 0; + char mac_buffer[12]; + uint8_t *p; + uint8_t cur_iface = 0xff; + uint8_t mac_str_idx = 0xff; + + struct usbh_cdc_ncm *cdc_ncm_class = &g_cdc_ncm_class; + + memset(cdc_ncm_class, 0, sizeof(struct usbh_cdc_ncm)); + + cdc_ncm_class->hport = hport; + cdc_ncm_class->ctrl_intf = intf; + cdc_ncm_class->data_intf = intf + 1; + + hport->config.intf[intf].priv = cdc_ncm_class; + hport->config.intf[intf + 1].priv = NULL; + + p = hport->raw_config_desc; + while (p[DESC_bLength]) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + //cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + break; + case CDC_CS_INTERFACE: + if ((cur_iface == cdc_ncm_class->ctrl_intf) && p[DESC_bDescriptorSubType] == CDC_FUNC_DESC_ETHERNET_NETWORKING) { + struct cdc_eth_descriptor *desc = (struct cdc_eth_descriptor *)p; + mac_str_idx = desc->iMACAddress; + cdc_ncm_class->max_segment_size = desc->wMaxSegmentSize; + goto get_mac; + } + break; + + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + +get_mac: + if (mac_str_idx == 0xff) { + USB_LOG_ERR("Do not find cdc ncm mac string\r\n"); + return -1; + } + + memset(mac_buffer, 0, 12); + ret = usbh_get_string_desc(cdc_ncm_class->hport, mac_str_idx, (uint8_t *)mac_buffer); + if (ret < 0) { + return ret; + } + + for (int i = 0, j = 0; i < 12; i += 2, j++) { + char byte_str[3]; + byte_str[0] = mac_buffer[i]; + byte_str[1] = mac_buffer[i + 1]; + byte_str[2] = '\0'; + + uint32_t byte = strtoul(byte_str, NULL, 16); + cdc_ncm_class->mac[j] = (unsigned char)byte; + } + + USB_LOG_INFO("CDC NCM MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + cdc_ncm_class->mac[0], + cdc_ncm_class->mac[1], + cdc_ncm_class->mac[2], + cdc_ncm_class->mac[3], + cdc_ncm_class->mac[4], + cdc_ncm_class->mac[5]); + + if (cdc_ncm_class->max_segment_size > CONFIG_USBHOST_CDC_NCM_ETH_MAX_SEGSZE) { + USB_LOG_ERR("CDC NCM Max Segment Size is overflow, default is %u, but now %u\r\n", CONFIG_USBHOST_CDC_NCM_ETH_MAX_SEGSZE, cdc_ncm_class->max_segment_size); + } else { + USB_LOG_INFO("CDC NCM Max Segment Size:%u\r\n", cdc_ncm_class->max_segment_size); + } + + usbh_cdc_ncm_get_ntb_parameters(cdc_ncm_class, &cdc_ncm_class->ntb_param); + print_ntb_parameters(&cdc_ncm_class->ntb_param); + + /* enable int ep */ + ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + USBH_EP_INIT(cdc_ncm_class->intin, ep_desc); + + if (hport->config.intf[intf + 1].altsetting_num > 1) { + altsetting = hport->config.intf[intf + 1].altsetting_num - 1; + + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[altsetting].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[altsetting].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_ncm_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(cdc_ncm_class->bulkout, ep_desc); + } + } + + USB_LOG_INFO("Select cdc ncm altsetting: %d\r\n", altsetting); + usbh_set_interface(cdc_ncm_class->hport, cdc_ncm_class->data_intf, altsetting); + } else { + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cdc_ncm_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(cdc_ncm_class->bulkout, ep_desc); + } + } + } + + memcpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register CDC NCM Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_cdc_ncm_run(cdc_ncm_class); + return ret; +} + +static int usbh_cdc_ncm_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_cdc_ncm *cdc_ncm_class = (struct usbh_cdc_ncm *)hport->config.intf[intf].priv; + + if (cdc_ncm_class) { + if (cdc_ncm_class->bulkin) { + usbh_kill_urb(&cdc_ncm_class->bulkin_urb); + } + + if (cdc_ncm_class->bulkout) { + usbh_kill_urb(&cdc_ncm_class->bulkout_urb); + } + + if (cdc_ncm_class->intin) { + usbh_kill_urb(&cdc_ncm_class->intin_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister CDC NCM Class:%s\r\n", hport->config.intf[intf].devname); + usbh_cdc_ncm_stop(cdc_ncm_class); + } + + memset(cdc_ncm_class, 0, sizeof(struct usbh_cdc_ncm)); + } + + return ret; +} + +void usbh_cdc_ncm_rx_thread(void *argument) +{ + uint32_t g_cdc_ncm_rx_length; + int ret; + + USB_LOG_INFO("Create cdc ncm rx thread\r\n"); + // clang-format off +find_class: + // clang-format on + g_cdc_ncm_class.connect_status = false; + if (usbh_find_class_instance("/dev/cdc_ncm") == NULL) { + goto delete; + } + + while (g_cdc_ncm_class.connect_status == false) { + ret = usbh_cdc_ncm_get_connect_status(&g_cdc_ncm_class); + if (ret < 0) { + usb_osal_msleep(100); + goto find_class; + } + } + + g_cdc_ncm_rx_length = 0; + while (1) { + usbh_bulk_urb_fill(&g_cdc_ncm_class.bulkin_urb, g_cdc_ncm_class.hport, g_cdc_ncm_class.bulkin, &g_cdc_ncm_rx_buffer[g_cdc_ncm_rx_length], (CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE > (16 * 1024)) ? (16 * 1024) : CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_cdc_ncm_class.bulkin_urb); + if (ret < 0) { + goto find_class; + } + + g_cdc_ncm_rx_length += g_cdc_ncm_class.bulkin_urb.actual_length; + + if (g_cdc_ncm_rx_length % USB_GET_MAXPACKETSIZE(g_cdc_ncm_class.bulkin->wMaxPacketSize)) { + USB_LOG_DBG("rxlen:%d\r\n", g_cdc_ncm_rx_length); + + struct cdc_ncm_nth16 *nth16 = (struct cdc_ncm_nth16 *)&g_cdc_ncm_rx_buffer[0]; + if ((nth16->dwSignature != CDC_NCM_NTH16_SIGNATURE) || + (nth16->wHeaderLength != 12) || + (nth16->wBlockLength != g_cdc_ncm_rx_length)) { + USB_LOG_ERR("invalid rx nth16\r\n"); + g_cdc_ncm_rx_length = 0; + continue; + } + + struct cdc_ncm_ndp16 *ndp16 = (struct cdc_ncm_ndp16 *)&g_cdc_ncm_rx_buffer[nth16->wNdpIndex]; + if ((ndp16->dwSignature != CDC_NCM_NDP16_SIGNATURE_NCM0) && (ndp16->dwSignature != CDC_NCM_NDP16_SIGNATURE_NCM1)) { + USB_LOG_ERR("invalid rx ndp16\r\n"); + g_cdc_ncm_rx_length = 0; + continue; + } + + uint16_t datagram_num = (ndp16->wLength - 8) / 4; + + USB_LOG_DBG("datagram num:%02x\r\n", datagram_num); + for (uint16_t i = 0; i < datagram_num; i++) { + struct cdc_ncm_ndp16_datagram *ndp16_datagram = (struct cdc_ncm_ndp16_datagram *)&g_cdc_ncm_rx_buffer[nth16->wNdpIndex + 8 + 4 * i]; + if (ndp16_datagram->wDatagramIndex && ndp16_datagram->wDatagramLength) { + USB_LOG_DBG("ndp16_datagram index:%02x, length:%02x\r\n", ndp16_datagram->wDatagramIndex, ndp16_datagram->wDatagramLength); + + uint8_t *buf = (uint8_t *)&g_cdc_ncm_rx_buffer[ndp16_datagram->wDatagramIndex]; + usbh_cdc_ncm_eth_input(buf, ndp16_datagram->wDatagramLength); + } + } + + g_cdc_ncm_rx_length = 0; + + } else { + if (g_cdc_ncm_rx_length > CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE) { + USB_LOG_ERR("Rx packet is overflow\r\n"); + g_cdc_ncm_rx_length = 0; + } + } + } + // clang-format off +delete: + USB_LOG_INFO("Delete cdc ncm rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +int usbh_cdc_ncm_eth_output(uint8_t *buf, uint32_t buflen) +{ + uint8_t *buffer; + struct cdc_ncm_ndp16_datagram *ndp16_datagram; + + if (g_cdc_ncm_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + struct cdc_ncm_nth16 *nth16 = (struct cdc_ncm_nth16 *)&g_cdc_ncm_tx_buffer[0]; + + nth16->dwSignature = CDC_NCM_NTH16_SIGNATURE; + nth16->wHeaderLength = 12; + nth16->wSequence = g_cdc_ncm_class.bulkout_sequence++; + nth16->wBlockLength = 16 + 16 + USB_ALIGN_UP(buflen, 4); + nth16->wNdpIndex = 16 + USB_ALIGN_UP(buflen, 4); + + struct cdc_ncm_ndp16 *ndp16 = (struct cdc_ncm_ndp16 *)&g_cdc_ncm_tx_buffer[nth16->wNdpIndex]; + + ndp16->dwSignature = CDC_NCM_NDP16_SIGNATURE_NCM0; + ndp16->wLength = 16; + ndp16->wNextNdpIndex = 0; + + ndp16_datagram = (struct cdc_ncm_ndp16_datagram *)&g_cdc_ncm_tx_buffer[nth16->wNdpIndex + 8 + 4 * 0]; + ndp16_datagram->wDatagramIndex = 16; + ndp16_datagram->wDatagramLength = buflen; + + ndp16_datagram = (struct cdc_ncm_ndp16_datagram *)&g_cdc_ncm_tx_buffer[nth16->wNdpIndex + 8 + 4 * 1]; + ndp16_datagram->wDatagramIndex = 0; + ndp16_datagram->wDatagramLength = 0; + + buffer = &g_cdc_ncm_tx_buffer[16]; + memcpy(buffer, buf, buflen); + + USB_LOG_DBG("txlen:%d\r\n", nth16->wBlockLength); + + usbh_bulk_urb_fill(&g_cdc_ncm_class.bulkout_urb, g_cdc_ncm_class.hport, g_cdc_ncm_class.bulkout, g_cdc_ncm_tx_buffer, nth16->wBlockLength, USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_cdc_ncm_class.bulkout_urb); +} + +__WEAK void usbh_cdc_ncm_run(struct usbh_cdc_ncm *cdc_ncm_class) +{ +} + +__WEAK void usbh_cdc_ncm_stop(struct usbh_cdc_ncm *cdc_ncm_class) +{ +} + +const struct usbh_class_driver cdc_ncm_class_driver = { + .driver_name = "cdc_ncm", + .connect = usbh_cdc_ncm_connect, + .disconnect = usbh_cdc_ncm_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cdc_ncm_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .class = USB_DEVICE_CLASS_CDC, + .subclass = CDC_NETWORK_CONTROL_MODEL, + .protocol = CDC_COMMON_PROTOCOL_NONE, + .id_table = NULL, + .class_driver = &cdc_ncm_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.h b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.h new file mode 100644 index 00000000000..5f069401faf --- /dev/null +++ b/components/drivers/usb/cherryusb/class/cdc/usbh_cdc_ncm.h @@ -0,0 +1,53 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CDC_NCM_H +#define USBH_CDC_NCM_H + +#include "usb_cdc.h" + +struct usbh_cdc_ncm { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usb_endpoint_descriptor *intin; /* Interrupt IN endpoint */ + struct usbh_urb bulkout_urb; /* Bulk out endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN endpoint */ + struct usbh_urb intin_urb; /* Interrupt IN endpoint */ + + uint8_t ctrl_intf; /* Control interface number */ + uint8_t data_intf; /* Data interface number */ + uint8_t minor; + + struct cdc_ncm_ntb_parameters ntb_param; + uint16_t bulkin_sequence; + uint16_t bulkout_sequence; + + uint8_t mac[6]; + bool connect_status; + uint16_t max_segment_size; + uint32_t speed[2]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_cdc_ncm_get_connect_status(struct usbh_cdc_ncm *cdc_ncm_class); + +void usbh_cdc_ncm_run(struct usbh_cdc_ncm *cdc_ncm_class); +void usbh_cdc_ncm_stop(struct usbh_cdc_ncm *cdc_ncm_class); + +int usbh_cdc_ncm_eth_output(uint8_t *buf, uint32_t buflen); +void usbh_cdc_ncm_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_cdc_ncm_rx_thread(void *argument); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CDC_NCM_H */ diff --git a/components/drivers/usb/cherryusb/class/dfu/usb_dfu.h b/components/drivers/usb/cherryusb/class/dfu/usb_dfu.h new file mode 100644 index 00000000000..f1ccba88cfb --- /dev/null +++ b/components/drivers/usb/cherryusb/class/dfu/usb_dfu.h @@ -0,0 +1,137 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DFU_H +#define USB_DFU_H + +/**\addtogroup USB_MODULE_DFU USB DFU class + * \brief This module contains USB Device Firmware Upgrade class definitions. + * \details This module based on + * + [USB Device Firmware Upgrade Specification, Revision 1.1] + * (https://www.usb.org/sites/default/files/DFU_1.1.pdf) + * @{ */ + +/** DFU Specification release */ +#define DFU_VERSION 0x0110 + +/** DFU Class Subclass */ +#define DFU_SUBCLASS_DFU 0x01 + +/** DFU Class runtime Protocol */ +#define DFU_PROTOCOL_RUNTIME 0x01 + +/** DFU Class DFU mode Protocol */ +#define DFU_PROTOCOL_MODE 0x02 + +/** + * @brief DFU Class Specific Requests + */ +#define DFU_REQUEST_DETACH 0x00 +#define DFU_REQUEST_DNLOAD 0x01 +#define DFU_REQUEST_UPLOAD 0x02 +#define DFU_REQUEST_GETSTATUS 0x03 +#define DFU_REQUEST_CLRSTATUS 0x04 +#define DFU_REQUEST_GETSTATE 0x05 +#define DFU_REQUEST_ABORT 0x06 + +/** DFU FUNCTIONAL descriptor type */ +#define DFU_FUNC_DESC 0x21 + +/** DFU attributes DFU Functional Descriptor */ +#define DFU_ATTR_WILL_DETACH 0x08 +#define DFU_ATTR_MANIFESTATION_TOLERANT 0x04 +#define DFU_ATTR_CAN_UPLOAD 0x02 +#define DFU_ATTR_CAN_DNLOAD 0x01 + +/** bStatus values for the DFU_GETSTATUS response */ +#define DFU_STATUS_OK 0x00U +#define DFU_STATUS_ERR_TARGET 0x01U +#define DFU_STATUS_ERR_FILE 0x02U +#define DFU_STATUS_ERR_WRITE 0x03U +#define DFU_STATUS_ERR_ERASE 0x04U +#define DFU_STATUS_ERR_CHECK_ERASED 0x05U +#define DFU_STATUS_ERR_PROG 0x06U +#define DFU_STATUS_ERR_VERIFY 0x07U +#define DFU_STATUS_ERR_ADDRESS 0x08U +#define DFU_STATUS_ERR_NOTDONE 0x09U +#define DFU_STATUS_ERR_FIRMWARE 0x0AU +#define DFU_STATUS_ERR_VENDOR 0x0BU +#define DFU_STATUS_ERR_USB 0x0CU +#define DFU_STATUS_ERR_POR 0x0DU +#define DFU_STATUS_ERR_UNKNOWN 0x0EU +#define DFU_STATUS_ERR_STALLEDPKT 0x0FU + +/** bState values for the DFU_GETSTATUS response */ +#define DFU_STATE_APP_IDLE 0U +#define DFU_STATE_APP_DETACH 1U +#define DFU_STATE_DFU_IDLE 2U +#define DFU_STATE_DFU_DNLOAD_SYNC 3U +#define DFU_STATE_DFU_DNLOAD_BUSY 4U +#define DFU_STATE_DFU_DNLOAD_IDLE 5U +#define DFU_STATE_DFU_MANIFEST_SYNC 6U +#define DFU_STATE_DFU_MANIFEST 7U +#define DFU_STATE_DFU_MANIFEST_WAIT_RESET 8U +#define DFU_STATE_DFU_UPLOAD_IDLE 9U +#define DFU_STATE_DFU_ERROR 10U + +/** DFU Manifestation State */ +#define DFU_MANIFEST_COMPLETE 0U +#define DFU_MANIFEST_IN_PROGRESS 1U + +/** Special Commands with Download Request */ +#define DFU_CMD_GETCOMMANDS 0U +#define DFU_CMD_SETADDRESSPOINTER 0x21U +#define DFU_CMD_ERASE 0x41U +#define DFU_MEDIA_ERASE 0x00U +#define DFU_MEDIA_PROGRAM 0x01U + +/** Other defines */ +/* Bit Detach capable = bit 3 in bmAttributes field */ +#define DFU_DETACH_MASK (1U << 3) +#define DFU_MANIFEST_MASK (1U << 2) + +/** Run-Time Functional Descriptor */ +struct dfu_runtime_descriptor { + uint8_t bLength; /**<\brief Descriptor length in bytes.*/ + uint8_t bDescriptorType; /**<\brief DFU functional descriptor type.*/ + uint8_t bmAttributes; /**<\brief USB DFU capabilities \ref USB_DFU_CAPAB*/ + uint16_t wDetachTimeout; /**<\brief USB DFU detach timeout in ms.*/ + uint16_t wTransferSize; /**<\brief USB DFU maximum transfer block size in bytes.*/ + uint16_t bcdDFUVersion; /**<\brief USB DFU version \ref VERSION_BCD utility macro.*/ +} __PACKED; + +/**\brief Payload packet to response in DFU_GETSTATUS request */ +struct dfu_info { + uint8_t bStatus; /**<\brief An indication of the status resulting from the + * execution of the most recent request.*/ + uint8_t bPollTimeout; /**<\brief Minimum time (LSB) in ms, that the host should wait + * before sending a subsequent DFU_GETSTATUS request.*/ + uint16_t wPollTimeout; /**<\brief Minimum time (MSB) in ms, that the host should wait + * before sending a subsequent DFU_GETSTATUS request.*/ + uint8_t bState; /**<\brief An indication of the state that the device is going + * to enter immediately following transmission of this response.*/ + uint8_t iString; /**<\brief Index of the status string descriptor.*/ +}; + +// clang-format off +#define DFU_DESCRIPTOR_INIT() \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + 0x00, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x00, /* bNumEndpoints Default Control Pipe only */ \ + USB_DEVICE_CLASS_APP_SPECIFIC, /* bInterfaceClass */ \ + 0x01, /* bInterfaceSubClass Device Firmware Upgrade */ \ + 0x02, /* bInterfaceProtocol DFU mode */ \ + 0x04, /* iInterface */ /*!< Device Firmware Update Functional Descriptor */ \ + 0x09, /* bLength */ \ + 0x21, /* DFU Functional Descriptor */ \ + 0x0B, /* bmAttributes */ \ + WBVAL(0x00ff), /* wDetachTimeOut */ \ + WBVAL(USBD_DFU_XFER_SIZE), /* wTransferSize */ \ + WBVAL(0x011a) /* bcdDFUVersion */ +// clang-format on + +#endif /* USB_DFU_H */ diff --git a/components/drivers/usb/cherryusb/class/dfu/usbd_dfu.c b/components/drivers/usb/cherryusb/class/dfu/usbd_dfu.c new file mode 100644 index 00000000000..a870aee3a94 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/dfu/usbd_dfu.c @@ -0,0 +1,505 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_dfu.h" + +/** Modify the following three parameters according to different platforms */ +#ifndef USBD_DFU_XFER_SIZE +#define USBD_DFU_XFER_SIZE 1024 +#endif + +#ifndef USBD_DFU_APP_DEFAULT_ADD +#define USBD_DFU_APP_DEFAULT_ADD 0x8004000 +#endif + +#ifndef FLASH_PROGRAM_TIME +#define FLASH_PROGRAM_TIME 50 +#endif + +#ifndef FLASH_ERASE_TIME +#define FLASH_ERASE_TIME 50 +#endif + +struct usbd_dfu_priv { + struct dfu_info info; + union { + uint32_t d32[USBD_DFU_XFER_SIZE / 4U]; + uint8_t d8[USBD_DFU_XFER_SIZE]; + } buffer; + + uint32_t wblock_num; + uint32_t wlength; + uint32_t data_ptr; + uint32_t alt_setting; + + uint8_t dev_status[6]; + uint8_t ReservedForAlign[2]; + uint8_t dev_state; + uint8_t manif_state; + uint8_t firmwar_flag; +} g_usbd_dfu; + +static void dfu_reset(void) +{ + memset(&g_usbd_dfu, 0, sizeof(g_usbd_dfu)); + + g_usbd_dfu.alt_setting = 0U; + g_usbd_dfu.data_ptr = USBD_DFU_APP_DEFAULT_ADD; + g_usbd_dfu.wblock_num = 0U; + g_usbd_dfu.wlength = 0U; + + g_usbd_dfu.manif_state = DFU_MANIFEST_COMPLETE; + g_usbd_dfu.dev_state = DFU_STATE_DFU_IDLE; + + g_usbd_dfu.dev_status[0] = DFU_STATUS_OK; + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = DFU_STATE_DFU_IDLE; + g_usbd_dfu.dev_status[5] = 0U; +} + +static uint16_t dfu_getstatus(uint32_t add, uint8_t cmd, uint8_t *buffer) +{ + switch (cmd) { + case DFU_MEDIA_PROGRAM: + buffer[1] = (uint8_t)FLASH_PROGRAM_TIME; + buffer[2] = (uint8_t)(FLASH_PROGRAM_TIME << 8); + buffer[3] = 0; + break; + + case DFU_MEDIA_ERASE: + buffer[1] = (uint8_t)FLASH_ERASE_TIME; + buffer[2] = (uint8_t)(FLASH_ERASE_TIME << 8); + buffer[3] = 0; + default: + + break; + } + return (0); +} + +static void dfu_request_detach(void) +{ + if ((g_usbd_dfu.dev_state == DFU_STATE_DFU_IDLE) || + (g_usbd_dfu.dev_state == DFU_STATE_DFU_DNLOAD_SYNC) || + (g_usbd_dfu.dev_state == DFU_STATE_DFU_DNLOAD_IDLE) || + (g_usbd_dfu.dev_state == DFU_STATE_DFU_MANIFEST_SYNC) || + (g_usbd_dfu.dev_state == DFU_STATE_DFU_UPLOAD_IDLE)) { + /* Update the state machine */ + g_usbd_dfu.dev_state = DFU_STATE_DFU_IDLE; + g_usbd_dfu.dev_status[0] = DFU_STATUS_OK; + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; /*bwPollTimeout=0ms*/ + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + g_usbd_dfu.dev_status[5] = 0U; /*iString*/ + g_usbd_dfu.wblock_num = 0U; + g_usbd_dfu.wlength = 0U; + } +} + +static void dfu_request_upload(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + struct usb_setup_packet *req = setup; + uint32_t addr; + uint8_t *phaddr; + /* Data setup request */ + if (req->wLength > 0U) { + if ((g_usbd_dfu.dev_state == DFU_STATE_DFU_IDLE) || (g_usbd_dfu.dev_state == DFU_STATE_DFU_UPLOAD_IDLE)) { + /* Update the global length and block number */ + g_usbd_dfu.wblock_num = req->wValue; + g_usbd_dfu.wlength = MIN(req->wLength, USBD_DFU_XFER_SIZE); + + /* DFU Get Command */ + if (g_usbd_dfu.wblock_num == 0U) { + /* Update the state machine */ + g_usbd_dfu.dev_state = (g_usbd_dfu.wlength > 3U) ? DFU_STATE_DFU_IDLE : DFU_STATE_DFU_UPLOAD_IDLE; + + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + + /* Store the values of all supported commands */ + g_usbd_dfu.buffer.d8[0] = DFU_CMD_GETCOMMANDS; + g_usbd_dfu.buffer.d8[1] = DFU_CMD_SETADDRESSPOINTER; + g_usbd_dfu.buffer.d8[2] = DFU_CMD_ERASE; + + /* Send the status data over EP0 */ + memcpy(*data, g_usbd_dfu.buffer.d8, 3); + *len = 3; + } else if (g_usbd_dfu.wblock_num > 1U) { + g_usbd_dfu.dev_state = DFU_STATE_DFU_UPLOAD_IDLE; + + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + + addr = ((g_usbd_dfu.wblock_num - 2U) * USBD_DFU_XFER_SIZE) + g_usbd_dfu.data_ptr; + + /* Return the physical address where data are stored */ + phaddr = dfu_read_flash((uint8_t *)addr, g_usbd_dfu.buffer.d8, g_usbd_dfu.wlength); + + /* Send the status data over EP0 */ + memcpy(*data, g_usbd_dfu.buffer.d8, g_usbd_dfu.wlength); + *len = g_usbd_dfu.wlength; + } else /* unsupported g_usbd_dfu.wblock_num */ + { + g_usbd_dfu.dev_state = DFU_STATUS_ERR_STALLEDPKT; + + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + + /* Call the error management function (command will be NAKed */ + USB_LOG_ERR("Dfu_request_upload unsupported g_usbd_dfu.wblock_num\r\n"); + } + } + /* Unsupported state */ + else { + g_usbd_dfu.wlength = 0U; + g_usbd_dfu.wblock_num = 0U; + + /* Call the error management function (command will be NAKed */ + USB_LOG_ERR("Dfu_request_upload unsupported state\r\n"); + } + } + /* No Data setup request */ + else { + g_usbd_dfu.dev_state = DFU_STATE_DFU_IDLE; + + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + } +} + +static void dfu_request_dnload(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + /* Data setup request */ + struct usb_setup_packet *req = setup; + if (req->wLength > 0U) { + if ((g_usbd_dfu.dev_state == DFU_STATE_DFU_IDLE) || (g_usbd_dfu.dev_state == DFU_STATE_DFU_DNLOAD_IDLE)) { + /* Update the global length and block number */ + g_usbd_dfu.wblock_num = req->wValue; + g_usbd_dfu.wlength = MIN(req->wLength, USBD_DFU_XFER_SIZE); + + /* Update the state machine */ + g_usbd_dfu.dev_state = DFU_STATE_DFU_DNLOAD_SYNC; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + + /*!< Data has received complete */ + memcpy((uint8_t *)g_usbd_dfu.buffer.d8, (uint8_t *)*data, g_usbd_dfu.wlength); + /*!< Set flag = 1 Write the firmware to the flash in the next dfu_request_getstatus */ + g_usbd_dfu.firmwar_flag = 1; + } + /* Unsupported state */ + else { + USB_LOG_ERR("Dfu_request_dnload unsupported state\r\n"); + } + } + /* 0 Data DNLOAD request */ + else { + /* End of DNLOAD operation*/ + if ((g_usbd_dfu.dev_state == DFU_STATE_DFU_DNLOAD_IDLE) || (g_usbd_dfu.dev_state == DFU_STATE_DFU_IDLE)) { + g_usbd_dfu.manif_state = DFU_MANIFEST_IN_PROGRESS; + g_usbd_dfu.dev_state = DFU_STATE_DFU_MANIFEST_SYNC; + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + } else { + /* Call the error management function (command will be NAKed */ + USB_LOG_ERR("Dfu_request_dnload End of DNLOAD operation but dev_state %02x \r\n", g_usbd_dfu.dev_state); + } + } +} + +static int8_t dfu_getstatus_special_handler(void) +{ + uint32_t addr; + if (g_usbd_dfu.dev_state == DFU_STATE_DFU_DNLOAD_BUSY) { + /* Decode the Special Command */ + if (g_usbd_dfu.wblock_num == 0U) { + if (g_usbd_dfu.wlength == 1U) { + if (g_usbd_dfu.buffer.d8[0] == DFU_CMD_GETCOMMANDS) { + /* Nothing to do */ + } + } else if (g_usbd_dfu.wlength == 5U) { + if (g_usbd_dfu.buffer.d8[0] == DFU_CMD_SETADDRESSPOINTER) { + g_usbd_dfu.data_ptr = g_usbd_dfu.buffer.d8[1]; + g_usbd_dfu.data_ptr += (uint32_t)g_usbd_dfu.buffer.d8[2] << 8; + g_usbd_dfu.data_ptr += (uint32_t)g_usbd_dfu.buffer.d8[3] << 16; + g_usbd_dfu.data_ptr += (uint32_t)g_usbd_dfu.buffer.d8[4] << 24; + } else if (g_usbd_dfu.buffer.d8[0] == DFU_CMD_ERASE) { + g_usbd_dfu.data_ptr = g_usbd_dfu.buffer.d8[1]; + g_usbd_dfu.data_ptr += (uint32_t)g_usbd_dfu.buffer.d8[2] << 8; + g_usbd_dfu.data_ptr += (uint32_t)g_usbd_dfu.buffer.d8[3] << 16; + g_usbd_dfu.data_ptr += (uint32_t)g_usbd_dfu.buffer.d8[4] << 24; + + USB_LOG_DBG("Erase start add %08x \r\n", g_usbd_dfu.data_ptr); + /*!< Erase */ + dfu_erase_flash(g_usbd_dfu.data_ptr); + } else { + return -1; + } + } else { + /* Reset the global length and block number */ + g_usbd_dfu.wlength = 0U; + g_usbd_dfu.wblock_num = 0U; + /* Call the error management function (command will be NAKed) */ + USB_LOG_ERR("Reset the global length and block number\r\n"); + } + } + /* Regular Download Command */ + else { + if (g_usbd_dfu.wblock_num > 1U) { + /* Decode the required address */ + addr = ((g_usbd_dfu.wblock_num - 2U) * USBD_DFU_XFER_SIZE) + g_usbd_dfu.data_ptr; + + /* Perform the write operation */ + /* Write flash */ + USB_LOG_DBG("Write start add %08x length %d\r\n", addr, g_usbd_dfu.wlength); + dfu_write_flash(g_usbd_dfu.buffer.d8, (uint8_t *)addr, g_usbd_dfu.wlength); + } + } + + /* Reset the global length and block number */ + g_usbd_dfu.wlength = 0U; + g_usbd_dfu.wblock_num = 0U; + + /* Update the state machine */ + g_usbd_dfu.dev_state = DFU_STATE_DFU_DNLOAD_SYNC; + + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + } + return 0; +} + +static void dfu_request_getstatus(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + /*!< Determine whether to leave DFU mode */ + if (g_usbd_dfu.manif_state == DFU_MANIFEST_IN_PROGRESS && + g_usbd_dfu.dev_state == DFU_STATE_DFU_MANIFEST_SYNC && + g_usbd_dfu.dev_status[1] == 0U && + g_usbd_dfu.dev_status[2] == 0U && + g_usbd_dfu.dev_status[3] == 0U && + g_usbd_dfu.dev_status[4] == g_usbd_dfu.dev_state) { + g_usbd_dfu.manif_state = DFU_MANIFEST_COMPLETE; + + if ((0x0B & DFU_MANIFEST_MASK) != 0U) { + g_usbd_dfu.dev_state = DFU_STATE_DFU_MANIFEST_SYNC; + + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + return; + } else { + g_usbd_dfu.dev_state = DFU_STATE_DFU_MANIFEST_WAIT_RESET; + + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + /* Generate system reset to allow jumping to the user code */ + dfu_leave(); + } + } + + switch (g_usbd_dfu.dev_state) { + case DFU_STATE_DFU_DNLOAD_SYNC: + if (g_usbd_dfu.wlength != 0U) { + g_usbd_dfu.dev_state = DFU_STATE_DFU_DNLOAD_BUSY; + + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + + if ((g_usbd_dfu.wblock_num == 0U) && (g_usbd_dfu.buffer.d8[0] == DFU_CMD_ERASE)) { + dfu_getstatus(g_usbd_dfu.data_ptr, DFU_MEDIA_ERASE, g_usbd_dfu.dev_status); + } else { + dfu_getstatus(g_usbd_dfu.data_ptr, DFU_MEDIA_PROGRAM, g_usbd_dfu.dev_status); + } + } else /* (g_usbd_dfu.wlength==0)*/ + { + g_usbd_dfu.dev_state = DFU_STATE_DFU_DNLOAD_IDLE; + + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + } + break; + + case DFU_STATE_DFU_MANIFEST_SYNC: + if (g_usbd_dfu.manif_state == DFU_MANIFEST_IN_PROGRESS) { + g_usbd_dfu.dev_state = DFU_STATE_DFU_MANIFEST; + + g_usbd_dfu.dev_status[1] = 1U; /*bwPollTimeout = 1ms*/ + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + } else { + if ((g_usbd_dfu.manif_state == DFU_MANIFEST_COMPLETE) && + ((0x0B & DFU_MANIFEST_MASK) != 0U)) { + g_usbd_dfu.dev_state = DFU_STATE_DFU_IDLE; + + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + } + } + break; + + default: + break; + } + + /* Send the status data over EP0 */ + memcpy(*data, g_usbd_dfu.dev_status, 6); + *len = 6; + + if (g_usbd_dfu.firmwar_flag == 1) { + if (dfu_getstatus_special_handler() != 0) { + USB_LOG_ERR("dfu_getstatus_special_handler error \r\n"); + } + g_usbd_dfu.firmwar_flag = 0; + } +} + +static void dfu_request_clrstatus(void) +{ + if (g_usbd_dfu.dev_state == DFU_STATE_DFU_ERROR) { + g_usbd_dfu.dev_state = DFU_STATE_DFU_IDLE; + g_usbd_dfu.dev_status[0] = DFU_STATUS_OK; /* bStatus */ + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; /* bwPollTimeout=0ms */ + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; /* bState */ + g_usbd_dfu.dev_status[5] = 0U; /* iString */ + } else { + /* State Error */ + g_usbd_dfu.dev_state = DFU_STATE_DFU_ERROR; + g_usbd_dfu.dev_status[0] = DFU_STATUS_ERR_UNKNOWN; /* bStatus */ + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; /* bwPollTimeout=0ms */ + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; /* bState */ + g_usbd_dfu.dev_status[5] = 0U; /* iString */ + } +} + +static void dfu_request_getstate(struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + /* Return the current state of the DFU interface */ + (*data)[0] = g_usbd_dfu.dev_state; + *len = 1; +} + +void dfu_request_abort(void) +{ + if ((g_usbd_dfu.dev_state == DFU_STATE_DFU_IDLE) || + (g_usbd_dfu.dev_state == DFU_STATE_DFU_DNLOAD_SYNC) || + (g_usbd_dfu.dev_state == DFU_STATE_DFU_DNLOAD_IDLE) || + (g_usbd_dfu.dev_state == DFU_STATE_DFU_MANIFEST_SYNC) || + (g_usbd_dfu.dev_state == DFU_STATE_DFU_UPLOAD_IDLE)) { + g_usbd_dfu.dev_state = DFU_STATE_DFU_IDLE; + g_usbd_dfu.dev_status[0] = DFU_STATUS_OK; + g_usbd_dfu.dev_status[1] = 0U; + g_usbd_dfu.dev_status[2] = 0U; + g_usbd_dfu.dev_status[3] = 0U; /* bwPollTimeout=0ms */ + g_usbd_dfu.dev_status[4] = g_usbd_dfu.dev_state; + g_usbd_dfu.dev_status[5] = 0U; /* iString */ + g_usbd_dfu.wblock_num = 0U; + g_usbd_dfu.wlength = 0U; + } +} + +static int dfu_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("DFU Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + switch (setup->bRequest) { + case DFU_REQUEST_DETACH: + dfu_request_detach(); + break; + case DFU_REQUEST_DNLOAD: + dfu_request_dnload(setup, data, len); + break; + case DFU_REQUEST_UPLOAD: + dfu_request_upload(setup, data, len); + break; + case DFU_REQUEST_GETSTATUS: + dfu_request_getstatus(setup, data, len); + break; + case DFU_REQUEST_CLRSTATUS: + dfu_request_clrstatus(); + break; + case DFU_REQUEST_GETSTATE: + dfu_request_getstate(setup, data, len); + break; + case DFU_REQUEST_ABORT: + dfu_request_abort(); + break; + default: + USB_LOG_WRN("Unhandled DFU Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +static void dfu_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + dfu_reset(); + break; + default: + break; + } +} + +struct usbd_interface *usbd_dfu_init_intf(struct usbd_interface *intf) +{ + intf->class_interface_handler = dfu_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = dfu_notify_handler; + + return intf; +} + +__WEAK uint8_t *dfu_read_flash(uint8_t *src, uint8_t *dest, uint32_t len) +{ + return dest; +} + +__WEAK uint16_t dfu_write_flash(uint8_t *src, uint8_t *dest, uint32_t len) +{ + return 0; +} + +__WEAK uint16_t dfu_erase_flash(uint32_t add) +{ + return 0; +} + +__WEAK void dfu_leave(void) +{ +} diff --git a/components/drivers/usb/cherryusb/class/dfu/usbd_dfu.h b/components/drivers/usb/cherryusb/class/dfu/usbd_dfu.h new file mode 100644 index 00000000000..9081d0dda1c --- /dev/null +++ b/components/drivers/usb/cherryusb/class/dfu/usbd_dfu.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_DFU_H +#define USBD_DFU_H + +#include "usb_dfu.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init dfu interface driver */ +struct usbd_interface *usbd_dfu_init_intf(struct usbd_interface *intf); + +/* Interface functions that need to be implemented by the user */ +uint8_t *dfu_read_flash(uint8_t *src, uint8_t *dest, uint32_t len); +uint16_t dfu_write_flash(uint8_t *src, uint8_t *dest, uint32_t len); +uint16_t dfu_erase_flash(uint32_t add); +void dfu_leave(void); +#ifdef __cplusplus +} +#endif + +#endif /* USBD_DFU_H */ diff --git a/components/drivers/usb/cherryusb/class/hid/usb_hid.h b/components/drivers/usb/cherryusb/class/hid/usb_hid.h new file mode 100644 index 00000000000..5a88a34be47 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/hid/usb_hid.h @@ -0,0 +1,585 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HID_H +#define USB_HID_H + +/* Subclass codes (HID 4.2) */ +#define HID_SUBCLASS_NONE 0 /* No subclass */ +#define HID_SUBCLASS_BOOTIF 1 /* Boot Interface Subclass */ + +/* HID Protocol Codes (HID 4.3) */ +#define HID_PROTOCOL_NONE 0x00 +#define HID_PROTOCOL_BOOT 0x00 +#define HID_PROTOCOL_KEYBOARD 0x01 +#define HID_PROTOCOL_REPORT 0x01 +#define HID_PROTOCOL_MOUSE 0x02 + +/* HID Class Descriptor Types (HID 7.1) */ +#define HID_DESCRIPTOR_TYPE_HID 0x21 +#define HID_DESCRIPTOR_TYPE_HID_REPORT 0x22 +#define HID_DESCRIPTOR_TYPE_HID_PHYSICAL 0x23 + +/* HID Class Specific Requests (HID 7.2) */ +#define HID_REQUEST_GET_REPORT 0x01 +#define HID_REQUEST_GET_IDLE 0x02 +#define HID_REQUEST_GET_PROTOCOL 0x03 +#define HID_REQUEST_SET_REPORT 0x09 +#define HID_REQUEST_SET_IDLE 0x0A +#define HID_REQUEST_SET_PROTOCOL 0x0B + +/* Report Type (MS byte of wValue for GET_REPORT) (HID 7.2.1) */ +#define HID_REPORT_INPUT 0x01 +#define HID_REPORT_OUTPUT 0x02 +#define HID_REPORT_FEATURE 0x03 + +/* HID Descriptor ***********************************************************/ + +#define HID_COUNTRY_NONE 0x00 /* Not Supported */ +#define HID_COUNTRY_ARABIC 0x01 /* Arabic */ +#define HID_COUNTRY_BELGIAN 0x02 /* Belgian */ +#define HID_COUNTRY_CANADA 0x03 /* Canadian-Bilingual */ +#define HID_COUNTRY_CANADRFR 0x04 /* Canadian-French */ +#define HID_COUNTRY_CZECH 0x05 /* Czech Republic */ +#define HID_COUNTRY_DANISH 0x06 /* Danish */ +#define HID_COUNTRY_FINNISH 0x07 /* Finnish */ +#define HID_COUNTRY_FRENCH 0x08 /* French */ +#define HID_COUNTRY_GERMAN 0x09 /* German */ +#define HID_COUNTRY_GREEK 0x10 /* Greek */ +#define HID_COUNTRY_HEBREW 0x11 /* Hebrew */ +#define HID_COUNTRY_HUNGARY 0x12 /* Hungary */ +#define HID_COUNTRY_ISO 0x13 /* International (ISO) */ +#define HID_COUNTRY_ITALIAN 0x14 /* Italian */ +#define HID_COUNTRY_JAPAN 0x15 /* Japan (Katakana) */ +#define HID_COUNTRY_KOREAN 0x16 /* Korean */ +#define HID_COUNTRY_LATINAM 0x17 /* Latin American */ +#define HID_COUNTRY_DUTCH 0x18 /* Netherlands/Dutch */ +#define HID_COUNTRY_NORWEGIAN 0x19 /* Norwegian */ +#define HID_COUNTRY_PERSIAN 0x20 /* Persian (Farsi) */ +#define HID_COUNTRY_POLAND 0x21 /* Poland */ +#define HID_COUNTRY_PORTUGUESE 0x22 /* Portuguese */ +#define HID_COUNTRY_RUSSIA 0x23 /* Russia */ +#define HID_COUNTRY_SLOVAKIA 0x24 /* Slovakia */ +#define HID_COUNTRY_SPANISH 0x25 /* Spanish */ +#define HID_COUNTRY_SWEDISH 0x26 /* Swedish */ +#define HID_COUNTRY_SWISSFR 0x27 /* Swiss/French */ +#define HID_COUNTRY_SWISSGR 0x28 /* Swiss/German */ +#define HID_COUNTRY_SWITZERLAND 0x29 /* Switzerland */ +#define HID_COUNTRY_TAIWAN 0x30 /* Taiwan */ +#define HID_COUNTRY_TURKISHQ 0x31 /* Turkish-Q */ +#define HID_COUNTRY_UK 0x32 /* UK */ +#define HID_COUNTRY_US 0x33 /* US */ +#define HID_COUNTRY_YUGOSLAVIA 0x34 /* Yugoslavia */ +#define HID_COUNTRY_TURKISHF 0x35 /* Turkish-F */ + +/* HID report items */ +#define HID_REPORT_ITEM_SIZE_MASK 0x03 +#define HID_REPORT_ITEM_SIZE_0 0x00 /* No data follows */ +#define HID_REPORT_ITEM_SIZE_1 0x01 /* 1 byte of data follows */ +#define HID_REPORT_ITEM_SIZE_2 0x02 /* 2 bytes of data follow */ +#define HID_REPORT_ITEM_SIZE_4 0x03 /* 4 bytes of data follow */ +#define HID_REPORT_ITEM_TYPE_MASK 0x0c +#define HID_REPORT_ITEM_TYPE_MAIN 0x00 +#define HID_REPORT_ITEM_TYPE_GLOBAL 0x04 +#define HID_REPORT_ITEM_TYPE_LOCAL 0x08 +#define HID_REPORT_ITEM_TAG_MASK 0xf0 + +/* Main Items (HID 6.2.2.4) */ +#define HID_MAIN_ITEM_CONSTANT (1 << 0) /* Constant(1) vs Data(0) */ +#define HID_MAIN_ITEM_VARIABLE (1 << 1) /* Variable(1) vs Array(0) */ +#define HID_MAIN_ITEM_RELATIVE (1 << 2) /* Relative(1) vs Absolute(0) */ +#define HID_MAIN_ITEM_WRAP (1 << 3) /* Wrap(1) vs No Wrap(0) */ +#define HID_MAIN_ITEM_NONLINEAR (1 << 4) /* Non Linear(1) vs Linear(0) */ +#define HID_MAIN_ITEM_NOPREFERRED (1 << 5) /* No Preferred (1) vs Preferred State(0) */ +#define HID_MAIN_ITEM_NULLSTATE (1 << 6) /* Null state(1) vs No Null position(0) */ +#define HID_MAIN_ITEM_VOLATILE (1 << 7) /* Volatile(1) vs Non volatile(0) */ +#define HID_MAIN_ITEM_BUFFEREDBYTES (1 << 8) /* Buffered Bytes(1) vs Bit Field(0) */ + +#define HID_MAIN_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) +#define HID_MAIN_ITEM_INPUT_PREFIX 0x80 +#define HID_MAIN_ITEM_INPUT_CONSTANT HID_MAIN_ITEM_CONSTANT +#define HID_MAIN_ITEM_INPUT_VARIABLE HID_MAIN_ITEM_VARIABLE +#define HID_MAIN_ITEM_INPUT_RELATIVE HID_MAIN_ITEM_RELATIVE +#define HID_MAIN_ITEM_INPUT_WRAP HID_MAIN_ITEM_WRAP +#define HID_MAIN_ITEM_INPUT_NONLINEAR HID_MAIN_ITEM_NONLINEAR +#define HID_MAIN_ITEM_INPUT_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED +#define HID_MAIN_ITEM_INPUT_NULLSTATE HID_MAIN_ITEM_NULLSTATE +#define HID_MAIN_ITEM_INPUT_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES + +#define HID_MAIN_ITEM_OUTPUT_PREFIX 0x90 +#define HID_MAIN_ITEM_OUTPUT_CONSTANT HID_MAIN_ITEM_CONSTANT +#define HID_MAIN_ITEM_OUTPUT_VARIABLE HID_MAIN_ITEM_VARIABLE +#define HID_MAIN_ITEM_OUTPUT_RELATIVE HID_MAIN_ITEM_RELATIVE +#define HID_MAIN_ITEM_OUTPUT_WRAP HID_MAIN_ITEM_WRAP +#define HID_MAIN_ITEM_OUTPUT_NONLINEAR HID_MAIN_ITEM_NONLINEAR +#define HID_MAIN_ITEM_OUTPUT_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED +#define HID_MAIN_ITEM_OUTPUT_NULLSTATE HID_MAIN_ITEM_NULLSTATE +#define HID_MAIN_ITEM_OUTPUT_VOLATILE HID_MAIN_ITEM_VOLATILE +#define HID_MAIN_ITEM_OUTPUT_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES + +#define HID_MAIN_ITEM_FEATURE_PREFIX 0xb0 +#define HID_MAIN_ITEM_FEATURE_CONSTANT HID_MAIN_ITEM_CONSTANT +#define HID_MAIN_ITEM_FEATURE_VARIABLE HID_MAIN_ITEM_VARIABLE +#define HID_MAIN_ITEM_FEATURE_RELATIVE HID_MAIN_ITEM_RELATIVE +#define HID_MAIN_ITEM_FEATURE_WRAP HID_MAIN_ITEM_WRAP +#define HID_MAIN_ITEM_FEATURE_NONLINEAR HID_MAIN_ITEM_NONLINEAR +#define HID_MAIN_ITEM_FEATURE_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED +#define HID_MAIN_ITEM_FEATURE_NULLSTATE HID_MAIN_ITEM_NULLSTATE +#define HID_MAIN_ITEM_FEATURE_VOLATILE HID_MAIN_ITEM_VOLATILE +#define HID_MAIN_ITEM_FEATURE_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES + +#define HID_MAIN_ITEM_COLLECTION_PREFIX 0xa0 +#define HID_MAIN_ITEM_COLLECTION_PHYSICAL 0x00 /* Physical (group of axes) */ +#define HID_MAIN_ITEM_COLLECTION_APPL 0x01 /* Application (mouse, keyboard) */ +#define HID_MAIN_ITEM_COLLECTION_LOGICAL 0x02 /* Logical (interrelated data) */ +#define HID_MAIN_ITEM_COLLECTION_REPORT 0x03 /* Report */ +#define HID_MAIN_ITEM_COLLECTION_ARRAY 0x04 /* Named Array */ +#define HID_MAIN_ITEM_COLLECTION_SWITCH 0x05 /* Usage Switch */ +#define HID_MAIN_ITEM_COLLECTION_MODIFIER 0x06 /* Usage Modifier */ +#define HID_MAIN_ITEM_ENDCOLLECTION_PREFIX 0xc0 + +/* Global Items (HID 6.2.2.7) */ +#define HID_GLOBAL_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) +#define HID_GLOBAL_ITEM_USAGEPAGE_PREFIX 0x04 /* Usage Page */ +#define HID_GLOBAL_ITEM_LOGICALMIN_PREFIX 0x14 /* Logical Minimum */ +#define HID_GLOBAL_ITEM_LOGICALMAX_PREFIX 0x24 /* Logical Maximum */ +#define HID_GLOBAL_ITEM_PHYSICALMIN_PREFIX 0x34 /* Physical Minimum */ +#define HID_GLOBAL_ITEM_PHYSMICALAX_PREFIX 0x44 /* Physical Maximum */ +#define HID_GLOBAL_ITEM_UNITEXP_PREFIX 0x54 /* Unit Exponent */ +#define HID_GLOBAL_ITEM_UNIT_PREFIX 0x64 /* Unit */ +#define HID_GLOBAL_ITEM_REPORTSIZE_PREFIX 0x74 /* Report Size */ +#define HID_GLOBAL_ITEM_REPORTID_PREFIX 0x84 /* Report ID */ +#define HID_GLOBAL_ITEM_REPORTCOUNT_PREFIX 0x94 /* Report Count */ +#define HID_GLOBAL_ITEM_PUSH_PREFIX 0xa4 /* Push */ +#define HID_GLOBAL_ITEM_POP_PREFIX 0xb4 /* Pop */ + +/* Local Items (HID 6.2.2.8) */ +#define HID_LOCAL_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) +#define HID_LOCAL_ITEM_USAGE_PREFIX 0x08 /* Usage */ +#define HID_LOCAL_ITEM_USAGEMIN_PREFIX 0x18 /* Usage Minimum */ +#define HID_LOCAL_ITEM_USAGEMAX_PREFIX 0x28 /* Usage Maximum */ +#define HID_LOCAL_ITEM_DESIGNATORIDX_PREFIX 0x38 /* Designator Index */ +#define HID_LOCAL_ITEM_DESIGNATORMIN_PREFIX 0x48 /* Designator Minimum */ +#define HID_LOCAL_ITEM_DESIGNATORMAX_PREFIX 0x58 /* Designator Maximum */ +#define HID_LOCAL_ITEM_STRINGIDX_PREFIX 0x78 /* String Index */ +#define HID_LOCAL_ITEM_STRINGMIN_PREFIX 0x88 /* String Minimum */ +#define HID_LOCAL_ITEM_STRINGMAX_PREFIX 0x98 /* xx */ +#define HID_LOCAL_ITEM_DELIMITER_PREFIX 0xa8 /* Delimiter */ + +/* Modifier Keys (HID 8.3) */ +#define HID_MODIFER_LCTRL (1 << 0) /* Left Ctrl */ +#define HID_MODIFER_LSHIFT (1 << 1) /* Left Shift */ +#define HID_MODIFER_LALT (1 << 2) /* Left Alt */ +#define HID_MODIFER_LGUI (1 << 3) /* Left GUI */ +#define HID_MODIFER_RCTRL (1 << 4) /* Right Ctrl */ +#define HID_MODIFER_RSHIFT (1 << 5) /* Right Shift */ +#define HID_MODIFER_RALT (1 << 6) /* Right Alt */ +#define HID_MODIFER_RGUI (1 << 7) /* Right GUI */ + +/* Keyboard output report (1 byte) (HID B.1) */ +#define HID_KBD_OUTPUT_REPORT_NUMLOCK (1 << 0) +#define HID_KBD_OUTPUT_REPORT_CAPSLOCK (1 << 1) +#define HID_KBD_OUTPUT_REPORT_SCROLLLOCK (1 << 2) +#define HID_KBD_OUTPUT_REPORT_COMPOSE (1 << 3) +#define HID_KBD_OUTPUT_REPORT_KANA (1 << 4) + +/* Mouse input report (HID B.2) */ +#define HID_MOUSE_INPUT_REPORT_BUTTON1 (1 << 0) +#define HID_MOUSE_INPUT_REPORT_BUTTON2 (1 << 1) +#define HID_MOUSE_INPUT_REPORT_BUTTON3 (1 << 2) +#define HID_MOUSE_INPUT_REPORT_BUTTON_MASK (7) + +#define HID_MOUSE_INPUT_BUTTON_LEFT (1 << 0) +#define HID_MOUSE_INPUT_BUTTON_RIGHT (1 << 1) +#define HID_MOUSE_INPUT_BUTTON_MIDDLE (1 << 2) +#define HID_MOUSE_INPUT_BUTTON_BACKWARD (1 << 3) +#define HID_MOUSE_INPUT_BUTTON_FORWARD (1 << 4) + +/* Joystick input report (4 bytes) (HID D.1) */ +#define HID_JS_INPUT_REPORT_HATSWITCH_SHIFT (0) +#define HID_JS_INPUT_REPORT_HATSWITCH_MASK (15 << HID_JSIN_HATSWITCH_SHIFT) +#define HID_JS_INPUT_REPORT_BUTTON1 (1 << 4) +#define HID_JS_INPUT_REPORT_BUTTON2 (1 << 5) +#define HID_JS_INPUT_REPORT_BUTTON3 (1 << 6) +#define HID_JS_INPUT_REPORT_BUTTON4 (1 << 7) + +/* Usage pages (HuT 3) */ +#define HID_USAGE_PAGE_UNDEFINED 0x00 /* Undefined */ +#define HID_USAGE_PAGE_GENERIC_DCTRL 0x01 /* Generic Desktop Controls */ +#define HID_USAGE_PAGE_SIMCTRL 0x02 /* Simulation Controls */ +#define HID_USAGE_PAGE_VRCTRL 0x03 /* VR Controls */ +#define HID_USAGE_PAGE_SPORTCTRL 0x04 /* Sport Controls */ +#define HID_USAGE_PAGE_GAMECTRL 0x05 /* Game Controls */ +#define HID_USAGE_PAGE_GENERIC_DEVCTRL 0x06 /* Generic Device Controls */ +#define HID_USAGE_PAGE_KBD 0x07 /* Keyboard/Keypad */ +#define HID_USAGE_PAGE_LEDS 0x08 /* LEDs */ +#define HID_USAGE_PAGE_BUTTON 0x09 /* Button */ +#define HID_USAGE_PAGE_ORDINAL 0x0a /* Ordinal */ +#define HID_USAGE_PAGE_TELEPHONY 0x0b /* Telephony */ +#define HID_USAGE_PAGE_CONSUMER 0x0c /* Consumer */ +#define HID_USAGE_PAGE_DIGITIZER 0x0d /* Digitizer */ + /* 0x0e Reserved */ +#define HID_USAGE_PAGE_PIDPAGE 0x0f /* PID Page Physical Interface Device */ +#define HID_USAGE_PAGE_UNICODE 0x10 /* Unicode */ + /* 0x11-13 Reserved */ +#define HID_USAGE_PAGE_ALPHA_DISPLAY 0x14 /* Alphanumeric Display */ + /* 0x15-3f Reserved */ +#define HID_USAGE_PAGE_MEDICAL 0x40 /* Medical Instruments */ + /* 0x41-7f Reserved */ + /* 0x80-83 Monitor Devices */ + /* 0x84-87 Power Devices */ + /* 0x88-8b Reserved */ +#define HID_USAGE_PAGE_BARCODE_SCANNER 0x8c /* Bar Code Scanner page */ +#define HID_USAGE_PAGE_SCALE 0x8d /* Scale page */ +#define HID_USAGE_PAGE_MSR 0x8e /* Magnetic Stripe Reading (MSR) Devices */ +#define HID_USAGE_PAGE_POS 0x8f /* Point of Sale devices */ +#define HID_USAGE_PAGE_CAMERA_CTRL 0x90 /* Camera Control Page */ + +/* Generic Desktop Page Usage IDs (HuT 4) */ +#define HID_DESKTOP_USAGE_UNDEFINED 0x00 /* Undefined */ +#define HID_DESKTOP_USAGE_POINTER 0x01 /* Pointer */ +#define HID_DESKTOP_USAGE_MOUSE 0x02 /* Mouse */ + /* 0x03 Reserved */ +#define HID_DESKTOP_USAGE_JOYSTICK 0x04 /* Joystick */ +#define HID_DESKTOP_USAGE_GAMEPAD 0x05 /* Game Pad */ +#define HID_DESKTOP_USAGE_KEYBOARD 0x06 /* Keyboard */ +#define HID_DESKTOP_USAGE_KEYPAD 0x07 /* Keypad */ +#define HID_DESKTOP_USAGE_MULTIAXIS 0x08 /* Multi-axis Controller */ +#define HID_DESKTOP_USAGE_TABLET 0x09 /* Tablet PC System Controls */ + /* 0x0a-2f Reserved */ +#define HID_DESKTOP_USAGE_X 0x30 /* X */ +#define HID_DESKTOP_USAGE_Y 0x31 /* Y */ +#define HID_DESKTOP_USAGE_Z 0x32 /* Z */ +#define HID_DESKTOP_USAGE_RX 0x33 /* Rx */ +#define HID_DESKTOP_USAGE_RY 0x34 /* Ry */ +#define HID_DESKTOP_USAGE_RZ 0x35 /* Rz */ +#define HID_DESKTOP_USAGE_SLIDER 0x36 /* Slider */ +#define HID_DESKTOP_USAGE_DIAL 0x37 /* Dial */ +#define HID_DESKTOP_USAGE_WHEEL 0x38 /* Wheel */ +#define HID_DESKTOP_USAGE_HATSWITCH 0x39 /* Hat switch */ +#define HID_DESKTOP_USAGE_COUNTED 0x3a /* Counted Buffer */ +#define HID_DESKTOP_USAGE_BYTECOUNT 0x3b /* Byte Count */ +#define HID_DESKTOP_USAGE_MOTION 0x3c /* Motion Wakeup */ +#define HID_DESKTOP_USAGE_START 0x3d /* Start */ +#define HID_DESKTOP_USAGE_SELECT 0x3e /* Select */ + /* 0x3f Reserved */ +#define HID_DESKTOP_USAGE_VX 0x40 /* Vx */ +#define HID_DESKTOP_USAGE_VY 0x41 /* Vy */ +#define HID_DESKTOP_USAGE_VZ 0x42 /* Vz */ +#define HID_DESKTOP_USAGE_VBRX 0x43 /* Vbrx */ +#define HID_DESKTOP_USAGE_VBRY 0x44 /* Vbry */ +#define HID_DESKTOP_USAGE_VBRZ 0x45 /* Vbrz */ +#define HID_DESKTOP_USAGE_VNO 0x46 /* Vno */ +#define HID_DESKTOP_USAGE_FEATURE 0x47 /* Feature Notification */ +#define HID_DESKTOP_USAGE_RESOLUTION 0x48 /* Resolution Multiplier */ + /* 0x49-7f Reserved */ +#define HID_DESKTOP_USAGE_CONTROL 0x80 /* System Control */ +#define HID_DESKTOP_USAGE_POWERDOWN 0x81 /* System Power Down */ +#define HID_DESKTOP_USAGE_SLEEP 0x82 /* System Sleep */ +#define HID_DESKTOP_USAGE_WAKEUP 0x83 /* System Wake Up */ +#define HID_DESKTOP_USAGE_CONTEXT_MENU 0x84 /* System Context Menu */ +#define HID_DESKTOP_USAGE_MAIN_MENU 0x85 /* System Main Menu */ +#define HID_DESKTOP_USAGE_APP_MENU 0x86 /* System App Menu */ +#define HID_DESKTOP_USAGE_MENU_HELP 0x87 /* System Menu Help */ +#define HID_DESKTOP_USAGE_MENU_EXIT 0x88 /* System Menu Exit */ +#define HID_DESKTOP_USAGE_MENU_SELECT 0x89 /* System Menu Select */ +#define HID_DESKTOP_USAGE_MENU_RIGHT 0x8a /* System Menu Right */ +#define HID_DESKTOP_USAGE_MENU_LEFT 0x8b /* System Menu Left */ +#define HID_DESKTOP_USAGE_MENU_UP 0x8c /* System Menu Up */ +#define HID_DESKTOP_USAGE_MENU_DOWN 0x8d /* System Menu Down */ +#define HID_DESKTOP_USAGE_COLD_RESTART 0x8e /* System Cold Restart */ +#define HID_DESKTOP_USAGE_WARM_RESTART 0x8f /* System Warm Restart */ +#define HID_DESKTOP_USAGE_DPAD_UP 0x90 /* D-pad Up */ +#define HID_DESKTOP_USAGE_DPAD_DOWN 0x91 /* D-pad Down */ +#define HID_DESKTOP_USAGE_DPAD_RIGHT 0x92 /* D-pad Right */ +#define HID_DESKTOP_USAGE_DPAD_LEFT 0x93 /* D-pad Left */ + /* 0x94-9f Reserved */ +#define HID_DESKTOP_USAGE_DOCK 0xa0 /* System Dock */ +#define HID_DESKTOP_USAGE_UNDOCK 0xa1 /* System Undock */ +#define HID_DESKTOP_USAGE_SETUP 0xa2 /* System Setup */ +#define HID_DESKTOP_USAGE_BREAK 0xa3 /* System Break */ +#define HID_DESKTOP_USAGE_DEBUG_BREAK 0xa4 /* System Debugger Break */ +#define HID_DESKTOP_USAGE_APP_BREAK 0xa5 /* Application Break */ +#define HID_DESKTOP_USAGE_APP_DEBUG_BREAK 0xa6 /* Application Debugger Break */ +#define HID_DESKTOP_USAGE_MUTE 0xa7 /* System Speaker Mute */ +#define HID_DESKTOP_USAGE_HIBERNATE 0xa8 /* System Hibernate */ + /* 0xa9-af Reserved */ +#define HID_DESKTOP_USAGE_DISPLAY_INVERT 0xb0 /* System Display Invert */ +#define HID_DESKTOP_USAGE_DISPALY_INTERNAL 0xb1 /* System Display Internal */ +#define HID_DESKTOP_USAGE_DISPLAY_EXTERNAL 0xb2 /* System Display External */ +#define HID_DESKTOP_USAGE_DISPLAY_BOTH 0xb3 /* System Display Both */ +#define HID_DESKTOP_USAGE_DISPLAY_DUAL 0xb4 /* System Display Dual */ +#define HID_DESKTOP_USAGE_DISPLAY_TOGGLE 0xb5 /* System Display Toggle Int/Ext */ +#define HID_DESKTOP_USAGE_DISPLAY_SWAP 0xb6 /* System Display Swap */ +#define HID_DESKTOP_USAGE_ 0xb7 /* System Display LCD Autoscale */ + /* 0xb8-ffff Reserved */ + +/* Keyboard usage IDs (HuT 10) */ +#define HID_KBD_USAGE_NONE 0x00 /* Reserved (no event indicated) */ +#define HID_KBD_USAGE_ERRORROLLOVER 0x01 /* Keyboard ErrorRollOver */ +#define HID_KBD_USAGE_POSTFAIL 0x02 /* Keyboard POSTFail */ +#define HID_KBD_USAGE_ERRUNDEF 0x03 /* Keyboard ErrorUndefined */ +#define HID_KBD_USAGE_A 0x04 /* Keyboard a or A (B-Z follow) */ +#define HID_KBD_USAGE_1 0x1e /* Keyboard 1 (2-9 follow) */ +#define HID_KBD_USAGE_EXCLAM 0x1e /* Keyboard 1 and ! */ +#define HID_KBD_USAGE_AT 0x1f /* Keyboard 2 and @ */ +#define HID_KBD_USAGE_POUND 0x20 /* Keyboard 3 and # */ +#define HID_KBD_USAGE_DOLLAR 0x21 /* Keyboard 4 and $ */ +#define HID_KBD_USAGE_PERCENT 0x22 /* Keyboard 5 and % */ +#define HID_KBD_USAGE_CARAT 0x23 /* Keyboard 6 and ^ */ +#define HID_KBD_USAGE_AMPERSAND 0x24 /* Keyboard 7 and & */ +#define HID_KBD_USAGE_ASTERISK 0x25 /* Keyboard 8 and * */ +#define HID_KBD_USAGE_LPAREN 0x26 /* Keyboard 9 and ( */ +#define HID_KBD_USAGE_0 0x27 /* Keyboard 0 and ) */ +#define HID_KBD_USAGE_RPAREN 0x27 /* Keyboard 0 and ) */ +#define HID_KBD_USAGE_ENTER 0x28 /* Keyboard Return (ENTER) */ +#define HID_KBD_USAGE_ESCAPE 0x29 /* Keyboard ESCAPE */ +#define HID_KBD_USAGE_DELETE 0x2a /* Keyboard DELETE (Backspace) */ +#define HID_KBD_USAGE_TAB 0x2b /* Keyboard Tab */ +#define HID_KBD_USAGE_SPACE 0x2c /* Keyboard Spacebar */ +#define HID_KBD_USAGE_HYPHEN 0x2d /* Keyboard - and (underscore) */ +#define HID_KBD_USAGE_UNDERSCORE 0x2d /* Keyboard - and (underscore) */ +#define HID_KBD_USAGE_EQUAL 0x2e /* Keyboard = and + */ +#define HID_KBD_USAGE_PLUS 0x2e /* Keyboard = and + */ +#define HID_KBD_USAGE_LBRACKET 0x2f /* Keyboard [ and { */ +#define HID_KBD_USAGE_LBRACE 0x2f /* Keyboard [ and { */ +#define HID_KBD_USAGE_RBRACKET 0x30 /* Keyboard ] and } */ +#define HID_KBD_USAGE_RBRACE 0x30 /* Keyboard ] and } */ +#define HID_KBD_USAGE_BSLASH 0x31 /* Keyboard \ and | */ +#define HID_KBD_USAGE_VERTBAR 0x31 /* Keyboard \ and | */ +#define HID_KBD_USAGE_NONUSPOUND 0x32 /* Keyboard Non-US # and ~ */ +#define HID_KBD_USAGE_TILDE 0x32 /* Keyboard Non-US # and ~ */ +#define HID_KBD_USAGE_SEMICOLON 0x33 /* Keyboard ; and : */ +#define HID_KBD_USAGE_COLON 0x33 /* Keyboard ; and : */ +#define HID_KBD_USAGE_SQUOTE 0x34 /* Keyboard ' and " */ +#define HID_KBD_USAGE_DQUOUTE 0x34 /* Keyboard ' and " */ +#define HID_KBD_USAGE_GACCENT 0x35 /* Keyboard Grave Accent and Tilde */ +#define HID_KBD_USAGE_GTILDE 0x35 /* Keyboard Grave Accent and Tilde */ +#define HID_KBD_USAGE_COMMON 0x36 /* Keyboard , and < */ +#define HID_KBD_USAGE_LT 0x36 /* Keyboard , and < */ +#define HID_KBD_USAGE_PERIOD 0x37 /* Keyboard . and > */ +#define HID_KBD_USAGE_GT 0x37 /* Keyboard . and > */ +#define HID_KBD_USAGE_DIV 0x38 /* Keyboard / and ? */ +#define HID_KBD_USAGE_QUESTION 0x38 /* Keyboard / and ? */ +#define HID_KBD_USAGE_CAPSLOCK 0x39 /* Keyboard Caps Lock */ +#define HID_KBD_USAGE_F1 0x3a /* Keyboard F1 */ +#define HID_KBD_USAGE_F2 0x3b /* Keyboard F2 */ +#define HID_KBD_USAGE_F3 0x3c /* Keyboard F3 */ +#define HID_KBD_USAGE_F4 0x3d /* Keyboard F4 */ +#define HID_KBD_USAGE_F5 0x3e /* Keyboard F5 */ +#define HID_KBD_USAGE_F6 0x3f /* Keyboard F6 */ +#define HID_KBD_USAGE_F7 0x40 /* Keyboard F7 */ +#define HID_KBD_USAGE_F8 0x41 /* Keyboard F8 */ +#define HID_KBD_USAGE_F9 0x42 /* Keyboard F9 */ +#define HID_KBD_USAGE_F10 0x43 /* Keyboard F10 */ +#define HID_KBD_USAGE_F11 0x44 /* Keyboard F11 */ +#define HID_KBD_USAGE_F12 0x45 /* Keyboard F12 */ +#define HID_KBD_USAGE_PRINTSCN 0x46 /* Keyboard PrintScreen */ +#define HID_KBD_USAGE_SCROLLLOCK 0x47 /* Keyboard Scroll Lock */ +#define HID_KBD_USAGE_PAUSE 0x48 /* Keyboard Pause */ +#define HID_KBD_USAGE_INSERT 0x49 /* Keyboard Insert */ +#define HID_KBD_USAGE_HOME 0x4a /* Keyboard Home */ +#define HID_KBD_USAGE_PAGEUP 0x4b /* Keyboard PageUp */ +#define HID_KBD_USAGE_DELFWD 0x4c /* Keyboard Delete Forward */ +#define HID_KBD_USAGE_END 0x4d /* Keyboard End */ +#define HID_KBD_USAGE_PAGEDOWN 0x4e /* Keyboard PageDown */ +#define HID_KBD_USAGE_RIGHT 0x4f /* eyboard RightArrow */ +#define HID_KBD_USAGE_LEFT 0x50 /* Keyboard LeftArrow */ +#define HID_KBD_USAGE_DOWN 0x51 /* Keyboard DownArrow */ +#define HID_KBD_USAGE_UP 0x52 /* Keyboard UpArrow */ +#define HID_KBD_USAGE_KPDNUMLOCK 0x53 /* Keypad Num Lock and Clear */ +#define HID_KBD_USAGE_KPDNUMLOCKCLEAR 0x53 /* Keypad Num Lock and Clear */ +#define HID_KBD_USAGE_KPDDIV 0x54 /* Keypad / */ +#define HID_KBD_USAGE_KPDMUL 0x55 /* Keypad * */ +#define HID_KBD_USAGE_KPDHMINUS 0x56 /* Keypad - */ +#define HID_KBD_USAGE_KPDPLUS 0x57 /* Keypad + */ +#define HID_KBD_USAGE_KPDEMTER 0x58 /* Keypad ENTER */ +#define HID_KBD_USAGE_KPD1 0x59 /* Keypad 1 (2-9 follow) */ +#define HID_KBD_USAGE_KPDEND 0x59 /* Keypad 1 and End */ +#define HID_KBD_USAGE_KPDDOWN 0x5a /* Keypad 2 and Down Arrow */ +#define HID_KBD_USAGE_KPDPAGEDN 0x5b /* Keypad 3 and PageDn */ +#define HID_KBD_USAGE_KPDLEFT 0x5c /* Keypad 4 and Left Arrow */ +#define HID_KBD_USAGE_KPDRIGHT 0x5e /* Keypad 6 and Right Arrow */ +#define HID_KBD_USAGE_KPDHOME 0x5f /* Keypad 7 and Home */ +#define HID_KBD_USAGE_KPDUP 0x60 /* Keypad 8 and Up Arrow */ +#define HID_KBD_USAGE_KPDPAGEUP 0x61 /* Keypad 9 and PageUp */ +#define HID_KBD_USAGE_KPD0 0x62 /* Keypad 0 and Insert */ +#define HID_KBD_USAGE_KPDINSERT 0x62 /* Keypad 0 and Insert */ +#define HID_KBD_USAGE_KPDDECIMALPT 0x63 /* Keypad . and Delete */ +#define HID_KBD_USAGE_KPDDELETE 0x63 /* Keypad . and Delete */ +#define HID_KBD_USAGE_NONSLASH 0x64 /* Keyboard Non-US \ and | */ +#define HID_KBD_USAGE_NONUSVERT 0x64 /* Keyboard Non-US \ and | */ +#define HID_KBD_USAGE_APPLICATION 0x65 /* Keyboard Application */ +#define HID_KBD_USAGE_POWER 0x66 /* Keyboard Power */ +#define HID_KBD_USAGE_KPDEQUAL 0x67 /* Keypad = */ +#define HID_KBD_USAGE_F13 0x68 /* Keyboard F13 */ +#define HID_KBD_USAGE_F14 0x69 /* Keyboard F14 */ +#define HID_KBD_USAGE_F15 0x6a /* Keyboard F15 */ +#define HID_KBD_USAGE_F16 0x6b /* Keyboard F16 */ +#define HID_KBD_USAGE_F17 0x6c /* Keyboard F17 */ +#define HID_KBD_USAGE_F18 0x6d /* Keyboard F18 */ +#define HID_KBD_USAGE_F19 0x6e /* Keyboard F19 */ +#define HID_KBD_USAGE_F20 0x6f /* Keyboard F20 */ +#define HID_KBD_USAGE_F21 0x70 /* Keyboard F21 */ +#define HID_KBD_USAGE_F22 0x71 /* Keyboard F22 */ +#define HID_KBD_USAGE_F23 0x72 /* Keyboard F23 */ +#define HID_KBD_USAGE_F24 0x73 /* Keyboard F24 */ +#define HID_KBD_USAGE_EXECUTE 0x74 /* Keyboard Execute */ +#define HID_KBD_USAGE_HELP 0x75 /* Keyboard Help */ +#define HID_KBD_USAGE_MENU 0x76 /* Keyboard Menu */ +#define HID_KBD_USAGE_SELECT 0x77 /* Keyboard Select */ +#define HID_KBD_USAGE_STOP 0x78 /* Keyboard Stop */ +#define HID_KBD_USAGE_AGAIN 0x79 /* Keyboard Again */ +#define HID_KBD_USAGE_UNDO 0x7a /* Keyboard Undo */ +#define HID_KBD_USAGE_CUT 0x7b /* Keyboard Cut */ +#define HID_KBD_USAGE_COPY 0x7c /* Keyboard Copy */ +#define HID_KBD_USAGE_PASTE 0x7d /* Keyboard Paste */ +#define HID_KBD_USAGE_FIND 0x7e /* Keyboard Find */ +#define HID_KBD_USAGE_MUTE 0x7f /* Keyboard Mute */ +#define HID_KBD_USAGE_VOLUP 0x80 /* Keyboard Volume Up */ +#define HID_KBD_USAGE_VOLDOWN 0x81 /* Keyboard Volume Down */ +#define HID_KBD_USAGE_LCAPSLOCK 0x82 /* Keyboard Locking Caps Lock */ +#define HID_KBD_USAGE_LNUMLOCK 0x83 /* Keyboard Locking Num Lock */ +#define HID_KBD_USAGE_LSCROLLLOCK 0x84 /* Keyboard Locking Scroll Lock */ +#define HID_KBD_USAGE_KPDCOMMA 0x85 /* Keypad Comma */ +#define HID_KBD_USAGE_KPDEQUALSIGN 0x86 /* Keypad Equal Sign */ +#define HID_KBD_USAGE_INTERNATIONAL1 0x87 /* Keyboard International 1 */ +#define HID_KBD_USAGE_INTERNATIONAL2 0x88 /* Keyboard International 2 */ +#define HID_KBD_USAGE_INTERNATIONAL3 0x89 /* Keyboard International 3 */ +#define HID_KBD_USAGE_INTERNATIONAL4 0x8a /* Keyboard International 4 */ +#define HID_KBD_USAGE_INTERNATIONAL5 0x8b /* Keyboard International 5 */ +#define HID_KBD_USAGE_INTERNATIONAL6 0x8c /* Keyboard International 6 */ +#define HID_KBD_USAGE_INTERNATIONAL7 0x8d /* Keyboard International 7 */ +#define HID_KBD_USAGE_INTERNATIONAL8 0x8e /* Keyboard International 8 */ +#define HID_KBD_USAGE_INTERNATIONAL9 0x8f /* Keyboard International 9 */ +#define HID_KBD_USAGE_LANG1 0x90 /* Keyboard LANG1 */ +#define HID_KBD_USAGE_LANG2 0x91 /* Keyboard LANG2 */ +#define HID_KBD_USAGE_LANG3 0x92 /* Keyboard LANG3 */ +#define HID_KBD_USAGE_LANG4 0x93 /* Keyboard LANG4 */ +#define HID_KBD_USAGE_LANG5 0x94 /* Keyboard LANG5 */ +#define HID_KBD_USAGE_LANG6 0x95 /* Keyboard LANG6 */ +#define HID_KBD_USAGE_LANG7 0x96 /* Keyboard LANG7 */ +#define HID_KBD_USAGE_LANG8 0x97 /* Keyboard LANG8 */ +#define HID_KBD_USAGE_LANG9 0x98 /* Keyboard LANG9 */ +#define HID_KBD_USAGE_ALTERASE 0x99 /* Keyboard Alternate Erase */ +#define HID_KBD_USAGE_SYSREQ 0x9a /* Keyboard SysReq/Attention */ +#define HID_KBD_USAGE_CANCEL 0x9b /* Keyboard Cancel */ +#define HID_KBD_USAGE_CLEAR 0x9c /* Keyboard Clear */ +#define HID_KBD_USAGE_PRIOR 0x9d /* Keyboard Prior */ +#define HID_KBD_USAGE_RETURN 0x9e /* Keyboard Return */ +#define HID_KBD_USAGE_SEPARATOR 0x9f /* Keyboard Separator */ +#define HID_KBD_USAGE_OUT 0xa0 /* Keyboard Out */ +#define HID_KBD_USAGE_OPER 0xa1 /* Keyboard Oper */ +#define HID_KBD_USAGE_CLEARAGAIN 0xa2 /* Keyboard Clear/Again */ +#define HID_KBD_USAGE_CLRSEL 0xa3 /* Keyboard CrSel/Props */ +#define HID_KBD_USAGE_EXSEL 0xa4 /* Keyboard ExSel */ +#define HID_KBD_USAGE_KPD00 0xb0 /* Keypad 00 */ +#define HID_KBD_USAGE_KPD000 0xb1 /* Keypad 000 */ +#define HID_KBD_USAGE_THOUSEPARATOR 0xb2 /* Thousands Separator */ +#define HID_KBD_USAGE_DECSEPARATOR 0xb3 /* Decimal Separator */ +#define HID_KBD_USAGE_CURRUNIT 0xb4 /* Currency Unit */ +#define HID_KBD_USAGE_CURRSUBUNIT 0xb5 /* Currency Sub-unit */ +#define HID_KBD_USAGE_KPDLPAREN 0xb6 /* Keypad ( */ +#define HID_KBD_USAGE_KPDRPAREN 0xb7 /* Keypad ) */ +#define HID_KBD_USAGE_KPDLBRACE 0xb8 /* Keypad { */ +#define HID_KBD_USAGE_KPDRBRACE 0xb9 /* Keypad } */ +#define HID_KBD_USAGE_KPDTAB 0xba /* Keypad Tab */ +#define HID_KBD_USAGE_KPDBACKSPACE 0xbb /* Keypad Backspace */ +#define HID_KBD_USAGE_KPDA 0xbc /* Keypad A (B-F follow) */ +#define HID_KBD_USAGE_KPDXOR 0xc2 /* Keypad XOR */ +#define HID_KBD_USAGE_KPDEXP 0xc3 /* Keypad ^ */ +#define HID_KBD_USAGE_KPDPERCENT 0xc4 /* Keypad % */ +#define HID_KBD_USAGE_KPDLT 0xc5 /* Keypad < */ +#define HID_KBD_USAGE_KPDGT 0xc6 /* Keypad > */ +#define HID_KBD_USAGE_KPDAMPERSAND 0xc7 /* Keypad & */ +#define HID_KBD_USAGE_KPDAND 0xc8 /* Keypad && */ +#define HID_KBD_USAGE_KPDVERT 0xc9 /* Keypad | */ +#define HID_KBD_USAGE_KPDOR 0xca /* Keypad || */ +#define HID_KBD_USAGE_KPDCOLON 0xcb /* Keypad : */ +#define HID_KBD_USAGE_KPDPOUND 0xcc /* Keypad # */ +#define HID_KBD_USAGE_KPDSPACE 0xcd /* Keypad Space */ +#define HID_KBD_USAGE_KPDAT 0xce /* Keypad @ */ +#define HID_KBD_USAGE_KPDEXCLAM 0xcf /* Keypad ! */ +#define HID_KBD_USAGE_KPDMEMSTORE 0xd0 /* Keypad Memory Store */ +#define HID_KBD_USAGE_KPDMEMRECALL 0xd1 /* Keypad Memory Recall */ +#define HID_KBD_USAGE_KPDMEMCLEAR 0xd2 /* Keypad Memory Clear */ +#define HID_KBD_USAGE_KPDMEMADD 0xd3 /* Keypad Memory Add */ +#define HID_KBD_USAGE_KPDMEMSUB 0xd4 /* Keypad Memory Subtract */ +#define HID_KBD_USAGE_KPDMEMMULT 0xd5 /* Keypad Memory Multiply */ +#define HID_KBD_USAGE_KPDMEMDIV 0xd6 /* Keypad Memory Divide */ +#define HID_KBD_USAGE_KPDPLUSMINUS 0xd7 /* Keypad +/- */ +#define HID_KBD_USAGE_KPDCLEAR 0xd8 /* Keypad Clear */ +#define HID_KBD_USAGE_KPDCLEARENTRY 0xd9 /* Keypad Clear Entry */ +#define HID_KBD_USAGE_KPDBINARY 0xda /* Keypad Binary */ +#define HID_KBD_USAGE_KPDOCTAL 0xdb /* Keypad Octal */ +#define HID_KBD_USAGE_KPDDECIMAL 0xdc /* Keypad Decimal */ +#define HID_KBD_USAGE_KPDHEXADECIMAL 0xdd /* Keypad Hexadecimal */ +#define HID_KBD_USAGE_LCTRL 0xe0 /* Keyboard LeftControl */ +#define HID_KBD_USAGE_LSHIFT 0xe1 /* Keyboard LeftShift */ +#define HID_KBD_USAGE_LALT 0xe2 /* Keyboard LeftAlt */ +#define HID_KBD_USAGE_LGUI 0xe3 /* Keyboard Left GUI */ +#define HID_KBD_USAGE_RCTRL 0xe4 /* Keyboard RightControl */ +#define HID_KBD_USAGE_RSHIFT 0xe5 /* Keyboard RightShift */ +#define HID_KBD_USAGE_RALT 0xe6 /* Keyboard RightAlt */ +#define HID_KBD_USAGE_RGUI 0xe7 /* Keyboard Right GUI */ + +#define HID_KBD_USAGE_MAX 0xe7 + +/* HID Report Definitions */ +struct usb_hid_class_subdescriptor { + uint8_t bDescriptorType;/* Class descriptor type (See 7.1) */ + uint16_t wDescriptorLength;/* Size of the report descriptor */ +} __PACKED; + +struct usb_hid_descriptor { + uint8_t bLength; /* Size of the HID descriptor */ + uint8_t bDescriptorType;/* HID descriptor type */ + uint16_t bcdHID;/* HID class specification release */ + uint8_t bCountryCode;/* Country code */ + uint8_t bNumDescriptors;/* Number of descriptors (>=1) */ + + /* + * Specification says at least one Class Descriptor needs to + * be present (Report Descriptor). + */ + struct usb_hid_class_subdescriptor subdesc[1]; +} __PACKED; + +/* Standard Reports *********************************************************/ + +/* Keyboard input report (8 bytes) (HID B.1) */ +struct usb_hid_kbd_report +{ + uint8_t modifier; /* Modifier keys. See HID_MODIFER_* definitions */ + uint8_t reserved; + uint8_t key[6]; /* Keycode 1-6 */ +}; + +/* Keyboard output report (1 byte) (HID B.1), + * see USBHID_KBDOUT_* definitions + */ + +/* Mouse input report (HID B.2) */ +struct usb_hid_mouse_report +{ + uint8_t buttons; /* See HID_MOUSE_INPUT_BUTTON_* definitions */ + uint8_t xdisp; /* X displacement */ + uint8_t ydisp; /* y displacement */ + /* Device specific additional bytes may follow */ +#ifdef CONFIG_INPUT_MOUSE_WHEEL + uint8_t wdisp; /* Wheel displacement */ +#endif +}; + +/* Joystick input report (1 bytes) (HID D.1) */ +struct usb_hid_js_report +{ + uint8_t xpos; /* X position */ + uint8_t ypos; /* X position */ + uint8_t buttons; /* See USBHID_JSIN_* definitions */ + uint8_t throttle; /* Throttle */ +}; + +#endif /* USB_HID_H */ diff --git a/components/drivers/usb/cherryusb/class/hid/usbd_hid.c b/components/drivers/usb/cherryusb/class/hid/usbd_hid.c new file mode 100644 index 00000000000..d98b82eb841 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/hid/usbd_hid.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" + +static int hid_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("HID Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + uint8_t intf_num = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case HID_REQUEST_GET_REPORT: + /* report id ,report type */ + usbd_hid_get_report(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue), data, len); + break; + case HID_REQUEST_GET_IDLE: + (*data)[0] = usbd_hid_get_idle(busid, intf_num, LO_BYTE(setup->wValue)); + *len = 1; + break; + case HID_REQUEST_GET_PROTOCOL: + (*data)[0] = usbd_hid_get_protocol(busid, intf_num); + *len = 1; + break; + case HID_REQUEST_SET_REPORT: + /* report id ,report type, report, report len */ + usbd_hid_set_report(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue), *data, *len); + break; + case HID_REQUEST_SET_IDLE: + /* report id, duration */ + usbd_hid_set_idle(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue)); + break; + case HID_REQUEST_SET_PROTOCOL: + /* protocol */ + usbd_hid_set_protocol(busid, intf_num, LO_BYTE(setup->wValue)); + break; + + default: + USB_LOG_WRN("Unhandled HID Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t *desc, uint32_t desc_len) +{ + intf->class_interface_handler = hid_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = NULL; + + intf->hid_report_descriptor = desc; + intf->hid_report_descriptor_len = desc_len; + return intf; +} + +__WEAK void usbd_hid_get_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len) +{ + (*data[0]) = 0; + *len = 1; +} + +__WEAK uint8_t usbd_hid_get_idle(uint8_t busid, uint8_t intf, uint8_t report_id) +{ + return 0; +} + +__WEAK uint8_t usbd_hid_get_protocol(uint8_t busid, uint8_t intf) +{ + return 0; +} + +__WEAK void usbd_hid_set_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len) +{ +} + +__WEAK void usbd_hid_set_idle(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t duration) +{ +} + +__WEAK void usbd_hid_set_protocol(uint8_t busid, uint8_t intf, uint8_t protocol) +{ +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/hid/usbd_hid.h b/components/drivers/usb/cherryusb/class/hid/usbd_hid.h new file mode 100644 index 00000000000..d5c3484f2fd --- /dev/null +++ b/components/drivers/usb/cherryusb/class/hid/usbd_hid.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_HID_H +#define USBD_HID_H + +#include "usb_hid.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init hid interface driver */ +struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t *desc, uint32_t desc_len); + +/* Register desc api */ +void usbd_hid_descriptor_register(uint8_t busid, uint8_t intf_num, const uint8_t *desc); +void usbd_hid_report_descriptor_register(uint8_t busid, uint8_t intf_num, const uint8_t *desc, uint32_t desc_len); + +/* Setup request command callback api */ +void usbd_hid_get_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len); +uint8_t usbd_hid_get_idle(uint8_t busid, uint8_t intf, uint8_t report_id); +uint8_t usbd_hid_get_protocol(uint8_t busid, uint8_t intf); +void usbd_hid_set_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len); +void usbd_hid_set_idle(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t duration); +void usbd_hid_set_protocol(uint8_t busid, uint8_t intf, uint8_t protocol); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_HID_H */ diff --git a/components/drivers/usb/cherryusb/class/hid/usbh_hid.c b/components/drivers/usb/cherryusb/class/hid/usbh_hid.c new file mode 100644 index 00000000000..f3b2546f22f --- /dev/null +++ b/components/drivers/usb/cherryusb/class/hid/usbh_hid.c @@ -0,0 +1,231 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_hid.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_hid" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/input%d" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hid_buf[128]; + +static struct usbh_hid g_hid_class[CONFIG_USBHOST_MAX_HID_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_hid *usbh_hid_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_HID_CLASS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_hid_class[devno], 0, sizeof(struct usbh_hid)); + g_hid_class[devno].minor = devno; + return &g_hid_class[devno]; + } + } + return NULL; +} + +static void usbh_hid_class_free(struct usbh_hid *hid_class) +{ + int devno = hid_class->minor; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(hid_class, 0, sizeof(struct usbh_hid)); +} + +static int usbh_hid_get_report_descriptor(struct usbh_hid *hid_class, uint8_t *buffer) +{ + struct usb_setup_packet *setup = hid_class->hport->setup; + int ret; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = HID_DESCRIPTOR_TYPE_HID_REPORT << 8; + setup->wIndex = hid_class->intf; + setup->wLength = 128; + + ret = usbh_control_transfer(hid_class->hport, setup, g_hid_buf); + if (ret < 0) { + return ret; + } + memcpy(buffer, g_hid_buf, ret - 8); + return ret; +} + +int usbh_hid_set_idle(struct usbh_hid *hid_class, uint8_t report_id, uint8_t duration) +{ + struct usb_setup_packet *setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_SET_IDLE; + setup->wValue = (duration << 8) | report_id; + setup->wIndex = hid_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(hid_class->hport, setup, NULL); +} + +int usbh_hid_get_idle(struct usbh_hid *hid_class, uint8_t *buffer) +{ + struct usb_setup_packet *setup = hid_class->hport->setup; + int ret; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_GET_IDLE; + setup->wValue = 0; + setup->wIndex = hid_class->intf; + setup->wLength = 1; + + ret = usbh_control_transfer(hid_class->hport, setup, g_hid_buf); + if (ret < 0) { + return ret; + } + memcpy(buffer, g_hid_buf, 1); + return ret; +} + +int usbh_hid_set_protocol(struct usbh_hid *hid_class, uint8_t protocol) +{ + struct usb_setup_packet *setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_SET_PROTOCOL; + setup->wValue = protocol; + setup->wIndex = 0; + setup->wLength = 0; + + return usbh_control_transfer(hid_class->hport, setup, NULL); +} + +int usbh_hid_set_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen) +{ + struct usb_setup_packet *setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_SET_REPORT; + setup->wValue = (uint16_t)(((uint32_t)report_type << 8U) | (uint32_t)report_id); + setup->wIndex = 0; + setup->wLength = buflen; + + return usbh_control_transfer(hid_class->hport, setup, buffer); +} + +int usbh_hid_get_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen) +{ + struct usb_setup_packet *setup = hid_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = HID_REQUEST_GET_REPORT; + setup->wValue = (uint16_t)(((uint32_t)report_type << 8U) | (uint32_t)report_id); + setup->wIndex = 0; + setup->wLength = buflen; + + return usbh_control_transfer(hid_class->hport, setup, buffer); +} + +int usbh_hid_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + + struct usbh_hid *hid_class = usbh_hid_class_alloc(); + if (hid_class == NULL) { + USB_LOG_ERR("Fail to alloc hid_class\r\n"); + return -USB_ERR_NOMEM; + } + + hid_class->hport = hport; + hid_class->intf = intf; + + hport->config.intf[intf].priv = hid_class; + + // /* 0x0 = boot protocol, 0x1 = report protocol */ + // ret = usbh_hid_set_protocol(hid_class, 0x1); + // if (ret < 0) { + // return ret; + // } + + ret = usbh_hid_set_idle(hid_class, 0, 0); + if (ret < 0) { + USB_LOG_WRN("Do not support set idle\r\n"); + } + + ret = usbh_hid_get_report_descriptor(hid_class, hid_class->report_desc); + if (ret < 0) { + return ret; + } + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(hid_class->intin, ep_desc); + } else { + USBH_EP_INIT(hid_class->intout, ep_desc); + } + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, hid_class->minor); + + USB_LOG_INFO("Register HID Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_hid_run(hid_class); + return ret; +} + +int usbh_hid_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_hid *hid_class = (struct usbh_hid *)hport->config.intf[intf].priv; + + if (hid_class) { + if (hid_class->intin) { + usbh_kill_urb(&hid_class->intin_urb); + } + + if (hid_class->intout) { + usbh_kill_urb(&hid_class->intout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister HID Class:%s\r\n", hport->config.intf[intf].devname); + usbh_hid_stop(hid_class); + } + + usbh_hid_class_free(hid_class); + } + + return ret; +} + +__WEAK void usbh_hid_run(struct usbh_hid *hid_class) +{ +} + +__WEAK void usbh_hid_stop(struct usbh_hid *hid_class) +{ +} + +const struct usbh_class_driver hid_class_driver = { + .driver_name = "hid", + .connect = usbh_hid_connect, + .disconnect = usbh_hid_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info hid_custom_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS, + .class = USB_DEVICE_CLASS_HID, + .subclass = 0x00, + .protocol = 0x00, + .id_table = NULL, + .class_driver = &hid_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/hid/usbh_hid.h b/components/drivers/usb/cherryusb/class/hid/usbh_hid.h new file mode 100644 index 00000000000..17caaba277b --- /dev/null +++ b/components/drivers/usb/cherryusb/class/hid/usbh_hid.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_HID_H +#define USBH_HID_H + +#include "usb_hid.h" + +struct usbh_hid { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *intin; /* INTR IN endpoint */ + struct usb_endpoint_descriptor *intout; /* INTR OUT endpoint */ + struct usbh_urb intin_urb; /* INTR IN urb */ + struct usbh_urb intout_urb; /* INTR OUT urb */ + + uint8_t report_desc[256]; + uint8_t intf; /* interface number */ + uint8_t minor; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_hid_set_idle(struct usbh_hid *hid_class, uint8_t report_id, uint8_t duration); +int usbh_hid_get_idle(struct usbh_hid *hid_class, uint8_t *buffer); +int usbh_hid_set_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen); +int usbh_hid_get_report(struct usbh_hid *hid_class, uint8_t report_type, uint8_t report_id, uint8_t *buffer, uint32_t buflen); + +void usbh_hid_run(struct usbh_hid *hid_class); +void usbh_hid_stop(struct usbh_hid *hid_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_HID_H */ diff --git a/components/drivers/usb/cherryusb/class/hub/usb_hub.h b/components/drivers/usb/cherryusb/class/hub/usb_hub.h new file mode 100644 index 00000000000..7956b163e72 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/hub/usb_hub.h @@ -0,0 +1,121 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HUB_H +#define USB_HUB_H + +/* HUB Class Descriptor Types */ +#define HUB_DESCRIPTOR_TYPE_HUB 0x29 +#define HUB_DESCRIPTOR_TYPE_HUB3 0x2A + +/* Hub class requests */ +#define HUB_REQUEST_GET_STATUS USB_REQUEST_GET_STATUS +#define HUB_REQUEST_CLEAR_FEATURE USB_REQUEST_CLEAR_FEATURE +#define HUB_REQUEST_SET_FEATURE USB_REQUEST_SET_FEATURE +#define HUB_REQUEST_GET_DESCRIPTOR USB_REQUEST_GET_DESCRIPTOR +#define HUB_REQUEST_SET_DESCRIPTOR USB_REQUEST_SET_DESCRIPTOR +#define HUB_REQUEST_CLEAR_TT_BUFFER (0x08) +#define HUB_REQUEST_RESET_TT (0x09) +#define HUB_REQUEST_GET_TT_STATE (0x0a) +#define HUB_REQUEST_STOP_TT (0x0b) +#define HUB_REQUEST_SET_HUB_DEPTH (0x0C) + +/* Hub class features */ +#define HUB_FEATURE_HUB_C_LOCALPOWER (0x0) +#define HUB_FEATURE_HUB_C_OVERCURRENT (0x1) + +/* Port features */ +#define HUB_PORT_FEATURE_CONNECTION (0x00) +#define HUB_PORT_FEATURE_ENABLE (0x01) +#define HUB_PORT_FEATURE_SUSPEND (0x02) +#define HUB_PORT_FEATURE_OVERCURRENT (0x03) +#define HUB_PORT_FEATURE_RESET (0x04) +#define HUB_PORT_FEATURE_L1 (0x05) +#define HUB_PORT_FEATURE_POWER (0x08) +#define HUB_PORT_FEATURE_LOWSPEED (0x09) +#define HUB_PORT_FEATURE_HIGHSPEED (0x0a) +#define HUB_PORT_FEATURE_C_CONNECTION (0x10) +#define HUB_PORT_FEATURE_C_ENABLE (0x11) +#define HUB_PORT_FEATURE_C_SUSPEND (0x12) +#define HUB_PORT_FEATURE_C_OVER_CURREN (0x13) +#define HUB_PORT_FEATURE_C_RESET (0x14) +#define HUB_PORT_FEATURE_TEST (0x15) +#define HUB_PORT_FEATURE_INDICATOR (0x16) +#define HUB_PORT_FEATURE_C_PORTL1 (0x17) + +/* Hub status */ +#define HUB_STATUS_LOCALPOWER (1 << 0) +#define HUB_STATUS_OVERCURRENT (1 << 1) + +/* Hub status change */ +#define HUB_STATUS_C_LOCALPOWER (1 << 0) +#define HUB_STATUS_C_OVERCURRENT (1 << 1) + +/* Hub port status */ +#define HUB_PORT_STATUS_CONNECTION (1 << 0) +#define HUB_PORT_STATUS_ENABLE (1 << 1) +#define HUB_PORT_STATUS_SUSPEND (1 << 2) +#define HUB_PORT_STATUS_OVERCURRENT (1 << 3) +#define HUB_PORT_STATUS_RESET (1 << 4) +#define HUB_PORT_STATUS_L1 (1 << 5) +#define HUB_PORT_STATUS_POWER (1 << 8) +#define HUB_PORT_STATUS_LOW_SPEED (1 << 9) +#define HUB_PORT_STATUS_HIGH_SPEED (1 << 10) +#define HUB_PORT_STATUS_TEST (1 << 11) +#define HUB_PORT_STATUS_INDICATOR (1 << 12) + +/* Hub port status change */ +#define HUB_PORT_STATUS_C_CONNECTION (1 << 0) +#define HUB_PORT_STATUS_C_ENABLE (1 << 1) +#define HUB_PORT_STATUS_C_SUSPEND (1 << 2) +#define HUB_PORT_STATUS_C_OVERCURRENT (1 << 3) +#define HUB_PORT_STATUS_C_RESET (1 << 4) +#define HUB_PORT_STATUS_C_L1 (1 << 5) + +/* Hub characteristics */ +#define HUB_CHAR_LPSM_SHIFT (0) /* Bits 0-1: Logical Power Switching Mode */ +#define HUB_CHAR_LPSM_MASK (3 << HUB_CHAR_LPSM_SHIFT) +#define HUB_CHAR_LPSM_GANGED (0 << HUB_CHAR_LPSM_SHIFT) +#define HUB_CHAR_LPSM_INDIVIDUAL (1 << HUB_CHAR_LPSM_SHIFT) +#define HUB_CHAR_COMPOUND (1 << 2) /* Bit 2: Compound device */ +#define HUB_CHAR_OCPM_SHIFT (3) /* Bits 3-4: Over-current Protection Mode */ +#define HUB_CHAR_OCPM_MASK (3 << HUB_CHAR_OCPM_SHIFT) +#define HUB_CHAR_OCPM_GLOBAL (0 << HUB_CHAR_OCPM_SHIFT) +#define HUB_CHAR_OCPM_INDIVIDUAL (1 << HUB_CHAR_OCPM_SHIFT) +#define HUB_CHAR_TTTT_SHIFT (5) /* Bits 5-6: TT Think Time */ +#define HUB_CHAR_TTTT_MASK (3 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_8_BITS (0 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_16_BITS (1 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_24_BITS (2 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_TTTT_32_BITS (3 << HUB_CHAR_TTTT_SHIFT) +#define HUB_CHAR_PORTIND (1 << 7) /* Bit 7: Port Indicators Supported */ + +/* Hub descriptor */ +struct usb_hub_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bNbrPorts; + uint16_t wHubCharacteristics; + uint8_t bPwrOn2PwrGood; + uint8_t bHubContrCurrent; + uint8_t DeviceRemovable; + uint8_t PortPwrCtrlMask; +} __PACKED; + +#define USB_SIZEOF_HUB_DESC 9 + +/* Hub status */ +struct hub_status { + uint16_t wPortStatus; + uint16_t wPortChange; +}; + +/* Hub port status */ +struct hub_port_status { + uint16_t wPortStatus; + uint16_t wPortChange; +}; + +#endif /* USB_HUB_H */ diff --git a/components/drivers/usb/cherryusb/class/hub/usbh_hub.c b/components/drivers/usb/cherryusb/class/hub/usbh_hub.c new file mode 100644 index 00000000000..6755b8594c0 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/hub/usbh_hub.c @@ -0,0 +1,711 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_hub.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_hub" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/hub%d" + +#define HUB_DEBOUNCE_TIMEOUT 1500 +#define HUB_DEBOUNCE_STEP 25 +#define HUB_DEBOUNCE_STABLE 100 +#define DELAY_TIME_AFTER_RESET 200 + +#define EXTHUB_FIRST_INDEX 2 + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hub_buf[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(32, CONFIG_USB_ALIGN_SIZE)]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_hub_intbuf[CONFIG_USBHOST_MAX_BUS][CONFIG_USBHOST_MAX_EXTHUBS + 1][USB_ALIGN_UP(1, CONFIG_USB_ALIGN_SIZE)]; + +extern int usbh_enumerate(struct usbh_hubport *hport); +extern void usbh_hubport_release(struct usbh_hubport *hport); + +static const char *speed_table[] = { "error-speed", "low-speed", "full-speed", "high-speed", "wireless-speed", "super-speed", "superplus-speed" }; + +#ifdef CONFIG_USBHOST_XHCI +struct usbh_hubport *usbh_get_roothub_port(unsigned int port) +{ + return &roothub.child[port - 1]; +} +#endif + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static struct usbh_hub g_hub_class[CONFIG_USBHOST_MAX_EXTHUBS]; +static uint32_t g_devinuse = 0; + +static struct usbh_hub *usbh_hub_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_EXTHUBS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_hub_class[devno], 0, sizeof(struct usbh_hub)); + g_hub_class[devno].index = EXTHUB_FIRST_INDEX + devno; + return &g_hub_class[devno]; + } + } + return NULL; +} + +static void usbh_hub_class_free(struct usbh_hub *hub_class) +{ + int devno = hub_class->index - EXTHUB_FIRST_INDEX; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(hub_class, 0, sizeof(struct usbh_hub)); +} +#endif + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static int _usbh_hub_get_hub_descriptor(struct usbh_hub *hub, uint8_t *buffer) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + + /* TODO: hub descriptor has some difference between USB 2.0 and USB 3.x, + and we havn't handle the difference here */ + if ((hub->parent->speed == USB_SPEED_SUPER) || + (hub->parent->speed == USB_SPEED_SUPER_PLUS)) { + setup->wValue = HUB_DESCRIPTOR_TYPE_HUB3 << 8; + } else { + setup->wValue = HUB_DESCRIPTOR_TYPE_HUB << 8; + } + + setup->wIndex = 0; + setup->wLength = USB_SIZEOF_HUB_DESC; + + ret = usbh_control_transfer(hub->parent, setup, g_hub_buf[hub->bus->busid]); + if (ret < 0) { + return ret; + } + memcpy(buffer, g_hub_buf[hub->bus->busid], USB_SIZEOF_HUB_DESC); + return ret; +} +#if 0 +static int _usbh_hub_get_status(struct usbh_hub *hub, uint8_t *buffer) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = HUB_REQUEST_GET_STATUS; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 2; + + ret = usbh_control_transfer(hub->parent, setup, g_hub_buf[hub->bus->busid]); + if (ret < 0) { + return ret; + } + memcpy(buffer, g_hub_buf[hub->bus->busid], 2); + return ret; +} +#endif +#endif + +static int _usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct hub_port_status *port_status) +{ + struct usb_setup_packet *setup; + int ret; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_GET_STATUS; + setup->wValue = 0; + setup->wIndex = port; + setup->wLength = 4; + + ret = usbh_control_transfer(hub->parent, setup, g_hub_buf[hub->bus->busid]); + if (ret < 0) { + return ret; + } + memcpy(port_status, g_hub_buf[hub->bus->busid], 4); + return ret; +} + +static int _usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet *setup; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_SET_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + + return usbh_control_transfer(hub->parent, setup, NULL); +} + +static int _usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet *setup; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_CLEAR_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + + return usbh_control_transfer(hub->parent, setup, NULL); +} + +static int _usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth) +{ + struct usb_setup_packet *setup; + + setup = hub->parent->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = HUB_REQUEST_SET_HUB_DEPTH; + setup->wValue = depth; + setup->wIndex = 0; + setup->wLength = 0; + + return usbh_control_transfer(hub->parent, setup, NULL); +} + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static int parse_hub_descriptor(struct usb_hub_descriptor *desc, uint16_t length) +{ + if (desc->bLength != USB_SIZEOF_HUB_DESC) { + USB_LOG_ERR("invalid device bLength 0x%02x\r\n", desc->bLength); + return -1; + } else if (desc->bDescriptorType != HUB_DESCRIPTOR_TYPE_HUB) { + USB_LOG_ERR("unexpected descriptor 0x%02x\r\n", desc->bDescriptorType); + return -2; + } else { + USB_LOG_RAW("Hub Descriptor:\r\n"); + USB_LOG_RAW("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_RAW("bNbrPorts: 0x%02x \r\n", desc->bNbrPorts); + USB_LOG_RAW("wHubCharacteristics: 0x%04x \r\n", desc->wHubCharacteristics); + USB_LOG_RAW("bPwrOn2PwrGood: 0x%02x \r\n", desc->bPwrOn2PwrGood); + USB_LOG_RAW("bHubContrCurrent: 0x%02x \r\n", desc->bHubContrCurrent); + USB_LOG_RAW("DeviceRemovable: 0x%02x \r\n", desc->DeviceRemovable); + USB_LOG_RAW("PortPwrCtrlMask: 0x%02x \r\n", desc->PortPwrCtrlMask); + } + return 0; +} +#endif + +static int usbh_hub_get_portstatus(struct usbh_hub *hub, uint8_t port, struct hub_port_status *port_status) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_GET_STATUS; + setup->wValue = 0; + setup->wIndex = port; + setup->wLength = 4; + return usbh_roothub_control(hub->bus, &roothub_setup, (uint8_t *)port_status); + } else { + return _usbh_hub_get_portstatus(hub, port, port_status); + } +} + +int usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_SET_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + return usbh_roothub_control(hub->bus, setup, NULL); + } else { + return _usbh_hub_set_feature(hub, port, feature); + } +} + +int usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_OTHER; + setup->bRequest = HUB_REQUEST_CLEAR_FEATURE; + setup->wValue = feature; + setup->wIndex = port; + setup->wLength = 0; + return usbh_roothub_control(hub->bus, setup, NULL); + } else { + return _usbh_hub_clear_feature(hub, port, feature); + } +} + +static int usbh_hub_set_depth(struct usbh_hub *hub, uint16_t depth) +{ + struct usb_setup_packet roothub_setup; + struct usb_setup_packet *setup; + + if (hub->is_roothub) { + setup = &roothub_setup; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = HUB_REQUEST_SET_HUB_DEPTH; + setup->wValue = depth; + setup->wIndex = 0; + setup->wLength = 0; + return usbh_roothub_control(hub->bus, setup, NULL); + } else { + return _usbh_hub_set_depth(hub, depth); + } +} + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +static void hub_int_complete_callback(void *arg, int nbytes) +{ + struct usbh_hub *hub = (struct usbh_hub *)arg; + + if (nbytes > 0) { + usbh_hub_thread_wakeup(hub); + } else if (nbytes == -USB_ERR_NAK) { + /* Restart timer to submit urb again */ + USB_LOG_DBG("Restart timer\r\n"); + usb_osal_timer_start(hub->int_timer); + } else { + } +} + +static void hub_int_timeout(void *arg) +{ + struct usbh_hub *hub = (struct usbh_hub *)arg; + + usbh_int_urb_fill(&hub->intin_urb, hub->parent, hub->intin, hub->int_buffer, 1, 0, hub_int_complete_callback, hub); + usbh_submit_urb(&hub->intin_urb); +} + +static int usbh_hub_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + struct hub_port_status port_status; + int ret; + + struct usbh_hub *hub = usbh_hub_class_alloc(); + if (hub == NULL) { + USB_LOG_ERR("Fail to alloc hub_class\r\n"); + return -USB_ERR_NOMEM; + } + + hub->hub_addr = hport->dev_addr; + hub->parent = hport; + hub->bus = hport->bus; + + hport->config.intf[intf].priv = hub; + + ret = _usbh_hub_get_hub_descriptor(hub, (uint8_t *)&hub->hub_desc); + if (ret < 0) { + return ret; + } + + parse_hub_descriptor(&hub->hub_desc, USB_SIZEOF_HUB_DESC); + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + hub->child[port].port = port + 1; + hub->child[port].parent = hub; + hub->child[port].bus = hport->bus; + } + + ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(hub->intin, ep_desc); + } else { + return -1; + } + + if (hport->speed == USB_SPEED_SUPER) { + uint16_t depth = 0; + struct usbh_hubport *parent = hport->parent->parent; + while (parent) { + depth++; + parent = parent->parent->parent; + } + + ret = usbh_hub_set_depth(hub, depth); + if (ret < 0) { + return ret; + } + } + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + ret = usbh_hub_set_feature(hub, port + 1, HUB_PORT_FEATURE_POWER); + if (ret < 0) { + return ret; + } + } + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + USB_LOG_INFO("port %u, status:0x%02x, change:0x%02x\r\n", port + 1, port_status.wPortStatus, port_status.wPortChange); + if (ret < 0) { + return ret; + } + } + + hub->connected = true; + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, hub->index); + + usb_slist_add_tail(&hub->bus->hub_list, &hub->list); + + USB_LOG_INFO("Register HUB Class:%s\r\n", hport->config.intf[intf].devname); + + hub->int_buffer = g_hub_intbuf[hub->bus->busid][hub->index - 1]; + + hub->int_timer = usb_osal_timer_create("hubint_tim", USBH_GET_URB_INTERVAL(hub->intin->bInterval, hport->speed), hub_int_timeout, hub, 0); + if (hub->int_timer == NULL) { + USB_LOG_ERR("No memory to alloc int_timer\r\n"); + return -USB_ERR_NOMEM; + } + usb_osal_timer_start(hub->int_timer); + return 0; +} + +static int usbh_hub_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usbh_hubport *child; + int ret = 0; + + struct usbh_hub *hub = (struct usbh_hub *)hport->config.intf[intf].priv; + + if (hub) { + if (hub->intin) { + usbh_kill_urb(&hub->intin_urb); + } + + if (hub->int_timer) { + usb_osal_timer_delete(hub->int_timer); + } + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + child = &hub->child[port]; + usbh_hubport_release(child); + child->parent = NULL; + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister HUB Class:%s\r\n", hport->config.intf[intf].devname); + usb_slist_remove(&hub->bus->hub_list, &hub->list); + } + + usbh_hub_class_free(hub); + } + return ret; +} +#endif + +static void usbh_hubport_enumerate_thread(void *argument) +{ + struct usbh_hubport *child = (struct usbh_hubport *)argument; + + if (usbh_enumerate(child) < 0) { + /** release child sources */ + usbh_hubport_release(child); + USB_LOG_ERR("Port %u enumerate fail\r\n", child->port); + } + usb_osal_thread_delete(NULL); +} + +static void usbh_hub_events(struct usbh_hub *hub) +{ + struct usbh_hubport *child; + struct hub_port_status port_status; + uint8_t portchange_index; + uint16_t portstatus; + uint16_t portchange; + uint16_t mask; + uint16_t feat; + uint8_t speed; + int ret; + + if (!hub->connected) { + return; + } + + portchange_index = hub->int_buffer[0]; + hub->int_buffer[0] &= ~portchange_index; + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + USB_LOG_DBG("Port change:0x%02x\r\n", portchange_index); + + if (!(portchange_index & (1 << (port + 1)))) { + continue; + } + portchange_index &= ~(1 << (port + 1)); + USB_LOG_DBG("Port %d change\r\n", port + 1); + + /* Read hub port status */ + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + if (ret < 0) { + USB_LOG_ERR("Failed to read port %u status, errorcode: %d\r\n", port + 1, ret); + continue; + } + + portstatus = port_status.wPortStatus; + portchange = port_status.wPortChange; + + USB_LOG_DBG("port %u, status:0x%02x, change:0x%02x\r\n", port + 1, portstatus, portchange); + + /* First, clear all change bits */ + mask = 1; + feat = HUB_PORT_FEATURE_C_CONNECTION; + while (portchange) { + if (portchange & mask) { + ret = usbh_hub_clear_feature(hub, port + 1, feat); + if (ret < 0) { + USB_LOG_ERR("Failed to clear port %u, change mask:%04x, errorcode:%d\r\n", port + 1, mask, ret); + continue; + } + portchange &= (~mask); + } + mask <<= 1; + feat++; + } + + portchange = port_status.wPortChange; + + /* Second, if port changes, debounces first */ + if (portchange & HUB_PORT_STATUS_C_CONNECTION) { + uint16_t connection = 0; + uint16_t debouncestable = 0; + for (uint32_t debouncetime = 0; debouncetime < HUB_DEBOUNCE_TIMEOUT; debouncetime += HUB_DEBOUNCE_STEP) { + /* Read hub port status */ + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + if (ret < 0) { + USB_LOG_ERR("Failed to read port %u status, errorcode: %d\r\n", port + 1, ret); + continue; + } + + portstatus = port_status.wPortStatus; + portchange = port_status.wPortChange; + + USB_LOG_DBG("Port %u, status:0x%02x, change:0x%02x\r\n", port + 1, portstatus, portchange); + + if (!(portchange & HUB_PORT_STATUS_C_CONNECTION) && + ((portstatus & HUB_PORT_STATUS_CONNECTION) == connection)) { + debouncestable += HUB_DEBOUNCE_STEP; + if (debouncestable >= HUB_DEBOUNCE_STABLE) { + break; + } + } else { + debouncestable = 0; + connection = portstatus & HUB_PORT_STATUS_CONNECTION; + } + + if (portchange & HUB_PORT_STATUS_C_CONNECTION) { + usbh_hub_clear_feature(hub, port + 1, HUB_PORT_FEATURE_C_CONNECTION); + } + + usb_osal_msleep(HUB_DEBOUNCE_STEP); + } + + /** check if debounce ok */ + if (debouncestable < HUB_DEBOUNCE_STABLE) { + USB_LOG_ERR("Failed to debounce port %u\r\n", port + 1); + break; + } + + /* Last, check connect status */ + if (portstatus & HUB_PORT_STATUS_CONNECTION) { + ret = usbh_hub_set_feature(hub, port + 1, HUB_PORT_FEATURE_RESET); + if (ret < 0) { + USB_LOG_ERR("Failed to reset port %u,errorcode:%d\r\n", port, ret); + continue; + } + + usb_osal_msleep(DELAY_TIME_AFTER_RESET); + /* Read hub port status */ + ret = usbh_hub_get_portstatus(hub, port + 1, &port_status); + if (ret < 0) { + USB_LOG_ERR("Failed to read port %u status, errorcode: %d\r\n", port + 1, ret); + continue; + } + + portstatus = port_status.wPortStatus; + portchange = port_status.wPortChange; + if (!(portstatus & HUB_PORT_STATUS_RESET) && (portstatus & HUB_PORT_STATUS_ENABLE)) { + if (portchange & HUB_PORT_STATUS_C_RESET) { + ret = usbh_hub_clear_feature(hub, port + 1, HUB_PORT_FEATURE_C_RESET); + if (ret < 0) { + USB_LOG_ERR("Failed to clear port %u reset change, errorcode: %d\r\n", port, ret); + } + } + + if (portstatus & HUB_PORT_STATUS_HIGH_SPEED) { + speed = USB_SPEED_HIGH; + } else if (portstatus & HUB_PORT_STATUS_LOW_SPEED) { + speed = USB_SPEED_LOW; + } +#ifdef CONFIG_USBHOST_XHCI + else { + extern uint8_t usbh_get_port_speed(struct usbh_hub * hub, const uint8_t port); + + /* USB3.0 speed cannot get from portstatus, checkout port speed instead */ + uint8_t super_speed = usbh_get_port_speed(hub, port + 1); + if (super_speed > USB_SPEED_HIGH) { + /* assert that when using USB 3.0 ports, attached device must also be USB 3.0 speed */ + speed = super_speed; + } else { + speed = USB_SPEED_FULL; + } + } +#else + else { + speed = USB_SPEED_FULL; + } +#endif + + child = &hub->child[port]; + /** release child sources first */ + usbh_hubport_release(child); + + memset(child, 0, sizeof(struct usbh_hubport)); + child->parent = hub; + child->connected = true; + child->port = port + 1; + child->speed = speed; + child->bus = hub->bus; + child->mutex = usb_osal_mutex_create(); + + USB_LOG_INFO("New %s device on Bus %u, Hub %u, Port %u connected\r\n", speed_table[speed], hub->bus->busid, hub->index, port + 1); + + /* create disposable thread to enumerate device on current hport, do not block hub thread */ + usb_osal_thread_create("usbh_enum", CONFIG_USBHOST_PSC_STACKSIZE, CONFIG_USBHOST_PSC_PRIO + 1, usbh_hubport_enumerate_thread, (void *)child); + } else { + child = &hub->child[port]; + /** release child sources */ + usbh_hubport_release(child); + + /** some USB 3.0 ip may failed to enable USB 2.0 port for USB 3.0 device */ + USB_LOG_WRN("Failed to enable port %u\r\n", port + 1); + + continue; + } + } else { + child = &hub->child[port]; + /** release child sources */ + usbh_hubport_release(child); + USB_LOG_INFO("Device on Bus %u, Hub %u, Port %u disconnected\r\n", hub->bus->busid, hub->index, port + 1); + } + } + } + + /* Start next hub int transfer */ + if (!hub->is_roothub && hub->connected) { + usb_osal_timer_start(hub->int_timer); + } +} + +static void usbh_hub_thread(void *argument) +{ + struct usbh_hub *hub; + int ret = 0; + + struct usbh_bus *bus = (struct usbh_bus *)argument; + + usb_hc_init(bus); + while (1) { + ret = usb_osal_mq_recv(bus->hub_mq, (uintptr_t *)&hub, USB_OSAL_WAITING_FOREVER); + if (ret < 0) { + continue; + } + usbh_hub_events(hub); + } +} + +void usbh_hub_thread_wakeup(struct usbh_hub *hub) +{ + usb_osal_mq_send(hub->bus->hub_mq, (uintptr_t)hub); +} + +int usbh_hub_initialize(struct usbh_bus *bus) +{ + char thread_name[32] = { 0 }; + + bus->hub_mq = usb_osal_mq_create(7); + if (bus->hub_mq == NULL) { + USB_LOG_ERR("Failed to create hub mq\r\n"); + return -1; + } + + snprintf(thread_name, 32, "usbh_hub%u", bus->busid); + bus->hub_thread = usb_osal_thread_create(thread_name, CONFIG_USBHOST_PSC_STACKSIZE, CONFIG_USBHOST_PSC_PRIO, usbh_hub_thread, bus); + if (bus->hub_thread == NULL) { + USB_LOG_ERR("Failed to create hub thread\r\n"); + return -1; + } + return 0; +} + +int usbh_hub_deinitialize(struct usbh_bus *bus) +{ + usb_slist_t *hub_list; + struct usbh_hubport *hport; + size_t flags; + + flags = usb_osal_enter_critical_section(); + + usb_slist_for_each(hub_list, &bus->hub_list) + { + struct usbh_hub *hub = usb_slist_entry(hub_list, struct usbh_hub, list); + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + hport = &hub->child[port]; + + usbh_hubport_release(hport); + } + } + + usb_hc_deinit(bus); + + usb_osal_leave_critical_section(flags); + + usb_osal_mq_delete(bus->hub_mq); + usb_osal_thread_delete(bus->hub_thread); + + return 0; +} + +#if CONFIG_USBHOST_MAX_EXTHUBS > 0 +const struct usbh_class_driver hub_class_driver = { + .driver_name = "hub", + .connect = usbh_hub_connect, + .disconnect = usbh_hub_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info hub_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS, + .class = USB_DEVICE_CLASS_HUB, + .subclass = 0, + .protocol = 0, + .id_table = NULL, + .class_driver = &hub_class_driver +}; +#endif diff --git a/components/drivers/usb/cherryusb/class/hub/usbh_hub.h b/components/drivers/usb/cherryusb/class/hub/usbh_hub.h new file mode 100644 index 00000000000..1f34c53ba71 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/hub/usbh_hub.h @@ -0,0 +1,33 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_HUB_H +#define USBH_HUB_H + +#include "usb_hub.h" + +struct usbh_hub; + +#define USBH_HUB_MAX_PORTS 4 +/* Maximum size of an interrupt IN transfer */ +#define USBH_HUB_INTIN_BUFSIZE ((USBH_HUB_MAX_PORTS + 8) >> 3) + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_hub_set_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature); +int usbh_hub_clear_feature(struct usbh_hub *hub, uint8_t port, uint8_t feature); + +void usbh_hub_thread_wakeup(struct usbh_hub *hub); + +int usbh_hub_initialize(struct usbh_bus *bus); +int usbh_hub_deinitialize(struct usbh_bus *bus); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_HUB_H */ diff --git a/components/drivers/usb/cherryusb/class/midi/usb_midi.h b/components/drivers/usb/cherryusb/class/midi/usb_midi.h new file mode 100644 index 00000000000..3e7a846f4ef --- /dev/null +++ b/components/drivers/usb/cherryusb/class/midi/usb_midi.h @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_MIDI_H +#define USB_MIDI_H + +/* bDescriptorSubType */ +#define MIDI_VC_HEADER_DESCRIPTOR_SUBTYPE 0x01U +#define MIDI_MS_HEADER_DESCRIPTOR_SUBTYPE 0x01U +#define MIDI_MS_GENERAL_DESCRIPTOR_SUBTYPE 0x01U +#define MIDI_MIDI_IN_JACK_DESCRIPTOR_SUBTYPE 0x02U +#define MIDI_MIDI_OUT_JACK_DESCRIPTOR_SUBTYPE 0x03U + +/* bJackType */ +#define MIDI_JACK_TYPE_EMBEDDED 0x01 +#define MIDI_JACK_TYPE_EXTERNAL 0x02 + +#define MIDI_CHANNEL_OMNI 0 +#define MIDI_CHANNEL_OFF 17 + +#define MIDI_PITCHBEND_MIN -8192 +#define MIDI_PITCHBEND_MAX 8191 + +/*! Enumeration of MIDI code index number */ +enum MidiCodeIndexNumber { + MIDI_CIN_MISC = 0, + MIDI_CIN_CABLE_EVENT = 1, + MIDI_CIN_SYSCOM_2BYTE = 2, ///< 2 byte system common message e.g MTC, SongSelect + MIDI_CIN_SYSCOM_3BYTE = 3, ///< 3 byte system common message e.g SPP + MIDI_CIN_SYSEX_START = 4, ///< SysEx starts or continue + MIDI_CIN_SYSEX_END_1BYTE = 5, ///< SysEx ends with 1 data, or 1 byte system common message + MIDI_CIN_SYSEX_END_2BYTE = 6, ///< SysEx ends with 2 data + MIDI_CIN_SYSEX_END_3BYTE = 7, ///< SysEx ends with 3 data + MIDI_CIN_NOTE_OFF = 8, + MIDI_CIN_NOTE_ON = 9, + MIDI_CIN_POLY_KEYPRESS = 10, + MIDI_CIN_CONTROL_CHANGE = 11, + MIDI_CIN_PROGRAM_CHANGE = 12, + MIDI_CIN_CHANNEL_PRESSURE = 13, + MIDI_CIN_PITCH_BEND_CHANGE = 14, + MIDI_CIN_1BYTE_DATA = 15 +}; + +/*! Enumeration of MIDI types */ +enum MidiType { + InvalidType = 0x00, ///< For notifying errors + NoteOff = 0x80, ///< Note Off + NoteOn = 0x90, ///< Note On + AfterTouchPoly = 0xA0, ///< Polyphonic AfterTouch + ControlChange = 0xB0, ///< Control Change / Channel Mode + ProgramChange = 0xC0, ///< Program Change + AfterTouchChannel = 0xD0, ///< Channel (monophonic) AfterTouch + PitchBend = 0xE0, ///< Pitch Bend + SystemExclusive = 0xF0, ///< System Exclusive + TimeCodeQuarterFrame = 0xF1, ///< System Common - MIDI Time Code Quarter Frame + SongPosition = 0xF2, ///< System Common - Song Position Pointer + SongSelect = 0xF3, ///< System Common - Song Select + TuneRequest = 0xF6, ///< System Common - Tune Request + Clock = 0xF8, ///< System Real Time - Timing Clock + Start = 0xFA, ///< System Real Time - Start + Continue = 0xFB, ///< System Real Time - Continue + Stop = 0xFC, ///< System Real Time - Stop + ActiveSensing = 0xFE, ///< System Real Time - Active Sensing + SystemReset = 0xFF, ///< System Real Time - System Reset +}; + +/*! Enumeration of Thru filter modes */ +enum MidiFilterMode { + Off = 0, ///< Thru disabled (nothing passes through). + Full = 1, ///< Fully enabled Thru (every incoming message is sent back). + SameChannel = 2, ///< Only the messages on the Input Channel will be sent back. + DifferentChannel = 3, ///< All the messages but the ones on the Input Channel will be sent back. +}; + +/*! \brief Enumeration of Control Change command numbers. + See the detailed controllers numbers & description here: + http://www.somascape.org/midi/tech/spec.html#ctrlnums + */ +enum MidiControlChangeNumber { + // High resolution Continuous Controllers MSB (+32 for LSB) ---------------- + BankSelect = 0, + ModulationWheel = 1, + BreathController = 2, + // CC3 undefined + FootController = 4, + PortamentoTime = 5, + DataEntry = 6, + ChannelVolume = 7, + Balance = 8, + // CC9 undefined + Pan = 10, + ExpressionController = 11, + EffectControl1 = 12, + EffectControl2 = 13, + // CC14 undefined + // CC15 undefined + GeneralPurposeController1 = 16, + GeneralPurposeController2 = 17, + GeneralPurposeController3 = 18, + GeneralPurposeController4 = 19, + + // Switches ---------------------------------------------------------------- + Sustain = 64, + Portamento = 65, + Sostenuto = 66, + SoftPedal = 67, + Legato = 68, + Hold = 69, + + // Low resolution continuous controllers ----------------------------------- + SoundController1 = 70, ///< Synth: Sound Variation FX: Exciter On/Off + SoundController2 = 71, ///< Synth: Harmonic Content FX: Compressor On/Off + SoundController3 = 72, ///< Synth: Release Time FX: Distortion On/Off + SoundController4 = 73, ///< Synth: Attack Time FX: EQ On/Off + SoundController5 = 74, ///< Synth: Brightness FX: Expander On/Off + SoundController6 = 75, ///< Synth: Decay Time FX: Reverb On/Off + SoundController7 = 76, ///< Synth: Vibrato Rate FX: Delay On/Off + SoundController8 = 77, ///< Synth: Vibrato Depth FX: Pitch Transpose On/Off + SoundController9 = 78, ///< Synth: Vibrato Delay FX: Flange/Chorus On/Off + SoundController10 = 79, ///< Synth: Undefined FX: Special Effects On/Off + GeneralPurposeController5 = 80, + GeneralPurposeController6 = 81, + GeneralPurposeController7 = 82, + GeneralPurposeController8 = 83, + PortamentoControl = 84, + // CC85 to CC90 undefined + Effects1 = 91, ///< Reverb send level + Effects2 = 92, ///< Tremolo depth + Effects3 = 93, ///< Chorus send level + Effects4 = 94, ///< Celeste depth + Effects5 = 95, ///< Phaser depth + + // Channel Mode messages --------------------------------------------------- + AllSoundOff = 120, + ResetAllControllers = 121, + LocalControl = 122, + AllNotesOff = 123, + OmniModeOff = 124, + OmniModeOn = 125, + MonoModeOn = 126, + PolyModeOn = 127 +}; + +struct midi_cs_if_ac_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint16_t bcdADC; + uint16_t wTotalLength; + uint8_t bInCollection; + uint8_t baInterfaceNr[]; +} __PACKED; + +#define MIDI_SIZEOF_AC_HEADER_DESC(n) (8 + n) + +struct midi_cs_if_ms_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint16_t bcdMSC; + uint16_t wTotalLength; +} __PACKED; + +#define MIDI_SIZEOF_MS_HEADER_DESC (7) + +struct midi_cs_if_in_jack_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bJackType; + uint8_t bJackId; + uint8_t iJack; +} __PACKED; + +#define MIDI_SIZEOF_IN_JACK_DESC (6) + +struct midi_cs_if_out_jack_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bJackType; + uint8_t bJackId; + uint8_t bNrInputPins; + uint8_t baSourceId; + uint8_t baSourcePin; + uint8_t iJack; +} __PACKED; + +#define MIDI_SIZEOF_OUT_JACK_DESC (9) + +struct midi_cs_ep_ms_general_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumEmbMIDIJack; + uint8_t baAssocJackID[]; +} __PACKED; + +#define MIDI_SIZEOF_MS_GENERAL_DESC(n) (4 + n) + +// clang-format off +#define MIDI_CS_HEADER_DESCRIPTOR_INIT(wTotalLength) \ + 0x07, /* bLength */ \ + USB_CS_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + MIDI_MS_HEADER_DESCRIPTOR_SUBTYPE, /* bDescriptorSubtype */ \ + WBVAL(0x0100), /* bcdMSC */ \ + WBVAL(wTotalLength) /* wTotalLength */ + +#define MIDI_IN_JACK_DESCRIPTOR_INIT(bJackType, bJackID) \ + 0x06, \ + 0x24, \ + MIDI_MIDI_IN_JACK_DESCRIPTOR_SUBTYPE, \ + bJackType, \ + bJackID, \ + 0x00 + +#define MIDI_OUT_JACK_DESCRIPTOR_INIT(bJackType, bJackID, baSourceID) \ + 0x09, \ + 0x24, \ + MIDI_MIDI_OUT_JACK_DESCRIPTOR_SUBTYPE, \ + bJackType, \ + bJackID, \ + 0x01, \ + baSourceID, \ + 0x01, \ + 0x00 + +#define MIDI_JACK_DESCRIPTOR_INIT(bJackFirstID) \ + MIDI_IN_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EMBEDDED, bJackFirstID), \ + MIDI_IN_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EXTERNAL, (bJackFirstID + 1)), \ + MIDI_OUT_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EMBEDDED, (bJackFirstID + 2), (bJackFirstID + 1)), \ + MIDI_OUT_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EXTERNAL, (bJackFirstID + 3), (bJackFirstID)) + +#define MIDI_SIZEOF_JACK_DESC (6 + 6 + 9 + 9) + +// clang-format on + +#endif /* USB_MIDI_H */ diff --git a/components/drivers/usb/cherryusb/class/msc/usb_msc.h b/components/drivers/usb/cherryusb/class/msc/usb_msc.h new file mode 100644 index 00000000000..75187f5ee63 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/msc/usb_msc.h @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_MSC_H +#define USB_MSC_H + +/* MSC Subclass Codes */ +#define MSC_SUBCLASS_RBC 0x01 /* Reduced block commands (e.g., flash devices) */ +#define MSC_SUBCLASS_SFF8020I_MMC2 0x02 /* SFF-8020i/MMC-2 (ATAPI) (e.g., C/DVD) */ +#define MSC_SUBCLASS_QIC157 0x03 /* QIC-157 (e.g., tape device) */ +#define MSC_SUBCLASS_UFI 0x04 /* e.g. floppy device */ +#define MSC_SUBCLASS_SFF8070I 0x05 /* SFF-8070i (e.g. floppy disk) */ +#define MSC_SUBCLASS_SCSI 0x06 /* SCSI transparent */ + +/* MSC Protocol Codes */ +#define MSC_PROTOCOL_CBI_INT 0x00 /* CBI transport with command completion interrupt */ +#define MSC_PROTOCOL_CBI_NOINT 0x01 /* CBI transport without command completion interrupt */ +#define MSC_PROTOCOL_BULK_ONLY 0x50 /* Bulk only transport */ + +/* MSC Request Codes */ +#define MSC_REQUEST_RESET 0xFF +#define MSC_REQUEST_GET_MAX_LUN 0xFE + +/** MSC Command Block Wrapper (CBW) Signature */ +#define MSC_CBW_Signature 0x43425355 +/** Bulk-only Command Status Wrapper (CSW) Signature */ +#define MSC_CSW_Signature 0x53425355 + +/** MSC Command Block Status Values */ +#define CSW_STATUS_CMD_PASSED 0x00 +#define CSW_STATUS_CMD_FAILED 0x01 +#define CSW_STATUS_PHASE_ERROR 0x02 + +#define MSC_MAX_CDB_LEN (16) /* Max length of SCSI Command Data Block */ + +/** MSC Bulk-Only Command Block Wrapper (CBW) */ +struct CBW { + uint32_t dSignature; /* 'USBC' = 0x43425355 */ + uint32_t dTag; /* Depends on command id */ + uint32_t dDataLength; /* Number of bytes that host expects to transfer */ + uint8_t bmFlags; /* Bit 7: Direction=IN (other obsolete or reserved) */ + uint8_t bLUN; /* LUN (normally 0) */ + uint8_t bCBLength; /* len of cdb[] */ + uint8_t CB[MSC_MAX_CDB_LEN]; /* Command Data Block */ +} __PACKED; + +#define USB_SIZEOF_MSC_CBW 31 + +/** MSC Bulk-Only Command Status Wrapper (CSW) */ +struct CSW { + uint32_t dSignature; /* 'USBS' = 0x53425355 */ + uint32_t dTag; /* Same tag as original command */ + uint32_t dDataResidue; /* Amount not transferred */ + uint8_t bStatus; /* Status of transfer */ +} __PACKED; + +#define USB_SIZEOF_MSC_CSW 13 + +/*Length of template descriptor: 23 bytes*/ +#define MSC_DESCRIPTOR_LEN (9 + 7 + 7) +// clang-format off +#define MSC_DESCRIPTOR_INIT(bFirstInterface, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_MASS_STORAGE, /* bInterfaceClass */ \ + MSC_SUBCLASS_SCSI, /* bInterfaceSubClass */ \ + MSC_PROTOCOL_BULK_ONLY, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#endif /* USB_MSC_H */ diff --git a/components/drivers/usb/cherryusb/class/msc/usb_scsi.h b/components/drivers/usb/cherryusb/class/msc/usb_scsi.h new file mode 100644 index 00000000000..7eeb50a72ca --- /dev/null +++ b/components/drivers/usb/cherryusb/class/msc/usb_scsi.h @@ -0,0 +1,972 @@ +/* + * Apache NuttX + * Copyright 2020 The Apache Software Foundation + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __INCLUDE_NUTTX_SCSI_H +#define __INCLUDE_NUTTX_SCSI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* SCSI commands ************************************************************/ + +#define SCSI_CMD_TESTUNITREADY 0x00 +#define SCSI_CMD_REZEROUNIT 0x01 +#define SCSI_CMD_REQUESTSENSE 0x03 +#define SCSI_CMD_FORMAT_UNIT 0x04 +#define SCSI_CMD_REASSIGNBLOCKS 0x07 +#define SCSI_CMD_READ6 0x08 +#define SCSI_CMD_WRITE6 0x0a +#define SCSI_CMD_SEEK6 0x0b +#define SCSI_CMD_SPACE6 0x11 +#define SCSI_CMD_INQUIRY 0x12 +#define SCSI_CMD_MODESELECT6 0x15 +#define SCSI_CMD_RESERVE6 0x16 +#define SCSI_CMD_RELEASE6 0x17 +#define SCSI_CMD_COPY 0x18 +#define SCSI_CMD_MODESENSE6 0x1a +#define SCSI_CMD_STARTSTOPUNIT 0x1b +#define SCSI_CMD_RECEIVEDIAGNOSTICRESULTS 0x1c +#define SCSI_CMD_SENDDIAGNOSTIC 0x1d +#define SCSI_CMD_PREVENTMEDIAREMOVAL 0x1e +#define SCSI_CMD_READFORMATCAPACITIES 0x23 +#define SCSI_CMD_READCAPACITY10 0x25 +#define SCSI_CMD_READ10 0x28 +#define SCSI_CMD_WRITE10 0x2a +#define SCSI_CMD_SEEK10 0x2b +#define SCSI_CMD_WRITEANDVERIFY 0x2e +#define SCSI_CMD_VERIFY10 0x2f +#define SCSI_CMD_SEARCHDATAHIGH 0x30 +#define SCSI_CMD_SEARCHDATAEQUAL 0x31 +#define SCSI_CMD_SEARCHDATALOW 0x32 +#define SCSI_CMD_SETLIMITS10 0x33 +#define SCSI_CMD_PREFETCH10 0x34 +#define SCSI_CMD_SYNCHCACHE10 0x35 +#define SCSI_CMD_LOCKCACHE 0x36 +#define SCSI_CMD_READDEFECTDATA10 0x37 +#define SCSI_CMD_COMPARE 0x39 +#define SCSI_CMD_COPYANDVERIFY 0x3a +#define SCSI_CMD_WRITEBUFFER 0x3b +#define SCSI_CMD_READBUFFER 0x3c +#define SCSI_CMD_READLONG10 0x3e +#define SCSI_CMD_WRITELONG10 0x3f +#define SCSI_CMD_CHANGEDEFINITION 0x40 +#define SCSI_CMD_WRITESAME10 0x41 +#define SCSI_CMD_LOGSELECT 0x4c +#define SCSI_CMD_LOGSENSE 0x4d +#define SCSI_CMD_XDWRITE10 0x50 +#define SCSI_CMD_XPWRITE10 0x51 +#define SCSI_CMD_XDREAD10 0x52 +#define SCSI_CMD_MODESELECT10 0x55 +#define SCSI_CMD_RESERVE10 0x56 +#define SCSI_CMD_RELEASE10 0x57 +#define SCSI_CMD_MODESENSE10 0x5a +#define SCSI_CMD_PERSISTENTRESERVEIN 0x5e +#define SCSI_CMD_PERSISTENTRESERVEOUT 0x5f +#define SCSI_CMD_32 0x7f +#define SCSI_CMD_XDWRITEEXTENDED 0x80 +#define SCSI_CMD_REBUILD 0x82 +#define SCSI_CMD_REGENERATE 0x82 +#define SCSI_CMD_EXTENDEDCOPY 0x83 +#define SCSI_CMD_COPYRESULTS 0x84 +#define SCSI_CMD_ACCESSCONTROLIN 0x86 +#define SCSI_CMD_ACCESSCONTROLOUT 0x87 +#define SCSI_CMD_READ16 0x88 +#define SCSI_CMD_WRITE16 0x8a +#define SCSI_CMD_READATTRIBUTE 0x8c +#define SCSI_CMD_WRITEATTRIBUTE 0x8d +#define SCSI_CMD_WRITEANDVERIFY16 0x8e +#define SCSI_CMD_PREFETCH16 0x90 +#define SCSI_CMD_SYNCHCACHE16 0x91 +#define SCSI_CMD_LOCKUNLOCKACACHE 0x92 +#define SCSI_CMD_WRITESAME16 0x93 +#define SCSI_CMD_READCAPACITY16 0x9e +#define SCSI_CMD_READLONG16 0x9e +#define SCSI_CMD_WRITELONG106 0x9f +#define SCSI_CMD_REPORTLUNS 0xa0 +#define SCSI_CMD_MAINTENANCEIN 0xa3 +#define SCSI_CMD_MAINTENANCEOUT 0xa4 +#define SCSI_CMD_MOVEMEDIUM 0xa5 +#define SCSI_CMD_MOVEMEDIUMATTACHED 0xa7 +#define SCSI_CMD_READ12 0xa8 +#define SCSI_CMD_WRITE12 0xaa +#define SCSI_CMD_READMEDIASERIALNUMBER 0xab +#define SCSI_CMD_WRITEANDVERIFY12 0xae +#define SCSI_CMD_VERIFY12 0xaf +#define SCSI_CMD_SETLIMITS12 0xb3 +#define SCSI_CMD_READELEMENTSTATUS 0xb4 +#define SCSI_CMD_READDEFECTDATA12 0xb7 +#define SCSI_CMD_REDUNDANCYGROUPIN 0xba +#define SCSI_CMD_REDUNDANCYGROUPOUT 0xbb +#define SCSI_CMD_SPAREIN 0xbc +#define SCSI_CMD_SPAREOUT 0xbd +#define SCSI_CMD_VOLUMESETIN 0xbe +#define SCSI_CMD_VOLUMESETOUT 0xbf + +/* Common SCSI KCQ values (sense Key/additional sense Code/ASC Qualifier) *** + * + * 0xnn0386 Write Fault Data Corruption + * 0xnn0500 Illegal request + * 0xnn0600 Unit attention + * 0xnn0700 Data protect + * 0xnn0800 LUN communication failure + * 0xnn0801 LUN communication timeout + * 0xnn0802 LUN communication parity error + * 0xnn0803 LUN communication CRC error + * 0xnn0900 vendor specific sense key + * 0xnn0901 servo fault + * 0xnn0904 head select fault + * 0xnn0a00 error log overflow + * 0xnn0b00 aborted command + * 0xnn0c00 write error + * 0xnn0c02 write error - auto-realloc failed + * 0xnn0e00 data miscompare + * 0xnn1200 address mark not founf for ID field + * 0xnn1400 logical block not found + * 0xnn1500 random positioning error + * 0xnn1501 mechanical positioning error + * 0xnn1502 positioning error detected by read of medium + * 0xnn2700 write protected + * 0xnn2900 POR or bus reset occurred + * 0xnn3101 format failed + * 0xnn3191 format corrupted + * 0xnn3201 defect list update error + * 0xnn3202 no spares available + * 0xnn3501 unspecified enclosure services failure + * 0xnn3700 parameter rounded + * 0xnn3d00 invalid bits in identify message + * 0xnn3e00 LUN not self-configured yet + * 0xnn4001 DRAM parity error + * 0xnn4002 DRAM parity error + * 0xnn4200 power-on or self-test failure + * 0xnn4c00 LUN failed self-configuration + * 0xnn5c00 RPL status change + * 0xnn5c01 spindles synchronized + * 0xnn5c02 spindles not synchronized + * 0xnn6500 voltage fault + * 0xnn8000 general firmware error + */ + +/* No sense KCQ values */ + +#define SCSI_KCQ_NOSENSE 0x000000 /* No error */ +#define SCSI_KCQ_PFATHRESHOLDREACHED 0x005c00 /* No sense - PFA threshold reached */ + +/* Soft error KCQ values */ + +#define SCSI_KCQSE_RWENOINDEX 0x010100 /* Recovered Write error - no index */ +#define SCSI_KCQSE_RECOVEREDNOSEEKCOMPLETION 0x010200 /* Recovered no seek completion */ +#define SCSI_KCQSE_RWEWRITEFAULT 0x010300 /* Recovered Write error - write fault */ +#define SCSI_KCQSE_TRACKFOLLOWINGERROR 0x010900 /* Track following error */ +#define SCSI_KCQSE_TEMPERATUREWARNING 0x010b01 /* Temperature warning */ +#define SCSI_KCQSE_RWEWARREALLOCATED 0x010c01 /* Recovered Write error with auto-realloc - reallocated */ +#define SCSI_KCQSE_RWERECOMMENDREASSIGN 0x010c03 /* Recovered Write error - recommend reassign */ +#define SCSI_KCQSE_RDWOEUSINGPREVLBI 0x011201 /* Recovered data without ECC using prev logical block ID */ +#define SCSI_KCQSE_RDWEUSINGPREVLBI 0x011202 /* Recovered data with ECC using prev logical block ID */ +#define SCSI_KCQSE_RECOVEREDRECORDNOTFOUND 0x011401 /* Recovered Record Not Found */ +#define SCSI_KCQSE_RWEDSME 0x011600 /* Recovered Write error - Data Sync Mark Error */ +#define SCSI_KCQSE_RWEDSEDATAREWRITTEN 0x011601 /* Recovered Write error - Data Sync Error - data rewritten */ +#define SCSI_KCQSE_RWEDSERECOMMENDREWRITE 0x011602 /* Recovered Write error - Data Sync Error - recommend rewrite */ +#define SCSI_KCQSE_RWEDSEDATAAUTOREALLOCATED 0x011603 /* Recovered Write error - Data Sync Error - data auto-reallocated */ +#define SCSI_KCQSE_RWEDSERECOMMENDREASSIGNMENT 0x011604 /* Recovered Write error - Data Sync Error - recommend reassignment */ +#define SCSI_KCQSE_RDWNECORRECTIONAPPLIED 0x011700 /* Recovered data with no error correction applied */ +#define SCSI_KCQSE_RREWITHRETRIES 0x011701 /* Recovered Read error - with retries */ +#define SCSI_KCQSE_RDUSINGPOSITIVEOFFSET 0x011702 /* Recovered data using positive offset */ +#define SCSI_KCQSE_RDUSINGNEGATIVEOFFSET 0x011703 /* Recovered data using negative offset */ +#define SCSI_KCQSE_RDUSINGPREVIOUSLBI 0x011705 /* Recovered data using previous logical block ID */ +#define SCSI_KCQSE_RREWOEAUTOREALLOCATED 0x011706 /* Recovered Read error - without ECC, auto reallocated */ +#define SCSI_KCQSE_RREWOERECOMMENDREASSIGN 0x011707 /* Recovered Read error - without ECC, recommend reassign */ +#define SCSI_KCQSE_RREWOERECOMMENDREWRITE 0x011708 /* Recovered Read error - without ECC, recommend rewrite */ +#define SCSI_KCQSE_RREWOEDATAREWRITTEN 0x011709 /* Recovered Read error - without ECC, data rewritten */ +#define SCSI_KCQSE_RREWE 0x011800 /* Recovered Read error - with ECC */ +#define SCSI_KCQSE_RDWEANDRETRIES 0x011801 /* Recovered data with ECC and retries */ +#define SCSI_KCQSE_RREWEAUTOREALLOCATED 0x011802 /* Recovered Read error - with ECC, auto reallocated */ +#define SCSI_KCQSE_RREWERECOMMENDREASSIGN 0x011805 /* Recovered Read error - with ECC, recommend reassign */ +#define SCSI_KCQSE_RDUSINGECCANDOFFSETS 0x011806 /* Recovered data using ECC and offsets */ +#define SCSI_KCQSE_RREWEDATAREWRITTEN 0x011807 /* Recovered Read error - with ECC, data rewritten */ +#define SCSI_KCQSE_DLNOTFOUND 0x011c00 /* Defect List not found */ +#define SCSI_KCQSE_PRIMARYDLNOTFOUND 0x011c01 /* Primary defect list not found */ +#define SCSI_KCQSE_GROWNDLNOTFOUND 0x011c02 /* Grown defect list not found */ +#define SCSI_KCQSE_PARTIALDLTRANSFERRED 0x011f00 /* Partial defect list transferred */ +#define SCSI_KCQSE_INTERNALTARGETFAILURE 0x014400 /* Internal target failure */ +#define SCSI_KCQSE_PFATHRESHOLDREACHED 0x015d00 /* PFA threshold reached */ +#define SCSI_KCQSE_PFATESTWARNING 0x015dff /* PFA test warning */ +#define SCSI_KCQSE_INTERNALLOGICFAILURE 0x018100 /* Internal logic failure */ + +/* Not Ready / Diagnostic Failure KCQ values */ + +#define SCSI_KCQNR_CAUSENOTREPORTABLE 0x020400 /* Not Ready - Cause not reportable. */ +#define SCSI_KCQNR_BECOMINGREADY 0x020401 /* Not Ready - becoming ready */ +#define SCSI_KCQNR_NEEDINITIALIZECOMMAND 0x020402 /* Not Ready - need initialize command (start unit) */ +#define SCSI_KCQNR_MANUALINTERVENTIONREQUIRED 0x020403 /* Not Ready - manual intervention required */ +#define SCSI_KCQNR_FORMATINPROGRESS 0x020404 /* Not Ready - format in progress */ +#define SCSI_KCQNR_SELFTESTINPROGRESS 0x020409 /* Not Ready - self-test in progress */ +#define SCSI_KCQNR_MEDIUMFORMATCORRUPTED 0x023100 /* Not Ready - medium format corrupted */ +#define SCSI_KCQNR_FORMATCOMMANDFAILED 0x023101 /* Not Ready - format command failed */ +#define SCSI_KCQNR_ESUNAVAILABLE 0x023502 /* Not Ready - enclosure services unavailable */ +#define SCSI_KCQNR_MEDIANOTPRESENT 0x023a00 /* Not Ready - media not present */ +#define SCSI_KCQDF_BRINGUPFAILORDEGRADEDMODE 0x024080 /* Diagnostic Failure - bring-up fail or degraded mode */ +#define SCSI_KCQDF_HARDDISKCONTROLLER 0x024081 /* Diagnostic Failure - Hard Disk Controller */ +#define SCSI_KCQDF_RAMMICROCODENOTLOADED 0x024085 /* Diagnostic Failure - RAM microcode not loaded */ +#define SCSI_KCQDF_RROCALIBRATION 0x024090 /* Diagnostic Failure - RRO Calibration */ +#define SCSI_KCQDF_CHANNELCALIBRATION 0x024091 /* Diagnostic Failure - Channel Calibration */ +#define SCSI_KCQDF_HEADLOAD 0x024092 /* Diagnostic Failure - Head Load */ +#define SCSI_KCQDF_WRITEAE 0x024093 /* Diagnostic Failure - Write AE */ +#define SCSI_KCQDF_12VOVERCURRENT 0x024094 /* Diagnostic Failure - 12V over current */ +#define SCSI_KCQDF_OTHERSPINDLEFAILURE 0x024095 /* Diagnostic Failure - Other spindle failure */ +#define SCSI_KCQDF_SELFRESET 0x0240b0 /* Diagnostic Failure - self-reset */ +#define SCSI_KCQDF_CONFIGNOTLOADED 0x024c00 /* Diagnostic Failure - config not loaded */ + +/* Medium error KCQ values */ + +#define SCSI_KCQME_WRITEFAULT 0x030300 /* Medium Error - write fault */ +#define SCSI_KCQME_WRITEFAULTAUTOREALLOCFAILED 0x030c02 /* Medium Error - write error - auto-realloc failed */ +#define SCSI_KCQME_WRITERTLIMITEXCEEDED 0x030cbb /* Medium Error - write recovery time limit exceeded */ +#define SCSI_KCQME_IDCRCERROR 0x031000 /* Medium Error - ID CRC error */ +#define SCSI_KCQME_UNRRE1 0x031100 /* Medium Error - unrecovered read error */ +#define SCSI_KCQME_READRETRIESEXHAUSTED 0x031101 /* Medium Error - read retries exhausted */ +#define SCSI_KCQME_ERRORTOOLONGTOCORRECT 0x031102 /* Medium Error - error too long to correct */ +#define SCSI_KCQME_UREAUTOREALLOCFAILED 0x031104 /* Medium Error - unrecovered read error - auto re-alloc failed */ +#define SCSI_KCQME_URERECOMMENDREASSIGN 0x03110b /* Medium Error - unrecovered read error - recommend reassign */ +#define SCSI_KCQME_READRTLIMITEXCEEDED 0x0311ff /* Medium Error - read recovery time limit exceeded */ +#define SCSI_KCQME_RECORDNOTFOUND 0x031401 /* Medium Error - record not found */ +#define SCSI_KCQME_DSME 0x031600 /* Medium Error - Data Sync Mark error */ +#define SCSI_KCQME_DSERECOMMENDREASSIGN 0x031604 /* Medium Error - Data Sync Error - recommend reassign */ +#define SCSI_KCQME_DLE 0x031900 /* Medium Error - defect list error */ +#define SCSI_KCQME_DLNOTAVAILABLE 0x031901 /* Medium Error - defect list not available */ +#define SCSI_KCQME_DLEINPRIMARYLIST 0x031902 /* Medium Error - defect list error in primary list */ +#define SCSI_KCQME_DLEINGROWNLIST 0x031903 /* Medium Error - defect list error in grown list */ +#define SCSI_KCQME_FEWERTHAN50PCTDLCOPIES 0x03190e /* Medium Error - fewer than 50% defect list copies */ +#define SCSI_KCQME_MEDIUMFORMATCORRUPTED 0x033100 /* Medium Error - medium format corrupted */ +#define SCSI_KCQME_FORMATCOMMANDFAILED 0x033101 /* Medium Error - format command failed */ +#define SCSI_KCQME_DATAAUTOREALLOCATED 0x038000 /* Medium Error - data auto-reallocated */ + +/* Hardware Error KCQ values */ + +#define SCSI_KCQHE_NOINDEXORSECTOR 0x040100 /* Hardware Error - no index or sector */ +#define SCSI_KCQHE_NOSEEKCOMPLETE 0x040200 /* Hardware Error - no seek complete */ +#define SCSI_KCQHE_WRITEFAULT 0x040300 /* Hardware Error - write fault */ +#define SCSI_KCQHE_COMMUNICATIONFAILURE 0x040800 /* Hardware Error - communication failure */ +#define SCSI_KCQHE_TRACKFOLLOWINGERROR 0x040900 /* Hardware Error - track following error */ +#define SCSI_KCQHE_UREINRESERVEDAREA 0x041100 /* Hardware Error - unrecovered read error in reserved area */ +#define SCSI_KCQHE_DSMEINRESERVEDAREA 0x041600 /* Hardware Error - Data Sync Mark error in reserved area */ +#define SCSI_KCQHE_DLE 0x041900 /* Hardware Error - defect list error */ +#define SCSI_KCQHE_DLEINPRIMARYLIST 0x041902 /* Hardware Error - defect list error in Primary List */ +#define SCSI_KCQHE_DLEINGROWNLIST 0x041903 /* Hardware Error - defect list error in Grown List */ +#define SCSI_KCQHE_REASSIGNFAILED 0x043100 /* Hardware Error - reassign failed */ +#define SCSI_KCQHE_NODEFECTSPAREAVAILABLE 0x043200 /* Hardware Error - no defect spare available */ +#define SCSI_KCQHE_UNSUPPORTEDENCLOSUREFUNCTION 0x043501 /* Hardware Error - unsupported enclosure function */ +#define SCSI_KCQHE_ESUNAVAILABLE 0x043502 /* Hardware Error - enclosure services unavailable */ +#define SCSI_KCQHE_ESTRANSFERFAILURE 0x043503 /* Hardware Error - enclosure services transfer failure */ +#define SCSI_KCQHE_ESREFUSED 0x043504 /* Hardware Error - enclosure services refused */ +#define SCSI_KCQHE_SELFTESTFAILED 0x043e03 /* Hardware Error - self-test failed */ +#define SCSI_KCQHE_UNABLETOUPDATESELFTEST 0x043e04 /* Hardware Error - unable to update self-test */ +#define SCSI_KCQHE_DMDIAGNOSTICFAIL 0x044080 /* Hardware Error - Degrade Mode. Diagnostic Fail */ +#define SCSI_KCQHE_DMHWERROR 0x044081 /* Hardware Error - Degrade Mode. H/W Error */ +#define SCSI_KCQHE_DMRAMMICROCODENOTLOADED 0x044085 /* Hardware Error - Degrade Mode. RAM microcode not loaded */ +#define SCSI_KCQHE_SEEKTESTFAILURE 0x044090 /* Hardware Error - seek test failure */ +#define SCSI_KCQHE_READWRITETESTFAILURE 0x0440a0 /* Hardware Error - read/write test failure */ +#define SCSI_KCQHE_DEVICESELFRESET 0x0440b0 /* Hardware Error - device self-reset */ +#define SCSI_KCQHE_COMPONENTMISMATCH 0x0440d0 /* Hardware Error - component mismatch */ +#define SCSI_KCQHE_INTERNALTARGETFAILURE 0x044400 /* Hardware Error - internal target failure */ +#define SCSI_KCQHE_INTERNALLOGICERROR 0x048100 /* Hardware Error - internal logic error */ +#define SCSI_KCQHE_COMMANDTIMEOUT 0x048200 /* Hardware Error - command timeout */ + +/* Illegal Request KCQ values */ + +#define SCSI_KCQIR_PARMLISTLENGTHERROR 0x051a00 /* Illegal Request - parm list length error */ +#define SCSI_KCQIR_INVALIDCOMMAND 0x052000 /* Illegal Request - invalid/unsupported command code */ +#define SCSI_KCQIR_LBAOUTOFRANGE 0x052100 /* Illegal Request - LBA out of range */ +#define SCSI_KCQIR_INVALIDFIELDINCBA 0x052400 /* Illegal Request - invalid field in CDB (Command Descriptor Block) */ +#define SCSI_KCQIR_INVALIDLUN 0x052500 /* Illegal Request - invalid LUN */ +#define SCSI_KCQIR_INVALIDFIELDSINPARMLIST 0x052600 /* Illegal Request - invalid fields in parm list */ +#define SCSI_KCQIR_PARAMETERNOTSUPPORTED 0x052601 /* Illegal Request - parameter not supported */ +#define SCSI_KCQIR_INVALIDPARMVALUE 0x052602 /* Illegal Request - invalid parm value */ +#define SCSI_KCQIR_IFPTHRESHOLDPARAMETER 0x052603 /* Illegal Request - invalid field parameter - threshold parameter */ +#define SCSI_KCQIR_INVALIDRELEASEOFPR 0x052604 /* Illegal Request - invalid release of persistent reservation */ +#define SCSI_KCQIR_IFPTMSFIRMWARETAG 0x052697 /* Illegal Request - invalid field parameter - TMS firmware tag */ +#define SCSI_KCQIR_IFPCHECKSUM 0x052698 /* Illegal Request - invalid field parameter - check sum */ +#define SCSI_KCQIR_IFPFIRMWARETAG 0x052699 /* Illegal Request - invalid field parameter - firmware tag */ +#define SCSI_KCQIR_COMMANDSEQUENCEERROR 0x052c00 /* Illegal Request - command sequence error */ +#define SCSI_KCQIR_UNSUPPORTEDENCLOSUREFUNCTION 0x053501 /* Illegal Request - unsupported enclosure function */ +#define SCSI_KCQIR_SAVINGPARMSNOTSUPPORTED 0x053900 /* Illegal Request - Saving parameters not supported */ +#define SCSI_KCQIR_INVALIDMESSAGE 0x054900 /* Illegal Request - invalid message */ +#define SCSI_KCQIR_MEDIALOADOREJECTFAILED 0x055300 /* Illegal Request - media load or eject failed */ +#define SCSI_KCQIR_UNLOADTAPEFAILURE 0x055301 /* Illegal Request - unload tape failure */ +#define SCSI_KCQIR_MEDIUMREMOVALPREVENTED 0x055302 /* Illegal Request - medium removal prevented */ +#define SCSI_KCQIR_SYSTEMRESOURCEFAILURE 0x055500 /* Illegal Request - system resource failure */ +#define SCSI_KCQIR_SYSTEMBUFFERFULL 0x055501 /* Illegal Request - system buffer full */ +#define SCSI_KCQIR_INSUFFICIENTRR 0x055504 /* Illegal Request - Insufficient Registration Resources */ + +/* Unit Attention KCQ values */ + +#define SCSI_KCQUA_NOTREADYTOTRANSITION 0x062800 /* Unit Attention - not-ready to ready transition (format complete) */ +#define SCSI_KCQUA_DEVICERESETOCCURRED 0x062900 /* Unit Attention - POR or device reset occurred */ +#define SCSI_KCQUA_POROCCURRED 0x062901 /* Unit Attention - POR occurred */ +#define SCSI_KCQUA_SCSIBUSRESETOCCURRED 0x062902 /* Unit Attention - SCSI bus reset occurred */ +#define SCSI_KCQUA_TARGETRESETOCCURRED 0x062903 /* Unit Attention - TARGET RESET occurred */ +#define SCSI_KCQUA_SELFINITIATEDRESETOCCURRED 0x062904 /* Unit Attention - self-initiated-reset occurred */ +#define SCSI_KCQUA_TRANSCEIVERMODECHANGETOSE 0x062905 /* Unit Attention - transceiver mode change to SE */ +#define SCSI_KCQUA_TRANSCEIVERMODECHANGETOLVD 0x062906 /* Unit Attention - transceiver mode change to LVD */ +#define SCSI_KCQUA_PARAMETERSCHANGED 0x062a00 /* Unit Attention - parameters changed */ +#define SCSI_KCQUA_MODEPARAMETERSCHANGED 0x062a01 /* Unit Attention - mode parameters changed */ +#define SCSI_KCQUA_LOGSELECTPARMSCHANGED 0x062a02 /* Unit Attention - log select parms changed */ +#define SCSI_KCQUA_RESERVATIONSPREEMPTED 0x062a03 /* Unit Attention - Reservations pre-empted */ +#define SCSI_KCQUA_RESERVATIONSRELEASED 0x062a04 /* Unit Attention - Reservations released */ +#define SCSI_KCQUA_REGISTRATIONSPREEMPTED 0x062a05 /* Unit Attention - Registrations pre-empted */ +#define SCSI_KCQUA_COMMANDSCLEARED 0x062f00 /* Unit Attention - commands cleared by another initiator */ +#define SCSI_KCQUA_OPERATINGCONDITIONSCHANGED 0x063f00 /* Unit Attention - target operating conditions have changed */ +#define SCSI_KCQUA_MICROCODECHANGED 0x063f01 /* Unit Attention - microcode changed */ +#define SCSI_KCQUA_CHANGEDOPERATINGDEFINITION 0x063f02 /* Unit Attention - changed operating definition */ +#define SCSI_KCQUA_INQUIRYPARAMETERSCHANGED 0x063f03 /* Unit Attention - inquiry parameters changed */ +#define SCSI_KCQUA_DEVICEIDENTIFIERCHANGED 0x063f05 /* Unit Attention - device identifier changed */ +#define SCSI_KCQUA_INVALIDAPMPARAMETERS 0x063f90 /* Unit Attention - invalid APM parameters */ +#define SCSI_KCQUA_WORLDWIDENAMEMISMATCH 0x063f91 /* Unit Attention - world-wide name mismatch */ +#define SCSI_KCQUA_PFATHRESHOLDREACHED 0x065d00 /* Unit Attention - PFA threshold reached */ +#define SCSI_KCQUA_PFATHRESHOLDEXCEEDED 0x065dff /* Unit Attention - PFA threshold exceeded */ + +/* Write Protect KCQ values */ + +#define SCSI_KCQWP_COMMANDNOTALLOWED 0x072700 /* Write Protect - command not allowed */ + +/* Aborted Command KCQ values */ + +#define SCSI_KCQAC_NOADDITIONALSENSECODE 0x0b0000 /* Aborted Command - no additional sense code */ +#define SCSI_KCQAC_SYNCDATATRANSFERERROR 0x0b1b00 /* Aborted Command - sync data transfer error (extra ACK) */ +#define SCSI_KCQAC_UNSUPPORTEDLUN 0x0b2500 /* Aborted Command - unsupported LUN */ +#define SCSI_KCQAC_ECHOBUFFEROVERWRITTEN 0x0b3f0f /* Aborted Command - echo buffer overwritten */ +#define SCSI_KCQAC_MESSAGEREJECTERROR 0x0b4300 /* Aborted Command - message reject error */ +#define SCSI_KCQAC_INTERNALTARGETFAILURE 0x0b4400 /* Aborted Command - internal target failure */ +#define SCSI_KCQAC_SELECTIONFAILURE 0x0b4500 /* Aborted Command - Selection/Reselection failure */ +#define SCSI_KCQAC_SCSIPARITYERROR 0x0b4700 /* Aborted Command - SCSI parity error */ +#define SCSI_KCQAC_INITIATORDETECTEDERRORECEIVED 0x0b4800 /* Aborted Command - initiator-detected error message received */ +#define SCSI_KCQAC_ILLEGALMESSAGE 0x0b4900 /* Aborted Command - inappropriate/illegal message */ +#define SCSI_KCQAC_DATAPHASEERROR 0x0b4b00 /* Aborted Command - data phase error */ +#define SCSI_KCQAC_OVERLAPPEDCOMMANDSATTEMPTED 0x0b4e00 /* Aborted Command - overlapped commands attempted */ +#define SCSI_KCQAC_LOOPINITIALIZATION 0x0b4f00 /* Aborted Command - due to loop initialization */ + +/* Other KCQ values: */ + +#define SCSO_KCQOTHER_MISCOMPARE 0x0e1d00 /* Miscompare - during verify byte check operation */ + +/* SSCSI Status Codes *******************************************************/ + +#define SCSI_STATUS_OK 0x00 /* OK */ +#define SCSI_STATUS_CHECKCONDITION 0x02 /* Check condition */ +#define SCSI_STATUS_CONDITIONMET 0x04 /* Condition met */ +#define SCSI_STATUS_BUSY 0x08 /* Busy */ +#define SCSI_STATUS_INTERMEDIATE 0x10 /* Intermediate */ +#define SCSI_STATUS_DATAOVERUNDERRUN 0x12 /* Data Under/Over Run? */ +#define SCSI_STATUS_INTERMEDIATECONDITIONMET 0x14 /* Intermediate - Condition met */ +#define SCSI_STATUS_RESERVATIONCONFLICT 0x18 /* Reservation conflict */ +#define SCSI_STATUS_COMMANDTERMINATED 0x22 /* Command terminated */ +#define SCSI_STATUS_QUEUEFULL 0x28 /* Queue (task set) full */ +#define SCSI_STATUS_ACAACTIVE 0x30 /* ACA active */ +#define SCSI_STATUS_TASKABORTED 0x40 /* Task aborted */ + +/* Definitions for selected SCSI commands ***********************************/ + +/* Inquiry */ + +#define SCSICMD_INQUIRYFLAGS_EVPD 0x01 /* Bit 0: EVPD */ + /* Bits 5-7: Peripheral Qualifier */ +#define SCSIRESP_INQUIRYPQ_CONNECTED 0x00 /* 000: Device is connected */ +#define SCSIRESP_INQUIRYPQ_NOTCONNECTED 0x20 /* 001: Device is NOT connected */ +#define SCSIRESP_INQUIRYPQ_NOTCAPABLE 0x60 /* 011: LUN not supported */ + /* Bits 0-4: Peripheral Device */ +#define SCSIRESP_INQUIRYPD_DIRECTACCESS 0x00 /* Direct-access block device */ +#define SCSIRESP_INQUIRYPD_SEQUENTIALACCESS 0x01 /* Sequential-access block device */ +#define SCSIRESP_INQUIRYPD_PRINTER 0x02 /* Printer device */ +#define SCSIRESP_INQUIRYPD_PROCESSOR 0x03 /* Processor device */ +#define SCSIRESP_INQUIRYPD_WRONCE 0x04 /* Write once device */ +#define SCSIRESP_INQUIRYPD_CDDVD 0x05 /* CD/DVD device */ +#define SCSIRESP_INQUIRYPD_SCANNER 0x06 /* Scanner device (obsolete) */ +#define SCSIRESP_INQUIRYPD_OPTICAL 0x07 /* Optical memory device */ +#define SCSIRESP_INQUIRYPD_MEDIUMCHANGER 0x08 /* Medium changer device (Jukebox) */ +#define SCSIRESP_INQUIRYPD_COMMUNICATIONS 0x09 /* Communications device (obsolete) */ +#define SCSIRESP_INQUIRYPD_STORAGEARRAY 0x0c /* Storage array controller device */ +#define SCSIRESP_INQUIRYPD_ENCLOSURESERVICES 0x0d /* Enclosure services device */ +#define SCSIRESP_INQUIRYPD_RBC 0x0e /* Simplified direct-access device */ +#define SCSIRESP_INQUIRYPD_OCRW 0x0f /* Optical reader/writer device */ +#define SCSIRESP_INQUIRYPD_BCC 0x10 /* Bridge controller commands */ +#define SCSIRESP_INQUIRYPD_OSD 0x11 /* Object-based storage device */ +#define SCSIRESP_INQUIRYPD_ADC 0x12 /* Automation/drive interface */ +#define SCSIRESP_INQUIRYPD_WKLU 0x1e /* Well-known logical unit */ +#define SCSIRESP_INQUIRYPD_UNKNOWN 0x1f /* Direct-access block device */ + +#define SCSIRESP_INQUIRYFLAGS1_RMB 0x80 /* Bit 7: RMB */ +#define SCSIRESP_INQUIRYFLAGS2_NORMACA 0x20 /* Bit 5: NormACA */ +#define SCSIRESP_INQUIRYFLAGS2_HISUP 0x10 /* Bit 4: HiSup */ +#define SCSIRESP_INQUIRYFLAGS2_FMTMASK 0x0f /* Bits 0-3: Response data format */ + +#define SCSIRESP_INQUIRYFLAGS3_SCCS 0x80 /* Bit 8: SCCS */ +#define SCSIRESP_INQUIRYFLAGS3_ACC 0x40 /* Bit 7: ACC */ +#define SCSIRESP_INQUIRYFLAGS3_TPGSMASK 0x30 /* Bits 4-5: TPGS */ +#define SCSIRESP_INQUIRYFLAGS3_3PC 0x08 /* Bit 3: 3PC */ +#define SCSIRESP_INQUIRYFLAGS3_PROTECT 0x01 /* Bit 0: Protect */ + +#define SCSIRESP_INQUIRYFLAGS4_BQUE 0x80 /* Bit 7: BQue */ +#define SCSIRESP_INQUIRYFLAGS4_ENCSERV 0x40 /* Bit 6: EncServ */ +#define SCSIRESP_INQUIRYFLAGS4_VS 0x20 /* Bit 5: VS */ +#define SCSIRESP_INQUIRYFLAGS4_MULTIP 0x10 /* Bit 4: MultIP */ +#define SCSIRESP_INQUIRYFLAGS4_MCHNGR 0x08 /* Bit 3: MChngr */ +#define SCSIRESP_INQUIRYFLAGS4_ADDR16 0x01 /* Bit 0: Addr16 */ + +#define SCSIRESP_INQUIRYFLAGS5_WBUS16 0x20 /* Bit 5: WBus16 */ +#define SCSIRESP_INQUIRYFLAGS5_SYNC 0x10 /* Bit 4: SYNC */ +#define SCSIRESP_INQUIRYFLAGS5_LINKED 0x08 /* Bit 3: LINKED */ +#define SCSIRESP_INQUIRYFLAGS5_CMDQUEUE 0x02 /* Bit 1: CmdQue */ +#define SCSIRESP_INQUIRYFLAGS5_VS 0x01 /* Bit 0: VS */ + +#define SCSIRESP_INQUIRYFLAGS6_CLOCKINGMASK 0xc0 /* Bits 2-3: Clocking */ +#define SCSIRESP_INQUIRYFLAGS6_QAS 0x02 /* Bit 1: QAS */ +#define SCSIRESP_INQUIRYFLAGS6_IUS 0x01 /* Bit 0: IUS */ + +/* Sense data */ + +/* Sense data response codes */ + +#define SCSIRESP_SENSEDATA_CURRENTFIXED 0x70 /* Byte 1 is always the response code */ +#define SCSIRESP_SENSEDATA_DEFERREDFIXED 0x71 +#define SCSIRESP_SENSEDATA_CURRENTDESC 0x72 +#define SCSIRESP_SENSEDATA_DEFERREDDESC 0x73 + +#define SCSIRESP_SENSEDATA_RESPVALID 0x80 + +/* Fixed sense data flags */ + +#define SCSIRESP_SENSEDATA_FILEMARK 0x80 /* Bit 7: FileMark */ +#define SCSIRESP_SENSEDATA_EOM 0x40 /* Bit 6: EOM */ +#define SCSIRESP_SENSEDATA_ILI 0x20 /* Bit 5: ILI */ +#define SCSIRESP_SENSEDATA_SENSEKEYMASK 0x0f /* Bits 0-3: Sense key */ +#define SCSIRESP_SENSEDATA_NOSENSE 0x00 /* Nothing to be reported */ +#define SCSIRESP_SENSEDATA_RECOVEREDERROR 0x01 /* Successful after recovery action */ +#define SCSIRESP_SENSEDATA_NOTREADY 0x02 /* Logical unit is not accessible */ +#define SCSIRESP_SENSEDATA_MEDIUMERROR 0x03 /* Error possibly caused by flaw in medium */ +#define SCSIRESP_SENSEDATA_HARDWAREERROR 0x04 /* Non-recoverable hardware error */ +#define SCSIRESP_SENSEDATA_ILLEGALREQUEST 0x05 /* Error in received request */ +#define SCSIRESP_SENSEDATA_UNITATTENTION 0x06 /* Unit attention condition */ +#define SCSIRESP_SENSEDATA_DATAPROTECT 0x07 /* Action failed, medium protected */ +#define SCSIRESP_SENSEDATA_BLANKCHECK 0x08 /* Encountered blank media */ +#define SCSIRESP_SENSEDATA_VENDORSPECIFIC 0x09 /* Vendor specific condition */ +#define SCSIRESP_SENSEDATA_ABORTEDCOMMAND 0x0b /* Command was aborted */ + +#define SCSIRESP_SENSEDATA_KEYVALID 0x80 /* Sense-specific data valid */ + +/* Mode Select 6 */ + +#define SCSICMD_MODESELECT6_PF 0x10 /* Bit 4: PF */ +#define SCSICMD_MODESELECT6_SP 0x01 /* Bit 0: SP */ + +/* Mode Sense 6 */ + +#define SCSICMD_MODESENSE6_DBD 0x08 /* Bit 3: PF */ + +#define SCSICMD_MODESENSE_PCMASK 0xc0 /* Bits 6-7: Page control (PC) */ +#define SCSICMD_MODESENSE_PCCURRENT 0x00 /* Current values */ +#define SCSICMD_MODESENSE_PCCHANGEABLE 0x40 /* Changeable values */ +#define SCSICMD_MODESENSE_PCDEFAULT 0x80 /* Default values */ +#define SCSICMD_MODESENSE_PCSAVED 0xc0 /* Saved values */ +#define SCSICMD_MODESENSE_PGCODEMASK 0x3f /* Bits 0-5: Page code */ + +#define SCSICMD_MODESENSE6_PCDEFAULT 0x80 /* Default values */ + /* Direct-access device page codes */ +#define SCSIRESP_MODESENSE_PGCCODE_VENDOR 0x00 /* Vendor-specific */ +#define SCSIRESP_MODESENSE_PGCCODE_RWERROR 0x01 /* Read/Write error recovery mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_RECONNECT 0x02 /* Disconnect-reconnect mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_FORMATDEV 0x03 /* Format device mode page (obsolete) */ +#define SCSIRESP_MODESENSE_PGCCODE_RIGID 0x04 /* Rigid disk geometry mode page (obsolete) */ +#define SCSIRESP_MODESENSE_PGCCODE_FLEXIBLE 0x05 /* Flexible disk geometry mode page (obsolete) */ +#define SCSIRESP_MODESENSE_PGCCODE_VERIFY 0x07 /* Verify error recovery mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_CACHING 0x08 /* Caching mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_CONTROL 0x0a /* Control mode page (0x0a/0x00) */ +#define SCSIRESP_MODESENSE_PGCCODE_CONTROLEXT 0x0a /* Control extension mode page (0x0a/0x01) */ +#define SCSIRESP_MODESENSE_PGCCODE_MEDIUMTYPES 0x0b /* Medum types supported mode page (obsolete) */ +#define SCSIRESP_MODESENSE_PGCCODE_NP 0x0c /* Notch and partition mode page (obsolete) */ +#define SCSIRESP_MODESENSE_PGCCODE_XOR 0x10 /* XOR control mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_ES 0x14 /* Enclosure services mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_PSLUN 0x18 /* Protocol-specific LUN mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_PSPORT 0x19 /* Protocol-specific port mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_POWER 0x1a /* Power condition mode page */ +#define SCSIRESP_MODESENSE_PGCCODE_IE 0x1c /* Informational exceptions control mode page (0x1c/0x00) */ +#define SCSIRESP_MODESENSE_PGCCODE_BC 0x1c /* Background control mode page (0x1c/0x01) */ +#define SCSIRESP_MODESENSE_PGCCODE_RETURNALL 0x3f /* Return all mode pages */ + /* Direct-access caching mode page */ +#define SCSIRESP_CACHINGMODEPG_PS 0x80 /* Byte 0, Bit 7: PS */ +#define SCSIRESP_CACHINGMODEPG_SPF 0x60 /* Byte 0, Bit 6: SPF */ +#define SCSIRESP_CACHINGMODEPG_IC 0x80 /* Byte 2, Bit 7: IC */ +#define SCSIRESP_CACHINGMODEPG_ABPF 0x40 /* Byte 2, Bit 6: ABPF */ +#define SCSIRESP_CACHINGMODEPG_CAP 0x20 /* Byte 2, Bit 5: CAP */ +#define SCSIRESP_CACHINGMODEPG_DISC 0x10 /* Byte 2, Bit 4: DISC */ +#define SCSIRESP_CACHINGMODEPG_SIZE 0x08 /* Byte 2, Bit 3: SIZE */ +#define SCSIRESP_CACHINGMODEPG_WCE 0x04 /* Byte 2, Bit 2: Write cache enable (WCE) */ +#define SCSIRESP_CACHINGMODEPG_MF 0x02 /* Byte 2, Bit 1: MF */ +#define SCSIRESP_CACHINGMODEPG_RCD 0x01 /* Byte 2, Bit 0: Read cache disable (RCD) */ + +#define SCSIRESP_MODEPARMHDR_DAPARM_WP 0x80 /* Bit 7: WP (Direct-access block devices only) */ +#define SCSIRESP_MODEPARMHDR_DAPARM_DBPFUA 0x10 /* Bit 4: DBOFUA (Direct-access block devices only) */ + +#define SCSIRESP_PAGEFMT_PS 0x80 /* Bit 7: PS */ +#define SCSIRESP_PAGEFMT_SPF 0x40 /* Bit 6: SPF */ +#define SCSIRESP_PAGEFMT_PGCODEMASK 0x3f /* Bits 0-5: Page code */ + +/* Prevent / Allow Medium Removal */ + +#define SCSICMD_PREVENTMEDIUMREMOVAL_TRANSPORT 0x01 /* Removal prohibited from data transport */ +#define SCSICMD_PREVENTMEDIUMREMOVAL_MCHANGER 0x02 /* Removal prohibited from medium changer */ + +/* Read format capacities */ + +#define SCIRESP_RDFMTCAPACITIES_UNFORMATED 0x01 /* Unformatted media */ +#define SCIRESP_RDFMTCAPACITIES_FORMATED 0x02 /* Formatted media */ +#define SCIRESP_RDFMTCAPACITIES_NOMEDIA 0x03 /* No media */ + +/* Read 6 */ + +#define SCSICMD_READ6_MSLBAMASK 0x1f + +/* Write 6 */ + +#define SCSICMD_WRITE6_MSLBAMASK 0x1f + +/* Mode Select 10 */ + +#define SCSICMD_MODESELECT10_PF 0x10 /* Bit 4: PF */ +#define SCSICMD_MODESELECT10_SP 0x01 /* Bit 0: SP */ + +/* Mode Sense 10 */ + +#define SCSICMD_MODESENSE10_LLBAA 0x10 /* Bit 4: LLBAA */ +#define SCSICMD_MODESENSE10_DBD 0x08 /* Bit 3: PF */ + +/* Read 10 */ + +#define SCSICMD_READ10FLAGS_RDPROTECTMASK 0xe0 +#define SCSICMD_READ10FLAGS_DPO 0x10 /* Disable Page Out */ +#define SCSICMD_READ10FLAGS_FUA 0x08 +#define SCSICMD_READ10FLAGS_FUANV 0x02 + +/* Write 10 */ + +#define SCSICMD_WRITE10FLAGS_WRPROTECTMASK 0xe0 +#define SCSICMD_WRITE10FLAGS_DPO 0x10 /* Disable Page Out */ +#define SCSICMD_WRITE10FLAGS_FUA 0x08 +#define SCSICMD_WRITE10FLAGS_FUANV 0x02 + +/* Verify 10 */ + +#define SCSICMD_VERIFY10_VRPROTECTMASK 0xe0 /* Byte 1: Bits 5-7: VRPROTECT */ +#define SCSICMD_VERIFY10_DPO 0x10 /* Byte 1: Bit 4: Disable Page Out (DPO) */ +#define SCSICMD_VERIFY10_BYTCHK 0x02 /* Byte 1: Bit 2: BytChk */ + +/* Read 12 */ + +#define SCSICMD_READ12FLAGS_RDPROTECTMASK 0xe0 +#define SCSICMD_READ12FLAGS_DPO 0x10 /* Disable Page Out */ +#define SCSICMD_READ12FLAGS_FUA 0x08 +#define SCSICMD_READ12FLAGS_FUANV 0x02 + +/* Write 12 */ + +#define SCSICMD_WRITE12FLAGS_WRPROTECTMASK 0xe0 +#define SCSICMD_WRITE12FLAGS_DPO 0x10 /* Disable Page Out */ +#define SCSICMD_WRITE12FLAGS_FUA 0x08 +#define SCSICMD_WRITE12FLAGS_FUANV 0x02 + +/* Verify 12 */ + +#define SCSICMD_VERIFY12_VRPROTECTMASK 0xe0 /* Byte 1: Bits 5-7: VRPROTECT */ +#define SCSICMD_VERIFY12_DPO 0x10 /* Byte 1: Bit 4: Disable Page Out (DPO) */ +#define SCSICMD_VERIFY12_BYTCHK 0x02 /* Byte 1: Bit 2: BytChk */ + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Format structures for selected SCSI primary commands */ + +#define SCSICMD_TESTUNITREADY_SIZEOF 6 + +struct scsicmd_requestsense_s +{ + uint8_t opcode; /* 0: 0x03 */ + uint8_t flags; /* 1: See SCSICMD_REQUESTSENSE_FLAGS_* */ + uint8_t reserved[2]; /* 2-3: Reserved */ + uint8_t alloclen; /* 4: Allocation length */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_REQUESTSENSE_SIZEOF 6 +#define SCSICMD_REQUESTSENSE_MSSIZEOF 12 /* MS-Windows REQUEST SENSE with cbw->cdblen == 12 */ + +struct scsiresp_fixedsensedata_s +{ + uint8_t code; /* 0: Response code See SCSIRESP_SENSEDATA_*FIXED defns */ + uint8_t obsolete; /* 1: */ + uint8_t flags; /* 2: See SCSIRESP_SENSEDATA_* definitions */ + uint8_t info[4]; /* 3-6: Information */ + uint8_t len; /* 7: Additional length */ + uint8_t cmdinfo[4]; /* 8-11: Command-specific information */ + uint8_t code2; /* 12: Additional sense code */ + uint8_t qual2; /* 13: Additional sense code qualifier */ + uint8_t fru; /* 14: Field replacement unit code */ + uint8_t key[3]; /* 15-17: Sense key specific */ + /* 18-: Additional bytes may follow */ +}; +#define SCSIRESP_FIXEDSENSEDATA_SIZEOF 18 /* Minimum size */ + +struct scscicmd_inquiry_s +{ + uint8_t opcode; /* 0: 0x12 */ + uint8_t flags; /* 1: See SCSICMD_INQUIRY_FLAGS_* */ + uint8_t pagecode; /* 2: Page code */ + uint8_t alloclen[2]; /* 3-4: Allocation length */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_INQUIRY_SIZEOF 6 + +struct scsiresp_inquiry_s +{ + /* Mandatory */ + + uint8_t qualtype; /* 0: Bits 5-7: Peripheral qualifier; Bits 0-4: Peripheral device type */ + uint8_t flags1; /* 1: See SCSIRESP_INQUIRY_FLAGS1_* */ + uint8_t version; /* 2: Version */ + uint8_t flags2; /* 3: See SCSIRESP_INQUIRY_FLAGS2_* */ + uint8_t len; /* 4: Additional length */ + uint8_t flags3; /* 5: See SCSIRESP_INQUIRY_FLAGS3_* */ + uint8_t flags4; /* 6: See SCSIRESP_INQUIRY_FLAGS4_* */ + uint8_t flags5; /* 7: See SCSIRESP_INQUIRY_FLAGS5_* */ + uint8_t vendorid[8]; /* 8-15: T10 Vendor Identification */ + uint8_t productid[16]; /* 16-31: Product Identification */ + uint8_t revision[4]; /* 32-35: Product Revision Level */ + + /* Optional */ + + uint8_t vendor[20]; /* 36-55: Vendor specific */ + uint8_t flags6; /* 56: See SCSIRESP_INQUIRY_FLAGS6_* */ + uint8_t reserved1; /* 57: Reserved */ + uint8_t version1[2]; /* 58-59: Version Descriptor 1 */ + uint8_t version2[2]; /* 60-61: Version Descriptor 2 */ + uint8_t version3[2]; /* 62-63: Version Descriptor 3 */ + uint8_t version4[2]; /* 64-65: Version Descriptor 4 */ + uint8_t version5[2]; /* 66-67: Version Descriptor 5 */ + uint8_t version6[2]; /* 68-69: Version Descriptor 6 */ + uint8_t version7[2]; /* 70-71: Version Descriptor 7 */ + uint8_t version8[2]; /* 72-73: Version Descriptor 8 */ + uint8_t reserved2[22]; /* 74-95: Reserved */ + /* 96-: Vendor-specific parameters may follow */ +}; +#define SCSIRESP_INQUIRY_SIZEOF 36 /* Minimum size */ + +struct scsicmd_modeselect6_s +{ + uint8_t opcode; /* 0x15 */ + uint8_t flags; /* 1: See SCSICMD_MODESELECT6_FLAGS_* */ + uint8_t reserved[2]; /* 2-3: Reserved */ + uint8_t plen; /* 4: Parameter list length */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_MODESELECT6_SIZEOF 6 + +struct scsicmd_modesense6_s +{ + uint8_t opcode; /* 0x1a */ + uint8_t flags; /* 1: See SCSICMD_MODESENSE6_FLAGS_* */ + uint8_t pcpgcode; /* 2: Bits 6-7: PC, bits 0-5: page code */ + uint8_t subpgcode; /* 3: subpage code */ + uint8_t alloclen; /* 4: Allocation length */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_MODESENSE6_SIZEOF 6 + +struct scsiresp_modeparameterhdr6_s +{ + uint8_t mdlen; /* 0: Mode data length */ + uint8_t type; /* 1: Medium type */ + uint8_t param; /* 2: Device-specific parameter */ + uint8_t bdlen; /* 3: Block descriptor length */ +}; +#define SCSIRESP_MODEPARAMETERHDR6_SIZEOF 4 + +struct scsiresp_blockdesc_s +{ + uint8_t density; /* 0: density code */ + uint8_t nblocks[3]; /* 1-3: Number of blocks */ + uint8_t reserved; /* 4: reserved */ + uint8_t blklen[3]; /* 5-7: Block len */ +}; +#define SCSIRESP_BLOCKDESC_SIZEOF 8 + +struct scsiresp_pageformat_s +{ + uint8_t pgcode; /* 0: See SCSIRESP_PAGEFMT_* definitions */ + uint8_t pglen; /* 1: Page length (n-1) */ + uint8_t parms[1]; /* 2-n: Mode parameters */ +}; + +struct scsiresp_subpageformat_s +{ + uint8_t pgcode; /* 0: See SCSIRESP_PAGEFMT_* definitions */ + uint8_t subpgcode; /* 1: sub-page code */ + uint8_t pglen[2]; /* 2-3: Page length (n-3) */ + uint8_t parms[1]; /* 4-n: Mode parameters */ +}; + +struct scsiresp_cachingmodepage_s +{ + uint8_t pgcode; /* 0: Bit 7: PS; Bit 6: SPF, Bits 0-5: page code == 8 */ + uint8_t len; /* 1: Page length (18) */ + uint8_t flags1; /* 2: See SCSIRESP_CACHINGMODEPG_* definitions */ + uint8_t priority; /* 3: Bits 4-7: Demand read retention priority; Bits 0-3: Write retention priority */ + uint8_t dpflen[2]; /* 4-5: Disable prefetch transfer length */ + uint8_t minpf[2]; /* 6-7: Minimum pre-fetch */ + uint8_t maxpf[2]; /* 8-9: Maximum pre-fetch */ + uint8_t maxpfc[2]; /* 10-11: Maximum pref-fetch ceiling */ + uint8_t flags2; /* 12: See SCSIRESP_CACHINGMODEPG_* definitions */ + uint8_t nsegments; /* 13: Number of cache segments */ + uint8_t segsize[2]; /* 14-15: Cache segment size */ + uint8_t reserved; /* 16: Reserved */ + uint8_t obsolete[3]; /* 17-19: Obsolete */ +}; + +/* Format structures for selected SCSI block commands */ + +struct scsicmd_read6_s +{ + uint8_t opcode; /* 0: 0x08 */ + uint8_t mslba; /* 1: Bits 5-7: reserved; Bits 0-6: MS Logical Block Address (LBA) */ + uint8_t lslba[2]; /* 2-3: LS Logical Block Address (LBA) */ + uint8_t xfrlen; /* 4: Transfer length (in contiguous logical blocks) */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_READ6_SIZEOF 6 + +struct scsicmd_write6_s +{ + uint8_t opcode; /* 0: 0x0a */ + uint8_t mslba; /* 1: Bits 5-7: reserved; Bits 0-6: MS Logical Block Address (LBA) */ + uint8_t lslba[2]; /* 2-3: LS Logical Block Address (LBA) */ + uint8_t xfrlen; /* 4: Transfer length (in contiguous logical blocks) */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_WRITE6_SIZEOF 6 + +struct scsicmd_startstopunit_s +{ + uint8_t opcode; /* 0: 0x1b */ + uint8_t immed; /* 1: Bits 2-7: Reserved, Bit 0: Immed */ + uint8_t reserved; /* 2: reserved */ + uint8_t pcm; /* 3: Bits 4-7: Reserved, Bits 0-3: Power condition modifier */ + uint8_t pc; /* 4: Bits 4-7: Power condition, Bit 2: NO_FLUSH, Bit 1: LOEJ, Bit 0: START */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_STARTSTOPUNIT_SIZEOF 6 + +struct scsicmd_preventmediumremoval_s +{ + uint8_t opcode; /* 0: 0x1e */ + uint8_t reserved[3]; /* 1-3: Reserved */ + uint8_t prevent; /* 4: Bits 2-7: Reserved, Bits 0:1: prevent */ + uint8_t control; /* 5: Control */ +}; +#define SCSICMD_PREVENTMEDIUMREMOVAL_SIZEOF 6 + +struct scsicmd_readformatcapcacities_s +{ + uint8_t opcode; /* 0: 0x23 */ + uint8_t reserved[6]; /* 1-6: Reserved */ + uint8_t alloclen[2]; /* 7-8: Allocation length */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_READFORMATCAPACITIES_SIZEOF 10 + +struct scsiresp_readformatcapacities_s +{ + /* Current capacity header */ + + uint8_t reserved[3]; /* 0-2: Reserved */ + uint8_t listlen; /* 3: Capacity list length */ + + /* Current/Maximum Capacity Descriptor (actually a separate structure) */ + + uint8_t nblocks[4]; /* 4-7: Number of blocks */ + uint8_t type; /* 8: Bits 2-7: Reserved, Bits 0-1: Descriptor type */ + uint8_t blocklen[3]; /* 9-11: Block length */ +}; +#define SCSIRESP_READFORMATCAPACITIES_SIZEOF 12 +#define SCSIRESP_CURRCAPACITYDESC_SIZEOF 8 + +struct scsiresp_formattedcapacitydesc_s +{ + uint8_t nblocks[4]; /* 0-3: Number of blocks */ + uint8_t type; /* 4: Bits 2-7: Type, bits 0-1, reserved */ + uint8_t param[3]; /* 5-7: Type dependent parameter */ +}; +#define SCSIRESP_FORMATTEDCAPACITYDESC_SIZEOF 8 + +struct scsicmd_readcapacity10_s +{ + uint8_t opcode; /* 0: 0x25 */ + uint8_t reserved1; /* 1: Bits 1-7: Reserved, Bit 0: Obsolete */ + uint8_t lba[4]; /* 2-5: Logical block address (LBA) */ + uint8_t reserved2[2]; /* 6-7: Reserved */ + uint8_t pmi; /* 8: Bits 1-7 Reserved; Bit 0: PMI */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_READCAPACITY10_SIZEOF 10 + +struct scsiresp_readcapacity10_s +{ + uint8_t lba[4]; /* 0-3: Returned logical block address (LBA) */ + uint8_t blklen[4]; /* 4-7: Logical block length (in bytes) */ +}; +#define SCSIRESP_READCAPACITY10_SIZEOF 8 + +struct scsicmd_read10_s +{ + uint8_t opcode; /* 0: 0x28 */ + uint8_t flags; /* 1: See SCSICMD_READ10FLAGS_* */ + uint8_t lba[4]; /* 2-5: Logical Block Address (LBA) */ + uint8_t groupno; /* 6: Bits 5-7: reserved; Bits 0-6: group number */ + uint8_t xfrlen[2]; /* 7-8: Transfer length (in contiguous logical blocks) */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_READ10_SIZEOF 10 + +struct scsicmd_write10_s +{ + uint8_t opcode; /* 0: 0x2a */ + uint8_t flags; /* 1: See SCSICMD_WRITE10FLAGS_* */ + uint8_t lba[4]; /* 2-5: Logical Block Address (LBA) */ + uint8_t groupno; /* 6: Bits 5-7: reserved; Bits 0-6: group number */ + uint8_t xfrlen[2]; /* 7-8: Transfer length (in contiguous logical blocks) */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_WRITE10_SIZEOF 10 + +struct scsicmd_verify10_s +{ + uint8_t opcode; /* 0: 0x2f */ + uint8_t flags; /* 1: See SCSICMD_VERIFY10_* definitions */ + uint8_t lba[4]; /* 2-5: Logical block address (LBA) */ + uint8_t groupno; /* 6: Bit 7: restricted; Bits 5-6: Reserved, Bits 0-4: Group number */ + uint8_t len[2]; /* 7-8: Verification length (in blocks) */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_VERIFY10_SIZEOF 10 + +struct scsicmd_synchronizecache10_s +{ + uint8_t opcode; /* 0: 0x35 */ + uint8_t flags; /* 1: See SCSICMD_SYNCHRONIZECACHE10_* definitions */ + uint8_t lba[4]; /* 2-5: Logical block address (LBA) */ + uint8_t groupno; /* 6: Bit 7: restricted; Bits 5-6: Reserved, Bits 0-4: Group number */ + uint8_t len[2]; /* 7-8: Number of logical blocks */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_SYNCHRONIZECACHE10_SIZEOF 10 + +struct scsicmd_modeselect10_s +{ + uint8_t opcode; /* 0: 0x55 */ + uint8_t flags; /* 1: See SCSICMD_MODESELECT10_FLAGS_* */ + uint8_t reserved[5]; /* 2-6: Reserved */ + uint8_t parmlen[2]; /* 7-8: Parameter list length */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_MODESELECT10_SIZEOF 10 + +struct scsiresp_modeparameterhdr10_s +{ + uint8_t mdlen[2]; /* 0-1: Mode data length */ + uint8_t type; /* 2: Medium type */ + uint8_t param; /* 3: Device-specific parameter */ + uint8_t reserved[2]; /* 4-5: reserved */ + uint8_t bdlen[2]; /* 6-7: Block descriptor length */ +}; +#define SCSIRESP_MODEPARAMETERHDR10_SIZEOF 8 + +struct scsicmd_modesense10_s +{ + uint8_t opcode; /* O: 0x5a */ + uint8_t flags; /* 1: See SCSICMD_MODESENSE10_FLAGS_* */ + uint8_t pcpgcode; /* 2: Bits 6-7: PC, bits 0-5: page code */ + uint8_t subpgcode; /* 3: subpage code */ + uint8_t reserved[3]; /* 4-6: reserved */ + uint8_t alloclen[2]; /* 7-8: Allocation length */ + uint8_t control; /* 9: Control */ +}; +#define SCSICMD_MODESENSE10_SIZEOF 10 + +struct scsicmd_readcapacity16_s +{ + uint8_t opcode; /* 0: 0x9e */ + uint8_t action; /* 1: Bits 5-7: Reserved, Bits 0-4: Service action */ + uint8_t lba[8]; /* 2-9: Logical block address (LBA) */ + uint8_t len[4]; /* 10-13: Allocation length */ + uint8_t reserved; /* 14: Reserved */ + uint8_t control; /* 15: Control */ +}; +#define SCSICMD_READCAPACITY16_SIZEOF 16 + +struct scsicmd_read12_s +{ + uint8_t opcode; /* 0: 0xa8 */ + uint8_t flags; /* 1: See SCSICMD_READ12FLAGS_* */ + uint8_t lba[4]; /* 2-5: Logical Block Address (LBA) */ + uint8_t xfrlen[4]; /* 6-9: Transfer length (in contiguous logical blocks) */ + uint8_t groupno; /* 10: Bit 7: restricted; Bits 5-6: reserved; Bits 0-6: group number */ + uint8_t control; /* 11: Control */ +}; +#define SCSICMD_READ12_SIZEOF 12 + +struct scsicmd_write12_s +{ + uint8_t opcode; /* 0: 0xaa */ + uint8_t flags; /* 1: See SCSICMD_WRITE12FLAGS_* */ + uint8_t lba[4]; /* 2-5: Logical Block Address (LBA) */ + uint8_t xfrlen[4]; /* 6-9: Transfer length (in contiguous logical blocks) */ + uint8_t groupno; /* 10: Bit 7: restricted; Bits 5-6: reserved; Bits 0-6: group number */ + uint8_t control; /* 11: Control */ +}; +#define SCSICMD_WRITE12_SIZEOF 12 + +struct scsicmd_verify12_s +{ + uint8_t opcode; /* 0: 0xaf */ + uint8_t flags; /* 1: See SCSICMD_VERIFY12_* definitions */ + uint8_t lba[4]; /* 2-5: Logical block address (LBA) */ + uint8_t len[4]; /* 6-9: Verification length */ + uint8_t groupno; /* 10: Bit 7: restricted; Bits 5-6: Reserved, Bits 0-4: Group number */ + uint8_t control; /* 11: Control */ +}; +#define SCSICMD_VERIFY12_SIZEOF 12 + +/**************************************************************************** + * Public Functions Definitions + ****************************************************************************/ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __INCLUDE_NUTTX_SCSI_H */ diff --git a/components/drivers/usb/cherryusb/class/msc/usbd_msc.c b/components/drivers/usb/cherryusb/class/msc/usbd_msc.c new file mode 100644 index 00000000000..055cdc4e65c --- /dev/null +++ b/components/drivers/usb/cherryusb/class/msc/usbd_msc.c @@ -0,0 +1,938 @@ +/* + * Copyright (c) 2022, sakumisu + * Copyright (c) 2024, zhihong chen + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_msc.h" +#include "usb_scsi.h" +#if defined(CONFIG_USBDEV_MSC_THREAD) +#include "usb_osal.h" +#endif + +#define MSD_OUT_EP_IDX 0 +#define MSD_IN_EP_IDX 1 + +/* Describe EndPoints configuration */ +static struct usbd_endpoint mass_ep_data[CONFIG_USBDEV_MAX_BUS][2]; + +/* MSC Bulk-only Stage */ +enum Stage { + MSC_READ_CBW = 0, /* Command Block Wrapper */ + MSC_DATA_OUT = 1, /* Data Out Phase */ + MSC_DATA_IN = 2, /* Data In Phase */ + MSC_SEND_CSW = 3, /* Command Status Wrapper */ + MSC_WAIT_CSW = 4, /* Command Status Wrapper */ +}; + +/* Device data structure */ +USB_NOCACHE_RAM_SECTION struct usbd_msc_priv { + /* state of the bulk-only state machine */ + enum Stage stage; + USB_MEM_ALIGNX struct CBW cbw; + USB_MEM_ALIGNX struct CSW csw; + + bool readonly; + bool popup; + uint8_t sKey; /* Sense key */ + uint8_t ASC; /* Additional Sense Code */ + uint8_t ASQ; /* Additional Sense Qualifier */ + uint8_t max_lun; + uint32_t start_sector; + uint32_t nsectors; + uint32_t scsi_blk_size[CONFIG_USBDEV_MSC_MAX_LUN]; + uint32_t scsi_blk_nbr[CONFIG_USBDEV_MSC_MAX_LUN]; + + USB_MEM_ALIGNX uint8_t block_buffer[CONFIG_USBDEV_MSC_MAX_BUFSIZE]; + +#if defined(CONFIG_USBDEV_MSC_THREAD) + usb_osal_mq_t usbd_msc_mq; + usb_osal_thread_t usbd_msc_thread; + uint32_t nbytes; +#endif +} g_usbd_msc[CONFIG_USBDEV_MAX_BUS]; + +#ifdef CONFIG_USBDEV_MSC_THREAD +static void usbdev_msc_thread(void *argument); +#endif + +static void usdb_msc_set_max_lun(uint8_t busid) +{ + g_usbd_msc[busid].max_lun = CONFIG_USBDEV_MSC_MAX_LUN - 1u; +} + +static void usbd_msc_reset(uint8_t busid) +{ + g_usbd_msc[busid].stage = MSC_READ_CBW; + g_usbd_msc[busid].readonly = false; +} + +static int msc_storage_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("MSC Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + switch (setup->bRequest) { + case MSC_REQUEST_RESET: + usbd_msc_reset(busid); + break; + + case MSC_REQUEST_GET_MAX_LUN: + (*data)[0] = g_usbd_msc[busid].max_lun; + *len = 1; + break; + + default: + USB_LOG_WRN("Unhandled MSC Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +void msc_storage_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_INIT: +#ifdef CONFIG_USBDEV_MSC_THREAD + g_usbd_msc[busid].usbd_msc_mq = usb_osal_mq_create(1); + if (g_usbd_msc[busid].usbd_msc_mq == NULL) { + USB_LOG_ERR("No memory to alloc for g_usbd_msc[busid].usbd_msc_mq\r\n"); + } + g_usbd_msc[busid].usbd_msc_thread = usb_osal_thread_create("usbd_msc", CONFIG_USBDEV_MSC_STACKSIZE, CONFIG_USBDEV_MSC_PRIO, usbdev_msc_thread, (void *)busid); + if (g_usbd_msc[busid].usbd_msc_thread == NULL) { + USB_LOG_ERR("No memory to alloc for g_usbd_msc[busid].usbd_msc_thread\r\n"); + } +#endif + break; + case USBD_EVENT_DEINIT: +#ifdef CONFIG_USBDEV_MSC_THREAD + if (g_usbd_msc[busid].usbd_msc_mq) { + usb_osal_mq_delete(g_usbd_msc[busid].usbd_msc_mq); + } + if (g_usbd_msc[busid].usbd_msc_thread) { + usb_osal_thread_delete(g_usbd_msc[busid].usbd_msc_thread); + } +#endif + break; + case USBD_EVENT_RESET: + usbd_msc_reset(busid); + break; + case USBD_EVENT_CONFIGURED: + USB_LOG_DBG("Start reading cbw\r\n"); + usbd_ep_start_read(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr, (uint8_t *)&g_usbd_msc[busid].cbw, USB_SIZEOF_MSC_CBW); + break; + + default: + break; + } +} + +static void usbd_msc_bot_abort(uint8_t busid) +{ + if ((g_usbd_msc[busid].cbw.bmFlags == 0) && (g_usbd_msc[busid].cbw.dDataLength != 0)) { + usbd_ep_set_stall(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr); + } + usbd_ep_set_stall(busid, mass_ep_data[busid][MSD_IN_EP_IDX].ep_addr); + usbd_ep_start_read(busid, mass_ep_data[busid][0].ep_addr, (uint8_t *)&g_usbd_msc[busid].cbw, USB_SIZEOF_MSC_CBW); +} + +static void usbd_msc_send_csw(uint8_t busid, uint8_t CSW_Status) +{ + g_usbd_msc[busid].csw.dSignature = MSC_CSW_Signature; + g_usbd_msc[busid].csw.bStatus = CSW_Status; + + /* updating the State Machine , so that we wait CSW when this + * transfer is complete, ie when we get a bulk in callback + */ + g_usbd_msc[busid].stage = MSC_WAIT_CSW; + + USB_LOG_DBG("Send csw\r\n"); + usbd_ep_start_write(busid, mass_ep_data[busid][MSD_IN_EP_IDX].ep_addr, (uint8_t *)&g_usbd_msc[busid].csw, sizeof(struct CSW)); +} + +static void usbd_msc_send_info(uint8_t busid, uint8_t *buffer, uint8_t size) +{ + size = MIN(size, g_usbd_msc[busid].cbw.dDataLength); + + /* updating the State Machine , so that we send CSW when this + * transfer is complete, ie when we get a bulk in callback + */ + g_usbd_msc[busid].stage = MSC_SEND_CSW; + + usbd_ep_start_write(busid, mass_ep_data[busid][MSD_IN_EP_IDX].ep_addr, buffer, size); + + g_usbd_msc[busid].csw.dDataResidue -= size; + g_usbd_msc[busid].csw.bStatus = CSW_STATUS_CMD_PASSED; +} + +static bool SCSI_processWrite(uint8_t busid, uint32_t nbytes); +static bool SCSI_processRead(uint8_t busid); + +/** +* @brief SCSI_SetSenseData +* Load the last error code in the error list +* @param sKey: Sense Key +* @param ASC: Additional Sense Code +* @retval none + +*/ +static void SCSI_SetSenseData(uint8_t busid, uint32_t KCQ) +{ + g_usbd_msc[busid].sKey = (uint8_t)(KCQ >> 16); + g_usbd_msc[busid].ASC = (uint8_t)(KCQ >> 8); + g_usbd_msc[busid].ASQ = (uint8_t)(KCQ); +} + +/** + * @brief SCSI Command list + * + */ + +static bool SCSI_testUnitReady(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (g_usbd_msc[busid].cbw.dDataLength != 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + *data = NULL; + *len = 0; + return true; +} + +static bool SCSI_requestSense(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint8_t data_len = SCSIRESP_FIXEDSENSEDATA_SIZEOF; + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + if (g_usbd_msc[busid].cbw.CB[4] < SCSIRESP_FIXEDSENSEDATA_SIZEOF) { + data_len = g_usbd_msc[busid].cbw.CB[4]; + } + + uint8_t request_sense[SCSIRESP_FIXEDSENSEDATA_SIZEOF] = { + 0x70, + 0x00, + 0x00, /* Sense Key */ + 0x00, + 0x00, + 0x00, + 0x00, + SCSIRESP_FIXEDSENSEDATA_SIZEOF - 8, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, /* Additional Sense Code */ + 0x00, /* Additional Sense Request */ + 0x00, + 0x00, + 0x00, + 0x00, + }; + + request_sense[2] = g_usbd_msc[busid].sKey; + request_sense[12] = g_usbd_msc[busid].ASC; + request_sense[13] = g_usbd_msc[busid].ASQ; +#if 0 + request_sense[ 2] = 0x06; /* UNIT ATTENTION */ + request_sense[12] = 0x28; /* Additional Sense Code: Not ready to ready transition */ + request_sense[13] = 0x00; /* Additional Sense Code Qualifier */ +#endif +#if 0 + request_sense[ 2] = 0x02; /* NOT READY */ + request_sense[12] = 0x3A; /* Additional Sense Code: Medium not present */ + request_sense[13] = 0x00; /* Additional Sense Code Qualifier */ +#endif +#if 0 + request_sense[ 2] = 0x05; /* ILLEGAL REQUEST */ + request_sense[12] = 0x20; /* Additional Sense Code: Invalid command */ + request_sense[13] = 0x00; /* Additional Sense Code Qualifier */ +#endif +#if 0 + request_sense[ 2] = 0x00; /* NO SENSE */ + request_sense[12] = 0x00; /* Additional Sense Code: No additional code */ + request_sense[13] = 0x00; /* Additional Sense Code Qualifier */ +#endif + + memcpy(*data, (uint8_t *)request_sense, data_len); + *len = data_len; + return true; +} + +static bool SCSI_inquiry(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint8_t data_len = SCSIRESP_INQUIRY_SIZEOF; + + uint8_t inquiry00[6] = { + 0x00, + 0x00, + 0x00, + (0x06 - 4U), + 0x00, + 0x80 + }; + + /* USB Mass storage VPD Page 0x80 Inquiry Data for Unit Serial Number */ + uint8_t inquiry80[8] = { + 0x00, + 0x80, + 0x00, + 0x08, + 0x20, /* Put Product Serial number */ + 0x20, + 0x20, + 0x20 + }; + + uint8_t inquiry[SCSIRESP_INQUIRY_SIZEOF] = { + /* 36 */ + + /* LUN 0 */ + 0x00, + 0x80, + 0x02, + 0x02, + (SCSIRESP_INQUIRY_SIZEOF - 5), + 0x00, + 0x00, + 0x00, + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', /* Manufacturer : 8 bytes */ + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', /* Product : 16 Bytes */ + ' ', ' ', ' ', ' ', ' ', ' ', ' ', ' ', + ' ', ' ', ' ', ' ' /* Version : 4 Bytes */ + }; + + memcpy(&inquiry[8], CONFIG_USBDEV_MSC_MANUFACTURER_STRING, strlen(CONFIG_USBDEV_MSC_MANUFACTURER_STRING)); + memcpy(&inquiry[16], CONFIG_USBDEV_MSC_PRODUCT_STRING, strlen(CONFIG_USBDEV_MSC_PRODUCT_STRING)); + memcpy(&inquiry[32], CONFIG_USBDEV_MSC_VERSION_STRING, strlen(CONFIG_USBDEV_MSC_VERSION_STRING)); + + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + if ((g_usbd_msc[busid].cbw.CB[1] & 0x01U) != 0U) { /* Evpd is set */ + if (g_usbd_msc[busid].cbw.CB[2] == 0U) { /* Request for Supported Vital Product Data Pages*/ + data_len = 0x06; + memcpy(*data, (uint8_t *)inquiry00, data_len); + } else if (g_usbd_msc[busid].cbw.CB[2] == 0x80U) { /* Request for VPD page 0x80 Unit Serial Number */ + data_len = 0x08; + memcpy(*data, (uint8_t *)inquiry80, data_len); + } else { /* Request Not supported */ + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDFIELDINCBA); + return false; + } + } else { + if (g_usbd_msc[busid].cbw.CB[4] < SCSIRESP_INQUIRY_SIZEOF) { + data_len = g_usbd_msc[busid].cbw.CB[4]; + } + memcpy(*data, (uint8_t *)inquiry, data_len); + } + + *len = data_len; + return true; +} + +static bool SCSI_startStopUnit(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (g_usbd_msc[busid].cbw.dDataLength != 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + if ((g_usbd_msc[busid].cbw.CB[4] & 0x3U) == 0x1U) /* START=1 */ + { + //SCSI_MEDIUM_UNLOCKED; + } else if ((g_usbd_msc[busid].cbw.CB[4] & 0x3U) == 0x2U) /* START=0 and LOEJ Load Eject=1 */ + { + //SCSI_MEDIUM_EJECTED; + g_usbd_msc[busid].popup = true; + } else if ((g_usbd_msc[busid].cbw.CB[4] & 0x3U) == 0x3U) /* START=1 and LOEJ Load Eject=1 */ + { + //SCSI_MEDIUM_UNLOCKED; + } else { + } + + *data = NULL; + *len = 0; + return true; +} + +static bool SCSI_preventAllowMediaRemoval(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (g_usbd_msc[busid].cbw.dDataLength != 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + if (g_usbd_msc[busid].cbw.CB[4] == 0U) { + //SCSI_MEDIUM_UNLOCKED; + } else { + //SCSI_MEDIUM_LOCKED; + } + *data = NULL; + *len = 0; + return true; +} + +static bool SCSI_modeSense6(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint8_t data_len = 4; + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + if (g_usbd_msc[busid].cbw.CB[4] < SCSIRESP_MODEPARAMETERHDR6_SIZEOF) { + data_len = g_usbd_msc[busid].cbw.CB[4]; + } + + uint8_t sense6[SCSIRESP_MODEPARAMETERHDR6_SIZEOF] = { 0x03, 0x00, 0x00, 0x00 }; + + if (g_usbd_msc[busid].readonly) { + sense6[2] = 0x80; + } + memcpy(*data, (uint8_t *)sense6, data_len); + *len = data_len; + return true; +} + +static bool SCSI_modeSense10(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint8_t data_len = 27; + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + if (g_usbd_msc[busid].cbw.CB[8] < 27) { + data_len = g_usbd_msc[busid].cbw.CB[8]; + } + + uint8_t sense10[27] = { + 0x00, + 0x26, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x08, + 0x12, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00 + }; + + memcpy(*data, (uint8_t *)sense10, data_len); + *len = data_len; + return true; +} + +static bool SCSI_readFormatCapacity(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + uint8_t format_capacity[SCSIRESP_READFORMATCAPACITIES_SIZEOF] = { + 0x00, + 0x00, + 0x00, + 0x08, /* Capacity List Length */ + (uint8_t)((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] >> 24) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] >> 16) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] >> 8) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] >> 0) & 0xff), + + 0x02, /* Descriptor Code: Formatted Media */ + 0x00, + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 8) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 0) & 0xff), + }; + + memcpy(*data, (uint8_t *)format_capacity, SCSIRESP_READFORMATCAPACITIES_SIZEOF); + *len = SCSIRESP_READFORMATCAPACITIES_SIZEOF; + return true; +} + +static bool SCSI_readCapacity10(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (g_usbd_msc[busid].cbw.dDataLength == 0U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + uint8_t capacity10[SCSIRESP_READCAPACITY10_SIZEOF] = { + (uint8_t)(((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] - 1) >> 24) & 0xff), + (uint8_t)(((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] - 1) >> 16) & 0xff), + (uint8_t)(((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] - 1) >> 8) & 0xff), + (uint8_t)(((g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN] - 1) >> 0) & 0xff), + + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 24) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 16) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 8) & 0xff), + (uint8_t)((g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN] >> 0) & 0xff), + }; + + memcpy(*data, (uint8_t *)capacity10, SCSIRESP_READCAPACITY10_SIZEOF); + *len = SCSIRESP_READCAPACITY10_SIZEOF; + return true; +} + +static bool SCSI_read10(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x80U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + g_usbd_msc[busid].start_sector = GET_BE32(&g_usbd_msc[busid].cbw.CB[2]); /* Logical Block Address of First Block */ + USB_LOG_DBG("lba: 0x%04x\r\n", g_usbd_msc[busid].start_sector); + + g_usbd_msc[busid].nsectors = GET_BE16(&g_usbd_msc[busid].cbw.CB[7]); /* Number of Blocks to transfer */ + USB_LOG_DBG("nsectors: 0x%02x\r\n", g_usbd_msc[busid].nsectors); + + if ((g_usbd_msc[busid].start_sector + g_usbd_msc[busid].nsectors) > g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN]) { + SCSI_SetSenseData(busid, SCSI_KCQIR_LBAOUTOFRANGE); + USB_LOG_ERR("LBA out of range\r\n"); + return false; + } + + if (g_usbd_msc[busid].cbw.dDataLength != (g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN])) { + USB_LOG_ERR("scsi_blk_len does not match with dDataLength\r\n"); + return false; + } + g_usbd_msc[busid].stage = MSC_DATA_IN; +#ifdef CONFIG_USBDEV_MSC_THREAD + usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_IN); + return true; +#else + return SCSI_processRead(busid); +#endif +} + +static bool SCSI_read12(uint8_t busid, uint8_t **data, uint32_t *len) +{ + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x80U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + g_usbd_msc[busid].start_sector = GET_BE32(&g_usbd_msc[busid].cbw.CB[2]); /* Logical Block Address of First Block */ + USB_LOG_DBG("lba: 0x%04x\r\n", g_usbd_msc[busid].start_sector); + + g_usbd_msc[busid].nsectors = GET_BE32(&g_usbd_msc[busid].cbw.CB[6]); /* Number of Blocks to transfer */ + USB_LOG_DBG("nsectors: 0x%02x\r\n", g_usbd_msc[busid].nsectors); + + if ((g_usbd_msc[busid].start_sector + g_usbd_msc[busid].nsectors) > g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN]) { + SCSI_SetSenseData(busid, SCSI_KCQIR_LBAOUTOFRANGE); + USB_LOG_ERR("LBA out of range\r\n"); + return false; + } + + if (g_usbd_msc[busid].cbw.dDataLength != (g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN])) { + USB_LOG_ERR("scsi_blk_len does not match with dDataLength\r\n"); + return false; + } + g_usbd_msc[busid].stage = MSC_DATA_IN; +#ifdef CONFIG_USBDEV_MSC_THREAD + usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_IN); + return true; +#else + return SCSI_processRead(busid); +#endif +} + +static bool SCSI_write10(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint32_t data_len = 0; + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x00U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + g_usbd_msc[busid].start_sector = GET_BE32(&g_usbd_msc[busid].cbw.CB[2]); /* Logical Block Address of First Block */ + USB_LOG_DBG("lba: 0x%04x\r\n", g_usbd_msc[busid].start_sector); + + g_usbd_msc[busid].nsectors = GET_BE16(&g_usbd_msc[busid].cbw.CB[7]); /* Number of Blocks to transfer */ + USB_LOG_DBG("nsectors: 0x%02x\r\n", g_usbd_msc[busid].nsectors); + + data_len = g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]; + if ((g_usbd_msc[busid].start_sector + g_usbd_msc[busid].nsectors) > g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN]) { + USB_LOG_ERR("LBA out of range\r\n"); + return false; + } + + if (g_usbd_msc[busid].cbw.dDataLength != data_len) { + return false; + } + g_usbd_msc[busid].stage = MSC_DATA_OUT; + data_len = MIN(data_len, CONFIG_USBDEV_MSC_MAX_BUFSIZE); + usbd_ep_start_read(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr, g_usbd_msc[busid].block_buffer, data_len); + return true; +} + +static bool SCSI_write12(uint8_t busid, uint8_t **data, uint32_t *len) +{ + uint32_t data_len = 0; + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x00U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + g_usbd_msc[busid].start_sector = GET_BE32(&g_usbd_msc[busid].cbw.CB[2]); /* Logical Block Address of First Block */ + USB_LOG_DBG("lba: 0x%04x\r\n", g_usbd_msc[busid].start_sector); + + g_usbd_msc[busid].nsectors = GET_BE32(&g_usbd_msc[busid].cbw.CB[6]); /* Number of Blocks to transfer */ + USB_LOG_DBG("nsectors: 0x%02x\r\n", g_usbd_msc[busid].nsectors); + + data_len = g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]; + if ((g_usbd_msc[busid].start_sector + g_usbd_msc[busid].nsectors) > g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN]) { + USB_LOG_ERR("LBA out of range\r\n"); + return false; + } + + if (g_usbd_msc[busid].cbw.dDataLength != data_len) { + return false; + } + g_usbd_msc[busid].stage = MSC_DATA_OUT; + data_len = MIN(data_len, CONFIG_USBDEV_MSC_MAX_BUFSIZE); + usbd_ep_start_read(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr, g_usbd_msc[busid].block_buffer, data_len); + return true; +} +/* do not use verify to reduce code size */ +#if 0 +static bool SCSI_verify10(uint8_t busid, uint8_t **data, uint32_t *len) +{ + /* Logical Block Address of First Block */ + uint32_t lba = 0; + uint32_t blk_num = 0; + + if ((g_usbd_msc[busid].cbw.CB[1] & 0x02U) == 0x00U) { + return true; + } + + if (((g_usbd_msc[busid].cbw.bmFlags & 0x80U) != 0x00U) || (g_usbd_msc[busid].cbw.dDataLength == 0U)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + if ((g_usbd_msc[busid].cbw.CB[1] & 0x02U) == 0x02U) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDFIELDINCBA); + return false; /* Error, Verify Mode Not supported*/ + } + + lba = GET_BE32(&g_usbd_msc[busid].cbw.CB[2]); + USB_LOG_DBG("lba: 0x%x\r\n", lba); + + g_usbd_msc[busid].scsi_blk_addr = lba * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]; + + /* Number of Blocks to transfer */ + blk_num = GET_BE16(&g_usbd_msc[busid].cbw.CB[7]); + + USB_LOG_DBG("num (block) : 0x%x\r\n", blk_num); + g_usbd_msc[busid].scsi_blk_len = blk_num * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]; + + if ((lba + blk_num) > g_usbd_msc[busid].scsi_blk_nbr[g_usbd_msc[busid].cbw.bLUN]) { + USB_LOG_ERR("LBA out of range\r\n"); + return false; + } + + if (g_usbd_msc[busid].cbw.dDataLength != g_usbd_msc[busid].scsi_blk_len) { + return false; + } + + g_usbd_msc[busid].stage = MSC_DATA_OUT; + return true; +} +#endif + +static bool SCSI_processRead(uint8_t busid) +{ + uint32_t transfer_len; + + USB_LOG_DBG("read lba:%d\r\n", g_usbd_msc[busid].start_sector); + + transfer_len = MIN(g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN], CONFIG_USBDEV_MSC_MAX_BUFSIZE); + + if (usbd_msc_sector_read(busid, g_usbd_msc[busid].cbw.bLUN, g_usbd_msc[busid].start_sector, g_usbd_msc[busid].block_buffer, transfer_len) != 0) { + SCSI_SetSenseData(busid, SCSI_KCQHE_UREINRESERVEDAREA); + return false; + } + + g_usbd_msc[busid].start_sector += (transfer_len / g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]); + g_usbd_msc[busid].nsectors -= (transfer_len / g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]); + g_usbd_msc[busid].csw.dDataResidue -= transfer_len; + + if (g_usbd_msc[busid].nsectors == 0) { + g_usbd_msc[busid].stage = MSC_SEND_CSW; + } + + usbd_ep_start_write(busid, mass_ep_data[busid][MSD_IN_EP_IDX].ep_addr, g_usbd_msc[busid].block_buffer, transfer_len); + + return true; +} + +static bool SCSI_processWrite(uint8_t busid, uint32_t nbytes) +{ + uint32_t data_len = 0; + USB_LOG_DBG("write lba:%d\r\n", g_usbd_msc[busid].start_sector); + + if (usbd_msc_sector_write(busid, g_usbd_msc[busid].cbw.bLUN, g_usbd_msc[busid].start_sector, g_usbd_msc[busid].block_buffer, nbytes) != 0) { + SCSI_SetSenseData(busid, SCSI_KCQHE_WRITEFAULT); + return false; + } + + g_usbd_msc[busid].start_sector += (nbytes / g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]); + g_usbd_msc[busid].nsectors -= (nbytes / g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN]); + g_usbd_msc[busid].csw.dDataResidue -= nbytes; + + if (g_usbd_msc[busid].nsectors == 0) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_PASSED); + } else { + data_len = MIN(g_usbd_msc[busid].nsectors * g_usbd_msc[busid].scsi_blk_size[g_usbd_msc[busid].cbw.bLUN], CONFIG_USBDEV_MSC_MAX_BUFSIZE); + usbd_ep_start_read(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr, g_usbd_msc[busid].block_buffer, data_len); + } + + return true; +} + +static bool SCSI_CBWDecode(uint8_t busid, uint32_t nbytes) +{ + uint8_t *buf2send = g_usbd_msc[busid].block_buffer; + uint32_t len2send = 0; + bool ret = false; + + if (nbytes != sizeof(struct CBW)) { + USB_LOG_ERR("size != sizeof(cbw)\r\n"); + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } + + g_usbd_msc[busid].csw.dTag = g_usbd_msc[busid].cbw.dTag; + g_usbd_msc[busid].csw.dDataResidue = g_usbd_msc[busid].cbw.dDataLength; + + if ((g_usbd_msc[busid].cbw.dSignature != MSC_CBW_Signature) || (g_usbd_msc[busid].cbw.bCBLength < 1) || (g_usbd_msc[busid].cbw.bCBLength > 16)) { + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + return false; + } else { + USB_LOG_DBG("Decode CB:0x%02x\r\n", g_usbd_msc[busid].cbw.CB[0]); + switch (g_usbd_msc[busid].cbw.CB[0]) { + case SCSI_CMD_TESTUNITREADY: + ret = SCSI_testUnitReady(busid, &buf2send, &len2send); + break; + case SCSI_CMD_REQUESTSENSE: + ret = SCSI_requestSense(busid, &buf2send, &len2send); + break; + case SCSI_CMD_INQUIRY: + ret = SCSI_inquiry(busid, &buf2send, &len2send); + break; + case SCSI_CMD_STARTSTOPUNIT: + ret = SCSI_startStopUnit(busid, &buf2send, &len2send); + break; + case SCSI_CMD_PREVENTMEDIAREMOVAL: + ret = SCSI_preventAllowMediaRemoval(busid, &buf2send, &len2send); + break; + case SCSI_CMD_MODESENSE6: + ret = SCSI_modeSense6(busid, &buf2send, &len2send); + break; + case SCSI_CMD_MODESENSE10: + ret = SCSI_modeSense10(busid, &buf2send, &len2send); + break; + case SCSI_CMD_READFORMATCAPACITIES: + ret = SCSI_readFormatCapacity(busid, &buf2send, &len2send); + break; + case SCSI_CMD_READCAPACITY10: + ret = SCSI_readCapacity10(busid, &buf2send, &len2send); + break; + case SCSI_CMD_READ10: + ret = SCSI_read10(busid, NULL, 0); + break; + case SCSI_CMD_READ12: + ret = SCSI_read12(busid, NULL, 0); + break; + case SCSI_CMD_WRITE10: + ret = SCSI_write10(busid, NULL, 0); + break; + case SCSI_CMD_WRITE12: + ret = SCSI_write12(busid, NULL, 0); + break; + case SCSI_CMD_VERIFY10: + //ret = SCSI_verify10(NULL, 0); + ret = false; + break; + + default: + SCSI_SetSenseData(busid, SCSI_KCQIR_INVALIDCOMMAND); + USB_LOG_WRN("unsupported cmd:0x%02x\r\n", g_usbd_msc[busid].cbw.CB[0]); + ret = false; + break; + } + } + if (ret) { + if (g_usbd_msc[busid].stage == MSC_READ_CBW) { + if (len2send) { + USB_LOG_DBG("Send info len:%d\r\n", len2send); + usbd_msc_send_info(busid, buf2send, len2send); + } else { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_PASSED); + } + } + } + return ret; +} + +void mass_storage_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + switch (g_usbd_msc[busid].stage) { + case MSC_READ_CBW: + if (SCSI_CBWDecode(busid, nbytes) == false) { + USB_LOG_ERR("Command:0x%02x decode err\r\n", g_usbd_msc[busid].cbw.CB[0]); + usbd_msc_bot_abort(busid); + return; + } + break; + case MSC_DATA_OUT: + switch (g_usbd_msc[busid].cbw.CB[0]) { + case SCSI_CMD_WRITE10: + case SCSI_CMD_WRITE12: +#ifdef CONFIG_USBDEV_MSC_THREAD + g_usbd_msc[busid].nbytes = nbytes; + usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_OUT); +#else + if (SCSI_processWrite(busid, nbytes) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + } +#endif + break; + default: + break; + } + break; + default: + break; + } +} + +void mass_storage_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + switch (g_usbd_msc[busid].stage) { + case MSC_DATA_IN: + switch (g_usbd_msc[busid].cbw.CB[0]) { + case SCSI_CMD_READ10: + case SCSI_CMD_READ12: +#ifdef CONFIG_USBDEV_MSC_THREAD + usb_osal_mq_send(g_usbd_msc[busid].usbd_msc_mq, MSC_DATA_IN); +#else + if (SCSI_processRead(busid) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + return; + } +#endif + break; + default: + break; + } + break; + /*the device has to send a CSW*/ + case MSC_SEND_CSW: + usbd_msc_send_csw(busid, CSW_STATUS_CMD_PASSED); + break; + + /*the host has received the CSW*/ + case MSC_WAIT_CSW: + g_usbd_msc[busid].stage = MSC_READ_CBW; + USB_LOG_DBG("Start reading cbw\r\n"); + usbd_ep_start_read(busid, mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr, (uint8_t *)&g_usbd_msc[busid].cbw, USB_SIZEOF_MSC_CBW); + break; + + default: + break; + } +} + +#ifdef CONFIG_USBDEV_MSC_THREAD +static void usbdev_msc_thread(void *argument) +{ + uintptr_t event; + int ret; + uint8_t busid = (uint8_t)argument; + + while (1) { + ret = usb_osal_mq_recv(g_usbd_msc[busid].usbd_msc_mq, (uintptr_t *)&event, USB_OSAL_WAITING_FOREVER); + if (ret < 0) { + continue; + } + USB_LOG_DBG("%d\r\n", event); + if (event == MSC_DATA_OUT) { + if (SCSI_processWrite(busid, g_usbd_msc[busid].nbytes) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + } + } else if (event == MSC_DATA_IN) { + if (SCSI_processRead(busid) == false) { + usbd_msc_send_csw(busid, CSW_STATUS_CMD_FAILED); /* send fail status to host,and the host will retry*/ + } + } else { + } + } +} +#endif + +struct usbd_interface *usbd_msc_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t out_ep, const uint8_t in_ep) +{ + intf->class_interface_handler = msc_storage_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = msc_storage_notify_handler; + + mass_ep_data[busid][MSD_OUT_EP_IDX].ep_addr = out_ep; + mass_ep_data[busid][MSD_OUT_EP_IDX].ep_cb = mass_storage_bulk_out; + mass_ep_data[busid][MSD_IN_EP_IDX].ep_addr = in_ep; + mass_ep_data[busid][MSD_IN_EP_IDX].ep_cb = mass_storage_bulk_in; + + usbd_add_endpoint(busid, &mass_ep_data[busid][MSD_OUT_EP_IDX]); + usbd_add_endpoint(busid, &mass_ep_data[busid][MSD_IN_EP_IDX]); + + memset((uint8_t *)&g_usbd_msc[busid], 0, sizeof(struct usbd_msc_priv)); + + usdb_msc_set_max_lun(busid); + for (uint8_t i = 0u; i <= g_usbd_msc[busid].max_lun; i++) { + usbd_msc_get_cap(busid, i, &g_usbd_msc[busid].scsi_blk_nbr[i], &g_usbd_msc[busid].scsi_blk_size[i]); + + if (g_usbd_msc[busid].scsi_blk_size[i] > CONFIG_USBDEV_MSC_MAX_BUFSIZE) { + USB_LOG_ERR("msc block buffer overflow\r\n"); + return NULL; + } + } + + return intf; +} + +void usbd_msc_set_readonly(uint8_t busid, bool readonly) +{ + g_usbd_msc[busid].readonly = readonly; +} + +bool usbd_msc_set_popup(uint8_t busid) +{ + return g_usbd_msc[busid].popup; +} diff --git a/components/drivers/usb/cherryusb/class/msc/usbd_msc.h b/components/drivers/usb/cherryusb/class/msc/usbd_msc.h new file mode 100644 index 00000000000..c71f64a2321 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/msc/usbd_msc.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2022, sakumisu + * Copyright (c) 2024, zhihong chen + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_MSC_H +#define USBD_MSC_H + +#include "usb_msc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init msc interface driver */ +struct usbd_interface *usbd_msc_init_intf(uint8_t busid, struct usbd_interface *intf, + const uint8_t out_ep, + const uint8_t in_ep); + +void usbd_msc_get_cap(uint8_t busid, uint8_t lun, uint32_t *block_num, uint32_t *block_size); +int usbd_msc_sector_read(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length); +int usbd_msc_sector_write(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length); + +void usbd_msc_set_readonly(uint8_t busid, bool readonly); +bool usbd_msc_set_popup(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_MSC_H */ diff --git a/components/drivers/usb/cherryusb/class/msc/usbh_msc.c b/components/drivers/usb/cherryusb/class/msc/usbh_msc.c new file mode 100644 index 00000000000..71e8e533705 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/msc/usbh_msc.c @@ -0,0 +1,436 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_msc.h" +#include "usb_scsi.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_msc" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/sd%c" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_msc_buf[64]; + +static struct usbh_msc g_msc_class[CONFIG_USBHOST_MAX_MSC_CLASS]; +static uint32_t g_devinuse = 0; +static struct usbh_msc_modeswitch_config *g_msc_modeswitch_config = NULL; + +static struct usbh_msc *usbh_msc_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_MSC_CLASS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_msc_class[devno], 0, sizeof(struct usbh_msc)); + g_msc_class[devno].sdchar = 'a' + devno; + return &g_msc_class[devno]; + } + } + return NULL; +} + +static void usbh_msc_class_free(struct usbh_msc *msc_class) +{ + int devno = msc_class->sdchar - 'a'; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(msc_class, 0, sizeof(struct usbh_msc)); +} + +static int usbh_msc_get_maxlun(struct usbh_msc *msc_class, uint8_t *buffer) +{ + struct usb_setup_packet *setup = msc_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = MSC_REQUEST_GET_MAX_LUN; + setup->wValue = 0; + setup->wIndex = msc_class->intf; + setup->wLength = 1; + + return usbh_control_transfer(msc_class->hport, setup, buffer); +} + +static void usbh_msc_cbw_dump(struct CBW *cbw) +{ + int i; + + USB_LOG_DBG("CBW:\r\n"); + USB_LOG_DBG(" signature: 0x%08x\r\n", (unsigned int)cbw->dSignature); + USB_LOG_DBG(" tag: 0x%08x\r\n", (unsigned int)cbw->dTag); + USB_LOG_DBG(" datlen: 0x%08x\r\n", (unsigned int)cbw->dDataLength); + USB_LOG_DBG(" flags: 0x%02x\r\n", cbw->bmFlags); + USB_LOG_DBG(" lun: 0x%02x\r\n", cbw->bLUN); + USB_LOG_DBG(" cblen: 0x%02x\r\n", cbw->bCBLength); + + USB_LOG_DBG("CB:\r\n"); + for (i = 0; i < cbw->bCBLength; i += 8) { + USB_LOG_DBG(" 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x 0x%02x\r\n", + cbw->CB[i], cbw->CB[i + 1], cbw->CB[i + 2], + cbw->CB[i + 3], cbw->CB[i + 4], cbw->CB[i + 5], + cbw->CB[i + 6], cbw->CB[i + 7]); + } +} + +static void usbh_msc_csw_dump(struct CSW *csw) +{ + USB_LOG_DBG("CSW:\r\n"); + USB_LOG_DBG(" signature: 0x%08x\r\n", (unsigned int)csw->dSignature); + USB_LOG_DBG(" tag: 0x%08x\r\n", (unsigned int)csw->dTag); + USB_LOG_DBG(" residue: 0x%08x\r\n", (unsigned int)csw->dDataResidue); + USB_LOG_DBG(" status: 0x%02x\r\n", csw->bStatus); +} + +static inline int usbh_msc_bulk_in_transfer(struct usbh_msc *msc_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &msc_class->bulkin_urb; + + usbh_bulk_urb_fill(urb, msc_class->hport, msc_class->bulkin, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +static inline int usbh_msc_bulk_out_transfer(struct usbh_msc *msc_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &msc_class->bulkout_urb; + + usbh_bulk_urb_fill(urb, msc_class->hport, msc_class->bulkout, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +static int usbh_bulk_cbw_csw_xfer(struct usbh_msc *msc_class, struct CBW *cbw, struct CSW *csw, uint8_t *buffer) +{ + int nbytes; + + usbh_msc_cbw_dump(cbw); + + /* Send the CBW */ + nbytes = usbh_msc_bulk_out_transfer(msc_class, (uint8_t *)cbw, USB_SIZEOF_MSC_CBW, CONFIG_USBHOST_MSC_TIMEOUT); + if (nbytes < 0) { + USB_LOG_ERR("cbw transfer error\r\n"); + goto __err_exit; + } + + if (cbw->dDataLength != 0) { + if (cbw->CB[0] == SCSI_CMD_WRITE10) { + nbytes = usbh_msc_bulk_out_transfer(msc_class, buffer, cbw->dDataLength, CONFIG_USBHOST_MSC_TIMEOUT); + } else if (cbw->CB[0] == SCSI_CMD_READCAPACITY10) { + nbytes = usbh_msc_bulk_in_transfer(msc_class, buffer, cbw->dDataLength, CONFIG_USBHOST_MSC_TIMEOUT); + if (nbytes >= 0) { + /* Save the capacity information */ + msc_class->blocknum = GET_BE32(&buffer[0]) + 1; + msc_class->blocksize = GET_BE32(&buffer[4]); + } + } else { + nbytes = usbh_msc_bulk_in_transfer(msc_class, buffer, cbw->dDataLength, CONFIG_USBHOST_MSC_TIMEOUT); + } + + if (nbytes < 0) { + USB_LOG_ERR("msc data transfer error\r\n"); + goto __err_exit; + } + } + + /* Receive the CSW */ + memset(csw, 0, USB_SIZEOF_MSC_CSW); + nbytes = usbh_msc_bulk_in_transfer(msc_class, (uint8_t *)csw, USB_SIZEOF_MSC_CSW, CONFIG_USBHOST_MSC_TIMEOUT); + if (nbytes < 0) { + USB_LOG_ERR("csw transfer error\r\n"); + goto __err_exit; + } + + usbh_msc_csw_dump(csw); + + /* check csw status */ + if (csw->dSignature != MSC_CSW_Signature) { + USB_LOG_ERR("csw signature error\r\n"); + return -USB_ERR_INVAL; + } + + if (csw->bStatus != 0) { + USB_LOG_ERR("csw bStatus %d\r\n", csw->bStatus); + return -USB_ERR_INVAL; + } +__err_exit: + return nbytes < 0 ? (int)nbytes : 0; +} + +static inline int usbh_msc_scsi_testunitready(struct usbh_msc *msc_class) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_buf; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->bCBLength = SCSICMD_TESTUNITREADY_SIZEOF; + cbw->CB[0] = SCSI_CMD_TESTUNITREADY; + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, NULL); +} + +static inline int usbh_msc_scsi_requestsense(struct usbh_msc *msc_class) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_buf; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->bmFlags = 0x80; + cbw->dDataLength = SCSIRESP_FIXEDSENSEDATA_SIZEOF; + cbw->bCBLength = SCSICMD_REQUESTSENSE_SIZEOF; + cbw->CB[0] = SCSI_CMD_REQUESTSENSE; + cbw->CB[4] = SCSIRESP_FIXEDSENSEDATA_SIZEOF; + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, g_msc_buf); +} + +static inline int usbh_msc_scsi_inquiry(struct usbh_msc *msc_class) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_buf; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->dDataLength = SCSIRESP_INQUIRY_SIZEOF; + cbw->bmFlags = 0x80; + cbw->bCBLength = SCSICMD_INQUIRY_SIZEOF; + cbw->CB[0] = SCSI_CMD_INQUIRY; + cbw->CB[4] = SCSIRESP_INQUIRY_SIZEOF; + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, g_msc_buf); +} + +static inline int usbh_msc_scsi_readcapacity10(struct usbh_msc *msc_class) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_buf; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->dDataLength = SCSIRESP_READCAPACITY10_SIZEOF; + cbw->bmFlags = 0x80; + cbw->bCBLength = SCSICMD_READCAPACITY10_SIZEOF; + cbw->CB[0] = SCSI_CMD_READCAPACITY10; + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, g_msc_buf); +} + +static inline void usbh_msc_modeswitch(struct usbh_msc *msc_class, const uint8_t *message) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_buf; + + memcpy(g_msc_buf, message, 31); + + usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, NULL); +} + +static int usbh_msc_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + struct usbh_msc_modeswitch_config *config; + + struct usbh_msc *msc_class = usbh_msc_class_alloc(); + if (msc_class == NULL) { + USB_LOG_ERR("Fail to alloc msc_class\r\n"); + return -USB_ERR_NOMEM; + } + + msc_class->hport = hport; + msc_class->intf = intf; + + hport->config.intf[intf].priv = msc_class; + + ret = usbh_msc_get_maxlun(msc_class, g_msc_buf); + if (ret < 0) { + return ret; + } + + USB_LOG_INFO("Get max LUN:%u\r\n", g_msc_buf[0] + 1); + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(msc_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(msc_class->bulkout, ep_desc); + } + } + + if (g_msc_modeswitch_config) { + uint8_t num = 0; + while (1) { + config = &g_msc_modeswitch_config[num]; + if (config && config->name) { + if ((hport->device_desc.idVendor == config->vid) && + (hport->device_desc.idProduct == config->pid)) { + USB_LOG_INFO("%s usb_modeswitch enable\r\n", config->name); + usbh_msc_modeswitch(msc_class, config->message_content); + return 0; + } + num++; + } else { + break; + } + } + } + + ret = usbh_msc_scsi_testunitready(msc_class); + if (ret < 0) { + ret = usbh_msc_scsi_requestsense(msc_class); + if (ret < 0) { + USB_LOG_ERR("Fail to scsi_testunitready\r\n"); + return ret; + } + } + + ret = usbh_msc_scsi_inquiry(msc_class); + if (ret < 0) { + USB_LOG_ERR("Fail to scsi_inquiry\r\n"); + return ret; + } + ret = usbh_msc_scsi_readcapacity10(msc_class); + if (ret < 0) { + USB_LOG_ERR("Fail to scsi_readcapacity10\r\n"); + return ret; + } + + if (msc_class->blocksize > 0) { + USB_LOG_INFO("Capacity info:\r\n"); + USB_LOG_INFO("Block num:%d,block size:%d\r\n", (unsigned int)msc_class->blocknum, (unsigned int)msc_class->blocksize); + } else { + USB_LOG_ERR("Invalid block size\r\n"); + return -USB_ERR_RANGE; + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, msc_class->sdchar); + + USB_LOG_INFO("Register MSC Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_msc_run(msc_class); + return ret; +} + +static int usbh_msc_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_msc *msc_class = (struct usbh_msc *)hport->config.intf[intf].priv; + + if (msc_class) { + if (msc_class->bulkin) { + usbh_kill_urb(&msc_class->bulkin_urb); + } + + if (msc_class->bulkout) { + usbh_kill_urb(&msc_class->bulkout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister MSC Class:%s\r\n", hport->config.intf[intf].devname); + usbh_msc_stop(msc_class); + } + + usbh_msc_class_free(msc_class); + } + + return ret; +} + + +int usbh_msc_scsi_write10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_buf; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->dDataLength = (msc_class->blocksize * nsectors); + cbw->bCBLength = SCSICMD_WRITE10_SIZEOF; + cbw->CB[0] = SCSI_CMD_WRITE10; + + SET_BE32(&cbw->CB[2], start_sector); + SET_BE16(&cbw->CB[7], nsectors); + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, (uint8_t *)buffer); +} + +int usbh_msc_scsi_read10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors) +{ + struct CBW *cbw; + + /* Construct the CBW */ + cbw = (struct CBW *)g_msc_buf; + memset(cbw, 0, USB_SIZEOF_MSC_CBW); + cbw->dSignature = MSC_CBW_Signature; + + cbw->dDataLength = (msc_class->blocksize * nsectors); + cbw->bmFlags = 0x80; + cbw->bCBLength = SCSICMD_READ10_SIZEOF; + cbw->CB[0] = SCSI_CMD_READ10; + + SET_BE32(&cbw->CB[2], start_sector); + SET_BE16(&cbw->CB[7], nsectors); + + return usbh_bulk_cbw_csw_xfer(msc_class, cbw, (struct CSW *)g_msc_buf, (uint8_t *)buffer); +} + +void usbh_msc_modeswitch_enable(struct usbh_msc_modeswitch_config *config) +{ + if (config) { + g_msc_modeswitch_config = config; + } else { + g_msc_modeswitch_config = NULL; + } +} + +__WEAK void usbh_msc_run(struct usbh_msc *msc_class) +{ +} + +__WEAK void usbh_msc_stop(struct usbh_msc *msc_class) +{ +} + +const struct usbh_class_driver msc_class_driver = { + .driver_name = "msc", + .connect = usbh_msc_connect, + .disconnect = usbh_msc_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info msc_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .class = USB_DEVICE_CLASS_MASS_STORAGE, + .subclass = MSC_SUBCLASS_SCSI, + .protocol = MSC_PROTOCOL_BULK_ONLY, + .id_table = NULL, + .class_driver = &msc_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/msc/usbh_msc.h b/components/drivers/usb/cherryusb/class/msc/usbh_msc.h new file mode 100644 index 00000000000..50a61a9c117 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/msc/usbh_msc.h @@ -0,0 +1,49 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_MSC_H +#define USBH_MSC_H + +#include "usb_msc.h" +#include "usb_scsi.h" + +struct usbh_msc { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN urb */ + struct usbh_urb bulkout_urb; /* Bulk OUT urb */ + + uint8_t intf; /* Data interface number */ + uint8_t sdchar; + uint32_t blocknum; /* Number of blocks on the USB mass storage device */ + uint16_t blocksize; /* Block size of USB mass storage device */ + + void *user_data; +}; + +struct usbh_msc_modeswitch_config { + const char *name; + uint16_t vid; /* Vendor ID (for vendor/product specific devices) */ + uint16_t pid; /* Product ID (for vendor/product specific devices) */ + const uint8_t *message_content; +}; + +void usbh_msc_modeswitch_enable(struct usbh_msc_modeswitch_config *config); +int usbh_msc_scsi_write10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors); +int usbh_msc_scsi_read10(struct usbh_msc *msc_class, uint32_t start_sector, const uint8_t *buffer, uint32_t nsectors); + +void usbh_msc_run(struct usbh_msc *msc_class); +void usbh_msc_stop(struct usbh_msc *msc_class); + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_MSC_H */ diff --git a/components/drivers/usb/cherryusb/class/template/usb_xxx.h b/components/drivers/usb/cherryusb/class/template/usb_xxx.h new file mode 100644 index 00000000000..d883c8b2e23 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/template/usb_xxx.h @@ -0,0 +1,4 @@ +#ifndef _USB_XXX_H +#define _USB_XXX_H + +#endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/template/usbd_xxx.c b/components/drivers/usb/cherryusb/class/template/usbd_xxx.c new file mode 100644 index 00000000000..aa4bc01bcdf --- /dev/null +++ b/components/drivers/usb/cherryusb/class/template/usbd_xxx.c @@ -0,0 +1,39 @@ +#include "usbd_core.h" +#include "usbd_xxx.h" + +static int xxx_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_WRN("XXX Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + switch (setup->bRequest) { + default: + USB_LOG_WRN("Unhandled XXX Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +static void xxx_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + + break; + + default: + break; + } +} + +struct usbd_interface *usbd_xxx_init_intf(uint8_t busid, struct usbd_interface *intf) +{ + intf->class_interface_handler = xxx_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = xxx_notify_handler; + + return intf; +} diff --git a/components/drivers/usb/cherryusb/class/template/usbd_xxx.h b/components/drivers/usb/cherryusb/class/template/usbd_xxx.h new file mode 100644 index 00000000000..8230c3021b7 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/template/usbd_xxx.h @@ -0,0 +1,16 @@ +#ifndef _USBD_XXX_H_ +#define _USBD_XXX_H_ + +#include "usb_xxx.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct usbd_interface *usbd_xxx_init_intf(uint8_t busid, struct usbd_interface *intf); + +#ifdef __cplusplus +} +#endif + +#endif /* _USBD_XXX_H_ */ diff --git a/components/drivers/usb/cherryusb/class/template/usbh_xxx.c b/components/drivers/usb/cherryusb/class/template/usbh_xxx.c new file mode 100644 index 00000000000..22b3636d62c --- /dev/null +++ b/components/drivers/usb/cherryusb/class/template/usbh_xxx.c @@ -0,0 +1,97 @@ +#include "usbh_core.h" +#include "usbh_xxx.h" + +#define DEV_FORMAT "/dev/xxx" + +#define CONFIG_USBHOST_MAX_CUSTOM_CLASS 1 +static struct usbh_xxx g_xxx_class[CONFIG_USBHOST_MAX_CUSTOM_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_xxx *usbh_xxx_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_CUSTOM_CLASS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_xxx_class[devno], 0, sizeof(struct usbh_xxx)); + g_xxx_class[devno].minor = devno; + return &g_xxx_class[devno]; + } + } + return NULL; +} + +static void usbh_xxx_class_free(struct usbh_xxx *xxx_class) +{ + int devno = xxx_class->minor; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(xxx_class, 0, sizeof(struct usbh_xxx)); +} + +static int usbh_xxx_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + + struct usbh_xxx *xxx_class = usbh_xxx_class_alloc(); + if (xxx_class == NULL) { + USB_LOG_ERR("Fail to alloc xxx_class\r\n"); + return -USB_ERR_NOMEM; + } + + return ret; +} + + +static int usbh_xxx_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_xxx *xxx_class = (struct usbh_xxx *)hport->config.intf[intf].priv; + + if (xxx_class) { + if (xxx_class->xxxin) { + usbh_kill_urb(&xxx_class->xxxin_urb); + } + + if (xxx_class->xxxout) { + usbh_kill_urb(&xxx_class->xxxout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister xxx Class:%s\r\n", hport->config.intf[intf].devname); + usbh_xxx_stop(xxx_class); + } + + usbh_xxx_class_free(xxx_class); + } + + return ret; +} + +__WEAK void usbh_xxx_run(struct usbh_xxx *xxx_class) +{ +} + +__WEAK void usbh_xxx_stop(struct usbh_xxx *xxx_class) +{ +} + +static const struct usbh_class_driver xxx_class_driver = { + .driver_name = "xxx", + .connect = usbh_xxx_connect, + .disconnect = usbh_xxx_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info xxx_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .class = 0, + .subclass = 0, + .protocol = 0, + .id_table = NULL, + .class_driver = &xxx_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/template/usbh_xxx.h b/components/drivers/usb/cherryusb/class/template/usbh_xxx.h new file mode 100644 index 00000000000..0858f51d74c --- /dev/null +++ b/components/drivers/usb/cherryusb/class/template/usbh_xxx.h @@ -0,0 +1,22 @@ +#ifndef _USBH_XXX_H +#define _USBH_XXX_H + +#include "usb_xxx.h" + +struct usbh_xxx { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *xxxin; + struct usb_endpoint_descriptor *xxxout; + struct usbh_urb xxxin_urb; + struct usbh_urb xxxout_urb; + + uint8_t intf; /* interface number */ + uint8_t minor; + + void *user_data; +}; + +void usbh_xxx_run(struct usbh_xxx *xxx_class); +void usbh_xxx_stop(struct usbh_xxx *xxx_class); + +#endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c b/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c new file mode 100644 index 00000000000..62d78ec3775 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.c @@ -0,0 +1,774 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_asix.h" +#include "usb_cdc.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "asix" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/asix" + +static struct usbh_asix g_asix_class; +#define CONFIG_USBHOST_ASIX_ETH_MAX_SIZE (1514U + 8) + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_rx_buffer[CONFIG_USBHOST_ASIX_ETH_MAX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_tx_buffer[CONFIG_USBHOST_ASIX_ETH_MAX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_inttx_buffer[16]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_buf[32]; + +#define ETH_ALEN 6 + +#define PHY_MODE_MARVELL 0x0000 +#define MII_MARVELL_LED_CTRL 0x0018 +#define MII_MARVELL_STATUS 0x001b +#define MII_MARVELL_CTRL 0x0014 + +#define MARVELL_LED_MANUAL 0x0019 + +#define MARVELL_STATUS_HWCFG 0x0004 + +#define MARVELL_CTRL_TXDELAY 0x0002 +#define MARVELL_CTRL_RXDELAY 0x0080 + +#define PHY_MODE_RTL8211CL 0x000C + +#define AX88772A_PHY14H 0x14 +#define AX88772A_PHY14H_DEFAULT 0x442C + +#define AX88772A_PHY15H 0x15 +#define AX88772A_PHY15H_DEFAULT 0x03C8 + +#define AX88772A_PHY16H 0x16 +#define AX88772A_PHY16H_DEFAULT 0x4044 + +#define SPEED_100 0 +#define SPEED_10 1 + +static int usbh_asix_read_cmd(struct usbh_asix *asix_class, + uint8_t cmd, + uint16_t value, + uint16_t index, + void *data, + uint16_t size) +{ + struct usb_setup_packet *setup = asix_class->hport->setup; + int ret; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = cmd; + setup->wValue = value; + setup->wIndex = index; + setup->wLength = size; + + ret = usbh_control_transfer(asix_class->hport, setup, g_asix_buf); + if (ret < 0) { + return ret; + } + memcpy(data, g_asix_buf, ret - 8); + + return ret; +} + +static int usbh_asix_write_cmd(struct usbh_asix *asix_class, + uint8_t cmd, + uint16_t value, + uint16_t index, + void *data, + uint16_t size) +{ + struct usb_setup_packet *setup = asix_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = cmd; + setup->wValue = value; + setup->wIndex = index; + setup->wLength = size; + + memcpy(g_asix_buf, data, size); + + return usbh_control_transfer(asix_class->hport, setup, g_asix_buf); +} + +static int usbh_asix_mdio_write(struct usbh_asix *asix_class, int phy_id, int loc, int val) +{ + uint8_t smsr; + uint16_t res = (uint16_t)val; + int ret; + + for (uint8_t i = 0; i < 10; i++) { + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_SW_MII, 0, 0, NULL, 0); + if (ret < 0) { + return ret; + } + usb_osal_msleep(1); + ret = usbh_asix_read_cmd(asix_class, AX_CMD_STATMNGSTS_REG, 0, 0, &smsr, 1); + if (ret < 0) { + return ret; + } + + if (smsr & AX_HOST_EN) { + break; + } + } + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_MII_REG, phy_id, loc, &res, 2); + if (ret < 0) { + return ret; + } + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_HW_MII, 0, 0, NULL, 0); + if (ret < 0) { + return ret; + } + return 0; +} + +static int usbh_asix_mdio_read(struct usbh_asix *asix_class, int phy_id, int loc) +{ + uint8_t smsr; + uint16_t res; + int ret; + + for (uint8_t i = 0; i < 10; i++) { + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_SW_MII, 0, 0, NULL, 0); + if (ret < 0) { + return ret; + } + usb_osal_msleep(1); + ret = usbh_asix_read_cmd(asix_class, AX_CMD_STATMNGSTS_REG, 0, 0, &smsr, 1); + if (ret < 0) { + return ret; + } + + if (smsr & AX_HOST_EN) { + break; + } + } + + ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_MII_REG, phy_id, loc, &res, 2); + if (ret < 0) { + return ret; + } + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_HW_MII, 0, 0, NULL, 0); + if (ret < 0) { + return ret; + } + return res; +} + +static int usbh_asix_read_phy_addr(struct usbh_asix *asix_class, bool internal) +{ + int ret, offset; + uint8_t buf[2]; + + ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_PHY_ID, 0, 0, buf, 2); + if (ret < 0) { + return ret; + } + + offset = (internal ? 1 : 0); + ret = buf[offset]; + + USB_LOG_INFO("%s PHY address 0x%x\r\n", internal ? "internal" : "external", ret); + + return ret; +} + +static int usbh_asix_sw_reset(struct usbh_asix *asix_class, uint8_t flags) +{ + int ret; + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SW_RESET, flags, 0, NULL, 0); + if (ret < 0) + USB_LOG_ERR("Failed to send software reset: %d\r\n", ret); + + return ret; +} + +static uint16_t usbh_asix_read_rx_ctl(struct usbh_asix *asix_class) +{ + uint16_t v; + int ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_RX_CTL, 0, 0, &v, 2); + if (ret < 0) { + return ret; + } + return v; +} + +static int usbh_asix_write_rx_ctl(struct usbh_asix *asix_class, uint16_t mode) +{ + int ret; + + USB_LOG_DBG("asix_write_rx_ctl() - mode = 0x%04x\r\n", mode); + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_RX_CTL, mode, 0, NULL, 0); + if (ret < 0) + USB_LOG_ERR("Failed to write RX_CTL mode to 0x%04x: %02x\r\n", + mode, ret); + + return ret; +} + +static uint16_t usbh_asix_read_medium_status(struct usbh_asix *asix_class) +{ + uint16_t v; + int ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_MEDIUM_STATUS, 0, 0, &v, 2); + + if (ret < 0) { + USB_LOG_ERR("Error reading Medium Status register: %02x\r\n", + ret); + return ret; /* TODO: callers not checking for error ret */ + } + + return v; +} + +static int usbh_asix_write_medium_mode(struct usbh_asix *asix_class, uint16_t mode) +{ + int ret; + + USB_LOG_DBG("asix_write_medium_mode() - mode = 0x%04x\r\n", mode); + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, NULL, 0); + if (ret < 0) + USB_LOG_ERR("Failed to write Medium Mode mode to 0x%04x: %02x\r\n", + mode, ret); + + return ret; +} + +static int usbh_asix_write_gpio(struct usbh_asix *asix_class, uint16_t value, int sleep) +{ + int ret; + + USB_LOG_DBG("asix_write_gpio() - value = 0x%04x\r\n", value); + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_GPIOS, value, 0, NULL, 0); + if (ret < 0) + USB_LOG_ERR("Failed to write GPIO value 0x%04x: %d\r\n", + value, ret); + + if (sleep) + usb_osal_msleep(sleep); + + return ret; +} + +/* + * AX88772 & AX88178 have a 16-bit RX_CTL value + */ +static void usbh_asix_set_multicast(struct usbh_asix *asix_class) +{ + uint16_t rx_ctl = AX_DEFAULT_RX_CTL | AX_RX_CTL_AM; + const uint8_t multi_filter[] = { 0x00, 0x00, 0x20, 0x80, 0x00, 0x00, 0x00, 0x40 }; + + usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_MULTI_FILTER, 0, 0, (uint8_t *)multi_filter, AX_MCAST_FILTER_SIZE); + usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, NULL, 0); +} + +static int usbh_ax88772_hw_reset(struct usbh_asix *asix_class) +{ + uint16_t rx_ctl; + int ret; + + ret = usbh_asix_write_gpio(asix_class, AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5); + if (ret < 0) + goto out; + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SW_PHY_SELECT, asix_class->embd_phy, + 0, NULL, 0); + if (ret < 0) { + USB_LOG_ERR("Select PHY #1 failed: %d\r\n", ret); + goto out; + } + + if (asix_class->embd_phy) { + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPPD); + if (ret < 0) + goto out; + + usb_osal_msleep(10); + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_CLEAR); + if (ret < 0) + goto out; + + usb_osal_msleep(60); + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPRL | AX_SWRESET_PRL); + if (ret < 0) + goto out; + } else { + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPPD | AX_SWRESET_PRL); + if (ret < 0) + goto out; + } + + usb_osal_msleep(150); + + ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL); + if (ret < 0) + goto out; + + ret = usbh_asix_write_medium_mode(asix_class, AX88772_MEDIUM_DEFAULT); + if (ret < 0) + goto out; + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_IPG0, + AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, + AX88772_IPG2_DEFAULT, NULL, 0); + if (ret < 0) { + USB_LOG_ERR("Write IPG,IPG1,IPG2 failed: %d\r\n", ret); + goto out; + } + + /* Rewrite MAC address */ + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_NODE_ID, 0, 0, asix_class->mac, ETH_ALEN); + if (ret < 0) + goto out; + + /* Set RX_CTL to default values with 2k buffer, and enable cactus */ + ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL); + if (ret < 0) + goto out; + + rx_ctl = usbh_asix_read_rx_ctl(asix_class); + USB_LOG_INFO("RX_CTL is 0x%04x after all initializations\r\n", + rx_ctl); + + rx_ctl = usbh_asix_read_medium_status(asix_class); + USB_LOG_INFO("Medium Status is 0x%04x after all initializations\r\n", + rx_ctl); + + return 0; + +out: + return ret; +} + +static int usbh_ax88772a_hw_reset(struct usbh_asix *asix_class) +{ + uint16_t rx_ctl, phy14h, phy15h, phy16h; + int ret; + + ret = usbh_asix_write_gpio(asix_class, AX_GPIO_RSE, 5); + if (ret < 0) + goto out; + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_SW_PHY_SELECT, asix_class->embd_phy | AX_PHYSEL_SSEN, 0, NULL, 0); + if (ret < 0) { + USB_LOG_ERR("Select PHY #1 failed: %d\r\n", ret); + goto out; + } + usb_osal_msleep(10); + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPPD | AX_SWRESET_IPRL); + if (ret < 0) + goto out; + + usb_osal_msleep(10); + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPRL); + if (ret < 0) + goto out; + + usb_osal_msleep(160); + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_CLEAR); + if (ret < 0) + goto out; + + ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPRL); + if (ret < 0) + goto out; + + usb_osal_msleep(200); + + if (asix_class->chipcode == AX_AX88772B_CHIPCODE) { + ret = usbh_asix_write_cmd(asix_class, AX_QCTCTRL, 0x8000, 0x8001, NULL, 0); + if (ret < 0) { + USB_LOG_ERR("Write BQ setting failed: %d\r\n", ret); + goto out; + } + } else if (asix_class->chipcode == AX_AX88772A_CHIPCODE) { + /* Check if the PHY registers have default settings */ + phy14h = usbh_asix_mdio_read(asix_class, asix_class->phy_addr, + AX88772A_PHY14H); + phy15h = usbh_asix_mdio_read(asix_class, asix_class->phy_addr, + AX88772A_PHY15H); + phy16h = usbh_asix_mdio_read(asix_class, asix_class->phy_addr, + AX88772A_PHY16H); + + USB_LOG_DBG("772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\r\n", + phy14h, phy15h, phy16h); + + /* Restore PHY registers default setting if not */ + if (phy14h != AX88772A_PHY14H_DEFAULT) + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, + AX88772A_PHY14H, + AX88772A_PHY14H_DEFAULT); + if (phy15h != AX88772A_PHY15H_DEFAULT) + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, + AX88772A_PHY15H, + AX88772A_PHY15H_DEFAULT); + if (phy16h != AX88772A_PHY16H_DEFAULT) + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, + AX88772A_PHY16H, + AX88772A_PHY16H_DEFAULT); + } + + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_IPG0, + AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT, + AX88772_IPG2_DEFAULT, NULL, 0); + if (ret < 0) { + USB_LOG_ERR("Write IPG,IPG1,IPG2 failed: %d\r\n", ret); + goto out; + } + + /* Rewrite MAC address */ + ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_NODE_ID, 0, 0, asix_class->mac, ETH_ALEN); + if (ret < 0) + goto out; + + /* Set RX_CTL to default values with 2k buffer, and enable cactus */ + ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL); + if (ret < 0) + goto out; + + ret = usbh_asix_write_medium_mode(asix_class, AX88772_MEDIUM_DEFAULT); + if (ret < 0) + return ret; + + /* Set RX_CTL to default values with 2k buffer, and enable cactus */ + ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL); + if (ret < 0) + goto out; + + rx_ctl = usbh_asix_read_rx_ctl(asix_class); + USB_LOG_INFO("RX_CTL is 0x%04x after all initializations\r\n", rx_ctl); + + rx_ctl = usbh_asix_read_medium_status(asix_class); + USB_LOG_INFO("Medium Status is 0x%04x after all initializations\r\n", rx_ctl); + + return 0; + +out: + return ret; +} + +static void usbh_ax88772_mac_link_down(struct usbh_asix *asix_class) +{ + usbh_asix_write_medium_mode(asix_class, 0); +} + +static void usbh_ax88772_mac_link_up(struct usbh_asix *asix_class, int speed, int duplex, bool tx_pause, bool rx_pause) +{ + uint16_t m = AX_MEDIUM_AC | AX_MEDIUM_RE; + + m |= duplex ? AX_MEDIUM_FD : 0; + + switch (speed) { + case SPEED_100: + m |= AX_MEDIUM_PS; + break; + case SPEED_10: + break; + default: + return; + } + + if (tx_pause) + m |= AX_MEDIUM_TFC; + + if (rx_pause) + m |= AX_MEDIUM_RFC; + + usbh_asix_write_medium_mode(asix_class, m); +} + +static int usbh_asix_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + + struct usbh_asix *asix_class = &g_asix_class; + + memset(asix_class, 0, sizeof(struct usbh_asix)); + + asix_class->hport = hport; + asix_class->intf = intf; + + hport->config.intf[intf].priv = asix_class; + + if ((hport->device_desc.idVendor == 0x0b95) && (hport->device_desc.idProduct == 0x772b)) { + asix_class->name = "ASIX AX88772B"; + } else if ((hport->device_desc.idVendor == 0x0b95) && (hport->device_desc.idProduct == 0x7720)) { + asix_class->name = "ASIX AX88772"; + } else if ((hport->device_desc.idVendor == 0x0b95) && (hport->device_desc.idProduct == 0x1780)) { + asix_class->name = "ASIX AX88178"; + } + + for (uint8_t i = 0; i < (ETH_ALEN >> 1); i++) { + ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_EEPROM, + 0x04 + i, 0, &asix_class->mac[i * 2], 2); + if (ret < 0) { + return ret; + } + } + + USB_LOG_INFO("asix MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + asix_class->mac[0], + asix_class->mac[1], + asix_class->mac[2], + asix_class->mac[3], + asix_class->mac[4], + asix_class->mac[5]); + + ret = usbh_asix_read_phy_addr(asix_class, true); + if (ret < 0) { + USB_LOG_ERR("Failed to read phy addr: %d\r\n", ret); + return ret; + } + asix_class->phy_addr = ret; + asix_class->embd_phy = ((ret & 0x1f) == AX_EMBD_PHY_ADDR); + + ret = usbh_asix_read_cmd(asix_class, AX_CMD_STATMNGSTS_REG, 0, 0, &asix_class->chipcode, 1); + if (ret < 0) { + USB_LOG_ERR("Failed to read STATMNGSTS_REG: %d\r\n", ret); + return ret; + } + + asix_class->chipcode &= AX_CHIPCODE_MASK; + USB_LOG_INFO("asix chipcode 0x%x\r\n", asix_class->chipcode); + + if (asix_class->chipcode == AX_AX88772_CHIPCODE) { + usbh_ax88772_hw_reset(asix_class); + } else { + usbh_ax88772a_hw_reset(asix_class); + } + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(asix_class->intin, ep_desc); + } else { + return -USB_ERR_NOTSUPP; + } + } else { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(asix_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(asix_class->bulkout, ep_desc); + } + } + } + + if (asix_class->chipcode == AX_AX88772B_CHIPCODE) { + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0); + + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x8200); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0); + + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x3900); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0); + + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x3100); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 4); + + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 4, 0x01e1); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 1); + + usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x3300); + usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0); + } + + USB_LOG_INFO("Init %s done\r\n", asix_class->name); + + memcpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register ASIX Class:%s\r\n", hport->config.intf[intf].devname); + usbh_asix_run(asix_class); + return ret; +} + +static int usbh_asix_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_asix *asix_class = (struct usbh_asix *)hport->config.intf[intf].priv; + + if (asix_class) { + if (asix_class->bulkin) { + usbh_kill_urb(&asix_class->bulkin_urb); + } + + if (asix_class->bulkout) { + usbh_kill_urb(&asix_class->bulkout_urb); + } + + if (asix_class->intin) { + usbh_kill_urb(&asix_class->intin_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister ASIX Class:%s\r\n", hport->config.intf[intf].devname); + usbh_asix_stop(asix_class); + } + + memset(asix_class, 0, sizeof(struct usbh_asix)); + } + + return ret; +} + +int usbh_asix_get_connect_status(struct usbh_asix *asix_class) +{ + int ret; + + usbh_int_urb_fill(&asix_class->intin_urb, asix_class->hport, asix_class->intin, g_asix_inttx_buffer, 8, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&asix_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (g_asix_inttx_buffer[1] == 0x00) { + if (g_asix_inttx_buffer[2] & 0x01) { + asix_class->connect_status = true; + usbh_ax88772_mac_link_up(asix_class, SPEED_100, 1, 1, 1); + usbh_asix_set_multicast(asix_class); + } else { + asix_class->connect_status = false; + usbh_ax88772_mac_link_down(asix_class); + } + } + return 0; +} + +void usbh_asix_rx_thread(void *argument) +{ + uint32_t g_asix_rx_length; + int ret; + uint16_t len; + uint16_t len_crc; + + USB_LOG_INFO("Create asix rx thread\r\n"); + // clang-format off +find_class: + // clang-format on + g_asix_class.connect_status = false; + if (usbh_find_class_instance("/dev/asix") == NULL) { + goto delete; + } + + while (g_asix_class.connect_status == false) { + ret = usbh_asix_get_connect_status(&g_asix_class); + if (ret < 0) { + usb_osal_msleep(100); + goto find_class; + } + } + + g_asix_rx_length = 0; + while (1) { + usbh_bulk_urb_fill(&g_asix_class.bulkin_urb, g_asix_class.hport, g_asix_class.bulkin, &g_asix_rx_buffer[g_asix_rx_length], CONFIG_USBHOST_ASIX_ETH_MAX_SIZE, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_asix_class.bulkin_urb); + if (ret < 0) { + goto find_class; + } + + g_asix_rx_length += g_asix_class.bulkin_urb.actual_length; + + if (g_asix_rx_length % USB_GET_MAXPACKETSIZE(g_asix_class.bulkin->wMaxPacketSize)) { + len = ((uint16_t)g_asix_rx_buffer[0] | ((uint16_t)(g_asix_rx_buffer[1]) << 8)) & 0x7ff; + len_crc = g_asix_rx_buffer[2] | ((uint16_t)(g_asix_rx_buffer[3]) << 8); + + if (len != (~len_crc & 0x7ff)) { + USB_LOG_ERR("asix rx header error\r\n"); + continue; + } + + USB_LOG_DBG("rxlen:%d\r\n", g_asix_rx_length); + + uint8_t *buf = (uint8_t *)&g_asix_rx_buffer[4]; + usbh_asix_eth_input(buf, len); + g_asix_rx_length = 0; + } else { + if (g_asix_rx_length > CONFIG_USBHOST_ASIX_ETH_MAX_SIZE) { + USB_LOG_ERR("Rx packet is overflow\r\n"); + g_asix_rx_length = 0; + } + } + } + // clang-format off +delete: + USB_LOG_INFO("Delete asix rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +int usbh_asix_eth_output(uint8_t *buf, uint32_t buflen) +{ + uint16_t actual_len; + uint8_t *buffer; + + if (g_asix_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + buffer = &g_asix_tx_buffer[4]; + memcpy(buffer, buf, buflen); + + g_asix_tx_buffer[0] = buflen & 0xff; + g_asix_tx_buffer[1] = (buflen >> 8) & 0xff; + g_asix_tx_buffer[2] = ~g_asix_tx_buffer[0]; + g_asix_tx_buffer[3] = ~g_asix_tx_buffer[1]; + + if (!(buflen + 4) % USB_GET_MAXPACKETSIZE(g_asix_class.bulkout->wMaxPacketSize)) { + USB_LOG_DBG("txlen:%d\r\n", buflen + 8); + g_asix_tx_buffer[buflen + 4 + 0] = 0x00; + g_asix_tx_buffer[buflen + 4 + 1] = 0x00; + g_asix_tx_buffer[buflen + 4 + 2] = 0xff; + g_asix_tx_buffer[buflen + 4 + 3] = 0xff; + actual_len = buflen + 8; + } else { + USB_LOG_DBG("txlen:%d\r\n", buflen + 4); + actual_len = buflen + 4; + } + + usbh_bulk_urb_fill(&g_asix_class.bulkout_urb, g_asix_class.hport, g_asix_class.bulkout, g_asix_tx_buffer, actual_len, USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_asix_class.bulkout_urb); +} + +__WEAK void usbh_asix_run(struct usbh_asix *asix_class) +{ +} + +__WEAK void usbh_asix_stop(struct usbh_asix *asix_class) +{ +} + +static const uint16_t asix_id_table[][2] = { + { 0x0B95, 0x772B }, + { 0x0B95, 0x7720 }, + { 0, 0 }, +}; + +static const struct usbh_class_driver asix_class_driver = { + .driver_name = "asix", + .connect = usbh_asix_connect, + .disconnect = usbh_asix_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info asix_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .class = 0xff, + .subclass = 0x00, + .protocol = 0x00, + .id_table = asix_id_table, + .class_driver = &asix_class_driver +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.h b/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.h new file mode 100644 index 00000000000..9f34e570a68 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/net/usbh_asix.h @@ -0,0 +1,176 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_ASIX_H +#define USBH_ASIX_H + +/* ASIX AX8817X based USB 2.0 Ethernet Devices */ + +#define AX_CMD_SET_SW_MII 0x06 +#define AX_CMD_READ_MII_REG 0x07 +#define AX_CMD_WRITE_MII_REG 0x08 +#define AX_CMD_STATMNGSTS_REG 0x09 +#define AX_CMD_SET_HW_MII 0x0a +#define AX_CMD_READ_EEPROM 0x0b +#define AX_CMD_WRITE_EEPROM 0x0c +#define AX_CMD_WRITE_ENABLE 0x0d +#define AX_CMD_WRITE_DISABLE 0x0e +#define AX_CMD_READ_RX_CTL 0x0f +#define AX_CMD_WRITE_RX_CTL 0x10 +#define AX_CMD_READ_IPG012 0x11 +#define AX_CMD_WRITE_IPG0 0x12 +#define AX_CMD_WRITE_IPG1 0x13 +#define AX_CMD_READ_NODE_ID 0x13 +#define AX_CMD_WRITE_NODE_ID 0x14 +#define AX_CMD_WRITE_IPG2 0x14 +#define AX_CMD_WRITE_MULTI_FILTER 0x16 +#define AX88172_CMD_READ_NODE_ID 0x17 +#define AX_CMD_READ_PHY_ID 0x19 +#define AX_CMD_READ_MEDIUM_STATUS 0x1a +#define AX_CMD_WRITE_MEDIUM_MODE 0x1b +#define AX_CMD_READ_MONITOR_MODE 0x1c +#define AX_CMD_WRITE_MONITOR_MODE 0x1d +#define AX_CMD_READ_GPIOS 0x1e +#define AX_CMD_WRITE_GPIOS 0x1f +#define AX_CMD_SW_RESET 0x20 +#define AX_CMD_SW_PHY_STATUS 0x21 +#define AX_CMD_SW_PHY_SELECT 0x22 +#define AX_QCTCTRL 0x2A + +#define AX_CHIPCODE_MASK 0x70 +#define AX_AX88772_CHIPCODE 0x00 +#define AX_AX88772A_CHIPCODE 0x10 +#define AX_AX88772B_CHIPCODE 0x20 +#define AX_HOST_EN 0x01 + +#define AX_PHYSEL_PSEL 0x01 +#define AX_PHYSEL_SSMII 0 +#define AX_PHYSEL_SSEN 0x10 + +#define AX_PHY_SELECT_MASK (BIT(3) | BIT(2)) +#define AX_PHY_SELECT_INTERNAL 0 +#define AX_PHY_SELECT_EXTERNAL BIT(2) + +#define AX_MONITOR_MODE 0x01 +#define AX_MONITOR_LINK 0x02 +#define AX_MONITOR_MAGIC 0x04 +#define AX_MONITOR_HSFS 0x10 + +/* AX88172 Medium Status Register values */ +#define AX88172_MEDIUM_FD 0x02 +#define AX88172_MEDIUM_TX 0x04 +#define AX88172_MEDIUM_FC 0x10 +#define AX88172_MEDIUM_DEFAULT \ + (AX88172_MEDIUM_FD | AX88172_MEDIUM_TX | AX88172_MEDIUM_FC) + +#define AX_MCAST_FILTER_SIZE 8 +#define AX_MAX_MCAST 64 + +#define AX_SWRESET_CLEAR 0x00 +#define AX_SWRESET_RR 0x01 +#define AX_SWRESET_RT 0x02 +#define AX_SWRESET_PRTE 0x04 +#define AX_SWRESET_PRL 0x08 +#define AX_SWRESET_BZ 0x10 +#define AX_SWRESET_IPRL 0x20 +#define AX_SWRESET_IPPD 0x40 + +#define AX88772_IPG0_DEFAULT 0x15 +#define AX88772_IPG1_DEFAULT 0x0c +#define AX88772_IPG2_DEFAULT 0x12 + +/* AX88772 & AX88178 Medium Mode Register */ +#define AX_MEDIUM_PF 0x0080 +#define AX_MEDIUM_JFE 0x0040 +#define AX_MEDIUM_TFC 0x0020 +#define AX_MEDIUM_RFC 0x0010 +#define AX_MEDIUM_ENCK 0x0008 +#define AX_MEDIUM_AC 0x0004 +#define AX_MEDIUM_FD 0x0002 +#define AX_MEDIUM_GM 0x0001 +#define AX_MEDIUM_SM 0x1000 +#define AX_MEDIUM_SBP 0x0800 +#define AX_MEDIUM_PS 0x0200 +#define AX_MEDIUM_RE 0x0100 + +#define AX88178_MEDIUM_DEFAULT \ + (AX_MEDIUM_PS | AX_MEDIUM_FD | AX_MEDIUM_AC | \ + AX_MEDIUM_RFC | AX_MEDIUM_TFC | AX_MEDIUM_JFE | \ + AX_MEDIUM_RE) + +#define AX88772_MEDIUM_DEFAULT \ + (AX_MEDIUM_FD | AX_MEDIUM_PS | \ + AX_MEDIUM_AC | AX_MEDIUM_RE) + +/* AX88772 & AX88178 RX_CTL values */ +#define AX_RX_CTL_SO 0x0080 +#define AX_RX_CTL_AP 0x0020 +#define AX_RX_CTL_AM 0x0010 +#define AX_RX_CTL_AB 0x0008 +#define AX_RX_CTL_SEP 0x0004 +#define AX_RX_CTL_AMALL 0x0002 +#define AX_RX_CTL_PRO 0x0001 +#define AX_RX_CTL_MFB_2048 0x0000 +#define AX_RX_CTL_MFB_4096 0x0100 +#define AX_RX_CTL_MFB_8192 0x0200 +#define AX_RX_CTL_MFB_16384 0x0300 + +#define AX_DEFAULT_RX_CTL (AX_RX_CTL_SO | AX_RX_CTL_AB) + +/* GPIO 0 .. 2 toggles */ +#define AX_GPIO_GPO0EN 0x01 /* GPIO0 Output enable */ +#define AX_GPIO_GPO_0 0x02 /* GPIO0 Output value */ +#define AX_GPIO_GPO1EN 0x04 /* GPIO1 Output enable */ +#define AX_GPIO_GPO_1 0x08 /* GPIO1 Output value */ +#define AX_GPIO_GPO2EN 0x10 /* GPIO2 Output enable */ +#define AX_GPIO_GPO_2 0x20 /* GPIO2 Output value */ +#define AX_GPIO_RESERVED 0x40 /* Reserved */ +#define AX_GPIO_RSE 0x80 /* Reload serial EEPROM */ + +#define AX_EEPROM_MAGIC 0xdeadbeef +#define AX_EEPROM_LEN 0x200 + +#define AX_EMBD_PHY_ADDR 0x10 + +struct usbh_asix { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usb_endpoint_descriptor *intin; /* INTR IN endpoint */ + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + struct usbh_urb intin_urb; + + uint8_t intf; + char *name; + uint8_t phy_addr; + uint8_t embd_phy; + uint8_t chipcode; + uint16_t mac_capabilities; + + bool connect_status; + uint8_t mac[6]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_asix_get_connect_status(struct usbh_asix *asix_class); + +void usbh_asix_run(struct usbh_asix *asix_class); +void usbh_asix_stop(struct usbh_asix *asix_class); + +int usbh_asix_eth_output(uint8_t *buf, uint32_t buflen); +void usbh_asix_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_asix_rx_thread(void *argument); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_ASIX_H */ \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c b/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c new file mode 100644 index 00000000000..3bd68a1dfdf --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.c @@ -0,0 +1,2249 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_rtl8152.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "rtl8152" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/rtl8152" + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_rx_buffer[CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_tx_buffer[CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_inttx_buffer[2]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rtl8152_buf[32]; + +static struct usbh_rtl8152 g_rtl8152_class; + +#define RTL8152_REQ_GET_REGS 0x05 +#define RTL8152_REQ_SET_REGS 0x05 + +#define BYTE_EN_DWORD 0xff +#define BYTE_EN_WORD 0x33 +#define BYTE_EN_BYTE 0x11 +#define BYTE_EN_SIX_BYTES 0x3f +#define BYTE_EN_START_MASK 0x0f +#define BYTE_EN_END_MASK 0xf0 + +#define MCU_TYPE_PLA 0x0100 +#define MCU_TYPE_USB 0x0000 + +/* Define these values to match your device */ +#define VENDOR_ID_REALTEK 0x0bda +#define VENDOR_ID_MICROSOFT 0x045e +#define VENDOR_ID_SAMSUNG 0x04e8 +#define VENDOR_ID_LENOVO 0x17ef +#define VENDOR_ID_LINKSYS 0x13b1 +#define VENDOR_ID_NVIDIA 0x0955 +#define VENDOR_ID_TPLINK 0x2357 +#define VENDOR_ID_DLINK 0x2001 +#define VENDOR_ID_ASUS 0x0b05 + +#define R8152_PHY_ID 32 + +#define PLA_IDR 0xc000 +#define PLA_RCR 0xc010 +#define PLA_RCR1 0xc012 +#define PLA_RMS 0xc016 +#define PLA_RXFIFO_CTRL0 0xc0a0 +#define PLA_RXFIFO_FULL 0xc0a2 +#define PLA_RXFIFO_CTRL1 0xc0a4 +#define PLA_RX_FIFO_FULL 0xc0a6 +#define PLA_RXFIFO_CTRL2 0xc0a8 +#define PLA_RX_FIFO_EMPTY 0xc0aa +#define PLA_DMY_REG0 0xc0b0 +#define PLA_FMC 0xc0b4 +#define PLA_CFG_WOL 0xc0b6 +#define PLA_TEREDO_CFG 0xc0bc +#define PLA_TEREDO_WAKE_BASE 0xc0c4 +#define PLA_MAR 0xcd00 +#define PLA_BACKUP 0xd000 +#define PLA_BDC_CR 0xd1a0 +#define PLA_TEREDO_TIMER 0xd2cc +#define PLA_REALWOW_TIMER 0xd2e8 +#define PLA_UPHY_TIMER 0xd388 +#define PLA_SUSPEND_FLAG 0xd38a +#define PLA_INDICATE_FALG 0xd38c +#define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */ +#define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */ +#define PLA_EXTRA_STATUS 0xd398 +#define PLA_GPHY_CTRL 0xd3ae +#define PLA_POL_GPIO_CTRL 0xdc6a +#define PLA_EFUSE_DATA 0xdd00 +#define PLA_EFUSE_CMD 0xdd02 +#define PLA_LEDSEL 0xdd90 +#define PLA_LED_FEATURE 0xdd92 +#define PLA_PHYAR 0xde00 +#define PLA_BOOT_CTRL 0xe004 +#define PLA_LWAKE_CTRL_REG 0xe007 +#define PLA_GPHY_INTR_IMR 0xe022 +#define PLA_EEE_CR 0xe040 +#define PLA_EEE_TXTWSYS 0xe04c +#define PLA_EEE_TXTWSYS_2P5G 0xe058 +#define PLA_EEEP_CR 0xe080 +#define PLA_MAC_PWR_CTRL 0xe0c0 +#define PLA_MAC_PWR_CTRL2 0xe0ca +#define PLA_MAC_PWR_CTRL3 0xe0cc +#define PLA_MAC_PWR_CTRL4 0xe0ce +#define PLA_WDT6_CTRL 0xe428 +#define PLA_TCR0 0xe610 +#define PLA_TCR1 0xe612 +#define PLA_MTPS 0xe615 +#define PLA_TXFIFO_CTRL 0xe618 +#define PLA_TXFIFO_FULL 0xe61a +#define PLA_RSTTALLY 0xe800 +#define PLA_CR 0xe813 +#define PLA_CRWECR 0xe81c +#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ +#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ +#define PLA_CONFIG5 0xe822 +#define PLA_PHY_PWR 0xe84c +#define PLA_OOB_CTRL 0xe84f +#define PLA_CPCR 0xe854 +#define PLA_MISC_0 0xe858 +#define PLA_MISC_1 0xe85a +#define PLA_OCP_GPHY_BASE 0xe86c +#define PLA_TALLYCNT 0xe890 +#define PLA_SFF_STS_7 0xe8de +#define PLA_PHYSTATUS 0xe908 +#define PLA_CONFIG6 0xe90a /* CONFIG6 */ +#define PLA_USB_CFG 0xe952 +#define PLA_BP_BA 0xfc26 +#define PLA_BP_0 0xfc28 +#define PLA_BP_1 0xfc2a +#define PLA_BP_2 0xfc2c +#define PLA_BP_3 0xfc2e +#define PLA_BP_4 0xfc30 +#define PLA_BP_5 0xfc32 +#define PLA_BP_6 0xfc34 +#define PLA_BP_7 0xfc36 +#define PLA_BP_EN 0xfc38 + +#define USB_USB2PHY 0xb41e +#define USB_SSPHYLINK1 0xb426 +#define USB_SSPHYLINK2 0xb428 +#define USB_L1_CTRL 0xb45e +#define USB_U2P3_CTRL 0xb460 +#define USB_CSR_DUMMY1 0xb464 +#define USB_CSR_DUMMY2 0xb466 +#define USB_DEV_STAT 0xb808 +#define USB_CONNECT_TIMER 0xcbf8 +#define USB_MSC_TIMER 0xcbfc +#define USB_BURST_SIZE 0xcfc0 +#define USB_FW_FIX_EN0 0xcfca +#define USB_FW_FIX_EN1 0xcfcc +#define USB_LPM_CONFIG 0xcfd8 +#define USB_ECM_OPTION 0xcfee +#define USB_CSTMR 0xcfef /* RTL8153A */ +#define USB_MISC_2 0xcfff +#define USB_ECM_OP 0xd26b +#define USB_GPHY_CTRL 0xd284 +#define USB_SPEED_OPTION 0xd32a +#define USB_FW_CTRL 0xd334 /* RTL8153B */ +#define USB_FC_TIMER 0xd340 +#define USB_USB_CTRL 0xd406 +#define USB_PHY_CTRL 0xd408 +#define USB_TX_AGG 0xd40a +#define USB_RX_BUF_TH 0xd40c +#define USB_USB_TIMER 0xd428 +#define USB_RX_EARLY_TIMEOUT 0xd42c +#define USB_RX_EARLY_SIZE 0xd42e +#define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ +#define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ +#define USB_TX_DMA 0xd434 +#define USB_UPT_RXDMA_OWN 0xd437 +#define USB_UPHY3_MDCMDIO 0xd480 +#define USB_TOLERANCE 0xd490 +#define USB_LPM_CTRL 0xd41a +#define USB_BMU_RESET 0xd4b0 +#define USB_BMU_CONFIG 0xd4b4 +#define USB_U1U2_TIMER 0xd4da +#define USB_FW_TASK 0xd4e8 /* RTL8153B */ +#define USB_RX_AGGR_NUM 0xd4ee +#define USB_UPS_CTRL 0xd800 +#define USB_POWER_CUT 0xd80a +#define USB_MISC_0 0xd81a +#define USB_MISC_1 0xd81f +#define USB_AFE_CTRL2 0xd824 +#define USB_UPHY_XTAL 0xd826 +#define USB_UPS_CFG 0xd842 +#define USB_UPS_FLAGS 0xd848 +#define USB_WDT1_CTRL 0xe404 +#define USB_WDT11_CTRL 0xe43c +#define USB_BP_BA PLA_BP_BA +#define USB_BP_0 PLA_BP_0 +#define USB_BP_1 PLA_BP_1 +#define USB_BP_2 PLA_BP_2 +#define USB_BP_3 PLA_BP_3 +#define USB_BP_4 PLA_BP_4 +#define USB_BP_5 PLA_BP_5 +#define USB_BP_6 PLA_BP_6 +#define USB_BP_7 PLA_BP_7 +#define USB_BP_EN PLA_BP_EN /* RTL8153A */ +#define USB_BP_8 0xfc38 /* RTL8153B */ +#define USB_BP_9 0xfc3a +#define USB_BP_10 0xfc3c +#define USB_BP_11 0xfc3e +#define USB_BP_12 0xfc40 +#define USB_BP_13 0xfc42 +#define USB_BP_14 0xfc44 +#define USB_BP_15 0xfc46 +#define USB_BP2_EN 0xfc48 + +/* OCP Registers */ +#define OCP_ALDPS_CONFIG 0x2010 +#define OCP_EEE_CONFIG1 0x2080 +#define OCP_EEE_CONFIG2 0x2092 +#define OCP_EEE_CONFIG3 0x2094 +#define OCP_BASE_MII 0xa400 +#define OCP_EEE_AR 0xa41a +#define OCP_EEE_DATA 0xa41c +#define OCP_PHY_STATUS 0xa420 +#define OCP_INTR_EN 0xa424 +#define OCP_NCTL_CFG 0xa42c +#define OCP_POWER_CFG 0xa430 +#define OCP_EEE_CFG 0xa432 +#define OCP_SRAM_ADDR 0xa436 +#define OCP_SRAM_DATA 0xa438 +#define OCP_DOWN_SPEED 0xa442 +#define OCP_EEE_ABLE 0xa5c4 +#define OCP_EEE_ADV 0xa5d0 +#define OCP_EEE_LPABLE 0xa5d2 +#define OCP_10GBT_CTRL 0xa5d4 +#define OCP_10GBT_STAT 0xa5d6 +#define OCP_EEE_ADV2 0xa6d4 +#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ +#define OCP_PHY_PATCH_STAT 0xb800 +#define OCP_PHY_PATCH_CMD 0xb820 +#define OCP_PHY_LOCK 0xb82e +#define OCP_ADC_IOFFSET 0xbcfc +#define OCP_ADC_CFG 0xbc06 +#define OCP_SYSCLK_CFG 0xc416 + +/* SRAM Register */ +#define SRAM_GREEN_CFG 0x8011 +#define SRAM_LPF_CFG 0x8012 +#define SRAM_GPHY_FW_VER 0x801e +#define SRAM_10M_AMP1 0x8080 +#define SRAM_10M_AMP2 0x8082 +#define SRAM_IMPEDANCE 0x8084 +#define SRAM_PHY_LOCK 0xb82e + +/* PLA_RCR */ +#define RCR_AAP 0x00000001 +#define RCR_APM 0x00000002 +#define RCR_AM 0x00000004 +#define RCR_AB 0x00000008 +#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) +#define SLOT_EN BIT(11) + +/* PLA_RCR1 */ +#define OUTER_VLAN BIT(7) +#define INNER_VLAN BIT(6) + +/* PLA_RXFIFO_CTRL0 */ +#define RXFIFO_THR1_NORMAL 0x00080002 +#define RXFIFO_THR1_OOB 0x01800003 + +/* PLA_RXFIFO_FULL */ +#define RXFIFO_FULL_MASK 0xfff + +/* PLA_RXFIFO_CTRL1 */ +#define RXFIFO_THR2_FULL 0x00000060 +#define RXFIFO_THR2_HIGH 0x00000038 +#define RXFIFO_THR2_OOB 0x0000004a +#define RXFIFO_THR2_NORMAL 0x00a0 + +/* PLA_RXFIFO_CTRL2 */ +#define RXFIFO_THR3_FULL 0x00000078 +#define RXFIFO_THR3_HIGH 0x00000048 +#define RXFIFO_THR3_OOB 0x0000005a +#define RXFIFO_THR3_NORMAL 0x0110 + +/* PLA_TXFIFO_CTRL */ +#define TXFIFO_THR_NORMAL 0x00400008 +#define TXFIFO_THR_NORMAL2 0x01000008 + +/* PLA_DMY_REG0 */ +#define ECM_ALDPS 0x0002 + +/* PLA_FMC */ +#define FMC_FCR_MCU_EN 0x0001 + +/* PLA_EEEP_CR */ +#define EEEP_CR_EEEP_TX 0x0002 + +/* PLA_WDT6_CTRL */ +#define WDT6_SET_MODE 0x0010 + +/* PLA_TCR0 */ +#define TCR0_TX_EMPTY 0x0800 +#define TCR0_AUTO_FIFO 0x0080 + +/* PLA_TCR1 */ +#define VERSION_MASK 0x7cf0 +#define IFG_MASK (BIT(3) | BIT(9) | BIT(8)) +#define IFG_144NS BIT(9) +#define IFG_96NS (BIT(9) | BIT(8)) + +/* PLA_MTPS */ +#define MTPS_JUMBO (12 * 1024 / 64) +#define MTPS_DEFAULT (6 * 1024 / 64) + +/* PLA_RSTTALLY */ +#define TALLY_RESET 0x0001 + +/* PLA_CR */ +#define CR_RST 0x10 +#define CR_RE 0x08 +#define CR_TE 0x04 + +/* PLA_CRWECR */ +#define CRWECR_NORAML 0x00 +#define CRWECR_CONFIG 0xc0 + +/* PLA_OOB_CTRL */ +#define NOW_IS_OOB 0x80 +#define TXFIFO_EMPTY 0x20 +#define RXFIFO_EMPTY 0x10 +#define LINK_LIST_READY 0x02 +#define DIS_MCU_CLROOB 0x01 +#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) + +/* PLA_MISC_1 */ +#define RXDY_GATED_EN 0x0008 + +/* PLA_SFF_STS_7 */ +#define RE_INIT_LL 0x8000 +#define MCU_BORW_EN 0x4000 + +/* PLA_CPCR */ +#define FLOW_CTRL_EN BIT(0) +#define CPCR_RX_VLAN 0x0040 + +/* PLA_CFG_WOL */ +#define MAGIC_EN 0x0001 + +/* PLA_TEREDO_CFG */ +#define TEREDO_SEL 0x8000 +#define TEREDO_WAKE_MASK 0x7f00 +#define TEREDO_RS_EVENT_MASK 0x00fe +#define OOB_TEREDO_EN 0x0001 + +/* PLA_BDC_CR */ +#define ALDPS_PROXY_MODE 0x0001 + +/* PLA_EFUSE_CMD */ +#define EFUSE_READ_CMD BIT(15) +#define EFUSE_DATA_BIT16 BIT(7) + +/* PLA_CONFIG34 */ +#define LINK_ON_WAKE_EN 0x0010 +#define LINK_OFF_WAKE_EN 0x0008 + +/* PLA_CONFIG6 */ +#define LANWAKE_CLR_EN BIT(0) + +/* PLA_USB_CFG */ +#define EN_XG_LIP BIT(1) +#define EN_G_LIP BIT(2) + +/* PLA_CONFIG5 */ +#define BWF_EN 0x0040 +#define MWF_EN 0x0020 +#define UWF_EN 0x0010 +#define LAN_WAKE_EN 0x0002 + +/* PLA_LED_FEATURE */ +#define LED_MODE_MASK 0x0700 + +/* PLA_PHY_PWR */ +#define TX_10M_IDLE_EN 0x0080 +#define PFM_PWM_SWITCH 0x0040 +#define TEST_IO_OFF BIT(4) + +/* PLA_MAC_PWR_CTRL */ +#define D3_CLK_GATED_EN 0x00004000 +#define MCU_CLK_RATIO 0x07010f07 +#define MCU_CLK_RATIO_MASK 0x0f0f0f0f +#define ALDPS_SPDWN_RATIO 0x0f87 + +/* PLA_MAC_PWR_CTRL2 */ +#define EEE_SPDWN_RATIO 0x8007 +#define MAC_CLK_SPDWN_EN BIT(15) +#define EEE_SPDWN_RATIO_MASK 0xff + +/* PLA_MAC_PWR_CTRL3 */ +#define PLA_MCU_SPDWN_EN BIT(14) +#define PKT_AVAIL_SPDWN_EN 0x0100 +#define SUSPEND_SPDWN_EN 0x0004 +#define U1U2_SPDWN_EN 0x0002 +#define L1_SPDWN_EN 0x0001 + +/* PLA_MAC_PWR_CTRL4 */ +#define PWRSAVE_SPDWN_EN 0x1000 +#define RXDV_SPDWN_EN 0x0800 +#define TX10MIDLE_EN 0x0100 +#define IDLE_SPDWN_EN BIT(6) +#define TP100_SPDWN_EN 0x0020 +#define TP500_SPDWN_EN 0x0010 +#define TP1000_SPDWN_EN 0x0008 +#define EEE_SPDWN_EN 0x0001 + +/* PLA_GPHY_INTR_IMR */ +#define GPHY_STS_MSK 0x0001 +#define SPEED_DOWN_MSK 0x0002 +#define SPDWN_RXDV_MSK 0x0004 +#define SPDWN_LINKCHG_MSK 0x0008 + +/* PLA_PHYAR */ +#define PHYAR_FLAG 0x80000000 + +/* PLA_EEE_CR */ +#define EEE_RX_EN 0x0001 +#define EEE_TX_EN 0x0002 + +/* PLA_BOOT_CTRL */ +#define AUTOLOAD_DONE 0x0002 + +/* PLA_LWAKE_CTRL_REG */ +#define LANWAKE_PIN BIT(7) + +/* PLA_SUSPEND_FLAG */ +#define LINK_CHG_EVENT BIT(0) + +/* PLA_INDICATE_FALG */ +#define UPCOMING_RUNTIME_D3 BIT(0) + +/* PLA_MACDBG_PRE and PLA_MACDBG_POST */ +#define DEBUG_OE BIT(0) +#define DEBUG_LTSSM 0x0082 + +/* PLA_EXTRA_STATUS */ +#define CUR_LINK_OK BIT(15) +#define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */ +#define LINK_CHANGE_FLAG BIT(8) +#define POLL_LINK_CHG BIT(0) + +/* PLA_GPHY_CTRL */ +#define GPHY_FLASH BIT(1) + +/* PLA_POL_GPIO_CTRL */ +#define DACK_DET_EN BIT(15) +#define POL_GPHY_PATCH BIT(4) + +/* USB_USB2PHY */ +#define USB2PHY_SUSPEND 0x0001 +#define USB2PHY_L1 0x0002 + +/* USB_SSPHYLINK1 */ +#define DELAY_PHY_PWR_CHG BIT(1) + +/* USB_SSPHYLINK2 */ +#define pwd_dn_scale_mask 0x3ffe +#define pwd_dn_scale(x) ((x) << 1) + +/* USB_CSR_DUMMY1 */ +#define DYNAMIC_BURST 0x0001 + +/* USB_CSR_DUMMY2 */ +#define EP4_FULL_FC 0x0001 + +/* USB_DEV_STAT */ +#define STAT_SPEED_MASK 0x0006 +#define STAT_SPEED_HIGH 0x0000 +#define STAT_SPEED_FULL 0x0002 + +/* USB_FW_FIX_EN0 */ +#define FW_FIX_SUSPEND BIT(14) + +/* USB_FW_FIX_EN1 */ +#define FW_IP_RESET_EN BIT(9) + +/* USB_LPM_CONFIG */ +#define LPM_U1U2_EN BIT(0) + +/* USB_TX_AGG */ +#define TX_AGG_MAX_THRESHOLD 0x03 + +/* USB_RX_BUF_TH */ +#define RX_THR_SUPPER 0x0c350180 +#define RX_THR_HIGH 0x7a120180 +#define RX_THR_SLOW 0xffff0180 +#define RX_THR_B 0x00010001 + +/* USB_TX_DMA */ +#define TEST_MODE_DISABLE 0x00000001 +#define TX_SIZE_ADJUST1 0x00000100 + +/* USB_BMU_RESET */ +#define BMU_RESET_EP_IN 0x01 +#define BMU_RESET_EP_OUT 0x02 + +/* USB_BMU_CONFIG */ +#define ACT_ODMA BIT(1) + +/* USB_UPT_RXDMA_OWN */ +#define OWN_UPDATE BIT(0) +#define OWN_CLEAR BIT(1) + +/* USB_FW_TASK */ +#define FC_PATCH_TASK BIT(1) + +/* USB_RX_AGGR_NUM */ +#define RX_AGGR_NUM_MASK 0x1ff + +/* USB_UPS_CTRL */ +#define POWER_CUT 0x0100 + +/* USB_PM_CTRL_STATUS */ +#define RESUME_INDICATE 0x0001 + +/* USB_ECM_OPTION */ +#define BYPASS_MAC_RESET BIT(5) + +/* USB_CSTMR */ +#define FORCE_SUPER BIT(0) + +/* USB_MISC_2 */ +#define UPS_FORCE_PWR_DOWN BIT(0) + +/* USB_ECM_OP */ +#define EN_ALL_SPEED BIT(0) + +/* USB_GPHY_CTRL */ +#define GPHY_PATCH_DONE BIT(2) +#define BYPASS_FLASH BIT(5) +#define BACKUP_RESTRORE BIT(6) + +/* USB_SPEED_OPTION */ +#define RG_PWRDN_EN BIT(8) +#define ALL_SPEED_OFF BIT(9) + +/* USB_FW_CTRL */ +#define FLOW_CTRL_PATCH_OPT BIT(1) +#define AUTO_SPEEDUP BIT(3) +#define FLOW_CTRL_PATCH_2 BIT(8) + +/* USB_FC_TIMER */ +#define CTRL_TIMER_EN BIT(15) + +/* USB_USB_CTRL */ +#define CDC_ECM_EN BIT(3) +#define RX_AGG_DISABLE 0x0010 +#define RX_ZERO_EN 0x0080 + +/* USB_U2P3_CTRL */ +#define U2P3_ENABLE 0x0001 +#define RX_DETECT8 BIT(3) + +/* USB_POWER_CUT */ +#define PWR_EN 0x0001 +#define PHASE2_EN 0x0008 +#define UPS_EN BIT(4) +#define USP_PREWAKE BIT(5) + +/* USB_MISC_0 */ +#define PCUT_STATUS 0x0001 + +/* USB_RX_EARLY_TIMEOUT */ +#define COALESCE_SUPER 85000U +#define COALESCE_HIGH 250000U +#define COALESCE_SLOW 524280U + +/* USB_WDT1_CTRL */ +#define WTD1_EN BIT(0) + +/* USB_WDT11_CTRL */ +#define TIMER11_EN 0x0001 + +/* USB_LPM_CTRL */ +/* bit 4 ~ 5: fifo empty boundary */ +#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ +/* bit 2 ~ 3: LMP timer */ +#define LPM_TIMER_MASK 0x0c +#define LPM_TIMER_500MS 0x04 /* 500 ms */ +#define LPM_TIMER_500US 0x0c /* 500 us */ +#define ROK_EXIT_LPM 0x02 + +/* USB_AFE_CTRL2 */ +#define SEN_VAL_MASK 0xf800 +#define SEN_VAL_NORMAL 0xa000 +#define SEL_RXIDLE 0x0100 + +/* USB_UPHY_XTAL */ +#define OOBS_POLLING BIT(8) + +/* USB_UPS_CFG */ +#define SAW_CNT_1MS_MASK 0x0fff +#define MID_REVERSE BIT(5) /* RTL8156A */ + +/* USB_UPS_FLAGS */ +#define UPS_FLAGS_R_TUNE BIT(0) +#define UPS_FLAGS_EN_10M_CKDIV BIT(1) +#define UPS_FLAGS_250M_CKDIV BIT(2) +#define UPS_FLAGS_EN_ALDPS BIT(3) +#define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) +#define UPS_FLAGS_SPEED_MASK (0xf << 16) +#define ups_flags_speed(x) ((x) << 16) +#define UPS_FLAGS_EN_EEE BIT(20) +#define UPS_FLAGS_EN_500M_EEE BIT(21) +#define UPS_FLAGS_EN_EEE_CKDIV BIT(22) +#define UPS_FLAGS_EEE_PLLOFF_100 BIT(23) +#define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) +#define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) +#define UPS_FLAGS_EN_GREEN BIT(26) +#define UPS_FLAGS_EN_FLOW_CTR BIT(27) + +enum spd_duplex { + NWAY_10M_HALF, + NWAY_10M_FULL, + NWAY_100M_HALF, + NWAY_100M_FULL, + NWAY_1000M_FULL, + FORCE_10M_HALF, + FORCE_10M_FULL, + FORCE_100M_HALF, + FORCE_100M_FULL, + FORCE_1000M_FULL, + NWAY_2500M_FULL, +}; + +/* OCP_ALDPS_CONFIG */ +#define ENPWRSAVE 0x8000 +#define ENPDNPS 0x0200 +#define LINKENA 0x0100 +#define DIS_SDSAVE 0x0010 + +/* OCP_PHY_STATUS */ +#define PHY_STAT_MASK 0x0007 +#define PHY_STAT_EXT_INIT 2 +#define PHY_STAT_LAN_ON 3 +#define PHY_STAT_PWRDN 5 + +/* OCP_INTR_EN */ +#define INTR_SPEED_FORCE BIT(3) + +/* OCP_NCTL_CFG */ +#define PGA_RETURN_EN BIT(1) + +/* OCP_POWER_CFG */ +#define EEE_CLKDIV_EN 0x8000 +#define EN_ALDPS 0x0004 +#define EN_10M_PLLOFF 0x0001 + +/* OCP_EEE_CONFIG1 */ +#define RG_TXLPI_MSK_HFDUP 0x8000 +#define RG_MATCLR_EN 0x4000 +#define EEE_10_CAP 0x2000 +#define EEE_NWAY_EN 0x1000 +#define TX_QUIET_EN 0x0200 +#define RX_QUIET_EN 0x0100 +#define sd_rise_time_mask 0x0070 +#define sd_rise_time(x) (MIN(x, 7) << 4) /* bit 4 ~ 6 */ +#define RG_RXLPI_MSK_HFDUP 0x0008 +#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ + +/* OCP_EEE_CONFIG2 */ +#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ +#define RG_DACQUIET_EN 0x0400 +#define RG_LDVQUIET_EN 0x0200 +#define RG_CKRSEL 0x0020 +#define RG_EEEPRG_EN 0x0010 + +/* OCP_EEE_CONFIG3 */ +#define fast_snr_mask 0xff80 +#define fast_snr(x) (MIN(x, 0x1ff) << 7) /* bit 7 ~ 15 */ +#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ +#define MSK_PH 0x0006 /* bit 0 ~ 3 */ + +/* OCP_EEE_AR */ +/* bit[15:14] function */ +#define FUN_ADDR 0x0000 +#define FUN_DATA 0x4000 +/* bit[4:0] device addr */ + +/* OCP_EEE_CFG */ +#define CTAP_SHORT_EN 0x0040 +#define EEE10_EN 0x0010 + +/* OCP_DOWN_SPEED */ +#define EN_EEE_CMODE BIT(14) +#define EN_EEE_1000 BIT(13) +#define EN_EEE_100 BIT(12) +#define EN_10M_CLKDIV BIT(11) +#define EN_10M_BGOFF 0x0080 + +/* OCP_10GBT_CTRL */ +#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */ + +/* OCP_PHY_STATE */ +#define TXDIS_STATE 0x01 +#define ABD_STATE 0x02 + +/* OCP_PHY_PATCH_STAT */ +#define PATCH_READY BIT(6) + +/* OCP_PHY_PATCH_CMD */ +#define PATCH_REQUEST BIT(4) + +/* OCP_PHY_LOCK */ +#define PATCH_LOCK BIT(0) + +/* OCP_ADC_CFG */ +#define CKADSEL_L 0x0100 +#define ADC_EN 0x0080 +#define EN_EMI_L 0x0040 + +/* OCP_SYSCLK_CFG */ +#define sysclk_div_expo(x) (MIN(x, 5) << 8) +#define clk_div_expo(x) (MIN(x, 5) << 4) + +/* SRAM_GREEN_CFG */ +#define GREEN_ETH_EN BIT(15) +#define R_TUNE_EN BIT(11) + +/* SRAM_LPF_CFG */ +#define LPF_AUTO_TUNE 0x8000 + +/* SRAM_10M_AMP1 */ +#define GDAC_IB_UPALL 0x0008 + +/* SRAM_10M_AMP2 */ +#define AMP_DN 0x0200 + +/* SRAM_IMPEDANCE */ +#define RX_DRIVING_MASK 0x6000 + +/* SRAM_PHY_LOCK */ +#define PHY_PATCH_LOCK 0x0001 + +/* MAC PASSTHRU */ +#define AD_MASK 0xfee0 +#define BND_MASK 0x0004 +#define BD_MASK 0x0001 +#define EFUSE 0xcfdb +#define PASS_THRU_MASK 0x1 + +#define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */ + +enum rtl_register_content { + _2500bps = BIT(10), + _1250bps = BIT(9), + _500bps = BIT(8), + _tx_flow = BIT(6), + _rx_flow = BIT(5), + _1000bps = 0x10, + _100bps = 0x08, + _10bps = 0x04, + LINK_STATUS = 0x02, + FULL_DUP = 0x01, +}; + +#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS)) +#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow)) + +#define RTL8152_MAX_TX 4 +#define RTL8152_MAX_RX 10 +#define INTBUFSIZE 2 +#define TX_ALIGN 4 +#define RX_ALIGN 8 + +#define RTL8152_RX_MAX_PENDING 4096 +#define RTL8152_RXFG_HEADSZ 256 + +#define INTR_LINK 0x0004 + +#define VLAN_ETH_HLEN 18 +#define ETH_FCS_LEN 4 +#define VLAN_ETH_FRAME_LEN 1514 + +#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) +#define RTL8153_RMS RTL8153_MAX_PACKET +#define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN) +#define size_to_mtu(s) ((s)-VLAN_ETH_HLEN - ETH_FCS_LEN) +#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN) + +struct rx_desc { + uint32_t opts1; +#define RD_CRC BIT(15) +#define RX_LEN_MASK 0x7fff + + uint32_t opts2; +#define RD_UDP_CS BIT(23) +#define RD_TCP_CS BIT(22) +#define RD_IPV6_CS BIT(20) +#define RD_IPV4_CS BIT(19) + + uint32_t opts3; +#define IPF BIT(23) /* IP checksum fail */ +#define UDPF BIT(22) /* UDP checksum fail */ +#define TCPF BIT(21) /* TCP checksum fail */ +#define RX_VLAN_TAG BIT(16) + + uint32_t opts4; + uint32_t opts5; + uint32_t opts6; +}; + +struct tx_desc { + uint32_t opts1; +#define TX_FS BIT(31) /* First segment of a packet */ +#define TX_LS BIT(30) /* Final segment of a packet */ +#define LGSEND BIT(29) +#define GTSENDV4 BIT(28) +#define GTSENDV6 BIT(27) +#define GTTCPHO_SHIFT 18 +#define GTTCPHO_MAX 0x7fU +#define TX_LEN_MAX 0x3ffffU + + uint32_t opts2; +#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ +#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ +#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ +#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ +#define MSS_SHIFT 17 +#define MSS_MAX 0x7ffU +#define TCPHO_SHIFT 17 +#define TCPHO_MAX 0x7ffU +#define TX_VLAN_TAG BIT(16) +}; + +enum rtl_version { + RTL_VER_UNKNOWN = 0, + RTL_VER_01, + RTL_VER_02, + RTL_VER_03, + RTL_VER_04, + RTL_VER_05, + RTL_VER_06, + RTL_VER_07, + RTL_VER_08, + RTL_VER_09, + + RTL_TEST_01, + RTL_VER_10, + RTL_VER_11, + RTL_VER_12, + RTL_VER_13, + RTL_VER_14, + RTL_VER_15, + + RTL_VER_MAX +}; + +/* mii.h */ +/* Generic MII registers. */ +#define MII_BMCR 0x00 /* Basic mode control register */ +#define MII_BMSR 0x01 /* Basic mode status register */ +#define MII_PHYSID1 0x02 /* PHYS ID 1 */ +#define MII_PHYSID2 0x03 /* PHYS ID 2 */ +#define MII_ADVERTISE 0x04 /* Advertisement control reg */ +#define MII_LPA 0x05 /* Link partner ability reg */ +#define MII_EXPANSION 0x06 /* Expansion register */ +#define MII_CTRL1000 0x09 /* 1000BASE-T control */ +#define MII_STAT1000 0x0a /* 1000BASE-T status */ +#define MII_MMD_CTRL 0x0d /* MMD Access Control Register */ +#define MII_MMD_DATA 0x0e /* MMD Access Data Register */ +#define MII_ESTATUS 0x0f /* Extended Status */ +#define MII_DCOUNTER 0x12 /* Disconnect counter */ +#define MII_FCSCOUNTER 0x13 /* False carrier counter */ +#define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ +#define MII_RERRCOUNTER 0x15 /* Receive error counter */ +#define MII_SREVISION 0x16 /* Silicon revision */ +#define MII_RESV1 0x17 /* Reserved... */ +#define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ +#define MII_PHYADDR 0x19 /* PHY address */ +#define MII_RESV2 0x1a /* Reserved... */ +#define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ +#define MII_NCONFIG 0x1c /* Network interface config */ + +/* Basic mode control register. */ +#define BMCR_RESV 0x003f /* Unused... */ +#define BMCR_SPEED1000 0x0040 /* MSB of Speed (1000) */ +#define BMCR_CTST 0x0080 /* Collision test */ +#define BMCR_FULLDPLX 0x0100 /* Full duplex */ +#define BMCR_ANRESTART 0x0200 /* Auto negotiation restart */ +#define BMCR_ISOLATE 0x0400 /* Isolate data paths from MII */ +#define BMCR_PDOWN 0x0800 /* Enable low power state */ +#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */ +#define BMCR_SPEED100 0x2000 /* Select 100Mbps */ +#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */ +#define BMCR_RESET 0x8000 /* Reset to default state */ +#define BMCR_SPEED10 0x0000 /* Select 10Mbps */ + +/* Basic mode status register. */ +#define BMSR_ERCAP 0x0001 /* Ext-reg capability */ +#define BMSR_JCD 0x0002 /* Jabber detected */ +#define BMSR_LSTATUS 0x0004 /* Link status */ +#define BMSR_ANEGCAPABLE 0x0008 /* Able to do auto-negotiation */ +#define BMSR_RFAULT 0x0010 /* Remote fault detected */ +#define BMSR_ANEGCOMPLETE 0x0020 /* Auto-negotiation complete */ +#define BMSR_RESV 0x00c0 /* Unused... */ +#define BMSR_ESTATEN 0x0100 /* Extended Status in R15 */ +#define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */ +#define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */ +#define BMSR_10HALF 0x0800 /* Can do 10mbps, half-duplex */ +#define BMSR_10FULL 0x1000 /* Can do 10mbps, full-duplex */ +#define BMSR_100HALF 0x2000 /* Can do 100mbps, half-duplex */ +#define BMSR_100FULL 0x4000 /* Can do 100mbps, full-duplex */ +#define BMSR_100BASE4 0x8000 /* Can do 100mbps, 4k packets */ + +/* Advertisement control register. */ +#define ADVERTISE_SLCT 0x001f /* Selector bits */ +#define ADVERTISE_CSMA 0x0001 /* Only selector supported */ +#define ADVERTISE_10HALF 0x0020 /* Try for 10mbps half-duplex */ +#define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */ +#define ADVERTISE_10FULL 0x0040 /* Try for 10mbps full-duplex */ +#define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */ +#define ADVERTISE_100HALF 0x0080 /* Try for 100mbps half-duplex */ +#define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */ +#define ADVERTISE_100FULL 0x0100 /* Try for 100mbps full-duplex */ +#define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */ +#define ADVERTISE_100BASE4 0x0200 /* Try for 100mbps 4k packets */ +#define ADVERTISE_PAUSE_CAP 0x0400 /* Try for pause */ +#define ADVERTISE_PAUSE_ASYM 0x0800 /* Try for asymetric pause */ +#define ADVERTISE_RESV 0x1000 /* Unused... */ +#define ADVERTISE_RFAULT 0x2000 /* Say we can detect faults */ +#define ADVERTISE_LPACK 0x4000 /* Ack link partners response */ +#define ADVERTISE_NPAGE 0x8000 /* Next page bit */ + +#define ADVERTISE_FULL (ADVERTISE_100FULL | ADVERTISE_10FULL | \ + ADVERTISE_CSMA) +#define ADVERTISE_ALL (ADVERTISE_10HALF | ADVERTISE_10FULL | \ + ADVERTISE_100HALF | ADVERTISE_100FULL) + +/* 1000BASE-T Control register */ +#define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */ +#define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */ +#define CTL1000_AS_MASTER 0x0800 +#define CTL1000_ENABLE_MASTER 0x1000 + +/* ethtool.h */ +/* The forced speed, 10Mb, 100Mb, gigabit. */ +#define SPEED_10 10 +#define SPEED_100 100 +#define SPEED_1000 1000 + +#define SPEED_UNKNOWN -1 + +/* Duplex, half or full. */ +#define DUPLEX_HALF 0x00 +#define DUPLEX_FULL 0x01 +#define DUPLEX_UNKNOWN 0xff + +/* Enable or disable autonegotiation. */ +#define AUTONEG_DISABLE 0x00 +#define AUTONEG_ENABLE 0x01 + +static int usbh_rtl8152_read_regs(struct usbh_rtl8152 *rtl8152_class, + uint16_t value, + uint16_t index, + uint16_t size, + void *data) +{ + struct usb_setup_packet *setup = rtl8152_class->hport->setup; + int ret; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = RTL8152_REQ_GET_REGS; + setup->wValue = value; + setup->wIndex = index; + setup->wLength = size; + + ret = usbh_control_transfer(rtl8152_class->hport, setup, g_rtl8152_buf); + if (ret < 0) { + return ret; + } + memcpy(data, g_rtl8152_buf, ret - 8); + + return ret; +} + +static int usbh_rtl8152_write_regs(struct usbh_rtl8152 *rtl8152_class, + uint16_t value, + uint16_t index, + uint16_t size, + void *data) +{ + struct usb_setup_packet *setup = rtl8152_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = RTL8152_REQ_SET_REGS; + setup->wValue = value; + setup->wIndex = index; + setup->wLength = size; + + memcpy(g_rtl8152_buf, data, size); + return usbh_control_transfer(rtl8152_class->hport, setup, g_rtl8152_buf); +} + +static int generic_ocp_read(struct usbh_rtl8152 *tp, uint16_t index, uint16_t size, + void *data, uint16_t type) +{ + uint16_t limit = 64; + int ret = 0; + + /* both size and indix must be 4 bytes align */ + if ((size & 3) || !size || (index & 3) || !data) + return -USB_ERR_INVAL; + + if ((uint32_t)index + (uint32_t)size > 0xffff) + return -USB_ERR_INVAL; + + while (size) { + if (size > limit) { + ret = usbh_rtl8152_read_regs(tp, index, type, limit, data); + if (ret < 0) + break; + + index += limit; + data += limit; + size -= limit; + } else { + ret = usbh_rtl8152_read_regs(tp, index, type, size, data); + if (ret < 0) + break; + + index += size; + data += size; + size = 0; + break; + } + } + + return ret; +} + +static int generic_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t byteen, + uint16_t size, void *data, uint16_t type) +{ + int ret; + uint16_t byteen_start, byteen_end, byen; + uint16_t limit = 512; + + /* both size and indix must be 4 bytes align */ + if ((size & 3) || !size || (index & 3) || !data) + return -USB_ERR_INVAL; + + if ((uint32_t)index + (uint32_t)size > 0xffff) + return -USB_ERR_INVAL; + + byteen_start = byteen & BYTE_EN_START_MASK; + byteen_end = byteen & BYTE_EN_END_MASK; + + byen = byteen_start | (byteen_start << 4); + + /* Split the first DWORD if the byte_en is not 0xff */ + if (byen != BYTE_EN_DWORD) { + ret = usbh_rtl8152_write_regs(tp, index, type | byen, 4, data); + if (ret < 0) + goto error1; + + index += 4; + data += 4; + size -= 4; + } + + if (size) { + byen = byteen_end | (byteen_end >> 4); + + /* Split the last DWORD if the byte_en is not 0xff */ + if (byen != BYTE_EN_DWORD) + size -= 4; + + while (size) { + if (size > limit) { + ret = usbh_rtl8152_write_regs(tp, index, + type | BYTE_EN_DWORD, + limit, data); + if (ret < 0) + goto error1; + + index += limit; + data += limit; + size -= limit; + } else { + ret = usbh_rtl8152_write_regs(tp, index, + type | BYTE_EN_DWORD, + size, data); + if (ret < 0) + goto error1; + + index += size; + data += size; + size = 0; + break; + } + } + + /* Set the last DWORD */ + if (byen != BYTE_EN_DWORD) + ret = usbh_rtl8152_write_regs(tp, index, type | byen, 4, data); + } + +error1: + + return ret; +} + +static inline int pla_ocp_read(struct usbh_rtl8152 *tp, uint16_t index, uint16_t size, void *data) +{ + return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); +} + +static inline int pla_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t byteen, uint16_t size, void *data) +{ + return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); +} + +static inline int usb_ocp_write(struct usbh_rtl8152 *tp, uint16_t index, uint16_t byteen, uint16_t size, void *data) +{ + return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); +} + +static uint32_t ocp_read_dword(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index) +{ + uint32_t data; + + generic_ocp_read(tp, index, sizeof(data), &data, type); + + return data; +} + +static void ocp_write_dword(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index, uint32_t data) +{ + uint32_t tmp = data; + + generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); +} + +static uint16_t ocp_read_word(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index) +{ + uint32_t data; + uint32_t tmp; + uint16_t byen = BYTE_EN_WORD; + uint8_t shift = index & 2; + + index &= ~3; + byen <<= shift; + + generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); + + data = tmp; + data >>= (shift * 8); + data &= 0xffff; + + return (uint16_t)data; +} + +static void ocp_write_word(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index, uint32_t data) +{ + uint32_t mask = 0xffff; + uint32_t tmp; + uint16_t byen = BYTE_EN_WORD; + uint8_t shift = index & 2; + + data &= mask; + + if (index & 2) { + byen <<= shift; + mask <<= (shift * 8); + data <<= (shift * 8); + index &= ~3; + } + + tmp = data; + + generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); +} + +static uint8_t ocp_read_byte(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index) +{ + uint32_t data; + uint32_t tmp; + uint8_t shift = index & 3; + + index &= ~3; + + generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); + + data = tmp; + data >>= (shift * 8); + data &= 0xff; + + return (uint8_t)data; +} + +static void ocp_write_byte(struct usbh_rtl8152 *tp, uint16_t type, uint16_t index, uint32_t data) +{ + uint32_t mask = 0xff; + uint32_t tmp; + uint16_t byen = BYTE_EN_BYTE; + uint8_t shift = index & 3; + + data &= mask; + + if (index & 3) { + byen <<= shift; + mask <<= (shift * 8); + data <<= (shift * 8); + index &= ~3; + } + + tmp = data; + + generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); +} + +static uint16_t ocp_reg_read(struct usbh_rtl8152 *tp, uint16_t addr) +{ + uint16_t ocp_base, ocp_index; + + ocp_base = addr & 0xf000; + if (ocp_base != tp->ocp_base) { + ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); + tp->ocp_base = ocp_base; + } + + ocp_index = (addr & 0x0fff) | 0xb000; + return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); +} + +static void ocp_reg_write(struct usbh_rtl8152 *tp, uint16_t addr, uint16_t data) +{ + uint16_t ocp_base, ocp_index; + + ocp_base = addr & 0xf000; + if (ocp_base != tp->ocp_base) { + ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); + tp->ocp_base = ocp_base; + } + + ocp_index = (addr & 0x0fff) | 0xb000; + ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); +} + +static inline void r8152_mdio_write(struct usbh_rtl8152 *tp, uint32_t reg_addr, uint32_t value) +{ + ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); +} + +static inline int r8152_mdio_read(struct usbh_rtl8152 *tp, uint32_t reg_addr) +{ + return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); +} + +static uint8_t usbh_rtl8152_get_version(struct usbh_rtl8152 *rtl8152_class) +{ + uint8_t version; + uint32_t temp; + uint32_t ocp_data; + + usbh_rtl8152_read_regs(rtl8152_class, PLA_TCR0, MCU_TYPE_PLA, 4, &temp); + + ocp_data = (temp >> 16) & VERSION_MASK; + switch (ocp_data) { + case 0x4c00: + version = RTL_VER_01; + break; + case 0x4c10: + version = RTL_VER_02; + break; + case 0x5c00: + version = RTL_VER_03; + break; + case 0x5c10: + version = RTL_VER_04; + break; + case 0x5c20: + version = RTL_VER_05; + break; + case 0x5c30: + version = RTL_VER_06; + break; + case 0x4800: + version = RTL_VER_07; + break; + case 0x6000: + version = RTL_VER_08; + break; + case 0x6010: + version = RTL_VER_09; + break; + case 0x7010: + version = RTL_TEST_01; + break; + case 0x7020: + version = RTL_VER_10; + break; + case 0x7030: + version = RTL_VER_11; + break; + case 0x7400: + version = RTL_VER_12; + break; + case 0x7410: + version = RTL_VER_13; + break; + case 0x6400: + version = RTL_VER_14; + break; + case 0x7420: + version = RTL_VER_15; + break; + default: + version = RTL_VER_UNKNOWN; + break; + } + + return version; +} + +#define WAKE_PHY (1 << 0) +#define WAKE_UCAST (1 << 1) +#define WAKE_MCAST (1 << 2) +#define WAKE_BCAST (1 << 3) +#define WAKE_ARP (1 << 4) +#define WAKE_MAGIC (1 << 5) +#define WAKE_MAGICSECURE (1 << 6) /* only meaningful if WAKE_MAGIC */ +#define WAKE_FILTER (1 << 7) + +#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) + +static uint32_t __rtl_get_wol(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + uint32_t wolopts = 0; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); + if (ocp_data & LINK_ON_WAKE_EN) + wolopts |= WAKE_PHY; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); + if (ocp_data & UWF_EN) + wolopts |= WAKE_UCAST; + if (ocp_data & BWF_EN) + wolopts |= WAKE_BCAST; + if (ocp_data & MWF_EN) + wolopts |= WAKE_MCAST; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); + if (ocp_data & MAGIC_EN) + wolopts |= WAKE_MAGIC; + + return wolopts; +} + +static void r8152_aldps_en(struct usbh_rtl8152 *tp, bool enable) +{ + if (enable) { + ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | LINKENA | DIS_SDSAVE); + } else { + ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | DIS_SDSAVE); + usb_osal_msleep(20); + } +} + +static void r8152_power_cut_en(struct usbh_rtl8152 *tp, bool enable) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); + if (enable) + ocp_data |= POWER_CUT; + else + ocp_data &= ~POWER_CUT; + ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); + ocp_data &= ~RESUME_INDICATE; + ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); +} + +static void rtl_tally_reset(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); + ocp_data |= TALLY_RESET; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); +} + +static void r8152b_reset_packet_filter(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); + ocp_data &= ~FMC_FCR_MCU_EN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); + ocp_data |= FMC_FCR_MCU_EN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); +} + +static inline void r8153b_rx_agg_chg_indicate(struct usbh_rtl8152 *tp) +{ + ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, + OWN_UPDATE | OWN_CLEAR); +} + +static void rxdy_gated_en(struct usbh_rtl8152 *tp, bool enable) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); + if (enable) + ocp_data |= RXDY_GATED_EN; + else + ocp_data &= ~RXDY_GATED_EN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); +} + +static inline uint16_t rtl8152_get_speed(struct usbh_rtl8152 *tp) +{ + return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); +} + +static void rtl_eee_plus_en(struct usbh_rtl8152 *tp, bool enable) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); + if (enable) + ocp_data |= EEEP_CR_EEEP_TX; + else + ocp_data &= ~EEEP_CR_EEEP_TX; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); +} + +static void rtl_set_eee_plus(struct usbh_rtl8152 *tp) +{ + if (rtl8152_get_speed(tp) & _10bps) + rtl_eee_plus_en(tp, true); + else + rtl_eee_plus_en(tp, false); +} + +static void rtl8152_nic_reset(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + int i; + + switch (tp->version) { + case RTL_TEST_01: + case RTL_VER_10: + case RTL_VER_11: + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); + ocp_data &= ~CR_TE; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); + ocp_data &= ~BMU_RESET_EP_IN; + ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + ocp_data |= CDC_ECM_EN; + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); + ocp_data &= ~CR_RE; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); + ocp_data |= BMU_RESET_EP_IN; + ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + ocp_data &= ~CDC_ECM_EN; + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); + break; + + default: + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); + + for (i = 0; i < 1000; i++) { + if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) + break; + usb_osal_msleep(400); + } + break; + } +} + +static void rtl_disable(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + int i; + + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data &= ~RCR_ACPT_ALL; + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + + rxdy_gated_en(tp, true); + + for (i = 0; i < 1000; i++) { + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) + break; + usb_osal_msleep(1); + } + + for (i = 0; i < 1000; i++) { + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) + break; + usb_osal_msleep(1); + } + + rtl8152_nic_reset(tp); +} + +static void rtl_rx_vlan_en(struct usbh_rtl8152 *tp, bool enable) +{ + uint32_t ocp_data; + + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + case RTL_VER_07: + case RTL_VER_08: + case RTL_VER_09: + case RTL_VER_14: + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); + if (enable) + ocp_data |= CPCR_RX_VLAN; + else + ocp_data &= ~CPCR_RX_VLAN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); + break; + + case RTL_TEST_01: + case RTL_VER_10: + case RTL_VER_11: + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_15: + default: + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1); + if (enable) + ocp_data |= OUTER_VLAN | INNER_VLAN; + else + ocp_data &= ~(OUTER_VLAN | INNER_VLAN); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data); + break; + } +} + +static void wait_oob_link_list_ready(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + int i; + + for (i = 0; i < 1000; i++) { + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + if (ocp_data & LINK_LIST_READY) + break; + usb_osal_msleep(1); + } +} + +static void r8153_teredo_off(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + case RTL_VER_07: + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); + ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | + OOB_TEREDO_EN); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); + break; + + case RTL_VER_08: + case RTL_VER_09: + case RTL_TEST_01: + case RTL_VER_10: + case RTL_VER_11: + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_14: + case RTL_VER_15: + default: + /* The bit 0 ~ 7 are relative with teredo settings. They are + * W1C (write 1 to clear), so set all 1 to disable it. + */ + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); + break; + } + + ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); + ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); +} + +static void r8152b_exit_oob(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data &= ~RCR_ACPT_ALL; + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); + + rxdy_gated_en(tp, true); + r8153_teredo_off(tp); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + ocp_data &= ~NOW_IS_OOB; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); + ocp_data &= ~MCU_BORW_EN; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + + wait_oob_link_list_ready(tp); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); + ocp_data |= RE_INIT_LL; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + + wait_oob_link_list_ready(tp); + + rtl8152_nic_reset(tp); + + /* rx share fifo credit full threshold */ + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); + + if (tp->hport->speed == USB_SPEED_FULL || + tp->hport->speed == USB_SPEED_LOW) { + /* rx share fifo credit near full threshold */ + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, + RXFIFO_THR2_FULL); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, + RXFIFO_THR3_FULL); + } else { + /* rx share fifo credit near full threshold */ + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, + RXFIFO_THR2_HIGH); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, + RXFIFO_THR3_HIGH); + } + + /* TX share fifo free credit full threshold */ + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); + + ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); + ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, + TEST_MODE_DISABLE | TX_SIZE_ADJUST1); + + rtl_rx_vlan_en(tp, true); + + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); + ocp_data |= TCR0_AUTO_FIFO; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); +} + +static void r8152b_enter_oob(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + ocp_data &= ~NOW_IS_OOB; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); + + rtl_disable(tp); + + wait_oob_link_list_ready(tp); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); + ocp_data |= RE_INIT_LL; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); + + wait_oob_link_list_ready(tp); + + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); + + rtl_rx_vlan_en(tp, true); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); + ocp_data |= ALDPS_PROXY_MODE; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); + ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); + + rxdy_gated_en(tp, false); + + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data |= RCR_APM | RCR_AM | RCR_AB; + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); +} + +static void r8152b_init(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + uint16_t data; + + data = r8152_mdio_read(tp, MII_BMCR); + if (data & BMCR_PDOWN) { + data &= ~BMCR_PDOWN; + r8152_mdio_write(tp, MII_BMCR, data); + } + + r8152_aldps_en(tp, false); + + if (tp->version == RTL_VER_01) { + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); + ocp_data &= ~LED_MODE_MASK; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); + } + + r8152_power_cut_en(tp, false); + + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); + ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); + ocp_data &= ~MCU_CLK_RATIO_MASK; + ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); + ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | + SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; + ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); + + rtl_tally_reset(tp); + + /* enable rx aggregation */ + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); +} + +static int rtl_enable(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + + r8152b_reset_packet_filter(tp); + + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); + ocp_data |= CR_RE | CR_TE; + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); + + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + case RTL_VER_07: + break; + default: + r8153b_rx_agg_chg_indicate(tp); + break; + } + + rxdy_gated_en(tp, false); + + return 0; +} + +static int rtl8152_enable(struct usbh_rtl8152 *tp) +{ + rtl_set_eee_plus(tp); + + return rtl_enable(tp); +} + +static void rtl8152_disable(struct usbh_rtl8152 *tp) +{ + r8152_aldps_en(tp, false); + rtl_disable(tp); + r8152_aldps_en(tp, true); +} + +static void rtl8152_up(struct usbh_rtl8152 *tp) +{ + r8152_aldps_en(tp, false); + r8152b_exit_oob(tp); + r8152_aldps_en(tp, true); +} + +static void rtl8152_down(struct usbh_rtl8152 *tp) +{ + r8152_power_cut_en(tp, false); + r8152_aldps_en(tp, false); + r8152b_enter_oob(tp); + r8152_aldps_en(tp, true); +} + +static int rtl_ops_init(struct usbh_rtl8152 *tp) +{ + struct rtl_ops *ops = &tp->rtl_ops; + int ret = 0; + + switch (tp->version) { + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_07: + ops->init = r8152b_init; + ops->enable = rtl8152_enable; + ops->disable = rtl8152_disable; + ops->up = rtl8152_up; + ops->down = rtl8152_down; + // ops->unload = rtl8152_unload; + // ops->eee_get = r8152_get_eee; + // ops->eee_set = r8152_set_eee; + // ops->in_nway = rtl8152_in_nway; + // ops->hw_phy_cfg = r8152b_hw_phy_cfg; + // ops->autosuspend_en = rtl_runtime_suspend_enable; + tp->rx_buf_sz = 16 * 1024; + tp->eee_en = true; + //tp->eee_adv = MDIO_EEE_100TX; + break; + + // case RTL_VER_03: + // case RTL_VER_04: + // case RTL_VER_05: + // case RTL_VER_06: + // break; + + // case RTL_VER_08: + // case RTL_VER_09: + // break; + + // case RTL_VER_11: + // case RTL_VER_10: + // break; + + // case RTL_VER_12: + // case RTL_VER_13: + // case RTL_VER_15: + // break; + + // case RTL_VER_14: + // break; + + default: + ret = -USB_ERR_NODEV; + USB_LOG_ERR("Unsupport rtl version:%d\r\n", tp->version); + break; + } + + return ret; +} + +static void rtl8152_set_rx_mode(struct usbh_rtl8152 *tp) +{ + uint32_t ocp_data; + uint32_t mc_filter[2]; + + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); + ocp_data &= ~RCR_ACPT_ALL; + ocp_data |= RCR_AB | RCR_APM; + + ocp_data |= RCR_AM; + mc_filter[1] = 0xffffffff; + mc_filter[0] = 0xffffffff; + + pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(mc_filter), mc_filter); + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); +} + +static int rtl8152_set_speed(struct usbh_rtl8152 *tp, uint8_t autoneg, uint16_t speed, uint8_t duplex) +{ + uint16_t bmcr, anar, gbcr; + + anar = r8152_mdio_read(tp, MII_ADVERTISE); + anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL | + ADVERTISE_100HALF | ADVERTISE_100FULL); + if (tp->supports_gmii) { + gbcr = r8152_mdio_read(tp, MII_CTRL1000); + gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF); + } else { + gbcr = 0; + } + + if (autoneg == AUTONEG_DISABLE) { + if (speed == SPEED_10) { + bmcr = 0; + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + } else if (speed == SPEED_100) { + bmcr = BMCR_SPEED100; + anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; + } else if (speed == SPEED_1000 && tp->supports_gmii) { + bmcr = BMCR_SPEED1000; + gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; + } else { + return -USB_ERR_INVAL; + } + + if (duplex == DUPLEX_FULL) + bmcr |= BMCR_FULLDPLX; + } else { + if (speed == SPEED_10) { + if (duplex == DUPLEX_FULL) + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + else + anar |= ADVERTISE_10HALF; + } else if (speed == SPEED_100) { + if (duplex == DUPLEX_FULL) { + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; + } else { + anar |= ADVERTISE_10HALF; + anar |= ADVERTISE_100HALF; + } + } else if (speed == SPEED_1000 && tp->supports_gmii) { + if (duplex == DUPLEX_FULL) { + anar |= ADVERTISE_10HALF | ADVERTISE_10FULL; + anar |= ADVERTISE_100HALF | ADVERTISE_100FULL; + gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF; + } else { + anar |= ADVERTISE_10HALF; + anar |= ADVERTISE_100HALF; + gbcr |= ADVERTISE_1000HALF; + } + } else { + return -USB_ERR_INVAL; + } + + bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_RESET; + } + + if (tp->supports_gmii) + r8152_mdio_write(tp, MII_CTRL1000, gbcr); + + r8152_mdio_write(tp, MII_ADVERTISE, anar); + r8152_mdio_write(tp, MII_BMCR, bmcr); + + return 0; +} + +int r8152_write_hwaddr(struct usbh_rtl8152 *tp, unsigned char *mac) +{ + unsigned char enetaddr[8] = { 0 }; + memcpy(enetaddr, mac, 6); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); + pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, enetaddr); + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); + return 0; +} + +int usbh_rtl8152_get_connect_status(struct usbh_rtl8152 *rtl8152_class) +{ + int ret; + + usbh_int_urb_fill(&rtl8152_class->intin_urb, rtl8152_class->hport, rtl8152_class->intin, g_rtl8152_inttx_buffer, 2, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&rtl8152_class->intin_urb); + if (ret < 0) { + return ret; + } + + if (g_rtl8152_inttx_buffer[0] & INTR_LINK) { + rtl8152_class->connect_status = true; + } else { + rtl8152_class->connect_status = false; + } + return 0; +} + +static int usbh_rtl8152_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + char mac_buffer[12]; + int ret; + + struct usbh_rtl8152 *rtl8152_class = &g_rtl8152_class; + + memset(rtl8152_class, 0, sizeof(struct usbh_rtl8152)); + + rtl8152_class->hport = hport; + rtl8152_class->intf = intf; + + hport->config.intf[intf].priv = rtl8152_class; + + rtl8152_class->version = usbh_rtl8152_get_version(rtl8152_class); + + if (rtl8152_class->version == RTL_VER_UNKNOWN) { + USB_LOG_ERR("Unknown version 0x%04x\r\n", rtl8152_class->version); + return -USB_ERR_NOTSUPP; + } else { + USB_LOG_INFO("rtl8152 version 0x%04x\r\n", rtl8152_class->version); + } + + /* MTU range: 68 - 1500 or 9194 */ + rtl8152_class->min_mtu = 68; + switch (rtl8152_class->version) { + case RTL_VER_03: + case RTL_VER_04: + case RTL_VER_05: + case RTL_VER_06: + case RTL_VER_08: + case RTL_VER_09: + case RTL_VER_14: + rtl8152_class->max_mtu = size_to_mtu(9 * 1024); + break; + case RTL_VER_10: + case RTL_VER_11: + rtl8152_class->max_mtu = size_to_mtu(15 * 1024); + break; + case RTL_VER_12: + case RTL_VER_13: + case RTL_VER_15: + rtl8152_class->max_mtu = size_to_mtu(16 * 1024); + break; + case RTL_VER_01: + case RTL_VER_02: + case RTL_VER_07: + default: + rtl8152_class->max_mtu = 1500; + break; + } + + rtl8152_class->saved_wolopts = __rtl_get_wol(rtl8152_class); + if (rtl_ops_init(rtl8152_class) < 0) { + return -USB_ERR_NODEV; + } + + rtl8152_class->rtl_ops.init(rtl8152_class); + rtl8152_class->rtl_ops.up(rtl8152_class); + + if (rtl8152_class->rx_buf_sz > CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) { + USB_LOG_ERR("rx_buf_sz is overflow, default is %d\r\n", CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE); + return -USB_ERR_NOMEM; + } + + memset(mac_buffer, 0, 12); + ret = usbh_get_string_desc(rtl8152_class->hport, 3, (uint8_t *)mac_buffer); + if (ret < 0) { + return ret; + } + + for (int i = 0, j = 0; i < 12; i += 2, j++) { + char byte_str[3]; + byte_str[0] = mac_buffer[i]; + byte_str[1] = mac_buffer[i + 1]; + byte_str[2] = '\0'; + + uint32_t byte = strtoul(byte_str, NULL, 16); + rtl8152_class->mac[j] = (unsigned char)byte; + } + + r8152_write_hwaddr(rtl8152_class, rtl8152_class->mac); + + USB_LOG_INFO("RTL8152 MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + rtl8152_class->mac[0], + rtl8152_class->mac[1], + rtl8152_class->mac[2], + rtl8152_class->mac[3], + rtl8152_class->mac[4], + rtl8152_class->mac[5]); + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(rtl8152_class->intin, ep_desc); + } else { + return -USB_ERR_NOTSUPP; + } + } else { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(rtl8152_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(rtl8152_class->bulkout, ep_desc); + } + } + } + + memcpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register RTL8152 Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_rtl8152_run(rtl8152_class); + return 0; +} + +static int usbh_rtl8152_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_rtl8152 *rtl8152_class = (struct usbh_rtl8152 *)hport->config.intf[intf].priv; + + if (rtl8152_class) { + if (rtl8152_class->bulkin) { + usbh_kill_urb(&rtl8152_class->bulkin_urb); + } + + if (rtl8152_class->bulkout) { + usbh_kill_urb(&rtl8152_class->bulkout_urb); + } + + if (rtl8152_class->intin) { + usbh_kill_urb(&rtl8152_class->intin_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister rtl8152 Class:%s\r\n", hport->config.intf[intf].devname); + usbh_rtl8152_stop(rtl8152_class); + } + + memset(rtl8152_class, 0, sizeof(struct usbh_rtl8152)); + } + + return ret; +} + +void usbh_rtl8152_rx_thread(void *argument) +{ + uint32_t g_rtl8152_rx_length; + int ret; + uint16_t len; + uint16_t data_offset; + + USB_LOG_INFO("Create rtl8152 rx thread\r\n"); + // clang-format off +find_class: + // clang-format on + g_rtl8152_class.connect_status = false; + if (usbh_find_class_instance("/dev/rtl8152") == NULL) { + goto delete; + } + + while (g_rtl8152_class.connect_status == false) { + ret = usbh_rtl8152_get_connect_status(&g_rtl8152_class); + if (ret < 0) { + usb_osal_msleep(100); + goto find_class; + } + usb_osal_msleep(128); + } + + if (g_rtl8152_class.rtl_ops.enable) { + g_rtl8152_class.rtl_ops.enable(&g_rtl8152_class); + } else { + goto delete; + } + + rtl8152_set_rx_mode(&g_rtl8152_class); + rtl8152_set_speed(&g_rtl8152_class, AUTONEG_ENABLE, g_rtl8152_class.supports_gmii ? SPEED_1000 : SPEED_100, DUPLEX_FULL); + + g_rtl8152_rx_length = 0; + while (1) { + usbh_bulk_urb_fill(&g_rtl8152_class.bulkin_urb, g_rtl8152_class.hport, g_rtl8152_class.bulkin, &g_rtl8152_rx_buffer[g_rtl8152_rx_length], (CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE > (16 * 1024)) ? (16 * 1024) : CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_rtl8152_class.bulkin_urb); + if (ret < 0) { + goto find_class; + } + + g_rtl8152_rx_length += g_rtl8152_class.bulkin_urb.actual_length; + + if (g_rtl8152_rx_length % USB_GET_MAXPACKETSIZE(g_rtl8152_class.bulkin->wMaxPacketSize)) { + data_offset = 0; + + USB_LOG_DBG("rxlen:%d\r\n", g_rtl8152_rx_length); + while (g_rtl8152_rx_length > 0) { + struct rx_desc *rx_desc = (struct rx_desc *)&g_rtl8152_rx_buffer[data_offset]; + + len = rx_desc->opts1 & RX_LEN_MASK; + + USB_LOG_DBG("data_offset:%d, eth len:%d\r\n", data_offset, len); + + uint8_t *buf = (uint8_t *)&g_rtl8152_rx_buffer[data_offset + sizeof(struct rx_desc)]; + usbh_rtl8152_eth_input(buf, len); + + data_offset += (len + sizeof(struct rx_desc)); + g_rtl8152_rx_length -= (len + sizeof(struct rx_desc)); + + if (len & (RX_ALIGN - 1)) { + data_offset += (RX_ALIGN - (len & (RX_ALIGN - 1))); + g_rtl8152_rx_length -= (RX_ALIGN - (len & (RX_ALIGN - 1))); + } + } + } else { + if (g_rtl8152_rx_length > CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE) { + USB_LOG_ERR("Rx packet is overflow\r\n"); + g_rtl8152_rx_length = 0; + } + } + } + // clang-format off +delete: + USB_LOG_INFO("Delete rtl8152 rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +int usbh_rtl8152_eth_output(uint8_t *buf, uint32_t buflen) +{ + uint8_t *buffer; + struct tx_desc *tx_desc; + + if (g_rtl8152_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + tx_desc = (struct tx_desc *)g_rtl8152_tx_buffer; + tx_desc->opts1 = buflen | TX_FS | TX_LS; + tx_desc->opts2 = 0; + + buffer = g_rtl8152_tx_buffer + sizeof(struct tx_desc); + memcpy(buffer, buf, buflen); + + USB_LOG_DBG("txlen:%d\r\n", buflen + sizeof(struct tx_desc)); + + usbh_bulk_urb_fill(&g_rtl8152_class.bulkout_urb, g_rtl8152_class.hport, g_rtl8152_class.bulkout, g_rtl8152_tx_buffer, buflen + sizeof(struct tx_desc), USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_rtl8152_class.bulkout_urb); +} + +__WEAK void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class) +{ +} + +__WEAK void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class) +{ +} + +static const uint16_t rtl_id_table[][2] = { + { 0x0BDA, 0x8152 }, + { 0, 0 }, +}; + +static const struct usbh_class_driver rtl8152_class_driver = { + .driver_name = "rtl8152", + .connect = usbh_rtl8152_connect, + .disconnect = usbh_rtl8152_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info rtl8152_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .class = 0xff, + .subclass = 0x00, + .protocol = 0x00, + .id_table = rtl_id_table, + .class_driver = &rtl8152_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.h b/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.h new file mode 100644 index 00000000000..a9aa794355c --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/net/usbh_rtl8152.h @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_RTL8152_H +#define USBH_RTL8152_H + +struct usbh_rtl8152 { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usb_endpoint_descriptor *intin; /* INTR IN endpoint */ + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + struct usbh_urb intin_urb; + + uint8_t intf; + + uint8_t mac[6]; + bool connect_status; + uint32_t speed[2]; + + uint8_t version; + uint8_t eee_adv; + uint8_t eee_en; + uint8_t supports_gmii; + uint16_t min_mtu; + uint16_t max_mtu; + uint16_t ocp_base; + uint32_t saved_wolopts; + uint32_t rx_buf_sz; + + struct rtl_ops { + void (*init)(struct usbh_rtl8152 *tp); + int (*enable)(struct usbh_rtl8152 *tp); + void (*disable)(struct usbh_rtl8152 *tp); + void (*up)(struct usbh_rtl8152 *tp); + void (*down)(struct usbh_rtl8152 *tp); + void (*unload)(struct usbh_rtl8152 *tp); + bool (*in_nway)(struct usbh_rtl8152 *tp); + void (*hw_phy_cfg)(struct usbh_rtl8152 *tp); + void (*autosuspend_en)(struct usbh_rtl8152 *tp, bool enable); + void (*change_mtu)(struct usbh_rtl8152 *tp); + } rtl_ops; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_rtl8152_get_connect_status(struct usbh_rtl8152 *rtl8152_class); + +void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class); +void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class); + +int usbh_rtl8152_eth_output(uint8_t *buf, uint32_t buflen); +void usbh_rtl8152_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_rtl8152_rx_thread(void *argument); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_RTL8152_H */ \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c new file mode 100644 index 00000000000..6321d813395 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.c @@ -0,0 +1,356 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_ch34x.h" + +#define DEV_FORMAT "/dev/ttyUSB%d" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_ch34x_buf[64]; + +#define CONFIG_USBHOST_MAX_CP210X_CLASS 1 + +static struct usbh_ch34x g_ch34x_class[CONFIG_USBHOST_MAX_CP210X_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_ch34x *usbh_ch34x_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_CP210X_CLASS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_ch34x_class[devno], 0, sizeof(struct usbh_ch34x)); + g_ch34x_class[devno].minor = devno; + return &g_ch34x_class[devno]; + } + } + return NULL; +} + +static void usbh_ch34x_class_free(struct usbh_ch34x *ch34x_class) +{ + int devno = ch34x_class->minor; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(ch34x_class, 0, sizeof(struct usbh_ch34x)); +} + +static int usbh_ch34x_get_baudrate_div(uint32_t baudrate, uint8_t *factor, uint8_t *divisor) +{ + uint8_t a; + uint8_t b; + uint32_t c; + + switch (baudrate) { + case 921600: + a = 0xf3; + b = 7; + break; + + case 307200: + a = 0xd9; + b = 7; + break; + + default: + if (baudrate > 6000000 / 255) { + b = 3; + c = 6000000; + } else if (baudrate > 750000 / 255) { + b = 2; + c = 750000; + } else if (baudrate > 93750 / 255) { + b = 1; + c = 93750; + } else { + b = 0; + c = 11719; + } + a = (uint8_t)(c / baudrate); + if (a == 0 || a == 0xFF) { + return -USB_ERR_INVAL; + } + if ((c / a - baudrate) > (baudrate - c / (a + 1))) { + a++; + } + a = (uint8_t)(256 - a); + break; + } + + *factor = a; + *divisor = b; + + return 0; +} + +static int usbh_ch34x_get_version(struct usbh_ch34x *ch34x_class) +{ + struct usb_setup_packet *setup = ch34x_class->hport->setup; + int ret; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = CH34X_READ_VERSION; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 2; + + ret = usbh_control_transfer(ch34x_class->hport, setup, g_ch34x_buf); + if (ret < 0) { + return ret; + } + + USB_LOG_INFO("Ch34x chip version %02x:%02x\r\n", g_ch34x_buf[0], g_ch34x_buf[1]); + return ret; +} + +static int usbh_ch34x_flow_ctrl(struct usbh_ch34x *ch34x_class) +{ + struct usb_setup_packet *setup = ch34x_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = CH34X_WRITE_REG; + setup->wValue = 0x2727; + setup->wIndex = 0; + setup->wLength = 0; + + return usbh_control_transfer(ch34x_class->hport, setup, NULL); +} + +int usbh_ch34x_set_line_coding(struct usbh_ch34x *ch34x_class, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup = ch34x_class->hport->setup; + uint16_t reg_value = 0; + uint16_t value = 0; + uint8_t factor = 0; + uint8_t divisor = 0; + + memcpy((uint8_t *)&ch34x_class->line_coding, line_coding, sizeof(struct cdc_line_coding)); + + /* refer to https://github.com/WCHSoftGroup/ch341ser_linux/blob/main/driver/ch341.c */ + + switch (line_coding->bParityType) { + case 0: + break; + case 1: + reg_value |= CH341_L_PO; + break; + case 2: + reg_value |= CH341_L_PE; + break; + case 3: + reg_value |= CH341_L_PM; + break; + case 4: + reg_value |= CH341_L_PS; + break; + default: + return -USB_ERR_INVAL; + } + + switch (line_coding->bDataBits) { + case 5: + reg_value |= CH341_L_D5; + break; + case 6: + reg_value |= CH341_L_D6; + break; + case 7: + reg_value |= CH341_L_D7; + break; + case 8: + reg_value |= CH341_L_D8; + break; + default: + return -USB_ERR_INVAL; + } + + if (line_coding->bCharFormat == 2) { + reg_value |= CH341_L_SB; + } + + reg_value |= 0xC0; + + value |= 0x9c; + value |= reg_value << 8; + + usbh_ch34x_get_baudrate_div(line_coding->dwDTERate, &factor, &divisor); + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = CH34X_SERIAL_INIT; + setup->wValue = value; + setup->wIndex = (factor << 8) | 0x80 | divisor; + setup->wLength = 0; + + return usbh_control_transfer(ch34x_class->hport, setup, NULL); +} + +int usbh_ch34x_get_line_coding(struct usbh_ch34x *ch34x_class, struct cdc_line_coding *line_coding) +{ + memcpy(line_coding, (uint8_t *)&ch34x_class->line_coding, sizeof(struct cdc_line_coding)); + return 0; +} + +int usbh_ch34x_set_line_state(struct usbh_ch34x *ch34x_class, bool dtr, bool rts) +{ + struct usb_setup_packet *setup = ch34x_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = CH34X_MODEM_CTRL; + setup->wValue = 0x0f | (dtr << 5) | (rts << 6); + setup->wIndex = 0; + setup->wLength = 0; + + return usbh_control_transfer(ch34x_class->hport, setup, NULL); +} + +static int usbh_ch34x_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret = 0; + + struct usbh_ch34x *ch34x_class = usbh_ch34x_class_alloc(); + if (ch34x_class == NULL) { + USB_LOG_ERR("Fail to alloc ch34x_class\r\n"); + return -USB_ERR_NOMEM; + } + + ch34x_class->hport = hport; + ch34x_class->intf = intf; + + hport->config.intf[intf].priv = ch34x_class; + + usbh_ch34x_get_version(ch34x_class); + usbh_ch34x_flow_ctrl(ch34x_class); + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + continue; + } else { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(ch34x_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(ch34x_class->bulkout, ep_desc); + } + } + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, ch34x_class->minor); + + USB_LOG_INFO("Register CH34X Class:%s\r\n", hport->config.intf[intf].devname); + +#if 0 + USB_LOG_INFO("Test ch34x rx and tx and rx for 5 times, baudrate is 115200\r\n"); + + struct cdc_line_coding linecoding; + uint8_t count = 5; + + linecoding.dwDTERate = 115200; + linecoding.bDataBits = 8; + linecoding.bParityType = 0; + linecoding.bCharFormat = 0; + usbh_ch34x_set_line_coding(ch34x_class, &linecoding); + usbh_ch34x_set_line_state(ch34x_class, true, false); + + memset(g_ch34x_buf, 'a', sizeof(g_ch34x_buf)); + ret = usbh_ch34x_bulk_out_transfer(ch34x_class, g_ch34x_buf, sizeof(g_ch34x_buf), 0xfffffff); + USB_LOG_RAW("out ret:%d\r\n", ret); + while (count--) { + ret = usbh_ch34x_bulk_in_transfer(ch34x_class, g_ch34x_buf, sizeof(g_ch34x_buf), 0xfffffff); + USB_LOG_RAW("in ret:%d\r\n", ret); + if (ret > 0) { + for (uint32_t i = 0; i < ret; i++) { + USB_LOG_RAW("%02x ", g_ch34x_buf[i]); + } + USB_LOG_RAW("\r\n"); + } + } +#endif + usbh_ch34x_run(ch34x_class); + return ret; +} + +static int usbh_ch34x_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_ch34x *ch34x_class = (struct usbh_ch34x *)hport->config.intf[intf].priv; + + if (ch34x_class) { + if (ch34x_class->bulkin) { + usbh_kill_urb(&ch34x_class->bulkin_urb); + } + + if (ch34x_class->bulkout) { + usbh_kill_urb(&ch34x_class->bulkout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister CH34X Class:%s\r\n", hport->config.intf[intf].devname); + usbh_ch34x_stop(ch34x_class); + } + + usbh_ch34x_class_free(ch34x_class); + } + + return ret; +} + +int usbh_ch34x_bulk_in_transfer(struct usbh_ch34x *ch34x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &ch34x_class->bulkin_urb; + + usbh_bulk_urb_fill(urb, ch34x_class->hport, ch34x_class->bulkin, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +int usbh_ch34x_bulk_out_transfer(struct usbh_ch34x *ch34x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &ch34x_class->bulkout_urb; + + usbh_bulk_urb_fill(urb, ch34x_class->hport, ch34x_class->bulkout, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +__WEAK void usbh_ch34x_run(struct usbh_ch34x *ch34x_class) +{ +} + +__WEAK void usbh_ch34x_stop(struct usbh_ch34x *ch34x_class) +{ +} + +static const uint16_t ch34x_id_table[][2] = { + { 0x1A86, 0x7523 }, + { 0, 0 }, +}; + +const struct usbh_class_driver ch34x_class_driver = { + .driver_name = "ch34x", + .connect = usbh_ch34x_connect, + .disconnect = usbh_ch34x_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info ch34x_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .class = 0xff, + .subclass = 0x00, + .protocol = 0x00, + .id_table = ch34x_id_table, + .class_driver = &ch34x_class_driver +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.h b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.h new file mode 100644 index 00000000000..c90bf9bda60 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ch34x.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CH34X_H +#define USBH_CH34X_H + +#include "usb_cdc.h" + +/* Requests */ +#define CH34X_READ_VERSION 0x5F +#define CH34X_WRITE_REG 0x9A +#define CH34X_READ_REG 0x95 +#define CH34X_SERIAL_INIT 0xA1 +#define CH34X_MODEM_CTRL 0xA4 + +// modem control bits +#define CH34X_BIT_RTS (1 << 6) +#define CH34X_BIT_DTR (1 << 5) + +#define CH341_CTO_O 0x10 +#define CH341_CTO_D 0x20 +#define CH341_CTO_R 0x40 +#define CH341_CTI_C 0x01 +#define CH341_CTI_DS 0x02 +#define CH341_CTRL_RI 0x04 +#define CH341_CTI_DC 0x08 +#define CH341_CTI_ST 0x0f + +#define CH341_L_ER 0x80 +#define CH341_L_ET 0x40 +#define CH341_L_PS 0x38 +#define CH341_L_PM 0x28 +#define CH341_L_PE 0x18 +#define CH341_L_PO 0x08 +#define CH341_L_SB 0x04 +#define CH341_L_D8 0x03 +#define CH341_L_D7 0x02 +#define CH341_L_D6 0x01 +#define CH341_L_D5 0x00 + +struct usbh_ch34x { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + + struct cdc_line_coding line_coding; + + uint8_t intf; + uint8_t minor; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_ch34x_set_line_coding(struct usbh_ch34x *ch34x_class, struct cdc_line_coding *line_coding); +int usbh_ch34x_get_line_coding(struct usbh_ch34x *ch34x_class, struct cdc_line_coding *line_coding); +int usbh_ch34x_set_line_state(struct usbh_ch34x *ch34x_class, bool dtr, bool rts); + +int usbh_ch34x_bulk_in_transfer(struct usbh_ch34x *ch34x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); +int usbh_ch34x_bulk_out_transfer(struct usbh_ch34x *ch34x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); + +void usbh_ch34x_run(struct usbh_ch34x *ch34x_class); +void usbh_ch34x_stop(struct usbh_ch34x *ch34x_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CH34X_H */ diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c new file mode 100644 index 00000000000..e27161bdec6 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.c @@ -0,0 +1,295 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_cp210x.h" + +#define DEV_FORMAT "/dev/ttyUSB%d" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cp210x_buf[64]; + +#define CONFIG_USBHOST_MAX_CP210X_CLASS 4 + +static struct usbh_cp210x g_cp210x_class[CONFIG_USBHOST_MAX_CP210X_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_cp210x *usbh_cp210x_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_CP210X_CLASS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_cp210x_class[devno], 0, sizeof(struct usbh_cp210x)); + g_cp210x_class[devno].minor = devno; + return &g_cp210x_class[devno]; + } + } + return NULL; +} + +static void usbh_cp210x_class_free(struct usbh_cp210x *cp210x_class) +{ + int devno = cp210x_class->minor; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(cp210x_class, 0, sizeof(struct usbh_cp210x)); +} + +static int usbh_cp210x_enable(struct usbh_cp210x *cp210x_class) +{ + struct usb_setup_packet *setup = cp210x_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CP210X_IFC_ENABLE; + setup->wValue = 1; + setup->wIndex = cp210x_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(cp210x_class->hport, setup, NULL); +} + +static int usbh_cp210x_set_flow(struct usbh_cp210x *cp210x_class) +{ + struct usb_setup_packet *setup = cp210x_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CP210X_SET_FLOW; + setup->wValue = 0; + setup->wIndex = cp210x_class->intf; + setup->wLength = 16; + + memset(g_cp210x_buf, 0, 16); + g_cp210x_buf[13] = 0x20; + return usbh_control_transfer(cp210x_class->hport, setup, g_cp210x_buf); +} + +static int usbh_cp210x_set_chars(struct usbh_cp210x *cp210x_class) +{ + struct usb_setup_packet *setup = cp210x_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CP210X_SET_CHARS; + setup->wValue = 0; + setup->wIndex = cp210x_class->intf; + setup->wLength = 6; + + memset(g_cp210x_buf, 0, 6); + g_cp210x_buf[0] = 0x80; + g_cp210x_buf[4] = 0x88; + g_cp210x_buf[5] = 0x28; + return usbh_control_transfer(cp210x_class->hport, setup, g_cp210x_buf); +} + +static int usbh_cp210x_set_baudrate(struct usbh_cp210x *cp210x_class, uint32_t baudrate) +{ + struct usb_setup_packet *setup = cp210x_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CP210X_SET_BAUDRATE; + setup->wValue = 0; + setup->wIndex = cp210x_class->intf; + setup->wLength = 4; + + memcpy(g_cp210x_buf, (uint8_t *)&baudrate, 4); + return usbh_control_transfer(cp210x_class->hport, setup, g_cp210x_buf); +} + +static int usbh_cp210x_set_data_format(struct usbh_cp210x *cp210x_class, uint8_t databits, uint8_t parity, uint8_t stopbits) +{ + struct usb_setup_packet *setup = cp210x_class->hport->setup; + uint16_t value; + + value = ((databits & 0x0F) << 8) | ((parity & 0x0f) << 4) | ((stopbits & 0x03) << 0); + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CP210X_SET_LINE_CTL; + setup->wValue = value; + setup->wIndex = cp210x_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(cp210x_class->hport, setup, NULL); +} + +static int usbh_cp210x_set_mhs(struct usbh_cp210x *cp210x_class, uint8_t dtr, uint8_t rts, uint8_t dtr_mask, uint8_t rts_mask) +{ + struct usb_setup_packet *setup = cp210x_class->hport->setup; + uint16_t value; + + value = ((dtr & 0x01) << 0) | ((rts & 0x01) << 1) | ((dtr_mask & 0x01) << 8) | ((rts_mask & 0x01) << 9); + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CP210X_SET_MHS; + setup->wValue = value; + setup->wIndex = cp210x_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(cp210x_class->hport, setup, NULL); +} + +int usbh_cp210x_set_line_coding(struct usbh_cp210x *cp210x_class, struct cdc_line_coding *line_coding) +{ + memcpy((uint8_t *)&cp210x_class->line_coding, line_coding, sizeof(struct cdc_line_coding)); + usbh_cp210x_set_baudrate(cp210x_class, line_coding->dwDTERate); + return usbh_cp210x_set_data_format(cp210x_class, line_coding->bDataBits, line_coding->bParityType, line_coding->bCharFormat); +} + +int usbh_cp210x_get_line_coding(struct usbh_cp210x *cp210x_class, struct cdc_line_coding *line_coding) +{ + memcpy(line_coding, (uint8_t *)&cp210x_class->line_coding, sizeof(struct cdc_line_coding)); + return 0; +} + +int usbh_cp210x_set_line_state(struct usbh_cp210x *cp210x_class, bool dtr, bool rts) +{ + return usbh_cp210x_set_mhs(cp210x_class, dtr, rts, 1, 1); +} + +static int usbh_cp210x_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret = 0; + + struct usbh_cp210x *cp210x_class = usbh_cp210x_class_alloc(); + if (cp210x_class == NULL) { + USB_LOG_ERR("Fail to alloc cp210x_class\r\n"); + return -USB_ERR_NOMEM; + } + + cp210x_class->hport = hport; + cp210x_class->intf = intf; + + hport->config.intf[intf].priv = cp210x_class; + + usbh_cp210x_enable(cp210x_class); + usbh_cp210x_set_flow(cp210x_class); + usbh_cp210x_set_chars(cp210x_class); + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(cp210x_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(cp210x_class->bulkout, ep_desc); + } + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, cp210x_class->minor); + + USB_LOG_INFO("Register CP210X Class:%s\r\n", hport->config.intf[intf].devname); + +#if 0 + USB_LOG_INFO("Test cp2102 rx and tx and rx for 5 times, baudrate is 115200\r\n"); + + struct cdc_line_coding linecoding; + uint8_t count = 5; + + linecoding.dwDTERate = 115200; + linecoding.bDataBits = 8; + linecoding.bParityType = 0; + linecoding.bCharFormat = 0; + usbh_cp210x_set_line_coding(cp210x_class, &linecoding); + usbh_cp210x_set_line_state(cp210x_class, true, false); + + memset(g_cp210x_buf, 'a', sizeof(g_cp210x_buf)); + ret = usbh_cp210x_bulk_out_transfer(cp210x_class, g_cp210x_buf, sizeof(g_cp210x_buf), 0xfffffff); + USB_LOG_RAW("out ret:%d\r\n", ret); + while (count--) { + ret = usbh_cp210x_bulk_in_transfer(cp210x_class, g_cp210x_buf, sizeof(g_cp210x_buf), 0xfffffff); + USB_LOG_RAW("in ret:%d\r\n", ret); + if (ret > 0) { + for (uint32_t i = 0; i < ret; i++) { + USB_LOG_RAW("%02x ", g_cp210x_buf[i]); + } + USB_LOG_RAW("\r\n"); + } + } +#endif + usbh_cp210x_run(cp210x_class); + return ret; +} + +static int usbh_cp210x_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_cp210x *cp210x_class = (struct usbh_cp210x *)hport->config.intf[intf].priv; + + if (cp210x_class) { + if (cp210x_class->bulkin) { + usbh_kill_urb(&cp210x_class->bulkin_urb); + } + + if (cp210x_class->bulkout) { + usbh_kill_urb(&cp210x_class->bulkout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister CP210X Class:%s\r\n", hport->config.intf[intf].devname); + usbh_cp210x_stop(cp210x_class); + } + + usbh_cp210x_class_free(cp210x_class); + } + + return ret; +} + +int usbh_cp210x_bulk_in_transfer(struct usbh_cp210x *cp210x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &cp210x_class->bulkin_urb; + + usbh_bulk_urb_fill(urb, cp210x_class->hport, cp210x_class->bulkin, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +int usbh_cp210x_bulk_out_transfer(struct usbh_cp210x *cp210x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &cp210x_class->bulkout_urb; + + usbh_bulk_urb_fill(urb, cp210x_class->hport, cp210x_class->bulkout, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +__WEAK void usbh_cp210x_run(struct usbh_cp210x *cp210x_class) +{ +} + +__WEAK void usbh_cp210x_stop(struct usbh_cp210x *cp210x_class) +{ +} + +static const uint16_t cp210x_id_table[][2] = { + { 0x10C4, 0xEA60 }, + { 0, 0 }, +}; + +const struct usbh_class_driver cp210x_class_driver = { + .driver_name = "cp210x", + .connect = usbh_cp210x_connect, + .disconnect = usbh_cp210x_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info cp210x_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .class = 0xff, + .subclass = 0x00, + .protocol = 0x00, + .id_table = cp210x_id_table, + .class_driver = &cp210x_class_driver +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.h b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.h new file mode 100644 index 00000000000..d380c36c584 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_cp210x.h @@ -0,0 +1,73 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CP210X_H +#define USBH_CP210X_H + +#include "usb_cdc.h" + +/* Requests */ +#define CP210X_IFC_ENABLE 0x00 +#define CP210X_SET_BAUDDIV 0x01 +#define CP210X_GET_BAUDDIV 0x02 +#define CP210X_SET_LINE_CTL 0x03 // Set parity, data bits, stop bits +#define CP210X_GET_LINE_CTL 0x04 +#define CP210X_SET_BREAK 0x05 +#define CP210X_IMM_CHAR 0x06 +#define CP210X_SET_MHS 0x07 // Set DTR, RTS +#define CP210X_GET_MDMSTS 0x08 +#define CP210X_SET_XON 0x09 +#define CP210X_SET_XOFF 0x0A +#define CP210X_SET_EVENTMASK 0x0B +#define CP210X_GET_EVENTMASK 0x0C +#define CP210X_SET_CHAR 0x0D +#define CP210X_GET_CHARS 0x0E +#define CP210X_GET_PROPS 0x0F +#define CP210X_GET_COMM_STATUS 0x10 +#define CP210X_RESET 0x11 +#define CP210X_PURGE 0x12 +#define CP210X_SET_FLOW 0x13 +#define CP210X_GET_FLOW 0x14 +#define CP210X_EMBED_EVENTS 0x15 +#define CP210X_GET_EVENTSTATE 0x16 +#define CP210X_SET_CHARS 0x19 +#define CP210X_GET_BAUDRATE 0x1D +#define CP210X_SET_BAUDRATE 0x1E // Set baudrate +#define CP210X_VENDOR_SPECIFIC 0xFF + +struct usbh_cp210x { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + + struct cdc_line_coding line_coding; + + uint8_t intf; + uint8_t minor; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_cp210x_set_line_coding(struct usbh_cp210x *ftdi_class, struct cdc_line_coding *line_coding); +int usbh_cp210x_get_line_coding(struct usbh_cp210x *ftdi_class, struct cdc_line_coding *line_coding); +int usbh_cp210x_set_line_state(struct usbh_cp210x *ftdi_class, bool dtr, bool rts); + +int usbh_cp210x_bulk_in_transfer(struct usbh_cp210x *cp210x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); +int usbh_cp210x_bulk_out_transfer(struct usbh_cp210x *cp210x_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); + +void usbh_cp210x_run(struct usbh_cp210x *cp210x_class); +void usbh_cp210x_stop(struct usbh_cp210x *cp210x_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CP210X_H */ diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c new file mode 100644 index 00000000000..c84d2d8c01b --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.c @@ -0,0 +1,363 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_ftdi.h" + +#define DEV_FORMAT "/dev/ttyUSB%d" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_ftdi_buf[64]; + +#define CONFIG_USBHOST_MAX_FTDI_CLASS 4 + +static struct usbh_ftdi g_ftdi_class[CONFIG_USBHOST_MAX_FTDI_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_ftdi *usbh_ftdi_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_FTDI_CLASS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_ftdi_class[devno], 0, sizeof(struct usbh_ftdi)); + g_ftdi_class[devno].minor = devno; + return &g_ftdi_class[devno]; + } + } + return NULL; +} + +static void usbh_ftdi_class_free(struct usbh_ftdi *ftdi_class) +{ + int devno = ftdi_class->minor; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(ftdi_class, 0, sizeof(struct usbh_ftdi)); +} + +static void usbh_ftdi_caculate_baudrate(uint32_t *itdf_divisor, uint32_t actual_baudrate) +{ +#define FTDI_USB_CLK 48000000 + int baudrate; + uint8_t frac[] = { 0, 8, 4, 2, 6, 10, 12, 14 }; + + if (actual_baudrate == 2000000) { + *itdf_divisor = 0x01; + } else if (actual_baudrate == 3000000) { + *itdf_divisor = 0x00; + } else { + baudrate = actual_baudrate; + if (baudrate > 100000 && baudrate < 12000000) { + baudrate = (baudrate / 100000) + 100000; + } + int divisor = FTDI_USB_CLK / baudrate; + int frac_bits = 0; + for (int i = 0; i < sizeof(frac) / sizeof(frac[0]); i++) { + if ((divisor & 0xF) == frac[i]) { + frac_bits = i; + break; + } + } + divisor >>= 4; + divisor &= 0x3FFF; + *itdf_divisor = (divisor << 14) | (frac_bits << 8); + } +} + +int usbh_ftdi_reset(struct usbh_ftdi *ftdi_class) +{ + struct usb_setup_packet *setup = ftdi_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = SIO_RESET_REQUEST; + setup->wValue = 0; + setup->wIndex = ftdi_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(ftdi_class->hport, setup, NULL); +} + +static int usbh_ftdi_set_modem(struct usbh_ftdi *ftdi_class, uint16_t value) +{ + struct usb_setup_packet *setup = ftdi_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = SIO_SET_MODEM_CTRL_REQUEST; + setup->wValue = value; + setup->wIndex = ftdi_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(ftdi_class->hport, setup, NULL); +} + +static int usbh_ftdi_set_baudrate(struct usbh_ftdi *ftdi_class, uint32_t baudrate) +{ + struct usb_setup_packet *setup = ftdi_class->hport->setup; + uint32_t itdf_divisor; + uint16_t value; + uint8_t baudrate_high; + + usbh_ftdi_caculate_baudrate(&itdf_divisor, baudrate); + value = itdf_divisor & 0xFFFF; + baudrate_high = (itdf_divisor >> 16) & 0xff; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = SIO_SET_BAUDRATE_REQUEST; + setup->wValue = value; + setup->wIndex = (baudrate_high << 8) | ftdi_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(ftdi_class->hport, setup, NULL); +} + +static int usbh_ftdi_set_data_format(struct usbh_ftdi *ftdi_class, uint8_t databits, uint8_t parity, uint8_t stopbits, uint8_t isbreak) +{ + /** + * D0-D7 databits BITS_7=7, BITS_8=8 + * D8-D10 parity NONE=0, ODD=1, EVEN=2, MARK=3, SPACE=4 + * D11-D12 STOP_BIT_1=0, STOP_BIT_15=1, STOP_BIT_2=2 + * D14 BREAK_OFF=0, BREAK_ON=1 + **/ + + uint16_t value = ((isbreak & 0x01) << 14) | ((stopbits & 0x03) << 11) | ((parity & 0x0f) << 8) | (databits & 0x0f); + + struct usb_setup_packet *setup = ftdi_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = SIO_SET_DATA_REQUEST; + setup->wValue = value; + setup->wIndex = ftdi_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(ftdi_class->hport, setup, NULL); +} + +static int usbh_ftdi_set_latency_timer(struct usbh_ftdi *ftdi_class, uint16_t value) +{ + struct usb_setup_packet *setup = ftdi_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = SIO_SET_LATENCY_TIMER_REQUEST; + setup->wValue = value; + setup->wIndex = ftdi_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(ftdi_class->hport, setup, NULL); +} + +static int usbh_ftdi_set_flow_ctrl(struct usbh_ftdi *ftdi_class, uint16_t value) +{ + struct usb_setup_packet *setup = ftdi_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = SIO_SET_FLOW_CTRL_REQUEST; + setup->wValue = value; + setup->wIndex = ftdi_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(ftdi_class->hport, setup, NULL); +} + +static int usbh_ftdi_read_modem_status(struct usbh_ftdi *ftdi_class) +{ + struct usb_setup_packet *setup = ftdi_class->hport->setup; + int ret; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = SIO_POLL_MODEM_STATUS_REQUEST; + setup->wValue = 0x0000; + setup->wIndex = ftdi_class->intf; + setup->wLength = 2; + + ret = usbh_control_transfer(ftdi_class->hport, setup, g_ftdi_buf); + if (ret < 0) { + return ret; + } + memcpy(ftdi_class->modem_status, g_ftdi_buf, 2); + return ret; +} + +int usbh_ftdi_set_line_coding(struct usbh_ftdi *ftdi_class, struct cdc_line_coding *line_coding) +{ + memcpy((uint8_t *)&ftdi_class->line_coding, line_coding, sizeof(struct cdc_line_coding)); + usbh_ftdi_set_baudrate(ftdi_class, line_coding->dwDTERate); + return usbh_ftdi_set_data_format(ftdi_class, line_coding->bDataBits, line_coding->bParityType, line_coding->bCharFormat, 0); +} + +int usbh_ftdi_get_line_coding(struct usbh_ftdi *ftdi_class, struct cdc_line_coding *line_coding) +{ + memcpy(line_coding, (uint8_t *)&ftdi_class->line_coding, sizeof(struct cdc_line_coding)); + return 0; +} + +int usbh_ftdi_set_line_state(struct usbh_ftdi *ftdi_class, bool dtr, bool rts) +{ + int ret; + + if (dtr) { + usbh_ftdi_set_modem(ftdi_class, SIO_SET_DTR_HIGH); + } else { + usbh_ftdi_set_modem(ftdi_class, SIO_SET_DTR_LOW); + } + + if (rts) { + ret = usbh_ftdi_set_modem(ftdi_class, SIO_SET_RTS_HIGH); + } else { + ret = usbh_ftdi_set_modem(ftdi_class, SIO_SET_RTS_LOW); + } + + return ret; +} + +static int usbh_ftdi_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret = 0; + + struct usbh_ftdi *ftdi_class = usbh_ftdi_class_alloc(); + if (ftdi_class == NULL) { + USB_LOG_ERR("Fail to alloc ftdi_class\r\n"); + return -USB_ERR_NOMEM; + } + + ftdi_class->hport = hport; + ftdi_class->intf = intf; + + hport->config.intf[intf].priv = ftdi_class; + + usbh_ftdi_reset(ftdi_class); + usbh_ftdi_set_flow_ctrl(ftdi_class, SIO_DISABLE_FLOW_CTRL); + usbh_ftdi_set_latency_timer(ftdi_class, 0x10); + usbh_ftdi_read_modem_status(ftdi_class); + USB_LOG_INFO("modem status:%02x:%02x\r\n", ftdi_class->modem_status[0], ftdi_class->modem_status[1]); + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(ftdi_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(ftdi_class->bulkout, ep_desc); + } + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, ftdi_class->minor); + + USB_LOG_INFO("Register FTDI Class:%s\r\n", hport->config.intf[intf].devname); + +#if 0 + USB_LOG_INFO("Test ftdi rx and tx and rx for 5 times, baudrate is 115200\r\n"); + + struct cdc_line_coding linecoding; + uint8_t count = 5; + + linecoding.dwDTERate = 115200; + linecoding.bDataBits = 8; + linecoding.bParityType = 0; + linecoding.bCharFormat = 0; + usbh_ftdi_set_line_coding(ftdi_class, &linecoding); + usbh_ftdi_set_line_state(ftdi_class, true, false); + + memset(g_ftdi_buf, 'a', sizeof(g_ftdi_buf)); + ret = usbh_ftdi_bulk_out_transfer(ftdi_class, g_ftdi_buf, sizeof(g_ftdi_buf), 0xfffffff); + USB_LOG_RAW("out ret:%d\r\n", ret); + while (count--) { + ret = usbh_ftdi_bulk_in_transfer(ftdi_class, g_ftdi_buf, sizeof(g_ftdi_buf), 0xfffffff); + USB_LOG_RAW("in ret:%d\r\n", ret); + if (ret > 0) { + for (uint32_t i = 0; i < ret; i++) { + USB_LOG_RAW("%02x ", g_ftdi_buf[i]); + } + } + USB_LOG_RAW("\r\n"); + } +#endif + usbh_ftdi_run(ftdi_class); + return ret; +} + +static int usbh_ftdi_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_ftdi *ftdi_class = (struct usbh_ftdi *)hport->config.intf[intf].priv; + + if (ftdi_class) { + if (ftdi_class->bulkin) { + usbh_kill_urb(&ftdi_class->bulkin_urb); + } + + if (ftdi_class->bulkout) { + usbh_kill_urb(&ftdi_class->bulkout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister FTDI Class:%s\r\n", hport->config.intf[intf].devname); + usbh_ftdi_stop(ftdi_class); + } + + usbh_ftdi_class_free(ftdi_class); + } + + return ret; +} + +int usbh_ftdi_bulk_in_transfer(struct usbh_ftdi *ftdi_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &ftdi_class->bulkin_urb; + + usbh_bulk_urb_fill(urb, ftdi_class->hport, ftdi_class->bulkin, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +int usbh_ftdi_bulk_out_transfer(struct usbh_ftdi *ftdi_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &ftdi_class->bulkout_urb; + + usbh_bulk_urb_fill(urb, ftdi_class->hport, ftdi_class->bulkout, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +__WEAK void usbh_ftdi_run(struct usbh_ftdi *ftdi_class) +{ +} + +__WEAK void usbh_ftdi_stop(struct usbh_ftdi *ftdi_class) +{ +} + +static const uint16_t ftdi_id_table[][2] = { + { 0x0403, 0x6001 }, + { 0x0403, 0x6010 }, + { 0, 0 }, +}; + +const struct usbh_class_driver ftdi_class_driver = { + .driver_name = "ftdi", + .connect = usbh_ftdi_connect, + .disconnect = usbh_ftdi_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info ftdi_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .class = 0xff, + .subclass = 0x00, + .protocol = 0x00, + .id_table = ftdi_id_table, + .class_driver = &ftdi_class_driver +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.h b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.h new file mode 100644 index 00000000000..faaf52147f3 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_ftdi.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_FTDI_H +#define USBH_FTDI_H + +#include "usb_cdc.h" + +/* Requests */ +#define SIO_RESET_REQUEST 0x00 /* Reset the port */ +#define SIO_SET_MODEM_CTRL_REQUEST 0x01 /* Set the modem control register */ +#define SIO_SET_FLOW_CTRL_REQUEST 0x02 /* Set flow control register */ +#define SIO_SET_BAUDRATE_REQUEST 0x03 /* Set baud rate */ +#define SIO_SET_DATA_REQUEST 0x04 /* Set the data characteristics of the port */ +#define SIO_POLL_MODEM_STATUS_REQUEST 0x05 +#define SIO_SET_EVENT_CHAR_REQUEST 0x06 +#define SIO_SET_ERROR_CHAR_REQUEST 0x07 +#define SIO_SET_LATENCY_TIMER_REQUEST 0x09 +#define SIO_GET_LATENCY_TIMER_REQUEST 0x0A +#define SIO_SET_BITMODE_REQUEST 0x0B +#define SIO_READ_PINS_REQUEST 0x0C +#define SIO_READ_EEPROM_REQUEST 0x90 +#define SIO_WRITE_EEPROM_REQUEST 0x91 +#define SIO_ERASE_EEPROM_REQUEST 0x92 + +#define SIO_DISABLE_FLOW_CTRL 0x0 +#define SIO_RTS_CTS_HS (0x1 << 8) +#define SIO_DTR_DSR_HS (0x2 << 8) +#define SIO_XON_XOFF_HS (0x4 << 8) + +#define SIO_SET_DTR_MASK 0x1 +#define SIO_SET_DTR_HIGH (1 | (SIO_SET_DTR_MASK << 8)) +#define SIO_SET_DTR_LOW (0 | (SIO_SET_DTR_MASK << 8)) +#define SIO_SET_RTS_MASK 0x2 +#define SIO_SET_RTS_HIGH (2 | (SIO_SET_RTS_MASK << 8)) +#define SIO_SET_RTS_LOW (0 | (SIO_SET_RTS_MASK << 8)) + +#define SIO_RTS_CTS_HS (0x1 << 8) + +struct usbh_ftdi { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + + struct cdc_line_coding line_coding; + + uint8_t intf; + uint8_t minor; + uint8_t modem_status[2]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_ftdi_set_line_coding(struct usbh_ftdi *ftdi_class, struct cdc_line_coding *line_coding); +int usbh_ftdi_get_line_coding(struct usbh_ftdi *ftdi_class, struct cdc_line_coding *line_coding); +int usbh_ftdi_set_line_state(struct usbh_ftdi *ftdi_class, bool dtr, bool rts); + +int usbh_ftdi_bulk_in_transfer(struct usbh_ftdi *ftdi_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); +int usbh_ftdi_bulk_out_transfer(struct usbh_ftdi *ftdi_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); + +void usbh_ftdi_run(struct usbh_ftdi *ftdi_class); +void usbh_ftdi_stop(struct usbh_ftdi *ftdi_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_FTDI_H */ diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c new file mode 100644 index 00000000000..2305f445975 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.c @@ -0,0 +1,426 @@ +/* + * Copyright (c) 2024, sakumisu + * Copyright (c) 2024, Derek Konigsberg + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_pl2303.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_pl2303" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/ttyUSB%d" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_pl2303_buf[64]; + +#define CONFIG_USBHOST_MAX_PL2303_CLASS 4 + +#define UT_WRITE_VENDOR_DEVICE (USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE) +#define UT_READ_VENDOR_DEVICE (USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE) + +static struct usbh_pl2303 g_pl2303_class[CONFIG_USBHOST_MAX_PL2303_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_pl2303 *usbh_pl2303_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_PL2303_CLASS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_pl2303_class[devno], 0, sizeof(struct usbh_pl2303)); + g_pl2303_class[devno].minor = devno; + return &g_pl2303_class[devno]; + } + } + return NULL; +} + +static void usbh_pl2303_class_free(struct usbh_pl2303 *pl2303_class) +{ + int devno = pl2303_class->minor; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(pl2303_class, 0, sizeof(struct usbh_pl2303)); +} + +static int usbh_pl2303_get_chiptype(struct usbh_pl2303 *pl2303_class) +{ + int ret = 0; + + switch (pl2303_class->hport->device_desc.bcdDevice) { + case 0x0300: + pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303HX; + /* or TA, that is HX with external crystal */ + break; + case 0x0400: + pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303HXD; + /* or EA, that is HXD with ESD protection */ + /* or RA, that has internal voltage level converter that works only up to 1Mbaud (!) */ + break; + case 0x0500: + pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303HXD; + /* in fact it's TB, that is HXD with external crystal */ + break; + default: + /* NOTE: I have no info about the bcdDevice for the base PL2303 (up to 1.2Mbaud, + only fixed rates) and for PL2303SA (8-pin chip, up to 115200 baud */ + /* Determine the chip type. This algorithm is taken from Linux. */ + if (pl2303_class->hport->device_desc.bDeviceClass == 0x02) { + pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303; + } else if (pl2303_class->hport->device_desc.bMaxPacketSize0 == 0x40) { + pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303HX; + } else { + pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303; + } + break; + } + + /* + * The new chip revision PL2303HXN is only compatible with the new + * PLCOM_SET_REQUEST_PL2303HXN command. Issuing the old command + * PLCOM_SET_REQUEST to the new chip raises an error. Thus, PL2303HX + * and PL2303HXN can be distinguished by issuing an old-style request + * (on a status register) to the new chip and checking the error. + */ + if (pl2303_class->chiptype == USBH_PL2303_TYPE_PL2303HX) { + struct usb_setup_packet *setup = pl2303_class->hport->setup; + + setup->bmRequestType = UT_READ_VENDOR_DEVICE; + setup->bRequest = PL2303_SET_REQUEST; + setup->wValue = PL2303_STATUS_REG_PL2303HX; + setup->wIndex = 0; + setup->wLength = 1; + + ret = usbh_control_transfer(pl2303_class->hport, setup, g_pl2303_buf); + if (ret == -USB_ERR_STALL) { + pl2303_class->chiptype = USBH_PL2303_TYPE_PL2303HXN; + ret = 0; + } else if (ret < 0) { + USB_LOG_WRN("Error checking chip type: %d\r\n", ret); + return ret; + } + } + + switch (pl2303_class->chiptype) { + case USBH_PL2303_TYPE_PL2303: + USB_LOG_INFO("chiptype = 2303\r\n"); + break; + case USBH_PL2303_TYPE_PL2303HX: + USB_LOG_INFO("chiptype = 2303HX/TA\r\n"); + break; + case USBH_PL2303_TYPE_PL2303HXN: + USB_LOG_INFO("chiptype = 2303HXN\r\n"); + break; + case USBH_PL2303_TYPE_PL2303HXD: + USB_LOG_INFO("chiptype = 2303HXD/TB/RA/EA\r\n"); + break; + default: + USB_LOG_INFO("chiptype = [%d]\r\n", pl2303_class->chiptype); + break; + } + + return ret; +} + +static int usbh_pl2303_do(struct usbh_pl2303 *pl2303_class, + uint8_t req_type, uint8_t request, uint16_t value, uint16_t index, + uint16_t length) +{ + struct usb_setup_packet *setup = pl2303_class->hport->setup; + + setup->bmRequestType = req_type; + setup->bRequest = request; + setup->wValue = value; + setup->wIndex = index; + setup->wLength = length; + + return usbh_control_transfer(pl2303_class->hport, setup, g_pl2303_buf); +} + +int usbh_pl2303_set_line_coding(struct usbh_pl2303 *pl2303_class, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup = pl2303_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = pl2303_class->intf; + setup->wLength = 7; + + memcpy(g_pl2303_buf, line_coding, sizeof(struct cdc_line_coding)); + + return usbh_control_transfer(pl2303_class->hport, setup, g_pl2303_buf); +} + +int usbh_pl2303_get_line_coding(struct usbh_pl2303 *pl2303_class, struct cdc_line_coding *line_coding) +{ + struct usb_setup_packet *setup = pl2303_class->hport->setup; + int ret; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_LINE_CODING; + setup->wValue = 0; + setup->wIndex = pl2303_class->intf; + setup->wLength = 7; + + ret = usbh_control_transfer(pl2303_class->hport, setup, g_pl2303_buf); + if (ret < 0) { + return ret; + } + memcpy(line_coding, g_pl2303_buf, sizeof(struct cdc_line_coding)); + return ret; +} + +int usbh_pl2303_set_line_state(struct usbh_pl2303 *pl2303_class, bool dtr, bool rts) +{ + struct usb_setup_packet *setup = pl2303_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SET_CONTROL_LINE_STATE; + setup->wValue = (dtr << 0) | (rts << 1); + setup->wIndex = pl2303_class->intf; + setup->wLength = 0; + + return usbh_control_transfer(pl2303_class->hport, setup, NULL); +} + +static int usbh_pl2303_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret = 0; + + struct usbh_pl2303 *pl2303_class = usbh_pl2303_class_alloc(); + if (pl2303_class == NULL) { + USB_LOG_ERR("Fail to alloc pl2303_class\r\n"); + return -USB_ERR_NOMEM; + } + + pl2303_class->hport = hport; + pl2303_class->intf = intf; + + hport->config.intf[intf].priv = pl2303_class; + + do { + ret = usbh_pl2303_get_chiptype(pl2303_class); + if (ret < 0) { + break; + } + + /* Startup reset sequence, if necessary for the chip type */ + if (pl2303_class->chiptype != USBH_PL2303_TYPE_PL2303HXN) { + struct usb_setup_packet *setup = pl2303_class->hport->setup; + + setup->bmRequestType = UT_WRITE_VENDOR_DEVICE; + setup->bRequest = PL2303_SET_REQUEST; + setup->wValue = 0; + setup->wIndex = pl2303_class->intf; + setup->wLength = 0; + + ret = usbh_control_transfer(pl2303_class->hport, setup, g_pl2303_buf); + if (ret < 0) { + USB_LOG_WRN("Initialization reset failed: %d\r\n", ret); + break; + } + } + + if (pl2303_class->chiptype == USBH_PL2303_TYPE_PL2303) { + /* HX variants seem to lock up after a clear stall request. */ + /* + * The FreeBSD code sets the stall flags on the in and out pipes + * here. Have no idea exactly how to do this, or if it is necessary. + * May just leave this code unwritten until test hardware is available. + */ + } else if (pl2303_class->chiptype == USBH_PL2303_TYPE_PL2303HX || pl2303_class->chiptype == USBH_PL2303_TYPE_PL2303HXD) { + /* Reset upstream data pipes */ + ret = usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 8, 0, 0); + if (ret < 0) { + USB_LOG_WRN("Could not reset upstream data pipes (8,0): %d\r\n", ret); + break; + } + ret = usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 9, 0, 0); + if (ret < 0) { + USB_LOG_WRN("Could not reset upstream data pipes (9,0): %d\r\n", ret); + break; + } + } else if (pl2303_class->chiptype == USBH_PL2303_TYPE_PL2303HXN) { + /* Reset upstream data pipes */ + ret = usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST_PL2303HXN, 0x07, 0x03, 0); + if (ret < 0) { + USB_LOG_WRN("Could not reset upstream data pipes (7,3): %d\r\n", ret); + break; + } + } + + /* Final device initialization, if necessary for the chip type */ + if (pl2303_class->chiptype != USBH_PL2303_TYPE_PL2303HXN) { + if (usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8484, 0, 1) < 0 || + usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x0404, 0, 0) < 0 || + usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8484, 0, 1) < 0 || + usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8383, 0, 1) < 0 || + usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8484, 0, 1) < 0 || + usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x0404, 1, 0) < 0 || + usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8484, 0, 1) < 0 || + usbh_pl2303_do(pl2303_class, UT_READ_VENDOR_DEVICE, PL2303_SET_REQUEST, 0x8383, 0, 1) < 0 || + usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 0, 1, 0) < 0 || + usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 1, 0, 0) < 0) { + USB_LOG_WRN("Could not complete init sequence\r\n"); + ret = -USB_ERR_INVAL; + break; + } + + if (pl2303_class->chiptype != USBH_PL2303_TYPE_PL2303) { + ret = usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 2, 0x44, 0); + } else { + ret = usbh_pl2303_do(pl2303_class, UT_WRITE_VENDOR_DEVICE, PL2303_SET_REQUEST, 2, 0x24, 0); + } + if (ret < 0) { + USB_LOG_WRN("Could not complete final init request: %d\r\n", ret); + break; + } + } + } while (0); + + if (ret < 0) { + USB_LOG_ERR("Failed to initialize PL2303 device: %d\r\n", ret); + return ret; + } + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + continue; + } else { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(pl2303_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(pl2303_class->bulkout, ep_desc); + } + } + } + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, pl2303_class->minor); + + USB_LOG_INFO("Register PL2303 Class:%s\r\n", hport->config.intf[intf].devname); + +#if 0 + USB_LOG_INFO("Test pl2303 rx and tx and rx for 5 times, baudrate is 115200\r\n"); + + struct cdc_line_coding linecoding; + uint8_t count = 5; + + linecoding.dwDTERate = 115200; + linecoding.bDataBits = 8; + linecoding.bParityType = 0; + linecoding.bCharFormat = 0; + usbh_pl2303_set_line_coding(pl2303_class, &linecoding); + usbh_pl2303_set_line_state(pl2303_class, true, false); + + memset(g_pl2303_buf, 'a', sizeof(g_pl2303_buf)); + ret = usbh_pl2303_bulk_out_transfer(pl2303_class, g_pl2303_buf, sizeof(g_pl2303_buf), 0xfffffff); + USB_LOG_RAW("out ret:%d\r\n", ret); + while (count--) { + ret = usbh_pl2303_bulk_in_transfer(pl2303_class, g_pl2303_buf, sizeof(g_pl2303_buf), 0xfffffff); + USB_LOG_RAW("in ret:%d\r\n", ret); + if (ret > 0) { + for (uint32_t i = 0; i < ret; i++) { + USB_LOG_RAW("%02x ", g_pl2303_buf[i]); + } + } + USB_LOG_RAW("\r\n"); + } +#endif + + usbh_pl2303_run(pl2303_class); + return ret; +} + +static int usbh_pl2303_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_pl2303 *pl2303_class = (struct usbh_pl2303 *)hport->config.intf[intf].priv; + + if (pl2303_class) { + if (pl2303_class->bulkin) { + usbh_kill_urb(&pl2303_class->bulkin_urb); + } + + if (pl2303_class->bulkout) { + usbh_kill_urb(&pl2303_class->bulkout_urb); + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister PL2303 Class:%s\r\n", hport->config.intf[intf].devname); + usbh_pl2303_stop(pl2303_class); + } + + usbh_pl2303_class_free(pl2303_class); + } + + return ret; +} + +int usbh_pl2303_bulk_in_transfer(struct usbh_pl2303 *pl2303_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &pl2303_class->bulkin_urb; + + usbh_bulk_urb_fill(urb, pl2303_class->hport, pl2303_class->bulkin, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +int usbh_pl2303_bulk_out_transfer(struct usbh_pl2303 *pl2303_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout) +{ + int ret; + struct usbh_urb *urb = &pl2303_class->bulkout_urb; + + usbh_bulk_urb_fill(urb, pl2303_class->hport, pl2303_class->bulkout, buffer, buflen, timeout, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +__WEAK void usbh_pl2303_run(struct usbh_pl2303 *pl2303_class) +{ +} + +__WEAK void usbh_pl2303_stop(struct usbh_pl2303 *pl2303_class) +{ +} + +static const uint16_t pl2303_id_table[][2] = { + { 0x067B, 0x2303 }, // PL2303 Serial (ATEN/IOGEAR UC232A) + { 0x067B, 0x23A3 }, // PL2303HXN Serial, type GC + { 0x067B, 0x23B3 }, // PL2303HXN Serial, type GB + { 0x067B, 0x23C3 }, // PL2303HXN Serial, type GT + { 0x067B, 0x23D3 }, // PL2303HXN Serial, type GL + { 0x067B, 0x23E3 }, // PL2303HXN Serial, type GE + { 0x067B, 0x23F3 }, // PL2303HXN Serial, type GS + { 0, 0 }, +}; + +const struct usbh_class_driver pl2303_class_driver = { + .driver_name = "pl2303", + .connect = usbh_pl2303_connect, + .disconnect = usbh_pl2303_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info pl2303_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .class = 0xff, + .subclass = 0x00, + .protocol = 0x00, + .id_table = pl2303_id_table, + .class_driver = &pl2303_class_driver +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.h b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.h new file mode 100644 index 00000000000..2b3d05f9e2d --- /dev/null +++ b/components/drivers/usb/cherryusb/class/vendor/serial/usbh_pl2303.h @@ -0,0 +1,62 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_PL2303_H +#define USBH_PL2303_H + +#include "usb_cdc.h" + +#define PL2303_SET_REQUEST 0x01 +#define PL2303_SET_REQUEST_PL2303HXN 0x80 +#define PL2303_SET_CRTSCTS 0x41 +#define PL2303_SET_CRTSCTS_PL2303X 0x61 +#define PL2303_SET_CRTSCTS_PL2303HXN 0xFA +#define PL2303_CLEAR_CRTSCTS_PL2303HXN 0xFF +#define PL2303_CRTSCTS_REG_PL2303HXN 0x0A +#define PL2303_STATUS_REG_PL2303HX 0x8080 + +/* Different PL2303 IC types */ +#define USBH_PL2303_TYPE_UNKNOWN 0 +#define USBH_PL2303_TYPE_PL2303 1 +#define USBH_PL2303_TYPE_PL2303HX 2 +#define USBH_PL2303_TYPE_PL2303HXD 3 +#define USBH_PL2303_TYPE_PL2303HXN 4 + +struct usbh_pl2303 { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + + struct usbh_urb bulkout_urb; + struct usbh_urb bulkin_urb; + + struct cdc_line_coding linecoding; + + uint8_t intf; + uint8_t minor; + uint8_t chiptype; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_pl2303_set_line_coding(struct usbh_pl2303 *pl2303_class, struct cdc_line_coding *line_coding); +int usbh_pl2303_get_line_coding(struct usbh_pl2303 *pl2303_class, struct cdc_line_coding *line_coding); +int usbh_pl2303_set_line_state(struct usbh_pl2303 *pl2303_class, bool dtr, bool rts); + +int usbh_pl2303_bulk_in_transfer(struct usbh_pl2303 *pl2303_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); +int usbh_pl2303_bulk_out_transfer(struct usbh_pl2303 *pl2303_class, uint8_t *buffer, uint32_t buflen, uint32_t timeout); + +void usbh_pl2303_run(struct usbh_pl2303 *pl2303_class); +void usbh_pl2303_stop(struct usbh_pl2303 *pl2303_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_PL2303_H */ diff --git a/components/drivers/usb/cherryusb/class/video/usb_video.h b/components/drivers/usb/cherryusb/class/video/usb_video.h new file mode 100644 index 00000000000..4997526baab --- /dev/null +++ b/components/drivers/usb/cherryusb/class/video/usb_video.h @@ -0,0 +1,1198 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_VIDEO_H +#define USB_VIDEO_H + +#define USB_DEVICE_VIDEO_CLASS_VERSION_1_5 0 + +/*! @brief Video device subclass code */ +#define VIDEO_SC_UNDEFINED 0x00U +#define VIDEO_SC_VIDEOCONTROL 0x01U +#define VIDEO_SC_VIDEOSTREAMING 0x02U +#define VIDEO_SC_VIDEO_INTERFACE_COLLECTION 0x03U + +/*! @brief Video device protocol code */ +#define VIDEO_PC_PROTOCOL_UNDEFINED 0x00U +#define VIDEO_PC_PROTOCOL_15 0x01U + +/*! @brief Video device class-specific descriptor type */ +#define VIDEO_CS_UNDEFINED_DESCRIPTOR_TYPE 0x20U +#define VIDEO_CS_DEVICE_DESCRIPTOR_TYPE 0x21U +#define VIDEO_CS_CONFIGURATION_DESCRIPTOR_TYPE 0x22U +#define VIDEO_CS_STRING_DESCRIPTOR_TYPE 0x23U +#define VIDEO_CS_INTERFACE_DESCRIPTOR_TYPE 0x24U +#define VIDEO_CS_ENDPOINT_DESCRIPTOR_TYPE 0x25U + +/*! @brief Video device class-specific VC interface descriptor subtype */ +#define VIDEO_VC_DESCRIPTOR_UNDEFINED_DESCRIPTOR_SUBTYPE 0x00U +#define VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE 0x01U +#define VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE 0x02U +#define VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE 0x03U +#define VIDEO_VC_SELECTOR_UNIT_DESCRIPTOR_SUBTYPE 0x04U +#define VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE 0x05U +#define VIDEO_VC_EXTENSION_UNIT_DESCRIPTOR_SUBTYPE 0x06U +#define VIDEO_VC_ENCODING_UNIT_DESCRIPTOR_SUBTYPE 0x07U + +/*! @brief Video device class-specific VS interface descriptor subtype */ +#define VIDEO_VS_UNDEFINED_DESCRIPTOR_SUBTYPE 0x00U +#define VIDEO_VS_INPUT_HEADER_DESCRIPTOR_SUBTYPE 0x01U +#define VIDEO_VS_OUTPUT_HEADER_DESCRIPTOR_SUBTYPE 0x02U +#define VIDEO_VS_STILL_IMAGE_FRAME_DESCRIPTOR_SUBTYPE 0x03U +#define VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_SUBTYPE 0x04U +#define VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_SUBTYPE 0x05U +#define VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_SUBTYPE 0x06U +#define VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_SUBTYPE 0x07U +#define VIDEO_VS_FORMAT_MPEG2TS_DESCRIPTOR_SUBTYPE 0x0AU +#define VIDEO_VS_FORMAT_DV_DESCRIPTOR_SUBTYPE 0x0CU +#define VIDEO_VS_COLORFORMAT_DESCRIPTOR_SUBTYPE 0x0DU +#define VIDEO_VS_FORMAT_FRAME_BASED_DESCRIPTOR_SUBTYPE 0x10U +#define VIDEO_VS_FRAME_FRAME_BASED_DESCRIPTOR_SUBTYPE 0x11U +#define VIDEO_VS_FORMAT_STREAM_BASED_DESCRIPTOR_SUBTYPE 0x12U +#define VIDEO_VS_FORMAT_H264_DESCRIPTOR_SUBTYPE 0x13U +#define VIDEO_VS_FRAME_H264_DESCRIPTOR_SUBTYPE 0x14U +#define VIDEO_VS_FORMAT_H264_SIMULCAST_DESCRIPTOR_SUBTYPE 0x15U +#define VIDEO_VS_FORMAT_VP8_DESCRIPTOR_SUBTYPE 0x16U +#define VIDEO_VS_FRAME_VP8_DESCRIPTOR_SUBTYPE 0x17U +#define VIDEO_VS_FORMAT_VP8_SIMULCAST_DESCRIPTOR_SUBTYPE 0x18U + +/*! @brief Video device class-specific VC endpoint descriptor subtype */ +#define VIDEO_EP_UNDEFINED_DESCRIPTOR_SUBTYPE 0x00U +#define VIDEO_EP_GENERAL_DESCRIPTOR_SUBTYPE 0x01U +#define VIDEO_EP_ENDPOINT_DESCRIPTOR_SUBTYPE 0x02U +#define VIDEO_EP_INTERRUPT_DESCRIPTOR_SUBTYPE 0x03U + +/*! @brief Video device class-specific request code */ +#define VIDEO_REQUEST_UNDEFINED 0x00U +#define VIDEO_REQUEST_SET_CUR 0x01U +#define VIDEO_REQUEST_SET_CUR_ALL 0x11U +#define VIDEO_REQUEST_GET_CUR 0x81U +#define VIDEO_REQUEST_GET_MIN 0x82U +#define VIDEO_REQUEST_GET_MAX 0x83U +#define VIDEO_REQUEST_GET_RES 0x84U +#define VIDEO_REQUEST_GET_LEN 0x85U +#define VIDEO_REQUEST_GET_INFO 0x86U +#define VIDEO_REQUEST_GET_DEF 0x87U +#define VIDEO_REQUEST_GET_CUR_ALL 0x91U +#define VIDEO_REQUEST_GET_MIN_ALL 0x92U +#define VIDEO_REQUEST_GET_MAX_ALL 0x93U +#define VIDEO_REQUEST_GET_RES_ALL 0x94U +#define VIDEO_REQUEST_GET_DEF_ALL 0x97U + +/*! @brief Video device class-specific VideoControl interface control selector */ +#define VIDEO_VC_CONTROL_UNDEFINED 0x00U +#define VIDEO_VC_VIDEO_POWER_MODE_CONTROL 0x01U +#define VIDEO_VC_REQUEST_ERROR_CODE_CONTROL 0x02U + +/*! @brief Video device class-specific Terminal control selector */ +#define VIDEO_TE_CONTROL_UNDEFINED 0x00U + +/*! @brief Video device class-specific Selector Unit control selector */ +#define VIDEO_SU_CONTROL_UNDEFINED 0x00U +#define VIDEO_SU_INPUT_SELECT_CONTROL 0x01U + +/*! @brief Video device class-specific Camera Terminal control selector */ +#define VIDEO_CT_CONTROL_UNDEFINED 0x00U +#define VIDEO_CT_SCANNING_MODE_CONTROL 0x01U +#define VIDEO_CT_AE_MODE_CONTROL 0x02U +#define VIDEO_CT_AE_PRIORITY_CONTROL 0x03U +#define VIDEO_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x04U +#define VIDEO_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x05U +#define VIDEO_CT_FOCUS_ABSOLUTE_CONTROL 0x06U +#define VIDEO_CT_FOCUS_RELATIVE_CONTROL 0x07U +#define VIDEO_CT_FOCUS_AUTO_CONTROL 0x08U +#define VIDEO_CT_IRIS_ABSOLUTE_CONTROL 0x09U +#define VIDEO_CT_IRIS_RELATIVE_CONTROL 0x0AU +#define VIDEO_CT_ZOOM_ABSOLUTE_CONTROL 0x0BU +#define VIDEO_CT_ZOOM_RELATIVE_CONTROL 0x0CU +#define VIDEO_CT_PANTILT_ABSOLUTE_CONTROL 0x0DU +#define VIDEO_CT_PANTILT_RELATIVE_CONTROL 0x0EU +#define VIDEO_CT_ROLL_ABSOLUTE_CONTROL 0x0FU +#define VIDEO_CT_ROLL_RELATIVE_CONTROL 0x10U +#define VIDEO_CT_PRIVACY_CONTROL 0x11U +#define VIDEO_CT_FOCUS_SIMPLE_CONTROL 0x12U +#define VIDEO_CT_WINDOW_CONTROL 0x13U +#define VIDEO_CT_REGION_OF_INTEREST_CONTROL 0x14U + +/*! @brief Video device class-specific Processing Unit control selector */ +#define VIDEO_PU_CONTROL_UNDEFINED 0x00U +#define VIDEO_PU_BACKLIGHT_COMPENSATION_CONTROL 0x01U +#define VIDEO_PU_BRIGHTNESS_CONTROL 0x02U +#define VIDEO_PU_CONTRAST_CONTROL 0x03U +#define VIDEO_PU_GAIN_CONTROL 0x04U +#define VIDEO_PU_POWER_LINE_FREQUENCY_CONTROL 0x05U +#define VIDEO_PU_HUE_CONTROL 0x06U +#define VIDEO_PU_SATURATION_CONTROL 0x07U +#define VIDEO_PU_SHARPNESS_CONTROL 0x08U +#define VIDEO_PU_GAMMA_CONTROL 0x09U +#define VIDEO_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x0AU +#define VIDEO_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x0BU +#define VIDEO_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x0CU +#define VIDEO_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x0DU +#define VIDEO_PU_DIGITAL_MULTIPLIER_CONTROL 0x0EU +#define VIDEO_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x0FU +#define VIDEO_PU_HUE_AUTO_CONTROL 0x10U +#define VIDEO_PU_ANALOG_VIDEO_STANDARD_CONTROL 0x11U +#define VIDEO_PU_ANALOG_LOCK_STATUS_CONTROL 0x12U +#define VIDEO_PU_CONTRAST_AUTO_CONTROL 0x13U + +/*! @brief Video device class-specific Encoding Unit control selector */ +#define VIDEO_EU_CONTROL_UNDEFINED 0x00U +#define VIDEO_EU_SELECT_LAYER_CONTROL 0x01U +#define VIDEO_EU_PROFILE_TOOLSET_CONTROL 0x02U +#define VIDEO_EU_VIDEO_RESOLUTION_CONTROL 0x03U +#define VIDEO_EU_MIN_FRAME_INTERVAL_CONTROL 0x04U +#define VIDEO_EU_SLICE_MODE_CONTROL 0x05U +#define VIDEO_EU_RATE_CONTROL_MODE_CONTROL 0x06U +#define VIDEO_EU_AVERAGE_BITRATE_CONTROL 0x07U +#define VIDEO_EU_CPB_SIZE_CONTROL 0x08U +#define VIDEO_EU_PEAK_BIT_RATE_CONTROL 0x09U +#define VIDEO_EU_QUANTIZATION_PARAMS_CONTROL 0x0AU +#define VIDEO_EU_SYNC_REF_FRAME_CONTROL 0x0BU +#define VIDEO_EU_LTR_BUFFER_CONTROL 0x0CU +#define VIDEO_EU_LTR_PICTURE_CONTROL 0x0DU +#define VIDEO_EU_LTR_VALIDATION_CONTROL 0x0EU +#define VIDEO_EU_LEVEL_IDC_LIMIT_CONTROL 0x0FU +#define VIDEO_EU_SEI_PAYLOADTYPE_CONTROL 0x10U +#define VIDEO_EU_QP_RANGE_CONTROL 0x11U +#define VIDEO_EU_PRIORITY_CONTROL 0x12U +#define VIDEO_EU_START_OR_STOP_LAYER_CONTROL 0x13U +#define VIDEO_EU_ERROR_RESILIENCY_CONTROL 0x14U + +/*! @brief Video device class-specific Extension Unit control selector */ +#define VIDEO_XU_CONTROL_UNDEFINED 0x00U + +/*! @brief Video device class-specific VideoStreaming Interface control selector */ +#define VIDEO_VS_CONTROL_UNDEFINED 0x00U +#define VIDEO_VS_PROBE_CONTROL 0x01U +#define VIDEO_VS_COMMIT_CONTROL 0x02U +#define VIDEO_VS_STILL_PROBE_CONTROL 0x03U +#define VIDEO_VS_STILL_COMMIT_CONTROL 0x04U +#define VIDEO_VS_STILL_IMAGE_TRIGGER_CONTROL 0x05U +#define VIDEO_VS_STREAM_ERROR_CODE_CONTROL 0x06U +#define VIDEO_VS_GENERATE_KEY_FRAME_CONTROL 0x07U +#define VIDEO_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x08U +#define VIDEO_VS_SYNCH_DELAY_CONTROL 0x09U + +/*! @}*/ + +/*! + * @name USB Video class terminal types + * @{ + */ + +/*! @brief Video device USB terminal type */ +#define VIDEO_TT_VENDOR_SPECIFIC 0x0100U +#define VIDEO_TT_STREAMING 0x0101U + +/*! @brief Video device input terminal type */ +#define VIDEO_ITT_VENDOR_SPECIFIC 0x0200U +#define VIDEO_ITT_CAMERA 0x0201U +#define VIDEO_ITT_MEDIA_TRANSPORT_INPUT 0x0202U + +/*! @brief Video device output terminal type */ +#define VIDEO_OTT_VENDOR_SPECIFIC 0x0300U +#define VIDEO_OTT_DISPLAY 0x0301U +#define VIDEO_OTT_MEDIA_TRANSPORT_OUTPUT 0x0302U + +/*! @brief Video device external terminal type */ +#define VIDEO_ET_VENDOR_SPECIFIC 0x0400U +#define VIDEO_ET_COMPOSITE_CONNECTOR 0x0401U +#define VIDEO_ET_SVIDEO_CONNECTOR 0x0402U +#define VIDEO_ET_COMPONENT_CONNECTOR 0x0403U + +/*! @}*/ + +/*! + * @name USB Video class setup request types + * @{ + */ + +/*! @brief Video device class setup request set type */ +#define VIDEO_SET_REQUEST_INTERFACE 0x21U +#define VIDEO_SET_REQUEST_ENDPOINT 0x22U + +/*! @brief Video device class setup request get type */ +#define VIDEO_GET_REQUEST_INTERFACE 0xA1U +#define VIDEO_GET_REQUEST_ENDPOINT 0xA2U + +/*! @}*/ + +/*! @brief Video device still image trigger control */ +#define VIDEO_STILL_IMAGE_TRIGGER_NORMAL_OPERATION 0x00U +#define VIDEO_STILL_IMAGE_TRIGGER_TRANSMIT_STILL_IMAGE 0x01U +#define VIDEO_STILL_IMAGE_TRIGGER_TRANSMIT_STILL_IMAGE_VS_DEDICATED_BULK_PIPE 0x02U +#define VIDEO_STILL_IMAGE_TRIGGER_ABORT_STILL_IMAGE_TRANSMISSION 0x03U + +/*! + * @name USB Video device class-specific request commands + * @{ + */ + +/*! @brief Video device class-specific request GET CUR COMMAND */ +#define VIDEO_GET_CUR_VC_POWER_MODE_CONTROL 0x8101U +#define VIDEO_GET_CUR_VC_ERROR_CODE_CONTROL 0x8102U + +#define VIDEO_GET_CUR_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8121U +#define VIDEO_GET_CUR_PU_BRIGHTNESS_CONTROL 0x8122U +#define VIDEO_GET_CUR_PU_CONTRACT_CONTROL 0x8123U +#define VIDEO_GET_CUR_PU_GAIN_CONTROL 0x8124U +#define VIDEO_GET_CUR_PU_POWER_LINE_FREQUENCY_CONTROL 0x8125U +#define VIDEO_GET_CUR_PU_HUE_CONTROL 0x8126U +#define VIDEO_GET_CUR_PU_SATURATION_CONTROL 0x8127U +#define VIDEO_GET_CUR_PU_SHARRNESS_CONTROL 0x8128U +#define VIDEO_GET_CUR_PU_GAMMA_CONTROL 0x8129U +#define VIDEO_GET_CUR_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x812AU +#define VIDEO_GET_CUR_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x812BU +#define VIDEO_GET_CUR_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x812CU +#define VIDEO_GET_CUR_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x812DU +#define VIDEO_GET_CUR_PU_DIGITAL_MULTIPLIER_CONTROL 0x812EU +#define VIDEO_GET_CUR_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x812FU +#define VIDEO_GET_CUR_PU_HUE_AUTO_CONTROL 0x8130U +#define VIDEO_GET_CUR_PU_ANALOG_VIDEO_STANDARD_CONTROL 0x8131U +#define VIDEO_GET_CUR_PU_ANALOG_LOCK_STATUS_CONTROL 0x8132U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_CUR_PU_CONTRAST_AUTO_CONTROL 0x8133U +#endif + +#define VIDEO_GET_CUR_CT_SCANNING_MODE_CONTROL 0x8141U +#define VIDEO_GET_CUR_CT_AE_MODE_CONTROL 0x8142U +#define VIDEO_GET_CUR_CT_AE_PRIORITY_CONTROL 0x8143U +#define VIDEO_GET_CUR_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8144U +#define VIDEO_GET_CUR_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x8145U +#define VIDEO_GET_CUR_CT_FOCUS_ABSOLUTE_CONTROL 0x8146U +#define VIDEO_GET_CUR_CT_FOCUS_RELATIVE_CONTROL 0x8147U +#define VIDEO_GET_CUR_CT_FOCUS_AUTO_CONTROL 0x8148U +#define VIDEO_GET_CUR_CT_IRIS_ABSOLUTE_CONTROL 0x8149U +#define VIDEO_GET_CUR_CT_IRIS_RELATIVE_CONTROL 0x814AU +#define VIDEO_GET_CUR_CT_ZOOM_ABSOLUTE_CONTROL 0x814BU +#define VIDEO_GET_CUR_CT_ZOOM_RELATIVE_CONTROL 0x814CU +#define VIDEO_GET_CUR_CT_PANTILT_ABSOLUTE_CONTROL 0x814DU +#define VIDEO_GET_CUR_CT_PANTILT_RELATIVE_CONTROL 0x814EU +#define VIDEO_GET_CUR_CT_ROLL_ABSOLUTE_CONTROL 0x814FU +#define VIDEO_GET_CUR_CT_ROLL_RELATIVE_CONTROL 0x8150U +#define VIDEO_GET_CUR_CT_PRIVACY_CONTROL 0x8151U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_CUR_CT_FOCUS_SIMPLE_CONTROL 0x8152U +#define VIDEO_GET_CUR_CT_DIGITAL_WINDOW_CONTROL 0x8153U +#define VIDEO_GET_CUR_CT_REGION_OF_INTEREST_CONTROL 0x8154U +#endif + +#define VIDEO_GET_CUR_VS_PROBE_CONTROL 0x8161U +#define VIDEO_GET_CUR_VS_COMMIT_CONTROL 0x8162U +#define VIDEO_GET_CUR_VS_STILL_PROBE_CONTROL 0x8163U +#define VIDEO_GET_CUR_VS_STILL_COMMIT_CONTROL 0x8164U +#define VIDEO_GET_CUR_VS_STILL_IMAGE_TRIGGER_CONTROL 0x8165U +#define VIDEO_GET_CUR_VS_STREAM_ERROR_CODE_CONTROL 0x8166U +#define VIDEO_GET_CUR_VS_GENERATE_KEY_FRAME_CONTROL 0x8167U +#define VIDEO_GET_CUR_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8168U +#define VIDEO_GET_CUR_VS_SYNCH_DELAY_CONTROL 0x8169U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_CUR_EU_SELECT_LAYER_CONTROL 0x8181U +#define VIDEO_GET_CUR_EU_PROFILE_TOOLSET_CONTROL 0x8182U +#define VIDEO_GET_CUR_EU_VIDEO_RESOLUTION_CONTROL 0x8183U +#define VIDEO_GET_CUR_EU_MIN_FRAME_INTERVAL_CONTROL 0x8184U +#define VIDEO_GET_CUR_EU_SLICE_MODE_CONTROL 0x8185U +#define VIDEO_GET_CUR_EU_RATE_CONTROL_MODE_CONTROL 0x8186U +#define VIDEO_GET_CUR_EU_AVERAGE_BITRATE_CONTROL 0x8187U +#define VIDEO_GET_CUR_EU_CPB_SIZE_CONTROL 0x8188U +#define VIDEO_GET_CUR_EU_PEAK_BIT_RATE_CONTROL 0x8189U +#define VIDEO_GET_CUR_EU_QUANTIZATION_PARAMS_CONTROL 0x818AU +#define VIDEO_GET_CUR_EU_SYNC_REF_FRAME_CONTROL 0x818BU +#define VIDEO_GET_CUR_EU_LTR_BUFFER_CONTROL 0x818CU +#define VIDEO_GET_CUR_EU_LTR_PICTURE_CONTROL 0x818DU +#define VIDEO_GET_CUR_EU_LTR_VALIDATION_CONTROL 0x818EU +#define VIDEO_GET_CUR_EU_LEVEL_IDC_LIMIT_CONTROL 0x818FU +#define VIDEO_GET_CUR_EU_SEI_PAYLOADTYPE_CONTROL 0x8190U +#define VIDEO_GET_CUR_EU_QP_RANGE_CONTROL 0x8191U +#define VIDEO_GET_CUR_EU_PRIORITY_CONTROL 0x8192U +#define VIDEO_GET_CUR_EU_START_OR_STOP_LAYER_CONTROL 0x8193U +#define VIDEO_GET_CUR_EU_ERROR_RESILIENCY_CONTROL 0x8194U +#endif + +/*! @brief Video device class-specific request GET MIN COMMAND */ +#define VIDEO_GET_MIN_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8221U +#define VIDEO_GET_MIN_PU_BRIGHTNESS_CONTROL 0x8222U +#define VIDEO_GET_MIN_PU_CONTRACT_CONTROL 0x8223U +#define VIDEO_GET_MIN_PU_GAIN_CONTROL 0x8224U +#define VIDEO_GET_MIN_PU_HUE_CONTROL 0x8226U +#define VIDEO_GET_MIN_PU_SATURATION_CONTROL 0x8227U +#define VIDEO_GET_MIN_PU_SHARRNESS_CONTROL 0x8228U +#define VIDEO_GET_MIN_PU_GAMMA_CONTROL 0x8229U +#define VIDEO_GET_MIN_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x822AU +#define VIDEO_GET_MIN_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x822CU +#define VIDEO_GET_MIN_PU_DIGITAL_MULTIPLIER_CONTROL 0x822EU +#define VIDEO_GET_MIN_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x822FU + +#define VIDEO_GET_MIN_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8244U +#define VIDEO_GET_MIN_CT_FOCUS_ABSOLUTE_CONTROL 0x8246U +#define VIDEO_GET_MIN_CT_FOCUS_RELATIVE_CONTROL 0x8247U +#define VIDEO_GET_MIN_CT_IRIS_ABSOLUTE_CONTROL 0x8249U +#define VIDEO_GET_MIN_CT_ZOOM_ABSOLUTE_CONTROL 0x824BU +#define VIDEO_GET_MIN_CT_ZOOM_RELATIVE_CONTROL 0x824CU +#define VIDEO_GET_MIN_CT_PANTILT_ABSOLUTE_CONTROL 0x824DU +#define VIDEO_GET_MIN_CT_PANTILT_RELATIVE_CONTROL 0x824EU +#define VIDEO_GET_MIN_CT_ROLL_ABSOLUTE_CONTROL 0x824FU +#define VIDEO_GET_MIN_CT_ROLL_RELATIVE_CONTROL 0x8250U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_MIN_CT_DIGITAL_WINDOW_CONTROL 0x8251U +#define VIDEO_GET_MIN_CT_REGION_OF_INTEREST_CONTROL 0x8252U +#endif + +#define VIDEO_GET_MIN_VS_PROBE_CONTROL 0x8261U +#define VIDEO_GET_MIN_VS_STILL_PROBE_CONTROL 0x8263U +#define VIDEO_GET_MIN_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8268U +#define VIDEO_GET_MIN_VS_SYNCH_DELAY_CONTROL 0x8269U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_MIN_EU_VIDEO_RESOLUTION_CONTROL 0x8283U +#define VIDEO_GET_MIN_EU_MIN_FRAME_INTERVAL_CONTROL 0x8284U +#define VIDEO_GET_MIN_EU_SLICE_MODE_CONTROL 0x8285U +#define VIDEO_GET_MIN_EU_AVERAGE_BITRATE_CONTROL 0x8287U +#define VIDEO_GET_MIN_EU_CPB_SIZE_CONTROL 0x8288U +#define VIDEO_GET_MIN_EU_PEAK_BIT_RATE_CONTROL 0x8289U +#define VIDEO_GET_MIN_EU_QUANTIZATION_PARAMS_CONTROL 0x828AU +#define VIDEO_GET_MIN_EU_SYNC_REF_FRAME_CONTROL 0x828BU +#define VIDEO_GET_MIN_EU_LEVEL_IDC_LIMIT_CONTROL 0x828FU +#define VIDEO_GET_MIN_EU_SEI_PAYLOADTYPE_CONTROL 0x8290U +#define VIDEO_GET_MIN_EU_QP_RANGE_CONTROL 0x8291U +#endif + +/*! @brief Video device class-specific request GET MAX COMMAND */ +#define VIDEO_GET_MAX_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8321U +#define VIDEO_GET_MAX_PU_BRIGHTNESS_CONTROL 0x8322U +#define VIDEO_GET_MAX_PU_CONTRACT_CONTROL 0x8323U +#define VIDEO_GET_MAX_PU_GAIN_CONTROL 0x8324U +#define VIDEO_GET_MAX_PU_HUE_CONTROL 0x8326U +#define VIDEO_GET_MAX_PU_SATURATION_CONTROL 0x8327U +#define VIDEO_GET_MAX_PU_SHARRNESS_CONTROL 0x8328U +#define VIDEO_GET_MAX_PU_GAMMA_CONTROL 0x8329U +#define VIDEO_GET_MAX_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x832AU +#define VIDEO_GET_MAX_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x832CU +#define VIDEO_GET_MAX_PU_DIGITAL_MULTIPLIER_CONTROL 0x832EU +#define VIDEO_GET_MAX_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x832FU + +#define VIDEO_GET_MAX_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8344U +#define VIDEO_GET_MAX_CT_FOCUS_ABSOLUTE_CONTROL 0x8346U +#define VIDEO_GET_MAX_CT_FOCUS_RELATIVE_CONTROL 0x8347U +#define VIDEO_GET_MAX_CT_IRIS_ABSOLUTE_CONTROL 0x8349U +#define VIDEO_GET_MAX_CT_ZOOM_ABSOLUTE_CONTROL 0x834BU +#define VIDEO_GET_MAX_CT_ZOOM_RELATIVE_CONTROL 0x834CU +#define VIDEO_GET_MAX_CT_PANTILT_ABSOLUTE_CONTROL 0x834DU +#define VIDEO_GET_MAX_CT_PANTILT_RELATIVE_CONTROL 0x834EU +#define VIDEO_GET_MAX_CT_ROLL_ABSOLUTE_CONTROL 0x834FU +#define VIDEO_GET_MAX_CT_ROLL_RELATIVE_CONTROL 0x8350U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_MAX_CT_DIGITAL_WINDOW_CONTROL 0x8351U +#define VIDEO_GET_MAX_CT_REGION_OF_INTEREST_CONTROL 0x8352U +#endif + +#define VIDEO_GET_MAX_VS_PROBE_CONTROL 0x8361U +#define VIDEO_GET_MAX_VS_STILL_PROBE_CONTROL 0x8363U +#define VIDEO_GET_MAX_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8368U +#define VIDEO_GET_MAX_VS_SYNCH_DELAY_CONTROL 0x8369U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_MAX_EU_VIDEO_RESOLUTION_CONTROL 0x8383U +#define VIDEO_GET_MAX_EU_MIN_FRAME_INTERVAL_CONTROL 0x8384U +#define VIDEO_GET_MAX_EU_SLICE_MODE_CONTROL 0x8385U +#define VIDEO_GET_MAX_EU_AVERAGE_BITRATE_CONTROL 0x8387U +#define VIDEO_GET_MAX_EU_CPB_SIZE_CONTROL 0x8388U +#define VIDEO_GET_MAX_EU_PEAK_BIT_RATE_CONTROL 0x8389U +#define VIDEO_GET_MAX_EU_QUANTIZATION_PARAMS_CONTROL 0x838AU +#define VIDEO_GET_MAX_EU_SYNC_REF_FRAME_CONTROL 0x838BU +#define VIDEO_GET_MAX_EU_LTR_BUFFER_CONTROL 0x838CU +#define VIDEO_GET_MAX_EU_LEVEL_IDC_LIMIT_CONTROL 0x838FU +#define VIDEO_GET_MAX_EU_SEI_PAYLOADTYPE_CONTROL 0x8390U +#define VIDEO_GET_MAX_EU_QP_RANGE_CONTROL 0x8391U +#endif + +/*! @brief Video device class-specific request GET RES COMMAND */ +#define VIDEO_GET_RES_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8421U +#define VIDEO_GET_RES_PU_BRIGHTNESS_CONTROL 0x8422U +#define VIDEO_GET_RES_PU_CONTRACT_CONTROL 0x8423U +#define VIDEO_GET_RES_PU_GAIN_CONTROL 0x8424U +#define VIDEO_GET_RES_PU_HUE_CONTROL 0x8426U +#define VIDEO_GET_RES_PU_SATURATION_CONTROL 0x8427U +#define VIDEO_GET_RES_PU_SHARRNESS_CONTROL 0x8428U +#define VIDEO_GET_RES_PU_GAMMA_CONTROL 0x8429U +#define VIDEO_GET_RES_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x842AU +#define VIDEO_GET_RES_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x842CU +#define VIDEO_GET_RES_PU_DIGITAL_MULTIPLIER_CONTROL 0x842EU +#define VIDEO_GET_RES_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x842FU + +#define VIDEO_GET_RES_CT_AE_MODE_CONTROL 0x8442U +#define VIDEO_GET_RES_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8444U +#define VIDEO_GET_RES_CT_FOCUS_ABSOLUTE_CONTROL 0x8446U +#define VIDEO_GET_RES_CT_FOCUS_RELATIVE_CONTROL 0x8447U +#define VIDEO_GET_RES_CT_IRIS_ABSOLUTE_CONTROL 0x8449U +#define VIDEO_GET_RES_CT_ZOOM_ABSOLUTE_CONTROL 0x844BU +#define VIDEO_GET_RES_CT_ZOOM_RELATIVE_CONTROL 0x844CU +#define VIDEO_GET_RES_CT_PANTILT_ABSOLUTE_CONTROL 0x844DU +#define VIDEO_GET_RES_CT_PANTILT_RELATIVE_CONTROL 0x844EU +#define VIDEO_GET_RES_CT_ROLL_ABSOLUTE_CONTROL 0x844FU +#define VIDEO_GET_RES_CT_ROLL_RELATIVE_CONTROL 0x8450U + +#define VIDEO_GET_RES_VS_PROBE_CONTROL 0x8461U +#define VIDEO_GET_RES_VS_STILL_PROBE_CONTROL 0x8463U +#define VIDEO_GET_RES_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8468U +#define VIDEO_GET_RES_VS_SYNCH_DELAY_CONTROL 0x8469U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_RES_EU_AVERAGE_BITRATE_CONTROL 0x8487U +#define VIDEO_GET_RES_EU_CPB_SIZE_CONTROL 0x8488U +#define VIDEO_GET_RES_EU_PEAK_BIT_RATE_CONTROL 0x8489U +#define VIDEO_GET_RES_EU_QUANTIZATION_PARAMS_CONTROL 0x848AU +#define VIDEO_GET_RES_EU_ERROR_RESILIENCY_CONTROL 0x8494U +#endif + +/*! @brief Video device class-specific request GET LEN COMMAND */ + +#define VIDEO_GET_LEN_VS_PROBE_CONTROL 0x8561U +#define VIDEO_GET_LEN_VS_COMMIT_CONTROL 0x8562U +#define VIDEO_GET_LEN_VS_STILL_PROBE_CONTROL 0x8563U +#define VIDEO_GET_LEN_VS_STILL_COMMIT_CONTROL 0x8564U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_LEN_EU_SELECT_LAYER_CONTROL 0x8581U +#define VIDEO_GET_LEN_EU_PROFILE_TOOLSET_CONTROL 0x8582U +#define VIDEO_GET_LEN_EU_VIDEO_RESOLUTION_CONTROL 0x8583U +#define VIDEO_GET_LEN_EU_MIN_FRAME_INTERVAL_CONTROL 0x8584U +#define VIDEO_GET_LEN_EU_SLICE_MODE_CONTROL 0x8585U +#define VIDEO_GET_LEN_EU_RATE_CONTROL_MODE_CONTROL 0x8586U +#define VIDEO_GET_LEN_EU_AVERAGE_BITRATE_CONTROL 0x8587U +#define VIDEO_GET_LEN_EU_CPB_SIZE_CONTROL 0x8588U +#define VIDEO_GET_LEN_EU_PEAK_BIT_RATE_CONTROL 0x8589U +#define VIDEO_GET_LEN_EU_QUANTIZATION_PARAMS_CONTROL 0x858AU +#define VIDEO_GET_LEN_EU_SYNC_REF_FRAME_CONTROL 0x858BU +#define VIDEO_GET_LEN_EU_LTR_BUFFER_CONTROL 0x858CU +#define VIDEO_GET_LEN_EU_LTR_PICTURE_CONTROL 0x858DU +#define VIDEO_GET_LEN_EU_LTR_VALIDATION_CONTROL 0x858EU +#define VIDEO_GET_LEN_EU_QP_RANGE_CONTROL 0x8591U +#define VIDEO_GET_LEN_EU_PRIORITY_CONTROL 0x8592U +#define VIDEO_GET_LEN_EU_START_OR_STOP_LAYER_CONTROL 0x8593U +#endif + +/*! @brief Video device class-specific request GET INFO COMMAND */ +#define VIDEO_GET_INFO_VC_POWER_MODE_CONTROL 0x8601U +#define VIDEO_GET_INFO_VC_ERROR_CODE_CONTROL 0x8602U + +#define VIDEO_GET_INFO_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8621U +#define VIDEO_GET_INFO_PU_BRIGHTNESS_CONTROL 0x8622U +#define VIDEO_GET_INFO_PU_CONTRACT_CONTROL 0x8623U +#define VIDEO_GET_INFO_PU_GAIN_CONTROL 0x8624U +#define VIDEO_GET_INFO_PU_POWER_LINE_FREQUENCY_CONTROL 0x8625U +#define VIDEO_GET_INFO_PU_HUE_CONTROL 0x8626U +#define VIDEO_GET_INFO_PU_SATURATION_CONTROL 0x8627U +#define VIDEO_GET_INFO_PU_SHARRNESS_CONTROL 0x8628U +#define VIDEO_GET_INFO_PU_GAMMA_CONTROL 0x8629U +#define VIDEO_GET_INFO_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x862AU +#define VIDEO_GET_INFO_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x862BU +#define VIDEO_GET_INFO_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x862CU +#define VIDEO_GET_INFO_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x862DU +#define VIDEO_GET_INFO_PU_DIGITAL_MULTIPLIER_CONTROL 0x862EU +#define VIDEO_GET_INFO_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x862FU +#define VIDEO_GET_INFO_PU_HUE_AUTO_CONTROL 0x8630U +#define VIDEO_GET_INFO_PU_ANALOG_VIDEO_STANDARD_CONTROL 0x8631U +#define VIDEO_GET_INFO_PU_ANALOG_LOCK_STATUS_CONTROL 0x8632U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_INFO_PU_CONTRAST_AUTO_CONTROL 0x8633U +#endif + +#define VIDEO_GET_INFO_CT_SCANNING_MODE_CONTROL 0x8641U +#define VIDEO_GET_INFO_CT_AE_MODE_CONTROL 0x8642U +#define VIDEO_GET_INFO_CT_AE_PRIORITY_CONTROL 0x8643U +#define VIDEO_GET_INFO_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8644U +#define VIDEO_GET_INFO_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x8645U +#define VIDEO_GET_INFO_CT_FOCUS_ABSOLUTE_CONTROL 0x8646U +#define VIDEO_GET_INFO_CT_FOCUS_RELATIVE_CONTROL 0x8647U +#define VIDEO_GET_INFO_CT_FOCUS_AUTO_CONTROL 0x8648U +#define VIDEO_GET_INFO_CT_IRIS_ABSOLUTE_CONTROL 0x8649U +#define VIDEO_GET_INFO_CT_IRIS_RELATIVE_CONTROL 0x864AU +#define VIDEO_GET_INFO_CT_ZOOM_ABSOLUTE_CONTROL 0x864BU +#define VIDEO_GET_INFO_CT_ZOOM_RELATIVE_CONTROL 0x864CU +#define VIDEO_GET_INFO_CT_PANTILT_ABSOLUTE_CONTROL 0x864DU +#define VIDEO_GET_INFO_CT_PANTILT_RELATIVE_CONTROL 0x864EU +#define VIDEO_GET_INFO_CT_ROLL_ABSOLUTE_CONTROL 0x864FU +#define VIDEO_GET_INFO_CT_ROLL_RELATIVE_CONTROL 0x8650U +#define VIDEO_GET_INFO_CT_PRIVACY_CONTROL 0x8651U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_INFO_CT_FOCUS_SIMPLE_CONTROL 0x8652U +#endif + +#define VIDEO_GET_INFO_VS_PROBE_CONTROL 0x8661U +#define VIDEO_GET_INFO_VS_COMMIT_CONTROL 0x8662U +#define VIDEO_GET_INFO_VS_STILL_PROBE_CONTROL 0x8663U +#define VIDEO_GET_INFO_VS_STILL_COMMIT_CONTROL 0x8664U +#define VIDEO_GET_INFO_VS_STILL_IMAGE_TRIGGER_CONTROL 0x8665U +#define VIDEO_GET_INFO_VS_STREAM_ERROR_CODE_CONTROL 0x8666U +#define VIDEO_GET_INFO_VS_GENERATE_KEY_FRAME_CONTROL 0x8667U +#define VIDEO_GET_INFO_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8668U +#define VIDEO_GET_INFO_VS_SYNCH_DELAY_CONTROL 0x8669U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_INFO_EU_SELECT_LAYER_CONTROL 0x8681U +#define VIDEO_GET_INFO_EU_PROFILE_TOOLSET_CONTROL 0x8682U +#define VIDEO_GET_INFO_EU_VIDEO_RESOLUTION_CONTROL 0x8683U +#define VIDEO_GET_INFO_EU_MIN_FRAME_INTERVAL_CONTROL 0x8684U +#define VIDEO_GET_INFO_EU_SLICE_MODE_CONTROL 0x8685U +#define VIDEO_GET_INFO_EU_RATE_CONTROL_MODE_CONTROL 0x8686U +#define VIDEO_GET_INFO_EU_AVERAGE_BITRATE_CONTROL 0x8687U +#define VIDEO_GET_INFO_EU_CPB_SIZE_CONTROL 0x8688U +#define VIDEO_GET_INFO_EU_PEAK_BIT_RATE_CONTROL 0x8689U +#define VIDEO_GET_INFO_EU_QUANTIZATION_PARAMS_CONTROL 0x868AU +#define VIDEO_GET_INFO_EU_SYNC_REF_FRAME_CONTROL 0x868BU +#define VIDEO_GET_INFO_EU_LTR_BUFFER_CONTROL 0x868CU +#define VIDEO_GET_INFO_EU_LTR_PICTURE_CONTROL 0x868DU +#define VIDEO_GET_INFO_EU_LTR_VALIDATION_CONTROL 0x868EU +#define VIDEO_GET_INFO_EU_SEI_PAYLOADTYPE_CONTROL 0x8690U +#define VIDEO_GET_INFO_EU_QP_RANGE_CONTROL 0x8691U +#define VIDEO_GET_INFO_EU_PRIORITY_CONTROL 0x8692U +#define VIDEO_GET_INFO_EU_START_OR_STOP_LAYER_CONTROL 0x8693U +#endif + +/*! @brief Video device class-specific request GET DEF COMMAND */ +#define VIDEO_GET_DEF_PU_BACKLIGHT_COMPENSATION_CONTROL 0x8721U +#define VIDEO_GET_DEF_PU_BRIGHTNESS_CONTROL 0x8722U +#define VIDEO_GET_DEF_PU_CONTRACT_CONTROL 0x8723U +#define VIDEO_GET_DEF_PU_GAIN_CONTROL 0x8724U +#define VIDEO_GET_DEF_PU_POWER_LINE_FREQUENCY_CONTROL 0x8725U +#define VIDEO_GET_DEF_PU_HUE_CONTROL 0x8726U +#define VIDEO_GET_DEF_PU_SATURATION_CONTROL 0x8727U +#define VIDEO_GET_DEF_PU_SHARRNESS_CONTROL 0x8728U +#define VIDEO_GET_DEF_PU_GAMMA_CONTROL 0x8729U +#define VIDEO_GET_DEF_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x872AU +#define VIDEO_GET_DEF_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x872BU +#define VIDEO_GET_DEF_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x872CU +#define VIDEO_GET_DEF_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x872DU +#define VIDEO_GET_DEF_PU_DIGITAL_MULTIPLIER_CONTROL 0x872EU +#define VIDEO_GET_DEF_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x872FU +#define VIDEO_GET_DEF_PU_HUE_AUTO_CONTROL 0x8730U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_DEF_PU_CONTRAST_AUTO_CONTROL 0x8731U +#endif + +#define VIDEO_GET_DEF_CT_AE_MODE_CONTROL 0x8742U +#define VIDEO_GET_DEF_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x8744U +#define VIDEO_GET_DEF_CT_FOCUS_ABSOLUTE_CONTROL 0x8746U +#define VIDEO_GET_DEF_CT_FOCUS_RELATIVE_CONTROL 0x8747U +#define VIDEO_GET_DEF_CT_FOCUS_AUTO_CONTROL 0x8748U +#define VIDEO_GET_DEF_CT_IRIS_ABSOLUTE_CONTROL 0x8749U +#define VIDEO_GET_DEF_CT_ZOOM_ABSOLUTE_CONTROL 0x874BU +#define VIDEO_GET_DEF_CT_ZOOM_RELATIVE_CONTROL 0x874CU +#define VIDEO_GET_DEF_CT_PANTILT_ABSOLUTE_CONTROL 0x874DU +#define VIDEO_GET_DEF_CT_PANTILT_RELATIVE_CONTROL 0x874EU +#define VIDEO_GET_DEF_CT_ROLL_ABSOLUTE_CONTROL 0x874FU +#define VIDEO_GET_DEF_CT_ROLL_RELATIVE_CONTROL 0x8750U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_DEF_CT_FOCUS_SIMPLE_CONTROL 0x8751U +#define VIDEO_GET_DEF_CT_DIGITAL_WINDOW_CONTROL 0x8752U +#define VIDEO_GET_DEF_CT_REGION_OF_INTEREST_CONTROL 0x8753U +#endif + +#define VIDEO_GET_DEF_VS_PROBE_CONTROL 0x8761U +#define VIDEO_GET_DEF_VS_STILL_PROBE_CONTROL 0x8763U +#define VIDEO_GET_DEF_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x8768U +#define VIDEO_GET_DEF_VS_SYNCH_DELAY_CONTROL 0x8769U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_GET_DEF_EU_PROFILE_TOOLSET_CONTROL 0x8782U +#define VIDEO_GET_DEF_EU_VIDEO_RESOLUTION_CONTROL 0x8783U +#define VIDEO_GET_DEF_EU_MIN_FRAME_INTERVAL_CONTROL 0x8784U +#define VIDEO_GET_DEF_EU_SLICE_MODE_CONTROL 0x8785U +#define VIDEO_GET_DEF_EU_RATE_CONTROL_MODE_CONTROL 0x8786U +#define VIDEO_GET_DEF_EU_AVERAGE_BITRATE_CONTROL 0x8787U +#define VIDEO_GET_DEF_EU_CPB_SIZE_CONTROL 0x8788U +#define VIDEO_GET_DEF_EU_PEAK_BIT_RATE_CONTROL 0x8789U +#define VIDEO_GET_DEF_EU_QUANTIZATION_PARAMS_CONTROL 0x878AU +#define VIDEO_GET_DEF_EU_LTR_BUFFER_CONTROL 0x878CU +#define VIDEO_GET_DEF_EU_LTR_PICTURE_CONTROL 0x878DU +#define VIDEO_GET_DEF_EU_LTR_VALIDATION_CONTROL 0x878EU +#define VIDEO_GET_DEF_EU_LEVEL_IDC_LIMIT_CONTROL 0x878FU +#define VIDEO_GET_DEF_EU_SEI_PAYLOADTYPE_CONTROL 0x8790U +#define VIDEO_GET_DEF_EU_QP_RANGE_CONTROL 0x8791U +#define VIDEO_GET_DEF_EU_ERROR_RESILIENCY_CONTROL 0x8794U +#endif + +/*! @brief Video device class-specific request SET CUR COMMAND */ +#define VIDEO_SET_CUR_VC_POWER_MODE_CONTROL 0x0101U + +#define VIDEO_SET_CUR_PU_BACKLIGHT_COMPENSATION_CONTROL 0x0121U +#define VIDEO_SET_CUR_PU_BRIGHTNESS_CONTROL 0x0122U +#define VIDEO_SET_CUR_PU_CONTRACT_CONTROL 0x0123U +#define VIDEO_SET_CUR_PU_GAIN_CONTROL 0x0124U +#define VIDEO_SET_CUR_PU_POWER_LINE_FREQUENCY_CONTROL 0x0125U +#define VIDEO_SET_CUR_PU_HUE_CONTROL 0x0126U +#define VIDEO_SET_CUR_PU_SATURATION_CONTROL 0x0127U +#define VIDEO_SET_CUR_PU_SHARRNESS_CONTROL 0x0128U +#define VIDEO_SET_CUR_PU_GAMMA_CONTROL 0x0129U +#define VIDEO_SET_CUR_PU_WHITE_BALANCE_TEMPERATURE_CONTROL 0x012AU +#define VIDEO_SET_CUR_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL 0x012BU +#define VIDEO_SET_CUR_PU_WHITE_BALANCE_COMPONENT_CONTROL 0x012CU +#define VIDEO_SET_CUR_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL 0x012DU +#define VIDEO_SET_CUR_PU_DIGITAL_MULTIPLIER_CONTROL 0x012EU +#define VIDEO_SET_CUR_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL 0x012FU +#define VIDEO_SET_CUR_PU_HUE_AUTO_CONTROL 0x0130U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_SET_CUR_PU_CONTRAST_AUTO_CONTROL 0x0131U +#endif + +#define VIDEO_SET_CUR_CT_SCANNING_MODE_CONTROL 0x0141U +#define VIDEO_SET_CUR_CT_AE_MODE_CONTROL 0x0142U +#define VIDEO_SET_CUR_CT_AE_PRIORITY_CONTROL 0x0143U +#define VIDEO_SET_CUR_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL 0x0144U +#define VIDEO_SET_CUR_CT_EXPOSURE_TIME_RELATIVE_CONTROL 0x0145U +#define VIDEO_SET_CUR_CT_FOCUS_ABSOLUTE_CONTROL 0x0146U +#define VIDEO_SET_CUR_CT_FOCUS_RELATIVE_CONTROL 0x0147U +#define VIDEO_SET_CUR_CT_FOCUS_AUTO_CONTROL 0x0148U +#define VIDEO_SET_CUR_CT_IRIS_ABSOLUTE_CONTROL 0x0149U +#define VIDEO_SET_CUR_CT_IRIS_RELATIVE_CONTROL 0x014AU +#define VIDEO_SET_CUR_CT_ZOOM_ABSOLUTE_CONTROL 0x014BU +#define VIDEO_SET_CUR_CT_ZOOM_RELATIVE_CONTROL 0x014CU +#define VIDEO_SET_CUR_CT_PANTILT_ABSOLUTE_CONTROL 0x014DU +#define VIDEO_SET_CUR_CT_PANTILT_RELATIVE_CONTROL 0x014EU +#define VIDEO_SET_CUR_CT_ROLL_ABSOLUTE_CONTROL 0x014FU +#define VIDEO_SET_CUR_CT_ROLL_RELATIVE_CONTROL 0x0150U +#define VIDEO_SET_CUR_CT_PRIVACY_CONTROL 0x0151U +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_SET_CUR_CT_FOCUS_SIMPLE_CONTROL 0x0152U +#define VIDEO_SET_CUR_CT_DIGITAL_WINDOW_CONTROL 0x0153U +#define VIDEO_SET_CUR_CT_REGION_OF_INTEREST_CONTROL 0x0154U +#endif + +#define VIDEO_SET_CUR_VS_PROBE_CONTROL 0x0161U +#define VIDEO_SET_CUR_VS_COMMIT_CONTROL 0x0162U +#define VIDEO_SET_CUR_VS_STILL_PROBE_CONTROL 0x0163U +#define VIDEO_SET_CUR_VS_STILL_COMMIT_CONTROL 0x0164U +#define VIDEO_SET_CUR_VS_STILL_IMAGE_TRIGGER_CONTROL 0x0165U +#define VIDEO_SET_CUR_VS_STREAM_ERROR_CODE_CONTROL 0x0166U +#define VIDEO_SET_CUR_VS_GENERATE_KEY_FRAME_CONTROL 0x0167U +#define VIDEO_SET_CUR_VS_UPDATE_FRAME_SEGMENT_CONTROL 0x0168U +#define VIDEO_SET_CUR_VS_SYNCH_DELAY_CONTROL 0x0169U + +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 +#define VIDEO_SET_CUR_EU_SELECT_LAYER_CONTROL 0x0181U +#define VIDEO_SET_CUR_EU_PROFILE_TOOLSET_CONTROL 0x0182U +#define VIDEO_SET_CUR_EU_VIDEO_RESOLUTION_CONTROL 0x0183U +#define VIDEO_SET_CUR_EU_MIN_FRAME_INTERVAL_CONTROL 0x0184U +#define VIDEO_SET_CUR_EU_SLICE_MODE_CONTROL 0x0185U +#define VIDEO_SET_CUR_EU_RATE_CONTROL_MODE_CONTROL 0x0186U +#define VIDEO_SET_CUR_EU_AVERAGE_BITRATE_CONTROL 0x0187U +#define VIDEO_SET_CUR_EU_CPB_SIZE_CONTROL 0x0188U +#define VIDEO_SET_CUR_EU_PEAK_BIT_RATE_CONTROL 0x0189U +#define VIDEO_SET_CUR_EU_QUANTIZATION_PARAMS_CONTROL 0x018AU +#define VIDEO_SET_CUR_EU_SYNC_REF_FRAME_CONTROL 0x018BU +#define VIDEO_SET_CUR_EU_LTR_BUFFER_CONTROL 0x018CU +#define VIDEO_SET_CUR_EU_LTR_PICTURE_CONTROL 0x018DU +#define VIDEO_SET_CUR_EU_LTR_VALIDATION_CONTROL 0x018EU +#define VIDEO_SET_CUR_EU_LEVEL_IDC_LIMIT_CONTROL 0x018FU +#define VIDEO_SET_CUR_EU_SEI_PAYLOADTYPE_CONTROL 0x0190U +#define VIDEO_SET_CUR_EU_QP_RANGE_CONTROL 0x0191U +#define VIDEO_SET_CUR_EU_PRIORITY_CONTROL 0x0192U +#define VIDEO_SET_CUR_EU_START_OR_STOP_LAYER_CONTROL 0x0193U +#define VIDEO_SET_CUR_EU_ERROR_RESILIENCY_CONTROL 0x0194U +#endif + +/*! @brief The payload header structure. */ +struct video_payload_header { + uint8_t bHeaderLength; /*!< The payload header length. */ + union { + uint8_t bmheaderInfo; /*!< The payload header bitmap field. */ + struct + { + uint8_t frameIdentifier : 1U; /*!< Frame Identifier. This bit toggles at each frame start boundary and stays + constant for the rest of the frame.*/ + uint8_t endOfFrame : 1U; /*!< End of Frame. This bit indicates the end of a video frame and is set in the + last video sample that belongs to a frame.*/ + uint8_t + presentationTimeStamp : 1U; /*!< Presentation Time Stamp. This bit, when set, indicates the presence of + a PTS field.*/ + uint8_t sourceClockReference : 1U; /*!< Source Clock Reference. This bit, when set, indicates the presence + of a SCR field.*/ + uint8_t reserved : 1U; /*!< Reserved. Set to 0. */ + uint8_t stillImage : 1U; /*!< Still Image. This bit, when set, identifies a video sample that belongs to a + still image.*/ + uint8_t errorBit : 1U; /*!< Error Bit. This bit, when set, indicates an error in the device streaming.*/ + uint8_t endOfHeader : 1U; /*!< End of Header. This bit, when set, indicates the end of the BFH fields.*/ + } headerInfoBits; + struct + { + uint8_t FID : 1U; /*!< Frame Identifier. This bit toggles at each frame start boundary and stays constant + for the rest of the frame.*/ + uint8_t EOI : 1U; /*!< End of Frame. This bit indicates the end of a video frame and is set in the last + video sample that belongs to a frame.*/ + uint8_t PTS : 1U; /*!< Presentation Time Stamp. This bit, when set, indicates the presence of a PTS field.*/ + uint8_t SCR : 1U; /*!< Source Clock Reference. This bit, when set, indicates the presence of a SCR field.*/ + uint8_t RES : 1U; /*!< Reserved. Set to 0. */ + uint8_t STI : 1U; /*!< Still Image. This bit, when set, identifies a video sample that belongs to a still + image.*/ + uint8_t ERR : 1U; /*!< Error Bit. This bit, when set, indicates an error in the device streaming.*/ + uint8_t EOH : 1U; /*!< End of Header. This bit, when set, indicates the end of the BFH fields.*/ + } headerInfoBitmap; + } headerInfoUnion; + uint32_t dwPresentationTime; /*!< Presentation time stamp (PTS) field.*/ + uint8_t bSourceClockReference[6]; /*!< Source clock reference (SCR) field.*/ +} __PACKED; + +/*! @brief The Video probe and commit controls structure.*/ +struct video_probe_and_commit_controls { + union { + uint8_t bmHint; /*!< Bit-field control indicating to the function what fields shall be kept fixed. */ + struct + { + uint8_t dwFrameInterval : 1U; /*!< dwFrameInterval field.*/ + uint8_t wKeyFrameRate : 1U; /*!< wKeyFrameRate field.*/ + uint8_t wPFrameRate : 1U; /*!< wPFrameRate field.*/ + uint8_t wCompQuality : 1U; /*!< wCompQuality field.*/ + uint8_t wCompWindowSize : 1U; /*!< wCompWindowSize field.*/ + uint8_t reserved : 3U; /*!< Reserved field.*/ + } hintBitmap; + } hintUnion; + union { + uint8_t bmHint; /*!< Bit-field control indicating to the function what fields shall be kept fixed. */ + struct + { + uint8_t reserved : 8U; /*!< Reserved field.*/ + } hintBitmap; + } hintUnion1; + uint8_t bFormatIndex; /*!< Video format index from a format descriptor.*/ + uint8_t bFrameIndex; /*!< Video frame index from a frame descriptor.*/ + uint32_t dwFrameInterval; /*!< Frame interval in 100ns units.*/ + uint16_t wKeyFrameRate; /*!< Key frame rate in key-frame per video-frame units.*/ + uint16_t wPFrameRate; /*!< PFrame rate in PFrame/key frame units.*/ + uint16_t wCompQuality; /*!< Compression quality control in abstract units 0U (lowest) to 10000U (highest).*/ + uint16_t wCompWindowSize; /*!< Window size for average bit rate control.*/ + uint16_t wDelay; /*!< Internal video streaming interface latency in ms from video data capture to presentation on + the USB.*/ + uint32_t dwMaxVideoFrameSize; /*!< Maximum video frame or codec-specific segment size in bytes.*/ + uint32_t dwMaxPayloadTransferSize; /*!< Specifies the maximum number of bytes that the device can transmit or + receive in a single payload transfer.*/ + uint32_t dwClockFrequency; /*!< The device clock frequency in Hz for the specified format. This specifies the + units used for the time information fields in the Video Payload Headers in the data + stream.*/ + uint8_t bmFramingInfo; /*!< Bit-field control supporting the following values: D0 Frame ID, D1 EOF.*/ + uint8_t bPreferedVersion; /*!< The preferred payload format version supported by the host or device for the + specified bFormatIndex value.*/ + uint8_t bMinVersion; /*!< The minimum payload format version supported by the device for the specified bFormatIndex + value.*/ + uint8_t bMaxVersion; /*!< The maximum payload format version supported by the device for the specified bFormatIndex + value.*/ +#if defined(USB_DEVICE_VIDEO_CLASS_VERSION_1_5) && USB_DEVICE_VIDEO_CLASS_VERSION_1_5 + uint8_t bUsage; /*!< This bitmap enables features reported by the bmUsages field of the Video Frame Descriptor.*/ + uint8_t + bBitDepthLuma; /*!< Represents bit_depth_luma_minus8 + 8U, which must be the same as bit_depth_chroma_minus8 + + 8.*/ + uint8_t bmSettings; /*!< A bitmap of flags that is used to discover and control specific features of a temporally + encoded video stream.*/ + uint8_t bMaxNumberOfRefFramesPlus1; /*!< Host indicates the maximum number of frames stored for use as references.*/ + uint16_t bmRateControlModes; /*!< This field contains 4U sub-fields, each of which is a 4U bit number.*/ + uint64_t bmLayoutPerStream; /*!< This field contains 4U sub-fields, each of which is a 2U byte number.*/ +#endif +} __PACKED; + +/*! @brief The Video still probe and still commit controls structure.*/ +struct video_still_probe_and_commit_controls { + uint8_t bFormatIndex; /*!< Video format index from a format descriptor.*/ + uint8_t bFrameIndex; /*!< Video frame index from a frame descriptor.*/ + uint8_t bCompressionIndex; /*!< Compression index from a frame descriptor.*/ + uint32_t dwMaxVideoFrameSize; /*!< Maximum still image size in bytes.*/ + uint32_t dwMaxPayloadTransferSize; /*!< Specifies the maximum number of bytes that the device can transmit or + receive in a single payload transfer.*/ +} __PACKED; + +struct video_cs_if_vc_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bcdVDC; + uint16_t wTotalLength; + uint32_t dwClockFrequency; + uint8_t bInCollection; + uint8_t baInterfaceNr[]; +} __PACKED; + +#define VIDEO_SIZEOF_VC_HEADER_DESC(n) (11 + n) + +struct video_cs_if_vc_input_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t iTerminal; + uint16_t wObjectiveFocalLenMin; + uint16_t wObjectiveFocalLenMax; + uint16_t wOcularFocalLength; + uint8_t bControlSize; + uint8_t bmaControls[]; +} __PACKED; + +#define VIDEO_SIZEOF_VC_INPUT_TERMINAL_DESC(n) (15 + n) + +struct video_cs_if_vc_processing_unit_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bUnitID; + uint8_t bSourceID; + uint16_t wMaxMultiplier; + uint8_t bControlSize; + // uint8_t bmaControls[]; + uint8_t iProcessing; + uint8_t bmVideoStandards; +} __PACKED; + +#define VIDEO_SIZEOF_VC_PROCESSING_UNIT_DESC(n) (10 + n) + +struct video_cs_if_vc_output_terminal_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bTerminalID; + uint16_t wTerminalType; + uint8_t bAssocTerminal; + uint8_t bSourceID; + uint8_t iTerminal; +} __PACKED; + +#define VIDEO_SIZEOF_VC_OUTPUT_TERMINAL_DESC 9 + +struct video_cs_ep_vc_ep_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint16_t wMaxTransferSize; +} __PACKED; + +#define VIDEO_SIZEOF_VC_EP_DESC 5 + +struct video_cs_if_vs_input_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumFormats; + uint16_t wTotalLength; + uint8_t bEndpointAddress; + uint8_t bmInfo; + uint8_t bTerminalLink; + uint8_t bStillCaptureMethod; + uint8_t bTriggerSupport; + uint8_t bTriggerUsage; + uint8_t bControlSize; + uint8_t bmaControls[]; +} __PACKED; + +#define VIDEO_SIZEOF_VS_INPUT_HEADER_DESC(p, n) (13 + p * n) + +struct video_cs_if_vs_output_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bNumFormats; + uint16_t wTotalLength; + uint8_t bEndpointAddress; + uint8_t bTerminalLink; + uint8_t bControlSize; + uint8_t bmaControls[]; +} __PACKED; + +#define VIDEO_SIZEOF_VS_OUTPUT_TERMINAL_DESC(p, n) (9 + p * n) + +struct video_cs_if_vs_format_uncompressed_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFormatIndex; + uint8_t bNumFrameDescriptors; + uint8_t guidFormat[16]; + uint8_t bBitsPerPixel; + uint8_t bDefaultFrameIndex; + uint8_t bAspectRatioX; + uint8_t bAspectRatioY; + uint8_t bmInterlaceFlags; + uint8_t bCopyProtect; +} __PACKED; + +#define VIDEO_SIZEOF_VS_FORMAT_UNCOMPRESSED_DESC (27) + +struct video_cs_if_vs_frame_uncompressed_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFormatIndex; + uint8_t bmCapabilities; + uint16_t wWidth; + uint16_t wHeight; + uint32_t dwMinBitRate; + uint32_t dwMaxBitRate; + uint32_t dwMaxVideoFrameBufferSize; + uint32_t dwDefaultFrameInterval; + uint8_t bFrameIntervalType; + uint32_t dwFrameInterval; +} __PACKED; + +#define VIDEO_SIZEOF_VS_FRAME_UNCOMPRESSED_DESC 30 + +struct video_cs_if_vs_format_mjpeg_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFormatIndex; + uint8_t bNumFrameDescriptors; + uint8_t bmFlags; + uint8_t bDefaultFrameIndex; + uint8_t bAspectRatioX; + uint8_t bAspectRatioY; + uint8_t bmInterlaceFlags; + uint8_t bCopyProtect; +} __PACKED; + +#define VIDEO_SIZEOF_VS_FORMAT_MJPEG_DESC 11 + +struct video_cs_if_vs_frame_mjpeg_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bFormatIndex; + uint8_t bmCapabilities; + uint16_t wWidth; + uint16_t wHeight; + uint32_t dwMinBitRate; + uint32_t dwMaxBitRate; + uint32_t dwMaxVideoFrameBufferSize; + uint32_t dwDefaultFrameInterval; + uint8_t bFrameIntervalType; + uint32_t dwFrameInterval1; + uint32_t dwFrameInterval2; +} __PACKED; + +#define VIDEO_SIZEOF_VS_FRAME_MJPEG_DESC(n) (26 + n) + +struct video_cs_if_vs_colorformat_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubType; + uint8_t bColorPrimaries; + uint8_t bXferCharacteristics; + uint8_t bMatrixCoefficients; +} __PACKED; + +#define VIDEO_SIZEOF_VS_COLORFORMAT_DESC 6 + +struct video_vc_input_terminal_bmcontrol_bitmap { + uint32_t scanning_mode : 1; + uint32_t auto_exposure_mode : 1; + uint32_t auto_exposure_priority : 1; + uint32_t exposure_time_absolute : 1; + uint32_t exposure_time_relative : 1; + uint32_t focus_absolute : 1; + uint32_t focus_relative : 1; + uint32_t iris_absolute : 1; + uint32_t iris_relative : 1; + uint32_t zoom_absolute : 1; + uint32_t zoom_relative : 1; + uint32_t pantilt_absolute : 1; + uint32_t pantilt_relative : 1; + uint32_t roll_absolute : 1; + uint32_t roll_relative : 1; + uint32_t reserved : 2; + uint32_t focus_auto : 1; + uint32_t pricvcy : 1; +}; + +struct video_vc_processing_unit_bmcontrol_bitmap { + uint16_t brightness : 1; + uint16_t contrast : 1; + uint16_t hue : 1; + uint16_t saturation : 1; + uint16_t sharpness : 1; + uint16_t gamma : 1; + uint16_t white_bal_temp : 1; + uint16_t white_bal_comp : 1; + uint16_t backlight_comp : 1; + uint16_t gain : 1; + uint16_t power_line_freq : 1; + uint16_t hue_auto : 1; + uint16_t white_bal_temp_auto : 1; + uint16_t white_bal_comp_auto : 1; + uint16_t digital_mult : 1; + uint16_t digital_mult_limit : 1; +}; + +struct video_camera_capabilities { + uint8_t support_get_request : 1; + uint8_t support_set_request : 1; + uint8_t disabled_by_automatic_mode : 1; + uint8_t auto_update_control : 1; + uint8_t async_control : 1; + uint8_t reserved : 3; +}; + +struct video_autoexposure_mode { + uint8_t manual_mode : 1; + uint8_t auto_mode : 1; + uint8_t shutter_priority_mode : 1; + uint8_t aperture_priority_mode : 1; + uint8_t reserved : 4; +}; + +#define VIDEO_GUID_YUY2 0x59, 0x55, 0x59, 0x32, 0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71 +#define VIDEO_GUID_NV12 0x4E, 0x56, 0x31, 0x32, 0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71 +#define VIDEO_GUID_M420 0x4D, 0x34, 0x32, 0x30, 0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71 +#define VIDEO_GUID_I420 0x49, 0x34, 0x32, 0x30, 0x00, 0x00, 0x10, 0x00, 0x80, 0x00, 0x00, 0xAA, 0x00, 0x38, 0x9B, 0x71 + +// clang-format off +#define VIDEO_VC_DESCRIPTOR_INIT(bFirstInterface, bNumEndpoints, bcdUVC, wTotalLength, dwClockFrequency, stridx) \ + /* Interface Association Descriptor */ \ + 0x08, \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, \ + bFirstInterface, \ + 0x02, \ + USB_DEVICE_CLASS_VIDEO, \ + VIDEO_SC_VIDEO_INTERFACE_COLLECTION, \ + 0x00, \ + 0x00, \ + /* VideoControl Interface Descriptor */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + 0x00, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + bNumEndpoints, /* bNumEndpoints:1 endpoint (interrupt endpoint) */ \ + USB_DEVICE_CLASS_VIDEO, /* bInterfaceClass : CC_VIDEO */ \ + VIDEO_SC_VIDEOCONTROL, /* bInterfaceSubClass : SC_VIDEOCONTROL */ \ + VIDEO_PC_PROTOCOL_UNDEFINED, /* bInterfaceProtocol : PC_PROTOCOL_UNDEFINED */ \ + stridx, /* iInterface:Index to string descriptor that contains the string */ \ + /*Class-specific VideoControl Interface Descriptor */ \ + 0x0d, /* bLength */ \ + 0x24, /* bDescriptorType : CS_INTERFACE */ \ + VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE, /* bDescriptorSubType : VC_HEADER subtype */ \ + WBVAL(bcdUVC), /* bcdUVC : Revision of class specification that this device is based upon.*/ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + DBVAL(dwClockFrequency), /* dwClockFrequency : 0x005b8d80 -> 6,000,000 == 6MHz*/ \ + 0x01, /* bInCollection : Number of streaming interfaces. */ \ + (uint8_t)(bFirstInterface + 1), /* baInterfaceNr(0) : VideoStreaming interface 1 belongs to this VideoControl interface.*/ \ + /* Input Terminal 1 -> Processing Unit 2 -> Output Terminal 3 */ \ + 0x12, \ + 0x24, \ + VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE, \ + 0x01, /* bTerminalID */ \ + WBVAL(VIDEO_ITT_CAMERA), /* wTerminalType : 0x0201 Camera Sensor*/ \ + 0x00, /* bAssocTerminal */ \ + 0x00, /* iTerminal */ \ + WBVAL(0x0000), /* wObjectiveFocalLengthMin */ \ + WBVAL(0x0000), /* wObjectiveFocalLengthMax */ \ + WBVAL(0x0000), /* wOcularFocalLength */ \ + 0x03, /* bControlSize */ \ + 0x00, 0x00, 0x00, /* bmControls */ \ + 0x0c, \ + 0x24, \ + VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE, \ + 0x02, /* bUnitID */ \ + 0x01, /* bSourceID */ \ + 0x00, 0x00, /* wMaxMultiplier */ \ + 0x02, /* bControlSize */ \ + 0x00, 0x00, /* bmControls */ \ + 0x00, /* iProcessing */ \ + 0x00, /* bmVideoStandards */ \ + 0x09, \ + 0x24, \ + VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE, \ + 0x03, /* bTerminalID */ \ + WBVAL(VIDEO_TT_STREAMING), \ + 0x00, /* bAssocTerminal */ \ + 0x02, /* bSourceID */ \ + 0x00 /* iTerminal */ + +#define VIDEO_VS_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bNumEndpoints) \ + /* Video Streaming (VS) Interface Descriptor */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType : INTERFACE */ \ + bInterfaceNumber, /* bInterfaceNumber: Index of this interface */ \ + bAlternateSetting, /* bAlternateSetting: Index of this alternate setting */ \ + bNumEndpoints, /* bNumEndpoints : 0 endpoints – no bandwidth used*/ \ + 0x0e, /* bInterfaceClass : CC_VIDEO */ \ + 0x02, /* bInterfaceSubClass : SC_VIDEOSTREAMING */ \ + 0x00, /* bInterfaceProtocol : PC_PROTOCOL_UNDEFINED */ \ + 0x00 /* iInterface : unused */ + +#define VIDEO_VS_HEADER_DESCRIPTOR_INIT(bNumFormats, wTotalLength, bEndpointAddress, ...) \ + /*Class-specific VideoStream Header Descriptor (Input) */ \ + 0x0d + PP_NARG(__VA_ARGS__), \ + 0x24, \ + VIDEO_VS_INPUT_HEADER_DESCRIPTOR_SUBTYPE, \ + bNumFormats, /* bNumFormats : One format descriptor follows. */ \ + WBVAL(wTotalLength), \ + bEndpointAddress, \ + 0x00, /* bmInfo : No dynamic format change supported. */ \ + 0x03, /* bTerminalLink : This VideoStreaming interface supplies terminal ID 2 (Output Terminal). */ \ + 0x00, /* bStillCaptureMethod : Device supports still image capture method 0. */ \ + 0x00, /* bTriggerSupport : Hardware trigger supported for still image capture */ \ + 0x00, /* bTriggerUsage : Hardware trigger should initiate a still image capture. */ \ + PP_NARG(__VA_ARGS__), /* bControlSize : Size of the bmaControls field */ \ + __VA_ARGS__ /* bmaControls : No VideoStreaming specific controls are supported.*/ + +#define VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_INIT(bFormatIndex, bNumFrameDescriptors, GUIDFormat) \ + /*Payload Format(UNCOMPRESSED) Descriptor */ \ + 0x1b, \ + 0x24, \ + VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_SUBTYPE, /* bDescriptorSubType : VS_FORMAT_UNCOMPRESSED subtype */ \ + bFormatIndex, /* bFormatIndex : First (and only) format descriptor */ \ + bNumFrameDescriptors, /* bNumFrameDescriptors : One frame descriptor for this format follows. */ \ + GUIDFormat, /* GUID Format YUY2 {32595559-0000-0010-8000-00AA00389B71} */ \ + 0x0c, /* bBitsPerPixel : Number of bits per pixel used to specify color in the decoded video frame - 16 for yuy2*/ \ + 0x01, /* bDefaultFrameIndex : Default frame index is 1. */ \ + 0x00, /* bAspectRatioX : Non-interlaced stream not required. */ \ + 0x00, /* bAspectRatioY : Non-interlaced stream not required. */ \ + 0x00, /* bmInterlaceFlags : Non-interlaced stream */ \ + 0x00 /* bCopyProtect : No restrictions imposed on the duplication of this video stream. */ + +#define VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_INIT(bFrameIndex, wWidth, wHeight, dwMinBitRate, dwMaxBitRate, \ + dwMaxVideoFrameBufferSize, dwDefaultFrameInterval, dwFrameInterval) \ + 0x1e, \ + 0x24, \ + VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_SUBTYPE, \ + bFrameIndex, \ + 0x00, \ + WBVAL(wWidth), \ + WBVAL(wHeight), \ + DBVAL(dwMinBitRate), \ + DBVAL(dwMaxBitRate), \ + DBVAL(dwMaxVideoFrameBufferSize), \ + DBVAL(dwDefaultFrameInterval), \ + 0x01, \ + DBVAL(dwFrameInterval) + +#define VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_INIT(bFormatIndex, bNumFrameDescriptors) \ + /*Payload Format(MJPEG) Descriptor */ \ + 0x0b, /* bLength */ \ + 0x24, /* bDescriptorType : CS_INTERFACE */ \ + 0x06, /* bDescriptorSubType : VS_FORMAT_MJPEG subtype */ \ + bFormatIndex, /* bFormatIndex : First (and only) format descriptor */ \ + bNumFrameDescriptors, /* bNumFrameDescriptors : One frame descriptor for this format follows. */ \ + 0x00, /* bmFlags : Uses fixed size samples.. */ \ + 0x01, /* bDefaultFrameIndex : Default frame index is 1. */ \ + 0x00, /* bAspectRatioX : Non-interlaced stream – not required. */ \ + 0x00, /* bAspectRatioY : Non-interlaced stream – not required. */ \ + 0x00, /* bmInterlaceFlags : Non-interlaced stream */ \ + 0x00 /* bCopyProtect : No restrictions imposed on the duplication of this video stream. */ + +#define VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_INIT(bFrameIndex, wWidth, wHeight, dwMinBitRate, dwMaxBitRate, \ + dwMaxVideoFrameBufferSize, dwDefaultFrameInterval, bFrameIntervalType, ...) \ + 0x1a + PP_NARG(__VA_ARGS__), /* bLength */ \ + 0x24, /* bDescriptorType : CS_INTERFACE */ \ + VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_SUBTYPE, /* bDescriptorSubType : VS_FRAME_MJPEG */ \ + bFrameIndex, /* bFrameIndex : First (and only) frame descriptor */ \ + 0x00, /* bmCapabilities : Still images using capture method 0 are supported at this frame setting.D1: Fixed frame-rate. */ \ + WBVAL(wWidth), /* wWidth (2bytes): Width of frame is 128 pixels. */ \ + WBVAL(wHeight), /* wHeight (2bytes): Height of frame is 64 pixels. */ \ + DBVAL(dwMinBitRate), /* dwMinBitRate (4bytes): Min bit rate in bits/s */ \ + DBVAL(dwMaxBitRate), /* dwMaxBitRate (4bytes): Max bit rate in bits/s */ \ + DBVAL(dwMaxVideoFrameBufferSize), /* dwMaxVideoFrameBufSize (4bytes): Maximum video or still frame size, in bytes. */ \ + dwDefaultFrameInterval, /* dwDefaultFrameInterval : 1,000,000 * 100ns -> 10 FPS */ \ + bFrameIntervalType, /* bFrameIntervalType : Indicates how the frame interval can be programmed. 0: Continuous frame interval 1..255: The number of discrete frame */ \ + __VA_ARGS__ +// clang-format on +#endif /*USB_VIDEO_H */ \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/video/usbd_video.c b/components/drivers/usb/cherryusb/class/video/usbd_video.c new file mode 100644 index 00000000000..07059ee0d73 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/video/usbd_video.c @@ -0,0 +1,789 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_video.h" + +struct video_entity_info { + uint8_t bDescriptorSubtype; + uint8_t bEntityId; + uint16_t wTerminalType; +}; + +struct usbd_video_priv { + struct video_probe_and_commit_controls probe; + struct video_probe_and_commit_controls commit; + uint8_t power_mode; + uint8_t error_code; + struct video_entity_info info[3]; +} g_usbd_video[CONFIG_USBDEV_MAX_BUS]; + +static int usbd_video_control_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t control_selector = (uint8_t)(setup->wValue >> 8); + + switch (control_selector) { + case VIDEO_VC_VIDEO_POWER_MODE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_SET_CUR: + break; + case VIDEO_REQUEST_GET_CUR: + break; + case VIDEO_REQUEST_GET_INFO: + break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + break; + case VIDEO_VC_REQUEST_ERROR_CODE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: + (*data)[0] = 0x06; + *len = 1; + break; + case VIDEO_REQUEST_GET_INFO: + break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + break; + default: + break; + } + + return 0; +} + +static int usbd_video_control_unit_terminal_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t entity_id = (uint8_t)(setup->wIndex >> 8); + uint8_t control_selector = (uint8_t)(setup->wValue >> 8); + + for (uint8_t i = 0; i < 3; i++) { + struct video_entity_info *entity_info = &g_usbd_video[busid].info[i]; + if (entity_info->bEntityId == entity_id) { + switch (entity_info->bDescriptorSubtype) { + case VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE: + if (entity_info->wTerminalType == VIDEO_ITT_CAMERA) { + switch (control_selector) { + case VIDEO_CT_AE_MODE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: + (*data)[0] = 0x08; + *len = 1; + break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint32_t dwExposureTimeAbsolute = 2500; + memcpy(*data, (uint8_t *)&dwExposureTimeAbsolute, 4); + *len = 4; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint32_t dwExposureTimeAbsolute = 5; //0.0005sec + memcpy(*data, (uint8_t *)&dwExposureTimeAbsolute, 4); + *len = 4; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint32_t dwExposureTimeAbsolute = 2500; //0.2500sec + memcpy(*data, (uint8_t *)&dwExposureTimeAbsolute, 4); + *len = 4; + } break; + case VIDEO_REQUEST_GET_RES: { + uint32_t dwExposureTimeAbsolute = 5; //0.0005sec + memcpy(*data, (uint8_t *)&dwExposureTimeAbsolute, 4); + *len = 4; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint32_t dwExposureTimeAbsolute = 2500; //0.2500sec + memcpy(*data, (uint8_t *)&dwExposureTimeAbsolute, 4); + *len = 4; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_CT_FOCUS_ABSOLUTE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wFocusAbsolute = 0x0080; + memcpy(*data, (uint8_t *)&wFocusAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wFocusAbsolute = 0; + memcpy(*data, (uint8_t *)&wFocusAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wFocusAbsolute = 0x00ff; + memcpy(*data, (uint8_t *)&wFocusAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wFocusAbsolute = 0x0001; + memcpy(*data, (uint8_t *)&wFocusAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wFocusAbsolute = 0x0080; + memcpy(*data, (uint8_t *)&wFocusAbsolute, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_CT_ZOOM_ABSOLUTE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wObjectiveFocalLength = 0x0064; + memcpy(*data, (uint8_t *)&wObjectiveFocalLength, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wObjectiveFocalLength = 0x0064; + memcpy(*data, (uint8_t *)&wObjectiveFocalLength, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wObjectiveFocalLength = 0x00c8; + memcpy(*data, (uint8_t *)&wObjectiveFocalLength, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wObjectiveFocalLength = 0x0001; + memcpy(*data, (uint8_t *)&wObjectiveFocalLength, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wObjectiveFocalLength = 0x0064; + memcpy(*data, (uint8_t *)&wObjectiveFocalLength, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_CT_ROLL_ABSOLUTE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wRollAbsolute = 0x0000; + memcpy(*data, (uint8_t *)&wRollAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wRollAbsolute = 0x0000; + memcpy(*data, (uint8_t *)&wRollAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wRollAbsolute = 0x00ff; + memcpy(*data, (uint8_t *)&wRollAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wRollAbsolute = 0x0001; + memcpy(*data, (uint8_t *)&wRollAbsolute, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wRollAbsolute = 0x0000; + memcpy(*data, (uint8_t *)&wRollAbsolute, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_CT_FOCUS_AUTO_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wFocusAuto = 0x0000; + memcpy(*data, (uint8_t *)&wFocusAuto, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + default: + USB_LOG_WRN("Unhandled Video Class control selector 0x%02x\r\n", control_selector); + return -1; + } + } else { + USB_LOG_WRN("Unhandled Video Class wTerminalType 0x%02x\r\n", entity_info->wTerminalType); + return -2; + } + break; + case VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_SELECTOR_UNIT_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE: + switch (control_selector) { + case VIDEO_PU_BACKLIGHT_COMPENSATION_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wBacklightCompensation = 0x0004; + memcpy(*data, (uint8_t *)&wBacklightCompensation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wBacklightCompensation = 0; + memcpy(*data, (uint8_t *)&wBacklightCompensation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wBacklightCompensation = 8; + memcpy(*data, (uint8_t *)&wBacklightCompensation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wBacklightCompensation = 1; + memcpy(*data, (uint8_t *)&wBacklightCompensation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wBacklightCompensation = 4; + memcpy(*data, (uint8_t *)&wBacklightCompensation, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_PU_BRIGHTNESS_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_SET_CUR: { + uint16_t wBrightness = (uint16_t)(*data)[1] << 8 | (uint16_t)(*data)[0]; + USB_LOG_INFO("Video set brightness:%d\r\n", wBrightness); + } break; + case VIDEO_REQUEST_GET_CUR: { + uint16_t wBrightness = 0x0080; + memcpy(*data, (uint8_t *)&wBrightness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wBrightness = 0x0001; + memcpy(*data, (uint8_t *)&wBrightness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wBrightness = 0x00ff; + memcpy(*data, (uint8_t *)&wBrightness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wBrightness = 0x0001; + memcpy(*data, (uint8_t *)&wBrightness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wBrightness = 0x0080; + memcpy(*data, (uint8_t *)&wBrightness, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_PU_CONTRAST_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wContrast = 0x0080; + memcpy(*data, (uint8_t *)&wContrast, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wContrast = 0x0001; + memcpy(*data, (uint8_t *)&wContrast, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wContrast = 0x00ff; + memcpy(*data, (uint8_t *)&wContrast, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wContrast = 0x0001; + memcpy(*data, (uint8_t *)&wContrast, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wContrast = 0x0080; + memcpy(*data, (uint8_t *)&wContrast, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_PU_HUE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wHue = 0x0080; + memcpy(*data, (uint8_t *)&wHue, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wHue = 0x0001; + memcpy(*data, (uint8_t *)&wHue, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wHue = 0x00ff; + memcpy(*data, (uint8_t *)&wHue, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wHue = 0x0001; + memcpy(*data, (uint8_t *)&wHue, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wHue = 0x0080; + memcpy(*data, (uint8_t *)&wHue, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_PU_SATURATION_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_MIN: { + uint16_t wSaturation = 0x0001; + memcpy(*data, (uint8_t *)&wSaturation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wSaturation = 0x00ff; + memcpy(*data, (uint8_t *)&wSaturation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wSaturation = 0x0001; + memcpy(*data, (uint8_t *)&wSaturation, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wSaturation = 0x0080; + memcpy(*data, (uint8_t *)&wSaturation, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_PU_SHARPNESS_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_MIN: { + uint16_t wSharpness = 0x0001; + memcpy(*data, (uint8_t *)&wSharpness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wSharpness = 0x00ff; + memcpy(*data, (uint8_t *)&wSharpness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wSharpness = 0x0001; + memcpy(*data, (uint8_t *)&wSharpness, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wSharpness = 0x0080; + memcpy(*data, (uint8_t *)&wSharpness, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_PU_GAIN_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_MIN: { + uint16_t wGain = 0; + memcpy(*data, (uint8_t *)&wGain, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wGain = 255; + memcpy(*data, (uint8_t *)&wGain, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wGain = 1; + memcpy(*data, (uint8_t *)&wGain, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wGain = 255; + memcpy(*data, (uint8_t *)&wGain, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_PU_WHITE_BALANCE_TEMPERATURE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wWhiteBalance_Temprature = 417; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MIN: { + uint16_t wWhiteBalance_Temprature = 300; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_MAX: { + uint16_t wWhiteBalance_Temprature = 600; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_RES: { + uint16_t wWhiteBalance_Temprature = 1; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature, 2); + *len = 2; + } break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; //struct video_camera_capabilities + *len = 1; + break; + case VIDEO_REQUEST_GET_DEF: { + uint16_t wWhiteBalance_Temprature = 417; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature, 2); + *len = 2; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: { + uint16_t wWhiteBalance_Temprature_Auto = 1; + memcpy(*data, (uint8_t *)&wWhiteBalance_Temprature_Auto, 1); + *len = 1; + } break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + default: + g_usbd_video[busid].error_code = 0x06; + USB_LOG_WRN("Unhandled Video Class control selector 0x%02x\r\n", control_selector); + return -1; + } + break; + case VIDEO_VC_EXTENSION_UNIT_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_ENCODING_UNIT_DESCRIPTOR_SUBTYPE: + break; + + default: + break; + } + } + } + return 0; +} + +static int usbd_video_stream_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t control_selector = (uint8_t)(setup->wValue >> 8); + + switch (control_selector) { + case VIDEO_VS_PROBE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_SET_CUR: + //memcpy((uint8_t *)&g_usbd_video[busid].probe, *data, setup->wLength); + break; + case VIDEO_REQUEST_GET_CUR: + memcpy(*data, (uint8_t *)&g_usbd_video[busid].probe, setup->wLength); + *len = sizeof(struct video_probe_and_commit_controls); + break; + + case VIDEO_REQUEST_GET_MIN: + case VIDEO_REQUEST_GET_MAX: + case VIDEO_REQUEST_GET_RES: + case VIDEO_REQUEST_GET_DEF: + memcpy(*data, (uint8_t *)&g_usbd_video[busid].probe, setup->wLength); + *len = sizeof(struct video_probe_and_commit_controls); + break; + case VIDEO_REQUEST_GET_LEN: + (*data)[0] = sizeof(struct video_probe_and_commit_controls); + *len = 1; + break; + + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; + *len = 1; + break; + + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_VS_COMMIT_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_SET_CUR: + //memcpy((uint8_t *)&g_usbd_video[busid].commit, *data, setup->wLength); + break; + case VIDEO_REQUEST_GET_CUR: + memcpy(*data, (uint8_t *)&g_usbd_video[busid].commit, setup->wLength); + *len = sizeof(struct video_probe_and_commit_controls); + break; + case VIDEO_REQUEST_GET_MIN: + case VIDEO_REQUEST_GET_MAX: + case VIDEO_REQUEST_GET_RES: + case VIDEO_REQUEST_GET_DEF: + memcpy(*data, (uint8_t *)&g_usbd_video[busid].commit, setup->wLength); + *len = sizeof(struct video_probe_and_commit_controls); + break; + + case VIDEO_REQUEST_GET_LEN: + (*data)[0] = sizeof(struct video_probe_and_commit_controls); + *len = 1; + break; + + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x03; + *len = 1; + break; + + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + case VIDEO_VS_STREAM_ERROR_CODE_CONTROL: + switch (setup->bRequest) { + case VIDEO_REQUEST_GET_CUR: + (*data)[0] = g_usbd_video[busid].error_code; + *len = 1; + break; + case VIDEO_REQUEST_GET_INFO: + (*data)[0] = 0x01; + *len = 1; + break; + default: + USB_LOG_WRN("Unhandled Video Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + break; + default: + break; + } + + return 0; +} + +static int video_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("Video Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + uint8_t intf_num = (uint8_t)setup->wIndex; + uint8_t entity_id = (uint8_t)(setup->wIndex >> 8); + + if (intf_num == 0) { /* Video Control Interface */ + if (entity_id == 0) { + return usbd_video_control_request_handler(busid, setup, data, len); /* Interface Control Requests */ + } else { + return usbd_video_control_unit_terminal_request_handler(busid, setup, data, len); /* Unit and Terminal Requests */ + } + } else if (intf_num == 1) { /* Video Stream Inteface */ + return usbd_video_stream_request_handler(busid, setup, data, len); /* Interface Stream Requests */ + } + return -1; +} + +static void video_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + g_usbd_video[busid].error_code = 0; + g_usbd_video[busid].power_mode = 0; + break; + + case USBD_EVENT_SET_INTERFACE: { + struct usb_interface_descriptor *intf = (struct usb_interface_descriptor *)arg; + if (intf->bAlternateSetting == 1) { + usbd_video_open(busid, intf->bInterfaceNumber); + } else { + usbd_video_close(busid, intf->bInterfaceNumber); + } + } + + break; + default: + break; + } +} + +void usbd_video_probe_and_commit_controls_init(uint8_t busid, uint32_t dwFrameInterval, uint32_t dwMaxVideoFrameSize, uint32_t dwMaxPayloadTransferSize) +{ + g_usbd_video[busid].probe.hintUnion.bmHint = 0x01; + g_usbd_video[busid].probe.hintUnion1.bmHint = 0; + g_usbd_video[busid].probe.bFormatIndex = 1; + g_usbd_video[busid].probe.bFrameIndex = 1; + g_usbd_video[busid].probe.dwFrameInterval = dwFrameInterval; + g_usbd_video[busid].probe.wKeyFrameRate = 0; + g_usbd_video[busid].probe.wPFrameRate = 0; + g_usbd_video[busid].probe.wCompQuality = 0; + g_usbd_video[busid].probe.wCompWindowSize = 0; + g_usbd_video[busid].probe.wDelay = 0; + g_usbd_video[busid].probe.dwMaxVideoFrameSize = dwMaxVideoFrameSize; + g_usbd_video[busid].probe.dwMaxPayloadTransferSize = dwMaxPayloadTransferSize; + g_usbd_video[busid].probe.dwClockFrequency = 0; + g_usbd_video[busid].probe.bmFramingInfo = 0; + g_usbd_video[busid].probe.bPreferedVersion = 0; + g_usbd_video[busid].probe.bMinVersion = 0; + g_usbd_video[busid].probe.bMaxVersion = 0; + + g_usbd_video[busid].commit.hintUnion.bmHint = 0x01; + g_usbd_video[busid].commit.hintUnion1.bmHint = 0; + g_usbd_video[busid].commit.bFormatIndex = 1; + g_usbd_video[busid].commit.bFrameIndex = 1; + g_usbd_video[busid].commit.dwFrameInterval = dwFrameInterval; + g_usbd_video[busid].commit.wKeyFrameRate = 0; + g_usbd_video[busid].commit.wPFrameRate = 0; + g_usbd_video[busid].commit.wCompQuality = 0; + g_usbd_video[busid].commit.wCompWindowSize = 0; + g_usbd_video[busid].commit.wDelay = 0; + g_usbd_video[busid].commit.dwMaxVideoFrameSize = dwMaxVideoFrameSize; + g_usbd_video[busid].commit.dwMaxPayloadTransferSize = dwMaxPayloadTransferSize; + g_usbd_video[busid].commit.dwClockFrequency = 0; + g_usbd_video[busid].commit.bmFramingInfo = 0; + g_usbd_video[busid].commit.bPreferedVersion = 0; + g_usbd_video[busid].commit.bMinVersion = 0; + g_usbd_video[busid].commit.bMaxVersion = 0; +} + +struct usbd_interface *usbd_video_init_intf(uint8_t busid, struct usbd_interface *intf, + uint32_t dwFrameInterval, + uint32_t dwMaxVideoFrameSize, + uint32_t dwMaxPayloadTransferSize) +{ + intf->class_interface_handler = video_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = video_notify_handler; + + g_usbd_video[busid].info[0].bDescriptorSubtype = VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE; + g_usbd_video[busid].info[0].bEntityId = 0x01; + g_usbd_video[busid].info[0].wTerminalType = VIDEO_ITT_CAMERA; + g_usbd_video[busid].info[1].bDescriptorSubtype = VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE; + g_usbd_video[busid].info[1].bEntityId = 0x03; + g_usbd_video[busid].info[1].wTerminalType = 0x00; + g_usbd_video[busid].info[2].bDescriptorSubtype = VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE; + g_usbd_video[busid].info[2].bEntityId = 0x02; + g_usbd_video[busid].info[2].wTerminalType = 0x00; + + usbd_video_probe_and_commit_controls_init(busid, dwFrameInterval, dwMaxVideoFrameSize, dwMaxPayloadTransferSize); + return intf; +} + +uint32_t usbd_video_mjpeg_payload_fill(uint8_t busid, uint8_t *input, uint32_t input_len, uint8_t *output, uint32_t *out_len) +{ + uint32_t packets; + uint32_t last_packet_size; + uint32_t picture_pos = 0; + static uint8_t uvc_header[2] = { 0x02, 0x80 }; + + packets = (input_len + (g_usbd_video[busid].probe.dwMaxPayloadTransferSize - 2) ) / (g_usbd_video[busid].probe.dwMaxPayloadTransferSize - 2); + last_packet_size = input_len - ((packets - 1) * (g_usbd_video[busid].probe.dwMaxPayloadTransferSize - 2)); + + for (size_t i = 0; i < packets; i++) { + output[g_usbd_video[busid].probe.dwMaxPayloadTransferSize * i] = uvc_header[0]; + output[g_usbd_video[busid].probe.dwMaxPayloadTransferSize * i + 1] = uvc_header[1]; + if (i == (packets - 1)) { + memcpy(&output[2 + g_usbd_video[busid].probe.dwMaxPayloadTransferSize * i], &input[picture_pos], last_packet_size); + output[g_usbd_video[busid].probe.dwMaxPayloadTransferSize * i + 1] |= (1 << 1); + } else { + memcpy(&output[2 + g_usbd_video[busid].probe.dwMaxPayloadTransferSize * i], &input[picture_pos], g_usbd_video[busid].probe.dwMaxPayloadTransferSize - 2); + picture_pos += g_usbd_video[busid].probe.dwMaxPayloadTransferSize - 2; + } + } + uvc_header[1] ^= 1; + *out_len = (input_len + 2 * packets); + return packets; +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/class/video/usbd_video.h b/components/drivers/usb/cherryusb/class/video/usbd_video.h new file mode 100644 index 00000000000..5044af69bc0 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/video/usbd_video.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_VIDEO_H +#define USBD_VIDEO_H + +#include "usb_video.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init video interface driver */ +struct usbd_interface *usbd_video_init_intf(uint8_t busid, struct usbd_interface *intf, + uint32_t dwFrameInterval, + uint32_t dwMaxVideoFrameSize, + uint32_t dwMaxPayloadTransferSize); + +void usbd_video_open(uint8_t busid, uint8_t intf); +void usbd_video_close(uint8_t busid, uint8_t intf); +uint32_t usbd_video_mjpeg_payload_fill(uint8_t busid, uint8_t *input, uint32_t input_len, uint8_t *output, uint32_t *out_len); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_VIDEO_H */ diff --git a/components/drivers/usb/cherryusb/class/video/usbh_video.c b/components/drivers/usb/cherryusb/class/video/usbh_video.c new file mode 100644 index 00000000000..06910668818 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/video/usbh_video.c @@ -0,0 +1,522 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_video.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_video" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/video%d" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ +#define DESC_bDescriptorSubType 2 /** Descriptor subtype offset */ +#define DESC_bNumFormats 3 /** Descriptor numformat offset */ +#define DESC_bNumFrameDescriptors 4 /** Descriptor numframe offset */ +#define DESC_bFormatIndex 3 /** Descriptor format index offset */ +#define DESC_bFrameIndex 3 /** Descriptor frame index offset */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_video_buf[128]; + +static const char *format_type[] = { "uncompressed", "mjpeg" }; + +static struct usbh_video g_video_class[CONFIG_USBHOST_MAX_VIDEO_CLASS]; +static uint32_t g_devinuse = 0; + +static struct usbh_video *usbh_video_class_alloc(void) +{ + int devno; + + for (devno = 0; devno < CONFIG_USBHOST_MAX_VIDEO_CLASS; devno++) { + if ((g_devinuse & (1 << devno)) == 0) { + g_devinuse |= (1 << devno); + memset(&g_video_class[devno], 0, sizeof(struct usbh_video)); + g_video_class[devno].minor = devno; + return &g_video_class[devno]; + } + } + return NULL; +} + +static void usbh_video_class_free(struct usbh_video *video_class) +{ + int devno = video_class->minor; + + if (devno >= 0 && devno < 32) { + g_devinuse &= ~(1 << devno); + } + memset(video_class, 0, sizeof(struct usbh_video)); +} + +int usbh_video_get(struct usbh_video *video_class, uint8_t request, uint8_t intf, uint8_t entity_id, uint8_t cs, uint8_t *buf, uint16_t len) +{ + struct usb_setup_packet *setup = video_class->hport->setup; + int ret; + uint8_t retry; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = request; + setup->wValue = cs << 8; + setup->wIndex = (entity_id << 8) | intf; + setup->wLength = len; + + retry = 0; + while (1) { + ret = usbh_control_transfer(video_class->hport, setup, g_video_buf); + if (ret > 0) { + break; + } + retry++; + + if (retry == 3) { + return ret; + } + } + + if (buf) { + memcpy(buf, g_video_buf, len); + } + + return ret; +} + +int usbh_video_set(struct usbh_video *video_class, uint8_t request, uint8_t intf, uint8_t entity_id, uint8_t cs, uint8_t *buf, uint16_t len) +{ + struct usb_setup_packet *setup = video_class->hport->setup; + int ret; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = request; + setup->wValue = cs << 8; + setup->wIndex = (entity_id << 8) | intf; + setup->wLength = len; + + memcpy(g_video_buf, buf, len); + + ret = usbh_control_transfer(video_class->hport, setup, g_video_buf); + usb_osal_msleep(50); + return ret; +} + +int usbh_videostreaming_get_cur_probe(struct usbh_video *video_class) +{ + return usbh_video_get(video_class, VIDEO_REQUEST_GET_CUR, video_class->data_intf, 0x00, VIDEO_VS_PROBE_CONTROL, (uint8_t *)&video_class->probe, 26); +} + +int usbh_videostreaming_set_cur_probe(struct usbh_video *video_class, uint8_t formatindex, uint8_t frameindex) +{ + video_class->probe.bFormatIndex = formatindex; + video_class->probe.bFrameIndex = frameindex; + video_class->probe.dwMaxPayloadTransferSize = 0; + video_class->probe.dwFrameInterval = 333333; + return usbh_video_set(video_class, VIDEO_REQUEST_SET_CUR, video_class->data_intf, 0x00, VIDEO_VS_PROBE_CONTROL, (uint8_t *)&video_class->probe, 26); +} + +int usbh_videostreaming_set_cur_commit(struct usbh_video *video_class, uint8_t formatindex, uint8_t frameindex) +{ + memcpy(&video_class->commit, &video_class->probe, sizeof(struct video_probe_and_commit_controls)); + video_class->commit.bFormatIndex = formatindex; + video_class->commit.bFrameIndex = frameindex; + video_class->commit.dwFrameInterval = 333333; + return usbh_video_set(video_class, VIDEO_REQUEST_SET_CUR, video_class->data_intf, 0x00, VIDEO_VS_COMMIT_CONTROL, (uint8_t *)&video_class->commit, 26); +} + +int usbh_video_open(struct usbh_video *video_class, + uint8_t format_type, + uint16_t wWidth, + uint16_t wHeight, + uint8_t altsetting) +{ + struct usb_setup_packet *setup = video_class->hport->setup; + struct usb_endpoint_descriptor *ep_desc; + uint8_t mult; + uint16_t mps; + int ret; + bool found = false; + uint8_t formatidx = 0; + uint8_t frameidx = 0; + uint8_t step; + + if (video_class->is_opened) { + return 0; + } + + for (uint8_t i = 0; i < video_class->num_of_formats; i++) { + if (format_type == video_class->format[i].format_type) { + formatidx = i + 1; + for (uint8_t j = 0; j < video_class->format[i].num_of_frames; j++) { + if ((wWidth == video_class->format[i].frame[j].wWidth) && + (wHeight == video_class->format[i].frame[j].wHeight)) { + frameidx = j + 1; + found = true; + break; + } + } + } + } + + if (found == false) { + return -USB_ERR_NODEV; + } + + if (altsetting > (video_class->num_of_intf_altsettings - 1)) { + return -USB_ERR_INVAL; + } + + /* Open video step: + * Get CUR request (probe) + * Set CUR request (probe) + * Get CUR request (probe) + * Get MAX request (probe) + * Get MIN request (probe) + * Get CUR request (probe) + * Set CUR request (commit) + * + */ + step = 0; + ret = usbh_videostreaming_get_cur_probe(video_class); + if (ret < 0) { + goto errout; + } + + step = 1; + ret = usbh_videostreaming_set_cur_probe(video_class, formatidx, frameidx); + if (ret < 0) { + goto errout; + } + + step = 2; + ret = usbh_videostreaming_get_cur_probe(video_class); + if (ret < 0) { + goto errout; + } + + step = 3; + ret = usbh_video_get(video_class, VIDEO_REQUEST_GET_MAX, video_class->data_intf, 0x00, VIDEO_VS_PROBE_CONTROL, NULL, 26); + if (ret < 0) { + goto errout; + } + + step = 4; + ret = usbh_video_get(video_class, VIDEO_REQUEST_GET_MIN, video_class->data_intf, 0x00, VIDEO_VS_PROBE_CONTROL, NULL, 26); + if (ret < 0) { + goto errout; + } + + step = 5; + ret = usbh_videostreaming_set_cur_probe(video_class, formatidx, frameidx); + if (ret < 0) { + goto errout; + } + + step = 6; + ret = usbh_videostreaming_get_cur_probe(video_class); + if (ret < 0) { + goto errout; + } + + step = 7; + ret = usbh_videostreaming_set_cur_commit(video_class, formatidx, frameidx); + if (ret < 0) { + goto errout; + } + + step = 8; + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = altsetting; + setup->wIndex = video_class->data_intf; + setup->wLength = 0; + + ret = usbh_control_transfer(video_class->hport, setup, NULL); + if (ret < 0) { + goto errout; + } + + ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[altsetting].ep[0].ep_desc; + mult = (ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT; + mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK; + if (ep_desc->bEndpointAddress & 0x80) { + video_class->isoin_mps = mps * (mult + 1); + USBH_EP_INIT(video_class->isoin, ep_desc); + } else { + video_class->isoout_mps = mps * (mult + 1); + USBH_EP_INIT(video_class->isoout, ep_desc); + } + + USB_LOG_INFO("Open video and select formatidx:%u, frameidx:%u, altsetting:%u\r\n", formatidx, frameidx, altsetting); + video_class->is_opened = true; + video_class->current_format = format_type; + return ret; + +errout: + USB_LOG_ERR("Fail to open video in step %u\r\n", step); + return ret; +} + +int usbh_video_close(struct usbh_video *video_class) +{ + struct usb_setup_packet *setup = video_class->hport->setup; + int ret = 0; + + USB_LOG_INFO("Close video device\r\n"); + + video_class->is_opened = false; + + if (video_class->isoin) { + video_class->isoin = NULL; + } + + if (video_class->isoout) { + video_class->isoout = NULL; + } + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = 0; + setup->wIndex = video_class->data_intf; + setup->wLength = 0; + + ret = usbh_control_transfer(video_class->hport, setup, NULL); + if (ret < 0) { + return ret; + } + return ret; +} + +void usbh_video_list_info(struct usbh_video *video_class) +{ + struct usb_endpoint_descriptor *ep_desc; + uint8_t mult; + uint16_t mps; + + USB_LOG_INFO("============= Video device information ===================\r\n"); + USB_LOG_RAW("bcdVDC:%04x\r\n", video_class->bcdVDC); + USB_LOG_RAW("Num of altsettings:%u\r\n", video_class->num_of_intf_altsettings); + + for (uint8_t i = 0; i < video_class->num_of_intf_altsettings; i++) { + if (i == 0) { + USB_LOG_RAW("Ingore altsetting 0\r\n"); + continue; + } + ep_desc = &video_class->hport->config.intf[video_class->data_intf].altsetting[i].ep[0].ep_desc; + + mult = (ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT; + mps = ep_desc->wMaxPacketSize & USB_MAXPACKETSIZE_MASK; + + USB_LOG_RAW("Altsetting:%u, Ep=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", + i, + ep_desc->bEndpointAddress, + ep_desc->bmAttributes, + mps, + ep_desc->bInterval, + mult); + } + + USB_LOG_RAW("bNumFormats:%u\r\n", video_class->num_of_formats); + for (uint8_t i = 0; i < video_class->num_of_formats; i++) { + USB_LOG_RAW(" FormatIndex:%u\r\n", i + 1); + USB_LOG_RAW(" FormatType:%s\r\n", format_type[video_class->format[i].format_type]); + USB_LOG_RAW(" bNumFrames:%u\r\n", video_class->format[i].num_of_frames); + USB_LOG_RAW(" Resolution:\r\n"); + for (uint8_t j = 0; j < video_class->format[i].num_of_frames; j++) { + USB_LOG_RAW(" FrameIndex:%u\r\n", j + 1); + USB_LOG_RAW(" wWidth: %d, wHeight: %d\r\n", + video_class->format[i].frame[j].wWidth, + video_class->format[i].frame[j].wHeight); + } + } + + USB_LOG_INFO("============= Video device information ===================\r\n"); +} + +static int usbh_video_ctrl_connect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret; + uint8_t cur_iface = 0xff; + // uint8_t cur_alt_setting = 0xff; + uint8_t frame_index = 0xff; + uint8_t format_index = 0xff; + uint8_t num_of_frames = 0xff; + uint8_t *p; + + struct usbh_video *video_class = usbh_video_class_alloc(); + if (video_class == NULL) { + USB_LOG_ERR("Fail to alloc video_class\r\n"); + return -USB_ERR_NOMEM; + } + + video_class->hport = hport; + video_class->ctrl_intf = intf; + video_class->data_intf = intf + 1; + video_class->num_of_intf_altsettings = hport->config.intf[intf + 1].altsetting_num; + + hport->config.intf[intf].priv = video_class; + + ret = usbh_video_close(video_class); + if (ret < 0) { + USB_LOG_ERR("Fail to close video device\r\n"); + return ret; + } + + p = hport->raw_config_desc; + while (p[DESC_bLength]) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + //cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + break; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + //ep_desc = (struct usb_endpoint_descriptor *)p; + break; + case VIDEO_CS_INTERFACE_DESCRIPTOR_TYPE: + if (cur_iface == video_class->ctrl_intf) { + switch (p[DESC_bDescriptorSubType]) { + case VIDEO_VC_HEADER_DESCRIPTOR_SUBTYPE: + video_class->bcdVDC = ((uint16_t)p[4] << 8) | (uint16_t)p[3]; + break; + case VIDEO_VC_INPUT_TERMINAL_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_OUTPUT_TERMINAL_DESCRIPTOR_SUBTYPE: + break; + case VIDEO_VC_PROCESSING_UNIT_DESCRIPTOR_SUBTYPE: + break; + + default: + break; + } + } else if (cur_iface == video_class->data_intf) { + switch (p[DESC_bDescriptorSubType]) { + case VIDEO_VS_INPUT_HEADER_DESCRIPTOR_SUBTYPE: + video_class->num_of_formats = p[DESC_bNumFormats]; + break; + case VIDEO_VS_FORMAT_UNCOMPRESSED_DESCRIPTOR_SUBTYPE: + format_index = p[DESC_bFormatIndex]; + num_of_frames = p[DESC_bNumFrameDescriptors]; + + video_class->format[format_index - 1].num_of_frames = num_of_frames; + video_class->format[format_index - 1].format_type = USBH_VIDEO_FORMAT_UNCOMPRESSED; + break; + case VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_SUBTYPE: + format_index = p[DESC_bFormatIndex]; + num_of_frames = p[DESC_bNumFrameDescriptors]; + + video_class->format[format_index - 1].num_of_frames = num_of_frames; + video_class->format[format_index - 1].format_type = USBH_VIDEO_FORMAT_MJPEG; + break; + case VIDEO_VS_FRAME_UNCOMPRESSED_DESCRIPTOR_SUBTYPE: + frame_index = p[DESC_bFrameIndex]; + + video_class->format[format_index - 1].frame[frame_index - 1].wWidth = ((struct video_cs_if_vs_frame_uncompressed_descriptor *)p)->wWidth; + video_class->format[format_index - 1].frame[frame_index - 1].wHeight = ((struct video_cs_if_vs_frame_uncompressed_descriptor *)p)->wHeight; + break; + case VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_SUBTYPE: + frame_index = p[DESC_bFrameIndex]; + + video_class->format[format_index - 1].frame[frame_index - 1].wWidth = ((struct video_cs_if_vs_frame_mjpeg_descriptor *)p)->wWidth; + video_class->format[format_index - 1].frame[frame_index - 1].wHeight = ((struct video_cs_if_vs_frame_mjpeg_descriptor *)p)->wHeight; + break; + default: + break; + } + } + + break; + + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + + usbh_video_list_info(video_class); + + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, video_class->minor); + + USB_LOG_INFO("Register Video Class:%s\r\n", hport->config.intf[intf].devname); + + usbh_video_run(video_class); + return ret; +} + +static int usbh_video_ctrl_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_video *video_class = (struct usbh_video *)hport->config.intf[intf].priv; + + if (video_class) { + if (video_class->isoin) { + } + + if (video_class->isoout) { + } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister Video Class:%s\r\n", hport->config.intf[intf].devname); + usbh_video_stop(video_class); + } + + usbh_video_class_free(video_class); + } + + return ret; +} + +static int usbh_video_streaming_connect(struct usbh_hubport *hport, uint8_t intf) +{ + return 0; +} + +static int usbh_video_streaming_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + return 0; +} + +__WEAK void usbh_video_run(struct usbh_video *video_class) +{ +} + +__WEAK void usbh_video_stop(struct usbh_video *video_class) +{ +} + +const struct usbh_class_driver video_ctrl_class_driver = { + .driver_name = "video_ctrl", + .connect = usbh_video_ctrl_connect, + .disconnect = usbh_video_ctrl_disconnect +}; + +const struct usbh_class_driver video_streaming_class_driver = { + .driver_name = "video_streaming", + .connect = usbh_video_streaming_connect, + .disconnect = usbh_video_streaming_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info video_ctrl_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .class = USB_DEVICE_CLASS_VIDEO, + .subclass = VIDEO_SC_VIDEOCONTROL, + .protocol = VIDEO_PC_PROTOCOL_UNDEFINED, + .id_table = NULL, + .class_driver = &video_ctrl_class_driver +}; + +CLASS_INFO_DEFINE const struct usbh_class_info video_streaming_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .class = USB_DEVICE_CLASS_VIDEO, + .subclass = VIDEO_SC_VIDEOSTREAMING, + .protocol = VIDEO_PC_PROTOCOL_UNDEFINED, + .id_table = NULL, + .class_driver = &video_streaming_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/video/usbh_video.h b/components/drivers/usb/cherryusb/class/video/usbh_video.h new file mode 100644 index 00000000000..dac5792c141 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/video/usbh_video.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_VIDEO_H +#define USBH_VIDEO_H + +#include "usb_video.h" + +#define USBH_VIDEO_FORMAT_UNCOMPRESSED 0 +#define USBH_VIDEO_FORMAT_MJPEG 1 + +struct usbh_video_resolution { + uint16_t wWidth; + uint16_t wHeight; +}; + +struct usbh_video_format { + struct usbh_video_resolution frame[12]; + uint8_t format_type; + uint8_t num_of_frames; +}; + +struct usbh_videoframe { + uint8_t *frame_buf; + uint32_t frame_bufsize; + uint32_t frame_format; + uint32_t frame_size; +}; + +struct usbh_videostreaming { + struct usbh_videoframe *frame; + uint32_t frame_format; + uint32_t bufoffset; + uint16_t width; + uint16_t height; +}; + +struct usbh_video { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *isoin; /* ISO IN endpoint */ + struct usb_endpoint_descriptor *isoout; /* ISO OUT endpoint */ + + uint8_t ctrl_intf; /* interface number */ + uint8_t data_intf; /* interface number */ + uint8_t minor; + struct video_probe_and_commit_controls probe; + struct video_probe_and_commit_controls commit; + uint16_t isoin_mps; + uint16_t isoout_mps; + bool is_opened; + uint8_t current_format; + uint16_t bcdVDC; + uint8_t num_of_intf_altsettings; + uint8_t num_of_formats; + struct usbh_video_format format[3]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_video_get(struct usbh_video *video_class, uint8_t request, uint8_t intf, uint8_t entity_id, uint8_t cs, uint8_t *buf, uint16_t len); +int usbh_video_set(struct usbh_video *video_class, uint8_t request, uint8_t intf, uint8_t entity_id, uint8_t cs, uint8_t *buf, uint16_t len); + +int usbh_video_open(struct usbh_video *video_class, + uint8_t format_type, + uint16_t wWidth, + uint16_t wHeight, + uint8_t altsetting); +int usbh_video_close(struct usbh_video *video_class); + +void usbh_video_list_info(struct usbh_video *video_class); + +void usbh_video_run(struct usbh_video *video_class); +void usbh_video_stop(struct usbh_video *video_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_VIDEO_H */ diff --git a/components/drivers/usb/cherryusb/class/wireless/ndis.h b/components/drivers/usb/cherryusb/class/wireless/ndis.h new file mode 100644 index 00000000000..80a6e66968f --- /dev/null +++ b/components/drivers/usb/cherryusb/class/wireless/ndis.h @@ -0,0 +1,270 @@ +/* This file has been prepared for Doxygen automatic documentation generation.*/ +/*! \file ndis.h *************************************************************** + * + * \brief + * This file contains the possible external configuration of the USB. + * + * \addtogroup usbstick + * + * + ******************************************************************************/ + +/** + \ingroup usbstick + \defgroup RNDIS RNDIS Support + @{ + */ + +/* + * ndis.h + * + * Modified by Colin O'Flynn + * ntddndis.h modified by Benedikt Spranger + * + * Thanks to the cygwin development team, + * espacially to Casper S. Hornstrup + * + * THIS SOFTWARE IS NOT COPYRIGHTED + * + * This source code is offered for use in the public domain. You may + * use, modify or distribute it freely. + * + * This code is distributed in the hope that it will be useful but + * WITHOUT ANY WARRANTY. ALL WARRANTIES, EXPRESS OR IMPLIED ARE HEREBY + * DISCLAIMED. This includes but is not limited to warranties of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * + */ + +#ifndef _LINUX_NDIS_H +#define _LINUX_NDIS_H + +#define NDIS_STATUS_MULTICAST_FULL 0xC0010009 +#define NDIS_STATUS_MULTICAST_EXISTS 0xC001000A +#define NDIS_STATUS_MULTICAST_NOT_FOUND 0xC001000B + +/* from drivers/net/sk98lin/h/skgepnmi.h */ +#define OID_PNP_CAPABILITIES 0xFD010100 +#define OID_PNP_SET_POWER 0xFD010101 +#define OID_PNP_QUERY_POWER 0xFD010102 +#define OID_PNP_ADD_WAKE_UP_PATTERN 0xFD010103 +#define OID_PNP_REMOVE_WAKE_UP_PATTERN 0xFD010104 +#define OID_PNP_ENABLE_WAKE_UP 0xFD010106 + +enum NDIS_DEVICE_POWER_STATE { + NdisDeviceStateUnspecified = 0, + NdisDeviceStateD0, + NdisDeviceStateD1, + NdisDeviceStateD2, + NdisDeviceStateD3, + NdisDeviceStateMaximum +}; + +struct NDIS_PM_WAKE_UP_CAPABILITIES { + enum NDIS_DEVICE_POWER_STATE MinMagicPacketWakeUp; + enum NDIS_DEVICE_POWER_STATE MinPatternWakeUp; + enum NDIS_DEVICE_POWER_STATE MinLinkChangeWakeUp; +}; + +/* NDIS_PNP_CAPABILITIES.Flags constants */ +#define NDIS_DEVICE_WAKE_UP_ENABLE 0x00000001 +#define NDIS_DEVICE_WAKE_ON_PATTERN_MATCH_ENABLE 0x00000002 +#define NDIS_DEVICE_WAKE_ON_MAGIC_PACKET_ENABLE 0x00000004 + +/* +struct NDIS_PNP_CAPABILITIES { + __le32 Flags; + struct NDIS_PM_WAKE_UP_CAPABILITIES WakeUpCapabilities; +}; + +struct NDIS_PM_PACKET_PATTERN { + __le32 Priority; + __le32 Reserved; + __le32 MaskSize; + __le32 PatternOffset; + __le32 PatternSize; + __le32 PatternFlags; +}; +*/ + +/* Required Object IDs (OIDs) */ +#define OID_GEN_SUPPORTED_LIST 0x00010101 +#define OID_GEN_HARDWARE_STATUS 0x00010102 +#define OID_GEN_MEDIA_SUPPORTED 0x00010103 +#define OID_GEN_MEDIA_IN_USE 0x00010104 +#define OID_GEN_MAXIMUM_LOOKAHEAD 0x00010105 +#define OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106 +#define OID_GEN_LINK_SPEED 0x00010107 +#define OID_GEN_TRANSMIT_BUFFER_SPACE 0x00010108 +#define OID_GEN_RECEIVE_BUFFER_SPACE 0x00010109 +#define OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010A +#define OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010B +#define OID_GEN_VENDOR_ID 0x0001010C +#define OID_GEN_VENDOR_DESCRIPTION 0x0001010D +#define OID_GEN_CURRENT_PACKET_FILTER 0x0001010E +#define OID_GEN_CURRENT_LOOKAHEAD 0x0001010F +#define OID_GEN_DRIVER_VERSION 0x00010110 +#define OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111 +#define OID_GEN_PROTOCOL_OPTIONS 0x00010112 +#define OID_GEN_MAC_OPTIONS 0x00010113 +#define OID_GEN_MEDIA_CONNECT_STATUS 0x00010114 +#define OID_GEN_MAXIMUM_SEND_PACKETS 0x00010115 +#define OID_GEN_VENDOR_DRIVER_VERSION 0x00010116 +#define OID_GEN_SUPPORTED_GUIDS 0x00010117 +#define OID_GEN_NETWORK_LAYER_ADDRESSES 0x00010118 +#define OID_GEN_TRANSPORT_HEADER_OFFSET 0x00010119 +#define OID_GEN_MACHINE_NAME 0x0001021A +#define OID_GEN_RNDIS_CONFIG_PARAMETER 0x0001021B +#define OID_GEN_VLAN_ID 0x0001021C + +/* Optional OIDs */ +#define OID_GEN_MEDIA_CAPABILITIES 0x00010201 +#define OID_GEN_PHYSICAL_MEDIUM 0x00010202 + +/* Required statistics OIDs */ +#define OID_GEN_XMIT_OK 0x00020101 +#define OID_GEN_RCV_OK 0x00020102 +#define OID_GEN_XMIT_ERROR 0x00020103 +#define OID_GEN_RCV_ERROR 0x00020104 +#define OID_GEN_RCV_NO_BUFFER 0x00020105 + +/* Optional statistics OIDs */ +#define OID_GEN_DIRECTED_BYTES_XMIT 0x00020201 +#define OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202 +#define OID_GEN_MULTICAST_BYTES_XMIT 0x00020203 +#define OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204 +#define OID_GEN_BROADCAST_BYTES_XMIT 0x00020205 +#define OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206 +#define OID_GEN_DIRECTED_BYTES_RCV 0x00020207 +#define OID_GEN_DIRECTED_FRAMES_RCV 0x00020208 +#define OID_GEN_MULTICAST_BYTES_RCV 0x00020209 +#define OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A +#define OID_GEN_BROADCAST_BYTES_RCV 0x0002020B +#define OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C +#define OID_GEN_RCV_CRC_ERROR 0x0002020D +#define OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E +#define OID_GEN_GET_TIME_CAPS 0x0002020F +#define OID_GEN_GET_NETCARD_TIME 0x00020210 +#define OID_GEN_NETCARD_LOAD 0x00020211 +#define OID_GEN_DEVICE_PROFILE 0x00020212 +#define OID_GEN_INIT_TIME_MS 0x00020213 +#define OID_GEN_RESET_COUNTS 0x00020214 +#define OID_GEN_MEDIA_SENSE_COUNTS 0x00020215 +#define OID_GEN_FRIENDLY_NAME 0x00020216 +#define OID_GEN_MINIPORT_INFO 0x00020217 +#define OID_GEN_RESET_VERIFY_PARAMETERS 0x00020218 + +/* IEEE 802.3 (Ethernet) OIDs */ +#define NDIS_802_3_MAC_OPTION_PRIORITY 0x00000001 + +#define OID_802_3_PERMANENT_ADDRESS 0x01010101 +#define OID_802_3_CURRENT_ADDRESS 0x01010102 +#define OID_802_3_MULTICAST_LIST 0x01010103 +#define OID_802_3_MAXIMUM_LIST_SIZE 0x01010104 +#define OID_802_3_MAC_OPTIONS 0x01010105 +#define OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101 +#define OID_802_3_XMIT_ONE_COLLISION 0x01020102 +#define OID_802_3_XMIT_MORE_COLLISIONS 0x01020103 +#define OID_802_3_XMIT_DEFERRED 0x01020201 +#define OID_802_3_XMIT_MAX_COLLISIONS 0x01020202 +#define OID_802_3_RCV_OVERRUN 0x01020203 +#define OID_802_3_XMIT_UNDERRUN 0x01020204 +#define OID_802_3_XMIT_HEARTBEAT_FAILURE 0x01020205 +#define OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206 +#define OID_802_3_XMIT_LATE_COLLISIONS 0x01020207 + +/* Wireless LAN OIDs */ +/* Mandatory */ +#define OID_802_11_BSSID 0x0D010101 /* Q S */ +#define OID_802_11_SSID 0x0D010102 /* Q S */ +#define OID_802_11_NETWORK_TYPE_IN_USE 0x0D010204 /* Q S */ +#define OID_802_11_RSSI 0x0D010206 /* Q I */ +#define OID_802_11_BSSID_LIST 0x0D010217 /* Q */ +#define OID_802_11_BSSID_LIST_SCAN 0x0D01011A /* S */ +#define OID_802_11_INFRASTRUCTURE_MODE 0x0D010108 /* Q S */ +#define OID_802_11_SUPPORTED_RATES 0x0D01020E /* Q */ +#define OID_802_11_CONFIGURATION 0x0D010211 /* Q S */ +#define OID_802_11_ADD_WEP 0x0D010113 /* S */ +#define OID_802_11_WEP_STATUS 0x0D01011B /* Q S */ +#define OID_802_11_REMOVE_WEP 0x0D010114 /* S */ +#define OID_802_11_DISASSOCIATE 0x0D010115 /* S */ +#define OID_802_11_AUTHENTICATION_MODE 0x0D010118 /* Q S */ +#define OID_802_11_RELOAD_DEFAULTS 0x0D01011C /* S */ + +/* OID_GEN_MINIPORT_INFO constants */ +#define NDIS_MINIPORT_BUS_MASTER 0x00000001 +#define NDIS_MINIPORT_WDM_DRIVER 0x00000002 +#define NDIS_MINIPORT_SG_LIST 0x00000004 +#define NDIS_MINIPORT_SUPPORTS_MEDIA_QUERY 0x00000008 +#define NDIS_MINIPORT_INDICATES_PACKETS 0x00000010 +#define NDIS_MINIPORT_IGNORE_PACKET_QUEUE 0x00000020 +#define NDIS_MINIPORT_IGNORE_REQUEST_QUEUE 0x00000040 +#define NDIS_MINIPORT_IGNORE_TOKEN_RING_ERRORS 0x00000080 +#define NDIS_MINIPORT_INTERMEDIATE_DRIVER 0x00000100 +#define NDIS_MINIPORT_IS_NDIS_5 0x00000200 +#define NDIS_MINIPORT_IS_CO 0x00000400 +#define NDIS_MINIPORT_DESERIALIZE 0x00000800 +#define NDIS_MINIPORT_REQUIRES_MEDIA_POLLING 0x00001000 +#define NDIS_MINIPORT_SUPPORTS_MEDIA_SENSE 0x00002000 +#define NDIS_MINIPORT_NETBOOT_CARD 0x00004000 +#define NDIS_MINIPORT_PM_SUPPORTED 0x00008000 +#define NDIS_MINIPORT_SUPPORTS_MAC_ADDRESS_OVERWRITE 0x00010000 +#define NDIS_MINIPORT_USES_SAFE_BUFFER_APIS 0x00020000 +#define NDIS_MINIPORT_HIDDEN 0x00040000 +#define NDIS_MINIPORT_SWENUM 0x00080000 +#define NDIS_MINIPORT_SURPRISE_REMOVE_OK 0x00100000 +#define NDIS_MINIPORT_NO_HALT_ON_SUSPEND 0x00200000 +#define NDIS_MINIPORT_HARDWARE_DEVICE 0x00400000 +#define NDIS_MINIPORT_SUPPORTS_CANCEL_SEND_PACKETS 0x00800000 +#define NDIS_MINIPORT_64BITS_DMA 0x01000000 + +#define NDIS_MEDIUM_802_3 0x00000000 +#define NDIS_MEDIUM_802_5 0x00000001 +#define NDIS_MEDIUM_FDDI 0x00000002 +#define NDIS_MEDIUM_WAN 0x00000003 +#define NDIS_MEDIUM_LOCAL_TALK 0x00000004 +#define NDIS_MEDIUM_DIX 0x00000005 +#define NDIS_MEDIUM_ARCENT_RAW 0x00000006 +#define NDIS_MEDIUM_ARCENT_878_2 0x00000007 +#define NDIS_MEDIUM_ATM 0x00000008 +#define NDIS_MEDIUM_WIRELESS_LAN 0x00000009 +#define NDIS_MEDIUM_IRDA 0x0000000A +#define NDIS_MEDIUM_BPC 0x0000000B +#define NDIS_MEDIUM_CO_WAN 0x0000000C +#define NDIS_MEDIUM_1394 0x0000000D + +#define NDIS_PACKET_TYPE_DIRECTED 0x00000001 +#define NDIS_PACKET_TYPE_MULTICAST 0x00000002 +#define NDIS_PACKET_TYPE_ALL_MULTICAST 0x00000004 +#define NDIS_PACKET_TYPE_BROADCAST 0x00000008 +#define NDIS_PACKET_TYPE_SOURCE_ROUTING 0x00000010 +#define NDIS_PACKET_TYPE_PROMISCUOUS 0x00000020 +#define NDIS_PACKET_TYPE_SMT 0x00000040 +#define NDIS_PACKET_TYPE_ALL_LOCAL 0x00000080 +#define NDIS_PACKET_TYPE_GROUP 0x00000100 +#define NDIS_PACKET_TYPE_ALL_FUNCTIONAL 0x00000200 +#define NDIS_PACKET_TYPE_FUNCTIONAL 0x00000400 +#define NDIS_PACKET_TYPE_MAC_FRAME 0x00000800 + +#define NDIS_MEDIA_STATE_CONNECTED 0x00000000 +#define NDIS_MEDIA_STATE_DISCONNECTED 0x00000001 + +#define NDIS_MAC_OPTION_COPY_LOOKAHEAD_DATA 0x00000001 +#define NDIS_MAC_OPTION_RECEIVE_SERIALIZED 0x00000002 +#define NDIS_MAC_OPTION_TRANSFERS_NOT_PEND 0x00000004 +#define NDIS_MAC_OPTION_NO_LOOPBACK 0x00000008 +#define NDIS_MAC_OPTION_FULL_DUPLEX 0x00000010 +#define NDIS_MAC_OPTION_EOTX_INDICATION 0x00000020 +#define NDIS_MAC_OPTION_8021P_PRIORITY 0x00000040 +#define NDIS_MAC_OPTION_RESERVED 0x80000000 + +/** Hardware status of the underlying NIC */ +#define NDIS_HW_STS_READY 0x00000000UL +#define NDIS_HW_STS_INITIALIZING 0x00000001UL +#define NDIS_HW_STS_RESET 0x00000002UL +#define NDIS_HW_STS_CLOSING 0x00000003UL +#define NDIS_HW_STS_NOT_READY 0x00000004UL + +#endif /* _LINUX_NDIS_H */ + +/** @} */ diff --git a/components/drivers/usb/cherryusb/class/wireless/rndis_protocol.h b/components/drivers/usb/cherryusb/class/wireless/rndis_protocol.h new file mode 100644 index 00000000000..54b4ebf6262 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/wireless/rndis_protocol.h @@ -0,0 +1,302 @@ +/** + * \file rndis_protocol.h + * RNDIS Defines + * + * \author + * Colin O'Flynn + * + * \addtogroup usbstick + */ + +/* Copyright (c) 2008 Colin O'Flynn + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in + the documentation and/or other materials provided with the + distribution. + * Neither the name of the copyright holders nor the names of + contributors may be used to endorse or promote products derived + from this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. +*/ + +#ifndef _RNDIS_H +#define _RNDIS_H + +/** + \addtogroup RNDIS + @{ + */ + +#include + +#define RNDIS_MAJOR_VERSION 1 +#define RNDIS_MINOR_VERSION 0 + +#define RNDIS_STATUS_SUCCESS 0X00000000 +#define RNDIS_STATUS_FAILURE 0XC0000001 +#define RNDIS_STATUS_INVALID_DATA 0XC0010015 +#define RNDIS_STATUS_NOT_SUPPORTED 0XC00000BB +#define RNDIS_STATUS_MEDIA_CONNECT 0X4001000B +#define RNDIS_STATUS_MEDIA_DISCONNECT 0X4001000C + +/* Message set for Connectionless (802.3) Devices */ +#define REMOTE_NDIS_PACKET_MSG 0x00000001 +#define REMOTE_NDIS_INITIALIZE_MSG 0X00000002 +#define REMOTE_NDIS_HALT_MSG 0X00000003 +#define REMOTE_NDIS_QUERY_MSG 0X00000004 +#define REMOTE_NDIS_SET_MSG 0X00000005 +#define REMOTE_NDIS_RESET_MSG 0X00000006 +#define REMOTE_NDIS_INDICATE_STATUS_MSG 0X00000007 +#define REMOTE_NDIS_KEEPALIVE_MSG 0X00000008 +#define REMOTE_NDIS_INITIALIZE_CMPLT 0X80000002 +#define REMOTE_NDIS_QUERY_CMPLT 0X80000004 +#define REMOTE_NDIS_SET_CMPLT 0X80000005 +#define REMOTE_NDIS_RESET_CMPLT 0X80000006 +#define REMOTE_NDIS_KEEPALIVE_CMPLT 0X80000008 + +typedef uint32_t rndis_MessageType_t; +typedef uint32_t rndis_MessageLength_t; +typedef uint32_t rndis_RequestId_t; +typedef uint32_t rndis_MajorVersion_t; +typedef uint32_t rndis_MinorVersion_t; +typedef uint32_t rndis_MaxTransferSize_t; +typedef uint32_t rndis_Status_t; + +/* Device Flags */ +#define RNDIS_DF_CONNECTIONLESS 0x00000001 +#define RNDIS_DF_CONNECTION_ORIENTED 0x00000002 +typedef uint32_t rndis_DeviceFlags_t; + +/* Mediums */ +#define RNDIS_MEDIUM_802_3 0x00000000 +typedef uint32_t rndis_Medium_t; + +typedef uint32_t rndis_MaxPacketsPerTransfer_t; +typedef uint32_t rndis_PacketAlignmentFactor_t; +typedef uint32_t rndis_AfListOffset_t; +typedef uint32_t rndis_AfListSize_t; + +/*** Remote NDIS Generic Message type ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; +} rndis_generic_msg_t; + +/*** Remote NDIS Initialize Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_MajorVersion_t MajorVersion; + rndis_MinorVersion_t MinorVersion; + rndis_MaxTransferSize_t MaxTransferSize; +} rndis_initialize_msg_t; + +/* Response: */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; + rndis_MajorVersion_t MajorVersion; + rndis_MinorVersion_t MinorVersion; + rndis_DeviceFlags_t DeviceFlags; + rndis_Medium_t Medium; + rndis_MaxPacketsPerTransfer_t MaxPacketsPerTransfer; + rndis_MaxTransferSize_t MaxTransferSize; + rndis_PacketAlignmentFactor_t PacketAlignmentFactor; + rndis_AfListOffset_t AfListOffset; + rndis_AfListSize_t AfListSize; +} rndis_initialize_cmplt_t; + +/*** Remote NDIS Halt Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; +} rndis_halt_msg_t; + +typedef uint32_t rndis_Oid_t; +typedef uint32_t rndis_InformationBufferLength_t; +typedef uint32_t rndis_InformationBufferOffset_t; +typedef uint32_t rndis_DeviceVcHandle_t; + +/*** Remote NDIS Query Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Oid_t Oid; + rndis_InformationBufferLength_t InformationBufferLength; + rndis_InformationBufferOffset_t InformationBufferOffset; + rndis_DeviceVcHandle_t DeviceVcHandle; +} rndis_query_msg_t; + +/* Response: */ + +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; + rndis_InformationBufferLength_t InformationBufferLength; + rndis_InformationBufferOffset_t InformationBufferOffset; +} rndis_query_cmplt_t; + +/*** Remote NDIS Set Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Oid_t Oid; + rndis_InformationBufferLength_t InformationBufferLength; + rndis_InformationBufferOffset_t InformationBufferOffset; + rndis_DeviceVcHandle_t DeviceVcHandle; +} rndis_set_msg_t; + +/* Response */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; +} rndis_set_cmplt_t; + +/* Information buffer layout for OID_GEN_RNDIS_CONFIG_PARAMETER */ +typedef uint32_t rndis_ParameterNameOffset_t; +typedef uint32_t rndis_ParameterNameLength_t; +typedef uint32_t rndis_ParameterType_t; +typedef uint32_t rndis_ParameterValueOffset_t; +typedef uint32_t rndis_ParameterValueLength_t; + +#define PARAMETER_TYPE_STRING 2 +#define PARAMETER_TYPE_NUMERICAL 0 + +typedef struct { + rndis_ParameterNameOffset_t ParameterNameOffset; + rndis_ParameterNameLength_t ParameterNameLength; + rndis_ParameterType_t ParameterType; + rndis_ParameterValueOffset_t ParameterValueOffset; + rndis_ParameterValueLength_t ParameterValueLength; +} rndis_config_parameter_t; + +typedef uint32_t rndis_Reserved_t; + +/*** Remote NDIS Soft Reset Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_Reserved_t Reserved; +} rndis_reset_msg_t; + +typedef uint32_t rndis_AddressingReset_t; + +/* Response: */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_Status_t Status; + rndis_AddressingReset_t AddressingReset; +} rndis_reset_cmplt_t; + +/*** Remote NDIS Indicate Status Message ***/ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_Status_t Status; + rndis_Status_t StatusBufferLength; + rndis_Status_t StatusBufferOffset; +} rndis_indicate_status_t; + +typedef uint32_t rndis_DiagStatus_t; +typedef uint32_t rndis_ErrorOffset_t; + +typedef struct { + rndis_DiagStatus_t DiagStatus; + rndis_ErrorOffset_t ErrorOffset; +} rndis_diagnostic_info_t; + +/*** Remote NDIS Keepalive Message */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; +} rndis_keepalive_msg_t; + +/* Response: */ +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_RequestId_t RequestId; + rndis_Status_t Status; +} rndis_keepalive_cmplt_t; + +/*** Remote NDIS Data Packet ***/ + +typedef uint32_t rndis_DataOffset_t; +typedef uint32_t rndis_DataLength_t; +typedef uint32_t rndis_OOBDataOffset_t; +typedef uint32_t rndis_OOBDataLength_t; +typedef uint32_t rndis_NumOOBDataElements_t; +typedef uint32_t rndis_PerPacketInfoOffset_t; +typedef uint32_t rndis_PerPacketInfoLength_t; + +typedef struct { + rndis_MessageType_t MessageType; + rndis_MessageLength_t MessageLength; + rndis_DataOffset_t DataOffset; + rndis_DataLength_t DataLength; + rndis_OOBDataOffset_t OOBDataOffset; + rndis_OOBDataLength_t OOBDataLength; + rndis_NumOOBDataElements_t NumOOBDataElements; + rndis_PerPacketInfoOffset_t PerPacketInfoOffset; + rndis_PerPacketInfoLength_t PerPacketInfoLength; + rndis_DeviceVcHandle_t DeviceVcHandle; + rndis_Reserved_t Reserved; +} rndis_data_packet_t; + +typedef uint32_t rndis_ClassInformationOffset_t; +typedef uint32_t rndis_Size_t; +typedef uint32_t rndis_Type_t; + +typedef struct { + rndis_Size_t Size; + rndis_Type_t Type; + rndis_ClassInformationOffset_t ClassInformationType; +} rndis_OOB_packet_t; + +#include "ndis.h" + +typedef enum rnids_state_e { + rndis_uninitialized, + rndis_initialized, + rndis_data_initialized +} rndis_state_t; + +typedef struct { + uint32_t txok; + uint32_t rxok; + uint32_t txbad; + uint32_t rxbad; +} usb_eth_stat_t; + +#endif /* _RNDIS_H */ + +/** @} */ diff --git a/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.c b/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.c new file mode 100644 index 00000000000..aaea5431a41 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.c @@ -0,0 +1,566 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_rndis.h" +#include "rndis_protocol.h" + +#define RNDIS_OUT_EP_IDX 0 +#define RNDIS_IN_EP_IDX 1 +#define RNDIS_INT_EP_IDX 2 + +/* Describe EndPoints configuration */ +static struct usbd_endpoint rndis_ep_data[3]; + +#define RNDIS_INQUIRY_PUT(src, len) (memcpy(infomation_buffer, src, len)) +#define RNDIS_INQUIRY_PUT_LE32(value) (*(uint32_t *)infomation_buffer = (value)) + +/* Device data structure */ +struct usbd_rndis_priv { + uint32_t drv_version; + uint32_t link_status; + uint32_t net_filter; + usb_eth_stat_t eth_state; + rndis_state_t init_state; + uint8_t mac[6]; +} g_usbd_rndis; + +#if CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE < 140 +#undef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +#if CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE < 1580 +#undef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_rx_buffer[CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_tx_buffer[CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE]; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t rndis_encapsulated_resp_buffer[CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t NOTIFY_RESPONSE_AVAILABLE[8]; + +volatile uint8_t *g_rndis_rx_data_buffer; +volatile uint32_t g_rndis_rx_data_length; +volatile uint32_t g_rndis_tx_data_length; + +/* RNDIS options list */ +const uint32_t oid_supported_list[] = { + /* General OIDs */ + OID_GEN_SUPPORTED_LIST, + OID_GEN_HARDWARE_STATUS, + OID_GEN_MEDIA_SUPPORTED, + OID_GEN_MEDIA_IN_USE, + OID_GEN_MAXIMUM_FRAME_SIZE, + OID_GEN_LINK_SPEED, + OID_GEN_TRANSMIT_BLOCK_SIZE, + OID_GEN_RECEIVE_BLOCK_SIZE, + OID_GEN_VENDOR_ID, + OID_GEN_VENDOR_DESCRIPTION, + OID_GEN_VENDOR_DRIVER_VERSION, + OID_GEN_CURRENT_PACKET_FILTER, + OID_GEN_MAXIMUM_TOTAL_SIZE, + OID_GEN_MEDIA_CONNECT_STATUS, + + OID_GEN_PHYSICAL_MEDIUM, + + /* General Statistic OIDs */ + OID_GEN_XMIT_OK, + OID_GEN_RCV_OK, + OID_GEN_XMIT_ERROR, + OID_GEN_RCV_ERROR, + OID_GEN_RCV_NO_BUFFER, + + /* Please configure us */ + OID_GEN_RNDIS_CONFIG_PARAMETER, + + /* 802.3 OIDs */ + OID_802_3_PERMANENT_ADDRESS, + OID_802_3_CURRENT_ADDRESS, + OID_802_3_MULTICAST_LIST, + OID_802_3_MAXIMUM_LIST_SIZE, + + /* 802.3 Statistic OIDs */ + OID_802_3_RCV_ERROR_ALIGNMENT, + OID_802_3_XMIT_ONE_COLLISION, + OID_802_3_XMIT_MORE_COLLISIONS, + + OID_802_3_MAC_OPTIONS, +}; + +static int rndis_encapsulated_cmd_handler(uint8_t *data, uint32_t len); + +static void rndis_notify_rsp(void) +{ + memset(NOTIFY_RESPONSE_AVAILABLE, 0, 8); + NOTIFY_RESPONSE_AVAILABLE[0] = 0x01; + usbd_ep_start_write(0, rndis_ep_data[RNDIS_INT_EP_IDX].ep_addr, NOTIFY_RESPONSE_AVAILABLE, 8); +} + +static int rndis_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + switch (setup->bRequest) { + case CDC_REQUEST_SEND_ENCAPSULATED_COMMAND: + rndis_encapsulated_cmd_handler(*data, setup->wLength); + break; + case CDC_REQUEST_GET_ENCAPSULATED_RESPONSE: + *data = rndis_encapsulated_resp_buffer; + *len = ((rndis_generic_msg_t *)rndis_encapsulated_resp_buffer)->MessageLength; + break; + + default: + return -1; + } + + return 0; +} + +static int rndis_init_cmd_handler(uint8_t *data, uint32_t len); +static int rndis_halt_cmd_handler(uint8_t *data, uint32_t len); +static int rndis_query_cmd_handler(uint8_t *data, uint32_t len); +static int rndis_set_cmd_handler(uint8_t *data, uint32_t len); +static int rndis_reset_cmd_handler(uint8_t *data, uint32_t len); +static int rndis_keepalive_cmd_handler(uint8_t *data, uint32_t len); + +static int rndis_encapsulated_cmd_handler(uint8_t *data, uint32_t len) +{ + switch (((rndis_generic_msg_t *)data)->MessageType) { + case REMOTE_NDIS_INITIALIZE_MSG: + return rndis_init_cmd_handler(data, len); + case REMOTE_NDIS_HALT_MSG: + return rndis_halt_cmd_handler(data, len); + case REMOTE_NDIS_QUERY_MSG: + return rndis_query_cmd_handler(data, len); + case REMOTE_NDIS_SET_MSG: + return rndis_set_cmd_handler(data, len); + case REMOTE_NDIS_RESET_MSG: + return rndis_reset_cmd_handler(data, len); + case REMOTE_NDIS_KEEPALIVE_MSG: + return rndis_keepalive_cmd_handler(data, len); + + default: + break; + } + return -1; +} + +static int rndis_init_cmd_handler(uint8_t *data, uint32_t len) +{ + rndis_initialize_msg_t *cmd = (rndis_initialize_msg_t *)data; + rndis_initialize_cmplt_t *resp; + + resp = ((rndis_initialize_cmplt_t *)rndis_encapsulated_resp_buffer); + resp->RequestId = cmd->RequestId; + resp->MessageType = REMOTE_NDIS_INITIALIZE_CMPLT; + resp->MessageLength = sizeof(rndis_initialize_cmplt_t); + resp->MajorVersion = RNDIS_MAJOR_VERSION; + resp->MinorVersion = RNDIS_MINOR_VERSION; + resp->Status = RNDIS_STATUS_SUCCESS; + resp->DeviceFlags = RNDIS_DF_CONNECTIONLESS; + resp->Medium = RNDIS_MEDIUM_802_3; + resp->MaxPacketsPerTransfer = CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE / 1580; + resp->MaxTransferSize = CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE; + resp->PacketAlignmentFactor = 0; + resp->AfListOffset = 0; + resp->AfListSize = 0; + + g_usbd_rndis.init_state = rndis_initialized; + + rndis_notify_rsp(); + return 0; +} + +static int rndis_halt_cmd_handler(uint8_t *data, uint32_t len) +{ + rndis_halt_msg_t *resp; + + resp = ((rndis_halt_msg_t *)rndis_encapsulated_resp_buffer); + resp->MessageLength = 0; + + g_usbd_rndis.init_state = rndis_uninitialized; + + return 0; +} + +static int rndis_query_cmd_handler(uint8_t *data, uint32_t len) +{ + rndis_query_msg_t *cmd = (rndis_query_msg_t *)data; + rndis_query_cmplt_t *resp; + uint8_t *infomation_buffer; + uint32_t infomation_len = 0; + + resp = ((rndis_query_cmplt_t *)rndis_encapsulated_resp_buffer); + resp->MessageType = REMOTE_NDIS_QUERY_CMPLT; + resp->RequestId = cmd->RequestId; + resp->InformationBufferOffset = sizeof(rndis_query_cmplt_t) - sizeof(rndis_generic_msg_t); + resp->Status = RNDIS_STATUS_SUCCESS; + + infomation_buffer = (uint8_t *)resp + sizeof(rndis_query_cmplt_t); + + switch (cmd->Oid) { + case OID_GEN_SUPPORTED_LIST: + RNDIS_INQUIRY_PUT(oid_supported_list, sizeof(oid_supported_list)); + infomation_len = sizeof(oid_supported_list); + break; + case OID_GEN_HARDWARE_STATUS: + RNDIS_INQUIRY_PUT_LE32(NDIS_HW_STS_READY); + infomation_len = 4; + break; + case OID_GEN_MEDIA_SUPPORTED: + case OID_GEN_MEDIA_IN_USE: + RNDIS_INQUIRY_PUT_LE32(NDIS_MEDIUM_802_3); + infomation_len = 4; + break; + case OID_GEN_MAXIMUM_FRAME_SIZE: + case OID_GEN_TRANSMIT_BLOCK_SIZE: + case OID_GEN_RECEIVE_BLOCK_SIZE: + RNDIS_INQUIRY_PUT_LE32(0x05DC); + infomation_len = 4; + break; + case OID_GEN_VENDOR_ID: + RNDIS_INQUIRY_PUT_LE32(CONFIG_USBDEV_RNDIS_VENDOR_ID); + infomation_len = 4; + break; + case OID_GEN_VENDOR_DRIVER_VERSION: + RNDIS_INQUIRY_PUT_LE32(0x0001); + infomation_len = 4; + break; + case OID_GEN_VENDOR_DESCRIPTION: + RNDIS_INQUIRY_PUT(CONFIG_USBDEV_RNDIS_VENDOR_DESC, strlen(CONFIG_USBDEV_RNDIS_VENDOR_DESC)); + infomation_len = (strlen(CONFIG_USBDEV_RNDIS_VENDOR_DESC) + 1); + break; + case OID_802_3_CURRENT_ADDRESS: + case OID_802_3_PERMANENT_ADDRESS: + RNDIS_INQUIRY_PUT(g_usbd_rndis.mac, 6); + infomation_len = 6; + break; + case OID_GEN_PHYSICAL_MEDIUM: + RNDIS_INQUIRY_PUT_LE32(NDIS_MEDIUM_802_3); + infomation_len = 4; + break; + case OID_GEN_LINK_SPEED: + if (usbd_get_ep_mps(0, rndis_ep_data[RNDIS_OUT_EP_IDX].ep_addr) > 64) { + RNDIS_INQUIRY_PUT_LE32(480000000 / 100); + } else { + RNDIS_INQUIRY_PUT_LE32(12000000 / 100); + } + + infomation_len = 4; + break; + case OID_GEN_CURRENT_PACKET_FILTER: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.net_filter); + infomation_len = 4; + break; + case OID_GEN_MAXIMUM_TOTAL_SIZE: + RNDIS_INQUIRY_PUT_LE32(CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE + CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE); + infomation_len = 4; + break; + case OID_GEN_MEDIA_CONNECT_STATUS: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.link_status); + infomation_len = 4; + break; + case OID_GEN_RNDIS_CONFIG_PARAMETER: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_802_3_MAXIMUM_LIST_SIZE: + RNDIS_INQUIRY_PUT_LE32(1); /* one address */ + infomation_len = 4; + break; + case OID_802_3_MULTICAST_LIST: + //RNDIS_INQUIRY_PUT_LE32(0xE0000000); /* 224.0.0.0 */ + resp->Status = RNDIS_STATUS_NOT_SUPPORTED; + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_802_3_MAC_OPTIONS: + // infomation_len = 0; + resp->Status = RNDIS_STATUS_NOT_SUPPORTED; + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_GEN_MAC_OPTIONS: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_802_3_RCV_ERROR_ALIGNMENT: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_802_3_XMIT_ONE_COLLISION: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_802_3_XMIT_MORE_COLLISIONS: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + case OID_GEN_XMIT_OK: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.eth_state.txok); + infomation_len = 4; + break; + case OID_GEN_RCV_OK: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.eth_state.rxok); + infomation_len = 4; + break; + case OID_GEN_RCV_ERROR: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.eth_state.rxbad); + infomation_len = 4; + break; + case OID_GEN_XMIT_ERROR: + RNDIS_INQUIRY_PUT_LE32(g_usbd_rndis.eth_state.txbad); + infomation_len = 4; + break; + case OID_GEN_RCV_NO_BUFFER: + RNDIS_INQUIRY_PUT_LE32(0); + infomation_len = 4; + break; + default: + resp->Status = RNDIS_STATUS_FAILURE; + infomation_len = 0; + USB_LOG_WRN("Unhandled query for Object ID 0x%x\r\n", cmd->Oid); + break; + } + + resp->MessageLength = sizeof(rndis_query_cmplt_t) + infomation_len; + resp->InformationBufferLength = infomation_len; + + rndis_notify_rsp(); + return 0; +} + +static int rndis_set_cmd_handler(uint8_t *data, uint32_t len) +{ + rndis_set_msg_t *cmd = (rndis_set_msg_t *)data; + rndis_set_cmplt_t *resp; + rndis_config_parameter_t *param; + + resp = ((rndis_set_cmplt_t *)rndis_encapsulated_resp_buffer); + resp->RequestId = cmd->RequestId; + resp->MessageType = REMOTE_NDIS_SET_CMPLT; + resp->MessageLength = sizeof(rndis_set_cmplt_t); + resp->Status = RNDIS_STATUS_SUCCESS; + + switch (cmd->Oid) { + case OID_GEN_RNDIS_CONFIG_PARAMETER: + param = (rndis_config_parameter_t *)((uint8_t *)&(cmd->RequestId) + cmd->InformationBufferOffset); + USB_LOG_WRN("RNDIS cfg param: NameOfs=%d, NameLen=%d, ValueOfs=%d, ValueLen=%d\r\n", + param->ParameterNameOffset, param->ParameterNameLength, + param->ParameterValueOffset, param->ParameterValueLength); + break; + case OID_GEN_CURRENT_PACKET_FILTER: + if (cmd->InformationBufferLength < sizeof(g_usbd_rndis.net_filter)) { + USB_LOG_WRN("PACKET_FILTER!\r\n"); + resp->Status = RNDIS_STATUS_INVALID_DATA; + } else { + uint32_t *filter; + /* Parameter starts at offset buf_offset of the req_id field */ + filter = (uint32_t *)((uint8_t *)&(cmd->RequestId) + cmd->InformationBufferOffset); + + //g_usbd_rndis.net_filter = param->ParameterNameOffset; + g_usbd_rndis.net_filter = *(uint32_t *)filter; + if (g_usbd_rndis.net_filter) { + g_usbd_rndis.init_state = rndis_data_initialized; + } else { + g_usbd_rndis.init_state = rndis_initialized; + } + } + break; + case OID_GEN_CURRENT_LOOKAHEAD: + break; + case OID_GEN_PROTOCOL_OPTIONS: + break; + case OID_802_3_MULTICAST_LIST: + break; + case OID_PNP_ADD_WAKE_UP_PATTERN: + case OID_PNP_REMOVE_WAKE_UP_PATTERN: + case OID_PNP_ENABLE_WAKE_UP: + default: + resp->Status = RNDIS_STATUS_FAILURE; + USB_LOG_WRN("Unhandled query for Object ID 0x%x\r\n", cmd->Oid); + break; + } + + rndis_notify_rsp(); + + return 0; +} + +static int rndis_reset_cmd_handler(uint8_t *data, uint32_t len) +{ + // rndis_reset_msg_t *cmd = (rndis_reset_msg_t *)data; + rndis_reset_cmplt_t *resp; + + resp = ((rndis_reset_cmplt_t *)rndis_encapsulated_resp_buffer); + resp->MessageType = REMOTE_NDIS_RESET_CMPLT; + resp->MessageLength = sizeof(rndis_reset_cmplt_t); + resp->Status = RNDIS_STATUS_SUCCESS; + resp->AddressingReset = 1; + + g_usbd_rndis.init_state = rndis_uninitialized; + + rndis_notify_rsp(); + + return 0; +} + +static int rndis_keepalive_cmd_handler(uint8_t *data, uint32_t len) +{ + rndis_keepalive_msg_t *cmd = (rndis_keepalive_msg_t *)data; + rndis_keepalive_cmplt_t *resp; + + resp = ((rndis_keepalive_cmplt_t *)rndis_encapsulated_resp_buffer); + resp->RequestId = cmd->RequestId; + resp->MessageType = REMOTE_NDIS_KEEPALIVE_CMPLT; + resp->MessageLength = sizeof(rndis_keepalive_cmplt_t); + resp->Status = RNDIS_STATUS_SUCCESS; + + rndis_notify_rsp(); + + return 0; +} + +static void rndis_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + switch (event) { + case USBD_EVENT_RESET: + g_usbd_rndis.link_status = NDIS_MEDIA_STATE_DISCONNECTED; + break; + case USBD_EVENT_CONFIGURED: + g_rndis_rx_data_length = 0; + g_rndis_tx_data_length = 0; + g_usbd_rndis.link_status = NDIS_MEDIA_STATE_CONNECTED; + usbd_ep_start_read(0, rndis_ep_data[RNDIS_OUT_EP_IDX].ep_addr, g_rndis_rx_buffer, sizeof(g_rndis_rx_buffer)); + break; + + default: + break; + } +} + +void rndis_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + rndis_data_packet_t *hdr; + + hdr = (rndis_data_packet_t *)g_rndis_rx_buffer; + g_rndis_rx_data_buffer = g_rndis_rx_buffer; + if ((hdr->MessageType != REMOTE_NDIS_PACKET_MSG) || (nbytes < hdr->MessageLength)) { + usbd_ep_start_read(0, rndis_ep_data[RNDIS_OUT_EP_IDX].ep_addr, g_rndis_rx_buffer, sizeof(g_rndis_rx_buffer)); + return; + } + + /* Point to the payload and update the message length */ + g_rndis_rx_data_buffer += hdr->DataOffset + sizeof(rndis_generic_msg_t); + g_rndis_rx_data_length = hdr->DataLength; + + usbd_rndis_data_recv_done(); +} + +void rndis_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(0, ep, NULL, 0); + } else { + g_rndis_tx_data_length = 0; + } +} + +void rndis_int_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + //USB_LOG_DBG("len:%d\r\n", nbytes); +} + +#ifdef CONFIG_USBDEV_RNDIS_USING_LWIP +#include + +struct pbuf *usbd_rndis_eth_rx(void) +{ + struct pbuf *p; + + if (g_rndis_rx_data_length == 0) { + return NULL; + } + p = pbuf_alloc(PBUF_RAW, g_rndis_rx_data_length, PBUF_POOL); + if (p == NULL) { + return NULL; + } + memcpy(p->payload, (uint8_t *)g_rndis_rx_data_buffer, g_rndis_rx_data_length); + p->len = g_rndis_rx_data_length; + + USB_LOG_DBG("rxlen:%d\r\n", g_rndis_rx_data_length); + g_rndis_rx_data_length = 0; + usbd_ep_start_read(0, rndis_ep_data[RNDIS_OUT_EP_IDX].ep_addr, g_rndis_rx_buffer, sizeof(g_rndis_rx_buffer)); + + return p; +} + +int usbd_rndis_eth_tx(struct pbuf *p) +{ + struct pbuf *q; + uint8_t *buffer; + rndis_data_packet_t *hdr; + + if (g_usbd_rndis.link_status == NDIS_MEDIA_STATE_DISCONNECTED) { + return -USB_ERR_NOTCONN; + } + + if (g_rndis_tx_data_length > 0) { + return -USB_ERR_BUSY; + } + + if (p->tot_len > sizeof(g_rndis_tx_buffer)) { + p->tot_len = sizeof(g_rndis_tx_buffer); + } + + buffer = (uint8_t *)(g_rndis_tx_buffer + sizeof(rndis_data_packet_t)); + for (q = p; q != NULL; q = q->next) { + memcpy(buffer, q->payload, q->len); + buffer += q->len; + } + + hdr = (rndis_data_packet_t *)g_rndis_tx_buffer; + + memset(hdr, 0, sizeof(rndis_data_packet_t)); + hdr->MessageType = REMOTE_NDIS_PACKET_MSG; + hdr->MessageLength = sizeof(rndis_data_packet_t) + p->tot_len; + hdr->DataOffset = sizeof(rndis_data_packet_t) - sizeof(rndis_generic_msg_t); + hdr->DataLength = p->tot_len; + + g_rndis_tx_data_length = sizeof(rndis_data_packet_t) + p->tot_len; + + USB_LOG_DBG("txlen:%d\r\n", g_rndis_tx_data_length); + return usbd_ep_start_write(0, rndis_ep_data[RNDIS_IN_EP_IDX].ep_addr, g_rndis_tx_buffer, g_rndis_tx_data_length); +} +#endif +struct usbd_interface *usbd_rndis_init_intf(struct usbd_interface *intf, + const uint8_t out_ep, + const uint8_t in_ep, + const uint8_t int_ep, uint8_t mac[6]) +{ + memcpy(g_usbd_rndis.mac, mac, 6); + + g_usbd_rndis.drv_version = 0x0001; + g_usbd_rndis.link_status = NDIS_MEDIA_STATE_DISCONNECTED; + + rndis_ep_data[RNDIS_OUT_EP_IDX].ep_addr = out_ep; + rndis_ep_data[RNDIS_OUT_EP_IDX].ep_cb = rndis_bulk_out; + rndis_ep_data[RNDIS_IN_EP_IDX].ep_addr = in_ep; + rndis_ep_data[RNDIS_IN_EP_IDX].ep_cb = rndis_bulk_in; + rndis_ep_data[RNDIS_INT_EP_IDX].ep_addr = int_ep; + rndis_ep_data[RNDIS_INT_EP_IDX].ep_cb = rndis_int_in; + + usbd_add_endpoint(0, &rndis_ep_data[RNDIS_OUT_EP_IDX]); + usbd_add_endpoint(0, &rndis_ep_data[RNDIS_IN_EP_IDX]); + usbd_add_endpoint(0, &rndis_ep_data[RNDIS_INT_EP_IDX]); + + intf->class_interface_handler = rndis_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = rndis_notify_handler; + + return intf; +} diff --git a/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.h b/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.h new file mode 100644 index 00000000000..8a9581f68d1 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/wireless/usbd_rndis.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_RNDIS_H +#define USBD_RNDIS_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init rndis interface driver */ +struct usbd_interface *usbd_rndis_init_intf(struct usbd_interface *intf, + const uint8_t out_ep, + const uint8_t in_ep, + const uint8_t int_ep, uint8_t mac[6]); + +void usbd_rndis_data_recv_done(void); + +#ifdef CONFIG_USBDEV_RNDIS_USING_LWIP +struct pbuf *usbd_rndis_eth_rx(void); +int usbd_rndis_eth_tx(struct pbuf *p); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_RNDIS_H */ diff --git a/components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.c b/components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.c new file mode 100644 index 00000000000..4c223dbfd67 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.c @@ -0,0 +1,402 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_bluetooth.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_bluetooth" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/bluetooth" + +static struct usbh_bluetooth g_bluetooth_class; + +#ifdef CONFIG_USBHOST_BLUETOOTH_HCI_H4 +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_tx_buf[1 + CONFIG_USBHOST_BLUETOOTH_TX_SIZE]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_rx_buf[1 + CONFIG_USBHOST_BLUETOOTH_RX_SIZE]; +#else +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_cmd_buf[1 + 256]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_evt_buf[1 + 256]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_tx_buf[1 + CONFIG_USBHOST_BLUETOOTH_TX_SIZE]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_bluetooth_rx_buf[1 + CONFIG_USBHOST_BLUETOOTH_RX_SIZE]; +#endif + +static int usbh_bluetooth_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret = 0; +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + uint8_t mult; + uint16_t mps; +#endif + + struct usbh_bluetooth *bluetooth_class = &g_bluetooth_class; + +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + if (intf != 0) { + return 0; + } +#endif + + memset(bluetooth_class, 0, sizeof(struct usbh_bluetooth)); + + bluetooth_class->hport = hport; + bluetooth_class->intf = intf; +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + bluetooth_class->num_of_intf_altsettings = hport->config.intf[intf + 1].altsetting_num; +#endif + hport->config.intf[intf].priv = bluetooth_class; + + for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc; +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(bluetooth_class->intin, ep_desc); + } else { + return -USB_ERR_NOTSUPP; + } + } else { +#endif + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(bluetooth_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(bluetooth_class->bulkout, ep_desc); + } +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + } +#endif + } +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + USB_LOG_INFO("Num of altsettings:%u\r\n", bluetooth_class->num_of_intf_altsettings); + + for (uint8_t i = 0; i < bluetooth_class->num_of_intf_altsettings; i++) { + USB_LOG_INFO("Altsetting:%u\r\n", i); + for (uint8_t j = 0; j < hport->config.intf[intf + 1].altsetting[i].intf_desc.bNumEndpoints; j++) { + ep_desc = &bluetooth_class->hport->config.intf[intf + 1].altsetting[i].ep[j].ep_desc; + + mult = USB_GET_MULT(ep_desc->wMaxPacketSize); + mps = USB_GET_MAXPACKETSIZE(ep_desc->wMaxPacketSize); + + USB_LOG_INFO("\tEp=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", + ep_desc->bEndpointAddress, + ep_desc->bmAttributes, + mps, + ep_desc->bInterval, + mult); + } + } + + ret = usbh_set_interface(hport, intf, 0); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("Bluetooth select altsetting 0\r\n"); +#endif + snprintf(hport->config.intf[intf].devname, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT); + USB_LOG_INFO("Register Bluetooth Class:%s\r\n", hport->config.intf[intf].devname); + usbh_bluetooth_run(bluetooth_class); + return ret; +} + +static int usbh_bluetooth_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_bluetooth *bluetooth_class = (struct usbh_bluetooth *)hport->config.intf[intf].priv; + + if (hport->config.config_desc.bNumInterfaces == (intf + 1)) { + return 0; + } + + if (bluetooth_class) { + if (bluetooth_class->bulkin) { + usbh_kill_urb(&bluetooth_class->bulkin_urb); + } + + if (bluetooth_class->bulkout) { + usbh_kill_urb(&bluetooth_class->bulkout_urb); + } +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + if (bluetooth_class->intin) { + usbh_kill_urb(&bluetooth_class->intin_urb); + } + + // if (bluetooth_class->isoin) { + // usbh_kill_urb(&bluetooth_class->isoin_urb); + // } + + // if (bluetooth_class->isoin) { + // usbh_kill_urb(&bluetooth_class->isoinin_urb); + // } +#endif + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister Bluetooth Class:%s\r\n", hport->config.intf[intf].devname); + usbh_bluetooth_stop(bluetooth_class); + } + + memset(bluetooth_class, 0, sizeof(struct usbh_bluetooth)); + } + + return ret; +} + +#ifdef CONFIG_USBHOST_BLUETOOTH_HCI_LOG +static void usbh_bluetooth_hci_dump(uint8_t *data, uint32_t len) +{ + uint32_t i = 0; + + for (i = 0; i < len; i++) { + if (i % 16 == 0) { + USB_LOG_RAW("\r\n"); + } + + USB_LOG_RAW("%02x ", data[i]); + } + + USB_LOG_RAW("\r\n"); +} +#else +#define usbh_bluetooth_hci_dump(data, len) +#endif + +static int usbh_bluetooth_hci_bulk_out(uint8_t *buffer, uint32_t buflen) +{ + struct usbh_bluetooth *bluetooth_class = &g_bluetooth_class; + struct usbh_urb *urb = &bluetooth_class->bulkout_urb; + int ret; + + usbh_bulk_urb_fill(urb, bluetooth_class->hport, bluetooth_class->bulkout, buffer, buflen, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + return ret; +} + +#ifdef CONFIG_USBHOST_BLUETOOTH_HCI_H4 +int usbh_bluetooth_hci_write(uint8_t hci_type, uint8_t *buffer, uint32_t buflen) +{ + int ret; + + g_bluetooth_tx_buf[0] = hci_type; + memcpy(&g_bluetooth_tx_buf[1], buffer, buflen); + usbh_bluetooth_hci_dump(g_bluetooth_tx_buf, buflen + 1); + ret = usbh_bluetooth_hci_bulk_out(g_bluetooth_tx_buf, buflen + 1); + return ret; +} + +void usbh_bluetooth_hci_rx_thread(void *argument) +{ + int ret; + uint32_t ep_mps; + uint8_t retry = 0; + uint16_t actual_len = 0; + + ep_mps = USB_GET_MAXPACKETSIZE(g_bluetooth_class.bulkin->wMaxPacketSize); + + USB_LOG_INFO("Create hc rx thread\r\n"); + while (1) { + usbh_bulk_urb_fill(&g_bluetooth_class.bulkin_urb, g_bluetooth_class.hport, g_bluetooth_class.bulkin, &g_bluetooth_rx_buf[actual_len], ep_mps, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_bluetooth_class.bulkin_urb); + if (ret < 0) { + if (ret == -USB_ERR_SHUTDOWN) { + goto delete; + } else { + retry++; + if (retry == 3) { + retry = 0; + goto delete; + } + continue; + } + } + actual_len += g_bluetooth_class.bulkin_urb.actual_length; + if (g_bluetooth_class.bulkin_urb.actual_length != ep_mps) { + usbh_bluetooth_hci_dump(g_bluetooth_rx_buf, actual_len); + usbh_bluetooth_hci_read_callback(g_bluetooth_rx_buf, actual_len); + actual_len = 0; + } else { + /* read continue util read short packet */ + } + } + // clang-format off +delete : + USB_LOG_INFO("Delete hc acl rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +#else +static int usbh_bluetooth_hci_cmd(uint8_t *buffer, uint32_t buflen) +{ + struct usbh_bluetooth *bluetooth_class = &g_bluetooth_class; + struct usb_setup_packet *setup = bluetooth_class->hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = 0x00; + setup->wValue = 0; + setup->wIndex = bluetooth_class->intf; + setup->wLength = buflen; + + return usbh_control_transfer(bluetooth_class->hport, setup, buffer); +} + +int usbh_bluetooth_hci_write(uint8_t hci_type, uint8_t *buffer, uint32_t buflen) +{ + int ret; + + if (hci_type == USB_BLUETOOTH_HCI_CMD) { + g_bluetooth_cmd_buf[0] = USB_BLUETOOTH_HCI_CMD; + memcpy(&g_bluetooth_cmd_buf[1], buffer, buflen); + usbh_bluetooth_hci_dump(g_bluetooth_cmd_buf, buflen + 1); + ret = usbh_bluetooth_hci_cmd(&g_bluetooth_cmd_buf[1], buflen); + } else if (hci_type == USB_BLUETOOTH_HCI_ACL) { + g_bluetooth_tx_buf[0] = USB_BLUETOOTH_HCI_ACL; + memcpy(&g_bluetooth_tx_buf[1], buffer, buflen); + usbh_bluetooth_hci_dump(g_bluetooth_tx_buf, buflen + 1); + ret = usbh_bluetooth_hci_bulk_out(&g_bluetooth_tx_buf[1], buflen); + } else { + ret = -1; + } + + return ret; +} + +void usbh_bluetooth_hci_evt_rx_thread(void *argument) +{ + int ret; + uint32_t ep_mps; + uint32_t interval; + uint8_t retry = 0; + uint16_t actual_len = 0; + + ep_mps = USB_GET_MAXPACKETSIZE(g_bluetooth_class.intin->wMaxPacketSize); + interval = g_bluetooth_class.intin->bInterval; + + USB_LOG_INFO("Create hc event rx thread\r\n"); + while (1) { + usbh_int_urb_fill(&g_bluetooth_class.intin_urb, g_bluetooth_class.hport, g_bluetooth_class.intin, &g_bluetooth_evt_buf[1 + actual_len], ep_mps, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_bluetooth_class.intin_urb); + if (ret < 0) { + if (ret == -USB_ERR_SHUTDOWN) { + goto delete; + } else if (ret == -USB_ERR_NAK) { + usb_osal_msleep(interval); + continue; + } else { + retry++; + if (retry == 3) { + retry = 0; + goto delete; + } + usb_osal_msleep(interval); + continue; + } + } + actual_len += g_bluetooth_class.intin_urb.actual_length; + if (g_bluetooth_class.intin_urb.actual_length != ep_mps) { + g_bluetooth_evt_buf[0] = USB_BLUETOOTH_HCI_EVT; + usbh_bluetooth_hci_dump(g_bluetooth_evt_buf, actual_len + 1); + usbh_bluetooth_hci_read_callback(g_bluetooth_evt_buf, actual_len + 1); + actual_len = 0; + } else { + /* read continue util read short packet */ + } + usb_osal_msleep(interval); + } + // clang-format off +delete : + USB_LOG_INFO("Delete hc event rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +void usbh_bluetooth_hci_acl_rx_thread(void *argument) +{ + int ret; + uint32_t ep_mps; + uint8_t retry = 0; + uint16_t actual_len = 0; + + ep_mps = USB_GET_MAXPACKETSIZE(g_bluetooth_class.bulkin->wMaxPacketSize); + + USB_LOG_INFO("Create hc acl rx thread\r\n"); + while (1) { + usbh_bulk_urb_fill(&g_bluetooth_class.bulkin_urb, g_bluetooth_class.hport, g_bluetooth_class.bulkin, &g_bluetooth_rx_buf[1 + actual_len], ep_mps, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_bluetooth_class.bulkin_urb); + if (ret < 0) { + if (ret == -USB_ERR_SHUTDOWN) { + goto delete; + } else { + retry++; + if (retry == 3) { + retry = 0; + goto delete; + } + continue; + } + } + actual_len += g_bluetooth_class.bulkin_urb.actual_length; + if (g_bluetooth_class.bulkin_urb.actual_length != ep_mps) { + g_bluetooth_rx_buf[0] = USB_BLUETOOTH_HCI_ACL; + usbh_bluetooth_hci_dump(g_bluetooth_rx_buf, actual_len + 1); + usbh_bluetooth_hci_read_callback(g_bluetooth_rx_buf, actual_len + 1); + actual_len = 0; + } else { + /* read continue util read short packet */ + } + } + // clang-format off +delete : + USB_LOG_INFO("Delete hc acl rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} +#endif + +__WEAK void usbh_bluetooth_hci_read_callback(uint8_t *data, uint32_t len) +{ +} + +__WEAK void usbh_bluetooth_run(struct usbh_bluetooth *bluetooth_class) +{ +} + +__WEAK void usbh_bluetooth_stop(struct usbh_bluetooth *bluetooth_class) +{ +} + +static const struct usbh_class_driver bluetooth_class_driver = { + .driver_name = "bluetooth", + .connect = usbh_bluetooth_connect, + .disconnect = usbh_bluetooth_disconnect +}; + +#ifdef CONFIG_USBHOST_BLUETOOTH_HCI_H4 +static const uint16_t bluetooth_id_table[][2] = { + { 0x2fe3, 0x000c }, + { 0, 0 }, +}; + +CLASS_INFO_DEFINE const struct usbh_class_info bluetooth_h4_nrf_class_info = { + .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS, + .class = 0xff, + .subclass = 0x00, + .protocol = 0x00, + .id_table = bluetooth_id_table, + .class_driver = &bluetooth_class_driver +}; +#else +CLASS_INFO_DEFINE const struct usbh_class_info bluetooth_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .class = USB_DEVICE_CLASS_WIRELESS, + .subclass = 0x01, + .protocol = 0x01, + .id_table = NULL, + .class_driver = &bluetooth_class_driver +}; +#endif diff --git a/components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.h b/components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.h new file mode 100644 index 00000000000..868ff2c2cc2 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/wireless/usbh_bluetooth.h @@ -0,0 +1,56 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_BLUETOOTH_H +#define USBH_BLUETOOTH_H + +#define USB_BLUETOOTH_HCI_NONE 0x00 +#define USB_BLUETOOTH_HCI_CMD 0x01 +#define USB_BLUETOOTH_HCI_ACL 0x02 +#define USB_BLUETOOTH_HCI_SCO 0x03 +#define USB_BLUETOOTH_HCI_EVT 0x04 +#define USB_BLUETOOTH_HCI_ISO 0x05 + +struct usbh_bluetooth { + struct usbh_hubport *hport; + uint8_t intf; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN urb */ + struct usbh_urb bulkout_urb; /* Bulk OUT urb */ +#ifndef CONFIG_USBHOST_BLUETOOTH_HCI_H4 + struct usb_endpoint_descriptor *intin; /* INTR endpoint */ + struct usb_endpoint_descriptor *isoin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *isoout; /* Bulk OUT endpoint */ + struct usbh_urb intin_urb; /* INTR IN urb */ + struct usbh_urb *isoin_urb; /* Bulk IN urb */ + struct usbh_urb *isoout_urb; /* Bulk OUT urb */ + uint8_t num_of_intf_altsettings; +#endif + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_bluetooth_hci_write(uint8_t hci_type, uint8_t *buffer, uint32_t buflen); +void usbh_bluetooth_hci_read_callback(uint8_t *data, uint32_t len); +#ifdef CONFIG_USBHOST_BLUETOOTH_HCI_H4 +void usbh_bluetooth_hci_rx_thread(void *argument); +#else +void usbh_bluetooth_hci_evt_rx_thread(void *argument); +void usbh_bluetooth_hci_acl_rx_thread(void *argument); +#endif + +void usbh_bluetooth_run(struct usbh_bluetooth *bluetooth_class); +void usbh_bluetooth_stop(struct usbh_bluetooth *bluetooth_class); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_BLUETOOTH_H */ diff --git a/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c b/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c new file mode 100644 index 00000000000..969e6e53a58 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.c @@ -0,0 +1,561 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_rndis.h" +#include "rndis_protocol.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_rndis" +#include "usb_log.h" + +#define DEV_FORMAT "/dev/rndis" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_buf[4096]; + +#define CONFIG_USBHOST_RNDIS_ETH_MAX_FRAME_SIZE 1514 +#define CONFIG_USBHOST_RNDIS_ETH_MSG_SIZE (CONFIG_USBHOST_RNDIS_ETH_MAX_FRAME_SIZE + 44) + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_rx_buffer[CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_tx_buffer[CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE]; +// static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_rndis_inttx_buffer[16]; + +static struct usbh_rndis g_rndis_class; + +static int usbh_rndis_get_notification(struct usbh_rndis *rndis_class) +{ + // int ret; + // struct usbh_urb *urb = &rndis_class->intin_urb; + + // usbh_int_urb_fill(urb, rndis_class->hport, rndis_class->intin, g_rndis_inttx_buffer, rndis_class->intin->wMaxPacketSize, USB_OSAL_WAITING_FOREVER, NULL, NULL); + // ret = usbh_submit_urb(urb); + // if (ret == 0) { + // ret = urb->actual_length; + // } + // return ret; + return 0; +} + +static int usbh_rndis_init_msg_transfer(struct usbh_rndis *rndis_class) +{ + struct usb_setup_packet *setup = rndis_class->hport->setup; + int ret = 0; + rndis_initialize_msg_t *cmd; + rndis_initialize_cmplt_t *resp; + + cmd = (rndis_initialize_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_INITIALIZE_MSG; + cmd->MessageLength = sizeof(rndis_initialize_msg_t); + cmd->RequestId = rndis_class->request_id++; + cmd->MajorVersion = 1; + cmd->MinorVersion = 0; + cmd->MaxTransferSize = 0x4000; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = sizeof(rndis_initialize_msg_t); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("rndis_initialize_msg_t send error, ret: %d\r\n", ret); + return ret; + } + + usbh_rndis_get_notification(rndis_class); + + resp = (rndis_initialize_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 4096; + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("rndis_initialize_cmplt_t recv error, ret: %d\r\n", ret); + return ret; + } + + return ret; +} + +int usbh_rndis_query_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, uint32_t query_len, uint8_t *info, uint32_t *info_len) +{ + struct usb_setup_packet *setup = rndis_class->hport->setup; + int ret = 0; + rndis_query_msg_t *cmd; + rndis_query_cmplt_t *resp; + + cmd = (rndis_query_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_QUERY_MSG; + cmd->MessageLength = query_len + sizeof(rndis_query_msg_t); + cmd->RequestId = rndis_class->request_id++; + cmd->Oid = oid; + cmd->InformationBufferLength = query_len; + cmd->InformationBufferOffset = 20; + cmd->DeviceVcHandle = 0; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = query_len + sizeof(rndis_query_msg_t); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + usbh_rndis_get_notification(rndis_class); + + resp = (rndis_query_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 4096; + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("oid:%08x recv error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + memcpy(info, ((uint8_t *)resp + sizeof(rndis_query_cmplt_t)), resp->InformationBufferLength); + *info_len = resp->InformationBufferLength; + + return ret; +} + +static int usbh_rndis_set_msg_transfer(struct usbh_rndis *rndis_class, uint32_t oid, uint8_t *info, uint32_t info_len) +{ + struct usb_setup_packet *setup = rndis_class->hport->setup; + int ret = 0; + rndis_set_msg_t *cmd; + rndis_set_cmplt_t *resp; + + cmd = (rndis_set_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_SET_MSG; + cmd->MessageLength = info_len + sizeof(rndis_set_msg_t); + cmd->RequestId = rndis_class->request_id++; + cmd->Oid = oid; + cmd->InformationBufferLength = info_len; + cmd->InformationBufferOffset = 20; + cmd->DeviceVcHandle = 0; + + memcpy(((uint8_t *)cmd + sizeof(rndis_set_msg_t)), info, info_len); + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = info_len + sizeof(rndis_set_msg_t); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("oid:%08x send error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + usbh_rndis_get_notification(rndis_class); + + resp = (rndis_set_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 4096; + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("oid:%08x recv error, ret: %d\r\n", (unsigned int)oid, ret); + return ret; + } + + return ret; +} + +int usbh_rndis_get_connect_status(struct usbh_rndis *rndis_class) +{ + int ret; + uint8_t data[32]; + uint32_t data_len; + + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_MEDIA_CONNECT_STATUS, 4, data, &data_len); + if (ret < 0) { + return ret; + } + if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { + rndis_class->connect_status = true; + } else { + rndis_class->connect_status = false; + } + return 0; +} + +int usbh_rndis_keepalive(struct usbh_rndis *rndis_class) +{ + struct usb_setup_packet *setup = rndis_class->hport->setup; + int ret = 0; + rndis_keepalive_msg_t *cmd; + rndis_keepalive_cmplt_t *resp; + + cmd = (rndis_keepalive_msg_t *)g_rndis_buf; + + cmd->MessageType = REMOTE_NDIS_KEEPALIVE_MSG; + cmd->MessageLength = sizeof(rndis_keepalive_msg_t); + cmd->RequestId = rndis_class->request_id++; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_SEND_ENCAPSULATED_COMMAND; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = sizeof(rndis_keepalive_msg_t); + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)cmd); + if (ret < 0) { + USB_LOG_ERR("keepalive send error, ret: %d\r\n", ret); + return ret; + } + + usbh_rndis_get_notification(rndis_class); + + resp = (rndis_keepalive_cmplt_t *)g_rndis_buf; + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_CLASS | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = CDC_REQUEST_GET_ENCAPSULATED_RESPONSE; + setup->wValue = 0; + setup->wIndex = 0; + setup->wLength = 4096; + + ret = usbh_control_transfer(rndis_class->hport, setup, (uint8_t *)resp); + if (ret < 0) { + USB_LOG_ERR("keepalive recv error, ret: %d\r\n", ret); + return ret; + } + + return ret; +} + +static int usbh_rndis_connect(struct usbh_hubport *hport, uint8_t intf) +{ + struct usb_endpoint_descriptor *ep_desc; + int ret; + uint32_t *oid_support_list; + unsigned int oid = 0; + unsigned int oid_num = 0; + uint32_t data_len; + uint8_t tmp_buffer[512]; + uint8_t data[32]; + + struct usbh_rndis *rndis_class = &g_rndis_class; + + memset(rndis_class, 0, sizeof(struct usbh_rndis)); + + rndis_class->hport = hport; + rndis_class->ctrl_intf = intf; + rndis_class->data_intf = intf + 1; + + hport->config.intf[intf].priv = rndis_class; + hport->config.intf[intf + 1].priv = NULL; + + // ep_desc = &hport->config.intf[intf].altsetting[0].ep[0].ep_desc; + // USBH_EP_INIT(rndis_class->intin, ep_desc); + + for (uint8_t i = 0; i < hport->config.intf[intf + 1].altsetting[0].intf_desc.bNumEndpoints; i++) { + ep_desc = &hport->config.intf[intf + 1].altsetting[0].ep[i].ep_desc; + + if (ep_desc->bEndpointAddress & 0x80) { + USBH_EP_INIT(rndis_class->bulkin, ep_desc); + } else { + USBH_EP_INIT(rndis_class->bulkout, ep_desc); + } + } + + ret = usbh_rndis_init_msg_transfer(rndis_class); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("rndis init success\r\n"); + + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_SUPPORTED_LIST, 0, tmp_buffer, &data_len); + if (ret < 0) { + return ret; + } + oid_num = (data_len / 4); + USB_LOG_INFO("rndis query OID_GEN_SUPPORTED_LIST success,oid num :%d\r\n", oid_num); + + oid_support_list = (uint32_t *)tmp_buffer; + + for (uint8_t i = 0; i < oid_num; i++) { + oid = oid_support_list[i]; + switch (oid) { + case OID_GEN_PHYSICAL_MEDIUM: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_PHYSICAL_MEDIUM, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + case OID_GEN_MAXIMUM_FRAME_SIZE: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_MAXIMUM_FRAME_SIZE, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + case OID_GEN_LINK_SPEED: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_LINK_SPEED, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + + memcpy(&rndis_class->link_speed, data, 4); + break; + case OID_GEN_MEDIA_CONNECT_STATUS: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_GEN_MEDIA_CONNECT_STATUS, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + if (NDIS_MEDIA_STATE_CONNECTED == data[0]) { + rndis_class->connect_status = true; + } else { + rndis_class->connect_status = false; + } + break; + case OID_802_3_MAXIMUM_LIST_SIZE: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_802_3_MAXIMUM_LIST_SIZE, 4, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + case OID_802_3_CURRENT_ADDRESS: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_802_3_CURRENT_ADDRESS, 6, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + + for (uint8_t j = 0; j < 6; j++) { + rndis_class->mac[j] = data[j]; + } + break; + case OID_802_3_PERMANENT_ADDRESS: + ret = usbh_rndis_query_msg_transfer(rndis_class, OID_802_3_PERMANENT_ADDRESS, 6, data, &data_len); + if (ret < 0) { + goto query_errorout; + } + break; + default: + USB_LOG_WRN("Ignore rndis query iod:%08x\r\n", oid); + continue; + } + USB_LOG_INFO("rndis query iod:%08x success\r\n", oid); + } + + uint32_t packet_filter = 0x0f; + usbh_rndis_set_msg_transfer(rndis_class, OID_GEN_CURRENT_PACKET_FILTER, (uint8_t *)&packet_filter, 4); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("rndis set OID_GEN_CURRENT_PACKET_FILTER success\r\n"); + + uint8_t multicast_list[6] = { 0x01, 0x00, 0x5E, 0x00, 0x00, 0x01 }; + usbh_rndis_set_msg_transfer(rndis_class, OID_802_3_MULTICAST_LIST, multicast_list, 6); + if (ret < 0) { + return ret; + } + USB_LOG_INFO("rndis set OID_802_3_MULTICAST_LIST success\r\n"); + + USB_LOG_INFO("rndis MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n", + rndis_class->mac[0], + rndis_class->mac[1], + rndis_class->mac[2], + rndis_class->mac[3], + rndis_class->mac[4], + rndis_class->mac[5]); + + memcpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN); + + USB_LOG_INFO("Register RNDIS Class:%s\r\n", hport->config.intf[intf].devname); + usbh_rndis_run(rndis_class); + return ret; +query_errorout: + USB_LOG_ERR("rndis query iod:%08x error\r\n", oid); + return ret; +} + +static int usbh_rndis_disconnect(struct usbh_hubport *hport, uint8_t intf) +{ + int ret = 0; + + struct usbh_rndis *rndis_class = (struct usbh_rndis *)hport->config.intf[intf].priv; + + if (rndis_class) { + if (rndis_class->bulkin) { + usbh_kill_urb(&rndis_class->bulkin_urb); + } + + if (rndis_class->bulkout) { + usbh_kill_urb(&rndis_class->bulkout_urb); + } + + // if (rndis_class->intin) { + // usbh_kill_urb(&rndis_class->intin_urb); + // } + + if (hport->config.intf[intf].devname[0] != '\0') { + USB_LOG_INFO("Unregister RNDIS Class:%s\r\n", hport->config.intf[intf].devname); + usbh_rndis_stop(rndis_class); + } + + memset(rndis_class, 0, sizeof(struct usbh_rndis)); + } + + return ret; +} + +void usbh_rndis_rx_thread(void *argument) +{ + uint32_t g_rndis_rx_length; + int ret; + uint32_t pmg_offset; + rndis_data_packet_t *pmsg; + rndis_data_packet_t temp; + + USB_LOG_INFO("Create rndis rx thread\r\n"); + // clang-format off +find_class: + // clang-format on + g_rndis_class.connect_status = false; + if (usbh_find_class_instance("/dev/rndis") == NULL) { + goto delete; + } + + while (g_rndis_class.connect_status == false) { + ret = usbh_rndis_get_connect_status(&g_rndis_class); + if (ret < 0) { + usb_osal_msleep(100); + goto find_class; + } + } + + g_rndis_rx_length = 0; + while (1) { + usbh_bulk_urb_fill(&g_rndis_class.bulkin_urb, g_rndis_class.hport, g_rndis_class.bulkin, g_rndis_rx_buffer, (CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE > (16 * 1024)) ? (16 * 1024) : CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE, USB_OSAL_WAITING_FOREVER, NULL, NULL); + ret = usbh_submit_urb(&g_rndis_class.bulkin_urb); + if (ret < 0) { + goto find_class; + } + + g_rndis_rx_length += g_rndis_class.bulkin_urb.actual_length; + if (g_rndis_rx_length % USB_GET_MAXPACKETSIZE(g_rndis_class.bulkin->wMaxPacketSize)) { + pmg_offset = 0; + + uint32_t total_len = g_rndis_rx_length; + + while (g_rndis_rx_length > 0) { + USB_LOG_DBG("rxlen:%d\r\n", g_rndis_rx_length); + + pmsg = (rndis_data_packet_t *)(g_rndis_rx_buffer + pmg_offset); + + /* Not word-aligned case */ + if (pmg_offset & 0x3) { + memcpy(&temp, pmsg, sizeof(rndis_data_packet_t)); + pmsg = &temp; + } + + if (pmsg->MessageType == REMOTE_NDIS_PACKET_MSG) { + uint8_t *buf = (uint8_t *)(g_rndis_rx_buffer + pmg_offset + sizeof(rndis_generic_msg_t) + pmsg->DataOffset); + + usbh_rndis_eth_input(buf, pmsg->DataLength); + pmg_offset += pmsg->MessageLength; + g_rndis_rx_length -= pmsg->MessageLength; + + /* drop the last dummy byte, it is a short packet to tell us we have received a multiple of wMaxPacketSize */ + if (g_rndis_rx_length < 4) { + g_rndis_rx_length = 0; + } + } else { + USB_LOG_ERR("offset:%d,remain:%d,total:%d\r\n", pmg_offset, g_rndis_rx_length, total_len); + g_rndis_rx_length = 0; + USB_LOG_ERR("Error rndis packet message\r\n"); + } + } + } else { + if (g_rndis_rx_length > CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE) { + USB_LOG_ERR("Rx packet is overflow\r\n"); + g_rndis_rx_length = 0; + } + } + } + + // clang-format off +delete: + USB_LOG_INFO("Delete rndis rx thread\r\n"); + usb_osal_thread_delete(NULL); + // clang-format on +} + +int usbh_rndis_eth_output(uint8_t *buf, uint32_t buflen) +{ + uint8_t *buffer; + rndis_data_packet_t *hdr; + uint32_t len; + + if (g_rndis_class.connect_status == false) { + return -USB_ERR_NOTCONN; + } + + hdr = (rndis_data_packet_t *)g_rndis_tx_buffer; + memset(hdr, 0, sizeof(rndis_data_packet_t)); + + hdr->MessageType = REMOTE_NDIS_PACKET_MSG; + hdr->MessageLength = sizeof(rndis_data_packet_t) + buflen; + hdr->DataOffset = sizeof(rndis_data_packet_t) - sizeof(rndis_generic_msg_t); + hdr->DataLength = buflen; + + buffer = (uint8_t *)(g_rndis_tx_buffer + sizeof(rndis_data_packet_t)); + memcpy(buffer, buf, buflen); + + len = hdr->MessageLength; + /* if message length is the multiple of wMaxPacketSize, we should add a short packet to tell device transfer is over. */ + if (!(hdr->MessageLength % g_rndis_class.bulkout->wMaxPacketSize)) { + len += 1; + } + + USB_LOG_DBG("txlen:%d\r\n", len); + + usbh_bulk_urb_fill(&g_rndis_class.bulkout_urb, g_rndis_class.hport, g_rndis_class.bulkout, g_rndis_tx_buffer, len, USB_OSAL_WAITING_FOREVER, NULL, NULL); + return usbh_submit_urb(&g_rndis_class.bulkout_urb); +} + +__WEAK void usbh_rndis_run(struct usbh_rndis *rndis_class) +{ +} + +__WEAK void usbh_rndis_stop(struct usbh_rndis *rndis_class) +{ +} + +static const struct usbh_class_driver rndis_class_driver = { + .driver_name = "rndis", + .connect = usbh_rndis_connect, + .disconnect = usbh_rndis_disconnect +}; + +CLASS_INFO_DEFINE const struct usbh_class_info rndis_class_info = { + .match_flags = USB_CLASS_MATCH_INTF_CLASS | USB_CLASS_MATCH_INTF_SUBCLASS | USB_CLASS_MATCH_INTF_PROTOCOL, + .class = USB_DEVICE_CLASS_WIRELESS, + .subclass = 0x01, + .protocol = 0x03, + .id_table = NULL, + .class_driver = &rndis_class_driver +}; diff --git a/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.h b/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.h new file mode 100644 index 00000000000..be56e4004e4 --- /dev/null +++ b/components/drivers/usb/cherryusb/class/wireless/usbh_rndis.h @@ -0,0 +1,51 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_RNDIS_H +#define USBH_RNDIS_H + +#include "usb_cdc.h" + +struct usbh_rndis { + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *bulkin; /* Bulk IN endpoint */ + struct usb_endpoint_descriptor *bulkout; /* Bulk OUT endpoint */ + struct usb_endpoint_descriptor *intin; /* INTR endpoint */ + struct usbh_urb bulkin_urb; /* Bulk IN urb */ + struct usbh_urb bulkout_urb; /* Bulk OUT urb */ + struct usbh_urb intin_urb; /* INTR IN urb */ + + uint8_t ctrl_intf; /* Control interface number */ + uint8_t data_intf; /* Data interface number */ + uint8_t minor; + + uint32_t request_id; + + uint32_t link_speed; + bool connect_status; + uint8_t mac[6]; + + void *user_data; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int usbh_rndis_get_connect_status(struct usbh_rndis *rndis_class); +int usbh_rndis_keepalive(struct usbh_rndis *rndis_class); + +void usbh_rndis_run(struct usbh_rndis *rndis_class); +void usbh_rndis_stop(struct usbh_rndis *rndis_class); + +int usbh_rndis_eth_output(uint8_t *buf, uint32_t buflen); +void usbh_rndis_eth_input(uint8_t *buf, uint32_t buflen); +void usbh_rndis_rx_thread(void *argument); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_RNDIS_H */ diff --git a/components/drivers/usb/cherryusb/common/usb_dc.h b/components/drivers/usb/cherryusb/common/usb_dc.h new file mode 100644 index 00000000000..a10869aacc1 --- /dev/null +++ b/components/drivers/usb/cherryusb/common/usb_dc.h @@ -0,0 +1,194 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DC_H +#define USB_DC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief init device controller registers. + * @return On success will return 0, and others indicate fail. + */ +int usb_dc_init(uint8_t busid); + +/** + * @brief deinit device controller registers. + * @return On success will return 0, and others indicate fail. + */ +int usb_dc_deinit(uint8_t busid); + +/** + * @brief Set USB device address + * + * @param[in] addr Device address + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_set_address(uint8_t busid, const uint8_t addr); + +/** + * @brief Get USB device speed + * + * @param[in] busid bus index + * + * @return port speed, USB_SPEED_LOW or USB_SPEED_FULL or USB_SPEED_HIGH + */ +uint8_t usbd_get_port_speed(uint8_t busid); + +/** + * @brief configure and enable endpoint. + * + * @param [in] ep_cfg Endpoint config. + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep); + +/** + * @brief Disable the selected endpoint + * + * @param[in] ep Endpoint address + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_close(uint8_t busid, const uint8_t ep); + +/** + * @brief Set stall condition for the selected endpoint + * + * @param[in] ep Endpoint address + * + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep); + +/** + * @brief Clear stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep); + +/** + * @brief Check if the selected endpoint is stalled + * + * @param[in] ep Endpoint address + * + * @param[out] stalled Endpoint stall status + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled); + +/** + * @brief Setup in ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with tx dma. + * + * This function is called to write data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is transmitted + * out. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of the data requested to write. This may + * be zero for a zero length status packet. + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len); + +/** + * @brief Setup out ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with rx dma. + * + * This function is called to read data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is received + * in. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to read + * @param[in] data_len Max length of the data requested to read. + * + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len); + +/* usb dcd irq callback */ + +/** + * @brief Usb connect irq callback. + */ +void usbd_event_connect_handler(uint8_t busid); + +/** + * @brief Usb disconnect irq callback. + */ +void usbd_event_disconnect_handler(uint8_t busid); + +/** + * @brief Usb resume irq callback. + */ +void usbd_event_resume_handler(uint8_t busid); + +/** + * @brief Usb suspend irq callback. + */ +void usbd_event_suspend_handler(uint8_t busid); + +/** + * @brief Usb reset irq callback. + */ +void usbd_event_reset_handler(uint8_t busid); + +/** + * @brief Usb setup packet recv irq callback. + * @param[in] psetup setup packet. + */ +void usbd_event_ep0_setup_complete_handler(uint8_t busid, uint8_t *psetup); + +/** + * @brief In ep transfer complete irq callback. + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] nbytes How many nbytes have transferred. + */ +void usbd_event_ep_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes); + +/** + * @brief Out ep transfer complete irq callback. + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] nbytes How many nbytes have transferred. + */ +void usbd_event_ep_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes); + +#ifdef CONFIG_USBDEV_TEST_MODE +/** + * @brief Usb execute test mode + * @param[in] busid device busid + * @param[in] test_mode usb test mode + */ +void usbd_execute_test_mode(uint8_t busid, uint8_t test_mode); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USB_DC_H */ diff --git a/components/drivers/usb/cherryusb/common/usb_def.h b/components/drivers/usb/cherryusb/common/usb_def.h new file mode 100644 index 00000000000..aea3d6ad5ad --- /dev/null +++ b/components/drivers/usb/cherryusb/common/usb_def.h @@ -0,0 +1,724 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DEF_H +#define USB_DEF_H + +/* Useful define */ +#define USB_1_1 0x0110 +#define USB_2_0 0x0200 +/* Set USB version to 2.1 so that the host will request the BOS descriptor */ +#define USB_2_1 0x0210 +#define USB_3_0 0x0300 +#define USB_3_1 0x0310 +#define USB_3_2 0x0320 + +/* Device speeds */ +#define USB_SPEED_UNKNOWN 0 /* Transfer rate not yet set */ +#define USB_SPEED_LOW 1 /* USB 1.1 */ +#define USB_SPEED_FULL 2 /* USB 1.1 */ +#define USB_SPEED_HIGH 3 /* USB 2.0 */ +#define USB_SPEED_WIRELESS 4 /* Wireless USB 2.5 */ +#define USB_SPEED_SUPER 5 /* USB 3.0 */ +#define USB_SPEED_SUPER_PLUS 6 /* USB 3.1 */ + +/* Maximum number of devices per controller */ +#define USB_MAX_DEVICES (127) + +/* Default USB control EP, always 0 and 0x80 */ +#define USB_CONTROL_OUT_EP0 0 +#define USB_CONTROL_IN_EP0 0x80 + +/**< maximum packet size (MPS) for EP 0 */ +#define USB_CTRL_EP_MPS 64 + +/**< maximum packet size (MPS) for bulk EP */ +#define USB_BULK_EP_MPS_HS 512 +#define USB_BULK_EP_MPS_FS 64 + +/* USB PID Types */ +#define USB_PID_OUT (0x01) /* Tokens */ +#define USB_PID_IN (0x09) +#define USB_PID_SOF (0x05) +#define USB_PID_SETUP (0x0d) + +#define USB_PID_DATA0 (0x03) /* Data */ +#define USB_PID_DATA1 (0x0b) +#define USB_PID_DATA2 (0x07) +#define USB_PID_MDATA (0x0f) + +#define USB_PID_ACK (0x02) /* Handshake */ +#define USB_PID_NAK (0x0a) +#define USB_PID_STALL (0x0e) +#define USB_PID_NYET (0x06) + +#define USB_PID_PRE (0x0c) /* Special */ +#define USB_PID_ERR (0x0c) +#define USB_PID_SPLIT (0x08) +#define USB_PID_PING (0x04) +#define USB_PID_RESERVED (0x00) + +#define USB_REQUEST_DIR_SHIFT 7U /* Bits 7: Request dir */ +#define USB_REQUEST_DIR_OUT (0U << USB_REQUEST_DIR_SHIFT) /* Bit 7=0: Host-to-device */ +#define USB_REQUEST_DIR_IN (1U << USB_REQUEST_DIR_SHIFT) /* Bit 7=1: Device-to-host */ +#define USB_REQUEST_DIR_MASK (1U << USB_REQUEST_DIR_SHIFT) /* Bit 7=1: Direction bit */ + +#define USB_REQUEST_TYPE_SHIFT 5U /* Bits 5:6: Request type */ +#define USB_REQUEST_STANDARD (0U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_CLASS (1U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_VENDOR (2U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_RESERVED (3U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_TYPE_MASK (3U << USB_REQUEST_TYPE_SHIFT) + +#define USB_REQUEST_RECIPIENT_SHIFT 0U /* Bits 0:4: Recipient */ +#define USB_REQUEST_RECIPIENT_DEVICE (0U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_INTERFACE (1U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_ENDPOINT (2U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_OTHER (3U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_MASK (3U << USB_REQUEST_RECIPIENT_SHIFT) + +/* USB Standard Request Codes */ +#define USB_REQUEST_GET_STATUS 0x00 +#define USB_REQUEST_CLEAR_FEATURE 0x01 +#define USB_REQUEST_SET_FEATURE 0x03 +#define USB_REQUEST_SET_ADDRESS 0x05 +#define USB_REQUEST_GET_DESCRIPTOR 0x06 +#define USB_REQUEST_SET_DESCRIPTOR 0x07 +#define USB_REQUEST_GET_CONFIGURATION 0x08 +#define USB_REQUEST_SET_CONFIGURATION 0x09 +#define USB_REQUEST_GET_INTERFACE 0x0A +#define USB_REQUEST_SET_INTERFACE 0x0B +#define USB_REQUEST_SYNCH_FRAME 0x0C +#define USB_REQUEST_SET_ENCRYPTION 0x0D +#define USB_REQUEST_GET_ENCRYPTION 0x0E +#define USB_REQUEST_RPIPE_ABORT 0x0E +#define USB_REQUEST_SET_HANDSHAKE 0x0F +#define USB_REQUEST_RPIPE_RESET 0x0F +#define USB_REQUEST_GET_HANDSHAKE 0x10 +#define USB_REQUEST_SET_CONNECTION 0x11 +#define USB_REQUEST_SET_SECURITY_DATA 0x12 +#define USB_REQUEST_GET_SECURITY_DATA 0x13 +#define USB_REQUEST_SET_WUSB_DATA 0x14 +#define USB_REQUEST_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQUEST_LOOPBACK_DATA_READ 0x16 +#define USB_REQUEST_SET_INTERFACE_DS 0x17 + +/* USB Standard Feature selectors */ +#define USB_FEATURE_ENDPOINT_HALT 0 +#define USB_FEATURE_SELF_POWERED 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 +#define USB_FEATURE_BATTERY 2 +#define USB_FEATURE_BHNPENABLE 3 +#define USB_FEATURE_WUSBDEVICE 3 +#define USB_FEATURE_AHNPSUPPORT 4 +#define USB_FEATURE_AALTHNPSUPPORT 5 +#define USB_FEATURE_DEBUGMODE 6 + +/* USB GET_STATUS Bit Values */ +#define USB_GETSTATUS_ENDPOINT_HALT 0x01 +#define USB_GETSTATUS_SELF_POWERED 0x01 +#define USB_GETSTATUS_REMOTE_WAKEUP 0x02 + +/* USB Descriptor Types */ +#define USB_DESCRIPTOR_TYPE_DEVICE 0x01U +#define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02U +#define USB_DESCRIPTOR_TYPE_STRING 0x03U +#define USB_DESCRIPTOR_TYPE_INTERFACE 0x04U +#define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05U +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06U +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED 0x07U +#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08U +#define USB_DESCRIPTOR_TYPE_OTG 0x09U +#define USB_DESCRIPTOR_TYPE_DEBUG 0x0AU +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION 0x0BU +#define USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE 0x0FU +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY 0x10U +#define USB_DESCRIPTOR_TYPE_WIRELESS_ENDPOINTCOMP 0x11U + +/* Class Specific Descriptor */ +#define USB_CS_DESCRIPTOR_TYPE_DEVICE 0x21U +#define USB_CS_DESCRIPTOR_TYPE_CONFIGURATION 0x22U +#define USB_CS_DESCRIPTOR_TYPE_STRING 0x23U +#define USB_CS_DESCRIPTOR_TYPE_INTERFACE 0x24U +#define USB_CS_DESCRIPTOR_TYPE_ENDPOINT 0x25U + +#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ENDPOINT_COMPANION 0x30U +#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ISO_ENDPOINT_COMPANION 0x31U + +/* USB Device Classes */ +#define USB_DEVICE_CLASS_RESERVED 0x00 +#define USB_DEVICE_CLASS_AUDIO 0x01 +#define USB_DEVICE_CLASS_CDC 0x02 +#define USB_DEVICE_CLASS_HID 0x03 +#define USB_DEVICE_CLASS_MONITOR 0x04 +#define USB_DEVICE_CLASS_PHYSICAL 0x05 +#define USB_DEVICE_CLASS_IMAGE 0x06 +#define USB_DEVICE_CLASS_PRINTER 0x07 +#define USB_DEVICE_CLASS_MASS_STORAGE 0x08 +#define USB_DEVICE_CLASS_HUB 0x09 +#define USB_DEVICE_CLASS_CDC_DATA 0x0a +#define USB_DEVICE_CLASS_SMART_CARD 0x0b +#define USB_DEVICE_CLASS_SECURITY 0x0d +#define USB_DEVICE_CLASS_VIDEO 0x0e +#define USB_DEVICE_CLASS_HEALTHCARE 0x0f +#define USB_DEVICE_CLASS_DIAG_DEVICE 0xdc +#define USB_DEVICE_CLASS_WIRELESS 0xe0 +#define USB_DEVICE_CLASS_MISC 0xef +#define USB_DEVICE_CLASS_APP_SPECIFIC 0xfe +#define USB_DEVICE_CLASS_VEND_SPECIFIC 0xff + +/* usb string index define */ +#define USB_STRING_LANGID_INDEX 0x00 +#define USB_STRING_MFC_INDEX 0x01 +#define USB_STRING_PRODUCT_INDEX 0x02 +#define USB_STRING_SERIAL_INDEX 0x03 +#define USB_STRING_CONFIG_INDEX 0x04 +#define USB_STRING_INTERFACE_INDEX 0x05 +#define USB_STRING_OS_INDEX 0x06 +#define USB_STRING_MAX USB_STRING_OS_INDEX +/* + * Devices supporting Microsoft OS Descriptors store special string + * descriptor at fixed index (0xEE). It is read when a new device is + * attached to a computer for the first time. + */ +#define USB_OSDESC_STRING_DESC_INDEX 0xEE + +/* bmAttributes in Configuration Descriptor */ +#define USB_CONFIG_REMOTE_WAKEUP 0x20 +#define USB_CONFIG_POWERED_MASK 0x40 +#define USB_CONFIG_BUS_POWERED 0x80 +#define USB_CONFIG_SELF_POWERED 0xC0 + +/* bMaxPower in Configuration Descriptor */ +#define USB_CONFIG_POWER_MA(mA) ((mA) / 2) + +/* bEndpointAddress in Endpoint Descriptor */ +#define USB_ENDPOINT_DIRECTION_MASK 0x80 +#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) + +/** + * USB endpoint direction and number. + */ +#define USB_EP_DIR_MASK 0x80U +#define USB_EP_DIR_IN 0x80U +#define USB_EP_DIR_OUT 0x00U + +/** Get endpoint index (number) from endpoint address */ +#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) +/** Get direction from endpoint address */ +#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) +/** Get endpoint address from endpoint index and direction */ +#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) +/** True if the endpoint is an IN endpoint */ +#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) +/** True if the endpoint is an OUT endpoint */ +#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) + +/* bmAttributes in Endpoint Descriptor */ +#define USB_ENDPOINT_TYPE_SHIFT 0 +#define USB_ENDPOINT_TYPE_CONTROL (0 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_ISOCHRONOUS (1 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_BULK (2 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_INTERRUPT (3 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_MASK (3 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_GET_ENDPOINT_TYPE(x) ((x & USB_ENDPOINT_TYPE_MASK) >> USB_ENDPOINT_TYPE_SHIFT) + +#define USB_ENDPOINT_SYNC_SHIFT 2 +#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION (0 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_ASYNCHRONOUS (1 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_ADAPTIVE (2 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_SYNCHRONOUS (3 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_MASK (3 << USB_ENDPOINT_SYNC_SHIFT) + +#define USB_ENDPOINT_USAGE_SHIFT 4 +#define USB_ENDPOINT_USAGE_DATA (0 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_FEEDBACK (1 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK (2 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_MASK (3 << USB_ENDPOINT_USAGE_SHIFT) + +#define USB_ENDPOINT_MAX_ADJUSTABLE (1 << 7) + +/* wMaxPacketSize in Endpoint Descriptor */ +#define USB_MAXPACKETSIZE_SHIFT 0 +#define USB_MAXPACKETSIZE_MASK (0x7ff << USB_MAXPACKETSIZE_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT 11 +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_NONE (0 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_ONE (1 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_TWO (2 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK (3 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_GET_MAXPACKETSIZE(x) ((x & USB_MAXPACKETSIZE_MASK) >> USB_MAXPACKETSIZE_SHIFT) +#define USB_GET_MULT(x) ((x & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) + +/* bDevCapabilityType in Device Capability Descriptor */ +#define USB_DEVICE_CAPABILITY_WIRELESS_USB 1 +#define USB_DEVICE_CAPABILITY_USB_2_0_EXTENSION 2 +#define USB_DEVICE_CAPABILITY_SUPERSPEED_USB 3 +#define USB_DEVICE_CAPABILITY_CONTAINER_ID 4 +#define USB_DEVICE_CAPABILITY_PLATFORM 5 +#define USB_DEVICE_CAPABILITY_POWER_DELIVERY_CAPABILITY 6 +#define USB_DEVICE_CAPABILITY_BATTERY_INFO_CAPABILITY 7 +#define USB_DEVICE_CAPABILITY_PD_CONSUMER_PORT_CAPABILITY 8 +#define USB_DEVICE_CAPABILITY_PD_PROVIDER_PORT_CAPABILITY 9 +#define USB_DEVICE_CAPABILITY_SUPERSPEED_PLUS 10 +#define USB_DEVICE_CAPABILITY_PRECISION_TIME_MEASUREMENT 11 +#define USB_DEVICE_CAPABILITY_WIRELESS_USB_EXT 12 + +#define USB_BOS_CAPABILITY_EXTENSION 0x02 +#define USB_BOS_CAPABILITY_PLATFORM 0x05 + +/* OTG SET FEATURE Constants */ +#define USB_OTG_FEATURE_B_HNP_ENABLE 3 /* Enable B device to perform HNP */ +#define USB_OTG_FEATURE_A_HNP_SUPPORT 4 /* A device supports HNP */ +#define USB_OTG_FEATURE_A_ALT_HNP_SUPPORT 5 /* Another port on the A device supports HNP */ + +/* WinUSB Microsoft OS 2.0 descriptor request codes */ +#define WINUSB_REQUEST_GET_DESCRIPTOR_SET 0x07 +#define WINUSB_REQUEST_SET_ALT_ENUM 0x08 + +/* WinUSB Microsoft OS 2.0 descriptor sizes */ +#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 +#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 +#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 + +/* WinUSB Microsoft OS 2.0 Descriptor Types */ +#define WINUSB_SET_HEADER_DESCRIPTOR_TYPE 0x00 +#define WINUSB_SUBSET_HEADER_CONFIGURATION_TYPE 0x01 +#define WINUSB_SUBSET_HEADER_FUNCTION_TYPE 0x02 +#define WINUSB_FEATURE_COMPATIBLE_ID_TYPE 0x03 +#define WINUSB_FEATURE_REG_PROPERTY_TYPE 0x04 +#define WINUSB_FEATURE_MIN_RESUME_TIME_TYPE 0x05 +#define WINUSB_FEATURE_MODEL_ID_TYPE 0x06 +#define WINUSB_FEATURE_CCGP_DEVICE_TYPE 0x07 + +#define WINUSB_PROP_DATA_TYPE_REG_SZ 0x01 +#define WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ 0x07 + +/* WebUSB Descriptor Types */ +#define WEBUSB_DESCRIPTOR_SET_HEADER_TYPE 0x00 +#define WEBUSB_CONFIGURATION_SUBSET_HEADER_TYPE 0x01 +#define WEBUSB_FUNCTION_SUBSET_HEADER_TYPE 0x02 +#define WEBUSB_URL_TYPE 0x03 + +/* WebUSB Request Codes */ +#define WEBUSB_REQUEST_GET_URL 0x02 + +/* bScheme in URL descriptor */ +#define WEBUSB_URL_SCHEME_HTTP 0x00 +#define WEBUSB_URL_SCHEME_HTTPS 0x01 + +/* WebUSB Descriptor sizes */ +#define WEBUSB_DESCRIPTOR_SET_HEADER_SIZE 5 +#define WEBUSB_CONFIGURATION_SUBSET_HEADER_SIZE 4 +#define WEBUSB_FUNCTION_SUBSET_HEADER_SIZE 3 + +/* Setup packet definition used to read raw data from USB line */ +struct usb_setup_packet { + /** Request type. Bits 0:4 determine recipient, see + * \ref usb_request_recipient. Bits 5:6 determine type, see + * \ref usb_request_type. Bit 7 determines data transfer direction, see + * \ref usb_endpoint_direction. + */ + uint8_t bmRequestType; + + /** Request. If the type bits of bmRequestType are equal to + * \ref usb_request_type::LIBUSB_REQUEST_TYPE_STANDARD + * "USB_REQUEST_TYPE_STANDARD" then this field refers to + * \ref usb_standard_request. For other cases, use of this field is + * application-specific. */ + uint8_t bRequest; + + /** Value. Varies according to request */ + uint16_t wValue; + + /** Index. Varies according to request, typically used to pass an index + * or offset */ + uint16_t wIndex; + + /** Number of bytes to transfer */ + uint16_t wLength; +} __PACKED; + +#define USB_SIZEOF_SETUP_PACKET 8 + +/** Standard Device Descriptor */ +struct usb_device_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 18 */ + uint8_t bDescriptorType; /* DEVICE descriptor type = 1 */ + uint16_t bcdUSB; /* USB spec in BCD, e.g. 0x0200 */ + uint8_t bDeviceClass; /* Class code, if 0 see interface */ + uint8_t bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bDeviceProtocol; /* Protocol, if 0 see interface */ + uint8_t bMaxPacketSize0; /* Endpoint 0 max. size */ + uint16_t idVendor; /* Vendor ID per USB-IF */ + uint16_t idProduct; /* Product ID per manufacturer */ + uint16_t bcdDevice; /* Device release # in BCD */ + uint8_t iManufacturer; /* Index to manufacturer string */ + uint8_t iProduct; /* Index to product string */ + uint8_t iSerialNumber; /* Index to serial number string */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} __PACKED; + +#define USB_SIZEOF_DEVICE_DESC 18 + +/** Standard Configuration Descriptor */ +struct usb_configuration_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 9 */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2 or 7 */ + uint16_t wTotalLength; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this config. */ + uint8_t bConfigurationValue; /* Value to set this config. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Config. characteristics */ + uint8_t bMaxPower; /* Max.power from bus, 2mA units */ +} __PACKED; + +#define USB_SIZEOF_CONFIG_DESC 9 + +/** Standard Interface Descriptor */ +struct usb_interface_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 9 */ + uint8_t bDescriptorType; /* INTERFACE descriptor type = 4 */ + uint8_t bInterfaceNumber; /* Interface no.*/ + uint8_t bAlternateSetting; /* Value to select this IF */ + uint8_t bNumEndpoints; /* Number of endpoints excluding 0 */ + uint8_t bInterfaceClass; /* Class code, 0xFF = vendor */ + uint8_t bInterfaceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bInterfaceProtocol; /* Protocol, 0xFF = vendor */ + uint8_t iInterface; /* Index to interface string */ +} __PACKED; + +#define USB_SIZEOF_INTERFACE_DESC 9 + +/** Standard Endpoint Descriptor */ +struct usb_endpoint_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 7 */ + uint8_t bDescriptorType; /* ENDPOINT descriptor type = 5 */ + uint8_t bEndpointAddress; /* Endpoint # 0 - 15 | IN/OUT */ + uint8_t bmAttributes; /* Transfer type */ + uint16_t wMaxPacketSize; /* Bits 10:0 = max. packet size */ + uint8_t bInterval; /* Polling interval in (micro) frames */ +} __PACKED; + +#define USB_SIZEOF_ENDPOINT_DESC 7 + +/** Unicode (UTF16LE) String Descriptor */ +struct usb_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString; +} __PACKED; + +#define USB_SIZEOF_STRING_LANGID_DESC 4 + +/* USB Interface Association Descriptor */ +struct usb_interface_association_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __PACKED; + +#define USB_SIZEOF_IAD_DESC 8 + +/** USB device_qualifier descriptor */ +struct usb_device_qualifier_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 10 */ + uint8_t bDescriptorType; /* DEVICE QUALIFIER type = 6 */ + uint16_t bcdUSB; /* USB spec in BCD, e.g. 0x0200 */ + uint8_t bDeviceClass; /* Class code, if 0 see interface */ + uint8_t bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bDeviceProtocol; /* Protocol, if 0 see interface */ + uint8_t bMaxPacketSize; /* Endpoint 0 max. size */ + uint8_t bNumConfigurations; /* Number of possible configurations */ + uint8_t bReserved; /* Reserved = 0 */ +} __PACKED; + +#define USB_SIZEOF_DEVICE_QUALIFIER_DESC 10 + +/* Microsoft OS function descriptor. + * This can be used to request a specific driver (such as WINUSB) to be + * loaded on Windows. Unlike other descriptors, it is requested by a special + * request USB_REQ_GETMSFTOSDESCRIPTOR. + * More details: + * https://msdn.microsoft.com/en-us/windows/hardware/gg463179 + * And excellent explanation: + * https://github.com/pbatard/libwdi/wiki/WCID-Devices + * + * The device will have exactly one "Extended Compat ID Feature Descriptor", + * which may contain multiple "Function Descriptors" associated with + * different interfaces. + */ + +/* MS OS 1.0 string descriptor */ +struct usb_msosv1_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bString[14]; + uint8_t bMS_VendorCode; /* Vendor Code, used for a control request */ + uint8_t bPad; /* Padding byte for VendorCode look as UTF16 */ +} __PACKED; + +/* MS OS 1.0 Header descriptor */ +struct usb_msosv1_compat_id_header_descriptor { + uint32_t dwLength; + uint16_t bcdVersion; + uint16_t wIndex; + uint8_t bCount; + uint8_t reserved[7]; +} __PACKED; + +/* MS OS 1.0 Function descriptor */ +struct usb_msosv1_comp_id_function_descriptor { + uint8_t bFirstInterfaceNumber; + uint8_t reserved1; + uint8_t compatibleID[8]; + uint8_t subCompatibleID[8]; + uint8_t reserved2[6]; +} __PACKED; + +#define usb_msosv1_comp_id_create(x) \ + struct usb_msosv1_comp_id { \ + struct usb_msosv1_compat_id_header_descriptor compat_id_header; \ + struct usb_msosv1_comp_id_function_descriptor compat_id_function[x]; \ + }; + +struct usb_msosv1_descriptor { + const uint8_t *string; + uint8_t vendor_code; + const uint8_t *compat_id; + const uint8_t **comp_id_property; +}; + +/* MS OS 2.0 Header descriptor */ +struct usb_msosv2_header_descriptor { + uint32_t dwLength; + uint16_t bcdVersion; + uint16_t wIndex; + uint8_t bCount; +} __PACKED; + +/*Microsoft OS 2.0 set header descriptor*/ +struct usb_msosv2_set_header_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint32_t dwWindowsVersion; + uint16_t wDescriptorSetTotalLength; +} __PACKED; + +/* Microsoft OS 2.0 compatibleID descriptor*/ +struct usb_msosv2_comp_id_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t compatibleID[8]; + uint8_t subCompatibleID[8]; +} __PACKED; + +/* MS OS 2.0 property descriptor */ +struct usb_msosv2_property_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint32_t dwPropertyDataType; + uint16_t wPropertyNameLength; + const char *bPropertyName; + uint32_t dwPropertyDataLength; + const char *bPropertyData; +}; + +/* Microsoft OS 2.0 subset function descriptor */ +struct usb_msosv2_subset_function_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t bFirstInterface; + uint8_t bReserved; + uint16_t wSubsetLength; +} __PACKED; + +struct usb_msosv2_descriptor { + const uint8_t *compat_id; + uint16_t compat_id_len; + uint8_t vendor_code; +}; + +/* BOS header Descriptor */ +struct usb_bos_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumDeviceCaps; +} __PACKED; + +/* BOS Capability platform Descriptor */ +struct usb_bos_capability_platform_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bReserved; + uint8_t PlatformCapabilityUUID[16]; +} __PACKED; + +/* BOS Capability MS OS Descriptors version 2 */ +struct usb_bos_capability_msosv2_descriptor { + uint32_t dwWindowsVersion; + uint16_t wMSOSDescriptorSetTotalLength; + uint8_t bVendorCode; + uint8_t bAltEnumCode; +} __PACKED; + +/* BOS Capability webusb */ +struct usb_bos_capability_webusb_descriptor { + uint16_t bcdVersion; + uint8_t bVendorCode; + uint8_t iLandingPage; +} __PACKED; + +/* BOS Capability extension Descriptor*/ +struct usb_bos_capability_extension_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint32_t bmAttributes; +} __PACKED; + +/* Microsoft OS 2.0 Platform Capability Descriptor +* See https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/ +* microsoft-defined-usb-descriptors +* Adapted from the source: +* https://github.com/sowbug/weblight/blob/master/firmware/webusb.c +* (BSD-2) Thanks http://janaxelson.com/files/ms_os_20_descriptors.c +*/ +struct usb_bos_capability_platform_msosv2_descriptor { + struct usb_bos_capability_platform_descriptor platform_msos; + struct usb_bos_capability_msosv2_descriptor data_msosv2; +} __PACKED; + +/* WebUSB Platform Capability Descriptor: +* https://wicg.github.io/webusb/#webusb-platform-capability-descriptor +*/ +struct usb_bos_capability_platform_webusb_descriptor { + struct usb_bos_capability_platform_descriptor platform_webusb; + struct usb_bos_capability_webusb_descriptor data_webusb; +} __PACKED; + +struct usb_webusb_url_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bScheme; + char URL[]; +} __PACKED; + +struct usb_webusb_url_ex_descriptor { + uint8_t vendor_code; + const uint8_t *string; + uint32_t string_len; +} __PACKED; + +struct usb_bos_descriptor { + const uint8_t *string; + uint32_t string_len; +}; + +/* USB Device Capability Descriptor */ +struct usb_device_capability_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; +} __PACKED; + +/** USB descriptor header */ +struct usb_desc_header { + uint8_t bLength; /**< descriptor length */ + uint8_t bDescriptorType; /**< descriptor type */ +}; +// clang-format off +#define USB_DEVICE_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, idVendor, idProduct, bcdDevice, bNumConfigurations) \ + 0x12, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE, /* bDescriptorType */ \ + WBVAL(bcdUSB), /* bcdUSB */ \ + bDeviceClass, /* bDeviceClass */ \ + bDeviceSubClass, /* bDeviceSubClass */ \ + bDeviceProtocol, /* bDeviceProtocol */ \ + 0x40, /* bMaxPacketSize */ \ + WBVAL(idVendor), /* idVendor */ \ + WBVAL(idProduct), /* idProduct */ \ + WBVAL(bcdDevice), /* bcdDevice */ \ + USB_STRING_MFC_INDEX, /* iManufacturer */ \ + USB_STRING_PRODUCT_INDEX, /* iProduct */ \ + USB_STRING_SERIAL_INDEX, /* iSerial */ \ + bNumConfigurations /* bNumConfigurations */ + +#define USB_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_CONFIGURATION, /* bDescriptorType */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + bNumInterfaces, /* bNumInterfaces */ \ + bConfigurationValue, /* bConfigurationValue */ \ + 0x00, /* iConfiguration */ \ + bmAttributes, /* bmAttributes */ \ + USB_CONFIG_POWER_MA(bMaxPower) /* bMaxPower */ + +#define USB_DEVICE_QUALIFIER_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, bNumConfigurations) \ + 0x0A, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, /* bDescriptorType */ \ + WBVAL(bcdUSB), /* bcdUSB */ \ + bDeviceClass, /* bDeviceClass */ \ + bDeviceSubClass, /* bDeviceSubClass */ \ + bDeviceProtocol, /* bDeviceProtocol */ \ + 0x40, /* bMaxPacketSize */ \ + bNumConfigurations, /* bNumConfigurations */ \ + 0x00 /* bReserved */ + +#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_OTHER_SPEED, /* bDescriptorType */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + bNumInterfaces, /* bNumInterfaces */ \ + bConfigurationValue, /* bConfigurationValue */ \ + 0x00, /* iConfiguration */ \ + bmAttributes, /* bmAttributes */ \ + USB_CONFIG_POWER_MA(bMaxPower) /* bMaxPower */ + +#define USB_INTERFACE_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bNumEndpoints, \ + bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, iInterface) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + bAlternateSetting, /* bAlternateSetting */ \ + bNumEndpoints, /* bNumEndpoints */ \ + bInterfaceClass, /* bInterfaceClass */ \ + bInterfaceSubClass, /* bInterfaceSubClass */ \ + bInterfaceProtocol, /* bInterfaceProtocol */ \ + iInterface /* iInterface */ + +#define USB_ENDPOINT_DESCRIPTOR_INIT(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + bInterval /* bInterval */ + +#define USB_IAD_INIT(bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol) \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + bInterfaceCount, /* bInterfaceCount */ \ + bFunctionClass, /* bFunctionClass */ \ + bFunctionSubClass, /* bFunctionSubClass */ \ + bFunctionProtocol, /* bFunctionProtocol */ \ + 0x00 /* iFunction */ + +#define USB_LANGID_INIT(id) \ + 0x04, /* bLength */ \ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ \ + WBVAL(id) /* wLangID0 */ +// clang-format on + +#endif /* USB_DEF_H */ diff --git a/components/drivers/usb/cherryusb/common/usb_errno.h b/components/drivers/usb/cherryusb/common/usb_errno.h new file mode 100644 index 00000000000..57f37c165df --- /dev/null +++ b/components/drivers/usb/cherryusb/common/usb_errno.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_ERRNO_H +#define USB_ERRNO_H + +#define USB_ERR_NOMEM 1 +#define USB_ERR_INVAL 2 +#define USB_ERR_NODEV 3 +#define USB_ERR_NOTCONN 4 +#define USB_ERR_NOTSUPP 5 +#define USB_ERR_BUSY 6 +#define USB_ERR_RANGE 7 +#define USB_ERR_STALL 8 +#define USB_ERR_BABBLE 9 +#define USB_ERR_NAK 10 +#define USB_ERR_DT 11 +#define USB_ERR_IO 12 +#define USB_ERR_SHUTDOWN 13 +#define USB_ERR_TIMEOUT 14 + +#endif /* USB_ERRNO_H */ diff --git a/components/drivers/usb/cherryusb/common/usb_hc.h b/components/drivers/usb/cherryusb/common/usb_hc.h new file mode 100644 index 00000000000..adfddbea771 --- /dev/null +++ b/components/drivers/usb/cherryusb/common/usb_hc.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HC_H +#define USB_HC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*usbh_complete_callback_t)(void *arg, int nbytes); + +struct usbh_bus; + +/** + * @brief USB Iso Configuration. + * + * Structure containing the USB Iso configuration. + */ +struct usbh_iso_frame_packet { + uint8_t *transfer_buffer; + uint32_t transfer_buffer_length; + uint32_t actual_length; + int errorcode; +}; + +/** + * @brief USB Urb Configuration. + * + * Structure containing the USB Urb configuration. + */ +struct usbh_urb { + void *hcpriv; + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *ep; + uint8_t data_toggle; + uint8_t interval; + struct usb_setup_packet *setup; + uint8_t *transfer_buffer; + uint32_t transfer_buffer_length; + int transfer_flags; + uint32_t actual_length; + uint32_t timeout; + int errorcode; + uint32_t num_of_iso_packets; + uint32_t start_frame; + usbh_complete_callback_t complete; + void *arg; +#if defined(__ICCARM__) || defined(__ICCRISCV__) || defined(__ICCRX__) + struct usbh_iso_frame_packet *iso_packet; +#else + struct usbh_iso_frame_packet iso_packet[0]; +#endif +}; + +/** + * @brief usb host controller hardware init. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_hc_init(struct usbh_bus *bus); + +/** + * @brief usb host controller hardware deinit. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_hc_deinit(struct usbh_bus *bus); + +/** + * @brief Get frame number. + * + * @return frame number. + */ +uint16_t usbh_get_frame_number(struct usbh_bus *bus); +/** + * @brief control roothub. + * + * @param setup setup request buffer. + * @param buf buf for reading response or write data. + * @return On success will return 0, and others indicate fail. + */ +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf); + +/** + * @brief Submit a usb transfer request to an endpoint. + * + * If timeout is not zero, this function will be in poll transfer mode, + * otherwise will be in async transfer mode. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int usbh_submit_urb(struct usbh_urb *urb); + +/** + * @brief Cancel a transfer request. + * + * This function will call When calls usbh_submit_urb and return -USB_ERR_TIMEOUT or -USB_ERR_SHUTDOWN. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int usbh_kill_urb(struct usbh_urb *urb); + +#ifdef __cplusplus +} +#endif + +#endif /* USB_HC_H */ diff --git a/components/drivers/usb/cherryusb/common/usb_list.h b/components/drivers/usb/cherryusb/common/usb_list.h new file mode 100644 index 00000000000..3078a1f24e7 --- /dev/null +++ b/components/drivers/usb/cherryusb/common/usb_list.h @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_LIST_H +#define USB_LIST_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * usb_container_of - return the member address of ptr, if the type of ptr is the + * struct type. + */ +#define usb_container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * Single List structure + */ +struct usb_slist_node { + struct usb_slist_node *next; /**< point to next node. */ +}; +typedef struct usb_slist_node usb_slist_t; /**< Type for single list. */ + +/** + * @brief initialize a single list + * + * @param l the single list to be initialized + */ +static inline void usb_slist_init(usb_slist_t *l) +{ + l->next = NULL; +} + +static inline void usb_slist_add_head(usb_slist_t *l, usb_slist_t *n) +{ + n->next = l->next; + l->next = n; +} + +static inline void usb_slist_add_tail(usb_slist_t *l, usb_slist_t *n) +{ + usb_slist_t *tmp = l; + + while (tmp->next) { + tmp = tmp->next; + } + + /* append the node to the tail */ + tmp->next = n; + n->next = NULL; +} + +static inline void usb_slist_insert(usb_slist_t *l, usb_slist_t *next, usb_slist_t *n) +{ + if (!next) { + usb_slist_add_tail(next, l); + return; + } + + while (l->next) { + if (l->next == next) { + l->next = n; + n->next = next; + } + + l = l->next; + } +} + +static inline usb_slist_t *usb_slist_remove(usb_slist_t *l, usb_slist_t *n) +{ + usb_slist_t *tmp = l; + /* remove slist head */ + while (tmp->next && tmp->next != n) { + tmp = tmp->next; + } + + /* remove node */ + if (tmp->next != (usb_slist_t *)0) { + tmp->next = tmp->next->next; + } + + return l; +} + +static inline unsigned int usb_slist_len(const usb_slist_t *l) +{ + unsigned int len = 0; + const usb_slist_t *list = l->next; + + while (list != NULL) { + list = list->next; + len++; + } + + return len; +} + +static inline unsigned int usb_slist_contains(usb_slist_t *l, usb_slist_t *n) +{ + while (l->next) { + if (l->next == n) { + return 0; + } + + l = l->next; + } + + return 1; +} + +static inline usb_slist_t *usb_slist_head(usb_slist_t *l) +{ + return l->next; +} + +static inline usb_slist_t *usb_slist_tail(usb_slist_t *l) +{ + while (l->next) { + l = l->next; + } + + return l; +} + +static inline usb_slist_t *usb_slist_next(usb_slist_t *n) +{ + return n->next; +} + +static inline int usb_slist_isempty(usb_slist_t *l) +{ + return l->next == NULL; +} + +/** + * @brief initialize a slist object + */ +#define USB_SLIST_OBJECT_INIT(object) \ + { \ + NULL \ + } + +/** + * @brief initialize a slist object + */ +#define USB_SLIST_DEFINE(slist) \ + usb_slist_t slist = { NULL } + +/** + * @brief get the struct for this single list node + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define usb_slist_entry(node, type, member) \ + usb_container_of(node, type, member) + +/** + * usb_slist_first_entry - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_first_entry(ptr, type, member) \ + usb_slist_entry((ptr)->next, type, member) + +/** + * usb_slist_tail_entry - get the tail element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_tail_entry(ptr, type, member) \ + usb_slist_entry(usb_slist_tail(ptr), type, member) + +/** + * usb_slist_first_entry_or_null - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_first_entry_or_null(ptr, type, member) \ + (usb_slist_isempty(ptr) ? NULL : usb_slist_first_entry(ptr, type, member)) + +/** + * usb_slist_for_each - iterate over a single list + * @pos: the usb_slist_t * to use as a loop cursor. + * @head: the head for your single list. + */ +#define usb_slist_for_each(pos, head) \ + for (pos = (head)->next; pos != NULL; pos = pos->next) + +#define usb_slist_for_each_safe(pos, next, head) \ + for (pos = (head)->next, next = pos->next; pos; \ + pos = next, next = pos->next) + +/** + * usb_slist_for_each_entry - iterate over single list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your single list. + * @member: the name of the list_struct within the struct. + */ +#define usb_slist_for_each_entry(pos, head, member) \ + for (pos = usb_slist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = usb_slist_entry(pos->member.next, typeof(*pos), member)) + +#define usb_slist_for_each_entry_safe(pos, n, head, member) \ + for (pos = usb_slist_entry((head)->next, typeof(*pos), member), \ + n = usb_slist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = n, n = usb_slist_entry(pos->member.next, typeof(*pos), member)) + +/** + * Double List structure + */ +struct usb_dlist_node { + struct usb_dlist_node *next; /**< point to next node. */ + struct usb_dlist_node *prev; /**< point to prev node. */ +}; +typedef struct usb_dlist_node usb_dlist_t; /**< Type for lists. */ + +/** + * @brief initialize a list + * + * @param l list to be initialized + */ +static inline void usb_dlist_init(usb_dlist_t *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * + * @param l list to insert it + * @param n new node to be inserted + */ +static inline void usb_dlist_insert_after(usb_dlist_t *l, usb_dlist_t *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * + * @param n new node to be inserted + * @param l list to insert it + */ +static inline void usb_dlist_insert_before(usb_dlist_t *l, usb_dlist_t *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_remove(usb_dlist_t *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_move_head(usb_dlist_t *l, usb_dlist_t *n) +{ + usb_dlist_remove(n); + usb_dlist_insert_after(l, n); +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_move_tail(usb_dlist_t *l, usb_dlist_t *n) +{ + usb_dlist_remove(n); + usb_dlist_insert_before(l, n); +} + +/** + * @brief tests whether a list is empty + * @param l the list to test. + */ +static inline int usb_dlist_isempty(const usb_dlist_t *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l the list to get. + */ +static inline unsigned int usb_dlist_len(const usb_dlist_t *l) +{ + unsigned int len = 0; + const usb_dlist_t *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief initialize a dlist object + */ +#define USB_DLIST_OBJECT_INIT(object) \ + { \ + &(object), &(object) \ + } +/** + * @brief initialize a dlist object + */ +#define USB_DLIST_DEFINE(list) \ + usb_dlist_t list = { &(list), &(list) } + +/** + * @brief get the struct for this entry + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define usb_dlist_entry(node, type, member) \ + usb_container_of(node, type, member) + +/** + * dlist_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define usb_dlist_first_entry(ptr, type, member) \ + usb_dlist_entry((ptr)->next, type, member) +/** + * dlist_first_entry_or_null - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define usb_dlist_first_entry_or_null(ptr, type, member) \ + (usb_dlist_isempty(ptr) ? NULL : usb_dlist_first_entry(ptr, type, member)) + +/** + * usb_dlist_for_each - iterate over a list + * @pos: the usb_dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define usb_dlist_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * usb_dlist_for_each_prev - iterate over a list + * @pos: the dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define usb_dlist_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * usb_dlist_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the dlist_t * to use as a loop cursor. + * @n: another dlist_t * to use as temporary storage + * @head: the head for your list. + */ +#define usb_dlist_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +#define usb_dlist_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; pos != (head); \ + pos = n, n = pos->prev) +/** + * usb_dlist_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry(pos, head, member) \ + for (pos = usb_dlist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = usb_dlist_entry(pos->member.next, typeof(*pos), member)) + +/** + * usb_usb_dlist_for_each_entry_reverse - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_reverse(pos, head, member) \ + for (pos = usb_dlist_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = usb_dlist_entry(pos->member.prev, typeof(*pos), member)) + +/** + * usb_usb_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_safe(pos, n, head, member) \ + for (pos = usb_dlist_entry((head)->next, typeof(*pos), member), \ + n = usb_dlist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = usb_dlist_entry(n->member.next, typeof(*n), member)) + +/** + * usb_usb_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = usb_dlist_entry((head)->prev, typeof(*pos), field), \ + n = usb_dlist_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = usb_dlist_entry(pos->member.prev, typeof(*pos), member)) + +#ifdef __cplusplus +} +#endif + +#endif /* USB_LIST_H */ diff --git a/components/drivers/usb/cherryusb/common/usb_log.h b/components/drivers/usb/cherryusb/common/usb_log.h new file mode 100644 index 00000000000..923e8006c7a --- /dev/null +++ b/components/drivers/usb/cherryusb/common/usb_log.h @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_LOG_H +#define USB_LOG_H + +#include + +/* DEBUG level */ +#define USB_DBG_ERROR 0 +#define USB_DBG_WARNING 1 +#define USB_DBG_INFO 2 +#define USB_DBG_LOG 3 + +#ifndef USB_DBG_TAG +#define USB_DBG_TAG "USB" +#endif +/* + * The color for terminal (foreground) + * BLACK 30 + * RED 31 + * GREEN 32 + * YELLOW 33 + * BLUE 34 + * PURPLE 35 + * CYAN 36 + * WHITE 37 + */ + +#ifdef CONFIG_USB_PRINTF_COLOR_ENABLE +#define _USB_DBG_COLOR(n) CONFIG_USB_PRINTF("\033[" #n "m") +#define _USB_DBG_LOG_HDR(lvl_name, color_n) \ + CONFIG_USB_PRINTF("\033[" #color_n "m[" lvl_name "/" USB_DBG_TAG "] ") +#define _USB_DBG_LOG_X_END \ + CONFIG_USB_PRINTF("\033[0m") +#else +#define _USB_DBG_COLOR(n) +#define _USB_DBG_LOG_HDR(lvl_name, color_n) \ + CONFIG_USB_PRINTF("[" lvl_name "/" USB_DBG_TAG "] ") +#define _USB_DBG_LOG_X_END +#endif + +#define usb_dbg_log_line(lvl, color_n, fmt, ...) \ + do { \ + _USB_DBG_LOG_HDR(lvl, color_n); \ + CONFIG_USB_PRINTF(fmt, ##__VA_ARGS__); \ + _USB_DBG_LOG_X_END; \ + } while (0) + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG) +#define USB_LOG_DBG(fmt, ...) usb_dbg_log_line("D", 0, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_DBG(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_INFO) +#define USB_LOG_INFO(fmt, ...) usb_dbg_log_line("I", 32, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_INFO(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_WARNING) +#define USB_LOG_WRN(fmt, ...) usb_dbg_log_line("W", 33, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_WRN(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_ERROR) +#define USB_LOG_ERR(fmt, ...) usb_dbg_log_line("E", 31, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_ERR(...) {} +#endif + +#define USB_LOG_RAW(...) CONFIG_USB_PRINTF(__VA_ARGS__) + +void usb_assert(const char *filename, int linenum); +#define USB_ASSERT(f) \ + do { \ + if (!(f)) \ + usb_assert(__FILE__, __LINE__); \ + } while (0) + +#endif /* USB_LOG_H */ diff --git a/components/drivers/usb/cherryusb/common/usb_osal.h b/components/drivers/usb/cherryusb/common/usb_osal.h new file mode 100644 index 00000000000..f487c48599a --- /dev/null +++ b/components/drivers/usb/cherryusb/common/usb_osal.h @@ -0,0 +1,61 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_OSAL_H +#define USB_OSAL_H + +#include +#include +#include + +#define USB_OSAL_WAITING_FOREVER (0xFFFFFFFFU) + +typedef void *usb_osal_thread_t; +typedef void *usb_osal_sem_t; +typedef void *usb_osal_mutex_t; +typedef void *usb_osal_mq_t; +typedef void (*usb_thread_entry_t)(void *argument); +typedef void (*usb_timer_handler_t)(void *argument); +struct usb_osal_timer { + usb_timer_handler_t handler; + void *argument; + bool is_period; + uint32_t ticks; + void *timer; +}; + +/* + * Task with smaller priority value indicates higher task priority +*/ +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args); +void usb_osal_thread_delete(usb_osal_thread_t thread); + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count); +void usb_osal_sem_delete(usb_osal_sem_t sem); +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout); +int usb_osal_sem_give(usb_osal_sem_t sem); +void usb_osal_sem_reset(usb_osal_sem_t sem); + +usb_osal_mutex_t usb_osal_mutex_create(void); +void usb_osal_mutex_delete(usb_osal_mutex_t mutex); +int usb_osal_mutex_take(usb_osal_mutex_t mutex); +int usb_osal_mutex_give(usb_osal_mutex_t mutex); + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs); +void usb_osal_mq_delete(usb_osal_mq_t mq); +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr); +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout); + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period); +void usb_osal_timer_delete(struct usb_osal_timer *timer); +void usb_osal_timer_start(struct usb_osal_timer *timer); +void usb_osal_timer_stop(struct usb_osal_timer *timer); + +size_t usb_osal_enter_critical_section(void); +void usb_osal_leave_critical_section(size_t flag); + +void usb_osal_msleep(uint32_t delay); + +#endif /* USB_OSAL_H */ diff --git a/components/drivers/usb/cherryusb/common/usb_util.h b/components/drivers/usb/cherryusb/common/usb_util.h new file mode 100644 index 00000000000..624cd9fcb30 --- /dev/null +++ b/components/drivers/usb/cherryusb/common/usb_util.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2022-2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_UTIL_H +#define USB_UTIL_H + +#if defined(__CC_ARM) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION __packed union +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__GNUC__) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__ICCARM__) || defined(__ICCRX__) || defined(__ICCRISCV__) +#ifndef __USED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __USED __attribute__((used)) +#else +#define __USED __root +#endif +#endif + +#ifndef __WEAK +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __WEAK __attribute__((weak)) +#else +#define __WEAK _Pragma("__weak") +#endif +#endif + +#ifndef __PACKED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED __packed +#endif +#endif + +#ifndef __PACKED_STRUCT +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_STRUCT __packed struct +#endif +#endif + +#ifndef __PACKED_UNION +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_UNION __packed union +#endif +#endif + +#ifndef __ALIGNED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __ALIGNED(x) __attribute__((aligned(x))) +#elif (__VER__ >= 7080000) +/* Needs IAR language extensions */ +#define __ALIGNED(x) __attribute__((aligned(x))) +#else +#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. +#define __ALIGNED(x) +#endif +#endif + +#endif + +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned(4))) +#endif + +#ifndef ARG_UNUSED +#define ARG_UNUSED(x) (void)(x) +#endif + +#ifndef LO_BYTE +#define LO_BYTE(x) ((uint8_t)(x & 0x00FF)) +#endif + +#ifndef HI_BYTE +#define HI_BYTE(x) ((uint8_t)((x & 0xFF00) >> 8)) +#endif + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef BCD +#define BCD(x) ((((x) / 10) << 4) | ((x) % 10)) +#endif + +#ifdef BIT +#undef BIT +#define BIT(n) (1UL << (n)) +#else +#define BIT(n) (1UL << (n)) +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) \ + ((int)((sizeof(array) / sizeof((array)[0])))) +#endif + +#ifndef BSWAP16 +#define BSWAP16(u16) (__builtin_bswap16(u16)) +#endif +#ifndef BSWAP32 +#define BSWAP32(u32) (__builtin_bswap32(u32)) +#endif + +#define GET_BE16(field) \ + (((uint16_t)(field)[0] << 8) | ((uint16_t)(field)[1])) + +#define GET_BE32(field) \ + (((uint32_t)(field)[0] << 24) | ((uint32_t)(field)[1] << 16) | ((uint32_t)(field)[2] << 8) | ((uint32_t)(field)[3] << 0)) + +#define SET_BE16(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 8); \ + (field)[1] = (uint8_t)((value) >> 0); \ + } while (0) + +#define SET_BE24(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 16); \ + (field)[1] = (uint8_t)((value) >> 8); \ + (field)[2] = (uint8_t)((value) >> 0); \ + } while (0) + +#define SET_BE32(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 24); \ + (field)[1] = (uint8_t)((value) >> 16); \ + (field)[2] = (uint8_t)((value) >> 8); \ + (field)[3] = (uint8_t)((value) >> 0); \ + } while (0) + +#define WBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF) +#define DBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF), ((x >> 16) & 0xFF), ((x >> 24) & 0xFF) + +#define PP_NARG(...) \ + PP_NARG_(__VA_ARGS__, PP_RSEQ_N()) +#define PP_NARG_(...) \ + PP_ARG_N(__VA_ARGS__) +#define PP_ARG_N( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ + _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ + _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ + _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ + _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ + _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ + _61, _62, _63, N, ...) N +#define PP_RSEQ_N() \ + 63, 62, 61, 60, \ + 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, \ + 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, \ + 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, \ + 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, \ + 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, \ + 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 + +#define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) + +#define USB_ALIGN_UP(size, align) (((size) + (align)-1) & ~((align)-1)) + +#endif /* USB_UTIL_H */ diff --git a/components/drivers/usb/cherryusb/core/usbd_core.c b/components/drivers/usb/cherryusb/core/usbd_core.c new file mode 100644 index 00000000000..375c123c8c9 --- /dev/null +++ b/components/drivers/usb/cherryusb/core/usbd_core.c @@ -0,0 +1,1306 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ + +/* config descriptor field offsets */ +#define CONF_DESC_wTotalLength 2 /** Total length offset */ +#define CONF_DESC_bConfigurationValue 5 /** Configuration value offset */ +#define CONF_DESC_bmAttributes 7 /** configuration characteristics */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +struct usbd_tx_rx_msg { + uint8_t ep; + uint8_t ep_mult; + uint16_t ep_mps; + uint32_t nbytes; + usbd_endpoint_callback cb; +}; + +USB_NOCACHE_RAM_SECTION struct usbd_core_priv { + /** Setup packet */ + USB_MEM_ALIGNX struct usb_setup_packet setup; + /** Pointer to data buffer */ + uint8_t *ep0_data_buf; + /** Remaining bytes in buffer */ + uint32_t ep0_data_buf_residue; + /** Total length of control transfer */ + uint32_t ep0_data_buf_len; + /** Zero length packet flag of control transfer */ + bool zlp_flag; + /** Pointer to registered descriptors */ +#ifdef CONFIG_USBDEV_ADVANCE_DESC + const struct usb_descriptor *descriptors; +#else + const uint8_t *descriptors; + struct usb_msosv1_descriptor *msosv1_desc; + struct usb_msosv2_descriptor *msosv2_desc; + struct usb_bos_descriptor *bos_desc; +#endif + /* Buffer used for storing standard, class and vendor request data */ + USB_MEM_ALIGNX uint8_t req_data[CONFIG_USBDEV_REQUEST_BUFFER_LEN]; + + /** Currently selected configuration */ + uint8_t configuration; +#ifdef CONFIG_USBDEV_ADVANCE_DESC + uint8_t speed; +#endif +#ifdef CONFIG_USBDEV_TEST_MODE + bool test_req; +#endif + struct usbd_interface *intf[8]; + uint8_t intf_offset; + + struct usbd_tx_rx_msg tx_msg[CONFIG_USBDEV_EP_NUM]; + struct usbd_tx_rx_msg rx_msg[CONFIG_USBDEV_EP_NUM]; + + void (*event_handler)(uint8_t busid, uint8_t event); +} g_usbd_core[CONFIG_USBDEV_MAX_BUS]; + +struct usbd_bus g_usbdev_bus[CONFIG_USBDEV_MAX_BUS]; + +static void usbd_class_event_notify_handler(uint8_t busid, uint8_t event, void *arg); + +static void usbd_print_setup(struct usb_setup_packet *setup) +{ + USB_LOG_INFO("Setup: " + "bmRequestType 0x%02x, bRequest 0x%02x, wValue 0x%04x, wIndex 0x%04x, wLength 0x%04x\r\n", + setup->bmRequestType, + setup->bRequest, + setup->wValue, + setup->wIndex, + setup->wLength); +} + +static bool is_device_configured(uint8_t busid) +{ + return (g_usbd_core[busid].configuration != 0); +} + +/** + * @brief configure and enable endpoint + * + * This function sets endpoint configuration according to one specified in USB + * endpoint descriptor and then enables it for data transfers. + * + * @param [in] ep Endpoint descriptor byte array + * + * @return true if successfully configured and enabled + */ +static bool usbd_set_endpoint(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + USB_LOG_INFO("Open ep:0x%02x type:%u mps:%u\r\n", + ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(ep->bmAttributes), + USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + + if (ep->bEndpointAddress & 0x80) { + g_usbd_core[busid].tx_msg[ep->bEndpointAddress & 0x7f].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_usbd_core[busid].tx_msg[ep->bEndpointAddress & 0x7f].ep_mult = USB_GET_MULT(ep->wMaxPacketSize); + } else { + g_usbd_core[busid].rx_msg[ep->bEndpointAddress & 0x7f].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_usbd_core[busid].rx_msg[ep->bEndpointAddress & 0x7f].ep_mult = USB_GET_MULT(ep->wMaxPacketSize); + } + + return usbd_ep_open(busid, ep) == 0 ? true : false; +} +/** + * @brief Disable endpoint for transferring data + * + * This function cancels transfers that are associated with endpoint and + * disabled endpoint itself. + * + * @param [in] ep Endpoint descriptor byte array + * + * @return true if successfully deconfigured and disabled + */ +static bool usbd_reset_endpoint(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + USB_LOG_INFO("Close ep:0x%02x type:%u\r\n", + ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(ep->bmAttributes)); + + return usbd_ep_close(busid, ep->bEndpointAddress) == 0 ? true : false; +} + +/** + * @brief get specified USB descriptor + * + * This function parses the list of installed USB descriptors and attempts + * to find the specified USB descriptor. + * + * @param [in] type_index Type and index of the descriptor + * @param [out] data Descriptor data + * @param [out] len Descriptor length + * + * @return true if the descriptor was found, false otherwise + */ +#ifdef CONFIG_USBDEV_ADVANCE_DESC +static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **data, uint32_t *len) +{ + uint8_t type = 0U; + uint8_t index = 0U; + bool found = true; + uint32_t desc_len = 0; + const char *string = NULL; + const uint8_t *desc = NULL; + + type = HI_BYTE(type_index); + index = LO_BYTE(type_index); + + switch (type) { + case USB_DESCRIPTOR_TYPE_DEVICE: + g_usbd_core[busid].speed = usbd_get_port_speed(busid); /* before we get device descriptor, we have known steady port speed */ + desc = g_usbd_core[busid].descriptors->device_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = desc[0]; + break; + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + desc = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = ((desc[CONF_DESC_wTotalLength]) | (desc[CONF_DESC_wTotalLength + 1] << 8)); + break; + case USB_DESCRIPTOR_TYPE_STRING: + if (index == USB_OSDESC_STRING_DESC_INDEX) { + USB_LOG_INFO("read MS OS 2.0 descriptor string\r\n"); + + if (!g_usbd_core[busid].descriptors->msosv1_descriptor) { + found = false; + break; + } + + desc = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->string; + desc_len = g_usbd_core[busid].descriptors->msosv1_descriptor->string[0]; + } else { + string = g_usbd_core[busid].descriptors->string_descriptor_callback(g_usbd_core[busid].speed, index); + if (string == NULL) { + found = false; + break; + } + + if (index == USB_STRING_LANGID_INDEX) { + (*data)[0] = 4; + (*data)[1] = USB_DESCRIPTOR_TYPE_STRING; + (*data)[2] = string[0]; + (*data)[3] = string[1]; + + *len = 4; + return true; + } + + uint16_t str_size = strlen(string); + uint16_t total_size = 2 * str_size + 2; + if (total_size > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + USB_LOG_ERR("string size overflow\r\n"); + return false; + } + + (*data)[0] = total_size; + (*data)[1] = USB_DESCRIPTOR_TYPE_STRING; + + for (uint16_t i = 0; i < str_size; i++) { + (*data)[2 * i + 2] = string[i]; + (*data)[2 * i + 3] = 0x00; + } + + *len = total_size; + return true; + } + break; + case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: +#ifndef CONFIG_USB_HS + return false; +#else + desc = g_usbd_core[busid].descriptors->device_quality_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = desc[0]; + break; +#endif + case USB_DESCRIPTOR_TYPE_OTHER_SPEED: + desc = g_usbd_core[busid].descriptors->other_speed_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = ((desc[CONF_DESC_wTotalLength]) | (desc[CONF_DESC_wTotalLength + 1] << 8)); + break; + + case USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE: + USB_LOG_INFO("read BOS descriptor string\r\n"); + + if (!g_usbd_core[busid].descriptors->bos_descriptor) { + found = false; + break; + } + + desc = (uint8_t *)g_usbd_core[busid].descriptors->bos_descriptor->string; + desc_len = g_usbd_core[busid].descriptors->bos_descriptor->string_len; + break; + + default: + found = false; + break; + } + + if (found == false) { + /* nothing found */ + USB_LOG_ERR("descriptor not found!\r\n", type, index); + } else { + *data = (uint8_t *)desc; + //memcpy(*data, desc, desc_len); + *len = desc_len; + } + return found; +} +#else +static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **data, uint32_t *len) +{ + uint8_t type = 0U; + uint8_t index = 0U; + uint8_t *p = NULL; + uint32_t cur_index = 0U; + bool found = false; + + type = HI_BYTE(type_index); + index = LO_BYTE(type_index); + + if ((type == USB_DESCRIPTOR_TYPE_STRING) && (index == USB_OSDESC_STRING_DESC_INDEX)) { + USB_LOG_INFO("read MS OS 2.0 descriptor string\r\n"); + + if (!g_usbd_core[busid].msosv1_desc) { + return false; + } + + *data = (uint8_t *)g_usbd_core[busid].msosv1_desc->string; + //memcpy(*data, (uint8_t *)g_usbd_core[busid].msosv1_desc->string, g_usbd_core[busid].msosv1_desc->string[0]); + *len = g_usbd_core[busid].msosv1_desc->string[0]; + + return true; + } else if (type == USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE) { + USB_LOG_INFO("read BOS descriptor string\r\n"); + + if (!g_usbd_core[busid].bos_desc) { + return false; + } + + *data = (uint8_t *)g_usbd_core[busid].bos_desc->string; + //memcpy(*data, (uint8_t *)g_usbd_core[busid].bos_desc->string, g_usbd_core[busid].bos_desc->string_len); + *len = g_usbd_core[busid].bos_desc->string_len; + return true; + } + /* + * Invalid types of descriptors, + * see USB Spec. Revision 2.0, 9.4.3 Get Descriptor + */ + else if ((type == USB_DESCRIPTOR_TYPE_INTERFACE) || (type == USB_DESCRIPTOR_TYPE_ENDPOINT) || +#ifndef CONFIG_USB_HS + (type > USB_DESCRIPTOR_TYPE_ENDPOINT)) { +#else + (type > USB_DESCRIPTOR_TYPE_OTHER_SPEED)) { +#endif + return false; + } + + p = (uint8_t *)g_usbd_core[busid].descriptors; + + cur_index = 0U; + + while (p[DESC_bLength] != 0U) { + if (p[DESC_bDescriptorType] == type) { + if (cur_index == index) { + found = true; + break; + } + + cur_index++; + } + + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + + if (found) { + if ((type == USB_DESCRIPTOR_TYPE_CONFIGURATION) || ((type == USB_DESCRIPTOR_TYPE_OTHER_SPEED))) { + /* configuration or other speed descriptor is an + * exception, length is at offset 2 and 3 + */ + *len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + } else { + /* normally length is at offset 0 */ + *len = p[DESC_bLength]; + } + *data = p; + //memcpy(*data, p, *len); + } else { + /* nothing found */ + USB_LOG_ERR("descriptor not found!\r\n", type, index); + } + + return found; +} +#endif + +/** + * @brief set USB configuration + * + * This function configures the device according to the specified configuration + * index and alternate setting by parsing the installed USB descriptor list. + * A configuration index of 0 unconfigures the device. + * + * @param [in] config_index Configuration index + * @param [in] alt_setting Alternate setting number + * + * @return true if successfully configured false if error or unconfigured + */ +static bool usbd_set_configuration(uint8_t busid, uint8_t config_index, uint8_t alt_setting) +{ + uint8_t cur_alt_setting = 0xFF; + uint8_t cur_config = 0xFF; + bool found = false; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + +#ifdef CONFIG_USBDEV_ADVANCE_DESC + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); +#else + p = (uint8_t *)g_usbd_core[busid].descriptors; +#endif + /* configure endpoints for this configuration/altsetting */ + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + /* remember current configuration index */ + cur_config = p[CONF_DESC_bConfigurationValue]; + + if (cur_config == config_index) { + found = true; + + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + } + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + /* remember current alternate setting */ + cur_alt_setting = + p[INTF_DESC_bAlternateSetting]; + break; + + case USB_DESCRIPTOR_TYPE_ENDPOINT: + if ((cur_config != config_index) || + (cur_alt_setting != alt_setting)) { + break; + } + + found = usbd_set_endpoint(busid, (struct usb_endpoint_descriptor *)p); + break; + + default: + break; + } + + /* skip to next descriptor */ + p += p[DESC_bLength]; + current_desc_len += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + + return found; +} + +/** + * @brief set USB interface + * + * @param [in] iface Interface index + * @param [in] alt_setting Alternate setting number + * + * @return true if successfully configured false if error or unconfigured + */ +static bool usbd_set_interface(uint8_t busid, uint8_t iface, uint8_t alt_setting) +{ + const uint8_t *if_desc = NULL; + struct usb_endpoint_descriptor *ep_desc; + uint8_t cur_alt_setting = 0xFF; + uint8_t cur_iface = 0xFF; + bool ret = false; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + +#ifdef CONFIG_USBDEV_ADVANCE_DESC + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); +#else + p = (uint8_t *)g_usbd_core[busid].descriptors; +#endif + USB_LOG_DBG("iface %u alt_setting %u\r\n", iface, alt_setting); + + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + /* remember current alternate setting */ + cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + cur_iface = p[INTF_DESC_bInterfaceNumber]; + + if (cur_iface == iface && + cur_alt_setting == alt_setting) { + if_desc = (void *)p; + } + + USB_LOG_DBG("Current iface %u alt setting %u", + cur_iface, cur_alt_setting); + break; + + case USB_DESCRIPTOR_TYPE_ENDPOINT: + if (cur_iface == iface) { + ep_desc = (struct usb_endpoint_descriptor *)p; + + if (cur_alt_setting != alt_setting) { + ret = usbd_reset_endpoint(busid, ep_desc); + } else { + ret = usbd_set_endpoint(busid, ep_desc); + } + } + + break; + + default: + break; + } + + /* skip to next descriptor */ + p += p[DESC_bLength]; + current_desc_len += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + + usbd_class_event_notify_handler(busid, USBD_EVENT_SET_INTERFACE, (void *)if_desc); + + return ret; +} + +/** + * @brief handle a standard device request + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_device_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint16_t value = setup->wValue; + bool ret = true; + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + /* bit 0: self-powered */ + /* bit 1: remote wakeup */ + (*data)[0] = 0x00; + (*data)[1] = 0x00; + *len = 2; + break; + + case USB_REQUEST_CLEAR_FEATURE: + case USB_REQUEST_SET_FEATURE: + if (value == USB_FEATURE_REMOTE_WAKEUP) { + if (setup->bRequest == USB_REQUEST_SET_FEATURE) { + g_usbd_core[busid].event_handler(busid, USBD_EVENT_SET_REMOTE_WAKEUP); + } else { + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CLR_REMOTE_WAKEUP); + } + } else if (value == USB_FEATURE_TEST_MODE) { +#ifdef CONFIG_USBDEV_TEST_MODE + g_usbd_core[busid].test_req = true; +#endif + } + *len = 0; + break; + + case USB_REQUEST_SET_ADDRESS: + usbd_set_address(busid, value); + *len = 0; + break; + + case USB_REQUEST_GET_DESCRIPTOR: + ret = usbd_get_descriptor(busid, value, data, len); + break; + + case USB_REQUEST_SET_DESCRIPTOR: + ret = false; + break; + + case USB_REQUEST_GET_CONFIGURATION: + *data = (uint8_t *)&g_usbd_core[busid].configuration; + *len = 1; + break; + + case USB_REQUEST_SET_CONFIGURATION: + value &= 0xFF; + + if (!usbd_set_configuration(busid, value, 0)) { + ret = false; + } else { + g_usbd_core[busid].configuration = value; + usbd_class_event_notify_handler(busid, USBD_EVENT_CONFIGURED, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CONFIGURED); + } + *len = 0; + break; + + case USB_REQUEST_GET_INTERFACE: + case USB_REQUEST_SET_INTERFACE: + ret = false; + break; + + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle a standard interface request + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_interface_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t type = HI_BYTE(setup->wValue); + uint8_t intf_num = LO_BYTE(setup->wIndex); + bool ret = true; + + /* Only when device is configured, then interface requests can be valid. */ + if (!is_device_configured(busid)) { + return false; + } + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + (*data)[0] = 0x00; + (*data)[1] = 0x00; + *len = 2; + break; + + case USB_REQUEST_GET_DESCRIPTOR: + if (type == 0x22) { /* HID_DESCRIPTOR_TYPE_HID_REPORT */ + USB_LOG_INFO("read hid report descriptor\r\n"); + + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && (intf->intf_num == intf_num)) { + *data = (uint8_t *)intf->hid_report_descriptor; + //memcpy(*data, intf->hid_report_descriptor, intf->hid_report_descriptor_len); + *len = intf->hid_report_descriptor_len; + return true; + } + } + } + ret = false; + break; + case USB_REQUEST_CLEAR_FEATURE: + case USB_REQUEST_SET_FEATURE: + ret = false; + break; + case USB_REQUEST_GET_INTERFACE: + (*data)[0] = 0; + *len = 1; + break; + + case USB_REQUEST_SET_INTERFACE: + usbd_set_interface(busid, setup->wIndex, setup->wValue); + *len = 0; + break; + + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle a standard endpoint request + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_endpoint_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t ep = (uint8_t)setup->wIndex; + bool ret = true; + + /* Only when device is configured, then endpoint requests can be valid. */ + if (!is_device_configured(busid)) { + return false; + } + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + (*data)[0] = 0x00; + (*data)[1] = 0x00; + *len = 2; + break; + case USB_REQUEST_CLEAR_FEATURE: + if (setup->wValue == USB_FEATURE_ENDPOINT_HALT) { + USB_LOG_ERR("ep:%02x clear halt\r\n", ep); + + usbd_ep_clear_stall(busid, ep); + break; + } else { + ret = false; + } + *len = 0; + break; + case USB_REQUEST_SET_FEATURE: + if (setup->wValue == USB_FEATURE_ENDPOINT_HALT) { + USB_LOG_ERR("ep:%02x set halt\r\n", ep); + + usbd_ep_set_stall(busid, ep); + } else { + ret = false; + } + *len = 0; + break; + + case USB_REQUEST_SYNCH_FRAME: + ret = false; + break; + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle standard requests (list in chapter 9) + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_standard_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + int rc = 0; + + switch (setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) { + case USB_REQUEST_RECIPIENT_DEVICE: + if (usbd_std_device_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + case USB_REQUEST_RECIPIENT_INTERFACE: + if (usbd_std_interface_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + case USB_REQUEST_RECIPIENT_ENDPOINT: + if (usbd_std_endpoint_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + default: + rc = -1; + break; + } + + return rc; +} + +/** + * @brief handler for class requests + * + * If a custom request handler was installed, this handler is called first. + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_class_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + if ((setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) == USB_REQUEST_RECIPIENT_INTERFACE) { + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->class_interface_handler && (intf->intf_num == (setup->wIndex & 0xFF))) { + return intf->class_interface_handler(busid, setup, data, len); + } + } + } else if ((setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) == USB_REQUEST_RECIPIENT_ENDPOINT) { + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->class_endpoint_handler) { + return intf->class_endpoint_handler(busid, setup, data, len); + } + } + } + return -1; +} + +/** + * @brief handler for vendor requests + * + * If a custom request handler was installed, this handler is called first. + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_vendor_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint32_t desclen; +#ifdef CONFIG_USBDEV_ADVANCE_DESC + if (g_usbd_core[busid].descriptors->msosv1_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->msosv1_descriptor->vendor_code) { + switch (setup->wIndex) { + case 0x04: + USB_LOG_INFO("get Compat ID\r\n"); + desclen = g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[0] + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[1] << 8) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[2] << 16) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[3] << 24); + + *data = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id; + //memcpy(*data, g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id, desclen); + *len = desclen; + return 0; + case 0x05: + USB_LOG_INFO("get Compat id properties\r\n"); + desclen = g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][0] + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][1] << 8) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][2] << 16) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][3] << 24); + + *data = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue]; + //memcpy(*data, g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue], desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } else if (g_usbd_core[busid].descriptors->msosv2_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->msosv2_descriptor->vendor_code) { + switch (setup->wIndex) { + case WINUSB_REQUEST_GET_DESCRIPTOR_SET: + USB_LOG_INFO("GET MS OS 2.0 Descriptor\r\n"); + + desclen = g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id_len; + *data = (uint8_t *)g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id; + //memcpy(*data, g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id, desclen); + *len = g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id_len; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } else if (g_usbd_core[busid].descriptors->webusb_url_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->webusb_url_descriptor->vendor_code) { + switch (setup->wIndex) { + case WINUSB_REQUEST_GET_DESCRIPTOR_SET: + USB_LOG_INFO("GET Webusb url Descriptor\r\n"); + + desclen = g_usbd_core[busid].descriptors->webusb_url_descriptor->string_len; + *data = (uint8_t *)g_usbd_core[busid].descriptors->webusb_url_descriptor->string; + //memcpy(*data, g_usbd_core[busid].descriptors->webusb_url_descriptor->string, desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } +#else + if (g_usbd_core[busid].msosv1_desc) { + if (setup->bRequest == g_usbd_core[busid].msosv1_desc->vendor_code) { + switch (setup->wIndex) { + case 0x04: + USB_LOG_INFO("get Compat ID\r\n"); + *data = (uint8_t *)g_usbd_core[busid].msosv1_desc->compat_id; + desclen = g_usbd_core[busid].msosv1_desc->compat_id[0] + + (g_usbd_core[busid].msosv1_desc->compat_id[1] << 8) + + (g_usbd_core[busid].msosv1_desc->compat_id[2] << 16) + + (g_usbd_core[busid].msosv1_desc->compat_id[3] << 24); + //memcpy(*data, g_usbd_core[busid].msosv1_desc->compat_id, desclen); + *len = desclen; + return 0; + case 0x05: + USB_LOG_INFO("get Compat id properties\r\n"); + *data = (uint8_t *)g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue]; + desclen = g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][0] + + (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][1] << 8) + + (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][2] << 16) + + (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][3] << 24); + //memcpy(*data, g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue], desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } else if (g_usbd_core[busid].msosv2_desc) { + if (setup->bRequest == g_usbd_core[busid].msosv2_desc->vendor_code) { + switch (setup->wIndex) { + case WINUSB_REQUEST_GET_DESCRIPTOR_SET: + USB_LOG_INFO("GET MS OS 2.0 Descriptor\r\n"); + *data = (uint8_t *)g_usbd_core[busid].msosv2_desc->compat_id; + //memcpy(*data, g_usbd_core[busid].msosv2_desc->compat_id, g_usbd_core[busid].msosv2_desc->compat_id_len); + *len = g_usbd_core[busid].msosv2_desc->compat_id_len; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } +#endif + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->vendor_handler && (intf->vendor_handler(busid, setup, data, len) == 0)) { + return 0; + } + } + + return -1; +} + +/** + * @brief handle setup request( standard/class/vendor/other) + * + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handles successfully + */ +static bool usbd_setup_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + switch (setup->bmRequestType & USB_REQUEST_TYPE_MASK) { + case USB_REQUEST_STANDARD: + if (usbd_standard_request_handler(busid, setup, data, len) < 0) { + /* Ignore error log for getting Device Qualifier Descriptor request */ + if ((setup->bRequest == 0x06) && (setup->wValue == 0x0600)) { + //USB_LOG_DBG("Ignore DQD in fs\r\n"); + return false; + } + USB_LOG_ERR("standard request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + case USB_REQUEST_CLASS: + if (usbd_class_request_handler(busid, setup, data, len) < 0) { + USB_LOG_ERR("class request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + case USB_REQUEST_VENDOR: + if (usbd_vendor_request_handler(busid, setup, data, len) < 0) { + USB_LOG_ERR("vendor request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + + default: + return false; + } + + return true; +} + +static void usbd_class_event_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (arg) { + struct usb_interface_descriptor *desc = (struct usb_interface_descriptor *)arg; + if (intf && intf->notify_handler && (desc->bInterfaceNumber == (intf->intf_num))) { + intf->notify_handler(busid, event, arg); + } + } else { + if (intf && intf->notify_handler) { + intf->notify_handler(busid, event, arg); + } + } + } +} + +void usbd_event_connect_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CONNECTED); +} + +void usbd_event_disconnect_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_DISCONNECTED); +} + +void usbd_event_resume_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_RESUME); +} + +void usbd_event_suspend_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_SUSPEND); +} + +void usbd_event_reset_handler(uint8_t busid) +{ + usbd_set_address(busid, 0); + g_usbd_core[busid].configuration = 0; +#ifdef CONFIG_USBDEV_ADVANCE_DESC + g_usbd_core[busid].speed = USB_SPEED_UNKNOWN; +#endif + struct usb_endpoint_descriptor ep0; + + ep0.bLength = 7; + ep0.bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT; + ep0.wMaxPacketSize = USB_CTRL_EP_MPS; + ep0.bmAttributes = USB_ENDPOINT_TYPE_CONTROL; + ep0.bEndpointAddress = USB_CONTROL_IN_EP0; + ep0.bInterval = 0; + usbd_ep_open(busid, &ep0); + + ep0.bEndpointAddress = USB_CONTROL_OUT_EP0; + usbd_ep_open(busid, &ep0); + + usbd_class_event_notify_handler(busid, USBD_EVENT_RESET, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_RESET); +} + +void usbd_event_ep0_setup_complete_handler(uint8_t busid, uint8_t *psetup) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + uint8_t *buf; + + memcpy(setup, psetup, 8); +#ifdef CONFIG_USBDEV_SETUP_LOG_PRINT + usbd_print_setup(setup); +#endif + if (setup->wLength > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + if ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT) { + USB_LOG_ERR("Request buffer too small\r\n"); + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + } + + g_usbd_core[busid].ep0_data_buf = g_usbd_core[busid].req_data; + g_usbd_core[busid].ep0_data_buf_residue = setup->wLength; + g_usbd_core[busid].ep0_data_buf_len = setup->wLength; + g_usbd_core[busid].zlp_flag = false; + buf = g_usbd_core[busid].ep0_data_buf; + + /* handle class request when all the data is received */ + if (setup->wLength && ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + USB_LOG_DBG("Start reading %d bytes from ep0\r\n", setup->wLength); + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, g_usbd_core[busid].ep0_data_buf, setup->wLength); + return; + } + + /* Ask installed handler to process request */ + if (!usbd_setup_request_handler(busid, setup, &buf, &g_usbd_core[busid].ep0_data_buf_len)) { + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + /* Send smallest of requested and offered length */ + g_usbd_core[busid].ep0_data_buf_residue = MIN(g_usbd_core[busid].ep0_data_buf_len, setup->wLength); + if (g_usbd_core[busid].ep0_data_buf_residue > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + USB_LOG_ERR("Request buffer too small\r\n"); + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + /* use *data = xxx; g_usbd_core[busid].ep0_data_buf records real data address, we should copy data into ep0 buffer. + * Why we should copy once? because some chips are not access to flash with dma if real data address is in flash address(such as ch32). + */ + if (buf != g_usbd_core[busid].ep0_data_buf) { +#ifdef CONFIG_USBDEV_EP0_INDATA_NO_COPY + g_usbd_core[busid].ep0_data_buf = buf; +#else + memcpy(g_usbd_core[busid].ep0_data_buf, buf, g_usbd_core[busid].ep0_data_buf_residue); +#endif + } else { + /* use memcpy(*data, xxx, len); has copied into ep0 buffer, we do nothing */ + } + + /* Send data or status to host */ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + /* + * Set ZLP flag when host asks for a bigger length and the data size is + * multiplier of USB_CTRL_EP_MPS, to indicate the transfer done after zlp + * sent. + */ + if ((setup->wLength > g_usbd_core[busid].ep0_data_buf_len) && (!(g_usbd_core[busid].ep0_data_buf_len % USB_CTRL_EP_MPS))) { + g_usbd_core[busid].zlp_flag = true; + USB_LOG_DBG("EP0 Set zlp\r\n"); + } +} + +void usbd_event_ep0_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + g_usbd_core[busid].ep0_data_buf += nbytes; + g_usbd_core[busid].ep0_data_buf_residue -= nbytes; + + USB_LOG_DBG("EP0 send %d bytes, %d remained\r\n", nbytes, g_usbd_core[busid].ep0_data_buf_residue); + + if (g_usbd_core[busid].ep0_data_buf_residue != 0) { + /* Start sending the remain data */ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + } else { + if (g_usbd_core[busid].zlp_flag == true) { + g_usbd_core[busid].zlp_flag = false; + /* Send zlp to host */ + USB_LOG_DBG("EP0 Send zlp\r\n"); + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, NULL, 0); + } else { + /* Satisfying three conditions will jump here. + * 1. send status completely + * 2. send zlp completely + * 3. send last data completely. + */ + if (setup->wLength && ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_IN)) { + /* if all data has sent completely, start reading out status */ + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, NULL, 0); + } + +#ifdef CONFIG_USBDEV_TEST_MODE + if (g_usbd_core[busid].test_req) { + usbd_execute_test_mode(busid, HI_BYTE(setup->wIndex)); + g_usbd_core[busid].test_req = false; + } +#endif + } + } +} + +void usbd_event_ep0_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + if (nbytes > 0) { + g_usbd_core[busid].ep0_data_buf += nbytes; + g_usbd_core[busid].ep0_data_buf_residue -= nbytes; + + USB_LOG_DBG("EP0 recv %d bytes, %d remained\r\n", nbytes, g_usbd_core[busid].ep0_data_buf_residue); + + if (g_usbd_core[busid].ep0_data_buf_residue == 0) { + /* Received all, send data to handler */ + g_usbd_core[busid].ep0_data_buf = g_usbd_core[busid].req_data; + if (!usbd_setup_request_handler(busid, setup, &g_usbd_core[busid].ep0_data_buf, &g_usbd_core[busid].ep0_data_buf_len)) { + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + /*Send status to host*/ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, NULL, 0); + } else { + /* Start reading the remain data */ + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + } + } else { + /* Read out status completely, do nothing */ + USB_LOG_DBG("EP0 recv out status\r\n"); + } +} + +void usbd_event_ep_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (g_usbd_core[busid].tx_msg[ep & 0x7f].cb) { + g_usbd_core[busid].tx_msg[ep & 0x7f].cb(busid, ep, nbytes); + } +} + +void usbd_event_ep_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (g_usbd_core[busid].rx_msg[ep & 0x7f].cb) { + g_usbd_core[busid].rx_msg[ep & 0x7f].cb(busid, ep, nbytes); + } +} + +#ifdef CONFIG_USBDEV_ADVANCE_DESC +void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc) +{ + memset(&g_usbd_core[busid], 0, sizeof(struct usbd_core_priv)); + + g_usbd_core[busid].descriptors = desc; + g_usbd_core[busid].intf_offset = 0; + + g_usbd_core[busid].tx_msg[0].ep = 0x80; + g_usbd_core[busid].tx_msg[0].cb = usbd_event_ep0_in_complete_handler; + g_usbd_core[busid].rx_msg[0].ep = 0x00; + g_usbd_core[busid].rx_msg[0].cb = usbd_event_ep0_out_complete_handler; +} +#else +void usbd_desc_register(uint8_t busid, const uint8_t *desc) +{ + memset(&g_usbd_core[busid], 0, sizeof(struct usbd_core_priv)); + + g_usbd_core[busid].descriptors = desc; + g_usbd_core[busid].intf_offset = 0; + + g_usbd_core[busid].tx_msg[0].ep = 0x80; + g_usbd_core[busid].tx_msg[0].cb = usbd_event_ep0_in_complete_handler; + g_usbd_core[busid].rx_msg[0].ep = 0x00; + g_usbd_core[busid].rx_msg[0].cb = usbd_event_ep0_out_complete_handler; +} + +/* Register MS OS Descriptors version 1 */ +void usbd_msosv1_desc_register(uint8_t busid, struct usb_msosv1_descriptor *desc) +{ + g_usbd_core[busid].msosv1_desc = desc; +} + +/* Register MS OS Descriptors version 2 */ +void usbd_msosv2_desc_register(uint8_t busid, struct usb_msosv2_descriptor *desc) +{ + g_usbd_core[busid].msosv2_desc = desc; +} + +void usbd_bos_desc_register(uint8_t busid, struct usb_bos_descriptor *desc) +{ + g_usbd_core[busid].bos_desc = desc; +} +#endif + +void usbd_add_interface(uint8_t busid, struct usbd_interface *intf) +{ + intf->intf_num = g_usbd_core[busid].intf_offset; + g_usbd_core[busid].intf[g_usbd_core[busid].intf_offset] = intf; + g_usbd_core[busid].intf_offset++; +} + +void usbd_add_endpoint(uint8_t busid, struct usbd_endpoint *ep) +{ + if (ep->ep_addr & 0x80) { + g_usbd_core[busid].tx_msg[ep->ep_addr & 0x7f].ep = ep->ep_addr; + g_usbd_core[busid].tx_msg[ep->ep_addr & 0x7f].cb = ep->ep_cb; + } else { + g_usbd_core[busid].rx_msg[ep->ep_addr & 0x7f].ep = ep->ep_addr; + g_usbd_core[busid].rx_msg[ep->ep_addr & 0x7f].cb = ep->ep_cb; + } +} + +uint16_t usbd_get_ep_mps(uint8_t busid, uint8_t ep) +{ + if (ep & 0x80) { + return g_usbd_core[busid].tx_msg[ep & 0x7f].ep_mps; + } else { + return g_usbd_core[busid].rx_msg[ep & 0x7f].ep_mps; + } +} + +uint8_t usbd_get_ep_mult(uint8_t busid, uint8_t ep) +{ + if (ep & 0x80) { + return g_usbd_core[busid].tx_msg[ep & 0x7f].ep_mult; + } else { + return g_usbd_core[busid].rx_msg[ep & 0x7f].ep_mult; + } +} + +bool usb_device_is_configured(uint8_t busid) +{ + return g_usbd_core[busid].configuration; +} + +int usbd_initialize(uint8_t busid, uint32_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)) +{ + int ret; + struct usbd_bus *bus; + + if (busid >= CONFIG_USBDEV_MAX_BUS) { + USB_LOG_ERR("bus overflow\r\n"); + while (1) { + } + } + + bus = &g_usbdev_bus[busid]; + bus->reg_base = reg_base; + + g_usbd_core[busid].event_handler = event_handler; + ret = usb_dc_init(busid); + usbd_class_event_notify_handler(busid, USBD_EVENT_INIT, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_INIT); + return ret; +} + +int usbd_deinitialize(uint8_t busid) +{ + g_usbd_core[busid].intf_offset = 0; + usb_dc_deinit(busid); + usbd_class_event_notify_handler(busid, USBD_EVENT_DEINIT, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_DEINIT); + return 0; +} diff --git a/components/drivers/usb/cherryusb/core/usbd_core.h b/components/drivers/usb/cherryusb/core/usbd_core.h new file mode 100644 index 00000000000..a1a943ecfe7 --- /dev/null +++ b/components/drivers/usb/cherryusb/core/usbd_core.h @@ -0,0 +1,111 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CORE_H +#define USBD_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#include "usb_config.h" +#include "usb_util.h" +#include "usb_errno.h" +#include "usb_def.h" +#include "usb_list.h" +#include "usb_log.h" +#include "usb_dc.h" + +enum usbd_event_type { + /* USB DCD IRQ */ + USBD_EVENT_ERROR, /** USB error reported by the controller */ + USBD_EVENT_RESET, /** USB reset */ + USBD_EVENT_SOF, /** Start of Frame received */ + USBD_EVENT_CONNECTED, /** USB connected*/ + USBD_EVENT_DISCONNECTED, /** USB disconnected */ + USBD_EVENT_SUSPEND, /** USB connection suspended by the HOST */ + USBD_EVENT_RESUME, /** USB connection resumed by the HOST */ + + /* USB DEVICE STATUS */ + USBD_EVENT_CONFIGURED, /** USB configuration done */ + USBD_EVENT_SET_INTERFACE, /** USB interface selected */ + USBD_EVENT_SET_REMOTE_WAKEUP, /** USB set remote wakeup */ + USBD_EVENT_CLR_REMOTE_WAKEUP, /** USB clear remote wakeup */ + USBD_EVENT_INIT, /** USB init done when call usbd_initialize */ + USBD_EVENT_DEINIT, /** USB deinit done when call usbd_deinitialize */ + USBD_EVENT_UNKNOWN +}; + +typedef int (*usbd_request_handler)(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len); +typedef void (*usbd_endpoint_callback)(uint8_t busid, uint8_t ep, uint32_t nbytes); +typedef void (*usbd_notify_handler)(uint8_t busid, uint8_t event, void *arg); + +struct usbd_endpoint { + uint8_t ep_addr; + usbd_endpoint_callback ep_cb; +}; + +struct usbd_interface { + usbd_request_handler class_interface_handler; + usbd_request_handler class_endpoint_handler; + usbd_request_handler vendor_handler; + usbd_notify_handler notify_handler; + const uint8_t *hid_report_descriptor; + uint32_t hid_report_descriptor_len; + uint8_t intf_num; +}; + +struct usb_descriptor { + const uint8_t *(*device_descriptor_callback)(uint8_t speed); + const uint8_t *(*config_descriptor_callback)(uint8_t speed); + const uint8_t *(*device_quality_descriptor_callback)(uint8_t speed); + const uint8_t *(*other_speed_descriptor_callback)(uint8_t speed); + const char *(*string_descriptor_callback)(uint8_t speed, uint8_t index); + const struct usb_msosv1_descriptor *msosv1_descriptor; + const struct usb_msosv2_descriptor *msosv2_descriptor; + const struct usb_webusb_url_ex_descriptor *webusb_url_descriptor; + const struct usb_bos_descriptor *bos_descriptor; +}; + +struct usbd_bus { + uint8_t busid; + uint32_t reg_base; +}; + +extern struct usbd_bus g_usbdev_bus[]; + +#ifdef USBD_IRQHandler +#error USBD_IRQHandler is obsolete, please call USBD_IRQHandler(xxx) in your irq +#endif + +#ifdef CONFIG_USBDEV_ADVANCE_DESC +void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc); +#else +void usbd_desc_register(uint8_t busid, const uint8_t *desc); +void usbd_msosv1_desc_register(uint8_t busid, struct usb_msosv1_descriptor *desc); +void usbd_msosv2_desc_register(uint8_t busid, struct usb_msosv2_descriptor *desc); +void usbd_bos_desc_register(uint8_t busid, struct usb_bos_descriptor *desc); +#endif + +void usbd_add_interface(uint8_t busid, struct usbd_interface *intf); +void usbd_add_endpoint(uint8_t busid, struct usbd_endpoint *ep); + +uint16_t usbd_get_ep_mps(uint8_t busid, uint8_t ep); +uint8_t usbd_get_ep_mult(uint8_t busid, uint8_t ep); +bool usb_device_is_configured(uint8_t busid); + +int usbd_initialize(uint8_t busid, uint32_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)); +int usbd_deinitialize(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CORE_H */ diff --git a/components/drivers/usb/cherryusb/core/usbh_core.c b/components/drivers/usb/cherryusb/core/usbh_core.c new file mode 100644 index 00000000000..cda801c33b8 --- /dev/null +++ b/components/drivers/usb/cherryusb/core/usbh_core.c @@ -0,0 +1,878 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbh_core" +#include "usb_log.h" + +struct usbh_class_info *usbh_class_info_table_begin = NULL; +struct usbh_class_info *usbh_class_info_table_end = NULL; + +usb_slist_t g_bus_head = USB_SLIST_OBJECT_INIT(g_bus_head); + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t ep0_request_buffer[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USBHOST_REQUEST_BUFFER_LEN, CONFIG_USB_ALIGN_SIZE)]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX struct usb_setup_packet g_setup_buffer[CONFIG_USBHOST_MAX_BUS][CONFIG_USBHOST_MAX_EXTHUBS + 1][CONFIG_USBHOST_MAX_EHPORTS]; + +struct usbh_bus g_usbhost_bus[CONFIG_USBHOST_MAX_BUS]; + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ + +#define USB_DEV_ADDR_MAX 0x7f +#define USB_DEV_ADDR_MARK_OFFSET 5 +#define USB_DEV_ADDR_MARK_MASK 0x1f + +static int usbh_allocate_devaddr(struct usbh_devaddr_map *devgen) +{ + uint8_t startaddr = devgen->next; + uint8_t devaddr; + int index; + int bitno; + + for (;;) { + devaddr = devgen->next; + if (devgen->next >= 0x7f) { + devgen->next = 2; + } else { + devgen->next++; + } + + index = devaddr >> 5; + bitno = devaddr & 0x1f; + if ((devgen->alloctab[index] & (1 << bitno)) == 0) { + devgen->alloctab[index] |= (1 << bitno); + return (int)devaddr; + } + + if (startaddr == devaddr) { + return -USB_ERR_NOMEM; + } + } +} + +static int __usbh_free_devaddr(struct usbh_devaddr_map *devgen, uint8_t devaddr) +{ + int index; + int bitno; + + if ((devaddr > 0) && (devaddr < USB_DEV_ADDR_MAX)) { + index = devaddr >> USB_DEV_ADDR_MARK_OFFSET; + bitno = devaddr & USB_DEV_ADDR_MARK_MASK; + + /* Free the address */ + if ((devgen->alloctab[index] |= (1 << bitno)) != 0) { + devgen->alloctab[index] &= ~(1 << bitno); + } else { + return -1; + } + + if (devaddr < devgen->next) { + devgen->next = devaddr; + } + } + + return 0; +} + +static int usbh_free_devaddr(struct usbh_hubport *hport) +{ +#ifndef CONFIG_USBHOST_XHCI + if (hport->dev_addr > 0) { + __usbh_free_devaddr(&hport->bus->devgen, hport->dev_addr); + } +#endif + + hport->dev_addr = 0; + return 0; +} + +static const struct usbh_class_driver *usbh_find_class_driver(uint8_t class, uint8_t subclass, uint8_t protocol, + uint16_t vid, uint16_t pid) +{ + struct usbh_class_info *index = NULL; + + for (index = usbh_class_info_table_begin; index < usbh_class_info_table_end; index++) { + if ((index->match_flags & USB_CLASS_MATCH_INTF_CLASS) && !(index->class == class)) { + continue; + } + if ((index->match_flags & USB_CLASS_MATCH_INTF_SUBCLASS) && !(index->subclass == subclass)) { + continue; + } + if ((index->match_flags & USB_CLASS_MATCH_INTF_PROTOCOL) && !(index->protocol == protocol)) { + continue; + } + if (index->match_flags & USB_CLASS_MATCH_VID_PID && index->id_table) { + /* scan id table */ + uint32_t i; + for (i = 0; index->id_table[i][0] && index->id_table[i][0] != vid && index->id_table[i][1] != pid; i++) { + } + /* do not match, continue next */ + if (!index->id_table[i][0]) { + continue; + } + } + return index->class_driver; + } + return NULL; +} + +static int parse_device_descriptor(struct usbh_hubport *hport, struct usb_device_descriptor *desc, uint16_t length) +{ + if (desc->bLength != USB_SIZEOF_DEVICE_DESC) { + USB_LOG_ERR("invalid device bLength 0x%02x\r\n", desc->bLength); + return -USB_ERR_INVAL; + } else if (desc->bDescriptorType != USB_DESCRIPTOR_TYPE_DEVICE) { + USB_LOG_ERR("unexpected device descriptor 0x%02x\r\n", desc->bDescriptorType); + return -USB_ERR_INVAL; + } else { + if (length <= 8) { + return 0; + } +#if 0 + USB_LOG_DBG("Device Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_DBG("bcdUSB: 0x%04x \r\n", desc->bcdUSB); + USB_LOG_DBG("bDeviceClass: 0x%02x \r\n", desc->bDeviceClass); + USB_LOG_DBG("bDeviceSubClass: 0x%02x \r\n", desc->bDeviceSubClass); + USB_LOG_DBG("bDeviceProtocol: 0x%02x \r\n", desc->bDeviceProtocol); + USB_LOG_DBG("bMaxPacketSize0: 0x%02x \r\n", desc->bMaxPacketSize0); + USB_LOG_DBG("idVendor: 0x%04x \r\n", desc->idVendor); + USB_LOG_DBG("idProduct: 0x%04x \r\n", desc->idProduct); + USB_LOG_DBG("bcdDevice: 0x%04x \r\n", desc->bcdDevice); + USB_LOG_DBG("iManufacturer: 0x%02x \r\n", desc->iManufacturer); + USB_LOG_DBG("iProduct: 0x%02x \r\n", desc->iProduct); + USB_LOG_DBG("iSerialNumber: 0x%02x \r\n", desc->iSerialNumber); + USB_LOG_DBG("bNumConfigurations: 0x%02x\r\n", desc->bNumConfigurations); +#endif + hport->device_desc.bLength = desc->bLength; + hport->device_desc.bDescriptorType = desc->bDescriptorType; + hport->device_desc.bcdUSB = desc->bcdUSB; + hport->device_desc.bDeviceClass = desc->bDeviceClass; + hport->device_desc.bDeviceSubClass = desc->bDeviceSubClass; + hport->device_desc.bDeviceProtocol = desc->bDeviceProtocol; + hport->device_desc.bMaxPacketSize0 = desc->bMaxPacketSize0; + hport->device_desc.idVendor = desc->idVendor; + hport->device_desc.idProduct = desc->idProduct; + hport->device_desc.bcdDevice = desc->bcdDevice; + hport->device_desc.iManufacturer = desc->iManufacturer; + hport->device_desc.iProduct = desc->iProduct; + hport->device_desc.iSerialNumber = desc->iSerialNumber; + hport->device_desc.bNumConfigurations = desc->bNumConfigurations; + } + return 0; +} + +static int parse_config_descriptor(struct usbh_hubport *hport, struct usb_configuration_descriptor *desc, uint16_t length) +{ + struct usb_interface_descriptor *intf_desc; + struct usb_endpoint_descriptor *ep_desc; + uint8_t cur_alt_setting = 0xff; + uint8_t cur_iface = 0xff; + uint8_t cur_ep = 0xff; + uint8_t cur_ep_num = 0xff; + uint32_t desc_len = 0; + uint8_t *p; + + if (desc->bLength != USB_SIZEOF_CONFIG_DESC) { + USB_LOG_ERR("invalid config bLength 0x%02x\r\n", desc->bLength); + return -USB_ERR_INVAL; + } else if (desc->bDescriptorType != USB_DESCRIPTOR_TYPE_CONFIGURATION) { + USB_LOG_ERR("unexpected config descriptor 0x%02x\r\n", desc->bDescriptorType); + return -USB_ERR_INVAL; + } else { + if (length <= USB_SIZEOF_CONFIG_DESC) { + return 0; + } +#if 0 + USB_LOG_DBG("Config Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", desc->bDescriptorType); + USB_LOG_DBG("wTotalLength: 0x%04x \r\n", desc->wTotalLength); + USB_LOG_DBG("bNumInterfaces: 0x%02x \r\n", desc->bNumInterfaces); + USB_LOG_DBG("bConfigurationValue: 0x%02x \r\n", desc->bConfigurationValue); + USB_LOG_DBG("iConfiguration: 0x%02x \r\n", desc->iConfiguration); + USB_LOG_DBG("bmAttributes: 0x%02x \r\n", desc->bmAttributes); + USB_LOG_DBG("bMaxPower: 0x%02x \r\n", desc->bMaxPower); +#endif + hport->config.config_desc.bLength = desc->bLength; + hport->config.config_desc.bDescriptorType = desc->bDescriptorType; + hport->config.config_desc.wTotalLength = desc->wTotalLength; + hport->config.config_desc.bNumInterfaces = desc->bNumInterfaces; + hport->config.config_desc.bConfigurationValue = desc->bConfigurationValue; + hport->config.config_desc.iConfiguration = desc->iConfiguration; + hport->config.config_desc.iConfiguration = desc->iConfiguration; + hport->config.config_desc.bmAttributes = desc->bmAttributes; + hport->config.config_desc.bMaxPower = desc->bMaxPower; + + p = (uint8_t *)desc; + p += USB_SIZEOF_CONFIG_DESC; + desc_len = USB_SIZEOF_CONFIG_DESC; + + memset(hport->config.intf, 0, sizeof(struct usbh_interface) * CONFIG_USBHOST_MAX_INTERFACES); + + while (p[DESC_bLength] && (desc_len <= length)) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_INTERFACE: + intf_desc = (struct usb_interface_descriptor *)p; + cur_iface = intf_desc->bInterfaceNumber; + cur_alt_setting = intf_desc->bAlternateSetting; + cur_ep_num = intf_desc->bNumEndpoints; + cur_ep = 0; + if (cur_iface > (CONFIG_USBHOST_MAX_INTERFACES - 1)) { + USB_LOG_ERR("Interface num overflow\r\n"); + while (1) { + } + } + if (cur_alt_setting > (CONFIG_USBHOST_MAX_INTF_ALTSETTINGS - 1)) { + USB_LOG_ERR("Interface altsetting num overflow\r\n"); + while (1) { + } + } + if (cur_ep_num > CONFIG_USBHOST_MAX_ENDPOINTS) { + USB_LOG_ERR("Endpoint num overflow\r\n"); + while (1) { + } + } +#if 0 + USB_LOG_DBG("Interface Descriptor:\r\n"); + USB_LOG_DBG("bLength: 0x%02x \r\n", intf_desc->bLength); + USB_LOG_DBG("bDescriptorType: 0x%02x \r\n", intf_desc->bDescriptorType); + USB_LOG_DBG("bInterfaceNumber: 0x%02x \r\n", intf_desc->bInterfaceNumber); + USB_LOG_DBG("bAlternateSetting: 0x%02x \r\n", intf_desc->bAlternateSetting); + USB_LOG_DBG("bNumEndpoints: 0x%02x \r\n", intf_desc->bNumEndpoints); + USB_LOG_DBG("bInterfaceClass: 0x%02x \r\n", intf_desc->bInterfaceClass); + USB_LOG_DBG("bInterfaceSubClass: 0x%02x \r\n", intf_desc->bInterfaceSubClass); + USB_LOG_DBG("bInterfaceProtocol: 0x%02x \r\n", intf_desc->bInterfaceProtocol); + USB_LOG_DBG("iInterface: 0x%02x \r\n", intf_desc->iInterface); +#endif + memcpy(&hport->config.intf[cur_iface].altsetting[cur_alt_setting].intf_desc, intf_desc, 9); + hport->config.intf[cur_iface].altsetting_num = cur_alt_setting + 1; + break; + case USB_DESCRIPTOR_TYPE_ENDPOINT: + ep_desc = (struct usb_endpoint_descriptor *)p; + memcpy(&hport->config.intf[cur_iface].altsetting[cur_alt_setting].ep[cur_ep].ep_desc, ep_desc, 7); + cur_ep++; + break; + + default: + break; + } + /* skip to next descriptor */ + p += p[DESC_bLength]; + desc_len += p[DESC_bLength]; + } + } + return 0; +} + +static void usbh_print_hubport_info(struct usbh_hubport *hport) +{ + USB_LOG_RAW("Device Descriptor:\r\n"); + USB_LOG_RAW("bLength: 0x%02x \r\n", hport->device_desc.bLength); + USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", hport->device_desc.bDescriptorType); + USB_LOG_RAW("bcdUSB: 0x%04x \r\n", hport->device_desc.bcdUSB); + USB_LOG_RAW("bDeviceClass: 0x%02x \r\n", hport->device_desc.bDeviceClass); + USB_LOG_RAW("bDeviceSubClass: 0x%02x \r\n", hport->device_desc.bDeviceSubClass); + USB_LOG_RAW("bDeviceProtocol: 0x%02x \r\n", hport->device_desc.bDeviceProtocol); + USB_LOG_RAW("bMaxPacketSize0: 0x%02x \r\n", hport->device_desc.bMaxPacketSize0); + USB_LOG_RAW("idVendor: 0x%04x \r\n", hport->device_desc.idVendor); + USB_LOG_RAW("idProduct: 0x%04x \r\n", hport->device_desc.idProduct); + USB_LOG_RAW("bcdDevice: 0x%04x \r\n", hport->device_desc.bcdDevice); + USB_LOG_RAW("iManufacturer: 0x%02x \r\n", hport->device_desc.iManufacturer); + USB_LOG_RAW("iProduct: 0x%02x \r\n", hport->device_desc.iProduct); + USB_LOG_RAW("iSerialNumber: 0x%02x \r\n", hport->device_desc.iSerialNumber); + USB_LOG_RAW("bNumConfigurations: 0x%02x\r\n", hport->device_desc.bNumConfigurations); + + USB_LOG_RAW("Config Descriptor:\r\n"); + USB_LOG_RAW("bLength: 0x%02x \r\n", hport->config.config_desc.bLength); + USB_LOG_RAW("bDescriptorType: 0x%02x \r\n", hport->config.config_desc.bDescriptorType); + USB_LOG_RAW("wTotalLength: 0x%04x \r\n", hport->config.config_desc.wTotalLength); + USB_LOG_RAW("bNumInterfaces: 0x%02x \r\n", hport->config.config_desc.bNumInterfaces); + USB_LOG_RAW("bConfigurationValue: 0x%02x \r\n", hport->config.config_desc.bConfigurationValue); + USB_LOG_RAW("iConfiguration: 0x%02x \r\n", hport->config.config_desc.iConfiguration); + USB_LOG_RAW("bmAttributes: 0x%02x \r\n", hport->config.config_desc.bmAttributes); + USB_LOG_RAW("bMaxPower: 0x%02x \r\n", hport->config.config_desc.bMaxPower); + + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + for (uint8_t j = 0; j < hport->config.intf[i].altsetting_num; j++) { + USB_LOG_RAW("\tInterface Descriptor:\r\n"); + USB_LOG_RAW("\tbLength: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bLength); + USB_LOG_RAW("\tbDescriptorType: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bDescriptorType); + USB_LOG_RAW("\tbInterfaceNumber: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceNumber); + USB_LOG_RAW("\tbAlternateSetting: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bAlternateSetting); + USB_LOG_RAW("\tbNumEndpoints: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bNumEndpoints); + USB_LOG_RAW("\tbInterfaceClass: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceClass); + USB_LOG_RAW("\tbInterfaceSubClass: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceSubClass); + USB_LOG_RAW("\tbInterfaceProtocol: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.bInterfaceProtocol); + USB_LOG_RAW("\tiInterface: 0x%02x \r\n", hport->config.intf[i].altsetting[j].intf_desc.iInterface); + + for (uint8_t k = 0; k < hport->config.intf[i].altsetting[j].intf_desc.bNumEndpoints; k++) { + USB_LOG_RAW("\t\tEndpoint Descriptor:\r\n"); + USB_LOG_RAW("\t\tbLength: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bLength); + USB_LOG_RAW("\t\tbDescriptorType: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bDescriptorType); + USB_LOG_RAW("\t\tbEndpointAddress: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bEndpointAddress); + USB_LOG_RAW("\t\tbmAttributes: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bmAttributes); + USB_LOG_RAW("\t\twMaxPacketSize: 0x%04x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.wMaxPacketSize); + USB_LOG_RAW("\t\tbInterval: 0x%02x \r\n", hport->config.intf[i].altsetting[j].ep[k].ep_desc.bInterval); + } + } + } +} + +static int usbh_get_default_mps(int speed) +{ + switch (speed) { + case USB_SPEED_LOW: /* For low speed, we use 8 bytes */ + return 8; + case USB_SPEED_FULL: /* For full or high speed, we use 64 bytes */ + case USB_SPEED_HIGH: + return 64; + case USB_SPEED_SUPER: /* For super speed , we must use 512 bytes */ + case USB_SPEED_SUPER_PLUS: + return 512; + default: + return 64; + } +} + +int usbh_enumerate(struct usbh_hubport *hport) +{ + struct usb_interface_descriptor *intf_desc; + struct usb_setup_packet *setup; + struct usb_device_descriptor *dev_desc; + struct usb_endpoint_descriptor *ep; + int dev_addr; + uint16_t ep_mps; + uint8_t config_value; + uint8_t config_index; + int ret; + + hport->setup = &g_setup_buffer[hport->bus->busid][hport->parent->index - 1][hport->port - 1]; + setup = hport->setup; + ep = &hport->ep0; + + /* Config EP0 mps from speed */ + ep->bEndpointAddress = 0x00; + ep->bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT; + ep->bmAttributes = USB_ENDPOINT_TYPE_CONTROL; + ep->wMaxPacketSize = usbh_get_default_mps(hport->speed); + ep->bInterval = 0; + ep->bLength = 7; + + /* Configure EP0 with zero address */ + hport->dev_addr = 0; + + /* Read the first 8 bytes of the device descriptor */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_DEVICE << 8) | 0); + setup->wIndex = 0; + setup->wLength = 8; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0) { + USB_LOG_ERR("Failed to get device descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + parse_device_descriptor(hport, (struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid], 8); + + /* Extract the correct max packetsize from the device descriptor */ + dev_desc = (struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid]; + if (dev_desc->bcdUSB >= USB_3_0) { + ep_mps = 1 << dev_desc->bMaxPacketSize0; + } else { + ep_mps = dev_desc->bMaxPacketSize0; + } + + USB_LOG_DBG("Device rev=%04x cls=%02x sub=%02x proto=%02x size=%d\r\n", + dev_desc->bcdUSB, dev_desc->bDeviceClass, dev_desc->bDeviceSubClass, + dev_desc->bDeviceProtocol, ep_mps); + + /* Reconfigure EP0 with the correct maximum packet size */ + ep->wMaxPacketSize = ep_mps; + +#ifdef CONFIG_USBHOST_XHCI + extern int usbh_get_xhci_devaddr(usbh_pipe_t * pipe); + + /* Assign a function address to the device connected to this port */ + dev_addr = usbh_get_xhci_devaddr(hport->ep0); + if (dev_addr < 0) { + USB_LOG_ERR("Failed to allocate devaddr,errorcode:%d\r\n", ret); + goto errout; + } +#else + /* Assign a function address to the device connected to this port */ + dev_addr = usbh_allocate_devaddr(&hport->bus->devgen); + if (dev_addr < 0) { + USB_LOG_ERR("Failed to allocate devaddr,errorcode:%d\r\n", ret); + goto errout; + } +#endif + + /* Set the USB device address */ + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_SET_ADDRESS; + setup->wValue = dev_addr; + setup->wIndex = 0; + setup->wLength = 0; + + ret = usbh_control_transfer(hport, setup, NULL); + if (ret < 0) { + USB_LOG_ERR("Failed to set devaddr,errorcode:%d\r\n", ret); + goto errout; + } + + /* Wait device set address completely */ + usb_osal_msleep(2); + + /*Reconfigure EP0 with the correct address */ + hport->dev_addr = dev_addr; + + /* Read the full device descriptor */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_DEVICE << 8) | 0); + setup->wIndex = 0; + setup->wLength = USB_SIZEOF_DEVICE_DESC; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0) { + USB_LOG_ERR("Failed to get full device descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + parse_device_descriptor(hport, (struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid], USB_SIZEOF_DEVICE_DESC); + USB_LOG_INFO("New device found,idVendor:%04x,idProduct:%04x,bcdDevice:%04x\r\n", + ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->idVendor, + ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->idProduct, + ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->bcdDevice); + + USB_LOG_INFO("The device has %d bNumConfigurations\r\n", ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->bNumConfigurations); + + config_index = 0; + USB_LOG_DBG("The device selects config %d\r\n", config_index); + + /* Read the first 9 bytes of the config descriptor */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_CONFIGURATION << 8) | config_index); + setup->wIndex = 0; + setup->wLength = USB_SIZEOF_CONFIG_DESC; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0) { + USB_LOG_ERR("Failed to get config descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + parse_config_descriptor(hport, (struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid], USB_SIZEOF_CONFIG_DESC); + + /* Read the full size of the configuration data */ + uint16_t wTotalLength = ((struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid])->wTotalLength; + + if (wTotalLength > CONFIG_USBHOST_REQUEST_BUFFER_LEN) { + ret = -USB_ERR_NOMEM; + USB_LOG_ERR("wTotalLength %d is overflow, default is %d\r\n", wTotalLength, CONFIG_USBHOST_REQUEST_BUFFER_LEN); + goto errout; + } + + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_CONFIGURATION << 8) | config_index); + setup->wIndex = 0; + setup->wLength = wTotalLength; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0) { + USB_LOG_ERR("Failed to get full config descriptor,errorcode:%d\r\n", ret); + goto errout; + } + + ret = parse_config_descriptor(hport, (struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid], wTotalLength); + if (ret < 0) { + USB_LOG_ERR("Parse config fail\r\n"); + goto errout; + } + USB_LOG_INFO("The device has %d interfaces\r\n", ((struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid])->bNumInterfaces); + hport->raw_config_desc = usb_malloc(wTotalLength); + if (hport->raw_config_desc == NULL) { + ret = -USB_ERR_NOMEM; + USB_LOG_ERR("No memory to alloc for raw_config_desc\r\n"); + goto errout; + } + + config_value = ((struct usb_configuration_descriptor *)ep0_request_buffer[hport->bus->busid])->bConfigurationValue; + memcpy(hport->raw_config_desc, ep0_request_buffer[hport->bus->busid], wTotalLength); +#ifdef CONFIG_USBHOST_GET_STRING_DESC + uint8_t string_buffer[128]; + + /* Get Manufacturer string */ + memset(string_buffer, 0, 128); + ret = usbh_get_string_desc(hport, USB_STRING_MFC_INDEX, string_buffer); + if (ret < 0) { + USB_LOG_ERR("Failed to get Manufacturer string,errorcode:%d\r\n", ret); + goto errout; + } + + USB_LOG_INFO("Manufacturer: %s\r\n", string_buffer); + + /* Get Product string */ + memset(string_buffer, 0, 128); + ret = usbh_get_string_desc(hport, USB_STRING_PRODUCT_INDEX, string_buffer); + if (ret < 0) { + USB_LOG_ERR("Failed to get get Product string,errorcode:%d\r\n", ret); + goto errout; + } + + USB_LOG_INFO("Product: %s\r\n", string_buffer); + + /* Get SerialNumber string */ + memset(string_buffer, 0, 128); + ret = usbh_get_string_desc(hport, USB_STRING_SERIAL_INDEX, string_buffer); + if (ret < 0) { + USB_LOG_ERR("Failed to get get SerialNumber string,errorcode:%d\r\n", ret); + goto errout; + } + + USB_LOG_INFO("SerialNumber: %s\r\n", string_buffer); +#endif + /* Select device configuration 1 */ + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_SET_CONFIGURATION; + setup->wValue = config_value; + setup->wIndex = 0; + setup->wLength = 0; + + ret = usbh_control_transfer(hport, setup, NULL); + if (ret < 0) { + USB_LOG_ERR("Failed to set configuration,errorcode:%d\r\n", ret); + goto errout; + } + +#ifdef CONFIG_USBHOST_MSOS_ENABLE + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = CONFIG_USBHOST_MSOS_VENDOR_CODE; + setup->wValue = 0; + setup->wIndex = 0x0004; + setup->wLength = 16; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0 && (ret != -EPERM)) { + USB_LOG_ERR("Failed to get msosv1 compat id,errorcode:%d\r\n", ret); + goto errout; + } +#endif + USB_LOG_INFO("Enumeration success, start loading class driver\r\n"); + /*search supported class driver*/ + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + intf_desc = &hport->config.intf[i].altsetting[0].intf_desc; + + struct usbh_class_driver *class_driver = (struct usbh_class_driver *)usbh_find_class_driver(intf_desc->bInterfaceClass, intf_desc->bInterfaceSubClass, intf_desc->bInterfaceProtocol, hport->device_desc.idVendor, hport->device_desc.idProduct); + + if (class_driver == NULL) { + USB_LOG_ERR("do not support Class:0x%02x,Subclass:0x%02x,Protocl:0x%02x\r\n", + intf_desc->bInterfaceClass, + intf_desc->bInterfaceSubClass, + intf_desc->bInterfaceProtocol); + + continue; + } + hport->config.intf[i].class_driver = class_driver; + USB_LOG_INFO("Loading %s class driver\r\n", class_driver->driver_name); + ret = CLASS_CONNECT(hport, i); + } + +errout: + if (hport->raw_config_desc) { + usb_free(hport->raw_config_desc); + hport->raw_config_desc = NULL; + } + return ret; +} + +void usbh_hubport_release(struct usbh_hubport *hport) +{ + if (hport->connected) { + hport->connected = false; + usbh_free_devaddr(hport); + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + if (hport->config.intf[i].class_driver && hport->config.intf[i].class_driver->disconnect) { + CLASS_DISCONNECT(hport, i); + } + } + hport->config.config_desc.bNumInterfaces = 0; + usbh_kill_urb(&hport->ep0_urb); + if (hport->mutex) { + usb_osal_mutex_delete(hport->mutex); + } + } +} + +static void usbh_bus_init(struct usbh_bus *bus, uint8_t busid, uint32_t reg_base) +{ + struct usbh_hub *hub; + + memset(bus, 0, sizeof(struct usbh_bus)); + bus->busid = busid; + bus->hcd.hcd_id = busid; + bus->hcd.reg_base = reg_base; + + /* devaddr 1 is for roothub */ + bus->devgen.next = 2; + + usb_slist_init(&bus->hub_list); + + hub = &bus->hcd.roothub; + hub->connected = true; + hub->index = 1; + hub->is_roothub = true; + hub->parent = NULL; + hub->hub_addr = 1; + hub->hub_desc.bNbrPorts = CONFIG_USBHOST_MAX_RHPORTS; + hub->int_buffer = bus->hcd.roothub_intbuf; + hub->bus = bus; + + usb_slist_init(&bus->hub_list); + usb_slist_add_tail(&bus->hub_list, &hub->list); + usb_slist_add_tail(&g_bus_head, &bus->list); +} + +int usbh_initialize(uint8_t busid, uint32_t reg_base) +{ + struct usbh_bus *bus; + + if (busid >= CONFIG_USBHOST_MAX_BUS) { + USB_LOG_ERR("bus overflow\r\n"); + while (1) { + } + } + + bus = &g_usbhost_bus[busid]; + + usbh_bus_init(bus, busid, reg_base); + +#ifdef __ARMCC_VERSION /* ARM C Compiler */ + extern const int usbh_class_info$$Base; + extern const int usbh_class_info$$Limit; + usbh_class_info_table_begin = (struct usbh_class_info *)&usbh_class_info$$Base; + usbh_class_info_table_end = (struct usbh_class_info *)&usbh_class_info$$Limit; +#elif defined(__GNUC__) + extern uint32_t __usbh_class_info_start__; + extern uint32_t __usbh_class_info_end__; + usbh_class_info_table_begin = (struct usbh_class_info *)&__usbh_class_info_start__; + usbh_class_info_table_end = (struct usbh_class_info *)&__usbh_class_info_end__; +#elif defined(__ICCARM__) || defined(__ICCRX__) || defined(__ICCRISCV__) + usbh_class_info_table_begin = (struct usbh_class_info *)__section_begin(".usbh_class_info"); + usbh_class_info_table_end = (struct usbh_class_info *)__section_end(".usbh_class_info"); +#endif + usbh_hub_initialize(bus); + return 0; +} + +int usbh_deinitialize(uint8_t busid) +{ + struct usbh_bus *bus; + + bus = &g_usbhost_bus[busid]; + + usbh_hub_deinitialize(bus); + + usb_slist_init(&bus->hub_list); + usb_slist_remove(&g_bus_head, &bus->list); + + return 0; +} + +int usbh_control_transfer(struct usbh_hubport *hport, struct usb_setup_packet *setup, uint8_t *buffer) +{ + struct usbh_urb *urb; + int ret; + + urb = &hport->ep0_urb; + + usb_osal_mutex_take(hport->mutex); + + usbh_control_urb_fill(urb, hport, setup, buffer, setup->wLength, CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT, NULL, NULL); + ret = usbh_submit_urb(urb); + if (ret == 0) { + ret = urb->actual_length; + } + + usb_osal_mutex_give(hport->mutex); + return ret; +} + +int usbh_get_string_desc(struct usbh_hubport *hport, uint8_t index, uint8_t *output) +{ + struct usb_setup_packet *setup = hport->setup; + int ret; + uint8_t *src; + uint8_t *dst; + uint16_t len; + uint16_t i = 2; + uint16_t j = 0; + + /* Get Manufacturer string */ + setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_DEVICE; + setup->bRequest = USB_REQUEST_GET_DESCRIPTOR; + setup->wValue = (uint16_t)((USB_DESCRIPTOR_TYPE_STRING << 8) | index); + setup->wIndex = 0x0409; + setup->wLength = 255; + + ret = usbh_control_transfer(hport, setup, ep0_request_buffer[hport->bus->busid]); + if (ret < 0) { + return ret; + } + + src = ep0_request_buffer[hport->bus->busid]; + dst = output; + len = src[0]; + + while (i < len) { + dst[j] = src[i]; + i += 2; + j++; + } + + return 0; +} + +int usbh_set_interface(struct usbh_hubport *hport, uint8_t intf, uint8_t altsetting) +{ + struct usb_setup_packet *setup = hport->setup; + + setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_STANDARD | USB_REQUEST_RECIPIENT_INTERFACE; + setup->bRequest = USB_REQUEST_SET_INTERFACE; + setup->wValue = altsetting; + setup->wIndex = intf; + setup->wLength = 0; + + return usbh_control_transfer(hport, setup, NULL); +} + +void *usbh_find_class_instance(const char *devname) +{ + struct usbh_hubport *hport; + usb_slist_t *hub_list; + usb_slist_t *bus_list; + + usb_slist_for_each(bus_list, &g_bus_head) + { + struct usbh_bus *bus = usb_slist_entry(bus_list, struct usbh_bus, list); + usb_slist_for_each(hub_list, &bus->hub_list) + { + struct usbh_hub *hub = usb_slist_entry(hub_list, struct usbh_hub, list); + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + hport = &hub->child[port]; + if (hport->connected) { + for (uint8_t itf = 0; itf < hport->config.config_desc.bNumInterfaces; itf++) { + if ((strncmp(hport->config.intf[itf].devname, devname, CONFIG_USBHOST_DEV_NAMELEN) == 0) && hport->config.intf[itf].priv) + return hport->config.intf[itf].priv; + } + } + } + } + } + return NULL; +} + +int lsusb(int argc, char **argv) +{ + usb_slist_t *hub_list; + usb_slist_t *bus_list; + struct usbh_hubport *hport; + + if (argc < 2) { + USB_LOG_RAW("Usage: lsusb [options]...\r\n"); + USB_LOG_RAW("List USB devices\r\n"); + USB_LOG_RAW(" -v, --verbose\r\n"); + USB_LOG_RAW(" Increase verbosity (show descriptors)\r\n"); + // USB_LOG_RAW(" -s [[bus]:[devnum]]\r\n"); + // USB_LOG_RAW(" Show only devices with specified device and/or bus numbers (in decimal)\r\n"); + // USB_LOG_RAW(" -d vendor:[product]\r\n"); + // USB_LOG_RAW(" Show only devices with the specified vendor and product ID numbers (in hexadecimal)\r\n"); + USB_LOG_RAW(" -t, --tree\r\n"); + USB_LOG_RAW(" Dump the physical USB device hierachy as a tree\r\n"); + USB_LOG_RAW(" -V, --version\r\n"); + USB_LOG_RAW(" Show version of program\r\n"); + USB_LOG_RAW(" -h, --help\r\n"); + USB_LOG_RAW(" Show usage and help\r\n"); + return 0; + } + if (argc > 3) { + return 0; + } + + if (strcmp(argv[1], "-t") == 0) { + usb_slist_for_each(bus_list, &g_bus_head) + { + struct usbh_bus *bus = usb_slist_entry(bus_list, struct usbh_bus, list); + usb_slist_for_each(hub_list, &bus->hub_list) + { + struct usbh_hub *hub = usb_slist_entry(hub_list, struct usbh_hub, list); + + if (hub->is_roothub) { + USB_LOG_RAW("/: Bus %u, Hub %u, ports=%u, is roothub\r\n", + bus->busid, + hub->index, + hub->hub_desc.bNbrPorts); + } else { + USB_LOG_RAW("/: Bus %u, Hub %u, ports=%u, mounted on Hub %02u:Port %u\r\n", + bus->busid, + hub->index, + hub->hub_desc.bNbrPorts, + hub->parent->parent->index, + hub->parent->port); + } + + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + hport = &hub->child[port]; + if (hport->connected) { + for (uint8_t i = 0; i < hport->config.config_desc.bNumInterfaces; i++) { + if (hport->config.intf[i].class_driver && hport->config.intf[i].class_driver->driver_name) { + USB_LOG_RAW("\t|__Port %u, dev addr:0x%02x, If %u, ClassDriver=%s\r\n", + hport->port, + hport->dev_addr, + i, + hport->config.intf[i].class_driver->driver_name); + } + } + } + } + } + } + } + + if (strcmp(argv[1], "-v") == 0) { + usb_slist_for_each(bus_list, &g_bus_head) + { + struct usbh_bus *bus = usb_slist_entry(bus_list, struct usbh_bus, list); + usb_slist_for_each(hub_list, &bus->hub_list) + { + struct usbh_hub *hub = usb_slist_entry(hub_list, struct usbh_hub, list); + for (uint8_t port = 0; port < hub->hub_desc.bNbrPorts; port++) { + hport = &hub->child[port]; + if (hport->connected) { + USB_LOG_RAW("Bus %u, Hub %02u, Port %u, dev addr:0x%02x, VID:PID 0x%04x:0x%04x\r\n", + bus->busid, + hub->index, + hport->port, + hport->dev_addr, + hport->device_desc.idVendor, + hport->device_desc.idProduct); + usbh_print_hubport_info(hport); + } + } + } + } + } + + return 0; +} diff --git a/components/drivers/usb/cherryusb/core/usbh_core.h b/components/drivers/usb/cherryusb/core/usbh_core.h new file mode 100644 index 00000000000..9ce081fc5de --- /dev/null +++ b/components/drivers/usb/cherryusb/core/usbh_core.h @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBH_CORE_H +#define USBH_CORE_H + +#include +#include +#include +#include + +#include "usb_config.h" +#include "usb_util.h" +#include "usb_errno.h" +#include "usb_def.h" +#include "usb_list.h" +#include "usb_log.h" +#include "usb_hc.h" +#include "usb_osal.h" +#include "usbh_hub.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define USB_CLASS_MATCH_VENDOR 0x0001 +#define USB_CLASS_MATCH_PRODUCT 0x0002 +#define USB_CLASS_MATCH_INTF_CLASS 0x0004 +#define USB_CLASS_MATCH_INTF_SUBCLASS 0x0008 +#define USB_CLASS_MATCH_INTF_PROTOCOL 0x0010 +#define USB_CLASS_MATCH_VID_PID (USB_CLASS_MATCH_VENDOR | USB_CLASS_MATCH_PRODUCT) + +#define CLASS_CONNECT(hport, i) ((hport)->config.intf[i].class_driver->connect(hport, i)) +#define CLASS_DISCONNECT(hport, i) ((hport)->config.intf[i].class_driver->disconnect(hport, i)) + +#ifdef __ARMCC_VERSION /* ARM C Compiler */ +#define CLASS_INFO_DEFINE __attribute__((section("usbh_class_info"))) __USED __ALIGNED(1) +#elif defined(__GNUC__) +#define CLASS_INFO_DEFINE __attribute__((section(".usbh_class_info"))) __USED __ALIGNED(1) +#elif defined(__ICCARM__) || defined(__ICCRX__) || defined(__ICCRISCV__) +#pragma section = ".usbh_class_info" +#define CLASS_INFO_DEFINE __attribute__((section(".usbh_class_info"))) __USED __ALIGNED(1) +#endif + +#define USBH_GET_URB_INTERVAL(interval, speed) (speed < USB_SPEED_HIGH ? interval : (1 << (interval - 1))) + +#define USBH_EP_INIT(ep, ep_desc) \ + do { \ + ep = ep_desc; \ + USB_LOG_INFO("Ep=%02x Attr=%02u Mps=%d Interval=%02u Mult=%02u\r\n", \ + ep_desc->bEndpointAddress, \ + USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes), \ + USB_GET_MAXPACKETSIZE(ep_desc->wMaxPacketSize), \ + ep_desc->bInterval, \ + USB_GET_MULT(ep_desc->bmAttributes)); \ + } while (0) + +struct usbh_class_info { + uint8_t match_flags; /* Used for product specific matches; range is inclusive */ + uint8_t class; /* Base device class code */ + uint8_t subclass; /* Sub-class, depends on base class. Eg. */ + uint8_t protocol; /* Protocol, depends on base class. Eg. */ + const uint16_t (*id_table)[2]; /* List of Vendor/Product ID pairs */ + const struct usbh_class_driver *class_driver; +}; + +struct usbh_hubport; +struct usbh_class_driver { + const char *driver_name; + int (*connect)(struct usbh_hubport *hport, uint8_t intf); + int (*disconnect)(struct usbh_hubport *hport, uint8_t intf); +}; + +struct usbh_endpoint { + struct usb_endpoint_descriptor ep_desc; +}; + +struct usbh_interface_altsetting { + struct usb_interface_descriptor intf_desc; + struct usbh_endpoint ep[CONFIG_USBHOST_MAX_ENDPOINTS]; +}; + +struct usbh_interface { + char devname[CONFIG_USBHOST_DEV_NAMELEN]; + struct usbh_class_driver *class_driver; + void *priv; + struct usbh_interface_altsetting altsetting[CONFIG_USBHOST_MAX_INTF_ALTSETTINGS]; + uint8_t altsetting_num; +}; + +struct usbh_configuration { + struct usb_configuration_descriptor config_desc; + struct usbh_interface intf[CONFIG_USBHOST_MAX_INTERFACES]; +}; + +struct usbh_hubport { + bool connected; /* True: device connected; false: disconnected */ + uint8_t port; /* Hub port index */ + uint8_t dev_addr; /* device address */ + uint8_t speed; /* device speed */ + struct usb_device_descriptor device_desc; + struct usbh_configuration config; + const char *iManufacturer; + const char *iProduct; + const char *iSerialNumber; + uint8_t *raw_config_desc; + struct usb_setup_packet *setup; + struct usbh_hub *parent; + struct usbh_bus *bus; +#ifdef CONFIG_USBHOST_XHCI + uint32_t protocol; /* port protocol, for xhci, some ports are USB2.0, others are USB3.0 */ +#endif + struct usb_endpoint_descriptor ep0; + struct usbh_urb ep0_urb; + usb_osal_mutex_t mutex; +}; + +struct usbh_hub { + usb_slist_t list; + bool connected; + bool is_roothub; + uint8_t index; + uint8_t hub_addr; + struct usb_hub_descriptor hub_desc; + struct usbh_hubport child[CONFIG_USBHOST_MAX_EHPORTS]; + struct usbh_hubport *parent; + struct usbh_bus *bus; + struct usb_endpoint_descriptor *intin; + struct usbh_urb intin_urb; + uint8_t *int_buffer; + struct usb_osal_timer *int_timer; +}; + +struct usbh_devaddr_map { + /** + * alloctab[0]:addr from 0~31 + * alloctab[1]:addr from 32~63 + * alloctab[2]:addr from 64~95 + * alloctab[3]:addr from 96~127 + * + */ + uint8_t next; /* Next device address */ + uint32_t alloctab[4]; /* Bit allocation table */ +}; + +struct usbh_hcd { + uint32_t reg_base; + uint8_t hcd_id; + uint8_t roothub_intbuf[1]; + struct usbh_hub roothub; +}; + +struct usbh_bus { + usb_slist_t list; + uint8_t busid; + struct usbh_hcd hcd; + struct usbh_devaddr_map devgen; + usb_osal_thread_t hub_thread; + usb_osal_mq_t hub_mq; + usb_slist_t hub_list; +}; + +static inline void usbh_control_urb_fill(struct usbh_urb *urb, + struct usbh_hubport *hport, + struct usb_setup_packet *setup, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + urb->hport = hport; + urb->ep = &hport->ep0; + urb->setup = setup; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + +static inline void usbh_bulk_urb_fill(struct usbh_urb *urb, + struct usbh_hubport *hport, + struct usb_endpoint_descriptor *ep, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + urb->hport = hport; + urb->ep = ep; + urb->setup = NULL; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; +} + +static inline void usbh_int_urb_fill(struct usbh_urb *urb, + struct usbh_hubport *hport, + struct usb_endpoint_descriptor *ep, + uint8_t *transfer_buffer, + uint32_t transfer_buffer_length, + uint32_t timeout, + usbh_complete_callback_t complete, + void *arg) +{ + urb->hport = hport; + urb->ep = ep; + urb->setup = NULL; + urb->transfer_buffer = transfer_buffer; + urb->transfer_buffer_length = transfer_buffer_length; + urb->timeout = timeout; + urb->complete = complete; + urb->arg = arg; + urb->interval = USBH_GET_URB_INTERVAL(ep->bInterval, hport->speed); +} + +extern struct usbh_bus g_usbhost_bus[]; +#ifdef USBH_IRQHandler +#error USBH_IRQHandler is obsolete, please call USBH_IRQHandler(xxx) in your irq +#endif + +/** + * @brief Submit an control transfer to an endpoint. + * This is a blocking method; this method will not return until the transfer has completed. + * Default timeout is 500ms. + * + * @param pipe The control endpoint to send/receive the control request. + * @param setup Setup packet to be sent. + * @param buffer buffer used for sending the request and for returning any responses. + * @return On success will return 0, and others indicate fail. + */ +int usbh_control_transfer(struct usbh_hubport *hport, struct usb_setup_packet *setup, uint8_t *buffer); + +/** + * @brief Retrieves a USB string descriptor from a specific hub port. + * + * This function is responsible for retrieving the USB string descriptor + * with the specified index from the USB device connected to the given hub port. + * The retrieved descriptor is stored in the output buffer provided. + * + * @param hport Pointer to the USB hub port structure. + * @param index Index of the string descriptor to retrieve. + * @param output Pointer to the buffer where the retrieved descriptor will be stored. + * @return On success will return 0, and others indicate fail. + */ +int usbh_get_string_desc(struct usbh_hubport *hport, uint8_t index, uint8_t *output); + +/** + * @brief Sets the alternate setting for a USB interface on a specific hub port. + * + * This function is responsible for setting the alternate setting of the + * specified USB interface on the USB device connected to the given hub port. + * The interface and alternate setting are identified by the respective parameters. + * + * @param hport Pointer to the USB hub port structure. + * @param intf Interface number to set the alternate setting for. + * @param altsetting Alternate setting value to set for the interface. + * @return On success will return 0, and others indicate fail. + */ +int usbh_set_interface(struct usbh_hubport *hport, uint8_t intf, uint8_t altsetting); + +int usbh_initialize(uint8_t busid, uint32_t reg_base); +int usbh_deinitialize(uint8_t busid); +void *usbh_find_class_instance(const char *devname); + +int lsusb(int argc, char **argv); + +#ifdef __cplusplus +} +#endif + +#endif /* USBH_CORE_H */ diff --git a/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c b/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c new file mode 100644 index 00000000000..a80a221a689 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/audio_v1_mic_multichan_template.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_audio.h" + +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#ifdef CONFIG_USB_HS +#define EP_INTERVAL 0x04 +#else +#define EP_INTERVAL 0x01 +#endif + +#define AUDIO_IN_EP 0x81 + +#define AUDIO_IN_FU_ID 0x02 + +/* AUDIO Class Config */ +#define AUDIO_FREQ 16000U + +#define IN_CHANNEL_NUM 1 + +#if IN_CHANNEL_NUM == 1 +#define INPUT_CTRL 0x03, 0x03 +#define INPUT_CH_ENABLE 0x0000 +#elif IN_CHANNEL_NUM == 2 +#define INPUT_CTRL 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x0003 +#elif IN_CHANNEL_NUM == 3 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x0007 +#elif IN_CHANNEL_NUM == 4 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x000f +#elif IN_CHANNEL_NUM == 5 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x001f +#elif IN_CHANNEL_NUM == 6 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x003F +#elif IN_CHANNEL_NUM == 7 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x007f +#elif IN_CHANNEL_NUM == 8 +#define INPUT_CTRL 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03 +#define INPUT_CH_ENABLE 0x00ff +#endif + +/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 1) */ +/* 16bit(2 Bytes) 单声道(Mono:1) */ +#define AUDIO_IN_PACKET ((uint32_t)((AUDIO_FREQ * 2 * IN_CHANNEL_NUM) / 1000)) + +#define USB_AUDIO_CONFIG_DESC_SIZ (unsigned long)(9 + \ + AUDIO_AC_DESCRIPTOR_INIT_LEN(1) + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_AS_DESCRIPTOR_INIT_LEN(1)) + +#define AUDIO_AC_SIZ (AUDIO_SIZEOF_AC_HEADER_DESC(1) + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC) + +const uint8_t audio_v1_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + AUDIO_AC_DESCRIPTOR_INIT(0x00, 0x02, AUDIO_AC_SIZ, 0x00, 0x01), + AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x01, AUDIO_INTERM_MIC, IN_CHANNEL_NUM, INPUT_CH_ENABLE), + AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_IN_FU_ID, 0x01, 0x01, INPUT_CTRL), + AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x03, AUDIO_TERMINAL_STREAMING, AUDIO_IN_FU_ID), + AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x03, IN_CHANNEL_NUM, 2, 16, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_FREQ)), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'U', 0x00, /* wcChar10 */ + 'A', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '1', 0x00, /* wcChar3 */ + '0', 0x00, /* wcChar4 */ + '3', 0x00, /* wcChar5 */ + '1', 0x00, /* wcChar6 */ + '0', 0x00, /* wcChar7 */ + '0', 0x00, /* wcChar8 */ + '0' + IN_CHANNEL_NUM, 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +volatile bool tx_flag = 0; +volatile bool ep_tx_busy_flag = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_audio_open(uint8_t busid, uint8_t intf) +{ + tx_flag = 1; + ep_tx_busy_flag = false; + USB_LOG_RAW("OPEN\r\n"); +} + +void usbd_audio_close(uint8_t busid, uint8_t intf) +{ + USB_LOG_RAW("CLOSE\r\n"); + ep_tx_busy_flag = false; + tx_flag = 0; +} + +void usbd_audio_iso_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + ep_tx_busy_flag = false; +} + +static struct usbd_endpoint audio_in_ep = { + .ep_cb = usbd_audio_iso_callback, + .ep_addr = AUDIO_IN_EP +}; + +struct usbd_interface intf0; +struct usbd_interface intf1; + +struct audio_entity_info audio_entity_table[] = { + { .bEntityId = AUDIO_IN_FU_ID, + .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, + .ep = AUDIO_IN_EP }, +}; + +void audio_v1_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, audio_v1_descriptor); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0100, audio_entity_table, 1)); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf1, 0x0100, audio_entity_table, 1)); + usbd_add_endpoint(busid, &audio_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[AUDIO_IN_PACKET]; + +void audio_test(uint8_t busid) +{ + while (1) { + if (tx_flag) { + memset(write_buffer, 'a', AUDIO_IN_PACKET); + ep_tx_busy_flag = true; + usbd_ep_start_write(busid, AUDIO_IN_EP, write_buffer, AUDIO_IN_PACKET); + while (ep_tx_busy_flag) { + if (tx_flag == false) { + break; + } + } + } + } +} diff --git a/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c b/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c new file mode 100644 index 00000000000..351f66fed29 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/audio_v1_mic_speaker_multichan_template.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_audio.h" + +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#ifdef CONFIG_USB_HS +#define EP_INTERVAL 0x04 +#else +#define EP_INTERVAL 0x01 +#endif + +#define AUDIO_IN_EP 0x81 +#define AUDIO_OUT_EP 0x02 + +#define AUDIO_IN_FU_ID 0x02 +#define AUDIO_OUT_FU_ID 0x05 + +/* AUDIO Class Config */ +#define AUDIO_SPEAKER_FREQ 16000U +#define AUDIO_SPEAKER_FRAME_SIZE_BYTE 2u +#define AUDIO_SPEAKER_RESOLUTION_BIT 16u +#define AUDIO_MIC_FREQ 16000U +#define AUDIO_MIC_FRAME_SIZE_BYTE 2u +#define AUDIO_MIC_RESOLUTION_BIT 16u + +#define AUDIO_SAMPLE_FREQ(frq) (uint8_t)(frq), (uint8_t)((frq >> 8)), (uint8_t)((frq >> 16)) + +/* AudioFreq * DataSize (2 bytes) * NumChannels (Stereo: 2) */ +#define AUDIO_OUT_PACKET ((uint32_t)((AUDIO_SPEAKER_FREQ * AUDIO_SPEAKER_FRAME_SIZE_BYTE * 2) / 1000)) +/* 16bit(2 Bytes) 双声道(Mono:2) */ +#define AUDIO_IN_PACKET ((uint32_t)((AUDIO_MIC_FREQ * AUDIO_MIC_FRAME_SIZE_BYTE * 2) / 1000)) + +#define USB_AUDIO_CONFIG_DESC_SIZ (unsigned long)(9 + \ + AUDIO_AC_DESCRIPTOR_INIT_LEN(2) + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_AS_DESCRIPTOR_INIT_LEN(1) + \ + AUDIO_AS_DESCRIPTOR_INIT_LEN(1)) + +#define AUDIO_AC_SIZ (AUDIO_SIZEOF_AC_HEADER_DESC(2) + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_SIZEOF_AC_FEATURE_UNIT_DESC(2, 1) + \ + AUDIO_SIZEOF_AC_OUTPUT_TERMINAL_DESC) + +const uint8_t audio_v1_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + AUDIO_AC_DESCRIPTOR_INIT(0x00, 0x03, AUDIO_AC_SIZ, 0x00, 0x01, 0x02), + AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x01, AUDIO_INTERM_MIC, 0x02, 0x0003), + AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x02, 0x01, 0x01, 0x03, 0x00, 0x00), + AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x03, AUDIO_TERMINAL_STREAMING, 0x02), + AUDIO_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, 0x02, 0x0003), + AUDIO_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x05, 0x04, 0x01, 0x03, 0x00, 0x00), + AUDIO_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_OUTTERM_SPEAKER, 0x05), + AUDIO_AS_DESCRIPTOR_INIT(0x01, 0x04, 0x02, AUDIO_SPEAKER_FRAME_SIZE_BYTE, AUDIO_SPEAKER_RESOLUTION_BIT, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, + EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_SPEAKER_FREQ)), + AUDIO_AS_DESCRIPTOR_INIT(0x02, 0x03, 0x02, AUDIO_MIC_FRAME_SIZE_BYTE, AUDIO_MIC_RESOLUTION_BIT, AUDIO_IN_EP, 0x05, AUDIO_IN_PACKET, + EP_INTERVAL, AUDIO_SAMPLE_FREQ_3B(AUDIO_MIC_FREQ)), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'U', 0x00, /* wcChar10 */ + 'A', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '1', 0x00, /* wcChar3 */ + '0', 0x00, /* wcChar4 */ + '3', 0x00, /* wcChar5 */ + '1', 0x00, /* wcChar6 */ + '0', 0x00, /* wcChar7 */ + '0', 0x00, /* wcChar8 */ + '1', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[AUDIO_OUT_PACKET]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[AUDIO_IN_PACKET]; + +volatile bool tx_flag = 0; +volatile bool rx_flag = 0; +volatile bool ep_tx_busy_flag = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_audio_open(uint8_t busid, uint8_t intf) +{ + if (intf == 1) { + rx_flag = 1; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, AUDIO_OUT_EP, read_buffer, AUDIO_OUT_PACKET); + printf("OPEN1\r\n"); + } else { + tx_flag = 1; + ep_tx_busy_flag = false; + printf("OPEN2\r\n"); + } +} + +void usbd_audio_close(uint8_t busid, uint8_t intf) +{ + if (intf == 1) { + rx_flag = 1; + ep_tx_busy_flag = false; + printf("CLOSE1\r\n"); + } else { + tx_flag = 0; + printf("CLOSE2\r\n"); + } +} + +void usbd_audio_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + usbd_ep_start_read(busid, AUDIO_OUT_EP, read_buffer, AUDIO_OUT_PACKET); +} + +void usbd_audio_in_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + ep_tx_busy_flag = false; +} + +static struct usbd_endpoint audio_in_ep = { + .ep_cb = usbd_audio_in_callback, + .ep_addr = AUDIO_IN_EP +}; + +static struct usbd_endpoint audio_out_ep = { + .ep_cb = usbd_audio_out_callback, + .ep_addr = AUDIO_OUT_EP +}; + +struct usbd_interface intf0; +struct usbd_interface intf1; +struct usbd_interface intf2; + +struct audio_entity_info audio_entity_table[] = { + { .bEntityId = AUDIO_IN_FU_ID, + .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, + .ep = AUDIO_IN_EP }, + { .bEntityId = AUDIO_OUT_FU_ID, + .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, + .ep = AUDIO_OUT_EP }, +}; + +void audio_v1_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, audio_v1_descriptor); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0100, audio_entity_table, 2)); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf1, 0x0100, audio_entity_table, 2)); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf2, 0x0100, audio_entity_table, 2)); + usbd_add_endpoint(busid, &audio_in_ep); + usbd_add_endpoint(busid, &audio_out_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +void audio_v1_test(uint8_t busid) +{ + if (tx_flag) { + memset(write_buffer, 'a', AUDIO_IN_PACKET); + ep_tx_busy_flag = true; + usbd_ep_start_write(busid, AUDIO_IN_EP, write_buffer, AUDIO_IN_PACKET); + while (ep_tx_busy_flag) { + if (tx_flag == false) { + break; + } + } + } +} diff --git a/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c b/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c new file mode 100644 index 00000000000..bf85762c7cc --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/audio_v2_mic_multichan_template.c @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_audio.h" + +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#ifdef CONFIG_USB_HS +#define EP_INTERVAL 0x04 +#else +#define EP_INTERVAL 0x01 +#endif + +#define AUDIO_IN_EP 0x81 + +#define AUDIO_IN_CLOCK_ID 0x01 +#define AUDIO_IN_FU_ID 0x03 + +#define AUDIO_FREQ 48000 +#define HALF_WORD_BYTES 2 //2 half word (one channel) +#define SAMPLE_BITS 16 //16 bit per channel + +#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME) + +#define IN_CHANNEL_NUM 2 + +#if IN_CHANNEL_NUM == 1 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x00000000 +#elif IN_CHANNEL_NUM == 2 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x00000003 +#elif IN_CHANNEL_NUM == 3 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x00000007 +#elif IN_CHANNEL_NUM == 4 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x0000000f +#elif IN_CHANNEL_NUM == 5 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x0000001f +#elif IN_CHANNEL_NUM == 6 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x0000003F +#elif IN_CHANNEL_NUM == 7 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x0000007f +#elif IN_CHANNEL_NUM == 8 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x000000ff +#endif + +#define AUDIO_IN_PACKET ((uint32_t)((AUDIO_FREQ * HALF_WORD_BYTES * IN_CHANNEL_NUM) / 1000)) + +#define USB_AUDIO_CONFIG_DESC_SIZ (9 + \ + AUDIO_V2_AC_DESCRIPTOR_INIT_LEN + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_AS_DESCRIPTOR_INIT_LEN) + +#define AUDIO_AC_SIZ (AUDIO_V2_SIZEOF_AC_HEADER_DESC + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC) + +const uint8_t audio_v2_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + AUDIO_V2_AC_DESCRIPTOR_INIT(0x00, 0x02, AUDIO_AC_SIZ, AUDIO_CATEGORY_MICROPHONE, 0x00, 0x00), + AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(0x01, 0x03, 0x03), + AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_INTERM_MIC, 0x01, IN_CHANNEL_NUM, INPUT_CH_ENABLE, 0x0000), + AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x03, 0x02, INPUT_CTRL), + AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_TERMINAL_STREAMING, 0x03, 0x01, 0x0000), + AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x04, IN_CHANNEL_NUM, INPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_IN_EP, 0x05, (AUDIO_IN_PACKET + 4), EP_INTERVAL), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'U', 0x00, /* wcChar10 */ + 'A', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '1', 0x00, /* wcChar3 */ + '0', 0x00, /* wcChar4 */ + '3', 0x00, /* wcChar5 */ + '1', 0x00, /* wcChar6 */ + '0', 0x00, /* wcChar7 */ + '0', 0x00, /* wcChar8 */ + '4', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +static const uint8_t mic_default_sampling_freq_table[] = { + AUDIO_SAMPLE_FREQ_NUM(1), + AUDIO_SAMPLE_FREQ_4B(16000), + AUDIO_SAMPLE_FREQ_4B(16000), + AUDIO_SAMPLE_FREQ_4B(0x00) +}; + +volatile bool tx_flag = 0; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_audio_open(uint8_t busid, uint8_t intf) +{ + tx_flag = 1; + USB_LOG_RAW("OPEN\r\n"); +} + +void usbd_audio_close(uint8_t busid, uint8_t intf) +{ + USB_LOG_RAW("CLOSE\r\n"); + tx_flag = 0; +} + +void usbd_audio_get_sampling_freq_table(uint8_t busid, uint8_t ep, uint8_t **sampling_freq_table) +{ + if (ep == AUDIO_IN_EP) { + *sampling_freq_table = (uint8_t *)mic_default_sampling_freq_table; + } +} + +void usbd_audio_iso_in_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ +} + +static struct usbd_endpoint audio_in_ep = { + .ep_cb = usbd_audio_iso_in_callback, + .ep_addr = AUDIO_IN_EP +}; + +struct usbd_interface intf0; +struct usbd_interface intf1; + +struct audio_entity_info audio_entity_table[] = { + { .bEntityId = AUDIO_IN_CLOCK_ID, + .bDescriptorSubtype = AUDIO_CONTROL_CLOCK_SOURCE, + .ep = AUDIO_IN_EP }, + { .bEntityId = AUDIO_IN_FU_ID, + .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, + .ep = AUDIO_IN_EP }, +}; + +void audio_v2_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, audio_v2_descriptor); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0200, audio_entity_table, 2)); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf1, 0x0200, audio_entity_table, 2)); + usbd_add_endpoint(busid, &audio_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +void audio_v2_test(uint8_t busid) +{ + if (tx_flag) { + } +} diff --git a/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c b/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c new file mode 100644 index 00000000000..c0b2042c092 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/audio_v2_mic_speaker_multichan_template.c @@ -0,0 +1,367 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_audio.h" + +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#ifdef CONFIG_USB_HS +#define EP_INTERVAL 0x04 +#else +#define EP_INTERVAL 0x01 +#endif + +#define AUDIO_OUT_EP 0x02 +#define AUDIO_IN_EP 0x81 + +#define AUDIO_OUT_CLOCK_ID 0x01 +#define AUDIO_OUT_FU_ID 0x03 +#define AUDIO_IN_CLOCK_ID 0x05 +#define AUDIO_IN_FU_ID 0x07 + +#define AUDIO_FREQ 48000 +#define HALF_WORD_BYTES 2 //2 half word (one channel) +#define SAMPLE_BITS 16 //16 bit per channel + +#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME) + +#define IN_CHANNEL_NUM 2 + +#if IN_CHANNEL_NUM == 1 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x00000000 +#elif IN_CHANNEL_NUM == 2 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x00000003 +#elif IN_CHANNEL_NUM == 3 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x00000007 +#elif IN_CHANNEL_NUM == 4 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x0000000f +#elif IN_CHANNEL_NUM == 5 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x0000001f +#elif IN_CHANNEL_NUM == 6 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x0000003F +#elif IN_CHANNEL_NUM == 7 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x0000007f +#elif IN_CHANNEL_NUM == 8 +#define INPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define INPUT_CH_ENABLE 0x000000ff +#endif + +#define OUT_CHANNEL_NUM 2 + +#if OUT_CHANNEL_NUM == 1 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x00000000 +#elif OUT_CHANNEL_NUM == 2 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x00000003 +#elif OUT_CHANNEL_NUM == 3 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x00000007 +#elif OUT_CHANNEL_NUM == 4 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x0000000f +#elif OUT_CHANNEL_NUM == 5 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x0000001f +#elif OUT_CHANNEL_NUM == 6 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x0000003F +#elif OUT_CHANNEL_NUM == 7 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x0000007f +#elif OUT_CHANNEL_NUM == 8 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x000000ff +#endif + +/* AudioFreq * DataSize (2 bytes) * NumChannels */ +#define AUDIO_OUT_PACKET ((uint32_t)((AUDIO_FREQ * HALF_WORD_BYTES * OUT_CHANNEL_NUM) / 1000)) +#define AUDIO_IN_PACKET ((uint32_t)((AUDIO_FREQ * HALF_WORD_BYTES * IN_CHANNEL_NUM) / 1000)) + +#define USB_AUDIO_CONFIG_DESC_SIZ (9 + \ + AUDIO_V2_AC_DESCRIPTOR_INIT_LEN + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_AS_DESCRIPTOR_INIT_LEN + \ + AUDIO_V2_AS_DESCRIPTOR_INIT_LEN) + +#define AUDIO_AC_SIZ (AUDIO_V2_SIZEOF_AC_HEADER_DESC + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(IN_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC) + +uint8_t audio_v2_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + AUDIO_V2_AC_DESCRIPTOR_INIT(0x00, 0x03, AUDIO_AC_SIZ, AUDIO_CATEGORY_UNDEF, 0x00, 0x00), + AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(0x01, 0x03, 0x03), + AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_TERMINAL_STREAMING, 0x01, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, 0x0000), + AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x03, 0x02, OUTPUT_CTRL), + AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_OUTTERM_SPEAKER, 0x03, 0x01, 0x0000), + AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(0x05, 0x03, 0x03), + AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x06, AUDIO_INTERM_MIC, 0x05, IN_CHANNEL_NUM, INPUT_CH_ENABLE, 0x0000), + AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(0x07, 0x06, INPUT_CTRL), + AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x08, AUDIO_TERMINAL_STREAMING, 0x07, 0x05, 0x0000), + AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL), + AUDIO_V2_AS_DESCRIPTOR_INIT(0x02, 0x08, IN_CHANNEL_NUM, INPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_IN_EP, 0x05, (AUDIO_IN_PACKET + 4), EP_INTERVAL), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'U', 0x00, /* wcChar10 */ + 'A', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '1', 0x00, /* wcChar3 */ + '0', 0x00, /* wcChar4 */ + '3', 0x00, /* wcChar5 */ + '1', 0x00, /* wcChar6 */ + '0', 0x00, /* wcChar7 */ + '0', 0x00, /* wcChar8 */ + '5', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +static const uint8_t speaker_default_sampling_freq_table[] = { + AUDIO_SAMPLE_FREQ_NUM(5), + AUDIO_SAMPLE_FREQ_4B(8000), + AUDIO_SAMPLE_FREQ_4B(8000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(16000), + AUDIO_SAMPLE_FREQ_4B(16000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(32000), + AUDIO_SAMPLE_FREQ_4B(32000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(48000), + AUDIO_SAMPLE_FREQ_4B(48000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(96000), + AUDIO_SAMPLE_FREQ_4B(96000), + AUDIO_SAMPLE_FREQ_4B(0x00) +}; + +static const uint8_t mic_default_sampling_freq_table[] = { + AUDIO_SAMPLE_FREQ_NUM(1), + AUDIO_SAMPLE_FREQ_4B(16000), + AUDIO_SAMPLE_FREQ_4B(16000), + AUDIO_SAMPLE_FREQ_4B(0x00) +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[AUDIO_OUT_PACKET]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[AUDIO_IN_PACKET]; + +volatile bool tx_flag = 0; +volatile bool rx_flag = 0; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_audio_open(uint8_t busid, uint8_t intf) +{ + if (intf == 1) { + rx_flag = 1; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, AUDIO_OUT_EP, read_buffer, AUDIO_OUT_PACKET); + USB_LOG_RAW("OPEN1\r\n"); + } else { + tx_flag = 1; + USB_LOG_RAW("OPEN2\r\n"); + } +} + +void usbd_audio_close(uint8_t busid, uint8_t intf) +{ + if (intf == 1) { + rx_flag = 1; + USB_LOG_RAW("CLOSE1\r\n"); + } else { + tx_flag = 0; + USB_LOG_RAW("CLOSE2\r\n"); + } +} + +void usbd_audio_get_sampling_freq_table(uint8_t busid, uint8_t ep, uint8_t **sampling_freq_table) +{ + if (ep == AUDIO_OUT_EP) { + *sampling_freq_table = (uint8_t *)speaker_default_sampling_freq_table; + } else if (ep == AUDIO_IN_EP) { + *sampling_freq_table = (uint8_t *)mic_default_sampling_freq_table; + } else { + } +} + +void usbd_audio_set_sampling_freq(uint8_t busid, uint8_t ep, uint32_t sampling_freq) +{ + uint16_t packet_size = 0; + if (ep == AUDIO_OUT_EP) { + packet_size = ((sampling_freq * 2 * OUT_CHANNEL_NUM) / 1000); + audio_v2_descriptor[18 + USB_AUDIO_CONFIG_DESC_SIZ - AUDIO_V2_AS_DESCRIPTOR_INIT_LEN - 11] = packet_size; + audio_v2_descriptor[18 + USB_AUDIO_CONFIG_DESC_SIZ - AUDIO_V2_AS_DESCRIPTOR_INIT_LEN - 10] = packet_size >> 8; + } else if (ep == AUDIO_IN_EP) { + packet_size = ((sampling_freq * 2 * IN_CHANNEL_NUM) / 1000); + audio_v2_descriptor[18 + USB_AUDIO_CONFIG_DESC_SIZ - 11] = packet_size; + audio_v2_descriptor[18 + USB_AUDIO_CONFIG_DESC_SIZ - 10] = packet_size >> 8; + } +} + +void usbd_audio_iso_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + usbd_ep_start_read(busid, AUDIO_OUT_EP, read_buffer, AUDIO_OUT_PACKET); +} + +void usbd_audio_iso_in_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ +} + +static struct usbd_endpoint audio_out_ep = { + .ep_cb = usbd_audio_iso_out_callback, + .ep_addr = AUDIO_OUT_EP +}; + +static struct usbd_endpoint audio_in_ep = { + .ep_cb = usbd_audio_iso_in_callback, + .ep_addr = AUDIO_IN_EP +}; + +struct usbd_interface intf0; +struct usbd_interface intf1; +struct usbd_interface intf2; + +struct audio_entity_info audio_entity_table[] = { + { .bEntityId = AUDIO_OUT_CLOCK_ID, + .bDescriptorSubtype = AUDIO_CONTROL_CLOCK_SOURCE, + .ep = AUDIO_OUT_EP }, + { .bEntityId = AUDIO_OUT_FU_ID, + .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, + .ep = AUDIO_OUT_EP }, + { .bEntityId = AUDIO_IN_CLOCK_ID, + .bDescriptorSubtype = AUDIO_CONTROL_CLOCK_SOURCE, + .ep = AUDIO_IN_EP }, + { .bEntityId = AUDIO_IN_FU_ID, + .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, + .ep = AUDIO_IN_EP }, +}; + +void audio_v2_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, audio_v2_descriptor); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0200, audio_entity_table, 4)); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf1, 0x0200, audio_entity_table, 4)); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf2, 0x0200, audio_entity_table, 4)); + usbd_add_endpoint(busid, &audio_in_ep); + usbd_add_endpoint(busid, &audio_out_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +void audio_v2_test(uint8_t busid) +{ + if (tx_flag) { + } + if (rx_flag) { + } +} diff --git a/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c b/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c new file mode 100644 index 00000000000..3fc7a48b1ee --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/audio_v2_speaker_multichan_template.c @@ -0,0 +1,264 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_audio.h" + +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#ifdef CONFIG_USB_HS +#define EP_INTERVAL 0x04 +#else +#define EP_INTERVAL 0x01 +#endif + +#define AUDIO_OUT_EP 0x01 + +#define AUDIO_OUT_CLOCK_ID 0x01 +#define AUDIO_OUT_FU_ID 0x03 + +#define AUDIO_FREQ 48000 +#define HALF_WORD_BYTES 2 //2 half word (one channel) +#define SAMPLE_BITS 16 //16 bit per channel + +#define BMCONTROL (AUDIO_V2_FU_CONTROL_MUTE | AUDIO_V2_FU_CONTROL_VOLUME) + +#define OUT_CHANNEL_NUM 2 + +#if OUT_CHANNEL_NUM == 1 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x00000000 +#elif OUT_CHANNEL_NUM == 2 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x00000003 +#elif OUT_CHANNEL_NUM == 3 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x00000007 +#elif OUT_CHANNEL_NUM == 4 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x0000000f +#elif OUT_CHANNEL_NUM == 5 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x0000001f +#elif OUT_CHANNEL_NUM == 6 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x0000003F +#elif OUT_CHANNEL_NUM == 7 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x0000007f +#elif OUT_CHANNEL_NUM == 8 +#define OUTPUT_CTRL DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL), DBVAL(BMCONTROL) +#define OUTPUT_CH_ENABLE 0x000000ff +#endif + +#define AUDIO_OUT_PACKET ((uint32_t)((AUDIO_FREQ * HALF_WORD_BYTES * OUT_CHANNEL_NUM) / 1000)) + +#define USB_AUDIO_CONFIG_DESC_SIZ (9 + \ + AUDIO_V2_AC_DESCRIPTOR_INIT_LEN + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC + \ + AUDIO_V2_AS_DESCRIPTOR_INIT_LEN) + +#define AUDIO_AC_SIZ (AUDIO_V2_SIZEOF_AC_HEADER_DESC + \ + AUDIO_V2_SIZEOF_AC_CLOCK_SOURCE_DESC + \ + AUDIO_V2_SIZEOF_AC_INPUT_TERMINAL_DESC + \ + AUDIO_V2_SIZEOF_AC_FEATURE_UNIT_DESC(OUT_CHANNEL_NUM) + \ + AUDIO_V2_SIZEOF_AC_OUTPUT_TERMINAL_DESC) + +const uint8_t audio_v2_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + AUDIO_V2_AC_DESCRIPTOR_INIT(0x00, 0x02, AUDIO_AC_SIZ, AUDIO_CATEGORY_SPEAKER, 0x00, 0x00), + AUDIO_V2_AC_CLOCK_SOURCE_DESCRIPTOR_INIT(AUDIO_OUT_CLOCK_ID, 0x03, 0x03), + AUDIO_V2_AC_INPUT_TERMINAL_DESCRIPTOR_INIT(0x02, AUDIO_TERMINAL_STREAMING, 0x01, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, 0x0000), + AUDIO_V2_AC_FEATURE_UNIT_DESCRIPTOR_INIT(AUDIO_OUT_FU_ID, 0x02, OUTPUT_CTRL), + AUDIO_V2_AC_OUTPUT_TERMINAL_DESCRIPTOR_INIT(0x04, AUDIO_OUTTERM_SPEAKER, 0x03, 0x01, 0x0000), + AUDIO_V2_AS_DESCRIPTOR_INIT(0x01, 0x02, OUT_CHANNEL_NUM, OUTPUT_CH_ENABLE, HALF_WORD_BYTES, SAMPLE_BITS, AUDIO_OUT_EP, 0x09, AUDIO_OUT_PACKET, EP_INTERVAL), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'U', 0x00, /* wcChar10 */ + 'A', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '1', 0x00, /* wcChar3 */ + '0', 0x00, /* wcChar4 */ + '3', 0x00, /* wcChar5 */ + '1', 0x00, /* wcChar6 */ + '0', 0x00, /* wcChar7 */ + '0', 0x00, /* wcChar8 */ + '3', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +static const uint8_t default_sampling_freq_table[] = { + AUDIO_SAMPLE_FREQ_NUM(5), + AUDIO_SAMPLE_FREQ_4B(8000), + AUDIO_SAMPLE_FREQ_4B(8000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(16000), + AUDIO_SAMPLE_FREQ_4B(16000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(32000), + AUDIO_SAMPLE_FREQ_4B(32000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(48000), + AUDIO_SAMPLE_FREQ_4B(48000), + AUDIO_SAMPLE_FREQ_4B(0x00), + AUDIO_SAMPLE_FREQ_4B(96000), + AUDIO_SAMPLE_FREQ_4B(96000), + AUDIO_SAMPLE_FREQ_4B(0x00), +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[AUDIO_OUT_PACKET]; + +volatile bool rx_flag = 0; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_audio_open(uint8_t busid, uint8_t intf) +{ + rx_flag = 1; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, AUDIO_OUT_EP, read_buffer, AUDIO_OUT_PACKET); + USB_LOG_RAW("OPEN\r\n"); +} + +void usbd_audio_close(uint8_t busid, uint8_t intf) +{ + USB_LOG_RAW("CLOSE\r\n"); + rx_flag = 0; +} + +void usbd_audio_get_sampling_freq_table(uint8_t busid, uint8_t ep, uint8_t **sampling_freq_table) +{ + if (ep == AUDIO_OUT_EP) { + *sampling_freq_table = (uint8_t *)default_sampling_freq_table; + } +} + +void usbd_audio_iso_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + usbd_ep_start_read(busid, AUDIO_OUT_EP, read_buffer, AUDIO_OUT_PACKET); +} + +static struct usbd_endpoint audio_out_ep = { + .ep_cb = usbd_audio_iso_out_callback, + .ep_addr = AUDIO_OUT_EP +}; + +struct usbd_interface intf0; +struct usbd_interface intf1; + +struct audio_entity_info audio_entity_table[] = { + { .bEntityId = AUDIO_OUT_CLOCK_ID, + .bDescriptorSubtype = AUDIO_CONTROL_CLOCK_SOURCE, + .ep = AUDIO_OUT_EP }, + { .bEntityId = AUDIO_OUT_FU_ID, + .bDescriptorSubtype = AUDIO_CONTROL_FEATURE_UNIT, + .ep = AUDIO_OUT_EP }, +}; + +void audio_v2_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, audio_v2_descriptor); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf0, 0x0200, audio_entity_table, 2)); + usbd_add_interface(busid, usbd_audio_init_intf(busid, &intf1, 0x0200, audio_entity_table, 2)); + usbd_add_endpoint(busid, &audio_out_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +void audio_v2_test(uint8_t busid) +{ + if (rx_flag) { + } +} diff --git a/components/drivers/usb/cherryusb/demo/cdc_acm_hid_msc_template.c b/components/drivers/usb/cherryusb/demo/cdc_acm_hid_msc_template.c new file mode 100644 index 00000000000..93a3dc1391e --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/cdc_acm_hid_msc_template.c @@ -0,0 +1,396 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_msc.h" +#include "usbd_cdc.h" +#include "usbd_hid.h" + +/*!< endpoint address */ +#define CDC_IN_EP 0x81 +#define CDC_OUT_EP 0x02 +#define CDC_INT_EP 0x83 + +#define MSC_IN_EP 0x84 +#define MSC_OUT_EP 0x05 + +/*!< endpoint address */ +#define HID_INT_EP 0x86 +#define HID_INT_EP_SIZE 4 +#define HID_INT_EP_INTERVAL 10 + +#define USBD_VID 0xFFFF +#define USBD_PID 0xFFFF +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +/*!< report descriptor size */ +#define HID_MOUSE_REPORT_DESC_SIZE 74 + +#define USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN + MSC_DESCRIPTOR_LEN + 25) + +#ifdef CONFIG_USB_HS +#define CDC_MAX_MPS 512 +#else +#define CDC_MAX_MPS 64 +#endif + +#ifdef CONFIG_USB_HS +#define MSC_MAX_MPS 512 +#else +#define MSC_MAX_MPS 64 +#endif + +const uint8_t cdc_acm_hid_msc_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x04, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), + MSC_DESCRIPTOR_INIT(0x02, MSC_OUT_EP, MSC_IN_EP, MSC_MAX_MPS, 0x02), + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x03, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ + 0x00, + HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'C', 0x00, /* wcChar10 */ + 'M', 0x00, /* wcChar11 */ + 'H', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +/*!< hid mouse report descriptor */ +static const uint8_t hid_mouse_report_desc[HID_MOUSE_REPORT_DESC_SIZE] = { + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x02, // USAGE (Mouse) + 0xA1, 0x01, // COLLECTION (Application) + 0x09, 0x01, // USAGE (Pointer) + + 0xA1, 0x00, // COLLECTION (Physical) + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x03, // USAGE_MAXIMUM (Button 3) + + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x03, // REPORT_COUNT (3) + 0x75, 0x01, // REPORT_SIZE (1) + + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x05, // REPORT_SIZE (5) + 0x81, 0x01, // INPUT (Cnst,Var,Abs) + + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + 0x09, 0x38, + + 0x15, 0x81, // LOGICAL_MINIMUM (-127) + 0x25, 0x7F, // LOGICAL_MAXIMUM (127) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x03, // REPORT_COUNT (2) + + 0x81, 0x06, // INPUT (Data,Var,Rel) + 0xC0, 0x09, + 0x3c, 0x05, + 0xff, 0x09, + + 0x01, 0x15, + 0x00, 0x25, + 0x01, 0x75, + 0x01, 0x95, + + 0x02, 0xb1, + 0x22, 0x75, + 0x06, 0x95, + 0x01, 0xb1, + + 0x01, 0xc0 // END_COLLECTION +}; + +/*!< mouse report struct */ +struct hid_mouse { + uint8_t buttons; + int8_t x; + int8_t y; + int8_t wheel; +}; + +/*!< mouse report */ +static struct hid_mouse mouse_cfg; + +#define HID_STATE_IDLE 0 +#define HID_STATE_BUSY 1 + +/*!< hid state ! Data can be sent only when state is idle */ +static volatile uint8_t hid_state = HID_STATE_IDLE; + +/* function ------------------------------------------------------------------*/ +static void usbd_hid_int_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + hid_state = HID_STATE_IDLE; +} + +/*!< endpoint call back */ +static struct usbd_endpoint hid_in_ep = { + .ep_cb = usbd_hid_int_callback, + .ep_addr = HID_INT_EP +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; + +volatile bool ep_tx_busy_flag = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + ep_tx_busy_flag = false; + hid_state = HID_STATE_IDLE; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, CDC_OUT_EP, read_buffer, 2048); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_cdc_acm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + /* setup next out ep read transfer */ + usbd_ep_start_read(busid, CDC_OUT_EP, read_buffer, 2048); +} + +void usbd_cdc_acm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(busid, CDC_IN_EP, NULL, 0); + } else { + ep_tx_busy_flag = false; + } +} + +/*!< endpoint call back */ +struct usbd_endpoint cdc_out_ep = { + .ep_addr = CDC_OUT_EP, + .ep_cb = usbd_cdc_acm_bulk_out +}; + +struct usbd_endpoint cdc_in_ep = { + .ep_addr = CDC_IN_EP, + .ep_cb = usbd_cdc_acm_bulk_in +}; + +struct usbd_interface intf0; +struct usbd_interface intf1; +struct usbd_interface intf2; +struct usbd_interface intf3; + +void cdc_acm_hid_msc_descriptor_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, cdc_acm_hid_msc_descriptor); + + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf0)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); + usbd_add_endpoint(busid, &cdc_out_ep); + usbd_add_endpoint(busid, &cdc_in_ep); + + usbd_add_interface(busid, usbd_msc_init_intf(busid, &intf2, MSC_OUT_EP, MSC_IN_EP)); + + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf3, hid_mouse_report_desc, HID_MOUSE_REPORT_DESC_SIZE)); + usbd_add_endpoint(busid, &hid_in_ep); + + /*!< init mouse report data */ + mouse_cfg.buttons = 0; + mouse_cfg.wheel = 0; + mouse_cfg.x = 0; + mouse_cfg.y = 0; + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +/** + * @brief hid mouse test + * @pre none + * @param[in] none + * @retval none + */ +void hid_mouse_test(uint8_t busid) +{ + /*!< move mouse pointer */ + mouse_cfg.x += 10; + mouse_cfg.y = 0; + int ret = usbd_ep_start_write(busid, HID_INT_EP, (uint8_t *)&mouse_cfg, 4); + if (ret < 0) { + return; + } + hid_state = HID_STATE_BUSY; + while (hid_state == HID_STATE_BUSY) { + } +} + +volatile uint8_t dtr_enable = 0; + +void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr) +{ + if (dtr) { + dtr_enable = 1; + } else { + dtr_enable = 0; + } +} + +void cdc_acm_data_send_with_dtr_test(uint8_t busid) +{ + if (dtr_enable) { + memset(&write_buffer[10], 'a', 2038); + ep_tx_busy_flag = true; + usbd_ep_start_write(busid, CDC_IN_EP, write_buffer, 2048); + while (ep_tx_busy_flag) { + } + } +} + +#define BLOCK_SIZE 512 +#define BLOCK_COUNT 10 + +typedef struct +{ + uint8_t BlockSpace[BLOCK_SIZE]; +} BLOCK_TYPE; + +BLOCK_TYPE mass_block[BLOCK_COUNT]; + +void usbd_msc_get_cap(uint8_t busid, uint8_t lun, uint32_t *block_num, uint32_t *block_size) +{ + *block_num = 1000; //Pretend having so many buffer,not has actually. + *block_size = BLOCK_SIZE; +} +int usbd_msc_sector_read(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length) +{ + if (sector < 10) + memcpy(buffer, mass_block[sector].BlockSpace, length); + return 0; +} + +int usbd_msc_sector_write(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length) +{ + if (sector < 10) + memcpy(mass_block[sector].BlockSpace, buffer, length); + return 0; +} diff --git a/components/drivers/usb/cherryusb/demo/cdc_acm_msc_template.c b/components/drivers/usb/cherryusb/demo/cdc_acm_msc_template.c new file mode 100644 index 00000000000..7ab58106337 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/cdc_acm_msc_template.c @@ -0,0 +1,315 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc.h" +#include "usbd_msc.h" + +/*!< endpoint address */ +#define CDC_IN_EP 0x81 +#define CDC_OUT_EP 0x02 +#define CDC_INT_EP 0x83 + +#define MSC_IN_EP 0x84 +#define MSC_OUT_EP 0x05 + +#define USBD_VID 0xFFFF +#define USBD_PID 0xFFFF +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +/*!< config descriptor size */ +#define USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN + MSC_DESCRIPTOR_LEN) + +#ifdef CONFIG_USB_HS +#define CDC_MAX_MPS 512 +#else +#define CDC_MAX_MPS 64 +#endif + +#ifdef CONFIG_USB_HS +#define MSC_MAX_MPS 512 +#else +#define MSC_MAX_MPS 64 +#endif + +#ifdef CONFIG_USBDEV_ADVANCE_DESC +static const uint8_t device_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01) +}; + +static const uint8_t config_descriptor[] = { + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), + MSC_DESCRIPTOR_INIT(0x02, MSC_OUT_EP, MSC_IN_EP, MSC_MAX_MPS, 0x00) +}; + +static const uint8_t device_quality_descriptor[] = { + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x40, + 0x01, + 0x00, +}; + +static const char *string_descriptors[] = { + (const char[]){ 0x09, 0x04 }, /* Langid */ + "CherryUSB", /* Manufacturer */ + "CherryUSB CDC MSC DEMO", /* Product */ + "2022123456", /* Serial Number */ +}; + +static const uint8_t *device_descriptor_callback(uint8_t speed) +{ + return device_descriptor; +} + +static const uint8_t *config_descriptor_callback(uint8_t speed) +{ + return config_descriptor; +} + +static const uint8_t *device_quality_descriptor_callback(uint8_t speed) +{ + return device_quality_descriptor; +} + +static const char *string_descriptor_callback(uint8_t speed, uint8_t index) +{ + if (index > 3) { + return NULL; + } + return string_descriptors[index]; +} + +const struct usb_descriptor cdc_msc_descriptor = { + .device_descriptor_callback = device_descriptor_callback, + .config_descriptor_callback = config_descriptor_callback, + .device_quality_descriptor_callback = device_quality_descriptor_callback, + .string_descriptor_callback = string_descriptor_callback +}; +#else +/*!< global descriptor */ +static const uint8_t cdc_msc_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x03, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), + MSC_DESCRIPTOR_INIT(0x02, MSC_OUT_EP, MSC_IN_EP, MSC_MAX_MPS, 0x00), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'C', 0x00, /* wcChar10 */ + '-', 0x00, /* wcChar11 */ + 'M', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; +#endif + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; /* 2048 is only for test speed , please use CDC_MAX_MPS for common*/ +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; + +volatile bool ep_tx_busy_flag = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + ep_tx_busy_flag = false; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, CDC_OUT_EP, read_buffer, 2048); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_cdc_acm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + /* setup next out ep read transfer */ + usbd_ep_start_read(busid, CDC_OUT_EP, read_buffer, 2048); +} + +void usbd_cdc_acm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(busid, CDC_IN_EP, NULL, 0); + } else { + ep_tx_busy_flag = false; + } +} + +/*!< endpoint call back */ +struct usbd_endpoint cdc_out_ep = { + .ep_addr = CDC_OUT_EP, + .ep_cb = usbd_cdc_acm_bulk_out +}; + +struct usbd_endpoint cdc_in_ep = { + .ep_addr = CDC_IN_EP, + .ep_cb = usbd_cdc_acm_bulk_in +}; + +struct usbd_interface intf0; +struct usbd_interface intf1; +struct usbd_interface intf2; + +void cdc_acm_msc_init(uint8_t busid, uint32_t reg_base) +{ +#ifdef CONFIG_USBDEV_ADVANCE_DESC + usbd_desc_register(busid, &cdc_msc_descriptor); +#else + usbd_desc_register(busid, cdc_msc_descriptor); +#endif + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf0)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); + usbd_add_endpoint(busid, &cdc_out_ep); + usbd_add_endpoint(busid, &cdc_in_ep); + usbd_add_interface(busid, usbd_msc_init_intf(busid, &intf2, MSC_OUT_EP, MSC_IN_EP)); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +volatile uint8_t dtr_enable = 0; + +void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr) +{ + if (dtr) { + dtr_enable = 1; + } else { + dtr_enable = 0; + } +} + +void cdc_acm_data_send_with_dtr_test(uint8_t busid) +{ + if (dtr_enable) { + memset(&write_buffer[10], 'a', 2038); + ep_tx_busy_flag = true; + usbd_ep_start_write(busid, CDC_IN_EP, write_buffer, 2048); + while (ep_tx_busy_flag) { + } + } +} + +#define BLOCK_SIZE 512 +#define BLOCK_COUNT 10 + +typedef struct +{ + uint8_t BlockSpace[BLOCK_SIZE]; +} BLOCK_TYPE; + +BLOCK_TYPE mass_block[BLOCK_COUNT]; + +void usbd_msc_get_cap(uint8_t busid, uint8_t lun, uint32_t *block_num, uint32_t *block_size) +{ + *block_num = 1000; //Pretend having so many buffer,not has actually. + *block_size = BLOCK_SIZE; +} +int usbd_msc_sector_read(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length) +{ + if (sector < 10) + memcpy(buffer, mass_block[sector].BlockSpace, length); + return 0; +} + +int usbd_msc_sector_write(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length) +{ + if (sector < 10) + memcpy(mass_block[sector].BlockSpace, buffer, length); + return 0; +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/cdc_acm_multi_template.c b/components/drivers/usb/cherryusb/demo/cdc_acm_multi_template.c new file mode 100644 index 00000000000..fa3eb650e8f --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/cdc_acm_multi_template.c @@ -0,0 +1,251 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc.h" + +/*!< endpoint address */ +#define CDC_IN_EP 0x81 +#define CDC_OUT_EP 0x01 +#define CDC_INT_EP 0x85 + +#define CDC_IN_EP2 0x82 +#define CDC_OUT_EP2 0x02 +#define CDC_INT_EP2 0x86 + +#define CDC_IN_EP3 0x83 +#define CDC_OUT_EP3 0x03 +#define CDC_INT_EP3 0x87 + +#define CDC_IN_EP4 0x84 +#define CDC_OUT_EP4 0x04 +#define CDC_INT_EP4 0x88 + +#define USBD_VID 0xFFFF +#define USBD_PID 0xFFFF +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +/*!< config descriptor size */ +#define USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN * 4) + +#ifdef CONFIG_USB_HS +#define CDC_MAX_MPS 512 +#else +#define CDC_MAX_MPS 64 +#endif + +/*!< global descriptor */ +static const uint8_t cdc_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x08, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), + CDC_ACM_DESCRIPTOR_INIT(0x02, CDC_INT_EP2, CDC_OUT_EP2, CDC_IN_EP2, CDC_MAX_MPS, 0x02), + CDC_ACM_DESCRIPTOR_INIT(0x04, CDC_INT_EP3, CDC_OUT_EP3, CDC_IN_EP3, CDC_MAX_MPS, 0x02), + CDC_ACM_DESCRIPTOR_INIT(0x06, CDC_INT_EP4, CDC_OUT_EP4, CDC_IN_EP4, CDC_MAX_MPS, 0x02), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'C', 0x00, /* wcChar10 */ + 'D', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[4][2048]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[4][2048]; + +volatile bool ep_tx_busy_flag = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + ep_tx_busy_flag = false; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, CDC_OUT_EP, read_buffer, 2048); + usbd_ep_start_read(busid, CDC_OUT_EP2, read_buffer, 2048); + usbd_ep_start_read(busid, CDC_OUT_EP3, read_buffer, 2048); + usbd_ep_start_read(busid, CDC_OUT_EP4, read_buffer, 2048); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_cdc_acm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + /* setup next out ep read transfer */ + usbd_ep_start_read(busid, CDC_OUT_EP, read_buffer, 2048); +} + +void usbd_cdc_acm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + + if ((nbytes % CDC_MAX_MPS) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(CDC_IN_EP, NULL, 0); + } else { + ep_tx_busy_flag = false; + } +} + +struct usbd_endpoint cdc_out_ep1 = { + .ep_addr = CDC_OUT_EP, + .ep_cb = usbd_cdc_acm_bulk_out +}; + +struct usbd_endpoint cdc_in_ep1 = { + .ep_addr = CDC_IN_EP, + .ep_cb = usbd_cdc_acm_bulk_in +}; + +struct usbd_endpoint cdc_out_ep2 = { + .ep_addr = CDC_OUT_EP2, + .ep_cb = usbd_cdc_acm_bulk_out +}; + +struct usbd_endpoint cdc_in_ep2 = { + .ep_addr = CDC_IN_EP2, + .ep_cb = usbd_cdc_acm_bulk_in +}; + +struct usbd_endpoint cdc_out_ep3 = { + .ep_addr = CDC_OUT_EP3, + .ep_cb = usbd_cdc_acm_bulk_out +}; + +struct usbd_endpoint cdc_in_ep3 = { + .ep_addr = CDC_IN_EP3, + .ep_cb = usbd_cdc_acm_bulk_in +}; + +struct usbd_endpoint cdc_out_ep4 = { + .ep_addr = CDC_OUT_EP4, + .ep_cb = usbd_cdc_acm_bulk_out +}; + +struct usbd_endpoint cdc_in_ep4 = { + .ep_addr = CDC_IN_EP4, + .ep_cb = usbd_cdc_acm_bulk_in +}; + +struct usbd_interface intf0; +struct usbd_interface intf1; +struct usbd_interface intf2; +struct usbd_interface intf3; +struct usbd_interface intf4; +struct usbd_interface intf5; +struct usbd_interface intf6; +struct usbd_interface intf7; + +void cdc_acm_multi_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, cdc_descriptor); + + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf0)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); + usbd_add_endpoint(busid, &cdc_out_ep1); + usbd_add_endpoint(busid, &cdc_in_ep1); + + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf2)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf3)); + usbd_add_endpoint(busid, &cdc_out_ep2); + usbd_add_endpoint(busid, &cdc_in_ep2); + + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf4)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf5)); + usbd_add_endpoint(busid, &cdc_out_ep3); + usbd_add_endpoint(busid, &cdc_in_ep3); + + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf6)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf7)); + usbd_add_endpoint(busid, &cdc_out_ep4); + usbd_add_endpoint(busid, &cdc_in_ep4); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/cdc_acm_template.c b/components/drivers/usb/cherryusb/demo/cdc_acm_template.c new file mode 100644 index 00000000000..490b71694b3 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/cdc_acm_template.c @@ -0,0 +1,211 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc.h" + +/*!< endpoint address */ +#define CDC_IN_EP 0x81 +#define CDC_OUT_EP 0x02 +#define CDC_INT_EP 0x83 + +#define USBD_VID 0xFFFF +#define USBD_PID 0xFFFF +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +/*!< config descriptor size */ +#define USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN) + +#ifdef CONFIG_USB_HS +#define CDC_MAX_MPS 512 +#else +#define CDC_MAX_MPS 64 +#endif + +/*!< global descriptor */ +static const uint8_t cdc_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'C', 0x00, /* wcChar10 */ + 'D', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; /* 2048 is only for test speed , please use CDC_MAX_MPS for common*/ +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; + +volatile bool ep_tx_busy_flag = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + ep_tx_busy_flag = false; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, CDC_OUT_EP, read_buffer, 2048); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_cdc_acm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + // for (int i = 0; i < 100; i++) { + // printf("%02x ", read_buffer[i]); + // } + // printf("\r\n"); + /* setup next out ep read transfer */ + usbd_ep_start_read(busid, CDC_OUT_EP, read_buffer, 2048); +} + +void usbd_cdc_acm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(busid, CDC_IN_EP, NULL, 0); + } else { + ep_tx_busy_flag = false; + } +} + +/*!< endpoint call back */ +struct usbd_endpoint cdc_out_ep = { + .ep_addr = CDC_OUT_EP, + .ep_cb = usbd_cdc_acm_bulk_out +}; + +struct usbd_endpoint cdc_in_ep = { + .ep_addr = CDC_IN_EP, + .ep_cb = usbd_cdc_acm_bulk_in +}; + +static struct usbd_interface intf0; +static struct usbd_interface intf1; + +void cdc_acm_init(uint8_t busid, uint32_t reg_base) +{ + const uint8_t data[10] = { 0x31, 0x32, 0x33, 0x34, 0x35, 0x36, 0x37, 0x38, 0x39, 0x30 }; + + memcpy(&write_buffer[0], data, 10); + memset(&write_buffer[10], 'a', 2038); + + usbd_desc_register(busid, cdc_descriptor); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf0)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); + usbd_add_endpoint(busid, &cdc_out_ep); + usbd_add_endpoint(busid, &cdc_in_ep); + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +volatile uint8_t dtr_enable = 0; + +void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr) +{ + if (dtr) { + dtr_enable = 1; + } else { + dtr_enable = 0; + } +} + +void cdc_acm_data_send_with_dtr_test(uint8_t busid) +{ + if (dtr_enable) { + ep_tx_busy_flag = true; + usbd_ep_start_write(busid, CDC_IN_EP, write_buffer, 2048); + while (ep_tx_busy_flag) { + } + } +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/cdc_ecm_template.c b/components/drivers/usb/cherryusb/demo/cdc_ecm_template.c new file mode 100644 index 00000000000..eca74bc64e9 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/cdc_ecm_template.c @@ -0,0 +1,279 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc_ecm.h" + +/*!< endpoint address */ +#define CDC_IN_EP 0x81 +#define CDC_OUT_EP 0x02 +#define CDC_INT_EP 0x83 + +#define USBD_VID 0xFFFF +#define USBD_PID 0xFFFF +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +/*!< config descriptor size */ +#define USB_CONFIG_SIZE (9 + CDC_ECM_DESCRIPTOR_LEN) + +#ifdef CONFIG_USB_HS +#define CDC_MAX_MPS 512 +#else +#define CDC_MAX_MPS 64 +#endif + +#define CDC_ECM_ETH_STATISTICS_BITMAP 0x00000000 + +/* str idx = 4 is for mac address: aa:bb:cc:dd:ee:ff*/ +#define CDC_ECM_MAC_STRING_INDEX 4 + +/*!< global descriptor */ +static const uint8_t cdc_ecm_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + CDC_ECM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, CDC_ECM_ETH_STATISTICS_BITMAP, CONFIG_CDC_ECM_ETH_MAX_SEGSZE, 0, 0, CDC_ECM_MAC_STRING_INDEX), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x2E, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'C', 0x00, /* wcChar10 */ + 'D', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'E', 0x00, /* wcChar14 */ + 'C', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + ' ', 0x00, /* wcChar17 */ + 'D', 0x00, /* wcChar18 */ + 'E', 0x00, /* wcChar19 */ + 'M', 0x00, /* wcChar20 */ + 'O', 0x00, /* wcChar21 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ + /////////////////////////////////////// + /// string4 descriptor + /////////////////////////////////////// + 0x1A, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'a', 0x00, /* wcChar0 */ + 'a', 0x00, /* wcChar1 */ + 'b', 0x00, /* wcChar2 */ + 'b', 0x00, /* wcChar3 */ + 'c', 0x00, /* wcChar4 */ + 'c', 0x00, /* wcChar5 */ + 'd', 0x00, /* wcChar6 */ + 'd', 0x00, /* wcChar7 */ + 'e', 0x00, /* wcChar8 */ + 'e', 0x00, /* wcChar9 */ + 'f', 0x00, /* wcChar10 */ + 'f', 0x00, /* wcChar11 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +const uint8_t mac[6] = { 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff }; + +/*Static IP ADDRESS: IP_ADDR0.IP_ADDR1.IP_ADDR2.IP_ADDR3 */ +#define IP_ADDR0 (uint8_t)192 +#define IP_ADDR1 (uint8_t)168 +#define IP_ADDR2 (uint8_t)123 +#define IP_ADDR3 (uint8_t)100 + +/*NETMASK*/ +#define NETMASK_ADDR0 (uint8_t)255 +#define NETMASK_ADDR1 (uint8_t)255 +#define NETMASK_ADDR2 (uint8_t)255 +#define NETMASK_ADDR3 (uint8_t)0 + +/*Gateway Address*/ +#define GW_ADDR0 (uint8_t)192 +#define GW_ADDR1 (uint8_t)168 +#define GW_ADDR2 (uint8_t)123 +#define GW_ADDR3 (uint8_t)1 + +#include "netif/etharp.h" +#include "lwip/init.h" +#include "lwip/netif.h" +#include "lwip/pbuf.h" + +const ip_addr_t ipaddr = IPADDR4_INIT_BYTES(IP_ADDR0, IP_ADDR1, IP_ADDR2, IP_ADDR3); +const ip_addr_t netmask = IPADDR4_INIT_BYTES(NETMASK_ADDR0, NETMASK_ADDR1, NETMASK_ADDR2, NETMASK_ADDR3); +const ip_addr_t gateway = IPADDR4_INIT_BYTES(GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3); + +static struct netif cdc_ecm_netif; //network interface + +/* Network interface name */ +#define IFNAME0 'E' +#define IFNAME1 'X' + +static err_t linkoutput_fn(struct netif *netif, struct pbuf *p) +{ + static int ret; + + ret = usbd_cdc_ecm_eth_tx(p); + if (ret == 0) + return ERR_OK; + else + return ERR_BUF; +} + +err_t cdc_ecm_if_init(struct netif *netif) +{ + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + netif->mtu = 1500; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP | NETIF_FLAG_UP; + netif->state = NULL; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + netif->output = etharp_output; + netif->linkoutput = linkoutput_fn; + return ERR_OK; +} + +err_t cdc_ecm_if_input(struct netif *netif) +{ + static err_t err; + static struct pbuf *p; + + p = usbd_cdc_ecm_eth_rx(); + if (p != NULL) { + err = netif->input(p, netif); + if (err != ERR_OK) { + pbuf_free(p); + } + } else { + return ERR_BUF; + } + return err; +} + +void cdc_ecm_lwip_init(void) +{ + struct netif *netif = &cdc_ecm_netif; + + lwip_init(); + + netif->hwaddr_len = 6; + memcpy(netif->hwaddr, mac, 6); + + netif = netif_add(netif, &ipaddr, &netmask, &gateway, NULL, cdc_ecm_if_init, netif_input); + netif_set_default(netif); + while (!netif_is_up(netif)) { + } + + // while (dhserv_init(&dhcp_config)) {} + + // while (dnserv_init(&ipaddr, PORT_DNS, dns_query_proc)) {} +} + +void usbd_cdc_ecm_data_recv_done(uint8_t *buf, uint32_t len) +{ +} + +void cdc_ecm_input_poll(void) +{ + cdc_ecm_if_input(&cdc_ecm_netif); +} + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +struct usbd_interface intf0; +struct usbd_interface intf1; + +/* ecm only supports in linux, and you should input the following command + * + * sudo ifconfig enxaabbccddeeff up + * sudo dhcpclient enxaabbccddeeff +*/ +void cdc_ecm_init(uint8_t busid, uint32_t reg_base) +{ + cdc_ecm_lwip_init(); + + usbd_desc_register(busid, cdc_ecm_descriptor); + usbd_add_interface(busid, usbd_cdc_ecm_init_intf(&intf0, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP)); + usbd_add_interface(busid, usbd_cdc_ecm_init_intf(&intf1, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP)); + usbd_initialize(busid, reg_base, usbd_event_handler); +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/cdc_rndis_template.c b/components/drivers/usb/cherryusb/demo/cdc_rndis_template.c new file mode 100644 index 00000000000..032ea710f26 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/cdc_rndis_template.c @@ -0,0 +1,313 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_rndis.h" + +/*!< endpoint address */ +#define CDC_IN_EP 0x81 +#define CDC_OUT_EP 0x02 +#define CDC_INT_EP 0x83 + +#define USBD_VID 0xEFFF +#define USBD_PID 0xEFFF +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +/*!< config descriptor size */ +#define USB_CONFIG_SIZE (9 + CDC_RNDIS_DESCRIPTOR_LEN) + +#ifdef CONFIG_USB_HS +#define CDC_MAX_MPS 512 +#else +#define CDC_MAX_MPS 64 +#endif + +/*!< global descriptor */ +static const uint8_t cdc_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + CDC_RNDIS_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x2A, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'R', 0x00, /* wcChar10 */ + 'N', 0x00, /* wcChar11 */ + 'D', 0x00, /* wcChar12 */ + 'I', 0x00, /* wcChar13 */ + 'S', 0x00, /* wcChar14 */ + ' ', 0x00, /* wcChar15 */ + 'D', 0x00, /* wcChar16 */ + 'E', 0x00, /* wcChar17 */ + 'M', 0x00, /* wcChar18 */ + 'O', 0x00, /* wcChar19 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +const uint8_t mac[6] = { 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff }; +/*Static IP ADDRESS: IP_ADDR0.IP_ADDR1.IP_ADDR2.IP_ADDR3 */ +#define IP_ADDR0 (uint8_t)192 +#define IP_ADDR1 (uint8_t)168 +#define IP_ADDR2 (uint8_t)123 +#define IP_ADDR3 (uint8_t)100 + +/*NETMASK*/ +#define NETMASK_ADDR0 (uint8_t)255 +#define NETMASK_ADDR1 (uint8_t)255 +#define NETMASK_ADDR2 (uint8_t)255 +#define NETMASK_ADDR3 (uint8_t)0 + +/*Gateway Address*/ +#define GW_ADDR0 (uint8_t)192 +#define GW_ADDR1 (uint8_t)168 +#define GW_ADDR2 (uint8_t)123 +#define GW_ADDR3 (uint8_t)1 + +#ifdef RT_USING_LWIP +#include +#include +#include + +const ip_addr_t ipaddr = IPADDR4_INIT_BYTES(IP_ADDR0, IP_ADDR1, IP_ADDR2, IP_ADDR3); +const ip_addr_t netmask = IPADDR4_INIT_BYTES(NETMASK_ADDR0, NETMASK_ADDR1, NETMASK_ADDR2, NETMASK_ADDR3); +const ip_addr_t gateway = IPADDR4_INIT_BYTES(GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3); + +struct eth_device rndis_dev; + +static rt_err_t rt_usbd_rndis_control(rt_device_t dev, int cmd, void *args) +{ + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +struct pbuf *rt_usbd_rndis_eth_rx(rt_device_t dev) +{ + return usbd_rndis_eth_rx(); +} + +rt_err_t rt_usbd_rndis_eth_tx(rt_device_t dev, struct pbuf *p) +{ + return usbd_rndis_eth_tx(p); +} + +void usbd_rndis_data_recv_done(void) +{ + eth_device_ready(&rndis_dev); +} + +void rt_usbd_rndis_init(void) +{ + rndis_dev.parent.control = rt_usbd_rndis_control; + rndis_dev.eth_rx = rt_usbd_rndis_eth_rx; + rndis_dev.eth_tx = rt_usbd_rndis_eth_tx; + + eth_device_init(&rndis_dev, "u0"); + + eth_device_linkchange(&rndis_dev, RT_FALSE); +} +#else +#include "netif/etharp.h" +#include "lwip/init.h" +#include "lwip/netif.h" +#include "lwip/pbuf.h" + +const ip_addr_t ipaddr = IPADDR4_INIT_BYTES(IP_ADDR0, IP_ADDR1, IP_ADDR2, IP_ADDR3); +const ip_addr_t netmask = IPADDR4_INIT_BYTES(NETMASK_ADDR0, NETMASK_ADDR1, NETMASK_ADDR2, NETMASK_ADDR3); +const ip_addr_t gateway = IPADDR4_INIT_BYTES(GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3); + +static struct netif rndis_netif; //network interface + +/* Network interface name */ +#define IFNAME0 'E' +#define IFNAME1 'X' + +err_t linkoutput_fn(struct netif *netif, struct pbuf *p) +{ + static int ret; + + ret = usbd_rndis_eth_tx(p); + if (ret == 0) + return ERR_OK; + else + return ERR_BUF; +} + +err_t rndisif_init(struct netif *netif) +{ + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + netif->mtu = 1500; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP | NETIF_FLAG_UP; + netif->state = NULL; + netif->name[0] = IFNAME0; + netif->name[1] = IFNAME1; + netif->output = etharp_output; + netif->linkoutput = linkoutput_fn; + return ERR_OK; +} + +err_t rndisif_input(struct netif *netif) +{ + static err_t err; + static struct pbuf *p; + + p = usbd_rndis_eth_rx(); + if (p != NULL) { + err = netif->input(p, netif); + if (err != ERR_OK) { + pbuf_free(p); + } + } else { + return ERR_BUF; + } + return err; +} + +void rndis_lwip_init(void) +{ + struct netif *netif = &rndis_netif; + + lwip_init(); + + netif->hwaddr_len = 6; + memcpy(netif->hwaddr, mac, 6); + + netif = netif_add(netif, &ipaddr, &netmask, &gateway, NULL, rndisif_init, netif_input); + netif_set_default(netif); + while (!netif_is_up(netif)) { + } + + // while (dhserv_init(&dhcp_config)) {} + + // while (dnserv_init(&ipaddr, PORT_DNS, dns_query_proc)) {} +} + +void usbd_rndis_data_recv_done(void) +{ +} + +void rndis_input_poll(void) +{ + rndisif_input(&rndis_netif); +} +#endif /* RT_USING_LWIP */ + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: +#ifdef RT_USING_LWIP + eth_device_linkchange(&rndis_dev, RT_TRUE); +#endif + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +struct usbd_interface intf0; +struct usbd_interface intf1; + +void cdc_rndis_init(uint8_t busid, uint32_t reg_base) +{ +#ifdef RT_USING_LWIP + rt_usbd_rndis_init(); +#else + rndis_lwip_init(); +#endif + usbd_desc_register(busid, cdc_descriptor); + usbd_add_interface(busid, usbd_rndis_init_intf(&intf0, CDC_OUT_EP, CDC_IN_EP, CDC_INT_EP, mac)); + usbd_add_interface(busid, usbd_rndis_init_intf(&intf1, CDC_OUT_EP, CDC_IN_EP, CDC_INT_EP, mac)); + usbd_initialize(busid, reg_base, usbd_event_handler); +} diff --git a/components/drivers/usb/cherryusb/demo/dfu_st_cubemx_main.c b/components/drivers/usb/cherryusb/demo/dfu_st_cubemx_main.c new file mode 100644 index 00000000000..b845af3eda9 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/dfu_st_cubemx_main.c @@ -0,0 +1,372 @@ +/* USER CODE BEGIN Header */ +/** + ****************************************************************************** + * @file : main.c + * @brief : Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2021 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under Ultimate Liberty license + * SLA0044, the "License"; You may not use this file except in compliance with + * the License. You may obtain a copy of the License at: + * www.st.com/SLA0044 + * + ****************************************************************************** + */ +/* USER CODE END Header */ +/* Includes ------------------------------------------------------------------*/ +#include "main.h" + +/* Private includes ----------------------------------------------------------*/ +/* USER CODE BEGIN Includes */ +#include "usbd_core.h" +#include "usb_dfu.h" +/* USER CODE END Includes */ + +/* Private typedef -----------------------------------------------------------*/ +/* USER CODE BEGIN PTD */ + +/* USER CODE END PTD */ + +/* Private define ------------------------------------------------------------*/ +/* USER CODE BEGIN PD */ +/* USER CODE END PD */ + +/* Private macro -------------------------------------------------------------*/ +/* USER CODE BEGIN PM */ + +/* USER CODE END PM */ + +/* Private variables ---------------------------------------------------------*/ +UART_HandleTypeDef huart1; + +PCD_HandleTypeDef hpcd_USB_FS; + +/* USER CODE BEGIN PV */ + +/* USER CODE END PV */ + +/* Private function prototypes -----------------------------------------------*/ +void SystemClock_Config(void); +static void MX_GPIO_Init(void); +static void MX_USART1_UART_Init(void); +static void MX_USB_PCD_Init(void); +/* USER CODE BEGIN PFP */ +typedef void (*pFunction)(void); +static void jump_app(void) +{ + pFunction JumpToApplication; + uint32_t JumpAddress; + + if (((*(__IO uint32_t *)USBD_DFU_APP_DEFAULT_ADD) & 0x2FFFB000) == 0x20000000) + { + /* Jump to user application */ + /*!< Jump to app reset_handler */ + JumpAddress = *(__IO uint32_t *)(USBD_DFU_APP_DEFAULT_ADD + 4); + JumpToApplication = (pFunction)JumpAddress; + + /* Initialize user application's Stack Pointer */ + __set_MSP(*(__IO uint32_t *)USBD_DFU_APP_DEFAULT_ADD); + JumpToApplication(); + } +} +/* USER CODE END PFP */ + +/* Private user code ---------------------------------------------------------*/ +/* USER CODE BEGIN 0 */ +int fputc(int ch, FILE *f) +{ + while ((USART1->SR & USART_SR_TXE) == 0) + ; + USART1->DR = ch; + return ch; +} + +void usb_dc_low_level_init(void) +{ + /* Peripheral clock enable */ + __HAL_RCC_USB_CLK_ENABLE(); + /* USB interrupt Init */ + HAL_NVIC_SetPriority(USB_LP_CAN1_RX0_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn); + +} + +uint8_t *dfu_read_flash(uint8_t *src, uint8_t *dest, uint32_t len) +{ + uint32_t i = 0; + uint8_t *psrc = src; + + for (i = 0; i < len; i++) + { + dest[i] = *psrc++; + } + /* Return a valid address to avoid HardFault */ + return (uint8_t *)(dest); +} + +uint16_t dfu_write_flash(uint8_t *src, uint8_t *dest, uint32_t len) +{ + HAL_FLASH_Unlock(); + uint32_t i = 0; + + for (i = 0; i < len; i += 4) + { + /* Device voltage range supposed to be [2.7V to 3.6V], the operation will + * be done by byte */ + if (HAL_FLASH_Program(FLASH_TYPEPROGRAM_WORD, (uint32_t)(dest + i), + *(uint32_t *)(src + i)) == HAL_OK) + { + /* Check the written value */ + if (*(uint32_t *)(src + i) != *(uint32_t *)(dest + i)) + { + /* Flash content doesn't match SRAM content */ + return (1); + } + } + else + { + /* Error occurred while writing data in Flash memory */ + return (2); + } + } + return 0; +} + +uint16_t dfu_erase_flash(uint32_t add) +{ + HAL_FLASH_Unlock(); + uint32_t PageError; + /* Variable contains Flash operation status */ + HAL_StatusTypeDef status; + FLASH_EraseInitTypeDef eraseinitstruct; + + eraseinitstruct.TypeErase = FLASH_TYPEERASE_PAGES; + eraseinitstruct.PageAddress = add; + eraseinitstruct.NbPages = 1U; + status = HAL_FLASHEx_Erase(&eraseinitstruct, &PageError); + return 0; +} + +void dfu_leave(void) +{ + NVIC_SystemReset(); +} + +/* USER CODE END 0 */ + +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + /* USER CODE BEGIN 1 */ + jump_app(); + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + MX_USART1_UART_Init(); + //MX_USB_PCD_Init(); + /* USER CODE BEGIN 2 */ + + +// extern void cdc_acm_msc_init(void); +// cdc_acm_msc_init(); + extern void dfu_flash_init(void); + dfu_flash_init(); + + /* USER CODE END 2 */ + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) { + /* USER CODE END WHILE */ + + /* USER CODE BEGIN 3 */ +// extern void cdc_acm_data_send_with_dtr_test(void); +// cdc_acm_data_send_with_dtr_test(); +// HAL_Delay(100); + } + /* USER CODE END 3 */ +} + +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; + + /** Initializes the RCC Oscillators according to the specified parameters + * in the RCC_OscInitTypeDef structure. + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSEPredivValue = RCC_HSE_PREDIV_DIV1; + RCC_OscInitStruct.HSIState = RCC_HSI_ON; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL9; + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + Error_Handler(); + } + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK + |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + { + Error_Handler(); + } + PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB; + PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) + { + Error_Handler(); + } +} + +/** + * @brief USART1 Initialization Function + * @param None + * @retval None + */ +static void MX_USART1_UART_Init(void) +{ + + /* USER CODE BEGIN USART1_Init 0 */ + + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + huart1.Init.BaudRate = 115200; + huart1.Init.WordLength = UART_WORDLENGTH_8B; + huart1.Init.StopBits = UART_STOPBITS_1; + huart1.Init.Parity = UART_PARITY_NONE; + huart1.Init.Mode = UART_MODE_TX_RX; + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + if (HAL_UART_Init(&huart1) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + +/** + * @brief USB Initialization Function + * @param None + * @retval None + */ +static void MX_USB_PCD_Init(void) +{ + + /* USER CODE BEGIN USB_Init 0 */ + + /* USER CODE END USB_Init 0 */ + + /* USER CODE BEGIN USB_Init 1 */ + + /* USER CODE END USB_Init 1 */ + hpcd_USB_FS.Instance = USB; + hpcd_USB_FS.Init.dev_endpoints = 8; + hpcd_USB_FS.Init.speed = PCD_SPEED_FULL; + hpcd_USB_FS.Init.low_power_enable = DISABLE; + hpcd_USB_FS.Init.lpm_enable = DISABLE; + hpcd_USB_FS.Init.battery_charging_enable = DISABLE; + if (HAL_PCD_Init(&hpcd_USB_FS) != HAL_OK) + { + Error_Handler(); + } + /* USER CODE BEGIN USB_Init 2 */ + + /* USER CODE END USB_Init 2 */ + +} + +/** + * @brief GPIO Initialization Function + * @param None + * @retval None + */ +static void MX_GPIO_Init(void) +{ + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOD_CLK_ENABLE(); + __HAL_RCC_GPIOA_CLK_ENABLE(); + +} + +/* USER CODE BEGIN 4 */ + +/* USER CODE END 4 */ + +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) { + } + /* USER CODE END Error_Handler_Debug */ +} + +#ifdef USE_FULL_ASSERT +/** + * @brief Reports the name of the source file and the source line number + * where the assert_param error has occurred. + * @param file: pointer to the source file name + * @param line: assert_param error line source number + * @retval None + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* USER CODE BEGIN 6 */ + /* User can add his own implementation to report the file name and line number, + ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* USER CODE END 6 */ +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/components/drivers/usb/cherryusb/demo/dfu_with_st_tool_template.c b/components/drivers/usb/cherryusb/demo/dfu_with_st_tool_template.c new file mode 100644 index 00000000000..1d947024fd7 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/dfu_with_st_tool_template.c @@ -0,0 +1,177 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_dfu.h" + +#define USBD_VID 0x0483 +#define USBD_PID 0xDF11 +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#define FLASH_DESC_STR "@Internal Flash /0x08000000/16*001Ka,112*01Kg" + +#define USB_CONFIG_SIZE (9 + 9 + 9) + +const uint8_t dfu_flash_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + DFU_DESCRIPTOR_INIT(), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x1e, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'D', 0x00, /* wcChar0 */ + 'F', 0x00, /* wcChar1 */ + 'U', 0x00, /* wcChar2 */ + 'W', 0x00, /* wcChar3 */ + 'i', 0x00, /* wcChar4 */ + 't', 0x00, /* wcChar5 */ + 'h', 0x00, /* wcChar6 */ + 's', 0x00, /* wcChar7 */ + 't', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 't', 0x00, /* wcChar10 */ + 'o', 0x00, /* wcChar11 */ + 'o', 0x00, /* wcChar12 */ + 'l', 0x00, /* wcChar13 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ + /////////////////////////////////////// + /// string4 descriptor + /////////////////////////////////////// + 0x60, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '@', 0x00, /* wcChar0 */ + 'I', 0x00, /* wcChar1 */ + 'n', 0x00, /* wcChar2 */ + 't', 0x00, /* wcChar3 */ + 'e', 0x00, /* wcChar4 */ + 'r', 0x00, /* wcChar5 */ + 'n', 0x00, /* wcChar6 */ + 'a', 0x00, /* wcChar7 */ + 'l', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'F', 0x00, /* wcChar10 */ + 'l', 0x00, /* wcChar11*/ + 'a', 0x00, /* wcChar12 */ + 's', 0x00, /* wcChar13 */ + 'h', 0x00, /* wcChar14 */ + ' ', 0x00, /* wcChar15 */ + ' ', 0x00, /* wcChar16 */ + ' ', 0x00, /* wcChar17 */ + '/', 0x00, /* wcChar18 */ + '0', 0x00, /* wcChar19 */ + 'x', 0x00, /* wcChar20 */ + '0', 0x00, /* wcChar21*/ + '8', 0x00, /* wcChar22 */ + '0', 0x00, /* wcChar23 */ + '0', 0x00, /* wcChar24 */ + '0', 0x00, /* wcChar25 */ + '0', 0x00, /* wcChar26 */ + '0', 0x00, /* wcChar27 */ + '0', 0x00, /* wcChar28 */ + '/', 0x00, /* wcChar29 */ + '1', 0x00, /* wcChar30 */ + '6', 0x00, /* wcChar31*/ + '*', 0x00, /* wcChar32 */ + '0', 0x00, /* wcChar33 */ + '0', 0x00, /* wcChar34 */ + '1', 0x00, /* wcChar35 */ + 'K', 0x00, /* wcChar36 */ + 'a', 0x00, /* wcChar37 */ + ',', 0x00, /* wcChar38 */ + '1', 0x00, /* wcChar39 */ + '1', 0x00, /* wcChar40 */ + '2', 0x00, /* wcChar41*/ + '*', 0x00, /* wcChar42 */ + '0', 0x00, /* wcChar43 */ + '1', 0x00, /* wcChar44 */ + 'K', 0x00, /* wcChar45 */ + 'g', 0x00, /* wcChar46 */ + +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +struct usbd_interface intf0; + +void dfu_flash_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, dfu_flash_descriptor); + usbd_add_interface(busid, usbd_dfu_init_intf(&intf0)); + usbd_initialize(busid, reg_base, usbd_event_handler); +} diff --git a/components/drivers/usb/cherryusb/demo/hid_custom_inout_template.c b/components/drivers/usb/cherryusb/demo/hid_custom_inout_template.c new file mode 100644 index 00000000000..d5c3b7e0c0f --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/hid_custom_inout_template.c @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2022 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ + +#include "usbd_core.h" +#include "usbd_hid.h" + + +/*!< hidraw in endpoint */ +#define HIDRAW_IN_EP 0x81 +#ifdef CONFIG_USB_HS +#define HIDRAW_IN_EP_SIZE 1024 +#define HIDRAW_IN_INTERVAL 4 +#else +#define HIDRAW_IN_EP_SIZE 64 +#define HIDRAW_IN_INTERVAL 10 +#endif +/*!< hidraw out endpoint */ +#define HIDRAW_OUT_EP 0x02 +#ifdef CONFIG_USB_HS +#define HIDRAW_OUT_EP_SIZE 1024 +#define HIDRAW_OUT_EP_INTERVAL 4 +#else +#define HIDRAW_OUT_EP_SIZE 64 +#define HIDRAW_OUT_EP_INTERVAL 10 +#endif + +/*!< config descriptor size */ +#define USB_HID_CONFIG_DESC_SIZ (9 + 9 + 9 + 7 + 7) + +/*!< custom hid report descriptor size */ +#define HID_CUSTOM_REPORT_DESC_SIZE 38 + +/*!< global descriptor */ +static const uint8_t hid_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + /************** Descriptor of Custom interface *****************/ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x02, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Custom HID ********************/ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_CUSTOM_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Custom in endpoint ********************/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ + HIDRAW_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + WBVAL(HIDRAW_IN_EP_SIZE), /* wMaxPacketSize: 4 Byte max */ + HIDRAW_IN_INTERVAL, /* bInterval: Polling Interval */ + /******************** Descriptor of Custom out endpoint ********************/ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ + HIDRAW_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + WBVAL(HIDRAW_OUT_EP_SIZE), /* wMaxPacketSize: 4 Byte max */ + HIDRAW_OUT_EP_INTERVAL, /* bInterval: Polling Interval */ + /* 73 */ + /* + * string0 descriptor + */ + USB_LANGID_INIT(USBD_LANGID_STRING), + /* + * string1 descriptor + */ + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /* + * string2 descriptor + */ + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'H', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'D', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /* + * string3 descriptor + */ + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /* + * device qualifier descriptor + */ + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +/*!< custom hid report descriptor */ +static const uint8_t hid_custom_report_desc[HID_CUSTOM_REPORT_DESC_SIZE] = { +#ifdef CONFIG_USB_HS + /* USER CODE BEGIN 0 */ + 0x06, 0x00, 0xff, /* USAGE_PAGE (Vendor Defined Page 1) */ + 0x09, 0x01, /* USAGE (Vendor Usage 1) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + 0x85, 0x02, /* REPORT ID (0x02) */ + 0x09, 0x02, /* USAGE (Vendor Usage 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /*LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x96, 0xff, 0x03, /* REPORT_COUNT (63) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + /* <___________________________________________________> */ + 0x85, 0x01, /* REPORT ID (0x01) */ + 0x09, 0x03, /* USAGE (Vendor Usage 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x25, 0xff, /* LOGICAL_MAXIMUM (255) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x96, 0xff, 0x03, /* REPORT_COUNT (63) */ + 0x91, 0x02, /* OUTPUT (Data,Var,Abs) */ + /* USER CODE END 0 */ + 0xC0 /* END_COLLECTION */ +#else + /* USER CODE BEGIN 0 */ + 0x06, 0x00, 0xff, /* USAGE_PAGE (Vendor Defined Page 1) */ + 0x09, 0x01, /* USAGE (Vendor Usage 1) */ + 0xa1, 0x01, /* COLLECTION (Application) */ + 0x85, 0x02, /* REPORT ID (0x02) */ + 0x09, 0x01, /* USAGE (Vendor Usage 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x26, 0xff, 0x00, /* LOGICAL_MAXIMUM (255) */ + 0x95, 0x40 - 1, /* REPORT_COUNT (63) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x81, 0x02, /* INPUT (Data,Var,Abs) */ + /* <___________________________________________________> */ + 0x85, 0x01, /* REPORT ID (0x01) */ + 0x09, 0x01, /* USAGE (Vendor Usage 1) */ + 0x15, 0x00, /* LOGICAL_MINIMUM (0) */ + 0x26, 0xff, 0x00, /* LOGICAL_MAXIMUM (255) */ + 0x95, 0x40 - 1, /* REPORT_COUNT (63) */ + 0x75, 0x08, /* REPORT_SIZE (8) */ + 0x91, 0x02, /* OUTPUT (Data,Var,Abs) */ + /* USER CODE END 0 */ + 0xC0 /* END_COLLECTION */ +#endif +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[HIDRAW_OUT_EP_SIZE]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t send_buffer[HIDRAW_IN_EP_SIZE]; + +#define HID_STATE_IDLE 0 +#define HID_STATE_BUSY 1 + +/*!< hid state ! Data can be sent only when state is idle */ +static volatile uint8_t custom_state; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, HIDRAW_OUT_EP, read_buffer, HIDRAW_OUT_EP_SIZE); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +static void usbd_hid_custom_in_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)busid; + (void)ep; + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + custom_state = HID_STATE_IDLE; +} + +static void usbd_hid_custom_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + usbd_ep_start_read(busid, ep, read_buffer, HIDRAW_IN_EP_SIZE); + read_buffer[0] = 0x02; /* IN: report id */ + usbd_ep_start_write(busid, HIDRAW_IN_EP, read_buffer, nbytes); +} + +static struct usbd_endpoint custom_in_ep = { + .ep_cb = usbd_hid_custom_in_callback, + .ep_addr = HIDRAW_IN_EP +}; + +static struct usbd_endpoint custom_out_ep = { + .ep_cb = usbd_hid_custom_out_callback, + .ep_addr = HIDRAW_OUT_EP +}; + +/* function ------------------------------------------------------------------*/ +/** + * @brief hid custom init + * @pre none + * @param[in] none + * @retval none + */ +struct usbd_interface intf0; + +void hid_custom_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, hid_descriptor); + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_custom_report_desc, HID_CUSTOM_REPORT_DESC_SIZE)); + usbd_add_endpoint(busid, &custom_in_ep); + usbd_add_endpoint(busid, &custom_out_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} diff --git a/components/drivers/usb/cherryusb/demo/hid_keyboard_template.c b/components/drivers/usb/cherryusb/demo/hid_keyboard_template.c new file mode 100644 index 00000000000..5e106f2614e --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/hid_keyboard_template.c @@ -0,0 +1,247 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" + +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#define HID_INT_EP 0x81 +#define HID_INT_EP_SIZE 8 +#define HID_INT_EP_INTERVAL 10 + +#define USB_HID_CONFIG_DESC_SIZ 34 +#define HID_KEYBOARD_REPORT_DESC_SIZE 63 + +static const uint8_t hid_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ + 0x00, + HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ + /* 34 */ + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'H', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'D', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +/* USB HID device Configuration Descriptor */ +static uint8_t hid_desc[9] __ALIGN_END = { + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_KEYBOARD_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, +}; + +static const uint8_t hid_keyboard_report_desc[HID_KEYBOARD_REPORT_DESC_SIZE] = { + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x06, // USAGE (Keyboard) + 0xa1, 0x01, // COLLECTION (Application) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0xe0, // USAGE_MINIMUM (Keyboard LeftControl) + 0x29, 0xe7, // USAGE_MAXIMUM (Keyboard Right GUI) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x75, 0x01, // REPORT_SIZE (1) + 0x95, 0x08, // REPORT_COUNT (8) + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x08, // REPORT_SIZE (8) + 0x81, 0x03, // INPUT (Cnst,Var,Abs) + 0x95, 0x05, // REPORT_COUNT (5) + 0x75, 0x01, // REPORT_SIZE (1) + 0x05, 0x08, // USAGE_PAGE (LEDs) + 0x19, 0x01, // USAGE_MINIMUM (Num Lock) + 0x29, 0x05, // USAGE_MAXIMUM (Kana) + 0x91, 0x02, // OUTPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x03, // REPORT_SIZE (3) + 0x91, 0x03, // OUTPUT (Cnst,Var,Abs) + 0x95, 0x06, // REPORT_COUNT (6) + 0x75, 0x08, // REPORT_SIZE (8) + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0xFF, // LOGICAL_MAXIMUM (255) + 0x05, 0x07, // USAGE_PAGE (Keyboard) + 0x19, 0x00, // USAGE_MINIMUM (Reserved (no event indicated)) + 0x29, 0x65, // USAGE_MAXIMUM (Keyboard Application) + 0x81, 0x00, // INPUT (Data,Ary,Abs) + 0xc0 // END_COLLECTION +}; + +#define HID_STATE_IDLE 0 +#define HID_STATE_BUSY 1 + +/*!< hid state ! Data can be sent only when state is idle */ +static volatile uint8_t hid_state = HID_STATE_IDLE; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + hid_state = HID_STATE_IDLE; + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_hid_int_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + hid_state = HID_STATE_IDLE; +} + +static struct usbd_endpoint hid_in_ep = { + .ep_cb = usbd_hid_int_callback, + .ep_addr = HID_INT_EP +}; + +struct usbd_interface intf0; + +void hid_keyboard_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, hid_descriptor); + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_keyboard_report_desc, HID_KEYBOARD_REPORT_DESC_SIZE)); + usbd_add_endpoint(busid, &hid_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[64]; + +void hid_keyboard_test(uint8_t busid) +{ + const uint8_t sendbuffer[8] = { 0x00, 0x00, HID_KBD_USAGE_A, 0x00, 0x00, 0x00, 0x00, 0x00 }; + + memcpy(write_buffer, sendbuffer, 8); + int ret = usbd_ep_start_write(busid, HID_INT_EP, write_buffer, 8); + if (ret < 0) { + return; + } + hid_state = HID_STATE_BUSY; + while (hid_state == HID_STATE_BUSY) { + } +} diff --git a/components/drivers/usb/cherryusb/demo/hid_mouse_template.c b/components/drivers/usb/cherryusb/demo/hid_mouse_template.c new file mode 100644 index 00000000000..d335601b9bf --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/hid_mouse_template.c @@ -0,0 +1,281 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" + +/*!< endpoint address */ +#define HID_INT_EP 0x81 +#define HID_INT_EP_SIZE 4 +#define HID_INT_EP_INTERVAL 10 + +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +/*!< config descriptor size */ +#define USB_HID_CONFIG_DESC_SIZ 34 +/*!< report descriptor size */ +#define HID_MOUSE_REPORT_DESC_SIZE 74 + +/*!< global descriptor */ +const uint8_t hid_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_HID_CONFIG_DESC_SIZ, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x00, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ + 0x00, + HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ + /* 34 */ + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'H', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'D', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +/*!< hid mouse report descriptor */ +static const uint8_t hid_mouse_report_desc[HID_MOUSE_REPORT_DESC_SIZE] = { + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x02, // USAGE (Mouse) + 0xA1, 0x01, // COLLECTION (Application) + 0x09, 0x01, // USAGE (Pointer) + + 0xA1, 0x00, // COLLECTION (Physical) + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x03, // USAGE_MAXIMUM (Button 3) + + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x03, // REPORT_COUNT (3) + 0x75, 0x01, // REPORT_SIZE (1) + + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x05, // REPORT_SIZE (5) + 0x81, 0x01, // INPUT (Cnst,Var,Abs) + + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + 0x09, 0x38, + + 0x15, 0x81, // LOGICAL_MINIMUM (-127) + 0x25, 0x7F, // LOGICAL_MAXIMUM (127) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x03, // REPORT_COUNT (2) + + 0x81, 0x06, // INPUT (Data,Var,Rel) + 0xC0, 0x09, + 0x3c, 0x05, + 0xff, 0x09, + + 0x01, 0x15, + 0x00, 0x25, + 0x01, 0x75, + 0x01, 0x95, + + 0x02, 0xb1, + 0x22, 0x75, + 0x06, 0x95, + 0x01, 0xb1, + + 0x01, 0xc0 // END_COLLECTION +}; + +/*!< mouse report struct */ +struct hid_mouse { + uint8_t buttons; + int8_t x; + int8_t y; + int8_t wheel; +}; + +/*!< mouse report */ +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX struct hid_mouse mouse_cfg; + +#define HID_STATE_IDLE 0 +#define HID_STATE_BUSY 1 + +/*!< hid state ! Data can be sent only when state is idle */ +static volatile uint8_t hid_state = HID_STATE_IDLE; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + hid_state = HID_STATE_IDLE; + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +/* function ------------------------------------------------------------------*/ +static void usbd_hid_int_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + hid_state = HID_STATE_IDLE; +} + +/*!< endpoint call back */ +static struct usbd_endpoint hid_in_ep = { + .ep_cb = usbd_hid_int_callback, + .ep_addr = HID_INT_EP +}; + +struct usbd_interface intf0; + +void hid_mouse_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, hid_descriptor); + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_mouse_report_desc, HID_MOUSE_REPORT_DESC_SIZE)); + usbd_add_endpoint(busid, &hid_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); + + /*!< init mouse report data */ + mouse_cfg.buttons = 0; + mouse_cfg.wheel = 0; + mouse_cfg.x = 0; + mouse_cfg.y = 0; +} + +/** + * @brief hid mouse test + * @pre none + * @param[in] none + * @retval none + */ +void hid_mouse_test(uint8_t busid) +{ + int counter = 0; + while (counter < 1000) { + /*!< move mouse pointer */ + mouse_cfg.x += 40; + mouse_cfg.y += 0; + + int ret = usbd_ep_start_write(busid, HID_INT_EP, (uint8_t *)&mouse_cfg, 4); + if (ret < 0) { + return; + } + hid_state = HID_STATE_BUSY; + while (hid_state == HID_STATE_BUSY) { + } + + counter++; + } +} diff --git a/components/drivers/usb/cherryusb/demo/midi_template.c b/components/drivers/usb/cherryusb/demo/midi_template.c new file mode 100644 index 00000000000..d09a94305a6 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/midi_template.c @@ -0,0 +1,214 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_midi.h" + +#define MIDI_OUT_EP 0x02 +#define MIDI_IN_EP 0x81 + +#define USBD_VID 0x0d28 +#define USBD_PID 0x0404 +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#define USB_CONFIG_SIZE (9 + 9 + 9 + 9 + 7 + MIDI_SIZEOF_JACK_DESC + 9 + 5 + 9 + 5) + +#ifdef CONFIG_USB_HS +#define MIDI_EP_MPS 512 +#else +#define MIDI_EP_MPS 64 +#endif + +const uint8_t midi_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0100, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + // Standard AC Interface Descriptor + 0x09, + 0x04, + 0x00, + 0x00, + 0x00, + 0x01, + 0x01, + 0x00, + 0x00, + // Class-specific AC Interface Descriptor + 0x09, + 0x24, + 0x01, + 0x00, + 0x01, + 0x09, + 0x00, + 0x01, + 0x01, + // MIDIStreaming Interface Descriptors + 0x09, + 0x04, + 0x01, + 0x00, + 0x02, + 0x01, + 0x03, + 0x00, + 0x00, + // Class-Specific MS Interface Header Descriptor + 0x07, + 0x24, + 0x01, + 0x00, + 0x01, + WBVAL(65), + + // MIDI_IN_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EMBEDDED, 0x01), + // MIDI_IN_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EXTERNAL, 0x02), + // MIDI_OUT_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EMBEDDED, 0x03, 0x02), + // MIDI_OUT_JACK_DESCRIPTOR_INIT(MIDI_JACK_TYPE_EXTERNAL, 0x04, 0x01), + MIDI_JACK_DESCRIPTOR_INIT(0x01), + // OUT endpoint descriptor + 0x09, 0x05, MIDI_OUT_EP, 0x02, WBVAL(MIDI_EP_MPS), 0x00, 0x00, 0x00, + 0x05, 0x25, 0x01, 0x01, 0x01, + + // IN endpoint descriptor + 0x09, 0x05, MIDI_IN_EP, 0x02, WBVAL(MIDI_EP_MPS), 0x00, 0x00, 0x00, + 0x05, 0x25, 0x01, 0x01, 0x03, + + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x28, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'M', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'D', 0x00, /* wcChar12 */ + 'I', 0x00, /* wcChar13 */ + ' ', 0x00, /* wcChar14 */ + 'D', 0x00, /* wcChar15 */ + 'E', 0x00, /* wcChar16 */ + 'M', 0x00, /* wcChar17 */ + 'O', 0x00, /* wcChar18 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '1', 0x00, /* wcChar3 */ + '0', 0x00, /* wcChar4 */ + '3', 0x00, /* wcChar5 */ + '1', 0x00, /* wcChar6 */ + '0', 0x00, /* wcChar7 */ + '0', 0x00, /* wcChar8 */ + '0', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[MIDI_EP_MPS]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[MIDI_EP_MPS]; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + usbd_ep_start_read(busid, MIDI_OUT_EP, read_buffer, MIDI_EP_MPS); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_midi_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + usbd_ep_start_read(busid, MIDI_OUT_EP, read_buffer, MIDI_EP_MPS); +} + +void usbd_midi_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ +} + +struct usbd_interface intf0; +struct usbd_interface intf1; + +struct usbd_endpoint midi_out_ep = { + .ep_addr = MIDI_OUT_EP, + .ep_cb = usbd_midi_bulk_out +}; + +struct usbd_endpoint midi_in_ep = { + .ep_addr = MIDI_IN_EP, + .ep_cb = usbd_midi_bulk_in +}; + +void midi_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, midi_descriptor); + usbd_add_interface(busid, &intf0); + usbd_add_interface(busid, &intf1); + usbd_add_endpoint(busid, &midi_out_ep); + usbd_add_endpoint(busid, &midi_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/msc_ram_template.c b/components/drivers/usb/cherryusb/demo/msc_ram_template.c new file mode 100644 index 00000000000..933cd884a75 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/msc_ram_template.c @@ -0,0 +1,165 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_msc.h" + +#define MSC_IN_EP 0x81 +#define MSC_OUT_EP 0x02 + +#define USBD_VID 0xFFFF +#define USBD_PID 0xFFFF +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#define USB_CONFIG_SIZE (9 + MSC_DESCRIPTOR_LEN) + +#ifdef CONFIG_USB_HS +#define MSC_MAX_MPS 512 +#else +#define MSC_MAX_MPS 64 +#endif + +const uint8_t msc_ram_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + MSC_DESCRIPTOR_INIT(0x00, MSC_OUT_EP, MSC_IN_EP, MSC_MAX_MPS, 0x02), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'M', 0x00, /* wcChar10 */ + 'S', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +#define BLOCK_SIZE 512 +#define BLOCK_COUNT 10 + +typedef struct +{ + uint8_t BlockSpace[BLOCK_SIZE]; +} BLOCK_TYPE; + +BLOCK_TYPE mass_block[BLOCK_COUNT]; + +void usbd_msc_get_cap(uint8_t busid, uint8_t lun, uint32_t *block_num, uint32_t *block_size) +{ + *block_num = 1000; //Pretend having so many buffer,not has actually. + *block_size = BLOCK_SIZE; +} +int usbd_msc_sector_read(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length) +{ + if (sector < BLOCK_COUNT) + memcpy(buffer, mass_block[sector].BlockSpace, length); + return 0; +} + +int usbd_msc_sector_write(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length) +{ + if (sector < BLOCK_COUNT) + memcpy(mass_block[sector].BlockSpace, buffer, length); + return 0; +} + +struct usbd_interface intf0; + +void msc_ram_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, msc_ram_descriptor); + usbd_add_interface(busid, usbd_msc_init_intf(busid, &intf0, MSC_OUT_EP, MSC_IN_EP)); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} diff --git a/components/drivers/usb/cherryusb/demo/msc_storage_template.c b/components/drivers/usb/cherryusb/demo/msc_storage_template.c new file mode 100644 index 00000000000..a335164356b --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/msc_storage_template.c @@ -0,0 +1,172 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_msc.h" + +#ifdef __RT_THREAD_H__ + +#define MSC_IN_EP 0x81 +#define MSC_OUT_EP 0x02 + +#define USBD_VID 0xFFFF +#define USBD_PID 0xFFFF +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#define USB_CONFIG_SIZE (9 + MSC_DESCRIPTOR_LEN) + +#ifdef CONFIG_USB_HS +#define MSC_MAX_MPS 512 +#else +#define MSC_MAX_MPS 64 +#endif + + +const uint8_t msc_storage_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_1_1, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0200, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + MSC_DESCRIPTOR_INIT(0x00, MSC_OUT_EP, MSC_IN_EP, MSC_MAX_MPS, 0x02), + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'M', 0x00, /* wcChar10 */ + 'S', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '2', 0x00, /* wcChar3 */ + '1', 0x00, /* wcChar4 */ + '2', 0x00, /* wcChar5 */ + '3', 0x00, /* wcChar6 */ + '4', 0x00, /* wcChar7 */ + '5', 0x00, /* wcChar8 */ + '6', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +struct usbd_interface intf0; + +/* assume the block device is 512M */ +#define BLOCK_DEV_NAME "sd0" +#define BLOCK_SIZE 512U +#define BLOCK_COUNT 0x1024U * 0x1024U +static rt_device_t blk_dev = RT_NULL; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_msc_get_cap(uint8_t busid, uint8_t lun, uint32_t *block_num, uint32_t *block_size) +{ + *block_num = BLOCK_COUNT; + *block_size = BLOCK_SIZE; +} + +int usbd_msc_sector_read(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length) +{ + rt_device_read(blk_dev, sector, buffer, length / BLOCK_SIZE); + return 0; +} + +int usbd_msc_sector_write(uint8_t busid, uint8_t lun, uint32_t sector, uint8_t *buffer, uint32_t length) +{ + rt_device_write(blk_dev, sector, buffer, length / BLOCK_SIZE); + return 0; +} + +void msc_storage_init(uint8_t busid, uint32_t reg_base) +{ + rt_err_t res; + + blk_dev = rt_device_find(BLOCK_DEV_NAME); + RT_ASSERT(blk_dev); + + res = rt_device_open(blk_dev, RT_DEVICE_OFLAG_RDWR); + RT_ASSERT(res == RT_EOK); + + usbd_desc_register(busid, msc_storage_descriptor); + usbd_add_interface(busid, usbd_msc_init_intf(busid, &intf0, MSC_OUT_EP, MSC_IN_EP)); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} +#endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/music_16k_ac1.h b/components/drivers/usb/cherryusb/demo/music_16k_ac1.h new file mode 100644 index 00000000000..86807d79971 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/music_16k_ac1.h @@ -0,0 +1,109183 @@ +const unsigned char music[] = { + 0x24, 0xF1, 0x15, 0xF8, 0x83, 0xF6, 0x46, 0xEF, 0xAB, 0xE6, 0x6B, 0xE0, 0x69, 0xE0, 0xAD, 0xE4, + 0x8A, 0xE8, 0x75, 0xEB, 0xCC, 0xEF, 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0xF9, 0xDD, 0xEE, +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/music_16k_ac2.h b/components/drivers/usb/cherryusb/demo/music_16k_ac2.h new file mode 100644 index 00000000000..cb8388d7f96 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/music_16k_ac2.h @@ -0,0 +1,78605 @@ +const unsigned char music[943233] = { + 0x43, 0xEC, 0xC0, 0xF9, 0xC7, 0xFD, 0x22, 0x06, 0x04, 0x13, 0x76, 0xFA, + 0x90, 0x17, 0x87, 0xF6, 0x3A, 0x12, 0x3E, 0xFA, 0xCA, 0x10, 0x28, 0x02, + 0xF7, 0x0D, 0xFA, 0x0F, 0xFA, 0x0D, 0x8A, 0x16, 0x71, 0x12, 0xAC, 0x1A, + 0x82, 0x08, 0x5F, 0x17, 0x89, 0xFD, 0x5E, 0x22, 0xB3, 0x01, 0x10, 0x2F, + 0x43, 0x07, 0xC4, 0x1F, 0x4E, 0x08, 0x45, 0x15, 0x5A, 0xFC, 0x81, 0x1F, + 0xCA, 0xF8, 0x14, 0x21, 0x16, 0x0E, 0x3C, 0x11, 0xCF, 0x20, 0x05, 0x0F, + 0x32, 0x1C, 0x78, 0x20, 0x55, 0x0E, 0x34, 0x2E, 0xFF, 0x0C, 0xE2, 0x2E, + 0x22, 0x11, 0xD7, 0x28, 0x09, 0x0E, 0xDA, 0x22, 0x1B, 0x03, 0xB3, 0x1F, + 0x2E, 0xF9, 0x95, 0x21, 0x27, 0x02, 0x55, 0x1F, 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0x2F, 0x17, 0x8F, 0xFB, 0x4A, 0x10, 0x58, 0xEC, 0xB0, 0xF8, + 0x87, 0xE3, 0x0E, 0xEC, 0x9D, 0xD9, 0x6E, 0xE5, 0xA0, 0xC7, 0xEB, 0xD7, + 0x0B, 0xC0, 0x4D, 0xDB, 0x66, 0xCB, 0x49, 0xEE, 0x24, 0xDF, 0xBC, 0xF9, + 0x21, 0xF3, 0xED, 0xFE, 0xB1, 0x01, 0xD0, 0x08, 0x57, 0xFF, 0xC6, 0x05, + 0x3B, 0xEF, 0x93, 0xF3, 0x77, 0xE7, 0x51, 0xE7, 0x19, 0xED, 0xCC, 0xDB, + 0x12, 0xEF, 0x44, 0xD2, 0x2A, 0xE6, 0x6A, 0xD6, 0x27, 0xDA, 0xFB, 0xD7, + 0xBA, 0xCE, 0x41, 0xCB, 0xBA, 0xC6, 0x4F, 0xC0, 0x34, 0xCA, 0xCC, 0xBF, + 0x38, 0xD2, 0x23, 0xBF, 0x4C, 0xD5, 0xE1, 0xC2, 0x72, 0xD5, 0xBB, 0xC7, + 0x2C, 0xE1, 0xE2, 0xCA, 0xE3, 0xF1, 0x75, 0xD0, 0x45, 0xEE, 0x82, 0xC8, + 0xD4, 0xF8, 0x61, 0xC9, 0xB9, 0x08, 0x65, 0xDA, 0x61, 0xFD, 0x07, 0xE6, + 0xE1, 0xEF, 0x06, 0xEE, 0x50, 0xEC, 0x68, 0xF2, 0xA8 +}; diff --git a/components/drivers/usb/cherryusb/demo/pic_data.h b/components/drivers/usb/cherryusb/demo/pic_data.h new file mode 100644 index 00000000000..3a009c12bac --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/pic_data.h @@ -0,0 +1,1146 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __PIC_DATA_H_ +#define __PIC_DATA_H_ + +const unsigned char jpeg_data[8493] = { + 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x48, + 0x00, 0x48, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x0D, 0x09, 0x0A, 0x0B, 0x0A, 0x08, 0x0D, + 0x0B, 0x0A, 0x0B, 0x0E, 0x0E, 0x0D, 0x0F, 0x13, 0x20, 0x15, 0x13, 0x12, 0x12, 0x13, 0x27, 0x1C, + 0x1E, 0x17, 0x20, 0x2E, 0x29, 0x31, 0x30, 0x2E, 0x29, 0x2D, 0x2C, 0x33, 0x3A, 0x4A, 0x3E, 0x33, + 0x36, 0x46, 0x37, 0x2C, 0x2D, 0x40, 0x57, 0x41, 0x46, 0x4C, 0x4E, 0x52, 0x53, 0x52, 0x32, 0x3E, + 0x5A, 0x61, 0x5A, 0x50, 0x60, 0x4A, 0x51, 0x52, 0x4F, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x0E, 0x0E, + 0x0E, 0x13, 0x11, 0x13, 0x26, 0x15, 0x15, 0x26, 0x4F, 0x35, 0x2D, 0x35, 0x4F, 0x4F, 0x4F, 0x4F, + 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, + 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, + 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0x4F, 0xFF, 0xC0, + 0x00, 0x11, 0x08, 0x00, 0xF0, 0x01, 0x40, 0x03, 0x01, 0x22, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, + 0x01, 0xFF, 0xC4, 0x00, 0x1B, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x01, 0x03, 0x04, 0x05, 0x06, 0x07, 0xFF, 0xC4, + 0x00, 0x3B, 0x10, 0x01, 0x00, 0x02, 0x01, 0x02, 0x03, 0x05, 0x06, 0x04, 0x05, 0x04, 0x02, 0x02, + 0x03, 0x00, 0x00, 0x01, 0x00, 0x02, 0x03, 0x04, 0x11, 0x05, 0x21, 0x31, 0x12, 0x41, 0x51, 0x61, + 0x71, 0x06, 0x13, 0x81, 0x91, 0xA1, 0xC1, 0x14, 0x22, 0xB1, 0xD1, 0x07, 0x23, 0x32, 0x52, 0xF0, + 0x33, 0x42, 0x72, 0xE1, 0x15, 0x62, 0x24, 0xF1, 0x43, 0x53, 0xB2, 0xFF, 0xC4, 0x00, 0x1A, 0x01, + 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0xFF, 0xC4, 0x00, 0x23, 0x11, 0x01, 0x01, 0x00, 0x02, + 0x02, 0x03, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x02, 0x11, + 0x03, 0x21, 0x12, 0x31, 0x41, 0x13, 0x22, 0x51, 0x04, 0x33, 0x14, 0x61, 0xFF, 0xDA, 0x00, 0x0C, + 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, 0x00, 0x3F, 0x00, 0xE4, 0x12, 0x0A, 0x49, 0x12, 0x0A, + 0x4F, 0x66, 0xF2, 0xC6, 0x04, 0x82, 0x90, 0xD2, 0x32, 0x49, 0xAC, 0x68, 0xD2, 0x32, 0x43, 0x48, + 0x29, 0x15, 0x43, 0x02, 0x46, 0x48, 0x69, 0x05, 0x21, 0x31, 0x81, 0x20, 0xA4, 0x91, 0x20, 0xA4, + 0x55, 0x0D, 0x1A, 0x41, 0x49, 0x22, 0x41, 0x48, 0xAB, 0x18, 0x12, 0x0A, 0x43, 0x48, 0xC9, 0x15, + 0x43, 0x46, 0x90, 0x52, 0x48, 0x90, 0x52, 0x2A, 0x86, 0x04, 0x8A, 0x3A, 0x46, 0x48, 0xAA, 0x19, + 0x45, 0x14, 0x50, 0x9C, 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, + 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, + 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x44, 0xA2, 0x8A, 0x28, 0x45, 0xBC, 0x91, 0x92, 0x48, + 0x90, 0x12, 0x74, 0x5E, 0x58, 0xC0, 0x90, 0x52, 0x48, 0x90, 0x52, 0x15, 0x0C, 0x09, 0x05, 0x21, + 0xA4, 0x64, 0x93, 0x58, 0xD1, 0xA4, 0x64, 0x86, 0x90, 0x52, 0x2A, 0x86, 0x04, 0x8C, 0x90, 0xD2, + 0x0A, 0x42, 0x63, 0x02, 0x41, 0x49, 0x22, 0x41, 0x48, 0xAA, 0x1A, 0x34, 0x82, 0x92, 0x44, 0x82, + 0x91, 0x56, 0x30, 0x24, 0x14, 0x86, 0x91, 0x92, 0x2A, 0x86, 0x8D, 0x20, 0xA4, 0x91, 0x20, 0xA4, + 0x55, 0x0C, 0x09, 0x14, 0x74, 0x8C, 0x91, 0x54, 0x32, 0x8A, 0x28, 0x55, 0xAB, 0x62, 0xDB, 0x1F, + 0xD2, 0x6E, 0xF9, 0x1B, 0xED, 0xF7, 0x22, 0x9C, 0x31, 0xC7, 0x64, 0x50, 0x4F, 0x08, 0xD1, 0x47, + 0x15, 0xBC, 0xDA, 0x44, 0xC3, 0x5C, 0xF8, 0xB7, 0xB6, 0x2B, 0x1C, 0xFC, 0x6A, 0xF7, 0x8F, 0xEF, + 0x2A, 0x4D, 0x8D, 0x05, 0xF6, 0xD1, 0xD4, 0x7A, 0x2B, 0xC9, 0xF5, 0x94, 0x75, 0xB8, 0x0C, 0x79, + 0x56, 0x86, 0xD4, 0xB7, 0x30, 0xF0, 0xF2, 0x92, 0x36, 0x99, 0x61, 0xD7, 0x91, 0x55, 0x88, 0xE7, + 0x3A, 0x0E, 0x03, 0xC3, 0x31, 0xE4, 0xDF, 0x53, 0xAA, 0xA1, 0x70, 0xFE, 0x9A, 0xA7, 0x2D, 0xFC, + 0xCE, 0xFE, 0x5D, 0xDE, 0x64, 0x8B, 0x89, 0xD8, 0xD2, 0xEB, 0x2D, 0x4C, 0x54, 0x29, 0x4B, 0x73, + 0xA8, 0x1B, 0x07, 0x97, 0xCE, 0x1E, 0x5D, 0xE8, 0x9F, 0xE2, 0x4C, 0x7C, 0x9B, 0x12, 0x29, 0xAD, + 0x4C, 0x95, 0xCD, 0x56, 0xB9, 0x01, 0x1E, 0x53, 0x32, 0xF8, 0xDA, 0xE5, 0xB6, 0x33, 0x75, 0x14, + 0xE4, 0x75, 0x8C, 0x6C, 0xF2, 0xC7, 0x51, 0x61, 0xC1, 0x93, 0x35, 0x6E, 0xE3, 0x3B, 0x5D, 0x80, + 0x53, 0xBF, 0x69, 0x12, 0x6C, 0xEC, 0xCD, 0x7D, 0x26, 0x0B, 0xE9, 0xF1, 0x2B, 0x4B, 0x76, 0xAF, + 0xCD, 0xE4, 0xF2, 0x3C, 0x25, 0x7D, 0x6E, 0x22, 0xE3, 0x92, 0xA6, 0xD6, 0x3A, 0xED, 0xDF, 0x0D, + 0xCF, 0xC7, 0xAD, 0xD4, 0x22, 0x8A, 0x28, 0xE9, 0x94, 0x51, 0x45, 0x08, 0x94, 0x51, 0x45, 0x08, + 0x94, 0x51, 0x45, 0x08, 0xBA, 0x24, 0x8C, 0x90, 0xD2, 0x0A, 0x4E, 0x9B, 0xC9, 0x1A, 0x34, 0x8C, + 0x92, 0x44, 0x80, 0x91, 0x54, 0x30, 0x24, 0x14, 0x92, 0x24, 0x14, 0x85, 0x43, 0x02, 0x41, 0x48, + 0x69, 0x19, 0x24, 0xD6, 0x34, 0x69, 0x19, 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0x45, 0xAC, 0x4B, 0xB7, 0xD3, + 0x64, 0xCB, 0x9B, 0x4A, 0xE2, 0xC3, 0x6C, 0x39, 0xEB, 0x5A, 0x83, 0xA8, 0xC5, 0x90, 0xB9, 0x93, + 0x97, 0x3E, 0x9C, 0xC7, 0xD4, 0xE7, 0x38, 0x4F, 0x68, 0xBD, 0x9F, 0xC9, 0xA2, 0xC9, 0x7D, 0x56, + 0x9C, 0xB5, 0xF0, 0x2A, 0xDC, 0x77, 0x5A, 0x3E, 0x7D, 0xE9, 0xE7, 0xF3, 0xF1, 0x98, 0xD8, 0x33, + 0xE6, 0xD3, 0x65, 0x32, 0xE9, 0xF2, 0xDF, 0x16, 0x43, 0xA5, 0xA9, 0x64, 0x7E, 0x64, 0xED, 0x38, + 0x07, 0xB4, 0xD8, 0x75, 0xF5, 0xAE, 0x8B, 0x8C, 0x25, 0x73, 0xBC, 0xA9, 0x9D, 0x00, 0xBF, 0x93, + 0xDC, 0x3E, 0x7D, 0x1F, 0x5E, 0xB9, 0xBC, 0x59, 0xF0, 0x3E, 0x58, 0xF6, 0x55, 0xE4, 0x37, 0x04, + 0x92, 0xD7, 0x0C, 0xD6, 0x1A, 0x3D, 0x4F, 0xF3, 0x6B, 0xEF, 0x34, 0xD9, 0x0E, 0xC6, 0x6C, 0x6F, + 0x3E, 0xD5, 0x5E, 0xBB, 0x79, 0x9D, 0x47, 0xC6, 0x74, 0xFE, 0xD1, 0xFB, 0x23, 0x93, 0x0B, 0x6D, + 0x57, 0x0D, 0xA7, 0x6A, 0xAF, 0x3B, 0x62, 0xAF, 0xEB, 0x5F, 0xDB, 0xE5, 0xE1, 0x38, 0xEB, 0x55, + 0x14, 0x44, 0x47, 0x64, 0x7B, 0xA7, 0x4E, 0x39, 0xE3, 0xCB, 0x8F, 0x51, 0xEA, 0xEB, 0xBD, 0x9A, + 0xE1, 0x6E, 0x87, 0xDA, 0xEC, 0xB4, 0xDF, 0xB7, 0x8F, 0x16, 0x17, 0x26, 0x2C, 0x9D, 0xD7, 0xA5, + 0x90, 0x1F, 0x88, 0xBF, 0x11, 0x9C, 0xEF, 0xB4, 0x79, 0x7F, 0x11, 0xED, 0x06, 0xBF, 0x26, 0xFB, + 0xFF, 0x00, 0x3A, 0xD5, 0x1F, 0x21, 0xD8, 0xFD, 0x27, 0x6B, 0xEC, 0xAE, 0xAB, 0x0E, 0x5E, 0x09, + 0x8F, 0x55, 0x93, 0xFD, 0x7D, 0x35, 0x1C, 0x17, 0xB3, 0xFD, 0x95, 0x5B, 0x07, 0xC0, 0x7E, 0x93, + 0xCF, 0x32, 0xDD, 0xCB, 0x92, 0xD9, 0x2D, 0xFD, 0x57, 0x5B, 0x3E, 0xAB, 0xBB, 0x30, 0xE1, 0x5C, + 0xB9, 0x32, 0x5F, 0x96, 0x8F, 0x41, 0x76, 0x51, 0x45, 0x14, 0xF6, 0x6F, 0x9C, 0x94, 0x51, 0x45, + 0x08, 0x94, 0x51, 0x45, 0x08, 0x94, 0x51, 0x45, 0x08, 0x94, 0x51, 0x45, 0x08, 0x99, 0x20, 0xA4, + 0x38, 0xC9, 0x14, 0x0D, 0x1A, 0x46, 0x48, 0x69, 0x05, 0x22, 0xA8, 0x60, 0x48, 0x29, 0x24, 0x48, + 0x29, 0x0A, 0x86, 0x04, 0x82, 0x90, 0xD2, 0x32, 0x45, 0x50, 0xD1, 0xA4, 0x64, 0x86, 0x90, 0x52, + 0x2A, 0xC6, 0x04, 0x8C, 0x90, 0xD2, 0x0A, 0x42, 0xA1, 0x81, 0x20, 0xA4, 0x91, 0x20, 0xA4, 0x9A, + 0x86, 0x8D, 0x23, 0x24, 0x34, 0x82, 0x91, 0x54, 0x30, 0x24, 0x14, 0x92, 0x24, 0x04, 0x8A, 0xA1, + 0x81, 0x20, 0xA4, 0x91, 0x20, 0xA4, 0x2A, 0x18, 0x12, 0x0A, 0x43, 0x48, 0xC9, 0x26, 0xB1, 0xA3, + 0x48, 0xF9, 0x6F, 0x7C, 0xB7, 0x6F, 0x77, 0x75, 0x03, 0xE0, 0x1B, 0x1F, 0x42, 0x3A, 0x41, 0x48, + 0x92, 0xA1, 0x81, 0x23, 0x24, 0x34, 0x82, 0x90, 0xA8, 0x6E, 0x97, 0xD9, 0xEF, 0x6B, 0x33, 0x68, + 0x8A, 0xE9, 0x75, 0xF6, 0x72, 0x69, 0xFA, 0x17, 0x79, 0xB4, 0x3C, 0x1F, 0x13, 0xEA, 0x79, 0xF4, + 0x9B, 0x7C, 0x5F, 0x80, 0x70, 0xEE, 0x3B, 0x8B, 0xF1, 0x7A, 0x2C, 0x94, 0xC3, 0xA9, 0xB1, 0xB9, + 0x7A, 0xF3, 0xA6, 0x4F, 0x5D, 0xBF, 0x5E, 0xBE, 0xB3, 0xCF, 0x92, 0x5D, 0xE1, 0x7C, 0x57, 0x57, + 0xC3, 0xB2, 0x9F, 0x87, 0xBA, 0xD1, 0x79, 0xE3, 0x5E, 0x4B, 0xE5, 0xE0, 0xCE, 0x4E, 0x4E, 0x04, + 0x7C, 0xF0, 0x74, 0xDA, 0x19, 0x7F, 0x6E, 0x9F, 0xF0, 0x79, 0xF8, 0x17, 0xB1, 0x9A, 0xAC, 0x7A, + 0x9A, 0x76, 0x33, 0x64, 0x6F, 0xB8, 0x22, 0x3D, 0xA4, 0xA0, 0x89, 0xD4, 0xD8, 0x19, 0xC1, 0xA4, + 0xF5, 0xEE, 0x2B, 0xAA, 0xD0, 0xE7, 0xE1, 0xF8, 0x74, 0x1A, 0xFA, 0xD2, 0xDE, 0xF0, 0xD9, 0xAD, + 0x9E, 0xA8, 0x1B, 0xA3, 0xD7, 0xAA, 0x73, 0x27, 0x2D, 0xC4, 0x3D, 0x95, 0xC5, 0x6D, 0x46, 0x0C, + 0xDC, 0x22, 0xBD, 0xAC, 0x62, 0x19, 0x31, 0x5A, 0xDB, 0xF4, 0xEF, 0x17, 0xA8, 0xF7, 0x9F, 0x2F, + 0x03, 0x1F, 0xF3, 0xF3, 0x06, 0xFC, 0xBD, 0xB5, 0xE5, 0xF3, 0x57, 0xFF, 0xD9 +}; + +const unsigned char jpeg_data1[6603] = { + 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x48, + 0x00, 0x48, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x09, 0x06, 0x06, 0x08, 0x06, 0x05, 0x09, + 0x08, 0x07, 0x08, 0x0A, 0x09, 0x09, 0x0A, 0x0D, 0x16, 0x0E, 0x0D, 0x0C, 0x0C, 0x0D, 0x1A, 0x13, + 0x14, 0x10, 0x16, 0x1F, 0x1C, 0x21, 0x20, 0x1F, 0x1C, 0x1E, 0x1E, 0x23, 0x27, 0x32, 0x2A, 0x23, + 0x25, 0x2F, 0x25, 0x1E, 0x1E, 0x2B, 0x3B, 0x2C, 0x2F, 0x33, 0x35, 0x38, 0x38, 0x38, 0x21, 0x2A, + 0x3D, 0x41, 0x3C, 0x36, 0x41, 0x32, 0x37, 0x38, 0x35, 0xFF, 0xDB, 0x00, 0x43, 0x01, 0x09, 0x0A, + 0x0A, 0x0D, 0x0B, 0x0D, 0x19, 0x0E, 0x0E, 0x19, 0x35, 0x24, 0x1E, 0x24, 0x35, 0x35, 0x35, 0x35, + 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, + 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, + 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0x35, 0xFF, 0xC0, + 0x00, 0x11, 0x08, 0x00, 0xF0, 0x01, 0x40, 0x03, 0x01, 0x22, 0x00, 0x02, 0x11, 0x01, 0x03, 0x11, + 0x01, 0xFF, 0xC4, 0x00, 0x1B, 0x00, 0x00, 0x02, 0x03, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x00, 0x01, 0x04, 0x05, 0x06, 0x07, 0xFF, 0xC4, + 0x00, 0x3B, 0x10, 0x00, 0x02, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x05, 0x07, 0x03, 0x04, 0x03, + 0x00, 0x00, 0x00, 0x01, 0x02, 0x00, 0x03, 0x11, 0x04, 0x21, 0x05, 0x12, 0x31, 0x41, 0x06, 0x13, + 0x51, 0x61, 0x22, 0x71, 0x81, 0x07, 0x14, 0x91, 0xA1, 0xB1, 0x32, 0x33, 0x42, 0x52, 0x82, 0xC1, + 0xD1, 0x15, 0x23, 0x92, 0x24, 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0x67, 0x04, 0xFF, 0x00, 0xEA, 0x12, 0x86, 0x3F, 0xC3, + 0xB4, 0xD0, 0x2B, 0x3D, 0xB0, 0x23, 0x16, 0x92, 0x7D, 0x4C, 0xCF, 0xB3, 0x58, 0x48, 0x0D, 0xE9, + 0x18, 0xAA, 0x7D, 0x26, 0x84, 0xD3, 0x7B, 0x47, 0x26, 0x98, 0x0E, 0xA2, 0x73, 0xBD, 0xC6, 0xA7, + 0x35, 0x9D, 0x06, 0x3B, 0x47, 0x28, 0x6F, 0x48, 0xE1, 0x50, 0x5F, 0x48, 0x58, 0x02, 0x73, 0xBD, + 0x37, 0x26, 0x16, 0x10, 0xF7, 0x84, 0x16, 0x16, 0x65, 0x66, 0x1A, 0x50, 0x0F, 0x69, 0x62, 0x56, + 0x65, 0x80, 0x4C, 0x10, 0x81, 0xF7, 0x96, 0x0C, 0x10, 0x84, 0xC3, 0x09, 0x0D, 0x48, 0x0C, 0xB8, + 0x41, 0x04, 0x20, 0xB0, 0xD6, 0xB0, 0x00, 0x13, 0x08, 0x24, 0x30, 0x00, 0x97, 0x95, 0x10, 0xD3, + 0x81, 0x09, 0xED, 0x08, 0x21, 0x97, 0xCF, 0x2B, 0x9E, 0x08, 0x41, 0x64, 0xC4, 0x1E, 0x7F, 0x69, + 0x0B, 0x99, 0x62, 0x1C, 0x99, 0x8A, 0x2F, 0xEF, 0x21, 0x7F, 0x79, 0x61, 0xD3, 0x73, 0x27, 0x37, + 0xBC, 0x41, 0x7F, 0x79, 0x0D, 0x83, 0xD6, 0x58, 0x35, 0xFF, 0xD9 +}; + +const unsigned char jpeg_data2[] = { + 0xFF, 0xD8, 0xFF, 0xE0, 0x00, 0x10, 0x4A, 0x46, 0x49, 0x46, 0x00, 0x01, 0x01, 0x01, 0x00, 0x60, + 0x00, 0x60, 0x00, 0x00, 0xFF, 0xE1, 0x00, 0x22, 0x45, 0x78, 0x69, 0x66, 0x00, 0x00, 0x4D, 0x4D, + 0x00, 0x2A, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x01, 0x12, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, + 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xDB, 0x00, 0x43, 0x00, 0x02, 0x01, 0x01, + 0x02, 0x01, 0x01, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x05, 0x03, 0x03, 0x03, + 0x03, 0x03, 0x06, 0x04, 0x04, 0x03, 0x05, 0x07, 0x06, 0x07, 0x07, 0x07, 0x06, 0x07, 0x07, 0x08, + 0x09, 0x0B, 0x09, 0x08, 0x08, 0x0A, 0x08, 0x07, 0x07, 0x0A, 0x0D, 0x0A, 0x0A, 0x0B, 0x0C, 0x0C, + 0x0C, 0x0C, 0x07, 0x09, 0x0E, 0x0F, 0x0D, 0x0C, 0x0E, 0x0B, 0x0C, 0x0C, 0x0C, 0xFF, 0xDB, 0x00, + 0x43, 0x01, 0x02, 0x02, 0x02, 0x03, 0x03, 0x03, 0x06, 0x03, 0x03, 0x06, 0x0C, 0x08, 0x07, 0x08, + 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, + 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, + 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, + 0x0C, 0x0C, 0xFF, 0xC0, 0x00, 0x11, 0x08, 0x00, 0xF0, 0x01, 0x40, 0x03, 0x01, 0x22, 0x00, 0x02, + 0x11, 0x01, 0x03, 0x11, 0x01, 0xFF, 0xC4, 0x00, 0x1F, 0x00, 0x00, 0x01, 0x05, 0x01, 0x01, 0x01, + 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, + 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, 0x00, 0xB5, 0x10, 0x00, 0x02, 0x01, 0x03, 0x03, + 0x02, 0x04, 0x03, 0x05, 0x05, 0x04, 0x04, 0x00, 0x00, 0x01, 0x7D, 0x01, 0x02, 0x03, 0x00, 0x04, + 0x11, 0x05, 0x12, 0x21, 0x31, 0x41, 0x06, 0x13, 0x51, 0x61, 0x07, 0x22, 0x71, 0x14, 0x32, 0x81, + 0x91, 0xA1, 0x08, 0x23, 0x42, 0xB1, 0xC1, 0x15, 0x52, 0xD1, 0xF0, 0x24, 0x33, 0x62, 0x72, 0x82, + 0x09, 0x0A, 0x16, 0x17, 0x18, 0x19, 0x1A, 0x25, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x34, 0x35, 0x36, + 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, + 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, + 0x77, 0x78, 0x79, 0x7A, 0x83, 0x84, 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, + 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, + 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, + 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, 0xD8, 0xD9, 0xDA, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, + 0xE8, 0xE9, 0xEA, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xC4, 0x00, + 0x1F, 0x01, 0x00, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xFF, 0xC4, + 0x00, 0xB5, 0x11, 0x00, 0x02, 0x01, 0x02, 0x04, 0x04, 0x03, 0x04, 0x07, 0x05, 0x04, 0x04, 0x00, + 0x01, 0x02, 0x77, 0x00, 0x01, 0x02, 0x03, 0x11, 0x04, 0x05, 0x21, 0x31, 0x06, 0x12, 0x41, 0x51, + 0x07, 0x61, 0x71, 0x13, 0x22, 0x32, 0x81, 0x08, 0x14, 0x42, 0x91, 0xA1, 0xB1, 0xC1, 0x09, 0x23, + 0x33, 0x52, 0xF0, 0x15, 0x62, 0x72, 0xD1, 0x0A, 0x16, 0x24, 0x34, 0xE1, 0x25, 0xF1, 0x17, 0x18, + 0x19, 0x1A, 0x26, 0x27, 0x28, 0x29, 0x2A, 0x35, 0x36, 0x37, 0x38, 0x39, 0x3A, 0x43, 0x44, 0x45, + 0x46, 0x47, 0x48, 0x49, 0x4A, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x63, 0x64, 0x65, + 0x66, 0x67, 0x68, 0x69, 0x6A, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78, 0x79, 0x7A, 0x82, 0x83, 0x84, + 0x85, 0x86, 0x87, 0x88, 0x89, 0x8A, 0x92, 0x93, 0x94, 0x95, 0x96, 0x97, 0x98, 0x99, 0x9A, 0xA2, + 0xA3, 0xA4, 0xA5, 0xA6, 0xA7, 0xA8, 0xA9, 0xAA, 0xB2, 0xB3, 0xB4, 0xB5, 0xB6, 0xB7, 0xB8, 0xB9, + 0xBA, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD7, + 0xD8, 0xD9, 0xDA, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7, 0xE8, 0xE9, 0xEA, 0xF2, 0xF3, 0xF4, 0xF5, + 0xF6, 0xF7, 0xF8, 0xF9, 0xFA, 0xFF, 0xDA, 0x00, 0x0C, 0x03, 0x01, 0x00, 0x02, 0x11, 0x03, 0x11, + 0x00, 0x3F, 0x00, 0xFC, 0x77, 0xCD, 0x6A, 0x78, 0x21, 0x77, 0x78, 0xD7, 0x46, 0xFF, 0x00, 0xAF, + 0xF8, 0x3F, 0xF4, 0x62, 0xD6, 0x72, 0xA6, 0x2B, 0x53, 0xC1, 0x3F, 0xF2, 0x3B, 0x68, 0xBF, 0xF6, + 0x10, 0xB7, 0xFF, 0x00, 0xD1, 0x8B, 0x5F, 0x69, 0x53, 0xE1, 0x7E, 0x87, 0xCA, 0x53, 0x97, 0xBE, + 0xBD, 0x51, 0xFD, 0x06, 0xF8, 0xCF, 0xC3, 0xCB, 0xE2, 0x8F, 0x85, 0xB2, 0x58, 0xC8, 0x3E, 0x49, + 0xAD, 0xE3, 0x04, 0x1F, 0xA0, 0xAF, 0x9E, 0xFE, 0x2A, 0x7C, 0x1B, 0x8F, 0xC3, 0x5A, 0x0C, 0x72, + 0x58, 0xC7, 0x96, 0x8F, 0x96, 0x3E, 0xD5, 0xF4, 0xD5, 0xEE, 0x22, 0xF0, 0x3A, 0xB3, 0x36, 0xD5, + 0x10, 0xA7, 0x27, 0xE8, 0x2B, 0xC4, 0x3E, 0x33, 0xFC, 0x4E, 0xB5, 0xB1, 0xB4, 0x9B, 0x4E, 0x85, + 0x16, 0x69, 0x24, 0x5C, 0x1E, 0x7E, 0xED, 0x7E, 0x79, 0xC3, 0xB5, 0xB1, 0x2A, 0xB2, 0x85, 0x0D, + 0xAF, 0x76, 0x8F, 0xDD, 0xB8, 0xDF, 0x0F, 0x82, 0x96, 0x1D, 0xD4, 0xC5, 0x59, 0x3E, 0x5B, 0x27, + 0xD7, 0xA9, 0xE0, 0xE8, 0x9C, 0x54, 0xB0, 0xC3, 0x8F, 0xF3, 0xD2, 0xA6, 0x4B, 0x7F, 0xC3, 0xFA, + 0xD5, 0xAB, 0x7B, 0x36, 0x64, 0xDC, 0xB1, 0xB1, 0x19, 0xC6, 0x40, 0xAF, 0xD5, 0xF6, 0xDC, 0xFE, + 0x7B, 0x8E, 0xF6, 0x3D, 0x93, 0xF6, 0x73, 0xF1, 0x15, 0xAD, 0x9E, 0x92, 0x2D, 0xDD, 0x95, 0x64, + 0xC9, 0xC8, 0x35, 0xEE, 0x9A, 0x5E, 0xA9, 0x6E, 0xB6, 0x0D, 0x3F, 0x98, 0x0C, 0x68, 0x32, 0xDC, + 0xF4, 0xAF, 0x8E, 0xF4, 0x9F, 0xB4, 0x69, 0x53, 0x2C, 0x91, 0x33, 0x46, 0xFD, 0x32, 0x38, 0xAE, + 0x9B, 0x47, 0xF8, 0xA1, 0xAC, 0x68, 0x9A, 0x75, 0xD5, 0xB8, 0x9B, 0xCE, 0x86, 0xE5, 0x48, 0x21, + 0xF9, 0xC7, 0xD2, 0xBE, 0x3B, 0x34, 0xE1, 0xF9, 0x57, 0xA8, 0xEA, 0x53, 0x96, 0xEF, 0x63, 0xEF, + 0xF2, 0x6E, 0x2B, 0x86, 0x16, 0x8A, 0xA3, 0x5A, 0x3B, 0x2D, 0xD7, 0xE0, 0x7D, 0x05, 0xF1, 0x67, + 0xC3, 0x36, 0x7F, 0x11, 0xB4, 0x38, 0xAD, 0xA7, 0x6F, 0xF4, 0x5F, 0xF5, 0x87, 0x1D, 0xF8, 0xAE, + 0x5F, 0xC1, 0x1F, 0x0F, 0xF4, 0xDF, 0x0F, 0xE8, 0x92, 0x5A, 0xD9, 0xED, 0x96, 0x17, 0x2D, 0x96, + 0x23, 0x93, 0x9E, 0xB5, 0xE5, 0x3A, 0x6F, 0xC6, 0x5D, 0x6E, 0xD2, 0xC6, 0x1B, 0x7F, 0x3D, 0x99, + 0x62, 0x24, 0x64, 0xF3, 0xB8, 0x1E, 0xC6, 0xBA, 0x0F, 0x0C, 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0x18, 0xE6, 0x0C, 0x5B, 0x57, 0xB5, 0x5D, 0xA0, 0xE7, 0x93, 0x2A, 0x81, 0xFE, 0x7D, 0xAB, 0xF2, 0xF3, 0x5F, 0x8F, 0xEC, 0x3F, 0x12, 0x3C, 0x59, 0x0F, 0x3F, 0xBB, 0xD5, 0x6E, 0x57, 0x07, 0xB6, 0x25, 0x7A, 0x32, 0x7A, 0x74, 0xEB, 0xC2, 0x2E, 0xB5, 0x28, 0xA6, 0xD5, 0xF4, 0x8A, 0x5D, 0x5A, 0x33, 0xE2, 0x48, 0x54, 0xC1, 0xD6, 0x94, 0x30, 0xD8, 0x8A, 0x92, 0x8A, 0x93, 0x8E, 0xB3, 0x6F, 0xEC, 0xA7, 0xE5, 0xDC, 0xE9, 0xAE, 0x3F, 0x6A, 0x9F, 0x8B, 0xF7, 0x27, 0xF7, 0x9E, 0x34, 0xD6, 0x1F, 0xD4, 0xB4, 0xC0, 0xFF, 0x00, 0x4A, 0x8C, 0x7E, 0xD4, 0x1F, 0x17, 0x19, 0x7E, 0x5F, 0x1A, 0x6A, 0xCA, 0x3D, 0xA6, 0x03, 0xFA, 0x57, 0x27, 0x3C, 0xF8, 0xFC, 0x7D, 0x6A, 0x9C, 0x92, 0x90, 0x31, 0x9E, 0x2B, 0xDB, 0x96, 0x5F, 0x86, 0xFE, 0x45, 0xF7, 0x1F, 0x37, 0x1C, 0xC3, 0x17, 0xBF, 0xB5, 0x97, 0xFE, 0x04, 0xCF, 0x52, 0xB5, 0xF8, 0x8B, 0xF1, 0xBF, 0x57, 0xD2, 0x56, 0xFA, 0x1F, 0x16, 0x6A, 0x52, 0xC0, 0xDD, 0x1B, 0xED, 0x23, 0x3F, 0xCA, 0xB3, 0xE6, 0xF8, 0x9D, 0xF1, 0x9B, 0x3C, 0xF8, 0xAB, 0x55, 0xEB, 0xFF, 0x00, 0x3F, 0x03, 0xFC, 0x2B, 0x2B, 0xE1, 0xBF, 0xC5, 0x19, 0x7C, 0x34, 0x92, 0x59, 0x4C, 0xCC, 0xD6, 0xB3, 0xF0, 0xA0, 0xFF, 0x00, 0x01, 0xF6, 0xAE, 0xCD, 0xAF, 0xC5, 0xCA, 0xEF, 0x56, 0xCA, 0xB7, 0x35, 0x8C, 0x70, 0x74, 0x96, 0xF0, 0x5F, 0x71, 0xA4, 0xB1, 0x95, 0xDD, 0xB9, 0x6A, 0xCB, 0xFF, 0x00, 0x02, 0x67, 0xFF, 0xD9 +}; +#endif diff --git a/components/drivers/usb/cherryusb/demo/usb_host.c b/components/drivers/usb/cherryusb/demo/usb_host.c new file mode 100644 index 00000000000..dfcd66de364 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/usb_host.c @@ -0,0 +1,1100 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_cdc_acm.h" +#include "usbh_hid.h" +#include "usbh_msc.h" +#include "usbh_video.h" +#include "usbh_audio.h" + +#ifndef TEST_USBH_CDC_ACM +#define TEST_USBH_CDC_ACM 1 +#endif +#ifndef TEST_USBH_CDC_SPEED +#define TEST_USBH_CDC_SPEED 0 +#endif +#ifndef TEST_USBH_HID +#define TEST_USBH_HID 1 +#endif +#ifndef TEST_USBH_MSC +#define TEST_USBH_MSC 1 +#endif +#ifndef TEST_USBH_MSC_FATFS +#define TEST_USBH_MSC_FATFS 0 +#endif +#ifndef TEST_USBH_AUDIO +#define TEST_USBH_AUDIO 0 +#endif +#ifndef TEST_USBH_VIDEO +#define TEST_USBH_VIDEO 0 +#endif +#ifndef TEST_USBH_CDC_ECM +#define TEST_USBH_CDC_ECM 0 +#endif +#ifndef TEST_USBH_CDC_NCM +#define TEST_USBH_CDC_NCM 0 +#endif +#ifndef TEST_USBH_CDC_RNDIS +#define TEST_USBH_CDC_RNDIS 0 +#endif +#ifndef TEST_USBH_ASIX +#define TEST_USBH_ASIX 0 +#endif +#ifndef TEST_USBH_RTL8152 +#define TEST_USBH_RTL8152 0 +#endif + +#if TEST_USBH_CDC_ACM +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t cdc_buffer[512]; + +#if TEST_USBH_CDC_SPEED +#define TEST_LEN (16 * 1024) +#define TEST_COUNT (10240) + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t cdc_speed_buffer[TEST_LEN]; +#endif + +void usbh_cdc_acm_callback(void *arg, int nbytes) +{ + //struct usbh_cdc_acm *cdc_acm_class = (struct usbh_cdc_acm *)arg; + + if (nbytes > 0) { + for (size_t i = 0; i < nbytes; i++) { + USB_LOG_RAW("0x%02x ", cdc_buffer[i]); + } + USB_LOG_RAW("nbytes:%d\r\n", nbytes); + } +} + +static void usbh_cdc_acm_thread(void *argument) +{ + int ret; + struct usbh_cdc_acm *cdc_acm_class = (struct usbh_cdc_acm *)argument; + + /* test with only one buffer, if you have more cdc acm class, modify by yourself */ +#if TEST_USBH_CDC_SPEED + const uint32_t test_len[] = { 512, 1 * 1024, 2 * 1024, 4 * 1024, 8 * 1024, 16 * 1024 }; + + memset(cdc_speed_buffer, 0xAA, TEST_LEN); + + for (uint8_t j = 0; j < 6; j++) { + uint32_t start_time = (uint32_t)xTaskGetTickCount(); + for (uint32_t i = 0; i < TEST_COUNT; i++) { + usbh_bulk_urb_fill(&cdc_acm_class->bulkout_urb, cdc_acm_class->hport, cdc_acm_class->bulkout, cdc_speed_buffer, test_len[j], 0XFFFFFFF, NULL, NULL); + ret = usbh_submit_urb(&cdc_acm_class->bulkout_urb); + if (ret < 0) { + USB_LOG_RAW("bulk out error,ret:%d\r\n", ret); + while (1) { + } + } else { + } + } + uint32_t time_ms = xTaskGetTickCount() - start_time; + USB_LOG_RAW("per packet len:%d, out speed:%f MB/S\r\n", test_len[j], (test_len[j] * TEST_COUNT / 1024 / 1024) * 1000 / ((float)time_ms)); + } +#endif + memset(cdc_buffer, 0, 512); + + const uint8_t data1[10] = { 0x02, 0x00, 0x00, 0x00, 0x02, 0x02, 0x08, 0x14 }; + + memcpy(cdc_buffer, data1, 10); + usbh_bulk_urb_fill(&cdc_acm_class->bulkout_urb, cdc_acm_class->hport, cdc_acm_class->bulkout, cdc_buffer, 10, 3000, NULL, NULL); + ret = usbh_submit_urb(&cdc_acm_class->bulkout_urb); + if (ret < 0) { + USB_LOG_RAW("bulk out error,ret:%d\r\n", ret); + goto delete; + } else { + USB_LOG_RAW("send over:%d\r\n", cdc_acm_class->bulkout_urb.actual_length); + } + + usbh_bulk_urb_fill(&cdc_acm_class->bulkin_urb, cdc_acm_class->hport, cdc_acm_class->bulkin, cdc_buffer, cdc_acm_class->bulkin->wMaxPacketSize, 0xffffffff, usbh_cdc_acm_callback, cdc_acm_class); + ret = usbh_submit_urb(&cdc_acm_class->bulkin_urb); + if (ret < 0) { + USB_LOG_RAW("bulk in error,ret:%d\r\n", ret); + goto delete; + } else { + } + // clang-format off +delete: + usb_osal_thread_delete(NULL); + // clang-format on +} +#endif + +#if TEST_USBH_HID +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t hid_buffer[128]; + +void usbh_hid_callback(void *arg, int nbytes) +{ + struct usbh_hid *hid_class = (struct usbh_hid *)arg; + + if (nbytes > 0) { + for (size_t i = 0; i < nbytes; i++) { + USB_LOG_RAW("0x%02x ", hid_buffer[i]); + } + USB_LOG_RAW("nbytes:%d\r\n", nbytes); + usbh_submit_urb(&hid_class->intin_urb); + } else if (nbytes == -USB_ERR_NAK) { /* only dwc2 should do this */ + usbh_submit_urb(&hid_class->intin_urb); + } else { + } +} + +static void usbh_hid_thread(void *argument) +{ + int ret; + struct usbh_hid *hid_class = (struct usbh_hid *)argument; + ; + + /* test with only one buffer, if you have more hid class, modify by yourself */ + + /* Suggest you to use timer for int transfer and use ep interval */ + usbh_int_urb_fill(&hid_class->intin_urb, hid_class->hport, hid_class->intin, hid_buffer, hid_class->intin->wMaxPacketSize, 0, usbh_hid_callback, hid_class); + ret = usbh_submit_urb(&hid_class->intin_urb); + if (ret < 0) { + goto delete; + } + // clang-format off +delete: + usb_osal_thread_delete(NULL); + // clang-format on +} +#endif + +#if TEST_USBH_MSC + +#if TEST_USBH_MSC_FATFS +#include "ff.h" + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_write_buffer[25 * 100]; + +USB_NOCACHE_RAM_SECTION FATFS fs; +USB_NOCACHE_RAM_SECTION FIL fnew; +UINT fnum; +FRESULT res_sd = 0; + +int usb_msc_fatfs_test() +{ + const char *tmp_data = "cherryusb fatfs demo...\r\n"; + + USB_LOG_RAW("data len:%d\r\n", strlen(tmp_data)); + for (uint32_t i = 0; i < 100; i++) { + memcpy(&read_write_buffer[i * 25], tmp_data, strlen(tmp_data)); + } + + res_sd = f_mount(&fs, "2:", 1); + if (res_sd != FR_OK) { + USB_LOG_RAW("mount fail,res:%d\r\n", res_sd); + return -1; + } + + USB_LOG_RAW("test fatfs write\r\n"); + res_sd = f_open(&fnew, "2:test.txt", FA_CREATE_ALWAYS | FA_WRITE); + if (res_sd == FR_OK) { + res_sd = f_write(&fnew, read_write_buffer, sizeof(read_write_buffer), &fnum); + if (res_sd == FR_OK) { + USB_LOG_RAW("write success, write len:%d\n", fnum); + } else { + USB_LOG_RAW("write fail\r\n"); + goto unmount; + } + f_close(&fnew); + } else { + USB_LOG_RAW("open fail\r\n"); + goto unmount; + } + USB_LOG_RAW("test fatfs read\r\n"); + + res_sd = f_open(&fnew, "2:test.txt", FA_OPEN_EXISTING | FA_READ); + if (res_sd == FR_OK) { + res_sd = f_read(&fnew, read_write_buffer, sizeof(read_write_buffer), &fnum); + if (res_sd == FR_OK) { + USB_LOG_RAW("read success, read len:%d\n", fnum); + } else { + USB_LOG_RAW("read fail\r\n"); + goto unmount; + } + f_close(&fnew); + } else { + USB_LOG_RAW("open fail\r\n"); + goto unmount; + } + f_mount(NULL, "2:", 1); + return 0; +unmount: + f_mount(NULL, "2:", 1); + return -1; +} +#endif + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t partition_table[512]; + +static void usbh_msc_thread(void *argument) +{ + int ret; + struct usbh_msc *msc_class = (struct usbh_msc *)argument; + + /* test with only one buffer, if you have more msc class, modify by yourself */ +#if 1 + /* get the partition table */ + ret = usbh_msc_scsi_read10(msc_class, 0, partition_table, 1); + if (ret < 0) { + USB_LOG_RAW("scsi_read10 error,ret:%d\r\n", ret); + goto delete; + } + for (uint32_t i = 0; i < 512; i++) { + if (i % 16 == 0) { + USB_LOG_RAW("\r\n"); + } + USB_LOG_RAW("%02x ", partition_table[i]); + } + USB_LOG_RAW("\r\n"); +#endif + +#if TEST_USBH_MSC_FATFS + usb_msc_fatfs_test(); +#endif + // clang-format off +delete: + usb_osal_thread_delete(NULL); + // clang-format on +} +#endif + +#if 0 +void usbh_videostreaming_parse_mjpeg(struct usbh_urb *urb, struct usbh_videostreaming *stream) +{ + struct usbh_iso_frame_packet *iso_packet; + uint32_t num_of_iso_packets; + uint8_t data_offset; + uint32_t data_len; + uint8_t header_len = 0; + + num_of_iso_packets = urb->num_of_iso_packets; + iso_packet = urb->iso_packet; + + for (uint32_t i = 0; i < num_of_iso_packets; i++) { + /* + uint8_t frameIdentifier : 1U; + uint8_t endOfFrame : 1U; + uint8_t presentationTimeStamp : 1U; + uint8_t sourceClockReference : 1U; + uint8_t reserved : 1U; + uint8_t stillImage : 1U; + uint8_t errorBit : 1U; + uint8_t endOfHeader : 1U; + */ + if (iso_packet[i].actual_length == 0) { /* skip no data */ + continue; + } + + header_len = iso_packet[i].transfer_buffer[0]; + + if ((header_len > 12) || (header_len == 0)) { /* do not be illegal */ + while (1) { + } + } + if (iso_packet[i].transfer_buffer[1] & (1 << 6)) { /* error bit, re-receive */ + stream->bufoffset = 0; + continue; + } + + if ((stream->bufoffset == 0) && ((iso_packet[i].transfer_buffer[header_len] != 0xff) || (iso_packet[i].transfer_buffer[header_len + 1] != 0xd8))) { + stream->bufoffset = 0; + continue; + } + + data_offset = header_len; + data_len = iso_packet[i].actual_length - header_len; + + /** do something here */ + + stream->bufoffset += data_len; + + if (iso_packet[i].transfer_buffer[1] & (1 << 1)) { + if ((iso_packet[i].transfer_buffer[iso_packet[i].actual_length - 2] != 0xff) || (iso_packet[i].transfer_buffer[iso_packet[i].actual_length - 1] != 0xd9)) { + stream->bufoffset = 0; + continue; + } + + /** do something here */ + + if (stream->video_one_frame_callback) { + stream->video_one_frame_callback(stream); + } + stream->bufoffset = 0; + } + } + /** do something here */ +} + +void usbh_videostreaming_parse_yuyv2(struct usbh_urb *urb, struct usbh_videostreaming *stream) +{ + struct usbh_iso_frame_packet *iso_packet; + uint32_t num_of_iso_packets; + uint8_t data_offset; + uint32_t data_len; + uint8_t header_len = 0; + + num_of_iso_packets = urb->num_of_iso_packets; + iso_packet = urb->iso_packet; + + for (uint32_t i = 0; i < num_of_iso_packets; i++) { + /* + uint8_t frameIdentifier : 1U; + uint8_t endOfFrame : 1U; + uint8_t presentationTimeStamp : 1U; + uint8_t sourceClockReference : 1U; + uint8_t reserved : 1U; + uint8_t stillImage : 1U; + uint8_t errorBit : 1U; + uint8_t endOfHeader : 1U; + */ + + if (iso_packet[i].actual_length == 0) { /* skip no data */ + continue; + } + + header_len = iso_packet[i].transfer_buffer[0]; + + if ((header_len > 12) || (header_len == 0)) { /* do not be illegal */ + while (1) { + } + } + if (iso_packet[i].transfer_buffer[1] & (1 << 6)) { /* error bit, re-receive */ + stream->bufoffset = 0; + continue; + } + + data_offset = header_len; + data_len = iso_packet[i].actual_length - header_len; + + /** do something here */ + + stream->bufoffset += data_len; + + if (iso_packet[i].transfer_buffer[1] & (1 << 1)) { + /** do something here */ + + if (stream->video_one_frame_callback && (stream->bufoffset == stream->buflen)) { + stream->video_one_frame_callback(stream); + } + stream->bufoffset = 0; + } + } + + /** do something here */ +} +#endif + +#if TEST_USBH_CDC_ECM || TEST_USBH_CDC_NCM || TEST_USBH_CDC_RNDIS || TEST_USBH_ASIX || TEST_USBH_RTL8152 +#include "netif/etharp.h" +#include "lwip/netif.h" +#include "lwip/pbuf.h" +#include "lwip/tcpip.h" +#if LWIP_DHCP +#include "lwip/dhcp.h" +#include "lwip/prot/dhcp.h" +#endif + +#ifdef __RTTHREAD__ + +#include +#include +#include + +#else +#include "FreeRTOS.h" +#include "task.h" +#include "semphr.h" +#include "timers.h" + +TimerHandle_t dhcp_handle; + +static void dhcp_timeout(TimerHandle_t xTimer) +{ + struct netif *netif = (struct netif *)pvTimerGetTimerID(xTimer); + struct dhcp *dhcp; + + if (netif_is_up(netif)) { + dhcp = netif_dhcp_data(netif); + + if (dhcp && (dhcp->state == DHCP_STATE_BOUND)) { + USB_LOG_INFO("IPv4 Address : %s\r\n", ipaddr_ntoa(&netif->ip_addr)); + USB_LOG_INFO("IPv4 Subnet mask : %s\r\n", ipaddr_ntoa(&netif->netmask)); + USB_LOG_INFO("IPv4 Gateway : %s\r\n\r\n", ipaddr_ntoa(&netif->gw)); + + xTimerStop(xTimer, 0); + } + } +} +#endif +#endif + +#if TEST_USBH_CDC_ECM +#include "usbh_cdc_ecm.h" + +struct netif g_cdc_ecm_netif; + +#ifdef __RTTHREAD__ +static struct eth_device cdc_ecm_dev; + +static rt_err_t rt_usbh_cdc_ecm_control(rt_device_t dev, int cmd, void *args) +{ + struct usbh_cdc_ecm *cdc_ecm_class = (struct usbh_cdc_ecm *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, cdc_ecm_class->mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_usbh_cdc_ecm_eth_tx(rt_device_t dev, struct pbuf *p) +{ + return usbh_cdc_ecm_linkoutput(NULL, p); +} +#endif + +static err_t usbh_cdc_ecm_if_init(struct netif *netif) +{ + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + netif->mtu = 1500; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP | NETIF_FLAG_UP; + netif->state = NULL; + netif->name[0] = 'E'; + netif->name[1] = 'X'; + netif->output = etharp_output; + netif->linkoutput = usbh_cdc_ecm_linkoutput; + return ERR_OK; +} + +void usbh_cdc_ecm_run(struct usbh_cdc_ecm *cdc_ecm_class) +{ +#ifdef __RTTHREAD__ + memset(&cdc_ecm_dev, 0, sizeof(struct eth_device)); + + cdc_ecm_dev.parent.control = rt_usbh_cdc_ecm_control; + cdc_ecm_dev.eth_rx = NULL; + cdc_ecm_dev.eth_tx = rt_usbh_cdc_ecm_eth_tx; + cdc_ecm_dev.parent.user_data = cdc_ecm_class; + + eth_device_init(&cdc_ecm_dev, "u0"); + eth_device_linkchange(&cdc_ecm_dev, RT_TRUE); + + usb_osal_thread_create("usbh_cdc_ecm_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_ecm_rx_thread, cdc_ecm_dev.netif); +#else + struct netif *netif = &g_cdc_ecm_netif; + + netif->hwaddr_len = 6; + memcpy(netif->hwaddr, cdc_ecm_class->mac, 6); + + IP4_ADDR(&cdc_ecm_class->ipaddr, 0, 0, 0, 0); + IP4_ADDR(&cdc_ecm_class->netmask, 0, 0, 0, 0); + IP4_ADDR(&cdc_ecm_class->gateway, 0, 0, 0, 0); + + netif = netif_add(netif, &cdc_ecm_class->ipaddr, &cdc_ecm_class->netmask, &cdc_ecm_class->gateway, NULL, usbh_cdc_ecm_if_init, tcpip_input); + netif_set_default(netif); + while (!netif_is_up(netif)) { + } + + dhcp_handle = xTimerCreate((const char *)"dhcp", (TickType_t)200, (UBaseType_t)pdTRUE, (void *const)netif, (TimerCallbackFunction_t)dhcp_timeout); + if (dhcp_handle == NULL) { + USB_LOG_ERR("timer creation failed! \r\n"); + while (1) { + } + } + + usb_osal_thread_create("usbh_cdc_ecm_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_ecm_rx_thread, netif); +#if LWIP_DHCP + dhcp_start(netif); + xTimerStart(dhcp_handle, 0); +#endif +#endif +} + +void usbh_cdc_ecm_stop(struct usbh_cdc_ecm *cdc_ecm_class) +{ +#ifdef __RTTHREAD__ + eth_device_deinit(&cdc_ecm_dev); +#else + struct netif *netif = &g_cdc_ecm_netif; +#if LWIP_DHCP + dhcp_stop(netif); + dhcp_cleanup(netif); + xTimerStop(dhcp_handle, 0); + xTimerDelete(dhcp_handle, 0); +#endif + netif_set_down(netif); + netif_remove(netif); +#endif +} +#endif + +#if TEST_USBH_CDC_NCM +#include "usbh_cdc_ncm.h" + +struct netif g_cdc_ncm_netif; + +#ifdef __RTTHREAD__ +static struct eth_device cdc_ncm_dev; + +static rt_err_t rt_usbh_cdc_ncm_control(rt_device_t dev, int cmd, void *args) +{ + struct usbh_cdc_ncm *cdc_ncm_class = (struct usbh_cdc_ncm *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, cdc_ncm_class->mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_usbh_cdc_ncm_eth_tx(rt_device_t dev, struct pbuf *p) +{ + return usbh_cdc_ncm_linkoutput(NULL, p); +} +#endif + +static err_t usbh_cdc_ncm_if_init(struct netif *netif) +{ + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + netif->mtu = 1500; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP | NETIF_FLAG_UP; + netif->state = NULL; + netif->name[0] = 'E'; + netif->name[1] = 'X'; + netif->output = etharp_output; + netif->linkoutput = usbh_cdc_ncm_linkoutput; + return ERR_OK; +} + +void usbh_cdc_ncm_run(struct usbh_cdc_ncm *cdc_ncm_class) +{ +#ifdef __RTTHREAD__ + memset(&cdc_ncm_dev, 0, sizeof(struct eth_device)); + + cdc_ncm_dev.parent.control = rt_usbh_cdc_ncm_control; + cdc_ncm_dev.eth_rx = NULL; + cdc_ncm_dev.eth_tx = rt_usbh_cdc_ncm_eth_tx; + cdc_ncm_dev.parent.user_data = cdc_ncm_class; + + eth_device_init(&cdc_ncm_dev, "u1"); + eth_device_linkchange(&cdc_ncm_dev, RT_TRUE); + + usb_osal_thread_create("usbh_cdc_ncm_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_ncm_rx_thread, cdc_ncm_dev.netif); +#else + struct netif *netif = &g_cdc_ncm_netif; + + netif->hwaddr_len = 6; + memcpy(netif->hwaddr, cdc_ncm_class->mac, 6); + + IP4_ADDR(&cdc_ncm_class->ipaddr, 0, 0, 0, 0); + IP4_ADDR(&cdc_ncm_class->netmask, 0, 0, 0, 0); + IP4_ADDR(&cdc_ncm_class->gateway, 0, 0, 0, 0); + + netif = netif_add(netif, &cdc_ncm_class->ipaddr, &cdc_ncm_class->netmask, &cdc_ncm_class->gateway, NULL, usbh_cdc_ncm_if_init, tcpip_input); + netif_set_default(netif); + while (!netif_is_up(netif)) { + } + + dhcp_handle = xTimerCreate((const char *)"dhcp", (TickType_t)200, (UBaseType_t)pdTRUE, (void *const)netif, (TimerCallbackFunction_t)dhcp_timeout); + if (dhcp_handle == NULL) { + USB_LOG_ERR("timer creation failed! \r\n"); + while (1) { + } + } + + usb_osal_thread_create("usbh_cdc_ncm_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_ncm_rx_thread, netif); +#if LWIP_DHCP + dhcp_start(netif); + xTimerStart(dhcp_handle, 0); +#endif +#endif +} + +void usbh_cdc_ncm_stop(struct usbh_cdc_ncm *cdc_ncm_class) +{ +#ifdef __RTTHREAD__ + eth_device_deinit(&cdc_ncm_dev); +#else + struct netif *netif = &g_cdc_ncm_netif; +#if LWIP_DHCP + dhcp_stop(netif); + dhcp_cleanup(netif); + xTimerStop(dhcp_handle, 0); + xTimerDelete(dhcp_handle, 0); +#endif + netif_set_down(netif); + netif_remove(netif); +#endif +} +#endif + +#if TEST_USBH_CDC_RNDIS +#include "usbh_rndis.h" + +struct netif g_rndis_netif; + +#ifdef __RTTHREAD__ + +static struct eth_device rndis_dev; + +static rt_timer_t keep_timer = RT_NULL; + +static void rndis_dev_keepalive_timeout(void *parameter) +{ + struct usbh_rndis *rndis_class = (struct usbh_rndis *)parameter; + usbh_rndis_keepalive(rndis_class); +} + +static void timer_init(struct usbh_rndis *rndis_class) +{ + keep_timer = rt_timer_create("keep", + rndis_dev_keepalive_timeout, + rndis_class, + 5000, + RT_TIMER_FLAG_PERIODIC | + RT_TIMER_FLAG_SOFT_TIMER); + + rt_timer_start(keep_timer); +} + +static rt_err_t rt_usbh_rndis_control(rt_device_t dev, int cmd, void *args) +{ + struct usbh_rndis *rndis_class = (struct usbh_rndis *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, rndis_class->mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_usbh_rndis_eth_tx(rt_device_t dev, struct pbuf *p) +{ + return usbh_rndis_linkoutput(NULL, p); +} + +#else +TimerHandle_t timer_handle; + +static void rndis_dev_keepalive_timeout(TimerHandle_t xTimer) +{ + struct usbh_rndis *rndis_class = (struct usbh_rndis *)pvTimerGetTimerID(xTimer); + usbh_rndis_keepalive(rndis_class); +} + +void timer_init(struct usbh_rndis *rndis_class) +{ + timer_handle = xTimerCreate((const char *)NULL, (TickType_t)5000, (UBaseType_t)pdTRUE, (void *const)rndis_class, (TimerCallbackFunction_t)rndis_dev_keepalive_timeout); + if (NULL != timer_handle) { + xTimerStart(timer_handle, 0); + } else { + USB_LOG_ERR("timer creation failed! \r\n"); + for (;;) { + ; + } + } +} +#endif + +static err_t usbh_rndis_if_init(struct netif *netif) +{ + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + netif->mtu = 1500; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP | NETIF_FLAG_UP; + netif->state = NULL; + netif->name[0] = 'E'; + netif->name[1] = 'X'; + netif->output = etharp_output; + netif->linkoutput = usbh_rndis_linkoutput; + return ERR_OK; +} + +void usbh_rndis_run(struct usbh_rndis *rndis_class) +{ +#ifdef __RTTHREAD__ + memset(&rndis_dev, 0, sizeof(struct eth_device)); + + rndis_dev.parent.control = rt_usbh_rndis_control; + rndis_dev.eth_rx = NULL; + rndis_dev.eth_tx = rt_usbh_rndis_eth_tx; + rndis_dev.parent.user_data = rndis_class; + + eth_device_init(&rndis_dev, "u2"); + eth_device_linkchange(&rndis_dev, RT_TRUE); + + usb_osal_thread_create("usbh_rndis_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_rndis_rx_thread, rndis_dev.netif); + //timer_init(rndis_class); +#else + struct netif *netif = &g_rndis_netif; + + netif->hwaddr_len = 6; + memcpy(netif->hwaddr, rndis_class->mac, 6); + + IP4_ADDR(&rndis_class->ipaddr, 0, 0, 0, 0); + IP4_ADDR(&rndis_class->netmask, 0, 0, 0, 0); + IP4_ADDR(&rndis_class->gateway, 0, 0, 0, 0); + + netif = netif_add(netif, &rndis_class->ipaddr, &rndis_class->netmask, &rndis_class->gateway, NULL, usbh_rndis_if_init, tcpip_input); + netif_set_default(netif); + while (!netif_is_up(netif)) { + } + + dhcp_handle = xTimerCreate((const char *)"dhcp2", (TickType_t)200, (UBaseType_t)pdTRUE, (void *const)netif, (TimerCallbackFunction_t)dhcp_timeout); + if (dhcp_handle == NULL) { + USB_LOG_ERR("timer creation failed! \r\n"); + while (1) { + } + } + + usb_osal_thread_create("usbh_rndis_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_rndis_rx_thread, netif); + //timer_init(rndis_class); + +#if LWIP_DHCP + dhcp_start(netif); + xTimerStart(dhcp_handle, 0); +#endif +#endif +} + +void usbh_rndis_stop(struct usbh_rndis *rndis_class) +{ +#ifdef __RTTHREAD__ + eth_device_deinit(&rndis_dev); + // rt_timer_stop(keep_timer); + // rt_timer_delete(keep_timer); +#else + struct netif *netif = &g_rndis_netif; +#if LWIP_DHCP + dhcp_stop(netif); + dhcp_cleanup(netif); + xTimerStop(dhcp_handle, 0); + xTimerDelete(dhcp_handle, 0); +#endif + netif_set_down(netif); + netif_remove(netif); + // xTimerStop(timer_handle, 0); + // xTimerDelete(timer_handle, 0); +#endif +} +#endif + +#if TEST_USBH_ASIX +#include "usbh_asix.h" + +struct netif g_asix_netif; + +#ifdef __RTTHREAD__ +static struct eth_device asix_dev; + +static rt_err_t rt_usbh_asix_control(rt_device_t dev, int cmd, void *args) +{ + struct usbh_asix *asix_class = (struct usbh_asix *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, asix_class->mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_usbh_asix_eth_tx(rt_device_t dev, struct pbuf *p) +{ + return usbh_asix_linkoutput(NULL, p); +} +#endif + +static err_t usbh_asix_if_init(struct netif *netif) +{ + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + netif->mtu = 1500; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP | NETIF_FLAG_UP; + netif->state = NULL; + netif->name[0] = 'E'; + netif->name[1] = 'X'; + netif->output = etharp_output; + netif->linkoutput = usbh_asix_linkoutput; + return ERR_OK; +} + +void usbh_asix_run(struct usbh_asix *asix_class) +{ +#ifdef __RTTHREAD__ + memset(&asix_dev, 0, sizeof(struct eth_device)); + + asix_dev.parent.control = rt_usbh_asix_control; + asix_dev.eth_rx = NULL; + asix_dev.eth_tx = rt_usbh_asix_eth_tx; + asix_dev.parent.user_data = asix_class; + + eth_device_init(&asix_dev, "u3"); + eth_device_linkchange(&asix_dev, RT_TRUE); + + usb_osal_thread_create("usbh_asix_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_asix_rx_thread, asix_dev.netif); +#else + struct netif *netif = &g_asix_netif; + + netif->hwaddr_len = 6; + memcpy(netif->hwaddr, asix_class->mac, 6); + + IP4_ADDR(&asix_class->ipaddr, 0, 0, 0, 0); + IP4_ADDR(&asix_class->netmask, 0, 0, 0, 0); + IP4_ADDR(&asix_class->gateway, 0, 0, 0, 0); + + netif = netif_add(netif, &asix_class->ipaddr, &asix_class->netmask, &asix_class->gateway, NULL, usbh_asix_if_init, tcpip_input); + netif_set_default(netif); + while (!netif_is_up(netif)) { + } + + dhcp_handle = xTimerCreate((const char *)"dhcp", (TickType_t)200, (UBaseType_t)pdTRUE, (void *const)netif, (TimerCallbackFunction_t)dhcp_timeout); + if (dhcp_handle == NULL) { + USB_LOG_ERR("timer creation failed! \r\n"); + while (1) { + } + } + + usb_osal_thread_create("usbh_asix_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_asix_rx_thread, netif); +#if LWIP_DHCP + dhcp_start(netif); + xTimerStart(dhcp_handle, 0); +#endif +#endif +} + +void usbh_asix_stop(struct usbh_asix *asix_class) +{ +#ifdef __RTTHREAD__ + eth_device_deinit(&asix_dev); +#else + struct netif *netif = &g_asix_netif; +#if LWIP_DHCP + dhcp_stop(netif); + dhcp_cleanup(netif); + xTimerStop(dhcp_handle, 0); + xTimerDelete(dhcp_handle, 0); +#endif + netif_set_down(netif); + netif_remove(netif); +#endif +} +#endif + +#if TEST_USBH_RTL8152 +#include "usbh_rtl8152.h" + +struct netif g_rtl8152_netif; + +#ifdef __RTTHREAD__ +static struct eth_device rtl8152_dev; + +static rt_err_t rt_usbh_rtl8152_control(rt_device_t dev, int cmd, void *args) +{ + struct usbh_rtl8152 *rtl8152_class = (struct usbh_rtl8152 *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, rtl8152_class->mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_usbh_rtl8152_eth_tx(rt_device_t dev, struct pbuf *p) +{ + return usbh_rtl8152_linkoutput(NULL, p); +} +#endif + +static err_t usbh_rtl8152_if_init(struct netif *netif) +{ + LWIP_ASSERT("netif != NULL", (netif != NULL)); + + netif->mtu = 1500; + netif->flags = NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP | NETIF_FLAG_LINK_UP | NETIF_FLAG_UP; + netif->state = NULL; + netif->name[0] = 'E'; + netif->name[1] = 'X'; + netif->output = etharp_output; + netif->linkoutput = usbh_rtl8152_linkoutput; + return ERR_OK; +} + +void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class) +{ +#ifdef __RTTHREAD__ + memset(&rtl8152_dev, 0, sizeof(struct eth_device)); + + rtl8152_dev.parent.control = rt_usbh_rtl8152_control; + rtl8152_dev.eth_rx = NULL; + rtl8152_dev.eth_tx = rt_usbh_rtl8152_eth_tx; + rtl8152_dev.parent.user_data = rtl8152_class; + + eth_device_init(&rtl8152_dev, "u4"); + eth_device_linkchange(&rtl8152_dev, RT_TRUE); + + usb_osal_thread_create("usbh_rtl8152_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_rtl8152_rx_thread, rtl8152_dev.netif); +#else + struct netif *netif = &g_rtl8152_netif; + + netif->hwaddr_len = 6; + memcpy(netif->hwaddr, rtl8152_class->mac, 6); + + IP4_ADDR(&rtl8152_class->ipaddr, 0, 0, 0, 0); + IP4_ADDR(&rtl8152_class->netmask, 0, 0, 0, 0); + IP4_ADDR(&rtl8152_class->gateway, 0, 0, 0, 0); + + netif = netif_add(netif, &rtl8152_class->ipaddr, &rtl8152_class->netmask, &rtl8152_class->gateway, NULL, usbh_rtl8152_if_init, tcpip_input); + netif_set_default(netif); + while (!netif_is_up(netif)) { + } + + dhcp_handle = xTimerCreate((const char *)"dhcp", (TickType_t)200, (UBaseType_t)pdTRUE, (void *const)netif, (TimerCallbackFunction_t)dhcp_timeout); + if (dhcp_handle == NULL) { + USB_LOG_ERR("timer creation failed! \r\n"); + while (1) { + } + } + + usb_osal_thread_create("usbh_rtl8152_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_rtl8152_rx_thread, netif); +#if LWIP_DHCP + dhcp_start(netif); + xTimerStart(dhcp_handle, 0); +#endif +#endif +} + +void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class) +{ +#ifdef __RTTHREAD__ + eth_device_deinit(&rtl8152_dev); +#else + struct netif *netif = &g_rtl8152_netif; +#if LWIP_DHCP + dhcp_stop(netif); + dhcp_cleanup(netif); + xTimerStop(dhcp_handle, 0); + xTimerDelete(dhcp_handle, 0); +#endif + netif_set_down(netif); + netif_remove(netif); +#endif +} +#endif + +void usbh_cdc_acm_run(struct usbh_cdc_acm *cdc_acm_class) +{ +#if TEST_USBH_CDC_ACM + usb_osal_thread_create("usbh_cdc", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_acm_thread, cdc_acm_class); +#endif +} + +void usbh_cdc_acm_stop(struct usbh_cdc_acm *cdc_acm_class) +{ +} + +void usbh_hid_run(struct usbh_hid *hid_class) +{ +#if TEST_USBH_HID + usb_osal_thread_create("usbh_hid", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_hid_thread, hid_class); +#endif +} + +void usbh_hid_stop(struct usbh_hid *hid_class) +{ +} + +#ifndef __RTTHREAD__ +void usbh_msc_run(struct usbh_msc *msc_class) +{ +#if TEST_USBH_MSC + usb_osal_thread_create("usbh_msc", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_msc_thread, msc_class); +#endif +} + +void usbh_msc_stop(struct usbh_msc *msc_class) +{ +} +#endif + +#if TEST_USBH_AUDIO +#error "if you want to use iso, please contact with me" +#endif + +#if TEST_USBH_VIDEO +#error "if you want to use iso, please contact with me" +#endif + +void usbh_class_test(void) +{ +#ifdef __RTTHREAD__ + /* do nothing */ +#else +#if TEST_USBH_CDC_ECM || TEST_USBH_CDC_NCM || TEST_USBH_CDC_RNDIS || TEST_USBH_ASIX || TEST_USBH_RTL8152 + /* Initialize the LwIP stack */ + tcpip_init(NULL, NULL); +#endif +#endif +} diff --git a/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c b/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c new file mode 100644 index 00000000000..41d54b04594 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/video_static_mjpeg_template.c @@ -0,0 +1,258 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_video.h" +#include "pic_data.h" + +#define VIDEO_IN_EP 0x81 + +#ifdef CONFIG_USB_HS +#define MAX_PAYLOAD_SIZE 1024 // for high speed with one transcations every one micro frame +#define VIDEO_PACKET_SIZE (unsigned int)(((MAX_PAYLOAD_SIZE / 1)) | (0x00 << 11)) + +// #define MAX_PAYLOAD_SIZE 2048 // for high speed with two transcations every one micro frame +// #define VIDEO_PACKET_SIZE (unsigned int)(((MAX_PAYLOAD_SIZE / 2)) | (0x01 << 11)) + +// #define MAX_PAYLOAD_SIZE 3072 // for high speed with three transcations every one micro frame +// #define VIDEO_PACKET_SIZE (unsigned int)(((MAX_PAYLOAD_SIZE / 3)) | (0x02 << 11)) + +#else +#define MAX_PAYLOAD_SIZE 1020 +#define VIDEO_PACKET_SIZE (unsigned int)(((MAX_PAYLOAD_SIZE / 1)) | (0x00 << 11)) +#endif + +#define WIDTH (unsigned int)(640) +#define HEIGHT (unsigned int)(480) + +#define CAM_FPS (30) +#define INTERVAL (unsigned long)(10000000 / CAM_FPS) +#define MIN_BIT_RATE (unsigned long)(WIDTH * HEIGHT * 16 * CAM_FPS) //16 bit +#define MAX_BIT_RATE (unsigned long)(WIDTH * HEIGHT * 16 * CAM_FPS) +#define MAX_FRAME_SIZE (unsigned long)(WIDTH * HEIGHT * 2) + +#define USB_VIDEO_DESC_SIZ (unsigned long)(9 + \ + 8 + \ + 9 + \ + 13 + \ + 18 + \ + 9 + \ + 12 + \ + 9 + \ + 14 + \ + 11 + \ + 30 + \ + 9 + \ + 7) + +#define VC_TERMINAL_SIZ (unsigned int)(13 + 18 + 12 + 9) +#define VS_HEADER_SIZ (unsigned int)(13 + 1 + 11 + 30) + +#define USBD_VID 0xffff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +const uint8_t video_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0xef, 0x02, 0x01, USBD_VID, USBD_PID, 0x0001, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_VIDEO_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + VIDEO_VC_DESCRIPTOR_INIT(0x00, 0, 0x0100, VC_TERMINAL_SIZ, 48000000, 0x02), + VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x00, 0x00), + VIDEO_VS_HEADER_DESCRIPTOR_INIT(0x01, VS_HEADER_SIZ, VIDEO_IN_EP, 0x00), + VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_INIT(0x01, 0x01), + VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_INIT(0x01, WIDTH, HEIGHT, MIN_BIT_RATE, MAX_BIT_RATE, MAX_FRAME_SIZE, DBVAL(INTERVAL), 0x01, DBVAL(INTERVAL)), + VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x01, 0x01), + /* 1.2.2.2 Standard VideoStream Isochronous Video Data Endpoint Descriptor */ + 0x07, /* bLength */ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: ENDPOINT */ + 0x81, /* bEndpointAddress: IN endpoint 2 */ + 0x01, /* bmAttributes: Isochronous transfer type. Asynchronous synchronization type. */ + WBVAL(VIDEO_PACKET_SIZE), /* wMaxPacketSize */ + 0x01, /* bInterval: One frame interval */ + + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x26, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'U', 0x00, /* wcChar10 */ + 'V', 0x00, /* wcChar11 */ + 'C', 0x00, /* wcChar12 */ + ' ', 0x00, /* wcChar13 */ + 'D', 0x00, /* wcChar14 */ + 'E', 0x00, /* wcChar15 */ + 'M', 0x00, /* wcChar16 */ + 'O', 0x00, /* wcChar17 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '1', 0x00, /* wcChar3 */ + '0', 0x00, /* wcChar4 */ + '3', 0x00, /* wcChar5 */ + '1', 0x00, /* wcChar6 */ + '0', 0x00, /* wcChar7 */ + '0', 0x00, /* wcChar8 */ + '0', 0x00, /* wcChar9 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +volatile bool tx_flag = 0; +volatile bool iso_tx_busy = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + tx_flag = 0; + iso_tx_busy = false; + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_video_open(uint8_t busid, uint8_t intf) +{ + tx_flag = 1; + USB_LOG_RAW("OPEN\r\n"); + iso_tx_busy = false; +} +void usbd_video_close(uint8_t busid, uint8_t intf) +{ + USB_LOG_RAW("CLOSE\r\n"); + tx_flag = 0; + iso_tx_busy = false; +} + +void usbd_video_iso_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + iso_tx_busy = false; +} + +static struct usbd_endpoint video_in_ep = { + .ep_cb = usbd_video_iso_callback, + .ep_addr = VIDEO_IN_EP +}; + +struct usbd_interface intf0; +struct usbd_interface intf1; + +void video_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, video_descriptor); + usbd_add_interface(busid, usbd_video_init_intf(busid, &intf0, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); + usbd_add_interface(busid, usbd_video_init_intf(busid, &intf1, INTERVAL, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE)); + usbd_add_endpoint(busid, &video_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t packet_buffer[10 * 1024]; + +void video_test(uint8_t busid) +{ + uint32_t out_len; + uint32_t packets; + memset(packet_buffer, 0, 10 * 1024); + while (1) { + if (tx_flag) { + packets = usbd_video_mjpeg_payload_fill(busid, (uint8_t *)jpeg_data, sizeof(jpeg_data), packet_buffer, &out_len); +#if 0 + iso_tx_busy = true; + usbd_ep_start_write(busid, VIDEO_IN_EP, packet_buffer, out_len); + while (iso_tx_busy) { + if (tx_flag == 0) { + break; + } + } +#else + /* dwc2 must use this method */ + for (uint32_t i = 0; i < packets; i++) { + if (i == (packets - 1)) { + iso_tx_busy = true; + usbd_ep_start_write(busid, VIDEO_IN_EP, &packet_buffer[i * MAX_PAYLOAD_SIZE], out_len - (packets - 1) * MAX_PAYLOAD_SIZE); + while (iso_tx_busy) { + if (tx_flag == 0) { + break; + } + } + } else { + iso_tx_busy = true; + usbd_ep_start_write(busid, VIDEO_IN_EP, &packet_buffer[i * MAX_PAYLOAD_SIZE], MAX_PAYLOAD_SIZE); + while (iso_tx_busy) { + if (tx_flag == 0) { + break; + } + } + } + } +#endif + } + } +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/webusb_template.c b/components/drivers/usb/cherryusb/demo/webusb_template.c new file mode 100644 index 00000000000..dc8bc573ffc --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/webusb_template.c @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" + +#define MS_OS_20_DESCRIPTOR_LENGTH (0xB2) + +#define WEBUSB_URL_STRINGS \ + 'd', 'e', 'v', 'a', 'n', 'l', 'a', 'i', '.', 'g', 'i', 't', 'h', 'u', 'b', '.', 'i', 'o', '/', 'w', 'e', 'b', 'd', 'f', 'u', '/', 'd', 'f', 'u', '-', 'u', 't', 'i', 'l' + +#define WL_REQUEST_WEBUSB (0x22) +#define WL_REQUEST_WINUSB (0x21) + +#define URL_DESCRIPTOR_LENGTH 0x2C + +// 描述符集信息 +const uint8_t MS_OS_20_DESCRIPTOR_SET[MS_OS_20_DESCRIPTOR_LENGTH] = { + // Microsoft OS 2.0 描述符集标头 + 0x0A, 0x00, // Descriptor size (10 bytes) + 0x00, 0x00, // MS OS 2.0 descriptor set header + 0x00, 0x00, 0x03, 0x06, // Windows version (8.1) (0x06030000) + MS_OS_20_DESCRIPTOR_LENGTH, 0x00, // Size, MS OS 2.0 descriptor set + + // Microsoft OS 2.0 配置子集标头 + 0x08, 0x00, // wLength + 0x01, 0x00, // wDescriptorType + 0x00, // 适用于配置 1 + 0x00, // bReserved + 0XA8, 0X00, // Size, MS OS 2.0 configuration subset + + // Microsoft OS 2.0 功能子集头 + 0x08, 0x00, // Descriptor size (8 bytes) + 0x02, 0x00, // MS OS 2.0 function subset header + 0x01, // 第2个接口 + 0x00, // 必须设置为 0 + 0xA0, 0x00, + + // Microsoft OS 2.0 兼容 ID 描述符 + // 兼容 ID 描述符告诉 Windows 此设备与 WinUSB 驱动程序兼容 + 0x14, 0x00, // wLength 20 + 0x03, 0x00, // MS_OS_20_FEATURE_COMPATIBLE_ID + 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + + // Microsoft OS 2.0 注册表属性描述符 + // 注册表属性分配设备接口 GUID + 0x84, 0x00, //wLength: 132 + 0x04, 0x00, // wDescriptorType: MS_OS_20_FEATURE_REG_PROPERTY: 0x04 (Table 9) + 0x07, 0x00, //wPropertyDataType: REG_MULTI_SZ (Table 15) + 0x2a, 0x00, //wPropertyNameLength: + //bPropertyName: “DeviceInterfaceGUID” + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, 't', 0x00, 'e', 0x00, + 'r', 0x00, 'f', 0x00, 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, 'U', 0x00, 'I', 0x00, 'D', 0x00, 's', 0x00, + 0x00, 0x00, + 0x50, 0x00, // wPropertyDataLength + //bPropertyData: “{975F44D9-0D08-43FD-8B3E-127CA8AFFF9D}”. + '{', 0x00, '9', 0x00, 'd', 0x00, '7', 0x00, 'd', 0x00, 'e', 0x00, 'b', 0x00, 'b', 0x00, 'c', 0x00, '-', 0x00, + 'c', 0x00, '8', 0x00, '5', 0x00, 'd', 0x00, '-', 0x00, '1', 0x00, '1', 0x00, 'd', 0x00, '1', 0x00, '-', 0x00, + '9', 0x00, 'e', 0x00, 'b', 0x00, '4', 0x00, '-', 0x00, '0', 0x00, '0', 0x00, '6', 0x00, '0', 0x00, '0', 0x00, + '8', 0x00, 'c', 0x00, '3', 0x00, 'a', 0x00, '1', 0x00, '9', 0x00, 'a', 0x00, '}', 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +const uint8_t USBD_WebUSBURLDescriptor[URL_DESCRIPTOR_LENGTH] = { + URL_DESCRIPTOR_LENGTH, + WEBUSB_URL_TYPE, + WEBUSB_URL_SCHEME_HTTPS, + WEBUSB_URL_STRINGS +}; + +struct usb_webusb_url_ex_descriptor webusb_url_desc = { + .vendor_code = WL_REQUEST_WEBUSB, + .string = MS_OS_20_DESCRIPTOR_SET, + .string_len = MS_OS_20_DESCRIPTOR_LENGTH +}; \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/winusb1.0_template.c b/components/drivers/usb/cherryusb/demo/winusb1.0_template.c new file mode 100644 index 00000000000..c1fbba934f5 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/winusb1.0_template.c @@ -0,0 +1,462 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc.h" + +#define WCID_VENDOR_CODE 0x17 + +#define DOUBLE_WINUSB 0 + +__ALIGN_BEGIN const uint8_t WCID_StringDescriptor_MSOS[18] __ALIGN_END = { + /////////////////////////////////////// + /// MS OS string descriptor + /////////////////////////////////////// + 0x12, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + /* MSFT100 */ + 'M', 0x00, 'S', 0x00, 'F', 0x00, 'T', 0x00, /* wcChar_7 */ + '1', 0x00, '0', 0x00, '0', 0x00, /* wcChar_7 */ + WCID_VENDOR_CODE, /* bVendorCode */ + 0x00, /* bReserved */ +}; + +#if DOUBLE_WINUSB == 0 +__ALIGN_BEGIN const uint8_t WINUSB_WCIDDescriptor[40] __ALIGN_END = { + /////////////////////////////////////// + /// WCID descriptor + /////////////////////////////////////// + 0x28, 0x00, 0x00, 0x00, /* dwLength */ + 0x00, 0x01, /* bcdVersion */ + 0x04, 0x00, /* wIndex */ + 0x01, /* bCount */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_7 */ + + /////////////////////////////////////// + /// WCID function descriptor + /////////////////////////////////////// + 0x00, /* bFirstInterfaceNumber */ + 0x01, /* bReserved */ + /* WINUSB */ + 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, /* cCID_8 */ + /* */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* cSubCID_8 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_6 */ +}; +#else +__ALIGN_BEGIN const uint8_t WINUSB_WCIDDescriptor[64] __ALIGN_END = { + /////////////////////////////////////// + /// WCID descriptor + /////////////////////////////////////// + 0x40, 0x00, 0x00, 0x00, /* dwLength */ + 0x00, 0x01, /* bcdVersion */ + 0x04, 0x00, /* wIndex */ + 0x02, /* bCount */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_7 */ + + /////////////////////////////////////// + /// WCID function descriptor + /////////////////////////////////////// + 0x00, /* bFirstInterfaceNumber */ + 0x01, /* bReserved */ + /* WINUSB */ + 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, /* cCID_8 */ + /* */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* cSubCID_8 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_6 */ + + /////////////////////////////////////// + /// WCID function descriptor + /////////////////////////////////////// + 0x01, /* bFirstInterfaceNumber */ + 0x01, /* bReserved */ + /* WINUSB */ + 'W', 'I', 'N', 'U', 'S', 'B', 0x00, 0x00, /* cCID_8 */ + /* */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* cSubCID_8 */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* bReserved_6 */ +}; +#endif +__ALIGN_BEGIN const uint8_t WINUSB_IF0_WCIDProperties [142] __ALIGN_END = { + /////////////////////////////////////// + /// WCID property descriptor + /////////////////////////////////////// + 0x8e, 0x00, 0x00, 0x00, /* dwLength */ + 0x00, 0x01, /* bcdVersion */ + 0x05, 0x00, /* wIndex */ + 0x01, 0x00, /* wCount */ + + /////////////////////////////////////// + /// registry propter descriptor + /////////////////////////////////////// + 0x84, 0x00, 0x00, 0x00, /* dwSize */ + 0x01, 0x00, 0x00, 0x00, /* dwPropertyDataType */ + 0x28, 0x00, /* wPropertyNameLength */ + /* DeviceInterfaceGUID */ + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, /* wcName_20 */ + 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, /* wcName_20 */ + 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, /* wcName_20 */ + 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, /* wcName_20 */ + 'U', 0x00, 'I', 0x00, 'D', 0x00, 0x00, 0x00, /* wcName_20 */ + 0x4e, 0x00, 0x00, 0x00, /* dwPropertyDataLength */ + /* {1D4B2365-4749-48EA-B38A-7C6FDDDD7E26} */ + '{', 0x00, '1', 0x00, 'D', 0x00, '4', 0x00, /* wcData_39 */ + 'B', 0x00, '2', 0x00, '3', 0x00, '6', 0x00, /* wcData_39 */ + '5', 0x00, '-', 0x00, '4', 0x00, '7', 0x00, /* wcData_39 */ + '4', 0x00, '9', 0x00, '-', 0x00, '4', 0x00, /* wcData_39 */ + '8', 0x00, 'E', 0x00, 'A', 0x00, '-', 0x00, /* wcData_39 */ + 'B', 0x00, '3', 0x00, '8', 0x00, 'A', 0x00, /* wcData_39 */ + '-', 0x00, '7', 0x00, 'C', 0x00, '6', 0x00, /* wcData_39 */ + 'F', 0x00, 'D', 0x00, 'D', 0x00, 'D', 0x00, /* wcData_39 */ + 'D', 0x00, '7', 0x00, 'E', 0x00, '2', 0x00, /* wcData_39 */ + '6', 0x00, '}', 0x00, 0x00, 0x00, /* wcData_39 */ +}; +#define WINUSB_IF1_WCID_PROPERTIES_SIZE (142) +__ALIGN_BEGIN const uint8_t WINUSB_IF1_WCIDProperties [142] __ALIGN_END = { + /////////////////////////////////////// + /// WCID property descriptor + /////////////////////////////////////// + 0x8e, 0x00, 0x00, 0x00, /* dwLength */ + 0x00, 0x01, /* bcdVersion */ + 0x05, 0x00, /* wIndex */ + 0x01, 0x00, /* wCount */ + + /////////////////////////////////////// + /// registry propter descriptor + /////////////////////////////////////// + 0x84, 0x00, 0x00, 0x00, /* dwSize */ + 0x01, 0x00, 0x00, 0x00, /* dwPropertyDataType */ + 0x28, 0x00, /* wPropertyNameLength */ + /* DeviceInterfaceGUID */ + 'D', 0x00, 'e', 0x00, 'v', 0x00, 'i', 0x00, /* wcName_20 */ + 'c', 0x00, 'e', 0x00, 'I', 0x00, 'n', 0x00, /* wcName_20 */ + 't', 0x00, 'e', 0x00, 'r', 0x00, 'f', 0x00, /* wcName_20 */ + 'a', 0x00, 'c', 0x00, 'e', 0x00, 'G', 0x00, /* wcName_20 */ + 'U', 0x00, 'I', 0x00, 'D', 0x00, 0x00, 0x00, /* wcName_20 */ + 0x4e, 0x00, 0x00, 0x00, /* dwPropertyDataLength */ + /* {1D4B2365-4749-48EA-B38A-7C6FDDDD7E26} */ + '{', 0x00, '1', 0x00, 'D', 0x00, '4', 0x00, /* wcData_39 */ + 'B', 0x00, '2', 0x00, '3', 0x00, '6', 0x00, /* wcData_39 */ + '5', 0x00, '-', 0x00, '4', 0x00, '7', 0x00, /* wcData_39 */ + '4', 0x00, '9', 0x00, '-', 0x00, '4', 0x00, /* wcData_39 */ + '8', 0x00, 'E', 0x00, 'A', 0x00, '-', 0x00, /* wcData_39 */ + 'B', 0x00, '3', 0x00, '8', 0x00, 'A', 0x00, /* wcData_39 */ + '-', 0x00, '7', 0x00, 'C', 0x00, '6', 0x00, /* wcData_39 */ + 'F', 0x00, 'D', 0x00, 'D', 0x00, 'D', 0x00, /* wcData_39 */ + 'D', 0x00, '7', 0x00, 'E', 0x00, '2', 0x00, /* wcData_39 */ + '6', 0x00, '}', 0x00, 0x00, 0x00, /* wcData_39 */ +}; + +const uint8_t *WINUSB_IFx_WCIDProperties[] = { + WINUSB_IF0_WCIDProperties, + WINUSB_IF1_WCIDProperties, +}; + +struct usb_msosv1_descriptor msosv1_desc = { + .string = WCID_StringDescriptor_MSOS, + .vendor_code = WCID_VENDOR_CODE, + .compat_id = WINUSB_WCIDDescriptor, +#if DOUBLE_WINUSB == 0 + .comp_id_property = &WINUSB_IF0_WCIDProperties, +#else + .comp_id_property = WINUSB_IFx_WCIDProperties, +#endif +}; + +#define WINUSB_IN_EP 0x81 +#define WINUSB_OUT_EP 0x02 + +#define USBD_VID 0xefff +#define USBD_PID 0xffff +#define USBD_MAX_POWER 100 +#define USBD_LANGID_STRING 1033 + +#if DOUBLE_WINUSB == 0 +#define USB_CONFIG_SIZE (9 + 9 + 7 + 7) +#define INTF_NUM 1 +#else +#define WINUSB_IN_EP2 0x83 +#define WINUSB_OUT_EP2 0x04 + +#define USB_CONFIG_SIZE (9 + 9 + 7 + 7 + 9 + 7 + 7) +#define INTF_NUM 2 +#endif + +#ifdef CONFIG_USB_HS +#define WINUSB_EP_MPS 512 +#else +#define WINUSB_EP_MPS 64 +#endif + +const uint8_t winusb_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01), + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xff, 0xff, 0x00, 0x04), + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP, 0x02, WINUSB_EP_MPS, 0x00), + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP, 0x02, WINUSB_EP_MPS, 0x00), +#if DOUBLE_WINUSB == 1 + USB_INTERFACE_DESCRIPTOR_INIT(0x01, 0x00, 0x02, 0xff, 0xff, 0x00, 0x05), + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP2, 0x02, WINUSB_EP_MPS, 0x00), + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP2, 0x02, WINUSB_EP_MPS, 0x00), +#endif + /////////////////////////////////////// + /// string0 descriptor + /////////////////////////////////////// + USB_LANGID_INIT(USBD_LANGID_STRING), + /////////////////////////////////////// + /// string1 descriptor + /////////////////////////////////////// + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /////////////////////////////////////// + /// string2 descriptor + /////////////////////////////////////// + 0x2C, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'W', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'N', 0x00, /* wcChar12 */ + 'U', 0x00, /* wcChar13 */ + 'S', 0x00, /* wcChar14 */ + 'B', 0x00, /* wcChar15 */ + ' ', 0x00, /* wcChar16 */ + 'D', 0x00, /* wcChar17 */ + 'E', 0x00, /* wcChar18 */ + 'M', 0x00, /* wcChar19 */ + 'O', 0x00, /* wcChar20 */ + /////////////////////////////////////// + /// string3 descriptor + /////////////////////////////////////// + 0x16, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '2', 0x00, /* wcChar0 */ + '0', 0x00, /* wcChar1 */ + '2', 0x00, /* wcChar2 */ + '1', 0x00, /* wcChar3 */ + '0', 0x00, /* wcChar4 */ + '3', 0x00, /* wcChar5 */ + '1', 0x00, /* wcChar6 */ + '0', 0x00, /* wcChar7 */ + '0', 0x00, /* wcChar8 */ + '0', 0x00, /* wcChar9 */ + /////////////////////////////////////// + /// string4 descriptor + /////////////////////////////////////// + 0x30, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'W', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'N', 0x00, /* wcChar12 */ + 'U', 0x00, /* wcChar13 */ + 'S', 0x00, /* wcChar14 */ + 'B', 0x00, /* wcChar15 */ + ' ', 0x00, /* wcChar16 */ + 'D', 0x00, /* wcChar17 */ + 'E', 0x00, /* wcChar18 */ + 'M', 0x00, /* wcChar19 */ + 'O', 0x00, /* wcChar20 */ + ' ', 0x00, /* wcChar16 */ + '1', 0x00, /* wcChar21 */ + /////////////////////////////////////// + /// string5 descriptor + /////////////////////////////////////// + 0x30, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'W', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'N', 0x00, /* wcChar12 */ + 'U', 0x00, /* wcChar13 */ + 'S', 0x00, /* wcChar14 */ + 'B', 0x00, /* wcChar15 */ + ' ', 0x00, /* wcChar16 */ + 'D', 0x00, /* wcChar17 */ + 'E', 0x00, /* wcChar18 */ + 'M', 0x00, /* wcChar19 */ + 'O', 0x00, /* wcChar20 */ + ' ', 0x00, /* wcChar16 */ + '2', 0x00, /* wcChar21 */ +#ifdef CONFIG_USB_HS + /////////////////////////////////////// + /// device qualifier descriptor + /////////////////////////////////////// + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x00, + 0x02, + 0x02, + 0x02, + 0x01, + 0x40, + 0x01, + 0x00, +#endif + 0x00 +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; + +volatile bool ep_tx_busy_flag = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + ep_tx_busy_flag = false; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); +#if DOUBLE_WINUSB == 1 + usbd_ep_start_read(busid, WINUSB_OUT_EP2, read_buffer, 2048); +#endif + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_winusb_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + // for (int i = 0; i < 100; i++) { + // printf("%02x ", read_buffer[i]); + // } + // printf("\r\n"); + usbd_ep_start_write(busid, WINUSB_IN_EP, read_buffer, nbytes); + /* setup next out ep read transfer */ + usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); +} + +void usbd_winusb_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + + if ((nbytes % WINUSB_EP_MPS) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(busid, WINUSB_IN_EP, NULL, 0); + } else { + ep_tx_busy_flag = false; + } +} + +struct usbd_endpoint winusb_out_ep1 = { + .ep_addr = WINUSB_OUT_EP, + .ep_cb = usbd_winusb_out +}; + +struct usbd_endpoint winusb_in_ep1 = { + .ep_addr = WINUSB_IN_EP, + .ep_cb = usbd_winusb_in +}; + +struct usbd_interface intf0; + +#if DOUBLE_WINUSB == 1 + +void usbd_winusb_out2(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + // for (int i = 0; i < 100; i++) { + // printf("%02x ", read_buffer[i]); + // } + // printf("\r\n"); + usbd_ep_start_write(busid, WINUSB_IN_EP2, read_buffer, nbytes); + /* setup next out ep read transfer */ + usbd_ep_start_read(busid, WINUSB_OUT_EP2, read_buffer, 2048); +} + +void usbd_winusb_in2(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(busid, WINUSB_IN_EP2, NULL, 0); + } else { + ep_tx_busy_flag = false; + } +} + +struct usbd_endpoint winusb_out_ep2 = { + .ep_addr = WINUSB_OUT_EP2, + .ep_cb = usbd_winusb_out2 +}; + +struct usbd_endpoint winusb_in_ep2 = { + .ep_addr = WINUSB_IN_EP2, + .ep_cb = usbd_winusb_in2 +}; + +struct usbd_interface intf1; + +#endif + +void winusb_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, winusb_descriptor); + usbd_msosv1_desc_register(busid, &msosv1_desc); + usbd_add_interface(busid, &intf0); + usbd_add_endpoint(busid, &winusb_out_ep1); + usbd_add_endpoint(busid, &winusb_in_ep1); +#if DOUBLE_WINUSB == 1 + usbd_add_interface(busid, &intf1); + usbd_add_endpoint(busid, &winusb_out_ep2); + usbd_add_endpoint(busid, &winusb_in_ep2); +#endif + usbd_initialize(busid, reg_base, usbd_event_handler); +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c b/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c new file mode 100644 index 00000000000..8fe6e995aba --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/winusb2.0_cdc_template.c @@ -0,0 +1,339 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc.h" + +#define WINUSB_IN_EP 0x81 +#define WINUSB_OUT_EP 0x02 + +#define CDC_IN_EP 0x83 +#define CDC_OUT_EP 0x04 +#define CDC_INT_EP 0x85 + +#define USBD_VID 0xFFFE +#define USBD_PID 0xFFFF +#define USBD_MAX_POWER 500 +#define USBD_LANGID_STRING 1033 + +#define USB_CONFIG_SIZE (9 + 9 + 7 + 7 + CDC_ACM_DESCRIPTOR_LEN) +#define INTF_NUM 3 + +#ifdef CONFIG_USB_HS +#define WINUSB_EP_MPS 512 +#else +#define WINUSB_EP_MPS 64 +#endif + +#define USBD_WINUSB_VENDOR_CODE 0x20 + +#define USBD_WEBUSB_ENABLE 0 +#define USBD_BULK_ENABLE 1 +#define USBD_WINUSB_ENABLE 1 + +/* WinUSB Microsoft OS 2.0 descriptor sizes */ +#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 +#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 +#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 + +#define FUNCTION_SUBSET_LEN 160 +#define DEVICE_INTERFACE_GUIDS_FEATURE_LEN 132 + +#define USBD_WINUSB_DESC_SET_LEN (WINUSB_DESCRIPTOR_SET_HEADER_SIZE + USBD_WEBUSB_ENABLE * FUNCTION_SUBSET_LEN + USBD_BULK_ENABLE * FUNCTION_SUBSET_LEN) + +__ALIGN_BEGIN const uint8_t USBD_WinUSBDescriptorSetDescriptor[] = { + WBVAL(WINUSB_DESCRIPTOR_SET_HEADER_SIZE), /* wLength */ + WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */ + 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ + WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ +#if (USBD_WEBUSB_ENABLE) + WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), // wLength + WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), // wDescriptorType + 0, // bFirstInterface USBD_WINUSB_IF_NUM + 0, // bReserved + WBVAL(FUNCTION_SUBSET_LEN), // wSubsetLength + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), // wLength + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), // wDescriptorType + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, // CompatibleId + 0, 0, 0, 0, 0, 0, 0, 0, // SubCompatibleId + WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), // wLength + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), // wDescriptorType + WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), // wPropertyDataType + WBVAL(42), // wPropertyNameLength + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, + WBVAL(80), // wPropertyDataLength + '{', 0, + '9', 0, '2', 0, 'C', 0, 'E', 0, '6', 0, '4', 0, '6', 0, '2', 0, '-', 0, + '9', 0, 'C', 0, '7', 0, '7', 0, '-', 0, + '4', 0, '6', 0, 'F', 0, 'E', 0, '-', 0, + '9', 0, '3', 0, '3', 0, 'B', 0, '-', + 0, '3', 0, '1', 0, 'C', 0, 'B', 0, '9', 0, 'C', 0, '5', 0, 'A', 0, 'A', 0, '3', 0, 'B', 0, '9', 0, + '}', 0, 0, 0, 0, 0 +#endif +#if USBD_BULK_ENABLE + WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), /* wLength */ + WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), /* wDescriptorType */ + 0, /* bFirstInterface USBD_BULK_IF_NUM*/ + 0, /* bReserved */ + WBVAL(FUNCTION_SUBSET_LEN), /* wSubsetLength */ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ + 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ + WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), /* wLength */ + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ + WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), /* wPropertyDataType */ + WBVAL(42), /* wPropertyNameLength */ + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, + WBVAL(80), /* wPropertyDataLength */ + '{', 0, + 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, + '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, + '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, + 'A', 0, 'A', 0, '3', 0, '6', 0, '-', + 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, + '}', 0, 0, 0, 0, 0 +#endif +}; + +#define USBD_NUM_DEV_CAPABILITIES (USBD_WEBUSB_ENABLE + USBD_WINUSB_ENABLE) + +#define USBD_WEBUSB_DESC_LEN 24 +#define USBD_WINUSB_DESC_LEN 28 + +#define USBD_BOS_WTOTALLENGTH (0x05 + \ + USBD_WEBUSB_DESC_LEN * USBD_WEBUSB_ENABLE + \ + USBD_WINUSB_DESC_LEN * USBD_WINUSB_ENABLE) + +__ALIGN_BEGIN const uint8_t USBD_BinaryObjectStoreDescriptor[] = { + 0x05, /* bLength */ + 0x0f, /* bDescriptorType */ + WBVAL(USBD_BOS_WTOTALLENGTH), /* wTotalLength */ + USBD_NUM_DEV_CAPABILITIES, /* bNumDeviceCaps */ +#if (USBD_WEBUSB_ENABLE) + USBD_WEBUSB_DESC_LEN, /* bLength */ + 0x10, /* bDescriptorType */ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ + 0x00, /* bReserved */ + 0x38, 0xB6, 0x08, 0x34, /* PlatformCapabilityUUID */ + 0xA9, 0x09, 0xA0, 0x47, + 0x8B, 0xFD, 0xA0, 0x76, + 0x88, 0x15, 0xB6, 0x65, + WBVAL(0x0100), /* 1.00 */ /* bcdVersion */ + USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ + 0, /* iLandingPage */ +#endif +#if (USBD_WINUSB_ENABLE) + USBD_WINUSB_DESC_LEN, /* bLength */ + 0x10, /* bDescriptorType */ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ + 0x00, /* bReserved */ + 0xDF, 0x60, 0xDD, 0xD8, /* PlatformCapabilityUUID */ + 0x89, 0x45, 0xC7, 0x4C, + 0x9C, 0xD2, 0x65, 0x9D, + 0x9E, 0x64, 0x8A, 0x9F, + 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ + WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ + USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ + 0, /* bAltEnumCode */ +#endif +}; + +const uint8_t winusbv2_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), + /* Configuration 0 */ + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + /* Interface 0 */ + USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xFF, 0x00, 0x00, 0x02), + /* Endpoint OUT 2 */ + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP, USB_ENDPOINT_TYPE_BULK, WINUSB_EP_MPS, 0x00), + /* Endpoint IN 1 */ + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP, USB_ENDPOINT_TYPE_BULK, WINUSB_EP_MPS, 0x00), + CDC_ACM_DESCRIPTOR_INIT(0x01, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, WINUSB_EP_MPS, 0x00), + /* String 0 (LANGID) */ + USB_LANGID_INIT(USBD_LANGID_STRING), + /* String 1 (Manufacturer) */ + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /* String 2 (Product) */ + 0x2C, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'W', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'N', 0x00, /* wcChar12 */ + 'U', 0x00, /* wcChar13 */ + 'S', 0x00, /* wcChar14 */ + 'B', 0x00, /* wcChar15 */ + ' ', 0x00, /* wcChar16 */ + 'D', 0x00, /* wcChar17 */ + 'E', 0x00, /* wcChar18 */ + 'M', 0x00, /* wcChar19 */ + 'O', 0x00, /* wcChar20 */ + /* String 3 (Serial Number) */ + 0x1A, // bLength + USB_DESCRIPTOR_TYPE_STRING, // bDescriptorType + '0', 0, // wcChar0 + '1', 0, // wcChar1 + '2', 0, // wcChar2 + '3', 0, // wcChar3 + '4', 0, // wcChar4 + '5', 0, // wcChar5 + 'A', 0, // wcChar6 + 'B', 0, // wcChar7 + 'C', 0, // wcChar8 + 'D', 0, // wcChar9 + 'E', 0, // wcChar10 + 'F', 0, // wcChar11 +#ifdef CONFIG_USB_HS + /* Device Qualifier */ + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x10, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + /* End */ + 0x00 +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; + +volatile bool ep_tx_busy_flag = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + ep_tx_busy_flag = false; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_winusb_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + // for (int i = 0; i < 100; i++) { + // printf("%02x ", read_buffer[i]); + // } + // printf("\r\n"); + usbd_ep_start_write(busid, WINUSB_IN_EP, read_buffer, nbytes); + /* setup next out ep read transfer */ + usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); +} + +void usbd_winusb_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(busid, WINUSB_IN_EP, NULL, 0); + } else { + ep_tx_busy_flag = false; + } +} + +struct usbd_endpoint winusb_out_ep1 = { + .ep_addr = WINUSB_OUT_EP, + .ep_cb = usbd_winusb_out +}; + +struct usbd_endpoint winusb_in_ep1 = { + .ep_addr = WINUSB_IN_EP, + .ep_cb = usbd_winusb_in +}; + +static struct usbd_endpoint cdc_out_ep = { + .ep_addr = CDC_OUT_EP, + .ep_cb = NULL +}; + +static struct usbd_endpoint cdc_in_ep = { + .ep_addr = CDC_IN_EP, + .ep_cb = NULL +}; + +struct usbd_interface winusb_intf; +struct usbd_interface intf1; +struct usbd_interface intf2; + +struct usb_msosv2_descriptor msosv2_desc = { + .vendor_code = USBD_WINUSB_VENDOR_CODE, + .compat_id = USBD_WinUSBDescriptorSetDescriptor, + .compat_id_len = USBD_WINUSB_DESC_SET_LEN, +}; + +struct usb_bos_descriptor bos_desc = { + .string = USBD_BinaryObjectStoreDescriptor, + .string_len = USBD_BOS_WTOTALLENGTH +}; + +void winusbv2_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, winusbv2_descriptor); + usbd_bos_desc_register(busid, &bos_desc); + usbd_msosv2_desc_register(busid, &msosv2_desc); + + /*!< winusb */ + usbd_add_interface(busid, &winusb_intf); + usbd_add_endpoint(busid, &winusb_out_ep1); + usbd_add_endpoint(busid, &winusb_in_ep1); + + /*!< cdc acm */ + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf2)); + usbd_add_endpoint(busid, &cdc_out_ep); + usbd_add_endpoint(busid, &cdc_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c b/components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c new file mode 100644 index 00000000000..8df623edbe4 --- /dev/null +++ b/components/drivers/usb/cherryusb/demo/winusb2.0_hid_template.c @@ -0,0 +1,440 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" + +#define WINUSB_IN_EP 0x81 +#define WINUSB_OUT_EP 0x02 + +/*!< endpoint address */ +#define HID_INT_EP 0x83 +#define HID_INT_EP_SIZE 4 +#define HID_INT_EP_INTERVAL 10 + +#define USBD_VID 0xFFFE +#define USBD_PID 0xFFFF +#define USBD_MAX_POWER 500 +#define USBD_LANGID_STRING 1033 + +#define USB_CONFIG_SIZE (9 + 9 + 7 + 7 + 9 + 9 + 7) +#define INTF_NUM 2 + +/*!< config descriptor size */ +#define USB_HID_CONFIG_DESC_SIZ 34 +/*!< report descriptor size */ +#define HID_MOUSE_REPORT_DESC_SIZE 74 + +#ifdef CONFIG_USB_HS +#define WINUSB_EP_MPS 512 +#else +#define WINUSB_EP_MPS 64 +#endif + +#define USBD_WINUSB_VENDOR_CODE 0x20 + +#define USBD_WEBUSB_ENABLE 0 +#define USBD_BULK_ENABLE 1 +#define USBD_WINUSB_ENABLE 1 + +/* WinUSB Microsoft OS 2.0 descriptor sizes */ +#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 +#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 +#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 + +#define FUNCTION_SUBSET_LEN 160 +#define DEVICE_INTERFACE_GUIDS_FEATURE_LEN 132 + +#define USBD_WINUSB_DESC_SET_LEN (WINUSB_DESCRIPTOR_SET_HEADER_SIZE + USBD_WEBUSB_ENABLE * FUNCTION_SUBSET_LEN + USBD_BULK_ENABLE * FUNCTION_SUBSET_LEN) + +__ALIGN_BEGIN const uint8_t USBD_WinUSBDescriptorSetDescriptor[] = { + WBVAL(WINUSB_DESCRIPTOR_SET_HEADER_SIZE), /* wLength */ + WBVAL(WINUSB_SET_HEADER_DESCRIPTOR_TYPE), /* wDescriptorType */ + 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ + WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ +#if (USBD_WEBUSB_ENABLE) + WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), // wLength + WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), // wDescriptorType + 0, // bFirstInterface USBD_WINUSB_IF_NUM + 0, // bReserved + WBVAL(FUNCTION_SUBSET_LEN), // wSubsetLength + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), // wLength + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), // wDescriptorType + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, // CompatibleId + 0, 0, 0, 0, 0, 0, 0, 0, // SubCompatibleId + WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), // wLength + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), // wDescriptorType + WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), // wPropertyDataType + WBVAL(42), // wPropertyNameLength + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, + WBVAL(80), // wPropertyDataLength + '{', 0, + '9', 0, '2', 0, 'C', 0, 'E', 0, '6', 0, '4', 0, '6', 0, '2', 0, '-', 0, + '9', 0, 'C', 0, '7', 0, '7', 0, '-', 0, + '4', 0, '6', 0, 'F', 0, 'E', 0, '-', 0, + '9', 0, '3', 0, '3', 0, 'B', 0, '-', + 0, '3', 0, '1', 0, 'C', 0, 'B', 0, '9', 0, 'C', 0, '5', 0, 'A', 0, 'A', 0, '3', 0, 'B', 0, '9', 0, + '}', 0, 0, 0, 0, 0 +#endif +#if USBD_BULK_ENABLE + WBVAL(WINUSB_FUNCTION_SUBSET_HEADER_SIZE), /* wLength */ + WBVAL(WINUSB_SUBSET_HEADER_FUNCTION_TYPE), /* wDescriptorType */ + 0, /* bFirstInterface USBD_BULK_IF_NUM*/ + 0, /* bReserved */ + WBVAL(FUNCTION_SUBSET_LEN), /* wSubsetLength */ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_SIZE), /* wLength */ + WBVAL(WINUSB_FEATURE_COMPATIBLE_ID_TYPE), /* wDescriptorType */ + 'W', 'I', 'N', 'U', 'S', 'B', 0, 0, /* CompatibleId*/ + 0, 0, 0, 0, 0, 0, 0, 0, /* SubCompatibleId*/ + WBVAL(DEVICE_INTERFACE_GUIDS_FEATURE_LEN), /* wLength */ + WBVAL(WINUSB_FEATURE_REG_PROPERTY_TYPE), /* wDescriptorType */ + WBVAL(WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ), /* wPropertyDataType */ + WBVAL(42), /* wPropertyNameLength */ + 'D', 0, 'e', 0, 'v', 0, 'i', 0, 'c', 0, 'e', 0, + 'I', 0, 'n', 0, 't', 0, 'e', 0, 'r', 0, 'f', 0, 'a', 0, 'c', 0, 'e', 0, + 'G', 0, 'U', 0, 'I', 0, 'D', 0, 's', 0, 0, 0, + WBVAL(80), /* wPropertyDataLength */ + '{', 0, + 'C', 0, 'D', 0, 'B', 0, '3', 0, 'B', 0, '5', 0, 'A', 0, 'D', 0, '-', 0, + '2', 0, '9', 0, '3', 0, 'B', 0, '-', 0, + '4', 0, '6', 0, '6', 0, '3', 0, '-', 0, + 'A', 0, 'A', 0, '3', 0, '6', 0, '-', + 0, '1', 0, 'A', 0, 'A', 0, 'E', 0, '4', 0, '6', 0, '4', 0, '6', 0, '3', 0, '7', 0, '7', 0, '6', 0, + '}', 0, 0, 0, 0, 0 +#endif +}; + +#define USBD_NUM_DEV_CAPABILITIES (USBD_WEBUSB_ENABLE + USBD_WINUSB_ENABLE) + +#define USBD_WEBUSB_DESC_LEN 24 +#define USBD_WINUSB_DESC_LEN 28 + +#define USBD_BOS_WTOTALLENGTH (0x05 + \ + USBD_WEBUSB_DESC_LEN * USBD_WEBUSB_ENABLE + \ + USBD_WINUSB_DESC_LEN * USBD_WINUSB_ENABLE) + +__ALIGN_BEGIN const uint8_t USBD_BinaryObjectStoreDescriptor[] = { + 0x05, /* bLength */ + 0x0f, /* bDescriptorType */ + WBVAL(USBD_BOS_WTOTALLENGTH), /* wTotalLength */ + USBD_NUM_DEV_CAPABILITIES, /* bNumDeviceCaps */ +#if (USBD_WEBUSB_ENABLE) + USBD_WEBUSB_DESC_LEN, /* bLength */ + 0x10, /* bDescriptorType */ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ + 0x00, /* bReserved */ + 0x38, 0xB6, 0x08, 0x34, /* PlatformCapabilityUUID */ + 0xA9, 0x09, 0xA0, 0x47, + 0x8B, 0xFD, 0xA0, 0x76, + 0x88, 0x15, 0xB6, 0x65, + WBVAL(0x0100), /* 1.00 */ /* bcdVersion */ + USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ + 0, /* iLandingPage */ +#endif +#if (USBD_WINUSB_ENABLE) + USBD_WINUSB_DESC_LEN, /* bLength */ + 0x10, /* bDescriptorType */ + USB_DEVICE_CAPABILITY_PLATFORM, /* bDevCapabilityType */ + 0x00, /* bReserved */ + 0xDF, 0x60, 0xDD, 0xD8, /* PlatformCapabilityUUID */ + 0x89, 0x45, 0xC7, 0x4C, + 0x9C, 0xD2, 0x65, 0x9D, + 0x9E, 0x64, 0x8A, 0x9F, + 0x00, 0x00, 0x03, 0x06, /* >= Win 8.1 */ /* dwWindowsVersion*/ + WBVAL(USBD_WINUSB_DESC_SET_LEN), /* wDescriptorSetTotalLength */ + USBD_WINUSB_VENDOR_CODE, /* bVendorCode */ + 0, /* bAltEnumCode */ +#endif +}; + +const uint8_t winusbv2_descriptor[] = { + USB_DEVICE_DESCRIPTOR_INIT(USB_2_1, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), + /* Configuration 0 */ + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, INTF_NUM, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), + /* Interface 0 */ + USB_INTERFACE_DESCRIPTOR_INIT(0x00, 0x00, 0x02, 0xFF, 0x00, 0x00, 0x02), + /* Endpoint OUT 2 */ + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_OUT_EP, USB_ENDPOINT_TYPE_BULK, WINUSB_EP_MPS, 0x00), + /* Endpoint IN 1 */ + USB_ENDPOINT_DESCRIPTOR_INIT(WINUSB_IN_EP, USB_ENDPOINT_TYPE_BULK, WINUSB_EP_MPS, 0x00), + /************** Descriptor of Joystick Mouse interface ****************/ + /* 09 */ + 0x09, /* bLength: Interface Descriptor size */ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ + 0x01, /* bInterfaceNumber: Number of Interface */ + 0x00, /* bAlternateSetting: Alternate setting */ + 0x01, /* bNumEndpoints */ + 0x03, /* bInterfaceClass: HID */ + 0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ + 0, /* iInterface: Index of string descriptor */ + /******************** Descriptor of Joystick Mouse HID ********************/ + /* 18 */ + 0x09, /* bLength: HID Descriptor size */ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ + 0x11, /* bcdHID: HID Class Spec release number */ + 0x01, + 0x00, /* bCountryCode: Hardware target country */ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ + 0x22, /* bDescriptorType */ + HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */ + 0x00, + /******************** Descriptor of Mouse endpoint ********************/ + /* 27 */ + 0x07, /* bLength: Endpoint Descriptor size */ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ + HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */ + 0x03, /* bmAttributes: Interrupt endpoint */ + HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */ + 0x00, + HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */ + /* String 0 (LANGID) */ + USB_LANGID_INIT(USBD_LANGID_STRING), + /* String 1 (Manufacturer) */ + 0x14, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + /* String 2 (Product) */ + 0x2C, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'C', 0x00, /* wcChar0 */ + 'h', 0x00, /* wcChar1 */ + 'e', 0x00, /* wcChar2 */ + 'r', 0x00, /* wcChar3 */ + 'r', 0x00, /* wcChar4 */ + 'y', 0x00, /* wcChar5 */ + 'U', 0x00, /* wcChar6 */ + 'S', 0x00, /* wcChar7 */ + 'B', 0x00, /* wcChar8 */ + ' ', 0x00, /* wcChar9 */ + 'W', 0x00, /* wcChar10 */ + 'I', 0x00, /* wcChar11 */ + 'N', 0x00, /* wcChar12 */ + 'U', 0x00, /* wcChar13 */ + 'S', 0x00, /* wcChar14 */ + 'B', 0x00, /* wcChar15 */ + ' ', 0x00, /* wcChar16 */ + 'D', 0x00, /* wcChar17 */ + 'E', 0x00, /* wcChar18 */ + 'M', 0x00, /* wcChar19 */ + 'O', 0x00, /* wcChar20 */ + /* String 3 (Serial Number) */ + 0x1A, // bLength + USB_DESCRIPTOR_TYPE_STRING, // bDescriptorType + '0', 0, // wcChar0 + '1', 0, // wcChar1 + '2', 0, // wcChar2 + '3', 0, // wcChar3 + '4', 0, // wcChar4 + '5', 0, // wcChar5 + 'A', 0, // wcChar6 + 'B', 0, // wcChar7 + 'C', 0, // wcChar8 + 'D', 0, // wcChar9 + 'E', 0, // wcChar10 + 'F', 0, // wcChar11 +#ifdef CONFIG_USB_HS + /* Device Qualifier */ + 0x0a, + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, + 0x10, + 0x02, + 0x00, + 0x00, + 0x00, + 0x40, + 0x01, + 0x00, +#endif + /* End */ + 0x00 +}; + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t read_buffer[2048]; +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t write_buffer[2048]; + +volatile bool ep_tx_busy_flag = false; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + break; + case USBD_EVENT_CONNECTED: + break; + case USBD_EVENT_DISCONNECTED: + break; + case USBD_EVENT_RESUME: + break; + case USBD_EVENT_SUSPEND: + break; + case USBD_EVENT_CONFIGURED: + ep_tx_busy_flag = false; + /* setup first out ep read transfer */ + usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_winusb_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual out len:%d\r\n", nbytes); + // for (int i = 0; i < 100; i++) { + // printf("%02x ", read_buffer[i]); + // } + // printf("\r\n"); + usbd_ep_start_write(busid, WINUSB_IN_EP, read_buffer, nbytes); + /* setup next out ep read transfer */ + usbd_ep_start_read(busid, WINUSB_OUT_EP, read_buffer, 2048); +} + +void usbd_winusb_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + USB_LOG_RAW("actual in len:%d\r\n", nbytes); + + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(busid, WINUSB_IN_EP, NULL, 0); + } else { + ep_tx_busy_flag = false; + } +} + +struct usbd_endpoint winusb_out_ep1 = { + .ep_addr = WINUSB_OUT_EP, + .ep_cb = usbd_winusb_out +}; + +struct usbd_endpoint winusb_in_ep1 = { + .ep_addr = WINUSB_IN_EP, + .ep_cb = usbd_winusb_in +}; + +/*!< hid mouse report descriptor */ +static const uint8_t hid_mouse_report_desc[HID_MOUSE_REPORT_DESC_SIZE] = { + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x02, // USAGE (Mouse) + 0xA1, 0x01, // COLLECTION (Application) + 0x09, 0x01, // USAGE (Pointer) + + 0xA1, 0x00, // COLLECTION (Physical) + 0x05, 0x09, // USAGE_PAGE (Button) + 0x19, 0x01, // USAGE_MINIMUM (Button 1) + 0x29, 0x03, // USAGE_MAXIMUM (Button 3) + + 0x15, 0x00, // LOGICAL_MINIMUM (0) + 0x25, 0x01, // LOGICAL_MAXIMUM (1) + 0x95, 0x03, // REPORT_COUNT (3) + 0x75, 0x01, // REPORT_SIZE (1) + + 0x81, 0x02, // INPUT (Data,Var,Abs) + 0x95, 0x01, // REPORT_COUNT (1) + 0x75, 0x05, // REPORT_SIZE (5) + 0x81, 0x01, // INPUT (Cnst,Var,Abs) + + 0x05, 0x01, // USAGE_PAGE (Generic Desktop) + 0x09, 0x30, // USAGE (X) + 0x09, 0x31, // USAGE (Y) + 0x09, 0x38, + + 0x15, 0x81, // LOGICAL_MINIMUM (-127) + 0x25, 0x7F, // LOGICAL_MAXIMUM (127) + 0x75, 0x08, // REPORT_SIZE (8) + 0x95, 0x03, // REPORT_COUNT (2) + + 0x81, 0x06, // INPUT (Data,Var,Rel) + 0xC0, 0x09, + 0x3c, 0x05, + 0xff, 0x09, + + 0x01, 0x15, + 0x00, 0x25, + 0x01, 0x75, + 0x01, 0x95, + + 0x02, 0xb1, + 0x22, 0x75, + 0x06, 0x95, + 0x01, 0xb1, + + 0x01, 0xc0 // END_COLLECTION +}; + +/*!< mouse report struct */ +struct hid_mouse { + uint8_t buttons; + int8_t x; + int8_t y; + int8_t wheel; +}; + +/*!< mouse report */ +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX struct hid_mouse mouse_cfg; + +#define HID_STATE_IDLE 0 +#define HID_STATE_BUSY 1 + +/*!< hid state ! Data can be sent only when state is idle */ +static volatile uint8_t hid_state = HID_STATE_IDLE; + +/* function ------------------------------------------------------------------*/ +static void usbd_hid_int_callback(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + hid_state = HID_STATE_IDLE; +} + +/*!< endpoint call back */ +static struct usbd_endpoint hid_in_ep = { + .ep_cb = usbd_hid_int_callback, + .ep_addr = HID_INT_EP +}; + +struct usbd_interface winusb_intf; +struct usbd_interface intf1; + +struct usb_msosv2_descriptor msosv2_desc = { + .vendor_code = USBD_WINUSB_VENDOR_CODE, + .compat_id = USBD_WinUSBDescriptorSetDescriptor, + .compat_id_len = USBD_WINUSB_DESC_SET_LEN, +}; + +struct usb_bos_descriptor bos_desc = { + .string = USBD_BinaryObjectStoreDescriptor, + .string_len = USBD_BOS_WTOTALLENGTH +}; + +void winusbv2_init(uint8_t busid, uint32_t reg_base) +{ + usbd_desc_register(busid, winusbv2_descriptor); + usbd_bos_desc_register(busid, &bos_desc); + usbd_msosv2_desc_register(busid, &msosv2_desc); + + /*!< winusb */ + usbd_add_interface(busid, &winusb_intf); + usbd_add_endpoint(busid, &winusb_out_ep1); + usbd_add_endpoint(busid, &winusb_in_ep1); + + usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf1, hid_mouse_report_desc, HID_MOUSE_REPORT_DESC_SIZE)); + usbd_add_endpoint(busid, &hid_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/osal/usb_osal_rtthread.c b/components/drivers/usb/cherryusb/osal/usb_osal_rtthread.c new file mode 100644 index 00000000000..18b66a49618 --- /dev/null +++ b/components/drivers/usb/cherryusb/osal/usb_osal_rtthread.c @@ -0,0 +1,169 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_osal.h" +#include "usb_errno.h" +#include +#include + +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args) +{ + rt_thread_t htask; + htask = rt_thread_create(name, entry, args, stack_size, prio, 10); + rt_thread_startup(htask); + return (usb_osal_thread_t)htask; +} + +void usb_osal_thread_delete(usb_osal_thread_t thread) +{ + if (thread == NULL) { + return; + } + + rt_thread_delete(thread); +} + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count) +{ + return (usb_osal_sem_t)rt_sem_create("usbh_sem", initial_count, RT_IPC_FLAG_FIFO); +} + +void usb_osal_sem_delete(usb_osal_sem_t sem) +{ + rt_sem_delete((rt_sem_t)sem); +} + +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout) +{ + int ret = 0; + rt_err_t result = RT_EOK; + + if (timeout == USB_OSAL_WAITING_FOREVER) { + result = rt_sem_take((rt_sem_t)sem, RT_WAITING_FOREVER); + } else { + result = rt_sem_take((rt_sem_t)sem, rt_tick_from_millisecond(timeout)); + } + if (result == -RT_ETIMEOUT) { + ret = -USB_ERR_TIMEOUT; + } else if (result == -RT_ERROR) { + ret = -USB_ERR_INVAL; + } else { + ret = 0; + } + + return (int)ret; +} + +int usb_osal_sem_give(usb_osal_sem_t sem) +{ + return (int)rt_sem_release((rt_sem_t)sem); +} + +void usb_osal_sem_reset(usb_osal_sem_t sem) +{ + rt_sem_control((rt_sem_t)sem, RT_IPC_CMD_RESET, (void *)0); +} + +usb_osal_mutex_t usb_osal_mutex_create(void) +{ + return (usb_osal_mutex_t)rt_mutex_create("usbh_mutex", RT_IPC_FLAG_FIFO); +} + +void usb_osal_mutex_delete(usb_osal_mutex_t mutex) +{ + rt_mutex_delete((rt_mutex_t)mutex); +} + +int usb_osal_mutex_take(usb_osal_mutex_t mutex) +{ + return (int)rt_mutex_take((rt_mutex_t)mutex, RT_WAITING_FOREVER); +} + +int usb_osal_mutex_give(usb_osal_mutex_t mutex) +{ + return (int)rt_mutex_release((rt_mutex_t)mutex); +} + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs) +{ + return (usb_osal_mq_t)rt_mq_create("usbh_mq", sizeof(uintptr_t), max_msgs, RT_IPC_FLAG_FIFO); +} + +void usb_osal_mq_delete(usb_osal_mq_t mq) +{ + rt_mq_delete((rt_mq_t)mq); +} + +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr) +{ + return rt_mq_send((rt_mq_t)mq, &addr, sizeof(uintptr_t)); +} + +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout) +{ + int ret = 0; + rt_err_t result = RT_EOK; + + if (timeout == USB_OSAL_WAITING_FOREVER) { + result = rt_mq_recv((rt_mq_t)mq, addr, sizeof(uintptr_t), RT_WAITING_FOREVER); + } else { + result = rt_mq_recv((rt_mq_t)mq, addr, sizeof(uintptr_t), rt_tick_from_millisecond(timeout)); + } + if (result == -RT_ETIMEOUT) { + ret = -USB_ERR_TIMEOUT; + } else if (result == -RT_ERROR) { + ret = -USB_ERR_INVAL; + } else { + ret = 0; + } + + return (int)ret; +} + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period) +{ + struct usb_osal_timer *timer; + + timer = rt_malloc(sizeof(struct usb_osal_timer)); + memset(timer, 0, sizeof(struct usb_osal_timer)); + + timer->timer = (void *)rt_timer_create("usb_tim", handler, argument, timeout_ms, is_period ? (RT_TIMER_FLAG_PERIODIC | RT_TIMER_FLAG_SOFT_TIMER) : (RT_TIMER_FLAG_ONE_SHOT | RT_TIMER_FLAG_SOFT_TIMER)); + if (timer->timer == NULL) { + return NULL; + } + return timer; +} + +void usb_osal_timer_delete(struct usb_osal_timer *timer) +{ + rt_timer_stop(timer->timer); + rt_timer_delete(timer->timer); + rt_free(timer); +} + +void usb_osal_timer_start(struct usb_osal_timer *timer) +{ + rt_timer_start(timer->timer); +} + +void usb_osal_timer_stop(struct usb_osal_timer *timer) +{ + rt_timer_stop(timer->timer); +} + +size_t usb_osal_enter_critical_section(void) +{ + return rt_hw_interrupt_disable(); +} + +void usb_osal_leave_critical_section(size_t flag) +{ + rt_hw_interrupt_enable(flag); +} + +void usb_osal_msleep(uint32_t delay) +{ + rt_thread_mdelay(delay); +} diff --git a/components/drivers/usb/cherryusb/platform/README.md b/components/drivers/usb/cherryusb/platform/README.md new file mode 100644 index 00000000000..a6afc93ef3c --- /dev/null +++ b/components/drivers/usb/cherryusb/platform/README.md @@ -0,0 +1,14 @@ +# Platform Support + +This is a platform support for other os with their own components. + +| Platform | fs | net | serial | +|:---------:|:------------:|:------------:|:------------:| +|none | fatfs | lwip | none | +|rtthread | dfs | lwip | rt_device | +|nuttx | nuttx block driver | nuttx net | nuttx char driver| +|threadx | filex | netx | none | + +- **fs** is for usbd_msc and usbh_msc +- **net** is for cdc_ecm, cdc_rndis, cdc_ncm, asix, rtl8152 and so on. +- **serial** is for cdc_acm, ch340, ftdi, cp210x, pl2303 and so on. \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c b/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c new file mode 100644 index 00000000000..d4baf03e585 --- /dev/null +++ b/components/drivers/usb/cherryusb/platform/rtthread/usb_check.c @@ -0,0 +1,17 @@ +#include "rtthread.h" + +#ifdef PKG_CHERRYUSB_HOST + +#ifndef RT_USING_TIMER_SOFT +#error must enable RT_USING_TIMER_SOFT to support timer callback in thread +#endif + +#if IDLE_THREAD_STACK_SIZE < 2048 +#error "IDLE_THREAD_STACK_SIZE must be greater than 2048" +#endif + +#if RT_TIMER_THREAD_STACK_SIZE < 2048 +#error "RT_TIMER_THREAD_STACK_SIZE must be greater than 2048" +#endif + +#endif diff --git a/components/drivers/usb/cherryusb/platform/rtthread/usb_msh.c b/components/drivers/usb/cherryusb/platform/rtthread/usb_msh.c new file mode 100644 index 00000000000..4de11054720 --- /dev/null +++ b/components/drivers/usb/cherryusb/platform/rtthread/usb_msh.c @@ -0,0 +1,47 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "rtthread.h" + +#ifdef RT_CHERRYUSB_HOST + +#include "usbh_core.h" + +int usbh_init(int argc, char **argv) +{ + uint8_t busid; + uint32_t reg_base; + + if (argc < 3) { + USB_LOG_ERR("please input correct command: usbh_init \r\n"); + return -1; + } + + busid = atoi(argv[1]); + reg_base = strtoll(argv[2], NULL, 16); + usbh_initialize(busid, reg_base); + + return 0; +} + +int usbh_deinit(int argc, char **argv) +{ + uint8_t busid; + + if (argc < 2) { + USB_LOG_ERR("please input correct command: usbh_deinit \r\n"); + return -1; + } + + busid = atoi(argv[1]); + usbh_deinitialize(busid); + + return 0; +} + +MSH_CMD_EXPORT(usbh_init, init usb host); +MSH_CMD_EXPORT(usbh_deinit, deinit usb host); +MSH_CMD_EXPORT(lsusb, ls usb devices); +#endif diff --git a/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c b/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c new file mode 100644 index 00000000000..968064a6446 --- /dev/null +++ b/components/drivers/usb/cherryusb/platform/rtthread/usbh_dfs.c @@ -0,0 +1,241 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_msc.h" + +#include "rtthread.h" +#include + +#define DEV_FORMAT "/sd%c" + +#ifndef CONFIG_USB_DFS_MOUNT_POINT +#define CONFIG_USB_DFS_MOUNT_POINT "/" +#endif + +#if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7) || \ + defined(SOC_HPM5000) || defined(SOC_HPM6000) || defined(BSP_USING_BL61X) +#ifndef RT_USING_CACHE +#error usbh msc must enable RT_USING_CACHE in this chip +#endif +#if RT_ALIGN_SIZE != 32 && RT_ALIGN_SIZE != 64 +#error usbh msc must set cache line to 32 or 64 +#endif +#endif + +#if defined(BSP_USING_BL61X) +#include "bflb_l1c.h" + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) { + bflb_l1c_dcache_clean_range(addr, size); + } else { + bflb_l1c_dcache_invalidate_range(addr, size); + } +} +#elif defined(SOC_HPM5000) || defined(SOC_HPM6000) +#include "hpm_l1c_drv.h" + +void rt_hw_cpu_dcache_ops(int ops, void *addr, int size) +{ + if (ops == RT_HW_CACHE_FLUSH) { + l1c_dc_flush((uint32_t)addr, size); + } else { + l1c_dc_invalidate((uint32_t)addr, size); + } +} +#endif + +USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t msc_sector[512]; + +static rt_err_t rt_udisk_init(rt_device_t dev) +{ + return RT_EOK; +} + +static ssize_t rt_udisk_read(rt_device_t dev, rt_off_t pos, void *buffer, + rt_size_t size) +{ + struct usbh_msc *msc_class = (struct usbh_msc *)dev->user_data; + int ret; + +#ifdef RT_USING_CACHE + rt_uint32_t *align_buf; + + if ((uint32_t)buffer & (RT_ALIGN_SIZE - 1)) { + align_buf = rt_malloc_align(size * msc_class->blocksize, RT_ALIGN_SIZE); + if (!align_buf) { + rt_kprintf("msc get align buf failed\n"); + return 0; + } + } else { + align_buf = (rt_uint32_t *)buffer; + } + + ret = usbh_msc_scsi_read10(msc_class, pos, (uint8_t *)align_buf, size); + if (ret < 0) { + rt_kprintf("usb mass_storage read failed\n"); + return 0; + } + rt_hw_cpu_dcache_ops(RT_HW_CACHE_INVALIDATE, align_buf, size * msc_class->blocksize); + if ((uint32_t)buffer & (RT_ALIGN_SIZE - 1)) { + rt_memcpy(buffer, align_buf, size * msc_class->blocksize); + rt_free_align(align_buf); + } +#else + ret = usbh_msc_scsi_read10(msc_class, pos, buffer, size); + if (ret < 0) { + rt_kprintf("usb mass_storage read failed\n"); + return 0; + } +#endif + return size; +} + +static ssize_t rt_udisk_write(rt_device_t dev, rt_off_t pos, const void *buffer, + rt_size_t size) +{ + struct usbh_msc *msc_class = (struct usbh_msc *)dev->user_data; + int ret; + +#ifdef RT_USING_CACHE + rt_uint32_t *align_buf; + + if ((uint32_t)buffer & (RT_ALIGN_SIZE - 1)) { + align_buf = rt_malloc_align(size * msc_class->blocksize, RT_ALIGN_SIZE); + if (!align_buf) { + rt_kprintf("msc get align buf failed\n"); + return 0; + } + + rt_memcpy(align_buf, buffer, size * msc_class->blocksize); + } else { + align_buf = (rt_uint32_t *)buffer; + } + + rt_hw_cpu_dcache_ops(RT_HW_CACHE_FLUSH, align_buf, size * msc_class->blocksize); + ret = usbh_msc_scsi_write10(msc_class, pos, (uint8_t *)align_buf, size); + if (ret < 0) { + rt_kprintf("usb mass_storage write failed\n"); + return 0; + } + if ((uint32_t)buffer & (RT_ALIGN_SIZE - 1)) { + rt_free_align(align_buf); + } +#else + ret = usbh_msc_scsi_write10(msc_class, pos, buffer, size); + if (ret < 0) { + rt_kprintf("usb mass_storage write failed\n"); + return 0; + } +#endif + + return size; +} + +static rt_err_t rt_udisk_control(rt_device_t dev, int cmd, void *args) +{ + /* check parameter */ + RT_ASSERT(dev != RT_NULL); + struct usbh_msc *msc_class = (struct usbh_msc *)dev->user_data; + + if (cmd == RT_DEVICE_CTRL_BLK_GETGEOME) { + struct rt_device_blk_geometry *geometry; + + geometry = (struct rt_device_blk_geometry *)args; + if (geometry == RT_NULL) + return -RT_ERROR; + + geometry->bytes_per_sector = msc_class->blocksize; + geometry->block_size = msc_class->blocksize; + geometry->sector_count = msc_class->blocknum; + } + + return RT_EOK; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops udisk_device_ops = { + rt_udisk_init, + RT_NULL, + RT_NULL, + rt_udisk_read, + rt_udisk_write, + rt_udisk_control +}; +#endif + +int udisk_init(struct usbh_msc *msc_class) +{ + rt_err_t ret = 0; + rt_uint8_t i; + struct dfs_partition part0; + struct rt_device *dev; + char name[CONFIG_USBHOST_DEV_NAMELEN]; + char mount_point[CONFIG_USBHOST_DEV_NAMELEN]; + + dev = rt_malloc(sizeof(struct rt_device)); + memset(dev, 0, sizeof(struct rt_device)); + + snprintf(name, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, msc_class->sdchar); + snprintf(mount_point, CONFIG_USBHOST_DEV_NAMELEN, CONFIG_USB_DFS_MOUNT_POINT, msc_class->sdchar); + + ret = usbh_msc_scsi_read10(msc_class, 0, msc_sector, 1); + if (ret != RT_EOK) { + rt_kprintf("usb mass_storage read failed\n"); + return ret; + } + + for (i = 0; i < 16; i++) { + /* Get the first partition */ + ret = dfs_filesystem_get_partition(&part0, msc_sector, i); + if (ret == RT_EOK) { + rt_kprintf("Found partition %d: type = %d, offet=0x%x, size=0x%x\n", + i, part0.type, part0.offset, part0.size); + } else { + break; + } + } + + dev->type = RT_Device_Class_Block; +#ifdef RT_USING_DEVICE_OPS + dev->ops = &udisk_device_ops; +#else + dev->init = rt_udisk_init; + dev->read = rt_udisk_read; + dev->write = rt_udisk_write; + dev->control = rt_udisk_control; +#endif + dev->user_data = msc_class; + + rt_device_register(dev, name, RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_REMOVABLE | RT_DEVICE_FLAG_STANDALONE); + + ret = dfs_mount(name, mount_point, "elm", 0, 0); + if (ret == 0) { + rt_kprintf("udisk: %s mount successfully\n", name); + } else { + rt_kprintf("udisk: %s mount failed, ret = %d\n", name, ret); + } + + return ret; +} + +void usbh_msc_run(struct usbh_msc *msc_class) +{ + udisk_init(msc_class); +} + +void usbh_msc_stop(struct usbh_msc *msc_class) +{ + char name[CONFIG_USBHOST_DEV_NAMELEN]; + char mount_point[CONFIG_USBHOST_DEV_NAMELEN]; + + snprintf(name, CONFIG_USBHOST_DEV_NAMELEN, DEV_FORMAT, msc_class->sdchar); + snprintf(mount_point, CONFIG_USBHOST_DEV_NAMELEN, CONFIG_USB_DFS_MOUNT_POINT, msc_class->sdchar); + + dfs_unmount(mount_point); + rt_device_unregister(rt_device_find(name)); +} diff --git a/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c b/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c new file mode 100644 index 00000000000..2c0c7eaf93e --- /dev/null +++ b/components/drivers/usb/cherryusb/platform/rtthread/usbh_lwip.c @@ -0,0 +1,415 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "netif/etharp.h" +#include "lwip/netif.h" +#include "lwip/pbuf.h" +#include "lwip/tcpip.h" +#if LWIP_DHCP +#include "lwip/dhcp.h" +#include "lwip/prot/dhcp.h" +#endif + +#include +#include +#include + +#include "usbh_core.h" + +#include "lwip/opt.h" + +#ifndef RT_USING_LWIP212 +#error must enable RT_USING_LWIP212 +#endif + +#ifndef LWIP_NO_RX_THREAD +#error must enable LWIP_NO_RX_THREAD, we do not use rtthread eth rx thread +#endif + +#ifndef LWIP_NO_TX_THREAD +#warning suggest you to enable LWIP_NO_TX_THREAD, we do not use rtthread eth tx thread +#endif + +#if LWIP_TCPIP_CORE_LOCKING_INPUT !=1 +#warning suggest you to set LWIP_TCPIP_CORE_LOCKING_INPUT to 1, usb handles eth input with own thread +#endif + +#if LWIP_TCPIP_CORE_LOCKING !=1 +#error must set LWIP_TCPIP_CORE_LOCKING to 1 +#endif + +#if PBUF_POOL_BUFSIZE < 1600 +#error PBUF_POOL_BUFSIZE must be larger than 1600 +#endif + +// #define CONFIG_USBHOST_PLATFORM_CDC_ECM +// #define CONFIG_USBHOST_PLATFORM_CDC_RNDIS +// #define CONFIG_USBHOST_PLATFORM_CDC_NCM +// #define CONFIG_USBHOST_PLATFORM_ASIX +// #define CONFIG_USBHOST_PLATFORM_RTL8152 + +void usbh_lwip_eth_input_common(struct netif *netif, uint8_t *buf, uint32_t len) +{ +#if LWIP_TCPIP_CORE_LOCKING_INPUT + pbuf_type type = PBUF_REF; +#else + pbuf_type type = PBUF_POOL; +#endif + err_t err; + struct pbuf *p; + + p = pbuf_alloc(PBUF_RAW, len, type); + if (p != NULL) { +#if LWIP_TCPIP_CORE_LOCKING_INPUT + p->payload = buf; +#else + memcpy(p->payload, buf, len); +#endif + err = netif->input(p, netif); + if (err != ERR_OK) { + pbuf_free(p); + } + } else { + USB_LOG_ERR("No memory to alloc pbuf\r\n"); + } +} + +#ifdef CONFIG_USBHOST_PLATFORM_CDC_ECM +#include "usbh_cdc_ecm.h" + +static struct eth_device g_cdc_ecm_dev; + +static rt_err_t rt_usbh_cdc_ecm_control(rt_device_t dev, int cmd, void *args) +{ + struct usbh_cdc_ecm *cdc_ecm_class = (struct usbh_cdc_ecm *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, cdc_ecm_class->mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_usbh_cdc_ecm_eth_tx(rt_device_t dev, struct pbuf *p) +{ + int ret = usbh_cdc_ecm_eth_output(p->payload, p->tot_len); + if (ret < 0) { + return -RT_ERROR; + } else { + return RT_EOK; + } +} + +void usbh_cdc_ecm_eth_input(uint8_t *buf, uint32_t buflen) +{ + usbh_lwip_eth_input_common(g_cdc_ecm_dev.netif, buf, buflen); +} + +void usbh_cdc_ecm_run(struct usbh_cdc_ecm *cdc_ecm_class) +{ + memset(&g_cdc_ecm_dev, 0, sizeof(struct eth_device)); + + g_cdc_ecm_dev.parent.control = rt_usbh_cdc_ecm_control; + g_cdc_ecm_dev.eth_rx = NULL; + g_cdc_ecm_dev.eth_tx = rt_usbh_cdc_ecm_eth_tx; + g_cdc_ecm_dev.parent.user_data = cdc_ecm_class; + + eth_device_init(&g_cdc_ecm_dev, "u0"); + eth_device_linkchange(&g_cdc_ecm_dev, RT_TRUE); + + usb_osal_thread_create("usbh_cdc_ecm_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_ecm_rx_thread, NULL); +} + +void usbh_cdc_ecm_stop(struct usbh_cdc_ecm *cdc_ecm_class) +{ + eth_device_deinit(&g_cdc_ecm_dev); +} +#endif + +#ifdef CONFIG_USBHOST_PLATFORM_CDC_RNDIS +#include "usbh_rndis.h" + +static struct eth_device g_rndis_dev; + +static rt_timer_t keep_timer = RT_NULL; + +static void rndis_dev_keepalive_timeout(void *parameter) +{ + struct usbh_rndis *rndis_class = (struct usbh_rndis *)parameter; + usbh_rndis_keepalive(rndis_class); +} + +static void timer_init(struct usbh_rndis *rndis_class) +{ + keep_timer = rt_timer_create("keep", + rndis_dev_keepalive_timeout, + rndis_class, + 5000, + RT_TIMER_FLAG_PERIODIC | + RT_TIMER_FLAG_SOFT_TIMER); + + rt_timer_start(keep_timer); +} + +static rt_err_t rt_usbh_rndis_control(rt_device_t dev, int cmd, void *args) +{ + struct usbh_rndis *rndis_class = (struct usbh_rndis *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, rndis_class->mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_usbh_rndis_eth_tx(rt_device_t dev, struct pbuf *p) +{ + int ret = usbh_rndis_eth_output(p->payload, p->tot_len); + if (ret < 0) { + return -RT_ERROR; + } else { + return RT_EOK; + } +} + +void usbh_rndis_eth_input(uint8_t *buf, uint32_t buflen) +{ + usbh_lwip_eth_input_common(g_rndis_dev.netif, buf, buflen); +} + +void usbh_rndis_run(struct usbh_rndis *rndis_class) +{ + memset(&g_rndis_dev, 0, sizeof(struct eth_device)); + + g_rndis_dev.parent.control = rt_usbh_rndis_control; + g_rndis_dev.eth_rx = NULL; + g_rndis_dev.eth_tx = rt_usbh_rndis_eth_tx; + g_rndis_dev.parent.user_data = rndis_class; + + eth_device_init(&g_rndis_dev, "u2"); + eth_device_linkchange(&g_rndis_dev, RT_TRUE); + + usb_osal_thread_create("usbh_rndis_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_rndis_rx_thread, NULL); + //timer_init(rndis_class); +} + +void usbh_rndis_stop(struct usbh_rndis *rndis_class) +{ + eth_device_deinit(&g_rndis_dev); + // rt_timer_stop(keep_timer); + // rt_timer_delete(keep_timer); +} +#endif + +#ifdef CONFIG_USBHOST_PLATFORM_CDC_NCM +#include "usbh_cdc_ncm.h" + +static struct eth_device g_cdc_ncm_dev; + +static rt_err_t rt_usbh_cdc_ncm_control(rt_device_t dev, int cmd, void *args) +{ + struct usbh_cdc_ncm *cdc_ncm_class = (struct usbh_cdc_ncm *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, cdc_ncm_class->mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_usbh_cdc_ncm_eth_tx(rt_device_t dev, struct pbuf *p) +{ + int ret = usbh_cdc_ncm_eth_output(p->payload, p->tot_len); + if (ret < 0) { + return -RT_ERROR; + } else { + return RT_EOK; + } +} + +void usbh_cdc_ncm_eth_input(uint8_t *buf, uint32_t buflen) +{ + usbh_lwip_eth_input_common(g_cdc_ncm_dev.netif, buf, buflen); +} + +void usbh_cdc_ncm_run(struct usbh_cdc_ncm *cdc_ncm_class) +{ + memset(&g_cdc_ncm_dev, 0, sizeof(struct eth_device)); + + g_cdc_ncm_dev.parent.control = rt_usbh_cdc_ncm_control; + g_cdc_ncm_dev.eth_rx = NULL; + g_cdc_ncm_dev.eth_tx = rt_usbh_cdc_ncm_eth_tx; + g_cdc_ncm_dev.parent.user_data = cdc_ncm_class; + + eth_device_init(&g_cdc_ncm_dev, "u1"); + eth_device_linkchange(&g_cdc_ncm_dev, RT_TRUE); + + usb_osal_thread_create("usbh_cdc_ncm_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_cdc_ncm_rx_thread, NULL); +} + +void usbh_cdc_ncm_stop(struct usbh_cdc_ncm *cdc_ncm_class) +{ + eth_device_deinit(&g_cdc_ncm_dev); +} +#endif + +#ifdef CONFIG_USBHOST_PLATFORM_ASIX +#include "usbh_asix.h" + +static struct eth_device g_asix_dev; + +static rt_err_t rt_usbh_asix_control(rt_device_t dev, int cmd, void *args) +{ + struct usbh_asix *asix_class = (struct usbh_asix *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, asix_class->mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_usbh_asix_eth_tx(rt_device_t dev, struct pbuf *p) +{ + int ret = usbh_asix_eth_output(p->payload, p->tot_len); + if (ret < 0) { + return -RT_ERROR; + } else { + return RT_EOK; + } +} + +void usbh_asix_eth_input(uint8_t *buf, uint32_t buflen) +{ + usbh_lwip_eth_input_common(g_asix_dev.netif, buf, buflen); +} + +void usbh_asix_run(struct usbh_asix *asix_class) +{ + memset(&g_asix_dev, 0, sizeof(struct eth_device)); + + g_asix_dev.parent.control = rt_usbh_asix_control; + g_asix_dev.eth_rx = NULL; + g_asix_dev.eth_tx = rt_usbh_asix_eth_tx; + g_asix_dev.parent.user_data = asix_class; + + eth_device_init(&g_asix_dev, "u3"); + eth_device_linkchange(&g_asix_dev, RT_TRUE); + + usb_osal_thread_create("usbh_asix_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_asix_rx_thread, NULL); +} + +void usbh_asix_stop(struct usbh_asix *asix_class) +{ + eth_device_deinit(&g_asix_dev); +} +#endif + +#ifdef CONFIG_USBHOST_PLATFORM_RTL8152 +#include "usbh_rtl8152.h" + +static struct eth_device g_rtl8152_dev; + +static rt_err_t rt_usbh_rtl8152_control(rt_device_t dev, int cmd, void *args) +{ + struct usbh_rtl8152 *rtl8152_class = (struct usbh_rtl8152 *)dev->user_data; + + switch (cmd) { + case NIOCTL_GADDR: + + /* get mac address */ + if (args) + rt_memcpy(args, rtl8152_class->mac, 6); + else + return -RT_ERROR; + + break; + + default: + break; + } + + return RT_EOK; +} + +static rt_err_t rt_usbh_rtl8152_eth_tx(rt_device_t dev, struct pbuf *p) +{ + int ret = usbh_rtl8152_eth_output(p->payload, p->tot_len); + if (ret < 0) { + return -RT_ERROR; + } else { + return RT_EOK; + } +} + +void usbh_rtl8152_eth_input(uint8_t *buf, uint32_t buflen) +{ + usbh_lwip_eth_input_common(g_rtl8152_dev.netif, buf, buflen); +} + +void usbh_rtl8152_run(struct usbh_rtl8152 *rtl8152_class) +{ + memset(&g_rtl8152_dev, 0, sizeof(struct eth_device)); + + g_rtl8152_dev.parent.control = rt_usbh_rtl8152_control; + g_rtl8152_dev.eth_rx = NULL; + g_rtl8152_dev.eth_tx = rt_usbh_rtl8152_eth_tx; + g_rtl8152_dev.parent.user_data = rtl8152_class; + + eth_device_init(&g_rtl8152_dev, "u4"); + eth_device_linkchange(&g_rtl8152_dev, RT_TRUE); + + usb_osal_thread_create("usbh_rtl8152_rx", 2048, CONFIG_USBHOST_PSC_PRIO + 1, usbh_rtl8152_rx_thread, NULL); +} + +void usbh_rtl8152_stop(struct usbh_rtl8152 *rtl8152_class) +{ + eth_device_deinit(&g_rtl8152_dev); +} +#endif diff --git a/components/drivers/usb/cherryusb/port/bouffalolab/README.md b/components/drivers/usb/cherryusb/port/bouffalolab/README.md new file mode 100644 index 00000000000..7779b2bbd26 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/bouffalolab/README.md @@ -0,0 +1,5 @@ +# Note + +## Support Chip List + +- BL616/BL808 diff --git a/components/drivers/usb/cherryusb/port/bouffalolab/usb_dc_bl.c b/components/drivers/usb/cherryusb/port/bouffalolab/usb_dc_bl.c new file mode 100644 index 00000000000..6f45329c96c --- /dev/null +++ b/components/drivers/usb/cherryusb/port/bouffalolab/usb_dc_bl.c @@ -0,0 +1,1108 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "bflb_core.h" +#include "usbd_core.h" +#include "hardware/usb_v2_reg.h" + +/* select only one mode */ +// #define CONFIG_USB_PINGPONG_ENABLE +// #define CONFIG_USB_TRIPLE_ENABLE + +#define BFLB_USB_BASE ((uint32_t)0x20072000) +#define BFLB_PDS_BASE ((uint32_t)0x2000e000) + +#define PDS_USB_CTL_OFFSET (0x500) /* usb_ctl */ +#define PDS_USB_PHY_CTRL_OFFSET (0x504) /* usb_phy_ctrl */ + +/* 0x500 : usb_ctl */ +#define PDS_REG_USB_SW_RST_N (1 << 0U) +#define PDS_REG_USB_EXT_SUSP_N (1 << 1U) +#define PDS_REG_USB_WAKEUP (1 << 2U) +#define PDS_REG_USB_L1_WAKEUP (1 << 3U) +#define PDS_REG_USB_DRVBUS_POL (1 << 4U) +#define PDS_REG_USB_IDDIG (1 << 5U) + +/* 0x504 : usb_phy_ctrl */ +#define PDS_REG_USB_PHY_PONRST (1 << 0U) +#define PDS_REG_USB_PHY_OSCOUTEN (1 << 1U) +#define PDS_REG_USB_PHY_XTLSEL_SHIFT (2U) +#define PDS_REG_USB_PHY_XTLSEL_MASK (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT) +#define PDS_REG_USB_PHY_OUTCLKSEL (1 << 4U) +#define PDS_REG_USB_PHY_PLLALIV (1 << 5U) +#define PDS_REG_PU_USB20_PSW (1 << 6U) + +#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C) +#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710) + +extern void USBD_IRQHandler(uint8_t busid); + +void USBD_IRQ(int irq, void *arg) +{ + USBD_IRQHandler(0); +} + +static void bflb_usb_phy_init(void) +{ + uint32_t regval; + + /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */ + /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */ + /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */ + /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */ + /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */ + /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */ + /* #1.2ms; wait UCLK */ + /* wait(soc616_b0.usb_uclk); */ + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval |= PDS_REG_PU_USB20_PSW; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval |= PDS_REG_USB_PHY_PONRST; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + /* greater than 5T */ + bflb_mtimer_delay_us(1); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval &= ~PDS_REG_USB_SW_RST_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + /* greater than 5T */ + bflb_mtimer_delay_us(1); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval |= PDS_REG_USB_EXT_SUSP_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + /* wait UCLK 1.2ms */ + bflb_mtimer_delay_ms(3); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval |= PDS_REG_USB_SW_RST_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + bflb_mtimer_delay_ms(2); +} + +#define USB_FIFO_F0 0 +#define USB_FIFO_F1 1 +#define USB_FIFO_F2 2 +#define USB_FIFO_F3 3 +#define USB_FIFO_CXF 0xff + +#define USB_FIFO_DIR_OUT 0 +#define USB_FIFO_DIR_IN 1 +#define USB_FIFO_DIR_BID 2 + +#define USB_VDMA_DIR_FIFO2MEM 0 +#define USB_VDMA_DIR_MEM2FIFO 1 + +#define USB_NUM_BIDIR_ENDPOINTS 5 + +/* Endpoint state */ +struct bl_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + bool ep_active; + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +struct bl_udc { + struct bl_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters */ + struct bl_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ +} g_bl_udc; + +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_setup_buffer[8]; + +static void bflb_usb_reset_fifo(uint8_t fifo) +{ + uint32_t regval; + + if (fifo == USB_FIFO_CXF) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + regval |= USB_CX_CLR; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + } else { + regval = getreg32(BFLB_USB_BASE + USB_DEV_FIBC0_OFFSET + 4 * fifo); + regval |= USB_FFRST0_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_FIBC0_OFFSET + 4 * fifo); + } +} + +void bflb_usb_get_setup_packet(uint32_t setup[2]) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DMA_TFN_OFFSET); + regval |= USB_ACC_CXF_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DMA_TFN_OFFSET); + + setup[0] = getreg32(BFLB_USB_BASE + USB_DMA_CPS3_OFFSET); + setup[1] = getreg32(BFLB_USB_BASE + USB_DMA_CPS3_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_DMA_TFN_OFFSET); + regval &= ~USB_ACC_CXF_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DMA_TFN_OFFSET); +} + +static void bflb_usb_set_ep_fifomap(uint8_t ep_idx, uint8_t fifo) +{ + uint32_t regval; + + if (ep_idx < 5) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_EPMAP0_OFFSET); + regval &= ~(0xff << ((ep_idx - 1) * 8)); + regval |= (fifo << ((ep_idx - 1) * 8)); + regval |= (fifo << ((ep_idx - 1) * 8 + 4)); + putreg32(regval, BFLB_USB_BASE + USB_DEV_EPMAP0_OFFSET); + } else { + regval = getreg32(BFLB_USB_BASE + USB_DEV_EPMAP1_OFFSET); + regval &= ~(0xff << ((ep_idx - 4 - 1) * 8)); + regval |= (fifo << ((ep_idx - 4 - 1) * 8)); + regval |= (fifo << ((ep_idx - 4 - 1) * 8 + 4)); + putreg32(regval, BFLB_USB_BASE + USB_DEV_EPMAP1_OFFSET); + } +} + +static void bflb_usb_set_fifo_epmap(uint8_t fifo, uint8_t ep_idx, uint8_t dir) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_FMAP_OFFSET); + regval &= ~(0x3f << (fifo * 8)); + regval |= (ep_idx << (fifo * 8)); + regval |= (dir << (fifo * 8 + 4)); + putreg32(regval, BFLB_USB_BASE + USB_DEV_FMAP_OFFSET); +} + +static void bflb_usb_set_outep_mps(uint8_t ep_idx, uint16_t ep_mps) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + regval &= ~USB_MAXPS_OEP1_MASK; + regval |= ep_mps; + putreg32(regval, BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); +} + +static void bflb_usb_set_inep_mps(uint8_t ep_idx, uint16_t ep_mps) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + regval &= ~USB_MAXPS_IEP1_MASK; + regval |= ep_mps; + putreg32(regval, BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); +} + +static uint8_t bflb_usb_get_fifo_ep(uint8_t fifo) +{ + uint32_t regval; + + regval = (getreg32(BFLB_USB_BASE + USB_DEV_FMAP_OFFSET) & (0xf << (fifo * 8))); + regval >>= (fifo * 8); + return regval; +} + +static void bflb_usb_fifo_config(uint8_t fifo, uint8_t ep_type, uint16_t block_size, uint8_t block_num, bool fifo_en) +{ + uint32_t regval; + + if (fifo < 4) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_FCFG_OFFSET); + regval &= ~(0x3f << (fifo * 8)); + regval |= (ep_type << (fifo * 8 + 0)); + regval |= ((block_num - 1) << (fifo * 8 + 2)); + if (block_size == 1024) { + regval |= (1 << (fifo * 8 + 4)); + } + + if (fifo_en) { + regval |= (1 << (fifo * 8 + 5)); + } + putreg32(regval, BFLB_USB_BASE + USB_DEV_FCFG_OFFSET); + } +} + +static void bflb_usb_vdma_start_write(uint8_t fifo, const uint8_t *data, uint32_t len) +{ + uint32_t regval; + + if (fifo == USB_FIFO_CXF) { + regval = getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + regval &= ~USB_VDMA_LEN_CXF_MASK; + regval &= ~USB_VDMA_IO_CXF; + regval |= USB_VDMA_TYPE_CXF; + regval |= (len << USB_VDMA_LEN_CXF_SHIFT); + putreg32(regval, BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + + putreg32((uint32_t)data, BFLB_USB_BASE + USB_VDMA_CXFPS2_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + regval |= USB_VDMA_START_CXF; + putreg32(regval, BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + } else { + regval = getreg32(BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + regval &= ~USB_VDMA_LEN_CXF_MASK; + regval &= ~USB_VDMA_IO_CXF; + regval |= USB_VDMA_TYPE_CXF; + regval |= (len << USB_VDMA_LEN_CXF_SHIFT); + putreg32(regval, BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + + putreg32((uint32_t)data, BFLB_USB_BASE + USB_VDMA_F0PS2_OFFSET + fifo * 8); + + regval = getreg32(BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + regval |= USB_VDMA_START_CXF; + putreg32(regval, BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + } +} + +static void bflb_usb_vdma_start_read(uint8_t fifo, uint8_t *data, uint32_t len) +{ + uint32_t regval; + + if (fifo == USB_FIFO_CXF) { + regval = getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + regval &= ~USB_VDMA_LEN_CXF_MASK; + regval &= ~USB_VDMA_IO_CXF; + regval &= ~USB_VDMA_TYPE_CXF; + regval |= (len << USB_VDMA_LEN_CXF_SHIFT); + putreg32(regval, BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + + putreg32((uint32_t)data, BFLB_USB_BASE + USB_VDMA_CXFPS2_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + regval |= USB_VDMA_START_CXF; + putreg32(regval, BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET); + } else { + regval = getreg32(BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + regval &= ~USB_VDMA_LEN_CXF_MASK; + regval &= ~USB_VDMA_IO_CXF; + regval &= ~USB_VDMA_TYPE_CXF; + regval |= (len << USB_VDMA_LEN_CXF_SHIFT); + putreg32(regval, BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + + putreg32((uint32_t)data, BFLB_USB_BASE + USB_VDMA_F0PS2_OFFSET + fifo * 8); + + regval = getreg32(BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + regval |= USB_VDMA_START_CXF; + putreg32(regval, BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8); + } +} + +static uint32_t bflb_usb_vdma_get_remain_size(uint8_t fifo) +{ + uint32_t regval; + + if (fifo == USB_FIFO_CXF) { + regval = (getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET) & USB_VDMA_LEN_CXF_MASK); + regval >>= USB_VDMA_LEN_CXF_SHIFT; + + } else { + regval = (getreg32(BFLB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8) & USB_VDMA_LEN_CXF_MASK); + regval >>= USB_VDMA_LEN_CXF_SHIFT; + } + + return regval; +} + +static inline void bflb_usb_control_transfer_done(void) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + regval |= USB_CX_DONE; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); +} + +static inline void bflb_usb_set_mult(uint8_t ep_idx, uint8_t mult) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + regval &= ~USB_TX_NUM_HBW_IEP1_MASK; + regval |= (mult << USB_TX_NUM_HBW_IEP1_SHIFT); + putreg32(regval, BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); +} + +static inline void bflb_usb_send_zlp(uint8_t ep_idx) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + regval |= USB_TX0BYTE_IEP1; + putreg32(regval, BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); +} + +static inline uint32_t bflb_usb_get_tx_zlp_intstatus(void) +{ + return getreg32(BFLB_USB_BASE + USB_DEV_TXZ_OFFSET); +} + +static inline uint32_t bflb_usb_get_rx_zlp_intstatus(void) +{ + return getreg32(BFLB_USB_BASE + USB_DEV_RXZ_OFFSET); +} + +static inline void bflb_usb_clear_tx_zlp_intstatus(uint8_t ep_idx) +{ + putreg32((1 << (ep_idx - 1)), BFLB_USB_BASE + USB_DEV_TXZ_OFFSET); +} + +static inline void bflb_usb_clear_rx_zlp_intstatus(uint8_t ep_idx) +{ + putreg32((1 << (ep_idx - 1)), BFLB_USB_BASE + USB_DEV_RXZ_OFFSET); +} + +static uint32_t bflb_usb_get_source_group_intstatus(uint8_t group) +{ + switch (group) { + case 0: + return (getreg32(BFLB_USB_BASE + USB_DEV_ISG0_OFFSET) & ~getreg32(BFLB_USB_BASE + USB_DEV_MISG0_OFFSET)); + case 1: + return (getreg32(BFLB_USB_BASE + USB_DEV_ISG1_OFFSET) & ~getreg32(BFLB_USB_BASE + USB_DEV_MISG1_OFFSET)); + case 2: + return (getreg32(BFLB_USB_BASE + USB_DEV_ISG2_OFFSET) & ~getreg32(BFLB_USB_BASE + USB_DEV_MISG2_OFFSET)); + case 3: + return (getreg32(BFLB_USB_BASE + USB_DEV_ISG3_OFFSET) & ~getreg32(BFLB_USB_BASE + USB_DEV_MISG3_OFFSET)); + case 4: + return (getreg32(BFLB_USB_BASE + USB_DEV_ISG4_OFFSET) & ~getreg32(BFLB_USB_BASE + USB_DEV_MISG4_OFFSET)); + default: + break; + } + return 0; +} + +static void bflb_usb_source_group_int_clear(uint8_t group, uint32_t int_clear) +{ + switch (group) { + case 0: + putreg32(int_clear, BFLB_USB_BASE + USB_DEV_ISG0_OFFSET); + break; + case 1: + putreg32(int_clear, BFLB_USB_BASE + USB_DEV_ISG1_OFFSET); + break; + case 2: + putreg32(int_clear, BFLB_USB_BASE + USB_DEV_ISG2_OFFSET); + break; + case 3: + putreg32(int_clear, BFLB_USB_BASE + USB_DEV_ISG3_OFFSET); + break; + case 4: + putreg32(int_clear, BFLB_USB_BASE + USB_DEV_ISG4_OFFSET); + break; + + default: + break; + } +} + +static uint8_t usb_get_transfer_fifo(uint8_t ep_idx) +{ + uint8_t target_fifo_id; + + if ((g_bl_udc.out_ep[ep_idx].ep_mps > 512) || (g_bl_udc.in_ep[ep_idx].ep_mps > 512)) { +#if defined(CONFIG_USB_PINGPONG_ENABLE) + target_fifo_id = USB_FIFO_F0; +#elif defined(CONFIG_USB_TRIPLE_ENABLE) + while (1) { + } +#else + if (ep_idx == 1) { + target_fifo_id = USB_FIFO_F0; + } else { + target_fifo_id = USB_FIFO_F2; + } +#endif + } else { +#if defined(CONFIG_USB_PINGPONG_ENABLE) + if (ep_idx == 1) { + target_fifo_id = USB_FIFO_F0; + } else { + target_fifo_id = USB_FIFO_F2; + } +#elif defined(CONFIG_USB_TRIPLE_ENABLE) + if (ep_idx == 1) { + target_fifo_id = USB_FIFO_F0; + } else { + target_fifo_id = USB_FIFO_F3; + } +#else + target_fifo_id = (ep_idx - 1); +#endif + } + + return target_fifo_id; +} + +int usb_dc_init(uint8_t busid) +{ + uint32_t regval; + + bflb_usb_phy_init(); + + bflb_irq_attach(37, USBD_IRQ, NULL); + bflb_irq_enable(37); + + /* disable global irq */ + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval &= ~USB_GLINT_EN_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_UNPLUG; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval &= ~USB_CAP_RMWAKUP; + regval |= USB_CHIP_EN_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval |= USB_SFRST_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + while (getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET) & USB_SFRST_HOV) { + } + + regval = getreg32(BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + regval &= ~USB_AFT_CONF; + putreg32(regval, BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_SMT_OFFSET); + regval &= ~USB_SOFMT_MASK; +#ifdef CONFIG_USB_HS + regval |= USB_SOF_TIMER_MASK_AFTER_RESET_HS; +#else + regval |= USB_SOF_TIMER_MASK_AFTER_RESET_FS; +#endif + putreg32(regval, BFLB_USB_BASE + USB_DEV_SMT_OFFSET); + + /* enable setup irq in source group0 */ + regval = getreg32(BFLB_USB_BASE + USB_DEV_MISG0_OFFSET); + regval &= ~USB_MCX_SETUP_INT; + regval |= USB_MCX_IN_INT; + regval |= (1 << 3); + regval |= USB_MCX_OUT_INT; + regval |= USB_MCX_IN_INT; + regval |= USB_MCX_COMFAIL_INT; + regval |= USB_MCX_COMABORT_INT; + putreg32(regval, BFLB_USB_BASE + USB_DEV_MISG0_OFFSET); + + /* disable all fifo irq in source group1 */ + putreg32(0xffffffff, BFLB_USB_BASE + USB_DEV_MISG1_OFFSET); + + /* enable rst/tx0/rx0 irq in source group2 */ + regval = 0xffffffff; + regval &= ~USB_MUSBRST_INT; + regval &= ~USB_MSUSP_INT; + regval &= ~USB_MRESM_INT; + regval &= ~USB_MTX0BYTE_INT; + regval &= ~USB_MRX0BYTE_INT; + putreg32(regval, BFLB_USB_BASE + USB_DEV_MISG2_OFFSET); + + /* enable vdma cmplt and error irq in source group3 */ + regval = 0xffffffff; + regval &= ~(USB_MVDMA_CMPLT_CXF | + USB_MVDMA_CMPLT_F0 | + USB_MVDMA_CMPLT_F1 | + USB_MVDMA_CMPLT_F2 | + USB_MVDMA_CMPLT_F3); + // regval &= ~(USB_MVDMA_ERROR_CXF | + // USB_MVDMA_ERROR_F0 | + // USB_MVDMA_ERROR_F1 | + // USB_MVDMA_ERROR_F2 | + // USB_MVDMA_ERROR_F3); + putreg32(regval, BFLB_USB_BASE + USB_DEV_MISG3_OFFSET); + + /* enable group irq */ + regval = getreg32(BFLB_USB_BASE + USB_DEV_MIGR_OFFSET); + regval &= ~USB_MINT_G0; + regval &= ~USB_MINT_G1; + regval &= ~USB_MINT_G2; + regval &= ~USB_MINT_G3; + regval &= ~USB_MINT_G4; + putreg32(regval, BFLB_USB_BASE + USB_DEV_MIGR_OFFSET); + + /* enable device irq */ + regval = getreg32(BFLB_USB_BASE + USB_GLB_INT_OFFSET); + regval |= USB_MHC_INT; + regval |= USB_MOTG_INT; + regval &= ~USB_MDEV_INT; + putreg32(regval, BFLB_USB_BASE + USB_GLB_INT_OFFSET); + + bflb_usb_source_group_int_clear(2, 0x3ff); + bflb_usb_source_group_int_clear(3, 0xffffffff); + + for (uint8_t i = 1; i < 9; i++) { + bflb_usb_set_ep_fifomap(i, 15); + bflb_usb_set_fifo_epmap(i, 15, 0); + } + + /* enable vdma */ + regval = getreg32(BFLB_USB_BASE + USB_VDMA_CTRL_OFFSET); + regval |= USB_VDMA_EN; + putreg32(regval, BFLB_USB_BASE + USB_VDMA_CTRL_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval &= ~USB_UNPLUG; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + /* enable global irq */ + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval |= USB_GLINT_EN_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + uint32_t regval; + + /* disable global irq */ + regval = getreg32(BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + regval &= ~USB_GLINT_EN_HOV; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CTL_OFFSET); + + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_UNPLUG; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval &= ~PDS_REG_PU_USB20_PSW; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval &= ~PDS_REG_USB_PHY_PONRST; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval &= ~PDS_REG_USB_EXT_SUSP_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + uint32_t regval; + + regval = getreg32(BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + regval &= ~USB_DEVADR_MASK; + regval |= addr; + putreg32(regval, BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + uint8_t speed = 3; + + speed = (getreg32(BFLB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT; + + if (speed == 0) { + return USB_SPEED_FULL; + } else if (speed == 1) { + return USB_SPEED_LOW; + } else if (speed == 2) { + return USB_SPEED_HIGH; + } + return USB_SPEED_HIGH; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_addr; + uint32_t regval; + + ep_addr = ep->bEndpointAddress; + + uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); + + if ((ep_idx > 4) && (ep_idx < 9)) { + return 0; + } + + if (USB_EP_DIR_IS_OUT(ep_addr)) { + g_bl_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_bl_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_bl_udc.out_ep[ep_idx].ep_enable = 1U; + bflb_usb_set_outep_mps(ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + } else { + g_bl_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_bl_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_bl_udc.in_ep[ep_idx].ep_enable = 1U; + bflb_usb_set_inep_mps(ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + bflb_usb_set_mult(ep_idx, 0); + } + + if (ep_idx != 0) { +#if !defined(CONFIG_USB_PINGPONG_ENABLE) && !defined(CONFIG_USB_TRIPLE_ENABLE) + if (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) > 512) { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + bflb_usb_set_ep_fifomap(2, USB_FIFO_F2); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 2, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 2, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 1, true); + bflb_usb_fifo_config(USB_FIFO_F1, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 1, false); + } else if (ep_idx == 2) { + bflb_usb_fifo_config(USB_FIFO_F2, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 1, true); + bflb_usb_fifo_config(USB_FIFO_F3, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 1, false); + } else { + return -1; + } + } else { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + bflb_usb_set_ep_fifomap(2, USB_FIFO_F1); + bflb_usb_set_ep_fifomap(3, USB_FIFO_F2); + bflb_usb_set_ep_fifomap(4, USB_FIFO_F3); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 2, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 3, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 4, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 1, true); + } else if (ep_idx == 2) { + bflb_usb_fifo_config(USB_FIFO_F1, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 1, true); + } else if (ep_idx == 3) { + bflb_usb_fifo_config(USB_FIFO_F2, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 1, true); + } else if (ep_idx == 4) { + bflb_usb_fifo_config(USB_FIFO_F3, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 1, true); + } else { + return -1; + } + } +#elif defined(CONFIG_USB_PINGPONG_ENABLE) + if (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) > 512) { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 1, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 2, true); + bflb_usb_fifo_config(USB_FIFO_F1, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 2, false); + bflb_usb_fifo_config(USB_FIFO_F2, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 2, false); + bflb_usb_fifo_config(USB_FIFO_F3, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 1024, 2, false); + } else { + return -1; + } + } else { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + bflb_usb_set_ep_fifomap(2, USB_FIFO_F2); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 2, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 2, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 2, true); + bflb_usb_fifo_config(USB_FIFO_F1, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 2, false); + } else if (ep_idx == 2) { + bflb_usb_fifo_config(USB_FIFO_F2, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 2, true); + bflb_usb_fifo_config(USB_FIFO_F3, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 2, false); + } else { + return -1; + } + } +#elif defined(CONFIG_USB_TRIPLE_ENABLE) + if (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) > 512) { + return -1; + } else { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + bflb_usb_set_ep_fifomap(2, USB_FIFO_F3); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 2, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 3, true); + bflb_usb_fifo_config(USB_FIFO_F1, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 3, false); + bflb_usb_fifo_config(USB_FIFO_F2, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 3, false); + } else if (ep_idx == 2) { + bflb_usb_fifo_config(USB_FIFO_F3, USB_GET_ENDPOINT_TYPE(ep->bmAttributes), 512, 1, true); + } else { + return -1; + } + } +#endif + regval = getreg32(BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + regval |= USB_AFT_CONF; + putreg32(regval, BFLB_USB_BASE + USB_DEV_ADR_OFFSET); + } + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint32_t regval; + + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (ep_idx == 0) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + regval |= USB_CX_STL; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + } else { + if (USB_EP_DIR_IS_OUT(ep)) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + regval |= USB_STL_OEP1; + //regval |= USB_RSTG_OEP1; + putreg32(regval, BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + } else { + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + regval |= USB_STL_IEP1; + //regval |= USB_RSTG_IEP1; + putreg32(regval, BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + } + } + + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint32_t regval; + + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (ep_idx == 0) { + } else { + if (USB_EP_DIR_IS_OUT(ep)) { + regval = getreg32(BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + //regval &= ~USB_RSTG_OEP1; + regval &= ~USB_STL_OEP1; + putreg32(regval, BFLB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4); + } else { + regval = getreg32(BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + //regval &= ~USB_RSTG_IEP1; + regval &= ~USB_STL_IEP1; + putreg32(regval, BFLB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4); + } + } + + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + + if (!g_bl_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + g_bl_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_bl_udc.in_ep[ep_idx].xfer_len = data_len; + g_bl_udc.in_ep[ep_idx].actual_xfer_len = 0; + g_bl_udc.in_ep[ep_idx].ep_active = true; + + if (ep_idx == 0) { + if (data_len == 0) { + g_bl_udc.in_ep[ep_idx].ep_active = false; + bflb_usb_control_transfer_done(); + } else { + data_len = MIN(data_len, g_bl_udc.in_ep[ep_idx].ep_mps); + g_bl_udc.in_ep[ep_idx].xfer_len = data_len; + bflb_usb_vdma_start_write(USB_FIFO_CXF, data, data_len); + } + } else { + if (data_len == 0) { + bflb_usb_send_zlp(ep_idx); + } else { + bflb_usb_vdma_start_write(usb_get_transfer_fifo(ep_idx), data, data_len); + } + } + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + + if (!g_bl_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + + if (data_len == 0) { + return 0; + } + + g_bl_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_bl_udc.out_ep[ep_idx].xfer_len = data_len; + g_bl_udc.out_ep[ep_idx].actual_xfer_len = 0; + g_bl_udc.out_ep[ep_idx].ep_active = true; + + if (ep_idx == 0) { + data_len = MIN(data_len, g_bl_udc.out_ep[ep_idx].ep_mps); + g_bl_udc.out_ep[ep_idx].xfer_len = data_len; + bflb_usb_vdma_start_read(USB_FIFO_CXF, data, data_len); + } else { + bflb_usb_vdma_start_read(usb_get_transfer_fifo(ep_idx), data, data_len); + } + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t glb_intstatus; + uint32_t dev_intstatus; + uint32_t subgroup_intstatus; + uint32_t regval; + uint8_t ep_idx; + + glb_intstatus = getreg32(BFLB_USB_BASE + USB_GLB_ISR_OFFSET); + + if (glb_intstatus & USB_DEV_INT) { + dev_intstatus = getreg32(BFLB_USB_BASE + USB_DEV_IGR_OFFSET); + if (dev_intstatus & USB_INT_G0) { + subgroup_intstatus = bflb_usb_get_source_group_intstatus(0); + + if (subgroup_intstatus & USB_CX_SETUP_INT) { + bflb_usb_vdma_start_read(USB_FIFO_CXF, g_setup_buffer, 8); + while (getreg32(BFLB_USB_BASE + USB_VDMA_CXFPS1_OFFSET) & USB_VDMA_START_CXF) { + } + + bflb_usb_source_group_int_clear(3, USB_VDMA_CMPLT_CXF); + + usbd_event_ep0_setup_complete_handler(0, g_setup_buffer); + } + } + if (dev_intstatus & USB_INT_G1) { + } + if (dev_intstatus & USB_INT_G2) { + subgroup_intstatus = bflb_usb_get_source_group_intstatus(2); + + if (subgroup_intstatus & USB_SUSP_INT) { + bflb_usb_source_group_int_clear(2, USB_SUSP_INT); + + bflb_usb_reset_fifo(USB_FIFO_F0); + bflb_usb_reset_fifo(USB_FIFO_F1); + bflb_usb_reset_fifo(USB_FIFO_F2); + bflb_usb_reset_fifo(USB_FIFO_F3); + bflb_usb_reset_fifo(USB_FIFO_CXF); + + usbd_event_suspend_handler(0); + } + if (subgroup_intstatus & USB_RESM_INT) { + bflb_usb_source_group_int_clear(2, USB_RESM_INT); + usbd_event_resume_handler(0); + } + if (subgroup_intstatus & USB_TX0BYTE_INT) { + for (uint8_t i = 1; i < 5; i++) { + if (bflb_usb_get_tx_zlp_intstatus() & (1 << (i - 1))) { + bflb_usb_clear_tx_zlp_intstatus(i); + usbd_event_ep_in_complete_handler(0, i | 0x80, 0); + } + } + bflb_usb_source_group_int_clear(2, USB_TX0BYTE_INT); + } + if (subgroup_intstatus & USB_RX0BYTE_INT) { + for (uint8_t i = 1; i < 5; i++) { + if (bflb_usb_get_rx_zlp_intstatus() & (1 << (i - 1))) { + bflb_usb_clear_rx_zlp_intstatus(i); + usbd_event_ep_out_complete_handler(0, i, 0); + } + } + + bflb_usb_source_group_int_clear(2, USB_RX0BYTE_INT); + } + if (subgroup_intstatus & USBRST_INT) { + bflb_usb_source_group_int_clear(2, USBRST_INT); + + bflb_usb_reset_fifo(USB_FIFO_F0); + bflb_usb_reset_fifo(USB_FIFO_F1); + bflb_usb_reset_fifo(USB_FIFO_F2); + bflb_usb_reset_fifo(USB_FIFO_F3); + bflb_usb_reset_fifo(USB_FIFO_CXF); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_SMT_OFFSET); + regval &= ~USB_SOFMT_MASK; +#ifdef CONFIG_USB_HS + regval |= USB_SOF_TIMER_MASK_AFTER_RESET_HS; +#else + regval |= USB_SOF_TIMER_MASK_AFTER_RESET_FS; +#endif + putreg32(regval, BFLB_USB_BASE + USB_DEV_SMT_OFFSET); + + memset(&g_bl_udc, 0, sizeof(g_bl_udc)); + + usbd_event_reset_handler(0); + } + } + if (dev_intstatus & USB_INT_G3) { + subgroup_intstatus = bflb_usb_get_source_group_intstatus(3); + bflb_usb_source_group_int_clear(3, subgroup_intstatus); + if (subgroup_intstatus & USB_VDMA_CMPLT_CXF) { + if (g_bl_udc.in_ep[0].ep_active) { + g_bl_udc.in_ep[0].ep_active = false; + g_bl_udc.in_ep[0].actual_xfer_len = g_bl_udc.in_ep[0].xfer_len - bflb_usb_vdma_get_remain_size(USB_FIFO_CXF); + if (g_bl_udc.in_ep[0].actual_xfer_len < g_bl_udc.in_ep[0].ep_mps) { + bflb_usb_control_transfer_done(); + } + usbd_event_ep_in_complete_handler(0, 0x80, g_bl_udc.in_ep[0].actual_xfer_len); + } else { + g_bl_udc.out_ep[0].ep_active = false; + g_bl_udc.out_ep[0].actual_xfer_len = g_bl_udc.out_ep[0].xfer_len - bflb_usb_vdma_get_remain_size(USB_FIFO_CXF); + usbd_event_ep_out_complete_handler(0, 0x00, g_bl_udc.out_ep[0].actual_xfer_len); + } + } + + for (uint8_t i = 0; i < 4; i++) { + if (subgroup_intstatus & (1 << (i + 1))) { + ep_idx = bflb_usb_get_fifo_ep(i); + if (g_bl_udc.in_ep[ep_idx].ep_active) { + g_bl_udc.in_ep[ep_idx].ep_active = 0; + g_bl_udc.in_ep[ep_idx].actual_xfer_len = g_bl_udc.in_ep[ep_idx].xfer_len - bflb_usb_vdma_get_remain_size(i); + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_bl_udc.in_ep[ep_idx].actual_xfer_len); + } else if (g_bl_udc.out_ep[ep_idx].ep_active) { + g_bl_udc.out_ep[ep_idx].ep_active = 0; + g_bl_udc.out_ep[ep_idx].actual_xfer_len = g_bl_udc.out_ep[ep_idx].xfer_len - bflb_usb_vdma_get_remain_size(i); + usbd_event_ep_out_complete_handler(0, ep_idx & 0x7f, g_bl_udc.out_ep[ep_idx].actual_xfer_len); + } + } + } + } + if (dev_intstatus & USB_INT_G4) { + } + } +} + +#ifdef CONFIG_USBDEV_TEST_MODE +void usbd_execute_test_mode(struct usb_setup_packet *setup) +{ + uint32_t regval; + uint8_t index = setup->wIndex >> 8; + + switch (index) { + case 1: // Test_J + { + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_TST_JSTA; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + bflb_usb_control_transfer_done(); + } break; + case 2: // Test_K + { + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_TST_KSTA; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + bflb_usb_control_transfer_done(); + } break; + case 3: // TEST_SE0_NAK + { + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_TST_SE0NAK; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + bflb_usb_control_transfer_done(); + } break; + case 4: // Test_Packet + { + bflb_usb_control_transfer_done(); + regval = getreg32(BFLB_USB_BASE + USB_PHY_TST_OFFSET); + regval |= USB_TST_PKT; + putreg32(regval, BFLB_USB_BASE + USB_PHY_TST_OFFSET); + + __attribute__((aligned(32))) uint8_t temp[53]; + uint8_t *pp; + uint8_t i; + pp = temp; + + for (i = 0; i < 9; i++) /*JKJKJKJK x 9*/ + *pp++ = 0x00; + + for (i = 0; i < 8; i++) /* 8*AA */ + *pp++ = 0xAA; + + for (i = 0; i < 8; i++) /* 8*EE */ + *pp++ = 0xEE; + + *pp++ = 0xFE; + + for (i = 0; i < 11; i++) /* 11*FF */ + *pp++ = 0xFF; + + *pp++ = 0x7F; + *pp++ = 0xBF; + *pp++ = 0xDF; + *pp++ = 0xEF; + *pp++ = 0xF7; + *pp++ = 0xFB; + *pp++ = 0xFD; + *pp++ = 0xFC; + *pp++ = 0x7E; + *pp++ = 0xBF; + *pp++ = 0xDF; + *pp++ = 0xEF; + *pp++ = 0xF7; + *pp++ = 0xFB; + *pp++ = 0xFD; + *pp++ = 0x7E; + + bflb_usb_vdma_start_write(USB_FIFO_CXF, temp, 53); + + regval = getreg32(BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + regval |= USB_TST_PKDONE; + putreg32(regval, BFLB_USB_BASE + USB_DEV_CXCFE_OFFSET); + + } break; + case 5: // Test_Force_Enable + break; + + default: + break; + } +} +#endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/ch32/README.md b/components/drivers/usb/cherryusb/port/ch32/README.md new file mode 100644 index 00000000000..a625d04c3b7 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ch32/README.md @@ -0,0 +1,5 @@ +# Note + +## Support Chip List + +- CH32V30x diff --git a/components/drivers/usb/cherryusb/port/ch32/usb_ch32_usbfs_reg.h b/components/drivers/usb/cherryusb/port/ch32/usb_ch32_usbfs_reg.h new file mode 100644 index 00000000000..34a960725fa --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ch32/usb_ch32_usbfs_reg.h @@ -0,0 +1,409 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _USB_CH32_USBFS_REG_H +#define _USB_CH32_USBFS_REG_H + +#define __IO volatile /* defines 'read / write' permissions */ + +/* USBOTG_FS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; + __IO uint8_t UDEV_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t UEP4_1_MOD; + __IO uint8_t UEP2_3_MOD; + __IO uint8_t UEP5_6_MOD; + __IO uint8_t UEP7_MOD; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_DMA; + __IO uint32_t UEP2_DMA; + __IO uint32_t UEP3_DMA; + __IO uint32_t UEP4_DMA; + __IO uint32_t UEP5_DMA; + __IO uint32_t UEP6_DMA; + __IO uint32_t UEP7_DMA; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint32_t Reserve2; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBOTG_FS_TypeDef; + +typedef struct __attribute__((packed)) { + __IO uint8_t BASE_CTRL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_ADDR; + __IO uint8_t Reserve0; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t Reserve1; + __IO uint8_t Reserve2; + __IO uint8_t HOST_EP_MOD; + __IO uint16_t Reserve3; + __IO uint32_t Reserve4; + __IO uint32_t Reserve5; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t Reserve6; + __IO uint32_t Reserve7; + __IO uint32_t Reserve8; + __IO uint32_t Reserve9; + __IO uint32_t Reserve10; + __IO uint16_t Reserve11; + __IO uint16_t HOST_SETUP; + __IO uint8_t HOST_EP_PID; + __IO uint8_t Reserve12; + __IO uint8_t Reserve13; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t Reserve14; + __IO uint32_t Reserve15; + __IO uint32_t Reserve16; + __IO uint32_t Reserve17; + __IO uint32_t Reserve18; + __IO uint32_t Reserve19; + __IO uint32_t OTG_CR; + __IO uint32_t OTG_SR; +} USBOTGH_FS_TypeDef; + +typedef struct +{ + __IO uint8_t BASE_CTRL; /*!< 0x40008000 */ + __IO uint8_t HOST_CTRL; /*!< 0x40008001 */ + __IO uint8_t INT_EN; /*!< 0x40008002 */ + __IO uint8_t DEV_ADDR; /*!< 0x40008003 */ + __IO uint8_t USB_STATUS0; /*!< 0x40008004 */ + __IO uint8_t MIS_ST; /*!< 0x40008005 */ + __IO uint8_t INT_FG; /*!< 0x40008006 */ + __IO uint8_t INT_ST; /*!< 0x40008007 */ + __IO uint8_t RX_LEN; /*!< 0x40008008 */ + __IO uint8_t Reserve1; /*!< 0x40008009 */ + __IO uint8_t Reserve2; /*!< 0x4000800a */ + __IO uint8_t Reserve3; /*!< 0x4000800b */ + __IO uint8_t UEP4_1_MOD; /*!< 0x4000800c */ + __IO uint8_t HOST_EP_MOD; /*!< 0x4000800d */ + __IO uint8_t UEP567_MOD; /*!< 0x4000800e */ + __IO uint8_t Reserve4; /*!< 0x4000800f */ + __IO uint16_t UEP0_DMA; /*!< 0x40008010 */ + __IO uint16_t Reserve5; /*!< 0x40008012 */ + __IO uint16_t UEP1_DMA; /*!< 0x40008014 */ + __IO uint16_t Reserve6; /*!< 0x40008016 */ + __IO uint16_t HOST_RX_DMA; /*!< 0x40008018 */ + __IO uint16_t Reserve7; /*!< 0x4000801a */ + __IO uint16_t HOST_TX_DMA; /*!< 0x4000801c */ + __IO uint16_t Reserve8; /*!< 0x4000801e */ + __IO uint8_t UEP0_T_LEN; /*!< 0x40008020 */ + __IO uint8_t Reserve9; /*!< 0x40008021 */ + __IO uint8_t UEP0_CTRL; /*!< 0x40008022 */ + __IO uint8_t Reserve10; /*!< 0x40008023 */ + __IO uint8_t UEP1_T_LEN; /*!< 0x40008024 */ + __IO uint8_t Reserve11; /*!< 0x40008025 */ + __IO uint8_t HOST_SETUP; /*!< 0x40008026 */ + __IO uint8_t Reserve12; /*!< 0x40008027 */ + __IO uint8_t HOST_EP_PID; /*!< 0x40008028 */ + __IO uint8_t Reserve13; /*!< 0x40008029 */ + __IO uint8_t HOST_RX_CTRL; /*!< 0x4000802a */ + __IO uint8_t Reserve14; /*!< 0x4000802b */ + __IO uint8_t HOST_TX_LEN; /*!< 0x4000802c */ + __IO uint8_t Reserve15; /*!< 0x4000802d */ + __IO uint8_t HOST_TX_CTRL; /*!< 0x4000802e */ + __IO uint8_t Reserve16; /*!< 0x4000802f */ + __IO uint8_t UEP4_T_LEN; /*!< 0x40008030 */ + __IO uint8_t Reserve17; /*!< 0x40008031 */ + __IO uint8_t UEP4_CTRL; /*!< 0x40008032 */ + __IO uint8_t Reserve18[33]; /*!< 0x40008033 */ + __IO uint16_t UEP5_DMA; /*!< 0x40008054 */ + __IO uint16_t Reserve19; /*!< 0x40008056 */ + __IO uint16_t UEP6_DMA; /*!< 0x40008058 */ + __IO uint16_t Reserve20; /*!< 0x4000805a */ + __IO uint16_t UEP7_DMA; /*!< 0x4000805c */ + __IO uint8_t Reserve21[6]; /*!< 0x4000805e */ + __IO uint8_t UEP5_T_LEN; /*!< 0x40008064 */ + __IO uint8_t Reserve22; /*!< 0x40008065 */ + __IO uint8_t UEP5_CTRL; /*!< 0x40008066 */ + __IO uint8_t Reserve23; /*!< 0x40008067 */ + __IO uint8_t UEP6_T_LEN; /*!< 0x40008068 */ + __IO uint8_t Reserve24; /*!< 0x40008069 */ + __IO uint8_t UEP6_CTRL; /*!< 0x4000806a */ + __IO uint8_t Reserve25; /*!< 0x4000806b */ + __IO uint8_t UEP7_T_LEN; /*!< 0x4000806c */ + __IO uint8_t Reserve26; /*!< 0x4000806d */ + __IO uint8_t UEP7_CTRL; /*!< 0x4000806e */ +} USB_FS_TypeDef; + +#define USBFS_BASE ((uint32_t)0x50000000) + +#define USBFS_DEVICE ((USBOTG_FS_TypeDef *)USBFS_BASE) +#define USBFS_HOST ((USBOTGH_FS_TypeDef *)USBFS_BASE) + +/******************* GLOBAL ******************/ + +/* BASE USB_CTRL */ +#define USBFS_BASE_CTRL_OFFSET 0x00 // USB base control +#define USBFS_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define USBFS_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define USBFS_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define USBFS_UC_SYS_CTRL1 0x20 // USB system control high bit +#define USBFS_UC_SYS_CTRL0 0x10 // USB system control low bit +#define USBFS_UC_SYS_CTRL_MASK 0x30 // bit mask of USB system control +// UC_HOST_MODE & UC_SYS_CTRL1 & UC_SYS_CTRL0: USB system control +// 0 00: disable USB device and disable internal pullup resistance +// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance +// 0 1x: enable USB device and enable internal pullup resistance +// 1 00: enable USB host and normal status +// 1 01: enable USB host and force UDP/UDM output SE0 state +// 1 10: enable USB host and force UDP/UDM output J state +// 1 11: enable USB host and force UDP/UDM output resume or K state +#define USBFS_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define USBFS_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define USBFS_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define USBFS_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +/* USB INT EN */ +#define USBFS_INT_EN_OFFSET 0x02 +#define USBFS_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define USBFS_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define USBFS_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define USBFS_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define USBFS_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define USBFS_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define USBFS_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define USBFS_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode +/* USB_DEV_ADDR */ +#define USBFS_DEV_ADDR_OFFSET 0x03 +#define USBFS_UDA_GP_BIT 0x80 // general purpose bit +#define USBFS_USB_ADDR_MASK 0x7F // bit mask for USB device address + +/* USB_STATUS */ +#define USBFS_USB_STATUS_OFFSET 0x04 + +/* USB_MIS_ST */ +#define USBFS_MIS_ST_OFFSET 0x05 +#define USBFS_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define USBFS_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define USBFS_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define USBFS_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define USBFS_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define USBFS_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define USBFS_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host + +/* USB_INT_FG */ +#define USBFS_INT_FG_OFFSET 0x06 +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* USB_INT_ST */ +#define USBFS_INT_ST_OFFSET 0x07 +#define USBFS_UIS_IS_SETUP 0x80 // RO, indicate current USB transfer is setup received for USB device mode +#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define USBFS_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// UIS_TOKEN1 & UIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +/* USB_RX_LEN */ +#define USBFS_RX_LEN_OFFSET 0x08 + +/******************* DEVICE ******************/ + +/* UDEV_CTRL */ +#define USBFS_UDEV_CTRL_OFFSET 0x01 +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* UEP4_1_MOD */ +#define USBFS_UEP4_1_MOD_OFFSET 0x0C +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// UEPn_RX_EN & UEPn_TX_EN & UEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// UEP4_RX_EN & UEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +/* UEP2_3_MOD */ +#define USBFS_UEP2_3_MOD_OFFSET 0x0D +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* UEP5_6_MOD */ +#define USBFS_UEP5_6_MOD_OFFSET 0x0E +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* UEP7_MOD */ +#define USBFS_UEP7_MOD_OFFSET 0x0F +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* USB_DMA */ +#define USBFS_UEPx_DMA_OFFSET(n) (0x10 + 4 * (n)) // endpoint x DMA buffer address +#define USBFS_UEP0_DMA_OFFSET 0x10 // endpoint 0 DMA buffer address +#define USBFS_UEP1_DMA_OFFSET 0x14 // endpoint 1 DMA buffer address +#define USBFS_UEP2_DMA_OFFSET 0x18 // endpoint 2 DMA buffer address +#define USBFS_UEP3_DMA_OFFSET 0x1c // endpoint 3 DMA buffer address +#define USBFS_UEP4_DMA_OFFSET 0x20 // endpoint 4 DMA buffer address +#define USBFS_UEP5_DMA_OFFSET 0x24 // endpoint 5 DMA buffer address +#define USBFS_UEP6_DMA_OFFSET 0x28 // endpoint 6 DMA buffer address +#define USBFS_UEP7_DMA_OFFSET 0x2c // endpoint 7 DMA buffer address +/* USB_EP_CTRL */ +#define USBFS_UEPx_T_LEN_OFFSET(n) (0x30 + 4 * (n)) // endpoint x DMA buffer address +#define USBFS_UEPx_TX_CTRL_OFFSET(n) (0x30 + 4 * (n) + 2) // endpoint x DMA buffer address +#define USBFS_UEPx_RX_CTRL_OFFSET(n) (0x30 + 4 * (n) + 3) // endpoint x DMA buffer address + +#define USBFS_UEP_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x04 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_TOG 0x04 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + +#define USBFS_UEP_R_RES1 0x02 // handshake response type high bit for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES0 0x01 // handshake response type low bit for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_TOUT 0x01 +#define USBFS_UEP_R_RES_NAK 0x02 +#define USBFS_UEP_R_RES_STALL 0x03 +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +#define USBFS_UEP_T_RES1 0x02 // handshake response type high bit for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES0 0x01 // handshake response type low bit for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_TOUT 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: TALL (error) + +/******************* HOST ******************/ + +#define USBFS_UHOST_CTRL_OFFSET 0x01 // USB host physical prot control +#define USBFS_UH_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UH_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UH_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UH_LOW_SPEED 0x04 // enable USB port low speed: 0=full speed, 1=low speed +#define USBFS_UH_BUS_RESET 0x02 // control USB bus reset: 0=normal, 1=force bus reset +#define USBFS_UH_PORT_EN 0x01 // enable USB port: 0=disable, 1=enable port, automatic disabled if USB device detached + +#define USBFS_UH_EP_MOD_OFFSET USBFS_UEP2_3_MOD_OFFSET +#define USBFS_UH_EP_TX_EN 0x40 // enable USB host OUT endpoint transmittal +#define USBFS_UH_EP_TBUF_MOD 0x10 // buffer mode of USB host OUT endpoint +// bUH_EP_TX_EN & bUH_EP_TBUF_MOD: USB host OUT endpoint buffer mode, buffer start address is UH_TX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for transmittal (OUT endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_T_TOG selection for transmittal (OUT endpoint), total=128bytes +#define USBFS_UH_EP_RX_EN 0x08 // enable USB host IN endpoint receiving +#define USBFS_UH_EP_RBUF_MOD 0x01 // buffer mode of USB host IN endpoint +// bUH_EP_RX_EN & bUH_EP_RBUF_MOD: USB host IN endpoint buffer mode, buffer start address is UH_RX_DMA +// 0 x: disable endpoint and disable buffer +// 1 0: 64 bytes buffer for receiving (IN endpoint) +// 1 1: dual 64 bytes buffer by toggle bit bUH_R_TOG selection for receiving (IN endpoint), total=128bytes + +#define USBFS_UH_RX_DMA_OFFSET USBFS_UEPx_DMA_OFFSET(2) // host rx endpoint buffer high address +#define USBFS_UH_TX_DMA_OFFSET USBFS_UEPx_DMA_OFFSET(3) // host tx endpoint buffer high address + +#define USBFS_UH_SETUP_OFFSET USBFS_UEPx_TX_CTRL_OFFSET(1) +#define USBFS_UH_PRE_PID_EN 0x0400 // USB host PRE PID enable for low speed device via hub +#define USBFS_UH_SOF_EN 0x04 // USB host automatic SOF enable + +#define USBFS_UH_EP_PID_OFFSET USBFS_UEPx_T_LEN_OFFSET(2) +#define USBFS_UH_TOKEN_MASK 0xF0 // bit mask of token PID for USB host transfer +#define USBFS_UH_ENDP_MASK 0x0F // bit mask of endpoint number for USB host transfer + +#define USBFS_UH_RX_CTRL_OFFSET USBFS_UEPx_RX_CTRL_OFFSET(2) // host receiver endpoint control +#define USBFS_UH_R_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_R_TOG 0x04 // expected data toggle flag of host receiving (IN): 0=DATA0, 1=DATA1 +#define USBFS_UH_R_RES 0x01 // prepared handshake response type for host receiving (IN): 0=ACK (ready), 1=no response, time out to device, for isochronous transactions + +#define USBFS_UH_TX_LEN_OFFSET USBFS_UEPx_T_LEN_OFFSET(3) + +#define USBFS_UH_TX_CTRL_OFFSET USBFS_UEPx_TX_CTRL_OFFSET(3) // host transmittal endpoint control +#define USBFS_UH_T_AUTO_TOG 0x08 // enable automatic toggle after successful transfer completion: 0=manual toggle, 1=automatic toggle +#define USBFS_UH_T_TOG 0x04 // prepared data toggle flag of host transmittal (SETUP/OUT): 0=DATA0, 1=DATA1 +#define USBFS_UH_T_RES 0x01 // expected handshake response type for host transmittal (SETUP/OUT): 0=ACK (ready), 1=no response, time out from device, for isochronous transactions + +#endif diff --git a/components/drivers/usb/cherryusb/port/ch32/usb_ch32_usbhs_reg.h b/components/drivers/usb/cherryusb/port/ch32/usb_ch32_usbhs_reg.h new file mode 100644 index 00000000000..1dca5d1b87a --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ch32/usb_ch32_usbhs_reg.h @@ -0,0 +1,564 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _USB_CH32_USBHS_REG_H +#define _USB_CH32_USBHS_REG_H + +#define __IO volatile /* defines 'read / write' permissions */ + +/* USBHS Registers */ +typedef struct +{ + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t ENDP_CONFIG; + __IO uint32_t ENDP_TYPE; + __IO uint32_t BUF_MODE; + __IO uint32_t UEP0_DMA; + __IO uint32_t UEP1_RX_DMA; + __IO uint32_t UEP2_RX_DMA; + __IO uint32_t UEP3_RX_DMA; + __IO uint32_t UEP4_RX_DMA; + __IO uint32_t UEP5_RX_DMA; + __IO uint32_t UEP6_RX_DMA; + __IO uint32_t UEP7_RX_DMA; + __IO uint32_t UEP8_RX_DMA; + __IO uint32_t UEP9_RX_DMA; + __IO uint32_t UEP10_RX_DMA; + __IO uint32_t UEP11_RX_DMA; + __IO uint32_t UEP12_RX_DMA; + __IO uint32_t UEP13_RX_DMA; + __IO uint32_t UEP14_RX_DMA; + __IO uint32_t UEP15_RX_DMA; + __IO uint32_t UEP1_TX_DMA; + __IO uint32_t UEP2_TX_DMA; + __IO uint32_t UEP3_TX_DMA; + __IO uint32_t UEP4_TX_DMA; + __IO uint32_t UEP5_TX_DMA; + __IO uint32_t UEP6_TX_DMA; + __IO uint32_t UEP7_TX_DMA; + __IO uint32_t UEP8_TX_DMA; + __IO uint32_t UEP9_TX_DMA; + __IO uint32_t UEP10_TX_DMA; + __IO uint32_t UEP11_TX_DMA; + __IO uint32_t UEP12_TX_DMA; + __IO uint32_t UEP13_TX_DMA; + __IO uint32_t UEP14_TX_DMA; + __IO uint32_t UEP15_TX_DMA; + __IO uint16_t UEP0_MAX_LEN; + __IO uint16_t RESERVED2; + __IO uint16_t UEP1_MAX_LEN; + __IO uint16_t RESERVED3; + __IO uint16_t UEP2_MAX_LEN; + __IO uint16_t RESERVED4; + __IO uint16_t UEP3_MAX_LEN; + __IO uint16_t RESERVED5; + __IO uint16_t UEP4_MAX_LEN; + __IO uint16_t RESERVED6; + __IO uint16_t UEP5_MAX_LEN; + __IO uint16_t RESERVED7; + __IO uint16_t UEP6_MAX_LEN; + __IO uint16_t RESERVED8; + __IO uint16_t UEP7_MAX_LEN; + __IO uint16_t RESERVED9; + __IO uint16_t UEP8_MAX_LEN; + __IO uint16_t RESERVED10; + __IO uint16_t UEP9_MAX_LEN; + __IO uint16_t RESERVED11; + __IO uint16_t UEP10_MAX_LEN; + __IO uint16_t RESERVED12; + __IO uint16_t UEP11_MAX_LEN; + __IO uint16_t RESERVED13; + __IO uint16_t UEP12_MAX_LEN; + __IO uint16_t RESERVED14; + __IO uint16_t UEP13_MAX_LEN; + __IO uint16_t RESERVED15; + __IO uint16_t UEP14_MAX_LEN; + __IO uint16_t RESERVED16; + __IO uint16_t UEP15_MAX_LEN; + __IO uint16_t RESERVED17; + __IO uint16_t UEP0_TX_LEN; + __IO uint8_t UEP0_TX_CTRL; + __IO uint8_t UEP0_RX_CTRL; + __IO uint16_t UEP1_TX_LEN; + __IO uint8_t UEP1_TX_CTRL; + __IO uint8_t UEP1_RX_CTRL; + __IO uint16_t UEP2_TX_LEN; + __IO uint8_t UEP2_TX_CTRL; + __IO uint8_t UEP2_RX_CTRL; + __IO uint16_t UEP3_TX_LEN; + __IO uint8_t UEP3_TX_CTRL; + __IO uint8_t UEP3_RX_CTRL; + __IO uint16_t UEP4_TX_LEN; + __IO uint8_t UEP4_TX_CTRL; + __IO uint8_t UEP4_RX_CTRL; + __IO uint16_t UEP5_TX_LEN; + __IO uint8_t UEP5_TX_CTRL; + __IO uint8_t UEP5_RX_CTRL; + __IO uint16_t UEP6_TX_LEN; + __IO uint8_t UEP6_TX_CTRL; + __IO uint8_t UEP6_RX_CTRL; + __IO uint16_t UEP7_TX_LEN; + __IO uint8_t UEP7_TX_CTRL; + __IO uint8_t UEP7_RX_CTRL; + __IO uint16_t UEP8_TX_LEN; + __IO uint8_t UEP8_TX_CTRL; + __IO uint8_t UEP8_RX_CTRL; + __IO uint16_t UEP9_TX_LEN; + __IO uint8_t UEP9_TX_CTRL; + __IO uint8_t UEP9_RX_CTRL; + __IO uint16_t UEP10_TX_LEN; + __IO uint8_t UEP10_TX_CTRL; + __IO uint8_t UEP10_RX_CTRL; + __IO uint16_t UEP11_TX_LEN; + __IO uint8_t UEP11_TX_CTRL; + __IO uint8_t UEP11_RX_CTRL; + __IO uint16_t UEP12_TX_LEN; + __IO uint8_t UEP12_TX_CTRL; + __IO uint8_t UEP12_RX_CTRL; + __IO uint16_t UEP13_TX_LEN; + __IO uint8_t UEP13_TX_CTRL; + __IO uint8_t UEP13_RX_CTRL; + __IO uint16_t UEP14_TX_LEN; + __IO uint8_t UEP14_TX_CTRL; + __IO uint8_t UEP14_RX_CTRL; + __IO uint16_t UEP15_TX_LEN; + __IO uint8_t UEP15_TX_CTRL; + __IO uint8_t UEP15_RX_CTRL; +} USBHSD_TypeDef; + +typedef struct __attribute__((packed)) { + __IO uint8_t CONTROL; + __IO uint8_t HOST_CTRL; + __IO uint8_t INT_EN; + __IO uint8_t DEV_AD; + __IO uint16_t FRAME_NO; + __IO uint8_t SUSPEND; + __IO uint8_t RESERVED0; + __IO uint8_t SPEED_TYPE; + __IO uint8_t MIS_ST; + __IO uint8_t INT_FG; + __IO uint8_t INT_ST; + __IO uint16_t RX_LEN; + __IO uint16_t RESERVED1; + __IO uint32_t HOST_EP_CONFIG; + __IO uint32_t HOST_EP_TYPE; + __IO uint32_t RESERVED2; + __IO uint32_t RESERVED3; + __IO uint32_t RESERVED4; + __IO uint32_t HOST_RX_DMA; + __IO uint32_t RESERVED5; + __IO uint32_t RESERVED6; + __IO uint32_t RESERVED7; + __IO uint32_t RESERVED8; + __IO uint32_t RESERVED9; + __IO uint32_t RESERVED10; + __IO uint32_t RESERVED11; + __IO uint32_t RESERVED12; + __IO uint32_t RESERVED13; + __IO uint32_t RESERVED14; + __IO uint32_t RESERVED15; + __IO uint32_t RESERVED16; + __IO uint32_t RESERVED17; + __IO uint32_t RESERVED18; + __IO uint32_t RESERVED19; + __IO uint32_t HOST_TX_DMA; + __IO uint32_t RESERVED20; + __IO uint32_t RESERVED21; + __IO uint32_t RESERVED22; + __IO uint32_t RESERVED23; + __IO uint32_t RESERVED24; + __IO uint32_t RESERVED25; + __IO uint32_t RESERVED26; + __IO uint32_t RESERVED27; + __IO uint32_t RESERVED28; + __IO uint32_t RESERVED29; + __IO uint32_t RESERVED30; + __IO uint32_t RESERVED31; + __IO uint32_t RESERVED32; + __IO uint32_t RESERVED33; + __IO uint16_t HOST_RX_MAX_LEN; + __IO uint16_t RESERVED34; + __IO uint32_t RESERVED35; + __IO uint32_t RESERVED36; + __IO uint32_t RESERVED37; + __IO uint32_t RESERVED38; + __IO uint32_t RESERVED39; + __IO uint32_t RESERVED40; + __IO uint32_t RESERVED41; + __IO uint32_t RESERVED42; + __IO uint32_t RESERVED43; + __IO uint32_t RESERVED44; + __IO uint32_t RESERVED45; + __IO uint32_t RESERVED46; + __IO uint32_t RESERVED47; + __IO uint32_t RESERVED48; + __IO uint32_t RESERVED49; + __IO uint8_t HOST_EP_PID; + __IO uint8_t RESERVED50; + __IO uint8_t RESERVED51; + __IO uint8_t HOST_RX_CTRL; + __IO uint16_t HOST_TX_LEN; + __IO uint8_t HOST_TX_CTRL; + __IO uint8_t RESERVED52; + __IO uint16_t HOST_SPLIT_DATA; +} USBHSH_TypeDef; + +#define USBHS_BASE ((uint32_t)(0x40000000 + 0x23400)) + +#define USBHS_DEVICE ((USBHSD_TypeDef *)USBHS_BASE) +#define USBHS_HOST ((USBHSH_TypeDef *)USBHS_BASE) + +/******************* GLOBAL ******************/ + +// USB CONTROL +#define USBHS_CONTROL_OFFSET 0x00 +#define USBHS_DMA_EN (1 << 0) +#define USBHS_ALL_CLR (1 << 1) +#define USBHS_FORCE_RST (1 << 2) +#define USBHS_INT_BUSY_EN (1 << 3) +#define USBHS_DEV_PU_EN (1 << 4) +#define USBHS_SPEED_MASK (3 << 5) +#define USBHS_FULL_SPEED (0 << 5) +#define USBHS_HIGH_SPEED (1 << 5) +#define USBHS_LOW_SPEED (2 << 5) +#define USBHS_HOST_MODE (1 << 7) + +// USB_INT_EN +#define USBHS_INT_EN_OFFSET 0x02 +#define USBHS_BUS_RST_EN (1 << 0) +#define USBHS_DETECT_EN (1 << 0) +#define USBHS_TRANSFER_EN (1 << 1) +#define USBHS_SUSPEND_EN (1 << 2) +#define USBHS_SOF_ACT_EN (1 << 3) +#define USBHS_FIFO_OV_EN (1 << 4) +#define USBHS_SETUP_ACT_EN (1 << 5) +#define USBHS_ISO_ACT_EN (1 << 6) +#define USBHS_DEV_NAK_EN (1 << 7) + +// USB DEV AD +#define USBHS_DEV_AD_OFFSET 0x03 +// USB FRAME_NO +#define USBHS_FRAME_NO_OFFSET 0x04 +// USB SUSPEND +#define USBHS_SUSPEND_OFFSET 0x06 +#define USBHS_DEV_REMOTE_WAKEUP (1 << 2) +#define USBHS_LINESTATE_MASK (2 << 4) /* Read Only */ + +// RESERVED0 + +// USB SPEED TYPE +#define USBHS_SPEED_TYPE_OFFSET 0x08 +#define USBSPEED_MASK (0x03) + +// USB_MIS_ST +#define USBHS_MIS_ST_OFFSET 0x09 +#define USBHS_SPLIT_CAN (1 << 0) +#define USBHS_ATTACH (1 << 1) +#define USBHS_SUSPEND (1 << 2) +#define USBHS_BUS_RESET (1 << 3) +#define USBHS_R_FIFO_RDY (1 << 4) +#define USBHS_SIE_FREE (1 << 5) +#define USBHS_SOF_ACT (1 << 6) +#define USBHS_SOF_PRES (1 << 7) + +// INT_FLAG +#define USBHS_INT_FLAG_OFFSET 0x0A +#define USBHS_BUS_RST_FLAG (1 << 0) +#define USBHS_DETECT_FLAG (1 << 0) +#define USBHS_TRANSFER_FLAG (1 << 1) +#define USBHS_SUSPEND_FLAG (1 << 2) +#define USBHS_HST_SOF_FLAG (1 << 3) +#define USBHS_FIFO_OV_FLAG (1 << 4) +#define USBHS_SETUP_FLAG (1 << 5) +#define USBHS_ISO_ACT_FLAG (1 << 6) + +// INT_ST +#define USBHS_INT_ST_OFFSET 0x0B +#define USBHS_DEV_UIS_IS_NAK (1 << 7) +#define USBHS_DEV_UIS_TOG_OK (1 << 6) +#define MASK_UIS_TOKEN (3 << 4) +#define MASK_UIS_ENDP (0x0F) +#define MASK_UIS_H_RES (0x0F) + +#define USBHS_TOGGLE_OK (0x40) +#define USBHS_HOST_RES (0x0f) + +//USB_RX_LEN +#define USBHS_RX_LEN_OFFSET 0x0C +/******************* DEVICE ******************/ + +//UEP_CONFIG +#define USBHS_UEP_CONFIG_OFFSET 0x10 +#define USBHS_EP0_T_EN (1 << 0) +#define USBHS_EP0_R_EN (1 << 16) + +#define USBHS_EP1_T_EN (1 << 1) +#define USBHS_EP1_R_EN (1 << 17) + +#define USBHS_EP2_T_EN (1 << 2) +#define USBHS_EP2_R_EN (1 << 18) + +#define USBHS_EP3_T_EN (1 << 3) +#define USBHS_EP3_R_EN (1 << 19) + +#define USBHS_EP4_T_EN (1 << 4) +#define USBHS_EP4_R_EN (1 << 20) + +#define USBHS_EP5_T_EN (1 << 5) +#define USBHS_EP5_R_EN (1 << 21) + +#define USBHS_EP6_T_EN (1 << 6) +#define USBHS_EP6_R_EN (1 << 22) + +#define USBHS_EP7_T_EN (1 << 7) +#define USBHS_EP7_R_EN (1 << 23) + +#define USBHS_EP8_T_EN (1 << 8) +#define USBHS_EP8_R_EN (1 << 24) + +#define USBHS_EP9_T_EN (1 << 9) +#define USBHS_EP9_R_EN (1 << 25) + +#define USBHS_EP10_T_EN (1 << 10) +#define USBHS_EP10_R_EN (1 << 26) + +#define USBHS_EP11_T_EN (1 << 11) +#define USBHS_EP11_R_EN (1 << 27) + +#define USBHS_EP12_T_EN (1 << 12) +#define USBHS_EP12_R_EN (1 << 28) + +#define USBHS_EP13_T_EN (1 << 13) +#define USBHS_EP13_R_EN (1 << 29) + +#define USBHS_EP14_T_EN (1 << 14) +#define USBHS_EP14_R_EN (1 << 30) + +#define USBHS_EP15_T_EN (1 << 15) +#define USBHS_EP15_R_EN (1 << 31) + +//UEP_TYPE +#define USBHS_UEP_TYPE_OFFSET 0x14 +#define USBHS_EP0_T_TYP (1 << 0) +#define USBHS_EP0_R_TYP (1 << 16) + +#define USBHS_EP1_T_TYP (1 << 1) +#define USBHS_EP1_R_TYP (1 << 17) + +#define USBHS_EP2_T_TYP (1 << 2) +#define USBHS_EP2_R_TYP (1 << 18) + +#define USBHS_EP3_T_TYP (1 << 3) +#define USBHS_EP3_R_TYP (1 << 19) + +#define USBHS_EP4_T_TYP (1 << 4) +#define USBHS_EP4_R_TYP (1 << 20) + +#define USBHS_EP5_T_TYP (1 << 5) +#define USBHS_EP5_R_TYP (1 << 21) + +#define USBHS_EP6_T_TYP (1 << 6) +#define USBHS_EP6_R_TYP (1 << 22) + +#define USBHS_EP7_T_TYP (1 << 7) +#define USBHS_EP7_R_TYP (1 << 23) + +#define USBHS_EP8_T_TYP (1 << 8) +#define USBHS_EP8_R_TYP (1 << 24) + +#define USBHS_EP9_T_TYP (1 << 8) +#define USBHS_EP9_R_TYP (1 << 25) + +#define USBHS_EP10_T_TYP (1 << 10) +#define USBHS_EP10_R_TYP (1 << 26) + +#define USBHS_EP11_T_TYP (1 << 11) +#define USBHS_EP11_R_TYP (1 << 27) + +#define USBHS_EP12_T_TYP (1 << 12) +#define USBHS_EP12_R_TYP (1 << 28) + +#define USBHS_EP13_T_TYP (1 << 13) +#define USBHS_EP13_R_TYP (1 << 29) + +#define USBHS_EP14_T_TYP (1 << 14) +#define USBHS_EP14_R_TYP (1 << 30) + +#define USBHS_EP15_T_TYP (1 << 15) +#define USBHS_EP15_R_TYP (1 << 31) + +/* BUF_MOD UEP1~15 */ +#define USBHS_BUF_MOD_OFFSET 0x18 +#define USBHS_EP0_BUF_MOD (1 << 0) +#define USBHS_EP0_ISO_BUF_MOD (1 << 16) + +#define USBHS_EP1_BUF_MOD (1 << 1) +#define USBHS_EP1_ISO_BUF_MOD (1 << 17) + +#define USBHS_EP2_BUF_MOD (1 << 2) +#define USBHS_EP2_ISO_BUF_MOD (1 << 18) + +#define USBHS_EP3_BUF_MOD (1 << 3) +#define USBHS_EP3_ISO_BUF_MOD (1 << 19) + +#define USBHS_EP4_BUF_MOD (1 << 4) +#define USBHS_EP4_ISO_BUF_MOD (1 << 20) + +#define USBHS_EP5_BUF_MOD (1 << 5) +#define USBHS_EP5_ISO_BUF_MOD (1 << 21) + +#define USBHS_EP6_BUF_MOD (1 << 6) +#define USBHS_EP6_ISO_BUF_MOD (1 << 22) + +#define USBHS_EP7_BUF_MOD (1 << 7) +#define USBHS_EP7_ISO_BUF_MOD (1 << 23) + +#define USBHS_EP8_BUF_MOD (1 << 8) +#define USBHS_EP8_ISO_BUF_MOD (1 << 24) + +#define USBHS_EP9_BUF_MOD (1 << 9) +#define USBHS_EP9_ISO_BUF_MOD (1 << 25) + +#define USBHS_EP10_BUF_MOD (1 << 10) +#define USBHS_EP10_ISO_BUF_MOD (1 << 26) + +#define USBHS_EP11_BUF_MOD (1 << 11) +#define USBHS_EP11_ISO_BUF_MOD (1 << 27) + +#define USBHS_EP12_BUF_MOD (1 << 12) +#define USBHS_EP12_ISO_BUF_MOD (1 << 28) + +#define USBHS_EP13_BUF_MOD (1 << 13) +#define USBHS_EP13_ISO_BUF_MOD (1 << 29) + +#define USBHS_EP14_BUF_MOD (1 << 14) +#define USBHS_EP14_ISO_BUF_MOD (1 << 30) + +#define USBHS_EP15_BUF_MOD (1 << 15) +#define USBHS_EP15_ISO_BUF_MOD (1 << 31) +//USBHS_EPn_T_EN USBHS_EPn_R_EN USBHS_EPn_BUF_MOD 锟斤拷锟斤拷锟斤拷锟斤拷UEPn_DMA为锟斤拷始锟斤拷址锟缴碉拷锟斤拷锟斤拷锟斤拷锟� +// 0 0 x 锟剿点被锟斤拷锟矫ｏ拷未锟矫碉拷UEPn_*_DMA锟斤拷锟斤拷锟斤拷锟斤拷 +// 1 0 0 锟斤拷锟秸ｏ拷OUT锟斤拷锟斤拷锟斤拷锟斤拷锟阶碉拷址为UEPn_RX_DMA +// 1 0 1 bUEPn_RX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA锟斤拷bUEPn_RX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA +// 0 1 0 锟斤拷锟斤拷(IN)锟斤拷锟斤拷锟斤拷锟阶碉拷址为UEPn_TX_DMA锟斤拷 +// 0 1 1 bUEPn_TX_TOG[0]=0,使锟矫伙拷锟斤拷锟斤拷UEPn_TX_DMA锟斤拷bUEPn_TX_TOG[0]=1,使锟矫伙拷锟斤拷锟斤拷UEPn_RX_DMA + +/* USB0_DMA */ +#define USBHS_UEP0_DMA_OFFSET(n) (0x1C) // endpoint 0 DMA buffer address + +/* USBX_RX_DMA */ +#define USBHS_UEPx_RX_DMA_OFFSET(n) (0x1C + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_TX_DMA_OFFSET(n) (0x58 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_MAX_LEN_OFFSET(n) (0x98 + 4 * (n)) // endpoint x DMA buffer address + +#define USBHS_UEPx_T_LEN_OFFSET(n) (0xD8 + 4 * (n)) // endpoint x DMA buffer address +#define USBHS_UEPx_TX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 2) // endpoint x DMA buffer address +#define USBHS_UEPx_RX_CTRL_OFFSET(n) (0xD8 + 4 * (n) + 3) // endpoint x DMA buffer address + +// UEPn_T_LEN +#define USBHS_EP_T_LEN_MASK (0x7FF) + +//UEPn_TX_CTRL +#define USBHS_EP_T_RES_MASK (3 << 0) +#define USBHS_EP_T_RES_ACK (0 << 0) +#define USBHS_EP_T_RES_NYET (1 << 0) +#define USBHS_EP_T_RES_NAK (2 << 0) +#define USBHS_EP_T_RES_STALL (3 << 0) + +#define USBHS_EP_T_TOG_MASK (3 << 3) +#define USBHS_EP_T_TOG_0 (0 << 3) +#define USBHS_EP_T_TOG_1 (1 << 3) +#define USBHS_EP_T_TOG_2 (2 << 3) +#define USBHS_EP_T_TOG_M (3 << 3) + +#define USBHS_EP_T_AUTOTOG (1 << 5) + +//UEPn_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_EP_R_TOG_MASK (3 << 3) +#define USBHS_EP_R_TOG_0 (0 << 3) +#define USBHS_EP_R_TOG_1 (1 << 3) +#define USBHS_EP_R_TOG_2 (2 << 3) +#define USBHS_EP_R_TOG_M (3 << 3) + +#define USBHS_EP_R_AUTOTOG (1 << 5) + +#define USBHS_TOG_MATCH (1 << 6) + +/******************* HOST ******************/ +// USB HOST_CTRL +#define USBHS_SEND_BUS_RESET (1 << 0) +#define USBHS_SEND_BUS_SUSPEND (1 << 1) +#define USBHS_SEND_BUS_RESUME (1 << 2) +#define USBHS_REMOTE_WAKE (1 << 3) +#define USBHS_PHY_SUSPENDM (1 << 4) +#define USBHS_UH_SOFT_FREE (1 << 6) +#define USBHS_SEND_SOF_EN (1 << 7) + +//UH_CONFIG +#define USBHS_HOST_TX_EN (1 << 3) +#define USBHS_HOST_RX_EN (1 << 18) + +// HOST_EP_TYPE +#define USBHS_ENDP_TX_ISO (1 << 3) +#define USBHS_ENDP_RX_ISO (1 << (16 + 2)) + +// R32_UH_EP_PID +#define USBHS_HOST_MASK_TOKEN (0x0f) +#define USBHS_HOST_MASK_ENDP (0x0f << 4) + +//R8_UH_RX_CTRL +#define USBHS_EP_R_RES_MASK (3 << 0) +#define USBHS_EP_R_RES_ACK (0 << 0) +#define USBHS_EP_R_RES_NYET (1 << 0) +#define USBHS_EP_R_RES_NAK (2 << 0) +#define USBHS_EP_R_RES_STALL (3 << 0) + +#define USBHS_UH_R_RES_NO (1 << 2) +#define USBHS_UH_R_TOG_1 (1 << 3) +#define USBHS_UH_R_TOG_2 (2 << 3) +#define USBHS_UH_R_TOG_3 (3 << 3) +#define USBHS_UH_R_TOG_AUTO (1 << 5) +#define USBHS_UH_R_DATA_NO (1 << 6) +//R8_UH_TX_CTRL +#define USBHS_UH_T_RES_MASK (3 << 0) +#define USBHS_UH_T_RES_ACK (0 << 0) +#define USBHS_UH_T_RES_NYET (1 << 0) +#define USBHS_UH_T_RES_NAK (2 << 0) +#define USBHS_UH_T_RES_STALL (3 << 0) + +#define USBHS_UH_T_RES_NO (1 << 2) +#define USBHS_UH_T_TOG_1 (1 << 3) +#define USBHS_UH_T_TOG_2 (2 << 3) +#define USBHS_UH_T_TOG_3 (3 << 3) +#define USBHS_UH_T_TOG_AUTO (1 << 5) +#define USBHS_UH_T_DATA_NO (1 << 6) + +// 00: OUT, 01:SOF, 10:IN, 11:SETUP +#define PID_OUT 0 +#define PID_SOF 1 +#define PID_IN 2 +#define PID_SETUP 3 + +#endif diff --git a/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbfs.c b/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbfs.c new file mode 100644 index 00000000000..4b4b72d497c --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbfs.c @@ -0,0 +1,404 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_ch32_usbfs_reg.h" + +#ifdef CONFIG_USB_HS +#error "usb fs do not support hs" +#endif + +#ifndef USBD_IRQHandler +#define USBD_IRQHandler OTG_FS_IRQHandler //use actual usb irq name instead +#endif + +#ifndef USB_NUM_BIDIR_ENDPOINTS +#define USB_NUM_BIDIR_ENDPOINTS 8 +#endif + +#define USB_SET_DMA(ep_idx, addr) (*(volatile uint32_t *)((uint32_t)(&USBFS_DEVICE->UEP0_DMA) + 4 * ep_idx) = addr) +#define USB_SET_TX_LEN(ep_idx, len) (*(volatile uint16_t *)((uint32_t)(&USBFS_DEVICE->UEP0_TX_LEN) + 4 * ep_idx) = len) +#define USB_GET_TX_LEN(ep_idx) (*(volatile uint16_t *)((uint32_t)(&USBFS_DEVICE->UEP0_TX_LEN) + 4 * ep_idx)) +#define USB_SET_TX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_TX_CTRL) + 4 * ep_idx) = val) +#define USB_GET_TX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_TX_CTRL) + 4 * ep_idx)) +#define USB_SET_RX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_RX_CTRL) + 4 * ep_idx) = val) +#define USB_GET_RX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_RX_CTRL) + 4 * ep_idx)) + +/* Endpoint state */ +struct ch32_usbfs_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct ch32_usbfs_udc { + __attribute__((aligned(4))) struct usb_setup_packet setup; + volatile uint8_t dev_addr; + struct ch32_usbfs_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct ch32_usbfs_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ + __attribute__((aligned(4))) uint8_t ep_databuf[USB_NUM_BIDIR_ENDPOINTS - 1][64 + 64]; //epx_out(64)+epx_in(64) +} g_ch32_usbfs_udc; + +volatile bool ep0_rx_data_toggle; +volatile bool ep0_tx_data_toggle; + +void USBD_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + usb_dc_low_level_init(); + + USBFS_DEVICE->BASE_CTRL = 0x00; + + USBFS_DEVICE->UEP4_1_MOD = USBFS_UEP4_RX_EN | USBFS_UEP4_TX_EN | USBFS_UEP1_RX_EN | USBFS_UEP1_TX_EN; + USBFS_DEVICE->UEP2_3_MOD = USBFS_UEP2_RX_EN | USBFS_UEP2_TX_EN | USBFS_UEP3_RX_EN | USBFS_UEP3_TX_EN; + USBFS_DEVICE->UEP5_6_MOD = USBFS_UEP5_RX_EN | USBFS_UEP5_TX_EN | USBFS_UEP6_RX_EN | USBFS_UEP6_TX_EN; + USBFS_DEVICE->UEP7_MOD = USBFS_UEP7_RX_EN | USBFS_UEP7_TX_EN; + + USBFS_DEVICE->UEP1_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[0]; + USBFS_DEVICE->UEP2_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[1]; + USBFS_DEVICE->UEP3_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[2]; + USBFS_DEVICE->UEP4_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[3]; + USBFS_DEVICE->UEP5_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[4]; + USBFS_DEVICE->UEP6_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[5]; + USBFS_DEVICE->UEP7_DMA = (uint32_t)g_ch32_usbfs_udc.ep_databuf[6]; + + USBFS_DEVICE->INT_FG = 0xFF; + USBFS_DEVICE->INT_EN = USBFS_UIE_SUSPEND | USBFS_UIE_BUS_RST | USBFS_UIE_TRANSFER; + USBFS_DEVICE->DEV_ADDR = 0x00; + + USBFS_DEVICE->BASE_CTRL = USBFS_UC_DEV_PU_EN | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN; + USBFS_DEVICE->UDEV_CTRL = USBFS_UD_PD_DIS | USBFS_UD_PORT_EN; + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + if (addr == 0) { + USBFS_DEVICE->DEV_ADDR = (USBFS_DEVICE->DEV_ADDR & USBFS_UDA_GP_BIT) | 0; + } + g_ch32_usbfs_udc.dev_addr = addr; + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_ch32_usbfs_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_ch32_usbfs_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_ch32_usbfs_udc.out_ep[ep_idx].ep_enable = true; + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_NAK | USBFS_UEP_AUTO_TOG); + } else { + g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_ch32_usbfs_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_ch32_usbfs_udc.in_ep[ep_idx].ep_enable = true; + USB_SET_TX_CTRL(ep_idx, USBFS_UEP_T_RES_NAK | USBFS_UEP_AUTO_TOG); + } + return 0; +} +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + return 0; +} +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (ep_idx == 0) { + USBFS_DEVICE->UEP0_RX_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_R_RES_STALL; + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_STALL); + } + } else { + if (ep_idx == 0) { + USBFS_DEVICE->UEP0_TX_CTRL = USBFS_UEP_T_TOG | USBFS_UEP_T_RES_STALL; + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_STALL); + } + } + + if (ep_idx == 0) { + USB_SET_DMA(ep_idx, (uint32_t)&g_ch32_usbfs_udc.setup); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + } + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (ep_idx == 0) { + return 0; + } + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~(USBFS_UEP_R_TOG | USBFS_UEP_R_RES_MASK)) | USBFS_UEP_R_RES_ACK); + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~(USBFS_UEP_T_TOG | USBFS_UEP_T_RES_MASK)) | USBFS_UEP_T_RES_NAK); + } + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_ch32_usbfs_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + if ((uint32_t)data & 0x03) { + printf("data do not align4\r\n"); + return -3; + } + + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len = data_len; + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, data_len); + USB_SET_DMA(ep_idx, (uint32_t)data); + } + if (ep0_tx_data_toggle) { + USB_SET_TX_CTRL(ep_idx, USBFS_UEP_T_TOG | USBFS_UEP_T_RES_ACK); + } else { + USB_SET_TX_CTRL(ep_idx, USBFS_UEP_T_RES_ACK); + } + + } else { + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, data_len); + memcpy(&g_ch32_usbfs_udc.ep_databuf[ep_idx - 1][64], data, data_len); + } + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK); + } + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_ch32_usbfs_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + printf("data do not align4\r\n"); + return -3; + } + + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len = data_len; + g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + } else { + USB_SET_DMA(ep_idx, (uint32_t)data); + } + if (ep0_rx_data_toggle) { + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_TOG | USBFS_UEP_R_RES_ACK); + } else { + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + } + return 0; + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_ACK); + } + + return 0; +} + +void USBD_IRQHandler(void) +{ + uint32_t ep_idx = 0, token, write_count, read_count; + uint8_t intflag = 0; + + intflag = USBFS_DEVICE->INT_FG; + + if (intflag & USBFS_UIF_TRANSFER) { + token = USBFS_DEVICE->INT_ST & USBFS_UIS_TOKEN_MASK; + ep_idx = USBFS_DEVICE->INT_ST & USBFS_UIS_ENDP_MASK; + switch (token) { + case USBFS_UIS_TOKEN_SETUP: + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_NAK); + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_ch32_usbfs_udc.setup); + break; + + case USBFS_UIS_TOKEN_IN: + if (ep_idx == 0x00) { + if (g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len >= g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps) { + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len -= g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + ep0_tx_data_toggle ^= 1; + } else { + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len = 0; + ep0_tx_data_toggle = true; + } + + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len); + + if (g_ch32_usbfs_udc.dev_addr > 0) { + USBFS_DEVICE->DEV_ADDR = (USBFS_DEVICE->DEV_ADDR & USBFS_UDA_GP_BIT) | g_ch32_usbfs_udc.dev_addr; + g_ch32_usbfs_udc.dev_addr = 0; + } + + if (g_ch32_usbfs_udc.setup.wLength && ((g_ch32_usbfs_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + /* In status, start reading setup */ + USB_SET_DMA(ep_idx, (uint32_t)&g_ch32_usbfs_udc.setup); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + ep0_tx_data_toggle = true; + + } else if (g_ch32_usbfs_udc.setup.wLength == 0) { + /* In status, start reading setup */ + USB_SET_DMA(ep_idx, (uint32_t)&g_ch32_usbfs_udc.setup); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + ep0_tx_data_toggle = true; + } + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK); + + if (g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len > g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps) { + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_buf += g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len -= g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + + write_count = MIN(g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len, g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, write_count); + memcpy(&g_ch32_usbfs_udc.ep_databuf[ep_idx - 1][64], g_ch32_usbfs_udc.in_ep[ep_idx].xfer_buf, write_count); + + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK); + } else { + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len); + } + } + break; + case USBFS_UIS_TOKEN_OUT: + if (ep_idx == 0x00) { + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_NAK); + + read_count = USBFS_DEVICE->RX_LEN; + + g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len -= read_count; + + usbd_event_ep_out_complete_handler(0, 0x00, g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len); + + if (read_count == 0) { + /* Out status, start reading setup */ + USB_SET_DMA(ep_idx, (uint32_t)&g_ch32_usbfs_udc.setup); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + ep0_rx_data_toggle = true; + ep0_tx_data_toggle = true; + } else { + ep0_rx_data_toggle ^= 1; + } + } else { + if (USBFS_DEVICE->INT_ST & USBFS_UIS_TOG_OK) { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_NAK); + read_count = USBFS_DEVICE->RX_LEN; + + memcpy(g_ch32_usbfs_udc.out_ep[ep_idx].xfer_buf, &g_ch32_usbfs_udc.ep_databuf[ep_idx - 1][0], read_count); + + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_buf += read_count; + g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len -= read_count; + + if ((read_count < g_ch32_usbfs_udc.out_ep[ep_idx].ep_mps) || (g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(0, ep_idx, g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len); + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_ACK); + } + } + } + break; + + case USBFS_UIS_TOKEN_SOF: + + break; + + default: + break; + } + + USBFS_DEVICE->INT_FG = USBFS_UIF_TRANSFER; + } else if (intflag & USBFS_UIF_BUS_RST) { + USBFS_DEVICE->UEP0_TX_LEN = 0; + USBFS_DEVICE->UEP0_TX_CTRL = USBFS_UEP_T_RES_NAK; + USBFS_DEVICE->UEP0_RX_CTRL = USBFS_UEP_R_RES_NAK; + + for (uint8_t ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) { + USB_SET_TX_LEN(ep_idx, 0); + USB_SET_TX_CTRL(ep_idx, USBFS_UEP_T_RES_NAK | USBFS_UEP_AUTO_TOG); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_NAK | USBFS_UEP_AUTO_TOG); + } + + ep0_tx_data_toggle = true; + ep0_rx_data_toggle = true; + + memset(&g_ch32_usbfs_udc, 0, sizeof(struct ch32_usbfs_udc)); + usbd_event_reset_handler(0); + USB_SET_DMA(ep_idx, (uint32_t)&g_ch32_usbfs_udc.setup); + USB_SET_RX_CTRL(ep_idx, USBFS_UEP_R_RES_ACK); + + USBFS_DEVICE->INT_FG |= USBFS_UIF_BUS_RST; + } else if (intflag & USBFS_UIF_SUSPEND) { + if (USBFS_DEVICE->MIS_ST & USBFS_UMS_SUSPEND) { + } else { + } + USBFS_DEVICE->INT_FG = USBFS_UIF_SUSPEND; + } else { + USBFS_DEVICE->INT_FG = intflag; + } +} diff --git a/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbhs.c b/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbhs.c new file mode 100644 index 00000000000..758ffd77f37 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ch32/usb_dc_usbhs.c @@ -0,0 +1,382 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_ch32_usbhs_reg.h" + +#ifndef USBD_IRQHandler +#define USBD_IRQHandler USBHS_IRQHandler //use actual usb irq name instead +#endif + +#ifndef USB_NUM_BIDIR_ENDPOINTS +#define USB_NUM_BIDIR_ENDPOINTS 16 +#endif + +#define USB_SET_RX_DMA(ep_idx, addr) (*(volatile uint32_t *)((uint32_t)(&USBHS_DEVICE->UEP1_RX_DMA) + 4 * (ep_idx - 1)) = addr) +#define USB_SET_TX_DMA(ep_idx, addr) (*(volatile uint32_t *)((uint32_t)(&USBHS_DEVICE->UEP1_TX_DMA) + 4 * (ep_idx - 1)) = addr) +#define USB_SET_MAX_LEN(ep_idx, len) (*(volatile uint16_t *)((uint32_t)(&USBHS_DEVICE->UEP0_MAX_LEN) + 4 * ep_idx) = len) +#define USB_SET_TX_LEN(ep_idx, len) (*(volatile uint16_t *)((uint32_t)(&USBHS_DEVICE->UEP0_TX_LEN) + 4 * ep_idx) = len) +#define USB_GET_TX_LEN(ep_idx) (*(volatile uint16_t *)((uint32_t)(&USBHS_DEVICE->UEP0_TX_LEN) + 4 * ep_idx)) +#define USB_SET_TX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&USBHS_DEVICE->UEP0_TX_CTRL) + 4 * ep_idx) = val) +#define USB_GET_TX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&USBHS_DEVICE->UEP0_TX_CTRL) + 4 * ep_idx)) +#define USB_SET_RX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&USBHS_DEVICE->UEP0_RX_CTRL) + 4 * ep_idx) = val) +#define USB_GET_RX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&USBHS_DEVICE->UEP0_RX_CTRL) + 4 * ep_idx)) + +/* Endpoint state */ +struct ch32_usbhs_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct ch32_usbhs_udc { + __attribute__((aligned(4))) struct usb_setup_packet setup; + volatile uint8_t dev_addr; + struct ch32_usbhs_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct ch32_usbhs_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ +} g_ch32_usbhs_udc; + +void USBHS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +volatile uint8_t mps_over_flag = 0; +volatile bool ep0_rx_data_toggle; +volatile bool ep0_tx_data_toggle; +volatile bool epx_tx_data_toggle[USB_NUM_BIDIR_ENDPOINTS - 1]; + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + usb_dc_low_level_init(); + + USBHS_DEVICE->HOST_CTRL = 0x00; + USBHS_DEVICE->HOST_CTRL = USBHS_PHY_SUSPENDM; + + USBHS_DEVICE->CONTROL = 0; +#ifdef CONFIG_USB_HS + USBHS_DEVICE->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_HIGH_SPEED; +#else + USBHS_DEVICE->CONTROL = USBHS_DMA_EN | USBHS_INT_BUSY_EN | USBHS_FULL_SPEED; +#endif + + USBHS_DEVICE->INT_FG = 0xff; + USBHS_DEVICE->INT_EN = 0; + USBHS_DEVICE->INT_EN = USBHS_SETUP_ACT_EN | USBHS_TRANSFER_EN | USBHS_DETECT_EN; + + /* ALL endpoint enable */ + USBHS_DEVICE->ENDP_CONFIG = 0xffffffff; + + USBHS_DEVICE->ENDP_TYPE = 0x00; + USBHS_DEVICE->BUF_MODE = 0x00; + + USBHS_DEVICE->CONTROL |= USBHS_DEV_PU_EN; + + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + if (addr == 0) { + USBHS_DEVICE->DEV_AD = addr & 0xff; + } + g_ch32_usbhs_udc.dev_addr = addr; + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_HIGH; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_ch32_usbhs_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_ch32_usbhs_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_ch32_usbhs_udc.out_ep[ep_idx].ep_enable = true; + USBHS_DEVICE->ENDP_CONFIG |= (1 << (ep_idx + 16)); + USB_SET_RX_CTRL(ep_idx, USBHS_EP_R_RES_NAK | USBHS_EP_R_TOG_0 | USBHS_EP_R_AUTOTOG); + } else { + g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_ch32_usbhs_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_ch32_usbhs_udc.in_ep[ep_idx].ep_enable = true; + USBHS_DEVICE->ENDP_CONFIG |= (1 << (ep_idx)); + USB_SET_TX_CTRL(ep_idx, USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0 | USBHS_EP_T_AUTOTOG); + } + USB_SET_MAX_LEN(ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (ep_idx == 0) { + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_STALL; + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_STALL); + } + } else { + if (ep_idx == 0) { + USBHS_DEVICE->UEP0_TX_CTRL = USBHS_EP_T_RES_STALL; + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBHS_EP_T_RES_MASK) | USBHS_EP_T_RES_STALL); + } + } + + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_SET_RX_CTRL(ep_idx, USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_0); + } else { + USB_SET_TX_CTRL(ep_idx, USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0); + } + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t tmp; + + if (!data && data_len) { + return -1; + } + if (!g_ch32_usbhs_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + return -3; + } + + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len = data_len; + g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, data_len); + USBHS_DEVICE->UEP0_DMA = (uint32_t)data; + } + tmp = ep0_tx_data_toggle ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0; + USBHS_DEVICE->UEP0_TX_CTRL = USBHS_EP_T_RES_ACK | tmp; + } else { + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, data_len); + USB_SET_TX_DMA(ep_idx, (uint32_t)data); + } + tmp = USB_GET_TX_CTRL(ep_idx); + tmp &= ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK); + tmp |= USBHS_EP_T_RES_ACK; + tmp |= (epx_tx_data_toggle[ep_idx - 1] ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + USB_SET_TX_CTRL(ep_idx, tmp); + } + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_ch32_usbhs_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + if ((uint32_t)data & 0x03) { + return -3; + } + + g_ch32_usbhs_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_ch32_usbhs_udc.out_ep[ep_idx].xfer_len = data_len; + g_ch32_usbhs_udc.out_ep[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | USBHS_EP_R_TOG_1; + } else { + USBHS_DEVICE->UEP0_DMA = (uint32_t)data; + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK | (ep0_rx_data_toggle ? USBHS_EP_R_TOG_1 : USBHS_EP_R_TOG_0); + } + return 0; + } else { + USB_SET_RX_DMA(ep_idx, (uint32_t)data); + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_ACK); + } + + return 0; +} + +void USBD_IRQHandler(void) +{ + uint32_t ep_idx, token, write_count, read_count; + uint8_t intflag = 0; + + intflag = USBHS_DEVICE->INT_FG; + + if (intflag & USBHS_TRANSFER_FLAG) { + ep_idx = (USBHS_DEVICE->INT_ST) & MASK_UIS_ENDP; + token = (((USBHS_DEVICE->INT_ST) & MASK_UIS_TOKEN) >> 4) & 0x03; + + if (token == PID_IN) { + if (ep_idx == 0x00) { + if (g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len >= g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps) { + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len -= g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps; + ep0_tx_data_toggle ^= 1; + } else { + g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len; + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len = 0; + ep0_tx_data_toggle = true; + } + + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len); + + if (g_ch32_usbhs_udc.dev_addr > 0) { + USBHS_DEVICE->DEV_AD = g_ch32_usbhs_udc.dev_addr & 0xff; + g_ch32_usbhs_udc.dev_addr = 0; + } + + if (g_ch32_usbhs_udc.setup.wLength && ((g_ch32_usbhs_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + /* In status, start reading setup */ + USBHS_DEVICE->UEP0_DMA = (uint32_t)&g_ch32_usbhs_udc.setup; + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + ep0_tx_data_toggle = true; + + } else if (g_ch32_usbhs_udc.setup.wLength == 0) { + /* In status, start reading setup */ + USBHS_DEVICE->UEP0_DMA = (uint32_t)&g_ch32_usbhs_udc.setup; + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + ep0_tx_data_toggle = true; + } + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK)) | USBHS_EP_T_RES_NAK | USBHS_EP_T_TOG_0); + + if (g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len > g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps) { + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_buf += g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len -= g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps; + epx_tx_data_toggle[ep_idx - 1] ^= 1; + + write_count = MIN(g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len, g_ch32_usbhs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, write_count); + USB_SET_TX_DMA(ep_idx, (uint32_t)g_ch32_usbhs_udc.in_ep[ep_idx].xfer_buf); + + uint32_t tmp = USB_GET_TX_CTRL(ep_idx); + tmp &= ~(USBHS_EP_T_RES_MASK | USBHS_EP_T_TOG_MASK); + tmp |= USBHS_EP_T_RES_ACK; + tmp |= (epx_tx_data_toggle[ep_idx - 1] ? USBHS_EP_T_TOG_1 : USBHS_EP_T_TOG_0); + USB_SET_TX_CTRL(ep_idx, tmp); + } else { + g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len; + g_ch32_usbhs_udc.in_ep[ep_idx].xfer_len = 0; + epx_tx_data_toggle[ep_idx - 1] ^= 1; + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_ch32_usbhs_udc.in_ep[ep_idx].actual_xfer_len); + } + } + } else if (token == PID_OUT) { + if (ep_idx == 0x00) { + read_count = USBHS_DEVICE->RX_LEN; + + g_ch32_usbhs_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_ch32_usbhs_udc.out_ep[ep_idx].xfer_len -= read_count; + + usbd_event_ep_out_complete_handler(0, 0x00, g_ch32_usbhs_udc.out_ep[ep_idx].actual_xfer_len); + + if (read_count == 0) { + /* Out status, start reading setup */ + USBHS_DEVICE->UEP0_DMA = (uint32_t)&g_ch32_usbhs_udc.setup; + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + ep0_rx_data_toggle = true; + ep0_tx_data_toggle = true; + } else { + ep0_rx_data_toggle ^= 1; + } + } else { + if (USBHS_DEVICE->INT_ST & USBHS_DEV_UIS_TOG_OK) { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_NAK); + read_count = USBHS_DEVICE->RX_LEN; + + g_ch32_usbhs_udc.out_ep[ep_idx].xfer_buf += read_count; + g_ch32_usbhs_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_ch32_usbhs_udc.out_ep[ep_idx].xfer_len -= read_count; + + if ((read_count < g_ch32_usbhs_udc.out_ep[ep_idx].ep_mps) || (g_ch32_usbhs_udc.out_ep[ep_idx].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(0, ep_idx, g_ch32_usbhs_udc.out_ep[ep_idx].actual_xfer_len); + } else { + USB_SET_RX_DMA(ep_idx, (uint32_t)g_ch32_usbhs_udc.out_ep[ep_idx].xfer_buf); + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBHS_EP_R_RES_MASK) | USBHS_EP_R_RES_ACK); + } + } + } + } + USBHS_DEVICE->INT_FG = USBHS_TRANSFER_FLAG; + } else if (intflag & USBHS_SETUP_FLAG) { + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_ch32_usbhs_udc.setup); + USBHS_DEVICE->INT_FG = USBHS_SETUP_FLAG; + } else if (intflag & USBHS_DETECT_FLAG) { + USBHS_DEVICE->ENDP_CONFIG = USBHS_EP0_T_EN | USBHS_EP0_R_EN; + + USBHS_DEVICE->UEP0_TX_LEN = 0; + USBHS_DEVICE->UEP0_TX_CTRL = USBHS_EP_T_RES_NAK; + + ep0_tx_data_toggle = true; + ep0_rx_data_toggle = true; + + for (uint8_t ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) { + USB_SET_TX_LEN(ep_idx, 0); + USB_SET_TX_CTRL(ep_idx, USBHS_EP_T_AUTOTOG | USBHS_EP_T_RES_NAK); // autotog does not work + USB_SET_RX_CTRL(ep_idx, USBHS_EP_R_AUTOTOG | USBHS_EP_R_RES_NAK); + epx_tx_data_toggle[ep_idx - 1] = false; + } + + memset(&g_ch32_usbhs_udc, 0, sizeof(struct ch32_usbhs_udc)); + usbd_event_reset_handler(0); + USBHS_DEVICE->UEP0_DMA = (uint32_t)&g_ch32_usbhs_udc.setup; + USBHS_DEVICE->UEP0_RX_CTRL = USBHS_EP_R_RES_ACK; + USBHS_DEVICE->INT_FG = USBHS_DETECT_FLAG; + } +} diff --git a/components/drivers/usb/cherryusb/port/dwc2/README.md b/components/drivers/usb/cherryusb/port/dwc2/README.md new file mode 100644 index 00000000000..2c084afd683 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/dwc2/README.md @@ -0,0 +1,31 @@ +# Note + +## Support Chip List + +## STM32 + +- STM32F105xc、STM32F107xc +- STM32F205xx、STM32F207xx、STM32F215xx、STM32F217xx +- STM32F401xc、STM32F401xe、STM32F405xx、STM32F407xx、STM32F411xe、STM32F412cx、STM32F412rx、STM32F412vx、STM32F412zx、STM32F413xx、STM32F415xx、STM32F417xx、STM32F423xx、STM32F423xx、STM32F429xx、STM32F437xx、STM32F439xx、STM32F446xx、STM32F469xx、STM32F479xx +- STM32F7xx +- STM32H7xx +- STM32L4xx +- STM32MPxx + +## AT32 + +- AT32F402xx、AT32F405xx、AT32F415xx、AT32F423xx、AT32F425xx、AT32F435xx、AT32F437xx + +## GD32 + +- GD32F30X_CL +- GD32F405、GD32F407 +- GD32F450 + +## HC32 + +- HC32F4A0 + +## Espressif + +- ESP32S2、ESP32S3 diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c b/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c new file mode 100644 index 00000000000..9dee5c1d981 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_dc_dwc2.c @@ -0,0 +1,1191 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_dwc2_reg.h" + +// clang-format off +#if defined ( __CC_ARM ) +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#elif defined ( __GNUC__ ) +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#endif +// clang-format on + +//#define CONFIG_USB_DWC2_DMA_ENABLE + +#ifndef CONFIG_USB_DWC2_RXALL_FIFO_SIZE +#define CONFIG_USB_DWC2_RXALL_FIFO_SIZE (1024 / 4) +#endif + +#ifndef CONFIG_USB_DWC2_TX0_FIFO_SIZE +#define CONFIG_USB_DWC2_TX0_FIFO_SIZE (64 / 4) +#endif + +#ifndef CONFIG_USB_DWC2_TX1_FIFO_SIZE +#define CONFIG_USB_DWC2_TX1_FIFO_SIZE (512 / 4) +#endif + +#ifndef CONFIG_USB_DWC2_TX2_FIFO_SIZE +#define CONFIG_USB_DWC2_TX2_FIFO_SIZE (64 / 4) +#endif + +#ifndef CONFIG_USB_DWC2_TX3_FIFO_SIZE +#define CONFIG_USB_DWC2_TX3_FIFO_SIZE (64 / 4) +#endif + +#ifndef CONFIG_USB_DWC2_TX4_FIFO_SIZE +#define CONFIG_USB_DWC2_TX4_FIFO_SIZE (64 / 4) +#endif + +#ifndef CONFIG_USB_DWC2_TX5_FIFO_SIZE +#define CONFIG_USB_DWC2_TX5_FIFO_SIZE (64 / 4) +#endif + +#ifndef CONFIG_USB_DWC2_TX6_FIFO_SIZE +#define CONFIG_USB_DWC2_TX6_FIFO_SIZE (0 / 4) +#endif + +#ifndef CONFIG_USB_DWC2_TX7_FIFO_SIZE +#define CONFIG_USB_DWC2_TX7_FIFO_SIZE (0 / 4) +#endif + +#ifndef CONFIG_USB_DWC2_TX8_FIFO_SIZE +#define CONFIG_USB_DWC2_TX8_FIFO_SIZE (0 / 4) +#endif + +#define USBD_BASE (g_usbdev_bus[0].reg_base) + +#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(USBD_BASE)) +#define USB_OTG_DEV ((DWC2_DeviceTypeDef *)(USBD_BASE + USB_OTG_DEVICE_BASE)) +#define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)USBD_BASE + USB_OTG_PCGCCTL_BASE) +#define USB_OTG_INEP(i) ((DWC2_INEndpointTypeDef *)(USBD_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE))) +#define USB_OTG_OUTEP(i) ((DWC2_OUTEndpointTypeDef *)(USBD_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i)*USB_OTG_EP_REG_SIZE))) +#define USB_OTG_FIFO(i) *(__IO uint32_t *)(USBD_BASE + USB_OTG_FIFO_BASE + ((i)*USB_OTG_FIFO_SIZE)) + +extern uint32_t SystemCoreClock; + +/* Endpoint state */ +struct dwc2_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +USB_NOCACHE_RAM_SECTION struct dwc2_udc { + __attribute__((aligned(32))) struct usb_setup_packet setup; + struct dwc2_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ + struct dwc2_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ +} g_dwc2_udc; + +static inline int dwc2_reset(void) +{ + volatile uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USB_OTG_GLB->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return 0; +} + +static inline int dwc2_core_init(void) +{ + int ret; +#if defined(CONFIG_USB_HS) + /* Init The ULPI Interface */ + USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + + /* Reset after a PHY select */ + ret = dwc2_reset(); +#else + /* Select FS Embedded PHY */ + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + + /* Reset after a PHY select */ + ret = dwc2_reset(); +#endif + return ret; +} + +static inline void dwc2_set_mode(uint8_t mode) +{ + USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_OTG_MODE_HOST) { + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + } else if (mode == USB_OTG_MODE_DEVICE) { + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + } +} + +static inline int dwc2_flush_rxfifo(void) +{ + volatile uint32_t count = 0; + + USB_OTG_GLB->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return 0; +} + +static inline int dwc2_flush_txfifo(uint32_t num) +{ + volatile uint32_t count = 0U; + + USB_OTG_GLB->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return 0; +} + +static void dwc2_set_turnaroundtime(uint32_t hclk, uint8_t speed) +{ + uint32_t UsbTrd; + + /* The USBTRD is configured according to the tables below, depending on AHB frequency + used by application. In the low AHB frequency range it is used to stretch enough the USB response + time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access + latency to the Data FIFO */ + if (speed == USB_OTG_SPEED_FULL) { + if ((hclk >= 14200000U) && (hclk < 15000000U)) { + /* hclk Clock Range between 14.2-15 MHz */ + UsbTrd = 0xFU; + } else if ((hclk >= 15000000U) && (hclk < 16000000U)) { + /* hclk Clock Range between 15-16 MHz */ + UsbTrd = 0xEU; + } else if ((hclk >= 16000000U) && (hclk < 17200000U)) { + /* hclk Clock Range between 16-17.2 MHz */ + UsbTrd = 0xDU; + } else if ((hclk >= 17200000U) && (hclk < 18500000U)) { + /* hclk Clock Range between 17.2-18.5 MHz */ + UsbTrd = 0xCU; + } else if ((hclk >= 18500000U) && (hclk < 20000000U)) { + /* hclk Clock Range between 18.5-20 MHz */ + UsbTrd = 0xBU; + } else if ((hclk >= 20000000U) && (hclk < 21800000U)) { + /* hclk Clock Range between 20-21.8 MHz */ + UsbTrd = 0xAU; + } else if ((hclk >= 21800000U) && (hclk < 24000000U)) { + /* hclk Clock Range between 21.8-24 MHz */ + UsbTrd = 0x9U; + } else if ((hclk >= 24000000U) && (hclk < 27700000U)) { + /* hclk Clock Range between 24-27.7 MHz */ + UsbTrd = 0x8U; + } else if ((hclk >= 27700000U) && (hclk < 32000000U)) { + /* hclk Clock Range between 27.7-32 MHz */ + UsbTrd = 0x7U; + } else /* if(hclk >= 32000000) */ + { + /* hclk Clock Range between 32-200 MHz */ + UsbTrd = 0x6U; + } + } else if (speed == USB_OTG_SPEED_HIGH) { + UsbTrd = USBD_HS_TRDT_VALUE; + } else { + UsbTrd = USBD_DEFAULT_TRDT_VALUE; + } + + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_TOCAL; + + USB_OTG_GLB->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; + USB_OTG_GLB->GUSBCFG |= (uint32_t)((UsbTrd << USB_OTG_GUSBCFG_TRDT_Pos) & USB_OTG_GUSBCFG_TRDT); +} + +static void dwc2_set_txfifo(uint8_t fifo, uint16_t size) +{ + uint8_t i; + uint32_t tx_offset; + + /* TXn min size = 16 words. (n : Transmit FIFO index) + When a TxFIFO is not used, the Configuration should be as follows: + case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txm can use the space allocated for Txn. + case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) + --> Txn should be configured with the minimum space of 16 words + The FIFO is used optimally when used TxFIFOs are allocated in the top + of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. + When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ + + tx_offset = USB_OTG_GLB->GRXFSIZ; + + if (fifo == 0U) { + USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | tx_offset; + } else { + tx_offset += (USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ) >> 16; + for (i = 0U; i < (fifo - 1U); i++) { + tx_offset += (USB_OTG_GLB->DIEPTXF[i] >> 16); + } + + /* Multiply Tx_Size by 2 to get higher performance */ + USB_OTG_GLB->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | tx_offset; + } + + USB_LOG_INFO("fifo%d size:%04x, offset:%04x\r\n", fifo, size, tx_offset); +} + +static uint8_t dwc2_get_devspeed(void) +{ + uint8_t speed; + uint32_t DevEnumSpeed = USB_OTG_DEV->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) { + speed = USB_OTG_SPEED_HIGH; + } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { + speed = USB_OTG_SPEED_FULL; + } else { + speed = 0xFU; + } + + return speed; +} + +static void dwc2_ep0_start_read_setup(uint8_t *psetup) +{ + USB_OTG_OUTEP(0U)->DOEPTSIZ = 0U; + USB_OTG_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USB_OTG_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); + USB_OTG_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; + +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + USB_OTG_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; + /* EP enable */ + USB_OTG_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; +#endif +} + +void dwc2_ep_write(uint8_t ep_idx, uint8_t *src, uint16_t len) +{ + uint32_t *pSrc = (uint32_t *)src; + uint32_t count32b, i; + + count32b = ((uint32_t)len + 3U) / 4U; + for (i = 0U; i < count32b; i++) { + USB_OTG_FIFO((uint32_t)ep_idx) = __UNALIGNED_UINT32_READ(pSrc); + pSrc++; + } +} + +void dwc2_ep_read(uint8_t *dest, uint16_t len) +{ + uint32_t *pDest = (uint32_t *)dest; + uint32_t i; + uint32_t count32b = ((uint32_t)len + 3U) / 4U; + + for (i = 0U; i < count32b; i++) { + __UNALIGNED_UINT32_WRITE(pDest, USB_OTG_FIFO(0U)); + pDest++; + } +} + +static void dwc2_tx_fifo_empty_procecss(uint8_t ep_idx) +{ + uint32_t len; + uint32_t len32b; + uint32_t fifoemptymsk; + + len = g_dwc2_udc.in_ep[ep_idx].xfer_len - g_dwc2_udc.in_ep[ep_idx].actual_xfer_len; + if (len > g_dwc2_udc.in_ep[ep_idx].ep_mps) { + len = g_dwc2_udc.in_ep[ep_idx].ep_mps; + } + + len32b = (len + 3U) / 4U; + + while (((USB_OTG_INEP(ep_idx)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && + (g_dwc2_udc.in_ep[ep_idx].actual_xfer_len < g_dwc2_udc.in_ep[ep_idx].xfer_len) && (g_dwc2_udc.in_ep[ep_idx].xfer_len != 0U)) { + /* Write the FIFO */ + len = g_dwc2_udc.in_ep[ep_idx].xfer_len - g_dwc2_udc.in_ep[ep_idx].actual_xfer_len; + if (len > g_dwc2_udc.in_ep[ep_idx].ep_mps) { + len = g_dwc2_udc.in_ep[ep_idx].ep_mps; + } + + dwc2_ep_write(ep_idx, g_dwc2_udc.in_ep[ep_idx].xfer_buf, len); + g_dwc2_udc.in_ep[ep_idx].xfer_buf += len; + g_dwc2_udc.in_ep[ep_idx].actual_xfer_len += len; + } + + if (g_dwc2_udc.in_ep[ep_idx].xfer_len <= g_dwc2_udc.in_ep[ep_idx].actual_xfer_len) { + fifoemptymsk = (uint32_t)(0x1UL << (ep_idx & 0x0f)); + USB_OTG_DEV->DIEPEMPMSK &= ~fifoemptymsk; + } +} + +/** + * @brief dwc2_get_glb_intstatus: return the global USB interrupt status + * @retval status + */ +static inline uint32_t dwc2_get_glb_intstatus(void) +{ + uint32_t tmpreg; + + tmpreg = USB_OTG_GLB->GINTSTS; + tmpreg &= USB_OTG_GLB->GINTMSK; + + return tmpreg; +} + +/** + * @brief dwc2_get_outeps_intstatus: return the USB device OUT endpoints interrupt status + * @retval status + */ +static inline uint32_t dwc2_get_outeps_intstatus(void) +{ + uint32_t tmpreg; + + tmpreg = USB_OTG_DEV->DAINT; + tmpreg &= USB_OTG_DEV->DAINTMSK; + + return ((tmpreg & 0xffff0000U) >> 16); +} + +/** + * @brief dwc2_get_ineps_intstatus: return the USB device IN endpoints interrupt status + * @retval status + */ +static inline uint32_t dwc2_get_ineps_intstatus(void) +{ + uint32_t tmpreg; + + tmpreg = USB_OTG_DEV->DAINT; + tmpreg &= USB_OTG_DEV->DAINTMSK; + + return ((tmpreg & 0xFFFFU)); +} + +/** + * @brief Returns Device OUT EP Interrupt register + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device OUT EP Interrupt register + */ +static inline uint32_t dwc2_get_outep_intstatus(uint8_t epnum) +{ + uint32_t tmpreg; + + tmpreg = USB_OTG_OUTEP((uint32_t)epnum)->DOEPINT; + tmpreg &= USB_OTG_DEV->DOEPMSK; + + return tmpreg; +} + +/** + * @brief Returns Device IN EP Interrupt register + * @param epnum endpoint number + * This parameter can be a value from 0 to 15 + * @retval Device IN EP Interrupt register + */ +static inline uint32_t dwc2_get_inep_intstatus(uint8_t epnum) +{ + uint32_t tmpreg, msk, emp; + + msk = USB_OTG_DEV->DIEPMSK; + emp = USB_OTG_DEV->DIEPEMPMSK; + msk |= ((emp >> (epnum & 0x07)) & 0x1U) << 7; + tmpreg = USB_OTG_INEP((uint32_t)epnum)->DIEPINT & msk; + + return tmpreg; +} + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + int ret; + uint8_t fsphy_type; + uint8_t hsphy_type; + uint8_t dma_support; + uint8_t endpoints; + uint32_t fifo_num; + + memset(&g_dwc2_udc, 0, sizeof(struct dwc2_udc)); + + usb_dc_low_level_init(); + + /* + Full-Speed PHY Interface Type (FSPhyType) + 2'b00: Full-speed interface not supported + 2'b01: Dedicated full-speed interface + 2'b10: FS pins shared with UTMI+ pins + 2'b11: FS pins shared with ULPI pins + + High-Speed PHY Interface Type (HSPhyType) + 2'b00: High-Speed interface not supported + 2'b01: UTMI+ + 2'b10: ULPI + 2'b11: UTMI+ and ULPI + + Architecture (OtgArch) + 2'b00: Slave-Only + 2'b01: External DMA + 2'b10: Internal DMA + Others: Reserved + */ + fsphy_type = ((USB_OTG_GLB->GHWCFG2 & (0x03 << 8)) >> 8); + hsphy_type = ((USB_OTG_GLB->GHWCFG2 & (0x03 << 6)) >> 6); + dma_support = ((USB_OTG_GLB->GHWCFG2 & (0x03 << 3)) >> 3); + endpoints = ((USB_OTG_GLB->GHWCFG2 & (0x0f << 10)) >> 10) + 1; + + USB_LOG_INFO("========== dwc2 udc params ==========\r\n"); + USB_LOG_INFO("CID:%08x\r\n", USB_OTG_GLB->CID); + USB_LOG_INFO("GSNPSID:%08x\r\n", USB_OTG_GLB->GSNPSID); + USB_LOG_INFO("GHWCFG1:%08x\r\n", USB_OTG_GLB->GHWCFG1); + USB_LOG_INFO("GHWCFG2:%08x\r\n", USB_OTG_GLB->GHWCFG2); + USB_LOG_INFO("GHWCFG3:%08x\r\n", USB_OTG_GLB->GHWCFG3); + USB_LOG_INFO("GHWCFG4:%08x\r\n", USB_OTG_GLB->GHWCFG4); + + USB_LOG_INFO("dwc2 fsphy type:%d, hsphy type:%d, dma support:%d\r\n", fsphy_type, hsphy_type, dma_support); + USB_LOG_INFO("dwc2 has %d endpoints and dfifo depth(32-bit words) is %d, default config: %d endpoints\r\n", endpoints, (USB_OTG_GLB->GHWCFG3 >> 16), CONFIG_USBDEV_EP_NUM); + USB_LOG_INFO("=================================\r\n"); + + if (endpoints < CONFIG_USBDEV_EP_NUM) { + USB_LOG_ERR("dwc2 has less endpoints than config, please check\r\n"); + while (1) { + } + } + + USB_OTG_DEV->DCTL |= USB_OTG_DCTL_SDIS; + + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + + /* This is vendor register */ + USB_OTG_GLB->GCCFG = usbd_get_dwc2_gccfg_conf(USBD_BASE); + + ret = dwc2_core_init(); + + /* Force Device Mode*/ + dwc2_set_mode(USB_OTG_MODE_DEVICE); + + /* B-peripheral session valid override enable */ + // USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + // USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; + + for (uint8_t i = 0U; i < 15U; i++) { + USB_OTG_GLB->DIEPTXF[i] = 0U; + } + + /* Restart the Phy Clock */ + USB_OTG_PCGCCTL = 0U; + + /* Device speed configuration */ + USB_OTG_DEV->DCFG &= ~USB_OTG_DCFG_DSPD; +#if defined(CONFIG_USB_HS) + USB_OTG_DEV->DCFG |= USB_OTG_SPEED_HIGH; +#else + if (hsphy_type == 0) { + USB_OTG_DEV->DCFG |= USB_OTG_SPEED_FULL; + } else { + USB_OTG_DEV->DCFG |= USB_OTG_SPEED_HIGH_IN_FULL; + } +#endif + + /* Clear all pending Device Interrupts */ + USB_OTG_DEV->DIEPMSK = 0U; + USB_OTG_DEV->DOEPMSK = 0U; + USB_OTG_DEV->DAINTMSK = 0U; + + /* Disable all interrupts. */ + USB_OTG_GLB->GINTMSK = 0U; + /* Clear any pending interrupts */ + USB_OTG_GLB->GINTSTS = 0xBFFFFFFFU; + + /* Enable interrupts matching to the Device mode ONLY */ + USB_OTG_GLB->GINTMSK = USB_OTG_GINTMSK_USBRST | USB_OTG_GINTMSK_ENUMDNEM | + USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IEPINT | + USB_OTG_GINTMSK_IISOIXFRM | USB_OTG_GINTMSK_PXFRM_IISOOXFRM; + +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + if (((USB_OTG_GLB->GHWCFG2 & (0x3U << 3)) >> 3) != 2) { + USB_LOG_ERR("This dwc2 version does not support dma mode, so stop working\r\n"); + while (1) { + } + } + + USB_OTG_DEV->DCFG &= ~USB_OTG_DCFG_DESCDMA; + USB_OTG_GLB->GAHBCFG |= (USB_OTG_GAHBCFG_DMAEN | USB_OTG_GAHBCFG_HBSTLEN_4); +#else + USB_OTG_GLB->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; +#endif +#if CONFIG_DWC2_VBUS_SENSING + USB_OTG_GLB->GINTMSK |= (USB_OTG_GINTMSK_OTGINT | USB_OTG_GINTMSK_SRQIM); +#endif +#if 0 + USB_OTG_GLB->GINTMSK |= USB_OTG_GINTMSK_SOFM; +#endif + + USB_OTG_GLB->GRXFSIZ = (CONFIG_USB_DWC2_RXALL_FIFO_SIZE); + + dwc2_set_txfifo(0, CONFIG_USB_DWC2_TX0_FIFO_SIZE); + dwc2_set_txfifo(1, CONFIG_USB_DWC2_TX1_FIFO_SIZE); + dwc2_set_txfifo(2, CONFIG_USB_DWC2_TX2_FIFO_SIZE); + dwc2_set_txfifo(3, CONFIG_USB_DWC2_TX3_FIFO_SIZE); + + fifo_num = CONFIG_USB_DWC2_RXALL_FIFO_SIZE; + fifo_num += CONFIG_USB_DWC2_TX0_FIFO_SIZE; + fifo_num += CONFIG_USB_DWC2_TX1_FIFO_SIZE; + fifo_num += CONFIG_USB_DWC2_TX2_FIFO_SIZE; + fifo_num += CONFIG_USB_DWC2_TX3_FIFO_SIZE; +#if CONFIG_USBDEV_EP_NUM > 4 + dwc2_set_txfifo(4, CONFIG_USB_DWC2_TX4_FIFO_SIZE); + fifo_num += CONFIG_USB_DWC2_TX4_FIFO_SIZE; +#endif +#if CONFIG_USBDEV_EP_NUM > 5 + dwc2_set_txfifo(5, CONFIG_USB_DWC2_TX5_FIFO_SIZE); + fifo_num += CONFIG_USB_DWC2_TX5_FIFO_SIZE; +#endif +#if CONFIG_USBDEV_EP_NUM > 6 + dwc2_set_txfifo(6, CONFIG_USB_DWC2_TX6_FIFO_SIZE); + fifo_num += CONFIG_USB_DWC2_TX6_FIFO_SIZE; +#endif +#if CONFIG_USBDEV_EP_NUM > 7 + dwc2_set_txfifo(7, CONFIG_USB_DWC2_TX7_FIFO_SIZE); + fifo_num += CONFIG_USB_DWC2_TX7_FIFO_SIZE; +#endif +#if CONFIG_USBDEV_EP_NUM > 8 + dwc2_set_txfifo(8, CONFIG_USB_DWC2_TX8_FIFO_SIZE); + fifo_num += CONFIG_USB_DWC2_TX8_FIFO_SIZE; +#endif + + if (fifo_num > (USB_OTG_GLB->GHWCFG3 >> 16)) { + USB_LOG_ERR("Your fifo config is overflow, please check\r\n"); + while (1) { + } + } + + /* xxx32 chips do not follow (USB_OTG_GLB->GHWCFG3 >> 16) if hsphy_type is zero, they use 1.25KB(320 DWORD) */ + if ((hsphy_type == 0) && (fifo_num > 320)) { + USB_LOG_ERR("Your fifo config is larger than 320 , please check\r\n"); + while (1) { + } + } + + ret = dwc2_flush_txfifo(0x10U); + ret = dwc2_flush_rxfifo(); + + USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + USB_OTG_DEV->DCTL &= ~USB_OTG_DCTL_SDIS; + + return ret; +} + +int usb_dc_deinit(uint8_t busid) +{ + USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + USB_OTG_DEV->DCTL |= USB_OTG_DCTL_SDIS; + + /* Clear Pending interrupt */ + for (uint8_t i = 0U; i < 15U; i++) { + USB_OTG_INEP(i)->DIEPINT = 0xFB7FU; + USB_OTG_OUTEP(i)->DOEPINT = 0xFB7FU; + } + + /* Clear interrupt masks */ + USB_OTG_DEV->DIEPMSK = 0U; + USB_OTG_DEV->DOEPMSK = 0U; + USB_OTG_DEV->DAINTMSK = 0U; + + /* Flush the FIFO */ + dwc2_flush_txfifo(0x10U); + dwc2_flush_rxfifo(); + + usb_dc_low_level_deinit(); + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + USB_OTG_DEV->DCFG &= ~(USB_OTG_DCFG_DAD); + USB_OTG_DEV->DCFG |= ((uint32_t)addr << 4) & USB_OTG_DCFG_DAD; + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + uint8_t speed; + uint32_t DevEnumSpeed = USB_OTG_DEV->DSTS & USB_OTG_DSTS_ENUMSPD; + + if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) { + speed = USB_SPEED_HIGH; + } else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || + (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) { + speed = USB_SPEED_FULL; + } else { + speed = USB_SPEED_FULL; + } + + return speed; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + if (ep_idx > (CONFIG_USBDEV_EP_NUM - 1)) { + USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress); + return -1; + } + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_dwc2_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_dwc2_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + + USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & (uint32_t)(1UL << (16 + ep_idx)); + + if ((USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_USBAEP) == 0) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) & USB_OTG_DOEPCTL_MPSIZ) | + ((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DOEPCTL_USBAEP; + } + } else { + uint16_t fifo_size; + if (ep_idx == 0) { + fifo_size = (USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ >> 16); + } else { + fifo_size = (USB_OTG_GLB->DIEPTXF[ep_idx - 1U] >> 16); + } + if ((fifo_size * 4) < USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)) { + USB_LOG_ERR("Ep addr %02x fifo overflow\r\n", ep->bEndpointAddress); + return -2; + } + + g_dwc2_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_dwc2_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + + USB_OTG_DEV->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << ep_idx); + + if ((USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0) { + USB_OTG_INEP(ep_idx)->DIEPCTL |= (USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize) & USB_OTG_DIEPCTL_MPSIZ) | + ((uint32_t)USB_GET_ENDPOINT_TYPE(ep->bmAttributes) << 18) | (ep_idx << 22) | + USB_OTG_DIEPCTL_SD0PID_SEVNFRM | + USB_OTG_DIEPCTL_USBAEP; + } + dwc2_flush_txfifo(ep_idx); + } + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + volatile uint32_t count = 0U; + + if (USB_EP_DIR_IS_OUT(ep)) { + if (USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; + + /* Wait for endpoint disabled interrupt */ + count = 0; + do { + if (++count > 50000) { + break; + } + } while ((USB_OTG_OUTEP(ep_idx)->DOEPINT & USB_OTG_DOEPINT_EPDISD) != USB_OTG_DOEPINT_EPDISD); + + /* Clear and unmask endpoint disabled interrupt */ + USB_OTG_OUTEP(ep_idx)->DOEPINT |= USB_OTG_DOEPINT_EPDISD; + } + + USB_OTG_DEV->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep_idx & 0x07)) << 16)); + USB_OTG_DEV->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep_idx & 0x07)) << 16)); + USB_OTG_OUTEP(ep_idx)->DOEPCTL = 0; + } else { + if (USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) { + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; + + /* Wait for endpoint disabled interrupt */ + count = 0; + do { + if (++count > 50000) { + break; + } + } while ((USB_OTG_INEP(ep_idx)->DIEPINT & USB_OTG_DIEPINT_EPDISD) != USB_OTG_DIEPINT_EPDISD); + + /* Clear and unmask endpoint disabled interrupt */ + USB_OTG_INEP(ep_idx)->DIEPINT |= USB_OTG_DIEPINT_EPDISD; + } + + USB_OTG_DEV->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & 0x07))); + USB_OTG_DEV->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep_idx & 0x07))); + USB_OTG_INEP(ep_idx)->DIEPCTL = 0; + } + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (((USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (ep_idx != 0U)) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); + } + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; + } else { + if (((USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (ep_idx != 0U)) { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); + } + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; + } +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + if (ep_idx == 0) { + dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup); + } +#endif + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; + if ((g_dwc2_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) || + (g_dwc2_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_BULK)) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } else { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; + if ((g_dwc2_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_INTERRUPT) || + (g_dwc2_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_BULK)) { + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ + } + } + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + if (USB_EP_DIR_IS_OUT(ep)) { + } else { + } + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t pktcnt = 0; + + if (!data && data_len) { + return -1; + } +#if 0 /* some chips have confused with this, so disable as default */ + if (USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) { + return -2; + } +#endif + if (ep_idx && !(USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_MPSIZ)) { + return -3; + } + if ((uint32_t)data & 0x03) { + return -4; + } + + g_dwc2_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_dwc2_udc.in_ep[ep_idx].xfer_len = data_len; + g_dwc2_udc.in_ep[ep_idx].actual_xfer_len = 0; + + USB_OTG_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); + USB_OTG_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); + + if (data_len == 0) { + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USB_OTG_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + return 0; + } + + if (ep_idx == 0) { + if (data_len > g_dwc2_udc.in_ep[ep_idx].ep_mps) { + data_len = g_dwc2_udc.in_ep[ep_idx].ep_mps; + } + g_dwc2_udc.in_ep[ep_idx].xfer_len = data_len; + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len); + } else { + pktcnt = (uint16_t)((data_len + g_dwc2_udc.in_ep[ep_idx].ep_mps - 1U) / g_dwc2_udc.in_ep[ep_idx].ep_mps); + + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (pktcnt << 19)); + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & data_len); + } + + if (g_dwc2_udc.in_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if ((USB_OTG_DEV->DSTS & (1U << 8)) == 0U) { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } else { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SODDFRM; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + } + USB_OTG_INEP(ep_idx)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); + USB_OTG_INEP(ep_idx)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); + } + +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + USB_OTG_INEP(ep_idx)->DIEPDMA = (uint32_t)data; + + USB_OTG_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); +#else + USB_OTG_INEP(ep_idx)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); + /* Enable the Tx FIFO Empty Interrupt for this EP */ + if (data_len > 0U) { + USB_OTG_DEV->DIEPEMPMSK |= 1UL << (ep_idx & 0x0f); + } +#endif + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint32_t pktcnt = 0; + + if (!data && data_len) { + return -1; + } +#if 0 /* some chips have confused with this, so disable as default */ + if (USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) { + return -2; + } +#endif + if (ep_idx && !(USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_MPSIZ)) { + return -3; + } + if (((uint32_t)data) & 0x03) { + return -4; + } + + g_dwc2_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_dwc2_udc.out_ep[ep_idx].xfer_len = data_len; + g_dwc2_udc.out_ep[ep_idx].actual_xfer_len = 0; + + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); + if (data_len == 0) { + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)); + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & g_dwc2_udc.out_ep[ep_idx].ep_mps); + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + return 0; + } + + if (ep_idx == 0) { + if (data_len > g_dwc2_udc.out_ep[ep_idx].ep_mps) { + data_len = g_dwc2_udc.out_ep[ep_idx].ep_mps; + } + g_dwc2_udc.out_ep[ep_idx].xfer_len = data_len; + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & data_len); + } else { + pktcnt = (uint16_t)((data_len + g_dwc2_udc.out_ep[ep_idx].ep_mps - 1U) / g_dwc2_udc.out_ep[ep_idx].ep_mps); + + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19)); + USB_OTG_OUTEP(ep_idx)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & data_len); + } + +#ifdef CONFIG_USB_DWC2_DMA_ENABLE + USB_OTG_OUTEP(ep_idx)->DOEPDMA = (uint32_t)data; +#endif + if (g_dwc2_udc.out_ep[ep_idx].ep_type == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + if ((USB_OTG_DEV->DSTS & (1U << 8)) == 0U) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } else { + USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_SODDFRM; + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + } + } + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t gint_status, temp, ep_idx, ep_intr, epint, read_count, daintmask; + gint_status = dwc2_get_glb_intstatus(); + + if ((USB_OTG_GLB->GINTSTS & 0x1U) == USB_OTG_MODE_DEVICE) { + /* Avoid spurious interrupt */ + if (gint_status == 0) { + return; + } + +#ifndef CONFIG_USB_DWC2_DMA_ENABLE + /* Handle RxQLevel Interrupt */ + if (gint_status & USB_OTG_GINTSTS_RXFLVL) { + USB_MASK_INTERRUPT(USB_OTG_GLB, USB_OTG_GINTSTS_RXFLVL); + + temp = USB_OTG_GLB->GRXSTSP; + ep_idx = temp & USB_OTG_GRXSTSP_EPNUM; + + if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> USB_OTG_GRXSTSP_PKTSTS_Pos) == STS_DATA_UPDT) { + read_count = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + if (read_count != 0) { + dwc2_ep_read(g_dwc2_udc.out_ep[ep_idx].xfer_buf, read_count); + g_dwc2_udc.out_ep[ep_idx].xfer_buf += read_count; + } + } else if (((temp & USB_OTG_GRXSTSP_PKTSTS) >> USB_OTG_GRXSTSP_PKTSTS_Pos) == STS_SETUP_UPDT) { + read_count = (temp & USB_OTG_GRXSTSP_BCNT) >> 4; + dwc2_ep_read((uint8_t *)&g_dwc2_udc.setup, read_count); + } else { + /* ... */ + } + USB_UNMASK_INTERRUPT(USB_OTG_GLB, USB_OTG_GINTSTS_RXFLVL); + } +#endif + if (gint_status & USB_OTG_GINTSTS_OEPINT) { + ep_idx = 0; + ep_intr = dwc2_get_outeps_intstatus(); + while (ep_intr != 0U) { + if ((ep_intr & 0x1U) != 0U) { + epint = dwc2_get_outep_intstatus(ep_idx); + uint32_t DoepintReg = USB_OTG_OUTEP(ep_idx)->DOEPINT; + USB_OTG_OUTEP(ep_idx)->DOEPINT = DoepintReg; + + if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) { + if (ep_idx == 0) { + if (g_dwc2_udc.out_ep[ep_idx].xfer_len == 0) { + /* Out status, start reading setup */ + dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup); + } else { + g_dwc2_udc.out_ep[ep_idx].actual_xfer_len = g_dwc2_udc.out_ep[ep_idx].xfer_len - ((USB_OTG_OUTEP(ep_idx)->DOEPTSIZ) & USB_OTG_DOEPTSIZ_XFRSIZ); + g_dwc2_udc.out_ep[ep_idx].xfer_len = 0; + usbd_event_ep_out_complete_handler(0, 0x00, g_dwc2_udc.out_ep[ep_idx].actual_xfer_len); + } + } else { + g_dwc2_udc.out_ep[ep_idx].actual_xfer_len = g_dwc2_udc.out_ep[ep_idx].xfer_len - ((USB_OTG_OUTEP(ep_idx)->DOEPTSIZ) & USB_OTG_DOEPTSIZ_XFRSIZ); + g_dwc2_udc.out_ep[ep_idx].xfer_len = 0; + usbd_event_ep_out_complete_handler(0, ep_idx, g_dwc2_udc.out_ep[ep_idx].actual_xfer_len); + } + } + + if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) { + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_dwc2_udc.setup); + } + } + ep_intr >>= 1U; + ep_idx++; + } + } + if (gint_status & USB_OTG_GINTSTS_IEPINT) { + ep_idx = 0U; + ep_intr = dwc2_get_ineps_intstatus(); + while (ep_intr != 0U) { + if ((ep_intr & 0x1U) != 0U) { + epint = dwc2_get_inep_intstatus(ep_idx); + uint32_t DiepintReg = USB_OTG_INEP(ep_idx)->DIEPINT; + USB_OTG_INEP(ep_idx)->DIEPINT = DiepintReg; + + if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) { + if (ep_idx == 0) { + g_dwc2_udc.in_ep[ep_idx].actual_xfer_len = g_dwc2_udc.in_ep[ep_idx].xfer_len - ((USB_OTG_INEP(ep_idx)->DIEPTSIZ) & USB_OTG_DIEPTSIZ_XFRSIZ); + g_dwc2_udc.in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, 0x80, g_dwc2_udc.in_ep[ep_idx].actual_xfer_len); + + if (g_dwc2_udc.setup.wLength && ((g_dwc2_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + /* In status, start reading setup */ + dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup); + } else if (g_dwc2_udc.setup.wLength == 0) { + /* In status, start reading setup */ + dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup); + } + } else { + g_dwc2_udc.in_ep[ep_idx].actual_xfer_len = g_dwc2_udc.in_ep[ep_idx].xfer_len - ((USB_OTG_INEP(ep_idx)->DIEPTSIZ) & USB_OTG_DIEPTSIZ_XFRSIZ); + g_dwc2_udc.in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_dwc2_udc.in_ep[ep_idx].actual_xfer_len); + } + } + if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) { + dwc2_tx_fifo_empty_procecss(ep_idx); + } + } + ep_intr >>= 1U; + ep_idx++; + } + } + if (gint_status & USB_OTG_GINTSTS_USBRST) { + USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_USBRST; + USB_OTG_DEV->DCTL &= ~USB_OTG_DCTL_RWUSIG; + + dwc2_flush_txfifo(0x10U); + dwc2_flush_rxfifo(); + + for (uint8_t i = 0U; i < CONFIG_USBDEV_EP_NUM; i++) { + if (i == 0U) { + USB_OTG_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; + USB_OTG_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; + } else { + if (USB_OTG_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) { + USB_OTG_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK); + } else { + USB_OTG_INEP(i)->DIEPCTL = 0; + } + if (USB_OTG_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) { + USB_OTG_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK); + } else { + USB_OTG_OUTEP(i)->DOEPCTL = 0; + } + } + USB_OTG_INEP(i)->DIEPTSIZ = 0U; + USB_OTG_INEP(i)->DIEPINT = 0xFBFFU; + USB_OTG_OUTEP(i)->DOEPTSIZ = 0U; + USB_OTG_OUTEP(i)->DOEPINT = 0xFBFFU; + } + + USB_OTG_DEV->DAINTMSK |= 0x10001U; + + USB_OTG_DEV->DOEPMSK = USB_OTG_DOEPMSK_STUPM | + USB_OTG_DOEPMSK_XFRCM; + + USB_OTG_DEV->DIEPMSK = USB_OTG_DIEPMSK_XFRCM; + + memset(&g_dwc2_udc, 0, sizeof(struct dwc2_udc)); + usbd_event_reset_handler(0); + /* Start reading setup */ + dwc2_ep0_start_read_setup((uint8_t *)&g_dwc2_udc.setup); + } + if (gint_status & USB_OTG_GINTSTS_ENUMDNE) { + USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_ENUMDNE; + dwc2_set_turnaroundtime(SystemCoreClock, dwc2_get_devspeed()); + + USB_OTG_DEV->DCTL |= USB_OTG_DCTL_CGINAK; + } + if (gint_status & USB_OTG_GINTSTS_PXFR_INCOMPISOOUT) { + daintmask = USB_OTG_DEV->DAINTMSK; + daintmask >>= 16; + + for (ep_idx = 1; ep_idx < CONFIG_USBDEV_EP_NUM; ep_idx++) { + if ((BIT(ep_idx) & ~daintmask) || (g_dwc2_udc.out_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS)) + continue; + if (!(USB_OTG_OUTEP(ep_idx)->DOEPCTL & USB_OTG_DOEPCTL_USBAEP)) + continue; + + if ((USB_OTG_DEV->DSTS & (1U << 8)) != 0U) { + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_SODDFRM; + } else { + USB_OTG_OUTEP(ep_idx)->DOEPCTL &= ~USB_OTG_DOEPCTL_SD0PID_SEVNFRM; + USB_OTG_OUTEP(ep_idx)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; + } + } + + USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_PXFR_INCOMPISOOUT; + } + + if (gint_status & USB_OTG_GINTSTS_IISOIXFR) { + daintmask = USB_OTG_DEV->DAINTMSK; + daintmask >>= 16; + + for (ep_idx = 1; ep_idx < CONFIG_USBDEV_EP_NUM; ep_idx++) { + if (((BIT(ep_idx) & ~daintmask)) || (g_dwc2_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS)) + continue; + + if (!(USB_OTG_INEP(ep_idx)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP)) + continue; + + if ((USB_OTG_DEV->DSTS & (1U << 8)) != 0U) { + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SODDFRM; + } else { + USB_OTG_INEP(ep_idx)->DIEPCTL &= ~USB_OTG_DIEPCTL_SD0PID_SEVNFRM; + USB_OTG_INEP(ep_idx)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; + } + } + USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_IISOIXFR; + } + + if (gint_status & USB_OTG_GINTSTS_SOF) { + USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_SOF; + } + if (gint_status & USB_OTG_GINTSTS_USBSUSP) { + USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_USBSUSP; + } + if (gint_status & USB_OTG_GINTSTS_WKUINT) { + USB_OTG_GLB->GINTSTS |= USB_OTG_GINTSTS_WKUINT; + } + if (gint_status & USB_OTG_GINTSTS_OTGINT) { + temp = USB_OTG_GLB->GOTGINT; + if ((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) { + } else { + } + USB_OTG_GLB->GOTGINT |= temp; + } + } +} diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h b/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h new file mode 100644 index 00000000000..c3bd75d6644 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_dwc2_reg.h @@ -0,0 +1,1721 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __USB_DWC2_REG_H__ +#define __USB_DWC2_REG_H__ + +#define __IO volatile /*!< Defines 'read / write' permissions */ +/** + * @brief USB_OTG_Core_Registers + */ +typedef struct +{ + __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */ + __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */ + __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */ + __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */ + __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */ + __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */ + __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */ + __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */ + __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */ + __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */ + __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */ + __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */ + uint32_t Reserved30[2]; /*!< Reserved 030h */ + __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */ + __IO uint32_t CID; /*!< User ID Register 03Ch */ + __IO uint32_t GSNPSID; /*!< USB_OTG core ID 040h */ + __IO uint32_t GHWCFG1; /*!< User HW config1 044h */ + __IO uint32_t GHWCFG2; /*!< User HW config2 048h */ + __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */ + __IO uint32_t GHWCFG4; /*!< User HW config4 050h */ + __IO uint32_t GLPMCFG; /*!< LPM Register 054h */ + __IO uint32_t GPWRDN; /*!< Power Down Register 058h */ + __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */ + __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */ + uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */ + __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */ + __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */ +} DWC2_GlobalTypeDef; + +/** + * @brief USB_OTG_device_Registers + */ +typedef struct +{ + __IO uint32_t DCFG; /*!< dev Configuration Register 800h */ + __IO uint32_t DCTL; /*!< dev Control Register 804h */ + __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */ + uint32_t Reserved0C; /*!< Reserved 80Ch */ + __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */ + __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */ + __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */ + __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */ + uint32_t Reserved20; /*!< Reserved 820h */ + uint32_t Reserved9; /*!< Reserved 824h */ + __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */ + __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */ + __IO uint32_t DTHRCTL; /*!< dev threshold 830h */ + __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */ + __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */ + __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */ + uint32_t Reserved40; /*!< dedicated EP mask 840h */ + __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */ + uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */ + __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */ +} DWC2_DeviceTypeDef; + +/** + * @brief USB_OTG_IN_Endpoint-Specific_Register + */ +typedef struct +{ + __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */ + __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */ + __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */ + __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */ + uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */ +} DWC2_INEndpointTypeDef; + +/** + * @brief USB_OTG_OUT_Endpoint-Specific_Registers + */ +typedef struct +{ + __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */ + uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */ + __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */ + uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */ + __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */ + __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */ + uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */ +} DWC2_OUTEndpointTypeDef; + +/** + * @brief USB_OTG_Host_Mode_Register_Structures + */ +typedef struct +{ + __IO uint32_t HCFG; /*!< Host Configuration Register 400h */ + __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */ + __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */ + uint32_t Reserved40C; /*!< Reserved 40Ch */ + __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */ + __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */ + __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */ + __IO uint32_t HFLBADDR; /*!< Host frame list base address register 41Ch */ + uint32_t Reserved420[8]; /*!< Reserved 420h */ + __IO uint32_t HPRT; /*!< Host port control and status register 440h */ +} DWC2_HostTypeDef; + +/** + * @brief USB_OTG_Host_Channel_Specific_Registers + */ +typedef struct +{ + __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */ + __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */ + __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */ + __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */ + __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */ + __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */ + uint32_t Reserved0; /*!< Reserved 518h */ + __IO uint32_t HCDMAB; /*!< Host Channel DMA Address Buffer Register 51Ch */ + uint32_t Reserved[2]; /*!< Reserved */ +} DWC2_HostChannelTypeDef; + +#define USB_OTG_GLOBAL_BASE 0x000UL +#define USB_OTG_DEVICE_BASE 0x800UL +#define USB_OTG_IN_ENDPOINT_BASE 0x900UL +#define USB_OTG_OUT_ENDPOINT_BASE 0xB00UL +#define USB_OTG_EP_REG_SIZE 0x20UL +#define USB_OTG_HOST_BASE 0x400UL +#define USB_OTG_HOST_PORT_BASE 0x440UL +#define USB_OTG_HOST_CHANNEL_BASE 0x500UL +#define USB_OTG_HOST_CHANNEL_SIZE 0x20UL +#define USB_OTG_PCGCCTL_BASE 0xE00UL +#define USB_OTG_FIFO_BASE 0x1000UL +#define USB_OTG_FIFO_SIZE 0x1000UL + +/******************************************************************************/ +/* */ +/* USB_OTG */ +/* */ +/******************************************************************************/ +/******************** Bit definition for USB_OTG_GOTGCTL register ***********/ +#define USB_OTG_GOTGCTL_SRQSCS_Pos (0U) +#define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */ +#define USB_OTG_GOTGCTL_SRQ_Pos (1U) +#define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */ +#define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */ +#define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U) +#define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */ +#define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U) +#define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */ +#define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */ +#define USB_OTG_GOTGCTL_AVALOEN_Pos (4U) +#define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */ +#define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U) +#define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */ +#define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */ +#define USB_OTG_GOTGCTL_BVALOEN_Pos (6U) +#define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */ +#define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U) +#define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */ +#define USB_OTG_GOTGCTL_HNGSCS_Pos (8U) +#define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_HNPRQ_Pos (9U) +#define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */ +#define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U) +#define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */ +#define USB_OTG_GOTGCTL_DHNPEN_Pos (11U) +#define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */ +#define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */ +#define USB_OTG_GOTGCTL_EHEN_Pos (12U) +#define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */ +#define USB_OTG_GOTGCTL_CIDSTS_Pos (16U) +#define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */ +#define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */ +#define USB_OTG_GOTGCTL_DBCT_Pos (17U) +#define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */ +#define USB_OTG_GOTGCTL_ASVLD_Pos (18U) +#define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */ +#define USB_OTG_GOTGCTL_BSESVLD_Pos (19U) +#define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */ +#define USB_OTG_GOTGCTL_OTGVER_Pos (20U) +#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */ +#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */ + +/******************** Bit definition forUSB_OTG_HCFG register ********************/ + +#define USB_OTG_HCFG_FSLSPCS_Pos (0U) +#define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */ +#define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */ +#define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCFG_FSLSS_Pos (2U) +#define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */ + +/******************** Bit definition for USB_OTG_DCFG register ********************/ + +#define USB_OTG_DCFG_DSPD_Pos (0U) +#define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */ +#define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */ +#define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCFG_NZLSOHSK_Pos (2U) +#define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */ + +#define USB_OTG_DCFG_DAD_Pos (4U) +#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */ +#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */ +#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */ + +#define USB_OTG_DCFG_PFIVL_Pos (11U) +#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */ +#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */ +#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */ + +#define USB_OTG_DCFG_XCVRDLY_Pos (14U) +#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */ +#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */ + +#define USB_OTG_DCFG_ERRATIM_Pos (15U) +#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */ +#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */ + +#define USB_OTG_DCFG_DESCDMA_Pos (23U) +#define USB_OTG_DCFG_DESCDMA_Msk (0x1UL << USB_OTG_DCFG_DESCDMA_Pos) +#define USB_OTG_DCFG_DESCDMA USB_OTG_DCFG_DESCDMA_Msk + +#define USB_OTG_DCFG_PERSCHIVL_Pos (24U) +#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */ +#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */ +#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */ +#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */ + +/******************** Bit definition for USB_OTG_PCGCR register ********************/ +#define USB_OTG_PCGCR_STPPCLK_Pos (0U) +#define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */ +#define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */ +#define USB_OTG_PCGCR_GATEHCLK_Pos (1U) +#define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */ +#define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */ +#define USB_OTG_PCGCR_PHYSUSP_Pos (4U) +#define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */ +#define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */ + +/******************** Bit definition for USB_OTG_GOTGINT register ********************/ +#define USB_OTG_GOTGINT_SEDET_Pos (2U) +#define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */ +#define USB_OTG_GOTGINT_SRSSCHG_Pos (8U) +#define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */ +#define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */ +#define USB_OTG_GOTGINT_HNSSCHG_Pos (9U) +#define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */ +#define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */ +#define USB_OTG_GOTGINT_HNGDET_Pos (17U) +#define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */ +#define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */ +#define USB_OTG_GOTGINT_ADTOCHG_Pos (18U) +#define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */ +#define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */ +#define USB_OTG_GOTGINT_DBCDNE_Pos (19U) +#define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */ +#define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */ + +/******************** Bit definition for USB_OTG_DCTL register ********************/ +#define USB_OTG_DCTL_RWUSIG_Pos (0U) +#define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */ +#define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */ +#define USB_OTG_DCTL_SDIS_Pos (1U) +#define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */ +#define USB_OTG_DCTL_GINSTS_Pos (2U) +#define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */ +#define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */ +#define USB_OTG_DCTL_GONSTS_Pos (3U) +#define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */ +#define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */ + +#define USB_OTG_DCTL_TCTL_Pos (4U) +#define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */ +#define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */ +#define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */ +#define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */ +#define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */ +#define USB_OTG_DCTL_SGINAK_Pos (7U) +#define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */ +#define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */ +#define USB_OTG_DCTL_CGINAK_Pos (8U) +#define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */ +#define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */ +#define USB_OTG_DCTL_SGONAK_Pos (9U) +#define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */ +#define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */ +#define USB_OTG_DCTL_CGONAK_Pos (10U) +#define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */ +#define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */ +#define USB_OTG_DCTL_POPRGDNE_Pos (11U) +#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */ +#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */ + +/******************** Bit definition for USB_OTG_HFIR register ********************/ +#define USB_OTG_HFIR_FRIVL_Pos (0U) +#define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */ + +/******************** Bit definition for USB_OTG_HFNUM register ********************/ +#define USB_OTG_HFNUM_FRNUM_Pos (0U) +#define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */ +#define USB_OTG_HFNUM_FTREM_Pos (16U) +#define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */ + +/******************** Bit definition for USB_OTG_DSTS register ********************/ +#define USB_OTG_DSTS_SUSPSTS_Pos (0U) +#define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */ + +#define USB_OTG_DSTS_ENUMSPD_Pos (1U) +#define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */ +#define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */ +#define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */ +#define USB_OTG_DSTS_EERR_Pos (3U) +#define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */ +#define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */ +#define USB_OTG_DSTS_FNSOF_Pos (8U) +#define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */ +#define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */ + +/******************** Bit definition for USB_OTG_GAHBCFG register ********************/ +#define USB_OTG_GAHBCFG_GINT_Pos (0U) +#define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */ +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */ +#define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U) +#define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */ +#define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */ +#define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */ +#define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */ +#define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */ +#define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */ +#define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */ +#define USB_OTG_GAHBCFG_DMAEN_Pos (5U) +#define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */ +#define USB_OTG_GAHBCFG_TXFELVL_Pos (7U) +#define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */ +#define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */ +#define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U) +#define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */ +#define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */ + +/******************** Bit definition for USB_OTG_GUSBCFG register ********************/ + +#define USB_OTG_GUSBCFG_TOCAL_Pos (0U) +#define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */ +#define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */ +#define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */ +#define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */ +#define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */ +#define USB_OTG_GUSBCFG_PHYSEL_Pos (6U) +#define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */ +#define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */ +#define USB_OTG_GUSBCFG_SRPCAP_Pos (8U) +#define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */ +#define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */ +#define USB_OTG_GUSBCFG_HNPCAP_Pos (9U) +#define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */ +#define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */ +#define USB_OTG_GUSBCFG_TRDT_Pos (10U) +#define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */ +#define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */ +#define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */ +#define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */ +#define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */ +#define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */ +#define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U) +#define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */ +#define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U) +#define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */ +#define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */ +#define USB_OTG_GUSBCFG_ULPIAR_Pos (18U) +#define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */ +#define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */ +#define USB_OTG_GUSBCFG_ULPICSM_Pos (19U) +#define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */ +#define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U) +#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U) +#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */ +#define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */ +#define USB_OTG_GUSBCFG_TSDPS_Pos (22U) +#define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */ +#define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */ +#define USB_OTG_GUSBCFG_PCCI_Pos (23U) +#define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */ +#define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */ +#define USB_OTG_GUSBCFG_PTCI_Pos (24U) +#define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */ +#define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */ +#define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U) +#define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */ +#define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */ +#define USB_OTG_GUSBCFG_FHMOD_Pos (29U) +#define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */ +#define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */ +#define USB_OTG_GUSBCFG_FDMOD_Pos (30U) +#define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */ +#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */ +#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U) +#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */ + +/******************** Bit definition for USB_OTG_GRSTCTL register ********************/ +#define USB_OTG_GRSTCTL_CSRST_Pos (0U) +#define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */ +#define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */ +#define USB_OTG_GRSTCTL_HSRST_Pos (1U) +#define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */ +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */ +#define USB_OTG_GRSTCTL_FCRST_Pos (2U) +#define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */ +#define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */ +#define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U) +#define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */ +#define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */ +#define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U) +#define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */ +#define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */ + + +#define USB_OTG_GRSTCTL_TXFNUM_Pos (6U) +#define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */ +#define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */ +#define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */ +#define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GRSTCTL_DMAREQ_Pos (30U) +#define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */ +#define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */ +#define USB_OTG_GRSTCTL_AHBIDL_Pos (31U) +#define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */ +#define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */ + +/******************** Bit definition for USB_OTG_DIEPMSK register ********************/ +#define USB_OTG_DIEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPMSK_EPDM_Pos (1U) +#define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPMSK_TOM_Pos (3U) +#define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPMSK_INEPNMM_Pos (5U) +#define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPMSK_INEPNEM_Pos (6U) +#define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPMSK_TXFURM_Pos (8U) +#define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPMSK_BIM_Pos (9U) +#define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXSTS register ********************/ +#define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U) +#define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U) +#define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */ +#define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U) +#define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */ +#define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */ +#define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */ + +/******************** Bit definition for USB_OTG_HAINT register ********************/ +#define USB_OTG_HAINT_HAINT_Pos (0U) +#define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */ + +/******************** Bit definition for USB_OTG_DOEPMSK register ********************/ +#define USB_OTG_DOEPMSK_XFRCM_Pos (0U) +#define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPMSK_EPDM_Pos (1U) +#define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPMSK_AHBERRM_Pos (2U) +#define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */ +#define USB_OTG_DOEPMSK_STUPM_Pos (3U) +#define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */ +#define USB_OTG_DOEPMSK_OTEPDM_Pos (4U) +#define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */ +#define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U) +#define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */ +#define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U) +#define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */ +#define USB_OTG_DOEPMSK_OPEM_Pos (8U) +#define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPMSK_BOIM_Pos (9U) +#define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPMSK_BERRM_Pos (12U) +#define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */ +#define USB_OTG_DOEPMSK_NAKM_Pos (13U) +#define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */ +#define USB_OTG_DOEPMSK_NYETM_Pos (14U) +#define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */ +/******************** Bit definition for USB_OTG_GINTSTS register ********************/ +#define USB_OTG_GINTSTS_CMOD_Pos (0U) +#define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */ +#define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */ +#define USB_OTG_GINTSTS_MMIS_Pos (1U) +#define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */ +#define USB_OTG_GINTSTS_OTGINT_Pos (2U) +#define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */ +#define USB_OTG_GINTSTS_SOF_Pos (3U) +#define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */ +#define USB_OTG_GINTSTS_RXFLVL_Pos (4U) +#define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */ +#define USB_OTG_GINTSTS_NPTXFE_Pos (5U) +#define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */ +#define USB_OTG_GINTSTS_GINAKEFF_Pos (6U) +#define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */ +#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U) +#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */ +#define USB_OTG_GINTSTS_ESUSP_Pos (10U) +#define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */ +#define USB_OTG_GINTSTS_USBSUSP_Pos (11U) +#define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */ +#define USB_OTG_GINTSTS_USBRST_Pos (12U) +#define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */ +#define USB_OTG_GINTSTS_ENUMDNE_Pos (13U) +#define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */ +#define USB_OTG_GINTSTS_ISOODRP_Pos (14U) +#define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */ +#define USB_OTG_GINTSTS_EOPF_Pos (15U) +#define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */ +#define USB_OTG_GINTSTS_IEPINT_Pos (18U) +#define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */ +#define USB_OTG_GINTSTS_OEPINT_Pos (19U) +#define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */ +#define USB_OTG_GINTSTS_IISOIXFR_Pos (20U) +#define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U) +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */ +#define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U) +#define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */ +#define USB_OTG_GINTSTS_RSTDET_Pos (23U) +#define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */ +#define USB_OTG_GINTSTS_HPRTINT_Pos (24U) +#define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */ +#define USB_OTG_GINTSTS_HCINT_Pos (25U) +#define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */ +#define USB_OTG_GINTSTS_PTXFE_Pos (26U) +#define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */ +#define USB_OTG_GINTSTS_LPMINT_Pos (27U) +#define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */ +#define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */ +#define USB_OTG_GINTSTS_CIDSCHG_Pos (28U) +#define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */ +#define USB_OTG_GINTSTS_DISCINT_Pos (29U) +#define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */ +#define USB_OTG_GINTSTS_SRQINT_Pos (30U) +#define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */ +#define USB_OTG_GINTSTS_WKUINT_Pos (31U) +#define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */ + +/******************** Bit definition for USB_OTG_GINTMSK register ********************/ +#define USB_OTG_GINTMSK_MMISM_Pos (1U) +#define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */ +#define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */ +#define USB_OTG_GINTMSK_OTGINT_Pos (2U) +#define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */ +#define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */ +#define USB_OTG_GINTMSK_SOFM_Pos (3U) +#define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */ +#define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */ +#define USB_OTG_GINTMSK_RXFLVLM_Pos (4U) +#define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */ +#define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */ +#define USB_OTG_GINTMSK_NPTXFEM_Pos (5U) +#define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */ +#define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U) +#define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */ +#define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */ +#define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U) +#define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */ +#define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */ +#define USB_OTG_GINTMSK_ESUSPM_Pos (10U) +#define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */ +#define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */ +#define USB_OTG_GINTMSK_USBSUSPM_Pos (11U) +#define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */ +#define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */ +#define USB_OTG_GINTMSK_USBRST_Pos (12U) +#define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */ +#define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */ +#define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U) +#define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */ +#define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */ +#define USB_OTG_GINTMSK_ISOODRPM_Pos (14U) +#define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */ +#define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */ +#define USB_OTG_GINTMSK_EOPFM_Pos (15U) +#define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */ +#define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */ +#define USB_OTG_GINTMSK_EPMISM_Pos (17U) +#define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */ +#define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */ +#define USB_OTG_GINTMSK_IEPINT_Pos (18U) +#define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */ +#define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */ +#define USB_OTG_GINTMSK_OEPINT_Pos (19U) +#define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */ +#define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */ +#define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U) +#define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */ +#define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U) +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */ +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */ +#define USB_OTG_GINTMSK_FSUSPM_Pos (22U) +#define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */ +#define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */ +#define USB_OTG_GINTMSK_RSTDEM_Pos (23U) +#define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */ +#define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */ +#define USB_OTG_GINTMSK_PRTIM_Pos (24U) +#define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */ +#define USB_OTG_GINTMSK_HCIM_Pos (25U) +#define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */ +#define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */ +#define USB_OTG_GINTMSK_PTXFEM_Pos (26U) +#define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */ +#define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */ +#define USB_OTG_GINTMSK_LPMINTM_Pos (27U) +#define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */ +#define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */ +#define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U) +#define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */ +#define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */ +#define USB_OTG_GINTMSK_DISCINT_Pos (29U) +#define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */ +#define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */ +#define USB_OTG_GINTMSK_SRQIM_Pos (30U) +#define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */ +#define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */ +#define USB_OTG_GINTMSK_WUIM_Pos (31U) +#define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */ +#define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */ + +/******************** Bit definition for USB_OTG_DAINT register ********************/ +#define USB_OTG_DAINT_IEPINT_Pos (0U) +#define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */ +#define USB_OTG_DAINT_OEPINT_Pos (16U) +#define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */ + +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ + +/******************** Bit definition for USB_OTG_HAINTMSK register ********************/ +#define USB_OTG_HAINTMSK_HAINTM_Pos (0U) +#define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */ + +/******************** Bit definition for USB_OTG_GRXSTSP register ********************/ +#define USB_OTG_GRXSTSP_EPNUM_Pos (0U) +#define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_BCNT_Pos (4U) +#define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_DPID_Pos (15U) +#define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */ +#define USB_OTG_GRXSTSP_PKTSTS_Pos (17U) +#define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DAINTMSK register ********************/ +#define USB_OTG_DAINTMSK_IEPM_Pos (0U) +#define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */ +#define USB_OTG_DAINTMSK_OEPM_Pos (16U) +#define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ + +/******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ +#define USB_OTG_GRXFSIZ_RXFD_Pos (0U) +#define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */ + +/******************** Bit definition for USB_OTG_DVBUSDIS register ********************/ +#define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U) +#define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */ + +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_NPTXFSA_Pos (0U) +#define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */ +#define USB_OTG_NPTXFD_Pos (16U) +#define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */ +#define USB_OTG_TX0FSA_Pos (0U) +#define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */ +#define USB_OTG_TX0FD_Pos (16U) +#define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */ + +/******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/ +#define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U) +#define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */ +#define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */ + +/******************** Bit definition for USB_OTG_GNPTXSTS register ********************/ +#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U) +#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */ + +#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U) +#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */ +#define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */ + +#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U) +#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */ +#define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DTHRCTL register ********************/ +#define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U) +#define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */ +#define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */ +#define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U) +#define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */ +#define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */ + +#define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U) +#define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */ +#define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */ +#define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */ +#define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */ +#define USB_OTG_DTHRCTL_RXTHREN_Pos (16U) +#define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */ +#define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */ + +#define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U) +#define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */ +#define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */ +#define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */ +#define USB_OTG_DTHRCTL_ARPEN_Pos (27U) +#define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */ +#define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */ + +/******************** Bit definition for USB_OTG_DIEPEMPMSK register ********************/ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U) +#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */ + +/******************** Bit definition for USB_OTG_DEACHINT register ********************/ +#define USB_OTG_DEACHINT_IEP1INT_Pos (1U) +#define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */ +#define USB_OTG_DEACHINT_OEP1INT_Pos (17U) +#define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */ + +/******************** Bit definition for USB_OTG_GCCFG register ********************/ +#define USB_OTG_GCCFG_DCDET_Pos (0U) +#define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */ +#define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */ +#define USB_OTG_GCCFG_PDET_Pos (1U) +#define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */ +#define USB_OTG_GCCFG_SDET_Pos (2U) +#define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */ +#define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */ +#define USB_OTG_GCCFG_PS2DET_Pos (3U) +#define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */ +#define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */ +#define USB_OTG_GCCFG_PWRDWN_Pos (16U) +#define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */ +#define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */ +#define USB_OTG_GCCFG_BCDEN_Pos (17U) +#define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */ +#define USB_OTG_GCCFG_DCDEN_Pos (18U) +#define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/ +#define USB_OTG_GCCFG_PDEN_Pos (19U) +#define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/ +#define USB_OTG_GCCFG_SDEN_Pos (20U) +#define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */ +#define USB_OTG_GCCFG_VBDEN_Pos (21U) +#define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */ +#define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */ + +#define USB_OTG_GCCFG_I2CPADEN_Pos (17U) +#define USB_OTG_GCCFG_I2CPADEN_Msk (0x1UL << USB_OTG_GCCFG_I2CPADEN_Pos) /*!< 0x00020000 */ +#define USB_OTG_GCCFG_I2CPADEN USB_OTG_GCCFG_I2CPADEN_Msk /*!< Enable I2C bus connection for the external I2C PHY interface*/ +#define USB_OTG_GCCFG_VBUSASEN_Pos (18U) +#define USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos) /*!< 0x00040000 */ +#define USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_VBUSBSEN_Pos (19U) +#define USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos) /*!< 0x00080000 */ +#define USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk /*!< Enable the VBUS sensing device */ +#define USB_OTG_GCCFG_SOFOUTEN_Pos (20U) +#define USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos) /*!< 0x00100000 */ +#define USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk /*!< SOF output enable */ +#define USB_OTG_GCCFG_NOVBUSSENS_Pos (21U) +#define USB_OTG_GCCFG_NOVBUSSENS_Msk (0x1UL << USB_OTG_GCCFG_NOVBUSSENS_Pos) /*!< 0x00200000 */ +#define USB_OTG_GCCFG_NOVBUSSENS USB_OTG_GCCFG_NOVBUSSENS_Msk /*!< VBUS sensing disable option*/ + +/******************** Bit definition forUSB_OTG_GPWRDN) register ********************/ +#define USB_OTG_GPWRDN_ADPMEN_Pos (0U) +#define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */ +#define USB_OTG_GPWRDN_ADPIF_Pos (23U) +#define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */ +#define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */ + +/******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/ +#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U) +#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */ +#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U) +#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */ +#define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */ + +/******************** Bit definition for USB_OTG_CID register ********************/ +#define USB_OTG_CID_PRODUCT_ID_Pos (0U) +#define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */ + +/******************** Bit definition for USB_OTG_GLPMCFG register ********************/ +#define USB_OTG_GLPMCFG_LPMEN_Pos (0U) +#define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */ +#define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */ +#define USB_OTG_GLPMCFG_LPMACK_Pos (1U) +#define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */ +#define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */ +#define USB_OTG_GLPMCFG_BESL_Pos (2U) +#define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */ +#define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_REMWAKE_Pos (6U) +#define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */ +#define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */ +#define USB_OTG_GLPMCFG_L1SSEN_Pos (7U) +#define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */ +#define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */ +#define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U) +#define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */ +#define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */ +#define USB_OTG_GLPMCFG_L1DSEN_Pos (12U) +#define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */ +#define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */ +#define USB_OTG_GLPMCFG_LPMRSP_Pos (13U) +#define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */ +#define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */ +#define USB_OTG_GLPMCFG_SLPSTS_Pos (15U) +#define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */ +#define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */ +#define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U) +#define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */ +#define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */ +#define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U) +#define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */ +#define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */ +#define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U) +#define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */ +#define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */ +#define USB_OTG_GLPMCFG_SNDLPM_Pos (24U) +#define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */ +#define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U) +#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */ +#define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */ +#define USB_OTG_GLPMCFG_ENBESL_Pos (28U) +#define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */ +#define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */ + +/******************** Bit definition for USB_OTG_DIEPEACHMSK1 register ********************/ +#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */ +#define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ + +/******************** Bit definition for USB_OTG_HPRT register ********************/ +#define USB_OTG_HPRT_PCSTS_Pos (0U) +#define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */ +#define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */ +#define USB_OTG_HPRT_PCDET_Pos (1U) +#define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */ +#define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */ +#define USB_OTG_HPRT_PENA_Pos (2U) +#define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */ +#define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */ +#define USB_OTG_HPRT_PENCHNG_Pos (3U) +#define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */ +#define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */ +#define USB_OTG_HPRT_POCA_Pos (4U) +#define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */ +#define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */ +#define USB_OTG_HPRT_POCCHNG_Pos (5U) +#define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */ +#define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */ +#define USB_OTG_HPRT_PRES_Pos (6U) +#define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */ +#define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */ +#define USB_OTG_HPRT_PSUSP_Pos (7U) +#define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */ +#define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */ +#define USB_OTG_HPRT_PRST_Pos (8U) +#define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */ +#define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */ + +#define USB_OTG_HPRT_PLSTS_Pos (10U) +#define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */ +#define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */ +#define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */ +#define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_HPRT_PPWR_Pos (12U) +#define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */ + +#define USB_OTG_HPRT_PTCTL_Pos (13U) +#define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */ +#define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */ +#define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */ +#define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */ +#define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */ +#define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */ + +#define USB_OTG_HPRT_PSPD_Pos (17U) +#define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */ +#define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */ +#define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */ +#define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */ + +/******************** Bit definition for USB_OTG_DOEPEACHMSK1 register ********************/ +#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U) +#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U) +#define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */ +#define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U) +#define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */ +#define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U) +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */ +#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U) +#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */ +#define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U) +#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */ +#define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */ +#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U) +#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */ +#define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */ +#define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U) +#define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */ +#define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U) +#define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */ +#define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U) +#define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */ +#define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */ +#define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U) +#define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */ +#define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */ + +/******************** Bit definition for USB_OTG_HPTXFSIZ register ********************/ +#define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U) +#define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */ +#define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U) +#define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DIEPCTL register ********************/ +#define USB_OTG_DIEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */ +#define USB_OTG_DIEPCTL_USBAEP_Pos (15U) +#define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */ +#define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */ +#define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U) +#define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */ +#define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */ +#define USB_OTG_DIEPCTL_NAKSTS_Pos (17U) +#define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */ + +#define USB_OTG_DIEPCTL_EPTYP_Pos (18U) +#define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */ +#define USB_OTG_DIEPCTL_STALL_Pos (21U) +#define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */ +#define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */ + +#define USB_OTG_DIEPCTL_TXFNUM_Pos (22U) +#define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */ +#define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */ +#define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */ +#define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */ +#define USB_OTG_DIEPCTL_CNAK_Pos (26U) +#define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */ +#define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */ +#define USB_OTG_DIEPCTL_SNAK_Pos (27U) +#define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */ +#define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U) +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */ +#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */ +#define USB_OTG_DIEPCTL_SODDFRM_Pos (29U) +#define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */ +#define USB_OTG_DIEPCTL_EPDIS_Pos (30U) +#define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */ +#define USB_OTG_DIEPCTL_EPENA_Pos (31U) +#define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */ + +/******************** Bit definition for USB_OTG_HCCHAR register ********************/ +#define USB_OTG_HCCHAR_MPSIZ_Pos (0U) +#define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */ + +#define USB_OTG_HCCHAR_EPNUM_Pos (11U) +#define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */ +#define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */ +#define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCCHAR_EPDIR_Pos (15U) +#define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */ +#define USB_OTG_HCCHAR_LSDEV_Pos (17U) +#define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */ +#define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */ + +#define USB_OTG_HCCHAR_EPTYP_Pos (18U) +#define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */ +#define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */ +#define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */ +#define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */ + +#define USB_OTG_HCCHAR_MC_Pos (20U) +#define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */ +#define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */ +#define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */ + +#define USB_OTG_HCCHAR_DAD_Pos (22U) +#define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */ +#define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */ +#define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */ +#define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */ +#define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */ +#define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */ +#define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */ +#define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */ +#define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */ +#define USB_OTG_HCCHAR_ODDFRM_Pos (29U) +#define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */ +#define USB_OTG_HCCHAR_CHDIS_Pos (30U) +#define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */ +#define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */ +#define USB_OTG_HCCHAR_CHENA_Pos (31U) +#define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */ + +/******************** Bit definition for USB_OTG_HCSPLT register ********************/ + +#define USB_OTG_HCSPLT_PRTADDR_Pos (0U) +#define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */ +#define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */ +#define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */ + +#define USB_OTG_HCSPLT_HUBADDR_Pos (7U) +#define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */ +#define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */ +#define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */ +#define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */ +#define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */ + +#define USB_OTG_HCSPLT_XACTPOS_Pos (14U) +#define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */ +#define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */ +#define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */ +#define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */ +#define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U) +#define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */ +#define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */ +#define USB_OTG_HCSPLT_SPLITEN_Pos (31U) +#define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */ + +/******************** Bit definition for USB_OTG_HCINT register ********************/ +#define USB_OTG_HCINT_XFRC_Pos (0U) +#define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */ +#define USB_OTG_HCINT_CHH_Pos (1U) +#define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */ +#define USB_OTG_HCINT_AHBERR_Pos (2U) +#define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINT_STALL_Pos (3U) +#define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */ +#define USB_OTG_HCINT_NAK_Pos (4U) +#define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */ +#define USB_OTG_HCINT_ACK_Pos (5U) +#define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */ +#define USB_OTG_HCINT_NYET_Pos (6U) +#define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */ +#define USB_OTG_HCINT_TXERR_Pos (7U) +#define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */ +#define USB_OTG_HCINT_BBERR_Pos (8U) +#define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */ +#define USB_OTG_HCINT_FRMOR_Pos (9U) +#define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */ +#define USB_OTG_HCINT_DTERR_Pos (10U) +#define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */ + +/******************** Bit definition for USB_OTG_DIEPINT register ********************/ +#define USB_OTG_DIEPINT_XFRC_Pos (0U) +#define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */ +#define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */ +#define USB_OTG_DIEPINT_EPDISD_Pos (1U) +#define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */ +#define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */ +#define USB_OTG_DIEPINT_AHBERR_Pos (2U) +#define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */ +#define USB_OTG_DIEPINT_TOC_Pos (3U) +#define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */ +#define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */ +#define USB_OTG_DIEPINT_ITTXFE_Pos (4U) +#define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */ +#define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */ +#define USB_OTG_DIEPINT_INEPNM_Pos (5U) +#define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000004 */ +#define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */ +#define USB_OTG_DIEPINT_INEPNE_Pos (6U) +#define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */ +#define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */ +#define USB_OTG_DIEPINT_TXFE_Pos (7U) +#define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */ +#define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */ +#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U) +#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */ +#define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */ +#define USB_OTG_DIEPINT_BNA_Pos (9U) +#define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */ +#define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */ +#define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U) +#define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */ +#define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */ +#define USB_OTG_DIEPINT_BERR_Pos (12U) +#define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */ +#define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */ +#define USB_OTG_DIEPINT_NAK_Pos (13U) +#define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */ +#define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */ + +/******************** Bit definition forUSB_OTG_HCINTMSK register ********************/ +#define USB_OTG_HCINTMSK_XFRCM_Pos (0U) +#define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */ +#define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */ +#define USB_OTG_HCINTMSK_CHHM_Pos (1U) +#define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */ +#define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */ +#define USB_OTG_HCINTMSK_AHBERR_Pos (2U) +#define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */ +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */ +#define USB_OTG_HCINTMSK_STALLM_Pos (3U) +#define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */ +#define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */ +#define USB_OTG_HCINTMSK_NAKM_Pos (4U) +#define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */ +#define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */ +#define USB_OTG_HCINTMSK_ACKM_Pos (5U) +#define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */ +#define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */ +#define USB_OTG_HCINTMSK_NYET_Pos (6U) +#define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */ +#define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */ +#define USB_OTG_HCINTMSK_TXERRM_Pos (7U) +#define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */ +#define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */ +#define USB_OTG_HCINTMSK_BBERRM_Pos (8U) +#define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */ +#define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */ +#define USB_OTG_HCINTMSK_FRMORM_Pos (9U) +#define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */ +#define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */ +#define USB_OTG_HCINTMSK_DTERRM_Pos (10U) +#define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */ +#define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */ + +/******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/ + +#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U) +#define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */ +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */ +/******************** Bit definition for USB_OTG_HCTSIZ register ********************/ +#define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U) +#define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */ +#define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */ +#define USB_OTG_HCTSIZ_PKTCNT_Pos (19U) +#define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */ +#define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */ +#define USB_OTG_HCTSIZ_DOPING_Pos (31U) +#define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */ +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */ +#define USB_OTG_HCTSIZ_DPID_Pos (29U) +#define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */ +#define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */ +#define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */ +#define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */ + +/******************** Bit definition for USB_OTG_DIEPDMA register ********************/ +#define USB_OTG_DIEPDMA_DMAADDR_Pos (0U) +#define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_HCDMA register ********************/ +#define USB_OTG_HCDMA_DMAADDR_Pos (0U) +#define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */ +#define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */ + +/******************** Bit definition for USB_OTG_DTXFSTS register ********************/ +#define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U) +#define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */ + +/******************** Bit definition for USB_OTG_DIEPTXF register ********************/ +#define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U) +#define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */ +#define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */ +#define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U) +#define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */ +#define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */ + +/******************** Bit definition for USB_OTG_DOEPCTL register ********************/ + +#define USB_OTG_DOEPCTL_MPSIZ_Pos (0U) +#define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */ +#define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!GINTMSK &= ~(__INTERRUPT__)) +#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) +#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) +#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) +#define USB_MASK_HALT_HC_INT(chnum) (USB_OTG_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM) +#define USB_UNMASK_HALT_HC_INT(chnum) (USB_OTG_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM) +#define CLEAR_HC_INT(chnum, __INTERRUPT__) (USB_OTG_HC(chnum)->HCINT = (__INTERRUPT__)) + +uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base); +uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base); +#endif diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c new file mode 100644 index 00000000000..d9c26261a25 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_at.c @@ -0,0 +1,52 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_config.h" +#include "stdint.h" +#include "usb_dwc2_reg.h" + +/* you can find this config in function: usb_global_init, file:at32fxxx_usb.c, for example: + * + * usbx->gccfg_bit.pwrdown = TRUE; + * usbx->gccfg_bit.avalidsesen = TRUE; + * usbx->gccfg_bit.bvalidsesen = TRUE; + * +*/ + +uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) +{ +#ifdef CONFIG_USB_HS + return ((1 << 16) | (1 << 21)); +#else + // AT32F415 +#if defined(AT32F415RCT7) || defined(AT32F415RCT7_7) || defined(AT32F415CCT7) || \ + defined(AT32F415CCU7) || defined(AT32F415KCU7_4) || defined(AT32F415RBT7) || \ + defined(AT32F415RBT7_7) || defined(AT32F415CBT7) || defined(AT32F415CBU7) || \ + defined(AT32F415KBU7_4) || defined(AT32F415R8T7) || defined(AT32F415R8T7_7) || \ + defined(AT32F415C8T7) || defined(AT32F415K8U7_4) + return ((1 << 16) | (1 << 18) | (1 << 19) | (1 << 21)); +#else + return ((1 << 16) | (1 << 21)); +#endif +#endif +} + +uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) +{ +#ifdef CONFIG_USB_HS + return ((1 << 16) | (1 << 21)); +#else + // AT32F415 +#if defined(AT32F415RCT7) || defined(AT32F415RCT7_7) || defined(AT32F415CCT7) || \ + defined(AT32F415CCU7) || defined(AT32F415KCU7_4) || defined(AT32F415RBT7) || \ + defined(AT32F415RBT7_7) || defined(AT32F415CBT7) || defined(AT32F415CBU7) || \ + defined(AT32F415KBU7_4) || defined(AT32F415R8T7) || defined(AT32F415R8T7_7) || \ + defined(AT32F415C8T7) || defined(AT32F415K8U7_4) + return ((1 << 16) | (1 << 18) | (1 << 19) | (1 << 21)); +#else + return ((1 << 16) | (1 << 21)); +#endif +#endif +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c new file mode 100644 index 00000000000..47b4fb4ddb8 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_esp.c @@ -0,0 +1,120 @@ +/* + * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "sdkconfig.h" +#include "esp_idf_version.h" +#include "esp_intr_alloc.h" +#include "esp_private/usb_phy.h" +#include "soc/periph_defs.h" +#include "usb_config.h" +#include "usb_log.h" + +#ifdef CONFIG_IDF_TARGET_ESP32S2 +#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S2_DEFAULT_CPU_FREQ_MHZ +#elif CONFIG_IDF_TARGET_ESP32S3 +#define DEFAULT_CPU_FREQ_MHZ CONFIG_ESP32S3_DEFAULT_CPU_FREQ_MHZ +#else +#define DEFAULT_CPU_FREQ_MHZ 160 +#endif + +uint32_t SystemCoreClock = (DEFAULT_CPU_FREQ_MHZ * 1000 * 1000); +static usb_phy_handle_t s_phy_handle = NULL; +static intr_handle_t s_interrupt_handle = NULL; + +static void usb_dc_interrupt_cb(void *arg_pv) +{ + extern void USBD_IRQHandler(uint8_t busid); + USBD_IRQHandler(0); +} + +void usb_dc_low_level_init(void) +{ + usb_phy_config_t phy_config = { + .controller = USB_PHY_CTRL_OTG, + .otg_mode = USB_OTG_MODE_DEVICE, + .target = USB_PHY_TARGET_INT, + }; + + esp_err_t ret = usb_new_phy(&phy_config, &s_phy_handle); + if (ret != ESP_OK) { + USB_LOG_ERR("USB Phy Init Failed!\r\n"); + return; + } + + // TODO: Check when to enable interrupt + ret = esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LEVEL2, usb_dc_interrupt_cb, 0, &s_interrupt_handle); + if (ret != ESP_OK) { + USB_LOG_ERR("USB Interrupt Init Failed!\r\n"); + return; + } + USB_LOG_INFO("cherryusb, version: 0x%06x\r\n", CHERRYUSB_VERSION); +} + +void usb_dc_low_level_deinit(void) +{ + if (s_interrupt_handle) { + esp_intr_free(s_interrupt_handle); + s_interrupt_handle = NULL; + } + if (s_phy_handle) { + usb_del_phy(s_phy_handle); + s_phy_handle = NULL; + } +} + +uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) +{ + return 0; +} + +static void usb_hc_interrupt_cb(void *arg_pv) +{ + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(0); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + // Host Library defaults to internal PHY + usb_phy_config_t phy_config = { + .controller = USB_PHY_CTRL_OTG, + .target = USB_PHY_TARGET_INT, + .otg_mode = USB_OTG_MODE_HOST, + .otg_speed = USB_PHY_SPEED_UNDEFINED, // In Host mode, the speed is determined by the connected device + .ext_io_conf = NULL, + .otg_io_conf = NULL, + }; + + esp_err_t ret = usb_new_phy(&phy_config, &s_phy_handle); + if (ret != ESP_OK) { + USB_LOG_ERR("USB Phy Init Failed!\r\n"); + return; + } + + // TODO: Check when to enable interrupt + ret = esp_intr_alloc(ETS_USB_INTR_SOURCE, ESP_INTR_FLAG_LEVEL2, usb_hc_interrupt_cb, 0, &s_interrupt_handle); + if (ret != ESP_OK) { + USB_LOG_ERR("USB Interrupt Init Failed!\r\n"); + return; + } + USB_LOG_INFO("cherryusb, version: 0x%06x\r\n", CHERRYUSB_VERSION); +} + +void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ + if (s_interrupt_handle) { + esp_intr_free(s_interrupt_handle); + s_interrupt_handle = NULL; + } + if (s_phy_handle) { + usb_del_phy(s_phy_handle); + s_phy_handle = NULL; + } +} + +uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) +{ + return 0; +} diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_gd.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_gd.c new file mode 100644 index 00000000000..bdc0d68095e --- /dev/null +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_gd.c @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_config.h" +#include "stdint.h" +#include "usb_dwc2_reg.h" + +/* you can find this config in function:usb_core_init, file:drv_usb_core.c, for example: + * + * usb_regs->gr->GCCFG |= GCCFG_PWRON | GCCFG_VBUSACEN | GCCFG_VBUSBCEN; + * +*/ + +uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) +{ +#ifdef CONFIG_USB_HS + return 0; +#else + return ((1 << 16) | (1 << 18) | (1 << 19) | (1 << 21)); +#endif +} + +uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) +{ +#ifdef CONFIG_USB_HS + return 0; +#else + return ((1 << 16) | (1 << 18) | (1 << 19) | (1 << 21)); +#endif +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c new file mode 100644 index 00000000000..94293d29b78 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_glue_st.c @@ -0,0 +1,203 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_config.h" +#include "stdint.h" +#include "usb_dwc2_reg.h" + +/* you can find this config in function: USB_DevInit, file:stm32xxx_ll_usb.c, for example: + * + * USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; + * USBx->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS; + * USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSBSEN; + * USBx->GCCFG &= ~USB_OTG_GCCFG_VBUSASEN; + * +*/ + +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) +/** + * @brief USB_HS_PHY_Registers + */ +typedef struct +{ + +__IO uint32_t USB_HS_PHYC_PLL; /*!< This register is used to control the PLL of the HS PHY. 000h */ +__IO uint32_t Reserved04; /*!< Reserved 004h */ +__IO uint32_t Reserved08; /*!< Reserved 008h */ +__IO uint32_t USB_HS_PHYC_TUNE; /*!< This register is used to control the tuning interface of the High Speed PHY. 00Ch */ +__IO uint32_t Reserved10; /*!< Reserved 010h */ +__IO uint32_t Reserved14; /*!< Reserved 014h */ +__IO uint32_t USB_HS_PHYC_LDO; /*!< This register is used to control the regulator (LDO). 018h */ +} USB_HS_PHYC_GlobalTypeDef; + +#define USB_HS_PHYC_CONTROLLER_BASE 0x40017C00UL +#define USB_HS_PHYC ((USB_HS_PHYC_GlobalTypeDef *) USB_HS_PHYC_CONTROLLER_BASE) + +/******************** Bit definition for USBPHYC_PLL1 register ********************/ +#define USB_HS_PHYC_PLL1_PLLEN_Pos (0U) +#define USB_HS_PHYC_PLL1_PLLEN_Msk (0x1UL << USB_HS_PHYC_PLL1_PLLEN_Pos) /*!< 0x00000001 */ +#define USB_HS_PHYC_PLL1_PLLEN USB_HS_PHYC_PLL1_PLLEN_Msk /*!< Enable PLL */ +#define USB_HS_PHYC_PLL1_PLLSEL_Pos (1U) +#define USB_HS_PHYC_PLL1_PLLSEL_Msk (0x7UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x0000000E */ +#define USB_HS_PHYC_PLL1_PLLSEL USB_HS_PHYC_PLL1_PLLSEL_Msk /*!< Controls PHY frequency operation selection */ +#define USB_HS_PHYC_PLL1_PLLSEL_1 (0x1UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000002 */ +#define USB_HS_PHYC_PLL1_PLLSEL_2 (0x2UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000004 */ +#define USB_HS_PHYC_PLL1_PLLSEL_3 (0x4UL << USB_HS_PHYC_PLL1_PLLSEL_Pos) /*!< 0x00000008 */ + +#define USB_HS_PHYC_PLL1_PLLSEL_12MHZ 0x00000000U /*!< PHY PLL1 input clock frequency 12 MHz */ +#define USB_HS_PHYC_PLL1_PLLSEL_12_5MHZ USB_HS_PHYC_PLL1_PLLSEL_1 /*!< PHY PLL1 input clock frequency 12.5 MHz */ +#define USB_HS_PHYC_PLL1_PLLSEL_16MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_1 | USB_HS_PHYC_PLL1_PLLSEL_2) /*!< PHY PLL1 input clock frequency 16 MHz */ +#define USB_HS_PHYC_PLL1_PLLSEL_24MHZ USB_HS_PHYC_PLL1_PLLSEL_3 /*!< PHY PLL1 input clock frequency 24 MHz */ +#define USB_HS_PHYC_PLL1_PLLSEL_25MHZ (uint32_t)(USB_HS_PHYC_PLL1_PLLSEL_2 | USB_HS_PHYC_PLL1_PLLSEL_3) /*!< PHY PLL1 input clock frequency 25 MHz */ + +/******************** Bit definition for USBPHYC_LDO register ********************/ +#define USB_HS_PHYC_LDO_USED_Pos (0U) +#define USB_HS_PHYC_LDO_USED_Msk (0x1UL << USB_HS_PHYC_LDO_USED_Pos) /*!< 0x00000001 */ +#define USB_HS_PHYC_LDO_USED USB_HS_PHYC_LDO_USED_Msk /*!< Monitors the usage status of the PHY's LDO */ +#define USB_HS_PHYC_LDO_STATUS_Pos (1U) +#define USB_HS_PHYC_LDO_STATUS_Msk (0x1UL << USB_HS_PHYC_LDO_STATUS_Pos) /*!< 0x00000002 */ +#define USB_HS_PHYC_LDO_STATUS USB_HS_PHYC_LDO_STATUS_Msk /*!< Monitors the status of the PHY's LDO. */ +#define USB_HS_PHYC_LDO_DISABLE_Pos (2U) +#define USB_HS_PHYC_LDO_DISABLE_Msk (0x1UL << USB_HS_PHYC_LDO_DISABLE_Pos) /*!< 0x00000004 */ +#define USB_HS_PHYC_LDO_DISABLE USB_HS_PHYC_LDO_DISABLE_Msk /*!< Controls disable of the High Speed PHY's LDO */ + +/* Legacy */ +#define USB_HS_PHYC_PLL_PLLEN_Pos USB_HS_PHYC_PLL1_PLLEN_Pos +#define USB_HS_PHYC_PLL_PLLEN_Msk USB_HS_PHYC_PLL1_PLLEN_Msk +#define USB_HS_PHYC_PLL_PLLEN USB_HS_PHYC_PLL1_PLLEN +#define USB_HS_PHYC_PLL_PLLSEL_Pos USB_HS_PHYC_PLL1_PLLSEL_Pos +#define USB_HS_PHYC_PLL_PLLSEL_Msk USB_HS_PHYC_PLL1_PLLSEL_Msk +#define USB_HS_PHYC_PLL_PLLSEL USB_HS_PHYC_PLL1_PLLSEL +#define USB_HS_PHYC_PLL_PLLSEL_1 USB_HS_PHYC_PLL1_PLLSEL_1 +#define USB_HS_PHYC_PLL_PLLSEL_2 USB_HS_PHYC_PLL1_PLLSEL_2 +#define USB_HS_PHYC_PLL_PLLSEL_3 USB_HS_PHYC_PLL1_PLLSEL_3 + +#define USB_HS_PHYC_LDO_ENABLE_Pos USB_HS_PHYC_LDO_DISABLE_Pos +#define USB_HS_PHYC_LDO_ENABLE_Msk USB_HS_PHYC_LDO_DISABLE_Msk +#define USB_HS_PHYC_LDO_ENABLE USB_HS_PHYC_LDO_DISABLE + +#if !defined (USB_HS_PHYC_TUNE_VALUE) +#define USB_HS_PHYC_TUNE_VALUE 0x00000F13U /*!< Value of USB HS PHY Tune */ +#endif /* USB_HS_PHYC_TUNE_VALUE */ +/** + * @brief Enables control of a High Speed USB PHY + * Init the low level hardware : GPIO, CLOCK, NVIC... + * @param USBx Selected device + * @retval HAL status + */ +static int usb_hsphy_init(uint32_t hse_value) +{ + __IO uint32_t count = 0U; + + /* Enable LDO */ + USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE; + + /* wait for LDO Ready */ + while ((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == 0U) + { + count++; + + if (count > 200000U) + { + return -1; + } + } + + /* Controls PHY frequency operation selection */ + if (hse_value == 12000000U) /* HSE = 12MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1); + } + else if (hse_value == 12500000U) /* HSE = 12.5MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1); + } + else if (hse_value == 16000000U) /* HSE = 16MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1); + } + else if (hse_value == 24000000U) /* HSE = 24MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1); + } + else if (hse_value == 25000000U) /* HSE = 25MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1); + } + else if (hse_value == 32000000U) /* HSE = 32MHz */ + { + USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1); + } + else + { + /* ... */ + } + + /* Control the tuning interface of the High Speed PHY */ + USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE; + + /* Enable PLL internal PHY */ + USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN; + + + /* 2ms Delay required to get internal phy clock stable */ + HAL_Delay(2U); + + return 0; +} + +#endif + +uint32_t usbd_get_dwc2_gccfg_conf(uint32_t reg_base) +{ +#if __has_include("stm32h7xx.h") || __has_include("stm32f7xx.h") || __has_include("stm32l4xx.h") +#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(reg_base)) + /* B-peripheral session valid override enable */ + USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; + USB_OTG_GLB->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; +#endif + +#ifdef CONFIG_USB_HS +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) + USB_OTG_GLB->GCCFG = (1 << 23); + usb_hsphy_init(25000000U); + return (1 << 23); /* Enable USB HS PHY USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;*/ +#else + return 0; +#endif +#else +#if __has_include("stm32h7xx.h") || __has_include("stm32f7xx.h") || __has_include("stm32l4xx.h") + return (1 << 16); +#else + return ((1 << 16) | (1 << 21)); +#endif +#endif +} + +uint32_t usbh_get_dwc2_gccfg_conf(uint32_t reg_base) +{ +#if __has_include("stm32h7xx.h") || __has_include("stm32f7xx.h") || __has_include("stm32l4xx.h") +#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(reg_base)) + /* B-peripheral session valid override enable */ + USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOEN; + USB_OTG_GLB->GOTGCTL &= ~USB_OTG_GOTGCTL_BVALOVAL; +#endif + +#ifdef CONFIG_USB_HS +#if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx) + USB_OTG_GLB->GCCFG = (1 << 23); + usb_hsphy_init(25000000U); + return (1 << 23); /* Enable USB HS PHY USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;*/ +#else + return 0; +#endif +#else +#if __has_include("stm32h7xx.h") || __has_include("stm32f7xx.h") || __has_include("stm32l4xx.h") + return (1 << 16); +#else + return ((1 << 16) | (1 << 21)); +#endif +#endif +} diff --git a/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c b/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c new file mode 100644 index 00000000000..3dcf5fcc3f7 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/dwc2/usb_hc_dwc2.c @@ -0,0 +1,1094 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_hub.h" +#include "usb_dwc2_reg.h" + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 12 +#endif + +/* largest non-periodic USB packet used / 4 */ +#ifndef CONFIG_USB_DWC2_NPTX_FIFO_SIZE +#define CONFIG_USB_DWC2_NPTX_FIFO_SIZE (512 / 4) +#endif + +/* largest periodic USB packet used / 4 */ +#ifndef CONFIG_USB_DWC2_PTX_FIFO_SIZE +#define CONFIG_USB_DWC2_PTX_FIFO_SIZE (1024 / 4) +#endif + +/* + * (largest USB packet used / 4) + 1 for status information + 1 transfer complete + + * 1 location each for Bulk/Control endpoint for handling NAK/NYET scenario + */ +#ifndef CONFIG_USB_DWC2_RX_FIFO_SIZE +#define CONFIG_USB_DWC2_RX_FIFO_SIZE ((1012 - CONFIG_USB_DWC2_NPTX_FIFO_SIZE - CONFIG_USB_DWC2_PTX_FIFO_SIZE) / 4) +#endif + +#define USB_OTG_GLB ((DWC2_GlobalTypeDef *)(bus->hcd.reg_base)) +#define USB_OTG_PCGCCTL *(__IO uint32_t *)((uint32_t)bus->hcd.reg_base + USB_OTG_PCGCCTL_BASE) +#define USB_OTG_HPRT *(__IO uint32_t *)((uint32_t)bus->hcd.reg_base + USB_OTG_HOST_PORT_BASE) +#define USB_OTG_HOST ((DWC2_HostTypeDef *)(bus->hcd.reg_base + USB_OTG_HOST_BASE)) +#define USB_OTG_HC(i) ((DWC2_HostChannelTypeDef *)(bus->hcd.reg_base + USB_OTG_HOST_CHANNEL_BASE + ((i)*USB_OTG_HOST_CHANNEL_SIZE))) + +struct dwc2_chan { + uint8_t ep0_state; + uint16_t num_packets; + uint32_t xferlen; + uint8_t chidx; + bool inuse; + usb_osal_sem_t waitsem; + struct usbh_urb *urb; + uint32_t iso_frame_idx; +}; + +struct dwc2_hcd { + volatile bool port_csc; + volatile bool port_pec; + volatile bool port_occ; + struct dwc2_chan chan_pool[CONFIG_USBHOST_PIPE_NUM]; +} g_dwc2_hcd[CONFIG_USBHOST_MAX_BUS]; + +#define DWC2_EP0_STATE_SETUP 0 +#define DWC2_EP0_STATE_INDATA 1 +#define DWC2_EP0_STATE_OUTDATA 2 +#define DWC2_EP0_STATE_INSTATUS 3 +#define DWC2_EP0_STATE_OUTSTATUS 4 + +static inline int dwc2_reset(struct usbh_bus *bus) +{ + volatile uint32_t count = 0U; + + /* Wait for AHB master IDLE state. */ + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); + + /* Core Soft Reset */ + count = 0U; + USB_OTG_GLB->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; + + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); + + return 0; +} + +static inline int dwc2_core_init(struct usbh_bus *bus) +{ + int ret; +#if defined(CONFIG_USB_HS) + /* Init The ULPI Interface */ + USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL); + + /* Select vbus source */ + USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI); + + //USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD; + /* Reset after a PHY select */ + ret = dwc2_reset(bus); +#else + /* Select FS Embedded PHY */ + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; + /* Reset after a PHY select */ + ret = dwc2_reset(bus); +#endif + return ret; +} + +static inline void dwc2_set_mode(struct usbh_bus *bus, uint8_t mode) +{ + USB_OTG_GLB->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); + + if (mode == USB_OTG_MODE_HOST) { + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; + } else if (mode == USB_OTG_MODE_DEVICE) { + USB_OTG_GLB->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; + } +} + +static inline int dwc2_flush_rxfifo(struct usbh_bus *bus) +{ + volatile uint32_t count = 0; + + USB_OTG_GLB->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; + + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); + + return 0; +} + +static inline int dwc2_flush_txfifo(struct usbh_bus *bus, uint32_t num) +{ + volatile uint32_t count = 0U; + + USB_OTG_GLB->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); + + do { + if (++count > 200000U) { + return -1; + } + } while ((USB_OTG_GLB->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); + + return 0; +} + +static inline void dwc2_drivebus(struct usbh_bus *bus, uint8_t state) +{ + __IO uint32_t hprt0 = 0U; + + hprt0 = USB_OTG_HPRT; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) { + USB_OTG_HPRT = (USB_OTG_HPRT_PPWR | hprt0); + } + if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) { + USB_OTG_HPRT = ((~USB_OTG_HPRT_PPWR) & hprt0); + } +} + +static inline uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + __IO uint32_t hprt0 = 0U; + uint8_t speed; + + hprt0 = USB_OTG_HPRT; + + speed = (hprt0 & USB_OTG_HPRT_PSPD) >> 17; + + if (speed == HPRT0_PRTSPD_HIGH_SPEED) { + return USB_SPEED_HIGH; + } else if (speed == HPRT0_PRTSPD_FULL_SPEED) { + return USB_SPEED_FULL; + } else if (speed == HPRT0_PRTSPD_LOW_SPEED) { + return USB_SPEED_LOW; + } else { + return USB_SPEED_UNKNOWN; + } +} + +static inline void dwc2_chan_char_init(struct usbh_bus *bus, uint8_t ch_num, uint8_t devaddr, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps, uint8_t speed) +{ + uint32_t regval; + + /* Program the HCCHAR register */ + regval = (((uint32_t)ep_mps << USB_OTG_HCCHAR_MPSIZ_Pos) & USB_OTG_HCCHAR_MPSIZ) | + ((((uint32_t)ep_addr & 0x7FU) << USB_OTG_HCCHAR_EPNUM_Pos) & USB_OTG_HCCHAR_EPNUM) | + (((uint32_t)ep_type << USB_OTG_HCCHAR_EPTYP_Pos) & USB_OTG_HCCHAR_EPTYP) | + (((uint32_t)devaddr << USB_OTG_HCCHAR_DAD_Pos) & USB_OTG_HCCHAR_DAD); + + if ((ep_addr & 0x80U) == 0x80U) { + regval |= USB_OTG_HCCHAR_EPDIR; + } + + /* LS device plugged to HUB */ + if ((speed == USB_SPEED_LOW) && (usbh_get_port_speed(bus, 0) != USB_SPEED_LOW)) { + regval |= USB_OTG_HCCHAR_LSDEV; + } + + if (ep_type == USB_ENDPOINT_TYPE_INTERRUPT) { + regval |= USB_OTG_HCCHAR_ODDFRM; + } + + USB_OTG_HC((uint32_t)ch_num)->HCCHAR = regval; +} + +static void dwc2_chan_init(struct usbh_bus *bus, uint8_t ch_num, uint8_t devaddr, uint8_t ep_addr, uint8_t ep_type, uint16_t ep_mps, uint8_t speed) +{ + uint32_t regval; + + /* Clear old interrupt conditions for this host channel. */ + USB_OTG_HC((uint32_t)ch_num)->HCINT = 0xFFFFFFFFU; + + /* Enable channel interrupts required for this transfer. */ + regval = USB_OTG_HCINTMSK_CHHM; + + if (ep_type == USB_ENDPOINT_TYPE_INTERRUPT) { + regval |= USB_OTG_HCINTMSK_NAKM; + } + + USB_OTG_HC((uint32_t)ch_num)->HCINTMSK = regval; + + /* Enable the top level host channel interrupt. */ + USB_OTG_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); + + dwc2_chan_char_init(bus, ch_num, devaddr, ep_addr, ep_type, ep_mps, speed); +} + +/* For IN channel HCTSIZ.XferSize is expected to be an integer multiple of ep_mps size.*/ +static inline void dwc2_chan_transfer(struct usbh_bus *bus, uint8_t ch_num, uint8_t ep_addr, uint32_t *buf, uint32_t size, uint8_t num_packets, uint8_t pid) +{ + __IO uint32_t tmpreg; + uint8_t is_oddframe; + + /* Initialize the HCTSIZn register */ + USB_OTG_HC(ch_num)->HCTSIZ = (size & USB_OTG_HCTSIZ_XFRSIZ) | + (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | + (((uint32_t)pid << 29) & USB_OTG_HCTSIZ_DPID); + + /* xfer_buff MUST be 32-bits aligned */ + USB_OTG_HC(ch_num)->HCDMA = (uint32_t)buf; + + is_oddframe = (((uint32_t)USB_OTG_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; + USB_OTG_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; + USB_OTG_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; + + /* Set host channel enable */ + tmpreg = USB_OTG_HC(ch_num)->HCCHAR; + tmpreg &= ~USB_OTG_HCCHAR_CHDIS; + tmpreg |= USB_OTG_HCCHAR_CHENA; + USB_OTG_HC(ch_num)->HCCHAR = tmpreg; +} + +static void dwc2_halt(struct usbh_bus *bus, uint8_t ch_num) +{ + volatile uint32_t ChannelEna = (USB_OTG_HC(ch_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; + volatile uint32_t count = 0U; + __IO uint32_t value; + + if (((USB_OTG_GLB->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && + (ChannelEna == 0U)) { + return; + } + + USB_OTG_HC(ch_num)->HCINTMSK = 0; + + value = USB_OTG_HC(ch_num)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USB_OTG_HC(ch_num)->HCCHAR = value; + do { + if (++count > 200000U) { + break; + } + } while (USB_OTG_HC(ch_num)->HCCHAR & USB_OTG_HCCHAR_CHENA); + + USB_OTG_HC(ch_num)->HCINT = USB_OTG_HC(ch_num)->HCINT; +} + +static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port) +{ + __IO uint32_t hprt0 = 0U; + + hprt0 = USB_OTG_HPRT; + + hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + USB_OTG_HPRT = (USB_OTG_HPRT_PRST | hprt0); + usb_osal_msleep(100U); /* See Note #1 */ + USB_OTG_HPRT = ((~USB_OTG_HPRT_PRST) & hprt0); + usb_osal_msleep(10U); + + while (!(USB_OTG_HPRT & USB_OTG_HPRT_PENA)) { + usb_osal_msleep(10U); + } + return 0; +} + +/** + * @brief dwc2_get_glb_intstatus: return the global USB interrupt status + * @retval status + */ +static inline uint32_t dwc2_get_glb_intstatus(struct usbh_bus *bus) +{ + uint32_t tmpreg; + + tmpreg = USB_OTG_GLB->GINTSTS; + tmpreg &= USB_OTG_GLB->GINTMSK; + + return tmpreg; +} + +static int dwc2_chan_alloc(struct usbh_bus *bus) +{ + size_t flags; + int chidx; + + for (chidx = 0; chidx < CONFIG_USBHOST_PIPE_NUM; chidx++) { + if (!g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx].inuse) { + flags = usb_osal_enter_critical_section(); + g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx].inuse = true; + usb_osal_leave_critical_section(flags); + return chidx; + } + } + + return -1; +} + +static void dwc2_chan_free(struct dwc2_chan *chan) +{ + size_t flags; + + flags = usb_osal_enter_critical_section(); + chan->inuse = false; + usb_osal_leave_critical_section(flags); +} + +static uint8_t dwc2_calculate_packet_num(uint32_t input_size, uint8_t ep_addr, uint16_t ep_mps, uint32_t *output_size) +{ + uint16_t num_packets; + + num_packets = (uint16_t)((input_size + ep_mps - 1U) / ep_mps); + + if (num_packets > 256) { + num_packets = 256; + } + + if (input_size == 0) { + num_packets = 1; + } + + if (ep_addr & 0x80) { + input_size = num_packets * ep_mps; + } else { + } + + *output_size = input_size; + return num_packets; +} + +static void dwc2_control_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen) +{ + struct dwc2_chan *chan; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx]; + + if (chan->ep0_state == DWC2_EP0_STATE_SETUP) /* fill setup */ + { + chan->num_packets = dwc2_calculate_packet_num(8, 0x00, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, chidx, urb->hport->dev_addr, 0x00, USB_ENDPOINT_TYPE_CONTROL, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), urb->hport->speed); + dwc2_chan_transfer(bus, chidx, 0x00, (uint32_t *)setup, chan->xferlen, chan->num_packets, HC_PID_SETUP); + } else if (chan->ep0_state == DWC2_EP0_STATE_INDATA) /* fill in data */ + { + chan->num_packets = dwc2_calculate_packet_num(setup->wLength, 0x80, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, chidx, urb->hport->dev_addr, 0x80, USB_ENDPOINT_TYPE_CONTROL, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), urb->hport->speed); + dwc2_chan_transfer(bus, chidx, 0x80, (uint32_t *)buffer, chan->xferlen, chan->num_packets, HC_PID_DATA1); + } else if (chan->ep0_state == DWC2_EP0_STATE_OUTDATA) /* fill out data */ + { + chan->num_packets = dwc2_calculate_packet_num(setup->wLength, 0x00, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, chidx, urb->hport->dev_addr, 0x00, USB_ENDPOINT_TYPE_CONTROL, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), urb->hport->speed); + dwc2_chan_transfer(bus, chidx, 0x00, (uint32_t *)buffer, chan->xferlen, chan->num_packets, HC_PID_DATA1); + } else if (chan->ep0_state == DWC2_EP0_STATE_INSTATUS) /* fill in status */ + { + chan->num_packets = dwc2_calculate_packet_num(0, 0x80, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, chidx, urb->hport->dev_addr, 0x80, USB_ENDPOINT_TYPE_CONTROL, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), urb->hport->speed); + dwc2_chan_transfer(bus, chidx, 0x80, NULL, chan->xferlen, chan->num_packets, HC_PID_DATA1); + } else if (chan->ep0_state == DWC2_EP0_STATE_OUTSTATUS) /* fill out status */ + { + chan->num_packets = dwc2_calculate_packet_num(0, 0x00, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, chidx, urb->hport->dev_addr, 0x00, USB_ENDPOINT_TYPE_CONTROL, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), urb->hport->speed); + dwc2_chan_transfer(bus, chidx, 0x00, NULL, chan->xferlen, chan->num_packets, HC_PID_DATA1); + } +} + +static void dwc2_bulk_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + struct dwc2_chan *chan; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx]; + + chan->num_packets = dwc2_calculate_packet_num(buflen, urb->ep->bEndpointAddress, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, chidx, urb->hport->dev_addr, urb->ep->bEndpointAddress, USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes), USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), urb->hport->speed); + dwc2_chan_transfer(bus, chidx, urb->ep->bEndpointAddress, (uint32_t *)buffer, chan->xferlen, chan->num_packets, urb->data_toggle == 0 ? HC_PID_DATA0 : HC_PID_DATA1); +} + +static void dwc2_iso_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, struct usbh_iso_frame_packet *iso_packet) +{ + struct dwc2_chan *chan; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx]; + + chan->num_packets = dwc2_calculate_packet_num(iso_packet->transfer_buffer_length, urb->ep->bEndpointAddress, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), &chan->xferlen); + dwc2_chan_init(bus, chidx, urb->hport->dev_addr, urb->ep->bEndpointAddress, USB_ENDPOINT_TYPE_ISOCHRONOUS, USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), urb->hport->speed); + dwc2_chan_transfer(bus, chidx, urb->ep->bEndpointAddress, (uint32_t *)iso_packet->transfer_buffer, chan->xferlen, chan->num_packets, HC_PID_DATA0); +} + +__WEAK void usb_hc_low_level_init(struct usbh_bus *bus) +{ +} + +__WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ +} + +int usb_hc_init(struct usbh_bus *bus) +{ + int ret; + + memset(&g_dwc2_hcd[bus->hcd.hcd_id], 0, sizeof(struct dwc2_hcd)); + + for (uint8_t chidx = 0; chidx < CONFIG_USBHOST_PIPE_NUM; chidx++) { + g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx].waitsem = usb_osal_sem_create(0); + } + + usb_hc_low_level_init(bus); + + USB_LOG_INFO("========== dwc2 hcd params ==========\r\n"); + USB_LOG_INFO("CID:%08x\r\n", USB_OTG_GLB->CID); + USB_LOG_INFO("GSNPSID:%08x\r\n", USB_OTG_GLB->GSNPSID); + USB_LOG_INFO("GHWCFG1:%08x\r\n", USB_OTG_GLB->GHWCFG1); + USB_LOG_INFO("GHWCFG2:%08x\r\n", USB_OTG_GLB->GHWCFG2); + USB_LOG_INFO("GHWCFG3:%08x\r\n", USB_OTG_GLB->GHWCFG3); + USB_LOG_INFO("GHWCFG4:%08x\r\n", USB_OTG_GLB->GHWCFG4); + + USB_LOG_INFO("dwc2 has %d channels and dfifo depth(32-bit words) is %d\r\n", ((USB_OTG_GLB->GHWCFG2 & (0x0f << 14)) >> 14) + 1, (USB_OTG_GLB->GHWCFG3 >> 16)); + + if (((USB_OTG_GLB->GHWCFG2 & (0x3U << 3)) >> 3) != 2) { + USB_LOG_ERR("This dwc2 version does not support dma mode, so stop working\r\n"); + while (1) { + } + } + + if ((CONFIG_USB_DWC2_RX_FIFO_SIZE + CONFIG_USB_DWC2_NPTX_FIFO_SIZE + CONFIG_USB_DWC2_PTX_FIFO_SIZE) > (USB_OTG_GLB->GHWCFG3 >> 16)) { + USB_LOG_ERR("Your fifo config is overflow, please check\r\n"); + while (1) { + } + } + + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + + /* This is vendor register */ + USB_OTG_GLB->GCCFG = usbh_get_dwc2_gccfg_conf(bus->hcd.reg_base); + + ret = dwc2_core_init(bus); + + /* Force Host Mode*/ + dwc2_set_mode(bus, USB_OTG_MODE_HOST); + usb_osal_msleep(50); + + /* Restart the Phy Clock */ + USB_OTG_PCGCCTL = 0U; + + dwc2_drivebus(bus, 1); + usb_osal_msleep(200); + + /* Set default Max speed support */ + USB_OTG_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); + + /* Clear all pending HC Interrupts */ + for (uint8_t i = 0U; i < CONFIG_USBHOST_PIPE_NUM; i++) { + USB_OTG_HC(i)->HCINT = 0xFFFFFFFFU; + USB_OTG_HC(i)->HCINTMSK = 0U; + } + + /* Disable all interrupts. */ + USB_OTG_GLB->GINTMSK = 0U; + + /* Clear any pending interrupts */ + USB_OTG_GLB->GINTSTS = 0xFFFFFFFFU; + + /* set Rx FIFO size */ + USB_OTG_GLB->GRXFSIZ = CONFIG_USB_DWC2_RX_FIFO_SIZE; + USB_OTG_GLB->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((CONFIG_USB_DWC2_NPTX_FIFO_SIZE << 16) & USB_OTG_NPTXFD) | CONFIG_USB_DWC2_RX_FIFO_SIZE); + USB_OTG_GLB->HPTXFSIZ = (uint32_t)(((CONFIG_USB_DWC2_PTX_FIFO_SIZE << 16) & USB_OTG_HPTXFSIZ_PTXFD) | (CONFIG_USB_DWC2_RX_FIFO_SIZE + CONFIG_USB_DWC2_NPTX_FIFO_SIZE)); + + ret = dwc2_flush_txfifo(bus, 0x10U); + ret = dwc2_flush_rxfifo(bus); + + USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_4; + USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; + + /* Enable interrupts matching to the Host mode ONLY */ + USB_OTG_GLB->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | + USB_OTG_GINTSTS_DISCINT); + + USB_OTG_GLB->GAHBCFG |= USB_OTG_GAHBCFG_GINT; + + return ret; +} + +int usb_hc_deinit(struct usbh_bus *bus) +{ + volatile uint32_t count = 0U; + uint32_t value; + + USB_OTG_GLB->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; + + dwc2_flush_txfifo(bus, 0x10U); + dwc2_flush_rxfifo(bus); + + /* Flush out any leftover queued requests. */ + for (uint32_t i = 0U; i <= 15U; i++) { + value = USB_OTG_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value &= ~USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USB_OTG_HC(i)->HCCHAR = value; + } + + /* Halt all channels to put them into a known state. */ + for (uint32_t i = 0U; i <= 15U; i++) { + value = USB_OTG_HC(i)->HCCHAR; + value |= USB_OTG_HCCHAR_CHDIS; + value |= USB_OTG_HCCHAR_CHENA; + value &= ~USB_OTG_HCCHAR_EPDIR; + USB_OTG_HC(i)->HCCHAR = value; + + do { + if (++count > 1000U) { + return -USB_ERR_TIMEOUT; + } + } while ((USB_OTG_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); + } + + /* Disable all interrupts. */ + USB_OTG_GLB->GINTMSK = 0U; + + /* Clear any pending Host interrupts */ + USB_OTG_HOST->HAINT = 0xFFFFFFFFU; + USB_OTG_GLB->GINTSTS = 0xFFFFFFFFU; + + dwc2_drivebus(bus, 0); + usb_osal_msleep(200); + + for (uint8_t chidx = 0; chidx < CONFIG_USBHOST_PIPE_NUM; chidx++) { + usb_osal_sem_delete(g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx].waitsem); + } + + usb_hc_low_level_deinit(bus); + return 0; +} + +uint16_t usbh_get_frame_number(struct usbh_bus *bus) +{ + return (USB_OTG_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); +} + +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + __IO uint32_t hprt0; + uint8_t nports; + uint8_t port; + uint32_t status; + + nports = CONFIG_USBHOST_MAX_RHPORTS; + port = setup->wIndex; + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + break; + case HUB_REQUEST_GET_STATUS: + memset(buf, 0, 4); + break; + default: + break; + } + } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_ENABLE: + USB_OTG_HPRT &= ~USB_OTG_HPRT_PENA; + break; + case HUB_PORT_FEATURE_SUSPEND: + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_C_CONNECTION: + g_dwc2_hcd[bus->hcd.hcd_id].port_csc = 0; + break; + case HUB_PORT_FEATURE_C_ENABLE: + g_dwc2_hcd[bus->hcd.hcd_id].port_pec = 0; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + g_dwc2_hcd[bus->hcd.hcd_id].port_occ = 0; + break; + case HUB_PORT_FEATURE_C_RESET: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + USB_OTG_HPRT &= ~USB_OTG_HPRT_PPWR; + break; + case HUB_PORT_FEATURE_RESET: + usbh_reset_port(bus, port); + break; + + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + hprt0 = USB_OTG_HPRT; + + status = 0; + if (g_dwc2_hcd[bus->hcd.hcd_id].port_csc) { + status |= (1 << HUB_PORT_FEATURE_C_CONNECTION); + } + if (g_dwc2_hcd[bus->hcd.hcd_id].port_pec) { + status |= (1 << HUB_PORT_FEATURE_C_ENABLE); + } + if (g_dwc2_hcd[bus->hcd.hcd_id].port_occ) { + status |= (1 << HUB_PORT_FEATURE_C_OVER_CURREN); + } + + if (hprt0 & USB_OTG_HPRT_PCSTS) { + status |= (1 << HUB_PORT_FEATURE_CONNECTION); + } + if (hprt0 & USB_OTG_HPRT_PENA) { + status |= (1 << HUB_PORT_FEATURE_ENABLE); + if (usbh_get_port_speed(bus, port) == USB_SPEED_LOW) { + status |= (1 << HUB_PORT_FEATURE_LOWSPEED); + } else if (usbh_get_port_speed(bus, port) == USB_SPEED_HIGH) { + status |= (1 << HUB_PORT_FEATURE_HIGHSPEED); + } + } + if (hprt0 & USB_OTG_HPRT_POCA) { + status |= (1 << HUB_PORT_FEATURE_OVERCURRENT); + } + if (hprt0 & USB_OTG_HPRT_PRST) { + status |= (1 << HUB_PORT_FEATURE_RESET); + } + if (hprt0 & USB_OTG_HPRT_PPWR) { + status |= (1 << HUB_PORT_FEATURE_POWER); + } + + memcpy(buf, &status, 4); + break; + default: + break; + } + } + return 0; +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + struct dwc2_chan *chan; + struct usbh_bus *bus; + size_t flags; + int ret = 0; + int chidx; + + if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + /* dma addr must be aligned 4 bytes */ + if ((((uint32_t)urb->setup) & 0x03) || (((uint32_t)urb->transfer_buffer) & 0x03)) { + return -USB_ERR_INVAL; + } + + bus = urb->hport->bus; + + if (!(USB_OTG_HPRT & USB_OTG_HPRT_PCSTS) || !urb->hport->connected) { + return -USB_ERR_NOTCONN; + } + + if (urb->errorcode == -USB_ERR_BUSY) { + return -USB_ERR_BUSY; + } + + flags = usb_osal_enter_critical_section(); + + chidx = dwc2_chan_alloc(bus); + if (chidx == -1) { + usb_osal_leave_critical_section(flags); + return -USB_ERR_NOMEM; + } + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[chidx]; + chan->chidx = chidx; + chan->urb = urb; + + urb->hcpriv = chan; + urb->errorcode = -USB_ERR_BUSY; + urb->actual_length = 0; + + usb_osal_leave_critical_section(flags); + + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + chan->ep0_state = DWC2_EP0_STATE_SETUP; + dwc2_control_urb_init(bus, chidx, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + case USB_ENDPOINT_TYPE_INTERRUPT: + dwc2_bulk_intr_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_ISOCHRONOUS: + break; + default: + break; + } + + if (urb->timeout > 0) { + /* wait until timeout or sem give */ + ret = usb_osal_sem_take(chan->waitsem, urb->timeout); + if (ret < 0) { + goto errout_timeout; + } + urb->timeout = 0; + ret = urb->errorcode; + /* we can free chan when waitsem is done */ + dwc2_chan_free(chan); + } + return ret; +errout_timeout: + urb->timeout = 0; + usbh_kill_urb(urb); + return ret; +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + struct dwc2_chan *chan; + struct usbh_bus *bus; + size_t flags; + + if (!urb || !urb->hcpriv || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + bus = urb->hport->bus; + + flags = usb_osal_enter_critical_section(); + + chan = (struct dwc2_chan *)urb->hcpriv; + + dwc2_halt(bus, chan->chidx); + + chan->urb = NULL; + urb->hcpriv = NULL; + urb->errorcode = -USB_ERR_SHUTDOWN; + + if (urb->timeout) { + usb_osal_sem_give(chan->waitsem); + } else { + dwc2_chan_free(chan); + } + + usb_osal_leave_critical_section(flags); + + return 0; +} + +static inline void dwc2_urb_waitup(struct usbh_urb *urb) +{ + struct dwc2_chan *chan; + + chan = (struct dwc2_chan *)urb->hcpriv; + chan->urb = NULL; + urb->hcpriv = NULL; + + if (urb->timeout) { + usb_osal_sem_give(chan->waitsem); + } else { + dwc2_chan_free(chan); + } + + if (urb->complete) { + if (urb->errorcode < 0) { + urb->complete(urb->arg, urb->errorcode); + } else { + urb->complete(urb->arg, urb->actual_length); + } + } +} + +static void dwc2_inchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) +{ + uint32_t chan_intstatus; + struct dwc2_chan *chan; + struct usbh_urb *urb; + + chan_intstatus = USB_OTG_HC(ch_num)->HCINT; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[ch_num]; + urb = chan->urb; + //printf("s1:%08x\r\n", chan_intstatus); + + if (chan_intstatus & USB_OTG_HCINT_CHH) { + if (chan_intstatus & USB_OTG_HCINT_XFRC) { + urb->errorcode = 0; + + uint32_t count = chan->xferlen - (USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ); /* how many size has received */ + uint32_t has_used_packets = chan->num_packets - ((USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19); /* how many packets have used */ + + urb->actual_length += count; + + uint8_t data_toggle = ((USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_DPID) >> USB_OTG_HCTSIZ_DPID_Pos); + + if (data_toggle == HC_PID_DATA0) { + urb->data_toggle = 0; + } else { + urb->data_toggle = 1; + } + + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) { + if (chan->ep0_state == DWC2_EP0_STATE_INDATA) { + chan->ep0_state = DWC2_EP0_STATE_OUTSTATUS; + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + } else if (chan->ep0_state == DWC2_EP0_STATE_INSTATUS) { + chan->ep0_state = DWC2_EP0_STATE_SETUP; + dwc2_urb_waitup(urb); + } + } else if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + } else { + dwc2_urb_waitup(urb); + } + } else if (chan_intstatus & USB_OTG_HCINT_AHBERR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_STALL) { + urb->errorcode = -USB_ERR_STALL; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_NAK) { + urb->errorcode = -USB_ERR_NAK; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_NYET) { + urb->errorcode = -USB_ERR_NAK; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_TXERR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_BBERR) { + urb->errorcode = -USB_ERR_BABBLE; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_DTERR) { + urb->errorcode = -USB_ERR_DT; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_FRMOR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } + USB_OTG_HC(ch_num)->HCINT = chan_intstatus; + } +} + +static void dwc2_outchan_irq_handler(struct usbh_bus *bus, uint8_t ch_num) +{ + uint32_t chan_intstatus; + struct dwc2_chan *chan; + struct usbh_urb *urb; + + chan_intstatus = USB_OTG_HC(ch_num)->HCINT; + + chan = &g_dwc2_hcd[bus->hcd.hcd_id].chan_pool[ch_num]; + urb = chan->urb; + //printf("s2:%08x\r\n", chan_intstatus); + + if (chan_intstatus & USB_OTG_HCINT_CHH) { + if (chan_intstatus & USB_OTG_HCINT_XFRC) { + urb->errorcode = 0; + + uint32_t count = USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ; /* last packet size */ + uint32_t has_used_packets = chan->num_packets - ((USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) >> 19); /* how many packets have used */ + + urb->actual_length += (has_used_packets - 1) * USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize) + count; //the same with urb->actual_length += chan->xferlen; + + uint8_t data_toggle = ((USB_OTG_HC(ch_num)->HCTSIZ & USB_OTG_HCTSIZ_DPID) >> USB_OTG_HCTSIZ_DPID_Pos); + + if (data_toggle == HC_PID_DATA0) { + urb->data_toggle = 0; + } else { + urb->data_toggle = 1; + } + + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) { + if (chan->ep0_state == DWC2_EP0_STATE_SETUP) { + if (urb->setup->wLength) { + if (urb->setup->bmRequestType & 0x80) { + chan->ep0_state = DWC2_EP0_STATE_INDATA; + } else { + chan->ep0_state = DWC2_EP0_STATE_OUTDATA; + } + } else { + chan->ep0_state = DWC2_EP0_STATE_INSTATUS; + } + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + } else if (chan->ep0_state == DWC2_EP0_STATE_OUTDATA) { + chan->ep0_state = DWC2_EP0_STATE_INSTATUS; + dwc2_control_urb_init(bus, ch_num, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + } else if (chan->ep0_state == DWC2_EP0_STATE_OUTSTATUS) { + chan->ep0_state = DWC2_EP0_STATE_SETUP; + dwc2_urb_waitup(urb); + } + } else if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_ISOCHRONOUS) { + } else { + dwc2_urb_waitup(urb); + } + } else if (chan_intstatus & USB_OTG_HCINT_AHBERR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_STALL) { + urb->errorcode = -USB_ERR_STALL; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_NAK) { + urb->errorcode = -USB_ERR_NAK; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_NYET) { + urb->errorcode = -USB_ERR_NAK; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_TXERR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_BBERR) { + urb->errorcode = -USB_ERR_BABBLE; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_DTERR) { + urb->errorcode = -USB_ERR_DT; + dwc2_urb_waitup(urb); + } else if (chan_intstatus & USB_OTG_HCINT_FRMOR) { + urb->errorcode = -USB_ERR_IO; + dwc2_urb_waitup(urb); + } + USB_OTG_HC(ch_num)->HCINT = chan_intstatus; + } +} + +static void dwc2_port_irq_handler(struct usbh_bus *bus) +{ + __IO uint32_t hprt0, hprt0_dup, regval; + + /* Handle Host Port Interrupts */ + hprt0 = USB_OTG_HPRT; + hprt0_dup = USB_OTG_HPRT; + + hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | + USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); + + /* Check whether Port Connect detected */ + if ((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET) { + if ((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS) { + bus->hcd.roothub.int_buffer[0] = (1 << 1); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + hprt0_dup |= USB_OTG_HPRT_PCDET; + g_dwc2_hcd[bus->hcd.hcd_id].port_csc = 1; + } + + /* Check whether Port Enable Changed */ + if ((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG) { + hprt0_dup |= USB_OTG_HPRT_PENCHNG; + g_dwc2_hcd[bus->hcd.hcd_id].port_pec = 1; + + if ((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA) { +#if defined(CONFIG_USB_HS) +#else + if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17)) { + USB_OTG_HOST->HFIR = 6000U; + if ((USB_OTG_HOST->HCFG & USB_OTG_HCFG_FSLSPCS) != USB_OTG_HCFG_FSLSPCS_1) { + regval = USB_OTG_HOST->HCFG; + regval &= ~USB_OTG_HCFG_FSLSPCS; + regval |= USB_OTG_HCFG_FSLSPCS_1; + USB_OTG_HOST->HCFG = regval; + } + } else { + USB_OTG_HOST->HFIR = 48000U; + if ((USB_OTG_HOST->HCFG & USB_OTG_HCFG_FSLSPCS) != USB_OTG_HCFG_FSLSPCS_0) { + regval = USB_OTG_HOST->HCFG; + regval &= ~USB_OTG_HCFG_FSLSPCS; + regval |= USB_OTG_HCFG_FSLSPCS_0; + USB_OTG_HOST->HCFG = regval; + } + } +#endif + } else { + } + } + + /* Check for an overcurrent */ + if ((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG) { + hprt0_dup |= USB_OTG_HPRT_POCCHNG; + g_dwc2_hcd[bus->hcd.hcd_id].port_occ = 1; + } + /* Clear Port Interrupts */ + USB_OTG_HPRT = hprt0_dup; +} + +void USBH_IRQHandler(uint8_t busid) +{ + uint32_t gint_status, chan_int; + struct usbh_bus *bus; + + bus = &g_usbhost_bus[busid]; + gint_status = dwc2_get_glb_intstatus(bus); + if ((USB_OTG_GLB->GINTSTS & 0x1U) == USB_OTG_MODE_HOST) { + /* Avoid spurious interrupt */ + if (gint_status == 0) { + return; + } + + if (gint_status & USB_OTG_GINTSTS_HPRTINT) { + dwc2_port_irq_handler(bus); + } + if (gint_status & USB_OTG_GINTSTS_DISCINT) { + g_dwc2_hcd[bus->hcd.hcd_id].port_csc = 1; + bus->hcd.roothub.int_buffer[0] = (1 << 1); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_DISCINT; + } + if (gint_status & USB_OTG_GINTSTS_HCINT) { + chan_int = (USB_OTG_HOST->HAINT & USB_OTG_HOST->HAINTMSK) & 0xFFFFU; + for (uint8_t i = 0U; i < CONFIG_USBHOST_PIPE_NUM; i++) { + if ((chan_int & (1UL << (i & 0xFU))) != 0U) { + if ((USB_OTG_HC(i)->HCCHAR & USB_OTG_HCCHAR_EPDIR) == USB_OTG_HCCHAR_EPDIR) { + dwc2_inchan_irq_handler(bus, i); + } else { + dwc2_outchan_irq_handler(bus, i); + } + } + } + USB_OTG_GLB->GINTSTS = USB_OTG_GINTSTS_HCINT; + } + } +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/ehci/README.md b/components/drivers/usb/cherryusb/port/ehci/README.md new file mode 100644 index 00000000000..48b9a2b6eb5 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ehci/README.md @@ -0,0 +1,27 @@ +# Note + +## Support Chip List + +### BouffaloLab + +- BouffaloLab BL616/BL808 + +### HPMicro + +- HPM all series + +### AllwinnerTech + +- F133 + +### Nuvoton + +- Nuvoton all series + +### Artinchip + +- d13x, d21x + +### Intel + +- Intel 6 Series Chipset and Intel C200 Series Chipset diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_ehci_priv.h b/components/drivers/usb/cherryusb/port/ehci/usb_ehci_priv.h new file mode 100644 index 00000000000..03fa270c839 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ehci/usb_ehci_priv.h @@ -0,0 +1,76 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _USB_EHCI_PRIV_H +#define _USB_EHCI_PRIV_H + +#include "usbh_core.h" +#include "usbh_hub.h" +#include "usb_hc_ehci.h" + +#define EHCI_HCCR ((struct ehci_hccr *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET)) +#define EHCI_HCOR ((struct ehci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_EHCI_HCCR_OFFSET + g_ehci_hcd[bus->hcd.hcd_id].hcor_offset)) + +#define EHCI_PTR2ADDR(x) ((uint32_t)(uintptr_t)(x) & ~0x1F) +#define EHCI_ADDR2QH(x) ((struct ehci_qh_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F)) +#define EHCI_ADDR2QTD(x) ((struct ehci_qtd_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F)) +#define EHCI_ADDR2ITD(x) ((struct ehci_itd_hw *)(uintptr_t)((uint32_t)(x) & ~0x1F)) + +#ifndef CONFIG_USB_EHCI_QH_NUM +#define CONFIG_USB_EHCI_QH_NUM CONFIG_USBHOST_PIPE_NUM +#endif +#ifndef CONFIG_USB_EHCI_QTD_NUM +#define CONFIG_USB_EHCI_QTD_NUM 3 +#endif +#ifndef CONFIG_USB_EHCI_ITD_NUM +#define CONFIG_USB_EHCI_ITD_NUM 20 +#endif + +extern uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port); + +struct ehci_qtd_hw { + struct ehci_qtd hw; + struct usbh_urb *urb; + uint32_t length; +} __attribute__((aligned(32))); + +struct ehci_qh_hw { + struct ehci_qh hw; + struct ehci_qtd_hw qtd_pool[CONFIG_USB_EHCI_QTD_NUM]; + uint32_t first_qtd; + struct usbh_urb *urb; + usb_osal_sem_t waitsem; + uint8_t remove_in_iaad; +} __attribute__((aligned(32))); + +struct ehci_itd_hw { + struct ehci_itd hw; + struct usbh_urb *urb; + uint16_t start_frame; + uint8_t mf_unmask; + uint8_t mf_valid; + uint32_t pkt_idx[8]; + usb_slist_t list; +} __attribute__((aligned(32))); + +struct ehci_hcd { + bool ehci_qh_used[CONFIG_USB_EHCI_QH_NUM]; + bool ehci_itd_used[CONFIG_USB_EHCI_ITD_NUM]; + bool ppc; /* Port Power Control */ + bool has_tt; /* if use tt instead of Companion Controller */ + uint8_t n_cc; /* Number of Companion Controller */ + uint8_t n_pcc; /* Number of ports supported per companion host controller */ + uint8_t n_ports; + uint8_t hcor_offset; +}; + +extern struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS]; +extern uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USB_EHCI_FRAME_LIST_SIZE, 1024)]; + +int ehci_iso_urb_init(struct usbh_bus *bus, struct usbh_urb *urb); +void ehci_remove_itd_urb(struct usbh_bus *bus, struct usbh_urb *urb); +void ehci_scan_isochronous_list(struct usbh_bus *bus); + +#endif diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c b/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c new file mode 100644 index 00000000000..5445b535aeb --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ehci/usb_glue_aic.c @@ -0,0 +1,181 @@ +/* + * Copyright (c) 2022, Artinchip Technology Co., Ltd + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include "usbh_core.h" +#include "usb_ehci_priv.h" + +extern void USBH_IRQHandler(uint8_t busid); + +static void aic_ehci_isr(int vector, void *arg) +{ + struct usbh_bus *bus = (struct usbh_bus *)arg; + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(bus->hcd.hcd_id); +} + +static void aic_ohci_isr(int vector, void *arg) +{ + struct usbh_bus *bus = (struct usbh_bus *)arg; + extern void OHCI_IRQHandler(uint8_t busid); + OHCI_IRQHandler(bus->hcd.hcd_id); +} + +typedef struct aic_ehci_config { + uint32_t base_addr; + uint32_t clk_id; + uint32_t rst_id; + uint32_t phy_clk_id; + uint32_t phy_rst_id; + uint32_t irq_num; +}aic_ehci_config_t; + +aic_ehci_config_t config[] = { +#ifdef AIC_USING_USB0_HOST + { + USB_HOST0_BASE, + CLK_USBH0, + RESET_USBH0, + CLK_USB_PHY0, + RESET_USBPHY0, + USB_HOST0_EHCI_IRQn + }, +#else + { + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF, + 0xFFFFFFFF + }, +#endif +#ifdef AIC_USING_USB1_HOST + { + USB_HOST1_BASE, + CLK_USBH1, + RESET_USBH1, + CLK_USB_PHY1, + RESET_USBPHY1, + USB_HOST1_EHCI_IRQn + } +#endif +}; + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + uint32_t val; + int i = 0; + + for (i=0; ihcd.reg_base == config[i].base_addr) + break; + } + + if (i == sizeof(config)/sizeof(aic_ehci_config_t)) + return; + + /* set usb0 phy switch: Host/Device */ + if (i == 0) + syscfg_usb_phy0_sw_host(1); + + /* enable clock */ + hal_clk_enable(config[i].phy_clk_id); + hal_clk_enable(config[i].clk_id); + aicos_udelay(300); + hal_reset_assert(config[i].phy_rst_id); + hal_reset_assert(config[i].rst_id); + aicos_udelay(300); + hal_reset_deassert(config[i].phy_rst_id); + hal_reset_deassert(config[i].rst_id); + aicos_udelay(300); + + /* set phy type: UTMI/ULPI */ + val = readl((volatile void *)(unsigned long)(config[i].base_addr+0x800)); +#ifdef FPGA_BOARD_ARTINCHIP + /* fpga phy type = ULPI */ + writel((val & ~0x1U), (volatile void *)(unsigned long)(config[i].base_addr+0x800)); +#else + /* board phy type = UTMI */ + writel((val | 0x1), (volatile void *)(unsigned long)(config[i].base_addr+0x800)); +#endif + + /* Set AHB2STBUS_INSREG01 + Set EHCI packet buffer IN/OUT threshold (in DWORDs) + Must increase the OUT threshold to avoid underrun. (FIFO size - 4) + */ + writel((32 | (127 << 16)), (volatile void *)(unsigned long)(config[i].base_addr+0x94)); + + /* register interrupt callback */ + aicos_request_irq(config[i].irq_num, (irq_handler_t)aic_ehci_isr, + 0, "usb_host_ehci", bus); + aicos_request_irq(config[i].irq_num + 1, (irq_handler_t)aic_ohci_isr, + 0, "usb_host_ohci", bus); + aicos_irq_enable(config[i].irq_num); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + /* Defined by individual manufacturers */ + uint32_t regval; + + regval = EHCI_HCOR->portsc[port-1]; + if ((regval & EHCI_PORTSC_LSTATUS_MASK) == EHCI_PORTSC_LSTATUS_KSTATE) + return USB_SPEED_LOW; + + if (regval & EHCI_PORTSC_PE) + return USB_SPEED_HIGH; + else + return USB_SPEED_FULL; +} + +void usb_ehci_dcache_clean(uintptr_t addr, uint32_t len) +{ + aicos_dcache_clean_range((size_t *)addr, len); +} + +void usb_ehci_dcache_invalidate(uintptr_t addr, uint32_t len) +{ + aicos_dcache_invalid_range((size_t *)addr, len); +} + +void usb_ehci_dcache_clean_invalidate(uintptr_t addr, uint32_t len) +{ + aicos_dcache_clean_invalid_range((size_t *)addr, len); +} + +int usbh_init(void) +{ +#if defined(AIC_USING_USB0_HOST) || defined(AIC_USING_USB1_HOST) + int bus_id = 0; +#endif + +#ifdef AIC_USING_USB0_HOST + usbh_initialize(bus_id, USB_HOST0_BASE); + bus_id++; +#endif + +#ifdef AIC_USING_USB1_HOST + usbh_initialize(bus_id, USB_HOST1_BASE); + bus_id++; +#endif + return 0; +} + +#if defined(KERNEL_RTTHREAD) +#include +#include + +INIT_ENV_EXPORT(usbh_init); + +#if defined (RT_USING_FINSH) +#include + +MSH_CMD_EXPORT_ALIAS(lsusb, lsusb, list usb device); +#endif +#endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_glue_bouffalo.c b/components/drivers/usb/cherryusb/port/ehci/usb_glue_bouffalo.c new file mode 100644 index 00000000000..8f1e87fd1b9 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ehci/usb_glue_bouffalo.c @@ -0,0 +1,143 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "bflb_core.h" +#include "usbh_core.h" +#include "hardware/usb_v2_reg.h" + +#ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE +#error "usb host must enable CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE" +#endif + +#define BLFB_USB_BASE ((uint32_t)0x20072000) +#define BFLB_PDS_BASE ((uint32_t)0x2000e000) + +#define PDS_USB_CTL_OFFSET (0x500) /* usb_ctl */ +#define PDS_USB_PHY_CTRL_OFFSET (0x504) /* usb_phy_ctrl */ + +/* 0x500 : usb_ctl */ +#define PDS_REG_USB_SW_RST_N (1 << 0U) +#define PDS_REG_USB_EXT_SUSP_N (1 << 1U) +#define PDS_REG_USB_WAKEUP (1 << 2U) +#define PDS_REG_USB_L1_WAKEUP (1 << 3U) +#define PDS_REG_USB_DRVBUS_POL (1 << 4U) +#define PDS_REG_USB_IDDIG (1 << 5U) + +/* 0x504 : usb_phy_ctrl */ +#define PDS_REG_USB_PHY_PONRST (1 << 0U) +#define PDS_REG_USB_PHY_OSCOUTEN (1 << 1U) +#define PDS_REG_USB_PHY_XTLSEL_SHIFT (2U) +#define PDS_REG_USB_PHY_XTLSEL_MASK (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT) +#define PDS_REG_USB_PHY_OUTCLKSEL (1 << 4U) +#define PDS_REG_USB_PHY_PLLALIV (1 << 5U) +#define PDS_REG_PU_USB20_PSW (1 << 6U) + +#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C) +#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710) + +extern void USBH_IRQHandler(uint8_t busid); + +void USBH_IRQ(int irq, void *arg) { + USBH_IRQHandler(0); +} + +static void bflb_usb_phy_init(void) +{ + uint32_t regval; + + /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */ + /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */ + /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */ + /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */ + /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */ + /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */ + /* #1.2ms; wait UCLK */ + /* wait(soc616_b0.usb_uclk); */ + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval |= PDS_REG_PU_USB20_PSW; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + regval |= PDS_REG_USB_PHY_PONRST; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET); + + /* greater than 5T */ + bflb_mtimer_delay_us(1); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval &= ~PDS_REG_USB_SW_RST_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + /* greater than 5T */ + bflb_mtimer_delay_us(1); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval |= PDS_REG_USB_EXT_SUSP_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + /* wait UCLK 1.2ms */ + bflb_mtimer_delay_ms(3); + + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval |= PDS_REG_USB_SW_RST_N; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + bflb_mtimer_delay_ms(2); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + uint32_t regval; + + bflb_usb_phy_init(); + + bflb_irq_attach(37, USBH_IRQ, NULL); + bflb_irq_enable(37); + + /* enable device-A for host */ + regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + regval &= ~PDS_REG_USB_IDDIG; + putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET); + + regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET); + regval |= USB_A_BUS_DROP_HOV; + regval &= ~USB_A_BUS_REQ_HOV; + putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET); + + bflb_mtimer_delay_ms(10); + + /* enable vbus and bus control */ + regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET); + regval &= ~USB_A_BUS_DROP_HOV; + regval |= USB_A_BUS_REQ_HOV; + putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET); + + regval = getreg32(BLFB_USB_BASE + USB_GLB_INT_OFFSET); + regval |= USB_MDEV_INT; + regval |= USB_MOTG_INT; + regval &= ~USB_MHC_INT; + putreg32(regval, BLFB_USB_BASE + USB_GLB_INT_OFFSET); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + uint8_t speed = 3; + + speed = (getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT; + + if (speed == 0) { + return USB_SPEED_FULL; + } else if (speed == 1) { + return USB_SPEED_LOW; + } else if (speed == 2) { + return USB_SPEED_HIGH; + } + return USB_SPEED_HIGH; +} diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_glue_hpm.c b/components/drivers/usb/cherryusb/port/ehci/usb_glue_hpm.c new file mode 100644 index 00000000000..f616f2cf0b1 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ehci/usb_glue_hpm.c @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2022-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "usbh_core.h" +#include "hpm_common.h" +#include "hpm_soc.h" +#include "hpm_usb_drv.h" + +#if !defined(CONFIG_USB_EHCI_HPMICRO) || !CONFIG_USB_EHCI_HPMICRO +#error "hpm ehci must set CONFIG_USB_EHCI_HPMICRO=1" +#endif + +#if !defined(CONFIG_USB_EHCI_HCCR_OFFSET) || CONFIG_USB_EHCI_HCCR_OFFSET != 0x100 +#error "hpm ehci must config CONFIG_USB_EHCI_HCCR_OFFSET to 0x100" +#endif + +static uint32_t _hcd_irqnum[CONFIG_USBHOST_MAX_BUS]; +static uint8_t _hcd_busid[CONFIG_USBHOST_MAX_BUS]; + +static void usb_host_mode_init(USB_Type *ptr) +{ + /* Set mode to host, must be set immediately after reset */ + ptr->USBMODE &= ~USB_USBMODE_CM_MASK; + ptr->USBMODE |= USB_USBMODE_CM_SET(3); + + /* Set the endian */ + ptr->USBMODE &= ~USB_USBMODE_ES_MASK; + + /* Set parallel interface signal */ + ptr->PORTSC1 &= ~USB_PORTSC1_STS_MASK; + + /* Set parallel transceiver width */ + ptr->PORTSC1 &= ~USB_PORTSC1_PTW_MASK; + + /* Not use interrupt threshold. */ + ptr->USBCMD &= ~USB_USBCMD_ITC_MASK; +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + if (bus->hcd.reg_base == HPM_USB0_BASE) { + _hcd_irqnum[bus->hcd.hcd_id] = IRQn_USB0; + _hcd_busid[0] = bus->hcd.hcd_id; + } else { +#ifdef HPM_USB1_BASE + if (bus->hcd.reg_base == HPM_USB1_BASE) { + _hcd_irqnum[bus->hcd.hcd_id] = IRQn_USB1; + _hcd_busid[1] = bus->hcd.hcd_id; + } +#endif + } + + usb_phy_init((USB_Type *)(bus->hcd.reg_base)); + intc_m_enable_irq(_hcd_irqnum[bus->hcd.hcd_id]); +} + +void usb_hc_low_level2_init(struct usbh_bus *bus) +{ + usb_host_mode_init((USB_Type *)(bus->hcd.reg_base)); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + (void)port; + uint8_t speed; + + speed = usb_get_port_speed((USB_Type *)(bus->hcd.reg_base)); + + if (speed == 0x00) { + return USB_SPEED_FULL; + } + if (speed == 0x01) { + return USB_SPEED_LOW; + } + if (speed == 0x02) { + return USB_SPEED_HIGH; + } + + return 0; +} + +extern void USBH_IRQHandler(uint8_t busid); + +void isr_usbh0(void) +{ + USBH_IRQHandler(_hcd_busid[0]); +} +SDK_DECLARE_EXT_ISR_M(IRQn_USB0, isr_usbh0) + +#ifdef HPM_USB1_BASE +void isr_usbh1(void) +{ + USBH_IRQHandler(_hcd_busid[1]); +} +SDK_DECLARE_EXT_ISR_M(IRQn_USB1, isr_usbh1) +#endif diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_glue_intel.c b/components/drivers/usb/cherryusb/port/ehci/usb_glue_intel.c new file mode 100644 index 00000000000..74ed37862ec --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ehci/usb_glue_intel.c @@ -0,0 +1,55 @@ +#ifdef __rtems__ + +#include +#include +#include +#include "usbh_core.h" + +uint32_t echi_base; +static int ehci_bus; +static int ehci_slot; +static int ehci_function; +static int ehci_vector; + +extern void USBH_IRQHandler(uint8_t busid); + +void ehci_pci_scan(int bus, int slot, int fun, int vector) +{ + ehci_bus = bus; + ehci_slot = slot; + ehci_function = fun; + ehci_vector = vector; + pci_read_config_dword(bus, slot, fun, PCI_BASE_ADDRESS_0, &echi_base); +} +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + //set software own ehci + uint32_t legacy_val; + pci_write_config_dword(ehci_bus, ehci_slot, ehci_function, 0x68, 1 << 24); + pci_read_config_dword(ehci_bus, ehci_slot, ehci_function, 0x68, &legacy_val); + if ((legacy_val & 0x01010000) == 0x01000000) + printf("OS owned echi\n"); + else + printf("BIOS owned echi\n"); + + rtems_status_code sc; + sc = rtems_interrupt_handler_install( + ehci_vector, + "USBirq", + RTEMS_INTERRUPT_SHARED, + USBH_IRQHandler, + (void *)0); + + if (sc != RTEMS_SUCCESSFUL) { + printf("USB install isr falied,%s\n", rtems_status_text(sc)); + return; + } +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + printf("USB_SPEED_HIGH present\n"); + return USB_SPEED_HIGH; +} + +#endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_glue_ma35d0.c b/components/drivers/usb/cherryusb/port/ehci/usb_glue_ma35d0.c new file mode 100644 index 00000000000..76e621ef96a --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ehci/usb_glue_ma35d0.c @@ -0,0 +1,117 @@ +/**************************************************************************/ /** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2023-8-8 Wayne First version +* +******************************************************************************/ +#include "rtthread.h" + +#include "NuMicro.h" +#include "rthw.h" +#include "drv_sys.h" + +#define LOG_TAG "drv.cherry" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_LOG +#define DBG_COLOR +#include + +#if defined(PKG_CHERRYUSB_HOST) + +#include "usbh_core.h" + +static void nu_echi_isr(int vector, void *param) +{ + uint8_t busid = (uint8_t)param; + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(busid); +} + +static void nu_ochi_isr(int vector, void *param) +{ +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + int timeout = 100; + + if (bus->hcd.reg_base == HSUSBH0_BASE) { + /* Enable USBH clock */ + CLK_EnableModuleClock(HUSBH0_MODULE); + SYS_ResetModule(HSUSBH0_RST); + + /* Clock engine clock Configuration */ + SYS->USBPMISCR &= ~(SYS_USBPMISCR_PHY0POR_Msk | SYS_USBPMISCR_PHY0COMN_Msk); + rt_thread_mdelay(20); + SYS->USBPMISCR |= SYS_USBPMISCR_PHY0SUSPEND_Msk | SYS_USBPMISCR_PHY0COMN_Msk; + + /* set UHOVRCURH(SYS_MISCFCR0[12]) 1 => USBH Host over-current detect is high-active */ + /* 0 => USBH Host over-current detect is low-active */ + //SYS->MISCFCR0 |= SYS_MISCFCR0_UHOVRCURH_Msk; + SYS->MISCFCR0 &= ~SYS_MISCFCR0_UHOVRCURH_Msk; + while (1) { + rt_thread_mdelay(1); + if ((SYS->USBPMISCR & SYS_USBPMISCR_PHY0HSTCKSTB_Msk) &&) + break; /* both USB PHY0 and PHY1 clock 60MHz UTMI clock stable */ + + timeout--; + if (timeout == 0) { + rt_kprintf("USB PHY reset failed. USBPMISCR = 0x%08x\n", SYS->USBPMISCR); + return; + } + } + + /* Register interrupt service routine. */ + rt_hw_interrupt_install(HSUSBH0_IRQn, nu_echi_isr, (void *)bus->hcd.hcd_id, "ehci0"); + + /* Enable interrupt */ + rt_hw_interrupt_umask(HSUSBH0_IRQn); + } else if (bus->hcd.reg_base == HSUSBH1_BASE) { + /* Enable USBH clock */ + CLK_EnableModuleClock(HUSBH1_MODULE); + SYS_ResetModule(HSUSBH1_RST); + + /* Clock engine clock Configuration */ + SYS->USBPMISCR &= ~(SYS_USBPMISCR_PHY1POR_Msk | SYS_USBPMISCR_PHY1COMN_Msk); + rt_thread_mdelay(20); + SYS->USBPMISCR |= SYS_USBPMISCR_PHY1SUSPEND_Msk | SYS_USBPMISCR_PHY1COMN_Msk; + + /* set UHOVRCURH(SYS_MISCFCR0[12]) 1 => USBH Host over-current detect is high-active */ + /* 0 => USBH Host over-current detect is low-active */ + //SYS->MISCFCR0 |= SYS_MISCFCR0_UHOVRCURH_Msk; + SYS->MISCFCR0 &= ~SYS_MISCFCR0_UHOVRCURH_Msk; + while (1) { + rt_thread_mdelay(1); + if ((SYS->USBPMISCR & SYS_USBPMISCR_PHY1HSTCKSTB_Msk)) + break; /* both USB PHY0 and PHY1 clock 60MHz UTMI clock stable */ + + timeout--; + if (timeout == 0) { + rt_kprintf("USB PHY reset failed. USBPMISCR = 0x%08x\n", SYS->USBPMISCR); + return; + } + } + /* Register interrupt service routine. */ + rt_hw_interrupt_install(HSUSBH1_IRQn, nu_echi_isr, (void *)bus->hcd.hcd_id, "ehci1"); + + /* Enable interrupt */ + rt_hw_interrupt_umask(HSUSBH1_IRQn); + } +} + +void usb_hc_low_level2_init(struct usbh_bus *bus) +{ +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + return USB_SPEED_HIGH; +} + +#endif diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_glue_nuc980.c b/components/drivers/usb/cherryusb/port/ehci/usb_glue_nuc980.c new file mode 100644 index 00000000000..4b8a8b3379f --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ehci/usb_glue_nuc980.c @@ -0,0 +1,62 @@ +/**************************************************************************/ /** +* +* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved. +* +* SPDX-License-Identifier: Apache-2.0 +* +* Change Logs: +* Date Author Notes +* 2023-8-8 Wayne First version +* +******************************************************************************/ +#include "rtthread.h" + +#include "NuMicro.h" +#include "rthw.h" +#include "drv_sys.h" + +#define LOG_TAG "drv.cherry" +#define DBG_ENABLE +#define DBG_SECTION_NAME LOG_TAG +#define DBG_LEVEL DBG_LOG +#define DBG_COLOR +#include + +#if defined(PKG_CHERRYUSB_HOST) +#include "usbh_core.h" + +static void nu_ehci_isr(int vector, void *param) +{ + extern void USBH_IRQHandler(uint8_t busid); + USBH_IRQHandler(0); +} + +void usb_hc_low_level_init(struct usbh_bus *bus) +{ + LOG_D("%s %d", __FUNCTION__, __LINE__); + + rt_hw_interrupt_mask(IRQ_EHCI); + + /* Enable USBH clock */ + nu_sys_ipclk_enable(USBHCKEN); + nu_sys_ip_reset(USBHRST); + + outpw(0xB0015000 + 0xC4, 0x160); //HSUSBH->USBPCR0 = 0x160; /* enable PHY 0 */ + outpw(0xB0015000 + 0xC8, 0x520); //HSUSBH->USBPCR1 = 0x520; /* enable PHY 1 */ + + //USBH->HcMiscControl |= USBH_HcMiscControl_OCAL_Msk; /* Over-current active low */ + //outpw(0xB0017000 + 0x204, inpw(0xB0017000 + 0x204) | (0x1ul << 3)); + + //USBH->HcMiscControl &= ~USBH_HcMiscControl_OCAL_Msk; /* Over-current active high */ + outpw(0xB0017000 + 0x204, inpw(0xB0017000 + 0x204) & (~(0x1ul << 3))); + + rt_hw_interrupt_install(IRQ_EHCI, nu_ehci_isr, NULL, "ehci-1"); + rt_hw_interrupt_set_priority(IRQ_EHCI, IRQ_LEVEL_1); + rt_hw_interrupt_umask(IRQ_EHCI); +} + +uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + return USB_SPEED_HIGH; +} +#endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c b/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c new file mode 100644 index 00000000000..41c8f46db87 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.c @@ -0,0 +1,1371 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_ehci_priv.h" +#ifdef CONFIG_USB_EHCI_WITH_OHCI +#include "usb_ohci_priv.h" +#endif + +#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */ +#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */ +#define EHCI_TUNE_RL_TT 0 +#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */ +#define EHCI_TUNE_MULT_TT 1 + +struct ehci_hcd g_ehci_hcd[CONFIG_USBHOST_MAX_BUS]; + +USB_NOCACHE_RAM_SECTION struct ehci_qh_hw ehci_qh_pool[CONFIG_USBHOST_MAX_BUS][CONFIG_USB_EHCI_QH_NUM]; + +/* The head of the asynchronous queue */ +USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_async_qh_head[CONFIG_USBHOST_MAX_BUS]; +/* The head of the periodic queue */ +USB_NOCACHE_RAM_SECTION struct ehci_qh_hw g_periodic_qh_head[CONFIG_USBHOST_MAX_BUS]; + +/* The frame list */ +USB_NOCACHE_RAM_SECTION uint32_t g_framelist[CONFIG_USBHOST_MAX_BUS][USB_ALIGN_UP(CONFIG_USB_EHCI_FRAME_LIST_SIZE, 1024)] __attribute__((aligned(4096))); + +static struct ehci_qh_hw *ehci_qh_alloc(struct usbh_bus *bus) +{ + struct ehci_qh_hw *qh; + struct ehci_qtd_hw *qtd; + size_t flags; + + for (uint32_t i = 0; i < CONFIG_USB_EHCI_QH_NUM; i++) { + if (!g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i]) { + flags = usb_osal_enter_critical_section(); + g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i] = true; + usb_osal_leave_critical_section(flags); + + qh = &ehci_qh_pool[bus->hcd.hcd_id][i]; + memset(&qh->hw, 0, sizeof(struct ehci_qh)); + qh->hw.hlp = QTD_LIST_END; + qh->hw.overlay.next_qtd = QTD_LIST_END; + qh->hw.overlay.alt_next_qtd = QTD_LIST_END; + qh->urb = NULL; + + for (uint32_t j = 0; j < CONFIG_USB_EHCI_QTD_NUM; j++) { + qtd = &qh->qtd_pool[j]; + qtd->hw.next_qtd = QTD_LIST_END; + qtd->hw.alt_next_qtd = QTD_LIST_END; + qtd->hw.token = QTD_TOKEN_STATUS_HALTED; + qtd->urb = NULL; + } + + return qh; + } + } + return NULL; +} + +static void ehci_qh_free(struct usbh_bus *bus, struct ehci_qh_hw *qh) +{ + size_t flags; + + for (uint32_t i = 0; i < CONFIG_USB_EHCI_QH_NUM; i++) { + if (&ehci_qh_pool[bus->hcd.hcd_id][i] == qh) { + flags = usb_osal_enter_critical_section(); + g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[i] = false; + usb_osal_leave_critical_section(flags); + + qh->urb = NULL; + return; + } + } +} + +static inline void ehci_qh_add_head(struct ehci_qh_hw *head, struct ehci_qh_hw *n) +{ + n->hw.hlp = head->hw.hlp; + head->hw.hlp = QH_HLP_QH(n); +} + +static inline void ehci_qh_remove(struct ehci_qh_hw *head, struct ehci_qh_hw *n) +{ + struct ehci_qh_hw *tmp = head; + + while (EHCI_ADDR2QH(tmp->hw.hlp) && EHCI_ADDR2QH(tmp->hw.hlp) != n) { + tmp = EHCI_ADDR2QH(tmp->hw.hlp); + } + + if (tmp) { + tmp->hw.hlp = n->hw.hlp; + } +} + +static int ehci_caculate_smask(int binterval) +{ + int order, interval; + + interval = 1; + while (binterval > 1) { + interval *= 2; + binterval--; + } + + if (interval < 2) /* interval 1 */ + return 0xFF; + if (interval < 4) /* interval 2 */ + return 0x55; + if (interval < 8) /* interval 4 */ + return 0x22; + for (order = 0; (interval > 1); order++) { + interval >>= 1; + } + return (0x1 << (order % 8)); +} + +static void ehci_qh_fill(struct ehci_qh_hw *qh, + uint8_t dev_addr, + uint8_t ep_addr, + uint8_t ep_type, + uint16_t ep_mps, + uint8_t ep_mult, + uint8_t ep_interval, + uint8_t speed, + uint8_t hubaddr, + uint8_t hubport) +{ + uint32_t epchar = 0; + uint32_t epcap = 0; + + /* QH endpoint characteristics: + * + * FIELD DESCRIPTION + * -------- ------------------------------- + * DEVADDR Device address + * I Inactivate on Next Transaction + * ENDPT Endpoint number + * EPS Endpoint speed + * DTC Data toggle control + * MAXPKT Max packet size + * C Control endpoint + * RL NAK count reloaded + */ + + /* QH endpoint capabilities + * + * FIELD DESCRIPTION + * -------- ------------------------------- + * SSMASK Interrupt Schedule Mask + * SCMASK Split Completion Mask + * HUBADDR Hub Address + * PORT Port number + * MULT High band width multiplier + */ + + epchar |= ((ep_addr & 0xf) << QH_EPCHAR_ENDPT_SHIFT); + epchar |= (dev_addr << QH_EPCHAR_DEVADDR_SHIFT); + epchar |= (ep_mps << QH_EPCHAR_MAXPKT_SHIFT); + + if (ep_type == USB_ENDPOINT_TYPE_CONTROL) { + epchar |= QH_EPCHAR_DTC; /* toggle from qtd */ + } + + switch (speed) { + case USB_SPEED_LOW: + epchar |= QH_EPCHAR_EPS_LOW; + case USB_SPEED_FULL: + if (ep_type == USB_ENDPOINT_TYPE_CONTROL) { + epchar |= QH_EPCHAR_C; /* for TT */ + } + + if (ep_type != USB_ENDPOINT_TYPE_INTERRUPT) { + epchar |= (EHCI_TUNE_RL_TT << QH_EPCHAR_RL_SHIFT); + } + + epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_TT); + + epcap |= QH_EPCAPS_HUBADDR(hubaddr); + epcap |= QH_EPCAPS_PORT(hubport); + + if (ep_type == USB_ENDPOINT_TYPE_INTERRUPT) { + epcap |= QH_EPCAPS_SSMASK(2); + epcap |= QH_EPCAPS_SCMASK(0x78); + } + + break; + case USB_SPEED_HIGH: + epchar |= QH_EPCHAR_EPS_HIGH; + if (ep_type == USB_ENDPOINT_TYPE_CONTROL) { + epchar |= (EHCI_TUNE_RL_HS << QH_EPCHAR_RL_SHIFT); + + epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS); + } else if (ep_type == USB_ENDPOINT_TYPE_BULK) { + epcap |= QH_EPCAPS_MULT(EHCI_TUNE_MULT_HS); + } else { + /* only for interrupt ep */ + epcap |= QH_EPCAPS_MULT(ep_mult); + epcap |= ehci_caculate_smask(ep_interval); + } + break; + + default: + break; + } + + qh->hw.epchar = epchar; + qh->hw.epcap = epcap; +} + +static void ehci_qtd_bpl_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen) +{ + uint32_t rest; + + qtd->hw.bpl[0] = bufaddr; + rest = 0x1000 - (bufaddr & 0xfff); + + if (buflen < rest) { + rest = buflen; + } else { + bufaddr += 0x1000; + bufaddr &= ~0x0fff; + + for (int i = 1; rest < buflen && i < 5; i++) { + qtd->hw.bpl[i] = bufaddr; + bufaddr += 0x1000; + + if ((rest + 0x1000) < buflen) { + rest += 0x1000; + } else { + rest = buflen; + } + } + } +} + +static void ehci_qtd_fill(struct ehci_qtd_hw *qtd, uint32_t bufaddr, size_t buflen, uint32_t token) +{ + /* qTD token + * + * FIELD DESCRIPTION + * -------- ------------------------------- + * STATUS Status + * PID PID Code + * CERR Error Counter + * CPAGE Current Page + * IOC Interrupt on complete + * NBYTES Total Bytes to Transfer + * TOGGLE Data Toggle + */ + + qtd->hw.token = token; + + ehci_qtd_bpl_fill(qtd, bufaddr, buflen); + qtd->length = buflen; +} + +static struct ehci_qh_hw *ehci_control_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen) +{ + struct ehci_qh_hw *qh = NULL; + struct ehci_qtd_hw *qtd_setup = NULL; + struct ehci_qtd_hw *qtd_data = NULL; + struct ehci_qtd_hw *qtd_status = NULL; + uint32_t token; + size_t flags; + + qh = ehci_qh_alloc(bus); + if (qh == NULL) { + return NULL; + } + + qtd_setup = &qh->qtd_pool[0]; + qtd_data = &qh->qtd_pool[1]; + qtd_status = &qh->qtd_pool[2]; + + ehci_qh_fill(qh, + urb->hport->dev_addr, + urb->ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes), + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + 0, + 0, + urb->hport->speed, + urb->hport->parent->hub_addr, + urb->hport->port); + + /* fill setup qtd */ + token = QTD_TOKEN_STATUS_ACTIVE | + QTD_TOKEN_PID_SETUP | + ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) | + ((uint32_t)8 << QTD_TOKEN_NBYTES_SHIFT); + + ehci_qtd_fill(qtd_setup, (uintptr_t)setup, 8, token); + qtd_setup->urb = urb; + + /* fill data qtd */ + if (setup->wLength > 0) { + if ((setup->bmRequestType & 0x80) == 0x80) { + token = QTD_TOKEN_PID_IN; + } else { + token = QTD_TOKEN_PID_OUT; + } + token |= QTD_TOKEN_STATUS_ACTIVE | + QTD_TOKEN_PID_OUT | + QTD_TOKEN_TOGGLE | + ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) | + ((uint32_t)buflen << QTD_TOKEN_NBYTES_SHIFT); + + ehci_qtd_fill(qtd_data, (uintptr_t)buffer, buflen, token); + qtd_data->urb = urb; + qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_data); + qtd_data->hw.next_qtd = EHCI_PTR2ADDR(qtd_status); + } else { + qtd_setup->hw.next_qtd = EHCI_PTR2ADDR(qtd_status); + } + + /* fill status qtd */ + if ((setup->bmRequestType & 0x80) == 0x80) { + token = QTD_TOKEN_PID_OUT; + } else { + token = QTD_TOKEN_PID_IN; + } + token |= QTD_TOKEN_STATUS_ACTIVE | + QTD_TOKEN_TOGGLE | + QTD_TOKEN_IOC | + ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) | + ((uint32_t)0 << QTD_TOKEN_NBYTES_SHIFT); + + ehci_qtd_fill(qtd_status, 0, 0, token); + qtd_status->urb = urb; + qtd_status->hw.next_qtd = QTD_LIST_END; + + /* update qh first qtd */ + qh->hw.curr_qtd = EHCI_PTR2ADDR(qtd_setup); + qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(qtd_setup); + + /* record qh first qtd */ + qh->first_qtd = EHCI_PTR2ADDR(qtd_setup); + + flags = usb_osal_enter_critical_section(); + + qh->urb = urb; + urb->hcpriv = qh; + /* add qh into async list */ + ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh); + + EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN; + + usb_osal_leave_critical_section(flags); + return qh; +} + +static struct ehci_qh_hw *ehci_bulk_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + struct ehci_qh_hw *qh = NULL; + struct ehci_qtd_hw *qtd = NULL; + struct ehci_qtd_hw *first_qtd = NULL; + struct ehci_qtd_hw *prev_qtd = NULL; + uint32_t qtd_num = 0; + uint32_t xfer_len = 0; + uint32_t token; + size_t flags; + + qh = ehci_qh_alloc(bus); + if (qh == NULL) { + return NULL; + } + + ehci_qh_fill(qh, + urb->hport->dev_addr, + urb->ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes), + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + 0, + 0, + urb->hport->speed, + urb->hport->parent->hub_addr, + urb->hport->port); + + while (buflen >= 0) { + qtd = &qh->qtd_pool[qtd_num]; + + if (buflen > 0x4000) { + xfer_len = 0x4000; + buflen -= 0x4000; + } else { + xfer_len = buflen; + buflen = 0; + } + + if (urb->ep->bEndpointAddress & 0x80) { + token = QTD_TOKEN_PID_IN; + } else { + token = QTD_TOKEN_PID_OUT; + } + + token |= QTD_TOKEN_STATUS_ACTIVE | + ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) | + ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT); + + if (buflen == 0) { + token |= QTD_TOKEN_IOC; + } + + ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token); + qtd->urb = urb; + qtd->hw.next_qtd = QTD_LIST_END; + buffer += xfer_len; + + if (prev_qtd) { + prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd); + } else { + first_qtd = qtd; + } + prev_qtd = qtd; + + if (buflen == 0) { + break; + } + qtd_num++; + + if (qtd_num == CONFIG_USB_EHCI_QTD_NUM) { + return NULL; + } + } + + /* update qh first qtd */ + qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd); + qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd); + + /* update data toggle */ + if (urb->data_toggle) { + qh->hw.overlay.token = QTD_TOKEN_TOGGLE; + } else { + qh->hw.overlay.token = 0; + } + + /* record qh first qtd */ + qh->first_qtd = EHCI_PTR2ADDR(first_qtd); + + flags = usb_osal_enter_critical_section(); + + qh->urb = urb; + urb->hcpriv = qh; + /* add qh into async list */ + ehci_qh_add_head(&g_async_qh_head[bus->hcd.hcd_id], qh); + + EHCI_HCOR->usbcmd |= EHCI_USBCMD_ASEN; + + usb_osal_leave_critical_section(flags); + return qh; +} + +static struct ehci_qh_hw *ehci_intr_urb_init(struct usbh_bus *bus, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + struct ehci_qh_hw *qh = NULL; + struct ehci_qtd_hw *qtd = NULL; + struct ehci_qtd_hw *first_qtd = NULL; + struct ehci_qtd_hw *prev_qtd = NULL; + uint32_t qtd_num = 0; + uint32_t xfer_len = 0; + uint32_t token; + size_t flags; + + qh = ehci_qh_alloc(bus); + if (qh == NULL) { + return NULL; + } + + ehci_qh_fill(qh, + urb->hport->dev_addr, + urb->ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes), + USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize), + USB_GET_MULT(urb->ep->wMaxPacketSize) + 1, + urb->ep->bInterval, + urb->hport->speed, + urb->hport->parent->hub_addr, + urb->hport->port); + + while (buflen >= 0) { + qtd = &qh->qtd_pool[qtd_num]; + + if (buflen > 0x4000) { + xfer_len = 0x4000; + buflen -= 0x4000; + } else { + xfer_len = buflen; + buflen = 0; + } + + if (urb->ep->bEndpointAddress & 0x80) { + token = QTD_TOKEN_PID_IN; + } else { + token = QTD_TOKEN_PID_OUT; + } + + token |= QTD_TOKEN_STATUS_ACTIVE | + ((uint32_t)EHCI_TUNE_CERR << QTD_TOKEN_CERR_SHIFT) | + ((uint32_t)xfer_len << QTD_TOKEN_NBYTES_SHIFT); + + if (buflen == 0) { + token |= QTD_TOKEN_IOC; + } + + ehci_qtd_fill(qtd, (uintptr_t)buffer, xfer_len, token); + qtd->urb = urb; + qtd->hw.next_qtd = QTD_LIST_END; + buffer += xfer_len; + + if (prev_qtd) { + prev_qtd->hw.next_qtd = EHCI_PTR2ADDR(qtd); + } else { + first_qtd = qtd; + } + prev_qtd = qtd; + + if (buflen == 0) { + break; + } + qtd_num++; + + if (qtd_num == CONFIG_USB_EHCI_QTD_NUM) { + return NULL; + } + } + + /* update qh first qtd */ + qh->hw.curr_qtd = EHCI_PTR2ADDR(first_qtd); + qh->hw.overlay.next_qtd = EHCI_PTR2ADDR(first_qtd); + + /* update data toggle */ + if (urb->data_toggle) { + qh->hw.overlay.token = QTD_TOKEN_TOGGLE; + } else { + qh->hw.overlay.token = 0; + } + + /* record qh first qtd */ + qh->first_qtd = EHCI_PTR2ADDR(first_qtd); + + flags = usb_osal_enter_critical_section(); + + qh->urb = urb; + urb->hcpriv = qh; + /* add qh into periodic list */ + ehci_qh_add_head(&g_periodic_qh_head[bus->hcd.hcd_id], qh); + + EHCI_HCOR->usbcmd |= EHCI_USBCMD_PSEN; + + usb_osal_leave_critical_section(flags); + return qh; +} + +static void ehci_urb_waitup(struct usbh_bus *bus, struct usbh_urb *urb) +{ + struct ehci_qh_hw *qh; + + qh = (struct ehci_qh_hw *)urb->hcpriv; + qh->urb = NULL; + urb->hcpriv = NULL; + + qh->remove_in_iaad = 0; + + if (urb->timeout) { + usb_osal_sem_give(qh->waitsem); + } else { + ehci_qh_free(bus, qh); + } + + if (urb->complete) { + if (urb->errorcode < 0) { + urb->complete(urb->arg, urb->errorcode); + } else { + urb->complete(urb->arg, urb->actual_length); + } + } +} + +static void ehci_qh_scan_qtds(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh) +{ + struct ehci_qtd_hw *qtd; + + ehci_qh_remove(qhead, qh); + + qtd = EHCI_ADDR2QTD(qh->first_qtd); + + while (qtd) { + qtd->urb->actual_length += (qtd->length - ((qtd->hw.token & QTD_TOKEN_NBYTES_MASK) >> QTD_TOKEN_NBYTES_SHIFT)); + + qh->first_qtd = qtd->hw.next_qtd; + qtd = EHCI_ADDR2QTD(qh->first_qtd); + } +} + +static void ehci_check_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh) +{ + struct usbh_urb *urb; + struct ehci_qtd_hw *qtd; + uint32_t token; + + qtd = EHCI_ADDR2QTD(qh->first_qtd); + + if (qtd == NULL) { + return; + } + + while (qtd) { + token = qtd->hw.token; + + if (token & QTD_TOKEN_STATUS_ERRORS) { + break; + } else if (token & QTD_TOKEN_STATUS_ACTIVE) { + return; + } + + qtd = EHCI_ADDR2QTD(qtd->hw.next_qtd); + } + + urb = qh->urb; + + if ((token & QTD_TOKEN_STATUS_ERRORS) == 0) { + if (token & QTD_TOKEN_TOGGLE) { + urb->data_toggle = true; + } else { + urb->data_toggle = false; + } + urb->errorcode = 0; + } else { + if (token & QTD_TOKEN_STATUS_BABBLE) { + urb->errorcode = -USB_ERR_BABBLE; + urb->data_toggle = 0; + } else if (token & QTD_TOKEN_STATUS_HALTED) { + urb->errorcode = -USB_ERR_STALL; + urb->data_toggle = 0; + } else if (token & (QTD_TOKEN_STATUS_DBERR | QTD_TOKEN_STATUS_XACTERR)) { + urb->errorcode = -USB_ERR_IO; + } + } + + ehci_qh_scan_qtds(bus, qhead, qh); + + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + ehci_urb_waitup(bus, urb); + } else { + qh->remove_in_iaad = 1; + + EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD; + } +} + +static void ehci_kill_qh(struct usbh_bus *bus, struct ehci_qh_hw *qhead, struct ehci_qh_hw *qh) +{ + struct ehci_qtd_hw *qtd; + + ehci_qh_remove(qhead, qh); + + qtd = EHCI_ADDR2QTD(qh->first_qtd); + + while (qtd) { + qh->first_qtd = qtd->hw.next_qtd; + qtd = EHCI_ADDR2QTD(qh->first_qtd); + } +} + +static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port) +{ + volatile uint32_t timeout = 0; + uint32_t regval; + +#if defined(CONFIG_USB_EHCI_HPMICRO) && CONFIG_USB_EHCI_HPMICRO + if ((*(volatile uint32_t *)(bus->hcd.reg_base + 0x224) & 0xc0) == (2 << 6)) { /* Hardcode for hpm */ + EHCI_HCOR->portsc[port - 1] |= (1 << 29); + } else { + EHCI_HCOR->portsc[port - 1] &= ~(1 << 29); + } +#endif + regval = EHCI_HCOR->portsc[port - 1]; + regval &= ~EHCI_PORTSC_PE; + regval |= EHCI_PORTSC_RESET; + EHCI_HCOR->portsc[port - 1] = regval; + usb_osal_msleep(55); + + EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESET; + while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESET) != 0) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + return -USB_ERR_TIMEOUT; + } + } + + return 0; +} + +__WEAK void usb_hc_low_level_init(struct usbh_bus *bus) +{ +} + +__WEAK void usb_hc_low_level2_init(struct usbh_bus *bus) +{ +} + +__WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ +} + +int usb_hc_init(struct usbh_bus *bus) +{ + struct ehci_qh_hw *qh; + + volatile uint32_t timeout = 0; + uint32_t regval; + + memset(&g_ehci_hcd[bus->hcd.hcd_id], 0, sizeof(struct ehci_hcd)); + memset(ehci_qh_pool[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw) * CONFIG_USB_EHCI_QH_NUM); + + for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { + qh = &ehci_qh_pool[bus->hcd.hcd_id][index]; + if ((uint32_t)&qh->hw % 32) { + USB_LOG_ERR("struct ehci_qh_hw is not align 32\r\n"); + return -USB_ERR_INVAL; + } + for (uint8_t i = 0; i < CONFIG_USB_EHCI_QTD_NUM; i++) { + if ((uint32_t)&qh->qtd_pool[i] % 32) { + USB_LOG_ERR("struct ehci_qtd_hw is not align 32\r\n"); + return -USB_ERR_INVAL; + } + } + } + + for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { + qh = &ehci_qh_pool[bus->hcd.hcd_id][index]; + qh->waitsem = usb_osal_sem_create(0); + } + + memset(&g_async_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw)); + g_async_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_QH(&g_async_qh_head[bus->hcd.hcd_id]); + g_async_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCHAR_H; + g_async_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END; + g_async_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END; + g_async_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED; + g_async_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END; + + memset(g_framelist[bus->hcd.hcd_id], 0, sizeof(uint32_t) * CONFIG_USB_EHCI_FRAME_LIST_SIZE); + + memset(&g_periodic_qh_head[bus->hcd.hcd_id], 0, sizeof(struct ehci_qh_hw)); + g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp = QH_HLP_END; + g_periodic_qh_head[bus->hcd.hcd_id].hw.epchar = QH_EPCAPS_SSMASK(1); + g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.next_qtd = QTD_LIST_END; + g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.alt_next_qtd = QTD_LIST_END; + g_periodic_qh_head[bus->hcd.hcd_id].hw.overlay.token = QTD_TOKEN_STATUS_HALTED; + g_periodic_qh_head[bus->hcd.hcd_id].first_qtd = QTD_LIST_END; + + for (uint32_t i = 0; i < CONFIG_USB_EHCI_FRAME_LIST_SIZE; i++) { + g_framelist[bus->hcd.hcd_id][i] = QH_HLP_QH(&g_periodic_qh_head[bus->hcd.hcd_id]); + } + + usb_hc_low_level_init(bus); + + USB_LOG_INFO("EHCI HCIVERSION:0x%04x\r\n", (unsigned int)EHCI_HCCR->hciversion); + USB_LOG_INFO("EHCI HCSPARAMS:0x%06x\r\n", (unsigned int)EHCI_HCCR->hcsparams); + USB_LOG_INFO("EHCI HCCPARAMS:0x%04x\r\n", (unsigned int)EHCI_HCCR->hccparams); + + g_ehci_hcd[bus->hcd.hcd_id].ppc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_PPC) ? true : false; + g_ehci_hcd[bus->hcd.hcd_id].n_ports = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPORTS_MASK) >> EHCI_HCSPARAMS_NPORTS_SHIFT; + g_ehci_hcd[bus->hcd.hcd_id].n_cc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NCC_MASK) >> EHCI_HCSPARAMS_NCC_SHIFT; + g_ehci_hcd[bus->hcd.hcd_id].n_pcc = (EHCI_HCCR->hcsparams & EHCI_HCSPARAMS_NPCC_MASK) >> EHCI_HCSPARAMS_NPCC_SHIFT; + g_ehci_hcd[bus->hcd.hcd_id].has_tt = g_ehci_hcd[bus->hcd.hcd_id].n_cc ? false : true; + g_ehci_hcd[bus->hcd.hcd_id].hcor_offset = EHCI_HCCR->caplength; + + USB_LOG_INFO("EHCI ppc:%u, n_ports:%u, n_cc:%u, n_pcc:%u\r\n", + g_ehci_hcd[bus->hcd.hcd_id].ppc, + g_ehci_hcd[bus->hcd.hcd_id].n_ports, + g_ehci_hcd[bus->hcd.hcd_id].n_cc, + g_ehci_hcd[bus->hcd.hcd_id].n_pcc); + + EHCI_HCOR->usbcmd |= EHCI_USBCMD_HCRESET; + while (EHCI_HCOR->usbcmd & EHCI_USBCMD_HCRESET) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + return -USB_ERR_TIMEOUT; + } + } + + usb_hc_low_level2_init(bus); + + EHCI_HCOR->usbintr = 0; + EHCI_HCOR->usbsts = EHCI_HCOR->usbsts; + + /* Set the Current Asynchronous List Address. */ + EHCI_HCOR->asynclistaddr = EHCI_PTR2ADDR(&g_async_qh_head[bus->hcd.hcd_id]); + /* Set the Periodic Frame List Base Address. */ + EHCI_HCOR->periodiclistbase = EHCI_PTR2ADDR(g_framelist[bus->hcd.hcd_id]); + + regval = 0; +#if CONFIG_USB_EHCI_FRAME_LIST_SIZE == 1024 + regval |= EHCI_USBCMD_FLSIZE_1024; +#elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 512 + regval |= EHCI_USBCMD_FLSIZE_512; +#elif CONFIG_USB_EHCI_FRAME_LIST_SIZE == 256 + regval |= EHCI_USBCMD_FLSIZE_256; +#else +#error Unsupported frame size list size +#endif + + regval |= EHCI_USBCMD_ITHRE_1MF; + regval |= EHCI_USBCMD_ASEN; + regval |= EHCI_USBCMD_PSEN; + regval |= EHCI_USBCMD_RUN; + EHCI_HCOR->usbcmd = regval; + +#ifdef CONFIG_USB_EHCI_CONFIGFLAG + EHCI_HCOR->configflag = EHCI_CONFIGFLAG; +#endif + /* Wait for the EHCI to run (no longer report halted) */ + timeout = 0; + while (EHCI_HCOR->usbsts & EHCI_USBSTS_HALTED) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + return -USB_ERR_TIMEOUT; + } + } + + if (g_ehci_hcd[bus->hcd.hcd_id].ppc) { + for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) { + regval = EHCI_HCOR->portsc[port]; + regval |= EHCI_PORTSC_PP; + EHCI_HCOR->portsc[port] = regval; + } + } + + if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) { +#ifdef CONFIG_USB_EHCI_WITH_OHCI + USB_LOG_INFO("EHCI uses tt for ls/fs device, so cannot enable this macro\r\n"); + return -USB_ERR_INVAL; +#endif + } + + if (g_ehci_hcd[bus->hcd.hcd_id].has_tt) { + USB_LOG_INFO("EHCI uses tt for ls/fs device\r\n"); + } else { +#ifdef CONFIG_USB_EHCI_WITH_OHCI + USB_LOG_INFO("EHCI uses companion controller for ls/fs device\r\n"); + ohci_init(bus); +#else + USB_LOG_WRN("Do not enable companion controller, you should use a hub to support ls/fs device\r\n"); +#endif + } + + /* Enable EHCI interrupts. */ + EHCI_HCOR->usbintr = EHCI_USBIE_INT | EHCI_USBIE_ERR | EHCI_USBIE_PCD | EHCI_USBIE_FATAL | EHCI_USBIE_IAA; + return 0; +} + +int usb_hc_deinit(struct usbh_bus *bus) +{ + struct ehci_qh_hw *qh; + + volatile uint32_t timeout = 0; + uint32_t regval; + + EHCI_HCOR->usbintr = 0; + + regval = EHCI_HCOR->usbcmd; + regval &= ~EHCI_USBCMD_ASEN; + regval &= ~EHCI_USBCMD_PSEN; + regval &= ~EHCI_USBCMD_RUN; + EHCI_HCOR->usbcmd = regval; + + while ((EHCI_HCOR->usbsts & (EHCI_USBSTS_PSS | EHCI_USBSTS_ASS))) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + return -USB_ERR_TIMEOUT; + } + } + + if (g_ehci_hcd[bus->hcd.hcd_id].ppc) { + for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) { + regval = EHCI_HCOR->portsc[port]; + regval &= ~EHCI_PORTSC_PP; + EHCI_HCOR->portsc[port] = regval; + } + } + +#ifdef CONFIG_USB_EHCI_CONFIGFLAG + EHCI_HCOR->configflag = 0; +#endif + + EHCI_HCOR->usbsts = EHCI_HCOR->usbsts; + + for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { + qh = &ehci_qh_pool[bus->hcd.hcd_id][index]; + usb_osal_sem_delete(qh->waitsem); + } + +#ifdef CONFIG_USB_EHCI_WITH_OHCI + ohci_deinit(bus); +#endif + + usb_hc_low_level_deinit(bus); + return 0; +} + +uint16_t usbh_get_frame_number(struct usbh_bus *bus) +{ +#ifdef CONFIG_USB_EHCI_WITH_OHCI + if (EHCI_HCOR->portsc[0] & EHCI_PORTSC_OWNER) { + return ohci_get_frame_number(bus); + } +#endif + + return (((EHCI_HCOR->frindex & EHCI_FRINDEX_MASK) >> 3) & 0x3ff); +} + +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + uint8_t nports; + uint8_t port; + uint32_t temp, status; + + nports = g_ehci_hcd[bus->hcd.hcd_id].n_ports; + + port = setup->wIndex; + + temp = EHCI_HCOR->portsc[port - 1]; + +#ifdef CONFIG_USB_EHCI_WITH_OHCI + if (temp & EHCI_PORTSC_OWNER) { + return ohci_roothub_control(bus, setup, buf); + } + + if ((temp & EHCI_PORTSC_LSTATUS_MASK) == EHCI_PORTSC_LSTATUS_KSTATE) { + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER; + + while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) { + } + return ohci_roothub_control(bus, setup, buf); + } +#endif + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + break; + case HUB_REQUEST_GET_STATUS: + memset(buf, 0, 4); + break; + default: + break; + } + } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_ENABLE: + EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PE; + break; + case HUB_PORT_FEATURE_SUSPEND: + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_RESUME; + usb_osal_msleep(20); + EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_RESUME; + while (EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_RESUME) { + } + + temp = EHCI_HCOR->usbcmd; + temp |= EHCI_USBCMD_ASEN; + temp |= EHCI_USBCMD_PSEN; + temp |= EHCI_USBCMD_RUN; + EHCI_HCOR->usbcmd = temp; + + while ((EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) == 0) { + } + + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + EHCI_HCOR->portsc[port - 1] &= ~EHCI_PORTSC_PP; + break; + case HUB_PORT_FEATURE_C_CONNECTION: + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_CSC; + break; + case HUB_PORT_FEATURE_C_ENABLE: + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PEC; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OCC; + break; + case HUB_PORT_FEATURE_C_RESET: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_SUSPEND: + temp = EHCI_HCOR->usbcmd; + temp &= ~EHCI_USBCMD_ASEN; + temp &= ~EHCI_USBCMD_PSEN; + temp &= ~EHCI_USBCMD_RUN; + EHCI_HCOR->usbcmd = temp; + + while (EHCI_HCOR->usbcmd & EHCI_USBCMD_RUN) { + } + + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_SUSPEND; + while ((EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_SUSPEND) == 0) { + } + break; + case HUB_PORT_FEATURE_POWER: + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_PP; + break; + case HUB_PORT_FEATURE_RESET: + usbh_reset_port(bus, port); +#ifdef CONFIG_USB_EHCI_WITH_OHCI + if (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_PE)) { + EHCI_HCOR->portsc[port - 1] |= EHCI_PORTSC_OWNER; + + while (!(EHCI_HCOR->portsc[port - 1] & EHCI_PORTSC_OWNER)) { + } + return ohci_roothub_control(bus, setup, buf); + } +#endif + break; + + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + temp = EHCI_HCOR->portsc[port - 1]; + + status = 0; + if (temp & EHCI_PORTSC_CSC) { + status |= (1 << HUB_PORT_FEATURE_C_CONNECTION); + } + if (temp & EHCI_PORTSC_PEC) { + status |= (1 << HUB_PORT_FEATURE_C_ENABLE); + } + if (temp & EHCI_PORTSC_OCC) { + status |= (1 << HUB_PORT_FEATURE_C_OVER_CURREN); + } + + if (temp & EHCI_PORTSC_CCS) { + status |= (1 << HUB_PORT_FEATURE_CONNECTION); + } + if (temp & EHCI_PORTSC_PE) { + status |= (1 << HUB_PORT_FEATURE_ENABLE); + + if (usbh_get_port_speed(bus, port) == USB_SPEED_LOW) { + status |= (1 << HUB_PORT_FEATURE_LOWSPEED); + } else if (usbh_get_port_speed(bus, port) == USB_SPEED_HIGH) { + status |= (1 << HUB_PORT_FEATURE_HIGHSPEED); + } + } + if (temp & EHCI_PORTSC_SUSPEND) { + status |= (1 << HUB_PORT_FEATURE_SUSPEND); + } + if (temp & EHCI_PORTSC_OCA) { + status |= (1 << HUB_PORT_FEATURE_OVERCURRENT); + } + if (temp & EHCI_PORTSC_RESET) { + status |= (1 << HUB_PORT_FEATURE_RESET); + } + if (temp & EHCI_PORTSC_PP) { + status |= (1 << HUB_PORT_FEATURE_POWER); + } + memcpy(buf, &status, 4); + break; + default: + break; + } + } + return 0; +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + struct ehci_qh_hw *qh = NULL; + size_t flags; + int ret = 0; + struct usbh_hub *hub; + struct usbh_hubport *hport; + struct usbh_bus *bus; + + if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + bus = urb->hport->bus; + + /* find active hubport in roothub */ + hport = urb->hport; + hub = urb->hport->parent; + while (!hub->is_roothub) { + hport = hub->parent; + hub = hub->parent->parent; + } + +#ifdef CONFIG_USB_EHCI_WITH_OHCI + if (EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_OWNER) { + return ohci_submit_urb(urb); + } +#endif + + if (!urb->hport->connected || !(EHCI_HCOR->portsc[hport->port - 1] & EHCI_PORTSC_CCS)) { + return -USB_ERR_NOTCONN; + } + + if (urb->errorcode == -USB_ERR_BUSY) { + return -USB_ERR_BUSY; + } + + flags = usb_osal_enter_critical_section(); + + urb->hcpriv = NULL; + urb->errorcode = -USB_ERR_BUSY; + urb->actual_length = 0; + + usb_osal_leave_critical_section(flags); + + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + qh = ehci_control_urb_init(bus, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + if (qh == NULL) { + return -USB_ERR_NOMEM; + } + urb->hcpriv = qh; + break; + case USB_ENDPOINT_TYPE_BULK: + qh = ehci_bulk_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length); + if (qh == NULL) { + return -USB_ERR_NOMEM; + } + urb->hcpriv = qh; + break; + case USB_ENDPOINT_TYPE_INTERRUPT: + qh = ehci_intr_urb_init(bus, urb, urb->transfer_buffer, urb->transfer_buffer_length); + if (qh == NULL) { + return -USB_ERR_NOMEM; + } + urb->hcpriv = qh; + break; + case USB_ENDPOINT_TYPE_ISOCHRONOUS: +#ifdef CONFIG_USB_EHCI_ISO + ret = ehci_iso_urb_init(bus, urb); +#endif + break; + default: + break; + } + + if (urb->timeout > 0) { + /* wait until timeout or sem give */ + ret = usb_osal_sem_take(qh->waitsem, urb->timeout); + if (ret < 0) { + goto errout_timeout; + } + urb->timeout = 0; + ret = urb->errorcode; + /* we can free qh when waitsem is done */ + ehci_qh_free(bus, qh); + } + return ret; +errout_timeout: + urb->timeout = 0; + usbh_kill_urb(urb); + return ret; +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + struct ehci_qh_hw *qh; + struct usbh_bus *bus; + size_t flags; + bool remove_in_iaad = false; + + if (!urb || !urb->hport || !urb->hcpriv || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + bus = urb->hport->bus; + +#ifdef CONFIG_USB_EHCI_WITH_OHCI + if (EHCI_HCOR->portsc[urb->hport->port - 1] & EHCI_PORTSC_OWNER) { + return ohci_kill_urb(urb); + } +#endif + + flags = usb_osal_enter_critical_section(); + + EHCI_HCOR->usbcmd &= ~(EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN); + + if ((USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) || (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_BULK)) { + qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp); + while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) { + if (qh->urb == urb) { + remove_in_iaad = true; + ehci_kill_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh); + } + qh = EHCI_ADDR2QH(qh->hw.hlp); + } + } else if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) { + qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp); + while (qh) { + if (qh->urb == urb) { + ehci_kill_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh); + } + qh = EHCI_ADDR2QH(qh->hw.hlp); + } + } else { +#ifdef CONFIG_USB_EHCI_ISO + ehci_remove_itd_urb(bus, urb); + EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN); + usb_osal_leave_critical_section(flags); + return 0; +#endif + } + + EHCI_HCOR->usbcmd |= (EHCI_USBCMD_PSEN | EHCI_USBCMD_ASEN); + + qh = (struct ehci_qh_hw *)urb->hcpriv; + urb->hcpriv = NULL; + urb->errorcode = -USB_ERR_SHUTDOWN; + qh->urb = NULL; + + if (urb->timeout) { + usb_osal_sem_give(qh->waitsem); + } else { + ehci_qh_free(bus, qh); + } + + if (remove_in_iaad) { + volatile uint32_t timeout = 0; + EHCI_HCOR->usbcmd |= EHCI_USBCMD_IAAD; + while (!(EHCI_HCOR->usbsts & EHCI_USBSTS_IAA)) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + usb_osal_leave_critical_section(flags); + return -USB_ERR_TIMEOUT; + } + } + EHCI_HCOR->usbsts = EHCI_USBSTS_IAA; + } + + usb_osal_leave_critical_section(flags); + + return 0; +} + +static void ehci_scan_async_list(struct usbh_bus *bus) +{ + struct ehci_qh_hw *qh; + + qh = EHCI_ADDR2QH(g_async_qh_head[bus->hcd.hcd_id].hw.hlp); + while ((qh != &g_async_qh_head[bus->hcd.hcd_id]) && qh) { + if (qh->urb) { + ehci_check_qh(bus, &g_async_qh_head[bus->hcd.hcd_id], qh); + } + qh = EHCI_ADDR2QH(qh->hw.hlp); + } +} + +static void ehci_scan_periodic_list(struct usbh_bus *bus) +{ + struct ehci_qh_hw *qh; + + qh = EHCI_ADDR2QH(g_periodic_qh_head[bus->hcd.hcd_id].hw.hlp); + while (qh) { + if (qh->urb) { + ehci_check_qh(bus, &g_periodic_qh_head[bus->hcd.hcd_id], qh); + } + qh = EHCI_ADDR2QH(qh->hw.hlp); + } +} + +void USBH_IRQHandler(uint8_t busid) +{ + uint32_t usbsts; + struct usbh_bus *bus; + + bus = &g_usbhost_bus[busid]; + + usbsts = EHCI_HCOR->usbsts & EHCI_HCOR->usbintr; + EHCI_HCOR->usbsts = usbsts; + + if (usbsts & EHCI_USBSTS_INT) { + ehci_scan_async_list(bus); + ehci_scan_periodic_list(bus); +#ifdef CONFIG_USB_EHCI_ISO + ehci_scan_isochronous_list(bus); +#endif + } + + if (usbsts & EHCI_USBSTS_ERR) { + ehci_scan_async_list(bus); + ehci_scan_periodic_list(bus); +#ifdef CONFIG_USB_EHCI_ISO + ehci_scan_isochronous_list(bus); +#endif + } + + if (usbsts & EHCI_USBSTS_PCD) { + for (int port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_ports; port++) { + uint32_t portsc = EHCI_HCOR->portsc[port]; + + if (portsc & EHCI_PORTSC_CSC) { + if ((portsc & EHCI_PORTSC_CCS) == EHCI_PORTSC_CCS) { + } else { + for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { + g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[index] = false; + } + for (uint8_t index = 0; index < CONFIG_USB_EHCI_ITD_NUM; index++) { + g_ehci_hcd[bus->hcd.hcd_id].ehci_itd_used[index] = false; + } + } + + bus->hcd.roothub.int_buffer[0] |= (1 << (port + 1)); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + } + } + + if (usbsts & EHCI_USBSTS_IAA) { + for (uint8_t index = 0; index < CONFIG_USB_EHCI_QH_NUM; index++) { + struct ehci_qh_hw *qh = &ehci_qh_pool[bus->hcd.hcd_id][index]; + if (g_ehci_hcd[bus->hcd.hcd_id].ehci_qh_used[index] && qh->remove_in_iaad) { + ehci_urb_waitup(bus, qh->urb); + } + } + } + + if (usbsts & EHCI_USBSTS_FATAL) { + } +} diff --git a/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.h b/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.h new file mode 100644 index 00000000000..7f3febc23f2 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ehci/usb_hc_ehci.h @@ -0,0 +1,375 @@ +/* + * Copyright 2020 The Apache Software Foundation + * Copyright 2022 sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HC_EHCI_H +#define USB_HC_EHCI_H + +#define EHCI_FULL_SPEED (0) /* Full-Speed (12Mbs) */ +#define EHCI_LOW_SPEED (1) /* Low-Speed (1.5Mbs) */ +#define EHCI_HIGH_SPEED (2) /* High-Speed (480 Mb/s) */ + +/* Host Controller Capability Register Bit Definitions **********************/ + +/* Structural Parameters. Paragraph 2.2.3 */ + +#define EHCI_HCSPARAMS_NPORTS_SHIFT (0) /* Bit 0-3: Number of physical downstream ports */ +#define EHCI_HCSPARAMS_NPORTS_MASK (15 << EHCI_HCSPARAMS_NPORTS_SHIFT) +#define EHCI_HCSPARAMS_PPC (1 << 4) /* Bit 4: Port Power Control */ +#define EHCI_HCSPARAMS_PRR (1 << 7) /* Bit 7: Port Routing Rules */ +#define EHCI_HCSPARAMS_NPCC_SHIFT (8) /* Bit 8-11: Number of Ports per Companion Controller */ +#define EHCI_HCSPARAMS_NPCC_MASK (15 << EHCI_HCSPARAMS_NPCC_SHIFT) +#define EHCI_HCSPARAMS_NCC_SHIFT (12) /* Bit 12-15: Number of Companion Controllers */ +#define EHCI_HCSPARAMS_NCC_MASK (15 << EHCI_HCSPARAMS_NCC_SHIFT) +#define EHCI_HCSPARAMS_PIND (1 << 16) /* Bit 16: Port Indicators */ +#define EHCI_HCSPARAMS_DBGPORT_SHIFT (20) /* Bit 20-23: Debug Port Number */ +#define EHCI_HCSPARAMS_DBGPORT_MASK (15 << EHCI_HCSPARAMS_DBGPORT_SHIFT) + +/* Capability Parameters. Paragraph 2.2.4 */ + +#define EHCI_HCCPARAMS_64BIT (1 << 0) /* Bit 0: 64-bit Addressing Capability */ +#define EHCI_HCCPARAMS_PFLF (1 << 1) /* Bit 1: Programmable Frame List Flag */ +#define EHCI_HCCPARAMS_ASPC (1 << 2) /* Bit 2: Asynchronous Schedule Park Capability */ +#define EHCI_HCCPARAMS_IST_SHIFT (4) /* Bits 4-7: Isochronous Scheduling Threshold */ +#define EHCI_HCCPARAMS_IST_MASK (15 << EHCI_HCCPARAMS_IST_SHIFT) +#define EHCI_HCCPARAMS_EECP_SHIFT (8) /* Bits 8-15: EHCI Extended Capabilities Pointer */ +#define EHCI_HCCPARAMS_EECP_MASK (0xff << EHCI_HCCPARAMS_EECP_SHIFT) + +/* Host Controller Operational Register Bit Definitions *********************/ + +/* USB Command. Paragraph 2.3.1 */ + +#define EHCI_USBCMD_RUN (1 << 0) /* Bit 0: Run/Stop */ +#define EHCI_USBCMD_HCRESET (1 << 1) /* Bit 1: Host Controller Reset */ +#define EHCI_USBCMD_FLSIZE_SHIFT (2) /* Bits 2-3: Frame List Size */ +#define EHCI_USBCMD_FLSIZE_MASK (3 << EHCI_USBCMD_FLSIZE_SHIFT) +#define EHCI_USBCMD_FLSIZE_1024 (0 << EHCI_USBCMD_FLSIZE_SHIFT) /* 1024 elements (4096 bytes) */ +#define EHCI_USBCMD_FLSIZE_512 (1 << EHCI_USBCMD_FLSIZE_SHIFT) /* 512 elements (2048 bytes) */ +#define EHCI_USBCMD_FLSIZE_256 (2 << EHCI_USBCMD_FLSIZE_SHIFT) /* 256 elements (1024 bytes) */ +#define EHCI_USBCMD_PSEN (1 << 4) /* Bit 4: Periodic Schedule Enable */ +#define EHCI_USBCMD_ASEN (1 << 5) /* Bit 5: Asynchronous Schedule Enable */ +#define EHCI_USBCMD_IAAD (1 << 6) /* Bit 6: Interrupt on Async Advance Doorbell */ +#define EHCI_USBCMD_LRESET (1 << 7) /* Bit 7: Light Host Controller Reset */ +#define EHCI_USBCMD_ASYNC_PARKCNT_SHIFT (8) /* Bits 8-9: Asynchronous Schedule Park Mode Count */ +#define EHCI_USBCMD_ASYNC_PARKCNT_MASK (3 << EHCI_USBCMD_ASYNC_PARKCNT_SHIFT) +#define EHCI_USBCMD_ASYNC_PARK (1 << 11) /* Bit 11: Asynchronous Schedule Park Mode Enable */ +#define EHCI_USBCMD_ITHRE_SHIFT (16) /* Bits 16-23: Interrupt Threshold Control */ +#define EHCI_USBCMD_ITHRE_MASK (0xff << EHCI_USBCMD_ITHRE_SHIFT) +#define EHCI_USBCMD_ITHRE_1MF (0x01 << EHCI_USBCMD_ITHRE_SHIFT) /* 1 micro-frame */ +#define EHCI_USBCMD_ITHRE_2MF (0x02 << EHCI_USBCMD_ITHRE_SHIFT) /* 2 micro-frames */ +#define EHCI_USBCMD_ITHRE_4MF (0x04 << EHCI_USBCMD_ITHRE_SHIFT) /* 4 micro-frames */ +#define EHCI_USBCMD_ITHRE_8MF (0x08 << EHCI_USBCMD_ITHRE_SHIFT) /* 8 micro-frames (default, 1 ms) */ +#define EHCI_USBCMD_ITHRE_16MF (0x10 << EHCI_USBCMD_ITHRE_SHIFT) /* 16 micro-frames (2 ms) */ +#define EHCI_USBCMD_ITHRE_32MF (0x20 << EHCI_USBCMD_ITHRE_SHIFT) /* 32 micro-frames (4 ms) */ +#define EHCI_USBCMD_ITHRE_64MF (0x40 << EHCI_USBCMD_ITHRE_SHIFT) /* 64 micro-frames (8 ms) */ + +/* USB Status. Paragraph 2.3.2 */ + +#define EHCI_USBSTS_INT (1 << 0) /* Bit 0: USB Interrupt */ +#define EHCI_USBSTS_ERR (1 << 1) /* Bit 1: USB Error Interrupt */ +#define EHCI_USBSTS_PCD (1 << 2) /* Bit 2: Port Change Detect */ +#define EHCI_USBSTS_FLR (1 << 3) /* Bit 3: Frame List Rollover */ +#define EHCI_USBSTS_FATAL (1 << 4) /* Bit 4: Host System Error */ +#define EHCI_USBSTS_IAA (1 << 5) /* Bit 5: Interrupt on Async Advance */ +#define EHCI_USBSTS_HALTED (1 << 12) /* Bit 12: HC Halted */ +#define EHCI_USBSTS_RECLAM (1 << 13) /* Bit 13: Reclamation */ +#define EHCI_USBSTS_PSS (1 << 14) /* Bit 14: Periodic Schedule Status */ +#define EHCI_USBSTS_ASS (1 << 15) /* Bit 15: Asynchronous Schedule Status */ + /* Bits 16-31: Reserved */ + +/* USB Interrupt Enable. Paragraph 2.3.3 */ + +#define EHCI_USBIE_INT (1 << 0) /* Bit 0: USB Interrupt */ +#define EHCI_USBIE_ERR (1 << 1) /* Bit 1: USB Error Interrupt */ +#define EHCI_USBIE_PCD (1 << 2) /* Bit 2: Port Change Detect */ +#define EHCI_USBIE_FLROLL (1 << 3) /* Bit 3: Frame List Rollover */ +#define EHCI_USBIE_FATAL (1 << 4) /* Bit 4: Host System Error */ +#define EHCI_USBIE_IAA (1 << 5) /* Bit 5: Interrupt on Async Advance */ +#define EHCI_USBIE_ALLINTS (0x3f) /* Bits 0-5: All interrupts */ + +/* USB Frame Index. Paragraph 2.3.4 */ + +#define EHCI_FRINDEX_MASK (0x3fff) /* Bits 0-13: Frame index */ + +/* 4G Segment Selector. + * Paragraph 2.3.5, Bits[64:32] of data structure addresses + */ + +/* Frame List Base Address. Paragraph 2.3.6 */ +#define EHCI_PERIODICLISTBASE_MASK (0xfffff000) /* Bits 12-31: Base Address (Low) */ + +/* Next Asynchronous List Address. Paragraph 2.3.7 */ + +#define EHCI_ASYNCLISTADDR_MASK (0xffffffe0) /* Bits 5-31: Link Pointer Low (LPL) */ + +/* Configured Flag Register. Paragraph 2.3.8 */ + +#define EHCI_CONFIGFLAG (1 << 0) /* Bit 0: Configure Flag */ + +/* Port Status/Control, Port 1-n. Paragraph 2.3.9 */ + +#define EHCI_PORTSC_CCS (1 << 0) /* Bit 0: Current Connect Status */ +#define EHCI_PORTSC_CSC (1 << 1) /* Bit 1: Connect Status Change */ +#define EHCI_PORTSC_PE (1 << 2) /* Bit 2: Port Enable */ +#define EHCI_PORTSC_PEC (1 << 3) /* Bit 3: Port Enable/Disable Change */ +#define EHCI_PORTSC_OCA (1 << 4) /* Bit 4: Over-current Active */ +#define EHCI_PORTSC_OCC (1 << 5) /* Bit 5: Over-current Change */ +#define EHCI_PORTSC_RESUME (1 << 6) /* Bit 6: Force Port Resume */ +#define EHCI_PORTSC_SUSPEND (1 << 7) /* Bit 7: Suspend */ +#define EHCI_PORTSC_RESET (1 << 8) /* Bit 8: Port Reset */ +#define EHCI_PORTSC_LSTATUS_SHIFT (10) /* Bits 10-11: Line Status */ +#define EHCI_PORTSC_LSTATUS_MASK (3 << EHCI_PORTSC_LSTATUS_SHIFT) +#define EHCI_PORTSC_LSTATUS_SE0 (0 << EHCI_PORTSC_LSTATUS_SHIFT) /* SE0 Not Low-speed device, perform EHCI reset */ +#define EHCI_PORTSC_LSTATUS_KSTATE (1 << EHCI_PORTSC_LSTATUS_SHIFT) /* K-state Low-speed device, release ownership of port */ +#define EHCI_PORTSC_LSTATUS_JSTATE (2 << EHCI_PORTSC_LSTATUS_SHIFT) /* J-state Not Low-speed device, perform EHCI reset */ +#define EHCI_PORTSC_PP (1 << 12) /* Bit 12: Port Power */ +#define EHCI_PORTSC_OWNER (1 << 13) /* Bit 13: Port Owner */ +#define EHCI_PORTSC_PIC_SHIFT (14) /* Bits 14-15: Port Indicator Control */ +#define EHCI_PORTSC_PIC_MASK (3 << EHCI_PORTSC_PIC_SHIFT) +#define EHCI_PORTSC_PIC_OFF (0 << EHCI_PORTSC_PIC_SHIFT) /* Port indicators are off */ +#define EHCI_PORTSC_PIC_AMBER (1 << EHCI_PORTSC_PIC_SHIFT) /* Amber */ +#define EHCI_PORTSC_PIC_GREEN (2 << EHCI_PORTSC_PIC_SHIFT) /* Green */ +#define EHCI_PORTSC_PTC_SHIFT (16) /* Bits 16-19: Port Test Control */ +#define EHCI_PORTSC_PTC_MASK (15 << EHCI_PORTSC_PTC_SHIFT) +#define EHCI_PORTSC_PTC_DISABLED (0 << EHCI_PORTSC_PTC_SHIFT) /* Test mode not enabled */ +#define EHCI_PORTSC_PTC_JSTATE (1 << EHCI_PORTSC_PTC_SHIFT) /* Test J_STATE */ +#define EHCI_PORTSC_PTC_KSTATE (2 << EHCI_PORTSC_PTC_SHIFT) /* Test K_STATE */ +#define EHCI_PORTSC_PTC_SE0NAK (3 << EHCI_PORTSC_PTC_SHIFT) /* Test SE0_NAK */ +#define EHCI_PORTSC_PTC_PACKET (4 << EHCI_PORTSC_PTC_SHIFT) /* Test Packet */ +#define EHCI_PORTSC_PTC_ENABLE (5 << EHCI_PORTSC_PTC_SHIFT) /* Test FORCE_ENABLE */ +#define EHCI_PORTSC_WKCCNTE (1 << 20) /* Bit 20: Wake on Connect Enable */ +#define EHCI_PORTSC_WKDSCNNTE (1 << 21) /* Bit 21: Wake on Disconnect Enable */ +#define EHCI_PORTSC_WKOCE (1 << 22) /* Bit 22: Wake on Over-current Enable */ + /* Bits 23-31: Reserved */ + +#define EHCI_PORTSC_ALLINTS (EHCI_PORTSC_CSC | EHCI_PORTSC_PEC | \ + EHCI_PORTSC_OCC | EHCI_PORTSC_RESUME) + +/* Queue Head. Paragraph 3.6 */ + +/* Queue Head Horizontal Link Pointer: Queue Head DWord 0. Table 3-19 */ + +#define QH_HLP_END 0x1 + +#define QH_HLP_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) /* Isochronous Transfer Descriptor */ +#define QH_HLP_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) /* Queue Head */ +#define QH_HLP_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) /* Split Transaction Isochronous Transfer Descriptor */ +#define QH_HLP_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) /* Frame Span Traversal Node */ + +/* Endpoint Characteristics: Queue Head DWord 1. Table 3-19 */ + +#define QH_EPCHAR_DEVADDR_SHIFT (0) /* Bitx 0-6: Device Address */ +#define QH_EPCHAR_DEVADDR_MASK (0x7f << QH_EPCHAR_DEVADDR_SHIFT) +#define QH_EPCHAR_I (1 << 7) /* Bit 7: Inactivate on Next Transaction */ +#define QH_EPCHAR_ENDPT_SHIFT (8) /* Bitx 8-11: Endpoint Number */ +#define QH_EPCHAR_ENDPT_MASK (15 << QH_EPCHAR_ENDPT_SHIFT) +#define QH_EPCHAR_EPS_SHIFT (12) /* Bitx 12-13: Endpoint Speed */ +#define QH_EPCHAR_EPS_MASK (3 << QH_EPCHAR_EPS_SHIFT) +#define QH_EPCHAR_EPS_FULL (0 << QH_EPCHAR_EPS_SHIFT) /* Full-Speed (12Mbs) */ +#define QH_EPCHAR_EPS_LOW (1 << QH_EPCHAR_EPS_SHIFT) /* Low-Speed (1.5Mbs) */ +#define QH_EPCHAR_EPS_HIGH (2 << QH_EPCHAR_EPS_SHIFT) /* High-Speed (480 Mb/s) */ +#define QH_EPCHAR_DTC (1 << 14) /* Bit 14: Data Toggle Control */ +#define QH_EPCHAR_H (1 << 15) /* Bit 15: Head of Reclamation List Flag */ +#define QH_EPCHAR_MAXPKT_SHIFT (16) /* Bitx 16-26: Maximum Packet Length */ +#define QH_EPCHAR_MAXPKT_MASK (0x7ff << QH_EPCHAR_MAXPKT_SHIFT) +#define QH_EPCHAR_C (1 << 27) /* Bit 27: Control Endpoint Flag */ +#define QH_EPCHAR_RL_SHIFT (28) /* Bitx 28-31: Nak Count Reload */ +#define QH_EPCHAR_RL_MASK (15 << QH_EPCHAR_RL_SHIFT) + +/* Endpoint Capabilities: Queue Head DWord 2. Table 3-20 */ + +#define QH_EPCAPS_SSMASK_SHIFT (0) /* Bitx 0-7: Interrupt Schedule Mask (Frame S-mask) */ +#define QH_EPCAPS_SSMASK_MASK (0xff << QH_EPCAPS_SSMASK_SHIFT) +#define QH_EPCAPS_SSMASK(n) ((n) << QH_EPCAPS_SSMASK_SHIFT) +#define QH_EPCAPS_SCMASK_SHIFT (8) /* Bitx 8-15: Split Completion Mask (Frame C-Mask) */ +#define QH_EPCAPS_SCMASK_MASK (0xff << QH_EPCAPS_SCMASK_SHIFT) +#define QH_EPCAPS_SCMASK(n) ((n) << QH_EPCAPS_SCMASK_SHIFT) +#define QH_EPCAPS_HUBADDR_SHIFT (16) /* Bitx 16-22: Hub Address */ +#define QH_EPCAPS_HUBADDR_MASK (0x7f << QH_EPCAPS_HUBADDR_SHIFT) +#define QH_EPCAPS_HUBADDR(n) ((n) << QH_EPCAPS_HUBADDR_SHIFT) +#define QH_EPCAPS_PORT_SHIFT (23) /* Bit 23-29: Port Number */ +#define QH_EPCAPS_PORT_MASK (0x7f << QH_EPCAPS_PORT_SHIFT) +#define QH_EPCAPS_PORT(n) ((n) << QH_EPCAPS_PORT_SHIFT) +#define QH_EPCAPS_MULT_SHIFT (30) /* Bit 30-31: High-Bandwidth Pipe Multiplier */ +#define QH_EPCAPS_MULT_MASK (3 << QH_EPCAPS_MULT_SHIFT) +#define QH_EPCAPS_MULT(n) ((n) << QH_EPCAPS_MULT_SHIFT) + +/* qTD Token. Paragraph 3.5.3 */ + +#define QTD_LIST_END 1 + +#define QTD_TOKEN_STATUS_SHIFT (0) /* Bits 0-7: Status */ +#define QTD_TOKEN_STATUS_MASK (0xff << QTD_TOKEN_STATUS_SHIFT) +#define QTD_TOKEN_STATUS_PINGSTATE (1 << 0) /* Bit 0 Ping State */ +#define QTD_TOKEN_STATUS_ERR (1 << 0) /* Bit 0 Error */ +#define QTD_TOKEN_STATUS_SPLITXSTATE (1 << 1) /* Bit 1 Split Transaction State */ +#define QTD_TOKEN_STATUS_MMF (1 << 2) /* Bit 2 Missed Micro-Frame */ +#define QTD_TOKEN_STATUS_XACTERR (1 << 3) /* Bit 3 Transaction Error */ +#define QTD_TOKEN_STATUS_BABBLE (1 << 4) /* Bit 4 Babble Detected */ +#define QTD_TOKEN_STATUS_DBERR (1 << 5) /* Bit 5 Data Buffer Error */ +#define QTD_TOKEN_STATUS_HALTED (1 << 6) /* Bit 6 Halted */ +#define QTD_TOKEN_STATUS_ACTIVE (1 << 7) /* Bit 7 Active */ +#define QTD_TOKEN_STATUS_ERRORS (0x78 << QTD_TOKEN_STATUS_SHIFT) +#define QTD_TOKEN_PID_SHIFT (8) /* Bits 8-9: PID Code */ +#define QTD_TOKEN_PID_MASK (3 << QTD_TOKEN_PID_SHIFT) +#define QTD_TOKEN_PID_OUT (0 << QTD_TOKEN_PID_SHIFT) /* OUT Token generates token (E1H) */ +#define QTD_TOKEN_PID_IN (1 << QTD_TOKEN_PID_SHIFT) /* IN Token generates token (69H) */ +#define QTD_TOKEN_PID_SETUP (2 << QTD_TOKEN_PID_SHIFT) /* SETUP Token generates token (2DH) */ +#define QTD_TOKEN_CERR_SHIFT (10) /* Bits 10-11: Error Counter */ +#define QTD_TOKEN_CERR_MASK (3 << QTD_TOKEN_CERR_SHIFT) +#define QTD_TOKEN_CPAGE_SHIFT (12) /* Bits 12-14: Current Page */ +#define QTD_TOKEN_CPAGE_MASK (7 << QTD_TOKEN_CPAGE_SHIFT) +#define QTD_TOKEN_IOC (1 << 15) /* Bit 15: Interrupt On Complete */ +#define QTD_TOKEN_NBYTES_SHIFT (16) /* Bits 16-30: Total Bytes to Transfer */ +#define QTD_TOKEN_NBYTES_MASK (0x7fff << QTD_TOKEN_NBYTES_SHIFT) +#define QTD_TOKEN_TOGGLE (1 << 31) /* Bit 31: Data Toggle */ + +/* Isochronous (High-Speed) Transfer Descriptor (iTD). Paragraph 3.3 */ + +/* iTD Next Link Pointer. Paragraph 3.3.1 */ + +#define ITD_NLP_ITD(x) (((uint32_t)(x) & ~0x1F) | 0x0) +#define ITD_NLP_QH(x) (((uint32_t)(x) & ~0x1F) | 0x2) +#define ITD_NLP_SITD(x) (((uint32_t)(x) & ~0x1F) | 0x4) +#define ITD_NLP_FSTN(x) (((uint32_t)(x) & ~0x1F) | 0x6) + +/* iTD Transaction Status and Control List. Paragraph 3.3.2 */ +#define ITD_TSCL_XOFFS_SHIFT (0) /* Bits 0-11: Transaction X offset */ +#define ITD_TSCL_XOFFS_MASK (0xfff << ITD_TSCL_XOFFS_SHIFT) +#define ITD_TSCL_PG_SHIFT (12) /* Bits 12-14: Page select */ +#define ITD_TSCL_PG_MASK (7 << ITD_TSCL_PG_SHIFT) +#define ITD_TSCL_IOC (1 << 15) /* Bit 15: Interrupt On Comp */ +#define ITD_TSCL_LENGTH_SHIFT (16) /* Bits 16-27: Transaction length */ +#define ITD_TSCL_LENGTH_MASK (0xfff << ITD_TSCL_LENGTH_SHIFT) +#define ITD_TSCL_STATUS_SHIFT (28) /* Bits 28-31: Transaction status */ +#define ITD_TSCL_STATUS_MASK (15 << ITD_TSCL_STATUS_SHIFT) +#define ITD_TSCL_STATUS_XACTERR (1 << 28) /* Bit 28: Transaction error */ +#define ITD_TSCL_STATUS_BABBLE (1 << 29) /* Bit 29: Babble Detected */ +#define ITD_TSCL_STATUS_DBERROR (1 << 30) /* Bit 30: Data Buffer Error */ +#define ITD_TSCL_STATUS_ACTIVE (1 << 31) /* Bit 31: Active error */ + +/* iTD Buffer Page Pointer List. Paragraph 3.3.4 */ + +/* iTD Buffer Pointer Page 0. Table 3-4 */ + +#define ITD_BUFPTR0_DEVADDR_SHIFT (0) /* Bits 0-6: Device Address */ +#define ITD_BUFPTR0_DEVADDR_MASK (0x7f << ITD_BUFPTR0_DEVADDR_SHIFT) +#define ITD_BUFPTR0_ENDPT_SHIFT (8) /* Bits 8-11: Endpoint Number */ +#define ITD_BUFPTR0_ENDPT_MASK (15 << ITD_BUFPTR0_ENDPT_SHIFT) + +/* iTD Buffer Pointer Page 1. Table 3-5 */ + +#define ITD_BUFPTR1_MAXPKT_SHIFT (0) /* Bits 0-10: Maximum Packet Size */ +#define ITD_BUFPTR1_MAXPKT_MASK (0x7ff << ITD_BUFPTR1_MAXPKT_SHIFT) +#define ITD_BUFPTR1_DIRIN (1 << 11) /* Bit 11: Direction 1=IN */ +#define ITD_BUFPTR1_DIROUT (0) /* Bit 11: Direction 0=OUT */ + +/* iTD Buffer Pointer Page 2. Table 3-6 */ + +#define ITD_BUFPTR2_MULTI_SHIFT (0) /* Bits 0-1: Multi */ +#define ITD_BUFPTR2_MULTI_MASK (3 << ITD_BUFPTR2_MULTI_SHIFT) +#define ITD_BUFPTR2_MULTI_1 (1 << ITD_BUFPTR2_MULTI_SHIFT) /* One transaction per micro-frame */ +#define ITD_BUFPTR2_MULTI_2 (2 << ITD_BUFPTR2_MULTI_SHIFT) /* Two transactions per micro-frame */ +#define ITD_BUFPTR2_MULTI_3 (3 << ITD_BUFPTR2_MULTI_SHIFT) /* Three transactions per micro-frame */ + +/* Registers ****************************************************************/ + +/* Host Controller Capability Registers. + * This register block must be positioned at a well known address. + */ + +struct ehci_hccr { + volatile uint8_t caplength; /* 0x00: Capability Register Length */ + volatile uint8_t reserved; /* 0x01: reserved */ + volatile uint16_t hciversion; /* 0x02: Interface Version Number */ + volatile uint32_t hcsparams; /* 0x04: Structural Parameters */ + volatile uint32_t hccparams; /* 0x08: Capability Parameters */ + volatile uint8_t hcspportroute[8]; /* 0x0c: Companion Port Route Description */ +}; + +/* Host Controller Operational Registers. + * This register block is positioned at an offset of 'caplength' from the + * beginning of the Host Controller Capability Registers. + */ + +struct ehci_hcor { + volatile uint32_t usbcmd; /* 0x00: USB Command */ + volatile uint32_t usbsts; /* 0x04: USB Status */ + volatile uint32_t usbintr; /* 0x08: USB Interrupt Enable */ + volatile uint32_t frindex; /* 0x0c: USB Frame Index */ + volatile uint32_t ctrldssegment; /* 0x10: 4G Segment Selector */ + volatile uint32_t periodiclistbase; /* 0x14: Frame List Base Address */ + volatile uint32_t asynclistaddr; /* 0x18: Next Asynchronous List Address */ +#ifndef CONFIG_USB_EHCI_HCOR_RESERVED_DISABLE + uint32_t reserved[9]; +#endif + volatile uint32_t configflag; /* 0x40: Configured Flag Register */ + volatile uint32_t portsc[15]; /* 0x44: Port Status/Control */ +}; + +/* USB2 Debug Port Register Interface. + * This register block is normally found via the PCI capabalities. + * In non-PCI implementions, you need apriori information about the + * location of these registers. + */ + +struct ehci_debug { + uint32_t psc; /* 0x00: Debug Port Control/Status Register */ + uint32_t pids; /* 0x04: Debug USB PIDs Register */ + uint32_t data[2]; /* 0x08: Debug Data buffer Registers */ + uint32_t addr; /* 0x10: Device Address Register */ +}; + +/* Data Structures **********************************************************/ + +/* Queue Element Transfer Descriptor (qTD). Paragraph 3.5 */ + +struct ehci_qtd { + uint32_t next_qtd; /* 0x00-0x03: Next qTD Pointer */ + uint32_t alt_next_qtd; /* 0x04-0x07: Alternate Next qTD Pointer */ + uint32_t token; /* 0x08-0x0b: qTD Token */ + uint32_t bpl[5]; /* 0x0c-0x1c: Buffer Page Pointer List */ +}; + +#define SIZEOF_EHCI_QTD (32) /* 8*sizeof(uint32_t) */ + +/* Queue Head. Paragraph 3.6 */ + +struct ehci_qh { + uint32_t hlp; /* 0x00-0x03: Queue Head Horizontal Link Pointer */ + uint32_t epchar; /* 0x04-0x07: Endpoint Characteristics */ + uint32_t epcap; /* 0x08-0x0b: Endpoint Capabilities */ + uint32_t curr_qtd; /* 0x0c-0x0f: Current qTD Pointer */ + struct ehci_qtd overlay; /* 0x10-0x2c: Transfer overlay */ +}; + +#define SIZEOF_EHCI_QH (48) /* 4*sizeof(uint32_t) + 32 */ + +/* Isochronous (High-Speed) Transfer Descriptor (iTD). + * Paragraph 3.3. Must be aligned to 32-byte boundaries. + */ + +struct ehci_itd { + uint32_t nlp; /* 0x00-0x03: Next link pointer */ + uint32_t tscl[8]; /* 0x04-0x23: Transaction Status and Control List */ + uint32_t bpl[7]; /* 0x24-0x3c: Buffer Page Pointer List */ +}; + +#define SIZEOF_EHCI_ITD (64) /* 16*sizeof(uint32_t) */ + +/* Split Transaction Isochronous Transfer Descriptor (siTD). Paragraph 3.4 */ + +struct ehci_sitd { + uint32_t nlp; /* 0x00-0x03: Next link pointer */ + uint32_t epchar; /* 0x04-0x07: Endpoint and Transaction Translator Characteristics */ + uint32_t mfsc; /* 0x08-0x0b: Micro-frame Schedule Control */ + uint32_t tsc; /* 0x0c-0x0f: Transfer Status and Control */ + uint32_t bpl[2]; /* 0x10-0x17: Buffer Pointer List */ + uint32_t blp; /* 0x18-0x1b: Back link pointer */ +}; + +#define SIZEOF_EHCI_SITD (28) /* 7*sizeof(uint32_t) */ + +#endif /* USB_HC_EHCI_H */ diff --git a/components/drivers/usb/cherryusb/port/fsdev/README.md b/components/drivers/usb/cherryusb/port/fsdev/README.md new file mode 100644 index 00000000000..ecb9c33c117 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/fsdev/README.md @@ -0,0 +1,33 @@ +# Note + +## Support Chip List + +## STM32 + +- STM32F042x6、STM32F048xx、STM32F070x6、STM32F070xb、STM32F072xb、STM32F078xx +- STM32F102x6、STM32F102xb、STM32F103x6、STM32F103xb、STM32F103xe、STM32F103xg +- STM32F302x8、STM32F302xc、STM32F302xe、STM32F373xc +- STM32g431xx、STM32g441xx、STM32g471xx、STM32g483xx、STM32g484xx、STM32gbk1cb +- STM32l052xx、STM32l053xx、STM32l062xx、STM32l063xx、STM32l072xx、STM32l073xx、STM32l082xx、STM32l083xx +- STM32l100xb、STM32l100xba、STM32l100xc、STM32l151xb、STM32l151xba、STM32l151xc、STM32l151xca、STM32l151xd、STM32l151xdx、STM32l151xe、STM32l152xb、STM32l152xba、STM32l152xc、STM32l152xa、STM32l152xd、STM32l152xdx、STM32l152xe、STM32l162xc、STM32l162xca、STM32l162xd、STM32l162xdx、STM32l162xe +- STM32l412xx、STM32l422xx、STM32l432xx、STM32l433xx、STM32l442xx、STM32l452xx、STM32l462xx +- STM32wb5mxx、STM32wb35xx、STM32wb55xx + +## AT32 + +- AT32F403xx、AT32F407xx、AT32F413xx + +## APM32 + +- APM32f10x + +## GD32 + +- GD32F10X_MD、GD32F10X_HD、GD32F10X_XD +- GD32F30X_HD、GD32F30X_XD +- GD32F350 +- GD32F407 + +## CH32 + +- CH32F10x、CH32V10x diff --git a/components/drivers/usb/cherryusb/port/fsdev/usb_dc_fsdev.c b/components/drivers/usb/cherryusb/port/fsdev/usb_dc_fsdev.c new file mode 100644 index 00000000000..b3bfb5c4cb3 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/fsdev/usb_dc_fsdev.c @@ -0,0 +1,540 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" + +#ifndef CONFIG_USBDEV_FSDEV_PMA_ACCESS +#error "please define CONFIG_USBDEV_FSDEV_PMA_ACCESS in usb_config.h" +#endif + +#define PMA_ACCESS CONFIG_USBDEV_FSDEV_PMA_ACCESS +#include "usb_fsdev_reg.h" + +#ifndef CONFIG_USB_FSDEV_RAM_SIZE +#define CONFIG_USB_FSDEV_RAM_SIZE 512 +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +#define USB ((USB_TypeDef *)g_usbdev_bus[0].reg_base) + +#define USB_BTABLE_SIZE (8 * CONFIG_USBDEV_EP_NUM) + +static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); +static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes); + +/* Endpoint state */ +struct fsdev_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint16_t ep_pma_buf_len; /* Previously allocated buffer size */ + uint16_t ep_pma_addr; /* ep pmd allocated addr */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct fsdev_udc { + struct usb_setup_packet setup; + volatile uint8_t dev_addr; /*!< USB Address */ + volatile uint32_t pma_offset; /*!< pma offset */ + struct fsdev_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ + struct fsdev_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ +} g_fsdev_udc; + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + usb_dc_low_level_init(); + + /* Init Device */ + /* CNTR_FRES = 1 */ + USB->CNTR = (uint16_t)USB_CNTR_FRES; + + /* CNTR_FRES = 0 */ + USB->CNTR = 0U; + + /* Clear pending interrupts */ + USB->ISTR = 0U; + + /*Set Btable Address*/ + USB->BTABLE = BTABLE_ADDRESS; + + uint32_t winterruptmask; + + /* Set winterruptmask variable */ + winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | + USB_CNTR_SUSPM | USB_CNTR_ERRM | + USB_CNTR_SOFM | USB_CNTR_ESOFM | + USB_CNTR_RESETM; + + /* Set interrupt mask */ + USB->CNTR = (uint16_t)winterruptmask; + + /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ + USB->BCDR |= (uint16_t)USB_BCDR_DPPU; + + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + /* disable all interrupts and force USB reset */ + USB->CNTR = (uint16_t)USB_CNTR_FRES; + + /* clear interrupt status register */ + USB->ISTR = 0U; + + /* switch-off device */ + USB->CNTR = (uint16_t)(USB_CNTR_FRES | USB_CNTR_PDWN); + + usb_dc_low_level_deinit(); + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + if (addr == 0U) { + /* set device address and enable function */ + USB->DADDR = (uint16_t)USB_DADDR_EF; + } + + g_fsdev_udc.dev_addr = addr; + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + if (ep_idx > (CONFIG_USBDEV_EP_NUM - 1)) { + USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress); + return -1; + } + + uint16_t wEpRegVal; + + /* initialize Endpoint */ + switch (USB_GET_ENDPOINT_TYPE(ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + wEpRegVal = USB_EP_CONTROL; + break; + + case USB_ENDPOINT_TYPE_BULK: + wEpRegVal = USB_EP_BULK; + break; + + case USB_ENDPOINT_TYPE_INTERRUPT: + wEpRegVal = USB_EP_INTERRUPT; + break; + + case USB_ENDPOINT_TYPE_ISOCHRONOUS: + wEpRegVal = USB_EP_ISOCHRONOUS; + break; + + default: + break; + } + + PCD_SET_EPTYPE(USB, ep_idx, wEpRegVal); + + PCD_SET_EP_ADDRESS(USB, ep_idx, ep_idx); + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_fsdev_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_fsdev_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_fsdev_udc.out_ep[ep_idx].ep_enable = true; + if (g_fsdev_udc.out_ep[ep_idx].ep_mps > g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len) { + if (g_fsdev_udc.pma_offset + g_fsdev_udc.out_ep[ep_idx].ep_mps > CONFIG_USB_FSDEV_RAM_SIZE) { + USB_LOG_ERR("Ep pma %02x overflow\r\n", ep->bEndpointAddress); + return -1; + } + g_fsdev_udc.out_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_fsdev_udc.out_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset; + /*Set the endpoint Receive buffer address */ + PCD_SET_EP_RX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset); + g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + } + /*Set the endpoint Receive buffer counter*/ + PCD_SET_EP_RX_CNT(USB, ep_idx, USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + PCD_CLEAR_RX_DTOG(USB, ep_idx); + } else { + g_fsdev_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_fsdev_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_fsdev_udc.in_ep[ep_idx].ep_enable = true; + if (g_fsdev_udc.in_ep[ep_idx].ep_mps > g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len) { + if (g_fsdev_udc.pma_offset + g_fsdev_udc.in_ep[ep_idx].ep_mps > CONFIG_USB_FSDEV_RAM_SIZE) { + USB_LOG_ERR("Ep pma %02x overflow\r\n", ep->bEndpointAddress); + return -1; + } + g_fsdev_udc.in_ep[ep_idx].ep_pma_buf_len = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_fsdev_udc.in_ep[ep_idx].ep_pma_addr = g_fsdev_udc.pma_offset; + /*Set the endpoint Transmit buffer address */ + PCD_SET_EP_TX_ADDRESS(USB, ep_idx, g_fsdev_udc.pma_offset); + g_fsdev_udc.pma_offset += USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + } + + PCD_CLEAR_TX_DTOG(USB, ep_idx); + if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK); + } else { + /* Configure TX Endpoint to disabled state */ + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS); + } + } + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + PCD_CLEAR_RX_DTOG(USB, ep_idx); + + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_DIS); + } else { + PCD_CLEAR_TX_DTOG(USB, ep_idx); + + /* Configure DISABLE status for the Endpoint*/ + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_DIS); + } + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_STALL); + } else { + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_STALL); + } + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + PCD_CLEAR_RX_DTOG(USB, ep_idx); + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID); + } else { + PCD_CLEAR_TX_DTOG(USB, ep_idx); + + if (g_fsdev_udc.in_ep[ep_idx].ep_type != USB_ENDPOINT_TYPE_ISOCHRONOUS) { + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_NAK); + } + } + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + if (USB_EP_DIR_IS_OUT(ep)) { + } else { + } + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + + if (!g_fsdev_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + g_fsdev_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_fsdev_udc.in_ep[ep_idx].xfer_len = data_len; + g_fsdev_udc.in_ep[ep_idx].actual_xfer_len = 0; + + data_len = MIN(data_len, g_fsdev_udc.in_ep[ep_idx].ep_mps); + + fsdev_write_pma(USB, (uint8_t *)data, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)data_len); + PCD_SET_EP_TX_CNT(USB, ep_idx, (uint16_t)data_len); + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID); + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_fsdev_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + + g_fsdev_udc.out_ep[ep_idx].xfer_buf = data; + g_fsdev_udc.out_ep[ep_idx].xfer_len = data_len; + g_fsdev_udc.out_ep[ep_idx].actual_xfer_len = 0; + + PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID); + + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint16_t wIstr, wEPVal; + uint8_t ep_idx; + uint8_t read_count; + uint16_t write_count; + uint16_t store_ep[8]; + + wIstr = USB->ISTR; + if (wIstr & USB_ISTR_CTR) { + while ((USB->ISTR & USB_ISTR_CTR) != 0U) { + wIstr = USB->ISTR; + + /* extract highest priority endpoint number */ + ep_idx = (uint8_t)(wIstr & USB_ISTR_EP_ID); + + if (ep_idx == 0U) { + if ((wIstr & USB_ISTR_DIR) == 0U) { + PCD_CLEAR_TX_EP_CTR(USB, ep_idx); + + write_count = PCD_GET_EP_TX_CNT(USB, ep_idx); + + g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count; + g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count; + g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count; + + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len); + + if (g_fsdev_udc.setup.wLength == 0) { + /* In status, start reading setup */ + usbd_ep_start_read(0, 0x00, NULL, 0); + } else if (g_fsdev_udc.setup.wLength && ((g_fsdev_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + /* In status, start reading setup */ + usbd_ep_start_read(0, 0x00, NULL, 0); + } + + if ((g_fsdev_udc.dev_addr > 0U) && (write_count == 0U)) { + USB->DADDR = ((uint16_t)g_fsdev_udc.dev_addr | USB_DADDR_EF); + g_fsdev_udc.dev_addr = 0U; + } + + } else { + wEPVal = PCD_GET_ENDPOINT(USB, ep_idx); + + if ((wEPVal & USB_EP_SETUP) != 0U) { + PCD_CLEAR_RX_EP_CTR(USB, ep_idx); + + read_count = PCD_GET_EP_RX_CNT(USB, ep_idx); + fsdev_read_pma(USB, (uint8_t *)&g_fsdev_udc.setup, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count); + + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_fsdev_udc.setup); + + } else if ((wEPVal & USB_EP_CTR_RX) != 0U) { + PCD_CLEAR_RX_EP_CTR(USB, ep_idx); + + read_count = PCD_GET_EP_RX_CNT(USB, ep_idx); + + fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count); + + g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count; + g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count; + g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count; + + usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len); + + if (read_count == 0) { + /* Out status, start reading setup */ + usbd_ep_start_read(0, 0x00, NULL, 0); + } + } + } + } else { + wEPVal = PCD_GET_ENDPOINT(USB, ep_idx); + + if ((wEPVal & USB_EP_CTR_RX) != 0U) { + PCD_CLEAR_RX_EP_CTR(USB, ep_idx); + read_count = PCD_GET_EP_RX_CNT(USB, ep_idx); + fsdev_read_pma(USB, g_fsdev_udc.out_ep[ep_idx].xfer_buf, g_fsdev_udc.out_ep[ep_idx].ep_pma_addr, (uint16_t)read_count); + g_fsdev_udc.out_ep[ep_idx].xfer_buf += read_count; + g_fsdev_udc.out_ep[ep_idx].xfer_len -= read_count; + g_fsdev_udc.out_ep[ep_idx].actual_xfer_len += read_count; + + if ((read_count < g_fsdev_udc.out_ep[ep_idx].ep_mps) || + (g_fsdev_udc.out_ep[ep_idx].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(0, ep_idx, g_fsdev_udc.out_ep[ep_idx].actual_xfer_len); + } else { + PCD_SET_EP_RX_STATUS(USB, ep_idx, USB_EP_RX_VALID); + } + } + + if ((wEPVal & USB_EP_CTR_TX) != 0U) { + PCD_CLEAR_TX_EP_CTR(USB, ep_idx); + write_count = PCD_GET_EP_TX_CNT(USB, ep_idx); + + g_fsdev_udc.in_ep[ep_idx].xfer_buf += write_count; + g_fsdev_udc.in_ep[ep_idx].xfer_len -= write_count; + g_fsdev_udc.in_ep[ep_idx].actual_xfer_len += write_count; + + if (g_fsdev_udc.in_ep[ep_idx].xfer_len == 0) { + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_fsdev_udc.in_ep[ep_idx].actual_xfer_len); + } else { + write_count = MIN(g_fsdev_udc.in_ep[ep_idx].xfer_len, g_fsdev_udc.in_ep[ep_idx].ep_mps); + fsdev_write_pma(USB, g_fsdev_udc.in_ep[ep_idx].xfer_buf, g_fsdev_udc.in_ep[ep_idx].ep_pma_addr, (uint16_t)write_count); + PCD_SET_EP_TX_CNT(USB, ep_idx, write_count); + PCD_SET_EP_TX_STATUS(USB, ep_idx, USB_EP_TX_VALID); + } + } + } + } + } + if (wIstr & USB_ISTR_RESET) { + memset(&g_fsdev_udc, 0, sizeof(struct fsdev_udc)); + g_fsdev_udc.pma_offset = USB_BTABLE_SIZE; + usbd_event_reset_handler(0); + /* start reading setup packet */ + PCD_SET_EP_RX_STATUS(USB, 0, USB_EP_RX_VALID); + USB->ISTR &= (uint16_t)(~USB_ISTR_RESET); + } + if (wIstr & USB_ISTR_PMAOVR) { + USB->ISTR &= (uint16_t)(~USB_ISTR_PMAOVR); + } + if (wIstr & USB_ISTR_ERR) { + USB->ISTR &= (uint16_t)(~USB_ISTR_ERR); + } + if (wIstr & USB_ISTR_WKUP) { + USB->CNTR &= (uint16_t) ~(USB_CNTR_LP_MODE); + USB->CNTR &= (uint16_t) ~(USB_CNTR_FSUSP); + + USB->ISTR &= (uint16_t)(~USB_ISTR_WKUP); + } + if (wIstr & USB_ISTR_SUSP) { + /* WA: To Clear Wakeup flag if raised with suspend signal */ + + /* Store Endpoint register */ + for (uint8_t i = 0U; i < 8U; i++) { + store_ep[i] = PCD_GET_ENDPOINT(USB, i); + } + + /* FORCE RESET */ + USB->CNTR |= (uint16_t)(USB_CNTR_FRES); + + /* CLEAR RESET */ + USB->CNTR &= (uint16_t)(~USB_CNTR_FRES); + + /* wait for reset flag in ISTR */ + while ((USB->ISTR & USB_ISTR_RESET) == 0U) { + } + + /* Clear Reset Flag */ + USB->ISTR &= (uint16_t)(~USB_ISTR_RESET); + /* Restore Registre */ + for (uint8_t i = 0U; i < 8U; i++) { + PCD_SET_ENDPOINT(USB, i, store_ep[i]); + } + + /* Force low-power mode in the macrocell */ + USB->CNTR |= (uint16_t)USB_CNTR_FSUSP; + + /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ + USB->ISTR &= (uint16_t)(~USB_ISTR_SUSP); + + USB->CNTR |= (uint16_t)USB_CNTR_LP_MODE; + } + if (wIstr & USB_ISTR_SOF) { + USB->ISTR &= (uint16_t)(~USB_ISTR_SOF); + } + if (wIstr & USB_ISTR_ESOF) { + USB->ISTR &= (uint16_t)(~USB_ISTR_ESOF); + } +} + +static void fsdev_write_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = ((uint32_t)wNBytes + 1U) >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp1, temp2; + __IO uint16_t *pdwVal; + uint8_t *pBuf = pbUsrBuf; + + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) { + temp1 = *pBuf; + pBuf++; + temp2 = temp1 | ((uint16_t)((uint16_t)*pBuf << 8)); + *pdwVal = (uint16_t)temp2; + pdwVal++; + +#if PMA_ACCESS > 1U + pdwVal++; +#endif + + pBuf++; + } +} + +/** + * @brief Copy data from packet memory area (PMA) to user memory buffer + * @param USBx USB peripheral instance register address. + * @param pbUsrBuf pointer to user memory area. + * @param wPMABufAddr address into PMA. + * @param wNBytes no. of bytes to be copied. + * @retval None + */ +static void fsdev_read_pma(USB_TypeDef *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) +{ + uint32_t n = (uint32_t)wNBytes >> 1; + uint32_t BaseAddr = (uint32_t)USBx; + uint32_t i, temp; + __IO uint16_t *pdwVal; + uint8_t *pBuf = pbUsrBuf; + + pdwVal = (__IO uint16_t *)(BaseAddr + 0x400U + ((uint32_t)wPMABufAddr * PMA_ACCESS)); + + for (i = n; i != 0U; i--) { + temp = *(__IO uint16_t *)pdwVal; + pdwVal++; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + pBuf++; + *pBuf = (uint8_t)((temp >> 8) & 0xFFU); + pBuf++; + +#if PMA_ACCESS > 1U + pdwVal++; +#endif + } + + if ((wNBytes % 2U) != 0U) { + temp = *pdwVal; + *pBuf = (uint8_t)((temp >> 0) & 0xFFU); + } +} diff --git a/components/drivers/usb/cherryusb/port/fsdev/usb_fsdev_reg.h b/components/drivers/usb/cherryusb/port/fsdev/usb_fsdev_reg.h new file mode 100644 index 00000000000..c67cf5731d1 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/fsdev/usb_fsdev_reg.h @@ -0,0 +1,1684 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __USB_FSDEV_REG_H__ +#define __USB_FSDEV_REG_H__ + +#define __IO volatile /*!< Defines 'read / write' permissions */ +/** + * @brief Universal Serial Bus Full Speed Device + */ + +typedef struct +{ + __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */ + __IO uint16_t RESERVED0; /*!< Reserved */ + __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */ + __IO uint16_t RESERVED1; /*!< Reserved */ + __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */ + __IO uint16_t RESERVED2; /*!< Reserved */ + __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */ + __IO uint16_t RESERVED3; /*!< Reserved */ + __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */ + __IO uint16_t RESERVED4; /*!< Reserved */ + __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */ + __IO uint16_t RESERVED5; /*!< Reserved */ + __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */ + __IO uint16_t RESERVED6; /*!< Reserved */ + __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */ + __IO uint16_t RESERVED7[17]; /*!< Reserved */ + __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */ + __IO uint16_t RESERVED8; /*!< Reserved */ + __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */ + __IO uint16_t RESERVED9; /*!< Reserved */ + __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */ + __IO uint16_t RESERVEDA; /*!< Reserved */ + __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */ + __IO uint16_t RESERVEDB; /*!< Reserved */ + __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */ + __IO uint16_t RESERVEDC; /*!< Reserved */ + __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */ + __IO uint16_t RESERVEDD; /*!< Reserved */ + __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */ + __IO uint16_t RESERVEDE; /*!< Reserved */ +} USB_TypeDef; + +/******************************************************************************/ +/* */ +/* USB Device FS */ +/* */ +/******************************************************************************/ + +/*!< Endpoint-specific registers */ +#define USB_EP0R USB_BASE /*!< Endpoint 0 register address */ +#define USB_EP1R (USB_BASE + 0x00000004) /*!< Endpoint 1 register address */ +#define USB_EP2R (USB_BASE + 0x00000008) /*!< Endpoint 2 register address */ +#define USB_EP3R (USB_BASE + 0x0000000C) /*!< Endpoint 3 register address */ +#define USB_EP4R (USB_BASE + 0x00000010) /*!< Endpoint 4 register address */ +#define USB_EP5R (USB_BASE + 0x00000014) /*!< Endpoint 5 register address */ +#define USB_EP6R (USB_BASE + 0x00000018) /*!< Endpoint 6 register address */ +#define USB_EP7R (USB_BASE + 0x0000001C) /*!< Endpoint 7 register address */ + +/* bit positions */ +#define USB_EP_CTR_RX_Pos (15U) +#define USB_EP_CTR_RX_Msk (0x1UL << USB_EP_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP_CTR_RX USB_EP_CTR_RX_Msk /*!< EndPoint Correct TRansfer RX */ +#define USB_EP_DTOG_RX_Pos (14U) +#define USB_EP_DTOG_RX_Msk (0x1UL << USB_EP_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP_DTOG_RX USB_EP_DTOG_RX_Msk /*!< EndPoint Data TOGGLE RX */ +#define USB_EPRX_STAT_Pos (12U) +#define USB_EPRX_STAT_Msk (0x3UL << USB_EPRX_STAT_Pos) /*!< 0x00003000 */ +#define USB_EPRX_STAT USB_EPRX_STAT_Msk /*!< EndPoint RX STATus bit field */ +#define USB_EP_SETUP_Pos (11U) +#define USB_EP_SETUP_Msk (0x1UL << USB_EP_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP_SETUP USB_EP_SETUP_Msk /*!< EndPoint SETUP */ +#define USB_EP_T_FIELD_Pos (9U) +#define USB_EP_T_FIELD_Msk (0x3UL << USB_EP_T_FIELD_Pos) /*!< 0x00000600 */ +#define USB_EP_T_FIELD USB_EP_T_FIELD_Msk /*!< EndPoint TYPE */ +#define USB_EP_KIND_Pos (8U) +#define USB_EP_KIND_Msk (0x1UL << USB_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP_KIND USB_EP_KIND_Msk /*!< EndPoint KIND */ +#define USB_EP_CTR_TX_Pos (7U) +#define USB_EP_CTR_TX_Msk (0x1UL << USB_EP_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP_CTR_TX USB_EP_CTR_TX_Msk /*!< EndPoint Correct TRansfer TX */ +#define USB_EP_DTOG_TX_Pos (6U) +#define USB_EP_DTOG_TX_Msk (0x1UL << USB_EP_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP_DTOG_TX USB_EP_DTOG_TX_Msk /*!< EndPoint Data TOGGLE TX */ +#define USB_EPTX_STAT_Pos (4U) +#define USB_EPTX_STAT_Msk (0x3UL << USB_EPTX_STAT_Pos) /*!< 0x00000030 */ +#define USB_EPTX_STAT USB_EPTX_STAT_Msk /*!< EndPoint TX STATus bit field */ +#define USB_EPADDR_FIELD_Pos (0U) +#define USB_EPADDR_FIELD_Msk (0xFUL << USB_EPADDR_FIELD_Pos) /*!< 0x0000000F */ +#define USB_EPADDR_FIELD USB_EPADDR_FIELD_Msk /*!< EndPoint ADDRess FIELD */ + +/* EndPoint REGister MASK (no toggle fields) */ +#define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD) + /*!< EP_TYPE[1:0] EndPoint TYPE */ +#define USB_EP_TYPE_MASK_Pos (9U) +#define USB_EP_TYPE_MASK_Msk (0x3UL << USB_EP_TYPE_MASK_Pos) /*!< 0x00000600 */ +#define USB_EP_TYPE_MASK USB_EP_TYPE_MASK_Msk /*!< EndPoint TYPE Mask */ +#define USB_EP_BULK 0x00000000U /*!< EndPoint BULK */ +#define USB_EP_CONTROL 0x00000200U /*!< EndPoint CONTROL */ +#define USB_EP_ISOCHRONOUS 0x00000400U /*!< EndPoint ISOCHRONOUS */ +#define USB_EP_INTERRUPT 0x00000600U /*!< EndPoint INTERRUPT */ +#define USB_EP_T_MASK (~USB_EP_T_FIELD & USB_EPREG_MASK) + +#define USB_EPKIND_MASK (~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */ + /*!< STAT_TX[1:0] STATus for TX transfer */ +#define USB_EP_TX_DIS 0x00000000U /*!< EndPoint TX DISabled */ +#define USB_EP_TX_STALL 0x00000010U /*!< EndPoint TX STALLed */ +#define USB_EP_TX_NAK 0x00000020U /*!< EndPoint TX NAKed */ +#define USB_EP_TX_VALID 0x00000030U /*!< EndPoint TX VALID */ +#define USB_EPTX_DTOG1 0x00000010U /*!< EndPoint TX Data TOGgle bit1 */ +#define USB_EPTX_DTOG2 0x00000020U /*!< EndPoint TX Data TOGgle bit2 */ +#define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK) + /*!< STAT_RX[1:0] STATus for RX transfer */ +#define USB_EP_RX_DIS 0x00000000U /*!< EndPoint RX DISabled */ +#define USB_EP_RX_STALL 0x00001000U /*!< EndPoint RX STALLed */ +#define USB_EP_RX_NAK 0x00002000U /*!< EndPoint RX NAKed */ +#define USB_EP_RX_VALID 0x00003000U /*!< EndPoint RX VALID */ +#define USB_EPRX_DTOG1 0x00001000U /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOG2 0x00002000U /*!< EndPoint RX Data TOGgle bit1 */ +#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) + +/******************* Bit definition for USB_EP0R register *******************/ +#define USB_EP0R_EA_Pos (0U) +#define USB_EP0R_EA_Msk (0xFUL << USB_EP0R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP0R_EA USB_EP0R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP0R_STAT_TX_Pos (4U) +#define USB_EP0R_STAT_TX_Msk (0x3UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP0R_STAT_TX USB_EP0R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP0R_STAT_TX_0 (0x1UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP0R_STAT_TX_1 (0x2UL << USB_EP0R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP0R_DTOG_TX_Pos (6U) +#define USB_EP0R_DTOG_TX_Msk (0x1UL << USB_EP0R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP0R_DTOG_TX USB_EP0R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP0R_CTR_TX_Pos (7U) +#define USB_EP0R_CTR_TX_Msk (0x1UL << USB_EP0R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP0R_CTR_TX USB_EP0R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP0R_EP_KIND_Pos (8U) +#define USB_EP0R_EP_KIND_Msk (0x1UL << USB_EP0R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP0R_EP_KIND USB_EP0R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP0R_EP_TYPE_Pos (9U) +#define USB_EP0R_EP_TYPE_Msk (0x3UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP0R_EP_TYPE USB_EP0R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP0R_EP_TYPE_0 (0x1UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP0R_EP_TYPE_1 (0x2UL << USB_EP0R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP0R_SETUP_Pos (11U) +#define USB_EP0R_SETUP_Msk (0x1UL << USB_EP0R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP0R_SETUP USB_EP0R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP0R_STAT_RX_Pos (12U) +#define USB_EP0R_STAT_RX_Msk (0x3UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP0R_STAT_RX USB_EP0R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP0R_STAT_RX_0 (0x1UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP0R_STAT_RX_1 (0x2UL << USB_EP0R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP0R_DTOG_RX_Pos (14U) +#define USB_EP0R_DTOG_RX_Msk (0x1UL << USB_EP0R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP0R_DTOG_RX USB_EP0R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP0R_CTR_RX_Pos (15U) +#define USB_EP0R_CTR_RX_Msk (0x1UL << USB_EP0R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP0R_CTR_RX USB_EP0R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP1R register *******************/ +#define USB_EP1R_EA_Pos (0U) +#define USB_EP1R_EA_Msk (0xFUL << USB_EP1R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP1R_EA USB_EP1R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP1R_STAT_TX_Pos (4U) +#define USB_EP1R_STAT_TX_Msk (0x3UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP1R_STAT_TX USB_EP1R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP1R_STAT_TX_0 (0x1UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP1R_STAT_TX_1 (0x2UL << USB_EP1R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP1R_DTOG_TX_Pos (6U) +#define USB_EP1R_DTOG_TX_Msk (0x1UL << USB_EP1R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP1R_DTOG_TX USB_EP1R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP1R_CTR_TX_Pos (7U) +#define USB_EP1R_CTR_TX_Msk (0x1UL << USB_EP1R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP1R_CTR_TX USB_EP1R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP1R_EP_KIND_Pos (8U) +#define USB_EP1R_EP_KIND_Msk (0x1UL << USB_EP1R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP1R_EP_KIND USB_EP1R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP1R_EP_TYPE_Pos (9U) +#define USB_EP1R_EP_TYPE_Msk (0x3UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP1R_EP_TYPE USB_EP1R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP1R_EP_TYPE_0 (0x1UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP1R_EP_TYPE_1 (0x2UL << USB_EP1R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP1R_SETUP_Pos (11U) +#define USB_EP1R_SETUP_Msk (0x1UL << USB_EP1R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP1R_SETUP USB_EP1R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP1R_STAT_RX_Pos (12U) +#define USB_EP1R_STAT_RX_Msk (0x3UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP1R_STAT_RX USB_EP1R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP1R_STAT_RX_0 (0x1UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP1R_STAT_RX_1 (0x2UL << USB_EP1R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP1R_DTOG_RX_Pos (14U) +#define USB_EP1R_DTOG_RX_Msk (0x1UL << USB_EP1R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP1R_DTOG_RX USB_EP1R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP1R_CTR_RX_Pos (15U) +#define USB_EP1R_CTR_RX_Msk (0x1UL << USB_EP1R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP1R_CTR_RX USB_EP1R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP2R register *******************/ +#define USB_EP2R_EA_Pos (0U) +#define USB_EP2R_EA_Msk (0xFUL << USB_EP2R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP2R_EA USB_EP2R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP2R_STAT_TX_Pos (4U) +#define USB_EP2R_STAT_TX_Msk (0x3UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP2R_STAT_TX USB_EP2R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP2R_STAT_TX_0 (0x1UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP2R_STAT_TX_1 (0x2UL << USB_EP2R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP2R_DTOG_TX_Pos (6U) +#define USB_EP2R_DTOG_TX_Msk (0x1UL << USB_EP2R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP2R_DTOG_TX USB_EP2R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP2R_CTR_TX_Pos (7U) +#define USB_EP2R_CTR_TX_Msk (0x1UL << USB_EP2R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP2R_CTR_TX USB_EP2R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP2R_EP_KIND_Pos (8U) +#define USB_EP2R_EP_KIND_Msk (0x1UL << USB_EP2R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP2R_EP_KIND USB_EP2R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP2R_EP_TYPE_Pos (9U) +#define USB_EP2R_EP_TYPE_Msk (0x3UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP2R_EP_TYPE USB_EP2R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP2R_EP_TYPE_0 (0x1UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP2R_EP_TYPE_1 (0x2UL << USB_EP2R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP2R_SETUP_Pos (11U) +#define USB_EP2R_SETUP_Msk (0x1UL << USB_EP2R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP2R_SETUP USB_EP2R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP2R_STAT_RX_Pos (12U) +#define USB_EP2R_STAT_RX_Msk (0x3UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP2R_STAT_RX USB_EP2R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP2R_STAT_RX_0 (0x1UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP2R_STAT_RX_1 (0x2UL << USB_EP2R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP2R_DTOG_RX_Pos (14U) +#define USB_EP2R_DTOG_RX_Msk (0x1UL << USB_EP2R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP2R_DTOG_RX USB_EP2R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP2R_CTR_RX_Pos (15U) +#define USB_EP2R_CTR_RX_Msk (0x1UL << USB_EP2R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP2R_CTR_RX USB_EP2R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP3R register *******************/ +#define USB_EP3R_EA_Pos (0U) +#define USB_EP3R_EA_Msk (0xFUL << USB_EP3R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP3R_EA USB_EP3R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP3R_STAT_TX_Pos (4U) +#define USB_EP3R_STAT_TX_Msk (0x3UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP3R_STAT_TX USB_EP3R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP3R_STAT_TX_0 (0x1UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP3R_STAT_TX_1 (0x2UL << USB_EP3R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP3R_DTOG_TX_Pos (6U) +#define USB_EP3R_DTOG_TX_Msk (0x1UL << USB_EP3R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP3R_DTOG_TX USB_EP3R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP3R_CTR_TX_Pos (7U) +#define USB_EP3R_CTR_TX_Msk (0x1UL << USB_EP3R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP3R_CTR_TX USB_EP3R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP3R_EP_KIND_Pos (8U) +#define USB_EP3R_EP_KIND_Msk (0x1UL << USB_EP3R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP3R_EP_KIND USB_EP3R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP3R_EP_TYPE_Pos (9U) +#define USB_EP3R_EP_TYPE_Msk (0x3UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP3R_EP_TYPE USB_EP3R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP3R_EP_TYPE_0 (0x1UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP3R_EP_TYPE_1 (0x2UL << USB_EP3R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP3R_SETUP_Pos (11U) +#define USB_EP3R_SETUP_Msk (0x1UL << USB_EP3R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP3R_SETUP USB_EP3R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP3R_STAT_RX_Pos (12U) +#define USB_EP3R_STAT_RX_Msk (0x3UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP3R_STAT_RX USB_EP3R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP3R_STAT_RX_0 (0x1UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP3R_STAT_RX_1 (0x2UL << USB_EP3R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP3R_DTOG_RX_Pos (14U) +#define USB_EP3R_DTOG_RX_Msk (0x1UL << USB_EP3R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP3R_DTOG_RX USB_EP3R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP3R_CTR_RX_Pos (15U) +#define USB_EP3R_CTR_RX_Msk (0x1UL << USB_EP3R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP3R_CTR_RX USB_EP3R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP4R register *******************/ +#define USB_EP4R_EA_Pos (0U) +#define USB_EP4R_EA_Msk (0xFUL << USB_EP4R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP4R_EA USB_EP4R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP4R_STAT_TX_Pos (4U) +#define USB_EP4R_STAT_TX_Msk (0x3UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP4R_STAT_TX USB_EP4R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP4R_STAT_TX_0 (0x1UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP4R_STAT_TX_1 (0x2UL << USB_EP4R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP4R_DTOG_TX_Pos (6U) +#define USB_EP4R_DTOG_TX_Msk (0x1UL << USB_EP4R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP4R_DTOG_TX USB_EP4R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP4R_CTR_TX_Pos (7U) +#define USB_EP4R_CTR_TX_Msk (0x1UL << USB_EP4R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP4R_CTR_TX USB_EP4R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP4R_EP_KIND_Pos (8U) +#define USB_EP4R_EP_KIND_Msk (0x1UL << USB_EP4R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP4R_EP_KIND USB_EP4R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP4R_EP_TYPE_Pos (9U) +#define USB_EP4R_EP_TYPE_Msk (0x3UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP4R_EP_TYPE USB_EP4R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP4R_EP_TYPE_0 (0x1UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP4R_EP_TYPE_1 (0x2UL << USB_EP4R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP4R_SETUP_Pos (11U) +#define USB_EP4R_SETUP_Msk (0x1UL << USB_EP4R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP4R_SETUP USB_EP4R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP4R_STAT_RX_Pos (12U) +#define USB_EP4R_STAT_RX_Msk (0x3UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP4R_STAT_RX USB_EP4R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP4R_STAT_RX_0 (0x1UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP4R_STAT_RX_1 (0x2UL << USB_EP4R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP4R_DTOG_RX_Pos (14U) +#define USB_EP4R_DTOG_RX_Msk (0x1UL << USB_EP4R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP4R_DTOG_RX USB_EP4R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP4R_CTR_RX_Pos (15U) +#define USB_EP4R_CTR_RX_Msk (0x1UL << USB_EP4R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP4R_CTR_RX USB_EP4R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP5R register *******************/ +#define USB_EP5R_EA_Pos (0U) +#define USB_EP5R_EA_Msk (0xFUL << USB_EP5R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP5R_EA USB_EP5R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP5R_STAT_TX_Pos (4U) +#define USB_EP5R_STAT_TX_Msk (0x3UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP5R_STAT_TX USB_EP5R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP5R_STAT_TX_0 (0x1UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP5R_STAT_TX_1 (0x2UL << USB_EP5R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP5R_DTOG_TX_Pos (6U) +#define USB_EP5R_DTOG_TX_Msk (0x1UL << USB_EP5R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP5R_DTOG_TX USB_EP5R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP5R_CTR_TX_Pos (7U) +#define USB_EP5R_CTR_TX_Msk (0x1UL << USB_EP5R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP5R_CTR_TX USB_EP5R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP5R_EP_KIND_Pos (8U) +#define USB_EP5R_EP_KIND_Msk (0x1UL << USB_EP5R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP5R_EP_KIND USB_EP5R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP5R_EP_TYPE_Pos (9U) +#define USB_EP5R_EP_TYPE_Msk (0x3UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP5R_EP_TYPE USB_EP5R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP5R_EP_TYPE_0 (0x1UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP5R_EP_TYPE_1 (0x2UL << USB_EP5R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP5R_SETUP_Pos (11U) +#define USB_EP5R_SETUP_Msk (0x1UL << USB_EP5R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP5R_SETUP USB_EP5R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP5R_STAT_RX_Pos (12U) +#define USB_EP5R_STAT_RX_Msk (0x3UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP5R_STAT_RX USB_EP5R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP5R_STAT_RX_0 (0x1UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP5R_STAT_RX_1 (0x2UL << USB_EP5R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP5R_DTOG_RX_Pos (14U) +#define USB_EP5R_DTOG_RX_Msk (0x1UL << USB_EP5R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP5R_DTOG_RX USB_EP5R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP5R_CTR_RX_Pos (15U) +#define USB_EP5R_CTR_RX_Msk (0x1UL << USB_EP5R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP5R_CTR_RX USB_EP5R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP6R register *******************/ +#define USB_EP6R_EA_Pos (0U) +#define USB_EP6R_EA_Msk (0xFUL << USB_EP6R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP6R_EA USB_EP6R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP6R_STAT_TX_Pos (4U) +#define USB_EP6R_STAT_TX_Msk (0x3UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP6R_STAT_TX USB_EP6R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP6R_STAT_TX_0 (0x1UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP6R_STAT_TX_1 (0x2UL << USB_EP6R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP6R_DTOG_TX_Pos (6U) +#define USB_EP6R_DTOG_TX_Msk (0x1UL << USB_EP6R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP6R_DTOG_TX USB_EP6R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP6R_CTR_TX_Pos (7U) +#define USB_EP6R_CTR_TX_Msk (0x1UL << USB_EP6R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP6R_CTR_TX USB_EP6R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP6R_EP_KIND_Pos (8U) +#define USB_EP6R_EP_KIND_Msk (0x1UL << USB_EP6R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP6R_EP_KIND USB_EP6R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP6R_EP_TYPE_Pos (9U) +#define USB_EP6R_EP_TYPE_Msk (0x3UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP6R_EP_TYPE USB_EP6R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP6R_EP_TYPE_0 (0x1UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP6R_EP_TYPE_1 (0x2UL << USB_EP6R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP6R_SETUP_Pos (11U) +#define USB_EP6R_SETUP_Msk (0x1UL << USB_EP6R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP6R_SETUP USB_EP6R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP6R_STAT_RX_Pos (12U) +#define USB_EP6R_STAT_RX_Msk (0x3UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP6R_STAT_RX USB_EP6R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP6R_STAT_RX_0 (0x1UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP6R_STAT_RX_1 (0x2UL << USB_EP6R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP6R_DTOG_RX_Pos (14U) +#define USB_EP6R_DTOG_RX_Msk (0x1UL << USB_EP6R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP6R_DTOG_RX USB_EP6R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP6R_CTR_RX_Pos (15U) +#define USB_EP6R_CTR_RX_Msk (0x1UL << USB_EP6R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP6R_CTR_RX USB_EP6R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/******************* Bit definition for USB_EP7R register *******************/ +#define USB_EP7R_EA_Pos (0U) +#define USB_EP7R_EA_Msk (0xFUL << USB_EP7R_EA_Pos) /*!< 0x0000000F */ +#define USB_EP7R_EA USB_EP7R_EA_Msk /*!< Endpoint Address */ + +#define USB_EP7R_STAT_TX_Pos (4U) +#define USB_EP7R_STAT_TX_Msk (0x3UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000030 */ +#define USB_EP7R_STAT_TX USB_EP7R_STAT_TX_Msk /*!< STAT_TX[1:0] bits (Status bits, for transmission transfers) */ +#define USB_EP7R_STAT_TX_0 (0x1UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000010 */ +#define USB_EP7R_STAT_TX_1 (0x2UL << USB_EP7R_STAT_TX_Pos) /*!< 0x00000020 */ + +#define USB_EP7R_DTOG_TX_Pos (6U) +#define USB_EP7R_DTOG_TX_Msk (0x1UL << USB_EP7R_DTOG_TX_Pos) /*!< 0x00000040 */ +#define USB_EP7R_DTOG_TX USB_EP7R_DTOG_TX_Msk /*!< Data Toggle, for transmission transfers */ +#define USB_EP7R_CTR_TX_Pos (7U) +#define USB_EP7R_CTR_TX_Msk (0x1UL << USB_EP7R_CTR_TX_Pos) /*!< 0x00000080 */ +#define USB_EP7R_CTR_TX USB_EP7R_CTR_TX_Msk /*!< Correct Transfer for transmission */ +#define USB_EP7R_EP_KIND_Pos (8U) +#define USB_EP7R_EP_KIND_Msk (0x1UL << USB_EP7R_EP_KIND_Pos) /*!< 0x00000100 */ +#define USB_EP7R_EP_KIND USB_EP7R_EP_KIND_Msk /*!< Endpoint Kind */ + +#define USB_EP7R_EP_TYPE_Pos (9U) +#define USB_EP7R_EP_TYPE_Msk (0x3UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000600 */ +#define USB_EP7R_EP_TYPE USB_EP7R_EP_TYPE_Msk /*!< EP_TYPE[1:0] bits (Endpoint type) */ +#define USB_EP7R_EP_TYPE_0 (0x1UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000200 */ +#define USB_EP7R_EP_TYPE_1 (0x2UL << USB_EP7R_EP_TYPE_Pos) /*!< 0x00000400 */ + +#define USB_EP7R_SETUP_Pos (11U) +#define USB_EP7R_SETUP_Msk (0x1UL << USB_EP7R_SETUP_Pos) /*!< 0x00000800 */ +#define USB_EP7R_SETUP USB_EP7R_SETUP_Msk /*!< Setup transaction completed */ + +#define USB_EP7R_STAT_RX_Pos (12U) +#define USB_EP7R_STAT_RX_Msk (0x3UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00003000 */ +#define USB_EP7R_STAT_RX USB_EP7R_STAT_RX_Msk /*!< STAT_RX[1:0] bits (Status bits, for reception transfers) */ +#define USB_EP7R_STAT_RX_0 (0x1UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00001000 */ +#define USB_EP7R_STAT_RX_1 (0x2UL << USB_EP7R_STAT_RX_Pos) /*!< 0x00002000 */ + +#define USB_EP7R_DTOG_RX_Pos (14U) +#define USB_EP7R_DTOG_RX_Msk (0x1UL << USB_EP7R_DTOG_RX_Pos) /*!< 0x00004000 */ +#define USB_EP7R_DTOG_RX USB_EP7R_DTOG_RX_Msk /*!< Data Toggle, for reception transfers */ +#define USB_EP7R_CTR_RX_Pos (15U) +#define USB_EP7R_CTR_RX_Msk (0x1UL << USB_EP7R_CTR_RX_Pos) /*!< 0x00008000 */ +#define USB_EP7R_CTR_RX USB_EP7R_CTR_RX_Msk /*!< Correct Transfer for reception */ + +/*!< Common registers */ +/******************* Bit definition for USB_CNTR register *******************/ +#define USB_CNTR_FRES_Pos (0U) +#define USB_CNTR_FRES_Msk (0x1UL << USB_CNTR_FRES_Pos) /*!< 0x00000001 */ +#define USB_CNTR_FRES USB_CNTR_FRES_Msk /*!< Force USB Reset */ +#define USB_CNTR_PDWN_Pos (1U) +#define USB_CNTR_PDWN_Msk (0x1UL << USB_CNTR_PDWN_Pos) /*!< 0x00000002 */ +#define USB_CNTR_PDWN USB_CNTR_PDWN_Msk /*!< Power down */ +#define USB_CNTR_LP_MODE_Pos (2U) +#define USB_CNTR_LP_MODE_Msk (0x1UL << USB_CNTR_LP_MODE_Pos) /*!< 0x00000004 */ +#define USB_CNTR_LP_MODE USB_CNTR_LP_MODE_Msk /*!< Low-power mode */ +#define USB_CNTR_FSUSP_Pos (3U) +#define USB_CNTR_FSUSP_Msk (0x1UL << USB_CNTR_FSUSP_Pos) /*!< 0x00000008 */ +#define USB_CNTR_FSUSP USB_CNTR_FSUSP_Msk /*!< Force suspend */ +#define USB_CNTR_RESUME_Pos (4U) +#define USB_CNTR_RESUME_Msk (0x1UL << USB_CNTR_RESUME_Pos) /*!< 0x00000010 */ +#define USB_CNTR_RESUME USB_CNTR_RESUME_Msk /*!< Resume request */ +#define USB_CNTR_ESOFM_Pos (8U) +#define USB_CNTR_ESOFM_Msk (0x1UL << USB_CNTR_ESOFM_Pos) /*!< 0x00000100 */ +#define USB_CNTR_ESOFM USB_CNTR_ESOFM_Msk /*!< Expected Start Of Frame Interrupt Mask */ +#define USB_CNTR_SOFM_Pos (9U) +#define USB_CNTR_SOFM_Msk (0x1UL << USB_CNTR_SOFM_Pos) /*!< 0x00000200 */ +#define USB_CNTR_SOFM USB_CNTR_SOFM_Msk /*!< Start Of Frame Interrupt Mask */ +#define USB_CNTR_RESETM_Pos (10U) +#define USB_CNTR_RESETM_Msk (0x1UL << USB_CNTR_RESETM_Pos) /*!< 0x00000400 */ +#define USB_CNTR_RESETM USB_CNTR_RESETM_Msk /*!< RESET Interrupt Mask */ +#define USB_CNTR_SUSPM_Pos (11U) +#define USB_CNTR_SUSPM_Msk (0x1UL << USB_CNTR_SUSPM_Pos) /*!< 0x00000800 */ +#define USB_CNTR_SUSPM USB_CNTR_SUSPM_Msk /*!< Suspend mode Interrupt Mask */ +#define USB_CNTR_WKUPM_Pos (12U) +#define USB_CNTR_WKUPM_Msk (0x1UL << USB_CNTR_WKUPM_Pos) /*!< 0x00001000 */ +#define USB_CNTR_WKUPM USB_CNTR_WKUPM_Msk /*!< Wakeup Interrupt Mask */ +#define USB_CNTR_ERRM_Pos (13U) +#define USB_CNTR_ERRM_Msk (0x1UL << USB_CNTR_ERRM_Pos) /*!< 0x00002000 */ +#define USB_CNTR_ERRM USB_CNTR_ERRM_Msk /*!< Error Interrupt Mask */ +#define USB_CNTR_PMAOVRM_Pos (14U) +#define USB_CNTR_PMAOVRM_Msk (0x1UL << USB_CNTR_PMAOVRM_Pos) /*!< 0x00004000 */ +#define USB_CNTR_PMAOVRM USB_CNTR_PMAOVRM_Msk /*!< Packet Memory Area Over / Underrun Interrupt Mask */ +#define USB_CNTR_CTRM_Pos (15U) +#define USB_CNTR_CTRM_Msk (0x1UL << USB_CNTR_CTRM_Pos) /*!< 0x00008000 */ +#define USB_CNTR_CTRM USB_CNTR_CTRM_Msk /*!< Correct Transfer Interrupt Mask */ + +/******************* Bit definition for USB_ISTR register *******************/ +#define USB_ISTR_EP_ID_Pos (0U) +#define USB_ISTR_EP_ID_Msk (0xFUL << USB_ISTR_EP_ID_Pos) /*!< 0x0000000F */ +#define USB_ISTR_EP_ID USB_ISTR_EP_ID_Msk /*!< Endpoint Identifier */ +#define USB_ISTR_DIR_Pos (4U) +#define USB_ISTR_DIR_Msk (0x1UL << USB_ISTR_DIR_Pos) /*!< 0x00000010 */ +#define USB_ISTR_DIR USB_ISTR_DIR_Msk /*!< Direction of transaction */ +#define USB_ISTR_ESOF_Pos (8U) +#define USB_ISTR_ESOF_Msk (0x1UL << USB_ISTR_ESOF_Pos) /*!< 0x00000100 */ +#define USB_ISTR_ESOF USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame */ +#define USB_ISTR_SOF_Pos (9U) +#define USB_ISTR_SOF_Msk (0x1UL << USB_ISTR_SOF_Pos) /*!< 0x00000200 */ +#define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame */ +#define USB_ISTR_RESET_Pos (10U) +#define USB_ISTR_RESET_Msk (0x1UL << USB_ISTR_RESET_Pos) /*!< 0x00000400 */ +#define USB_ISTR_RESET USB_ISTR_RESET_Msk /*!< USB RESET request */ +#define USB_ISTR_SUSP_Pos (11U) +#define USB_ISTR_SUSP_Msk (0x1UL << USB_ISTR_SUSP_Pos) /*!< 0x00000800 */ +#define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< Suspend mode request */ +#define USB_ISTR_WKUP_Pos (12U) +#define USB_ISTR_WKUP_Msk (0x1UL << USB_ISTR_WKUP_Pos) /*!< 0x00001000 */ +#define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< Wake up */ +#define USB_ISTR_ERR_Pos (13U) +#define USB_ISTR_ERR_Msk (0x1UL << USB_ISTR_ERR_Pos) /*!< 0x00002000 */ +#define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< Error */ +#define USB_ISTR_PMAOVR_Pos (14U) +#define USB_ISTR_PMAOVR_Msk (0x1UL << USB_ISTR_PMAOVR_Pos) /*!< 0x00004000 */ +#define USB_ISTR_PMAOVR USB_ISTR_PMAOVR_Msk /*!< Packet Memory Area Over / Underrun */ +#define USB_ISTR_CTR_Pos (15U) +#define USB_ISTR_CTR_Msk (0x1UL << USB_ISTR_CTR_Pos) /*!< 0x00008000 */ +#define USB_ISTR_CTR USB_ISTR_CTR_Msk /*!< Correct Transfer */ + +/******************* Bit definition for USB_FNR register ********************/ +#define USB_FNR_FN_Pos (0U) +#define USB_FNR_FN_Msk (0x7FFUL << USB_FNR_FN_Pos) /*!< 0x000007FF */ +#define USB_FNR_FN USB_FNR_FN_Msk /*!< Frame Number */ +#define USB_FNR_LSOF_Pos (11U) +#define USB_FNR_LSOF_Msk (0x3UL << USB_FNR_LSOF_Pos) /*!< 0x00001800 */ +#define USB_FNR_LSOF USB_FNR_LSOF_Msk /*!< Lost SOF */ +#define USB_FNR_LCK_Pos (13U) +#define USB_FNR_LCK_Msk (0x1UL << USB_FNR_LCK_Pos) /*!< 0x00002000 */ +#define USB_FNR_LCK USB_FNR_LCK_Msk /*!< Locked */ +#define USB_FNR_RXDM_Pos (14U) +#define USB_FNR_RXDM_Msk (0x1UL << USB_FNR_RXDM_Pos) /*!< 0x00004000 */ +#define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< Receive Data - Line Status */ +#define USB_FNR_RXDP_Pos (15U) +#define USB_FNR_RXDP_Msk (0x1UL << USB_FNR_RXDP_Pos) /*!< 0x00008000 */ +#define USB_FNR_RXDP USB_FNR_RXDP_Msk /*!< Receive Data + Line Status */ + +/****************** Bit definition for USB_DADDR register *******************/ +#define USB_DADDR_ADD_Pos (0U) +#define USB_DADDR_ADD_Msk (0x7FUL << USB_DADDR_ADD_Pos) /*!< 0x0000007F */ +#define USB_DADDR_ADD USB_DADDR_ADD_Msk /*!< ADD[6:0] bits (Device Address) */ +#define USB_DADDR_ADD0_Pos (0U) +#define USB_DADDR_ADD0_Msk (0x1UL << USB_DADDR_ADD0_Pos) /*!< 0x00000001 */ +#define USB_DADDR_ADD0 USB_DADDR_ADD0_Msk /*!< Bit 0 */ +#define USB_DADDR_ADD1_Pos (1U) +#define USB_DADDR_ADD1_Msk (0x1UL << USB_DADDR_ADD1_Pos) /*!< 0x00000002 */ +#define USB_DADDR_ADD1 USB_DADDR_ADD1_Msk /*!< Bit 1 */ +#define USB_DADDR_ADD2_Pos (2U) +#define USB_DADDR_ADD2_Msk (0x1UL << USB_DADDR_ADD2_Pos) /*!< 0x00000004 */ +#define USB_DADDR_ADD2 USB_DADDR_ADD2_Msk /*!< Bit 2 */ +#define USB_DADDR_ADD3_Pos (3U) +#define USB_DADDR_ADD3_Msk (0x1UL << USB_DADDR_ADD3_Pos) /*!< 0x00000008 */ +#define USB_DADDR_ADD3 USB_DADDR_ADD3_Msk /*!< Bit 3 */ +#define USB_DADDR_ADD4_Pos (4U) +#define USB_DADDR_ADD4_Msk (0x1UL << USB_DADDR_ADD4_Pos) /*!< 0x00000010 */ +#define USB_DADDR_ADD4 USB_DADDR_ADD4_Msk /*!< Bit 4 */ +#define USB_DADDR_ADD5_Pos (5U) +#define USB_DADDR_ADD5_Msk (0x1UL << USB_DADDR_ADD5_Pos) /*!< 0x00000020 */ +#define USB_DADDR_ADD5 USB_DADDR_ADD5_Msk /*!< Bit 5 */ +#define USB_DADDR_ADD6_Pos (6U) +#define USB_DADDR_ADD6_Msk (0x1UL << USB_DADDR_ADD6_Pos) /*!< 0x00000040 */ +#define USB_DADDR_ADD6 USB_DADDR_ADD6_Msk /*!< Bit 6 */ + +#define USB_DADDR_EF_Pos (7U) +#define USB_DADDR_EF_Msk (0x1UL << USB_DADDR_EF_Pos) /*!< 0x00000080 */ +#define USB_DADDR_EF USB_DADDR_EF_Msk /*!< Enable Function */ + +/****************** Bit definition for USB_BTABLE register ******************/ +#define USB_BTABLE_BTABLE_Pos (3U) +#define USB_BTABLE_BTABLE_Msk (0x1FFFUL << USB_BTABLE_BTABLE_Pos) /*!< 0x0000FFF8 */ +#define USB_BTABLE_BTABLE USB_BTABLE_BTABLE_Msk /*!< Buffer Table */ + +/****************** Bits definition for USB_BCDR register *******************/ +#define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */ +#define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */ +#define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */ +#define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */ +#define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */ +#define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */ +#define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */ +#define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */ +#define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */ + +/******************* Bit definition for LPMCSR register *********************/ +#define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */ +#define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/ +#define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */ +#define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */ + +/*!< Buffer descriptor table */ +/***************** Bit definition for USB_ADDR0_TX register *****************/ +#define USB_ADDR0_TX_ADDR0_TX_Pos (1U) +#define USB_ADDR0_TX_ADDR0_TX_Msk (0x7FFFUL << USB_ADDR0_TX_ADDR0_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR0_TX_ADDR0_TX USB_ADDR0_TX_ADDR0_TX_Msk /*!< Transmission Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_TX register *****************/ +#define USB_ADDR1_TX_ADDR1_TX_Pos (1U) +#define USB_ADDR1_TX_ADDR1_TX_Msk (0x7FFFUL << USB_ADDR1_TX_ADDR1_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR1_TX_ADDR1_TX USB_ADDR1_TX_ADDR1_TX_Msk /*!< Transmission Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_TX register *****************/ +#define USB_ADDR2_TX_ADDR2_TX_Pos (1U) +#define USB_ADDR2_TX_ADDR2_TX_Msk (0x7FFFUL << USB_ADDR2_TX_ADDR2_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR2_TX_ADDR2_TX USB_ADDR2_TX_ADDR2_TX_Msk /*!< Transmission Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_TX register *****************/ +#define USB_ADDR3_TX_ADDR3_TX_Pos (1U) +#define USB_ADDR3_TX_ADDR3_TX_Msk (0x7FFFUL << USB_ADDR3_TX_ADDR3_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR3_TX_ADDR3_TX USB_ADDR3_TX_ADDR3_TX_Msk /*!< Transmission Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_TX register *****************/ +#define USB_ADDR4_TX_ADDR4_TX_Pos (1U) +#define USB_ADDR4_TX_ADDR4_TX_Msk (0x7FFFUL << USB_ADDR4_TX_ADDR4_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR4_TX_ADDR4_TX USB_ADDR4_TX_ADDR4_TX_Msk /*!< Transmission Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_TX register *****************/ +#define USB_ADDR5_TX_ADDR5_TX_Pos (1U) +#define USB_ADDR5_TX_ADDR5_TX_Msk (0x7FFFUL << USB_ADDR5_TX_ADDR5_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR5_TX_ADDR5_TX USB_ADDR5_TX_ADDR5_TX_Msk /*!< Transmission Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_TX register *****************/ +#define USB_ADDR6_TX_ADDR6_TX_Pos (1U) +#define USB_ADDR6_TX_ADDR6_TX_Msk (0x7FFFUL << USB_ADDR6_TX_ADDR6_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR6_TX_ADDR6_TX USB_ADDR6_TX_ADDR6_TX_Msk /*!< Transmission Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_TX register *****************/ +#define USB_ADDR7_TX_ADDR7_TX_Pos (1U) +#define USB_ADDR7_TX_ADDR7_TX_Msk (0x7FFFUL << USB_ADDR7_TX_ADDR7_TX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR7_TX_ADDR7_TX USB_ADDR7_TX_ADDR7_TX_Msk /*!< Transmission Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_TX register ****************/ +#define USB_COUNT0_TX_COUNT0_TX_Pos (0U) +#define USB_COUNT0_TX_COUNT0_TX_Msk (0x3FFUL << USB_COUNT0_TX_COUNT0_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT0_TX_COUNT0_TX USB_COUNT0_TX_COUNT0_TX_Msk /*!< Transmission Byte Count 0 */ + +/***************** Bit definition for USB_COUNT1_TX register ****************/ +#define USB_COUNT1_TX_COUNT1_TX_Pos (0U) +#define USB_COUNT1_TX_COUNT1_TX_Msk (0x3FFUL << USB_COUNT1_TX_COUNT1_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT1_TX_COUNT1_TX USB_COUNT1_TX_COUNT1_TX_Msk /*!< Transmission Byte Count 1 */ + +/***************** Bit definition for USB_COUNT2_TX register ****************/ +#define USB_COUNT2_TX_COUNT2_TX_Pos (0U) +#define USB_COUNT2_TX_COUNT2_TX_Msk (0x3FFUL << USB_COUNT2_TX_COUNT2_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT2_TX_COUNT2_TX USB_COUNT2_TX_COUNT2_TX_Msk /*!< Transmission Byte Count 2 */ + +/***************** Bit definition for USB_COUNT3_TX register ****************/ +#define USB_COUNT3_TX_COUNT3_TX_Pos (0U) +#define USB_COUNT3_TX_COUNT3_TX_Msk (0x3FFUL << USB_COUNT3_TX_COUNT3_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT3_TX_COUNT3_TX USB_COUNT3_TX_COUNT3_TX_Msk /*!< Transmission Byte Count 3 */ + +/***************** Bit definition for USB_COUNT4_TX register ****************/ +#define USB_COUNT4_TX_COUNT4_TX_Pos (0U) +#define USB_COUNT4_TX_COUNT4_TX_Msk (0x3FFUL << USB_COUNT4_TX_COUNT4_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT4_TX_COUNT4_TX USB_COUNT4_TX_COUNT4_TX_Msk /*!< Transmission Byte Count 4 */ + +/***************** Bit definition for USB_COUNT5_TX register ****************/ +#define USB_COUNT5_TX_COUNT5_TX_Pos (0U) +#define USB_COUNT5_TX_COUNT5_TX_Msk (0x3FFUL << USB_COUNT5_TX_COUNT5_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT5_TX_COUNT5_TX USB_COUNT5_TX_COUNT5_TX_Msk /*!< Transmission Byte Count 5 */ + +/***************** Bit definition for USB_COUNT6_TX register ****************/ +#define USB_COUNT6_TX_COUNT6_TX_Pos (0U) +#define USB_COUNT6_TX_COUNT6_TX_Msk (0x3FFUL << USB_COUNT6_TX_COUNT6_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT6_TX_COUNT6_TX USB_COUNT6_TX_COUNT6_TX_Msk /*!< Transmission Byte Count 6 */ + +/***************** Bit definition for USB_COUNT7_TX register ****************/ +#define USB_COUNT7_TX_COUNT7_TX_Pos (0U) +#define USB_COUNT7_TX_COUNT7_TX_Msk (0x3FFUL << USB_COUNT7_TX_COUNT7_TX_Pos) /*!< 0x000003FF */ +#define USB_COUNT7_TX_COUNT7_TX USB_COUNT7_TX_COUNT7_TX_Msk /*!< Transmission Byte Count 7 */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_TX_0 register ***************/ +#define USB_COUNT0_TX_0_COUNT0_TX_0 0x000003FFU /*!< Transmission Byte Count 0 (low) */ + +/**************** Bit definition for USB_COUNT0_TX_1 register ***************/ +#define USB_COUNT0_TX_1_COUNT0_TX_1 0x03FF0000U /*!< Transmission Byte Count 0 (high) */ + +/**************** Bit definition for USB_COUNT1_TX_0 register ***************/ +#define USB_COUNT1_TX_0_COUNT1_TX_0 0x000003FFU /*!< Transmission Byte Count 1 (low) */ + +/**************** Bit definition for USB_COUNT1_TX_1 register ***************/ +#define USB_COUNT1_TX_1_COUNT1_TX_1 0x03FF0000U /*!< Transmission Byte Count 1 (high) */ + +/**************** Bit definition for USB_COUNT2_TX_0 register ***************/ +#define USB_COUNT2_TX_0_COUNT2_TX_0 0x000003FFU /*!< Transmission Byte Count 2 (low) */ + +/**************** Bit definition for USB_COUNT2_TX_1 register ***************/ +#define USB_COUNT2_TX_1_COUNT2_TX_1 0x03FF0000U /*!< Transmission Byte Count 2 (high) */ + +/**************** Bit definition for USB_COUNT3_TX_0 register ***************/ +#define USB_COUNT3_TX_0_COUNT3_TX_0 0x000003FFU /*!< Transmission Byte Count 3 (low) */ + +/**************** Bit definition for USB_COUNT3_TX_1 register ***************/ +#define USB_COUNT3_TX_1_COUNT3_TX_1 0x03FF0000U /*!< Transmission Byte Count 3 (high) */ + +/**************** Bit definition for USB_COUNT4_TX_0 register ***************/ +#define USB_COUNT4_TX_0_COUNT4_TX_0 0x000003FFU /*!< Transmission Byte Count 4 (low) */ + +/**************** Bit definition for USB_COUNT4_TX_1 register ***************/ +#define USB_COUNT4_TX_1_COUNT4_TX_1 0x03FF0000U /*!< Transmission Byte Count 4 (high) */ + +/**************** Bit definition for USB_COUNT5_TX_0 register ***************/ +#define USB_COUNT5_TX_0_COUNT5_TX_0 0x000003FFU /*!< Transmission Byte Count 5 (low) */ + +/**************** Bit definition for USB_COUNT5_TX_1 register ***************/ +#define USB_COUNT5_TX_1_COUNT5_TX_1 0x03FF0000U /*!< Transmission Byte Count 5 (high) */ + +/**************** Bit definition for USB_COUNT6_TX_0 register ***************/ +#define USB_COUNT6_TX_0_COUNT6_TX_0 0x000003FFU /*!< Transmission Byte Count 6 (low) */ + +/**************** Bit definition for USB_COUNT6_TX_1 register ***************/ +#define USB_COUNT6_TX_1_COUNT6_TX_1 0x03FF0000U /*!< Transmission Byte Count 6 (high) */ + +/**************** Bit definition for USB_COUNT7_TX_0 register ***************/ +#define USB_COUNT7_TX_0_COUNT7_TX_0 0x000003FFU /*!< Transmission Byte Count 7 (low) */ + +/**************** Bit definition for USB_COUNT7_TX_1 register ***************/ +#define USB_COUNT7_TX_1_COUNT7_TX_1 0x03FF0000U /*!< Transmission Byte Count 7 (high) */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_ADDR0_RX register *****************/ +#define USB_ADDR0_RX_ADDR0_RX_Pos (1U) +#define USB_ADDR0_RX_ADDR0_RX_Msk (0x7FFFUL << USB_ADDR0_RX_ADDR0_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR0_RX_ADDR0_RX USB_ADDR0_RX_ADDR0_RX_Msk /*!< Reception Buffer Address 0 */ + +/***************** Bit definition for USB_ADDR1_RX register *****************/ +#define USB_ADDR1_RX_ADDR1_RX_Pos (1U) +#define USB_ADDR1_RX_ADDR1_RX_Msk (0x7FFFUL << USB_ADDR1_RX_ADDR1_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR1_RX_ADDR1_RX USB_ADDR1_RX_ADDR1_RX_Msk /*!< Reception Buffer Address 1 */ + +/***************** Bit definition for USB_ADDR2_RX register *****************/ +#define USB_ADDR2_RX_ADDR2_RX_Pos (1U) +#define USB_ADDR2_RX_ADDR2_RX_Msk (0x7FFFUL << USB_ADDR2_RX_ADDR2_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR2_RX_ADDR2_RX USB_ADDR2_RX_ADDR2_RX_Msk /*!< Reception Buffer Address 2 */ + +/***************** Bit definition for USB_ADDR3_RX register *****************/ +#define USB_ADDR3_RX_ADDR3_RX_Pos (1U) +#define USB_ADDR3_RX_ADDR3_RX_Msk (0x7FFFUL << USB_ADDR3_RX_ADDR3_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR3_RX_ADDR3_RX USB_ADDR3_RX_ADDR3_RX_Msk /*!< Reception Buffer Address 3 */ + +/***************** Bit definition for USB_ADDR4_RX register *****************/ +#define USB_ADDR4_RX_ADDR4_RX_Pos (1U) +#define USB_ADDR4_RX_ADDR4_RX_Msk (0x7FFFUL << USB_ADDR4_RX_ADDR4_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR4_RX_ADDR4_RX USB_ADDR4_RX_ADDR4_RX_Msk /*!< Reception Buffer Address 4 */ + +/***************** Bit definition for USB_ADDR5_RX register *****************/ +#define USB_ADDR5_RX_ADDR5_RX_Pos (1U) +#define USB_ADDR5_RX_ADDR5_RX_Msk (0x7FFFUL << USB_ADDR5_RX_ADDR5_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR5_RX_ADDR5_RX USB_ADDR5_RX_ADDR5_RX_Msk /*!< Reception Buffer Address 5 */ + +/***************** Bit definition for USB_ADDR6_RX register *****************/ +#define USB_ADDR6_RX_ADDR6_RX_Pos (1U) +#define USB_ADDR6_RX_ADDR6_RX_Msk (0x7FFFUL << USB_ADDR6_RX_ADDR6_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR6_RX_ADDR6_RX USB_ADDR6_RX_ADDR6_RX_Msk /*!< Reception Buffer Address 6 */ + +/***************** Bit definition for USB_ADDR7_RX register *****************/ +#define USB_ADDR7_RX_ADDR7_RX_Pos (1U) +#define USB_ADDR7_RX_ADDR7_RX_Msk (0x7FFFUL << USB_ADDR7_RX_ADDR7_RX_Pos) /*!< 0x0000FFFE */ +#define USB_ADDR7_RX_ADDR7_RX USB_ADDR7_RX_ADDR7_RX_Msk /*!< Reception Buffer Address 7 */ + +/*----------------------------------------------------------------------------*/ + +/***************** Bit definition for USB_COUNT0_RX register ****************/ +#define USB_COUNT0_RX_COUNT0_RX_Pos (0U) +#define USB_COUNT0_RX_COUNT0_RX_Msk (0x3FFUL << USB_COUNT0_RX_COUNT0_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT0_RX_COUNT0_RX USB_COUNT0_RX_COUNT0_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT0_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT0_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT0_RX_NUM_BLOCK USB_COUNT0_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT0_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT0_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT0_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT0_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT0_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT0_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT0_RX_BLSIZE_Pos (15U) +#define USB_COUNT0_RX_BLSIZE_Msk (0x1UL << USB_COUNT0_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT0_RX_BLSIZE USB_COUNT0_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT1_RX register ****************/ +#define USB_COUNT1_RX_COUNT1_RX_Pos (0U) +#define USB_COUNT1_RX_COUNT1_RX_Msk (0x3FFUL << USB_COUNT1_RX_COUNT1_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT1_RX_COUNT1_RX USB_COUNT1_RX_COUNT1_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT1_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT1_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT1_RX_NUM_BLOCK USB_COUNT1_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT1_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT1_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT1_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT1_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT1_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT1_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT1_RX_BLSIZE_Pos (15U) +#define USB_COUNT1_RX_BLSIZE_Msk (0x1UL << USB_COUNT1_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT1_RX_BLSIZE USB_COUNT1_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT2_RX register ****************/ +#define USB_COUNT2_RX_COUNT2_RX_Pos (0U) +#define USB_COUNT2_RX_COUNT2_RX_Msk (0x3FFUL << USB_COUNT2_RX_COUNT2_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT2_RX_COUNT2_RX USB_COUNT2_RX_COUNT2_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT2_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT2_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT2_RX_NUM_BLOCK USB_COUNT2_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT2_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT2_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT2_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT2_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT2_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT2_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT2_RX_BLSIZE_Pos (15U) +#define USB_COUNT2_RX_BLSIZE_Msk (0x1UL << USB_COUNT2_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT2_RX_BLSIZE USB_COUNT2_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT3_RX register ****************/ +#define USB_COUNT3_RX_COUNT3_RX_Pos (0U) +#define USB_COUNT3_RX_COUNT3_RX_Msk (0x3FFUL << USB_COUNT3_RX_COUNT3_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT3_RX_COUNT3_RX USB_COUNT3_RX_COUNT3_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT3_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT3_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT3_RX_NUM_BLOCK USB_COUNT3_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT3_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT3_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT3_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT3_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT3_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT3_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT3_RX_BLSIZE_Pos (15U) +#define USB_COUNT3_RX_BLSIZE_Msk (0x1UL << USB_COUNT3_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT3_RX_BLSIZE USB_COUNT3_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT4_RX register ****************/ +#define USB_COUNT4_RX_COUNT4_RX_Pos (0U) +#define USB_COUNT4_RX_COUNT4_RX_Msk (0x3FFUL << USB_COUNT4_RX_COUNT4_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT4_RX_COUNT4_RX USB_COUNT4_RX_COUNT4_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT4_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT4_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT4_RX_NUM_BLOCK USB_COUNT4_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT4_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT4_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT4_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT4_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT4_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT4_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT4_RX_BLSIZE_Pos (15U) +#define USB_COUNT4_RX_BLSIZE_Msk (0x1UL << USB_COUNT4_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT4_RX_BLSIZE USB_COUNT4_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT5_RX register ****************/ +#define USB_COUNT5_RX_COUNT5_RX_Pos (0U) +#define USB_COUNT5_RX_COUNT5_RX_Msk (0x3FFUL << USB_COUNT5_RX_COUNT5_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT5_RX_COUNT5_RX USB_COUNT5_RX_COUNT5_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT5_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT5_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT5_RX_NUM_BLOCK USB_COUNT5_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT5_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT5_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT5_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT5_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT5_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT5_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT5_RX_BLSIZE_Pos (15U) +#define USB_COUNT5_RX_BLSIZE_Msk (0x1UL << USB_COUNT5_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT5_RX_BLSIZE USB_COUNT5_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT6_RX register ****************/ +#define USB_COUNT6_RX_COUNT6_RX_Pos (0U) +#define USB_COUNT6_RX_COUNT6_RX_Msk (0x3FFUL << USB_COUNT6_RX_COUNT6_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT6_RX_COUNT6_RX USB_COUNT6_RX_COUNT6_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT6_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT6_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT6_RX_NUM_BLOCK USB_COUNT6_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT6_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT6_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT6_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT6_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT6_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT6_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT6_RX_BLSIZE_Pos (15U) +#define USB_COUNT6_RX_BLSIZE_Msk (0x1UL << USB_COUNT6_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT6_RX_BLSIZE USB_COUNT6_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/***************** Bit definition for USB_COUNT7_RX register ****************/ +#define USB_COUNT7_RX_COUNT7_RX_Pos (0U) +#define USB_COUNT7_RX_COUNT7_RX_Msk (0x3FFUL << USB_COUNT7_RX_COUNT7_RX_Pos) /*!< 0x000003FF */ +#define USB_COUNT7_RX_COUNT7_RX USB_COUNT7_RX_COUNT7_RX_Msk /*!< Reception Byte Count */ + +#define USB_COUNT7_RX_NUM_BLOCK_Pos (10U) +#define USB_COUNT7_RX_NUM_BLOCK_Msk (0x1FUL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00007C00 */ +#define USB_COUNT7_RX_NUM_BLOCK USB_COUNT7_RX_NUM_BLOCK_Msk /*!< NUM_BLOCK[4:0] bits (Number of blocks) */ +#define USB_COUNT7_RX_NUM_BLOCK_0 (0x01UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000400 */ +#define USB_COUNT7_RX_NUM_BLOCK_1 (0x02UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00000800 */ +#define USB_COUNT7_RX_NUM_BLOCK_2 (0x04UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00001000 */ +#define USB_COUNT7_RX_NUM_BLOCK_3 (0x08UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00002000 */ +#define USB_COUNT7_RX_NUM_BLOCK_4 (0x10UL << USB_COUNT7_RX_NUM_BLOCK_Pos) /*!< 0x00004000 */ + +#define USB_COUNT7_RX_BLSIZE_Pos (15U) +#define USB_COUNT7_RX_BLSIZE_Msk (0x1UL << USB_COUNT7_RX_BLSIZE_Pos) /*!< 0x00008000 */ +#define USB_COUNT7_RX_BLSIZE USB_COUNT7_RX_BLSIZE_Msk /*!< BLock SIZE */ + +/*----------------------------------------------------------------------------*/ + +/**************** Bit definition for USB_COUNT0_RX_0 register ***************/ +#define USB_COUNT0_RX_0_COUNT0_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT0_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT0_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT0_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT0_RX_1 register ***************/ +#define USB_COUNT0_RX_1_COUNT0_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT0_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT0_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT0_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT1_RX_0 register ***************/ +#define USB_COUNT1_RX_0_COUNT1_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT1_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT1_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT1_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT1_RX_1 register ***************/ +#define USB_COUNT1_RX_1_COUNT1_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT1_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT1_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT1_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT2_RX_0 register ***************/ +#define USB_COUNT2_RX_0_COUNT2_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT2_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT2_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT2_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT2_RX_1 register ***************/ +#define USB_COUNT2_RX_1_COUNT2_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT2_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT2_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT2_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT3_RX_0 register ***************/ +#define USB_COUNT3_RX_0_COUNT3_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT3_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT3_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT3_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT3_RX_1 register ***************/ +#define USB_COUNT3_RX_1_COUNT3_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT3_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT3_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT3_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT4_RX_0 register ***************/ +#define USB_COUNT4_RX_0_COUNT4_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT4_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT4_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT4_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT4_RX_1 register ***************/ +#define USB_COUNT4_RX_1_COUNT4_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT4_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT4_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT4_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/**************** Bit definition for USB_COUNT5_RX_0 register ***************/ +#define USB_COUNT5_RX_0_COUNT5_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT5_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT5_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT5_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT5_RX_1 register ***************/ +#define USB_COUNT5_RX_1_COUNT5_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT5_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT5_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT5_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT6_RX_0 register ***************/ +#define USB_COUNT6_RX_0_COUNT6_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT6_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT6_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT6_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/**************** Bit definition for USB_COUNT6_RX_1 register ***************/ +#define USB_COUNT6_RX_1_COUNT6_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT6_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT6_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT6_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/*************** Bit definition for USB_COUNT7_RX_0 register ****************/ +#define USB_COUNT7_RX_0_COUNT7_RX_0 0x000003FFU /*!< Reception Byte Count (low) */ + +#define USB_COUNT7_RX_0_NUM_BLOCK_0 0x00007C00U /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_0 0x00000400U /*!< Bit 0 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_1 0x00000800U /*!< Bit 1 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_2 0x00001000U /*!< Bit 2 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_3 0x00002000U /*!< Bit 3 */ +#define USB_COUNT7_RX_0_NUM_BLOCK_0_4 0x00004000U /*!< Bit 4 */ + +#define USB_COUNT7_RX_0_BLSIZE_0 0x00008000U /*!< BLock SIZE (low) */ + +/*************** Bit definition for USB_COUNT7_RX_1 register ****************/ +#define USB_COUNT7_RX_1_COUNT7_RX_1 0x03FF0000U /*!< Reception Byte Count (high) */ + +#define USB_COUNT7_RX_1_NUM_BLOCK_1 0x7C000000U /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_0 0x04000000U /*!< Bit 0 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_1 0x08000000U /*!< Bit 1 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_2 0x10000000U /*!< Bit 2 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_3 0x20000000U /*!< Bit 3 */ +#define USB_COUNT7_RX_1_NUM_BLOCK_1_4 0x40000000U /*!< Bit 4 */ + +#define USB_COUNT7_RX_1_BLSIZE_1 0x80000000U /*!< BLock SIZE (high) */ + +/** + * @} + */ + +#define BTABLE_ADDRESS 0x000U + +#ifndef PMA_ACCESS +#define PMA_ACCESS 2U +#endif +/******************** Bit definition for USB_COUNTn_RX register *************/ +#define USB_CNTRX_NBLK_MSK (0x1FU << 10) +#define USB_CNTRX_BLSIZE (0x1U << 15) + +/* SetENDPOINT */ +#define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U)) = (uint16_t)(wRegValue)) + +/* GetENDPOINT */ +#define PCD_GET_ENDPOINT(USBx, bEpNum) (*(__IO uint16_t *)(&(USBx)->EP0R + ((bEpNum) * 2U))) + +/** + * @brief sets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wType Endpoint Type. + * @retval None + */ +#define PCD_SET_EPTYPE(USBx, bEpNum, wType) (PCD_SET_ENDPOINT((USBx), (bEpNum), ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) | USB_EP_CTR_TX | USB_EP_CTR_RX))) + +/** + * @brief gets the type in the endpoint register(bits EP_TYPE[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Endpoint Type + */ +#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD) + +/** + * @brief free buffer used from the application realizing it to the line + * toggles bit SW_BUF in the double buffered endpoint register + * @param USBx USB device. + * @param bEpNum, bDir + * @retval None + */ +#define PCD_FreeUserBuffer(USBx, bEpNum, bDir) \ + do { \ + if ((bDir) == 0U) \ + { \ + /* OUT double buffered endpoint */ \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + else if ((bDir) == 1U) \ + { \ + /* IN double buffered endpoint */ \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) + +/** + * @brief sets the status for tx transfer (bits STAT_TX[1:0]). + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TX_STATUS */ + +/** + * @brief sets the status for rx transfer (bits STAT_TX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wState new state + * @retval None + */ +#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK; \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wState))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_RX_STATUS */ + +/** + * @brief sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wStaterx new state. + * @param wStatetx new state. + * @retval None + */ +#define PCD_SET_EP_TXRX_STATUS(USBx, bEpNum, wStaterx, wStatetx) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK | USB_EPTX_STAT); \ + /* toggle first bit ? */ \ + if ((USB_EPRX_DTOG1 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPRX_DTOG2 & (wStaterx))!= 0U) \ + { \ + _wRegVal ^= USB_EPRX_DTOG2; \ + } \ + /* toggle first bit ? */ \ + if ((USB_EPTX_DTOG1 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG1; \ + } \ + /* toggle second bit ? */ \ + if ((USB_EPTX_DTOG2 & (wStatetx))!= 0U) \ + { \ + _wRegVal ^= USB_EPTX_DTOG2; \ + } \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_TXRX_STATUS */ + +/** + * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] + * /STAT_RX[1:0]) + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval status + */ +#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT) +#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT) + +/** + * @brief sets directly the VALID tx/rx-status into the endpoint register + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_TX_VALID(USBx, bEpNum) (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID)) +#define PCD_SET_EP_RX_VALID(USBx, bEpNum) (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID)) + +/** + * @brief checks stall condition in an endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval TRUE = endpoint in stall condition. + */ +#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) == USB_EP_TX_STALL) +#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) == USB_EP_RX_STALL) + +/** + * @brief set & clear EP_KIND bit. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_KIND(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_KIND)); \ + } while(0) /* PCD_SET_EP_KIND */ + +#define PCD_CLEAR_EP_KIND(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_EP_KIND */ + +/** + * @brief Sets/clears directly STATUS_OUT bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_OUT_STATUS(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Sets/clears directly EP_KIND bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_SET_EP_DBUF(USBx, bEpNum) PCD_SET_EP_KIND((USBx), (bEpNum)) +#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum)) + +/** + * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0x7FFFU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_TX)); \ + } while(0) /* PCD_CLEAR_RX_EP_CTR */ + +#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (0xFF7FU & USB_EPREG_MASK); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX)); \ + } while(0) /* PCD_CLEAR_TX_EP_CTR */ + +/** + * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_RX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_RX)); \ + } while(0) /* PCD_RX_DTOG */ + +#define PCD_TX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wEPVal; \ + \ + _wEPVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK; \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wEPVal | USB_EP_CTR_RX | USB_EP_CTR_TX | USB_EP_DTOG_TX)); \ + } while(0) /* PCD_TX_DTOG */ +/** + * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_CLEAR_RX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_RX) != 0U)\ + { \ + PCD_RX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_RX_DTOG */ + +#define PCD_CLEAR_TX_DTOG(USBx, bEpNum) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)); \ + \ + if ((_wRegVal & USB_EP_DTOG_TX) != 0U)\ + { \ + PCD_TX_DTOG((USBx), (bEpNum)); \ + } \ + } while(0) /* PCD_CLEAR_TX_DTOG */ + +/** + * @brief Sets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bAddr Address. + * @retval None + */ +#define PCD_SET_EP_ADDRESS(USBx, bEpNum, bAddr) \ + do { \ + uint16_t _wRegVal; \ + \ + _wRegVal = (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr); \ + \ + PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX | USB_EP_CTR_TX)); \ + } while(0) /* PCD_SET_EP_ADDRESS */ + +/** + * @brief Gets address in an endpoint register. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD)) + +#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) +#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint16_t *)((((uint32_t)(USBx)->BTABLE + ((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS) + ((uint32_t)(USBx) + 0x400U))) + +/** + * @brief sets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wAddr address to be set (must be word aligned). + * @retval None + */ +#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + (((uint32_t)(bEpNum) * 8U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_TX_ADDRESS */ + +#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum, wAddr) \ + do { \ + __IO uint16_t *_wRegVal; \ + uint32_t _wRegBase = (uint32_t)USBx; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 4U) * PMA_ACCESS)); \ + *_wRegVal = ((wAddr) >> 1) << 1; \ + } while(0) /* PCD_SET_EP_RX_ADDRESS */ + +/** + * @brief Gets address of the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval address of the buffer. + */ +#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Sets counter of rx buffer with no. of blocks. + * @param pdwReg Register pointer + * @param wCount Counter. + * @param wNBlocks no. of Blocks. + * @retval None + */ +#define PCD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ + do { \ + (wNBlocks) = (wCount) >> 5; \ + if (((wCount) & 0x1fU) == 0U) \ + { \ + (wNBlocks)--; \ + } \ + *(pdwReg) = (uint16_t)(((wNBlocks) << 10) | USB_CNTRX_BLSIZE); \ + } while(0) /* PCD_CALC_BLK32 */ + +#define PCD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ + do { \ + (wNBlocks) = (wCount) >> 1; \ + if (((wCount) & 0x1U) != 0U) \ + { \ + (wNBlocks)++; \ + } \ + *(pdwReg) = (uint16_t)((wNBlocks) << 10); \ + } while(0) /* PCD_CALC_BLK2 */ + +#define PCD_SET_EP_CNT_RX_REG(pdwReg, wCount) \ + do { \ + uint32_t wNBlocks; \ + if ((wCount) == 0U) \ + { \ + *(pdwReg) &= (uint16_t)~USB_CNTRX_NBLK_MSK; \ + *(pdwReg) |= USB_CNTRX_BLSIZE; \ + } \ + else if((wCount) <= 62U) \ + { \ + PCD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ + } \ + else \ + { \ + PCD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ + } \ + } while(0) /* PCD_SET_EP_CNT_RX_REG */ + +#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *pdwReg; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + pdwReg = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount)); \ + } while(0) + +/** + * @brief sets counter for the tx/rx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wCount Counter value. + * @retval None + */ +#define PCD_SET_EP_TX_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 2U) * PMA_ACCESS)); \ + *_wRegVal = (uint16_t)(wCount); \ + } while(0) + +#define PCD_SET_EP_RX_CNT(USBx, bEpNum, wCount) \ + do { \ + uint32_t _wRegBase = (uint32_t)(USBx); \ + __IO uint16_t *_wRegVal; \ + \ + _wRegBase += (uint32_t)(USBx)->BTABLE; \ + _wRegVal = (__IO uint16_t *)(_wRegBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + PCD_SET_EP_CNT_RX_REG(_wRegVal, (wCount)); \ + } while(0) + +/** + * @brief gets counter of the tx buffer. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval Counter value + */ +#define PCD_GET_EP_TX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ffU) +#define PCD_GET_EP_RX_CNT(USBx, bEpNum) ((uint32_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ffU) + +/** + * @brief Sets buffer 0/1 address in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr buffer 0 address. + * @retval Counter value + */ +#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum, wBuf0Addr) \ + do { \ + PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr)); \ + } while(0) /* PCD_SET_EP_DBUF0_ADDR */ + +#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum, wBuf1Addr) \ + do { \ + PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF1_ADDR */ + +/** + * @brief Sets addresses in a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param wBuf0Addr: buffer 0 address. + * @param wBuf1Addr = buffer 1 address. + * @retval None + */ +#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum, wBuf0Addr, wBuf1Addr) \ + do { \ + PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr)); \ + PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr)); \ + } while(0) /* PCD_SET_EP_DBUF_ADDR */ + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum))) + +/** + * @brief Gets buffer 0/1 address of a double buffer endpoint. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @param bDir endpoint dir EP_DBUF_OUT = OUT + * EP_DBUF_IN = IN + * @param wCount: Counter value + * @retval None + */ +#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ + if ((bDir) == 0U) \ + /* OUT endpoint */ \ + { \ + PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + PCD_SET_EP_TX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + } \ + } while(0) /* SetEPDblBuf0Count*/ + +#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ + uint32_t _wBase = (uint32_t)(USBx); \ + __IO uint16_t *_wEPRegVal; \ + \ + if ((bDir) == 0U) \ + { \ + /* OUT endpoint */ \ + PCD_SET_EP_RX_CNT((USBx), (bEpNum), (wCount)); \ + } \ + else \ + { \ + if ((bDir) == 1U) \ + { \ + /* IN endpoint */ \ + _wBase += (uint32_t)(USBx)->BTABLE; \ + _wEPRegVal = (__IO uint16_t *)(_wBase + 0x400U + ((((uint32_t)(bEpNum) * 8U) + 6U) * PMA_ACCESS)); \ + *_wEPRegVal = (uint16_t)(wCount); \ + } \ + } \ + } while(0) /* SetEPDblBuf1Count */ + +#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) \ + do { \ + PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \ + } while(0) /* PCD_SET_EP_DBUF_CNT */ + +/** + * @brief Gets buffer 0/1 rx/tx counter for double buffering. + * @param USBx USB peripheral instance register address. + * @param bEpNum Endpoint Number. + * @retval None + */ +#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum))) +#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum))) + +#endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/hpm/usb_dc_hpm.c b/components/drivers/usb/cherryusb/port/hpm/usb_dc_hpm.c new file mode 100644 index 00000000000..31ad5b72ac6 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/hpm/usb_dc_hpm.c @@ -0,0 +1,350 @@ +/* + * Copyright (c) 2022-2024 HPMicro + * + * SPDX-License-Identifier: BSD-3-Clause + * + */ +#include "usbd_core.h" +#include "hpm_usb_device.h" + +#ifndef USB_NUM_BIDIR_ENDPOINTS +#define USB_NUM_BIDIR_ENDPOINTS CONFIG_USBDEV_EP_NUM +#endif + +/* USBSTS, USBINTR */ +enum { + intr_usb = HPM_BITSMASK(1, 0), + intr_error = HPM_BITSMASK(1, 1), + intr_port_change = HPM_BITSMASK(1, 2), + intr_reset = HPM_BITSMASK(1, 6), + intr_sof = HPM_BITSMASK(1, 7), + intr_suspend = HPM_BITSMASK(1, 8), + intr_nak = HPM_BITSMASK(1, 16) +}; + +/* Endpoint state */ +struct hpm_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/*---------------------------------------------------------------------* + * Variable Definitions + *---------------------------------------------------------------------*/ +/* Driver state */ +struct hpm_udc { + usb_device_handle_t *handle; + struct hpm_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct hpm_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ +} g_hpm_udc[CONFIG_USBDEV_MAX_BUS]; + +static ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT) dcd_data_t _dcd_data0; +#ifdef HPM_USB1_BASE +static ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(USB_SOC_DCD_DATA_RAM_ADDRESS_ALIGNMENT) dcd_data_t _dcd_data1; +#endif +static ATTR_PLACE_AT_NONCACHEABLE usb_device_handle_t usb_device_handle[CONFIG_USBDEV_MAX_BUS]; +static uint32_t _dcd_irqnum[CONFIG_USBDEV_MAX_BUS]; +static uint8_t _dcd_busid[CONFIG_USBDEV_MAX_BUS]; + +/* Index to bit position in register */ +static inline uint8_t ep_idx2bit(uint8_t ep_idx) +{ + return ep_idx / 2 + ((ep_idx % 2) ? 16 : 0); +} + +void usbd_execute_test_mode(uint8_t busid, uint8_t test_mode) +{ + usb_set_port_test_mode(g_hpm_udc[busid].handle->regs, test_mode); +} + +int usb_dc_init(uint8_t busid) +{ + memset(&g_hpm_udc[busid], 0, sizeof(struct hpm_udc)); + g_hpm_udc[busid].handle = &usb_device_handle[busid]; + g_hpm_udc[busid].handle->regs = (USB_Type *)g_usbdev_bus[busid].reg_base; + + if (g_usbdev_bus[busid].reg_base == HPM_USB0_BASE) { + _dcd_irqnum[busid] = IRQn_USB0; + _dcd_busid[0] = busid; + } else { +#ifdef HPM_USB1_BASE + if (g_usbdev_bus[busid].reg_base == HPM_USB1_BASE) { + _dcd_irqnum[busid] = IRQn_USB1; + _dcd_busid[1] = busid; + } +#endif + } + + if (busid == 0) { + g_hpm_udc[busid].handle->dcd_data = &_dcd_data0; + } else if (busid == 1) { +#ifdef HPM_USB1_BASE + g_hpm_udc[busid].handle->dcd_data = &_dcd_data1; +#endif + } else { + ; + } + + uint32_t int_mask; + int_mask = (USB_USBINTR_UE_MASK | USB_USBINTR_UEE_MASK | + USB_USBINTR_PCE_MASK | USB_USBINTR_URE_MASK); + + usb_device_init(g_hpm_udc[busid].handle, int_mask); + + intc_m_enable_irq(_dcd_irqnum[busid]); + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + intc_m_disable_irq(_dcd_irqnum[busid]); + + usb_device_deinit(g_hpm_udc[busid].handle); + + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + usb_dcd_set_address(handle->regs, addr); + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + uint8_t speed; + + speed = usb_get_port_speed(g_hpm_udc[busid].handle->regs); + + if (speed == 0x00) { + return USB_SPEED_FULL; + } + if (speed == 0x01) { + return USB_SPEED_LOW; + } + if (speed == 0x02) { + return USB_SPEED_HIGH; + } + + return 0; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + usb_endpoint_config_t tmp_ep_cfg; + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + tmp_ep_cfg.xfer = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + tmp_ep_cfg.ep_addr = ep->bEndpointAddress; + tmp_ep_cfg.max_packet_size = ep->wMaxPacketSize; + + usb_device_edpt_open(handle, &tmp_ep_cfg); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_hpm_udc[busid].out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_hpm_udc[busid].out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_hpm_udc[busid].out_ep[ep_idx].ep_enable = true; + } else { + g_hpm_udc[busid].in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_hpm_udc[busid].in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_hpm_udc[busid].in_ep[ep_idx].ep_enable = true; + } + + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + g_hpm_udc[busid].out_ep[ep_idx].ep_enable = false; + } else { + g_hpm_udc[busid].in_ep[ep_idx].ep_enable = false; + } + + usb_device_edpt_close(handle, ep); + + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + + usb_device_edpt_stall(handle, ep); + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + + usb_device_edpt_clear_stall(handle, ep); + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + + *stalled = usb_device_edpt_check_stall(handle, ep); + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + + if (!data && data_len) { + return -1; + } + if (!g_hpm_udc[busid].in_ep[ep_idx].ep_enable) { + return -2; + } + + g_hpm_udc[busid].in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_hpm_udc[busid].in_ep[ep_idx].xfer_len = data_len; + g_hpm_udc[busid].in_ep[ep_idx].actual_xfer_len = 0; + + usb_device_edpt_xfer(handle, ep, (uint8_t *)data, data_len); + + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + + if (!data && data_len) { + return -1; + } + if (!g_hpm_udc[busid].out_ep[ep_idx].ep_enable) { + return -2; + } + + g_hpm_udc[busid].out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_hpm_udc[busid].out_ep[ep_idx].xfer_len = data_len; + g_hpm_udc[busid].out_ep[ep_idx].actual_xfer_len = 0; + + usb_device_edpt_xfer(handle, ep, data, data_len); + + return 0; +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t int_status; + usb_device_handle_t *handle = g_hpm_udc[busid].handle; + uint32_t transfer_len; + bool ep_cb_req; + + /* Acknowledge handled interrupt */ + int_status = usb_device_status_flags(handle); + int_status &= usb_device_interrupts(handle); + usb_device_clear_status_flags(handle, int_status); + + if (int_status & intr_error) { + USB_LOG_ERR("usbd intr error!\r\n"); + } + + if (int_status & intr_reset) { + memset(g_hpm_udc[busid].in_ep, 0, sizeof(struct hpm_ep_state) * USB_NUM_BIDIR_ENDPOINTS); + memset(g_hpm_udc[busid].out_ep, 0, sizeof(struct hpm_ep_state) * USB_NUM_BIDIR_ENDPOINTS); + usbd_event_reset_handler(busid); + usb_device_bus_reset(handle, 64); + } + + if (int_status & intr_suspend) { + if (usb_device_get_suspend_status(handle)) { + usbd_event_suspend_handler(busid); + /* Note: Host may delay more than 3 ms before and/or after bus reset before doing enumeration. */ + if (usb_device_get_address(handle)) { + } + } + } + + if (int_status & intr_port_change) { + if (!usb_device_get_port_ccs(handle)) { + usbd_event_disconnect_handler(busid); + } else { + usbd_event_connect_handler(busid); + } + } + + if (int_status & intr_usb) { + uint32_t const edpt_complete = usb_device_get_edpt_complete_status(handle); + usb_device_clear_edpt_complete_status(handle, edpt_complete); + uint32_t edpt_setup_status = usb_device_get_setup_status(handle); + + if (edpt_setup_status) { + /*------------- Set up Received -------------*/ + usb_device_clear_setup_status(handle, edpt_setup_status); + dcd_qhd_t *qhd0 = usb_device_qhd_get(handle, 0); + usbd_event_ep0_setup_complete_handler(busid, (uint8_t *)&qhd0->setup_request); + } + + if (edpt_complete) { + for (uint8_t ep_idx = 0; ep_idx < USB_SOS_DCD_MAX_QHD_COUNT; ep_idx++) { + if (edpt_complete & (1 << ep_idx2bit(ep_idx))) { + transfer_len = 0; + ep_cb_req = true; + + /* Failed QTD also get ENDPTCOMPLETE set */ + dcd_qtd_t *p_qtd = usb_device_qtd_get(handle, ep_idx); + while (1) { + if (p_qtd->halted || p_qtd->xact_err || p_qtd->buffer_err) { + USB_LOG_ERR("usbd transfer error!\r\n"); + ep_cb_req = false; + break; + } else if (p_qtd->active) { + ep_cb_req = false; + break; + } else { + transfer_len += p_qtd->expected_bytes - p_qtd->total_bytes; + } + + if (p_qtd->next == USB_SOC_DCD_QTD_NEXT_INVALID){ + break; + } else { + p_qtd = (dcd_qtd_t *)p_qtd->next; + } + } + + if (ep_cb_req) { + uint8_t const ep_addr = (ep_idx / 2) | ((ep_idx & 0x01) ? 0x80 : 0); + if (ep_addr & 0x80) { + usbd_event_ep_in_complete_handler(busid, ep_addr, transfer_len); + } else { + usbd_event_ep_out_complete_handler(busid, ep_addr, transfer_len); + } + } + } + } + } + } +} + +void isr_usbd0(void) +{ + USBD_IRQHandler(_dcd_busid[0]); +} +SDK_DECLARE_EXT_ISR_M(IRQn_USB0, isr_usbd0) + +#ifdef HPM_USB1_BASE +void isr_usbd1(void) +{ + USBD_IRQHandler(_dcd_busid[1]); +} +SDK_DECLARE_EXT_ISR_M(IRQn_USB1, isr_usbd1) +#endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/musb/README.md b/components/drivers/usb/cherryusb/port/musb/README.md new file mode 100644 index 00000000000..d65b70a176a --- /dev/null +++ b/components/drivers/usb/cherryusb/port/musb/README.md @@ -0,0 +1,19 @@ +# Note + +## Support Chip List + +### HEZHOU + +- AIR105 + +### ES32 + +- ES32F3xx + +### TI + +- MSP432E4x + +### AllwinnerTech + +- F1Cxxx, F2Cxxx diff --git a/components/drivers/usb/cherryusb/port/musb/usb_dc_musb.c b/components/drivers/usb/cherryusb/port/musb/usb_dc_musb.c new file mode 100644 index 00000000000..4bcc7eeee52 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/musb/usb_dc_musb.c @@ -0,0 +1,886 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_musb_reg.h" + +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) + +#define USB_BASE (g_usbdev_bus[0].reg_base) + +#if defined(CONFIG_USB_MUSB_SUNXI) +#define MUSB_FADDR_OFFSET 0x98 +#define MUSB_POWER_OFFSET 0x40 +#define MUSB_TXIS_OFFSET 0x44 +#define MUSB_RXIS_OFFSET 0x46 +#define MUSB_TXIE_OFFSET 0x48 +#define MUSB_RXIE_OFFSET 0x4A +#define MUSB_IS_OFFSET 0x4C +#define MUSB_IE_OFFSET 0x50 +#define MUSB_EPIDX_OFFSET 0x42 + +#define MUSB_IND_TXMAP_OFFSET 0x80 +#define MUSB_IND_TXCSRL_OFFSET 0x82 +#define MUSB_IND_TXCSRH_OFFSET 0x83 +#define MUSB_IND_RXMAP_OFFSET 0x84 +#define MUSB_IND_RXCSRL_OFFSET 0x86 +#define MUSB_IND_RXCSRH_OFFSET 0x87 +#define MUSB_IND_RXCOUNT_OFFSET 0x88 + +#define MUSB_FIFO_OFFSET 0x00 + +#define MUSB_DEVCTL_OFFSET 0x41 + +#define MUSB_TXFIFOSZ_OFFSET 0x90 +#define MUSB_RXFIFOSZ_OFFSET 0x94 +#define MUSB_TXFIFOADD_OFFSET 0x92 +#define MUSB_RXFIFOADD_OFFSET 0x96 + +#elif defined(CONFIG_USB_MUSB_CUSTOM) +#include "musb_custom.h" +#else +#define MUSB_FADDR_OFFSET 0x00 +#define MUSB_POWER_OFFSET 0x01 +#define MUSB_TXIS_OFFSET 0x02 +#define MUSB_RXIS_OFFSET 0x04 +#define MUSB_TXIE_OFFSET 0x06 +#define MUSB_RXIE_OFFSET 0x08 +#define MUSB_IS_OFFSET 0x0A +#define MUSB_IE_OFFSET 0x0B + +#define MUSB_EPIDX_OFFSET 0x0E + +#define MUSB_IND_TXMAP_OFFSET 0x10 +#define MUSB_IND_TXCSRL_OFFSET 0x12 +#define MUSB_IND_TXCSRH_OFFSET 0x13 +#define MUSB_IND_RXMAP_OFFSET 0x14 +#define MUSB_IND_RXCSRL_OFFSET 0x16 +#define MUSB_IND_RXCSRH_OFFSET 0x17 +#define MUSB_IND_RXCOUNT_OFFSET 0x18 + +#define MUSB_FIFO_OFFSET 0x20 + +#define MUSB_DEVCTL_OFFSET 0x60 + +#define MUSB_TXFIFOSZ_OFFSET 0x62 +#define MUSB_RXFIFOSZ_OFFSET 0x63 +#define MUSB_TXFIFOADD_OFFSET 0x64 +#define MUSB_RXFIFOADD_OFFSET 0x66 + +#endif // CONFIG_USB_MUSB_SUNXI + +#define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx) + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +typedef enum { + USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */ + USB_EP0_STATE_IN_DATA = 0x1, /**< IN DATA */ + USB_EP0_STATE_OUT_DATA = 0x3, /**< OUT DATA */ + USB_EP0_STATE_IN_STATUS = 0x4, /**< IN status */ + USB_EP0_STATE_OUT_STATUS = 0x5, /**< OUT status */ + USB_EP0_STATE_IN_ZLP = 0x6, /**< OUT status */ + USB_EP0_STATE_STALL = 0x7, /**< STALL status */ +} ep0_state_t; + +/* Endpoint state */ +struct musb_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct musb_udc { + volatile uint8_t dev_addr; + volatile uint32_t fifo_size_offset; + __attribute__((aligned(32))) struct usb_setup_packet setup; + struct musb_ep_state in_ep[CONFIG_USBDEV_EP_NUM]; /*!< IN endpoint parameters*/ + struct musb_ep_state out_ep[CONFIG_USBDEV_EP_NUM]; /*!< OUT endpoint parameters */ +} g_musb_udc; + +static volatile uint8_t usb_ep0_state = USB_EP0_STATE_SETUP; +volatile bool zlp_flag = 0; + +/* get current active ep */ +static uint8_t musb_get_active_ep(void) +{ + return HWREGB(USB_BASE + MUSB_EPIDX_OFFSET); +} + +/* set the active ep */ +static void musb_set_active_ep(uint8_t ep_index) +{ + HWREGB(USB_BASE + MUSB_EPIDX_OFFSET) = ep_index; +} + +static void musb_write_packet(uint8_t ep_idx, uint8_t *buffer, uint16_t len) +{ + uint32_t *buf32; + uint8_t *buf8; + uint32_t count32; + uint32_t count8; + int i; + + if ((uint32_t)buffer & 0x03) { + buf8 = buffer; + for (i = 0; i < len; i++) { + HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++; + } + } else { + count32 = len >> 2; + count8 = len & 0x03; + + buf32 = (uint32_t *)buffer; + + while (count32--) { + HWREG(USB_FIFO_BASE(ep_idx)) = *buf32++; + } + + buf8 = (uint8_t *)buf32; + + while (count8--) { + HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++; + } + } +} + +static void musb_read_packet(uint8_t ep_idx, uint8_t *buffer, uint16_t len) +{ + uint32_t *buf32; + uint8_t *buf8; + uint32_t count32; + uint32_t count8; + int i; + + if ((uint32_t)buffer & 0x03) { + buf8 = buffer; + for (i = 0; i < len; i++) { + *buf8++ = HWREGB(USB_FIFO_BASE(ep_idx)); + } + } else { + count32 = len >> 2; + count8 = len & 0x03; + + buf32 = (uint32_t *)buffer; + + while (count32--) { + *buf32++ = HWREG(USB_FIFO_BASE(ep_idx)); + } + + buf8 = (uint8_t *)buf32; + + while (count8--) { + *buf8++ = HWREGB(USB_FIFO_BASE(ep_idx)); + } + } +} + +static uint32_t musb_get_fifo_size(uint16_t mps, uint16_t *used) +{ + uint32_t size; + + for (uint8_t i = USB_TXFIFOSZ_SIZE_8; i <= USB_TXFIFOSZ_SIZE_2048; i++) { + size = (8 << i); + if (mps <= size) { + *used = size; + return i; + } + } + + *used = 0; + return USB_TXFIFOSZ_SIZE_8; +} + +__WEAK void usb_dc_low_level_init(void) +{ +} + +__WEAK void usb_dc_low_level_deinit(void) +{ +} + +int usb_dc_init(uint8_t busid) +{ + usb_dc_low_level_init(); + +#ifdef CONFIG_USB_HS + HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_HSENAB; +#else + HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_HSENAB; +#endif + + musb_set_active_ep(0); + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = 0; + + HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) |= USB_DEVCTL_SESSION; + + /* Enable USB interrupts */ + HWREGB(USB_BASE + MUSB_IE_OFFSET) = USB_IE_RESET; + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0; + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; + + HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_SOFTCONN; + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + if (addr == 0) { + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = 0; + } + + g_musb_udc.dev_addr = addr; + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + uint8_t speed = USB_SPEED_UNKNOWN; + + if (HWREGB(USB_BASE + MUSB_POWER_OFFSET) & USB_POWER_HSMODE) + speed = USB_SPEED_HIGH; + else if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_FSDEV) + speed = USB_SPEED_FULL; + else if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_LSDEV) + speed = USB_SPEED_LOW; + + return speed; +} + +uint8_t usbd_force_full_speed(const uint8_t port) +{ + HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_HSENAB; + return (HWREGB(USB_BASE + MUSB_POWER_OFFSET) & USB_POWER_HSENAB); +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint16_t used = 0; + uint16_t fifo_size = 0; + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + uint8_t old_ep_idx; + uint32_t ui32Flags = 0; + uint16_t ui32Register = 0; + + if (ep_idx == 0) { + g_musb_udc.out_ep[0].ep_mps = USB_CTRL_EP_MPS; + g_musb_udc.out_ep[0].ep_type = 0x00; + g_musb_udc.out_ep[0].ep_enable = true; + g_musb_udc.in_ep[0].ep_mps = USB_CTRL_EP_MPS; + g_musb_udc.in_ep[0].ep_type = 0x00; + g_musb_udc.in_ep[0].ep_enable = true; + return 0; + } + + if (ep_idx > (CONFIG_USBDEV_EP_NUM - 1)) { + USB_LOG_ERR("Ep addr %02x overflow\r\n", ep->bEndpointAddress); + return -1; + } + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_musb_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_musb_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_musb_udc.out_ep[ep_idx].ep_enable = true; + + HWREGH(USB_BASE + MUSB_IND_RXMAP_OFFSET) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + + // + // Allow auto clearing of RxPktRdy when packet of size max packet + // has been unloaded from the FIFO. + // + if (ui32Flags & USB_EP_AUTO_CLEAR) { + ui32Register = USB_RXCSRH1_AUTOCL; + } + // + // Configure the DMA mode. + // + if (ui32Flags & USB_EP_DMA_MODE_1) { + ui32Register |= USB_RXCSRH1_DMAEN | USB_RXCSRH1_DMAMOD; + } else if (ui32Flags & USB_EP_DMA_MODE_0) { + ui32Register |= USB_RXCSRH1_DMAEN; + } + // + // If requested, disable NYET responses for high-speed bulk and + // interrupt endpoints. + // + if (ui32Flags & USB_EP_DIS_NYET) { + ui32Register |= USB_RXCSRH1_DISNYET; + } + + // + // Enable isochronous mode if requested. + // + if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) == 0x01) { + ui32Register |= USB_RXCSRH1_ISO; + } + + HWREGB(USB_BASE + MUSB_IND_RXCSRH_OFFSET) = ui32Register; + + // Reset the Data toggle to zero. + if (HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY) + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = (USB_RXCSRL1_CLRDT | USB_RXCSRL1_FLUSH); + else + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_CLRDT; + + fifo_size = musb_get_fifo_size(USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize), &used); + + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = fifo_size & 0x0f; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = (g_musb_udc.fifo_size_offset >> 3); + + g_musb_udc.fifo_size_offset += used; + } else { + g_musb_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_musb_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_musb_udc.in_ep[ep_idx].ep_enable = true; + + HWREGH(USB_BASE + MUSB_IND_TXMAP_OFFSET) = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + + // + // Allow auto setting of TxPktRdy when max packet size has been loaded + // into the FIFO. + // + if (ui32Flags & USB_EP_AUTO_SET) { + ui32Register |= USB_TXCSRH1_AUTOSET; + } + + // + // Configure the DMA mode. + // + if (ui32Flags & USB_EP_DMA_MODE_1) { + ui32Register |= USB_TXCSRH1_DMAEN | USB_TXCSRH1_DMAMOD; + } else if (ui32Flags & USB_EP_DMA_MODE_0) { + ui32Register |= USB_TXCSRH1_DMAEN; + } + + // + // Enable isochronous mode if requested. + // + if (USB_GET_ENDPOINT_TYPE(ep->bmAttributes) == 0x01) { + ui32Register |= USB_TXCSRH1_ISO; + } + + HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) = ui32Register; + + // Reset the Data toggle to zero. + if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_TXCSRL1_CLRDT | USB_TXCSRL1_FLUSH); + else + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_CLRDT; + + fifo_size = musb_get_fifo_size(USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize), &used); + + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = fifo_size & 0x0f; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = (g_musb_udc.fifo_size_offset >> 3); + + g_musb_udc.fifo_size_offset += used; + } + + musb_set_active_ep(old_ep_idx); + + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (ep_idx == 0x00) { + usb_ep0_state = USB_EP0_STATE_STALL; + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); + } else { + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_RXCSRL1_STALL; + } + } else { + if (ep_idx == 0x00) { + usb_ep0_state = USB_EP0_STATE_STALL; + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= (USB_CSRL0_STALL | USB_CSRL0_RXRDYC); + } else { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_STALL; + } + } + + musb_set_active_ep(old_ep_idx); + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (USB_EP_DIR_IS_OUT(ep)) { + if (ep_idx == 0x00) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED; + } else { + // Clear the stall on an OUT endpoint. + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + // Reset the data toggle. + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_RXCSRL1_CLRDT; + } + } else { + if (ep_idx == 0x00) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED; + } else { + // Clear the stall on an IN endpoint. + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~(USB_TXCSRL1_STALL | USB_TXCSRL1_STALLED); + // Reset the data toggle. + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_CLRDT; + } + } + + musb_set_active_ep(old_ep_idx); + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + return 0; +} + +int usb_ep_out_data_avail(uint8_t ep_addr) +{ + uint16_t old_ep_idx, length; + uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (ep_idx == 0) { + if (!(HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_RXRDY)) { + musb_set_active_ep(old_ep_idx); + return 0; + } + length = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET); + musb_set_active_ep(old_ep_idx); + return length; + } else { + if (!(HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY)) { + musb_set_active_ep(old_ep_idx); + return 0; + } + length = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET); + musb_set_active_ep(old_ep_idx); + return length; + } +} + +int usb_ep_in_data_avail(uint8_t ep_addr) +{ + uint16_t old_ep_idx, length; + uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (ep_idx == 0) { + if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_TXRDY) { + musb_set_active_ep(old_ep_idx); + return 0; + } + } else { + if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) { + musb_set_active_ep(old_ep_idx); + return 0; + } + } + length = HWREGH(USB_BASE + MUSB_IND_TXMAP_OFFSET); + musb_set_active_ep(old_ep_idx); + return length; +} + +int usb_ep_wait_in_data_avail(uint8_t ep_addr) +{ + uint32_t cnt; + + for (cnt = 0; cnt < 3000; cnt++) { + if (usb_ep_in_data_avail(ep_addr)) + return cnt; + } + return 0; +} + +int usbd_read_packet(uint8_t ep_addr, uint8_t *buffer, uint16_t len) +{ + uint16_t old_ep_idx, cnt; + uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + if (ep_idx == 0) { + if (!(HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_CSRL0_RXRDY)) { + musb_set_active_ep(old_ep_idx); + return 0; + } + } else { + if (!(HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY)) { + musb_set_active_ep(old_ep_idx); + return 0; + } + } + cnt = usb_ep_out_data_avail(ep_idx); + if (cnt) { + musb_read_packet(ep_idx, buffer, cnt); + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_OVER | USB_RXCSRL1_ERROR | USB_RXCSRL1_STALL | USB_RXCSRL1_STALLED); + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_RXRDY); + musb_set_active_ep(old_ep_idx); + } + return cnt; +} + +int usbd_write_packet(uint8_t ep_addr, uint8_t *buffer, uint16_t len) +{ + uint16_t old_ep_idx, cnt; + uint8_t ep_idx = USB_EP_GET_IDX(ep_addr); + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_UNDRN) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_UNDRN; + } + if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) { + musb_set_active_ep(old_ep_idx); + return -1; + } + + if (!buffer && len) { + return -2; + } + + if (!len) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_TXRDY; + return 0; + } + + cnt = usb_ep_in_data_avail(ep_idx); + if (cnt) { + cnt = MIN(cnt, len); + musb_write_packet(ep_idx, buffer, cnt); + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_TXRDY; + musb_set_active_ep(old_ep_idx); + } + return cnt; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + if (!data && data_len) { + return -1; + } + if (!g_musb_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) { + musb_set_active_ep(old_ep_idx); + return -3; + } + + g_musb_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_musb_udc.in_ep[ep_idx].xfer_len = data_len; + g_musb_udc.in_ep[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + if (ep_idx == 0x00) { + if (g_musb_udc.setup.wLength == 0) { + usb_ep0_state = USB_EP0_STATE_IN_STATUS; + } else { + usb_ep0_state = USB_EP0_STATE_IN_ZLP; + } + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND); + } else { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << ep_idx); + } + musb_set_active_ep(old_ep_idx); + return 0; + } + data_len = MIN(data_len, g_musb_udc.in_ep[ep_idx].ep_mps); + + musb_write_packet(ep_idx, (uint8_t *)data, data_len); + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << ep_idx); + + if (ep_idx == 0x00) { + usb_ep0_state = USB_EP0_STATE_IN_DATA; + if (data_len < g_musb_udc.in_ep[ep_idx].ep_mps) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_TXRDY | USB_CSRL0_DATAEND); + } else { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY; + } + } else { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + } + + musb_set_active_ep(old_ep_idx); + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + uint8_t old_ep_idx; + + if (!data && data_len) { + return -1; + } + if (!g_musb_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + + old_ep_idx = musb_get_active_ep(); + musb_set_active_ep(ep_idx); + + g_musb_udc.out_ep[ep_idx].xfer_buf = data; + g_musb_udc.out_ep[ep_idx].xfer_len = data_len; + g_musb_udc.out_ep[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + if (ep_idx == 0) { + usb_ep0_state = USB_EP0_STATE_SETUP; + } + musb_set_active_ep(old_ep_idx); + return 0; + } + if (ep_idx == 0) { + usb_ep0_state = USB_EP0_STATE_OUT_DATA; + } else { + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << ep_idx); + } + musb_set_active_ep(old_ep_idx); + return 0; +} + +static void handle_ep0(void) +{ + uint8_t ep0_status = HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET); + uint16_t read_count; + + if (ep0_status & USB_CSRL0_STALLED) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED; + usb_ep0_state = USB_EP0_STATE_SETUP; + return; + } + + if (ep0_status & USB_CSRL0_SETEND) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_SETENDC; + } + + if (g_musb_udc.dev_addr > 0) { + HWREGB(USB_BASE + MUSB_FADDR_OFFSET) = g_musb_udc.dev_addr; + g_musb_udc.dev_addr = 0; + } + + switch (usb_ep0_state) { + case USB_EP0_STATE_SETUP: + if (ep0_status & USB_CSRL0_RXRDY) { + read_count = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET); + + if (read_count != 8) { + return; + } + + musb_read_packet(0, (uint8_t *)&g_musb_udc.setup, 8); + if (g_musb_udc.setup.wLength) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_RXRDYC; + } else { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND); + } + + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_musb_udc.setup); + } + break; + + case USB_EP0_STATE_IN_DATA: + if (g_musb_udc.in_ep[0].xfer_len > g_musb_udc.in_ep[0].ep_mps) { + g_musb_udc.in_ep[0].actual_xfer_len += g_musb_udc.in_ep[0].ep_mps; + g_musb_udc.in_ep[0].xfer_len -= g_musb_udc.in_ep[0].ep_mps; + } else { + g_musb_udc.in_ep[0].actual_xfer_len += g_musb_udc.in_ep[0].xfer_len; + g_musb_udc.in_ep[0].xfer_len = 0; + } + + usbd_event_ep_in_complete_handler(0, 0x80, g_musb_udc.in_ep[0].actual_xfer_len); + + break; + case USB_EP0_STATE_OUT_DATA: + if (ep0_status & USB_CSRL0_RXRDY) { + read_count = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET); + + musb_read_packet(0, g_musb_udc.out_ep[0].xfer_buf, read_count); + g_musb_udc.out_ep[0].xfer_buf += read_count; + g_musb_udc.out_ep[0].actual_xfer_len += read_count; + + if (read_count < g_musb_udc.out_ep[0].ep_mps) { + usbd_event_ep_out_complete_handler(0, 0x00, g_musb_udc.out_ep[0].actual_xfer_len); + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_RXRDYC | USB_CSRL0_DATAEND); + usb_ep0_state = USB_EP0_STATE_IN_STATUS; + } else { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_RXRDYC; + } + } + break; + case USB_EP0_STATE_IN_STATUS: + case USB_EP0_STATE_IN_ZLP: + usb_ep0_state = USB_EP0_STATE_SETUP; + usbd_event_ep_in_complete_handler(0, 0x80, 0); + break; + } +} + +void USBD_IRQHandler(uint8_t busid) +{ + uint32_t is; + uint32_t txis; + uint32_t rxis; + uint8_t old_ep_idx; + uint8_t ep_idx; + uint16_t write_count, read_count; + + is = HWREGB(USB_BASE + MUSB_IS_OFFSET); + txis = HWREGH(USB_BASE + MUSB_TXIS_OFFSET); + rxis = HWREGH(USB_BASE + MUSB_RXIS_OFFSET); + + HWREGB(USB_BASE + MUSB_IS_OFFSET) = is; + + old_ep_idx = musb_get_active_ep(); + + /* Receive a reset signal from the USB bus */ + if (is & USB_IS_RESET) { + memset(&g_musb_udc, 0, sizeof(struct musb_udc)); + g_musb_udc.fifo_size_offset = USB_CTRL_EP_MPS; + usbd_event_reset_handler(0); + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0; + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; + + for (uint8_t i = 1; i < CONFIG_USBDEV_EP_NUM; i++) { + musb_set_active_ep(i); + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = 0; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = 0; + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = 0; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = 0; + } + usb_ep0_state = USB_EP0_STATE_SETUP; + } + + if (is & USB_IS_SOF) { + } + + if (is & USB_IS_RESUME) { + } + + if (is & USB_IS_SUSPEND) { + } + + txis &= HWREGH(USB_BASE + MUSB_TXIE_OFFSET); + /* Handle EP0 interrupt */ + if (txis & USB_TXIE_EP0) { + HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = USB_TXIE_EP0; + musb_set_active_ep(0); + handle_ep0(); + txis &= ~USB_TXIE_EP0; + } + + ep_idx = 1; + while (txis) { + if (txis & (1 << ep_idx)) { + musb_set_active_ep(ep_idx); + HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = (1 << ep_idx); + if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_UNDRN) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_UNDRN; + } + + if (g_musb_udc.in_ep[ep_idx].xfer_len > g_musb_udc.in_ep[ep_idx].ep_mps) { + g_musb_udc.in_ep[ep_idx].xfer_buf += g_musb_udc.in_ep[ep_idx].ep_mps; + g_musb_udc.in_ep[ep_idx].actual_xfer_len += g_musb_udc.in_ep[ep_idx].ep_mps; + g_musb_udc.in_ep[ep_idx].xfer_len -= g_musb_udc.in_ep[ep_idx].ep_mps; + } else { + g_musb_udc.in_ep[ep_idx].xfer_buf += g_musb_udc.in_ep[ep_idx].xfer_len; + g_musb_udc.in_ep[ep_idx].actual_xfer_len += g_musb_udc.in_ep[ep_idx].xfer_len; + g_musb_udc.in_ep[ep_idx].xfer_len = 0; + } + + if (g_musb_udc.in_ep[ep_idx].xfer_len == 0) { + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) &= ~(1 << ep_idx); + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_musb_udc.in_ep[ep_idx].actual_xfer_len); + } else { + write_count = MIN(g_musb_udc.in_ep[ep_idx].xfer_len, g_musb_udc.in_ep[ep_idx].ep_mps); + + musb_write_packet(ep_idx, g_musb_udc.in_ep[ep_idx].xfer_buf, write_count); + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + } + + txis &= ~(1 << ep_idx); + } + ep_idx++; + } + + rxis &= HWREGH(USB_BASE + MUSB_RXIE_OFFSET); + ep_idx = 1; + while (rxis) { + if (rxis & (1 << ep_idx)) { + musb_set_active_ep(ep_idx); + HWREGH(USB_BASE + MUSB_RXIS_OFFSET) = (1 << ep_idx); + if (HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY) { + read_count = HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET); + + musb_read_packet(ep_idx, g_musb_udc.out_ep[ep_idx].xfer_buf, read_count); + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~(USB_RXCSRL1_RXRDY); + + g_musb_udc.out_ep[ep_idx].xfer_buf += read_count; + g_musb_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_musb_udc.out_ep[ep_idx].xfer_len -= read_count; + + if ((read_count < g_musb_udc.out_ep[ep_idx].ep_mps) || (g_musb_udc.out_ep[ep_idx].xfer_len == 0)) { + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) &= ~(1 << ep_idx); + usbd_event_ep_out_complete_handler(0, ep_idx, g_musb_udc.out_ep[ep_idx].actual_xfer_len); + } else { + } + } + + rxis &= ~(1 << ep_idx); + } + ep_idx++; + } + + musb_set_active_ep(old_ep_idx); +} diff --git a/components/drivers/usb/cherryusb/port/musb/usb_glue_sunxi.c b/components/drivers/usb/cherryusb/port/musb/usb_glue_sunxi.c new file mode 100644 index 00000000000..c30681bfea4 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/musb/usb_glue_sunxi.c @@ -0,0 +1,5 @@ +#include "usb_config.h" + +#ifndef CONFIG_USB_MUSB_SUNXI +#error must define CONFIG_USB_MUSB_SUNXI when use sunxi chips +#endif \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c b/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c new file mode 100644 index 00000000000..ef700fbfc63 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/musb/usb_hc_musb.c @@ -0,0 +1,1018 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbh_core.h" +#include "usbh_hub.h" +#include "usb_musb_reg.h" + +#define HWREG(x) \ + (*((volatile uint32_t *)(x))) +#define HWREGH(x) \ + (*((volatile uint16_t *)(x))) +#define HWREGB(x) \ + (*((volatile uint8_t *)(x))) + +#define USB_BASE (bus->hcd.reg_base) + +#if CONFIG_USBHOST_PIPE_NUM != 4 +#error musb host ip only supports 4 pipe num +#endif + +#ifdef CONFIG_USB_MUSB_SUNXI +#define MUSB_FADDR_OFFSET 0x98 +#define MUSB_POWER_OFFSET 0x40 +#define MUSB_TXIS_OFFSET 0x44 +#define MUSB_RXIS_OFFSET 0x46 +#define MUSB_TXIE_OFFSET 0x48 +#define MUSB_RXIE_OFFSET 0x4A +#define MUSB_IS_OFFSET 0x4C +#define MUSB_IE_OFFSET 0x50 +#define MUSB_EPIDX_OFFSET 0x42 + +#define MUSB_IND_TXMAP_OFFSET 0x80 +#define MUSB_IND_TXCSRL_OFFSET 0x82 +#define MUSB_IND_TXCSRH_OFFSET 0x83 +#define MUSB_IND_RXMAP_OFFSET 0x84 +#define MUSB_IND_RXCSRL_OFFSET 0x86 +#define MUSB_IND_RXCSRH_OFFSET 0x87 +#define MUSB_IND_RXCOUNT_OFFSET 0x88 +#define MUSB_IND_TXTYPE_OFFSET 0x8C +#define MUSB_IND_TXINTERVAL_OFFSET 0x8D +#define MUSB_IND_RXTYPE_OFFSET 0x8E +#define MUSB_IND_RXINTERVAL_OFFSET 0x8F + +#define MUSB_FIFO_OFFSET 0x00 + +#define MUSB_DEVCTL_OFFSET 0x41 + +#define MUSB_TXFIFOSZ_OFFSET 0x90 +#define MUSB_RXFIFOSZ_OFFSET 0x94 +#define MUSB_TXFIFOADD_OFFSET 0x92 +#define MUSB_RXFIFOADD_OFFSET 0x96 + +#define MUSB_TXFUNCADDR0_OFFSET 0x98 +#define MUSB_TXHUBADDR0_OFFSET 0x9A +#define MUSB_TXHUBPORT0_OFFSET 0x9B +#define MUSB_TXFUNCADDRx_OFFSET 0x98 +#define MUSB_TXHUBADDRx_OFFSET 0x9A +#define MUSB_TXHUBPORTx_OFFSET 0x9B +#define MUSB_RXFUNCADDRx_OFFSET 0x9C +#define MUSB_RXHUBADDRx_OFFSET 0x9E +#define MUSB_RXHUBPORTx_OFFSET 0x9F + +#define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDRx_OFFSET) +#define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXHUBADDRx_OFFSET) +#define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXHUBPORTx_OFFSET) +#define USB_RXADDR_BASE(ep_idx) (USB_BASE + MUSB_RXFUNCADDRx_OFFSET) +#define USB_RXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_RXHUBADDRx_OFFSET) +#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_RXHUBPORTx_OFFSET) + +#elif defined(CONFIG_USB_MUSB_CUSTOM) +#include "musb_custom.h" +#else +#define MUSB_FADDR_OFFSET 0x00 +#define MUSB_POWER_OFFSET 0x01 +#define MUSB_TXIS_OFFSET 0x02 +#define MUSB_RXIS_OFFSET 0x04 +#define MUSB_TXIE_OFFSET 0x06 +#define MUSB_RXIE_OFFSET 0x08 +#define MUSB_IS_OFFSET 0x0A +#define MUSB_IE_OFFSET 0x0B + +#define MUSB_EPIDX_OFFSET 0x0E + +#define MUSB_IND_TXMAP_OFFSET 0x10 +#define MUSB_IND_TXCSRL_OFFSET 0x12 +#define MUSB_IND_TXCSRH_OFFSET 0x13 +#define MUSB_IND_RXMAP_OFFSET 0x14 +#define MUSB_IND_RXCSRL_OFFSET 0x16 +#define MUSB_IND_RXCSRH_OFFSET 0x17 +#define MUSB_IND_RXCOUNT_OFFSET 0x18 +#define MUSB_IND_TXTYPE_OFFSET 0x1A +#define MUSB_IND_TXINTERVAL_OFFSET 0x1B +#define MUSB_IND_RXTYPE_OFFSET 0x1C +#define MUSB_IND_RXINTERVAL_OFFSET 0x1D + +#define MUSB_FIFO_OFFSET 0x20 + +#define MUSB_DEVCTL_OFFSET 0x60 + +#define MUSB_TXFIFOSZ_OFFSET 0x62 +#define MUSB_RXFIFOSZ_OFFSET 0x63 +#define MUSB_TXFIFOADD_OFFSET 0x64 +#define MUSB_RXFIFOADD_OFFSET 0x66 + +#define MUSB_TXFUNCADDR0_OFFSET 0x80 +#define MUSB_TXHUBADDR0_OFFSET 0x82 +#define MUSB_TXHUBPORT0_OFFSET 0x83 +#define MUSB_TXFUNCADDRx_OFFSET 0x88 +#define MUSB_TXHUBADDRx_OFFSET 0x8A +#define MUSB_TXHUBPORTx_OFFSET 0x8B +#define MUSB_RXFUNCADDRx_OFFSET 0x8C +#define MUSB_RXHUBADDRx_OFFSET 0x8E +#define MUSB_RXHUBPORTx_OFFSET 0x8F + +#define USB_TXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx) +#define USB_TXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 2) +#define USB_TXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 3) +#define USB_RXADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 4) +#define USB_RXHUBADDR_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 6) +#define USB_RXHUBPORT_BASE(ep_idx) (USB_BASE + MUSB_TXFUNCADDR0_OFFSET + 0x8 * ep_idx + 7) +#endif + +#define USB_FIFO_BASE(ep_idx) (USB_BASE + MUSB_FIFO_OFFSET + 0x4 * ep_idx) + +#ifndef CONIFG_USB_MUSB_PIPE_NUM +#define CONIFG_USB_MUSB_PIPE_NUM 5 +#endif + +typedef enum { + USB_EP0_STATE_SETUP = 0x0, /**< SETUP DATA */ + USB_EP0_STATE_IN_DATA, /**< IN DATA */ + USB_EP0_STATE_IN_STATUS, /**< IN status*/ + USB_EP0_STATE_OUT_DATA, /**< OUT DATA */ + USB_EP0_STATE_OUT_STATUS, /**< OUT status */ +} ep0_state_t; + +struct musb_pipe { + uint8_t chidx; + bool inuse; + uint32_t xfrd; + volatile uint8_t ep0_state; + usb_osal_sem_t waitsem; + struct usbh_urb *urb; +}; + +struct musb_hcd { + volatile bool port_csc; + volatile bool port_pec; + volatile bool port_pe; + struct musb_pipe pipe_pool[CONFIG_USBHOST_PIPE_NUM]; +} g_musb_hcd[CONFIG_USBHOST_MAX_BUS]; + +/* get current active ep */ +static uint8_t musb_get_active_ep(struct usbh_bus *bus) +{ + return HWREGB(USB_BASE + MUSB_EPIDX_OFFSET); +} + +/* set the active ep */ +static void musb_set_active_ep(struct usbh_bus *bus, uint8_t ep_index) +{ + HWREGB(USB_BASE + MUSB_EPIDX_OFFSET) = ep_index; +} + +static void musb_fifo_flush(struct usbh_bus *bus, uint8_t ep) +{ + uint8_t ep_idx = ep & 0x7f; + if (ep_idx == 0) { + if ((HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & (USB_CSRL0_RXRDY | USB_CSRL0_TXRDY)) != 0) + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_CSRH0_FLUSH; + } else { + if (ep & 0x80) { + if (HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) & USB_TXCSRL1_TXRDY) + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) |= USB_TXCSRL1_FLUSH; + } else { + if (HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) & USB_RXCSRL1_RXRDY) + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) |= USB_RXCSRL1_FLUSH; + } + } +} + +static void musb_write_packet(struct usbh_bus *bus, uint8_t ep_idx, uint8_t *buffer, uint16_t len) +{ + uint32_t *buf32; + uint8_t *buf8; + uint32_t count32; + uint32_t count8; + int i; + + if ((uint32_t)buffer & 0x03) { + buf8 = buffer; + for (i = 0; i < len; i++) { + HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++; + } + } else { + count32 = len >> 2; + count8 = len & 0x03; + + buf32 = (uint32_t *)buffer; + + while (count32--) { + HWREG(USB_FIFO_BASE(ep_idx)) = *buf32++; + } + + buf8 = (uint8_t *)buf32; + + while (count8--) { + HWREGB(USB_FIFO_BASE(ep_idx)) = *buf8++; + } + } +} + +static void musb_read_packet(struct usbh_bus *bus, uint8_t ep_idx, uint8_t *buffer, uint16_t len) +{ + uint32_t *buf32; + uint8_t *buf8; + uint32_t count32; + uint32_t count8; + int i; + + if ((uint32_t)buffer & 0x03) { + buf8 = buffer; + for (i = 0; i < len; i++) { + *buf8++ = HWREGB(USB_FIFO_BASE(ep_idx)); + } + } else { + count32 = len >> 2; + count8 = len & 0x03; + + buf32 = (uint32_t *)buffer; + + while (count32--) { + *buf32++ = HWREG(USB_FIFO_BASE(ep_idx)); + } + + buf8 = (uint8_t *)buf32; + + while (count8--) { + *buf8++ = HWREGB(USB_FIFO_BASE(ep_idx)); + } + } +} + +void musb_control_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, struct usb_setup_packet *setup, uint8_t *buffer, uint32_t buflen) +{ + uint8_t old_ep_index; + uint8_t speed = USB_TXTYPE1_SPEED_FULL; + + old_ep_index = musb_get_active_ep(bus); + musb_set_active_ep(bus, chidx); + + if (urb->hport->speed == USB_SPEED_HIGH) { + speed = USB_TYPE0_SPEED_HIGH; + } else if (urb->hport->speed == USB_SPEED_FULL) { + speed = USB_TYPE0_SPEED_FULL; + } else if (urb->hport->speed == USB_SPEED_LOW) { + speed = USB_TYPE0_SPEED_LOW; + } + + HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; + HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = speed; + HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; + HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; + + musb_write_packet(bus, chidx, (uint8_t *)setup, 8); + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY | USB_CSRL0_SETUP; + musb_set_active_ep(bus, old_ep_index); +} + +void musb_bulk_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + uint8_t old_ep_index; + uint8_t speed = USB_TXTYPE1_SPEED_FULL; + + old_ep_index = musb_get_active_ep(bus); + musb_set_active_ep(bus, chidx); + + if (urb->hport->speed == USB_SPEED_HIGH) { + speed = USB_TXTYPE1_SPEED_HIGH; + } else if (urb->hport->speed == USB_SPEED_FULL) { + speed = USB_TXTYPE1_SPEED_FULL; + } else if (urb->hport->speed == USB_SPEED_LOW) { + speed = USB_TXTYPE1_SPEED_LOW; + } + + if (urb->ep->bEndpointAddress & 0x80) { + HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; + HWREGB(USB_BASE + MUSB_IND_RXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGB(USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) = 0; + HWREGB(USB_RXHUBADDR_BASE(chidx)) = 0; + HWREGB(USB_RXHUBPORT_BASE(chidx)) = 0; + HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE; + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT; + + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << chidx); + } else { + HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; + HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_BULK; + HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = 0; + HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; + HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; + + if (buflen > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + buflen = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + musb_write_packet(bus, chidx, buffer, buflen); + HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE; + HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) |= USB_TXCSRH1_MODE; + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << chidx); + } + musb_set_active_ep(bus, old_ep_index); +} + +void musb_intr_urb_init(struct usbh_bus *bus, uint8_t chidx, struct usbh_urb *urb, uint8_t *buffer, uint32_t buflen) +{ + uint8_t old_ep_index; + uint8_t speed = USB_TXTYPE1_SPEED_FULL; + + old_ep_index = musb_get_active_ep(bus); + musb_set_active_ep(bus, chidx); + + if (urb->hport->speed == USB_SPEED_HIGH) { + speed = USB_TXTYPE1_SPEED_HIGH; + } else if (urb->hport->speed == USB_SPEED_FULL) { + speed = USB_TXTYPE1_SPEED_FULL; + } else if (urb->hport->speed == USB_SPEED_LOW) { + speed = USB_TXTYPE1_SPEED_LOW; + } + + if (urb->ep->bEndpointAddress & 0x80) { + HWREGB(USB_RXADDR_BASE(chidx)) = urb->hport->dev_addr; + HWREGB(USB_BASE + MUSB_IND_RXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGB(USB_BASE + MUSB_IND_RXINTERVAL_OFFSET) = urb->ep->bInterval; + HWREGB(USB_RXHUBADDR_BASE(chidx)) = 0; + HWREGB(USB_RXHUBPORT_BASE(chidx)) = 0; + HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE; + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT; + + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) |= (1 << chidx); + } else { + HWREGB(USB_TXADDR_BASE(chidx)) = urb->hport->dev_addr; + HWREGB(USB_BASE + MUSB_IND_TXTYPE_OFFSET) = (urb->ep->bEndpointAddress & 0x0f) | speed | USB_TXTYPE1_PROTO_INT; + HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = urb->ep->bInterval; + HWREGB(USB_TXHUBADDR_BASE(chidx)) = 0; + HWREGB(USB_TXHUBPORT_BASE(chidx)) = 0; + + if (buflen > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + buflen = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + musb_write_packet(bus, chidx, buffer, buflen); + HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) &= ~USB_TXCSRH1_MODE; + HWREGB(USB_BASE + MUSB_IND_TXCSRH_OFFSET) |= USB_TXCSRH1_MODE; + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) |= (1 << chidx); + } + musb_set_active_ep(bus, old_ep_index); +} + +static int usbh_reset_port(struct usbh_bus *bus, const uint8_t port) +{ + g_musb_hcd[bus->hcd.hcd_id].port_pe = 0; + HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_RESET; + usb_osal_msleep(20); + HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~(USB_POWER_RESET); + usb_osal_msleep(20); + g_musb_hcd[bus->hcd.hcd_id].port_pe = 1; + return 0; +} + +static uint8_t usbh_get_port_speed(struct usbh_bus *bus, const uint8_t port) +{ + uint8_t speed = USB_SPEED_UNKNOWN; + + if (HWREGB(USB_BASE + MUSB_POWER_OFFSET) & USB_POWER_HSMODE) + speed = USB_SPEED_HIGH; + else if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_FSDEV) + speed = USB_SPEED_FULL; + else if (HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) & USB_DEVCTL_LSDEV) + speed = USB_SPEED_LOW; + + return speed; +} + +#if 0 +static int musb_pipe_alloc(void) +{ + int chidx; + + for (chidx = 1; chidx < CONFIG_USBHOST_PIPE_NUM; chidx++) { + if (!g_musb_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse) { + g_musb_hcd[bus->hcd.hcd_id].pipe_pool[chidx].inuse = true; + return chidx; + } + } + + return -1; +} +#endif + +static void musb_pipe_free(struct musb_pipe *pipe) +{ +#if 0 + pipe->inuse = false; +#endif +} + +__WEAK void usb_hc_low_level_init(struct usbh_bus *bus) +{ +} + +__WEAK void usb_hc_low_level_deinit(struct usbh_bus *bus) +{ +} + +int usb_hc_init(struct usbh_bus *bus) +{ + uint8_t regval; + uint32_t fifo_offset = 0; + + memset(&g_musb_hcd[bus->hcd.hcd_id], 0, sizeof(struct musb_hcd)); + + for (uint8_t i = 0; i < CONFIG_USBHOST_PIPE_NUM; i++) { + g_musb_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem = usb_osal_sem_create(0); + } + + usb_hc_low_level_init(bus); + + musb_set_active_ep(bus, 0); + HWREGB(USB_BASE + MUSB_IND_TXINTERVAL_OFFSET) = 0; + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_64; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = 0; + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_64; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = 0; + fifo_offset += 64; + + for (uint8_t i = 1; i < CONIFG_USB_MUSB_PIPE_NUM; i++) { + musb_set_active_ep(bus, i); + HWREGB(USB_BASE + MUSB_TXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_512; + HWREGH(USB_BASE + MUSB_TXFIFOADD_OFFSET) = fifo_offset; + HWREGB(USB_BASE + MUSB_RXFIFOSZ_OFFSET) = USB_TXFIFOSZ_SIZE_512; + HWREGH(USB_BASE + MUSB_RXFIFOADD_OFFSET) = fifo_offset; + fifo_offset += 512; + } + + /* Enable USB interrupts */ + regval = USB_IE_RESET | USB_IE_CONN | USB_IE_DISCON | + USB_IE_RESUME | USB_IE_SUSPND | + USB_IE_BABBLE | USB_IE_SESREQ | USB_IE_VBUSERR; + + HWREGB(USB_BASE + MUSB_IE_OFFSET) = regval; + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = USB_TXIE_EP0; + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; + + HWREGB(USB_BASE + MUSB_POWER_OFFSET) |= USB_POWER_HSENAB; + + HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) |= USB_DEVCTL_SESSION; + +#ifdef CONFIG_USB_MUSB_SUNXI + musb_set_active_ep(bus, 0); + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY; +#endif + return 0; +} + +int usb_hc_deinit(struct usbh_bus *bus) +{ + HWREGB(USB_BASE + MUSB_IE_OFFSET) = 0; + HWREGH(USB_BASE + MUSB_TXIE_OFFSET) = 0; + HWREGH(USB_BASE + MUSB_RXIE_OFFSET) = 0; + + HWREGB(USB_BASE + MUSB_POWER_OFFSET) &= ~USB_POWER_HSENAB; + HWREGB(USB_BASE + MUSB_DEVCTL_OFFSET) &= ~USB_DEVCTL_SESSION; + + for (uint8_t i = 0; i < CONFIG_USBHOST_PIPE_NUM; i++) { + usb_osal_sem_delete(g_musb_hcd[bus->hcd.hcd_id].pipe_pool[i].waitsem); + } + + usb_hc_low_level_deinit(bus); + return 0; +} + +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + uint8_t nports; + uint8_t port; + uint32_t status; + + nports = CONFIG_USBHOST_MAX_RHPORTS; + port = setup->wIndex; + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_SET_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + break; + case HUB_REQUEST_GET_STATUS: + memset(buf, 0, 4); + break; + default: + break; + } + } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_ENABLE: + break; + case HUB_PORT_FEATURE_SUSPEND: + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_C_CONNECTION: + g_musb_hcd[bus->hcd.hcd_id].port_csc = 0; + break; + case HUB_PORT_FEATURE_C_ENABLE: + g_musb_hcd[bus->hcd.hcd_id].port_pec = 0; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + break; + case HUB_PORT_FEATURE_C_RESET: + break; + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_RESET: + usbh_reset_port(bus, port); + break; + + default: + return -USB_ERR_INVAL; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + status = 0; + if (g_musb_hcd[bus->hcd.hcd_id].port_csc) { + status |= (1 << HUB_PORT_FEATURE_C_CONNECTION); + } + if (g_musb_hcd[bus->hcd.hcd_id].port_pec) { + status |= (1 << HUB_PORT_FEATURE_C_ENABLE); + } + + if (g_musb_hcd[bus->hcd.hcd_id].port_pe) { + status |= (1 << HUB_PORT_FEATURE_CONNECTION); + status |= (1 << HUB_PORT_FEATURE_ENABLE); + if (usbh_get_port_speed(bus, port) == USB_SPEED_LOW) { + status |= (1 << HUB_PORT_FEATURE_LOWSPEED); + } else if (usbh_get_port_speed(bus, port) == USB_SPEED_HIGH) { + status |= (1 << HUB_PORT_FEATURE_HIGHSPEED); + } + } + + memcpy(buf, &status, 4); + break; + default: + break; + } + } + return 0; +} + +int usbh_submit_urb(struct usbh_urb *urb) +{ + struct musb_pipe *pipe; + struct usbh_bus *bus; + int chidx; + size_t flags; + int ret = 0; + + if (!urb || !urb->hport || !urb->ep || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + if (!urb->hport->connected) { + return -USB_ERR_NOTCONN; + } + + if (urb->errorcode == -USB_ERR_BUSY) { + return -USB_ERR_BUSY; + } + + bus = urb->hport->bus; + + flags = usb_osal_enter_critical_section(); + + if (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes) == USB_ENDPOINT_TYPE_CONTROL) { + chidx = 0; + } else { + chidx = (urb->ep->bEndpointAddress & 0x0f); + + if (chidx > (CONFIG_USBHOST_PIPE_NUM - 1)) { + return -USB_ERR_RANGE; + } + } + + pipe = &g_musb_hcd[bus->hcd.hcd_id].pipe_pool[chidx]; + pipe->chidx = chidx; + pipe->urb = urb; + + urb->hcpriv = pipe; + urb->errorcode = -USB_ERR_BUSY; + urb->actual_length = 0; + + usb_osal_sem_reset(pipe->waitsem); + + switch (USB_GET_ENDPOINT_TYPE(urb->ep->bmAttributes)) { + case USB_ENDPOINT_TYPE_CONTROL: + pipe->ep0_state = USB_EP0_STATE_SETUP; + musb_control_urb_init(bus, 0, urb, urb->setup, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_BULK: + musb_bulk_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_INTERRUPT: + musb_intr_urb_init(bus, chidx, urb, urb->transfer_buffer, urb->transfer_buffer_length); + break; + case USB_ENDPOINT_TYPE_ISOCHRONOUS: + return -USB_ERR_NOTSUPP; + default: + break; + } + usb_osal_leave_critical_section(flags); + + if (urb->timeout > 0) { + /* wait until timeout or sem give */ + ret = usb_osal_sem_take(pipe->waitsem, urb->timeout); + if (ret < 0) { + goto errout_timeout; + } + urb->timeout = 0; + ret = urb->errorcode; + /* we can free pipe when waitsem is done */ + musb_pipe_free(pipe); + } + return ret; +errout_timeout: + urb->timeout = 0; + usbh_kill_urb(urb); + return ret; +} + +int usbh_kill_urb(struct usbh_urb *urb) +{ + struct musb_pipe *pipe; + struct usbh_bus *bus; + size_t flags; + + if (!urb || !urb->hcpriv || !urb->hport->bus) { + return -USB_ERR_INVAL; + } + + bus = urb->hport->bus; + + ARG_UNUSED(bus); + + flags = usb_osal_enter_critical_section(); + + pipe = (struct musb_pipe *)urb->hcpriv; + urb->hcpriv = NULL; + urb->errorcode = -USB_ERR_SHUTDOWN; + pipe->urb = NULL; + + if (urb->timeout) { + usb_osal_sem_give(pipe->waitsem); + } else { + musb_pipe_free(pipe); + } + + usb_osal_leave_critical_section(flags); + return 0; +} + +static void musb_urb_waitup(struct usbh_urb *urb) +{ + struct musb_pipe *pipe; + + pipe = (struct musb_pipe *)urb->hcpriv; + pipe->urb = NULL; + urb->hcpriv = NULL; + + if (urb->timeout) { + usb_osal_sem_give(pipe->waitsem); + } else { + musb_pipe_free(pipe); + } + + if (urb->complete) { + if (urb->errorcode < 0) { + urb->complete(urb->arg, urb->errorcode); + } else { + urb->complete(urb->arg, urb->actual_length); + } + } +} + +void handle_ep0(struct usbh_bus *bus) +{ + uint8_t ep0_status; + struct musb_pipe *pipe; + struct usbh_urb *urb; + uint32_t size; + + pipe = (struct musb_pipe *)&g_musb_hcd[bus->hcd.hcd_id].pipe_pool[0]; + urb = pipe->urb; + if (urb == NULL) { + return; + } + + musb_set_active_ep(bus, 0); + ep0_status = HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET); + if (ep0_status & USB_CSRL0_STALLED) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALLED; + pipe->ep0_state = USB_EP0_STATE_SETUP; + urb->errorcode = -USB_ERR_STALL; + musb_urb_waitup(urb); + return; + } + if (ep0_status & USB_CSRL0_ERROR) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_ERROR; + musb_fifo_flush(bus, 0); + pipe->ep0_state = USB_EP0_STATE_SETUP; + urb->errorcode = -USB_ERR_IO; + musb_urb_waitup(urb); + return; + } + if (ep0_status & USB_CSRL0_STALL) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_STALL; + pipe->ep0_state = USB_EP0_STATE_SETUP; + urb->errorcode = -USB_ERR_STALL; + musb_urb_waitup(urb); + return; + } + + switch (pipe->ep0_state) { + case USB_EP0_STATE_SETUP: + urb->actual_length += 8; + if (urb->transfer_buffer_length) { + if (urb->setup->bmRequestType & 0x80) { + pipe->ep0_state = USB_EP0_STATE_IN_DATA; + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_REQPKT; + } else { + pipe->ep0_state = USB_EP0_STATE_OUT_DATA; + size = urb->transfer_buffer_length; + if (size > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + size = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + musb_write_packet(bus, 0, urb->transfer_buffer, size); + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY; + + urb->transfer_buffer += size; + urb->transfer_buffer_length -= size; + urb->actual_length += size; + } + } else { + pipe->ep0_state = USB_EP0_STATE_IN_STATUS; + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_REQPKT | USB_CSRL0_STATUS); + } + break; + case USB_EP0_STATE_IN_DATA: + if (ep0_status & USB_CSRL0_RXRDY) { + size = urb->transfer_buffer_length; + if (size > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + size = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + size = MIN(size, HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET)); + musb_read_packet(bus, 0, urb->transfer_buffer, size); + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_CSRL0_RXRDY; + urb->transfer_buffer += size; + urb->transfer_buffer_length -= size; + urb->actual_length += size; + + if ((size < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) || (urb->transfer_buffer_length == 0)) { + pipe->ep0_state = USB_EP0_STATE_OUT_STATUS; + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_TXRDY | USB_CSRL0_STATUS); + } else { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_REQPKT; + } + } + break; + case USB_EP0_STATE_OUT_DATA: + if (urb->transfer_buffer_length > 0) { + size = urb->transfer_buffer_length; + if (size > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + size = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + musb_write_packet(bus, 0, urb->transfer_buffer, size); + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_CSRL0_TXRDY; + + urb->transfer_buffer += size; + urb->transfer_buffer_length -= size; + urb->actual_length += size; + } else { + pipe->ep0_state = USB_EP0_STATE_IN_STATUS; + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = (USB_CSRL0_REQPKT | USB_CSRL0_STATUS); + } + break; + case USB_EP0_STATE_OUT_STATUS: + urb->errorcode = 0; + musb_urb_waitup(urb); + break; + case USB_EP0_STATE_IN_STATUS: + if (ep0_status & (USB_CSRL0_RXRDY | USB_CSRL0_STATUS)) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~(USB_CSRL0_RXRDY | USB_CSRL0_STATUS); + urb->errorcode = 0; + musb_urb_waitup(urb); + } + break; + } +} + +void USBH_IRQHandler(uint8_t busid) +{ + uint32_t is; + uint32_t txis; + uint32_t rxis; + uint8_t ep_csrl_status; + // uint8_t ep_csrh_status; + struct musb_pipe *pipe; + struct usbh_urb *urb; + uint8_t ep_idx; + uint8_t old_ep_idx; + struct usbh_bus *bus; + + bus = &g_usbhost_bus[busid]; + + is = HWREGB(USB_BASE + MUSB_IS_OFFSET); + txis = HWREGH(USB_BASE + MUSB_TXIS_OFFSET); + rxis = HWREGH(USB_BASE + MUSB_RXIS_OFFSET); + + HWREGB(USB_BASE + MUSB_IS_OFFSET) = is; + + old_ep_idx = musb_get_active_ep(bus); + + if (is & USB_IS_CONN) { + g_musb_hcd[bus->hcd.hcd_id].port_csc = 1; + g_musb_hcd[bus->hcd.hcd_id].port_pec = 1; + g_musb_hcd[bus->hcd.hcd_id].port_pe = 1; + bus->hcd.roothub.int_buffer[0] = (1 << 1); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + + if (is & USB_IS_DISCON) { + g_musb_hcd[bus->hcd.hcd_id].port_csc = 1; + g_musb_hcd[bus->hcd.hcd_id].port_pec = 1; + g_musb_hcd[bus->hcd.hcd_id].port_pe = 0; + bus->hcd.roothub.int_buffer[0] = (1 << 1); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + + if (is & USB_IS_SOF) { + } + + if (is & USB_IS_RESUME) { + } + + if (is & USB_IS_SUSPEND) { + } + + if (is & USB_IS_VBUSERR) { + } + + if (is & USB_IS_SESREQ) { + } + + if (is & USB_IS_BABBLE) { + } + + txis &= HWREGH(USB_BASE + MUSB_TXIE_OFFSET); + /* Handle EP0 interrupt */ + if (txis & USB_TXIE_EP0) { + txis &= ~USB_TXIE_EP0; + HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = USB_TXIE_EP0; + handle_ep0(bus); + } + + for (ep_idx = 1; ep_idx < CONIFG_USB_MUSB_PIPE_NUM; ep_idx++) { + if (txis & (1 << ep_idx)) { + HWREGH(USB_BASE + MUSB_TXIS_OFFSET) = (1 << ep_idx); + + pipe = &g_musb_hcd[bus->hcd.hcd_id].pipe_pool[ep_idx]; + urb = pipe->urb; + musb_set_active_ep(bus, ep_idx); + + ep_csrl_status = HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET); + + if (ep_csrl_status & USB_TXCSRL1_ERROR) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_ERROR; + urb->errorcode = -USB_ERR_IO; + musb_urb_waitup(urb); + } else if (ep_csrl_status & USB_TXCSRL1_NAKTO) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_NAKTO; + urb->errorcode = -USB_ERR_NAK; + musb_urb_waitup(urb); + } else if (ep_csrl_status & USB_TXCSRL1_STALL) { + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) &= ~USB_TXCSRL1_STALL; + urb->errorcode = -USB_ERR_STALL; + musb_urb_waitup(urb); + } else { + uint32_t size = urb->transfer_buffer_length; + + if (size > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + size = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + + urb->transfer_buffer += size; + urb->transfer_buffer_length -= size; + urb->actual_length += size; + + if (urb->transfer_buffer_length == 0) { + //HWREGH(USB_BASE + MUSB_TXIE_OFFSET) &= ~(1 << ep_idx); + urb->errorcode = 0; + musb_urb_waitup(urb); + } else { + musb_write_packet(bus, ep_idx, urb->transfer_buffer, size); + HWREGB(USB_BASE + MUSB_IND_TXCSRL_OFFSET) = USB_TXCSRL1_TXRDY; + } + } + } + } + + rxis &= HWREGH(USB_BASE + MUSB_RXIE_OFFSET); + for (ep_idx = 1; ep_idx < CONIFG_USB_MUSB_PIPE_NUM; ep_idx++) { + if (rxis & (1 << ep_idx)) { + HWREGH(USB_BASE + MUSB_RXIS_OFFSET) = (1 << ep_idx); // clear isr flag + + pipe = &g_musb_hcd[bus->hcd.hcd_id].pipe_pool[ep_idx]; + urb = pipe->urb; + musb_set_active_ep(bus, ep_idx); + + ep_csrl_status = HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET); + //ep_csrh_status = HWREGB(USB_BASE + MUSB_IND_RXCSRH_OFFSET); // todo:for iso transfer + + if (ep_csrl_status & USB_RXCSRL1_ERROR) { + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_ERROR; + urb->errorcode = -USB_ERR_IO; + musb_urb_waitup(urb); + } else if (ep_csrl_status & USB_RXCSRL1_NAKTO) { + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_NAKTO; + urb->errorcode = -USB_ERR_NAK; + musb_urb_waitup(urb); + } else if (ep_csrl_status & USB_RXCSRL1_STALL) { + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_STALL; + urb->errorcode = -USB_ERR_STALL; + musb_urb_waitup(urb); + } else if (ep_csrl_status & USB_RXCSRL1_RXRDY) { + uint32_t size = urb->transfer_buffer_length; + if (size > USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) { + size = USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize); + } + size = MIN(size, HWREGH(USB_BASE + MUSB_IND_RXCOUNT_OFFSET)); + + musb_read_packet(bus, ep_idx, urb->transfer_buffer, size); + + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) &= ~USB_RXCSRL1_RXRDY; + + urb->transfer_buffer += size; + urb->transfer_buffer_length -= size; + urb->actual_length += size; + + if ((size < USB_GET_MAXPACKETSIZE(urb->ep->wMaxPacketSize)) || (urb->transfer_buffer_length == 0)) { + //HWREGH(USB_BASE + MUSB_RXIE_OFFSET) &= ~(1 << ep_idx); + urb->errorcode = 0; + musb_urb_waitup(urb); + } else { + HWREGB(USB_BASE + MUSB_IND_RXCSRL_OFFSET) = USB_RXCSRL1_REQPKT; + } + } + } + } + musb_set_active_ep(bus, old_ep_idx); +} diff --git a/components/drivers/usb/cherryusb/port/musb/usb_musb_reg.h b/components/drivers/usb/cherryusb/port/musb/usb_musb_reg.h new file mode 100644 index 00000000000..99d2cdfb618 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/musb/usb_musb_reg.h @@ -0,0 +1,3871 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef __USB_MUSB_REG_H__ +#define __USB_MUSB_REG_H__ + +#define __I volatile const /* defines 'read only' permissions */ +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/** + * @brief Register map for USB0 peripheral (USB0) + */ +#ifdef CONFIG_USB_MUSB_SUNXI +#if 0 +typedef __PACKED_STRUCT { /*!< USB0 Structure */ + union { + __IO uint8_t FIFO0_BYTE; /*!< USB FIFO Endpoint 0 */ + __IO uint16_t FIFO0_HALF; /*!< USB FIFO Endpoint 0 */ + __IO uint32_t FIFO0_WORD; /*!< USB FIFO Endpoint 0 */ + } FIFO0; + union { + __IO uint8_t FIFO1_BYTE; /*!< USB FIFO Endpoint 1 */ + __IO uint16_t FIFO1_HALF; /*!< USB FIFO Endpoint 1 */ + __IO uint32_t FIFO1_WORD; /*!< USB FIFO Endpoint 1 */ + } FIFO1; + union { + __IO uint8_t FIFO2_BYTE; /*!< USB FIFO Endpoint 2 */ + __IO uint16_t FIFO2_HALF; /*!< USB FIFO Endpoint 2 */ + __IO uint32_t FIFO2_WORD; /*!< USB FIFO Endpoint 2 */ + } FIFO2; + union { + __IO uint8_t FIFO3_BYTE; /*!< USB FIFO Endpoint 3 */ + __IO uint16_t FIFO3_HALF; /*!< USB FIFO Endpoint 3 */ + __IO uint32_t FIFO3_WORD; /*!< USB FIFO Endpoint 3 */ + } FIFO3; + union { + __IO uint8_t FIFO4_BYTE; /*!< USB FIFO Endpoint 4 */ + __IO uint16_t FIFO4_HALF; /*!< USB FIFO Endpoint 4 */ + __IO uint32_t FIFO4_WORD; /*!< USB FIFO Endpoint 4 */ + } FIFO4; + union { + __IO uint8_t FIFO5_BYTE; /*!< USB FIFO Endpoint 5 */ + __IO uint16_t FIFO5_HALF; /*!< USB FIFO Endpoint 5 */ + __IO uint32_t FIFO5_WORD; /*!< USB FIFO Endpoint 5 */ + } FIFO5; + union { + __IO uint8_t FIFO6_BYTE; /*!< USB FIFO Endpoint 6 */ + __IO uint16_t FIFO6_HALF; /*!< USB FIFO Endpoint 6 */ + __IO uint32_t FIFO6_WORD; /*!< USB FIFO Endpoint 6 */ + } FIFO6; + union { + __IO uint8_t FIFO7_BYTE; /*!< USB FIFO Endpoint 7 */ + __IO uint16_t FIFO7_HALF; /*!< USB FIFO Endpoint 7 */ + __IO uint32_t FIFO7_WORD; /*!< USB FIFO Endpoint 7 */ + } FIFO7; + union { + __IO uint8_t FIFO_BYTE; /*!< USB FIFO Endpoint 7 */ + __IO uint16_t FIFO_HALF; /*!< USB FIFO Endpoint 7 */ + __IO uint32_t FIFO_WORD; /*!< USB FIFO Endpoint 7 */ + } FIFO_RESERVED[8]; + + // 0x40 + __IO uint8_t POWER; /*!< USB Power */ + __IO uint8_t DEVCTL; /*!< USB Device Control */ + __IO uint8_t EPIDX; /*!< USB Endpoint Index */ + __IO uint8_t VEND0; +// 0x44 + __IO uint16_t TXIS; /*!< USB Transmit Interrupt Status */ + __IO uint16_t RXIS; /*!< USB Receive Interrupt Status */ + // 0x48 + __IO uint16_t TXIE; /*!< USB Transmit Interrupt Enable */ + __IO uint16_t RXIE; /*!< USB Receive Interrupt Enable */ +// 0x4c + __IO uint8_t IS; /*!< USB General Interrupt Status */ + __I uint8_t IS_RESERVED[3]; + + __IO uint8_t IE; /*!< USB Interrupt Enable */ + __I uint8_t IE_RESERVED[3]; + + __IO uint16_t FRAME; /*!< USB Frame Value */ + __I uint8_t FRAME_RESERVED[34]; + + __IO uint8_t EPINFO; /*!< USB Endpoint Information */ + __IO uint8_t RAMINFO; /*!< USB RAM Information */ + __IO uint8_t LINKINFO; + __IO uint8_t VPLEN; /*!< USB OTG VBUS Pulse Timing */ +// 0x7c + __IO uint8_t HSEOF; /*!< USB High-Speed Last Transaction to End of Frame Timing */ + __IO uint8_t FSEOF; /*!< USB Full-Speed Last Transaction to End of Frame Timing */ + __IO uint8_t LSEOF; /*!< USB Low-Speed Last Transaction to End of Frame Timing */ + __I uint8_t RESERVED7F; + +// 0x80 + __IO uint16_t TXMAXP1; /*!< USB Maximum Transmit Data Endpoint 1 */ + __PACKED_UNION + { + __IO uint8_t CSRL0; + __IO uint8_t TXCSRL1; /*!< USB Transmit Control and Status Endpoint 1 Low */ + } ; + + __PACKED_UNION + { + __O uint8_t CSRH0; /*!< USB Control and Status Endpoint 0 High */ + __IO uint8_t TXCSRH1; /*!< USB Transmit Control and Status Endpoint 1 High */ + } ; +// 0x84 + __IO uint16_t RXMAXP1; /*!< USB Maximum Receive Data Endpoint 1 */ + __IO uint8_t RXCSRL1; /*!< USB Receive Control and Status Endpoint 1 Low */ + __IO uint8_t RXCSRH1; /*!< USB Receive Control and Status Endpoint 1 High */ + + __PACKED_UNION + { + __IO uint16_t COUNT0; + __IO uint16_t RXCOUNT1; /*!< USB Receive Byte Count Endpoint 1 */ + } ; + // 0x8A + __IO uint8_t TYPE0; /*!< USB Type Endpoint 0 */ + __IO uint8_t NAKLMT; /*!< USB NAK Limit */ + // 0x8C + __IO uint8_t TXTYPE1; /*!< USB Host Transmit Configure Type Endpoint 1 */ + __IO uint8_t TXINTERVAL1; /*!< USB Host Transmit Interval Endpoint 1 */ + __IO uint8_t RXTYPE1; /*!< USB Host Configure Receive Type Endpoint 1 */ + __IO uint8_t RXINTERVAL1; /*!< USB Host Receive Polling Interval Endpoint 1 */ +// 0x90 + __IO uint8_t TXFIFOSZ; /*!< USB Transmit Dynamic FIFO Sizing */ + __I uint8_t RESERVED91; + __IO uint16_t TXFIFOADD; /*!< USB Transmit FIFO Start Address */ +// 0x94 + __IO uint8_t RXFIFOSZ; /*!< USB Receive Dynamic FIFO Sizing */ + __I uint8_t RESERVED95; + __IO uint16_t RXFIFOADD; /*!< USB Receive FIFO Start Address */ + +/* "bus control"/target registers, for host side multipoint (external hubs) */ +// 0x98 + __PACKED_UNION + { + __IO uint8_t FADDR; + __IO uint8_t TXFUNCADDR0; + }; + + __I uint8_t RESERVERD99; +// 0x9A + __IO uint8_t TXHUBADDR0; + __IO uint8_t TXHUBPORT0; +// 0x9c + __IO uint8_t RXFUNCADDR0; + __I uint8_t RESERVED9d; + __IO uint8_t RXHUBADDR0; + __IO uint8_t RXHUBPORT0; +} USB0_Type; +#endif +#else +#if 0 +typedef struct { /*!< USB0 Structure */ + __IO uint8_t FADDR; /*!< USB Device Functional Address */ + __IO uint8_t POWER; /*!< USB Power */ + __IO uint16_t TXIS; /*!< USB Transmit Interrupt Status */ + __IO uint16_t RXIS; /*!< USB Receive Interrupt Status */ + __IO uint16_t TXIE; /*!< USB Transmit Interrupt Enable */ + __IO uint16_t RXIE; /*!< USB Receive Interrupt Enable */ + __IO uint8_t IS; /*!< USB General Interrupt Status */ + __IO uint8_t IE; /*!< USB Interrupt Enable */ + __IO uint16_t FRAME; /*!< USB Frame Value */ + __IO uint8_t EPIDX; /*!< USB Endpoint Index */ + __IO uint8_t TEST; /*!< USB Test Mode */ + __I uint32_t RESERVED0[4]; + union { + __IO uint8_t FIFO0_BYTE; /*!< USB FIFO Endpoint 0 */ + __IO uint16_t FIFO0_HALF; /*!< USB FIFO Endpoint 0 */ + __IO uint32_t FIFO0_WORD; /*!< USB FIFO Endpoint 0 */ + } FIFO0; + union { + __IO uint8_t FIFO1_BYTE; /*!< USB FIFO Endpoint 1 */ + __IO uint16_t FIFO1_HALF; /*!< USB FIFO Endpoint 1 */ + __IO uint32_t FIFO1_WORD; /*!< USB FIFO Endpoint 1 */ + } FIFO1; + union { + __IO uint8_t FIFO2_BYTE; /*!< USB FIFO Endpoint 2 */ + __IO uint16_t FIFO2_HALF; /*!< USB FIFO Endpoint 2 */ + __IO uint32_t FIFO2_WORD; /*!< USB FIFO Endpoint 2 */ + } FIFO2; + union { + __IO uint8_t FIFO3_BYTE; /*!< USB FIFO Endpoint 3 */ + __IO uint16_t FIFO3_HALF; /*!< USB FIFO Endpoint 3 */ + __IO uint32_t FIFO3_WORD; /*!< USB FIFO Endpoint 3 */ + } FIFO3; + union { + __IO uint8_t FIFO4_BYTE; /*!< USB FIFO Endpoint 4 */ + __IO uint16_t FIFO4_HALF; /*!< USB FIFO Endpoint 4 */ + __IO uint32_t FIFO4_WORD; /*!< USB FIFO Endpoint 4 */ + } FIFO4; + union { + __IO uint8_t FIFO5_BYTE; /*!< USB FIFO Endpoint 5 */ + __IO uint16_t FIFO5_HALF; /*!< USB FIFO Endpoint 5 */ + __IO uint32_t FIFO5_WORD; /*!< USB FIFO Endpoint 5 */ + } FIFO5; + union { + __IO uint8_t FIFO6_BYTE; /*!< USB FIFO Endpoint 6 */ + __IO uint16_t FIFO6_HALF; /*!< USB FIFO Endpoint 6 */ + __IO uint32_t FIFO6_WORD; /*!< USB FIFO Endpoint 6 */ + } FIFO6; + union { + __IO uint8_t FIFO7_BYTE; /*!< USB FIFO Endpoint 7 */ + __IO uint16_t FIFO7_HALF; /*!< USB FIFO Endpoint 7 */ + __IO uint32_t FIFO7_WORD; /*!< USB FIFO Endpoint 7 */ + } FIFO7; + __I uint32_t RESERVED1[8]; + __IO uint8_t DEVCTL; /*!< USB Device Control */ + __IO uint8_t CCONF; /*!< USB Common Configuration */ + __IO uint8_t TXFIFOSZ; /*!< USB Transmit Dynamic FIFO Sizing */ + __IO uint8_t RXFIFOSZ; /*!< USB Receive Dynamic FIFO Sizing */ + __IO uint16_t TXFIFOADD; /*!< USB Transmit FIFO Start Address */ + __IO uint16_t RXFIFOADD; /*!< USB Receive FIFO Start Address */ + __I uint32_t RESERVED2[2]; + __IO uint8_t ULPIVBUSCTL; /*!< USB ULPI VBUS Control */ + __I uint8_t RESERVED3[3]; + __IO uint8_t ULPIREGDATA; /*!< USB ULPI Register Data */ + __IO uint8_t ULPIREGADDR; /*!< USB ULPI Register Address */ + __IO uint8_t ULPIREGCTL; /*!< USB ULPI Register Control */ + __I uint8_t RESERVED4; + __IO uint8_t EPINFO; /*!< USB Endpoint Information */ + __IO uint8_t RAMINFO; /*!< USB RAM Information */ + __IO uint8_t CONTIM; /*!< USB Connect Timing */ + __IO uint8_t VPLEN; /*!< USB OTG VBUS Pulse Timing */ + __IO uint8_t HSEOF; /*!< USB High-Speed Last Transaction to End of Frame Timing */ + __IO uint8_t FSEOF; /*!< USB Full-Speed Last Transaction to End of Frame Timing */ + __IO uint8_t LSEOF; /*!< USB Low-Speed Last Transaction to End of Frame Timing */ + __I uint8_t RESERVED5; + __IO uint8_t TXFUNCADDR0; /*!< USB Transmit Functional Address Endpoint 0 */ + __I uint8_t RESERVED6; + __IO uint8_t TXHUBADDR0; /*!< USB Transmit Hub Address Endpoint 0 */ + __IO uint8_t TXHUBPORT0; /*!< USB Transmit Hub Port Endpoint 0 */ + __I uint32_t RESERVED7; + __IO uint8_t TXFUNCADDR1; /*!< USB Transmit Functional Address Endpoint 1 */ + __I uint8_t RESERVED8; + __IO uint8_t TXHUBADDR1; /*!< USB Transmit Hub Address Endpoint 1 */ + __IO uint8_t TXHUBPORT1; /*!< USB Transmit Hub Port Endpoint 1 */ + __IO uint8_t RXFUNCADDR1; /*!< USB Receive Functional Address Endpoint 1 */ + __I uint8_t RESERVED9; + __IO uint8_t RXHUBADDR1; /*!< USB Receive Hub Address Endpoint 1 */ + __IO uint8_t RXHUBPORT1; /*!< USB Receive Hub Port Endpoint 1 */ + __IO uint8_t TXFUNCADDR2; /*!< USB Transmit Functional Address Endpoint 2 */ + __I uint8_t RESERVED10; + __IO uint8_t TXHUBADDR2; /*!< USB Transmit Hub Address Endpoint 2 */ + __IO uint8_t TXHUBPORT2; /*!< USB Transmit Hub Port Endpoint 2 */ + __IO uint8_t RXFUNCADDR2; /*!< USB Receive Functional Address Endpoint 2 */ + __I uint8_t RESERVED11; + __IO uint8_t RXHUBADDR2; /*!< USB Receive Hub Address Endpoint 2 */ + __IO uint8_t RXHUBPORT2; /*!< USB Receive Hub Port Endpoint 2 */ + __IO uint8_t TXFUNCADDR3; /*!< USB Transmit Functional Address Endpoint 3 */ + __I uint8_t RESERVED12; + __IO uint8_t TXHUBADDR3; /*!< USB Transmit Hub Address Endpoint 3 */ + __IO uint8_t TXHUBPORT3; /*!< USB Transmit Hub Port Endpoint 3 */ + __IO uint8_t RXFUNCADDR3; /*!< USB Receive Functional Address Endpoint 3 */ + __I uint8_t RESERVED13; + __IO uint8_t RXHUBADDR3; /*!< USB Receive Hub Address Endpoint 3 */ + __IO uint8_t RXHUBPORT3; /*!< USB Receive Hub Port Endpoint 3 */ + __IO uint8_t TXFUNCADDR4; /*!< USB Transmit Functional Address Endpoint 4 */ + __I uint8_t RESERVED14; + __IO uint8_t TXHUBADDR4; /*!< USB Transmit Hub Address Endpoint 4 */ + __IO uint8_t TXHUBPORT4; /*!< USB Transmit Hub Port Endpoint 4 */ + __IO uint8_t RXFUNCADDR4; /*!< USB Receive Functional Address Endpoint 4 */ + __I uint8_t RESERVED15; + __IO uint8_t RXHUBADDR4; /*!< USB Receive Hub Address Endpoint 4 */ + __IO uint8_t RXHUBPORT4; /*!< USB Receive Hub Port Endpoint 4 */ + __IO uint8_t TXFUNCADDR5; /*!< USB Transmit Functional Address Endpoint 5 */ + __I uint8_t RESERVED16; + __IO uint8_t TXHUBADDR5; /*!< USB Transmit Hub Address Endpoint 5 */ + __IO uint8_t TXHUBPORT5; /*!< USB Transmit Hub Port Endpoint 5 */ + __IO uint8_t RXFUNCADDR5; /*!< USB Receive Functional Address Endpoint 5 */ + __I uint8_t RESERVED17; + __IO uint8_t RXHUBADDR5; /*!< USB Receive Hub Address Endpoint 5 */ + __IO uint8_t RXHUBPORT5; /*!< USB Receive Hub Port Endpoint 5 */ + __IO uint8_t TXFUNCADDR6; /*!< USB Transmit Functional Address Endpoint 6 */ + __I uint8_t RESERVED18; + __IO uint8_t TXHUBADDR6; /*!< USB Transmit Hub Address Endpoint 6 */ + __IO uint8_t TXHUBPORT6; /*!< USB Transmit Hub Port Endpoint 6 */ + __IO uint8_t RXFUNCADDR6; /*!< USB Receive Functional Address Endpoint 6 */ + __I uint8_t RESERVED19; + __IO uint8_t RXHUBADDR6; /*!< USB Receive Hub Address Endpoint 6 */ + __IO uint8_t RXHUBPORT6; /*!< USB Receive Hub Port Endpoint 6 */ + __IO uint8_t TXFUNCADDR7; /*!< USB Transmit Functional Address Endpoint 7 */ + __I uint8_t RESERVED20; + __IO uint8_t TXHUBADDR7; /*!< USB Transmit Hub Address Endpoint 7 */ + __IO uint8_t TXHUBPORT7; /*!< USB Transmit Hub Port Endpoint 7 */ + __IO uint8_t RXFUNCADDR7; /*!< USB Receive Functional Address Endpoint 7 */ + __I uint8_t RESERVED21; + __IO uint8_t RXHUBADDR7; /*!< USB Receive Hub Address Endpoint 7 */ + __IO uint8_t RXHUBPORT7; /*!< USB Receive Hub Port Endpoint 7 */ + __I uint32_t RESERVED22[16]; + __I uint16_t RESERVED23; + __O uint8_t CSRL0; /*!< USB Control and Status Endpoint 0 Low */ + __O uint8_t CSRH0; /*!< USB Control and Status Endpoint 0 High */ + __I uint16_t RESERVED24[2]; + __IO uint8_t COUNT0; /*!< USB Receive Byte Count Endpoint 0 */ + __I uint8_t RESERVED25; + __IO uint8_t TYPE0; /*!< USB Type Endpoint 0 */ + __IO uint8_t NAKLMT; /*!< USB NAK Limit */ + __I uint32_t RESERVED26; + __IO uint16_t TXMAXP1; /*!< USB Maximum Transmit Data Endpoint 1 */ + __IO uint8_t TXCSRL1; /*!< USB Transmit Control and Status Endpoint 1 Low */ + __IO uint8_t TXCSRH1; /*!< USB Transmit Control and Status Endpoint 1 High */ + __IO uint16_t RXMAXP1; /*!< USB Maximum Receive Data Endpoint 1 */ + __IO uint8_t RXCSRL1; /*!< USB Receive Control and Status Endpoint 1 Low */ + __IO uint8_t RXCSRH1; /*!< USB Receive Control and Status Endpoint 1 High */ + __IO uint16_t RXCOUNT1; /*!< USB Receive Byte Count Endpoint 1 */ + __IO uint8_t TXTYPE1; /*!< USB Host Transmit Configure Type Endpoint 1 */ + __IO uint8_t TXINTERVAL1; /*!< USB Host Transmit Interval Endpoint 1 */ + __IO uint8_t RXTYPE1; /*!< USB Host Configure Receive Type Endpoint 1 */ + __IO uint8_t RXINTERVAL1; /*!< USB Host Receive Polling Interval Endpoint 1 */ + __I uint16_t RESERVED27; + __IO uint16_t TXMAXP2; /*!< USB Maximum Transmit Data Endpoint 2 */ + __IO uint8_t TXCSRL2; /*!< USB Transmit Control and Status Endpoint 2 Low */ + __IO uint8_t TXCSRH2; /*!< USB Transmit Control and Status Endpoint 2 High */ + __IO uint16_t RXMAXP2; /*!< USB Maximum Receive Data Endpoint 2 */ + __IO uint8_t RXCSRL2; /*!< USB Receive Control and Status Endpoint 2 Low */ + __IO uint8_t RXCSRH2; /*!< USB Receive Control and Status Endpoint 2 High */ + __IO uint16_t RXCOUNT2; /*!< USB Receive Byte Count Endpoint 2 */ + __IO uint8_t TXTYPE2; /*!< USB Host Transmit Configure Type Endpoint 2 */ + __IO uint8_t TXINTERVAL2; /*!< USB Host Transmit Interval Endpoint 2 */ + __IO uint8_t RXTYPE2; /*!< USB Host Configure Receive Type Endpoint 2 */ + __IO uint8_t RXINTERVAL2; /*!< USB Host Receive Polling Interval Endpoint 2 */ + __I uint16_t RESERVED28; + __IO uint16_t TXMAXP3; /*!< USB Maximum Transmit Data Endpoint 3 */ + __IO uint8_t TXCSRL3; /*!< USB Transmit Control and Status Endpoint 3 Low */ + __IO uint8_t TXCSRH3; /*!< USB Transmit Control and Status Endpoint 3 High */ + __IO uint16_t RXMAXP3; /*!< USB Maximum Receive Data Endpoint 3 */ + __IO uint8_t RXCSRL3; /*!< USB Receive Control and Status Endpoint 3 Low */ + __IO uint8_t RXCSRH3; /*!< USB Receive Control and Status Endpoint 3 High */ + __IO uint16_t RXCOUNT3; /*!< USB Receive Byte Count Endpoint 3 */ + __IO uint8_t TXTYPE3; /*!< USB Host Transmit Configure Type Endpoint 3 */ + __IO uint8_t TXINTERVAL3; /*!< USB Host Transmit Interval Endpoint 3 */ + __IO uint8_t RXTYPE3; /*!< USB Host Configure Receive Type Endpoint 3 */ + __IO uint8_t RXINTERVAL3; /*!< USB Host Receive Polling Interval Endpoint 3 */ + __I uint16_t RESERVED29; + __IO uint16_t TXMAXP4; /*!< USB Maximum Transmit Data Endpoint 4 */ + __IO uint8_t TXCSRL4; /*!< USB Transmit Control and Status Endpoint 4 Low */ + __IO uint8_t TXCSRH4; /*!< USB Transmit Control and Status Endpoint 4 High */ + __IO uint16_t RXMAXP4; /*!< USB Maximum Receive Data Endpoint 4 */ + __IO uint8_t RXCSRL4; /*!< USB Receive Control and Status Endpoint 4 Low */ + __IO uint8_t RXCSRH4; /*!< USB Receive Control and Status Endpoint 4 High */ + __IO uint16_t RXCOUNT4; /*!< USB Receive Byte Count Endpoint 4 */ + __IO uint8_t TXTYPE4; /*!< USB Host Transmit Configure Type Endpoint 4 */ + __IO uint8_t TXINTERVAL4; /*!< USB Host Transmit Interval Endpoint 4 */ + __IO uint8_t RXTYPE4; /*!< USB Host Configure Receive Type Endpoint 4 */ + __IO uint8_t RXINTERVAL4; /*!< USB Host Receive Polling Interval Endpoint 4 */ + __I uint16_t RESERVED30; + __IO uint16_t TXMAXP5; /*!< USB Maximum Transmit Data Endpoint 5 */ + __IO uint8_t TXCSRL5; /*!< USB Transmit Control and Status Endpoint 5 Low */ + __IO uint8_t TXCSRH5; /*!< USB Transmit Control and Status Endpoint 5 High */ + __IO uint16_t RXMAXP5; /*!< USB Maximum Receive Data Endpoint 5 */ + __IO uint8_t RXCSRL5; /*!< USB Receive Control and Status Endpoint 5 Low */ + __IO uint8_t RXCSRH5; /*!< USB Receive Control and Status Endpoint 5 High */ + __IO uint16_t RXCOUNT5; /*!< USB Receive Byte Count Endpoint 5 */ + __IO uint8_t TXTYPE5; /*!< USB Host Transmit Configure Type Endpoint 5 */ + __IO uint8_t TXINTERVAL5; /*!< USB Host Transmit Interval Endpoint 5 */ + __IO uint8_t RXTYPE5; /*!< USB Host Configure Receive Type Endpoint 5 */ + __IO uint8_t RXINTERVAL5; /*!< USB Host Receive Polling Interval Endpoint 5 */ + __I uint16_t RESERVED31; + __IO uint16_t TXMAXP6; /*!< USB Maximum Transmit Data Endpoint 6 */ + __IO uint8_t TXCSRL6; /*!< USB Transmit Control and Status Endpoint 6 Low */ + __IO uint8_t TXCSRH6; /*!< USB Transmit Control and Status Endpoint 6 High */ + __IO uint16_t RXMAXP6; /*!< USB Maximum Receive Data Endpoint 6 */ + __IO uint8_t RXCSRL6; /*!< USB Receive Control and Status Endpoint 6 Low */ + __IO uint8_t RXCSRH6; /*!< USB Receive Control and Status Endpoint 6 High */ + __IO uint16_t RXCOUNT6; /*!< USB Receive Byte Count Endpoint 6 */ + __IO uint8_t TXTYPE6; /*!< USB Host Transmit Configure Type Endpoint 6 */ + __IO uint8_t TXINTERVAL6; /*!< USB Host Transmit Interval Endpoint 6 */ + __IO uint8_t RXTYPE6; /*!< USB Host Configure Receive Type Endpoint 6 */ + __IO uint8_t RXINTERVAL6; /*!< USB Host Receive Polling Interval Endpoint 6 */ + __I uint16_t RESERVED32; + __IO uint16_t TXMAXP7; /*!< USB Maximum Transmit Data Endpoint 7 */ + __IO uint8_t TXCSRL7; /*!< USB Transmit Control and Status Endpoint 7 Low */ + __IO uint8_t TXCSRH7; /*!< USB Transmit Control and Status Endpoint 7 High */ + __IO uint16_t RXMAXP7; /*!< USB Maximum Receive Data Endpoint 7 */ + __IO uint8_t RXCSRL7; /*!< USB Receive Control and Status Endpoint 7 Low */ + __IO uint8_t RXCSRH7; /*!< USB Receive Control and Status Endpoint 7 High */ + __IO uint16_t RXCOUNT7; /*!< USB Receive Byte Count Endpoint 7 */ + __IO uint8_t TXTYPE7; /*!< USB Host Transmit Configure Type Endpoint 7 */ + __IO uint8_t TXINTERVAL7; /*!< USB Host Transmit Interval Endpoint 7 */ + __IO uint8_t RXTYPE7; /*!< USB Host Configure Receive Type Endpoint 7 */ + __IO uint8_t RXINTERVAL7; /*!< USB Host Receive Polling Interval Endpoint 7 */ + __I uint16_t RESERVED33[65]; + __IO uint8_t DMAINTR; /*!< USB DMA Interrupt */ + __I uint8_t RESERVED34[3]; + __IO uint16_t DMACTL0; /*!< USB DMA Control 0 */ + __I uint16_t RESERVED35; + __IO uint32_t DMAADDR0; /*!< USB DMA Address 0 */ + __IO uint32_t DMACOUNT0; /*!< USB DMA Count 0 */ + __I uint32_t RESERVED36; + __IO uint16_t DMACTL1; /*!< USB DMA Control 1 */ + __I uint16_t RESERVED37; + __IO uint32_t DMAADDR1; /*!< USB DMA Address 1 */ + __IO uint32_t DMACOUNT1; /*!< USB DMA Count 1 */ + __I uint32_t RESERVED38; + __IO uint16_t DMACTL2; /*!< USB DMA Control 2 */ + __I uint16_t RESERVED39; + __IO uint32_t DMAADDR2; /*!< USB DMA Address 2 */ + __IO uint32_t DMACOUNT2; /*!< USB DMA Count 2 */ + __I uint32_t RESERVED40; + __IO uint16_t DMACTL3; /*!< USB DMA Control 3 */ + __I uint16_t RESERVED41; + __IO uint32_t DMAADDR3; /*!< USB DMA Address 3 */ + __IO uint32_t DMACOUNT3; /*!< USB DMA Count 3 */ + __I uint32_t RESERVED42; + __IO uint16_t DMACTL4; /*!< USB DMA Control 4 */ + __I uint16_t RESERVED43; + __IO uint32_t DMAADDR4; /*!< USB DMA Address 4 */ + __IO uint32_t DMACOUNT4; /*!< USB DMA Count 4 */ + __I uint32_t RESERVED44; + __IO uint16_t DMACTL5; /*!< USB DMA Control 5 */ + __I uint16_t RESERVED45; + __IO uint32_t DMAADDR5; /*!< USB DMA Address 5 */ + __IO uint32_t DMACOUNT5; /*!< USB DMA Count 5 */ + __I uint32_t RESERVED46; + __IO uint16_t DMACTL6; /*!< USB DMA Control 6 */ + __I uint16_t RESERVED47; + __IO uint32_t DMAADDR6; /*!< USB DMA Address 6 */ + __IO uint32_t DMACOUNT6; /*!< USB DMA Count 6 */ + __I uint32_t RESERVED48; + __IO uint16_t DMACTL7; /*!< USB DMA Control 7 */ + __I uint16_t RESERVED49; + __IO uint32_t DMAADDR7; /*!< USB DMA Address 7 */ + __IO uint32_t DMACOUNT7; /*!< USB DMA Count 7 */ + __I uint32_t RESERVED50[33]; + __IO uint16_t RQPKTCOUNT1; /*!< USB Request Packet Count in Block Transfer Endpoint 1 */ + __I uint16_t RESERVED51; + __IO uint16_t RQPKTCOUNT2; /*!< USB Request Packet Count in Block Transfer Endpoint 2 */ + __I uint16_t RESERVED52; + __IO uint16_t RQPKTCOUNT3; /*!< USB Request Packet Count in Block Transfer Endpoint 3 */ + __I uint16_t RESERVED53; + __IO uint16_t RQPKTCOUNT4; /*!< USB Request Packet Count in Block Transfer Endpoint 4 */ + __I uint16_t RESERVED54; + __IO uint16_t RQPKTCOUNT5; /*!< USB Request Packet Count in Block Transfer Endpoint 5 */ + __I uint16_t RESERVED55; + __IO uint16_t RQPKTCOUNT6; /*!< USB Request Packet Count in Block Transfer Endpoint 6 */ + __I uint16_t RESERVED56; + __IO uint16_t RQPKTCOUNT7; /*!< USB Request Packet Count in Block Transfer Endpoint 7 */ + __I uint16_t RESERVED57[17]; + __IO uint16_t RXDPKTBUFDIS; /*!< USB Receive Double Packet Buffer Disable */ + __IO uint16_t TXDPKTBUFDIS; /*!< USB Transmit Double Packet Buffer Disable */ + __IO uint16_t CTO; /*!< USB Chirp Timeout */ + __IO uint16_t HHSRTN; /*!< USB High Speed to UTM Operating Delay */ + __IO uint16_t HSBT; /*!< USB High Speed Time-out Adder */ + __I uint16_t RESERVED58[11]; + __IO uint16_t LPMATTR; /*!< USB LPM Attributes */ + __IO uint8_t LPMCNTRL; /*!< USB LPM Control */ + __IO uint8_t LPMIM; /*!< USB LPM Interrupt Mask */ + __IO uint8_t LPMRIS; /*!< USB LPM Raw Interrupt Status */ + __IO uint8_t LPMFADDR; /*!< USB LPM Function Address */ + __I uint16_t RESERVED59[77]; + __IO uint32_t EPC; /*!< USB External Power Control */ + __IO uint32_t EPCRIS; /*!< USB External Power Control Raw Interrupt Status */ + __IO uint32_t EPCIM; /*!< USB External Power Control Interrupt Mask */ + __IO uint32_t EPCISC; /*!< USB External Power Control Interrupt Status and Clear */ + __IO uint32_t DRRIS; /*!< USB Device RESUME Raw Interrupt Status */ + __IO uint32_t DRIM; /*!< USB Device RESUME Interrupt Mask */ + __O uint32_t DRISC; /*!< USB Device RESUME Interrupt Status and Clear */ + __IO uint32_t GPCS; /*!< USB General-Purpose Control and Status */ + __I uint32_t RESERVED60[4]; + __IO uint32_t VDC; /*!< USB VBUS Droop Control */ + __IO uint32_t VDCRIS; /*!< USB VBUS Droop Control Raw Interrupt Status */ + __IO uint32_t VDCIM; /*!< USB VBUS Droop Control Interrupt Mask */ + __IO uint32_t VDCISC; /*!< USB VBUS Droop Control Interrupt Status and Clear */ + __I uint32_t RESERVED61[736]; + __IO uint32_t PP; /*!< USB Peripheral Properties */ + __IO uint32_t PC; /*!< USB Peripheral Configuration */ + __IO uint32_t CC; /*!< USB Clock Configuration */ +} USB0_Type; +#endif +#endif // CONFIG_USB_MUSB_SUNXI + +//***************************************************************************** +// +// The following are defines for the Univeral Serial Bus register offsets. +// +//***************************************************************************** +#define USB_O_FADDR 0x00000000 // USB Device Functional Address +#define USB_O_POWER 0x00000001 // USB Power +#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status +#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status +#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable +#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable +#define USB_O_IS 0x0000000A // USB General Interrupt Status +#define USB_O_IE 0x0000000B // USB Interrupt Enable +#define USB_O_FRAME 0x0000000C // USB Frame Value +#define USB_O_EPIDX 0x0000000E // USB Endpoint Index +#define USB_O_TEST 0x0000000F // USB Test Mode +#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0 +#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1 +#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2 +#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3 +#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4 +#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5 +#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6 +#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7 +#define USB_O_DEVCTL 0x00000060 // USB Device Control +#define USB_O_CCONF 0x00000061 // USB Common Configuration +#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing +#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing +#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address +#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address +#define USB_O_ULPIVBUSCTL 0x00000070 // USB ULPI VBUS Control +#define USB_O_ULPIREGDATA 0x00000074 // USB ULPI Register Data +#define USB_O_ULPIREGADDR 0x00000075 // USB ULPI Register Address +#define USB_O_ULPIREGCTL 0x00000076 // USB ULPI Register Control +#define USB_O_EPINFO 0x00000078 // USB Endpoint Information +#define USB_O_RAMINFO 0x00000079 // USB RAM Information +#define USB_O_CONTIM 0x0000007A // USB Connect Timing +#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing +#define USB_O_HSEOF 0x0000007C // USB High-Speed Last Transaction + // to End of Frame Timing +#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction + // to End of Frame Timing +#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction + // to End of Frame Timing +#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address + // Endpoint 0 +#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address + // Endpoint 0 +#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0 +#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address + // Endpoint 1 +#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address + // Endpoint 1 +#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1 +#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address + // Endpoint 1 +#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint + // 1 +#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1 +#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address + // Endpoint 2 +#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address + // Endpoint 2 +#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2 +#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address + // Endpoint 2 +#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint + // 2 +#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2 +#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address + // Endpoint 3 +#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address + // Endpoint 3 +#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3 +#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address + // Endpoint 3 +#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint + // 3 +#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3 +#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address + // Endpoint 4 +#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address + // Endpoint 4 +#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4 +#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address + // Endpoint 4 +#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint + // 4 +#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4 +#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address + // Endpoint 5 +#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address + // Endpoint 5 +#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5 +#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address + // Endpoint 5 +#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint + // 5 +#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5 +#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address + // Endpoint 6 +#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address + // Endpoint 6 +#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6 +#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address + // Endpoint 6 +#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint + // 6 +#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6 +#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address + // Endpoint 7 +#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address + // Endpoint 7 +#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7 +#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address + // Endpoint 7 +#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint + // 7 +#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7 +#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint + // 0 Low +#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint + // 0 High +#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint + // 0 +#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0 +#define USB_O_NAKLMT 0x0000010B // USB NAK Limit +#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data + // Endpoint 1 +#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status + // Endpoint 1 Low +#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status + // Endpoint 1 High +#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data + // Endpoint 1 +#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status + // Endpoint 1 Low +#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status + // Endpoint 1 High +#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint + // 1 +#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type + // Endpoint 1 +#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval + // Endpoint 1 +#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type + // Endpoint 1 +#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling + // Interval Endpoint 1 +#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data + // Endpoint 2 +#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status + // Endpoint 2 Low +#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status + // Endpoint 2 High +#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data + // Endpoint 2 +#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status + // Endpoint 2 Low +#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status + // Endpoint 2 High +#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint + // 2 +#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type + // Endpoint 2 +#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval + // Endpoint 2 +#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type + // Endpoint 2 +#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling + // Interval Endpoint 2 +#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data + // Endpoint 3 +#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status + // Endpoint 3 Low +#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status + // Endpoint 3 High +#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data + // Endpoint 3 +#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status + // Endpoint 3 Low +#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status + // Endpoint 3 High +#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint + // 3 +#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type + // Endpoint 3 +#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval + // Endpoint 3 +#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type + // Endpoint 3 +#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling + // Interval Endpoint 3 +#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data + // Endpoint 4 +#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status + // Endpoint 4 Low +#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status + // Endpoint 4 High +#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data + // Endpoint 4 +#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status + // Endpoint 4 Low +#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status + // Endpoint 4 High +#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint + // 4 +#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type + // Endpoint 4 +#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval + // Endpoint 4 +#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type + // Endpoint 4 +#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling + // Interval Endpoint 4 +#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data + // Endpoint 5 +#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status + // Endpoint 5 Low +#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status + // Endpoint 5 High +#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data + // Endpoint 5 +#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status + // Endpoint 5 Low +#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status + // Endpoint 5 High +#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint + // 5 +#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type + // Endpoint 5 +#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval + // Endpoint 5 +#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type + // Endpoint 5 +#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling + // Interval Endpoint 5 +#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data + // Endpoint 6 +#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status + // Endpoint 6 Low +#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status + // Endpoint 6 High +#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data + // Endpoint 6 +#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status + // Endpoint 6 Low +#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status + // Endpoint 6 High +#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint + // 6 +#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type + // Endpoint 6 +#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval + // Endpoint 6 +#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type + // Endpoint 6 +#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling + // Interval Endpoint 6 +#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data + // Endpoint 7 +#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status + // Endpoint 7 Low +#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status + // Endpoint 7 High +#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data + // Endpoint 7 +#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status + // Endpoint 7 Low +#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status + // Endpoint 7 High +#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint + // 7 +#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type + // Endpoint 7 +#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval + // Endpoint 7 +#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type + // Endpoint 7 +#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling + // Interval Endpoint 7 +#define USB_O_DMAINTR 0x00000200 // USB DMA Interrupt +#define USB_O_DMACTL0 0x00000204 // USB DMA Control 0 +#define USB_O_DMAADDR0 0x00000208 // USB DMA Address 0 +#define USB_O_DMACOUNT0 0x0000020C // USB DMA Count 0 +#define USB_O_DMACTL1 0x00000214 // USB DMA Control 1 +#define USB_O_DMAADDR1 0x00000218 // USB DMA Address 1 +#define USB_O_DMACOUNT1 0x0000021C // USB DMA Count 1 +#define USB_O_DMACTL2 0x00000224 // USB DMA Control 2 +#define USB_O_DMAADDR2 0x00000228 // USB DMA Address 2 +#define USB_O_DMACOUNT2 0x0000022C // USB DMA Count 2 +#define USB_O_DMACTL3 0x00000234 // USB DMA Control 3 +#define USB_O_DMAADDR3 0x00000238 // USB DMA Address 3 +#define USB_O_DMACOUNT3 0x0000023C // USB DMA Count 3 +#define USB_O_DMACTL4 0x00000244 // USB DMA Control 4 +#define USB_O_DMAADDR4 0x00000248 // USB DMA Address 4 +#define USB_O_DMACOUNT4 0x0000024C // USB DMA Count 4 +#define USB_O_DMACTL5 0x00000254 // USB DMA Control 5 +#define USB_O_DMAADDR5 0x00000258 // USB DMA Address 5 +#define USB_O_DMACOUNT5 0x0000025C // USB DMA Count 5 +#define USB_O_DMACTL6 0x00000264 // USB DMA Control 6 +#define USB_O_DMAADDR6 0x00000268 // USB DMA Address 6 +#define USB_O_DMACOUNT6 0x0000026C // USB DMA Count 6 +#define USB_O_DMACTL7 0x00000274 // USB DMA Control 7 +#define USB_O_DMAADDR7 0x00000278 // USB DMA Address 7 +#define USB_O_DMACOUNT7 0x0000027C // USB DMA Count 7 +#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in + // Block Transfer Endpoint 1 +#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in + // Block Transfer Endpoint 2 +#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in + // Block Transfer Endpoint 3 +#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in + // Block Transfer Endpoint 4 +#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in + // Block Transfer Endpoint 5 +#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in + // Block Transfer Endpoint 6 +#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in + // Block Transfer Endpoint 7 +#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer + // Disable +#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet + // Buffer Disable +#define USB_O_CTO 0x00000344 // USB Chirp Timeout +#define USB_O_HHSRTN 0x00000346 // USB High Speed to UTM Operating + // Delay +#define USB_O_HSBT 0x00000348 // USB High Speed Time-out Adder +#define USB_O_LPMATTR 0x00000360 // USB LPM Attributes +#define USB_O_LPMCNTRL 0x00000362 // USB LPM Control +#define USB_O_LPMIM 0x00000363 // USB LPM Interrupt Mask +#define USB_O_LPMRIS 0x00000364 // USB LPM Raw Interrupt Status +#define USB_O_LPMFADDR 0x00000365 // USB LPM Function Address +#define USB_O_EPC 0x00000400 // USB External Power Control +#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw + // Interrupt Status +#define USB_O_EPCIM 0x00000408 // USB External Power Control + // Interrupt Mask +#define USB_O_EPCISC 0x0000040C // USB External Power Control + // Interrupt Status and Clear +#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt + // Status +#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask +#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt + // Status and Clear +#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and + // Status +#define USB_O_VDC 0x00000430 // USB VBUS Droop Control +#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw + // Interrupt Status +#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt + // Mask +#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt + // Status and Clear +#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw + // Interrupt Status +#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt + // Mask +#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt + // Status and Clear +#define USB_O_PP 0x00000FC0 // USB Peripheral Properties +#define USB_O_PC 0x00000FC4 // USB Peripheral Configuration +#define USB_O_CC 0x00000FC8 // USB Clock Configuration + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FADDR register. +// +//***************************************************************************** +#define USB_FADDR_M 0x0000007F // Function Address +#define USB_FADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_POWER register. +// +//***************************************************************************** +#define USB_POWER_ISOUP 0x00000080 // Isochronous Update +#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect +#define USB_POWER_HSENAB 0x00000020 // High Speed Enable +#define USB_POWER_HSMODE 0x00000010 // High Speed Enable +#define USB_POWER_RESET 0x00000008 // RESET Signaling +#define USB_POWER_RESUME 0x00000004 // RESUME Signaling +#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode +#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIS register. +// +//***************************************************************************** +#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt +#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt +#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt +#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt +#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt +#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt +#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt +#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIS register. +// +//***************************************************************************** +#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt +#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt +#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt +#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt +#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt +#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt +#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXIE register. +// +//***************************************************************************** +#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable +#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable +#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable +#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable +#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable +#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable +#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable +#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt + // Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXIE register. +// +//***************************************************************************** +#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable +#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable +#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable +#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable +#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable +#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable +#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IS register. +// +//***************************************************************************** +#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only) +#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only) +#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only) +#define USB_IS_CONN 0x00000010 // Session Connect +#define USB_IS_SOF 0x00000008 // Start of Frame +#define USB_IS_BABBLE 0x00000004 // Babble Detected +#define USB_IS_RESET 0x00000004 // RESET Signaling Detected +#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected +#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IE register. +// +//***************************************************************************** +#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG + // only) +#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG + // only) +#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt +#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt +#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt +#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt +#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt +#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt +#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FRAME register. +// +//***************************************************************************** +#define USB_FRAME_M 0x000007FF // Frame Number +#define USB_FRAME_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPIDX register. +// +//***************************************************************************** +#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index +#define USB_EPIDX_EPIDX_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TEST register. +// +//***************************************************************************** +#define USB_TEST_FORCEH 0x00000080 // Force Host Mode +#define USB_TEST_FIFOACC 0x00000040 // FIFO Access +#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode +#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode +#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable +#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable +#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable +#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO0 register. +// +//***************************************************************************** +#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO0_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO1 register. +// +//***************************************************************************** +#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO1_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO2 register. +// +//***************************************************************************** +#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO2_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO3 register. +// +//***************************************************************************** +#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO3_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO4 register. +// +//***************************************************************************** +#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO4_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO5 register. +// +//***************************************************************************** +#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO5_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO6 register. +// +//***************************************************************************** +#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO6_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FIFO7 register. +// +//***************************************************************************** +#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data +#define USB_FIFO7_EPDATA_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DEVCTL register. +// +//***************************************************************************** +#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only) +#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected +#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected +#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only) +#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd +#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid +#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid +#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid +#define USB_DEVCTL_HOST 0x00000004 // Host Mode +#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only) +#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CCONF register. +// +//***************************************************************************** +#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable +#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOSZ register. +// +//***************************************************************************** +#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOSZ register. +// +//***************************************************************************** +#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support +#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size +#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8 +#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16 +#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32 +#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64 +#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128 +#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256 +#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512 +#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024 +#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFIFOADD +// register. +// +//***************************************************************************** +#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_TXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFIFOADD +// register. +// +//***************************************************************************** +#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address +#define USB_RXFIFOADD_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL +// register. +// +//***************************************************************************** +#define USB_ULPIVBUSCTL_USEEXTVBUSIND \ + 0x00000002 // Use External VBUS Indicator +#define USB_ULPIVBUSCTL_USEEXTVBUS \ + 0x00000001 // Use External VBUS + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGDATA +// register. +// +//***************************************************************************** +#define USB_ULPIREGDATA_REGDATA_M \ + 0x000000FF // Register Data +#define USB_ULPIREGDATA_REGDATA_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGADDR +// register. +// +//***************************************************************************** +#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address +#define USB_ULPIREGADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_ULPIREGCTL +// register. +// +//***************************************************************************** +#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control +#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete +#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPINFO register. +// +//***************************************************************************** +#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints +#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints +#define USB_EPINFO_RXEP_S 4 +#define USB_EPINFO_TXEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RAMINFO register. +// +//***************************************************************************** +#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels +#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width +#define USB_RAMINFO_DMACHAN_S 4 +#define USB_RAMINFO_RAMBITS_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CONTIM register. +// +//***************************************************************************** +#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait +#define USB_CONTIM_WTID_M 0x0000000F // Wait ID +#define USB_CONTIM_WTCON_S 4 +#define USB_CONTIM_WTID_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VPLEN register. +// +//***************************************************************************** +#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length +#define USB_VPLEN_VPLEN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSEOF register. +// +//***************************************************************************** +#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap +#define USB_HSEOF_HSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_FSEOF register. +// +//***************************************************************************** +#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap +#define USB_FSEOF_FSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LSEOF register. +// +//***************************************************************************** +#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap +#define USB_LSEOF_LSEOFG_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR0 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR0 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR0_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT0 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT0_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR1 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR1 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR1_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT1 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT1_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR2 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR2 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR2_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT2 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT2_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR3 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR3 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR3_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT3 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT3_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR4 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR4 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR4_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT4 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT4_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR5 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR5 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR5_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT5 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT5_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR6 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR6 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR6_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT6 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT6_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_TXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_TXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_TXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXFUNCADDR7 +// register. +// +//***************************************************************************** +#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address +#define USB_RXFUNCADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBADDR7 +// register. +// +//***************************************************************************** +#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address +#define USB_RXHUBADDR7_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXHUBPORT7 +// register. +// +//***************************************************************************** +#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port +#define USB_RXHUBPORT7_PORT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRL0 register. +// +//***************************************************************************** +#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout +#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear +#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet +#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear +#define USB_CSRL0_REQPKT 0x00000020 // Request Packet +#define USB_CSRL0_STALL 0x00000020 // Send Stall +#define USB_CSRL0_SETEND 0x00000010 // Setup End +#define USB_CSRL0_ERROR 0x00000010 // Error +#define USB_CSRL0_DATAEND 0x00000008 // Data End +#define USB_CSRL0_SETUP 0x00000008 // Setup Packet +#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled +#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready +#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CSRH0 register. +// +//***************************************************************************** +#define USB_CSRH0_DISPING 0x00000008 // PING Disable +#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_CSRH0_DT 0x00000002 // Data Toggle +#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_COUNT0 register. +// +//***************************************************************************** +#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count +#define USB_COUNT0_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TYPE0 register. +// +//***************************************************************************** +#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed +#define USB_TYPE0_SPEED_HIGH 0x00000040 // High +#define USB_TYPE0_SPEED_FULL 0x00000080 // Full +#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_NAKLMT register. +// +//***************************************************************************** +#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit +#define USB_NAKLMT_NAKLMT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP1 register. +// +//***************************************************************************** +#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL1 register. +// +//***************************************************************************** +#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL1_STALL 0x00000010 // Send STALL +#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL1_ERROR 0x00000004 // Error +#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH1 register. +// +//***************************************************************************** +#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH1_MODE 0x00000020 // Mode +#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH1_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP1 register. +// +//***************************************************************************** +#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP1_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL1 register. +// +//***************************************************************************** +#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL1_STALL 0x00000020 // Send STALL +#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL1_OVER 0x00000004 // Overrun +#define USB_RXCSRL1_ERROR 0x00000004 // Error +#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH1 register. +// +//***************************************************************************** +#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH1_DT 0x00000002 // Data Toggle +#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT1 register. +// +//***************************************************************************** +#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT1_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE1 register. +// +//***************************************************************************** +#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL1_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL1_TXPOLL_S \ + 0 +#define USB_TXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE1 register. +// +//***************************************************************************** +#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE1_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL1 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL1_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL1_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL1_TXPOLL_S \ + 0 +#define USB_RXINTERVAL1_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP2 register. +// +//***************************************************************************** +#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL2 register. +// +//***************************************************************************** +#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL2_STALL 0x00000010 // Send STALL +#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL2_ERROR 0x00000004 // Error +#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH2 register. +// +//***************************************************************************** +#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH2_MODE 0x00000020 // Mode +#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH2_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP2 register. +// +//***************************************************************************** +#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP2_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL2 register. +// +//***************************************************************************** +#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL2_STALL 0x00000020 // Send STALL +#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL2_ERROR 0x00000004 // Error +#define USB_RXCSRL2_OVER 0x00000004 // Overrun +#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH2 register. +// +//***************************************************************************** +#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH2_DT 0x00000002 // Data Toggle +#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT2 register. +// +//***************************************************************************** +#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT2_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE2 register. +// +//***************************************************************************** +#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL2_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL2_NAKLMT_S \ + 0 +#define USB_TXINTERVAL2_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE2 register. +// +//***************************************************************************** +#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE2_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL2 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL2_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL2_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL2_TXPOLL_S \ + 0 +#define USB_RXINTERVAL2_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP3 register. +// +//***************************************************************************** +#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL3 register. +// +//***************************************************************************** +#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL3_STALL 0x00000010 // Send STALL +#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL3_ERROR 0x00000004 // Error +#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH3 register. +// +//***************************************************************************** +#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH3_MODE 0x00000020 // Mode +#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH3_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP3 register. +// +//***************************************************************************** +#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP3_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL3 register. +// +//***************************************************************************** +#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL3_STALL 0x00000020 // Send STALL +#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL3_ERROR 0x00000004 // Error +#define USB_RXCSRL3_OVER 0x00000004 // Overrun +#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH3 register. +// +//***************************************************************************** +#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH3_DT 0x00000002 // Data Toggle +#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT3 register. +// +//***************************************************************************** +#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT3_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE3 register. +// +//***************************************************************************** +#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL3_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL3_TXPOLL_S \ + 0 +#define USB_TXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE3 register. +// +//***************************************************************************** +#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE3_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL3 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL3_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL3_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL3_TXPOLL_S \ + 0 +#define USB_RXINTERVAL3_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP4 register. +// +//***************************************************************************** +#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL4 register. +// +//***************************************************************************** +#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL4_STALL 0x00000010 // Send STALL +#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL4_ERROR 0x00000004 // Error +#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH4 register. +// +//***************************************************************************** +#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH4_MODE 0x00000020 // Mode +#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH4_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP4 register. +// +//***************************************************************************** +#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP4_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL4 register. +// +//***************************************************************************** +#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL4_STALL 0x00000020 // Send STALL +#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL4_OVER 0x00000004 // Overrun +#define USB_RXCSRL4_ERROR 0x00000004 // Error +#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH4 register. +// +//***************************************************************************** +#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH4_DT 0x00000002 // Data Toggle +#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT4 register. +// +//***************************************************************************** +#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE4 register. +// +//***************************************************************************** +#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL4_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL4_NAKLMT_S \ + 0 +#define USB_TXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE4 register. +// +//***************************************************************************** +#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE4_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL4 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL4_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL4_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL4_NAKLMT_S \ + 0 +#define USB_RXINTERVAL4_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP5 register. +// +//***************************************************************************** +#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL5 register. +// +//***************************************************************************** +#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL5_STALL 0x00000010 // Send STALL +#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL5_ERROR 0x00000004 // Error +#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH5 register. +// +//***************************************************************************** +#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH5_MODE 0x00000020 // Mode +#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH5_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP5 register. +// +//***************************************************************************** +#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP5_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL5 register. +// +//***************************************************************************** +#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL5_STALL 0x00000020 // Send STALL +#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL5_ERROR 0x00000004 // Error +#define USB_RXCSRL5_OVER 0x00000004 // Overrun +#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH5 register. +// +//***************************************************************************** +#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH5_DT 0x00000002 // Data Toggle +#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT5 register. +// +//***************************************************************************** +#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE5 register. +// +//***************************************************************************** +#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL5_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL5_NAKLMT_S \ + 0 +#define USB_TXINTERVAL5_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE5 register. +// +//***************************************************************************** +#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE5_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL5 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL5_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL5_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL5_TXPOLL_S \ + 0 +#define USB_RXINTERVAL5_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP6 register. +// +//***************************************************************************** +#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL6 register. +// +//***************************************************************************** +#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL6_STALL 0x00000010 // Send STALL +#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL6_ERROR 0x00000004 // Error +#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH6 register. +// +//***************************************************************************** +#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH6_MODE 0x00000020 // Mode +#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH6_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP6 register. +// +//***************************************************************************** +#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP6_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL6 register. +// +//***************************************************************************** +#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL6_STALL 0x00000020 // Send STALL +#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL6_ERROR 0x00000004 // Error +#define USB_RXCSRL6_OVER 0x00000004 // Overrun +#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH6 register. +// +//***************************************************************************** +#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH6_DT 0x00000002 // Data Toggle +#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT6 register. +// +//***************************************************************************** +#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE6 register. +// +//***************************************************************************** +#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL6_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL6_TXPOLL_S \ + 0 +#define USB_TXINTERVAL6_NAKLMT_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE6 register. +// +//***************************************************************************** +#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE6_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL6 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL6_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL6_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL6_NAKLMT_S \ + 0 +#define USB_RXINTERVAL6_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXMAXP7 register. +// +//***************************************************************************** +#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_TXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRL7 register. +// +//***************************************************************************** +#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout +#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle +#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled +#define USB_TXCSRL7_STALL 0x00000010 // Send STALL +#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet +#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO +#define USB_TXCSRL7_ERROR 0x00000004 // Error +#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun +#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty +#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXCSRH7 register. +// +//***************************************************************************** +#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set +#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_TXCSRH7_MODE 0x00000020 // Mode +#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable +#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle +#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode +#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable +#define USB_TXCSRH7_DT 0x00000001 // Data Toggle + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXMAXP7 register. +// +//***************************************************************************** +#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload +#define USB_RXMAXP7_MAXLOAD_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRL7 register. +// +//***************************************************************************** +#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle +#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled +#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet +#define USB_RXCSRL7_STALL 0x00000020 // Send STALL +#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO +#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error +#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout +#define USB_RXCSRL7_ERROR 0x00000004 // Error +#define USB_RXCSRL7_OVER 0x00000004 // Overrun +#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full +#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCSRH7 register. +// +//***************************************************************************** +#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear +#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers +#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request +#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable +#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error +#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET +#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode +#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable +#define USB_RXCSRH7_DT 0x00000002 // Data Toggle +#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXCOUNT7 register. +// +//***************************************************************************** +#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count +#define USB_RXCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXTYPE7 register. +// +//***************************************************************************** +#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_TXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_TXINTERVAL7_TXPOLL_M \ + 0x000000FF // TX Polling +#define USB_TXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_TXINTERVAL7_NAKLMT_S \ + 0 +#define USB_TXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXTYPE7 register. +// +//***************************************************************************** +#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed +#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default +#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High +#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full +#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low +#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol +#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control +#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous +#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk +#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt +#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number +#define USB_RXTYPE7_TEP_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXINTERVAL7 +// register. +// +//***************************************************************************** +#define USB_RXINTERVAL7_TXPOLL_M \ + 0x000000FF // RX Polling +#define USB_RXINTERVAL7_NAKLMT_M \ + 0x000000FF // NAK Limit +#define USB_RXINTERVAL7_NAKLMT_S \ + 0 +#define USB_RXINTERVAL7_TXPOLL_S \ + 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAINTR register. +// +//***************************************************************************** +#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt +#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt +#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt +#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt +#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt +#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt +#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt +#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL0 register. +// +//***************************************************************************** +#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL0_DIR 0x00000002 // DMA Direction +#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL0_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR0 register. +// +//***************************************************************************** +#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR0_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT0 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT0_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL1 register. +// +//***************************************************************************** +#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL1_DIR 0x00000002 // DMA Direction +#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL1_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR1 register. +// +//***************************************************************************** +#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR1_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT1 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT1_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL2 register. +// +//***************************************************************************** +#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL2_DIR 0x00000002 // DMA Direction +#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL2_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR2 register. +// +//***************************************************************************** +#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR2_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT2 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT2_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL3 register. +// +//***************************************************************************** +#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL3_DIR 0x00000002 // DMA Direction +#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL3_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR3 register. +// +//***************************************************************************** +#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR3_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT3 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT3_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL4 register. +// +//***************************************************************************** +#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL4_DIR 0x00000002 // DMA Direction +#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL4_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR4 register. +// +//***************************************************************************** +#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR4_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT4 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT4_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL5 register. +// +//***************************************************************************** +#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL5_DIR 0x00000002 // DMA Direction +#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL5_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR5 register. +// +//***************************************************************************** +#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR5_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT5 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT5_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL6 register. +// +//***************************************************************************** +#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL6_DIR 0x00000002 // DMA Direction +#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL6_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR6 register. +// +//***************************************************************************** +#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR6_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT6 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT6_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACTL7 register. +// +//***************************************************************************** +#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode +#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length +#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length +#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified + // length +#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or + // unspecified length +#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit +#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number +#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable +#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode +#define USB_DMACTL7_DIR 0x00000002 // DMA Direction +#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable +#define USB_DMACTL7_EP_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMAADDR7 register. +// +//***************************************************************************** +#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address +#define USB_DMAADDR7_ADDR_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DMACOUNT7 +// register. +// +//***************************************************************************** +#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count +#define USB_DMACOUNT7_COUNT_S 2 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT1_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT2_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT3_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT4_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT5_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT6_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7 +// register. +// +//***************************************************************************** +#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count +#define USB_RQPKTCOUNT7_COUNT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer + // Disable +#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS +// register. +// +//***************************************************************************** +#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer + // Disable +#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer + // Disable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CTO register. +// +//***************************************************************************** +#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value +#define USB_CTO_CCTV_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HHSRTN register. +// +//***************************************************************************** +#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating + // Delay +#define USB_HHSRTN_HHSRTN_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_HSBT register. +// +//***************************************************************************** +#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder +#define USB_HSBT_HSBT_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMATTR register. +// +//***************************************************************************** +#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint +#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake +#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration +#define USB_LPMATTR_LS_M 0x0000000F // Link State +#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1) +#define USB_LPMATTR_ENDPT_S 12 +#define USB_LPMATTR_HIRD_S 4 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMCNTRL register. +// +//***************************************************************************** +#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK +#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable +#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions + // are not supported. In this case, + // the USB does not respond to LPM + // transactions and LPM + // transactions cause a timeout +#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but + // extended transactions are + // supported. In this case, the USB + // does respond to an LPM + // transaction with a STALL +#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended + // transactions. In this case, the + // USB responds with a NYET or an + // ACK as determined by the value + // of TXLPM and other conditions +#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume +#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMIM register. +// +//***************************************************************************** +#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask +#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask +#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask +#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask +#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask +#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMRIS register. +// +//***************************************************************************** +#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status +#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status +#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status +#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status +#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status +#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_LPMFADDR register. +// +//***************************************************************************** +#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address +#define USB_LPMFADDR_ADDR_S 0 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPC register. +// +//***************************************************************************** +#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action +#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged +#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate +#define USB_EPC_PFLTACT_LOW 0x00000200 // Low +#define USB_EPC_PFLTACT_HIGH 0x00000300 // High +#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable +#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense +#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable +#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable +#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable + // Configuration +#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low +#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High +#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low + // (OTG only) +#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High + // (OTG only) + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCRIS register. +// +//***************************************************************************** +#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCIM register. +// +//***************************************************************************** +#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_EPCISC register. +// +//***************************************************************************** +#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRRIS register. +// +//***************************************************************************** +#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRIM register. +// +//***************************************************************************** +#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_DRISC register. +// +//***************************************************************************** +#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_GPCS register. +// +//***************************************************************************** +#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode +#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin +#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low +#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high +#define USB_GPCS_DEVMOD_HOSTVBUS \ + 0x00000004 // Use USB0VBUS and force USB0ID + // low +#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID + // high +#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode +#define USB_GPCS_DEVMOD 0x00000001 // Device Mode + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDC register. +// +//***************************************************************************** +#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCRIS register. +// +//***************************************************************************** +#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCIM register. +// +//***************************************************************************** +#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_VDCISC register. +// +//***************************************************************************** +#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and + // Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVRIS register. +// +//***************************************************************************** +#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt + // Status + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVIM register. +// +//***************************************************************************** +#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_IDVISC register. +// +//***************************************************************************** +#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status + // and Clear + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PP register. +// +//***************************************************************************** +#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count +#define USB_PP_USB_M 0x000000C0 // USB Capability +#define USB_PP_USB_DEVICE 0x00000040 // DEVICE +#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST +#define USB_PP_USB_OTG 0x000000C0 // OTG +#define USB_PP_ULPI 0x00000020 // ULPI Present +#define USB_PP_PHY 0x00000010 // PHY Present + +#define USB_PP_ECNT_S 8 + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_PC register. +// +//***************************************************************************** +#define USB_PC_ULPIEN 0x00010000 // ULPI Enable + +//***************************************************************************** +// +// The following are defines for the bit fields in the USB_O_CC register. +// +//***************************************************************************** +#define USB_CC_CLKEN 0x00000200 // USB Clock Enable +#define USB_CC_CSD 0x00000100 // Clock Source/Direction +#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor +#define USB_CC_CLKDIV_S 0 + + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableControl() and +// USBIntDisableControl() as the ui32Flags parameter, and are returned from +// USBIntStatusControl(). +// +//***************************************************************************** +#define USB_INTCTRL_ALL 0x000003FF // All control interrupt sources +#define USB_INTCTRL_STATUS 0x000000FF // Status Interrupts +#define USB_INTCTRL_VBUS_ERR 0x00000080 // VBUS Error +#define USB_INTCTRL_SESSION 0x00000040 // Session Start Detected +#define USB_INTCTRL_SESSION_END 0x00000040 // Session End Detected +#define USB_INTCTRL_DISCONNECT 0x00000020 // Disconnect Detected +#define USB_INTCTRL_CONNECT 0x00000010 // Device Connect Detected +#define USB_INTCTRL_SOF 0x00000008 // Start of Frame Detected +#define USB_INTCTRL_BABBLE 0x00000004 // Babble signaled +#define USB_INTCTRL_RESET 0x00000004 // Reset signaled +#define USB_INTCTRL_RESUME 0x00000002 // Resume detected +#define USB_INTCTRL_SUSPEND 0x00000001 // Suspend detected +#define USB_INTCTRL_MODE_DETECT 0x00000200 // Mode value valid +#define USB_INTCTRL_POWER_FAULT 0x00000100 // Power Fault detected + +//***************************************************************************** +// +// The following are values that can be passed to USBIntEnableEndpoint() and +// USBIntDisableEndpoint() as the ui32Flags parameter, and are returned from +// USBIntStatusEndpoint(). +// +//***************************************************************************** +#define USB_INTEP_ALL 0xFFFFFFFF // Host IN Interrupts +#define USB_INTEP_HOST_IN 0xFFFE0000 // Host IN Interrupts +#define USB_INTEP_HOST_IN_15 0x80000000 // Endpoint 15 Host IN Interrupt +#define USB_INTEP_HOST_IN_14 0x40000000 // Endpoint 14 Host IN Interrupt +#define USB_INTEP_HOST_IN_13 0x20000000 // Endpoint 13 Host IN Interrupt +#define USB_INTEP_HOST_IN_12 0x10000000 // Endpoint 12 Host IN Interrupt +#define USB_INTEP_HOST_IN_11 0x08000000 // Endpoint 11 Host IN Interrupt +#define USB_INTEP_HOST_IN_10 0x04000000 // Endpoint 10 Host IN Interrupt +#define USB_INTEP_HOST_IN_9 0x02000000 // Endpoint 9 Host IN Interrupt +#define USB_INTEP_HOST_IN_8 0x01000000 // Endpoint 8 Host IN Interrupt +#define USB_INTEP_HOST_IN_7 0x00800000 // Endpoint 7 Host IN Interrupt +#define USB_INTEP_HOST_IN_6 0x00400000 // Endpoint 6 Host IN Interrupt +#define USB_INTEP_HOST_IN_5 0x00200000 // Endpoint 5 Host IN Interrupt +#define USB_INTEP_HOST_IN_4 0x00100000 // Endpoint 4 Host IN Interrupt +#define USB_INTEP_HOST_IN_3 0x00080000 // Endpoint 3 Host IN Interrupt +#define USB_INTEP_HOST_IN_2 0x00040000 // Endpoint 2 Host IN Interrupt +#define USB_INTEP_HOST_IN_1 0x00020000 // Endpoint 1 Host IN Interrupt + +#define USB_INTEP_DEV_OUT 0xFFFE0000 // Device OUT Interrupts +#define USB_INTEP_DEV_OUT_15 0x80000000 // Endpoint 15 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_14 0x40000000 // Endpoint 14 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_13 0x20000000 // Endpoint 13 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_12 0x10000000 // Endpoint 12 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_11 0x08000000 // Endpoint 11 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_10 0x04000000 // Endpoint 10 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_9 0x02000000 // Endpoint 9 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_8 0x01000000 // Endpoint 8 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_7 0x00800000 // Endpoint 7 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_6 0x00400000 // Endpoint 6 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_5 0x00200000 // Endpoint 5 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_4 0x00100000 // Endpoint 4 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_3 0x00080000 // Endpoint 3 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_2 0x00040000 // Endpoint 2 Device OUT Interrupt +#define USB_INTEP_DEV_OUT_1 0x00020000 // Endpoint 1 Device OUT Interrupt + +#define USB_INTEP_HOST_OUT 0x0000FFFE // Host OUT Interrupts +#define USB_INTEP_HOST_OUT_15 0x00008000 // Endpoint 15 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_14 0x00004000 // Endpoint 14 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_13 0x00002000 // Endpoint 13 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_12 0x00001000 // Endpoint 12 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_11 0x00000800 // Endpoint 11 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_10 0x00000400 // Endpoint 10 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_9 0x00000200 // Endpoint 9 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_8 0x00000100 // Endpoint 8 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_7 0x00000080 // Endpoint 7 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_6 0x00000040 // Endpoint 6 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_5 0x00000020 // Endpoint 5 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_4 0x00000010 // Endpoint 4 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_3 0x00000008 // Endpoint 3 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_2 0x00000004 // Endpoint 2 Host OUT Interrupt +#define USB_INTEP_HOST_OUT_1 0x00000002 // Endpoint 1 Host OUT Interrupt + +#define USB_INTEP_DEV_IN 0x0000FFFE // Device IN Interrupts +#define USB_INTEP_DEV_IN_15 0x00008000 // Endpoint 15 Device IN Interrupt +#define USB_INTEP_DEV_IN_14 0x00004000 // Endpoint 14 Device IN Interrupt +#define USB_INTEP_DEV_IN_13 0x00002000 // Endpoint 13 Device IN Interrupt +#define USB_INTEP_DEV_IN_12 0x00001000 // Endpoint 12 Device IN Interrupt +#define USB_INTEP_DEV_IN_11 0x00000800 // Endpoint 11 Device IN Interrupt +#define USB_INTEP_DEV_IN_10 0x00000400 // Endpoint 10 Device IN Interrupt +#define USB_INTEP_DEV_IN_9 0x00000200 // Endpoint 9 Device IN Interrupt +#define USB_INTEP_DEV_IN_8 0x00000100 // Endpoint 8 Device IN Interrupt +#define USB_INTEP_DEV_IN_7 0x00000080 // Endpoint 7 Device IN Interrupt +#define USB_INTEP_DEV_IN_6 0x00000040 // Endpoint 6 Device IN Interrupt +#define USB_INTEP_DEV_IN_5 0x00000020 // Endpoint 5 Device IN Interrupt +#define USB_INTEP_DEV_IN_4 0x00000010 // Endpoint 4 Device IN Interrupt +#define USB_INTEP_DEV_IN_3 0x00000008 // Endpoint 3 Device IN Interrupt +#define USB_INTEP_DEV_IN_2 0x00000004 // Endpoint 2 Device IN Interrupt +#define USB_INTEP_DEV_IN_1 0x00000002 // Endpoint 1 Device IN Interrupt + +#define USB_INTEP_0 0x00000001 // Endpoint 0 Interrupt + +//***************************************************************************** +// +// The following are values that are returned from USBSpeedGet(). +// +//***************************************************************************** +#define USB_UNDEF_SPEED 0x80000000 // Current speed is undefined +#define USB_HIGH_SPEED 0x00000002 // Current speed is High Speed +#define USB_FULL_SPEED 0x00000001 // Current speed is Full Speed +#define USB_LOW_SPEED 0x00000000 // Current speed is Low Speed + +//***************************************************************************** +// +// The following are values that are returned from USBEndpointStatus(). The +// USB_HOST_* values are used when the USB controller is in host mode and the +// USB_DEV_* values are used when the USB controller is in device mode. +// +//***************************************************************************** +#define USB_HOST_IN_STATUS 0x114F0000 // Mask of all host IN interrupts +#define USB_HOST_IN_PID_ERROR 0x10000000 // Stall on this endpoint received +#define USB_HOST_IN_NOT_COMP 0x01000000 // Device failed to respond +#define USB_HOST_IN_STALL 0x00400000 // Stall on this endpoint received +#define USB_HOST_IN_DATA_ERROR 0x00080000 // CRC or bit-stuff error + // (ISOC Mode) +#define USB_HOST_IN_NAK_TO 0x00080000 // NAK received for more than the + // specified timeout period +#define USB_HOST_IN_ERROR 0x00040000 // Failed to communicate with a + // device +#define USB_HOST_IN_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_HOST_IN_PKTRDY 0x00010000 // Data packet ready +#define USB_HOST_OUT_STATUS 0x000000A7 // Mask of all host OUT interrupts +#define USB_HOST_OUT_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_OUT_NOT_COMP 0x00000080 // No response from device + // (ISOC mode) +#define USB_HOST_OUT_STALL 0x00000020 // Stall on this endpoint received +#define USB_HOST_OUT_ERROR 0x00000004 // Failed to communicate with a + // device +#define USB_HOST_OUT_FIFO_NE 0x00000002 // TX FIFO is not empty +#define USB_HOST_OUT_PKTPEND 0x00000001 // Transmit still being transmitted +#define USB_HOST_EP0_NAK_TO 0x00000080 // NAK received for more than the + // specified timeout period +#define USB_HOST_EP0_STATUS 0x00000040 // This was a status packet +#define USB_HOST_EP0_ERROR 0x00000010 // Failed to communicate with a + // device +#define USB_HOST_EP0_RX_STALL 0x00000004 // Stall on this endpoint received +#define USB_HOST_EP0_RXPKTRDY 0x00000001 // Receive data packet ready +#define USB_DEV_RX_PID_ERROR 0x01000000 // PID error in isochronous + // transfer +#define USB_DEV_RX_SENT_STALL 0x00400000 // Stall was sent on this endpoint +#define USB_DEV_RX_DATA_ERROR 0x00080000 // CRC error on the data +#define USB_DEV_RX_OVERRUN 0x00040000 // OUT packet was not loaded due to + // a full FIFO +#define USB_DEV_RX_FIFO_FULL 0x00020000 // RX FIFO full +#define USB_DEV_RX_PKT_RDY 0x00010000 // Data packet ready +#define USB_DEV_TX_NOT_COMP 0x00000080 // Large packet split up, more data + // to come +#define USB_DEV_TX_SENT_STALL 0x00000020 // Stall was sent on this endpoint +#define USB_DEV_TX_UNDERRUN 0x00000004 // IN received with no data ready +#define USB_DEV_TX_FIFO_NE 0x00000002 // The TX FIFO is not empty +#define USB_DEV_TX_TXPKTRDY 0x00000001 // Transmit still being transmitted +#define USB_DEV_EP0_SETUP_END 0x00000010 // Control transaction ended before + // Data End seen +#define USB_DEV_EP0_SENT_STALL 0x00000004 // Stall was sent on this endpoint +#define USB_DEV_EP0_IN_PKTPEND 0x00000002 // Transmit data packet pending +#define USB_DEV_EP0_OUT_PKTRDY 0x00000001 // Receive data packet ready + +//***************************************************************************** +// +// The following are values that can be passed to USBHostEndpointConfig() and +// USBDevEndpointConfigSet() as the ui32Flags parameter. +// +//***************************************************************************** +#define USB_EP_AUTO_SET 0x00000001 // Auto set feature enabled +#define USB_EP_AUTO_REQUEST 0x00000002 // Auto request feature enabled +#define USB_EP_AUTO_CLEAR 0x00000004 // Auto clear feature enabled +#define USB_EP_DMA_MODE_0 0x00000008 // Enable DMA access using mode 0 +#define USB_EP_DMA_MODE_1 0x00000010 // Enable DMA access using mode 1 +#define USB_EP_DIS_NYET 0x00000020 // Disable NYET response for + // high-speed Bulk and Interrupt + // endpoints in device mode. +#define USB_EP_MODE_ISOC 0x00000000 // Isochronous endpoint +#define USB_EP_MODE_BULK 0x00000100 // Bulk endpoint +#define USB_EP_MODE_INT 0x00000200 // Interrupt endpoint +#define USB_EP_MODE_CTRL 0x00000300 // Control endpoint +#define USB_EP_MODE_MASK 0x00000300 // Mode Mask +#define USB_EP_SPEED_LOW 0x00000000 // Low Speed +#define USB_EP_SPEED_FULL 0x00001000 // Full Speed +#define USB_EP_SPEED_HIGH 0x00004000 // High Speed +#define USB_EP_HOST_IN 0x00000000 // Host IN endpoint +#define USB_EP_HOST_OUT 0x00002000 // Host OUT endpoint +#define USB_EP_DEV_IN 0x00002000 // Device IN endpoint +#define USB_EP_DEV_OUT 0x00000000 // Device OUT endpoint + +//***************************************************************************** +// +// The following are values that can be passed to USBHostPwrConfig() as the +// ui32Flags parameter. +// +//***************************************************************************** +#define USB_HOST_PWRFLT_LOW 0x00000010 +#define USB_HOST_PWRFLT_HIGH 0x00000030 +#define USB_HOST_PWRFLT_EP_NONE 0x00000000 +#define USB_HOST_PWRFLT_EP_TRI 0x00000140 +#define USB_HOST_PWRFLT_EP_LOW 0x00000240 +#define USB_HOST_PWRFLT_EP_HIGH 0x00000340 +#define USB_HOST_PWREN_MAN_LOW 0x00000000 +#define USB_HOST_PWREN_MAN_HIGH 0x00000001 +#define USB_HOST_PWREN_AUTOLOW 0x00000002 +#define USB_HOST_PWREN_AUTOHIGH 0x00000003 +#define USB_HOST_PWREN_FILTER 0x00010000 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// USBHostLPMConfig() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_HOST_LPM_RMTWAKE 0x00000100 +#define USB_HOST_LPM_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that can be passed to the +// USBDevLPMConfig() function in the ui32Config parameter. +// +//***************************************************************************** +#define USB_DEV_LPM_NAK 0x00000010 +#define USB_DEV_LPM_NONE 0x00000000 +#define USB_DEV_LPM_EN 0x0000000c +#define USB_DEV_LPM_EXTONLY 0x00000004 + +//***************************************************************************** +// +// The following are the valid values that are returned from the +// USBLPMLinkStateGet() function. +// +//***************************************************************************** +#define USB_DEV_LPM_LS_RMTWAKE 0x00000100 +#define USB_DEV_LPM_LS_L1 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the USBLPMIntEnable() +// or USBLPMIntDisable() functions or are returned from the USBLPMIntStatus() +// function. +// +//***************************************************************************** +#define USB_INTLPM_ERROR 0x00000020 +#define USB_INTLPM_RESUME 0x00000010 +#define USB_INTLPM_INCOMPLETE 0x00000008 +#define USB_INTLPM_ACK 0x00000004 +#define USB_INTLPM_NYET 0x00000002 +#define USB_INTLPM_STALL 0x00000001 + +//***************************************************************************** +// +// The following are the valid values that are passed to the USBClockEnable() +// functions. +// +//***************************************************************************** +#define USB_CLOCK_INTERNAL 0x00000200 +#define USB_CLOCK_EXTERNAL 0x00000300 + +//***************************************************************************** +// +// The configuration options used with the USBULPIConfig() API. +// +//***************************************************************************** +#define USB_ULPI_EXTVBUS 0x00000001 +#define USB_ULPI_EXTVBUS_IND 0x00000002 + +//***************************************************************************** +// +// The following are special values that can be passed to +// USBHostEndpointConfig() as the ui32NAKPollInterval parameter. +// +//***************************************************************************** +#define MAX_NAK_LIMIT 31 // Maximum NAK interval +#define DISABLE_NAK_LIMIT 0 // No NAK timeouts + +//***************************************************************************** +// +// This value specifies the maximum size of transfers on endpoint 0 as 64 +// bytes. This value is fixed in hardware as the FIFO size for endpoint 0. +// +//***************************************************************************** +#define MAX_PACKET_SIZE_EP0 64 + +//***************************************************************************** +// +// These values are used to indicate which endpoint to access. +// +//***************************************************************************** +#define USB_EP_0 0x00000000 // Endpoint 0 +#define USB_EP_1 0x00000010 // Endpoint 1 +#define USB_EP_2 0x00000020 // Endpoint 2 +#define USB_EP_3 0x00000030 // Endpoint 3 +#define USB_EP_4 0x00000040 // Endpoint 4 +#define USB_EP_5 0x00000050 // Endpoint 5 +#define USB_EP_6 0x00000060 // Endpoint 6 +#define USB_EP_7 0x00000070 // Endpoint 7 +#define NUM_USB_EP 8 // Number of supported endpoints + +//***************************************************************************** +// +// These macros allow conversion between 0-based endpoint indices and the +// USB_EP_x values required when calling various USB APIs. +// +//***************************************************************************** +#define IndexToUSBEP(x) ((x) << 4) +#define USBEPToIndex(x) ((x) >> 4) + +//***************************************************************************** +// +// The following are values that can be passed to USBFIFOConfigSet() as the +// ui32FIFOSize parameter. +// +//***************************************************************************** +#define USB_FIFO_SZ_8 0x00000000 // 8 byte FIFO +#define USB_FIFO_SZ_16 0x00000001 // 16 byte FIFO +#define USB_FIFO_SZ_32 0x00000002 // 32 byte FIFO +#define USB_FIFO_SZ_64 0x00000003 // 64 byte FIFO +#define USB_FIFO_SZ_128 0x00000004 // 128 byte FIFO +#define USB_FIFO_SZ_256 0x00000005 // 256 byte FIFO +#define USB_FIFO_SZ_512 0x00000006 // 512 byte FIFO +#define USB_FIFO_SZ_1024 0x00000007 // 1024 byte FIFO +#define USB_FIFO_SZ_2048 0x00000008 // 2048 byte FIFO + +//***************************************************************************** +// +// This macro allow conversion from a FIFO size label as defined above to +// a number of bytes +// +//***************************************************************************** +#define USBFIFOSizeToBytes(x) (8 << (x)) + +//***************************************************************************** +// +// The following are values that can be passed to USBEndpointDataSend() as the +// ui32TransType parameter. +// +//***************************************************************************** +#define USB_TRANS_OUT 0x00000102 // Normal OUT transaction +#define USB_TRANS_IN 0x00000102 // Normal IN transaction +#define USB_TRANS_IN_LAST 0x0000010a // Final IN transaction (for + // endpoint 0 in device mode) +#define USB_TRANS_SETUP 0x0000110a // Setup transaction (for endpoint + // 0) +#define USB_TRANS_STATUS 0x00000142 // Status transaction (for endpoint + // 0) + +//***************************************************************************** +// +// The following are values are returned by the USBModeGet function. +// +//***************************************************************************** +#define USB_DUAL_MODE_HOST 0x00000001 // Dual mode controller is in Host + // mode. +#define USB_DUAL_MODE_DEVICE 0x00000081 // Dual mode controller is in + // Device mode. +#define USB_DUAL_MODE_NONE 0x00000080 // Dual mode controller mode is not + // set. +#define USB_OTG_MODE_ASIDE_HOST 0x0000001d // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_NPWR 0x00000001 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_ASIDE_SESS 0x00000009 // OTG controller on the A side of + // the cable Session Valid. +#define USB_OTG_MODE_ASIDE_AVAL 0x00000011 // OTG controller on the A side of + // the cable A valid. +#define USB_OTG_MODE_ASIDE_DEV 0x00000019 // OTG controller on the A side of + // the cable. +#define USB_OTG_MODE_BSIDE_HOST 0x0000009d // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_DEV 0x00000099 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_BSIDE_NPWR 0x00000081 // OTG controller on the B side of + // the cable. +#define USB_OTG_MODE_NONE 0x00000080 // OTG controller mode is not set. + +//***************************************************************************** +// +// The values for the USBDMAChannelIntEnable() and USBDMAChannelIntStatus() +// APIs. +// +//***************************************************************************** +#define USB_DMA_INT_CH8 0x00000080 +#define USB_DMA_INT_CH7 0x00000040 +#define USB_DMA_INT_CH6 0x00000020 +#define USB_DMA_INT_CH5 0x00000010 +#define USB_DMA_INT_CH4 0x00000008 +#define USB_DMA_INT_CH3 0x00000004 +#define USB_DMA_INT_CH2 0x00000002 +#define USB_DMA_INT_CH1 0x00000001 + +//***************************************************************************** +// +// The values for the USBDMAChannelStatus() API. +// +//***************************************************************************** +#define USB_DMA_STATUS_ERROR 0x00000100 + +//***************************************************************************** +// +// The valid return values for the USBDMAModeSet() and USBDMAModeGet() APIs or +// USBDMAChannelConfig(). +// +//***************************************************************************** +#define USB_DMA_CFG_BURST_NONE 0x00000000 +#define USB_DMA_CFG_BURST_4 0x00000200 +#define USB_DMA_CFG_BURST_8 0x00000400 +#define USB_DMA_CFG_BURST_16 0x00000600 +#define USB_DMA_CFG_INT_EN 0x00000008 +#define USB_DMA_CFG_MODE_0 0x00000000 +#define USB_DMA_CFG_MODE_1 0x00000004 +#define USB_DMA_CFG_DIR_RX 0x00000000 +#define USB_DMA_CFG_DIR_TX 0x00000002 +#define USB_DMA_CFG_EN 0x00000001 + +//***************************************************************************** +// +// The following are values that can be passed to USBModeConfig() as the +// ui3Mode parameter. +// +//***************************************************************************** +#define USB_MODE_HOST_VBUS 0x00000004 +#define USB_MODE_HOST 0x00000002 +#define USB_MODE_DEV_VBUS 0x00000005 +#define USB_MODE_DEV 0x00000003 +#define USB_MODE_OTG 0x00000000 + +#endif diff --git a/components/drivers/usb/cherryusb/port/ohci/README.md b/components/drivers/usb/cherryusb/port/ohci/README.md new file mode 100644 index 00000000000..34e753c3125 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ohci/README.md @@ -0,0 +1,18 @@ +# Note + +This OHCI is a companion controller of EHCI. + +## Support Chip List + +### AllwinnerTech + +- F133 + +### Nuvoton + +- Nuvoton all series + +### Artinchip + +- d13x, d21x + diff --git a/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.c b/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.c new file mode 100644 index 00000000000..b3d658290c2 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.c @@ -0,0 +1,240 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usb_ohci_priv.h" +#include "usb_ehci_priv.h" + +int ohci_init(struct usbh_bus *bus) +{ + volatile uint32_t timeout = 0; + uint32_t regval; + + USB_LOG_INFO("OHCI hcrevision:0x%02x\r\n", (unsigned int)OHCI_HCOR->hcrevision); + + OHCI_HCOR->hccontrol = 0; + OHCI_HCOR->hccontrolheaded = 0; + OHCI_HCOR->hcbulkheaded = 0; + + OHCI_HCOR->hccmdsts = OHCI_CMDST_HCR; + while (OHCI_HCOR->hccmdsts & OHCI_CMDST_HCR) { + usb_osal_msleep(1); + timeout++; + if (timeout > 100) { + return -USB_ERR_TIMEOUT; + } + } + + /* Frame Interval / Periodic Start. + * + * At 12Mbps, there are 12000 bit time in each 1Msec frame. + */ + +#define BITS_PER_FRAME 12000 +#define FI (BITS_PER_FRAME - 1) +#define FSMPS ((6 * (FI - 210)) / 7) +#define DEFAULT_FMINTERVAL ((FSMPS << OHCI_FMINT_FSMPS_SHIFT) | FI) +#define DEFAULT_PERSTART (((9 * BITS_PER_FRAME) / 10) - 1) + + OHCI_HCOR->hcfminterval = DEFAULT_FMINTERVAL; + OHCI_HCOR->hcperiodicstart = DEFAULT_PERSTART; + + /* Put HC in operational state */ + regval = OHCI_HCOR->hccontrol; + regval &= ~OHCI_CTRL_HCFS_MASK; + regval |= OHCI_CTRL_HCFS_OPER; + OHCI_HCOR->hccontrol = regval; + + /* Set global power in HcRhStatus */ + OHCI_HCOR->hcrhsts = OHCI_RHSTATUS_SGP; + + /* Set HCCA base address */ + OHCI_HCOR->hchcca = 0; + + /* Clear pending interrupts */ + regval = OHCI_HCOR->hcintsts; + OHCI_HCOR->hcintsts = regval; + + for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_pcc; port++) { + regval = OHCI_HCOR->hcrhportsts[port]; + regval |= OHCI_RHPORTST_PPS; + OHCI_HCOR->hcrhportsts[port] = regval; + } + + /* Enable OHCI interrupts */ + OHCI_HCOR->hcinten = OHCI_INT_SO | OHCI_INT_RD | OHCI_INT_UE | OHCI_INT_OC | + OHCI_INT_WDH | OHCI_INT_RHSC | OHCI_INT_MIE; + + return 0; +} + +int ohci_deinit(struct usbh_bus *bus) +{ + uint32_t regval; + + /* Disable OHCI interrupts */ + OHCI_HCOR->hcintdis = OHCI_INT_SO | OHCI_INT_RD | OHCI_INT_UE | OHCI_INT_OC | + OHCI_INT_WDH | OHCI_INT_RHSC | OHCI_INT_MIE; + + for (uint8_t port = 0; port < g_ehci_hcd[bus->hcd.hcd_id].n_pcc; port++) { + regval = OHCI_HCOR->hcrhportsts[port]; + regval &= ~OHCI_RHPORTST_PPS; + OHCI_HCOR->hcrhportsts[port] = regval; + } + + return 0; +} + +uint16_t ohci_get_frame_number(struct usbh_bus *bus) +{ + return OHCI_HCOR->hcfmnumber; +} + +int ohci_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf) +{ + uint8_t nports; + uint8_t port; + uint32_t temp; + + nports = g_ehci_hcd[bus->hcd.hcd_id].n_pcc; + + port = setup->wIndex; + if (setup->bmRequestType & USB_REQUEST_RECIPIENT_DEVICE) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + switch (setup->wValue) { + case HUB_FEATURE_HUB_C_LOCALPOWER: + break; + case HUB_FEATURE_HUB_C_OVERCURRENT: + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_DESCRIPTOR: + break; + case HUB_REQUEST_GET_STATUS: + memset(buf, 0, 4); + break; + default: + break; + } + } else if (setup->bmRequestType & USB_REQUEST_RECIPIENT_OTHER) { + switch (setup->bRequest) { + case HUB_REQUEST_CLEAR_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_ENABLE: + break; + case HUB_PORT_FEATURE_SUSPEND: + + case HUB_PORT_FEATURE_C_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_C_CONNECTION: + OHCI_HCOR->hcrhportsts[port - 1] |= OHCI_RHPORTST_CSC; + break; + case HUB_PORT_FEATURE_C_ENABLE: + OHCI_HCOR->hcrhportsts[port - 1] |= OHCI_RHPORTST_PESC; + break; + case HUB_PORT_FEATURE_C_OVER_CURREN: + OHCI_HCOR->hcrhportsts[port - 1] |= OHCI_RHPORTST_OCIC; + break; + case HUB_PORT_FEATURE_C_RESET: + OHCI_HCOR->hcrhportsts[port - 1] |= OHCI_RHPORTST_PRSC; + break; + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_SET_FEATURE: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + + switch (setup->wValue) { + case HUB_PORT_FEATURE_SUSPEND: + break; + case HUB_PORT_FEATURE_POWER: + break; + case HUB_PORT_FEATURE_RESET: + OHCI_HCOR->hcrhportsts[port - 1] |= OHCI_RHPORTST_PRS; + + while (OHCI_HCOR->hcrhportsts[port - 1] & OHCI_RHPORTST_PRS) { + } + break; + + default: + return -USB_ERR_NOTSUPP; + } + break; + case HUB_REQUEST_GET_STATUS: + if (!port || port > nports) { + return -USB_ERR_INVAL; + } + temp = OHCI_HCOR->hcrhportsts[port - 1]; + + memcpy(buf, &temp, 4); + break; + default: + break; + } + } + return 0; +} + +int ohci_submit_urb(struct usbh_urb *urb) +{ + return -USB_ERR_NOTSUPP; +} + +int ohci_kill_urb(struct usbh_urb *urb) +{ + return -USB_ERR_NOTSUPP; +} + +void OHCI_IRQHandler(uint8_t busid) +{ + uint32_t usbsts; + struct usbh_bus *bus; + + bus = &g_usbhost_bus[busid]; + + usbsts = OHCI_HCOR->hcintsts & OHCI_HCOR->hcinten; + OHCI_HCOR->hcintsts = usbsts; + + if (usbsts & OHCI_INT_RHSC) { + for (int port = 0; port < CONFIG_USBHOST_MAX_RHPORTS; port++) { + uint32_t portsc = OHCI_HCOR->hcrhportsts[port]; + + if (portsc & OHCI_RHPORTST_CSC) { + if (OHCI_HCOR->hcrhsts & OHCI_RHSTATUS_DRWE) { + /* If DRWE is set, Connect Status Change indicates a remote wake-up event */ + } else { + if (portsc & OHCI_RHPORTST_CCS) { + } else { + } + bus->hcd.roothub.int_buffer[0] |= (1 << (port + 1)); + usbh_hub_thread_wakeup(&bus->hcd.roothub); + } + } + } + } + if (usbsts & OHCI_INT_WDH) { + } +} \ No newline at end of file diff --git a/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.h b/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.h new file mode 100644 index 00000000000..030350e5cc6 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ohci/usb_hc_ohci.h @@ -0,0 +1,484 @@ +/**************************************************************************** + * include/nuttx/usb/ohci.h + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +#ifndef __INCLUDE_NUTTX_USB_OHCI_H +#define __INCLUDE_NUTTX_USB_OHCI_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Register offsets *********************************************************/ + +/* Control and status registers (section 7.1) */ + +#define OHCI_HCIREV_OFFSET 0x0000 /* HcRevision: Version of HCI specification */ +#define OHCI_CTRL_OFFSET 0x0004 /* HcControl: HC control */ +#define OHCI_CMDST_OFFSET 0x0008 /* HcCommandStatus: HC command status */ +#define OHCI_INTST_OFFSET 0x000c /* HcInterruptStatus: HC interrupt status */ +#define OHCI_INTEN_OFFSET 0x0010 /* HcInterruptEnable: HC interrupt enable */ +#define OHCI_INTDIS_OFFSET 0x0014 /* HcInterruptDisable: HC interrupt disable */ + +/* Memory pointer registers (section 7.2) */ + +#define OHCI_HCCA_OFFSET 0x0018 /* HcHCCA: HC communication area */ +#define OHCI_PERED_OFFSET 0x001c /* HcPeriodCurrentED: Current isoc or int endpoint desc */ +#define OHCI_CTRLHEADED_OFFSET 0x0020 /* HcControlHeadED: First EP desc in the control list */ +#define OHCI_CTRLED_OFFSET 0x0024 /* HcControlCurrentED: Current EP desc in the control list */ +#define OHCI_BULKHEADED_OFFSET 0x0028 /* HcBulkHeadED: First EP desc in the bulk list */ +#define OHCI_BULKED_OFFSET 0x002c /* HcBulkCurrentED: Current EP desc in the bulk list */ +#define OHCI_DONEHEAD_OFFSET 0x0030 /* HcDoneHead: Last transfer desc added to DONE queue */ + +/* Frame counter registers (section 7.3) */ + +#define OHCI_FMINT_OFFSET 0x0034 /* HcFmInterval: Bit time interval that would not cause overrun */ +#define OHCI_FMREM_OFFSET 0x0038 /* HcFmRemaining: Bit time remaining in current frame */ +#define OHCI_FMNO_OFFSET 0x003c /* HcFmNumber: Frame number counter */ +#define OHCI_PERSTART_OFFSET 0x0040 /* HcPeriodicStart: Time to start processing periodic list */ + +/* Root hub registers (section 7.4) */ + +#define OHCI_LSTHRES_OFFSET 0x0044 /* HcLSThreshold: Commit to transfer threshold */ +#define OHCI_RHDESCA_OFFSET 0x0048 /* HcRhDescriptorA: Describes root hub (part A) */ +#define OHCI_RHDESCB_OFFSET 0x004c /* HcRhDescriptorB: Describes root hub (part B) */ +#define OHCI_RHSTATUS_OFFSET 0x0050 /* HcRhStatus: Root hub status */ + +#define OHCI_MAX_RHPORT 15 /* Maximum number of OHCI root hub ports */ + +#define OHCI_RHPORTST_OFFSET(n) (0x0054 + (((n) - 1) << 2)) +#define OHCI_RHPORTST1_OFFSET 0x0054 /* HcRhPort1Status: Root hub port status 1 */ +#define OHCI_RHPORTST2_OFFSET 0x0058 /* HcRhPort2Status: Root hub port status 2 */ +#define OHCI_RHPORTST3_OFFSET 0x005c /* HcRhPort3Status: Root hub port status 3 */ +#define OHCI_RHPORTST4_OFFSET 0x0060 /* HcRhPort4Status: Root hub port status 4 */ +#define OHCI_RHPORTST5_OFFSET 0x0064 /* HcRhPort5Status: Root hub port status 5 */ +#define OHCI_RHPORTST6_OFFSET 0x0068 /* HcRhPort6Status: Root hub port status 6 */ +#define OHCI_RHPORTST7_OFFSET 0x006c /* HcRhPort7Status: Root hub port status 7 */ +#define OHCI_RHPORTST8_OFFSET 0x0070 /* HcRhPort8Status: Root hub port status 8 */ +#define OHCI_RHPORTST9_OFFSET 0x0074 /* HcRhPort9Status: Root hub port status 9 */ +#define OHCI_RHPORTST10_OFFSET 0x0078 /* HcRhPort10Status: Root hub port status 10 */ +#define OHCI_RHPORTST11_OFFSET 0x007c /* HcRhPort11Status: Root hub port status 11 */ +#define OHCI_RHPORTST12_OFFSET 0x0080 /* HcRhPort12Status: Root hub port status 12 */ +#define OHCI_RHPORTST13_OFFSET 0x0084 /* HcRhPort13Status: Root hub port status 13 */ +#define OHCI_RHPORTST14_OFFSET 0x0088 /* HcRhPort14Status: Root hub port status 14 */ +#define OHCI_RHPORTST15_OFFSET 0x008c /* HcRhPort15Status: Root hub port status 15 */ + +/* Register bit definitions *************************************************/ + +/* HcRevision: Version of HCI specification (7.1.1) */ + +#define OHCI_HCIREV_SHIFT (0) /* Bits 0-7: HCI spec version (BCD) */ +#define OHCI_HCIREV_MASK (0xff << OHCI_HCIREV_SHIFT) + +/* HcControl: HC control (7.1.2) */ + +#define OHCI_CTRL_CBSR (3 << 0) /* Bit 0: Control/bulk service ratio */ +#define OHCI_CTRL_PLE (1 << 2) /* Bit 1: Periodic list enable */ +#define OHCI_CTRL_IE (1 << 3) /* Bit 2: Isochronous enable */ +#define OHCI_CTRL_CLE (1 << 4) /* Bit 3: Control list enable */ +#define OHCI_CTRL_BLE (1 << 5) /* Bit 4: Bulk list enable */ +#define OHCI_CTRL_HCFS_SHIFT (6) /* Bits 6-7: Host controller functional state */ +#define OHCI_CTRL_HCFS_MASK (3 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_RESET (0 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_RESUME (1 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_OPER (2 << OHCI_CTRL_HCFS_SHIFT) +# define OHCI_CTRL_HCFS_SUSPEND (3 << OHCI_CTRL_HCFS_SHIFT) +#define OHCI_CTRL_IR (1 << 8) /* Bit 8: Interrupt routing */ +#define OHCI_CTRL_RWC (1 << 9) /* Bit 9: Remote wakeup connected */ +#define OHCI_CTRL_RWE (1 << 10) /* Bit 10: Remote wakeup enable */ + /* Bits 11-31: Reserved */ + +/* HcCommandStatus: HC command status (7.1.3) */ + +#define OHCI_CMDST_HCR (1 << 0) /* Bit 0: Host controller reset */ +#define OHCI_CMDST_CLF (1 << 1) /* Bit 1: Control list filled */ +#define OHCI_CMDST_BLF (1 << 2) /* Bit 2: Bulk list filled */ +#define OHCI_CMDST_OCR (1 << 3) /* Bit 3: Ownership change request */ + /* Bits 4-15: Reserved */ +#define OHCI_CMDST_SOC (3 << 16) /* Bit 16: Scheduling overrun count */ + /* Bits 17-31: Reserved */ + +/* HcInterruptStatus: HC interrupt status (7.1.4), + * HcInterruptEnable: HC interrupt enable (7.1.5), and + * HcInterruptDisable: HC interrupt disable (7.1.6) + */ + +#define OHCI_INT_SO (1 << 0) /* Bit 0: Scheduling overrun */ +#define OHCI_INT_WDH (1 << 1) /* Bit 1: Writeback done head */ +#define OHCI_INT_SF (1 << 2) /* Bit 2: Start of frame */ +#define OHCI_INT_RD (1 << 3) /* Bit 3: Resume detected */ +#define OHCI_INT_UE (1 << 4) /* Bit 4: Unrecoverable error */ +#define OHCI_INT_FNO (1 << 5) /* Bit 5: Frame number overflow */ +#define OHCI_INT_RHSC (1 << 6) /* Bit 6: Root hub status change */ + /* Bits 7-29: Reserved */ +#define OHCI_INT_OC (1 << 30) /* Bit 30: Ownership change */ +#define OHCI_INT_MIE (1 << 31) /* Bit 31: Master interrupt enable + * (Enable/disable only) */ + +/* HcHCCA: HC communication area (7.2.1): + * + * 32-bits aligned to 256 byte boundary. + */ + +/* HcPeriodCurrentED: Current isoc or int endpoint desc (7.2.2), + * HcControlHeadED: First EP desc in the control list (7.2.3), + * HcControlCurrentED: Current EP desc in the control list (7.2.4), + * HcBulkHeadED: First EP desc in the bulk list (7.2.5), + * HcBulkCurrentED: Current EP desc in the bulk list (7.2.6), and + * HcDoneHead: Last transfer desc added to DONE queue (7.2.7): + * + * All 32-bits aligned to an 8-byte boundary + */ + +/* HcFmInterval: Bit time interval that would not cause overrun (7.3.1) */ + +#define OHCI_FMINT_FI_SHIFT (0) /* Bits 0-13: Frame interval */ +#define OHCI_FMINT_FI_MASK (0x3fff << OHCI_FMINT_FI_SHIFT) + /* Bits 14-15: Reserved */ +#define OHCI_FMINT_FSMPS_SHIFT (16) /* Bits 16-30: FS largest packet data */ +#define OHCI_FMINT_FSMPS_MASK (0x7fff << OHCI_FMINT_FSMPS_SHIFT) +#define OHCI_FMINT_FIT (1 << 31) /* Bit 31: Frame interval toggle */ + +/* HcFmRemaining: Bit time remaining in current frame (7.3.2) */ + +#define OHCI_FMREM_FR_SHIFT (0) /* Bits 0-13: Frame remaining */ +#define OHCI_FMREM_FR_MASK (0x3fff << OHCI_FMREM_FR_SHIFT) + /* Bits 16-30: Reserved */ +#define OHCI_FMINT_FRT (1 << 31) /* Bit 31: Frame remaining toggle */ + +/* HcFmNumber: Frame number counter (7.3.3) */ + +#define OHCI_FMNO_FI_SHIFT (0) /* Bits 0-15: Frame number */ +#define OHCI_FMNO_FI_MASK (0xffff << OHCI_FMINT_FI_SHIFT) + /* Bits 16-31: Reserved */ + +/* HcPeriodicStart: Time to start processing periodic list (7.3.4) */ + +#define OHCI_PERSTART_SHIFT (0) /* Bits 0-13: Periodic start */ +#define OHCI_PERSTART_MASK (0x3fff << OHCI_PERSTART_SHIFT) + /* Bits 14-31: Reserved */ + +/* HcLSThreshold: Commit to transfer threshold (7.3.5) */ + +#define OHCI_LSTHRES_SHIFT (0) /* Bits 0-11: LS threshold */ +#define OHCI_LSTHRES_MASK (0x0fff << OHCI_PERSTART_SHIFT) + /* Bits 12-31: Reserved */ + +/* HcRhDescriptorN: Describes root hub (part A) (7.4.1) */ + +#define OHCI_RHDESCA_NDP_SHIFT (0) /* Bits 0-7: Number downstream ports */ +#define OHCI_RHDESCA_NDP_MASK (0xff << OHCI_RHDESCA_NDP_SHIFT) +#define OHCI_RHDESCA_PSM (1 << 8) /* Bit 8: Power switching mode */ +#define OHCI_RHDESCA_NPS (1 << 9) /* Bit 9: No power switching */ +#define OHCI_RHDESCA_DT (1 << 10) /* Bit 10: Device type */ +#define OHCI_RHDESCA_OCPM (1 << 11) /* Bit 11: Over current protection mode */ +#define OHCI_RHDESCA_NOCP (1 << 12) /* Bit 12: No over current protection */ + /* Bits 13-23: Reserved */ +#define OHCI_RHDESCA_POTPGT_SHIFT (24) /* Bits 24-31: Power on to power good time */ +#define OHCI_RHDESCA_POTPGT_MASK (0xff << OHCI_RHDESCA_POTPGT_SHIFT) + +/* HcRhDescriptorB: Describes root hub (part B) (7.4.2) */ + +#define OHCI_RHDESCB_DR_SHIFT (0) /* Bits 0-15: Device removable */ +#define OHCI_RHDESCB_DR_MASK (0xffff << OHCI_RHDESCB_DR_SHIFT) +# define OHCI_RHDESCB_ATTACHED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n))) +#define OHCI_RHDESCB_PPCM_SHIFT (16) /* Bits 16-31: Port power control mask */ +#define OHCI_RHDESCB_PPCM_MASK (0xffff << OHCI_RHDESCB_PPCM_SHIFT) +# define OHCI_RHDESCB_POWERED(n) (1 << (OHCI_RHDESCB_DR_SHIFT+(n))) + +/* HcRhStatus: Root hub status (7.4.3) */ + +#define OHCI_RHSTATUS_LPS (1 << 0) /* Bit 0: Local power status (read)*/ +#define OHCI_RHSTATUS_CGP (1 << 0) /* Bit 0: Clear global power (write)*/ +#define OHCI_RHSTATUS_OCI (1 << 1) /* Bit 1: Over current indicator */ + /* Bits 2-14: Reserved */ +#define OHCI_RHSTATUS_DRWE (1 << 15) /* Bit 15: Device remote wakeup enable */ +#define OHCI_RHSTATUS_LPSC (1 << 16) /* Bit 16: Local power status change (read) */ +#define OHCI_RHSTATUS_SGP (1 << 16) /* Bit 16: Set global power (write) */ +#define OHCI_RHSTATUS_OCIC (1 << 17) /* Bit 17: Overcurrent indicator change */ + /* Bits 18-30: Reserved */ +#define OHCI_RHSTATUS_CRWE (1 << 31) /* Bit 31: Clear remote wakeup enable */ + +/* HcRhPortStatus: Root hub port status (7.4.4) */ + +#define OHCI_RHPORTST_CCS (1 << 0) /* Bit 0: Current connect status */ +#define OHCI_RHPORTST_PES (1 << 1) /* Bit 1: Port enable status */ +#define OHCI_RHPORTST_PSS (1 << 2) /* Bit 2: Port suspend status */ +#define OHCI_RHPORTST_POCI (1 << 3) /* Bit 3: Port over current indicator */ +#define OHCI_RHPORTST_PRS (1 << 4) /* Bit 4: Port reset status */ + /* Bits 5-7: Reserved */ +#define OHCI_RHPORTST_PPS (1 << 8) /* Bit 8: Port power status */ +#define OHCI_RHPORTST_LSDA (1 << 9) /* Bit 9: Low speed device attached */ + /* Bits 10-15: Reserved */ +#define OHCI_RHPORTST_CSC (1 << 16) /* Bit 16: Connect status change */ +#define OHCI_RHPORTST_PESC (1 << 17) /* Bit 17: Port enable status change */ +#define OHCI_RHPORTST_PSSC (1 << 18) /* Bit 18: Port suspend status change */ +#define OHCI_RHPORTST_OCIC (1 << 19) /* Bit 19: Port over current indicator change */ +#define OHCI_RHPORTST_PRSC (1 << 20) /* Bit 20: Port reset status change */ + /* Bits 21-31: Reserved */ + +/* Transfer Descriptors *****************************************************/ + +/* Endpoint Descriptor Offsets (4.2.1) */ + +#define ED_CONTROL_OFFSET (0x00) /* ED status/control bits */ +#define ED_TAILP_OFFSET (0x04) /* TD Queue Tail Pointer (TailP) */ +#define ED_HEADP_OFFSET (0x08) /* TD Queue Head Pointer (HeadP) */ +#define ED_NEXTED_OFFSET (0x0c) /* Next Endpoint Descriptor (NextED) */ + +/* Endpoint Descriptor Bit Definitions (4.2.2) */ + +#define ED_CONTROL_FA_SHIFT (0) /* Bits 0-6: Function Address */ +#define ED_CONTROL_FA_MASK (0x7f << ED_CONTROL_FA_SHIFT) +#define ED_CONTROL_EN_SHIFT (7) /* Bits 7-10: Endpoint number */ +#define ED_CONTROL_EN_MASK (15 << ED_CONTROL_EN_SHIFT) +#define ED_CONTROL_D_SHIFT (11) /* Bits 11-12: Direction */ +#define ED_CONTROL_D_MASK (3 << ED_CONTROL_D_SHIFT) +# define ED_CONTROL_D_TD1 (0 << ED_CONTROL_D_SHIFT) /* Get direction from TD */ +# define ED_CONTROL_D_OUT (1 << ED_CONTROL_D_SHIFT) /* OUT */ +# define ED_CONTROL_D_IN (2 << ED_CONTROL_D_SHIFT) /* IN */ +# define ED_CONTROL_D_TD2 (3 << ED_CONTROL_D_SHIFT) /* Get direction from TD */ + +#define ED_CONTROL_S (1 << 13) /* Bit 13: Speed (low) */ +#define ED_CONTROL_K (1 << 14) /* Bit 14: Skip */ +#define ED_CONTROL_F (1 << 15) /* Bit 15: Format (isochronous) */ +#define ED_CONTROL_MPS_SHIFT (16) /* Bits 16-26: Maximum packet size */ +#define ED_CONTROL_MPS_MASK (0x7ff << ED_CONTROL_MPS_SHIFT) + +#define ED_HEADP_ADDR_SHIFT (0) +#define ED_HEADP_ADDR_MASK 0xfffffff0 +#define ED_HEADP_H (1 << 0) /* Bit 0: Halted */ +#define ED_HEADP_C (1 << 1) /* Bit 1: Toggle carry */ + +/* General Transfer Descriptor Offsets (4.3.1) */ + +#define GTD_STATUS_OFFSET (0x00) /* TD status bits */ +#define GTD_CBP_OFFSET (0x04) /* Current Buffer Pointer (CBP) */ +#define GTD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */ +#define GTD_BE_OFFSET (0x0c) /* Buffer End (BE) */ + +/* General Transfer Descriptor Bit Definitions */ + + /* Bits 0-17: Reserved */ + +#define GTD_STATUS_R (1 << 18) /* Bit 18: Buffer rounding */ +#define GTD_STATUS_DP_SHIFT (19) /* Bits 19-20: Direction/PID */ +#define GTD_STATUS_DP_MASK (3 << GTD_STATUS_DP_SHIFT) +# define GTD_STATUS_DP_SETUP (0 << GTD_STATUS_DP_SHIFT) /* To endpoint */ +# define GTD_STATUS_DP_OUT (1 << GTD_STATUS_DP_SHIFT) /* To endpoint */ +# define GTD_STATUS_DP_IN (2 << GTD_STATUS_DP_SHIFT) /* From endpoint */ + +#define GTD_STATUS_DI_SHIFT (21) /* Bits 21-23: Delay input */ +#define GTD_STATUS_DI_MASK (7 << GTD_STATUS_DI_SHIFT) +#define GTD_STATUS_T_SHIFT (24) /* Bits 24-25: Data Toggle */ +#define GTD_STATUS_T_MASK (3 << GTD_STATUS_T_SHIFT) +# define GTD_STATUS_T_TOGGLE (0 << GTD_STATUS_T_SHIFT) +# define GTD_STATUS_T_DATA0 (2 << GTD_STATUS_T_SHIFT) +# define GTD_STATUS_T_DATA1 (3 << GTD_STATUS_T_SHIFT) +#define GTD_STATUS_EC_SHIFT (26) /* Bits 26-27: Error count */ +#define GTD_STATUS_EC_MASK (3 << GTD_STATUS_EC_SHIFT) +#define GTD_STATUS_CC_SHIFT (28) /* Bits 28-31: Condition code */ +#define GTD_STATUS_CC_MASK (15 << GTD_STATUS_CC_SHIFT) + +/* Isochronous Transfer Descriptor Offsets (4.3.2) */ + +#define ITD_STATUS_OFFSET (0x00) /* TD status bits */ +#define ITD_BP0_OFFSET (0x04) /* Buffer page 0 (BP0) */ +#define ITD_NEXTTD_OFFSET (0x08) /* Next TD (NextTD) */ +#define ITD_BE_OFFSET (0x0c) /* Buffer End (BE) */ + +#define ITD_NPSW (8) +#define ITD_PSW0_OFFSET (0x10) /* Offset0/PSW0 */ +#define ITD_PSW1_OFFSET (0x12) /* Offset1/PSW1 */ +#define ITD_PSW2_OFFSET (0x14) /* Offset2/PSW2 */ +#define ITD_PSW3_OFFSET (0x16) /* Offset3/PSW3 */ +#define ITD_PSW4_OFFSET (0x18) /* Offset4/PSW4 */ +#define ITD_PSW5_OFFSET (0x1a) /* Offset5/PSW5 */ +#define ITD_PSW6_OFFSET (0x1c) /* Offset6/PSW6 */ +#define ITD_PSW7_OFFSET (0x1e) /* Offset7/PSW7 */ + +/* Condition codes (Table 4-7) */ + +#define TD_CC_NOERROR 0x00 +#define TD_CC_CRC 0x01 +#define TD_CC_BITSTUFFING 0x02 +#define TD_CC_DATATOGGLEMISMATCH 0x03 +#define TD_CC_STALL 0x04 +#define TD_CC_DEVNOTRESPONDING 0x05 +#define TD_CC_PIDCHECKFAILURE 0x06 +#define TD_CC_UNEXPECTEDPID 0x07 +#define TD_CC_DATAOVERRUN 0x08 +#define TD_CC_DATAUNDERRUN 0x09 +#define TD_CC_BUFFEROVERRUN 0x0c +#define TD_CC_BUFFERUNDERRUN 0x0d +#define TD_CC_NOTACCESSED 0x0f + +#define TD_CC_USER 0x10 /* For use by OHCI drivers */ + +/* Host Controller Communications Area Format (4.4.1) ***********************/ + +/* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */ + +#define HCCA_INTTBL_OFFSET (0x00) +#define HCCA_INTTBL_WSIZE (32) +#define HCCA_INTTBL_BSIZE (HCCA_INTTBL_WSIZE * 4) + +/* HccaFrameNumber: Current frame number */ + +#define HCCA_FMNO_OFFSET (0x80) +#define HCCA_FMNO_BSIZE (2) + +/* HccaPad1: Zero when frame no. updated */ + +#define HCCA_PAD1_OFFSET (0x82) +#define HCCA_PAD1_BSIZE (2) + +/* HccaDoneHead: When the HC reaches the end of a frame and its deferred + * interrupt register is 0, it writes the current value of its HcDoneHead to + * this location and generates an interrupt. + * + * The LSB of HCCADoneHead may be set to 1 to indicate that an unmasked + * HcInterruptStatus was set when HccaDoneHead was written. + */ + +#define HCCA_DONEHEAD_OFFSET (0x84) +#define HCCA_DONEHEAD_BSIZE (4) + +#define HCCA_DONEHEAD_MASK 0xfffffffe +#define HCCA_DONEHEAD_INTSTA (1 << 0) + +/* 0x88: 116 bytes reserved */ + +#define HCCA_RESERVED_OFFSET (0x88) +#define HCCA_RESERVED_BSIZE (116) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +struct ohci_hcor +{ + volatile uint32_t hcrevision; /* 0x00 */ + volatile uint32_t hccontrol; /* 0x04 */ + volatile uint32_t hccmdsts; /* 0x08 */ + volatile uint32_t hcintsts; /* 0x0c */ + volatile uint32_t hcinten; /* 0x10 */ + volatile uint32_t hcintdis; /* 0x14 */ + volatile uint32_t hchcca; /* 0x18 */ + volatile uint32_t hcperiodcurrented; /* 0x1c */ + volatile uint32_t hccontrolheaded; /* 0x20 */ + volatile uint32_t hccontrolcurrented; /* 0x24 */ + volatile uint32_t hcbulkheaded; /* 0x28 */ + volatile uint32_t hcbulkcurrented; /* 0x2c */ + volatile uint32_t hcdonehead; /* 0x30 */ + volatile uint32_t hcfminterval; /* 0x34 */ + volatile uint32_t hcfmremaining; /* 0x38 */ + volatile uint32_t hcfmnumber; /* 0x3c */ + volatile uint32_t hcperiodicstart; /* 0x40 */ + volatile uint32_t hclsthreshold; /* 0x44 */ + volatile uint32_t hcrhdescriptora; /* 0x48 */ + volatile uint32_t hcrhdescriptorb; /* 0x4c */ + volatile uint32_t hcrhsts; /* 0x50 */ + volatile uint32_t hcrhportsts[15]; /* 0x54 */ +}; + +/* Endpoint Descriptor Offsets (4.2.1) */ + +struct ohci_ed_s +{ + volatile uint32_t ctrl; /* ED status/control bits */ + volatile uint32_t tailp; /* TD Queue Tail Pointer (TailP) */ + volatile uint32_t headp; /* TD Queue Head Pointer (HeadP) */ + volatile uint32_t nexted; /* Next Endpoint Descriptor (NextED) */ +}; + +/* General Transfer Descriptor (4.3.1) */ + +struct ohci_gtd_s +{ + volatile uint32_t ctrl; /* TD status/control bits */ + volatile uint32_t cbp; /* Current Buffer Pointer (CBP) */ + volatile uint32_t nexttd; /* Next TD (NextTD) */ + volatile uint32_t be; /* Buffer End (BE) */ +}; + +/* Isochronous Transfer Descriptor Offsets (4.3.2) */ + +struct ohci_itd_s +{ + volatile uint32_t ctrl; /* TD status/control bits */ + volatile uint32_t bp0; /* Buffer page 0 (BP0 */ + volatile uint32_t nexttd; /* Next TD (NextTD) */ + volatile uint32_t be; /* Buffer End (BE) */ + volatile uint16_t psw[ITD_NPSW]; /* Offset/PSW */ +}; + +/* Host Controller Communications Area Format (4.4.1) */ + +struct ohci_hcca_s +{ + /* HccaInterruptTable: 32x32-bit pointers to interrupt EDs */ + + volatile uint32_t inttbl[HCCA_INTTBL_WSIZE]; + + /* HccaFrameNumber: Current frame number and + * HccaPad1: Zero when frame no. updated + */ + + volatile uint16_t fmno; + volatile uint16_t pad1; + + /* HccaDoneHead: When the HC reaches the end of a frame and its deferred + * interrupt register is 0, it writes the current value of its HcDoneHead + * to this location and generates an interrupt. + */ + + volatile uint32_t donehead; + volatile uint8_t reserved[HCCA_RESERVED_BSIZE]; + volatile uint32_t extra; +} __attribute__((aligned(256))); + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif + +#endif /* __INCLUDE_NUTTX_USB_OHCI_H */ diff --git a/components/drivers/usb/cherryusb/port/ohci/usb_ohci_priv.h b/components/drivers/usb/cherryusb/port/ohci/usb_ohci_priv.h new file mode 100644 index 00000000000..4404dc253e7 --- /dev/null +++ b/components/drivers/usb/cherryusb/port/ohci/usb_ohci_priv.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _USB_OHCI_PRIV_H +#define _USB_OHCI_PRIV_H + +#include "usbh_core.h" +#include "usbh_hub.h" +#include "usb_hc_ohci.h" + +#define OHCI_HCOR ((struct ohci_hcor *)(uintptr_t)(bus->hcd.reg_base + CONFIG_USB_OHCI_HCOR_OFFSET)) + +int ohci_init(struct usbh_bus *bus); +int ohci_deinit(struct usbh_bus *bus); +uint16_t ohci_get_frame_number(struct usbh_bus *bus); +int ohci_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf); +int ohci_submit_urb(struct usbh_urb *urb); +int ohci_kill_urb(struct usbh_urb *urb); + +void OHCI_IRQHandler(uint8_t busid); + +#endif \ No newline at end of file diff --git a/components/legacy/Kconfig b/components/legacy/Kconfig new file mode 100644 index 00000000000..d20c0f92f93 --- /dev/null +++ b/components/legacy/Kconfig @@ -0,0 +1,200 @@ +menu "Using USB legacy version" + config RT_USING_USB + bool + default n + + config RT_USING_USB_HOST + bool "Using USB host" + default n + select RT_USING_USB + + if RT_USING_USB_HOST + config RT_USBH_MSTORAGE + bool "Enable Udisk Drivers" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + config RT_USBH_HID + bool "Enable HID Drivers" + default n + if RT_USBH_HID + config RT_USBH_HID_MOUSE + bool "Enable HID mouse protocol" + default n + config RT_USBH_HID_KEYBOARD + bool "Enable HID keyboard protocol" + default n + endif + endif + config RT_USING_USB_DEVICE + bool "Using USB device" + default n + select RT_USING_USB + + if RT_USING_USB_DEVICE || RT_USING_USB_HOST + config RT_USBD_THREAD_STACK_SZ + int "usb thread stack size" + default 4096 + endif + if RT_USING_USB_DEVICE + config USB_VENDOR_ID + hex "USB Vendor ID" + default 0x0FFE + config USB_PRODUCT_ID + hex "USB Product ID" + default 0x0001 + + config RT_USB_DEVICE_COMPOSITE + bool "Enable composite device" + default n + choice + prompt "Device type" + default _RT_USB_DEVICE_NONE + depends on !RT_USB_DEVICE_COMPOSITE + config _RT_USB_DEVICE_NONE + bool "Using custom class by register interface" + select RT_USB_DEVICE_NONE + config _RT_USB_DEVICE_CDC + bool "Enable to use device as CDC device" + select RT_USB_DEVICE_CDC + config _RT_USB_DEVICE_MSTORAGE + bool "Enable to use device as Mass Storage device" + select RT_USB_DEVICE_MSTORAGE + config _RT_USB_DEVICE_HID + bool "Enable to use device as HID device" + select RT_USB_DEVICE_HID + config _RT_USB_DEVICE_RNDIS + bool "Enable to use device as rndis device" + select RT_USB_DEVICE_RNDIS + depends on RT_USING_LWIP + config _RT_USB_DEVICE_ECM + bool "Enable to use device as ecm device" + select RT_USB_DEVICE_ECM + depends on RT_USING_LWIP + config _RT_USB_DEVICE_WINUSB + bool "Enable to use device as winusb device" + select RT_USB_DEVICE_WINUSB + config _RT_USB_DEVICE_AUDIO + bool "Enable to use device as audio device" + select RT_USB_DEVICE_AUDIO + endchoice + if RT_USB_DEVICE_COMPOSITE + config RT_USB_DEVICE_CDC + bool "Enable to use device as CDC device" + default n + config RT_USB_DEVICE_NONE + bool + default y + config RT_USB_DEVICE_MSTORAGE + bool "Enable to use device as Mass Storage device" + default n + config RT_USB_DEVICE_HID + bool "Enable to use device as HID device" + default n + config RT_USB_DEVICE_RNDIS + bool "Enable to use device as rndis device" + default n + depends on RT_USING_LWIP + config RT_USB_DEVICE_ECM + bool "Enable to use device as ecm device" + default n + depends on RT_USING_LWIP + config RT_USB_DEVICE_WINUSB + bool "Enable to use device as winusb device" + default n + config RT_USB_DEVICE_AUDIO + bool "Enable to use device as audio device" + default n + endif + if RT_USB_DEVICE_CDC + config RT_VCOM_TASK_STK_SIZE + int "virtual com thread stack size" + default 512 + config RT_CDC_RX_BUFSIZE + int "virtual com rx buffer size" + default 128 + config RT_VCOM_TX_USE_DMA + bool "Enable to use dma for vcom tx" + default n + config RT_VCOM_SERNO + string "serial number of virtual com" + default "32021919830108" + config RT_VCOM_SER_LEN + int "serial number length of virtual com" + default 14 + config RT_VCOM_TX_TIMEOUT + int "tx timeout(ticks) of virtual com" + default 1000 + endif + if RT_USB_DEVICE_WINUSB + config RT_WINUSB_GUID + string "Guid for winusb" + default "{6860DC3C-C05F-4807-8807-1CA861CC1D66}" + endif + if RT_USB_DEVICE_MSTORAGE + config RT_USB_MSTORAGE_DISK_NAME + string "msc class disk name" + default "flash0" + endif + + if RT_USB_DEVICE_RNDIS + config RNDIS_DELAY_LINK_UP + bool "Delay linkup media connection" + select RT_USING_TIMER_SOFT + default n + endif + + if RT_USB_DEVICE_HID + config RT_USB_DEVICE_HID_KEYBOARD + bool "Use to HID device as Keyboard" + default n + if RT_USB_DEVICE_HID_KEYBOARD + config RT_USB_DEVICE_HID_KEYBOARD_NUMBER + int "Number of Keyboard(max 3)" + default 1 + range 1 3 + endif + config RT_USB_DEVICE_HID_MOUSE + bool "Use to HID device as Mouse" + default n + config RT_USB_DEVICE_HID_GENERAL + bool "Use to HID device as General HID device" + default y + if RT_USB_DEVICE_HID_GENERAL + config RT_USB_DEVICE_HID_GENERAL_OUT_REPORT_LENGTH + int "General HID device out report length" + default 63 + range 0 63 + + config RT_USB_DEVICE_HID_GENERAL_IN_REPORT_LENGTH + int "General HID device in report length" + default 63 + range 0 63 + endif + config RT_USB_DEVICE_HID_MEDIA + bool "Use to HID device as media keyboard" + default y + endif + if RT_USB_DEVICE_AUDIO + config RT_USB_DEVICE_AUDIO_MIC + bool "Use usb mic device as audio device" + default n + if RT_USB_DEVICE_AUDIO_MIC + config RT_USBD_MIC_DEVICE_NAME + string "audio mic device name" + default "mic0" + endif + config RT_USB_DEVICE_AUDIO_SPEAKER + bool "Use usb speaker device as audio device" + default n + if RT_USB_DEVICE_AUDIO_SPEAKER + config RT_USBD_SPEAKER_DEVICE_NAME + string "audio speaker device name" + default "sound0" + endif + endif + endif +endmenu diff --git a/components/legacy/usb/SConscript b/components/legacy/usb/SConscript new file mode 100644 index 00000000000..3e148cefe23 --- /dev/null +++ b/components/legacy/usb/SConscript @@ -0,0 +1,13 @@ +# for module compiling +import os +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) +Return('objs') diff --git a/components/drivers/usb/usbdevice/SConscript b/components/legacy/usb/usbdevice/SConscript similarity index 100% rename from components/drivers/usb/usbdevice/SConscript rename to components/legacy/usb/usbdevice/SConscript diff --git a/components/drivers/usb/usbdevice/class/audio_mic.c b/components/legacy/usb/usbdevice/class/audio_mic.c similarity index 100% rename from components/drivers/usb/usbdevice/class/audio_mic.c rename to components/legacy/usb/usbdevice/class/audio_mic.c diff --git a/components/drivers/usb/usbdevice/class/audio_speaker.c b/components/legacy/usb/usbdevice/class/audio_speaker.c similarity index 100% rename from components/drivers/usb/usbdevice/class/audio_speaker.c rename to components/legacy/usb/usbdevice/class/audio_speaker.c diff --git a/components/drivers/usb/usbdevice/class/cdc.h b/components/legacy/usb/usbdevice/class/cdc.h similarity index 100% rename from components/drivers/usb/usbdevice/class/cdc.h rename to components/legacy/usb/usbdevice/class/cdc.h diff --git a/components/drivers/usb/usbdevice/class/cdc_vcom.c b/components/legacy/usb/usbdevice/class/cdc_vcom.c similarity index 100% rename from components/drivers/usb/usbdevice/class/cdc_vcom.c rename to components/legacy/usb/usbdevice/class/cdc_vcom.c diff --git a/components/drivers/usb/usbdevice/class/ecm.c b/components/legacy/usb/usbdevice/class/ecm.c similarity index 100% rename from components/drivers/usb/usbdevice/class/ecm.c rename to components/legacy/usb/usbdevice/class/ecm.c diff --git a/components/drivers/usb/usbdevice/class/hid.c b/components/legacy/usb/usbdevice/class/hid.c similarity index 100% rename from components/drivers/usb/usbdevice/class/hid.c rename to components/legacy/usb/usbdevice/class/hid.c diff --git a/components/drivers/usb/usbdevice/class/hid.h b/components/legacy/usb/usbdevice/class/hid.h similarity index 100% rename from components/drivers/usb/usbdevice/class/hid.h rename to components/legacy/usb/usbdevice/class/hid.h diff --git a/components/drivers/usb/usbdevice/class/mstorage.c b/components/legacy/usb/usbdevice/class/mstorage.c similarity index 100% rename from components/drivers/usb/usbdevice/class/mstorage.c rename to components/legacy/usb/usbdevice/class/mstorage.c diff --git a/components/drivers/usb/usbdevice/class/mstorage.h b/components/legacy/usb/usbdevice/class/mstorage.h similarity index 100% rename from components/drivers/usb/usbdevice/class/mstorage.h rename to components/legacy/usb/usbdevice/class/mstorage.h diff --git a/components/drivers/usb/usbdevice/class/ndis.h b/components/legacy/usb/usbdevice/class/ndis.h similarity index 100% rename from components/drivers/usb/usbdevice/class/ndis.h rename to components/legacy/usb/usbdevice/class/ndis.h diff --git a/components/drivers/usb/usbdevice/class/rndis.c b/components/legacy/usb/usbdevice/class/rndis.c similarity index 100% rename from components/drivers/usb/usbdevice/class/rndis.c rename to components/legacy/usb/usbdevice/class/rndis.c diff --git a/components/drivers/usb/usbdevice/class/rndis.h b/components/legacy/usb/usbdevice/class/rndis.h similarity index 100% rename from components/drivers/usb/usbdevice/class/rndis.h rename to components/legacy/usb/usbdevice/class/rndis.h diff --git a/components/drivers/usb/usbdevice/class/uaudioreg.h b/components/legacy/usb/usbdevice/class/uaudioreg.h similarity index 100% rename from components/drivers/usb/usbdevice/class/uaudioreg.h rename to components/legacy/usb/usbdevice/class/uaudioreg.h diff --git a/components/drivers/usb/usbdevice/class/winusb.c b/components/legacy/usb/usbdevice/class/winusb.c similarity index 100% rename from components/drivers/usb/usbdevice/class/winusb.c rename to components/legacy/usb/usbdevice/class/winusb.c diff --git a/components/drivers/usb/usbdevice/class/winusb.h b/components/legacy/usb/usbdevice/class/winusb.h similarity index 100% rename from components/drivers/usb/usbdevice/class/winusb.h rename to components/legacy/usb/usbdevice/class/winusb.h diff --git a/components/drivers/usb/usbdevice/core/usbdevice.c b/components/legacy/usb/usbdevice/core/usbdevice.c similarity index 100% rename from components/drivers/usb/usbdevice/core/usbdevice.c rename to components/legacy/usb/usbdevice/core/usbdevice.c diff --git a/components/drivers/usb/usbdevice/core/usbdevice_core.c b/components/legacy/usb/usbdevice/core/usbdevice_core.c similarity index 100% rename from components/drivers/usb/usbdevice/core/usbdevice_core.c rename to components/legacy/usb/usbdevice/core/usbdevice_core.c diff --git a/components/drivers/usb/usbhost/SConscript b/components/legacy/usb/usbhost/SConscript similarity index 100% rename from components/drivers/usb/usbhost/SConscript rename to components/legacy/usb/usbhost/SConscript diff --git a/components/drivers/usb/usbhost/class/adk.c b/components/legacy/usb/usbhost/class/adk.c similarity index 100% rename from components/drivers/usb/usbhost/class/adk.c rename to components/legacy/usb/usbhost/class/adk.c diff --git a/components/drivers/usb/usbhost/class/adk.h b/components/legacy/usb/usbhost/class/adk.h similarity index 100% rename from components/drivers/usb/usbhost/class/adk.h rename to components/legacy/usb/usbhost/class/adk.h diff --git a/components/drivers/usb/usbhost/class/hid.c b/components/legacy/usb/usbhost/class/hid.c similarity index 100% rename from components/drivers/usb/usbhost/class/hid.c rename to components/legacy/usb/usbhost/class/hid.c diff --git a/components/drivers/usb/usbhost/class/hid.h b/components/legacy/usb/usbhost/class/hid.h similarity index 100% rename from components/drivers/usb/usbhost/class/hid.h rename to components/legacy/usb/usbhost/class/hid.h diff --git a/components/drivers/usb/usbhost/class/mass.c b/components/legacy/usb/usbhost/class/mass.c similarity index 100% rename from components/drivers/usb/usbhost/class/mass.c rename to components/legacy/usb/usbhost/class/mass.c diff --git a/components/drivers/usb/usbhost/class/mass.h b/components/legacy/usb/usbhost/class/mass.h similarity index 100% rename from components/drivers/usb/usbhost/class/mass.h rename to components/legacy/usb/usbhost/class/mass.h diff --git a/components/drivers/usb/usbhost/class/udisk.c b/components/legacy/usb/usbhost/class/udisk.c similarity index 100% rename from components/drivers/usb/usbhost/class/udisk.c rename to components/legacy/usb/usbhost/class/udisk.c diff --git a/components/drivers/usb/usbhost/class/ukbd.c b/components/legacy/usb/usbhost/class/ukbd.c similarity index 100% rename from components/drivers/usb/usbhost/class/ukbd.c rename to components/legacy/usb/usbhost/class/ukbd.c diff --git a/components/drivers/usb/usbhost/class/umouse.c b/components/legacy/usb/usbhost/class/umouse.c similarity index 100% rename from components/drivers/usb/usbhost/class/umouse.c rename to components/legacy/usb/usbhost/class/umouse.c diff --git a/components/drivers/usb/usbhost/core/driver.c b/components/legacy/usb/usbhost/core/driver.c similarity index 100% rename from components/drivers/usb/usbhost/core/driver.c rename to components/legacy/usb/usbhost/core/driver.c diff --git a/components/drivers/usb/usbhost/core/hub.c b/components/legacy/usb/usbhost/core/hub.c similarity index 100% rename from components/drivers/usb/usbhost/core/hub.c rename to components/legacy/usb/usbhost/core/hub.c diff --git a/components/drivers/usb/usbhost/core/usbhost.c b/components/legacy/usb/usbhost/core/usbhost.c similarity index 100% rename from components/drivers/usb/usbhost/core/usbhost.c rename to components/legacy/usb/usbhost/core/usbhost.c diff --git a/components/drivers/usb/usbhost/core/usbhost_core.c b/components/legacy/usb/usbhost/core/usbhost_core.c similarity index 100% rename from components/drivers/usb/usbhost/core/usbhost_core.c rename to components/legacy/usb/usbhost/core/usbhost_core.c