diff --git a/.github/ALL_BSP_COMPILE.json b/.github/ALL_BSP_COMPILE.json index 5a78a865e5e..2b896f265b6 100644 --- a/.github/ALL_BSP_COMPILE.json +++ b/.github/ALL_BSP_COMPILE.json @@ -53,12 +53,14 @@ "at32/at32f457-start", "at32/at32m412-start", "at32/at32m416-start", - "hc32/ev_hc32f4a0_lqfp176", - "hc32/ev_hc32f4a8_lqfp176", "hc32/ev_hc32f334_lqfp64", "hc32/ev_hc32f448_lqfp80", "hc32/ev_hc32f460_lqfp100_v2", + "hc32/ev_hc32f467_lqfp144", "hc32/ev_hc32f472_lqfp100", + "hc32/ev_hc32f4a0_lqfp176", + "hc32/ev_hc32f4a2_lqfp176", + "hc32/ev_hc32f4a8_lqfp176", "hc32/lckfb-hc32f4a0-lqfp100", "hc32l196", "hc32l136", diff --git "a/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" "b/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" index b2e3c102160..1ea5d2fbb24 100644 --- "a/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" +++ "b/bsp/hc32/docs/HC32\347\263\273\345\210\227BSP\345\210\266\344\275\234\346\225\231\347\250\213.md" @@ -227,7 +227,7 @@ HC32 BSP 的制作规范主要分为 3 个方面：工程配置，ENV 配置和 - 系统心跳统一设置为 1000（宏：RT_TICK_PER_SECOND） - BSP 中需要打开调试选项中的断言（宏：RT_DEBUG） -- 系统空闲线程栈大小统一设置为 256（宏：IDLE_THREAD_STACK_SIZE） +- 系统空闲线程栈大小统一设置为 512（宏：IDLE_THREAD_STACK_SIZE） - 开启组件自动初始化（宏：RT_USING_COMPONENTS_INIT） - 需要开启 user main 选项（宏：RT_USING_USER_MAIN） - FinSH 默认只使用 MSH 模式（宏：FINSH_USING_MSH_ONLY） diff --git "a/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" "b/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" index 6cfc4b402c3..36a07e7228d 100644 --- "a/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" +++ "b/bsp/hc32/docs/HC32\347\263\273\345\210\227\351\251\261\345\212\250\344\273\213\347\273\215.md" @@ -40,7 +40,7 @@ | 8 | [ADC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/adc/adc) | 测量管脚上的模拟量 | | 9 | [DAC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/dac/dac) | 通过管脚输出模拟量 | | 10 | [CAN](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/can/can) | 通过 CAN 收发数据 | -| 11 | [HWTIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/hwtimer/hwtimer) | 通过硬件定时器计时 | +| 11 | [CLOCK_TIMER](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/clock_timer/clock_timer) | 通过硬件定时器计时 | | 12 | [PWM](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/pwm/pwm) | 在特定的管脚输出 PWM 波形 | | 13 | [RTC](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/rtc/rtc) | 设置和读取时间 | | 14 | [WDT](https://www.rt-thread.org/document/site/#/rt-thread-version/rt-thread-standard/programming-manual/device/watchdog/watchdog) | 看门狗驱动 | diff --git a/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml index 84e83f68114..2fcf64d2937 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f334_lqfp64/.ci/attachconfig/ci.attachconfig.yml @@ -24,9 +24,9 @@ devices.flash: devices.gpio: kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f334_lqfp64/.config b/bsp/hc32/ev_hc32f334_lqfp64/.config index f88b9716ada..8c1d2ea196b 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/.config +++ b/bsp/hc32/ev_hc32f334_lqfp64/.config @@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set diff --git a/bsp/hc32/ev_hc32f334_lqfp64/README.md b/bsp/hc32/ev_hc32f334_lqfp64/README.md index a7e2ff21424..36242376cf8 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/README.md +++ b/bsp/hc32/ev_hc32f334_lqfp64/README.md @@ -46,7 +46,7 @@ EV_F334_LQ64 开发板常用 **板载资源** 如下： | DAC | 支持 | | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1...PF3 ---> PIN：0，1...68 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | MCAN | 支持 | | diff --git a/bsp/hc32/ev_hc32f334_lqfp64/applications/main.c b/bsp/hc32/ev_hc32f334_lqfp64/applications/main.c index 013a26633d4..aacd363b8f2 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/applications/main.c +++ b/bsp/hc32/ev_hc32f334_lqfp64/applications/main.c @@ -13,7 +13,7 @@ #include /* defined the LED_BLUE pin: PC13 */ -#define LED_BLUE_PIN GET_PIN(C, 13) +#define LED_BLUE_PIN GET_PIN(C, 13) int main(void) { diff --git a/bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c index 4b24e3ae667..d0d92b524cb 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c +++ b/bsp/hc32/ev_hc32f334_lqfp64/applications/xtal32_fcm.c @@ -18,8 +18,8 @@ #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) -#define XTAL32_FCM_THREAD_STACK_SIZE (1024) -#define XTAL32_FCM_UNIT (CM_FCM) +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM) /** * @brief This thread is used to monitor whether XTAL32 is stable. @@ -36,13 +36,13 @@ void xtal32_fcm_thread_entry(void *parameter) /* FCM config */ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); (void)FCM_StructInit(&stcFcmInit); - stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; - stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ - stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; - stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; - stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); - stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); /* Enable FCM, to ensure xtal32 stable */ FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig b/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig index a0367487403..74d429bcc13 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/Kconfig @@ -528,24 +528,24 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_CLOCK_TIMER - bool "Enable Hw Timer" + bool "Enable Clock Timer" default n select RT_USING_CLOCK_TIME if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 - bool "Use Timer_a1 As The Hw Timer" + bool "Use Timer_a1 As The Clock Timer" default n config BSP_USING_TMRA_2 - bool "Use Timer_a2 As The Hw Timer" + bool "Use Timer_a2 As The Clock Timer" default n config BSP_USING_TMRA_3 - bool "Use Timer_a3 As The Hw Timer" + bool "Use Timer_a3 As The Clock Timer" default n config BSP_USING_TMRA_4 - bool "Use Timer_a4 As The Hw Timer" + bool "Use Timer_a4 As The Clock Timer" default n config BSP_USING_TMRA_5 - bool "Use Timer_a5 As The Hw Timer" + bool "Use Timer_a5 As The Clock Timer" default n endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board.c b/bsp/hc32/ev_hc32f334_lqfp64/board/board.c index f5791403f24..aa105fcb8bb 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/board.c +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board.c @@ -12,9 +12,9 @@ #include "board_config.h" /* unlock/lock peripheral */ -#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ - LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) -#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) /** System Base Configuration */ @@ -54,9 +54,9 @@ void SystemClock_Config(void) GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); (void)CLK_XtalStructInit(&stcXtalInit); /* Config Xtal and enable Xtal */ - stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; - stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; - stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; (void)CLK_XtalInit(&stcXtalInit); @@ -82,8 +82,8 @@ void SystemClock_Config(void) /* Xtal32 config */ GPIO_AnalogCmd(XTAL32_PORT, XTAL32_PIN, ENABLE); (void)CLK_Xtal32StructInit(&stcXtal32Init); - stcXtal32Init.u8State = CLK_XTAL32_ON; - stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; (void)CLK_Xtal32Init(&stcXtal32Init); #endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board.h b/bsp/hc32/ev_hc32f334_lqfp64/board/board.h index 9976ff7bbd6..25ae127b30a 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/board.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board.h @@ -19,27 +19,27 @@ extern "C" { #endif -#define HC32_FLASH_ERASE_GRANULARITY (4 * 1024) -#define HC32_FLASH_WRITE_GRANULARITY (4) -#define HC32_FLASH_SIZE (128 * 1024) -#define HC32_FLASH_START_ADDRESS (0) -#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) +#define HC32_FLASH_ERASE_GRANULARITY (4 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (128 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) -#define HC32_SRAM_SIZE (32) -#define HC32_SRAM_END (0x1FFFC000 + HC32_SRAM_SIZE * 1024) +#define HC32_SRAM_SIZE (32) +#define HC32_SRAM_END (0x1FFFC000 + HC32_SRAM_SIZE * 1024) #ifdef __ARMCC_VERSION extern int Image$$RW_IRAM2$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) #elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) #else extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) +#define HEAP_BEGIN (&__bss_end) #endif -#define HEAP_END HC32_SRAM_END +#define HEAP_END HC32_SRAM_END void PeripheralRegister_Unlock(void); void PeripheralClock_Config(void); diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c index 46dc6f4c45f..5bd48b3c8bb 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.c @@ -141,13 +141,13 @@ void CanPhyEnable(void) #if defined(BSP_USING_MCAN1) GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinState = PIN_STAT_RST; - stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinDir = PIN_DIR_OUT; GPIO_Init(MCAN1_PHY_STBY_PORT, MCAN1_PHY_STBY_PIN, &stcGpioInit); #endif #if defined(BSP_USING_MCAN2) GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinState = PIN_STAT_RST; - stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinDir = PIN_DIR_OUT; GPIO_Init(MCAN2_PHY_STBY_PORT, MCAN2_PHY_STBY_PIN, &stcGpioInit); #endif } @@ -179,7 +179,7 @@ rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx) } #endif -#if defined (RT_USING_SPI) +#if defined(RT_USING_SPI) rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) { rt_err_t result = RT_EOK; @@ -194,10 +194,10 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; - (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); - GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); break; @@ -311,24 +311,24 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) #endif #endif -#if defined (BSP_USING_INPUT_CAPTURE) +#if defined(BSP_USING_INPUT_CAPTURE) rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) { rt_err_t result = RT_EOK; switch ((rt_uint32_t)tmr_instance) { -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) case (rt_uint32_t)CM_TMR6_1: GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) case (rt_uint32_t)CM_TMR6_2: GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) case (rt_uint32_t)CM_TMR6_3: GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC); break; diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h index 4fa4759a5df..91e15317356 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/board_config.h @@ -18,248 +18,248 @@ /************************* XTAL port **********************/ -#define XTAL_PORT (GPIO_PORT_F) -#define XTAL_IN_PIN (GPIO_PIN_00) -#define XTAL_OUT_PIN (GPIO_PIN_01) +#define XTAL_PORT (GPIO_PORT_F) +#define XTAL_IN_PIN (GPIO_PIN_00) +#define XTAL_OUT_PIN (GPIO_PIN_01) /************************ USART port **********************/ #if defined(BSP_USING_UART1) - #define USART1_RX_PORT (GPIO_PORT_B) - #define USART1_RX_PIN (GPIO_PIN_06) - #define USART1_RX_FUNC (GPIO_FUNC_33) +#define USART1_RX_PORT (GPIO_PORT_B) +#define USART1_RX_PIN (GPIO_PIN_06) +#define USART1_RX_FUNC (GPIO_FUNC_33) - #define USART1_TX_PORT (GPIO_PORT_B) - #define USART1_TX_PIN (GPIO_PIN_07) - #define USART1_TX_FUNC (GPIO_FUNC_32) +#define USART1_TX_PORT (GPIO_PORT_B) +#define USART1_TX_PIN (GPIO_PIN_07) +#define USART1_TX_FUNC (GPIO_FUNC_32) #endif #if defined(BSP_USING_UART2) - #define USART2_RX_PORT (GPIO_PORT_C) - #define USART2_RX_PIN (GPIO_PIN_04) - #define USART2_RX_FUNC (GPIO_FUNC_37) +#define USART2_RX_PORT (GPIO_PORT_C) +#define USART2_RX_PIN (GPIO_PIN_04) +#define USART2_RX_FUNC (GPIO_FUNC_37) - #define USART2_TX_PORT (GPIO_PORT_C) - #define USART2_TX_PIN (GPIO_PIN_10) - #define USART2_TX_FUNC (GPIO_FUNC_36) +#define USART2_TX_PORT (GPIO_PORT_C) +#define USART2_TX_PIN (GPIO_PIN_10) +#define USART2_TX_FUNC (GPIO_FUNC_36) #endif /************************ I2C port **********************/ #if defined(BSP_USING_I2C1) - #define I2C1_SDA_PORT (GPIO_PORT_B) - #define I2C1_SDA_PIN (GPIO_PIN_06) - #define I2C1_SDA_FUNC (GPIO_FUNC_52) +#define I2C1_SDA_PORT (GPIO_PORT_B) +#define I2C1_SDA_PIN (GPIO_PIN_06) +#define I2C1_SDA_FUNC (GPIO_FUNC_52) - #define I2C1_SCL_PORT (GPIO_PORT_B) - #define I2C1_SCL_PIN (GPIO_PIN_07) - #define I2C1_SCL_FUNC (GPIO_FUNC_53) +#define I2C1_SCL_PORT (GPIO_PORT_B) +#define I2C1_SCL_PIN (GPIO_PIN_07) +#define I2C1_SCL_FUNC (GPIO_FUNC_53) #endif /*********** ADC configure *********/ #if defined(BSP_USING_ADC1) - #define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */ - #define ADC1_CH_PIN (GPIO_PIN_00) +#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */ +#define ADC1_CH_PIN (GPIO_PIN_00) #endif #if defined(BSP_USING_ADC2) - #define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */ - #define ADC2_CH_PIN (GPIO_PIN_04) +#define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */ +#define ADC2_CH_PIN (GPIO_PIN_04) #endif #if defined(BSP_USING_ADC3) - #define ADC3_CH_PORT (GPIO_PORT_B) /* Default ADC3_IN1 */ - #define ADC3_CH_PIN (GPIO_PIN_13) +#define ADC3_CH_PORT (GPIO_PORT_B) /* Default ADC3_IN1 */ +#define ADC3_CH_PIN (GPIO_PIN_13) #endif /*********** DAC configure *********/ #if defined(BSP_USING_DAC1) - #define DAC1_CH1_PORT (GPIO_PORT_A) - #define DAC1_CH1_PIN (GPIO_PIN_04) - #define DAC1_CH2_PORT (GPIO_PORT_A) - #define DAC1_CH2_PIN (GPIO_PIN_05) +#define DAC1_CH1_PORT (GPIO_PORT_A) +#define DAC1_CH1_PIN (GPIO_PIN_04) +#define DAC1_CH2_PORT (GPIO_PORT_A) +#define DAC1_CH2_PIN (GPIO_PIN_05) #endif #if defined(BSP_USING_DAC2) - #define DAC2_CH1_PORT (GPIO_PORT_A) - #define DAC2_CH1_PIN (GPIO_PIN_06) +#define DAC2_CH1_PORT (GPIO_PORT_A) +#define DAC2_CH1_PIN (GPIO_PIN_06) #endif /*********** CAN configure *********/ #if defined(BSP_USING_MCAN1) - #define MCAN1_TX_PORT (GPIO_PORT_A) - #define MCAN1_TX_PIN (GPIO_PIN_02) - #define MCAN1_TX_PIN_FUNC (GPIO_FUNC_54) +#define MCAN1_TX_PORT (GPIO_PORT_A) +#define MCAN1_TX_PIN (GPIO_PIN_02) +#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_54) - #define MCAN1_RX_PORT (GPIO_PORT_C) - #define MCAN1_RX_PIN (GPIO_PIN_05) - #define MCAN1_RX_PIN_FUNC (GPIO_FUNC_55) +#define MCAN1_RX_PORT (GPIO_PORT_C) +#define MCAN1_RX_PIN (GPIO_PIN_05) +#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_55) - #define MCAN1_PHY_STBY_PORT (GPIO_PORT_B) - #define MCAN1_PHY_STBY_PIN (GPIO_PIN_01) +#define MCAN1_PHY_STBY_PORT (GPIO_PORT_B) +#define MCAN1_PHY_STBY_PIN (GPIO_PIN_01) #endif #if defined(BSP_USING_MCAN2) - #define MCAN2_TX_PORT (GPIO_PORT_B) - #define MCAN2_TX_PIN (GPIO_PIN_11) - #define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56) +#define MCAN2_TX_PORT (GPIO_PORT_B) +#define MCAN2_TX_PIN (GPIO_PIN_11) +#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56) - #define MCAN2_RX_PORT (GPIO_PORT_B) - #define MCAN2_RX_PIN (GPIO_PIN_10) - #define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57) +#define MCAN2_RX_PORT (GPIO_PORT_B) +#define MCAN2_RX_PIN (GPIO_PIN_10) +#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57) - #define MCAN2_PHY_STBY_PORT (GPIO_PORT_B) - #define MCAN2_PHY_STBY_PIN (GPIO_PIN_02) +#define MCAN2_PHY_STBY_PORT (GPIO_PORT_B) +#define MCAN2_PHY_STBY_PIN (GPIO_PIN_02) #endif /************************* SPI port ***********************/ #if defined(BSP_USING_SPI1) - #define SPI1_CS_PORT (GPIO_PORT_C) - #define SPI1_CS_PIN (GPIO_PIN_01) +#define SPI1_CS_PORT (GPIO_PORT_C) +#define SPI1_CS_PIN (GPIO_PIN_01) - #define SPI1_SCK_PORT (GPIO_PORT_B) - #define SPI1_SCK_PIN (GPIO_PIN_05) - #define SPI1_SCK_FUNC (GPIO_FUNC_49) +#define SPI1_SCK_PORT (GPIO_PORT_B) +#define SPI1_SCK_PIN (GPIO_PIN_05) +#define SPI1_SCK_FUNC (GPIO_FUNC_49) - #define SPI1_MOSI_PORT (GPIO_PORT_A) - #define SPI1_MOSI_PIN (GPIO_PIN_00) - #define SPI1_MOSI_FUNC (GPIO_FUNC_50) +#define SPI1_MOSI_PORT (GPIO_PORT_A) +#define SPI1_MOSI_PIN (GPIO_PIN_00) +#define SPI1_MOSI_FUNC (GPIO_FUNC_50) - #define SPI1_MISO_PORT (GPIO_PORT_A) - #define SPI1_MISO_PIN (GPIO_PIN_01) - #define SPI1_MISO_FUNC (GPIO_FUNC_51) +#define SPI1_MISO_PORT (GPIO_PORT_A) +#define SPI1_MISO_PIN (GPIO_PIN_01) +#define SPI1_MISO_FUNC (GPIO_FUNC_51) #endif /************************ RTC/PM *****************************/ #if defined(BSP_USING_RTC) || defined(RT_USING_PM) - #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) - #define XTAL32_PORT (GPIO_PORT_C) - #define XTAL32_PIN (GPIO_PIN_14 | GPIO_PIN_15) - #endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) +#define XTAL32_PORT (GPIO_PORT_C) +#define XTAL32_PIN (GPIO_PIN_14 | GPIO_PIN_15) +#endif #endif #if defined(RT_USING_PWM) /*********** PWM_TMRA configure *********/ - #if defined(BSP_USING_PWM_TMRA_1) - #if defined(BSP_USING_PWM_TMRA_1_CH1) - #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_00) - #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_15) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH2) - #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_01) - #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_15) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH3) - #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_02) - #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_15) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH4) - #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_03) - #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_15) - #endif - #endif +#if defined(BSP_USING_PWM_TMRA_1) +#if defined(BSP_USING_PWM_TMRA_1_CH1) +#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_00) +#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_15) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH2) +#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_01) +#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_15) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH3) +#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_02) +#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_15) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH4) +#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_03) +#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_15) +#endif +#endif /*********** PWM_TMR4 configure *********/ - #if defined(BSP_USING_PWM_TMR4_1) - #if defined(BSP_USING_PWM_TMR4_1_OUH) - #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_02) - #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OUL) - #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_01) - #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVH) - #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_06) - #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVL) - #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_04) - #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWH) - #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_07) - #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWL) - #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B) - #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_02) - #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OXH) - #define PWM_TMR4_1_OXH_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OXH_PIN (GPIO_PIN_01) - #define PWM_TMR4_1_OXH_PIN_FUNC (GPIO_FUNC_23) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OXL) - #define PWM_TMR4_1_OXL_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OXL_PIN (GPIO_PIN_00) - #define PWM_TMR4_1_OXL_PIN_FUNC (GPIO_FUNC_23) - #endif - #endif +#if defined(BSP_USING_PWM_TMR4_1) +#if defined(BSP_USING_PWM_TMR4_1_OUH) +#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_02) +#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OUL) +#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_01) +#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVH) +#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_06) +#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVL) +#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_04) +#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWH) +#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_07) +#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWL) +#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B) +#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_02) +#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OXH) +#define PWM_TMR4_1_OXH_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OXH_PIN (GPIO_PIN_01) +#define PWM_TMR4_1_OXH_PIN_FUNC (GPIO_FUNC_23) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OXL) +#define PWM_TMR4_1_OXL_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OXL_PIN (GPIO_PIN_00) +#define PWM_TMR4_1_OXL_PIN_FUNC (GPIO_FUNC_23) +#endif +#endif /*********** PWM_TMR6 configure *********/ - #if defined(BSP_USING_PWM_TMR6_1) - #if defined(BSP_USING_PWM_TMR6_1_A) - #define PWM_TMR6_1_A_PORT (GPIO_PORT_C) - #define PWM_TMR6_1_A_PIN (GPIO_PIN_00) - #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_12) - #endif - #if defined(BSP_USING_PWM_TMR6_1_B) - #define PWM_TMR6_1_B_PORT (GPIO_PORT_A) - #define PWM_TMR6_1_B_PIN (GPIO_PIN_00) - #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_12) - #endif - #endif +#if defined(BSP_USING_PWM_TMR6_1) +#if defined(BSP_USING_PWM_TMR6_1_A) +#define PWM_TMR6_1_A_PORT (GPIO_PORT_C) +#define PWM_TMR6_1_A_PIN (GPIO_PIN_00) +#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_12) +#endif +#if defined(BSP_USING_PWM_TMR6_1_B) +#define PWM_TMR6_1_B_PORT (GPIO_PORT_A) +#define PWM_TMR6_1_B_PIN (GPIO_PIN_00) +#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_12) +#endif +#endif #endif #if defined(BSP_USING_INPUT_CAPTURE) - #define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_14) - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) - #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_C) - #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_06) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) - #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_C) - #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) - #define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_B) - #define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_02) - #endif +#define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_14) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_C) +#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_06) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_C) +#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) +#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_B) +#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_02) +#endif #endif /*********** TMRA_PULSE_ENCODER configure *********/ #if defined(RT_USING_PULSE_ENCODER) - #if defined(BSP_USING_TMRA_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) - #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) - #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) - #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) - #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) - #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ - #endif /* BSP_USING_TMRA_PULSE_ENCODER */ - - #if defined(BSP_USING_TMR6_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) - #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) - #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05) - #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) - #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13) - #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ - #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) +#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#endif /* BSP_USING_TMRA_PULSE_ENCODER */ + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05) +#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13) +#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#endif /* BSP_USING_TMR6_PULSE_ENCODER */ #endif /* RT_USING_PULSE_ENCODER */ #endif diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h index 13bb213c9ad..58eb3aef102 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/adc_config.h @@ -20,42 +20,41 @@ extern "C" { #ifdef BSP_USING_ADC1 #ifndef ADC1_INIT_PARAMS -#define ADC1_INIT_PARAMS \ - { \ - .name = "adc1", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC1_INIT_PARAMS */ -#if defined (BSP_ADC1_USING_DMA) +#if defined(BSP_ADC1_USING_DMA) #ifndef ADC1_EOCA_DMA_CONFIG -#define ADC1_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC1_EOCA_DMA_INSTANCE, \ - .channel = ADC1_EOCA_DMA_CHANNEL, \ - .clock = ADC1_EOCA_DMA_CLOCK, \ - .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC1_EOCA, \ - .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC1_EOCA_DMA_IRQn, \ - .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ - .int_src = ADC1_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC1_EOCA_DMA_CONFIG */ #endif /* BSP_ADC1_USING_DMA */ @@ -63,42 +62,41 @@ extern "C" { #ifdef BSP_USING_ADC2 #ifndef ADC2_INIT_PARAMS -#define ADC2_INIT_PARAMS \ - { \ - .name = "adc2", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC2_INIT_PARAMS */ -#if defined (BSP_ADC2_USING_DMA) +#if defined(BSP_ADC2_USING_DMA) #ifndef ADC2_EOCA_DMA_CONFIG -#define ADC2_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC2_EOCA_DMA_INSTANCE, \ - .channel = ADC2_EOCA_DMA_CHANNEL, \ - .clock = ADC2_EOCA_DMA_CLOCK, \ - .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC2_EOCA, \ - .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC2_EOCA_DMA_IRQn, \ - .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ - .int_src = ADC2_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC2_EOCA_DMA_CONFIG */ #endif /* BSP_ADC2_USING_DMA */ @@ -106,42 +104,41 @@ extern "C" { #ifdef BSP_USING_ADC3 #ifndef ADC3_INIT_PARAMS -#define ADC3_INIT_PARAMS \ - { \ - .name = "adc3", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_TMR0_1_CMP_A, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC3_INIT_PARAMS */ -#if defined (BSP_ADC3_USING_DMA) +#if defined(BSP_ADC3_USING_DMA) #ifndef ADC3_EOCA_DMA_CONFIG -#define ADC3_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC3_EOCA_DMA_INSTANCE, \ - .channel = ADC3_EOCA_DMA_CHANNEL, \ - .clock = ADC3_EOCA_DMA_CLOCK, \ - .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC3_EOCA, \ - .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC3_EOCA_DMA_IRQn, \ - .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ - .int_src = ADC3_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC3_EOCA_DMA_CONFIG */ #endif /* BSP_ADC3_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h index e7bb3e89632..089240f4483 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/dac_config.h @@ -19,30 +19,30 @@ extern "C" { #ifdef BSP_USING_DAC1 #ifndef DAC1_INIT_PARAMS -#define DAC1_INIT_PARAMS \ - { \ - .name = "dac1", \ - .vref = 3300, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch2_output_enable = RT_TRUE, \ - .ch1_amp_enable = RT_TRUE, \ - .ch2_amp_enable = RT_TRUE, \ +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + .vref = 3300, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ #ifdef BSP_USING_DAC2 #ifndef DAC2_INIT_PARAMS -#define DAC2_INIT_PARAMS \ - { \ - .name = "dac2", \ - .vref = 3300, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch1_amp_enable = RT_TRUE, \ +#define DAC2_INIT_PARAMS \ + { \ + .name = "dac2", \ + .vref = 3300, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ } #endif /* DAC2_INIT_PARAMS */ #endif /* BSP_USING_DAC2 */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h index 64bda151cc6..25742dbe1af 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/dma_config.h @@ -20,168 +20,168 @@ extern "C" { /* DMA1 ch0 */ #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) -#define UART1_TX_DMA_INSTANCE CM_DMA -#define UART1_TX_DMA_CHANNEL DMA_CH0 -#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define UART1_TX_DMA_TRIG_SELECT AOS_DMA_0 -#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define UART1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define UART1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define UART1_TX_DMA_INT_SRC INT_SRC_DMA_TC0 +#define UART1_TX_DMA_INSTANCE CM_DMA +#define UART1_TX_DMA_CHANNEL DMA_CH0 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA_0 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA_TC0 #elif defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) -#define SPI1_TX_DMA_INSTANCE CM_DMA -#define SPI1_TX_DMA_CHANNEL DMA_CH0 -#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA_0 -#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SPI1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA_TC0 +#define SPI1_TX_DMA_INSTANCE CM_DMA +#define SPI1_TX_DMA_CHANNEL DMA_CH0 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA_0 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA_TC0 #endif /* DMA1 ch1 */ #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) -#define UART1_RX_DMA_INSTANCE CM_DMA -#define UART1_RX_DMA_CHANNEL DMA_CH1 -#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define UART1_RX_DMA_TRIG_SELECT AOS_DMA_1 -#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define UART1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define UART1_RX_DMA_INT_SRC INT_SRC_DMA_TC1 +#define UART1_RX_DMA_INSTANCE CM_DMA +#define UART1_RX_DMA_CHANNEL DMA_CH1 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA_1 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA_TC1 #elif defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) -#define SPI1_RX_DMA_INSTANCE CM_DMA -#define SPI1_RX_DMA_CHANNEL DMA_CH1 -#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA_1 -#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SPI1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA_TC1 +#define SPI1_RX_DMA_INSTANCE CM_DMA +#define SPI1_RX_DMA_CHANNEL DMA_CH1 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA_1 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA_TC1 #endif /* DMA1 ch2 */ #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) -#define UART2_TX_DMA_INSTANCE CM_DMA -#define UART2_TX_DMA_CHANNEL DMA_CH2 -#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define UART2_TX_DMA_TRIG_SELECT AOS_DMA_2 -#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define UART2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define UART2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define UART2_TX_DMA_INT_SRC INT_SRC_DMA_TC2 +#define UART2_TX_DMA_INSTANCE CM_DMA +#define UART2_TX_DMA_CHANNEL DMA_CH2 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA_2 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA_TC2 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) -#define I2C1_TX_DMA_INSTANCE CM_DMA -#define I2C1_TX_DMA_CHANNEL DMA_CH2 -#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA_2 -#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define I2C1_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA_TC2 +#define I2C1_TX_DMA_INSTANCE CM_DMA +#define I2C1_TX_DMA_CHANNEL DMA_CH2 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA_2 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA_TC2 #endif /* DMA1 ch3 */ #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) -#define UART2_RX_DMA_INSTANCE CM_DMA -#define UART2_RX_DMA_CHANNEL DMA_CH3 -#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define UART2_RX_DMA_TRIG_SELECT AOS_DMA_3 -#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define UART2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define UART2_RX_DMA_INT_SRC INT_SRC_DMA_TC3 +#define UART2_RX_DMA_INSTANCE CM_DMA +#define UART2_RX_DMA_CHANNEL DMA_CH3 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA_3 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA_TC3 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) -#define I2C1_RX_DMA_INSTANCE CM_DMA -#define I2C1_RX_DMA_CHANNEL DMA_CH3 -#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA_3 -#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define I2C1_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA_TC3 +#define I2C1_RX_DMA_INSTANCE CM_DMA +#define I2C1_RX_DMA_CHANNEL DMA_CH3 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA_3 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA_TC3 #endif /* DMA1 ch4 */ #if defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) -#define UART3_TX_DMA_INSTANCE CM_DMA -#define UART3_TX_DMA_CHANNEL DMA_CH4 -#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define UART3_TX_DMA_TRIG_SELECT AOS_DMA_4 -#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define UART3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define UART3_TX_DMA_INT_SRC INT_SRC_DMA_TC4 +#define UART3_TX_DMA_INSTANCE CM_DMA +#define UART3_TX_DMA_CHANNEL DMA_CH4 +#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART3_TX_DMA_TRIG_SELECT AOS_DMA_4 +#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define UART3_TX_DMA_INT_SRC INT_SRC_DMA_TC4 #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) -#define ADC1_EOCA_DMA_INSTANCE CM_DMA -#define ADC1_EOCA_DMA_CHANNEL DMA_CH4 -#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA_4 -#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA_TC4 +#define ADC1_EOCA_DMA_INSTANCE CM_DMA +#define ADC1_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA_4 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA_TC4 #endif /* DMA1 ch5 */ #if defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) -#define UART3_RX_DMA_INSTANCE CM_DMA -#define UART3_RX_DMA_CHANNEL DMA_CH5 -#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define UART3_RX_DMA_TRIG_SELECT AOS_DMA_5 -#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define UART3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define UART3_RX_DMA_INT_SRC INT_SRC_DMA_TC5 +#define UART3_RX_DMA_INSTANCE CM_DMA +#define UART3_RX_DMA_CHANNEL DMA_CH5 +#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART3_RX_DMA_TRIG_SELECT AOS_DMA_5 +#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define UART3_RX_DMA_INT_SRC INT_SRC_DMA_TC5 #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) -#define ADC2_EOCA_DMA_INSTANCE CM_DMA -#define ADC2_EOCA_DMA_CHANNEL DMA_CH5 -#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA_5 -#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA_TC5 +#define ADC2_EOCA_DMA_INSTANCE CM_DMA +#define ADC2_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA_5 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA_TC5 #endif /* DMA1 ch6 */ #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) -#define UART4_TX_DMA_INSTANCE CM_DMA -#define UART4_TX_DMA_CHANNEL DMA_CH6 -#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define UART4_TX_DMA_TRIG_SELECT AOS_DMA_6 -#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define UART4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM -#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO -#define UART4_TX_DMA_INT_SRC INT_SRC_DMA_TC6 +#define UART4_TX_DMA_INSTANCE CM_DMA +#define UART4_TX_DMA_CHANNEL DMA_CH6 +#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART4_TX_DMA_TRIG_SELECT AOS_DMA_6 +#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define UART4_TX_DMA_INT_SRC INT_SRC_DMA_TC6 #elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) -#define ADC3_EOCA_DMA_INSTANCE CM_DMA -#define ADC3_EOCA_DMA_CHANNEL DMA_CH6 -#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA_6 -#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM -#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO -#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA_TC6 +#define ADC3_EOCA_DMA_INSTANCE CM_DMA +#define ADC3_EOCA_DMA_CHANNEL DMA_CH6 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA_6 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA_TC6 #endif /* DMA1 ch7 */ #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) -#define UART4_RX_DMA_INSTANCE CM_DMA -#define UART4_RX_DMA_CHANNEL DMA_CH7 -#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) -#define UART4_RX_DMA_TRIG_SELECT AOS_DMA_7 -#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define UART4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM -#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO -#define UART4_RX_DMA_INT_SRC INT_SRC_DMA_TC7 +#define UART4_RX_DMA_INSTANCE CM_DMA +#define UART4_RX_DMA_CHANNEL DMA_CH7 +#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA | PWC_FCG0_AOS) +#define UART4_RX_DMA_TRIG_SELECT AOS_DMA_7 +#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define UART4_RX_DMA_INT_SRC INT_SRC_DMA_TC7 #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h index a1238ffe9a6..f13382a45b6 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/gpio_config.h @@ -22,146 +22,146 @@ extern "C" { #if defined(RT_USING_PIN) #ifndef EXTINT0_IRQ_CONFIG -#define EXTINT0_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT0_IRQ_NUM, \ - .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ0, \ +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT1_IRQ_CONFIG -#define EXTINT1_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT1_IRQ_NUM, \ - .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ1, \ +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT2_IRQ_CONFIG -#define EXTINT2_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT2_IRQ_NUM, \ - .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ2, \ +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ } #endif /* EXTINT2_IRQ_CONFIG */ #ifndef EXTINT3_IRQ_CONFIG -#define EXTINT3_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT3_IRQ_NUM, \ - .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ3, \ +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ } #endif /* EXTINT3_IRQ_CONFIG */ #ifndef EXTINT4_IRQ_CONFIG -#define EXTINT4_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT4_IRQ_NUM, \ - .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ4, \ +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ } #endif /* EXTINT4_IRQ_CONFIG */ #ifndef EXTINT5_IRQ_CONFIG -#define EXTINT5_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT5_IRQ_NUM, \ - .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ5, \ +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ } #endif /* EXTINT5_IRQ_CONFIG */ #ifndef EXTINT6_IRQ_CONFIG -#define EXTINT6_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT6_IRQ_NUM, \ - .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ6, \ +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ } #endif /* EXTINT6_IRQ_CONFIG */ #ifndef EXTINT7_IRQ_CONFIG -#define EXTINT7_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT7_IRQ_NUM, \ - .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ7, \ +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ } #endif /* EXTINT7_IRQ_CONFIG */ #ifndef EXTINT8_IRQ_CONFIG -#define EXTINT8_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT8_IRQ_NUM, \ - .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ8, \ +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ } #endif /* EXTINT8_IRQ_CONFIG */ #ifndef EXTINT9_IRQ_CONFIG -#define EXTINT9_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT9_IRQ_NUM, \ - .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ9, \ +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ } #endif /* EXTINT9_IRQ_CONFIG */ #ifndef EXTINT10_IRQ_CONFIG -#define EXTINT10_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT10_IRQ_NUM, \ - .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ10, \ +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ } #endif /* EXTINT10_IRQ_CONFIG */ #ifndef EXTINT11_IRQ_CONFIG -#define EXTINT11_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT11_IRQ_NUM, \ - .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ11, \ +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ } #endif /* EXTINT11_IRQ_CONFIG */ #ifndef EXTINT12_IRQ_CONFIG -#define EXTINT12_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT12_IRQ_NUM, \ - .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ12, \ +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ } #endif /* EXTINT12_IRQ_CONFIG */ #ifndef EXTINT13_IRQ_CONFIG -#define EXTINT13_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT13_IRQ_NUM, \ - .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ13, \ +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ } #endif /* EXTINT13_IRQ_CONFIG */ #ifndef EXTINT14_IRQ_CONFIG -#define EXTINT14_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT14_IRQ_NUM, \ - .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ14, \ +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ } #endif /* EXTINT14_IRQ_CONFIG */ #ifndef EXTINT15_IRQ_CONFIG -#define EXTINT15_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT15_IRQ_NUM, \ - .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ15, \ +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ } #endif /* EXTINT15_IRQ_CONFIG */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h index de883143386..cb4ebf9eceb 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/i2c_config.h @@ -20,51 +20,49 @@ extern "C" { #if defined(BSP_USING_I2C1) #ifndef I2C1_CONFIG -#define I2C1_CONFIG \ - { \ - .name = "i2c1", \ - .Instance = CM_I2C, \ - .clock = FCG1_PERIPH_I2C, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C, \ + .clock = FCG1_PERIPH_I2C, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C1_CONFIG */ #endif #if defined(BSP_I2C1_USING_DMA) #ifndef I2C1_TX_DMA_CONFIG -#define I2C1_TX_DMA_CONFIG \ - { \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .channel = I2C1_TX_DMA_CHANNEL, \ - .clock = I2C1_TX_DMA_CLOCK, \ - .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C_TEI, \ - .flag = I2C1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_TX_DMA_IRQn, \ - .irq_prio = I2C1_TX_DMA_INT_PRIO, \ - .int_src = I2C1_TX_DMA_INT_SRC, \ - }, \ +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_TX_DMA_CONFIG */ #ifndef I2C1_RX_DMA_CONFIG -#define I2C1_RX_DMA_CONFIG \ - { \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .channel = I2C1_RX_DMA_CHANNEL, \ - .clock = I2C1_RX_DMA_CLOCK, \ - .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C_RXI, \ - .flag = I2C1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_RX_DMA_IRQn, \ - .irq_prio = I2C1_RX_DMA_INT_PRIO, \ - .int_src = I2C1_RX_DMA_INT_SRC, \ - }, \ +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_RX_DMA_CONFIG */ #endif /* BSP_I2C1_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h index e968e9043fd..077f0e6dbf2 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/irq_config.h @@ -17,222 +17,222 @@ extern "C" { #endif -#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn -#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn -#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn -#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn -#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn -#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn -#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn -#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn -#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn -#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn -#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn -#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn -#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn -#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn -#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn -#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn -#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch0 */ -#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn -#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch1 */ -#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn -#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch2 */ -#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn -#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch3 */ -#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn -#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch4 */ -#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn -#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch5 */ -#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn -#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch6 */ -#define BSP_DMA1_CH6_IRQ_NUM INT006_IRQn -#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH6_IRQ_NUM INT006_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch7 */ -#define BSP_DMA1_CH7_IRQ_NUM INT007_IRQn -#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH7_IRQ_NUM INT007_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_USING_UART1) -#define BSP_UART1_IRQ_NUM USART1_IRQn -#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_IRQ_NUM USART1_IRQn +#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) -#define BSP_UART2_IRQ_NUM USART2_IRQn -#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_IRQ_NUM USART2_IRQn +#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) -#define BSP_UART3_IRQ_NUM USART3_IRQn -#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_IRQ_NUM USART3_IRQn +#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART3_TX_CPLT_IRQ_NUM USART3_TCI_IRQn -#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_CPLT_IRQ_NUM USART3_TCI_IRQn +#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART3 */ #if defined(BSP_USING_UART4) -#define BSP_UART4_IRQ_NUM USART4_IRQn -#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_IRQ_NUM USART4_IRQn +#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn -#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn +#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_SPI1) -#define BSP_SPI1_ERR_IRQ_NUM SPI_IRQn -#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI1_ERR_IRQ_NUM SPI_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif -#if defined (BSP_USING_QSPI) -#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn -#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#if defined(BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_QSPI */ #if defined(BSP_USING_TMRA_1) -#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn -#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_1 */ #if defined(BSP_USING_TMRA_2) -#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn -#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_2 */ #if defined(BSP_USING_TMRA_3) -#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn -#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_3 */ #if defined(BSP_USING_TMRA_4) -#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn -#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_4 */ #if defined(BSP_USING_TMRA_5) -#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn -#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_5 */ #if defined(BSP_USING_MCAN1) -#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn -#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn +#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN1 */ #if defined(BSP_USING_MCAN2) -#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn -#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn +#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN2 */ #if defined(RT_USING_ALARM) -#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn -#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* RT_USING_ALARM */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_2) -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_3) -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_4) -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_5) -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_2) -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ #if defined(BSP_USING_INPUT_CAPTURE) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT008_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT009_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT010_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT011_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT012_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT013_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM (INT014_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM (INT015_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT008_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT009_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT010_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT011_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #endif/* BSP_USING_INPUT_CAPTURE */ #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h index febd731d1d0..c3e8d7f52a9 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/mcan_config.h @@ -30,56 +30,56 @@ extern "C" { */ #ifdef RT_CAN_USING_CANFD -#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS -#define MCAN_TOTAL_FILTER_NUM (26U) -#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */ -#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */ -#define MCAN_TX_FIFO_NUM (6U) -#define MCAN_RX_FIFO_NUM (6U) -#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */ +#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS +#define MCAN_TOTAL_FILTER_NUM (26U) +#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */ +#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */ +#define MCAN_TX_FIFO_NUM (6U) +#define MCAN_RX_FIFO_NUM (6U) +#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */ #else -#define MCAN_FD_SEL MCAN_FD_CLASSICAL -#define MCAN_TOTAL_FILTER_NUM (32U) -#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */ -#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */ -#define MCAN_TX_FIFO_NUM (26U) -#define MCAN_RX_FIFO_NUM (26U) -#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */ +#define MCAN_FD_SEL MCAN_FD_CLASSICAL +#define MCAN_TOTAL_FILTER_NUM (32U) +#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */ +#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */ +#define MCAN_TX_FIFO_NUM (26U) +#define MCAN_RX_FIFO_NUM (26U) +#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */ #endif #ifdef BSP_USING_MCAN1 -#define MCAN1_NAME ("mcan1") -#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL) -#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ +#define MCAN1_NAME ("mcan1") +#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL) +#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ -#define MCAN1_FD_SEL MCAN_FD_SEL +#define MCAN1_FD_SEL MCAN_FD_SEL -#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM -#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM +#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM +#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM -#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM -#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM +#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM -#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U) +#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM +#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U) #endif /* BSP_USING_MCAN1 */ #ifdef BSP_USING_MCAN2 -#define MCAN2_NAME ("mcan2") -#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL) -#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ +#define MCAN2_NAME ("mcan2") +#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL) +#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ -#define MCAN2_FD_SEL MCAN_FD_SEL -#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM -#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM +#define MCAN2_FD_SEL MCAN_FD_SEL +#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM +#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM -#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM -#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM +#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM -#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U) +#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM +#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U) #endif /* BSP_USING_MCAN2 */ /***********************************************************************************************/ @@ -100,154 +100,154 @@ extern "C" { 2. For the corresponding function of u32TdcFilter, please refer to the reference manual for details(TDCR.TDCF). The u32TdcFilter can be get from PSR.TDCV. */ -#define MCAN_FD_CFG_500K_1M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 32, \ - .u32DataTimeSeg2 = 8, \ - .u32DataSyncJumpWidth = 8, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 32, \ - .u32TdcFilter = 32 + 1, \ +#define MCAN_FD_CFG_500K_1M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 32, \ + .u32DataTimeSeg2 = 8, \ + .u32DataSyncJumpWidth = 8, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 32, \ + .u32TdcFilter = 32 + 1, \ } -#define MCAN_FD_CFG_500K_2M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 16, \ - .u32DataTimeSeg2 = 4, \ - .u32DataSyncJumpWidth = 4, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 16, \ - .u32TdcFilter = 16 + 1, \ +#define MCAN_FD_CFG_500K_2M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 16, \ + .u32DataTimeSeg2 = 4, \ + .u32DataSyncJumpWidth = 4, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 16, \ + .u32TdcFilter = 16 + 1, \ } -#define MCAN_FD_CFG_500K_4M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 8, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 8, \ - .u32TdcFilter = 8 + 1, \ +#define MCAN_FD_CFG_500K_4M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 8, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 8, \ + .u32TdcFilter = 8 + 1, \ } -#define MCAN_FD_CFG_500K_5M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 6, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 6, \ - .u32TdcFilter = 6 + 1, \ +#define MCAN_FD_CFG_500K_5M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 6, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 6, \ + .u32TdcFilter = 6 + 1, \ } -#define MCAN_FD_CFG_500K_8M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 4, \ - .u32DataTimeSeg2 = 1, \ - .u32DataSyncJumpWidth = 1, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 4, \ - .u32TdcFilter = 4 + 1, \ +#define MCAN_FD_CFG_500K_8M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 4, \ + .u32DataTimeSeg2 = 1, \ + .u32DataSyncJumpWidth = 1, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 4, \ + .u32TdcFilter = 4 + 1, \ } -#define MCAN_FD_CFG_1M_1M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 32, \ - .u32DataTimeSeg2 = 8, \ - .u32DataSyncJumpWidth = 8, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 2*32, \ - .u32TdcFilter = 2*32 + 1, \ +#define MCAN_FD_CFG_1M_1M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 32, \ + .u32DataTimeSeg2 = 8, \ + .u32DataSyncJumpWidth = 8, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 2 * 32, \ + .u32TdcFilter = 2 * 32 + 1, \ } -#define MCAN_FD_CFG_1M_2M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 16, \ - .u32DataTimeSeg2 = 4, \ - .u32DataSyncJumpWidth = 4, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 16, \ - .u32TdcFilter = 16 + 1, \ +#define MCAN_FD_CFG_1M_2M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 16, \ + .u32DataTimeSeg2 = 4, \ + .u32DataSyncJumpWidth = 4, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 16, \ + .u32TdcFilter = 16 + 1, \ } -#define MCAN_FD_CFG_1M_4M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 8, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 8, \ - .u32TdcFilter = 8 + 1, \ +#define MCAN_FD_CFG_1M_4M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 8, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 8, \ + .u32TdcFilter = 8 + 1, \ } -#define MCAN_FD_CFG_1M_5M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 6, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 6, \ - .u32TdcFilter = 6 + 1, \ +#define MCAN_FD_CFG_1M_5M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 6, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 6, \ + .u32TdcFilter = 6 + 1, \ } -#define MCAN_FD_CFG_1M_8M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 4, \ - .u32DataTimeSeg2 = 1, \ - .u32DataSyncJumpWidth = 1, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 4, \ - .u32TdcFilter = 4 + 1, \ +#define MCAN_FD_CFG_1M_8M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 4, \ + .u32DataTimeSeg2 = 1, \ + .u32DataSyncJumpWidth = 1, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 4, \ + .u32TdcFilter = 4 + 1, \ } /* @@ -259,95 +259,95 @@ extern "C" { SamplePoint(%) = 16 / (16 + 4) = 80% The following bit rate configurations are based on the max MCAN Clock(40MHz). */ -#define MCAN_CC_CFG_1M \ - { \ - .u32NominalPrescaler = 2, \ - .u32NominalTimeSeg1 = 16, \ - .u32NominalTimeSeg2 = 4, \ - .u32NominalSyncJumpWidth = 4, \ +#define MCAN_CC_CFG_1M \ + { \ + .u32NominalPrescaler = 2, \ + .u32NominalTimeSeg1 = 16, \ + .u32NominalTimeSeg2 = 4, \ + .u32NominalSyncJumpWidth = 4, \ } -#define MCAN_CC_CFG_800K \ - { \ - .u32NominalPrescaler = 2, \ - .u32NominalTimeSeg1 = 20, \ - .u32NominalTimeSeg2 = 5, \ - .u32NominalSyncJumpWidth = 5, \ +#define MCAN_CC_CFG_800K \ + { \ + .u32NominalPrescaler = 2, \ + .u32NominalTimeSeg1 = 20, \ + .u32NominalTimeSeg2 = 5, \ + .u32NominalSyncJumpWidth = 5, \ } -#define MCAN_CC_CFG_500K \ - { \ - .u32NominalPrescaler = 4, \ - .u32NominalTimeSeg1 = 16, \ - .u32NominalTimeSeg2 = 4, \ - .u32NominalSyncJumpWidth = 4, \ +#define MCAN_CC_CFG_500K \ + { \ + .u32NominalPrescaler = 4, \ + .u32NominalTimeSeg1 = 16, \ + .u32NominalTimeSeg2 = 4, \ + .u32NominalSyncJumpWidth = 4, \ } -#define MCAN_CC_CFG_250K \ - { \ - .u32NominalPrescaler = 4, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_250K \ + { \ + .u32NominalPrescaler = 4, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_125K \ - { \ - .u32NominalPrescaler = 8, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_125K \ + { \ + .u32NominalPrescaler = 8, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_100K \ - { \ - .u32NominalPrescaler = 10, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_100K \ + { \ + .u32NominalPrescaler = 10, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_50K \ - { \ - .u32NominalPrescaler = 20, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_50K \ + { \ + .u32NominalPrescaler = 20, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_20K \ - { \ - .u32NominalPrescaler = 50, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_20K \ + { \ + .u32NominalPrescaler = 50, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_10K \ - { \ - .u32NominalPrescaler = 100, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_10K \ + { \ + .u32NominalPrescaler = 100, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } #ifdef RT_CAN_USING_CANFD -#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M -#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M -#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M +#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M +#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M +#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M -#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M -#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M -#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M +#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M +#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M +#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M #else -#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M -#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud -#define MCAN1_DATA_BAUD_RATE 0 +#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M +#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud +#define MCAN1_DATA_BAUD_RATE 0 -#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M -#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud -#define MCAN2_DATA_BAUD_RATE 0 +#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M +#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud +#define MCAN2_DATA_BAUD_RATE 0 #endif /* #ifdef RT_CAN_USING_CANFD */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h index 9804d7df223..4357f8e1130 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pm_config.h @@ -21,18 +21,18 @@ extern "C" { extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); #ifndef PM_TICKLESS_TIMER_ENABLE_MASK -#define PM_TICKLESS_TIMER_ENABLE_MASK \ -( (1UL << PM_SLEEP_MODE_IDLE) | \ - (1UL << PM_SLEEP_MODE_DEEP)) +#define PM_TICKLESS_TIMER_ENABLE_MASK \ + ((1UL << PM_SLEEP_MODE_IDLE) | \ + (1UL << PM_SLEEP_MODE_DEEP)) #endif /** * @brief run mode config @ref pm_run_mode_config structure */ #ifndef PM_RUN_MODE_CFG -#define PM_RUN_MODE_CFG \ - { \ - .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ } #endif /* PM_RUN_MODE_CFG */ @@ -40,50 +40,50 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); * @brief sleep idle config @ref pm_sleep_mode_idle_config structure */ #ifndef PM_SLEEP_IDLE_CFG -#define PM_SLEEP_IDLE_CFG \ -{ \ - .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ -} +#define PM_SLEEP_IDLE_CFG \ + { \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ + } #endif /*PM_SLEEP_IDLE_CFG*/ /** * @brief sleep deep config @ref pm_sleep_mode_deep_config structure */ #ifndef PM_SLEEP_DEEP_CFG -#define PM_SLEEP_DEEP_CFG \ -{ \ - { \ - .u16Clock = PWC_STOP_CLK_KEEP, \ - .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ - }, \ - .pwc_stop_type = PWC_STOP_WFE_INT, \ -} +#define PM_SLEEP_DEEP_CFG \ + { \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ + } #endif /*PM_SLEEP_DEEP_CFG*/ /** * @brief sleep standby config @ref pm_sleep_mode_standby_config structure */ #ifndef PM_SLEEP_STANDBY_CFG -#define PM_SLEEP_STANDBY_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD1, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - }, \ -} +#define PM_SLEEP_STANDBY_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + }, \ + } #endif /*PM_SLEEP_STANDBY_CFG*/ /** * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure */ #ifndef PM_SLEEP_SHUTDOWN_CFG -#define PM_SLEEP_SHUTDOWN_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD3, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - }, \ -} +#define PM_SLEEP_SHUTDOWN_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + }, \ + } #endif /*PM_SLEEP_SHUTDOWN_CFG*/ #endif /* BSP_USING_PM */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h index 5fa7584534e..0fccda7a252 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pulse_encoder_config.h @@ -21,182 +21,168 @@ extern "C" { #ifdef BSP_USING_PULSE_ENCODER_TMRA_1 #ifndef PULSE_ENCODER_TMRA_1_CONFIG -#define PULSE_ENCODER_TMRA_1_CONFIG \ - { \ - .tmr_handler = CM_TMRA_1, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a1" \ +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ } #endif /* PULSE_ENCODER_TMRA_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_2 #ifndef PULSE_ENCODER_TMRA_2_CONFIG -#define PULSE_ENCODER_TMRA_2_CONFIG \ - { \ - .tmr_handler = CM_TMRA_2, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a2" \ +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ } #endif /* PULSE_ENCODER_TMRA_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_3 #ifndef PULSE_ENCODER_TMRA_3_CONFIG -#define PULSE_ENCODER_TMRA_3_CONFIG \ - { \ - .tmr_handler = CM_TMRA_3, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a3" \ +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ } #endif /* PULSE_ENCODER_TMRA_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_4 #ifndef PULSE_ENCODER_TMRA_4_CONFIG -#define PULSE_ENCODER_TMRA_4_CONFIG \ - { \ - .tmr_handler = CM_TMRA_4, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a4" \ +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ } #endif /* PULSE_ENCODER_TMRA_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_5 #ifndef PULSE_ENCODER_TMRA_5_CONFIG -#define PULSE_ENCODER_TMRA_5_CONFIG \ - { \ - .tmr_handler = CM_TMRA_5, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a5" \ +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ } #endif /* PULSE_ENCODER_TMRA_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_1 #ifndef PULSE_ENCODER_TMR6_1_CONFIG -#define PULSE_ENCODER_TMR6_1_CONFIG \ - { \ - .tmr_handler = CM_TMR6_1, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_61" \ +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ } #endif /* PULSE_ENCODER_TMR6_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_2 #ifndef PULSE_ENCODER_TMR6_2_CONFIG -#define PULSE_ENCODER_TMR6_2_CONFIG \ - { \ - .tmr_handler = CM_TMR6_2, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_62" \ +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ } #endif /* PULSE_ENCODER_TMR6_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h index 651bbc22baa..ff0ef1b275f 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/pwm_tmr_config.h @@ -21,155 +21,135 @@ extern "C" { #ifdef BSP_USING_PWM_TMRA_1 #ifndef PWM_TMRA_1_CONFIG -#define PWM_TMRA_1_CONFIG \ - { \ - .name = "pwm_a1", \ - .instance = CM_TMRA_1, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_1_CONFIG */ #endif /* BSP_USING_PWM_TMRA_1 */ #ifdef BSP_USING_PWM_TMRA_2 #ifndef PWM_TMRA_2_CONFIG -#define PWM_TMRA_2_CONFIG \ - { \ - .name = "pwm_a2", \ - .instance = CM_TMRA_2, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_2_CONFIG */ #endif /* BSP_USING_PWM_TMRA_2 */ #ifdef BSP_USING_PWM_TMRA_3 #ifndef PWM_TMRA_3_CONFIG -#define PWM_TMRA_3_CONFIG \ - { \ - .name = "pwm_a3", \ - .instance = CM_TMRA_3, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_3_CONFIG */ #endif /* BSP_USING_PWM_TMRA_3 */ #ifdef BSP_USING_PWM_TMRA_4 #ifndef PWM_TMRA_4_CONFIG -#define PWM_TMRA_4_CONFIG \ - { \ - .name = "pwm_a4", \ - .instance = CM_TMRA_4, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_4_CONFIG */ #endif /* BSP_USING_PWM_TMRA_4 */ #ifdef BSP_USING_PWM_TMRA_5 #ifndef PWM_TMRA_5_CONFIG -#define PWM_TMRA_5_CONFIG \ - { \ - .name = "pwm_a5", \ - .instance = CM_TMRA_5, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_5_CONFIG */ #endif /* BSP_USING_PWM_TMRA_5 */ @@ -179,32 +159,29 @@ extern "C" { #ifdef BSP_USING_PWM_TMR4_1 #ifndef PWM_TMR4_1_CONFIG -#define PWM_TMR4_1_CONFIG \ - { \ - .name = "pwm_t41", \ - .instance = CM_TMR4, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_1_CONFIG */ #endif /* BSP_USING_PWM_TMR4_1 */ @@ -215,189 +192,169 @@ extern "C" { #ifdef BSP_USING_PWM_TMR6_1 #ifndef PWM_TMR6_1_CONFIG -#define PWM_TMR6_1_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_1, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_1_CONFIG */ #endif /* BSP_USING_PWM_TMR6_1 */ #ifdef BSP_USING_PWM_TMR6_2 #ifndef PWM_TMR6_2_CONFIG -#define PWM_TMR6_2_CONFIG \ - { \ - .name = "pwm_t62", \ - .instance = CM_TMR6_2, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t62", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_2_CONFIG */ #endif /* BSP_USING_PWM_TMR6_2 */ #ifdef BSP_USING_PWM_TMR6_3 #ifndef PWM_TMR6_3_CONFIG -#define PWM_TMR6_3_CONFIG \ - { \ - .name = "pwm_t63", \ - .instance = CM_TMR6_3, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t63", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_3_CONFIG */ #endif /* BSP_USING_PWM_TMR6_3 */ #ifdef BSP_USING_PWM_TMR6_4 #ifndef PWM_TMR6_4_CONFIG -#define PWM_TMR6_4_CONFIG \ - { \ - .name = "pwm_t64", \ - .instance = CM_TMR6_4, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t64", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_4_CONFIG */ #endif /* BSP_USING_PWM_TMR6_4 */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h index 9789abe9dfb..495680fa307 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/spi_config.h @@ -21,58 +21,55 @@ extern "C" { #ifdef BSP_USING_SPI1 #ifndef SPI1_BUS_CONFIG -#define SPI1_BUS_CONFIG \ - { \ - .Instance = CM_SPI, \ - .bus_name = "spi1", \ - .clock = FCG1_PERIPH_SPI, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI_SPEI, \ - }, \ +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI_SPEI, \ + }, \ } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .clock = SPI1_TX_DMA_CLOCK, \ - .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI_SPTI, \ - .flag = SPI1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_TX_DMA_IRQn, \ - .irq_prio = SPI1_TX_DMA_INT_PRIO, \ - .int_src = SPI1_TX_DMA_INT_SRC, \ - } \ +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .clock = SPI1_RX_DMA_CLOCK, \ - .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI_SPRI, \ - .flag = SPI1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_RX_DMA_IRQn, \ - .irq_prio = SPI1_RX_DMA_INT_PRIO, \ - .int_src = SPI1_RX_DMA_INT_SRC, \ - } \ +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h index 44d3362b803..2f56df2f339 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/timer_config.h @@ -19,95 +19,90 @@ extern "C" { #ifdef BSP_USING_TMRA_1 #ifndef TMRA_1_CONFIG -#define TMRA_1_CONFIG \ - { \ - .tmr_handle = CM_TMRA_1, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_1, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_1_OVF, \ - .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ - }, \ - .name = "tmra_1" \ +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ } #endif /* TMRA_1_CONFIG */ #endif /* BSP_USING_TMRA_1 */ #ifdef BSP_USING_TMRA_2 #ifndef TMRA_2_CONFIG -#define TMRA_2_CONFIG \ - { \ - .tmr_handle = CM_TMRA_2, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_2, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_2_OVF, \ - .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ - }, \ - .name = "tmra_2" \ +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ } #endif /* TMRA_2_CONFIG */ #endif /* BSP_USING_TMRA_2 */ #ifdef BSP_USING_TMRA_3 #ifndef TMRA_3_CONFIG -#define TMRA_3_CONFIG \ - { \ - .tmr_handle = CM_TMRA_3, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_3, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_3_OVF, \ - .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ - }, \ - .name = "tmra_3" \ +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ } #endif /* TMRA_3_CONFIG */ #endif /* BSP_USING_TMRA_3 */ #ifdef BSP_USING_TMRA_4 #ifndef TMRA_4_CONFIG -#define TMRA_4_CONFIG \ - { \ - .tmr_handle = CM_TMRA_4, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_4, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_4_OVF, \ - .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ - }, \ - .name = "tmra_4" \ +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ } #endif /* TMRA_4_CONFIG */ #endif /* BSP_USING_TMRA_4 */ #ifdef BSP_USING_TMRA_5 #ifndef TMRA_5_CONFIG -#define TMRA_5_CONFIG \ - { \ - .tmr_handle = CM_TMRA_5, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_5, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_5_OVF, \ - .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ - }, \ - .name = "tmra_5" \ +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ } #endif /* TMRA_5_CONFIG */ #endif /* BSP_USING_TMRA_5 */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h index d147ec7d084..a9ad8b21029 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/tmr_capture_config.h @@ -17,64 +17,64 @@ extern "C" { #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) #define IC1_NAME "ic1" -#define INPUT_CAPTURE_CFG_TMR6_1 \ -{ \ - .name = IC1_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_1 \ + { \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) #define IC2_NAME "ic2" -#define INPUT_CAPTURE_CFG_TMR6_2 \ -{ \ - .name = IC2_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_2 \ + { \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) #define IC3_NAME "ic3" -#define INPUT_CAPTURE_CFG_TMR6_3 \ -{ \ - .name = IC3_NAME, \ - .ch = TMR6_CH_B, \ - .clk_div = TMR6_CLK_DIV16, \ - .first_edge = TMR6_CAPT_COND_TRIGD_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_3 \ + { \ + .name = IC3_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGD_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_4) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_4) #define IC4_NAME "ic4" -#define INPUT_CAPTURE_CFG_TMR6_4 \ -{ \ - .name = IC4_NAME, \ - .ch = TMR6_CH_B, \ - .clk_div = TMR6_CLK_DIV16, \ - .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_4 \ + { \ + .name = IC4_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_4_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_4_OVF_IRQ_PRIO, \ + } #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h b/bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h index 13b166e9431..c604fd98e16 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/config/uart_config.h @@ -21,90 +21,86 @@ extern "C" { #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = CM_USART1, \ - .clock = FCG3_PERIPH_USART1, \ - .irq_num = BSP_UART1_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART1_EI, \ - .rx_int_src = INT_SRC_USART1_RI, \ - .tx_int_src = INT_SRC_USART1_TI, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .irq_num = BSP_UART1_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART1_EI, \ + .rx_int_src = INT_SRC_USART1_RI, \ + .tx_int_src = INT_SRC_USART1_TI, \ } #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .clock = UART1_RX_DMA_CLOCK, \ - .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_RI, \ - .flag = UART1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_RX_DMA_IRQn, \ - .irq_prio = UART1_RX_DMA_INT_PRIO, \ - .int_src = UART1_RX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_RX_CONFIG */ #ifndef UART1_RXTO_CONFIG -#define UART1_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ } #endif /* UART1_RXTO_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #endif /* UART1_TX_CPLT_CONFIG */ #if defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .clock = UART1_TX_DMA_CLOCK, \ - .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_TI, \ - .flag = UART1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_TX_DMA_IRQn, \ - .irq_prio = UART1_TX_DMA_INT_PRIO, \ - .int_src = UART1_TX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -112,90 +108,86 @@ extern "C" { #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = CM_USART2, \ - .clock = FCG3_PERIPH_USART2, \ - .irq_num = BSP_UART2_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART2_EI, \ - .rx_int_src = INT_SRC_USART2_RI, \ - .tx_int_src = INT_SRC_USART2_TI, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .irq_num = BSP_UART2_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART2_EI, \ + .rx_int_src = INT_SRC_USART2_RI, \ + .tx_int_src = INT_SRC_USART2_TI, \ } #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .clock = UART2_RX_DMA_CLOCK, \ - .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_RI, \ - .flag = UART2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_RX_DMA_IRQn, \ - .irq_prio = UART2_RX_DMA_INT_PRIO, \ - .int_src = UART2_RX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_RX_CONFIG */ #ifndef UART2_RXTO_CONFIG -#define UART2_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ } #endif /* UART2_RXTO_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #endif /* UART2_TX_CPLT_CONFIG */ #if defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .clock = UART2_TX_DMA_CLOCK, \ - .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_TI, \ - .flag = UART2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_TX_DMA_IRQn, \ - .irq_prio = UART2_TX_DMA_INT_PRIO, \ - .int_src = UART2_TX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -203,90 +195,86 @@ extern "C" { #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = CM_USART3, \ - .clock = FCG3_PERIPH_USART3, \ - .irq_num = BSP_UART3_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART3_EI, \ - .rx_int_src = INT_SRC_USART3_RI, \ - .tx_int_src = INT_SRC_USART3_TI, \ +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .irq_num = BSP_UART3_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART3_EI, \ + .rx_int_src = INT_SRC_USART3_RI, \ + .tx_int_src = INT_SRC_USART3_TI, \ } #endif /* UART3_CONFIG */ #if defined(BSP_UART3_RX_USING_DMA) #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .channel = UART3_RX_DMA_CHANNEL, \ - .clock = UART3_RX_DMA_CLOCK, \ - .trigger_select = UART3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART3_RI, \ - .flag = UART3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART3_RX_DMA_IRQn, \ - .irq_prio = UART3_RX_DMA_INT_PRIO, \ - .int_src = UART3_RX_DMA_INT_SRC, \ - }, \ +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .channel = UART3_RX_DMA_CHANNEL, \ + .clock = UART3_RX_DMA_CLOCK, \ + .trigger_select = UART3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART3_RI, \ + .flag = UART3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART3_RX_DMA_IRQn, \ + .irq_prio = UART3_RX_DMA_INT_PRIO, \ + .int_src = UART3_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART3_DMA_RX_CONFIG */ #ifndef UART3_RXTO_CONFIG -#define UART3_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ +#define UART3_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ } #endif /* UART3_RXTO_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA) #ifndef UART3_TX_CPLT_CONFIG -#define UART3_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TCI, \ - }, \ +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART3_TX_CPLT_CONFIG -#define UART3_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TCI, \ - }, \ +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ } #endif #endif /* UART3_TX_CPLT_CONFIG */ #if defined(BSP_UART3_TX_USING_DMA) #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .channel = UART3_TX_DMA_CHANNEL, \ - .clock = UART3_TX_DMA_CLOCK, \ - .trigger_select = UART3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART3_TI, \ - .flag = UART3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART3_TX_DMA_IRQn, \ - .irq_prio = UART3_TX_DMA_INT_PRIO, \ - .int_src = UART3_TX_DMA_INT_SRC, \ - }, \ +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .channel = UART3_TX_DMA_CHANNEL, \ + .clock = UART3_TX_DMA_CLOCK, \ + .trigger_select = UART3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART3_TI, \ + .flag = UART3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART3_TX_DMA_IRQn, \ + .irq_prio = UART3_TX_DMA_INT_PRIO, \ + .int_src = UART3_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ @@ -294,90 +282,86 @@ extern "C" { #if defined(BSP_USING_UART4) #ifndef UART4_CONFIG -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = CM_USART4, \ - .clock = FCG3_PERIPH_USART4, \ - .irq_num = BSP_UART4_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART4_EI, \ - .rx_int_src = INT_SRC_USART4_RI, \ - .tx_int_src = INT_SRC_USART4_TI, \ +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .irq_num = BSP_UART4_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART4_EI, \ + .rx_int_src = INT_SRC_USART4_RI, \ + .tx_int_src = INT_SRC_USART4_TI, \ } #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .channel = UART4_RX_DMA_CHANNEL, \ - .clock = UART4_RX_DMA_CLOCK, \ - .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART4_RI, \ - .flag = UART4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART4_RX_DMA_IRQn, \ - .irq_prio = UART4_RX_DMA_INT_PRIO, \ - .int_src = UART4_RX_DMA_INT_SRC, \ - }, \ +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .clock = UART4_RX_DMA_CLOCK, \ + .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_RI, \ + .flag = UART4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART4_RX_DMA_IRQn, \ + .irq_prio = UART4_RX_DMA_INT_PRIO, \ + .int_src = UART4_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART4_DMA_RX_CONFIG */ #ifndef UART4_RXTO_CONFIG -#define UART4_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ +#define UART4_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ } #endif /* UART4_RXTO_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #endif /* UART4_TX_CPLT_CONFIG */ #if defined(BSP_UART4_TX_USING_DMA) #ifndef UART4_DMA_TX_CONFIG -#define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .channel = UART4_TX_DMA_CHANNEL, \ - .clock = UART4_TX_DMA_CLOCK, \ - .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART4_TI, \ - .flag = UART4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART4_TX_DMA_IRQn, \ - .irq_prio = UART4_TX_DMA_INT_PRIO, \ - .int_src = UART4_TX_DMA_INT_SRC, \ - }, \ +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .clock = UART4_TX_DMA_CLOCK, \ + .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_TI, \ + .flag = UART4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART4_TX_DMA_IRQn, \ + .irq_prio = UART4_TX_DMA_INT_PRIO, \ + .int_src = UART4_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART4_DMA_TX_CONFIG */ #endif /* BSP_UART4_TX_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h b/bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h index c6927993ad7..5ee7d3e9197 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/hc32f3xx_conf.h @@ -27,8 +27,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -48,48 +47,48 @@ extern "C" * Library. * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. */ -#define LL_ICG_ENABLE (DDL_ON) -#define LL_UTILITY_ENABLE (DDL_ON) -#define LL_PRINT_ENABLE (DDL_OFF) +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) -#define LL_ADC_ENABLE (DDL_ON) -#define LL_AOS_ENABLE (DDL_ON) -#define LL_CLK_ENABLE (DDL_ON) -#define LL_CMP_ENABLE (DDL_ON) -#define LL_CRC_ENABLE (DDL_ON) -#define LL_CTC_ENABLE (DDL_ON) -#define LL_DAC_ENABLE (DDL_ON) -#define LL_DBGC_ENABLE (DDL_OFF) -#define LL_DMA_ENABLE (DDL_ON) -#define LL_EFM_ENABLE (DDL_ON) -#define LL_EMB_ENABLE (DDL_ON) -#define LL_EVENT_PORT_ENABLE (DDL_OFF) -#define LL_FCG_ENABLE (DDL_ON) -#define LL_FCM_ENABLE (DDL_ON) -#define LL_HRPWM_ENABLE (DDL_ON) -#define LL_GPIO_ENABLE (DDL_ON) -#define LL_I2C_ENABLE (DDL_ON) -#define LL_INTERRUPTS_ENABLE (DDL_ON) -#define LL_MCAN_ENABLE (DDL_ON) -#define LL_MPU_ENABLE (DDL_ON) -#define LL_PLA_ENABLE (DDL_ON) -#define LL_PWC_ENABLE (DDL_ON) -#define LL_RMU_ENABLE (DDL_ON) -#define LL_RTC_ENABLE (DDL_ON) -#define LL_SPI_ENABLE (DDL_ON) -#define LL_SRAM_ENABLE (DDL_ON) -#define LL_SWDT_ENABLE (DDL_ON) -#define LL_TMR0_ENABLE (DDL_ON) -#define LL_TMR4_ENABLE (DDL_ON) -#define LL_TMR6_ENABLE (DDL_ON) -#define LL_TMRA_ENABLE (DDL_ON) -#define LL_USART_ENABLE (DDL_ON) -#define LL_WDT_ENABLE (DDL_ON) +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_HRPWM_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_MCAN_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_PLA_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) /** * @brief The following is a list of currently supported BSP boards. */ -#define BSP_EV_HC32F334_LQFP64 (1U) +#define BSP_EV_HC32F334_LQFP64 (1U) /** * @brief The macro BSP_EV_HC32F3XX is used to specify the BSP board currently @@ -98,15 +97,15 @@ extern "C" * @note If there is no supported BSP board or the BSP function is not used, * the value needs to be set to 0U. */ -#define BSP_EV_HC32F3XX (0U) +#define BSP_EV_HC32F3XX (0U) /** * @brief This is the list of BSP components to be used. * Select the components you need to use to DDL_ON. */ -#define BSP_24CXX_ENABLE (DDL_OFF) -#define BSP_W25QXX_ENABLE (DDL_OFF) -#define BSP_INT_KEY_ENABLE (DDL_OFF) +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_INT_KEY_ENABLE (DDL_OFF) /******************************************************************************* * Global variable definitions ('extern') diff --git a/bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h index e0071375474..d302aacfbf1 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/board/ports/fal_cfg.h @@ -23,20 +23,20 @@ extern const struct fal_flash_dev hc32_onchip_flash; extern struct fal_flash_dev ext_nor_flash0; /* flash device table */ -#define FAL_FLASH_DEV_TABLE \ -{ \ - &hc32_onchip_flash, \ - &ext_nor_flash0, \ -} +#define FAL_FLASH_DEV_TABLE \ + { \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ + } /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ -#define FAL_PART_TABLE \ -{ \ - {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 128 * 1024, 0}, \ - {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ -} +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 128 * 1024, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \ + } #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h b/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h index 959fac2be73..7935d7a9bda 100644 --- a/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h +++ b/bsp/hc32/ev_hc32f334_lqfp64/rtconfig.h @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 /* kservice options */ @@ -326,14 +326,6 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ - -/* HPMicro SDK */ - -/* end of HPMicro SDK */ - -/* FT32 HAL & SDK Drivers */ - -/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml index 7eb2f098c02..38498a3c9b4 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f448_lqfp80/.ci/attachconfig/ci.attachconfig.yml @@ -22,11 +22,11 @@ devices.flash: - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SFUD=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f448_lqfp80/.config b/bsp/hc32/ev_hc32f448_lqfp80/.config index 2abef75e924..562533d9e4e 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/.config +++ b/bsp/hc32/ev_hc32f448_lqfp80/.config @@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set diff --git a/bsp/hc32/ev_hc32f448_lqfp80/README.md b/bsp/hc32/ev_hc32f448_lqfp80/README.md index e614500cca8..362bce9d743 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/README.md +++ b/bsp/hc32/ev_hc32f448_lqfp80/README.md @@ -47,7 +47,7 @@ EV_F448_LQ80 开发板常用 **板载资源** 如下： | DAC | 支持 | | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1...PH2 ---> PIN：0，1...82 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | MCAN | 支持 | | diff --git a/bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c index 0e356713230..a189bed9b8b 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c +++ b/bsp/hc32/ev_hc32f448_lqfp80/applications/xtal32_fcm.c @@ -19,7 +19,7 @@ #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) -#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) /** * @brief This thread is used to monitor whether XTAL32 is stable. @@ -36,13 +36,13 @@ void xtal32_fcm_thread_entry(void *parameter) /* FCM config */ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); (void)FCM_StructInit(&stcFcmInit); - stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; - stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ - stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; - stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; - stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); - stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); (void)FCM_Init(&stcFcmInit); /* Enable FCM, to ensure xtal32 stable */ FCM_Cmd(ENABLE); diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig b/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig index 76940804952..e0f7eb0c5b9 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/Kconfig @@ -641,24 +641,24 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_CLOCK_TIMER - bool "Enable Hw Timer" + bool "Enable Clock Timer" default n select RT_USING_CLOCK_TIME if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 - bool "Use Timer_a1 As The Hw Timer" + bool "Use Timer_a1 As The Clock Timer" default n config BSP_USING_TMRA_2 - bool "Use Timer_a2 As The Hw Timer" + bool "Use Timer_a2 As The Clock Timer" default n config BSP_USING_TMRA_3 - bool "Use Timer_a3 As The Hw Timer" + bool "Use Timer_a3 As The Clock Timer" default n config BSP_USING_TMRA_4 - bool "Use Timer_a4 As The Hw Timer" + bool "Use Timer_a4 As The Clock Timer" default n config BSP_USING_TMRA_5 - bool "Use Timer_a5 As The Hw Timer" + bool "Use Timer_a5 As The Clock Timer" default n endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/board.c b/bsp/hc32/ev_hc32f448_lqfp80/board/board.c index 3b821593e6d..b8382bd1aff 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/board.c +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/board.c @@ -14,9 +14,9 @@ #include "board_config.h" /* unlock/lock peripheral */ -#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ - LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) -#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) /** System Base Configuration */ @@ -58,9 +58,9 @@ void SystemClock_Config(void) GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); (void)CLK_XtalStructInit(&stcXtalInit); /* Config Xtal and enable Xtal */ - stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; - stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; - stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; (void)CLK_XtalInit(&stcXtalInit); @@ -86,8 +86,8 @@ void SystemClock_Config(void) /* Xtal32 config */ GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); (void)CLK_Xtal32StructInit(&stcXtal32Init); - stcXtal32Init.u8State = CLK_XTAL32_ON; - stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; (void)CLK_Xtal32Init(&stcXtal32Init); #endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/board.h b/bsp/hc32/ev_hc32f448_lqfp80/board/board.h index 085bc2d6f64..399804e8e44 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/board.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/board.h @@ -20,27 +20,27 @@ extern "C" { #endif -#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) -#define HC32_FLASH_WRITE_GRANULARITY (4) -#define HC32_FLASH_SIZE (256 * 1024) -#define HC32_FLASH_START_ADDRESS (0) -#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) +#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (256 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) -#define HC32_SRAM_SIZE (64) -#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024) +#define HC32_SRAM_SIZE (64) +#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024) #ifdef __ARMCC_VERSION extern int Image$$RW_IRAM2$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) #elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) #else extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) +#define HEAP_BEGIN (&__bss_end) #endif -#define HEAP_END HC32_SRAM_END +#define HEAP_END HC32_SRAM_END void PeripheralRegister_Unlock(void); void PeripheralClock_Config(void); diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c index 2df8c3583a1..e780a4e7764 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.c @@ -184,7 +184,7 @@ rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx) } #endif -#if defined (RT_USING_SPI) +#if defined(RT_USING_SPI) rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) { rt_err_t result = RT_EOK; @@ -198,17 +198,17 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) case (rt_uint32_t)CM_SPI1: GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinState = PIN_STAT_SET; - stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinDir = PIN_DIR_OUT; GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; - (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); - GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); break; @@ -332,19 +332,19 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) #endif #endif -#if defined (BSP_USING_INPUT_CAPTURE) +#if defined(BSP_USING_INPUT_CAPTURE) rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) { rt_err_t result = RT_EOK; switch ((rt_uint32_t)tmr_instance) { -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) case (rt_uint32_t)CM_TMR6_1: GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_1_FUNC); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) case (rt_uint32_t)CM_TMR6_2: GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_2_FUNC); break; @@ -358,7 +358,7 @@ rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) #endif #ifdef RT_USING_PM -#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) +#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) { switch (run_mode) @@ -385,8 +385,8 @@ rt_err_t rt_hw_qspi_board_init(void) (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; #ifndef BSP_QSPI_USING_SOFT_CS - (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); - GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); #endif (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h index b67c66df7cf..55479faeaef 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/board_config.h @@ -19,304 +19,304 @@ /************************* XTAL port **********************/ -#define XTAL_PORT (GPIO_PORT_H) -#define XTAL_IN_PIN (GPIO_PIN_00) -#define XTAL_OUT_PIN (GPIO_PIN_01) +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_IN_PIN (GPIO_PIN_00) +#define XTAL_OUT_PIN (GPIO_PIN_01) /************************ USART port **********************/ #if defined(BSP_USING_UART1) - #define USART1_RX_PORT (GPIO_PORT_A) - #define USART1_RX_PIN (GPIO_PIN_10) - #define USART1_RX_FUNC (GPIO_FUNC_33) +#define USART1_RX_PORT (GPIO_PORT_A) +#define USART1_RX_PIN (GPIO_PIN_10) +#define USART1_RX_FUNC (GPIO_FUNC_33) - #define USART1_TX_PORT (GPIO_PORT_A) - #define USART1_TX_PIN (GPIO_PIN_09) - #define USART1_TX_FUNC (GPIO_FUNC_32) +#define USART1_TX_PORT (GPIO_PORT_A) +#define USART1_TX_PIN (GPIO_PIN_09) +#define USART1_TX_FUNC (GPIO_FUNC_32) #endif #if defined(BSP_USING_UART2) - #define USART2_RX_PORT (GPIO_PORT_C) - #define USART2_RX_PIN (GPIO_PIN_11) - #define USART2_RX_FUNC (GPIO_FUNC_37) +#define USART2_RX_PORT (GPIO_PORT_C) +#define USART2_RX_PIN (GPIO_PIN_11) +#define USART2_RX_FUNC (GPIO_FUNC_37) - #define USART2_TX_PORT (GPIO_PORT_C) - #define USART2_TX_PIN (GPIO_PIN_10) - #define USART2_TX_FUNC (GPIO_FUNC_36) +#define USART2_TX_PORT (GPIO_PORT_C) +#define USART2_TX_PIN (GPIO_PIN_10) +#define USART2_TX_FUNC (GPIO_FUNC_36) #endif #if defined(BSP_USING_UART6) - #define USART6_RX_PORT (GPIO_PORT_D) - #define USART6_RX_PIN (GPIO_PIN_01) - #define USART6_RX_FUNC (GPIO_FUNC_55) +#define USART6_RX_PORT (GPIO_PORT_D) +#define USART6_RX_PIN (GPIO_PIN_01) +#define USART6_RX_FUNC (GPIO_FUNC_55) - #define USART6_TX_PORT (GPIO_PORT_D) - #define USART6_TX_PIN (GPIO_PIN_02) - #define USART6_TX_FUNC (GPIO_FUNC_54) +#define USART6_TX_PORT (GPIO_PORT_D) +#define USART6_TX_PIN (GPIO_PIN_02) +#define USART6_TX_FUNC (GPIO_FUNC_54) #endif /************************ I2C port **********************/ #if defined(BSP_USING_I2C1) - #define I2C1_SDA_PORT (GPIO_PORT_E) - #define I2C1_SDA_PIN (GPIO_PIN_00) - #define I2C1_SDA_FUNC (GPIO_FUNC_48) +#define I2C1_SDA_PORT (GPIO_PORT_E) +#define I2C1_SDA_PIN (GPIO_PIN_00) +#define I2C1_SDA_FUNC (GPIO_FUNC_48) - #define I2C1_SCL_PORT (GPIO_PORT_E) - #define I2C1_SCL_PIN (GPIO_PIN_01) - #define I2C1_SCL_FUNC (GPIO_FUNC_49) +#define I2C1_SCL_PORT (GPIO_PORT_E) +#define I2C1_SCL_PIN (GPIO_PIN_01) +#define I2C1_SCL_FUNC (GPIO_FUNC_49) #endif #if defined(BSP_USING_I2C2) // TODO, ch2 for test only - #define I2C2_SDA_PORT (GPIO_PORT_A) - #define I2C2_SDA_PIN (GPIO_PIN_09) - #define I2C2_SDA_FUNC (GPIO_FUNC_50) +#define I2C2_SDA_PORT (GPIO_PORT_A) +#define I2C2_SDA_PIN (GPIO_PIN_09) +#define I2C2_SDA_FUNC (GPIO_FUNC_50) - #define I2C2_SCL_PORT (GPIO_PORT_A) - #define I2C2_SCL_PIN (GPIO_PIN_10) - #define I2C2_SCL_FUNC (GPIO_FUNC_51) +#define I2C2_SCL_PORT (GPIO_PORT_A) +#define I2C2_SCL_PIN (GPIO_PIN_10) +#define I2C2_SCL_FUNC (GPIO_FUNC_51) #endif /*********** ADC configure *********/ #if defined(BSP_USING_ADC1) - #define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */ - #define ADC1_CH_PIN (GPIO_PIN_00) +#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */ +#define ADC1_CH_PIN (GPIO_PIN_00) #endif #if defined(BSP_USING_ADC2) - #define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */ - #define ADC2_CH_PIN (GPIO_PIN_04) +#define ADC2_CH_PORT (GPIO_PORT_A) /* Default ADC12_IN4 */ +#define ADC2_CH_PIN (GPIO_PIN_04) #endif #if defined(BSP_USING_ADC3) - #define ADC3_CH_PORT (GPIO_PORT_E) /* Default ADC3_IN1 */ - #define ADC3_CH_PIN (GPIO_PIN_03) +#define ADC3_CH_PORT (GPIO_PORT_E) /* Default ADC3_IN1 */ +#define ADC3_CH_PIN (GPIO_PIN_03) #endif /*********** DAC configure *********/ #if defined(BSP_USING_DAC1) - #define DAC1_CH1_PORT (GPIO_PORT_A) - #define DAC1_CH1_PIN (GPIO_PIN_04) - #define DAC1_CH2_PORT (GPIO_PORT_A) - #define DAC1_CH2_PIN (GPIO_PIN_05) +#define DAC1_CH1_PORT (GPIO_PORT_A) +#define DAC1_CH1_PIN (GPIO_PIN_04) +#define DAC1_CH2_PORT (GPIO_PORT_A) +#define DAC1_CH2_PIN (GPIO_PIN_05) #endif /*********** CAN configure *********/ #if defined(BSP_USING_MCAN1) - #define MCAN1_TX_PORT (GPIO_PORT_C) - #define MCAN1_TX_PIN (GPIO_PIN_12) - #define MCAN1_TX_PIN_FUNC (GPIO_FUNC_56) +#define MCAN1_TX_PORT (GPIO_PORT_C) +#define MCAN1_TX_PIN (GPIO_PIN_12) +#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_56) - #define MCAN1_RX_PORT (GPIO_PORT_D) - #define MCAN1_RX_PIN (GPIO_PIN_00) - #define MCAN1_RX_PIN_FUNC (GPIO_FUNC_57) +#define MCAN1_RX_PORT (GPIO_PORT_D) +#define MCAN1_RX_PIN (GPIO_PIN_00) +#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_57) #endif #if defined(BSP_USING_MCAN2) - #define MCAN2_TX_PORT (GPIO_PORT_H) - #define MCAN2_TX_PIN (GPIO_PIN_02) - #define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56) +#define MCAN2_TX_PORT (GPIO_PORT_H) +#define MCAN2_TX_PIN (GPIO_PIN_02) +#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_56) - #define MCAN2_RX_PORT (GPIO_PORT_E) - #define MCAN2_RX_PIN (GPIO_PIN_04) - #define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57) +#define MCAN2_RX_PORT (GPIO_PORT_E) +#define MCAN2_RX_PIN (GPIO_PIN_04) +#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_57) #endif /************************* SPI port ***********************/ #if defined(BSP_USING_SPI1) - #define SPI1_CS_PORT (GPIO_PORT_C) - #define SPI1_CS_PIN (GPIO_PIN_07) +#define SPI1_CS_PORT (GPIO_PORT_C) +#define SPI1_CS_PIN (GPIO_PIN_07) - #define SPI1_SCK_PORT (GPIO_PORT_B) - #define SPI1_SCK_PIN (GPIO_PIN_14) - #define SPI1_SCK_FUNC (GPIO_FUNC_47) +#define SPI1_SCK_PORT (GPIO_PORT_B) +#define SPI1_SCK_PIN (GPIO_PIN_14) +#define SPI1_SCK_FUNC (GPIO_FUNC_47) - #define SPI1_MOSI_PORT (GPIO_PORT_B) - #define SPI1_MOSI_PIN (GPIO_PIN_13) - #define SPI1_MOSI_FUNC (GPIO_FUNC_44) +#define SPI1_MOSI_PORT (GPIO_PORT_B) +#define SPI1_MOSI_PIN (GPIO_PIN_13) +#define SPI1_MOSI_FUNC (GPIO_FUNC_44) - #define SPI1_MISO_PORT (GPIO_PORT_D) - #define SPI1_MISO_PIN (GPIO_PIN_09) - #define SPI1_MISO_FUNC (GPIO_FUNC_45) +#define SPI1_MISO_PORT (GPIO_PORT_D) +#define SPI1_MISO_PIN (GPIO_PIN_09) +#define SPI1_MISO_FUNC (GPIO_FUNC_45) - #define SPI1_WP_PORT (GPIO_PORT_D) - #define SPI1_WP_PIN (GPIO_PIN_10) +#define SPI1_WP_PORT (GPIO_PORT_D) +#define SPI1_WP_PIN (GPIO_PIN_10) - #define SPI1_HOLD_PORT (GPIO_PORT_D) - #define SPI1_HOLD_PIN (GPIO_PIN_11) +#define SPI1_HOLD_PORT (GPIO_PORT_D) +#define SPI1_HOLD_PIN (GPIO_PIN_11) #endif /************************ RTC/PM *****************************/ #if defined(BSP_USING_RTC) || defined(RT_USING_PM) - #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) - #define XTAL32_PORT (GPIO_PORT_C) - #define XTAL32_IN_PIN (GPIO_PIN_14) - #define XTAL32_OUT_PIN (GPIO_PIN_15) - #endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) +#define XTAL32_PORT (GPIO_PORT_C) +#define XTAL32_IN_PIN (GPIO_PIN_14) +#define XTAL32_OUT_PIN (GPIO_PIN_15) +#endif #endif #if defined(RT_USING_PWM) /*********** PWM_TMRA configure *********/ - #if defined(BSP_USING_PWM_TMRA_1) - #if defined(BSP_USING_PWM_TMRA_1_CH1) - #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) - #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH2) - #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) - #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH3) - #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) - #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH4) - #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) - #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) - #endif - #endif - - #if defined(BSP_USING_PWM_TMRA_2) - #if defined(BSP_USING_PWM_TMRA_2_CH1) - #define PWM_TMRA_2_CH1_PORT (GPIO_PORT_A) - #define PWM_TMRA_2_CH1_PIN (GPIO_PIN_00) - #define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_2_CH2) - #define PWM_TMRA_2_CH2_PORT (GPIO_PORT_A) - #define PWM_TMRA_2_CH2_PIN (GPIO_PIN_01) - #define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_2_CH3) - #define PWM_TMRA_2_CH3_PORT (GPIO_PORT_A) - #define PWM_TMRA_2_CH3_PIN (GPIO_PIN_02) - #define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_2_CH4) - #define PWM_TMRA_2_CH4_PORT (GPIO_PORT_A) - #define PWM_TMRA_2_CH4_PIN (GPIO_PIN_03) - #define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_4) - #endif - #endif +#if defined(BSP_USING_PWM_TMRA_1) +#if defined(BSP_USING_PWM_TMRA_1_CH1) +#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) +#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH2) +#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) +#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH3) +#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) +#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH4) +#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) +#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) +#endif +#endif + +#if defined(BSP_USING_PWM_TMRA_2) +#if defined(BSP_USING_PWM_TMRA_2_CH1) +#define PWM_TMRA_2_CH1_PORT (GPIO_PORT_A) +#define PWM_TMRA_2_CH1_PIN (GPIO_PIN_00) +#define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_2_CH2) +#define PWM_TMRA_2_CH2_PORT (GPIO_PORT_A) +#define PWM_TMRA_2_CH2_PIN (GPIO_PIN_01) +#define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_2_CH3) +#define PWM_TMRA_2_CH3_PORT (GPIO_PORT_A) +#define PWM_TMRA_2_CH3_PIN (GPIO_PIN_02) +#define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_2_CH4) +#define PWM_TMRA_2_CH4_PORT (GPIO_PORT_A) +#define PWM_TMRA_2_CH4_PIN (GPIO_PIN_03) +#define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_4) +#endif +#endif /*********** PWM_TMR4 configure *********/ - #if defined(BSP_USING_PWM_TMR4_1) - #if defined(BSP_USING_PWM_TMR4_1_OUH) - #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_08) - #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OUL) - #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_07) - #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVH) - #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_09) - #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVL) - #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_B) - #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_00) - #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWH) - #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A) - #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10) - #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWL) - #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B) - #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_01) - #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) - #endif - #endif +#if defined(BSP_USING_PWM_TMR4_1) +#if defined(BSP_USING_PWM_TMR4_1_OUH) +#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_08) +#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OUL) +#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_07) +#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVH) +#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_09) +#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVL) +#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_B) +#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_00) +#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWH) +#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_A) +#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10) +#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWL) +#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_B) +#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_01) +#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) +#endif +#endif /*********** PWM_TMR6 configure *********/ - #if defined(BSP_USING_PWM_TMR6_1) - #if defined(BSP_USING_PWM_TMR6_1_A) - #define PWM_TMR6_1_A_PORT (GPIO_PORT_A) - #define PWM_TMR6_1_A_PIN (GPIO_PIN_08) - #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #endif - #if defined(BSP_USING_PWM_TMR6_1_B) - #define PWM_TMR6_1_B_PORT (GPIO_PORT_A) - #define PWM_TMR6_1_B_PIN (GPIO_PIN_07) - #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif - #endif +#if defined(BSP_USING_PWM_TMR6_1) +#if defined(BSP_USING_PWM_TMR6_1_A) +#define PWM_TMR6_1_A_PORT (GPIO_PORT_A) +#define PWM_TMR6_1_A_PIN (GPIO_PIN_08) +#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#endif +#if defined(BSP_USING_PWM_TMR6_1_B) +#define PWM_TMR6_1_B_PORT (GPIO_PORT_A) +#define PWM_TMR6_1_B_PIN (GPIO_PIN_07) +#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif +#endif #endif #if defined(BSP_USING_INPUT_CAPTURE) - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) - #define INPUT_CAPTURE_TMR6_1_FUNC (GPIO_FUNC_3) - #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A) - #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) - #define INPUT_CAPTURE_TMR6_2_FUNC (GPIO_FUNC_3) - #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B) - #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02) - #endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +#define INPUT_CAPTURE_TMR6_1_FUNC (GPIO_FUNC_3) +#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A) +#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +#define INPUT_CAPTURE_TMR6_2_FUNC (GPIO_FUNC_3) +#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B) +#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02) +#endif #endif #if defined(BSP_USING_QSPI) - #ifndef BSP_QSPI_USING_SOFT_CS +#ifndef BSP_QSPI_USING_SOFT_CS /* QSSN */ - #define QSPI_FLASH_CS_PORT (GPIO_PORT_C) - #define QSPI_FLASH_CS_PIN (GPIO_PIN_07) - #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_7) - #endif +#define QSPI_FLASH_CS_PORT (GPIO_PORT_C) +#define QSPI_FLASH_CS_PIN (GPIO_PIN_07) +#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_7) +#endif /* QSCK */ - #define QSPI_FLASH_SCK_PORT (GPIO_PORT_B) - #define QSPI_FLASH_SCK_PIN (GPIO_PIN_14) - #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_7) +#define QSPI_FLASH_SCK_PORT (GPIO_PORT_B) +#define QSPI_FLASH_SCK_PIN (GPIO_PIN_14) +#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_7) /* QSIO0 */ - #define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) - #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_7) +#define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) +#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_7) /* QSIO1 */ - #define QSPI_FLASH_IO1_PORT (GPIO_PORT_D) - #define QSPI_FLASH_IO1_PIN (GPIO_PIN_09) - #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_7) +#define QSPI_FLASH_IO1_PORT (GPIO_PORT_D) +#define QSPI_FLASH_IO1_PIN (GPIO_PIN_09) +#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_7) /* QSIO2 */ - #define QSPI_FLASH_IO2_PORT (GPIO_PORT_D) - #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) - #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_7) +#define QSPI_FLASH_IO2_PORT (GPIO_PORT_D) +#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) +#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_7) /* QSIO3 */ - #define QSPI_FLASH_IO3_PORT (GPIO_PORT_D) - #define QSPI_FLASH_IO3_PIN (GPIO_PIN_11) - #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_7) +#define QSPI_FLASH_IO3_PORT (GPIO_PORT_D) +#define QSPI_FLASH_IO3_PIN (GPIO_PIN_11) +#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_7) #endif /*********** TMRA_PULSE_ENCODER configure *********/ #if defined(RT_USING_PULSE_ENCODER) - #if defined(BSP_USING_TMRA_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) - #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) - #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) - #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) - #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) - #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ - #endif /* BSP_USING_TMRA_PULSE_ENCODER */ - - #if defined(BSP_USING_TMR6_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) - #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) - #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05) - #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) - #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13) - #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ - #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) +#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#endif /* BSP_USING_TMRA_PULSE_ENCODER */ + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_05) +#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_13) +#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#endif /* BSP_USING_TMR6_PULSE_ENCODER */ #endif /* RT_USING_PULSE_ENCODER */ #endif diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h index be6d4c6de34..a1fd5cc950a 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/adc_config.h @@ -20,42 +20,41 @@ extern "C" { #ifdef BSP_USING_ADC1 #ifndef ADC1_INIT_PARAMS -#define ADC1_INIT_PARAMS \ - { \ - .name = "adc1", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC1_INIT_PARAMS */ -#if defined (BSP_ADC1_USING_DMA) +#if defined(BSP_ADC1_USING_DMA) #ifndef ADC1_EOCA_DMA_CONFIG -#define ADC1_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC1_EOCA_DMA_INSTANCE, \ - .channel = ADC1_EOCA_DMA_CHANNEL, \ - .clock = ADC1_EOCA_DMA_CLOCK, \ - .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC1_EOCA, \ - .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC1_EOCA_DMA_IRQn, \ - .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ - .int_src = ADC1_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC1_EOCA_DMA_CONFIG */ #endif /* BSP_ADC1_USING_DMA */ @@ -63,42 +62,41 @@ extern "C" { #ifdef BSP_USING_ADC2 #ifndef ADC2_INIT_PARAMS -#define ADC2_INIT_PARAMS \ - { \ - .name = "adc2", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC2_INIT_PARAMS */ -#if defined (BSP_ADC2_USING_DMA) +#if defined(BSP_ADC2_USING_DMA) #ifndef ADC2_EOCA_DMA_CONFIG -#define ADC2_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC2_EOCA_DMA_INSTANCE, \ - .channel = ADC2_EOCA_DMA_CHANNEL, \ - .clock = ADC2_EOCA_DMA_CLOCK, \ - .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC2_EOCA, \ - .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC2_EOCA_DMA_IRQn, \ - .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ - .int_src = ADC2_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC2_EOCA_DMA_CONFIG */ #endif /* BSP_ADC2_USING_DMA */ @@ -106,42 +104,41 @@ extern "C" { #ifdef BSP_USING_ADC3 #ifndef ADC3_INIT_PARAMS -#define ADC3_INIT_PARAMS \ - { \ - .name = "adc3", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC3_INIT_PARAMS */ -#if defined (BSP_ADC3_USING_DMA) +#if defined(BSP_ADC3_USING_DMA) #ifndef ADC3_EOCA_DMA_CONFIG -#define ADC3_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC3_EOCA_DMA_INSTANCE, \ - .channel = ADC3_EOCA_DMA_CHANNEL, \ - .clock = ADC3_EOCA_DMA_CLOCK, \ - .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC3_EOCA, \ - .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC3_EOCA_DMA_IRQn, \ - .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ - .int_src = ADC3_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC3_EOCA_DMA_CONFIG */ #endif /* BSP_ADC3_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h index 610e3f5b2e5..88866454c91 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dac_config.h @@ -19,18 +19,18 @@ extern "C" { #ifdef BSP_USING_DAC1 #ifndef DAC1_INIT_PARAMS -#define DAC1_INIT_PARAMS \ - { \ - .name = "dac1", \ - .vref = 3300, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch2_output_enable = RT_TRUE, \ - .ch1_data_src = DAC_DATA_SRC_DATAREG, \ - .ch2_data_src = DAC_DATA_SRC_DATAREG, \ - .ch1_amp_enable = RT_TRUE, \ - .ch2_amp_enable = RT_TRUE, \ +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + .vref = 3300, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h index b5202f3eb93..76bab92f27e 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/dma_config.h @@ -21,248 +21,248 @@ extern "C" { /* DMA1 ch0 */ #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) -#define SPI1_RX_DMA_INSTANCE CM_DMA1 -#define SPI1_RX_DMA_CHANNEL DMA_CH0 -#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) -#define SPI3_RX_DMA_INSTANCE CM_DMA1 -#define SPI3_RX_DMA_CHANNEL DMA_CH0 -#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH0 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) -#define I2C1_TX_DMA_INSTANCE CM_DMA1 -#define I2C1_TX_DMA_CHANNEL DMA_CH0 -#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 -#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 #endif /* DMA1 ch1 */ #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) -#define SPI1_TX_DMA_INSTANCE CM_DMA1 -#define SPI1_TX_DMA_CHANNEL DMA_CH1 -#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) -#define SPI3_TX_DMA_INSTANCE CM_DMA1 -#define SPI3_TX_DMA_CHANNEL DMA_CH1 -#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH1 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) -#define I2C1_RX_DMA_INSTANCE CM_DMA1 -#define I2C1_RX_DMA_CHANNEL DMA_CH1 -#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 -#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 #endif /* DMA1 ch2 */ #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) -#define SPI2_RX_DMA_INSTANCE CM_DMA1 -#define SPI2_RX_DMA_CHANNEL DMA_CH2 -#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) -#define I2C2_TX_DMA_INSTANCE CM_DMA1 -#define I2C2_TX_DMA_CHANNEL DMA_CH2 -#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 -#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 #endif /* DMA1 ch3 */ #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) -#define SPI2_TX_DMA_INSTANCE CM_DMA1 -#define SPI2_TX_DMA_CHANNEL DMA_CH3 -#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) -#define I2C2_RX_DMA_INSTANCE CM_DMA1 -#define I2C2_RX_DMA_CHANNEL DMA_CH3 -#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 -#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) -#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 -#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 -#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 #endif /* DMA1 ch4 */ #if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) -#define UART5_RX_DMA_INSTANCE CM_DMA1 -#define UART5_RX_DMA_CHANNEL DMA_CH4 -#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4 -#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define UART5_RX_DMA_INSTANCE CM_DMA1 +#define UART5_RX_DMA_CHANNEL DMA_CH4 +#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) -#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 -#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 -#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 #endif /* DMA1 ch5 */ #if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) -#define UART5_TX_DMA_INSTANCE CM_DMA1 -#define UART5_TX_DMA_CHANNEL DMA_CH5 -#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5 -#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define UART5_TX_DMA_INSTANCE CM_DMA1 +#define UART5_TX_DMA_CHANNEL DMA_CH5 +#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 #elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) -#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 -#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 -#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 #endif /* DMA2 ch0 */ #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) -#define UART1_RX_DMA_INSTANCE CM_DMA2 -#define UART1_RX_DMA_CHANNEL DMA_CH0 -#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 -#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) -#define QSPI_DMA_INSTANCE CM_DMA2 -#define QSPI_DMA_CHANNEL DMA_CH0 -#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define QSPI_DMA_TRIG_SELECT AOS_DMA2_0 -#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define QSPI_DMA_INSTANCE CM_DMA2 +#define QSPI_DMA_CHANNEL DMA_CH0 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA2_0 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0 #endif /* DMA2 ch1 */ #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) -#define UART1_TX_DMA_INSTANCE CM_DMA2 -#define UART1_TX_DMA_CHANNEL DMA_CH1 -#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 -#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 #endif /* DMA2 ch2 */ #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) -#define UART2_RX_DMA_INSTANCE CM_DMA2 -#define UART2_RX_DMA_CHANNEL DMA_CH2 -#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 -#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 #endif /* DMA2 ch3 */ #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) -#define UART2_TX_DMA_INSTANCE CM_DMA2 -#define UART2_TX_DMA_CHANNEL DMA_CH3 -#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 -#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM -#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO -#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 #endif /* DMA2 ch4 */ #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) -#define UART4_RX_DMA_INSTANCE CM_DMA2 -#define UART4_RX_DMA_CHANNEL DMA_CH4 -#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4 -#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM -#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO -#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#define UART4_RX_DMA_INSTANCE CM_DMA2 +#define UART4_RX_DMA_CHANNEL DMA_CH4 +#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 #endif /* DMA2 ch5 */ #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) -#define UART4_TX_DMA_INSTANCE CM_DMA2 -#define UART4_TX_DMA_CHANNEL DMA_CH5 -#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5 -#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM -#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO -#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#define UART4_TX_DMA_INSTANCE CM_DMA2 +#define UART4_TX_DMA_CHANNEL DMA_CH5 +#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h index a0bbb41e1ab..bd3fd9cca2b 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/gpio_config.h @@ -23,146 +23,146 @@ extern "C" { #if defined(RT_USING_PIN) #ifndef EXTINT0_IRQ_CONFIG -#define EXTINT0_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT0_IRQ_NUM, \ - .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ0, \ +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT1_IRQ_CONFIG -#define EXTINT1_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT1_IRQ_NUM, \ - .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ1, \ +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT2_IRQ_CONFIG -#define EXTINT2_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT2_IRQ_NUM, \ - .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ2, \ +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ } #endif /* EXTINT2_IRQ_CONFIG */ #ifndef EXTINT3_IRQ_CONFIG -#define EXTINT3_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT3_IRQ_NUM, \ - .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ3, \ +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ } #endif /* EXTINT3_IRQ_CONFIG */ #ifndef EXTINT4_IRQ_CONFIG -#define EXTINT4_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT4_IRQ_NUM, \ - .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ4, \ +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ } #endif /* EXTINT4_IRQ_CONFIG */ #ifndef EXTINT5_IRQ_CONFIG -#define EXTINT5_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT5_IRQ_NUM, \ - .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ5, \ +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ } #endif /* EXTINT5_IRQ_CONFIG */ #ifndef EXTINT6_IRQ_CONFIG -#define EXTINT6_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT6_IRQ_NUM, \ - .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ6, \ +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ } #endif /* EXTINT6_IRQ_CONFIG */ #ifndef EXTINT7_IRQ_CONFIG -#define EXTINT7_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT7_IRQ_NUM, \ - .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ7, \ +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ } #endif /* EXTINT7_IRQ_CONFIG */ #ifndef EXTINT8_IRQ_CONFIG -#define EXTINT8_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT8_IRQ_NUM, \ - .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ8, \ +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ } #endif /* EXTINT8_IRQ_CONFIG */ #ifndef EXTINT9_IRQ_CONFIG -#define EXTINT9_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT9_IRQ_NUM, \ - .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ9, \ +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ } #endif /* EXTINT9_IRQ_CONFIG */ #ifndef EXTINT10_IRQ_CONFIG -#define EXTINT10_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT10_IRQ_NUM, \ - .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ10, \ +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ } #endif /* EXTINT10_IRQ_CONFIG */ #ifndef EXTINT11_IRQ_CONFIG -#define EXTINT11_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT11_IRQ_NUM, \ - .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ11, \ +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ } #endif /* EXTINT11_IRQ_CONFIG */ #ifndef EXTINT12_IRQ_CONFIG -#define EXTINT12_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT12_IRQ_NUM, \ - .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ12, \ +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ } #endif /* EXTINT12_IRQ_CONFIG */ #ifndef EXTINT13_IRQ_CONFIG -#define EXTINT13_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT13_IRQ_NUM, \ - .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ13, \ +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ } #endif /* EXTINT13_IRQ_CONFIG */ #ifndef EXTINT14_IRQ_CONFIG -#define EXTINT14_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT14_IRQ_NUM, \ - .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ14, \ +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ } #endif /* EXTINT14_IRQ_CONFIG */ #ifndef EXTINT15_IRQ_CONFIG -#define EXTINT15_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT15_IRQ_NUM, \ - .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ15, \ +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ } #endif /* EXTINT15_IRQ_CONFIG */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h index 8f7c6b62967..d3912a6e280 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/i2c_config.h @@ -21,101 +21,97 @@ extern "C" { #if defined(BSP_USING_I2C1) #ifndef I2C1_CONFIG -#define I2C1_CONFIG \ - { \ - .name = "i2c1", \ - .Instance = CM_I2C1, \ - .clock = FCG1_PERIPH_I2C1, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C1_CONFIG */ #endif #if defined(BSP_I2C1_USING_DMA) #ifndef I2C1_TX_DMA_CONFIG -#define I2C1_TX_DMA_CONFIG \ - { \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .channel = I2C1_TX_DMA_CHANNEL, \ - .clock = I2C1_TX_DMA_CLOCK, \ - .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_TEI, \ - .flag = I2C1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_TX_DMA_IRQn, \ - .irq_prio = I2C1_TX_DMA_INT_PRIO, \ - .int_src = I2C1_TX_DMA_INT_SRC, \ - }, \ +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_TX_DMA_CONFIG */ #ifndef I2C1_RX_DMA_CONFIG -#define I2C1_RX_DMA_CONFIG \ - { \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .channel = I2C1_RX_DMA_CHANNEL, \ - .clock = I2C1_RX_DMA_CLOCK, \ - .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_RXI, \ - .flag = I2C1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_RX_DMA_IRQn, \ - .irq_prio = I2C1_RX_DMA_INT_PRIO, \ - .int_src = I2C1_RX_DMA_INT_SRC, \ - }, \ +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_RX_DMA_CONFIG */ #endif /* BSP_I2C1_USING_DMA */ #if defined(BSP_USING_I2C2) #ifndef I2C2_CONFIG -#define I2C2_CONFIG \ - { \ - .name = "i2c2", \ - .Instance = CM_I2C2, \ - .clock = FCG1_PERIPH_I2C2, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C2_CONFIG */ #if defined(BSP_I2C2_USING_DMA) #ifndef I2C2_TX_DMA_CONFIG -#define I2C2_TX_DMA_CONFIG \ - { \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .channel = I2C2_TX_DMA_CHANNEL, \ - .clock = I2C2_TX_DMA_CLOCK, \ - .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_TEI, \ - .flag = I2C2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_TX_DMA_IRQn, \ - .irq_prio = I2C2_TX_DMA_INT_PRIO, \ - .int_src = I2C2_TX_DMA_INT_SRC, \ - }, \ +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_TX_DMA_CONFIG */ #ifndef I2C2_RX_DMA_CONFIG -#define I2C2_RX_DMA_CONFIG \ - { \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .channel = I2C2_RX_DMA_CHANNEL, \ - .clock = I2C2_RX_DMA_CLOCK, \ - .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_RXI, \ - .flag = I2C2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_RX_DMA_IRQn, \ - .irq_prio = I2C2_RX_DMA_INT_PRIO, \ - .int_src = I2C2_RX_DMA_INT_SRC, \ - }, \ +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_RX_DMA_CONFIG */ #endif /* BSP_I2C2_USING_DMA */ @@ -123,50 +119,48 @@ extern "C" { #if defined(BSP_USING_I2C3) #ifndef I2C3_CONFIG -#define I2C3_CONFIG \ - { \ - .name = "i2c3", \ - .Instance = CM_I2C3, \ - .clock = FCG1_PERIPH_I2C3, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C3_CONFIG */ #if defined(BSP_I2C3_USING_DMA) #ifndef I2C3_TX_DMA_CONFIG -#define I2C3_TX_DMA_CONFIG \ - { \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .channel = I2C3_TX_DMA_CHANNEL, \ - .clock = I2C3_TX_DMA_CLOCK, \ - .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_TEI, \ - .flag = I2C3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_TX_DMA_IRQn, \ - .irq_prio = I2C3_TX_DMA_INT_PRIO, \ - .int_src = I2C3_TX_DMA_INT_SRC, \ - }, \ +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_TX_DMA_CONFIG */ #ifndef I2C3_RX_DMA_CONFIG -#define I2C3_RX_DMA_CONFIG \ - { \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .channel = I2C3_RX_DMA_CHANNEL, \ - .clock = I2C3_RX_DMA_CLOCK, \ - .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_RXI, \ - .flag = I2C3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_RX_DMA_IRQn, \ - .irq_prio = I2C3_RX_DMA_INT_PRIO, \ - .int_src = I2C3_RX_DMA_INT_SRC, \ - }, \ +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_RX_DMA_CONFIG */ #endif /* BSP_I2C3_USING_DMA */ @@ -174,50 +168,48 @@ extern "C" { #if defined(BSP_USING_I2C4) #ifndef I2C4_CONFIG -#define I2C4_CONFIG \ - { \ - .name = "i2c4", \ - .Instance = CM_I2C4, \ - .clock = FCG1_PERIPH_I2C4, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C4_CONFIG \ + { \ + .name = "i2c4", \ + .Instance = CM_I2C4, \ + .clock = FCG1_PERIPH_I2C4, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C4_CONFIG */ #if defined(BSP_I2C4_USING_DMA) #ifndef I2C4_TX_DMA_CONFIG -#define I2C4_TX_DMA_CONFIG \ - { \ - .Instance = I2C4_TX_DMA_INSTANCE, \ - .channel = I2C4_TX_DMA_CHANNEL, \ - .clock = I2C4_TX_DMA_CLOCK, \ - .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C4_TEI, \ - .flag = I2C4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C4_TX_DMA_IRQn, \ - .irq_prio = I2C4_TX_DMA_INT_PRIO, \ - .int_src = I2C4_TX_DMA_INT_SRC, \ - }, \ +#define I2C4_TX_DMA_CONFIG \ + { \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + .clock = I2C4_TX_DMA_CLOCK, \ + .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_TEI, \ + .flag = I2C4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_TX_DMA_IRQn, \ + .irq_prio = I2C4_TX_DMA_INT_PRIO, \ + .int_src = I2C4_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C4_TX_DMA_CONFIG */ #ifndef I2C4_RX_DMA_CONFIG -#define I2C4_RX_DMA_CONFIG \ - { \ - .Instance = I2C4_RX_DMA_INSTANCE, \ - .channel = I2C4_RX_DMA_CHANNEL, \ - .clock = I2C4_RX_DMA_CLOCK, \ - .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C4_RXI, \ - .flag = I2C4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C4_RX_DMA_IRQn, \ - .irq_prio = I2C4_RX_DMA_INT_PRIO, \ - .int_src = I2C4_RX_DMA_INT_SRC, \ - }, \ +#define I2C4_RX_DMA_CONFIG \ + { \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + .clock = I2C4_RX_DMA_CLOCK, \ + .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_RXI, \ + .flag = I2C4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_RX_DMA_IRQn, \ + .irq_prio = I2C4_RX_DMA_INT_PRIO, \ + .int_src = I2C4_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C4_RX_DMA_CONFIG */ #endif /* BSP_I2C4_USING_DMA */ @@ -225,50 +217,48 @@ extern "C" { #if defined(BSP_USING_I2C5) #ifndef I2C5_CONFIG -#define I2C5_CONFIG \ - { \ - .name = "i2c5", \ - .Instance = CM_I2C5, \ - .clock = FCG1_PERIPH_I2C5, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C5_CONFIG \ + { \ + .name = "i2c5", \ + .Instance = CM_I2C5, \ + .clock = FCG1_PERIPH_I2C5, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C5_CONFIG */ #if defined(BSP_I2C5_USING_DMA) #ifndef I2C5_TX_DMA_CONFIG -#define I2C5_TX_DMA_CONFIG \ - { \ - .Instance = I2C5_TX_DMA_INSTANCE, \ - .channel = I2C5_TX_DMA_CHANNEL, \ - .clock = I2C5_TX_DMA_CLOCK, \ - .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C5_TEI, \ - .flag = I2C5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C5_TX_DMA_IRQn, \ - .irq_prio = I2C5_TX_DMA_INT_PRIO, \ - .int_src = I2C5_TX_DMA_INT_SRC, \ - }, \ +#define I2C5_TX_DMA_CONFIG \ + { \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .channel = I2C5_TX_DMA_CHANNEL, \ + .clock = I2C5_TX_DMA_CLOCK, \ + .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_TEI, \ + .flag = I2C5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_TX_DMA_IRQn, \ + .irq_prio = I2C5_TX_DMA_INT_PRIO, \ + .int_src = I2C5_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C5_TX_DMA_CONFIG */ #ifndef I2C5_RX_DMA_CONFIG -#define I2C5_RX_DMA_CONFIG \ - { \ - .Instance = I2C5_RX_DMA_INSTANCE, \ - .channel = I2C5_RX_DMA_CHANNEL, \ - .clock = I2C5_RX_DMA_CLOCK, \ - .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C5_RXI, \ - .flag = I2C5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C5_RX_DMA_IRQn, \ - .irq_prio = I2C5_RX_DMA_INT_PRIO, \ - .int_src = I2C5_RX_DMA_INT_SRC, \ - }, \ +#define I2C5_RX_DMA_CONFIG \ + { \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .channel = I2C5_RX_DMA_CHANNEL, \ + .clock = I2C5_RX_DMA_CLOCK, \ + .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_RXI, \ + .flag = I2C5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_RX_DMA_IRQn, \ + .irq_prio = I2C5_RX_DMA_INT_PRIO, \ + .int_src = I2C5_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C5_RX_DMA_CONFIG */ #endif /* BSP_I2C5_USING_DMA */ @@ -276,50 +266,48 @@ extern "C" { #if defined(BSP_USING_I2C6) #ifndef I2C6_CONFIG -#define I2C6_CONFIG \ - { \ - .name = "i2c6", \ - .Instance = CM_I2C6, \ - .clock = FCG1_PERIPH_I2C6, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C6_CONFIG \ + { \ + .name = "i2c6", \ + .Instance = CM_I2C6, \ + .clock = FCG1_PERIPH_I2C6, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C6_CONFIG */ #if defined(BSP_I2C6_USING_DMA) #ifndef I2C6_TX_DMA_CONFIG -#define I2C6_TX_DMA_CONFIG \ - { \ - .Instance = I2C6_TX_DMA_INSTANCE, \ - .channel = I2C6_TX_DMA_CHANNEL, \ - .clock = I2C6_TX_DMA_CLOCK, \ - .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C6_TEI, \ - .flag = I2C6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C6_TX_DMA_IRQn, \ - .irq_prio = I2C6_TX_DMA_INT_PRIO, \ - .int_src = I2C6_TX_DMA_INT_SRC, \ - }, \ +#define I2C6_TX_DMA_CONFIG \ + { \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .channel = I2C6_TX_DMA_CHANNEL, \ + .clock = I2C6_TX_DMA_CLOCK, \ + .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_TEI, \ + .flag = I2C6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_TX_DMA_IRQn, \ + .irq_prio = I2C6_TX_DMA_INT_PRIO, \ + .int_src = I2C6_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C6_TX_DMA_CONFIG */ #ifndef I2C6_RX_DMA_CONFIG -#define I2C6_RX_DMA_CONFIG \ - { \ - .Instance = I2C6_RX_DMA_INSTANCE, \ - .channel = I2C6_RX_DMA_CHANNEL, \ - .clock = I2C6_RX_DMA_CLOCK, \ - .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C6_RXI, \ - .flag = I2C6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C6_RX_DMA_IRQn, \ - .irq_prio = I2C6_RX_DMA_INT_PRIO, \ - .int_src = I2C6_RX_DMA_INT_SRC, \ - }, \ +#define I2C6_RX_DMA_CONFIG \ + { \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .channel = I2C6_RX_DMA_CHANNEL, \ + .clock = I2C6_RX_DMA_CLOCK, \ + .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_RXI, \ + .flag = I2C6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_RX_DMA_IRQn, \ + .irq_prio = I2C6_RX_DMA_INT_PRIO, \ + .int_src = I2C6_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C6_RX_DMA_CONFIG */ #endif /* BSP_I2C6_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h index 2e0cce799f4..88ff1036189 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/irq_config.h @@ -18,245 +18,245 @@ extern "C" { #endif -#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn -#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn -#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn -#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn -#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn -#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn -#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn -#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn -#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn -#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn -#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn -#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn -#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn -#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn -#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn -#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn -#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch0 */ -#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn -#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch1 */ -#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn -#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch2 */ -#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn -#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch3 */ -#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn -#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch4 */ -#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn -#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch5 */ -#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn -#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch0 */ -#define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn -#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch1 */ -#define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn -#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch2 */ -#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn -#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch3 */ -#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn -#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch4 */ -#define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn -#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch5 */ -#define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn -#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_USING_UART1) -#define BSP_UART1_IRQ_NUM USART1_IRQn -#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_IRQ_NUM USART1_IRQn +#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) -#define BSP_UART2_IRQ_NUM USART2_IRQn -#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_IRQ_NUM USART2_IRQn +#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) -#define BSP_UART3_IRQ_NUM USART3_IRQn -#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_IRQ_NUM USART3_IRQn +#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART3 */ #if defined(BSP_USING_UART4) -#define BSP_UART4_IRQ_NUM USART4_IRQn -#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_IRQ_NUM USART4_IRQn +#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn -#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn +#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_UART5) -#define BSP_UART5_IRQ_NUM USART5_IRQn -#define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_IRQ_NUM USART5_IRQn +#define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn -#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn +#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART5 */ #if defined(BSP_USING_UART6) -#define BSP_UART6_IRQ_NUM USART6_IRQn -#define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_IRQ_NUM USART6_IRQn +#define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART6 */ #if defined(BSP_USING_SPI1) -#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn -#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI2) -#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn -#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI3) -#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn -#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif -#if defined (BSP_USING_QSPI) -#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn -#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#if defined(BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_QSPI */ #if defined(BSP_USING_TMRA_1) -#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn -#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_1 */ #if defined(BSP_USING_TMRA_2) -#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn -#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_2 */ #if defined(BSP_USING_TMRA_3) -#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn -#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_3 */ #if defined(BSP_USING_TMRA_4) -#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn -#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_4 */ #if defined(BSP_USING_TMRA_5) -#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn -#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_5 */ #if defined(BSP_USING_MCAN1) -#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn -#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_MCAN1_INT0_IRQ_NUM MCAN1_INT0_IRQn +#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN1 */ #if defined(BSP_USING_MCAN2) -#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn -#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_MCAN2_INT0_IRQ_NUM MCAN2_INT0_IRQn +#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN2 */ #if defined(RT_USING_ALARM) -#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn -#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* RT_USING_ALARM */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_2) -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_3) -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_4) -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_5) -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_2) -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ #if defined(BSP_USING_INPUT_CAPTURE) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/mcan_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/mcan_config.h index 66d9f808ed6..0c9bb9263a3 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/mcan_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/mcan_config.h @@ -31,56 +31,56 @@ extern "C" { */ #ifdef RT_CAN_USING_CANFD -#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS -#define MCAN_TOTAL_FILTER_NUM (26U) -#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */ -#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */ -#define MCAN_TX_FIFO_NUM (6U) -#define MCAN_RX_FIFO_NUM (6U) -#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */ +#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS +#define MCAN_TOTAL_FILTER_NUM (26U) +#define MCAN_STD_FILTER_NUM (13U) /* Each standard filter element size is 4 bytes */ +#define MCAN_EXT_FILTER_NUM (13U) /* Each extended filter element size is 8 bytes */ +#define MCAN_TX_FIFO_NUM (6U) +#define MCAN_RX_FIFO_NUM (6U) +#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */ #else -#define MCAN_FD_SEL MCAN_FD_CLASSICAL -#define MCAN_TOTAL_FILTER_NUM (32U) -#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */ -#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */ -#define MCAN_TX_FIFO_NUM (26U) -#define MCAN_RX_FIFO_NUM (26U) -#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */ +#define MCAN_FD_SEL MCAN_FD_CLASSICAL +#define MCAN_TOTAL_FILTER_NUM (32U) +#define MCAN_STD_FILTER_NUM (16U) /* Each standard filter element size is 4 bytes */ +#define MCAN_EXT_FILTER_NUM (16U) /* Each extended filter element size is 8 bytes */ +#define MCAN_TX_FIFO_NUM (26U) +#define MCAN_RX_FIFO_NUM (26U) +#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */ #endif #ifdef BSP_USING_MCAN1 -#define MCAN1_NAME ("mcan1") -#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL) -#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ +#define MCAN1_NAME ("mcan1") +#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL) +#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ -#define MCAN1_FD_SEL MCAN_FD_SEL +#define MCAN1_FD_SEL MCAN_FD_SEL -#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM -#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM +#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM +#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM -#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM -#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM +#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM -#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U) +#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM +#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U) #endif /* BSP_USING_MCAN1 */ #ifdef BSP_USING_MCAN2 -#define MCAN2_NAME ("mcan2") -#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL) -#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ +#define MCAN2_NAME ("mcan2") +#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL) +#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ -#define MCAN2_FD_SEL MCAN_FD_SEL -#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM -#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM +#define MCAN2_FD_SEL MCAN_FD_SEL +#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM +#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM -#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM -#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM +#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM -#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U) +#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM +#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U) #endif /* BSP_USING_MCAN2 */ /***********************************************************************************************/ @@ -101,154 +101,154 @@ extern "C" { 2. For the corresponding function of u32TdcFilter, please refer to the reference manual for details(TDCR.TDCF). The u32TdcFilter can be get from PSR.TDCV. */ -#define MCAN_FD_CFG_500K_1M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 32, \ - .u32DataTimeSeg2 = 8, \ - .u32DataSyncJumpWidth = 8, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 32, \ - .u32TdcFilter = 32 + 1, \ +#define MCAN_FD_CFG_500K_1M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 32, \ + .u32DataTimeSeg2 = 8, \ + .u32DataSyncJumpWidth = 8, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 32, \ + .u32TdcFilter = 32 + 1, \ } -#define MCAN_FD_CFG_500K_2M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 16, \ - .u32DataTimeSeg2 = 4, \ - .u32DataSyncJumpWidth = 4, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 16, \ - .u32TdcFilter = 16 + 1, \ +#define MCAN_FD_CFG_500K_2M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 16, \ + .u32DataTimeSeg2 = 4, \ + .u32DataSyncJumpWidth = 4, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 16, \ + .u32TdcFilter = 16 + 1, \ } -#define MCAN_FD_CFG_500K_4M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 8, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 8, \ - .u32TdcFilter = 8 + 1, \ +#define MCAN_FD_CFG_500K_4M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 8, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 8, \ + .u32TdcFilter = 8 + 1, \ } -#define MCAN_FD_CFG_500K_5M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 6, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 6, \ - .u32TdcFilter = 6 + 1, \ +#define MCAN_FD_CFG_500K_5M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 6, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 6, \ + .u32TdcFilter = 6 + 1, \ } -#define MCAN_FD_CFG_500K_8M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 4, \ - .u32DataTimeSeg2 = 1, \ - .u32DataSyncJumpWidth = 1, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 4, \ - .u32TdcFilter = 4 + 1, \ +#define MCAN_FD_CFG_500K_8M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 4, \ + .u32DataTimeSeg2 = 1, \ + .u32DataSyncJumpWidth = 1, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 4, \ + .u32TdcFilter = 4 + 1, \ } -#define MCAN_FD_CFG_1M_1M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 32, \ - .u32DataTimeSeg2 = 8, \ - .u32DataSyncJumpWidth = 8, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 2*32, \ - .u32TdcFilter = 2*32 + 1, \ +#define MCAN_FD_CFG_1M_1M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 32, \ + .u32DataTimeSeg2 = 8, \ + .u32DataSyncJumpWidth = 8, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 2 * 32, \ + .u32TdcFilter = 2 * 32 + 1, \ } -#define MCAN_FD_CFG_1M_2M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 16, \ - .u32DataTimeSeg2 = 4, \ - .u32DataSyncJumpWidth = 4, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 16, \ - .u32TdcFilter = 16 + 1, \ +#define MCAN_FD_CFG_1M_2M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 16, \ + .u32DataTimeSeg2 = 4, \ + .u32DataSyncJumpWidth = 4, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 16, \ + .u32TdcFilter = 16 + 1, \ } -#define MCAN_FD_CFG_1M_4M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 8, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 8, \ - .u32TdcFilter = 8 + 1, \ +#define MCAN_FD_CFG_1M_4M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 8, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 8, \ + .u32TdcFilter = 8 + 1, \ } -#define MCAN_FD_CFG_1M_5M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 6, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 6, \ - .u32TdcFilter = 6 + 1, \ +#define MCAN_FD_CFG_1M_5M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 6, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 6, \ + .u32TdcFilter = 6 + 1, \ } -#define MCAN_FD_CFG_1M_8M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 4, \ - .u32DataTimeSeg2 = 1, \ - .u32DataSyncJumpWidth = 1, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 4, \ - .u32TdcFilter = 4 + 1, \ +#define MCAN_FD_CFG_1M_8M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 4, \ + .u32DataTimeSeg2 = 1, \ + .u32DataSyncJumpWidth = 1, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 4, \ + .u32TdcFilter = 4 + 1, \ } /* @@ -260,95 +260,95 @@ extern "C" { SamplePoint(%) = 16 / (16 + 4) = 80% The following bit rate configurations are based on the max MCAN Clock(40MHz). */ -#define MCAN_CC_CFG_1M \ - { \ - .u32NominalPrescaler = 2, \ - .u32NominalTimeSeg1 = 16, \ - .u32NominalTimeSeg2 = 4, \ - .u32NominalSyncJumpWidth = 4, \ +#define MCAN_CC_CFG_1M \ + { \ + .u32NominalPrescaler = 2, \ + .u32NominalTimeSeg1 = 16, \ + .u32NominalTimeSeg2 = 4, \ + .u32NominalSyncJumpWidth = 4, \ } -#define MCAN_CC_CFG_800K \ - { \ - .u32NominalPrescaler = 2, \ - .u32NominalTimeSeg1 = 20, \ - .u32NominalTimeSeg2 = 5, \ - .u32NominalSyncJumpWidth = 5, \ +#define MCAN_CC_CFG_800K \ + { \ + .u32NominalPrescaler = 2, \ + .u32NominalTimeSeg1 = 20, \ + .u32NominalTimeSeg2 = 5, \ + .u32NominalSyncJumpWidth = 5, \ } -#define MCAN_CC_CFG_500K \ - { \ - .u32NominalPrescaler = 4, \ - .u32NominalTimeSeg1 = 16, \ - .u32NominalTimeSeg2 = 4, \ - .u32NominalSyncJumpWidth = 4, \ +#define MCAN_CC_CFG_500K \ + { \ + .u32NominalPrescaler = 4, \ + .u32NominalTimeSeg1 = 16, \ + .u32NominalTimeSeg2 = 4, \ + .u32NominalSyncJumpWidth = 4, \ } -#define MCAN_CC_CFG_250K \ - { \ - .u32NominalPrescaler = 4, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_250K \ + { \ + .u32NominalPrescaler = 4, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_125K \ - { \ - .u32NominalPrescaler = 8, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_125K \ + { \ + .u32NominalPrescaler = 8, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_100K \ - { \ - .u32NominalPrescaler = 10, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_100K \ + { \ + .u32NominalPrescaler = 10, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_50K \ - { \ - .u32NominalPrescaler = 20, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_50K \ + { \ + .u32NominalPrescaler = 20, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_20K \ - { \ - .u32NominalPrescaler = 50, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_20K \ + { \ + .u32NominalPrescaler = 50, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_10K \ - { \ - .u32NominalPrescaler = 100, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_10K \ + { \ + .u32NominalPrescaler = 100, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } #ifdef RT_CAN_USING_CANFD -#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M -#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M -#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M +#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M +#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M +#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M -#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M -#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M -#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M +#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M +#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M +#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M #else -#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M -#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud -#define MCAN1_DATA_BAUD_RATE 0 +#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M +#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud +#define MCAN1_DATA_BAUD_RATE 0 -#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M -#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud -#define MCAN2_DATA_BAUD_RATE 0 +#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M +#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud +#define MCAN2_DATA_BAUD_RATE 0 #endif /* #ifdef RT_CAN_USING_CANFD */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h index e77cc0f20e4..8dc37b7f23c 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pm_config.h @@ -22,18 +22,18 @@ extern "C" { extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); #ifndef PM_TICKLESS_TIMER_ENABLE_MASK -#define PM_TICKLESS_TIMER_ENABLE_MASK \ -( (1UL << PM_SLEEP_MODE_IDLE) | \ - (1UL << PM_SLEEP_MODE_DEEP)) +#define PM_TICKLESS_TIMER_ENABLE_MASK \ + ((1UL << PM_SLEEP_MODE_IDLE) | \ + (1UL << PM_SLEEP_MODE_DEEP)) #endif /** * @brief run mode config @ref pm_run_mode_config structure */ #ifndef PM_RUN_MODE_CFG -#define PM_RUN_MODE_CFG \ - { \ - .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ } #endif /* PM_RUN_MODE_CFG */ @@ -41,54 +41,54 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); * @brief sleep idle config @ref pm_sleep_mode_idle_config structure */ #ifndef PM_SLEEP_IDLE_CFG -#define PM_SLEEP_IDLE_CFG \ -{ \ - .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ -} +#define PM_SLEEP_IDLE_CFG \ + { \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ + } #endif /*PM_SLEEP_IDLE_CFG*/ /** * @brief sleep deep config @ref pm_sleep_mode_deep_config structure */ #ifndef PM_SLEEP_DEEP_CFG -#define PM_SLEEP_DEEP_CFG \ -{ \ - { \ - .u16Clock = PWC_STOP_CLK_KEEP, \ - .u8StopDrv = PWC_STOP_DRV_HIGH, \ - .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ - .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ - }, \ - .pwc_stop_type = PWC_STOP_WFE_INT, \ -} +#define PM_SLEEP_DEEP_CFG \ + { \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ + } #endif /*PM_SLEEP_DEEP_CFG*/ /** * @brief sleep standby config @ref pm_sleep_mode_standby_config structure */ #ifndef PM_SLEEP_STANDBY_CFG -#define PM_SLEEP_STANDBY_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD1, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ - }, \ -} +#define PM_SLEEP_STANDBY_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } #endif /*PM_SLEEP_STANDBY_CFG*/ /** * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure */ #ifndef PM_SLEEP_SHUTDOWN_CFG -#define PM_SLEEP_SHUTDOWN_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD3, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ - }, \ -} +#define PM_SLEEP_SHUTDOWN_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } #endif /*PM_SLEEP_SHUTDOWN_CFG*/ #endif /* BSP_USING_PM */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h index 7b6c2696b65..dd8d7759417 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pulse_encoder_config.h @@ -22,182 +22,168 @@ extern "C" { #ifdef BSP_USING_PULSE_ENCODER_TMRA_1 #ifndef PULSE_ENCODER_TMRA_1_CONFIG -#define PULSE_ENCODER_TMRA_1_CONFIG \ - { \ - .tmr_handler = CM_TMRA_1, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a1" \ +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ } #endif /* PULSE_ENCODER_TMRA_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_2 #ifndef PULSE_ENCODER_TMRA_2_CONFIG -#define PULSE_ENCODER_TMRA_2_CONFIG \ - { \ - .tmr_handler = CM_TMRA_2, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a2" \ +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ } #endif /* PULSE_ENCODER_TMRA_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_3 #ifndef PULSE_ENCODER_TMRA_3_CONFIG -#define PULSE_ENCODER_TMRA_3_CONFIG \ - { \ - .tmr_handler = CM_TMRA_3, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a3" \ +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ } #endif /* PULSE_ENCODER_TMRA_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_4 #ifndef PULSE_ENCODER_TMRA_4_CONFIG -#define PULSE_ENCODER_TMRA_4_CONFIG \ - { \ - .tmr_handler = CM_TMRA_4, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a4" \ +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ } #endif /* PULSE_ENCODER_TMRA_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_5 #ifndef PULSE_ENCODER_TMRA_5_CONFIG -#define PULSE_ENCODER_TMRA_5_CONFIG \ - { \ - .tmr_handler = CM_TMRA_5, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a5" \ +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ } #endif /* PULSE_ENCODER_TMRA_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_1 #ifndef PULSE_ENCODER_TMR6_1_CONFIG -#define PULSE_ENCODER_TMR6_1_CONFIG \ - { \ - .tmr_handler = CM_TMR6_1, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_61" \ +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ } #endif /* PULSE_ENCODER_TMR6_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_2 #ifndef PULSE_ENCODER_TMR6_2_CONFIG -#define PULSE_ENCODER_TMR6_2_CONFIG \ - { \ - .tmr_handler = CM_TMR6_2, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_62" \ +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ } #endif /* PULSE_ENCODER_TMR6_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h index 4b2bc716f82..bc41f839832 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/pwm_tmr_config.h @@ -22,155 +22,135 @@ extern "C" { #ifdef BSP_USING_PWM_TMRA_1 #ifndef PWM_TMRA_1_CONFIG -#define PWM_TMRA_1_CONFIG \ - { \ - .name = "pwm_a1", \ - .instance = CM_TMRA_1, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_1_CONFIG */ #endif /* BSP_USING_PWM_TMRA_1 */ #ifdef BSP_USING_PWM_TMRA_2 #ifndef PWM_TMRA_2_CONFIG -#define PWM_TMRA_2_CONFIG \ - { \ - .name = "pwm_a2", \ - .instance = CM_TMRA_2, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_2_CONFIG */ #endif /* BSP_USING_PWM_TMRA_2 */ #ifdef BSP_USING_PWM_TMRA_3 #ifndef PWM_TMRA_3_CONFIG -#define PWM_TMRA_3_CONFIG \ - { \ - .name = "pwm_a3", \ - .instance = CM_TMRA_3, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_3_CONFIG */ #endif /* BSP_USING_PWM_TMRA_3 */ #ifdef BSP_USING_PWM_TMRA_4 #ifndef PWM_TMRA_4_CONFIG -#define PWM_TMRA_4_CONFIG \ - { \ - .name = "pwm_a4", \ - .instance = CM_TMRA_4, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_4_CONFIG */ #endif /* BSP_USING_PWM_TMRA_4 */ #ifdef BSP_USING_PWM_TMRA_5 #ifndef PWM_TMRA_5_CONFIG -#define PWM_TMRA_5_CONFIG \ - { \ - .name = "pwm_a5", \ - .instance = CM_TMRA_5, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_5_CONFIG */ #endif /* BSP_USING_PWM_TMRA_5 */ @@ -180,96 +160,87 @@ extern "C" { #ifdef BSP_USING_PWM_TMR4_1 #ifndef PWM_TMR4_1_CONFIG -#define PWM_TMR4_1_CONFIG \ - { \ - .name = "pwm_t41", \ - .instance = CM_TMR4_1, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_1_CONFIG */ #endif /* BSP_USING_PWM_TMR4_1 */ #ifdef BSP_USING_PWM_TMR4_2 #ifndef PWM_TMR4_2_CONFIG -#define PWM_TMR4_2_CONFIG \ - { \ - .name = "pwm_t42", \ - .instance = CM_TMR4_2, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_2_CONFIG */ #endif /* BSP_USING_PWM_TMR4_2 */ #ifdef BSP_USING_PWM_TMR4_3 #ifndef PWM_TMR4_3_CONFIG -#define PWM_TMR4_3_CONFIG \ - { \ - .name = "pwm_t43", \ - .instance = CM_TMR4_3, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_3_CONFIG */ #endif /* BSP_USING_PWM_TMR4_3 */ @@ -280,377 +251,337 @@ extern "C" { #ifdef BSP_USING_PWM_TMR6_1 #ifndef PWM_TMR6_1_CONFIG -#define PWM_TMR6_1_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_1, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_1_CONFIG */ #endif /* BSP_USING_PWM_TMR6_1 */ #ifdef BSP_USING_PWM_TMR6_2 #ifndef PWM_TMR6_2_CONFIG -#define PWM_TMR6_2_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_2, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_2_CONFIG */ #endif /* BSP_USING_PWM_TMR6_2 */ #ifdef BSP_USING_PWM_TMR6_3 #ifndef PWM_TMR6_3_CONFIG -#define PWM_TMR6_3_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_3, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_3_CONFIG */ #endif /* BSP_USING_PWM_TMR6_3 */ #ifdef BSP_USING_PWM_TMR6_4 #ifndef PWM_TMR6_4_CONFIG -#define PWM_TMR6_4_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_4, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_4_CONFIG */ #endif /* BSP_USING_PWM_TMR6_4 */ #ifdef BSP_USING_PWM_TMR6_5 #ifndef PWM_TMR6_5_CONFIG -#define PWM_TMR6_5_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_5, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_5_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_5, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_5_CONFIG */ #endif /* BSP_USING_PWM_TMR6_5 */ #ifdef BSP_USING_PWM_TMR6_6 #ifndef PWM_TMR6_6_CONFIG -#define PWM_TMR6_6_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_6, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_6_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_6, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_6_CONFIG */ #endif /* BSP_USING_PWM_TMR6_6 */ #ifdef BSP_USING_PWM_TMR6_7 #ifndef PWM_TMR6_7_CONFIG -#define PWM_TMR6_7_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_7, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_7_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_7, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_7_CONFIG */ #endif /* BSP_USING_PWM_TMR6_7 */ #ifdef BSP_USING_PWM_TMR6_8 #ifndef PWM_TMR6_8_CONFIG -#define PWM_TMR6_8_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_8, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_8_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_8, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_8_CONFIG */ #endif /* BSP_USING_PWM_TMR6_8 */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h index 0283f1ee530..3ddadfd8f1a 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/qspi_config.h @@ -21,54 +21,52 @@ extern "C" { #ifdef BSP_USING_QSPI #ifndef QSPI_BUS_CONFIG -#define QSPI_BUS_CONFIG \ - { \ - .Instance = CM_QSPI, \ - .clock = FCG1_PERIPH_QSPI, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ - .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_QSPI_INTR, \ - }, \ +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ } #endif /* QSPI_BUS_CONFIG */ #ifndef QSPI_INIT_PARAMS -#define QSPI_INIT_PARAMS \ - { \ - .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ - .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ - .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ - .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ } #endif /* QSPI_INIT_PARAMS */ -#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH #ifdef BSP_QSPI_USING_DMA #ifndef QSPI_DMA_CONFIG -#define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .channel = QSPI_DMA_CHANNEL, \ - .clock = QSPI_DMA_CLOCK, \ - .trigger_select = QSPI_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_AOS_STRG, \ - .flag = QSPI_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = QSPI_DMA_IRQn, \ - .irq_prio = QSPI_DMA_INT_PRIO, \ - .int_src = QSPI_DMA_INT_SRC, \ - } \ +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ } #endif /* QSPI_DMA_CONFIG */ /* unit: half-word, DMA data width of QSPI transmitting is 16bit */ #ifndef QSPI_DMA_TX_BUFSIZE -#define QSPI_DMA_TX_BUFSIZE 256 +#define QSPI_DMA_TX_BUFSIZE 256 #endif /* QSPI_DMA_TX_BUFSIZE */ #endif /* BSP_QSPI_USING_DMA */ #endif /* BSP_USING_QSPI */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h index 92bd3a05d0e..656292d8d93 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/spi_config.h @@ -22,134 +22,127 @@ extern "C" { #ifdef BSP_USING_SPI1 #ifndef SPI1_BUS_CONFIG -#define SPI1_BUS_CONFIG \ - { \ - .Instance = CM_SPI1, \ - .bus_name = "spi1", \ - .clock = FCG1_PERIPH_SPI1, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI1_SPEI, \ - }, \ +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .clock = SPI1_TX_DMA_CLOCK, \ - .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPTI, \ - .flag = SPI1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_TX_DMA_IRQn, \ - .irq_prio = SPI1_TX_DMA_INT_PRIO, \ - .int_src = SPI1_TX_DMA_INT_SRC, \ - } \ +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .clock = SPI1_RX_DMA_CLOCK, \ - .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPRI, \ - .flag = SPI1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_RX_DMA_IRQn, \ - .irq_prio = SPI1_RX_DMA_INT_PRIO, \ - .int_src = SPI1_RX_DMA_INT_SRC, \ - } \ +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 #ifndef SPI2_BUS_CONFIG -#define SPI2_BUS_CONFIG \ - { \ - .Instance = CM_SPI2, \ - .bus_name = "spi2", \ - .clock = FCG1_PERIPH_SPI2, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI2_SPEI, \ - }, \ +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .channel = SPI2_TX_DMA_CHANNEL, \ - .clock = SPI2_TX_DMA_CLOCK, \ - .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPTI, \ - .flag = SPI2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_TX_DMA_IRQn, \ - .irq_prio = SPI2_TX_DMA_INT_PRIO, \ - .int_src = SPI2_TX_DMA_INT_SRC, \ - } \ +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .channel = SPI2_RX_DMA_CHANNEL, \ - .clock = SPI2_RX_DMA_CLOCK, \ - .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPRI, \ - .flag = SPI2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_RX_DMA_IRQn, \ - .irq_prio = SPI2_RX_DMA_INT_PRIO, \ - .int_src = SPI2_RX_DMA_INT_SRC, \ - } \ +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 #ifndef SPI3_BUS_CONFIG -#define SPI3_BUS_CONFIG \ - { \ - .Instance = CM_SPI3, \ - .bus_name = "spi3", \ - .clock = FCG1_PERIPH_SPI3, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI3_SPEI, \ - }, \ +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ @@ -157,40 +150,38 @@ extern "C" { #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .channel = SPI3_TX_DMA_CHANNEL, \ - .clock = SPI3_TX_DMA_CLOCK, \ - .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPTI, \ - .flag = SPI3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_TX_DMA_IRQn, \ - .irq_prio = SPI3_TX_DMA_INT_PRIO, \ - .int_src = SPI3_TX_DMA_INT_SRC, \ - } \ +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .channel = SPI3_RX_DMA_CHANNEL, \ - .clock = SPI3_RX_DMA_CLOCK, \ - .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPRI, \ - .flag = SPI3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_RX_DMA_IRQn, \ - .irq_prio = SPI3_RX_DMA_INT_PRIO, \ - .int_src = SPI3_RX_DMA_INT_SRC, \ - } \ +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h index 6ac1e5a6817..16a9788c2c3 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/timer_config.h @@ -20,95 +20,90 @@ extern "C" { #ifdef BSP_USING_TMRA_1 #ifndef TMRA_1_CONFIG -#define TMRA_1_CONFIG \ - { \ - .tmr_handle = CM_TMRA_1, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_1, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_1_OVF, \ - .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ - }, \ - .name = "tmra_1" \ +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ } #endif /* TMRA_1_CONFIG */ #endif /* BSP_USING_TMRA_1 */ #ifdef BSP_USING_TMRA_2 #ifndef TMRA_2_CONFIG -#define TMRA_2_CONFIG \ - { \ - .tmr_handle = CM_TMRA_2, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_2, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_2_OVF, \ - .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ - }, \ - .name = "tmra_2" \ +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ } #endif /* TMRA_2_CONFIG */ #endif /* BSP_USING_TMRA_2 */ #ifdef BSP_USING_TMRA_3 #ifndef TMRA_3_CONFIG -#define TMRA_3_CONFIG \ - { \ - .tmr_handle = CM_TMRA_3, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_3, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_3_OVF, \ - .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ - }, \ - .name = "tmra_3" \ +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ } #endif /* TMRA_3_CONFIG */ #endif /* BSP_USING_TMRA_3 */ #ifdef BSP_USING_TMRA_4 #ifndef TMRA_4_CONFIG -#define TMRA_4_CONFIG \ - { \ - .tmr_handle = CM_TMRA_4, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_4, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_4_OVF, \ - .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ - }, \ - .name = "tmra_4" \ +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ } #endif /* TMRA_4_CONFIG */ #endif /* BSP_USING_TMRA_4 */ #ifdef BSP_USING_TMRA_5 #ifndef TMRA_5_CONFIG -#define TMRA_5_CONFIG \ - { \ - .tmr_handle = CM_TMRA_5, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_5, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_5_OVF, \ - .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ - }, \ - .name = "tmra_5" \ +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ } #endif /* TMRA_5_CONFIG */ #endif /* BSP_USING_TMRA_5 */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/tmr_capture_config.h index d5aa901a6cc..0baef1dd700 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/tmr_capture_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/tmr_capture_config.h @@ -17,34 +17,34 @@ extern "C" { #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) #define IC1_NAME "ic1" -#define INPUT_CAPTURE_CFG_TMR6_1 \ -{ \ - .name = IC1_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_1 \ + { \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) #define IC2_NAME "ic2" -#define INPUT_CAPTURE_CFG_TMR6_2 \ -{ \ - .name = IC2_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_2 \ + { \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ + } #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h b/bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h index c1ac81ae9eb..a660ea957e0 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/config/uart_config.h @@ -22,90 +22,86 @@ extern "C" { #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = CM_USART1, \ - .clock = FCG3_PERIPH_USART1, \ - .irq_num = BSP_UART1_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART1_EI, \ - .rx_int_src = INT_SRC_USART1_RI, \ - .tx_int_src = INT_SRC_USART1_TI, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .irq_num = BSP_UART1_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART1_EI, \ + .rx_int_src = INT_SRC_USART1_RI, \ + .tx_int_src = INT_SRC_USART1_TI, \ } #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .clock = UART1_RX_DMA_CLOCK, \ - .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_RI, \ - .flag = UART1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_RX_DMA_IRQn, \ - .irq_prio = UART1_RX_DMA_INT_PRIO, \ - .int_src = UART1_RX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_RX_CONFIG */ #ifndef UART1_RXTO_CONFIG -#define UART1_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ } #endif /* UART1_RXTO_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #endif /* UART1_TX_CPLT_CONFIG */ #if defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .clock = UART1_TX_DMA_CLOCK, \ - .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_TI, \ - .flag = UART1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_TX_DMA_IRQn, \ - .irq_prio = UART1_TX_DMA_INT_PRIO, \ - .int_src = UART1_TX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -113,90 +109,86 @@ extern "C" { #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = CM_USART2, \ - .clock = FCG3_PERIPH_USART2, \ - .irq_num = BSP_UART2_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART2_EI, \ - .rx_int_src = INT_SRC_USART2_RI, \ - .tx_int_src = INT_SRC_USART2_TI, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .irq_num = BSP_UART2_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART2_EI, \ + .rx_int_src = INT_SRC_USART2_RI, \ + .tx_int_src = INT_SRC_USART2_TI, \ } #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .clock = UART2_RX_DMA_CLOCK, \ - .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_RI, \ - .flag = UART2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_RX_DMA_IRQn, \ - .irq_prio = UART2_RX_DMA_INT_PRIO, \ - .int_src = UART2_RX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_RX_CONFIG */ #ifndef UART2_RXTO_CONFIG -#define UART2_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ } #endif /* UART2_RXTO_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #endif /* UART2_TX_CPLT_CONFIG */ #if defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .clock = UART2_TX_DMA_CLOCK, \ - .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_TI, \ - .flag = UART2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_TX_DMA_IRQn, \ - .irq_prio = UART2_TX_DMA_INT_PRIO, \ - .int_src = UART2_TX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -204,28 +196,27 @@ extern "C" { #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = CM_USART3, \ - .clock = FCG3_PERIPH_USART3, \ - .irq_num = BSP_UART3_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART3_EI, \ - .rx_int_src = INT_SRC_USART3_RI, \ - .tx_int_src = INT_SRC_USART3_TI, \ +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .irq_num = BSP_UART3_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART3_EI, \ + .rx_int_src = INT_SRC_USART3_RI, \ + .tx_int_src = INT_SRC_USART3_TI, \ } #endif /* UART3_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART3_TX_CPLT_CONFIG -#define UART3_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TCI, \ - }, \ +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ } #endif #endif /* UART3_TX_CPLT_CONFIG */ @@ -233,90 +224,86 @@ extern "C" { #if defined(BSP_USING_UART4) #ifndef UART4_CONFIG -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = CM_USART4, \ - .clock = FCG3_PERIPH_USART4, \ - .irq_num = BSP_UART4_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART4_EI, \ - .rx_int_src = INT_SRC_USART4_RI, \ - .tx_int_src = INT_SRC_USART4_TI, \ +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .irq_num = BSP_UART4_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART4_EI, \ + .rx_int_src = INT_SRC_USART4_RI, \ + .tx_int_src = INT_SRC_USART4_TI, \ } #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .channel = UART4_RX_DMA_CHANNEL, \ - .clock = UART4_RX_DMA_CLOCK, \ - .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART4_RI, \ - .flag = UART4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART4_RX_DMA_IRQn, \ - .irq_prio = UART4_RX_DMA_INT_PRIO, \ - .int_src = UART4_RX_DMA_INT_SRC, \ - }, \ +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .clock = UART4_RX_DMA_CLOCK, \ + .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_RI, \ + .flag = UART4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART4_RX_DMA_IRQn, \ + .irq_prio = UART4_RX_DMA_INT_PRIO, \ + .int_src = UART4_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART4_DMA_RX_CONFIG */ #ifndef UART4_RXTO_CONFIG -#define UART4_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ +#define UART4_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ } #endif /* UART4_RXTO_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #endif /* UART4_TX_CPLT_CONFIG */ #if defined(BSP_UART4_TX_USING_DMA) #ifndef UART4_DMA_TX_CONFIG -#define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .channel = UART4_TX_DMA_CHANNEL, \ - .clock = UART4_TX_DMA_CLOCK, \ - .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART4_TI, \ - .flag = UART4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART4_TX_DMA_IRQn, \ - .irq_prio = UART4_TX_DMA_INT_PRIO, \ - .int_src = UART4_TX_DMA_INT_SRC, \ - }, \ +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .clock = UART4_TX_DMA_CLOCK, \ + .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_TI, \ + .flag = UART4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART4_TX_DMA_IRQn, \ + .irq_prio = UART4_TX_DMA_INT_PRIO, \ + .int_src = UART4_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART4_DMA_TX_CONFIG */ #endif /* BSP_UART4_TX_USING_DMA */ @@ -324,90 +311,86 @@ extern "C" { #if defined(BSP_USING_UART5) #ifndef UART5_CONFIG -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = CM_USART5, \ - .clock = FCG3_PERIPH_USART5, \ - .irq_num = BSP_UART5_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART5_EI, \ - .rx_int_src = INT_SRC_USART5_RI, \ - .tx_int_src = INT_SRC_USART5_TI, \ +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .irq_num = BSP_UART5_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART5_EI, \ + .rx_int_src = INT_SRC_USART5_RI, \ + .tx_int_src = INT_SRC_USART5_TI, \ } #endif /* UART5_CONFIG */ #if defined(BSP_UART5_RX_USING_DMA) #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .channel = UART5_RX_DMA_CHANNEL, \ - .clock = UART5_RX_DMA_CLOCK, \ - .trigger_select = UART5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART5_RI, \ - .flag = UART5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART5_RX_DMA_IRQn, \ - .irq_prio = UART5_RX_DMA_INT_PRIO, \ - .int_src = UART5_RX_DMA_INT_SRC, \ - }, \ +#define UART5_DMA_RX_CONFIG \ + { \ + .Instance = UART5_RX_DMA_INSTANCE, \ + .channel = UART5_RX_DMA_CHANNEL, \ + .clock = UART5_RX_DMA_CLOCK, \ + .trigger_select = UART5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART5_RI, \ + .flag = UART5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART5_RX_DMA_IRQn, \ + .irq_prio = UART5_RX_DMA_INT_PRIO, \ + .int_src = UART5_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART5_DMA_RX_CONFIG */ #ifndef UART5_RXTO_CONFIG -#define UART5_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ +#define UART5_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ } #endif /* UART5_RXTO_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA) #ifndef UART5_TX_CPLT_CONFIG -#define UART5_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TCI, \ - }, \ +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART5_TX_CPLT_CONFIG -#define UART5_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TCI, \ - }, \ +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ } #endif #endif /* UART5_TX_CPLT_CONFIG */ #if defined(BSP_UART5_TX_USING_DMA) #ifndef UART5_DMA_TX_CONFIG -#define UART5_DMA_TX_CONFIG \ - { \ - .Instance = UART5_TX_DMA_INSTANCE, \ - .channel = UART5_TX_DMA_CHANNEL, \ - .clock = UART5_TX_DMA_CLOCK, \ - .trigger_select = UART5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART5_TI, \ - .flag = UART5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART5_TX_DMA_IRQn, \ - .irq_prio = UART5_TX_DMA_INT_PRIO, \ - .int_src = UART5_TX_DMA_INT_SRC, \ - }, \ +#define UART5_DMA_TX_CONFIG \ + { \ + .Instance = UART5_TX_DMA_INSTANCE, \ + .channel = UART5_TX_DMA_CHANNEL, \ + .clock = UART5_TX_DMA_CLOCK, \ + .trigger_select = UART5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART5_TI, \ + .flag = UART5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART5_TX_DMA_IRQn, \ + .irq_prio = UART5_TX_DMA_INT_PRIO, \ + .int_src = UART5_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART5_DMA_TX_CONFIG */ #endif /* BSP_UART5_TX_USING_DMA */ @@ -415,28 +398,27 @@ extern "C" { #if defined(BSP_USING_UART6) #ifndef UART6_CONFIG -#define UART6_CONFIG \ - { \ - .name = "uart6", \ - .Instance = CM_USART6, \ - .clock = FCG3_PERIPH_USART6, \ - .irq_num = BSP_UART6_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART6_EI, \ - .rx_int_src = INT_SRC_USART6_RI, \ - .tx_int_src = INT_SRC_USART6_TI, \ +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .irq_num = BSP_UART6_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART6_EI, \ + .rx_int_src = INT_SRC_USART6_RI, \ + .tx_int_src = INT_SRC_USART6_TI, \ } #endif /* UART6_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART6_TX_CPLT_CONFIG -#define UART6_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TCI, \ - }, \ +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ } #endif #endif /* UART6_TX_CPLT_CONFIG */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h index d6986cf429e..b569fecdb87 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/hc32f4xx_conf.h @@ -27,8 +27,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -48,53 +47,53 @@ extern "C" * Library. * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. */ -#define LL_ICG_ENABLE (DDL_ON) -#define LL_UTILITY_ENABLE (DDL_ON) -#define LL_PRINT_ENABLE (DDL_OFF) +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) -#define LL_ADC_ENABLE (DDL_ON) -#define LL_AES_ENABLE (DDL_ON) -#define LL_AOS_ENABLE (DDL_ON) -#define LL_CLK_ENABLE (DDL_ON) -#define LL_CMP_ENABLE (DDL_ON) -#define LL_CRC_ENABLE (DDL_ON) -#define LL_CTC_ENABLE (DDL_ON) -#define LL_DAC_ENABLE (DDL_ON) -#define LL_DBGC_ENABLE (DDL_OFF) -#define LL_DCU_ENABLE (DDL_ON) -#define LL_DMA_ENABLE (DDL_ON) -#define LL_EFM_ENABLE (DDL_ON) -#define LL_EMB_ENABLE (DDL_ON) -#define LL_EVENT_PORT_ENABLE (DDL_OFF) -#define LL_FCG_ENABLE (DDL_ON) -#define LL_FCM_ENABLE (DDL_ON) -#define LL_GPIO_ENABLE (DDL_ON) -#define LL_HASH_ENABLE (DDL_ON) -#define LL_I2C_ENABLE (DDL_ON) -#define LL_INTERRUPTS_ENABLE (DDL_ON) -#define LL_KEYSCAN_ENABLE (DDL_ON) -#define LL_MCAN_ENABLE (DDL_ON) -#define LL_MPU_ENABLE (DDL_ON) -#define LL_PWC_ENABLE (DDL_ON) -#define LL_QSPI_ENABLE (DDL_ON) -#define LL_RMU_ENABLE (DDL_ON) -#define LL_RTC_ENABLE (DDL_ON) -#define LL_SMC_ENABLE (DDL_ON) -#define LL_SPI_ENABLE (DDL_ON) -#define LL_SRAM_ENABLE (DDL_ON) -#define LL_SWDT_ENABLE (DDL_ON) -#define LL_TMR0_ENABLE (DDL_ON) -#define LL_TMR4_ENABLE (DDL_ON) -#define LL_TMR6_ENABLE (DDL_ON) -#define LL_TMRA_ENABLE (DDL_ON) -#define LL_TRNG_ENABLE (DDL_ON) -#define LL_USART_ENABLE (DDL_ON) -#define LL_WDT_ENABLE (DDL_ON) +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MCAN_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) /** * @brief The following is a list of currently supported BSP boards. */ -#define BSP_EV_HC32F448_LQFP80 (9U) +#define BSP_EV_HC32F448_LQFP80 (9U) /** * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently @@ -103,19 +102,19 @@ extern "C" * @note If there is no supported BSP board or the BSP function is not used, * the value needs to be set to 0U. */ -#define BSP_EV_HC32F4XX (0U) +#define BSP_EV_HC32F4XX (0U) /** * @brief This is the list of BSP components to be used. * Select the components you need to use to DDL_ON. */ -#define BSP_24CXX_ENABLE (DDL_OFF) -#define BSP_GT9XX_ENABLE (DDL_OFF) -#define BSP_IS61LV6416_ENABLE (DDL_OFF) -#define BSP_NT35510_ENABLE (DDL_OFF) -#define BSP_TCA9539_ENABLE (DDL_OFF) -#define BSP_W25QXX_ENABLE (DDL_OFF) -#define BSP_INT_KEY_ENABLE (DDL_OFF) +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_GT9XX_ENABLE (DDL_OFF) +#define BSP_IS61LV6416_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_INT_KEY_ENABLE (DDL_OFF) /******************************************************************************* * Global variable definitions ('extern') diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal_cfg.h index 1f8fb29c763..fdad15a82e9 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal_cfg.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/fal_cfg.h @@ -24,20 +24,20 @@ extern const struct fal_flash_dev hc32_onchip_flash; extern struct fal_flash_dev ext_nor_flash0; /* flash device table */ -#define FAL_FLASH_DEV_TABLE \ -{ \ - &hc32_onchip_flash, \ - &ext_nor_flash0, \ -} +#define FAL_FLASH_DEV_TABLE \ + { \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ + } /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ -#define FAL_PART_TABLE \ -{ \ - {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 256 * 1024, 0}, \ - {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ -} +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 256 * 1024, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \ + } #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539_port.h index 7a4608548ca..cf9494c05d7 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539_port.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/board/ports/tca9539_port.h @@ -17,18 +17,18 @@ * @defgroup HC32F448_EV_IO_Function_Sel Expand IO function definition * @{ */ -#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */ -#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */ -#define EIO_TOUCH_CTRST (TCA9539_IO_PIN5) /* 'Reset' for Cap touch panel, output */ -#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */ -#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */ +#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */ +#define EIO_TOUCH_CTRST (TCA9539_IO_PIN5) /* 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */ +#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */ -#define EIO_LIN_SLEEP (TCA9539_IO_PIN1) /* LIN PHY sleep, output */ -#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */ -#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */ -#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ -#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ -#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +#define EIO_LIN_SLEEP (TCA9539_IO_PIN1) /* LIN PHY sleep, output */ +#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */ +#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ /** * @} */ @@ -37,12 +37,12 @@ * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition * @{ */ -#define LED_RED_PORT (TCA9539_IO_PORT1) -#define LED_RED_PIN (EIO_LED_RED) -#define LED_YELLOW_PORT (TCA9539_IO_PORT1) -#define LED_YELLOW_PIN (EIO_LED_YELLOW) -#define LED_BLUE_PORT (TCA9539_IO_PORT1) -#define LED_BLUE_PIN (EIO_LED_BLUE) +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) /** * @} */ @@ -51,10 +51,10 @@ * @defgroup BSP CAN PHY STB port/pin definition * @{ */ -#define CAN1_STB_PORT (TCA9539_IO_PORT1) -#define CAN1_STB_PIN (EIO_CAN1_STB) -#define CAN2_STB_PORT (TCA9539_IO_PORT1) -#define CAN2_STB_PIN (EIO_CAN2_STB) +#define CAN1_STB_PORT (TCA9539_IO_PORT1) +#define CAN1_STB_PIN (EIO_CAN1_STB) +#define CAN2_STB_PORT (TCA9539_IO_PORT1) +#define CAN2_STB_PIN (EIO_CAN2_STB) /** * @} */ diff --git a/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h b/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h index 667256b56ec..d79dea3f70f 100644 --- a/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h +++ b/bsp/hc32/ev_hc32f448_lqfp80/rtconfig.h @@ -61,18 +61,18 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_CPUS_NR 1 +#define RT_NAME_MAX 24 +#define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 /* kservice options */ @@ -100,10 +100,10 @@ /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart2" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -119,12 +119,12 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -145,7 +145,7 @@ #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 -#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA @@ -163,8 +163,8 @@ #define RT_LIBC_USING_LIGHT_TZ_DST #define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* end of Timezone and Daylight Saving Time */ /* end of ISO-ANSI C layer */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml index 047a4483ef7..1412567fb0f 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/.ci/attachconfig/ci.attachconfig.yml @@ -23,11 +23,11 @@ devices.flash: - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SFUD=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/.config b/bsp/hc32/ev_hc32f460_lqfp100_v2/.config index 72db2dcd717..2791e070dcc 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/.config +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/.config @@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md b/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md index 7c6a879aef8..6712d20576d 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/README.md @@ -46,7 +46,7 @@ EV_F460_LQ100_V2 开发板常用 **板载资源** 如下： | Crypto | 支持 | CRC，HASH，RNG | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1... PH2 ---> PIN：0，1...82 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | PM | 支持 | | diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/xtal32_fcm.c index 67718d74e9c..b74f4138fd7 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/xtal32_fcm.c +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/applications/xtal32_fcm.c @@ -19,8 +19,8 @@ #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) -#define XTAL32_FCM_THREAD_STACK_SIZE (1024) -#define XTAL32_FCM_UNIT (CM_FCM) +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM) /** * @brief This thread is used to monitor whether XTAL32 is stable. @@ -37,13 +37,13 @@ void xtal32_fcm_thread_entry(void *parameter) /* FCM config */ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); (void)FCM_StructInit(&stcFcmInit); - stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; - stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ - stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; - stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; - stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); - stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); /* Enable FCM, to ensure xtal32 stable */ FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig index b2fab38d89e..4fa6b3994a9 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/Kconfig @@ -637,27 +637,27 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_CLOCK_TIMER - bool "Enable Hw Timer" + bool "Enable Clock Timer" default n select RT_USING_CLOCK_TIME if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 - bool "Use Timer_a1 As The Hw Timer" + bool "Use Timer_a1 As The Clock Timer" default n config BSP_USING_TMRA_2 - bool "Use Timer_a2 As The Hw Timer" + bool "Use Timer_a2 As The Clock Timer" default n config BSP_USING_TMRA_3 - bool "Use Timer_a3 As The Hw Timer" + bool "Use Timer_a3 As The Clock Timer" default n config BSP_USING_TMRA_4 - bool "Use Timer_a4 As The Hw Timer" + bool "Use Timer_a4 As The Clock Timer" default n config BSP_USING_TMRA_5 - bool "Use Timer_a5 As The Hw Timer" + bool "Use Timer_a5 As The Clock Timer" default n config BSP_USING_TMRA_6 - bool "Use Timer_a6 As The Hw Timer" + bool "Use Timer_a6 As The Clock Timer" default n endif menuconfig BSP_USING_INPUT_CAPTURE diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c index ba3672a90a6..121bede97ad 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.c @@ -13,9 +13,9 @@ #include "board_config.h" /* unlock/lock peripheral */ -#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ - LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) -#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) /** System Base Configuration */ @@ -30,8 +30,8 @@ void SystemBase_Config(void) */ void SystemClock_Config(void) { - stc_clock_xtal_init_t stcXtalInit; - stc_clock_pll_init_t stcMpllInit; + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcMpllInit; #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) stc_clock_pllx_init_t stcUpllInit; #endif @@ -43,14 +43,14 @@ void SystemClock_Config(void) /* PCLK1, PCLK4 Max 100MHz */ /* PCLK2, PCLK3 Max 50MHz */ /* EX BUS Max 100MHz */ - CLK_SetClockDiv(CLK_BUS_CLK_ALL, (CLK_HCLK_DIV1 | CLK_EXCLK_DIV2 | CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | \ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, (CLK_HCLK_DIV1 | CLK_EXCLK_DIV2 | CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2)); GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); (void)CLK_XtalStructInit(&stcXtalInit); /* Config Xtal and enable Xtal */ - stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; - stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; stcXtalInit.u8State = CLK_XTAL_ON; stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; (void)CLK_XtalInit(&stcXtalInit); @@ -98,8 +98,8 @@ void SystemClock_Config(void) /* Xtal32 config */ GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); (void)CLK_Xtal32StructInit(&stcXtal32Init); - stcXtal32Init.u8State = CLK_XTAL32_ON; - stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; (void)CLK_Xtal32Init(&stcXtal32Init); #endif diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h index 9ad0f9302cc..6555c11a2a1 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board.h @@ -20,27 +20,27 @@ extern "C" { #endif -#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) -#define HC32_FLASH_WRITE_GRANULARITY (4) -#define HC32_FLASH_SIZE (512 * 1024) -#define HC32_FLASH_START_ADDRESS (0) -#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) +#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (512 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) -#define HC32_SRAM_SIZE (188) -#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024) +#define HC32_SRAM_SIZE (188) +#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024) #ifdef __ARMCC_VERSION extern int Image$$RW_IRAM2$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) #elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) #else extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) +#define HEAP_BEGIN (&__bss_end) #endif -#define HEAP_END HC32_SRAM_END +#define HEAP_END HC32_SRAM_END void PeripheralRegister_Unlock(void); void PeripheralClock_Config(void); diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c index abeef5591bb..db58a649389 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.c @@ -127,7 +127,7 @@ rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) #endif -#if defined (RT_USING_SPI) +#if defined(RT_USING_SPI) rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) { rt_err_t result = RT_EOK; @@ -141,16 +141,16 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) case (rt_uint32_t)CM_SPI3: GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinState = PIN_STAT_SET; - stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinDir = PIN_DIR_OUT; GPIO_Init(SPI3_WP_PORT, SPI3_WP_PIN, &stcGpioInit); GPIO_Init(SPI3_HOLD_PORT, SPI3_HOLD_PIN, &stcGpioInit); (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; - (void)GPIO_Init(SPI3_SCK_PORT, SPI3_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI3_SCK_PORT, SPI3_SCK_PIN, &stcGpioInit); (void)GPIO_Init(SPI3_MOSI_PORT, SPI3_MOSI_PIN, &stcGpioInit); (void)GPIO_Init(SPI3_MISO_PORT, SPI3_MISO_PIN, &stcGpioInit); - GPIO_SetFunc(SPI3_SCK_PORT, SPI3_SCK_PIN, SPI3_SCK_FUNC); + GPIO_SetFunc(SPI3_SCK_PORT, SPI3_SCK_PIN, SPI3_SCK_FUNC); GPIO_SetFunc(SPI3_MOSI_PORT, SPI3_MOSI_PIN, SPI3_MOSI_FUNC); GPIO_SetFunc(SPI3_MISO_PORT, SPI3_MISO_PIN, SPI3_MISO_FUNC); break; @@ -164,7 +164,7 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) } #endif -#if defined (RT_USING_SDIO) +#if defined(RT_USING_SDIO) rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) { rt_err_t result = RT_EOK; @@ -177,19 +177,19 @@ rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) /************************* Set pin drive capacity *************************/ (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; - (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); - GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); + GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC); - GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); - GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); - GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); - GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); + GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); + GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); + GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); + GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); break; #endif default: @@ -298,24 +298,24 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) #endif #endif -#if defined (BSP_USING_INPUT_CAPTURE) +#if defined(BSP_USING_INPUT_CAPTURE) rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) { rt_err_t result = RT_EOK; switch ((rt_uint32_t)tmr_instance) { -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) case (rt_uint32_t)CM_TMR6_1: GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, GPIO_FUNC_3); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) case (rt_uint32_t)CM_TMR6_2: GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, GPIO_FUNC_3); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) case (rt_uint32_t)CM_TMR6_3: GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, GPIO_FUNC_3); break; @@ -395,8 +395,8 @@ rt_err_t rt_hw_qspi_board_init(void) (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; #ifndef BSP_QSPI_USING_SOFT_CS - (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); - GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); #endif (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h index 48a4d29a19c..64f9236470b 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/board_config.h @@ -16,309 +16,309 @@ #include "hc32_ll.h" #include "drv_config.h" #if defined(RT_USING_CHERRYUSB) - #include "usb_config.h" +#include "usb_config.h" #endif /************************* XTAL port **********************/ -#define XTAL_PORT (GPIO_PORT_H) -#define XTAL_IN_PIN (GPIO_PIN_01) -#define XTAL_OUT_PIN (GPIO_PIN_00) +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_IN_PIN (GPIO_PIN_01) +#define XTAL_OUT_PIN (GPIO_PIN_00) /************************ USART port **********************/ #if defined(BSP_USING_UART2) - #define USART2_RX_PORT (GPIO_PORT_A) - #define USART2_RX_PIN (GPIO_PIN_03) - #define USART2_RX_FUNC (GPIO_FUNC_37) +#define USART2_RX_PORT (GPIO_PORT_A) +#define USART2_RX_PIN (GPIO_PIN_03) +#define USART2_RX_FUNC (GPIO_FUNC_37) - #define USART2_TX_PORT (GPIO_PORT_A) - #define USART2_TX_PIN (GPIO_PIN_02) - #define USART2_TX_FUNC (GPIO_FUNC_36) +#define USART2_TX_PORT (GPIO_PORT_A) +#define USART2_TX_PIN (GPIO_PIN_02) +#define USART2_TX_FUNC (GPIO_FUNC_36) #endif #if defined(BSP_USING_UART4) - #define USART4_RX_PORT (GPIO_PORT_B) - #define USART4_RX_PIN (GPIO_PIN_09) - #define USART4_RX_FUNC (GPIO_FUNC_37) +#define USART4_RX_PORT (GPIO_PORT_B) +#define USART4_RX_PIN (GPIO_PIN_09) +#define USART4_RX_FUNC (GPIO_FUNC_37) - #define USART4_TX_PORT (GPIO_PORT_E) - #define USART4_TX_PIN (GPIO_PIN_06) - #define USART4_TX_FUNC (GPIO_FUNC_36) +#define USART4_TX_PORT (GPIO_PORT_E) +#define USART4_TX_PIN (GPIO_PIN_06) +#define USART4_TX_FUNC (GPIO_FUNC_36) #endif /************************ I2C port **********************/ #if defined(BSP_USING_I2C1) - #define I2C1_SDA_PORT (GPIO_PORT_A) - #define I2C1_SDA_PIN (GPIO_PIN_07) - #define I2C1_SDA_FUNC (GPIO_FUNC_48) +#define I2C1_SDA_PORT (GPIO_PORT_A) +#define I2C1_SDA_PIN (GPIO_PIN_07) +#define I2C1_SDA_FUNC (GPIO_FUNC_48) - #define I2C1_SCL_PORT (GPIO_PORT_C) - #define I2C1_SCL_PIN (GPIO_PIN_04) - #define I2C1_SCL_FUNC (GPIO_FUNC_49) +#define I2C1_SCL_PORT (GPIO_PORT_C) +#define I2C1_SCL_PIN (GPIO_PIN_04) +#define I2C1_SCL_FUNC (GPIO_FUNC_49) #endif #if defined(BSP_USING_I2C3) - #define I2C3_SDA_PORT (GPIO_PORT_B) - #define I2C3_SDA_PIN (GPIO_PIN_05) - #define I2C3_SDA_FUNC (GPIO_FUNC_48) +#define I2C3_SDA_PORT (GPIO_PORT_B) +#define I2C3_SDA_PIN (GPIO_PIN_05) +#define I2C3_SDA_FUNC (GPIO_FUNC_48) - #define I2C3_SCL_PORT (GPIO_PORT_E) - #define I2C3_SCL_PIN (GPIO_PIN_15) - #define I2C3_SCL_FUNC (GPIO_FUNC_49) +#define I2C3_SCL_PORT (GPIO_PORT_E) +#define I2C3_SCL_PIN (GPIO_PIN_15) +#define I2C3_SCL_FUNC (GPIO_FUNC_49) #endif /*********** ADC configure *********/ #if defined(BSP_USING_ADC1) - #define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */ - #define ADC1_CH_PIN (GPIO_PIN_00) +#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN10 */ +#define ADC1_CH_PIN (GPIO_PIN_00) #endif #if defined(BSP_USING_ADC2) - #define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN11 */ - #define ADC2_CH_PIN (GPIO_PIN_01) +#define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC12_IN11 */ +#define ADC2_CH_PIN (GPIO_PIN_01) #endif /*********** CAN configure *********/ #if defined(BSP_USING_CAN1) - #define CAN1_TX_PORT (GPIO_PORT_B) - #define CAN1_TX_PIN (GPIO_PIN_07) - #define CAN1_TX_PIN_FUNC (GPIO_FUNC_50) +#define CAN1_TX_PORT (GPIO_PORT_B) +#define CAN1_TX_PIN (GPIO_PIN_07) +#define CAN1_TX_PIN_FUNC (GPIO_FUNC_50) - #define CAN1_RX_PORT (GPIO_PORT_B) - #define CAN1_RX_PIN (GPIO_PIN_06) - #define CAN1_RX_PIN_FUNC (GPIO_FUNC_51) +#define CAN1_RX_PORT (GPIO_PORT_B) +#define CAN1_RX_PIN (GPIO_PIN_06) +#define CAN1_RX_PIN_FUNC (GPIO_FUNC_51) - #define CAN1_STB_PORT (GPIO_PORT_D) - #define CAN1_STB_PIN (GPIO_PIN_15) +#define CAN1_STB_PORT (GPIO_PORT_D) +#define CAN1_STB_PIN (GPIO_PIN_15) #endif /************************* SPI port ***********************/ #if defined(BSP_USING_SPI3) - #define SPI3_CS_PORT (GPIO_PORT_C) - #define SPI3_CS_PIN (GPIO_PIN_07) +#define SPI3_CS_PORT (GPIO_PORT_C) +#define SPI3_CS_PIN (GPIO_PIN_07) - #define SPI3_SCK_PORT (GPIO_PORT_C) - #define SPI3_SCK_PIN (GPIO_PIN_06) - #define SPI3_SCK_FUNC (GPIO_FUNC_43) +#define SPI3_SCK_PORT (GPIO_PORT_C) +#define SPI3_SCK_PIN (GPIO_PIN_06) +#define SPI3_SCK_FUNC (GPIO_FUNC_43) - #define SPI3_MOSI_PORT (GPIO_PORT_D) - #define SPI3_MOSI_PIN (GPIO_PIN_08) - #define SPI3_MOSI_FUNC (GPIO_FUNC_40) +#define SPI3_MOSI_PORT (GPIO_PORT_D) +#define SPI3_MOSI_PIN (GPIO_PIN_08) +#define SPI3_MOSI_FUNC (GPIO_FUNC_40) - #define SPI3_MISO_PORT (GPIO_PORT_D) - #define SPI3_MISO_PIN (GPIO_PIN_09) - #define SPI3_MISO_FUNC (GPIO_FUNC_41) +#define SPI3_MISO_PORT (GPIO_PORT_D) +#define SPI3_MISO_PIN (GPIO_PIN_09) +#define SPI3_MISO_FUNC (GPIO_FUNC_41) - #define SPI3_WP_PORT (GPIO_PORT_D) - #define SPI3_WP_PIN (GPIO_PIN_10) +#define SPI3_WP_PORT (GPIO_PORT_D) +#define SPI3_WP_PIN (GPIO_PIN_10) - #define SPI3_HOLD_PORT (GPIO_PORT_D) - #define SPI3_HOLD_PIN (GPIO_PIN_11) +#define SPI3_HOLD_PORT (GPIO_PORT_D) +#define SPI3_HOLD_PIN (GPIO_PIN_11) #endif /************************ SDIOC port **********************/ #if defined(BSP_USING_SDIO1) - #define SDIOC1_CK_PORT (GPIO_PORT_C) - #define SDIOC1_CK_PIN (GPIO_PIN_12) - #define SDIOC1_CK_FUNC (GPIO_FUNC_9) +#define SDIOC1_CK_PORT (GPIO_PORT_C) +#define SDIOC1_CK_PIN (GPIO_PIN_12) +#define SDIOC1_CK_FUNC (GPIO_FUNC_9) - #define SDIOC1_CMD_PORT (GPIO_PORT_D) - #define SDIOC1_CMD_PIN (GPIO_PIN_02) - #define SDIOC1_CMD_FUNC (GPIO_FUNC_9) +#define SDIOC1_CMD_PORT (GPIO_PORT_D) +#define SDIOC1_CMD_PIN (GPIO_PIN_02) +#define SDIOC1_CMD_FUNC (GPIO_FUNC_9) - #define SDIOC1_D0_PORT (GPIO_PORT_C) - #define SDIOC1_D0_PIN (GPIO_PIN_08) - #define SDIOC1_D0_FUNC (GPIO_FUNC_9) +#define SDIOC1_D0_PORT (GPIO_PORT_C) +#define SDIOC1_D0_PIN (GPIO_PIN_08) +#define SDIOC1_D0_FUNC (GPIO_FUNC_9) - #define SDIOC1_D1_PORT (GPIO_PORT_C) - #define SDIOC1_D1_PIN (GPIO_PIN_09) - #define SDIOC1_D1_FUNC (GPIO_FUNC_9) +#define SDIOC1_D1_PORT (GPIO_PORT_C) +#define SDIOC1_D1_PIN (GPIO_PIN_09) +#define SDIOC1_D1_FUNC (GPIO_FUNC_9) - #define SDIOC1_D2_PORT (GPIO_PORT_C) - #define SDIOC1_D2_PIN (GPIO_PIN_10) - #define SDIOC1_D2_FUNC (GPIO_FUNC_9) +#define SDIOC1_D2_PORT (GPIO_PORT_C) +#define SDIOC1_D2_PIN (GPIO_PIN_10) +#define SDIOC1_D2_FUNC (GPIO_FUNC_9) - #define SDIOC1_D3_PORT (GPIO_PORT_C) - #define SDIOC1_D3_PIN (GPIO_PIN_11) - #define SDIOC1_D3_FUNC (GPIO_FUNC_9) +#define SDIOC1_D3_PORT (GPIO_PORT_C) +#define SDIOC1_D3_PIN (GPIO_PIN_11) +#define SDIOC1_D3_FUNC (GPIO_FUNC_9) #endif /************************ RTC/PM *****************************/ #if defined(BSP_USING_RTC) || defined(RT_USING_PM) - #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) - #define XTAL32_PORT (GPIO_PORT_C) - #define XTAL32_IN_PIN (GPIO_PIN_15) - #define XTAL32_OUT_PIN (GPIO_PIN_14) - #endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) +#define XTAL32_PORT (GPIO_PORT_C) +#define XTAL32_IN_PIN (GPIO_PIN_15) +#define XTAL32_OUT_PIN (GPIO_PIN_14) +#endif #endif #if defined(RT_USING_PWM) /*********** PWM_TMRA configure *********/ - #if defined(BSP_USING_PWM_TMRA_1) - #if defined(BSP_USING_PWM_TMRA_1_CH1) - #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) - #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH2) - #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) - #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH3) - #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) - #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH4) - #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) - #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) - #endif - #endif +#if defined(BSP_USING_PWM_TMRA_1) +#if defined(BSP_USING_PWM_TMRA_1_CH1) +#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) +#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH2) +#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) +#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH3) +#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) +#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH4) +#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) +#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) +#endif +#endif /*********** PWM_TMR4 configure *********/ - #if defined(BSP_USING_PWM_TMR4_1) - #if defined(BSP_USING_PWM_TMR4_1_OUH) - #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) - #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OUL) - #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) - #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVH) - #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) - #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVL) - #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) - #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWH) - #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) - #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWL) - #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) - #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) - #endif - #endif +#if defined(BSP_USING_PWM_TMR4_1) +#if defined(BSP_USING_PWM_TMR4_1_OUH) +#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) +#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OUL) +#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) +#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVH) +#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) +#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVL) +#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) +#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWH) +#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) +#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWL) +#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) +#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) +#endif +#endif /*********** PWM_TMR6 configure *********/ - #if defined(BSP_USING_PWM_TMR6_1) - #if defined(BSP_USING_PWM_TMR6_1_A) - #define PWM_TMR6_1_A_PORT (GPIO_PORT_A) - #define PWM_TMR6_1_A_PIN (GPIO_PIN_08) - #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #endif - #if defined(BSP_USING_PWM_TMR6_1_B) - #define PWM_TMR6_1_B_PORT (GPIO_PORT_A) - #define PWM_TMR6_1_B_PIN (GPIO_PIN_07) - #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif - #endif +#if defined(BSP_USING_PWM_TMR6_1) +#if defined(BSP_USING_PWM_TMR6_1_A) +#define PWM_TMR6_1_A_PORT (GPIO_PORT_A) +#define PWM_TMR6_1_A_PIN (GPIO_PIN_08) +#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#endif +#if defined(BSP_USING_PWM_TMR6_1_B) +#define PWM_TMR6_1_B_PORT (GPIO_PORT_A) +#define PWM_TMR6_1_B_PIN (GPIO_PIN_07) +#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif +#endif #endif #if defined(BSP_USING_INPUT_CAPTURE) - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) - #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A) - #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08) - #define INPUT_CAPTURE_TMR6_1_PIN_FUNC (GPIO_FUNC_3) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) - #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B) - #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02) - #define INPUT_CAPTURE_TMR6_2_PIN_FUNC (GPIO_FUNC_3) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) - #define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) - #define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_12) - #define INPUT_CAPTURE_TMR6_3_PIN_FUNC (GPIO_FUNC_3) - #endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A) +#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08) +#define INPUT_CAPTURE_TMR6_1_PIN_FUNC (GPIO_FUNC_3) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B) +#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02) +#define INPUT_CAPTURE_TMR6_2_PIN_FUNC (GPIO_FUNC_3) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) +#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) +#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_12) +#define INPUT_CAPTURE_TMR6_3_PIN_FUNC (GPIO_FUNC_3) +#endif #endif #if defined(RT_USING_CHERRYUSB) - #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ - defined(BSP_USING_USBFS) || defined(RT_USING_USB) - #error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" - #endif +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(RT_USING_USB) +#error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" +#endif #endif #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) - #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) /* USBFS Core*/ - #define USBF_DP_PORT (GPIO_PORT_A) - #define USBF_DP_PIN (GPIO_PIN_12) - #define USBF_DM_PORT (GPIO_PORT_A) - #define USBF_DM_PIN (GPIO_PIN_11) - #define USBF_VBUS_PORT (GPIO_PORT_A) - #define USBF_VBUS_PIN (GPIO_PIN_09) - #define USBF_VBUS_FUNC (GPIO_FUNC_10) - #define USBF_DRVVBUS_PORT (GPIO_PORT_B) - #define USBF_DRVVBUS_PIN (GPIO_PIN_08) - #define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) - #endif +#define USBF_DP_PORT (GPIO_PORT_A) +#define USBF_DP_PIN (GPIO_PIN_12) +#define USBF_DM_PORT (GPIO_PORT_A) +#define USBF_DM_PIN (GPIO_PIN_11) +#define USBF_VBUS_PORT (GPIO_PORT_A) +#define USBF_VBUS_PIN (GPIO_PIN_09) +#define USBF_VBUS_FUNC (GPIO_FUNC_10) +#define USBF_DRVVBUS_PORT (GPIO_PORT_B) +#define USBF_DRVVBUS_PIN (GPIO_PIN_08) +#define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) +#endif #endif #if defined(BSP_USING_QSPI) - #ifndef BSP_QSPI_USING_SOFT_CS +#ifndef BSP_QSPI_USING_SOFT_CS /* QSSN */ - #define QSPI_FLASH_CS_PORT (GPIO_PORT_C) - #define QSPI_FLASH_CS_PIN (GPIO_PIN_07) - #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_7) - #endif +#define QSPI_FLASH_CS_PORT (GPIO_PORT_C) +#define QSPI_FLASH_CS_PIN (GPIO_PIN_07) +#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_7) +#endif /* QSCK */ - #define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) - #define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) - #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_7) +#define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) +#define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) +#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_7) /* QSIO0 */ - #define QSPI_FLASH_IO0_PORT (GPIO_PORT_D) - #define QSPI_FLASH_IO0_PIN (GPIO_PIN_08) - #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_7) +#define QSPI_FLASH_IO0_PORT (GPIO_PORT_D) +#define QSPI_FLASH_IO0_PIN (GPIO_PIN_08) +#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_7) /* QSIO1 */ - #define QSPI_FLASH_IO1_PORT (GPIO_PORT_D) - #define QSPI_FLASH_IO1_PIN (GPIO_PIN_09) - #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_7) +#define QSPI_FLASH_IO1_PORT (GPIO_PORT_D) +#define QSPI_FLASH_IO1_PIN (GPIO_PIN_09) +#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_7) /* QSIO2 */ - #define QSPI_FLASH_IO2_PORT (GPIO_PORT_D) - #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) - #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_7) +#define QSPI_FLASH_IO2_PORT (GPIO_PORT_D) +#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) +#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_7) /* QSIO3 */ - #define QSPI_FLASH_IO3_PORT (GPIO_PORT_D) - #define QSPI_FLASH_IO3_PIN (GPIO_PIN_11) - #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_7) +#define QSPI_FLASH_IO3_PORT (GPIO_PORT_D) +#define QSPI_FLASH_IO3_PIN (GPIO_PIN_11) +#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_7) #endif /*********** TMRA_PULSE_ENCODER configure *********/ #if defined(RT_USING_PULSE_ENCODER) - #if defined(BSP_USING_TMRA_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) - #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) - #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) - #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) - #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) - #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ - #endif /* BSP_USING_TMRA_PULSE_ENCODER */ - - #if defined(BSP_USING_TMR6_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) - #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_E) - #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) - #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_E) - #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) - #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ - #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) +#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#endif /* BSP_USING_TMRA_PULSE_ENCODER */ + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_E) +#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_E) +#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#endif /* BSP_USING_TMR6_PULSE_ENCODER */ #endif /* RT_USING_PULSE_ENCODER */ #endif diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h index 208ce7719c6..5bdbeb36178 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/adc_config.h @@ -20,42 +20,41 @@ extern "C" { #ifdef BSP_USING_ADC1 #ifndef ADC1_INIT_PARAMS -#define ADC1_INIT_PARAMS \ - { \ - .name = "adc1", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC1_INIT_PARAMS */ -#if defined (BSP_ADC1_USING_DMA) +#if defined(BSP_ADC1_USING_DMA) #ifndef ADC1_EOCA_DMA_CONFIG -#define ADC1_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC1_EOCA_DMA_INSTANCE, \ - .channel = ADC1_EOCA_DMA_CHANNEL, \ - .clock = ADC1_EOCA_DMA_CLOCK, \ - .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC1_EOCA, \ - .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC1_EOCA_DMA_IRQn, \ - .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ - .int_src = ADC1_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC1_EOCA_DMA_CONFIG */ #endif /* BSP_ADC1_USING_DMA */ @@ -63,42 +62,41 @@ extern "C" { #ifdef BSP_USING_ADC2 #ifndef ADC2_INIT_PARAMS -#define ADC2_INIT_PARAMS \ - { \ - .name = "adc2", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC2_INIT_PARAMS */ -#if defined (BSP_ADC2_USING_DMA) +#if defined(BSP_ADC2_USING_DMA) #ifndef ADC2_EOCA_DMA_CONFIG -#define ADC2_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC2_EOCA_DMA_INSTANCE, \ - .channel = ADC2_EOCA_DMA_CHANNEL, \ - .clock = ADC2_EOCA_DMA_CLOCK, \ - .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC2_EOCA, \ - .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC2_EOCA_DMA_IRQn, \ - .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ - .int_src = ADC2_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC2_EOCA_DMA_CONFIG */ #endif /* BSP_ADC2_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/can_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/can_config.h index 3f30ee9c322..e78a3110cfa 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/can_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/can_config.h @@ -19,12 +19,12 @@ extern "C" { #endif #ifdef BSP_USING_CAN1 -#define CAN1_NAME ("can1") +#define CAN1_NAME ("can1") #ifndef CAN1_INIT_PARAMS -#define CAN1_INIT_PARAMS \ - { \ - .name = CAN1_NAME, \ - .single_trans_mode = RT_FALSE \ +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ } #endif /* CAN1_INIT_PARAMS */ #endif /* BSP_USING_CAN1 */ @@ -38,76 +38,76 @@ extern "C" { The following bit time configures are based on CAN Clock 8M */ -#define CAN_BIT_TIME_CONFIG_1M_BAUD \ - { \ - .u32Prescaler = 1, \ - .u32TimeSeg1 = 6, \ - .u32TimeSeg2 = 2, \ - .u32SJW = 2 \ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 1, \ + .u32TimeSeg1 = 6, \ + .u32TimeSeg2 = 2, \ + .u32SJW = 2 \ } -#define CAN_BIT_TIME_CONFIG_800K_BAUD \ - { \ - .u32Prescaler = 1, \ - .u32TimeSeg1 = 7, \ - .u32TimeSeg2 = 3, \ - .u32SJW = 3 \ +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 1, \ + .u32TimeSeg1 = 7, \ + .u32TimeSeg2 = 3, \ + .u32SJW = 3 \ } -#define CAN_BIT_TIME_CONFIG_500K_BAUD \ - { \ - .u32Prescaler = 1, \ - .u32TimeSeg1 = 12, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 1, \ + .u32TimeSeg1 = 12, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_250K_BAUD \ - { \ - .u32Prescaler = 2, \ - .u32TimeSeg1 = 12, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 12, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_125K_BAUD \ - { \ - .u32Prescaler = 4, \ - .u32TimeSeg1 = 12, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 12, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_100K_BAUD \ - { \ - .u32Prescaler = 4, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_50K_BAUD \ - { \ - .u32Prescaler = 8, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_20K_BAUD \ - { \ - .u32Prescaler = 20, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_10K_BAUD \ - { \ - .u32Prescaler = 40, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/dma_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/dma_config.h index fc71a653222..6d1b6eebf4d 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/dma_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/dma_config.h @@ -20,287 +20,287 @@ extern "C" { /* DMA1 ch0 */ #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) -#define SPI1_RX_DMA_INSTANCE CM_DMA1 -#define SPI1_RX_DMA_CHANNEL DMA_CH0 -#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE) -#define SDIO1_RX_DMA_INSTANCE CM_DMA1 -#define SDIO1_RX_DMA_CHANNEL DMA_CH0 -#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SDIO1_RX_DMA_INSTANCE CM_DMA1 +#define SDIO1_RX_DMA_CHANNEL DMA_CH0 +#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) -#define I2C1_TX_DMA_INSTANCE CM_DMA1 -#define I2C1_TX_DMA_CHANNEL DMA_CH0 -#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 -#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) -#define UART1_RX_DMA_INSTANCE CM_DMA1 -#define UART1_RX_DMA_CHANNEL DMA_CH0 -#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define UART1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define UART1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define UART1_RX_DMA_INSTANCE CM_DMA1 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #endif /* DMA1 ch1 */ #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) -#define SPI1_TX_DMA_INSTANCE CM_DMA1 -#define SPI1_TX_DMA_CHANNEL DMA_CH1 -#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE) -#define SDIO1_TX_DMA_INSTANCE CM_DMA1 -#define SDIO1_TX_DMA_CHANNEL DMA_CH1 -#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SDIO1_TX_DMA_INSTANCE CM_DMA1 +#define SDIO1_TX_DMA_CHANNEL DMA_CH1 +#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) -#define I2C1_RX_DMA_INSTANCE CM_DMA1 -#define I2C1_RX_DMA_CHANNEL DMA_CH1 -#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 -#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) -#define UART2_RX_DMA_INSTANCE CM_DMA1 -#define UART2_RX_DMA_CHANNEL DMA_CH1 -#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART2_RX_DMA_TRIG_SELECT AOS_DMA1_1 -#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define UART2_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define UART2_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define UART2_RX_DMA_INSTANCE CM_DMA1 +#define UART2_RX_DMA_CHANNEL DMA_CH1 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART2_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 #endif /* DMA1 ch2 */ #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) -#define SPI2_RX_DMA_INSTANCE CM_DMA1 -#define SPI2_RX_DMA_CHANNEL DMA_CH2 -#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE) -#define SDIO2_RX_DMA_INSTANCE CM_DMA1 -#define SDIO2_RX_DMA_CHANNEL DMA_CH2 -#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define SDIO2_RX_DMA_INSTANCE CM_DMA1 +#define SDIO2_RX_DMA_CHANNEL DMA_CH2 +#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) -#define I2C2_TX_DMA_INSTANCE CM_DMA1 -#define I2C2_TX_DMA_CHANNEL DMA_CH2 -#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 -#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) -#define UART3_RX_DMA_INSTANCE CM_DMA1 -#define UART3_RX_DMA_CHANNEL DMA_CH2 -#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART3_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define UART3_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define UART3_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define UART3_RX_DMA_INSTANCE CM_DMA1 +#define UART3_RX_DMA_CHANNEL DMA_CH2 +#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART3_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART3_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define UART3_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) -#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC1_EOCA_DMA_CHANNEL DMA_CH2 -#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_2 -#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC1_EOCA_DMA_CHANNEL DMA_CH2 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_2 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC2 #endif /* DMA1 ch3 */ #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) -#define SPI2_TX_DMA_INSTANCE CM_DMA1 -#define SPI2_TX_DMA_CHANNEL DMA_CH3 -#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE) -#define SDIO2_TX_DMA_INSTANCE CM_DMA1 -#define SDIO2_TX_DMA_CHANNEL DMA_CH3 -#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define SDIO2_TX_DMA_INSTANCE CM_DMA1 +#define SDIO2_TX_DMA_CHANNEL DMA_CH3 +#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) -#define I2C2_RX_DMA_INSTANCE CM_DMA1 -#define I2C2_RX_DMA_CHANNEL DMA_CH3 -#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 -#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) -#define UART4_RX_DMA_INSTANCE CM_DMA1 -#define UART4_RX_DMA_CHANNEL DMA_CH3 -#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART4_RX_DMA_TRIG_SELECT AOS_DMA1_3 -#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define UART4_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define UART4_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define UART4_RX_DMA_INSTANCE CM_DMA1 +#define UART4_RX_DMA_CHANNEL DMA_CH3 +#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART4_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART4_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define UART4_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 #endif /* DMA2 ch0 */ #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) -#define SPI3_RX_DMA_INSTANCE CM_DMA2 -#define SPI3_RX_DMA_CHANNEL DMA_CH0 -#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA2_0 -#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SPI3_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define SPI3_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define SPI3_RX_DMA_INSTANCE CM_DMA2 +#define SPI3_RX_DMA_CHANNEL DMA_CH0 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI3_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 #elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) -#define I2C3_TX_DMA_INSTANCE CM_DMA2 -#define I2C3_TX_DMA_CHANNEL DMA_CH0 -#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA2_0 -#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define I2C3_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define I2C3_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define I2C3_TX_DMA_INSTANCE CM_DMA2 +#define I2C3_TX_DMA_CHANNEL DMA_CH0 +#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA2_0 +#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C3_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define I2C3_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 #elif defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) -#define UART1_TX_DMA_INSTANCE CM_DMA2 -#define UART1_TX_DMA_CHANNEL DMA_CH0 -#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_0 -#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define UART1_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH0 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) -#define ADC2_EOCA_DMA_INSTANCE CM_DMA2 -#define ADC2_EOCA_DMA_CHANNEL DMA_CH0 -#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA2_0 -#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define ADC2_EOCA_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define ADC2_EOCA_DMA_INSTANCE CM_DMA2 +#define ADC2_EOCA_DMA_CHANNEL DMA_CH0 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA2_0 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define ADC2_EOCA_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA2_TC0 #endif /* DMA2 ch1 */ #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) -#define SPI3_TX_DMA_INSTANCE CM_DMA2 -#define SPI3_TX_DMA_CHANNEL DMA_CH1 -#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA2_1 -#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SPI3_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define SPI3_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define SPI3_TX_DMA_INSTANCE CM_DMA2 +#define SPI3_TX_DMA_CHANNEL DMA_CH1 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI3_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 #elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) -#define I2C3_RX_DMA_INSTANCE CM_DMA2 -#define I2C3_RX_DMA_CHANNEL DMA_CH1 -#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA2_1 -#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define I2C3_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define I2C3_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define I2C3_RX_DMA_INSTANCE CM_DMA2 +#define I2C3_RX_DMA_CHANNEL DMA_CH1 +#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA2_1 +#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C3_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define I2C3_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 #elif defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) -#define UART2_TX_DMA_INSTANCE CM_DMA2 -#define UART2_TX_DMA_CHANNEL DMA_CH1 -#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_1 -#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define UART2_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH1 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 #endif /* DMA2 ch2 */ #if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) -#define SPI4_RX_DMA_INSTANCE CM_DMA2 -#define SPI4_RX_DMA_CHANNEL DMA_CH2 -#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA2_2 -#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SPI4_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define SPI4_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define SPI4_RX_DMA_INSTANCE CM_DMA2 +#define SPI4_RX_DMA_CHANNEL DMA_CH2 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI4_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) -#define UART3_TX_DMA_INSTANCE CM_DMA2 -#define UART3_TX_DMA_CHANNEL DMA_CH2 -#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART3_TX_DMA_TRIG_SELECT AOS_DMA2_2 -#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define UART3_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define UART3_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define UART3_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define UART3_TX_DMA_INSTANCE CM_DMA2 +#define UART3_TX_DMA_CHANNEL DMA_CH2 +#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART3_TX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART3_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART3_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART3_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 #elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE) -#define QSPI_DMA_INSTANCE CM_DMA2 -#define QSPI_DMA_CHANNEL DMA_CH2 -#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define QSPI_DMA_TRIG_SELECT AOS_DMA2_2 -#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define QSPI_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define QSPI_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define QSPI_DMA_INSTANCE CM_DMA2 +#define QSPI_DMA_CHANNEL DMA_CH2 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA2_2 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define QSPI_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC2 #endif /* DMA2 ch3 */ #if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) -#define SPI4_TX_DMA_INSTANCE CM_DMA2 -#define SPI4_TX_DMA_CHANNEL DMA_CH3 -#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA2_3 -#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SPI4_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM -#define SPI4_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO -#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#define SPI4_TX_DMA_INSTANCE CM_DMA2 +#define SPI4_TX_DMA_CHANNEL DMA_CH3 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI4_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 #elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) -#define UART4_TX_DMA_INSTANCE CM_DMA2 -#define UART4_TX_DMA_CHANNEL DMA_CH3 -#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_3 -#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define UART4_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM -#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO -#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#define UART4_TX_DMA_INSTANCE CM_DMA2 +#define UART4_TX_DMA_CHANNEL DMA_CH3 +#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART4_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/gpio_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/gpio_config.h index ee17e1230de..9a2be5862fa 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/gpio_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/gpio_config.h @@ -22,146 +22,146 @@ extern "C" { #if defined(RT_USING_PIN) #ifndef EXTINT0_IRQ_CONFIG -#define EXTINT0_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT0_IRQ_NUM, \ - .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ0, \ +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT1_IRQ_CONFIG -#define EXTINT1_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT1_IRQ_NUM, \ - .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ1, \ +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT2_IRQ_CONFIG -#define EXTINT2_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT2_IRQ_NUM, \ - .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ2, \ +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ } #endif /* EXTINT2_IRQ_CONFIG */ #ifndef EXTINT3_IRQ_CONFIG -#define EXTINT3_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT3_IRQ_NUM, \ - .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ3, \ +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ } #endif /* EXTINT3_IRQ_CONFIG */ #ifndef EXTINT4_IRQ_CONFIG -#define EXTINT4_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT4_IRQ_NUM, \ - .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ4, \ +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ } #endif /* EXTINT4_IRQ_CONFIG */ #ifndef EXTINT5_IRQ_CONFIG -#define EXTINT5_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT5_IRQ_NUM, \ - .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ5, \ +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ } #endif /* EXTINT5_IRQ_CONFIG */ #ifndef EXTINT6_IRQ_CONFIG -#define EXTINT6_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT6_IRQ_NUM, \ - .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ6, \ +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ } #endif /* EXTINT6_IRQ_CONFIG */ #ifndef EXTINT7_IRQ_CONFIG -#define EXTINT7_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT7_IRQ_NUM, \ - .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ7, \ +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ } #endif /* EXTINT7_IRQ_CONFIG */ #ifndef EXTINT8_IRQ_CONFIG -#define EXTINT8_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT8_IRQ_NUM, \ - .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ8, \ +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ } #endif /* EXTINT8_IRQ_CONFIG */ #ifndef EXTINT9_IRQ_CONFIG -#define EXTINT9_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT9_IRQ_NUM, \ - .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ9, \ +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ } #endif /* EXTINT9_IRQ_CONFIG */ #ifndef EXTINT10_IRQ_CONFIG -#define EXTINT10_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT10_IRQ_NUM, \ - .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ10, \ +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ } #endif /* EXTINT10_IRQ_CONFIG */ #ifndef EXTINT11_IRQ_CONFIG -#define EXTINT11_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT11_IRQ_NUM, \ - .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ11, \ +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ } #endif /* EXTINT11_IRQ_CONFIG */ #ifndef EXTINT12_IRQ_CONFIG -#define EXTINT12_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT12_IRQ_NUM, \ - .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ12, \ +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ } #endif /* EXTINT12_IRQ_CONFIG */ #ifndef EXTINT13_IRQ_CONFIG -#define EXTINT13_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT13_IRQ_NUM, \ - .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ13, \ +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ } #endif /* EXTINT13_IRQ_CONFIG */ #ifndef EXTINT14_IRQ_CONFIG -#define EXTINT14_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT14_IRQ_NUM, \ - .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ14, \ +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ } #endif /* EXTINT14_IRQ_CONFIG */ #ifndef EXTINT15_IRQ_CONFIG -#define EXTINT15_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT15_IRQ_NUM, \ - .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ15, \ +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ } #endif /* EXTINT15_IRQ_CONFIG */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/i2c_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/i2c_config.h index 6c81c2773fd..892a130e802 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/i2c_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/i2c_config.h @@ -20,101 +20,97 @@ extern "C" { #if defined(BSP_USING_I2C1) #ifndef I2C1_CONFIG -#define I2C1_CONFIG \ - { \ - .name = "i2c1", \ - .Instance = CM_I2C1, \ - .clock = FCG1_PERIPH_I2C1, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C1_CONFIG */ #endif #if defined(BSP_I2C1_USING_DMA) #ifndef I2C1_TX_DMA_CONFIG -#define I2C1_TX_DMA_CONFIG \ - { \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .channel = I2C1_TX_DMA_CHANNEL, \ - .clock = I2C1_TX_DMA_CLOCK, \ - .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_TEI, \ - .flag = I2C1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_TX_DMA_IRQn, \ - .irq_prio = I2C1_TX_DMA_INT_PRIO, \ - .int_src = I2C1_TX_DMA_INT_SRC, \ - }, \ +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_TX_DMA_CONFIG */ #ifndef I2C1_RX_DMA_CONFIG -#define I2C1_RX_DMA_CONFIG \ - { \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .channel = I2C1_RX_DMA_CHANNEL, \ - .clock = I2C1_RX_DMA_CLOCK, \ - .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_RXI, \ - .flag = I2C1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_RX_DMA_IRQn, \ - .irq_prio = I2C1_RX_DMA_INT_PRIO, \ - .int_src = I2C1_RX_DMA_INT_SRC, \ - }, \ +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_RX_DMA_CONFIG */ #endif /* BSP_I2C1_USING_DMA */ #if defined(BSP_USING_I2C2) #ifndef I2C2_CONFIG -#define I2C2_CONFIG \ - { \ - .name = "i2c2", \ - .Instance = CM_I2C2, \ - .clock = FCG1_PERIPH_I2C2, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C2_CONFIG */ #if defined(BSP_I2C2_USING_DMA) #ifndef I2C2_TX_DMA_CONFIG -#define I2C2_TX_DMA_CONFIG \ - { \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .channel = I2C2_TX_DMA_CHANNEL, \ - .clock = I2C2_TX_DMA_CLOCK, \ - .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_TEI, \ - .flag = I2C2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_TX_DMA_IRQn, \ - .irq_prio = I2C2_TX_DMA_INT_PRIO, \ - .int_src = I2C2_TX_DMA_INT_SRC, \ - }, \ +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_TX_DMA_CONFIG */ #ifndef I2C2_RX_DMA_CONFIG -#define I2C2_RX_DMA_CONFIG \ - { \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .channel = I2C2_RX_DMA_CHANNEL, \ - .clock = I2C2_RX_DMA_CLOCK, \ - .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_RXI, \ - .flag = I2C2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_RX_DMA_IRQn, \ - .irq_prio = I2C2_RX_DMA_INT_PRIO, \ - .int_src = I2C2_RX_DMA_INT_SRC, \ - }, \ +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_RX_DMA_CONFIG */ #endif /* BSP_I2C2_USING_DMA */ @@ -122,50 +118,48 @@ extern "C" { #if defined(BSP_USING_I2C3) #ifndef I2C3_CONFIG -#define I2C3_CONFIG \ - { \ - .name = "i2c3", \ - .Instance = CM_I2C3, \ - .clock = FCG1_PERIPH_I2C3, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C3_CONFIG */ #if defined(BSP_I2C3_USING_DMA) #ifndef I2C3_TX_DMA_CONFIG -#define I2C3_TX_DMA_CONFIG \ - { \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .channel = I2C3_TX_DMA_CHANNEL, \ - .clock = I2C3_TX_DMA_CLOCK, \ - .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_TEI, \ - .flag = I2C3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_TX_DMA_IRQn, \ - .irq_prio = I2C3_TX_DMA_INT_PRIO, \ - .int_src = I2C3_TX_DMA_INT_SRC, \ - }, \ +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_TX_DMA_CONFIG */ #ifndef I2C3_RX_DMA_CONFIG -#define I2C3_RX_DMA_CONFIG \ - { \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .channel = I2C3_RX_DMA_CHANNEL, \ - .clock = I2C3_RX_DMA_CLOCK, \ - .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_RXI, \ - .flag = I2C3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_RX_DMA_IRQn, \ - .irq_prio = I2C3_RX_DMA_INT_PRIO, \ - .int_src = I2C3_RX_DMA_INT_SRC, \ - }, \ +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_RX_DMA_CONFIG */ #endif /* BSP_I2C3_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h index 6290ce25438..19999e7111d 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/irq_config.h @@ -17,316 +17,316 @@ extern "C" { #endif -#define BSP_EXTINT0_IRQ_NUM INT022_IRQn -#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT1_IRQ_NUM INT023_IRQn -#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT2_IRQ_NUM INT024_IRQn -#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT3_IRQ_NUM INT025_IRQn -#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT4_IRQ_NUM INT026_IRQn -#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT5_IRQ_NUM INT027_IRQn -#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT6_IRQ_NUM INT028_IRQn -#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT7_IRQ_NUM INT029_IRQn -#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT8_IRQ_NUM INT030_IRQn -#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT9_IRQ_NUM INT031_IRQn -#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT10_IRQ_NUM INT032_IRQn -#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT11_IRQ_NUM INT033_IRQn -#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT12_IRQ_NUM INT034_IRQn -#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT13_IRQ_NUM INT035_IRQn -#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT14_IRQ_NUM INT036_IRQn -#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT15_IRQ_NUM INT037_IRQn -#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch0 */ -#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn -#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch1 */ -#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn -#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch2 */ -#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn -#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch3 */ -#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn -#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch0 */ -#define BSP_DMA2_CH0_IRQ_NUM INT042_IRQn -#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH0_IRQ_NUM INT042_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch1 */ -#define BSP_DMA2_CH1_IRQ_NUM INT043_IRQn -#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH1_IRQ_NUM INT043_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch2 */ -#define BSP_DMA2_CH2_IRQ_NUM INT020_IRQn -#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH2_IRQ_NUM INT020_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch3 */ -#define BSP_DMA2_CH3_IRQ_NUM INT021_IRQn -#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH3_IRQ_NUM INT021_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_USING_UART1) -#define BSP_UART1_RXERR_IRQ_NUM INT012_IRQn -#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART1_RX_IRQ_NUM INT082_IRQn -#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART1_TX_IRQ_NUM INT081_IRQn -#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT082_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT081_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART1_RX_USING_DMA) -#define BSP_UART1_RXTO_IRQ_NUM INT013_IRQn -#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RXTO_IRQ_NUM INT013_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) -#define BSP_UART1_TX_CPLT_IRQ_NUM INT080_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM INT080_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART1_TX_CPLT_IRQ_NUM INT080_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM INT080_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) -#define BSP_UART2_RXERR_IRQ_NUM INT014_IRQn -#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART2_RX_IRQ_NUM INT085_IRQn -#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART2_TX_IRQ_NUM INT084_IRQn -#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RXERR_IRQ_NUM INT014_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT085_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT084_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART2_RX_USING_DMA) -#define BSP_UART2_RXTO_IRQ_NUM INT015_IRQn -#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RXTO_IRQ_NUM INT015_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) -#define BSP_UART2_TX_CPLT_IRQ_NUM INT083_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM INT083_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART2_TX_CPLT_IRQ_NUM INT083_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM INT083_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) -#define BSP_UART3_RXERR_IRQ_NUM INT016_IRQn -#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART3_RX_IRQ_NUM INT088_IRQn -#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART3_TX_IRQ_NUM INT087_IRQn -#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RXERR_IRQ_NUM INT016_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT088_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT087_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART3_RX_USING_DMA) -#define BSP_UART3_RXTO_IRQ_NUM INT017_IRQn -#define BSP_UART3_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RXTO_IRQ_NUM INT017_IRQn +#define BSP_UART3_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA) -#define BSP_UART3_TX_CPLT_IRQ_NUM INT086_IRQn -#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART3_TX_CPLT_IRQ_NUM INT086_IRQn -#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART3 */ #if defined(BSP_USING_UART4) -#define BSP_UART4_RXERR_IRQ_NUM INT018_IRQn -#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART4_RX_IRQ_NUM INT091_IRQn -#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART4_TX_IRQ_NUM INT090_IRQn -#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RXERR_IRQ_NUM INT018_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT091_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT090_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART4_RX_USING_DMA) -#define BSP_UART4_RXTO_IRQ_NUM INT019_IRQn -#define BSP_UART4_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RXTO_IRQ_NUM INT019_IRQn +#define BSP_UART4_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA) -#define BSP_UART4_TX_CPLT_IRQ_NUM INT089_IRQn -#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_CPLT_IRQ_NUM INT089_IRQn +#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART4_TX_CPLT_IRQ_NUM INT089_IRQn -#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_CPLT_IRQ_NUM INT089_IRQn +#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_SPI1) -#define BSP_SPI1_ERR_IRQ_NUM INT008_IRQn -#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI1_ERR_IRQ_NUM INT008_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI2) -#define BSP_SPI2_ERR_IRQ_NUM INT009_IRQn -#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM INT009_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI3) -#define BSP_SPI3_ERR_IRQ_NUM INT010_IRQn -#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI3_ERR_IRQ_NUM INT010_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI4) -#define BSP_SPI4_ERR_IRQ_NUM INT011_IRQn -#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI4_ERR_IRQ_NUM INT011_IRQn +#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_CAN1) -#define BSP_CAN1_IRQ_NUM INT126_IRQn -#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_CAN1_IRQ_NUM INT126_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_CAN1 */ #if defined(BSP_USING_SDIO1) -#define BSP_SDIO1_IRQ_NUM INT122_IRQn -#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SDIO1_IRQ_NUM INT122_IRQn +#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_SDIO1 */ #if defined(BSP_USING_SDIO2) -#define BSP_SDIO2_IRQ_NUM INT124_IRQn -#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SDIO2_IRQ_NUM INT124_IRQn +#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_SDIO2 */ #if defined(RT_USING_ALARM) -#define BSP_RTC_ALARM_IRQ_NUM INT044_IRQn -#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_RTC_ALARM_IRQ_NUM INT044_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* RT_USING_ALARM */ #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) -#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn -#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn +#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBD */ -#if defined (BSP_USING_QSPI) -#define BSP_QSPI_ERR_IRQ_NUM INT004_IRQn -#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#if defined(BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM INT004_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_QSPI */ #if defined(BSP_USING_TMRA_1) -#define BSP_USING_TMRA_1_IRQ_NUM INT080_IRQn -#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_1_IRQ_NUM INT080_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_1 */ #if defined(BSP_USING_TMRA_2) -#define BSP_USING_TMRA_2_IRQ_NUM INT081_IRQn -#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_2_IRQ_NUM INT081_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_2 */ #if defined(BSP_USING_TMRA_3) -#define BSP_USING_TMRA_3_IRQ_NUM INT082_IRQn -#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_3_IRQ_NUM INT082_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_3 */ #if defined(BSP_USING_TMRA_4) -#define BSP_USING_TMRA_4_IRQ_NUM INT083_IRQn -#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_4_IRQ_NUM INT083_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_4 */ #if defined(BSP_USING_TMRA_5) -#define BSP_USING_TMRA_5_IRQ_NUM INT084_IRQn -#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_5_IRQ_NUM INT084_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_5 */ #if defined(BSP_USING_TMRA_6) -#define BSP_USING_TMRA_6_IRQ_NUM INT085_IRQn -#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_6_IRQ_NUM INT085_IRQn +#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_6 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT080_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT081_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_2) -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT082_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT083_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_3) -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT084_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT085_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT084_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT085_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_4) -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT080_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT081_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_5) -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT082_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT083_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_6) -#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT084_IRQn -#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT085_IRQn -#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT084_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT085_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT050_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT051_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT050_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT051_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_2) -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT052_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT053_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT052_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT053_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_3) -#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT054_IRQn -#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT055_IRQn -#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT054_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT055_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */ #if defined(BSP_USING_TMR0_1A) -#define BSP_USING_TMR0_1A_IRQ_NUM INT046_IRQn -#define BSP_USING_TMR0_1A_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMR0_1A_IRQ_NUM INT046_IRQn +#define BSP_USING_TMR0_1A_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMR0_1A */ #if defined(BSP_USING_TMR0_1B) -#define BSP_USING_TMR0_1B_IRQ_NUM INT047_IRQn -#define BSP_USING_TMR0_1B_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMR0_1B_IRQ_NUM INT047_IRQn +#define BSP_USING_TMR0_1B_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMR0_1B */ #if defined(BSP_USING_TMR0_2A) -#define BSP_USING_TMR0_2A_IRQ_NUM INT048_IRQn -#define BSP_USING_TMR0_2A_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMR0_2A_IRQ_NUM INT048_IRQn +#define BSP_USING_TMR0_2A_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMR0_2A */ #if defined(BSP_USING_TMR0_2B) -#define BSP_USING_TMR0_2B_IRQ_NUM INT049_IRQn -#define BSP_USING_TMR0_2B_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMR0_2B_IRQ_NUM INT049_IRQn +#define BSP_USING_TMR0_2B_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMR0_2B */ #if defined(BSP_USING_INPUT_CAPTURE) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pm_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pm_config.h index 2e317e89031..4ce382797eb 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pm_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pm_config.h @@ -23,16 +23,16 @@ extern "C" { extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); #ifndef PM_TICKLESS_TIMER_ENABLE_MASK -#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL) +#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL) #endif /** * @brief run mode config @ref pm_run_mode_config structure */ #ifndef PM_RUN_MODE_CFG -#define PM_RUN_MODE_CFG \ - { \ - .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ } #endif /* PM_RUN_MODE_CFG */ @@ -40,53 +40,53 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); * @brief sleep idle config @ref pm_sleep_mode_idle_config structure */ #ifndef PM_SLEEP_IDLE_CFG -#define PM_SLEEP_IDLE_CFG \ -{ \ - .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ -} +#define PM_SLEEP_IDLE_CFG \ + { \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ + } #endif /*PM_SLEEP_IDLE_CFG*/ /** * @brief sleep deep config @ref pm_sleep_mode_deep_config structure */ #ifndef PM_SLEEP_DEEP_CFG -#define PM_SLEEP_DEEP_CFG \ -{ \ - { \ - .u16Clock = PWC_STOP_CLK_KEEP, \ - .u8StopDrv = PWC_STOP_DRV_HIGH, \ - .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ - }, \ - .pwc_stop_type = PWC_STOP_WFE_INT, \ -} +#define PM_SLEEP_DEEP_CFG \ + { \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ + } #endif /*PM_SLEEP_DEEP_CFG*/ /** * @brief sleep standby config @ref pm_sleep_mode_standby_config structure */ #ifndef PM_SLEEP_STANDBY_CFG -#define PM_SLEEP_STANDBY_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD1, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ - }, \ -} +#define PM_SLEEP_STANDBY_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } #endif /*PM_SLEEP_STANDBY_CFG*/ /** * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure */ #ifndef PM_SLEEP_SHUTDOWN_CFG -#define PM_SLEEP_SHUTDOWN_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD3, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ - }, \ -} +#define PM_SLEEP_SHUTDOWN_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } #endif /*PM_SLEEP_SHUTDOWN_CFG*/ #endif /* BSP_USING_PM */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pulse_encoder_config.h index 62b4ca18ab9..8d0984c670a 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pulse_encoder_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pulse_encoder_config.h @@ -21,234 +21,216 @@ extern "C" { #ifdef BSP_USING_PULSE_ENCODER_TMRA_1 #ifndef PULSE_ENCODER_TMRA_1_CONFIG -#define PULSE_ENCODER_TMRA_1_CONFIG \ - { \ - .tmr_handler = CM_TMRA_1, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a1" \ +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ } #endif /* PULSE_ENCODER_TMRA_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_2 #ifndef PULSE_ENCODER_TMRA_2_CONFIG -#define PULSE_ENCODER_TMRA_2_CONFIG \ - { \ - .tmr_handler = CM_TMRA_2, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a2" \ +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ } #endif /* PULSE_ENCODER_TMRA_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_3 #ifndef PULSE_ENCODER_TMRA_3_CONFIG -#define PULSE_ENCODER_TMRA_3_CONFIG \ - { \ - .tmr_handler = CM_TMRA_3, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a3" \ +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ } #endif /* PULSE_ENCODER_TMRA_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_4 #ifndef PULSE_ENCODER_TMRA_4_CONFIG -#define PULSE_ENCODER_TMRA_4_CONFIG \ - { \ - .tmr_handler = CM_TMRA_4, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a4" \ +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ } #endif /* PULSE_ENCODER_TMRA_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_5 #ifndef PULSE_ENCODER_TMRA_5_CONFIG -#define PULSE_ENCODER_TMRA_5_CONFIG \ - { \ - .tmr_handler = CM_TMRA_5, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a5" \ +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ } #endif /* PULSE_ENCODER_TMRA_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_6 #ifndef PULSE_ENCODER_TMRA_6_CONFIG -#define PULSE_ENCODER_TMRA_6_CONFIG \ - { \ - .tmr_handler = CM_TMRA_6, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a6" \ +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ } #endif /* PULSE_ENCODER_TMRA_6_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_1 #ifndef PULSE_ENCODER_TMR6_1_CONFIG -#define PULSE_ENCODER_TMR6_1_CONFIG \ - { \ - .tmr_handler = CM_TMR6_1, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_61" \ +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ } #endif /* PULSE_ENCODER_TMR6_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_2 #ifndef PULSE_ENCODER_TMR6_2_CONFIG -#define PULSE_ENCODER_TMR6_2_CONFIG \ - { \ - .tmr_handler = CM_TMR6_2, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_62" \ +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ } #endif /* PULSE_ENCODER_TMR6_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_3 #ifndef PULSE_ENCODER_TMR6_3_CONFIG -#define PULSE_ENCODER_TMR6_3_CONFIG \ - { \ - .tmr_handler = CM_TMR6_3, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_63" \ +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ } #endif /* PULSE_ENCODER_TMR6_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pwm_tmr_config.h index f1850caa37c..a195854d187 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pwm_tmr_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/pwm_tmr_config.h @@ -21,180 +21,162 @@ extern "C" { #ifdef BSP_USING_PWM_TMRA_1 #ifndef PWM_TMRA_1_CONFIG -#define PWM_TMRA_1_CONFIG \ - { \ - .name = "pwm_a1", \ - .instance = CM_TMRA_1, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_1_CONFIG */ #endif /* BSP_USING_PWM_TMRA_1 */ #ifdef BSP_USING_PWM_TMRA_2 #ifndef PWM_TMRA_2_CONFIG -#define PWM_TMRA_2_CONFIG \ - { \ - .name = "pwm_a2", \ - .instance = CM_TMRA_2, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_2_CONFIG */ #endif /* BSP_USING_PWM_TMRA_2 */ #ifdef BSP_USING_PWM_TMRA_3 #ifndef PWM_TMRA_3_CONFIG -#define PWM_TMRA_3_CONFIG \ - { \ - .name = "pwm_a3", \ - .instance = CM_TMRA_3, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_3_CONFIG */ #endif /* BSP_USING_PWM_TMRA_3 */ #ifdef BSP_USING_PWM_TMRA_4 #ifndef PWM_TMRA_4_CONFIG -#define PWM_TMRA_4_CONFIG \ - { \ - .name = "pwm_a4", \ - .instance = CM_TMRA_4, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_4_CONFIG */ #endif /* BSP_USING_PWM_TMRA_4 */ #ifdef BSP_USING_PWM_TMRA_5 #ifndef PWM_TMRA_5_CONFIG -#define PWM_TMRA_5_CONFIG \ - { \ - .name = "pwm_a5", \ - .instance = CM_TMRA_5, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_5_CONFIG */ #endif /* BSP_USING_PWM_TMRA_5 */ #ifdef BSP_USING_PWM_TMRA_6 #ifndef PWM_TMRA_6_CONFIG -#define PWM_TMRA_6_CONFIG \ - { \ - .name = "pwm_a6", \ - .instance = CM_TMRA_6, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_6_CONFIG */ #endif /* BSP_USING_PWM_TMRA_6 */ @@ -205,96 +187,87 @@ extern "C" { #ifdef BSP_USING_PWM_TMR4_1 #ifndef PWM_TMR4_1_CONFIG -#define PWM_TMR4_1_CONFIG \ - { \ - .name = "pwm_t41", \ - .instance = CM_TMR4_1, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_1_CONFIG */ #endif /* BSP_USING_PWM_TMR4_1 */ #ifdef BSP_USING_PWM_TMR4_2 #ifndef PWM_TMR4_2_CONFIG -#define PWM_TMR4_2_CONFIG \ - { \ - .name = "pwm_t42", \ - .instance = CM_TMR4_2, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_2_CONFIG */ #endif /* BSP_USING_PWM_TMR4_2 */ #ifdef BSP_USING_PWM_TMR4_3 #ifndef PWM_TMR4_3_CONFIG -#define PWM_TMR4_3_CONFIG \ - { \ - .name = "pwm_t43", \ - .instance = CM_TMR4_3, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_3_CONFIG */ #endif /* BSP_USING_PWM_TMR4_3 */ @@ -305,121 +278,106 @@ extern "C" { #ifdef BSP_USING_PWM_TMR6_1 #ifndef PWM_TMR6_1_CONFIG -#define PWM_TMR6_1_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_1, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CompareMatchPolarity = TMR6_PWM_LOW, \ - .u32PeriodMatchPolarity = TMR6_PWM_HIGH, \ - .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CompareMatchPolarity = TMR6_PWM_LOW, \ - .u32PeriodMatchPolarity = TMR6_PWM_HIGH, \ - .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ - } \ - }, \ +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CompareMatchPolarity = TMR6_PWM_LOW, \ + .u32PeriodMatchPolarity = TMR6_PWM_HIGH, \ + .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CompareMatchPolarity = TMR6_PWM_LOW, \ + .u32PeriodMatchPolarity = TMR6_PWM_HIGH, \ + .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ + } }, \ } #endif /* PWM_TMR6_1_CONFIG */ #endif /* BSP_USING_PWM_TMR6_1 */ #ifdef BSP_USING_PWM_TMR6_2 #ifndef PWM_TMR6_2_CONFIG -#define PWM_TMR6_2_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_2, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CompareMatchPolarity = TMR6_PWM_HIGH, \ - .u32PeriodMatchPolarity = TMR6_PWM_LOW, \ - .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CompareMatchPolarity = TMR6_PWM_HIGH, \ - .u32PeriodMatchPolarity = TMR6_PWM_LOW, \ - .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ - } \ - }, \ +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CompareMatchPolarity = TMR6_PWM_HIGH, \ + .u32PeriodMatchPolarity = TMR6_PWM_LOW, \ + .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CompareMatchPolarity = TMR6_PWM_HIGH, \ + .u32PeriodMatchPolarity = TMR6_PWM_LOW, \ + .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ + } }, \ } #endif /* PWM_TMR6_2_CONFIG */ #endif /* BSP_USING_PWM_TMR6_2 */ #ifdef BSP_USING_PWM_TMR6_3 #ifndef PWM_TMR6_3_CONFIG -#define PWM_TMR6_3_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_3, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CompareMatchPolarity = TMR6_PWM_HIGH, \ - .u32PeriodMatchPolarity = TMR6_PWM_LOW, \ - .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CompareMatchPolarity = TMR6_PWM_HIGH, \ - .u32PeriodMatchPolarity = TMR6_PWM_LOW, \ - .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ - } \ - }, \ +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CompareMatchPolarity = TMR6_PWM_HIGH, \ + .u32PeriodMatchPolarity = TMR6_PWM_LOW, \ + .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CompareMatchPolarity = TMR6_PWM_HIGH, \ + .u32PeriodMatchPolarity = TMR6_PWM_LOW, \ + .u32StartStopHold = TMR6_PWM_START_STOP_HOLD, \ + } }, \ } #endif /* PWM_TMR6_3_CONFIG */ #endif /* BSP_USING_PWM_TMR6_3 */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/qspi_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/qspi_config.h index b8e74bfae19..929bf0a5a91 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/qspi_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/qspi_config.h @@ -20,48 +20,46 @@ extern "C" { #ifdef BSP_USING_QSPI #ifndef QSPI_BUS_CONFIG -#define QSPI_BUS_CONFIG \ - { \ - .Instance = CM_QSPI, \ - .clock = FCG1_PERIPH_QSPI, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ - .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_QSPI_INTR, \ - }, \ +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ } #endif /* QSPI_BUS_CONFIG */ #ifndef QSPI_INIT_PARAMS -#define QSPI_INIT_PARAMS \ - { \ - .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ - .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ - .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ - .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ } #endif /* QSPI_INIT_PARAMS */ -#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH #ifdef BSP_QSPI_USING_DMA #ifndef QSPI_DMA_CONFIG -#define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .channel = QSPI_DMA_CHANNEL, \ - .clock = QSPI_DMA_CLOCK, \ - .trigger_select = QSPI_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_AOS_STRG, \ - .flag = QSPI_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = QSPI_DMA_IRQn, \ - .irq_prio = QSPI_DMA_INT_PRIO, \ - .int_src = QSPI_DMA_INT_SRC, \ - } \ +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ } #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/sdio_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/sdio_config.h index 8d1d1bf8977..d4219976138 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/sdio_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/sdio_config.h @@ -21,66 +21,60 @@ extern "C" { #if defined(BSP_USING_SDIO1) #ifndef SDIO1_BUS_CONFIG -#define SDIO1_BUS_CONFIG \ - { \ - .name = "sdio1", \ - .instance = CM_SDIOC1, \ - .clock = FCG1_PERIPH_SDIOC1, \ - .irq_config = \ - { \ - .irq_num = BSP_SDIO1_IRQ_NUM, \ - .irq_prio = BSP_SDIO1_IRQ_PRIO, \ - .int_src = INT_SRC_SDIOC1_SD, \ - }, \ - .dma_rx = \ - { \ - .Instance = SDIO1_RX_DMA_INSTANCE, \ - .channel = SDIO1_RX_DMA_CHANNEL, \ - .clock = SDIO1_RX_DMA_CLOCK, \ - .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC1_DMAR, \ - }, \ - .dma_tx = \ - { \ - .Instance = SDIO1_TX_DMA_INSTANCE, \ - .channel = SDIO1_TX_DMA_CHANNEL, \ - .clock = SDIO1_TX_DMA_CLOCK, \ - .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC1_DMAW, \ - }, \ +#define SDIO1_BUS_CONFIG \ + { \ + .name = "sdio1", \ + .instance = CM_SDIOC1, \ + .clock = FCG1_PERIPH_SDIOC1, \ + .irq_config = { \ + .irq_num = BSP_SDIO1_IRQ_NUM, \ + .irq_prio = BSP_SDIO1_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC1_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO1_RX_DMA_INSTANCE, \ + .channel = SDIO1_RX_DMA_CHANNEL, \ + .clock = SDIO1_RX_DMA_CLOCK, \ + .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO1_TX_DMA_INSTANCE, \ + .channel = SDIO1_TX_DMA_CHANNEL, \ + .clock = SDIO1_TX_DMA_CLOCK, \ + .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAW, \ + }, \ } #endif /* SDIO1_BUS_CONFIG */ #endif /* BSP_USING_SDIO1 */ #if defined(BSP_USING_SDIO2) #ifndef SDIO2_BUS_CONFIG -#define SDIO2_BUS_CONFIG \ - { \ - .name = "sdio2", \ - .instance = CM_SDIOC2, \ - .clock = FCG1_PERIPH_SDIOC2, \ - .irq_config = \ - { \ - .irq_num = BSP_SDIO2_IRQ_NUM, \ - .irq_prio = BSP_SDIO2_IRQ_PRIO, \ - .int_src = INT_SRC_SDIOC2_SD, \ - }, \ - .dma_rx = \ - { \ - .Instance = SDIO2_RX_DMA_INSTANCE, \ - .channel = SDIO2_RX_DMA_CHANNEL, \ - .clock = SDIO2_RX_DMA_CLOCK, \ - .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC2_DMAR, \ - }, \ - .dma_tx = \ - { \ - .Instance = SDIO2_TX_DMA_INSTANCE, \ - .channel = SDIO2_TX_DMA_CHANNEL, \ - .clock = SDIO2_TX_DMA_CLOCK, \ - .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC2_DMAW, \ - }, \ +#define SDIO2_BUS_CONFIG \ + { \ + .name = "sdio2", \ + .instance = CM_SDIOC2, \ + .clock = FCG1_PERIPH_SDIOC2, \ + .irq_config = { \ + .irq_num = BSP_SDIO2_IRQ_NUM, \ + .irq_prio = BSP_SDIO2_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC2_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO2_RX_DMA_INSTANCE, \ + .channel = SDIO2_RX_DMA_CHANNEL, \ + .clock = SDIO2_RX_DMA_CLOCK, \ + .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO2_TX_DMA_INSTANCE, \ + .channel = SDIO2_TX_DMA_CHANNEL, \ + .clock = SDIO2_TX_DMA_CLOCK, \ + .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAW, \ + }, \ } #endif /* SDIO2_BUS_CONFIG */ #endif /* BSP_USING_SDIO2 */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/spi_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/spi_config.h index 2e908e3d055..8f6de9eb563 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/spi_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/spi_config.h @@ -21,134 +21,127 @@ extern "C" { #ifdef BSP_USING_SPI1 #ifndef SPI1_BUS_CONFIG -#define SPI1_BUS_CONFIG \ - { \ - .Instance = CM_SPI1, \ - .bus_name = "spi1", \ - .clock = FCG1_PERIPH_SPI1, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI1_SPEI, \ - }, \ +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .clock = SPI1_TX_DMA_CLOCK, \ - .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPTI, \ - .flag = SPI1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_TX_DMA_IRQn, \ - .irq_prio = SPI1_TX_DMA_INT_PRIO, \ - .int_src = SPI1_TX_DMA_INT_SRC, \ - } \ +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .clock = SPI1_RX_DMA_CLOCK, \ - .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPRI, \ - .flag = SPI1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_RX_DMA_IRQn, \ - .irq_prio = SPI1_RX_DMA_INT_PRIO, \ - .int_src = SPI1_RX_DMA_INT_SRC, \ - } \ +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 #ifndef SPI2_BUS_CONFIG -#define SPI2_BUS_CONFIG \ - { \ - .Instance = CM_SPI2, \ - .bus_name = "spi2", \ - .clock = FCG1_PERIPH_SPI2, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI2_SPEI, \ - }, \ +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .channel = SPI2_TX_DMA_CHANNEL, \ - .clock = SPI2_TX_DMA_CLOCK, \ - .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPTI, \ - .flag = SPI2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_TX_DMA_IRQn, \ - .irq_prio = SPI2_TX_DMA_INT_PRIO, \ - .int_src = SPI2_TX_DMA_INT_SRC, \ - } \ +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .channel = SPI2_RX_DMA_CHANNEL, \ - .clock = SPI2_RX_DMA_CLOCK, \ - .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPRI, \ - .flag = SPI2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_RX_DMA_IRQn, \ - .irq_prio = SPI2_RX_DMA_INT_PRIO, \ - .int_src = SPI2_RX_DMA_INT_SRC, \ - } \ +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 #ifndef SPI3_BUS_CONFIG -#define SPI3_BUS_CONFIG \ - { \ - .Instance = CM_SPI3, \ - .bus_name = "spi3", \ - .clock = FCG1_PERIPH_SPI3, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI3_SPEI, \ - }, \ +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ @@ -156,98 +149,93 @@ extern "C" { #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .channel = SPI3_TX_DMA_CHANNEL, \ - .clock = SPI3_TX_DMA_CLOCK, \ - .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPTI, \ - .flag = SPI3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_TX_DMA_IRQn, \ - .irq_prio = SPI3_TX_DMA_INT_PRIO, \ - .int_src = SPI3_TX_DMA_INT_SRC, \ - } \ +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .channel = SPI3_RX_DMA_CHANNEL, \ - .clock = SPI3_RX_DMA_CLOCK, \ - .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPRI, \ - .flag = SPI3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_RX_DMA_IRQn, \ - .irq_prio = SPI3_RX_DMA_INT_PRIO, \ - .int_src = SPI3_RX_DMA_INT_SRC, \ - } \ +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ #ifdef BSP_USING_SPI4 #ifndef SPI4_BUS_CONFIG -#define SPI4_BUS_CONFIG \ - { \ - .Instance = CM_SPI4, \ - .bus_name = "spi4", \ - .clock = FCG1_PERIPH_SPI4, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI4_SPEI, \ - }, \ +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ } #endif /* SPI4_BUS_CONFIG */ #endif /* BSP_USING_SPI4 */ #ifdef BSP_SPI4_TX_USING_DMA #ifndef SPI4_TX_DMA_CONFIG -#define SPI4_TX_DMA_CONFIG \ - { \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .channel = SPI4_TX_DMA_CHANNEL, \ - .clock = SPI4_TX_DMA_CLOCK, \ - .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI4_SPTI, \ - .flag = SPI4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI4_TX_DMA_IRQn, \ - .irq_prio = SPI4_TX_DMA_INT_PRIO, \ - .int_src = SPI4_TX_DMA_INT_SRC, \ - } \ +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ #ifdef BSP_SPI4_RX_USING_DMA #ifndef SPI4_RX_DMA_CONFIG -#define SPI4_RX_DMA_CONFIG \ - { \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .channel = SPI4_RX_DMA_CHANNEL, \ - .clock = SPI4_RX_DMA_CLOCK, \ - .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI4_SPRI, \ - .flag = SPI4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI4_RX_DMA_IRQn, \ - .irq_prio = SPI4_RX_DMA_INT_PRIO, \ - .int_src = SPI4_RX_DMA_INT_SRC, \ - } \ +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/timer_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/timer_config.h index b18d924d5b6..52b9ed00076 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/timer_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/timer_config.h @@ -19,114 +19,108 @@ extern "C" { #ifdef BSP_USING_TMRA_1 #ifndef TMRA_1_CONFIG -#define TMRA_1_CONFIG \ - { \ - .tmr_handle = CM_TMRA_1, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_1, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_1_OVF, \ - .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ - }, \ - .name = "tmra_1" \ +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ } #endif /* TMRA_1_CONFIG */ #endif /* BSP_USING_TMRA_1 */ #ifdef BSP_USING_TMRA_2 #ifndef TMRA_2_CONFIG -#define TMRA_2_CONFIG \ - { \ - .tmr_handle = CM_TMRA_2, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_2, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_2_OVF, \ - .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ - }, \ - .name = "tmra_2" \ +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ } #endif /* TMRA_2_CONFIG */ #endif /* BSP_USING_TMRA_2 */ #ifdef BSP_USING_TMRA_3 #ifndef TMRA_3_CONFIG -#define TMRA_3_CONFIG \ - { \ - .tmr_handle = CM_TMRA_3, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_3, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_3_OVF, \ - .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ - }, \ - .name = "tmra_3" \ +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ } #endif /* TMRA_3_CONFIG */ #endif /* BSP_USING_TMRA_3 */ #ifdef BSP_USING_TMRA_4 #ifndef TMRA_4_CONFIG -#define TMRA_4_CONFIG \ - { \ - .tmr_handle = CM_TMRA_4, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_4, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_4_OVF, \ - .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ - }, \ - .name = "tmra_4" \ +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ } #endif /* TMRA_4_CONFIG */ #endif /* BSP_USING_TMRA_4 */ #ifdef BSP_USING_TMRA_5 #ifndef TMRA_5_CONFIG -#define TMRA_5_CONFIG \ - { \ - .tmr_handle = CM_TMRA_5, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_5, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_5_OVF, \ - .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ - }, \ - .name = "tmra_5" \ +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ } #endif /* TMRA_5_CONFIG */ #endif /* BSP_USING_TMRA_5 */ #ifdef BSP_USING_TMRA_6 #ifndef TMRA_6_CONFIG -#define TMRA_6_CONFIG \ - { \ - .tmr_handle = CM_TMRA_6, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_6, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_6_OVF, \ - .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ - }, \ - .name = "tmra_6" \ +#define TMRA_6_CONFIG \ + { \ + .tmr_handle = CM_TMRA_6, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_6, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_6_OVF, \ + .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ + }, \ + .name = "tmra_6" \ } #endif /* TMRA_6_CONFIG */ #endif /* BSP_USING_TMRA_6 */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/tmr_capture_config.h index 59b01b0c5e1..e18932c7388 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/tmr_capture_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/tmr_capture_config.h @@ -17,49 +17,49 @@ extern "C" { #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) #define IC1_NAME "ic1" -#define INPUT_CAPTURE_CFG_TMR6_1 \ -{ \ - .name = IC1_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV4, \ - .first_edge = TMR6_CAPT_COND_PWMA_FALLING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_1 \ + { \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV4, \ + .first_edge = TMR6_CAPT_COND_PWMA_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) #define IC2_NAME "ic2" -#define INPUT_CAPTURE_CFG_TMR6_2 \ -{ \ - .name = IC2_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV8, \ - .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_2 \ + { \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV8, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) #define IC3_NAME "ic3" -#define INPUT_CAPTURE_CFG_TMR6_3 \ -{ \ - .name = IC3_NAME, \ - .ch = TMR6_CH_B, \ - .clk_div = TMR6_CLK_DIV16, \ - .first_edge = TMR6_CAPT_COND_TRIGA_FALLING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_3 \ + { \ + .name = IC3_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGA_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ + } #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/uart_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/uart_config.h index d4a42a4fea5..b883376b67a 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/uart_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/uart_config.h @@ -21,110 +21,102 @@ extern "C" { #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = CM_USART1, \ - .clock = FCG1_PERIPH_USART1, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_RX_IRQ_NUM, \ - .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_TX_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TI, \ - }, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG1_PERIPH_USART1, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ } #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .clock = UART1_RX_DMA_CLOCK, \ - .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_RI, \ - .flag = UART1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_RX_DMA_IRQn, \ - .irq_prio = UART1_RX_DMA_INT_PRIO, \ - .int_src = UART1_RX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_RX_CONFIG */ #ifndef UART1_RXTO_CONFIG -#define UART1_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_RTO, \ - }, \ +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ } #endif /* UART1_RXTO_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #endif /* UART1_TX_CPLT_CONFIG */ #if defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .clock = UART1_TX_DMA_CLOCK, \ - .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_TI, \ - .flag = UART1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_TX_DMA_IRQn, \ - .irq_prio = UART1_TX_DMA_INT_PRIO, \ - .int_src = UART1_TX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -132,110 +124,102 @@ extern "C" { #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = CM_USART2, \ - .clock = FCG1_PERIPH_USART2, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_RX_IRQ_NUM, \ - .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_TX_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TI, \ - }, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG1_PERIPH_USART2, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ } #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .clock = UART2_RX_DMA_CLOCK, \ - .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_RI, \ - .flag = UART2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_RX_DMA_IRQn, \ - .irq_prio = UART2_RX_DMA_INT_PRIO, \ - .int_src = UART2_RX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_RX_CONFIG */ #ifndef UART2_RXTO_CONFIG -#define UART2_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_RTO, \ - }, \ +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ } #endif /* UART2_RXTO_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #endif /* UART2_TX_CPLT_CONFIG */ #if defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .clock = UART2_TX_DMA_CLOCK, \ - .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_TI, \ - .flag = UART2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_TX_DMA_IRQn, \ - .irq_prio = UART2_TX_DMA_INT_PRIO, \ - .int_src = UART2_TX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -243,110 +227,102 @@ extern "C" { #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = CM_USART3, \ - .clock = FCG1_PERIPH_USART3, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_RX_IRQ_NUM, \ - .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_TX_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TI, \ - }, \ +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG1_PERIPH_USART3, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ } #endif /* UART3_CONFIG */ #if defined(BSP_UART3_RX_USING_DMA) #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .channel = UART3_RX_DMA_CHANNEL, \ - .clock = UART3_RX_DMA_CLOCK, \ - .trigger_select = UART3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART3_RI, \ - .flag = UART3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART3_RX_DMA_IRQn, \ - .irq_prio = UART3_RX_DMA_INT_PRIO, \ - .int_src = UART3_RX_DMA_INT_SRC, \ - }, \ +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .channel = UART3_RX_DMA_CHANNEL, \ + .clock = UART3_RX_DMA_CLOCK, \ + .trigger_select = UART3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART3_RI, \ + .flag = UART3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART3_RX_DMA_IRQn, \ + .irq_prio = UART3_RX_DMA_INT_PRIO, \ + .int_src = UART3_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART3_DMA_RX_CONFIG */ #ifndef UART3_RXTO_CONFIG -#define UART3_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART3_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_RTO, \ - }, \ +#define UART3_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART3_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RTO, \ + }, \ } #endif /* UART3_RXTO_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA) #ifndef UART3_TX_CPLT_CONFIG -#define UART3_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TCI, \ - }, \ +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART3_TX_CPLT_CONFIG -#define UART3_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TCI, \ - }, \ +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ } #endif #endif /* UART3_TX_CPLT_CONFIG */ #if defined(BSP_UART3_TX_USING_DMA) #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .channel = UART3_TX_DMA_CHANNEL, \ - .clock = UART3_TX_DMA_CLOCK, \ - .trigger_select = UART3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART3_TI, \ - .flag = UART3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART3_TX_DMA_IRQn, \ - .irq_prio = UART3_TX_DMA_INT_PRIO, \ - .int_src = UART3_TX_DMA_INT_SRC, \ - }, \ +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .channel = UART3_TX_DMA_CHANNEL, \ + .clock = UART3_TX_DMA_CLOCK, \ + .trigger_select = UART3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART3_TI, \ + .flag = UART3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART3_TX_DMA_IRQn, \ + .irq_prio = UART3_TX_DMA_INT_PRIO, \ + .int_src = UART3_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ @@ -354,110 +330,102 @@ extern "C" { #if defined(BSP_USING_UART4) #ifndef UART4_CONFIG -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = CM_USART4, \ - .clock = FCG1_PERIPH_USART4, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_RX_IRQ_NUM, \ - .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_TX_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TI, \ - }, \ +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG1_PERIPH_USART4, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ } #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .channel = UART4_RX_DMA_CHANNEL, \ - .clock = UART4_RX_DMA_CLOCK, \ - .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART4_RI, \ - .flag = UART4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART4_RX_DMA_IRQn, \ - .irq_prio = UART4_RX_DMA_INT_PRIO, \ - .int_src = UART4_RX_DMA_INT_SRC, \ - }, \ +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .clock = UART4_RX_DMA_CLOCK, \ + .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_RI, \ + .flag = UART4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART4_RX_DMA_IRQn, \ + .irq_prio = UART4_RX_DMA_INT_PRIO, \ + .int_src = UART4_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART4_DMA_RX_CONFIG */ #ifndef UART4_RXTO_CONFIG -#define UART4_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART4_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_RTO, \ - }, \ +#define UART4_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART4_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RTO, \ + }, \ } #endif /* UART4_RXTO_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #endif /* UART4_TX_CPLT_CONFIG */ #if defined(BSP_UART4_TX_USING_DMA) #ifndef UART4_DMA_TX_CONFIG -#define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .channel = UART4_TX_DMA_CHANNEL, \ - .clock = UART4_TX_DMA_CLOCK, \ - .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART4_TI, \ - .flag = UART4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART4_TX_DMA_IRQn, \ - .irq_prio = UART4_TX_DMA_INT_PRIO, \ - .int_src = UART4_TX_DMA_INT_SRC, \ - }, \ +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .clock = UART4_TX_DMA_CLOCK, \ + .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_TI, \ + .flag = UART4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART4_TX_DMA_IRQn, \ + .irq_prio = UART4_TX_DMA_INT_PRIO, \ + .int_src = UART4_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART4_DMA_TX_CONFIG */ #endif /* BSP_UART4_TX_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_app_conf.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_app_conf.h index b668b2f22ba..9c38d28cbdb 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_app_conf.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_app_conf.h @@ -13,8 +13,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -40,30 +39,30 @@ extern "C" #endif #ifndef USB_FS_MODE -#error "USB_FS_MODE should be defined" +#error "USB_FS_MODE should be defined" #endif #ifndef USE_DEVICE_MODE #ifndef USE_HOST_MODE -#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" +#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" #endif #endif #if defined(BSP_USING_USBD) /* USB DEVICE FIFO CONFIGURATION */ #ifdef USB_FS_MODE -#define RX_FIFO_FS_SIZE (128U) -#define TX0_FIFO_FS_SIZE (32U) -#define TX1_FIFO_FS_SIZE (32U) -#define TX2_FIFO_FS_SIZE (32U) -#define TX3_FIFO_FS_SIZE (32U) -#define TX4_FIFO_FS_SIZE (32U) -#define TX5_FIFO_FS_SIZE (32U) - -#if ((RX_FIFO_FS_SIZE + \ +#define RX_FIFO_FS_SIZE (128U) +#define TX0_FIFO_FS_SIZE (32U) +#define TX1_FIFO_FS_SIZE (32U) +#define TX2_FIFO_FS_SIZE (32U) +#define TX3_FIFO_FS_SIZE (32U) +#define TX4_FIFO_FS_SIZE (32U) +#define TX5_FIFO_FS_SIZE (32U) + +#if ((RX_FIFO_FS_SIZE + \ TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ TX5_FIFO_FS_SIZE) > 320U) -#error "The USB max FIFO size is 320 x 4 Bytes!" +#error "The USB max FIFO size is 320 x 4 Bytes!" #endif #endif @@ -75,12 +74,12 @@ extern "C" #if defined(BSP_USING_USBH) /* USB HOST FIFO CONFIGURATION */ #ifdef USB_FS_MODE -#define RX_FIFO_FS_SIZE (128U) -#define TXH_NP_FS_FIFOSIZ (64U) -#define TXH_P_FS_FIFOSIZ (128U) +#define RX_FIFO_FS_SIZE (128U) +#define TXH_NP_FS_FIFOSIZ (64U) +#define TXH_P_FS_FIFOSIZ (128U) #if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 320U) -#error "The USB max FIFO size is 320 x 4 Bytes!" +#error "The USB max FIFO size is 320 x 4 Bytes!" #endif #endif diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_bsp.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_bsp.h index 76b5b37d81c..0df0dfbeda3 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_bsp.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/config/usb_config/usb_bsp.h @@ -13,8 +13,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include "hc32_ll_utility.h" diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/hc32f4xx_conf.h index c7a25a5c856..702cb38e89b 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/hc32f4xx_conf.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/hc32f4xx_conf.h @@ -27,8 +27,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -48,55 +47,55 @@ extern "C" * Library. * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. */ -#define LL_ICG_ENABLE (DDL_ON) -#define LL_UTILITY_ENABLE (DDL_ON) -#define LL_PRINT_ENABLE (DDL_OFF) +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) -#define LL_ADC_ENABLE (DDL_ON) -#define LL_AES_ENABLE (DDL_ON) -#define LL_AOS_ENABLE (DDL_ON) -#define LL_CAN_ENABLE (DDL_ON) -#define LL_CLK_ENABLE (DDL_ON) -#define LL_CMP_ENABLE (DDL_ON) -#define LL_CRC_ENABLE (DDL_ON) -#define LL_DBGC_ENABLE (DDL_OFF) -#define LL_DCU_ENABLE (DDL_ON) -#define LL_DMA_ENABLE (DDL_ON) -#define LL_EFM_ENABLE (DDL_ON) -#define LL_EMB_ENABLE (DDL_ON) -#define LL_EVENT_PORT_ENABLE (DDL_OFF) -#define LL_FCG_ENABLE (DDL_ON) -#define LL_FCM_ENABLE (DDL_ON) -#define LL_GPIO_ENABLE (DDL_ON) -#define LL_HASH_ENABLE (DDL_ON) -#define LL_I2C_ENABLE (DDL_ON) -#define LL_I2S_ENABLE (DDL_ON) -#define LL_INTERRUPTS_ENABLE (DDL_ON) -#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) -#define LL_KEYSCAN_ENABLE (DDL_ON) -#define LL_MPU_ENABLE (DDL_ON) -#define LL_OTS_ENABLE (DDL_ON) -#define LL_PWC_ENABLE (DDL_ON) -#define LL_QSPI_ENABLE (DDL_ON) -#define LL_RMU_ENABLE (DDL_ON) -#define LL_RTC_ENABLE (DDL_ON) -#define LL_SDIOC_ENABLE (DDL_ON) -#define LL_SPI_ENABLE (DDL_ON) -#define LL_SRAM_ENABLE (DDL_ON) -#define LL_SWDT_ENABLE (DDL_ON) -#define LL_TMR0_ENABLE (DDL_ON) -#define LL_TMR4_ENABLE (DDL_ON) -#define LL_TMR6_ENABLE (DDL_ON) -#define LL_TMRA_ENABLE (DDL_ON) -#define LL_TRNG_ENABLE (DDL_ON) -#define LL_USART_ENABLE (DDL_ON) -#define LL_USB_ENABLE (DDL_ON) -#define LL_WDT_ENABLE (DDL_ON) +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) /** * @brief The following is a list of currently supported BSP boards. */ -#define BSP_EV_HC32F460_LQFP100_V2 (4U) +#define BSP_EV_HC32F460_LQFP100_V2 (4U) /** * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently @@ -105,15 +104,15 @@ extern "C" * @note If there is no supported BSP board or the BSP function is not used, * the value needs to be set to 0U. */ -#define BSP_EV_HC32F4XX (0U) +#define BSP_EV_HC32F4XX (0U) /** * @brief This is the list of BSP components to be used. * Select the components you need to use to DDL_ON. */ -#define BSP_24CXX_ENABLE (DDL_OFF) -#define BSP_W25QXX_ENABLE (DDL_OFF) -#define BSP_WM8731_ENABLE (DDL_OFF) +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_WM8731_ENABLE (DDL_OFF) /******************************************************************************* * Global variable definitions ('extern') diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal_cfg.h index 87b74d56944..e119fda470d 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal_cfg.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/fal_cfg.h @@ -23,20 +23,20 @@ extern const struct fal_flash_dev hc32_onchip_flash; extern struct fal_flash_dev ext_nor_flash0; /* flash device table */ -#define FAL_FLASH_DEV_TABLE \ -{ \ - &hc32_onchip_flash, \ - &ext_nor_flash0, \ -} +#define FAL_FLASH_DEV_TABLE \ + { \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ + } /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ -#define FAL_PART_TABLE \ -{ \ - {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 512 * 1024, 0}, \ - {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ -} +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 512 * 1024, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \ + } #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/usb_config.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/usb_config.h index 723f0b19040..91c6a46fb48 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/usb_config.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/board/ports/usb_config.h @@ -14,15 +14,15 @@ /* ================ USB common Configuration ================ */ #ifdef __RTTHREAD__ - #include +#include - #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) #else - #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) #endif #ifndef CONFIG_USB_DBG_LEVEL - #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO #endif /* Enable print with color */ @@ -32,9 +32,9 @@ /* data align size when use dma or use dcache */ #ifdef CONFIG_USB_DCACHE_ENABLE - #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 #else - #define CONFIG_USB_ALIGN_SIZE 4 +#define CONFIG_USB_ALIGN_SIZE 4 #endif /* attribute data into no cache ram */ @@ -49,7 +49,7 @@ /* Ep0 in and out transfer buffer */ #ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN - #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 #endif /* Send ep0 in data from user buffer instead of copying into ep0 reqdata @@ -70,31 +70,31 @@ // #define CONFIG_USBDEV_EP0_THREAD #ifndef CONFIG_USBDEV_EP0_PRIO - #define CONFIG_USBDEV_EP0_PRIO 4 +#define CONFIG_USBDEV_EP0_PRIO 4 #endif #ifndef CONFIG_USBDEV_EP0_STACKSIZE - #define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#define CONFIG_USBDEV_EP0_STACKSIZE 2048 #endif #ifndef CONFIG_USBDEV_MSC_MAX_LUN - #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#define CONFIG_USBDEV_MSC_MAX_LUN 1 #endif #ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE - #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 #endif #ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING - #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" #endif #ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING - #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" #endif #ifndef CONFIG_USBDEV_MSC_VERSION_STRING - #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" #endif /* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ @@ -104,50 +104,50 @@ // #define CONFIG_USBDEV_MSC_THREAD #ifndef CONFIG_USBDEV_MSC_PRIO - #define CONFIG_USBDEV_MSC_PRIO 4 +#define CONFIG_USBDEV_MSC_PRIO 4 #endif #ifndef CONFIG_USBDEV_MSC_STACKSIZE - #define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 #endif #ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE - #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 #endif #ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS - #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 #endif #ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME - #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 #endif #define CONFIG_USBDEV_MTP_THREAD #ifndef CONFIG_USBDEV_MTP_PRIO - #define CONFIG_USBDEV_MTP_PRIO 4 +#define CONFIG_USBDEV_MTP_PRIO 4 #endif #ifndef CONFIG_USBDEV_MTP_STACKSIZE - #define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#define CONFIG_USBDEV_MTP_STACKSIZE 4096 #endif #ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE - #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 #endif /* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ #ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE - #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 #endif #ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID - #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff #endif #ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC - #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" #endif #define CONFIG_USBDEV_RNDIS_USING_LWIP @@ -171,95 +171,95 @@ #define CONFIG_USBHOST_DEV_NAMELEN 16 #ifndef CONFIG_USBHOST_PSC_PRIO - #define CONFIG_USBHOST_PSC_PRIO 0 +#define CONFIG_USBHOST_PSC_PRIO 0 #endif #ifndef CONFIG_USBHOST_PSC_STACKSIZE - #define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 #endif //#define CONFIG_USBHOST_GET_STRING_DESC // #define CONFIG_USBHOST_MSOS_ENABLE #ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE - #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 #endif /* Ep0 max transfer buffer */ #ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN - #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 #endif #ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT - #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 #endif #ifndef CONFIG_USBHOST_MSC_TIMEOUT - #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) #endif #define CONFIG_USBHOST_BLUETOOTH_HCI_H4 // #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG #ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE - #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 #endif #ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE - #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 #endif /* ================ USB Device Port Configuration ================*/ #ifndef CONFIG_USBDEV_MAX_BUS - #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip #endif #ifndef CONFIG_USBDEV_EP_NUM - #define CONFIG_USBDEV_EP_NUM 8 +#define CONFIG_USBDEV_EP_NUM 8 #endif // #define CONFIG_USBDEV_SOF_ENABLE @@ -270,38 +270,38 @@ // #define CONFIG_USB_DWC2_DMA_ENABLE /* Defined FS Core device FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) -#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) /* Defined FS Core host FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) -#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) /* Defined FS Core total FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (320) +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (320) /* ================ USB Host Port Configuration ==================*/ #ifndef CONFIG_USBHOST_MAX_BUS - #define CONFIG_USBHOST_MAX_BUS 1 +#define CONFIG_USBHOST_MAX_BUS 1 #endif #ifndef CONFIG_USBHOST_PIPE_NUM - #define CONFIG_USBHOST_PIPE_NUM 10 +#define CONFIG_USBHOST_PIPE_NUM 10 #endif #ifndef usb_phyaddr2ramaddr - #define usb_phyaddr2ramaddr(addr) (addr) +#define usb_phyaddr2ramaddr(addr) (addr) #endif #ifndef usb_ramaddr2phyaddr - #define usb_ramaddr2phyaddr(addr) (addr) +#define usb_ramaddr2phyaddr(addr) (addr) #endif #endif diff --git a/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h index 9dbb237fcac..cffd14a0365 100644 --- a/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h +++ b/bsp/hc32/ev_hc32f460_lqfp100_v2/rtconfig.h @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 /* kservice options */ @@ -326,14 +326,6 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ - -/* HPMicro SDK */ - -/* end of HPMicro SDK */ - -/* FT32 HAL & SDK Drivers */ - -/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f467_lqfp144/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..a16d29885aa --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,188 @@ +# ------ device CI ------ +devices.adc: + kconfig: + - CONFIG_BSP_USING_ADC=y + - CONFIG_BSP_USING_ADC1=y + - CONFIG_BSP_ADC1_USING_DMA=y +devices.can: + kconfig: + - CONFIG_BSP_USING_CAN=y + - CONFIG_BSP_USING_CAN1=y + - CONFIG_RT_CAN_USING_HDR=y +devices.crypto: + kconfig: + - CONFIG_BSP_USING_HWCRYPTO=y + - CONFIG_BSP_USING_UQID=y + - CONFIG_BSP_USING_RNG=y + - CONFIG_BSP_USING_CRC=y + - CONFIG_BSP_USING_AES=y + - CONFIG_BSP_USING_HASH=y +devices.dac: + kconfig: + - CONFIG_BSP_USING_DAC=y + - CONFIG_BSP_USING_DAC1=y +devices.flash: + kconfig: + - CONFIG_BSP_USING_ON_CHIP_FLASH=y + - CONFIG_RT_USING_FAL=y + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_SFUD=y +devices.gpio: + kconfig: + - CONFIG_BSP_USING_GPIO=y +devices.clock_timer: + kconfig: + - CONFIG_BSP_USING_CLOCK_TIMER=y + - CONFIG_BSP_USING_TMRA_1=y +devices.i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1=y + - CONFIG_BSP_I2C1_TX_USING_DMA=y + - CONFIG_BSP_I2C1_RX_USING_DMA=y +devices.input_capture: + kconfig: + - CONFIG_BSP_USING_INPUT_CAPTURE=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y +devices.pm: + kconfig: + - CONFIG_BSP_USING_PM=y + - CONFIG_IDLE_THREAD_STACK_SIZE=512 +devices.pulse_encoder_tmr6: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y +devices.pulse_encoder_tmra: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y +devices.pwm_tmr4: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR4=y + - CONFIG_BSP_USING_PWM_TMR4_1=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUL=y +devices.pwm_tmr6: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR6=y + - CONFIG_BSP_USING_PWM_TMR6_1=y + - CONFIG_BSP_USING_PWM_TMR6_1_A=y + - CONFIG_BSP_USING_PWM_TMR6_1_B=y +devices.pwm_tmra: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMRA=y + - CONFIG_BSP_USING_PWM_TMRA_1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH2=y +devices.qspi: + kconfig: + - CONFIG_BSP_USING_QSPI=y + - CONFIG_BSP_QSPI_USING_DMA=y + - CONFIG_BSP_QSPI_USING_SOFT_CS=y +devices.rtc: + kconfig: + - CONFIG_BSP_USING_RTC=y + - CONFIG_RT_USING_ALARM=y +devices.sdio: + kconfig: + - CONFIG_BSP_USING_SDIO=y + - CONFIG_BSP_USING_SDIO1=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.soft_i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1_SW=y +devices.spi: + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI1=y + - CONFIG_BSP_SPI1_TX_USING_DMA=y + - CONFIG_BSP_SPI1_RX_USING_DMA=y + - CONFIG_BSP_SPI_USING_DMA=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.uart_v1: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART6=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART6_RX_USING_DMA=y + - CONFIG_BSP_UART6_TX_USING_DMA=y +devices.uart_v2: + kconfig: + - CONFIG_RT_USING_SERIAL_V2=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART6=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART6_RX_USING_DMA=y + - CONFIG_BSP_UART6_TX_USING_DMA=y +devices.usb_hs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBD_HS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_hs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBH_HS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.usb_fs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBD_FS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_fs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBH_FS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.watchdog_swdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_SWDT=y +devices.watchdog_wdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_WDT=y + +# ------ peripheral CI ------ +peripheral.eth_rmii: + kconfig: + - CONFIG_BSP_USING_ETH=y + - CONFIG_ETH_INTERFACE_USING_RMII=y + - CONFIG_ETH_PHY_USING_INTERRUPT_MODE=y + - CONFIG_RT_USING_LWIP212=y + - CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +peripheral.exmc_nand: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_NAND=y + - CONFIG_FINSH_USING_MSH=y +peripheral.exmc_sdram: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_SDRAM=y + - CONFIG_FINSH_USING_MSH=y +peripheral.spi_flash: + kconfig: + - CONFIG_BSP_USING_SPI_FLASH=y diff --git a/bsp/hc32/ev_hc32f467_lqfp144/.config b/bsp/hc32/ev_hc32f467_lqfp144/.config new file mode 100644 index 00000000000..8aa652309b1 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/.config @@ -0,0 +1,1482 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=24 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart7" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_USING_HW_ATOMIC_8=y +CONFIG_ARCH_USING_HW_ATOMIC_16=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +CONFIG_RT_USING_INPUT_CAPTURE=y +CONFIG_RT_INPUT_CAPTURE_RB_SIZE=100 +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER=y +CONFIG_PKG_HC32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32-f4-cmsis" +CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_HC32F4_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_HC32F4_SERIES_DRIVER=y +CONFIG_PKG_HC32F4_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32-f4-series" +CONFIG_PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest" +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_HC32=y +CONFIG_SOC_SERIES_HC32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HC32F467RG=y + +# +# On-chip Drivers +# +CONFIG_BSP_USING_ON_CHIP_FLASH_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_DCODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH=y +# end of On-chip Drivers + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_EXMC is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +CONFIG_BSP_USING_TCA9539=y +CONFIG_BSP_USING_EXT_IO=y +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +# CONFIG_BSP_USING_UART1 is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +CONFIG_BSP_USING_UART7=y +# CONFIG_BSP_UART7_RX_USING_DMA is not set +# CONFIG_BSP_UART7_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART10 is not set +CONFIG_BSP_USING_I2C=y +# CONFIG_BSP_USING_I2C1_SW is not set +CONFIG_BSP_USING_I2C_HW=y +CONFIG_BSP_USING_I2C1=y +# CONFIG_BSP_I2C1_TX_USING_DMA is not set +# CONFIG_BSP_I2C1_RX_USING_DMA is not set +# CONFIG_BSP_USING_I2C2 is not set +# CONFIG_BSP_USING_I2C3 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_WDT_TMR is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_PM is not set +# CONFIG_BSP_USING_HWCRYPTO is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_PULSE_ENCODER is not set +# CONFIG_BSP_USING_CLOCK_TIMER is not set +# CONFIG_BSP_USING_INPUT_CAPTURE is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/hc32/ev_hc32f467_lqfp144/.cproject b/bsp/hc32/ev_hc32f467_lqfp144/.cproject new file mode 100644 index 00000000000..09d16161fd5 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/.cproject @@ -0,0 +1,224 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/.gitignore b/bsp/hc32/ev_hc32f467_lqfp144/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32/ev_hc32f467_lqfp144/.project b/bsp/hc32/ev_hc32f467_lqfp144/.project new file mode 100644 index 00000000000..49763a6a327 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/.project @@ -0,0 +1,78 @@ + + + ev_hc32f467_lqfp144 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + rt-thread + 2 + virtual:/virtual + + + rt-thread/bsp + 2 + virtual:/virtual + + + rt-thread/components + 2 + $%7BPARENT-3-PROJECT_LOC%7D/components + + + rt-thread/include + 2 + $%7BPARENT-3-PROJECT_LOC%7D/include + + + rt-thread/libcpu + 2 + $%7BPARENT-3-PROJECT_LOC%7D/libcpu + + + rt-thread/src + 2 + $%7BPARENT-3-PROJECT_LOC%7D/src + + + rt-thread/bsp/hc32 + 2 + virtual:/virtual + + + rt-thread/bsp/hc32/libraries + 2 + $%7BPARENT-1-PROJECT_LOC%7D/libraries + + + rt-thread/bsp/hc32/platform + 2 + PARENT-1-PROJECT_LOC/platform + + + rt-thread/bsp/hc32/tests + 2 + PARENT-1-PROJECT_LOC/tests + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/EventRecorderStub.scvd b/bsp/hc32/ev_hc32f467_lqfp144/EventRecorderStub.scvd new file mode 100644 index 00000000000..2956b296838 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/Kconfig b/bsp/hc32/ev_hc32f467_lqfp144/Kconfig new file mode 100644 index 00000000000..73238d3a13b --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hc32/ev_hc32f467_lqfp144/README.md b/bsp/hc32/ev_hc32f467_lqfp144/README.md new file mode 100644 index 00000000000..11d05b9a50b --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/README.md @@ -0,0 +1,142 @@ +# XHSC EV_F467_LQ144 开发板 BSP 说明 + +## 简介 + +本文档为小华半导体为 EV_F467_LQ144 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +EV_F467_LQ144 是 XHSC 官方推出的开发板，搭载 HC32F467RGTI 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F467RGTI 的芯片性能。 + +开发板外观如下图所示： + + ![board](figures/board.jpg) + +EV_F467_LQ144 开发板常用 **板载资源** 如下： + +- MCU：HC32F466RGTI，主频240MHz，1048KB FLASH，512KB RAM +- 外部RAM：IS62WV51216(SRAM，1MB) IS42S16400J(SDRAM，8MB) +- 外部FLASH: MT29F2G08AB(Nand，256MB) W25Q64(SPI NOR，8MB) +- 常用外设 + - LED：3 个，User LED(LED0、LED1、LED2)。 + - 按键：6 个，矩阵键盘(K1~K4)、WAKEUP(K5)、RESET(K0)。 +- 常用接口：SD卡接口、以太网接口、LCD接口、USB FS/HS接口、DVP接口、3.5mm耳机接口、Line in接口、CAN接口、LIN接口。 +- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。 + +开发板更多详细信息请参考小华半导体半导体[EV_F467_LQ144](https://www.xhsc.com.cn) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ETH | 支持 | RTL8201F | +| Nand | 支持 | MT29F2G08AB | +| SDRAM | 支持 | IS42S16400J | +| USB 转串口 | 支持 | 使用 UART7 | + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ADC | 支持 | | +| CAN | 支持 | | +| Crypto | 支持 | AES，CRC，HASH，RNG | +| DAC | 支持 | | +| FLASH | 支持 | | +| GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 | +| CLOCK_TIMER | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| InputCapture | 支持 | | +| PM | 支持 | | +| PulseEncoder | 支持 | | +| PWM | 支持 | | +| QSPI | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| SDIO | 支持 | | +| SPI | 支持 | | +| UART V1 & V2 | 支持 | | +| USB | 支持 | USBFS/HS Core， device/host模式 | +| WDT | 支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用Type-A to MircoUSB线连接开发板和PC供电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED10会周期性闪烁。 + +USB虚拟COM端口默认连接串口7，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.1.0 build Apr 24 2022 13:32:39 + 2006 - 2022 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 7 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +| 板载外设 | 模式 | 协议栈 | 注意事项 | +| :------: | :----: | :------------: | :----------------------------------------------------------- | +| USB | device | ALL | 由于协议栈的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | +| USB | device | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需先通过J14连接到主机（如PC），再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | ALL | ALL | 由于main()函数中的LED闪烁示例，使用的是USBFS主机的供电控制管脚，因而当配置为使用USBFS Core时，需要将main()函数中的LED示例代码手动屏蔽。 | +| USB | host | ALL | 为确保USB主机对外供电充足，建议通过J35外接5V电源供电，并短接J32的EXT跳帽。 | +| USB | host | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需通过J14先连接好OTG线，再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | host | RTT legacy USB | 目前仅实现并测试了对U盘的支持。 | +| USB | host | RTT legacy USB | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | +| USB | ALL | ALL | 由于管脚复用的原因，当配置使用USBHS Core时，无法同时使用板载SPI FLASH。 | +| USB | ALL | ALL | CherryUSB 与 RTT legacy USB 组件不可同时使用;
CherryUSB与 ”On-Chip Peripheral Driver---> []Enable USB“ 不可同时使能及配置。 | +| USB | ALL | RTT legacy USB | 通过“board/config/usb_config/usb_app_conf.h” 进行应用个性化配置（主要为FIFO分配） | +| USB | ALL | CherryUSB | 通过“board/ports/usb_config.h”进行应用个性化配置（如FIFO分配、是否使用DMA[Device]、是否使用高速PHY等） | + +## 联系人信息 + +维护人: + +- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱： diff --git a/bsp/hc32/ev_hc32f467_lqfp144/SConscript b/bsp/hc32/ev_hc32f467_lqfp144/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/ev_hc32f467_lqfp144/SConstruct b/bsp/hc32/ev_hc32f467_lqfp144/SConstruct new file mode 100644 index 00000000000..6d2a0ea7e9c --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/SConstruct @@ -0,0 +1,83 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "hc32-f4-cmsis-latest"), + os.path.join("packages", "hc32-f4-series-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +rtconfig.BSP_LIBRARY_TYPE = None + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript'))) + +# include platform +platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform' +objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript'))) + +# include tests +test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests' +objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32/ev_hc32f467_lqfp144/applications/SConscript b/bsp/hc32/ev_hc32f467_lqfp144/applications/SConscript new file mode 100644 index 00000000000..9bb9abae897 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/hc32/ev_hc32f467_lqfp144/applications/main.c b/bsp/hc32/ev_hc32f467_lqfp144/applications/main.c new file mode 100644 index 00000000000..0cb11049480 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/applications/main.c @@ -0,0 +1,28 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#include +#include +#include +#include + +int main(void) +{ + /* set LED_BLUE_PIN pin mode to output */ + TCA9539_ConfigPin(LED_BLUE_PORT, LED_BLUE_PIN, TCA9539_DIR_OUT); + + while (1) + { + TCA9539_WritePin(LED_BLUE_PORT, LED_BLUE_PIN, TCA9539_PIN_SET); + rt_thread_mdelay(500); + TCA9539_WritePin(LED_BLUE_PORT, LED_BLUE_PIN, TCA9539_PIN_RESET); + rt_thread_mdelay(500); + } +} diff --git a/bsp/hc32/ev_hc32f467_lqfp144/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f467_lqfp144/applications/xtal32_fcm.c new file mode 100644 index 00000000000..9c28a06ea40 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/applications/xtal32_fcm.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include +#include +#include + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM) + +/** + * @brief This thread is used to monitor whether XTAL32 is stable. + * This thread only runs once after the system starts. + * When stability is detected or 2s times out, the thread will end. + * (When a timeout occurs it will be prompted via rt_kprintf) + */ +void xtal32_fcm_thread_entry(void *parameter) +{ + stc_fcm_init_t stcFcmInit; + uint32_t u32TimeOut = 0UL; + uint32_t u32Time = 200UL; /* 200*10ms = 2s */ + + /* FCM config */ + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); + (void)FCM_StructInit(&stcFcmInit); + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); + /* Enable FCM, to ensure xtal32 stable */ + FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); + + while (1) + { + if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END)) + { + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END); + if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF))) + { + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF); + } + else + { + (void)FCM_DeInit(XTAL32_FCM_UNIT); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + /* XTAL32 stabled */ + break; + } + } + u32TimeOut++; + if (u32TimeOut > u32Time) + { + (void)FCM_DeInit(XTAL32_FCM_UNIT); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + rt_kprintf("Error: XTAL32 still unstable, timeout.\n"); + break; + } + rt_thread_mdelay(10); + } +} + +int xtal32_fcm_thread_create(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL, + XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + rt_kprintf("create xtal32_fcm thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(xtal32_fcm_thread_create); + +#endif + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/Kconfig b/bsp/hc32/ev_hc32f467_lqfp144/board/Kconfig new file mode 100644 index 00000000000..b20ce601401 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/Kconfig @@ -0,0 +1,910 @@ +menu "Hardware Drivers Config" + +config SOC_HC32F467RG + bool + select SOC_SERIES_HC32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Drivers" + menuconfig BSP_USING_ON_CHIP_FLASH_CACHE + bool "Enable on-chip Flash Cache" + default y + if BSP_USING_ON_CHIP_FLASH_CACHE + config BSP_USING_ON_CHIP_FLASH_ICODE_CACHE + bool "Enable on-chip Flash ICODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_DCODE_CACHE + bool "Enable on-chip Flash DCODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH + bool "Enable on-chip Flash ICODE Prefetch" + default y + endif +endmenu + +menu "Onboard Peripheral Drivers" + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_LWIP + select RT_LWIP_USING_HW_CHECKSUM + + if BSP_USING_ETH + choice + prompt "Select ETH PHY type" + default ETH_PHY_USING_RTL8201F + + config ETH_PHY_USING_RTL8201F + bool "ETH PHY USING RTL8201F" + select BSP_USING_I2C + select BSP_USING_I2C1 + select BSP_USING_TCA9539 + endchoice + + choice + prompt "Select ETH Communication Interface" + default ETH_INTERFACE_USING_RMII + + config ETH_INTERFACE_USING_RMII + bool "ETH Communication USING RMII" + endchoice + endif + + config BSP_USING_EXMC + bool "Enable EXMC" + default n + if BSP_USING_EXMC + choice + prompt "Using SDRAM or NAND" + default BSP_USING_NAND + + config BSP_USING_NAND + bool "Using NAND (MT29F2G08AB)" + select RT_USING_MTD_NAND + + config BSP_USING_SDRAM + bool "Using SDRAM (IS42S16400J7TLI)" + endchoice + endif + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (w25q64 spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select BSP_USING_ON_CHIP_FLASH + select RT_USING_SFUD + select RT_USING_DFS + select RT_USING_FAL + select RT_USING_MTD_NOR + default n + + config BSP_USING_TCA9539 + bool "Enable TCA9539" + select BSP_USING_I2C + select BSP_USING_I2C1 + default n + + config BSP_USING_EXT_IO + bool + default y + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + select BSP_USING_TCA9539 + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default n + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_DMA_PING_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_DMA_PING_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default y + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART7_DMA_PING_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART10 + bool "Enable UART10" + default n + if BSP_USING_UART10 + config BSP_UART10_RX_BUFSIZE + int "Set UART10 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART10_TX_BUFSIZE + int "Set UART10 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + default n + select RT_USING_I2C + + if BSP_USING_I2C + menuconfig BSP_USING_I2C1_SW + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1_SW + config BSP_I2C1_SCL_PIN + int "I2C1 scl pin number" + range 1 144 + default 8 # PA8 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 144 + default 23 # PB7 + endif + endif + + if BSP_USING_I2C + config BSP_I2C_USING_DMA + bool + default n + config BSP_USING_I2C_HW + bool + default n + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool + default n + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool + default n + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + endif + + menuconfig BSP_USING_I2C3 + bool "Enable I2C3 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool + default n + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C3_USING_DMA + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C3_USING_DMA + endif + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_SPI_USING_DMA + bool + default n + + menuconfig BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + if BSP_USING_SPI1 + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI1_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + if BSP_USING_SPI2 + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI2_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + if BSP_USING_SPI3 + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI4 + bool "Enable SPI4 BUS" + default n + if BSP_USING_SPI4 + config BSP_SPI4_TX_USING_DMA + bool "Enable SPI4 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI4_RX_USING_DMA + bool "Enable SPI4 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI4_TX_USING_DMA + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC1 + bool "Enable ADC1" + default n + if BSP_USING_ADC1 + config BSP_ADC1_USING_DMA + bool "using adc1 dma" + default n + endif + menuconfig BSP_USING_ADC2 + bool "Enable ADC2" + default n + if BSP_USING_ADC2 + config BSP_ADC2_USING_DMA + bool "using adc2 dma" + default n + endif + menuconfig BSP_USING_ADC3 + bool "Enable ADC3" + default n + if BSP_USING_ADC3 + config BSP_ADC3_USING_DMA + bool "using adc3 dma" + default n + endif + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "using dac1" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + select RT_CAN_USING_HDR + select BSP_USING_TCA9539 + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using can1" + default n + config BSP_USING_CAN2 + bool "using can2" + default n + endif + + menuconfig BSP_USING_WDT_TMR + bool "Enable Watchdog Timer" + default n + select RT_USING_WDT + if BSP_USING_WDT_TMR + choice + prompt "Select SWDT/WDT" + default BSP_USING_SWDT + + config BSP_USING_SWDT + bool "SWDT(3.72hour(max))" + config BSP_USING_WDT + bool "WDT(10.7s(max))" + endchoice + + config BSP_WDT_CONTINUE_COUNT + bool "Low Power Mode Keeps Counting" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_XTAL32 + + config BSP_RTC_USING_XTAL32 + bool "RTC USING XTAL32" + + config BSP_RTC_USING_LRC + bool "RTC USING LRC" + endchoice + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + default n + select RT_USING_SDIO + select RT_USING_DFS + if BSP_USING_SDIO + config BSP_USING_SDIO1 + bool "Enable SDIO1" + default n + config BSP_USING_SDIO2 + bool "Enable SDIO2" + default n + endif + + menuconfig BSP_USING_PM + bool "Enable PM" + default n + select RT_USING_PM + if BSP_USING_PM + choice + prompt "Select WKTM Clock Src" + default BSP_USING_WKTM_LRC + + config BSP_USING_WKTM_XTAL32 + bool "Using Xtal32" + config BSP_USING_WKTM_LRC + bool "Using LRC" + if BSP_RTC_USING_XTAL32 + config BSP_USING_WKTM_64HZ + bool "Using 64HZ(Note:must use XTAL32 and run RTC)" + endif + endchoice + endif + + menuconfig BSP_USING_HWCRYPTO + bool "Using Hardware Crypto drivers" + default n + select RT_USING_HWCRYPTO + if BSP_USING_HWCRYPTO + config BSP_USING_UQID + bool "Enable UQID (unique id)" + default n + + config BSP_USING_RNG + bool "Using Hardware RNG" + default n + select RT_HWCRYPTO_USING_RNG + + config BSP_USING_CRC + bool "Using Hardware CRC" + default n + select RT_HWCRYPTO_USING_CRC + + config BSP_USING_AES + bool "Using Hardware AES" + default n + select RT_HWCRYPTO_USING_AES + if BSP_USING_AES + choice + prompt "Select AES Mode" + default BSP_USING_AES_ECB + + config BSP_USING_AES_ECB + bool "ECB mode" + select RT_HWCRYPTO_USING_AES_ECB + endchoice + endif + + config BSP_USING_HASH + bool "Using Hardware Hash" + default n + select RT_HWCRYPTO_USING_SHA2 + if BSP_USING_HASH + choice + prompt "Select Hash Mode" + default BSP_USING_SHA2_256 + + config BSP_USING_SHA2_256 + bool "SHA2_256 Mode" + select RT_HWCRYPTO_USING_SHA2_256 + endchoice + endif + + endif + + menuconfig BSP_USING_PWM + bool "Enable output PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM_TMRA + bool "Enable timerA output PWM" + default n + if BSP_USING_PWM_TMRA + menuconfig BSP_USING_PWM_TMRA_1 + bool "Enable timerA-1 output PWM" + default n + if BSP_USING_PWM_TMRA_1 + config BSP_USING_PWM_TMRA_1_CH1 + bool "Enable timerA-1 channel1" + default n + config BSP_USING_PWM_TMRA_1_CH2 + bool "Enable timerA-1 channel2" + default n + config BSP_USING_PWM_TMRA_1_CH3 + bool "Enable timerA-1 channel3" + default n + config BSP_USING_PWM_TMRA_1_CH4 + bool "Enable timerA-1 channel4" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR4 + bool "Enable timer4 output PWM" + default n + if BSP_USING_PWM_TMR4 + menuconfig BSP_USING_PWM_TMR4_1 + bool "Enable timer4-1 output PWM" + default n + if BSP_USING_PWM_TMR4_1 + config BSP_USING_PWM_TMR4_1_OUH + bool "Enable TMR4_1_OUH channel1" + default n + config BSP_USING_PWM_TMR4_1_OUL + bool "Enable TMR4_1_OUL channel2" + default n + config BSP_USING_PWM_TMR4_1_OVH + bool "Enable TMR4_1_OVH channel3" + default n + config BSP_USING_PWM_TMR4_1_OVL + bool "Enable TMR4_1_OVL channel4" + default n + config BSP_USING_PWM_TMR4_1_OWH + bool "Enable TMR4_1_OWH channel5" + default n + config BSP_USING_PWM_TMR4_1_OWL + bool "Enable TMR4_1_OWL channel6" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR6 + bool "Enable timer6 output PWM" + default n + if BSP_USING_PWM_TMR6 + menuconfig BSP_USING_PWM_TMR6_1 + bool "Enable timer6-1 output PWM" + default n + if BSP_USING_PWM_TMR6_1 + config BSP_USING_PWM_TMR6_1_A + bool "Enable TMR6_1_A channel1" + default n + config BSP_USING_PWM_TMR6_1_B + bool "Enable TMR6_1_B channel2" + default n + endif + endif + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + depends on !RT_USING_CHERRYUSB + if BSP_USING_USB + config BSP_USING_USBD + bool + default n + config BSP_USING_USBH + bool + default n + config BSP_USING_USBFS + bool "Use USBFS Core" + default n + if BSP_USING_USBFS + choice + prompt "Select USB Mode" + default BSP_USING_USBD_FS + + config BSP_USING_USBD_FS + bool "USB Device Mode" + select BSP_USING_USBD + select RT_USING_USB_DEVICE + + config BSP_USING_USBH_FS + bool "USB Host Mode" + select BSP_USING_USBH + select RT_USING_USB_HOST + endchoice + if BSP_USING_USBD_FS + config BSP_USING_USBD_VBUS_SENSING + bool "Enable VBUS Sensing for Device" + default y + endif + if BSP_USING_USBH_FS + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers for Host" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + endif + config BSP_USING_USBHS + bool "Use USBHS Core" + default n + if BSP_USING_USBHS + choice + prompt "Select USB Mode" + default BSP_USING_USBH_HS + + config BSP_USING_USBD_HS + bool "USB Device Mode" + select BSP_USING_USBD + select RT_USING_USB_DEVICE + depends on !BSP_USING_USBD_FS + + config BSP_USING_USBH_HS + bool "USB Host Mode" + select BSP_USING_USBH + select RT_USING_USB_HOST + depends on !BSP_USING_USBH_FS + endchoice + choice + prompt "Select USB PHY" + default BSP_USING_USBHS_PHY_EMBED + + config BSP_USING_USBHS_PHY_EMBED + bool "Use USBHS Embedded PHY" + + config BSP_USING_USBHS_PHY_EXTERN + bool "Use USBHS External PHY" + select BSP_USING_I2C1 + select BSP_USING_TCA9539 + endchoice + if BSP_USING_USBD_HS + config BSP_USING_USBD_VBUS_SENSING + bool "Enable VBUS Sensing for Device" + default y + endif + if BSP_USING_USBH_HS + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers for Host" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + endif + endif + + menuconfig BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + if BSP_USING_QSPI + config BSP_QSPI_USING_DMA + bool "Enable QSPI DMA support" + default n + config BSP_QSPI_USING_SOFT_CS + bool "Enable QSPI Soft CS Pin" + default n + endif + + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + default n + select RT_USING_PULSE_ENCODER + if BSP_USING_PULSE_ENCODER + menuconfig BSP_USING_TMRA_PULSE_ENCODER + bool "Use TIMERA As The Pulse Encoder" + default n + if BSP_USING_TMRA_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMRA_1 + bool "Use TIMERA_1 As The Pulse Encoder" + default n + endif + menuconfig BSP_USING_TMR6_PULSE_ENCODER + bool "Use TIMER6 As The Pulse Encoder" + default n + if BSP_USING_TMR6_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMR6_1 + bool "Use TIMER6_1 As The Pulse Encoder" + default n + endif + endif + + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable CLOCK_TIMER" + default n + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_TMRA_1 + bool "Use Timer_a1 As CLOCK_TIMER1" + default n + config BSP_USING_TMRA_2 + bool "Use Timer_a2 As CLOCK_TIMER2" + default n + config BSP_USING_TMRA_3 + bool "Use Timer_a3 As CLOCK_TIMER3" + default n + config BSP_USING_TMRA_4 + bool "Use Timer_a4 As CLOCK_TIMER4" + default n + config BSP_USING_TMRA_5 + bool "Use Timer_a5 As CLOCK_TIMER5" + default n + config BSP_USING_TMRA_6 + bool "Use Timer_a6 As CLOCK_TIMER6" + default n + config BSP_USING_TMRA_7 + bool "Use Timer_a7 As CLOCK_TIMER7" + default n + config BSP_USING_TMRA_8 + bool "Use Timer_a8 As CLOCK_TIMER8" + default n + endif + menuconfig BSP_USING_INPUT_CAPTURE + bool "Enable Input Capture" + default n + select RT_USING_INPUT_CAPTURE + if BSP_USING_INPUT_CAPTURE + menuconfig BSP_USING_INPUT_CAPTURE_TMR6 + bool "Use Timer6 As The Input Capture" + default n + if BSP_USING_INPUT_CAPTURE_TMR6 + config BSP_USING_INPUT_CAPTURE_TMR6_1 + bool "unit 1" + config BSP_USING_INPUT_CAPTURE_TMR6_2 + bool "unit 2" + config BSP_USING_INPUT_CAPTURE_TMR6_3 + bool "unit 3" + endif + endif +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/SConscript b/bsp/hc32/ev_hc32f467_lqfp144/board/SConscript new file mode 100644 index 00000000000..f7786d16aec --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/SConscript @@ -0,0 +1,20 @@ +import os +from building import * + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +path = [cwd] +path += [cwd + '/ports'] +path += [cwd + '/config'] +path += [cwd + '/config/usb_config'] + +CPPDEFINES = ['HC32F467', '__DEBUG'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/board.c b/bsp/hc32/ev_hc32f467_lqfp144/board/board.c new file mode 100644 index 00000000000..63c512920b0 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/board.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#include "board.h" +#include "board_config.h" + +/* unlock/lock peripheral */ +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) + +/** System Base Configuration +*/ +void SystemBase_Config(void) +{ +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE) + EFM_ICacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE) + EFM_DCacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH) + EFM_PrefetchCmd(ENABLE); +#endif + /* Reset the VBAT area */ + PWC_VBAT_Reset(); +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcPLLHInit; +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + stc_clock_pllx_init_t stcPLLAInit; +#endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + stc_clock_xtal32_init_t stcXtal32Init; +#endif + + /* PCLK0, HCLK Max 240MHz */ + /* PCLK1, PCLK4 Max 120MHz */ + /* PCLK2, PCLK3 Max 60MHz */ + /* EX BUS Max 120MHz */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | + CLK_HCLK_DIV1)); + + GPIO_AnalogCmd(XTAL_PORT, XTAL_PIN, ENABLE); + (void)CLK_XtalStructInit(&stcXtalInit); + /* Config Xtal and enable Xtal */ + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); + + (void)CLK_PLLStructInit(&stcPLLHInit); + /* VCO = (8/1)*120 = 960MHz*/ + stcPLLHInit.u8PLLState = CLK_PLL_ON; + stcPLLHInit.PLLCFGR = 0UL; + stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + (void)CLK_PLLInit(&stcPLLHInit); + + /* Highspeed SRAM set to 0 Read/Write wait cycle */ + SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0); + /* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */ + SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1); + /* 0-wait @ 40MHz */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5); + /* 4 cycles for 200 ~ 250MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT4); + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + /* PLLX for USB */ + (void)CLK_PLLxStructInit(&stcPLLAInit); + /* VCO = (8/2)*120 = 480MHz*/ + stcPLLAInit.u8PLLState = CLK_PLL_ON; + stcPLLAInit.PLLCFGR = 0UL; + stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL; + (void)CLK_PLLxInit(&stcPLLAInit); +#endif + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + /* Xtal32 config */ + GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); + (void)CLK_Xtal32StructInit(&stcXtal32Init); + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; + (void)CLK_Xtal32Init(&stcXtal32Init); +#endif +} + +/** Peripheral Clock Configuration +*/ +void PeripheralClock_Config(void) +{ +#if defined(BSP_USING_CAN1) + CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6); +#endif +#if defined(BSP_USING_CAN2) + CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6); +#endif + +#if defined(RT_USING_ADC) + CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP); +#endif +} + +/** Peripheral Registers Unlock +*/ +void PeripheralRegister_Unlock(void) +{ + LL_PERIPH_WE(EXAMPLE_PERIPH_WE); +} + +/*@}*/ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/board.h b/bsp/hc32/ev_hc32f467_lqfp144/board/board.h new file mode 100644 index 00000000000..6a9ede4ff05 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/board.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ll.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (1 * 1024 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) + +#define HC32_SRAM_SIZE (512) +#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION +extern int Image$$RW_IRAM2$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#elif __ICCARM__ +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END HC32_SRAM_END + +void PeripheralRegister_Unlock(void); +void PeripheralClock_Config(void); +void SystemBase_Config(void); +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.c b/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.c new file mode 100644 index 00000000000..f86b7a762ed --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.c @@ -0,0 +1,801 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#include +#include "board_config.h" +#include "tca9539_port.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)CM_USART1: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC); + GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC); + break; +#endif +#if defined(BSP_USING_UART6) + case (rt_uint32_t)CM_USART6: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, USART6_RX_FUNC); + GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, USART6_TX_FUNC); + break; +#endif +#if defined(BSP_USING_UART7) + case (rt_uint32_t)CM_USART7: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART7_RX_PORT, USART7_RX_PIN, USART7_RX_FUNC); + GPIO_SetFunc(USART7_TX_PORT, USART7_TX_PIN, USART7_TX_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_I2C) +rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + (void)GPIO_StructInit(&stcGpioInit); + + switch ((rt_uint32_t)I2Cx) + { +#if defined(BSP_USING_I2C1) + case (rt_uint32_t)CM_I2C1: + /* Configure I2C1 SDA/SCL pin. */ + GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC); + GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(RT_USING_ADC) +rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)ADCx) + { +#if defined(BSP_USING_ADC1) + case (rt_uint32_t)CM_ADC1: + (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC2) + case (rt_uint32_t)CM_ADC2: + (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC3) + case (rt_uint32_t)CM_ADC3: + (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_DAC) +rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)DACx) + { +#if defined(BSP_USING_DAC1) + case (rt_uint32_t)CM_DAC1: + (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit); + (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_CAN) +void CanPhyEnable(void) +{ + TCA9539_WritePin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_DIR_OUT); +} +rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)CANx) + { +#if defined(BSP_USING_CAN1) + case (rt_uint32_t)CM_CAN1: + GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC); + GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC); + break; +#endif +#if defined(BSP_USING_CAN2) + case (rt_uint32_t)CM_CAN2: + GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC); + GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + + +#if defined(RT_USING_SPI) +rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) +{ + rt_err_t result = RT_EOK; +#if defined(BSP_USING_SPI1) + stc_gpio_init_t stcGpioInit; +#endif + + switch ((rt_uint32_t)CM_SPIx) + { +#if defined(BSP_USING_SPI1) + case (rt_uint32_t)CM_SPI1: + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STAT_SET; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); + GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); + GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_ETH) +/* PHY hardware reset time */ +#define PHY_HW_RST_DELAY (0x40U) + +rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) +{ + TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + return RT_EOK; +} + +rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx) +{ + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); + GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); + GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); + GPIO_SetFunc(ETH_RMII_REF_CLK_PORT, ETH_RMII_REF_CLK_PIN, ETH_RMII_REF_CLK_FUNC); + GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); + GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); + GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); + + return RT_EOK; +} +#endif + +#if defined(RT_USING_SDIO) +rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + switch ((rt_uint32_t)SDIOCx) + { +#if defined(BSP_USING_SDIO1) + case (rt_uint32_t)CM_SDIOC1: + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); + + GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); + GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC); + GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); + GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); + GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); + GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_PWM) +#if defined(BSP_USING_PWM_TMRA) +rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PWM_TMRA_1) + case (rt_uint32_t)CM_TMRA_1: +#ifdef BSP_USING_PWM_TMRA_1_CH1 + GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH2 + GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH3 + GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH4 + GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR4) +rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR4x) + { +#if defined(BSP_USING_PWM_TMR4_1) + case (rt_uint32_t)CM_TMR4_1: +#ifdef BSP_USING_PWM_TMR4_1_OUH + GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OUL + GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVH + GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVL + GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWH + GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWL + GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR6) +rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR6x) + { +#if defined(BSP_USING_PWM_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: +#ifdef BSP_USING_PWM_TMR6_1_A + GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR6_1_B + GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif +#endif + +#if defined(BSP_USING_INPUT_CAPTURE) +rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)tmr_instance) + { +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) + case (rt_uint32_t)CM_TMR6_2: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) + case (rt_uint32_t)CM_TMR6_3: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(BSP_USING_SDRAM) +rt_err_t rt_hw_board_sdram_init(void) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + /* DMC_CKE */ + (void)GPIO_Init(SDRAM_CKE_PORT, SDRAM_CKE_PIN, &stcGpioInit); + /* DMC_CLK */ + (void)GPIO_Init(SDRAM_CLK_PORT, SDRAM_CLK_PIN, &stcGpioInit); + /* DMC_LDQM && DMC_UDQM */ + (void)GPIO_Init(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, &stcGpioInit); + /* DMC_BA[0:1] */ + (void)GPIO_Init(SDRAM_BA0_PORT, SDRAM_BA0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_BA1_PORT, SDRAM_BA1_PIN, &stcGpioInit); + /* DMC_CAS && DMC_RAS */ + (void)GPIO_Init(SDRAM_CAS_PORT, SDRAM_CAS_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_RAS_PORT, SDRAM_RAS_PIN, &stcGpioInit); + /* DMC_WE */ + (void)GPIO_Init(SDRAM_WE_PORT, SDRAM_WE_PIN, &stcGpioInit); + /* DMC_DATA[0:15] */ + (void)GPIO_Init(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, &stcGpioInit); + /* DMC_ADD[0:11]*/ + (void)GPIO_Init(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD12_PORT, SDRAM_ADD12_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* DMC_CKE */ + GPIO_SetFunc(SDRAM_CKE_PORT, SDRAM_CKE_PIN, SDRAM_CKE_FUNC); + /* DMC_CLK */ + GPIO_SetFunc(SDRAM_CLK_PORT, SDRAM_CLK_PIN, SDRAM_CLK_FUNC); + /* DMC_LDQM && DMC_UDQM */ + GPIO_SetFunc(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, SDRAM_DQM0_FUNC); + GPIO_SetFunc(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, SDRAM_DQM1_FUNC); + /* DMC_BA[0:1] */ + GPIO_SetFunc(SDRAM_BA0_PORT, SDRAM_BA0_PIN, SDRAM_BA0_FUNC); + GPIO_SetFunc(SDRAM_BA1_PORT, SDRAM_BA1_PIN, SDRAM_BA1_FUNC); + /* DMC_CS */ + GPIO_SetFunc(SDRAM_CS_PORT, SDRAM_CS_PIN, SDRAM_CS_FUNC); + /* DMC_CAS && DMC_RAS */ + GPIO_SetFunc(SDRAM_CAS_PORT, SDRAM_CAS_PIN, SDRAM_CAS_FUNC); + GPIO_SetFunc(SDRAM_RAS_PORT, SDRAM_RAS_PIN, SDRAM_RAS_FUNC); + /* DMC_WE */ + GPIO_SetFunc(SDRAM_WE_PORT, SDRAM_WE_PIN, SDRAM_WE_FUNC); + /* DMC_DATA[0:15] */ + GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); + GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); + GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); + GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); + GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); + GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); + GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); + GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); + GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); + GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); + GPIO_SetFunc(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, SDRAM_DATA10_FUNC); + GPIO_SetFunc(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, SDRAM_DATA11_FUNC); + GPIO_SetFunc(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, SDRAM_DATA12_FUNC); + GPIO_SetFunc(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, SDRAM_DATA13_FUNC); + GPIO_SetFunc(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, SDRAM_DATA14_FUNC); + GPIO_SetFunc(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, SDRAM_DATA15_FUNC); + /* DMC_ADD[0:11]*/ + GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); + GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); + GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); + GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); + GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); + GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); + GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); + GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); + GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); + GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); + GPIO_SetFunc(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, SDRAM_ADD10_FUNC); + GPIO_SetFunc(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, SDRAM_ADD11_FUNC); + GPIO_SetFunc(SDRAM_ADD12_PORT, SDRAM_ADD12_PIN, SDRAM_ADD11_FUNC); + + return result; +} +#endif + +#ifdef RT_USING_PM +void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) +{ + switch (run_mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + break; + + case PM_RUN_MODE_LOW_SPEED: + /* Ensure that system clock less than 8M */ + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL); + + default: + break; + } +} +#endif + +#if defined(BSP_USING_USBFS) +rt_err_t rt_hw_usbfs_board_init(void) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); +#if defined(BSP_USING_USBD_FS) + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ +#endif +#if defined(BSP_USING_USBH_FS) + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ +#endif + return RT_EOK; +} +#endif + +#if defined(BSP_USING_USBHS) +rt_err_t rt_hw_usbhs_board_init(void) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + +#if defined(BSP_USING_USBHS_PHY_EMBED) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); +#if defined(BSP_USING_USBD_HS) + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); +#endif +#if defined(BSP_USING_USBH_HS) + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ +#endif +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + + return RT_EOK; +} +#endif + +#if defined(RT_USING_CHERRYUSB) +rt_err_t rt_hw_usbfs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ + } + else + { + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ + } + return RT_EOK; +} + +rt_err_t rt_hw_usbhs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + +#if !defined(CONFIG_USB_HS) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); + } + else + { + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ + } +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + + return RT_EOK; +} +#endif + + +#if defined(BSP_USING_QSPI) +rt_err_t rt_hw_qspi_board_init(void) +{ + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; +#ifndef BSP_QSPI_USING_SOFT_CS + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); +#endif + (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC); + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmra_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC); +#endif + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC); +#endif + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_NAND) +rt_err_t rt_hw_board_nand_init(void) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + /* NFC_CE */ + (void)GPIO_Init(NAND_CE_PORT, NAND_CE_PIN, &stcGpioInit); + /* NFC_RE */ + (void)GPIO_Init(NAND_RE_PORT, NAND_RE_PIN, &stcGpioInit); + /* NFC_WE */ + (void)GPIO_Init(NAND_WE_PORT, NAND_WE_PIN, &stcGpioInit); + /* NFC_CLE */ + (void)GPIO_Init(NAND_CLE_PORT, NAND_CLE_PIN, &stcGpioInit); + /* NFC_ALE */ + (void)GPIO_Init(NAND_ALE_PORT, NAND_ALE_PIN, &stcGpioInit); + /* NFC_WP */ + (void)GPIO_Init(NAND_WP_PORT, NAND_WP_PIN, &stcGpioInit); + GPIO_SetPins(NAND_WP_PORT, NAND_WP_PIN); + + /* NFC_DATA[0:7] */ + (void)GPIO_Init(NAND_DATA0_PORT, NAND_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA1_PORT, NAND_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA2_PORT, NAND_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA3_PORT, NAND_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA4_PORT, NAND_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA5_PORT, NAND_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA6_PORT, NAND_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA7_PORT, NAND_DATA7_PIN, &stcGpioInit); + /* NFC_RB */ + (void)GPIO_Init(NAND_RB_PORT, NAND_RB_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* NFC_CE */ + GPIO_SetFunc(NAND_CE_PORT, NAND_CE_PIN, NAND_CE_FUNC); + /* NFC_RE */ + GPIO_SetFunc(NAND_RE_PORT, NAND_RE_PIN, NAND_RE_FUNC); + /* NFC_WE */ + GPIO_SetFunc(NAND_WE_PORT, NAND_WE_PIN, NAND_WE_FUNC); + /* NFC_CLE */ + GPIO_SetFunc(NAND_CLE_PORT, NAND_CLE_PIN, NAND_CLE_FUNC); + /* NFC_ALE */ + GPIO_SetFunc(NAND_ALE_PORT, NAND_ALE_PIN, NAND_ALE_FUNC); + /* NFC_WP */ + GPIO_SetFunc(NAND_WP_PORT, NAND_WP_PIN, NAND_WP_FUNC); + /* NFC_RB */ + GPIO_SetFunc(NAND_RB_PORT, NAND_RB_PIN, NAND_RB_FUNC); + /* NFC_DATA[0:7] */ + GPIO_SetFunc(NAND_DATA0_PORT, NAND_DATA0_PIN, NAND_DATA0_FUNC); + GPIO_SetFunc(NAND_DATA1_PORT, NAND_DATA1_PIN, NAND_DATA1_FUNC); + GPIO_SetFunc(NAND_DATA2_PORT, NAND_DATA2_PIN, NAND_DATA2_FUNC); + GPIO_SetFunc(NAND_DATA3_PORT, NAND_DATA3_PIN, NAND_DATA3_FUNC); + GPIO_SetFunc(NAND_DATA4_PORT, NAND_DATA4_PIN, NAND_DATA4_FUNC); + GPIO_SetFunc(NAND_DATA5_PORT, NAND_DATA5_PIN, NAND_DATA5_FUNC); + GPIO_SetFunc(NAND_DATA6_PORT, NAND_DATA6_PIN, NAND_DATA6_FUNC); + GPIO_SetFunc(NAND_DATA7_PORT, NAND_DATA7_PIN, NAND_DATA7_FUNC); + + return result; +} +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.h new file mode 100644 index 00000000000..9ff75acf352 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/board_config.h @@ -0,0 +1,630 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ll.h" +#include "drv_config.h" +#if defined(RT_USING_CHERRYUSB) +#include "usb_config.h" +#endif + +/************************* XTAL port **********************/ +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_PIN (GPIO_PIN_00 | GPIO_PIN_01) + +/************************ USART port **********************/ +#if defined(BSP_USING_UART7) +#define USART7_RX_PORT (GPIO_PORT_D) +#define USART7_RX_PIN (GPIO_PIN_06) +#define USART7_RX_FUNC (GPIO_FUNC_39) + +#define USART7_TX_PORT (GPIO_PORT_D) +#define USART7_TX_PIN (GPIO_PIN_07) +#define USART7_TX_FUNC (GPIO_FUNC_38) +#endif + +#if defined(BSP_USING_UART6) +#define USART6_RX_PORT (GPIO_PORT_D) +#define USART6_RX_PIN (GPIO_PIN_05) +#define USART6_RX_FUNC (GPIO_FUNC_37) + +#define USART6_TX_PORT (GPIO_PORT_E) +#define USART6_TX_PIN (GPIO_PIN_06) +#define USART6_TX_FUNC (GPIO_FUNC_36) +#endif + +/************************ I2C port **********************/ +#if defined(BSP_USING_I2C1) +#define I2C1_SDA_PORT (GPIO_PORT_F) +#define I2C1_SDA_PIN (GPIO_PIN_10) +#define I2C1_SDA_FUNC (GPIO_FUNC_48) + +#define I2C1_SCL_PORT (GPIO_PORT_B) +#define I2C1_SCL_PIN (GPIO_PIN_01) +#define I2C1_SCL_FUNC (GPIO_FUNC_51) +#endif + +/*********** ADC configure *********/ +#if defined(BSP_USING_ADC1) +#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */ +#define ADC1_CH_PIN (GPIO_PIN_00) +#endif + +#if defined(BSP_USING_ADC2) +#define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */ +#define ADC2_CH_PIN (GPIO_PIN_01) +#endif + +#if defined(BSP_USING_ADC3) +#define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */ +#define ADC3_CH_PIN (GPIO_PIN_02) +#endif + +/*********** DAC configure *********/ +#if defined(BSP_USING_DAC1) +#define DAC1_CH1_PORT (GPIO_PORT_A) +#define DAC1_CH1_PIN (GPIO_PIN_04) +#define DAC1_CH2_PORT (GPIO_PORT_A) +#define DAC1_CH2_PIN (GPIO_PIN_05) +#endif + +/*********** CAN configure *********/ +#if defined(BSP_USING_CAN1) +#define CAN1_TX_PORT (GPIO_PORT_D) +#define CAN1_TX_PIN (GPIO_PIN_11) +#define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) + +#define CAN1_RX_PORT (GPIO_PORT_D) +#define CAN1_RX_PIN (GPIO_PIN_04) +#define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) +#endif + +#if defined(BSP_USING_CAN2) +#define CAN2_TX_PORT (GPIO_PORT_D) +#define CAN2_TX_PIN (GPIO_PIN_13) +#define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) + +#define CAN2_RX_PORT (GPIO_PORT_D) +#define CAN2_RX_PIN (GPIO_PIN_12) +#define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) +#endif + +/************************* SPI port ***********************/ +#if defined(BSP_USING_SPI1) +#define SPI1_CS_PORT (GPIO_PORT_C) +#define SPI1_CS_PIN (GPIO_PIN_07) + +#define SPI1_SCK_PORT (GPIO_PORT_C) +#define SPI1_SCK_PIN (GPIO_PIN_06) +#define SPI1_SCK_FUNC (GPIO_FUNC_40) + +#define SPI1_MOSI_PORT (GPIO_PORT_B) +#define SPI1_MOSI_PIN (GPIO_PIN_13) +#define SPI1_MOSI_FUNC (GPIO_FUNC_41) + +#define SPI1_MISO_PORT (GPIO_PORT_B) +#define SPI1_MISO_PIN (GPIO_PIN_12) +#define SPI1_MISO_FUNC (GPIO_FUNC_42) + +#define SPI1_WP_PORT (GPIO_PORT_B) +#define SPI1_WP_PIN (GPIO_PIN_10) + +#define SPI1_HOLD_PORT (GPIO_PORT_B) +#define SPI1_HOLD_PIN (GPIO_PIN_02) +#endif + +/************************* ETH port ***********************/ + +#if defined(BSP_USING_ETH) +#define ETH_SMI_MDIO_PORT (GPIO_PORT_A) +#define ETH_SMI_MDIO_PIN (GPIO_PIN_02) +#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + +#define ETH_SMI_MDC_PORT (GPIO_PORT_C) +#define ETH_SMI_MDC_PIN (GPIO_PIN_01) +#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) +#define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) +#define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TXD0_PORT (GPIO_PORT_G) +#define ETH_RMII_TXD0_PIN (GPIO_PIN_13) +#define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TXD1_PORT (GPIO_PORT_G) +#define ETH_RMII_TXD1_PIN (GPIO_PIN_14) +#define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) +#define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) +#define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) +#define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) +#define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_RXD0_PORT (GPIO_PORT_C) +#define ETH_RMII_RXD0_PIN (GPIO_PIN_04) +#define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_RXD1_PORT (GPIO_PORT_C) +#define ETH_RMII_RXD1_PIN (GPIO_PIN_05) +#define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) +#endif + +/************************ NAND port **********************/ +#if defined(BSP_USING_NAND) +#define NAND_CE_PORT (GPIO_PORT_B) /* PB06 - EXMC_CE1 */ +#define NAND_CE_PIN (GPIO_PIN_06) +#define NAND_CE_FUNC (GPIO_FUNC_12) + +#define NAND_RE_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ +#define NAND_RE_PIN (GPIO_PIN_11) +#define NAND_RE_FUNC (GPIO_FUNC_12) + +#define NAND_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ +#define NAND_WE_PIN (GPIO_PIN_00) +#define NAND_WE_FUNC (GPIO_FUNC_12) + +#define NAND_CLE_PORT (GPIO_PORT_I) /* PI12 - EXMC_CLE */ +#define NAND_CLE_PIN (GPIO_PIN_12) +#define NAND_CLE_FUNC (GPIO_FUNC_12) + +#define NAND_ALE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ +#define NAND_ALE_PIN (GPIO_PIN_03) +#define NAND_ALE_FUNC (GPIO_FUNC_12) + +#define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ +#define NAND_WP_PIN (GPIO_PIN_15) +#define NAND_WP_FUNC (GPIO_FUNC_12) + +#define NAND_RB_PORT (GPIO_PORT_G) /* PG07 - EXMC_RB1 */ +#define NAND_RB_PIN (GPIO_PIN_07) +#define NAND_RB_FUNC (GPIO_FUNC_12) + +#define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ +#define NAND_DATA0_PIN (GPIO_PIN_14) +#define NAND_DATA0_FUNC (GPIO_FUNC_12) +#define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ +#define NAND_DATA1_PIN (GPIO_PIN_15) +#define NAND_DATA1_FUNC (GPIO_FUNC_12) +#define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ +#define NAND_DATA2_PIN (GPIO_PIN_00) +#define NAND_DATA2_FUNC (GPIO_FUNC_12) +#define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ +#define NAND_DATA3_PIN (GPIO_PIN_01) +#define NAND_DATA3_FUNC (GPIO_FUNC_12) +#define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ +#define NAND_DATA4_PIN (GPIO_PIN_07) +#define NAND_DATA4_FUNC (GPIO_FUNC_12) +#define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ +#define NAND_DATA5_PIN (GPIO_PIN_08) +#define NAND_DATA5_FUNC (GPIO_FUNC_12) +#define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ +#define NAND_DATA6_PIN (GPIO_PIN_09) +#define NAND_DATA6_FUNC (GPIO_FUNC_12) +#define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ +#define NAND_DATA7_PIN (GPIO_PIN_10) +#define NAND_DATA7_FUNC (GPIO_FUNC_12) +#endif + +/************************ SDIOC port **********************/ +#if defined(BSP_USING_SDIO1) +#define SDIOC1_CK_PORT (GPIO_PORT_C) +#define SDIOC1_CK_PIN (GPIO_PIN_12) +#define SDIOC1_CK_FUNC (GPIO_FUNC_9) + +#define SDIOC1_CMD_PORT (GPIO_PORT_D) +#define SDIOC1_CMD_PIN (GPIO_PIN_02) +#define SDIOC1_CMD_FUNC (GPIO_FUNC_9) + +#define SDIOC1_D0_PORT (GPIO_PORT_B) +#define SDIOC1_D0_PIN (GPIO_PIN_07) +#define SDIOC1_D0_FUNC (GPIO_FUNC_9) + +#define SDIOC1_D1_PORT (GPIO_PORT_A) +#define SDIOC1_D1_PIN (GPIO_PIN_08) +#define SDIOC1_D1_FUNC (GPIO_FUNC_9) + +#define SDIOC1_D2_PORT (GPIO_PORT_C) +#define SDIOC1_D2_PIN (GPIO_PIN_10) +#define SDIOC1_D2_FUNC (GPIO_FUNC_9) + +#define SDIOC1_D3_PORT (GPIO_PORT_B) +#define SDIOC1_D3_PIN (GPIO_PIN_05) +#define SDIOC1_D3_FUNC (GPIO_FUNC_9) +#endif + +/************************ SDRAM port **********************/ +#if defined(BSP_USING_SDRAM) +#define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ +#define SDRAM_CKE_PIN (GPIO_PIN_03) +#define SDRAM_CKE_FUNC (GPIO_FUNC_12) + +#define SDRAM_CLK_PORT (GPIO_PORT_G) /* PD03 - EXMC_CLK */ +#define SDRAM_CLK_PIN (GPIO_PIN_08) +#define SDRAM_CLK_FUNC (GPIO_FUNC_12) + +#define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ +#define SDRAM_DQM0_PIN (GPIO_PIN_00) +#define SDRAM_DQM0_FUNC (GPIO_FUNC_12) +#define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ +#define SDRAM_DQM1_PIN (GPIO_PIN_01) +#define SDRAM_DQM1_FUNC (GPIO_FUNC_12) + +#define SDRAM_BA0_PORT (GPIO_PORT_G) /* PG04 - EXMC_ADD16 */ +#define SDRAM_BA0_PIN (GPIO_PIN_04) +#define SDRAM_BA0_FUNC (GPIO_FUNC_13) +#define SDRAM_BA1_PORT (GPIO_PORT_G) /* PG05 - EXMC_ADD17 */ +#define SDRAM_BA1_PIN (GPIO_PIN_05) +#define SDRAM_BA1_FUNC (GPIO_FUNC_13) + +#define SDRAM_CS_PORT (GPIO_PORT_C) /* PC02 - EXMC_CE0 */ +#define SDRAM_CS_PIN (GPIO_PIN_02) +#define SDRAM_CS_FUNC (GPIO_FUNC_12) + +#define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ +#define SDRAM_RAS_PIN (GPIO_PIN_11) +#define SDRAM_RAS_FUNC (GPIO_FUNC_12) + +#define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ +#define SDRAM_CAS_PIN (GPIO_PIN_15) +#define SDRAM_CAS_FUNC (GPIO_FUNC_12) + +#define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ +#define SDRAM_WE_PIN (GPIO_PIN_00) +#define SDRAM_WE_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ +#define SDRAM_ADD0_PIN (GPIO_PIN_00) +#define SDRAM_ADD0_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ +#define SDRAM_ADD1_PIN (GPIO_PIN_01) +#define SDRAM_ADD1_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ +#define SDRAM_ADD2_PIN (GPIO_PIN_02) +#define SDRAM_ADD2_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ +#define SDRAM_ADD3_PIN (GPIO_PIN_03) +#define SDRAM_ADD3_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ +#define SDRAM_ADD4_PIN (GPIO_PIN_04) +#define SDRAM_ADD4_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ +#define SDRAM_ADD5_PIN (GPIO_PIN_05) +#define SDRAM_ADD5_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ +#define SDRAM_ADD6_PIN (GPIO_PIN_12) +#define SDRAM_ADD6_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ +#define SDRAM_ADD7_PIN (GPIO_PIN_13) +#define SDRAM_ADD7_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ +#define SDRAM_ADD8_PIN (GPIO_PIN_14) +#define SDRAM_ADD8_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ +#define SDRAM_ADD9_PIN (GPIO_PIN_15) +#define SDRAM_ADD9_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ +#define SDRAM_ADD10_PIN (GPIO_PIN_00) +#define SDRAM_ADD10_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ +#define SDRAM_ADD11_PIN (GPIO_PIN_01) +#define SDRAM_ADD11_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD12_PORT (GPIO_PORT_G) /* PG02 - EXMC_ADD12 */ +#define SDRAM_ADD12_PIN (GPIO_PIN_02) +#define SDRAM_ADD12_FUNC (GPIO_FUNC_12) + +#define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ +#define SDRAM_DATA0_PIN (GPIO_PIN_14) +#define SDRAM_DATA0_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ +#define SDRAM_DATA1_PIN (GPIO_PIN_15) +#define SDRAM_DATA1_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ +#define SDRAM_DATA2_PIN (GPIO_PIN_00) +#define SDRAM_DATA2_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ +#define SDRAM_DATA3_PIN (GPIO_PIN_01) +#define SDRAM_DATA3_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ +#define SDRAM_DATA4_PIN (GPIO_PIN_07) +#define SDRAM_DATA4_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ +#define SDRAM_DATA5_PIN (GPIO_PIN_08) +#define SDRAM_DATA5_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ +#define SDRAM_DATA6_PIN (GPIO_PIN_09) +#define SDRAM_DATA6_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ +#define SDRAM_DATA7_PIN (GPIO_PIN_10) +#define SDRAM_DATA7_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ +#define SDRAM_DATA8_PIN (GPIO_PIN_11) +#define SDRAM_DATA8_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ +#define SDRAM_DATA9_PIN (GPIO_PIN_12) +#define SDRAM_DATA9_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ +#define SDRAM_DATA10_PIN (GPIO_PIN_13) +#define SDRAM_DATA10_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ +#define SDRAM_DATA11_PIN (GPIO_PIN_14) +#define SDRAM_DATA11_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ +#define SDRAM_DATA12_PIN (GPIO_PIN_15) +#define SDRAM_DATA12_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ +#define SDRAM_DATA13_PIN (GPIO_PIN_08) +#define SDRAM_DATA13_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ +#define SDRAM_DATA14_PIN (GPIO_PIN_09) +#define SDRAM_DATA14_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ +#define SDRAM_DATA15_PIN (GPIO_PIN_10) +#define SDRAM_DATA15_FUNC (GPIO_FUNC_12) +#endif + +/************************ RTC/PM *****************************/ +#if defined(BSP_USING_RTC) || defined(RT_USING_PM) +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) +#define XTAL32_PORT (GPIO_PORT_C) +#define XTAL32_IN_PIN (GPIO_PIN_15) +#define XTAL32_OUT_PIN (GPIO_PIN_14) +#endif +#endif + +#if defined(RT_USING_PWM) + /*********** PWM_TMRA configure *********/ +#if defined(BSP_USING_PWM_TMRA_1) +#if defined(BSP_USING_PWM_TMRA_1_CH1) +#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) +#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH2) +#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) +#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH3) +#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) +#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH4) +#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) +#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) +#endif +#endif + + /*********** PWM_TMR4 configure *********/ +#if defined(BSP_USING_PWM_TMR4_1) +#if defined(BSP_USING_PWM_TMR4_1_OUH) +#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) +#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OUL) +#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) +#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVH) +#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) +#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVL) +#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) +#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWH) +#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) +#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWL) +#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) +#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) +#endif +#endif + + /*********** PWM_TMR6 configure *********/ +#if defined(BSP_USING_PWM_TMR6_1) +#if defined(BSP_USING_PWM_TMR6_1_A) +#define PWM_TMR6_1_A_PORT (GPIO_PORT_F) +#define PWM_TMR6_1_A_PIN (GPIO_PIN_13) +#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#endif +#if defined(BSP_USING_PWM_TMR6_1_B) +#define PWM_TMR6_1_B_PORT (GPIO_PORT_F) +#define PWM_TMR6_1_B_PIN (GPIO_PIN_14) +#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif +#endif + +#endif + +#if defined(BSP_USING_INPUT_CAPTURE) +#define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A) +#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_08) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B) +#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) +#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) +#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00) +#endif +#endif + +#if defined(RT_USING_CHERRYUSB) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(BSP_USING_USBHS) || \ + defined(BSP_USING_USBHS_PHY_EMBED) || defined(BSP_USING_USBHS_PHY_EXTERN) || \ + defined(RT_USING_USB) +#error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" +#endif +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) + /* USBFS Core*/ +#define USBF_DP_PORT (GPIO_PORT_A) +#define USBF_DP_PIN (GPIO_PIN_12) +#define USBF_DM_PORT (GPIO_PORT_A) +#define USBF_DM_PIN (GPIO_PIN_11) +#define USBF_VBUS_PORT (GPIO_PORT_A) +#define USBF_VBUS_PIN (GPIO_PIN_09) +#define USBF_VBUS_FUNC (GPIO_FUNC_10) +#define USBF_DRVVBUS_PORT (GPIO_PORT_C) +#define USBF_DRVVBUS_PIN (GPIO_PIN_09) +#define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) +#endif +#if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) + /* USBHS Core*/ +#if defined(BSP_USING_USBHS_PHY_EMBED) || (defined(RT_USING_CHERRYUSB) && !defined(CONFIG_USB_HS)) +#define USBH_DP_PORT (GPIO_PORT_B) +#define USBH_DP_PIN (GPIO_PIN_15) +#define USBH_DP_FUNC (GPIO_FUNC_10) +#define USBH_DM_PORT (GPIO_PORT_B) +#define USBH_DM_PIN (GPIO_PIN_14) +#define USBH_DM_FUNC (GPIO_FUNC_10) +#define USBH_VBUS_PORT (GPIO_PORT_B) +#define USBH_VBUS_PIN (GPIO_PIN_13) +#define USBH_VBUS_FUNC (GPIO_FUNC_12) +#define USBH_DRVVBUS_PORT (GPIO_PORT_B) +#define USBH_DRVVBUS_PIN (GPIO_PIN_11) +#define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) +#else + /* USBHS Core, external PHY */ +#define USBH_ULPI_CLK_PORT (GPIO_PORT_E) +#define USBH_ULPI_CLK_PIN (GPIO_PIN_12) +#define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_DIR_PORT (GPIO_PORT_C) +#define USBH_ULPI_DIR_PIN (GPIO_PIN_02) +#define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_NXT_PORT (GPIO_PORT_C) +#define USBH_ULPI_NXT_PIN (GPIO_PIN_03) +#define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_STP_PORT (GPIO_PORT_C) +#define USBH_ULPI_STP_PIN (GPIO_PIN_00) +#define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D0_PORT (GPIO_PORT_E) +#define USBH_ULPI_D0_PIN (GPIO_PIN_13) +#define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D1_PORT (GPIO_PORT_E) +#define USBH_ULPI_D1_PIN (GPIO_PIN_14) +#define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D2_PORT (GPIO_PORT_E) +#define USBH_ULPI_D2_PIN (GPIO_PIN_15) +#define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D3_PORT (GPIO_PORT_B) +#define USBH_ULPI_D3_PIN (GPIO_PIN_10) +#define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D4_PORT (GPIO_PORT_B) +#define USBH_ULPI_D4_PIN (GPIO_PIN_11) +#define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D5_PORT (GPIO_PORT_B) +#define USBH_ULPI_D5_PIN (GPIO_PIN_12) +#define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D6_PORT (GPIO_PORT_B) +#define USBH_ULPI_D6_PIN (GPIO_PIN_13) +#define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D7_PORT (GPIO_PORT_E) +#define USBH_ULPI_D7_PIN (GPIO_PIN_11) +#define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) + /* 3300 reset */ +#define USB_3300_RESET_PORT (EIO_PORT1) +#define USB_3300_RESET_PIN (EIO_USB3300_RST) +#endif +#endif +#endif + +#if defined(BSP_USING_QSPI) +#ifndef BSP_QSPI_USING_SOFT_CS + /* QSSN */ +#define QSPI_FLASH_CS_PORT (GPIO_PORT_C) +#define QSPI_FLASH_CS_PIN (GPIO_PIN_07) +#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) +#endif + /* QSCK */ +#define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) +#define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) +#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) + /* QSIO0 */ +#define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) +#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) + /* QSIO1 */ +#define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) +#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) + /* QSIO2 */ +#define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) +#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) + /* QSIO3 */ +#define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) +#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) +#endif + +/*********** TMRA_PULSE_ENCODER configure *********/ +#if defined(RT_USING_PULSE_ENCODER) +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) +#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#endif /* BSP_USING_TMRA_PULSE_ENCODER */ + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#endif /* RT_USING_PULSE_ENCODER */ + +#endif + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/adc_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/adc_config.h new file mode 100644 index 00000000000..2c8cfafca77 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/adc_config.h @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_INIT_PARAMS +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC1_INIT_PARAMS */ + +#if defined(BSP_ADC1_USING_DMA) +#ifndef ADC1_EOCA_DMA_CONFIG +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC1_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC1_USING_DMA */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_INIT_PARAMS +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC2_INIT_PARAMS */ + +#if defined(BSP_ADC2_USING_DMA) +#ifndef ADC2_EOCA_DMA_CONFIG +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC2_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC2_USING_DMA */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_INIT_PARAMS +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC3_INIT_PARAMS */ +#if defined(BSP_ADC3_USING_DMA) +#ifndef ADC3_EOCA_DMA_CONFIG +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC3_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC3_USING_DMA */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/can_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/can_config.h new file mode 100644 index 00000000000..19a6c41dfc8 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/can_config.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __CAN_CONFIG_H__ +#define __CAN_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_CAN1 +#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN1_NAME ("can1") +#ifndef CAN1_INIT_PARAMS +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN1_INIT_PARAMS */ +#endif /* BSP_USING_CAN1 */ + +#ifdef BSP_USING_CAN2 +#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN2_NAME ("can2") +#ifndef CAN2_INIT_PARAMS +#define CAN2_INIT_PARAMS \ + { \ + .name = CAN2_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN2_INIT_PARAMS */ +#endif /* BSP_USING_CAN2 */ + +/* Bit time config + Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW. + + Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2)) + TQ = u32Prescaler / CANClock. + Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ. + + The following bit time configures are based on CAN Clock 40M +*/ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/dac_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/dac_config.h new file mode 100644 index 00000000000..d1c05a5e7f2 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/dac_config.h @@ -0,0 +1,43 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_INIT_PARAMS +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + } +#endif /* DAC1_INIT_PARAMS */ +#endif /* BSP_USING_DAC1 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/dma_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/dma_config.h new file mode 100644 index 00000000000..abc4ca6d14c --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/dma_config.h @@ -0,0 +1,369 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 ch0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE) +#define SDIO1_RX_DMA_INSTANCE CM_DMA1 +#define SDIO1_RX_DMA_CHANNEL DMA_CH0 +#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#endif + +/* DMA1 ch1 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE) +#define SDIO1_TX_DMA_INSTANCE CM_DMA1 +#define SDIO1_TX_DMA_CHANNEL DMA_CH1 +#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#endif + +/* DMA1 ch2 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE) +#define SDIO2_RX_DMA_INSTANCE CM_DMA1 +#define SDIO2_RX_DMA_CHANNEL DMA_CH2 +#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#endif + +/* DMA1 ch3 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE) +#define SDIO2_TX_DMA_INSTANCE CM_DMA1 +#define SDIO2_TX_DMA_CHANNEL DMA_CH3 +#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_INSTANCE CM_DMA1 +#define QSPI_DMA_CHANNEL DMA_CH3 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) +#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 +#endif + +/* DMA1 ch4 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH4 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) +#define I2C3_TX_DMA_INSTANCE CM_DMA1 +#define I2C3_TX_DMA_CHANNEL DMA_CH4 +#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 +#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) +#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 +#endif + +/* DMA1 ch5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH5 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) +#define I2C3_RX_DMA_INSTANCE CM_DMA1 +#define I2C3_RX_DMA_CHANNEL DMA_CH5 +#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 +#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) +#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 +#endif + +/* DMA1 ch6 */ +#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_RX_DMA_INSTANCE CM_DMA1 +#define SPI4_RX_DMA_CHANNEL DMA_CH6 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 +#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#endif + +/* DMA1 ch7 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_TX_DMA_INSTANCE CM_DMA1 +#define SPI4_TX_DMA_CHANNEL DMA_CH7 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 +#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#endif + +/* DMA1 ch8 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_TX_DMA_INSTANCE CM_DMA1 +#define SPI5_TX_DMA_CHANNEL DMA_CH8 +#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 +#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 +#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM +#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO +#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 +#endif + +/* DMA1 ch9 */ +#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) +#define SPI6_TX_DMA_INSTANCE CM_DMA1 +#define SPI6_TX_DMA_CHANNEL DMA_CH9 +#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 +#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 +#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM +#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO +#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 +#endif + +/* DMA2 ch0 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#endif + +/* DMA2 ch1 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#endif + +/* DMA2 ch2 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#endif + +/* DMA2 ch3 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#endif + +/* DMA2 ch4 */ +#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) +#define UART6_RX_DMA_INSTANCE CM_DMA2 +#define UART6_RX_DMA_CHANNEL DMA_CH4 +#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#endif + +/* DMA2 ch5 */ +#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) +#define UART6_TX_DMA_INSTANCE CM_DMA2 +#define UART6_TX_DMA_CHANNEL DMA_CH5 +#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#endif + +/* DMA2 ch6 */ +#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) +#define UART7_RX_DMA_INSTANCE CM_DMA2 +#define UART7_RX_DMA_CHANNEL DMA_CH6 +#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 +#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM +#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO +#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 +#endif + +/* DMA2 ch7 */ +#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#define UART7_TX_DMA_INSTANCE CM_DMA2 +#define UART7_TX_DMA_CHANNEL DMA_CH7 +#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 +#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM +#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO +#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/eth_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/eth_config.h new file mode 100644 index 00000000000..425f5284338 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/eth_config.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __ETH_CONFIG_H__ +#define __ETH_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_ETH) + +#ifndef ETH_IRQ_CONFIG +#define ETH_IRQ_CONFIG \ + { \ + .irq_num = BSP_ETH_IRQ_NUM, \ + .irq_prio = BSP_ETH_IRQ_PRIO, \ + .int_src = INT_SRC_ETH_GLB_INT, \ + } +#endif /* ETH_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __ETH_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/gpio_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/gpio_config.h new file mode 100644 index 00000000000..71a37311f25 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/gpio_config.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __GPIO_CONFIG_H__ +#define __GPIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(RT_USING_PIN) + +#ifndef EXTINT0_IRQ_CONFIG +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT1_IRQ_CONFIG +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT2_IRQ_CONFIG +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ + } +#endif /* EXTINT2_IRQ_CONFIG */ + +#ifndef EXTINT3_IRQ_CONFIG +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ + } +#endif /* EXTINT3_IRQ_CONFIG */ + +#ifndef EXTINT4_IRQ_CONFIG +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ + } +#endif /* EXTINT4_IRQ_CONFIG */ + +#ifndef EXTINT5_IRQ_CONFIG +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ + } +#endif /* EXTINT5_IRQ_CONFIG */ + +#ifndef EXTINT6_IRQ_CONFIG +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ + } +#endif /* EXTINT6_IRQ_CONFIG */ + +#ifndef EXTINT7_IRQ_CONFIG +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ + } +#endif /* EXTINT7_IRQ_CONFIG */ + +#ifndef EXTINT8_IRQ_CONFIG +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ + } +#endif /* EXTINT8_IRQ_CONFIG */ + +#ifndef EXTINT9_IRQ_CONFIG +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ + } +#endif /* EXTINT9_IRQ_CONFIG */ + +#ifndef EXTINT10_IRQ_CONFIG +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ + } +#endif /* EXTINT10_IRQ_CONFIG */ + +#ifndef EXTINT11_IRQ_CONFIG +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ + } +#endif /* EXTINT11_IRQ_CONFIG */ + +#ifndef EXTINT12_IRQ_CONFIG +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ + } +#endif /* EXTINT12_IRQ_CONFIG */ + +#ifndef EXTINT13_IRQ_CONFIG +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ + } +#endif /* EXTINT13_IRQ_CONFIG */ + +#ifndef EXTINT14_IRQ_CONFIG +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ + } +#endif /* EXTINT14_IRQ_CONFIG */ + +#ifndef EXTINT15_IRQ_CONFIG +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ + } +#endif /* EXTINT15_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/i2c_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/i2c_config.h new file mode 100644 index 00000000000..987455e7596 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/i2c_config.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_I2C1) +#ifndef I2C1_CONFIG +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C1_CONFIG */ +#endif + +#if defined(BSP_I2C1_USING_DMA) +#ifndef I2C1_TX_DMA_CONFIG +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_TX_DMA_CONFIG */ + +#ifndef I2C1_RX_DMA_CONFIG +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_USING_DMA */ + +#if defined(BSP_USING_I2C2) +#ifndef I2C2_CONFIG +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C2_CONFIG */ + +#if defined(BSP_I2C2_USING_DMA) +#ifndef I2C2_TX_DMA_CONFIG +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_TX_DMA_CONFIG */ + +#ifndef I2C2_RX_DMA_CONFIG +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C3) +#ifndef I2C3_CONFIG +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C3_CONFIG */ + +#if defined(BSP_I2C3_USING_DMA) +#ifndef I2C3_TX_DMA_CONFIG +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_TX_DMA_CONFIG */ + +#ifndef I2C3_RX_DMA_CONFIG +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_USING_DMA */ +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/irq_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/irq_config.h new file mode 100644 index 00000000000..d42f2bb54c7 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/irq_config.h @@ -0,0 +1,426 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __IRQ_CONFIG_H__ +#define __IRQ_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA1 ch0 */ +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch1 */ +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch2 */ +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch3 */ +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch4 */ +#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch5 */ +#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch6 */ +#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch7 */ +#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch8 */ +#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn +#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch9 */ +#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn +#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA2 ch0 */ +#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch1 */ +#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch2 */ +#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch3 */ +#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch4 */ +#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch5 */ +#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch6 */ +#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn +#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch7 */ +#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn +#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_USING_ETH) +#define BSP_ETH_IRQ_NUM INT104_IRQn +#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART1) +#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT089_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT088_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART1_RX_USING_DMA) +#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT091_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT090_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART2_RX_USING_DMA) +#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#elif defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) +#define BSP_SPI1_ERR_IRQ_NUM INT007_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM INT011_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT095_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT094_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT097_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT096_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn +#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RX_IRQ_NUM INT101_IRQn +#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_IRQ_NUM INT100_IRQn +#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn +#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RX_IRQ_NUM INT103_IRQn +#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_IRQ_NUM INT102_IRQn +#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART6_RX_USING_DMA) +#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn +#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn +#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RX_IRQ_NUM INT107_IRQn +#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_IRQ_NUM INT106_IRQn +#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART7_RX_USING_DMA) +#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn +#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_SPI3) +#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI4) +#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn +#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI5) +#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn +#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI6) +#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn +#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART10) +#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn +#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RX_IRQ_NUM INT114_IRQn +#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_IRQ_NUM INT113_IRQn +#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART10 */ + +#if defined(BSP_USING_CAN1) +#define BSP_CAN1_IRQ_NUM INT092_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_CAN1 */ + +#if defined(BSP_USING_CAN2) +#define BSP_CAN2_IRQ_NUM INT093_IRQn +#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_CAN2 */ + +#if defined(BSP_USING_SDIO1) +#define BSP_SDIO1_IRQ_NUM INT004_IRQn +#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_SDIO1 */ + +#if defined(BSP_USING_SDIO2) +#define BSP_SDIO2_IRQ_NUM INT005_IRQn +#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_SDIO2 */ + +#if defined(RT_USING_ALARM) +#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* RT_USING_ALARM */ + + +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) +#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn +#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_USBFS */ + +#if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) +#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn +#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_USBHS */ + +#if defined(BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_QSPI */ + +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_2) +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_3) +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_4) +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_5) +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_6) +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_7) +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_7 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_8) +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_8 */ + +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_2) +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_3) +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */ + +#if defined(BSP_USING_TMRA_1) +#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_1 */ +#if defined(BSP_USING_TMRA_2) +#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_2 */ +#if defined(BSP_USING_TMRA_3) +#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_3 */ +#if defined(BSP_USING_TMRA_4) +#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_4 */ +#if defined(BSP_USING_TMRA_5) +#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_5 */ +#if defined(BSP_USING_TMRA_6) +#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn +#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_6 */ +#if defined(BSP_USING_TMRA_7) +#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn +#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_7 */ +#if defined(BSP_USING_TMRA_8) +#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn +#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_8 */ + +#if defined(BSP_USING_INPUT_CAPTURE) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/pm_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pm_config.h new file mode 100644 index 00000000000..892ab781024 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pm_config.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + * 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer + */ + +#ifndef __PM_CONFIG_H__ +#define __PM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PM +extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); + +/** + * @brief run mode config @ref pm_run_mode_config structure + */ +#ifndef PM_RUN_MODE_CFG +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ + } +#endif /* PM_RUN_MODE_CFG */ + +/** + * @brief sleep idle config @ref pm_sleep_mode_idle_config structure + */ +#ifndef PM_SLEEP_IDLE_CFG +#define PM_SLEEP_IDLE_CFG \ + { \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ + } +#endif /*PM_SLEEP_IDLE_CFG*/ + +/** + * @brief sleep deep config @ref pm_sleep_mode_deep_config structure + */ +#ifndef PM_SLEEP_DEEP_CFG +#define PM_SLEEP_DEEP_CFG \ + { \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ + } +#endif /*PM_SLEEP_DEEP_CFG*/ + +/** + * @brief sleep standby config @ref pm_sleep_mode_standby_config structure + */ +#ifndef PM_SLEEP_STANDBY_CFG +#define PM_SLEEP_STANDBY_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } +#endif /*PM_SLEEP_STANDBY_CFG*/ + +/** + * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure + */ +#ifndef PM_SLEEP_SHUTDOWN_CFG +#define PM_SLEEP_SHUTDOWN_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } +#endif /*PM_SLEEP_SHUTDOWN_CFG*/ + +#endif /* BSP_USING_PM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PM_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pulse_encoder_config.h new file mode 100644 index 00000000000..dd42f50ad9f --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pulse_encoder_config.h @@ -0,0 +1,288 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __PULSE_ENCODER_CONFIG_H__ +#define __PULSE_ENCODER_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_PULSE_ENCODER) + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_1 +#ifndef PULSE_ENCODER_TMRA_1_CONFIG +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ + } +#endif /* PULSE_ENCODER_TMRA_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_2 +#ifndef PULSE_ENCODER_TMRA_2_CONFIG +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ + } +#endif /* PULSE_ENCODER_TMRA_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_3 +#ifndef PULSE_ENCODER_TMRA_3_CONFIG +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ + } +#endif /* PULSE_ENCODER_TMRA_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_4 +#ifndef PULSE_ENCODER_TMRA_4_CONFIG +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ + } +#endif /* PULSE_ENCODER_TMRA_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_5 +#ifndef PULSE_ENCODER_TMRA_5_CONFIG +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ + } +#endif /* PULSE_ENCODER_TMRA_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_6 +#ifndef PULSE_ENCODER_TMRA_6_CONFIG +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ + } +#endif /* PULSE_ENCODER_TMRA_6_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_7 +#ifndef PULSE_ENCODER_TMRA_7_CONFIG +#define PULSE_ENCODER_TMRA_7_CONFIG \ + { \ + .tmr_handler = CM_TMRA_7, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_7, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a7" \ + } +#endif /* PULSE_ENCODER_TMRA_7_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_8 +#ifndef PULSE_ENCODER_TMRA_8_CONFIG +#define PULSE_ENCODER_TMRA_8_CONFIG \ + { \ + .tmr_handler = CM_TMRA_8, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_8, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a8" \ + } +#endif /* PULSE_ENCODER_TMRA_8_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_1 +#ifndef PULSE_ENCODER_TMR6_1_CONFIG +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ + } +#endif /* PULSE_ENCODER_TMR6_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_2 +#ifndef PULSE_ENCODER_TMR6_2_CONFIG +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ + } +#endif /* PULSE_ENCODER_TMR6_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_3 +#ifndef PULSE_ENCODER_TMR6_3_CONFIG +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ + } +#endif /* PULSE_ENCODER_TMR6_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ + +#endif /* RT_USING_PULSE_ENCODER */ + +#endif /* __PULSE_ENCODER_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pwm_tmr_config.h new file mode 100644 index 00000000000..6ac08beeadf --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/pwm_tmr_config.h @@ -0,0 +1,465 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __PWM_TMR_CONFIG_H__ +#define __PWM_TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM_TMRA + +#ifdef BSP_USING_PWM_TMRA_1 +#ifndef PWM_TMRA_1_CONFIG +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_1_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_1 */ + +#ifdef BSP_USING_PWM_TMRA_2 +#ifndef PWM_TMRA_2_CONFIG +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_2_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_2 */ + +#ifdef BSP_USING_PWM_TMRA_3 +#ifndef PWM_TMRA_3_CONFIG +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_3_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_3 */ + +#ifdef BSP_USING_PWM_TMRA_4 +#ifndef PWM_TMRA_4_CONFIG +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_4_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_4 */ + +#ifdef BSP_USING_PWM_TMRA_5 +#ifndef PWM_TMRA_5_CONFIG +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_5_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_5 */ + +#ifdef BSP_USING_PWM_TMRA_6 +#ifndef PWM_TMRA_6_CONFIG +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_6_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_6 */ + +#ifdef BSP_USING_PWM_TMRA_7 +#ifndef PWM_TMRA_7_CONFIG +#define PWM_TMRA_7_CONFIG \ + { \ + .name = "pwm_a7", \ + .instance = CM_TMRA_7, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_7_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_7 */ + +#ifdef BSP_USING_PWM_TMRA_8 +#ifndef PWM_TMRA_8_CONFIG +#define PWM_TMRA_8_CONFIG \ + { \ + .name = "pwm_a8", \ + .instance = CM_TMRA_8, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_8_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_8 */ + +#endif /* BSP_USING_PWM_TMRA */ + +#ifdef BSP_USING_PWM_TMR4 + +#ifdef BSP_USING_PWM_TMR4_1 +#ifndef PWM_TMR4_1_CONFIG +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ + } +#endif /* PWM_TMR4_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_1 */ + +#ifdef BSP_USING_PWM_TMR4_2 +#ifndef PWM_TMR4_2_CONFIG +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ + } +#endif /* PWM_TMR4_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_2 */ + +#ifdef BSP_USING_PWM_TMR4_3 +#ifndef PWM_TMR4_3_CONFIG +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ + } +#endif /* PWM_TMR4_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_3 */ + +#endif /* BSP_USING_PWM_TMR4 */ + +#ifdef BSP_USING_PWM_TMR6 + +#ifdef BSP_USING_PWM_TMR6_1 +#ifndef PWM_TMR6_1_CONFIG +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_1 */ +#ifdef BSP_USING_PWM_TMR6_2 +#ifndef PWM_TMR6_2_CONFIG +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t62", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_2 */ +#ifdef BSP_USING_PWM_TMR6_3 +#ifndef PWM_TMR6_3_CONFIG +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t63", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_3 */ +#endif /* BSP_USING_PWM_TMR6 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_TMRA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/qspi_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/qspi_config.h new file mode 100644 index 00000000000..3f4bb0bd969 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/qspi_config.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ + } +#endif /* QSPI_BUS_CONFIG */ + +#ifndef QSPI_INIT_PARAMS +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ + } +#endif /* QSPI_INIT_PARAMS */ + +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ +#endif /* BSP_USING_SPI1 */ + +#ifdef __cplusplus +} +#endif + +#endif /*__QSPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/sdio_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/sdio_config.h new file mode 100644 index 00000000000..dc1a65afc04 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/sdio_config.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_SDIO1) +#ifndef SDIO1_BUS_CONFIG +#define SDIO1_BUS_CONFIG \ + { \ + .name = "sdio1", \ + .instance = CM_SDIOC1, \ + .clock = FCG1_PERIPH_SDIOC1, \ + .irq_config = { \ + .irq_num = BSP_SDIO1_IRQ_NUM, \ + .irq_prio = BSP_SDIO1_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC1_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO1_RX_DMA_INSTANCE, \ + .channel = SDIO1_RX_DMA_CHANNEL, \ + .clock = SDIO1_RX_DMA_CLOCK, \ + .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO1_TX_DMA_INSTANCE, \ + .channel = SDIO1_TX_DMA_CHANNEL, \ + .clock = SDIO1_TX_DMA_CLOCK, \ + .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAW, \ + }, \ + } +#endif /* SDIO1_BUS_CONFIG */ +#endif /* BSP_USING_SDIO1 */ + +#if defined(BSP_USING_SDIO2) +#ifndef SDIO2_BUS_CONFIG +#define SDIO2_BUS_CONFIG \ + { \ + .name = "sdio2", \ + .instance = CM_SDIOC2, \ + .clock = FCG1_PERIPH_SDIOC2, \ + .irq_config = { \ + .irq_num = BSP_SDIO2_IRQ_NUM, \ + .irq_prio = BSP_SDIO2_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC2_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO2_RX_DMA_INSTANCE, \ + .channel = SDIO2_RX_DMA_CHANNEL, \ + .clock = SDIO2_RX_DMA_CLOCK, \ + .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO2_TX_DMA_INSTANCE, \ + .channel = SDIO2_TX_DMA_CHANNEL, \ + .clock = SDIO2_TX_DMA_CLOCK, \ + .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAW, \ + }, \ + } +#endif /* SDIO2_BUS_CONFIG */ +#endif /* BSP_USING_SDIO2 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/spi_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/spi_config.h new file mode 100644 index 00000000000..5924c6cf971 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/spi_config.h @@ -0,0 +1,358 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = CM_SPI5, \ + .bus_name = "spi5", \ + .clock = FCG1_PERIPH_SPI5, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI5_SPEI, \ + }, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .clock = SPI5_TX_DMA_CLOCK, \ + .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPTI, \ + .flag = SPI5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .clock = SPI5_RX_DMA_CLOCK, \ + .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPRI, \ + .flag = SPI5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .Instance = CM_SPI6, \ + .bus_name = "spi6", \ + .clock = FCG1_PERIPH_SPI6, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI6_SPEI, \ + }, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .clock = SPI6_TX_DMA_CLOCK, \ + .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPTI, \ + .flag = SPI6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ + +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .clock = SPI6_RX_DMA_CLOCK, \ + .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPRI, \ + .flag = SPI6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/timer_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/timer_config.h new file mode 100644 index 00000000000..3b2cce5519b --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/timer_config.h @@ -0,0 +1,163 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __TMR_CONFIG_H__ +#define __TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_TMRA_1 +#ifndef TMRA_1_CONFIG +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ + } +#endif /* TMRA_1_CONFIG */ +#endif /* BSP_USING_TMRA_1 */ + +#ifdef BSP_USING_TMRA_2 +#ifndef TMRA_2_CONFIG +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ + } +#endif /* TMRA_2_CONFIG */ +#endif /* BSP_USING_TMRA_2 */ + +#ifdef BSP_USING_TMRA_3 +#ifndef TMRA_3_CONFIG +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ + } +#endif /* TMRA_3_CONFIG */ +#endif /* BSP_USING_TMRA_3 */ + +#ifdef BSP_USING_TMRA_4 +#ifndef TMRA_4_CONFIG +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ + } +#endif /* TMRA_4_CONFIG */ +#endif /* BSP_USING_TMRA_4 */ + +#ifdef BSP_USING_TMRA_5 +#ifndef TMRA_5_CONFIG +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ + } +#endif /* TMRA_5_CONFIG */ +#endif /* BSP_USING_TMRA_5 */ + +#ifdef BSP_USING_TMRA_6 +#ifndef TMRA_6_CONFIG +#define TMRA_6_CONFIG \ + { \ + .tmr_handle = CM_TMRA_6, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_6, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_6_OVF, \ + .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ + }, \ + .name = "tmra_6" \ + } +#endif /* TMRA_6_CONFIG */ +#endif /* BSP_USING_TMRA_6 */ + +#ifdef BSP_USING_TMRA_7 +#ifndef TMRA_7_CONFIG +#define TMRA_7_CONFIG \ + { \ + .tmr_handle = CM_TMRA_7, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_7, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_7_OVF, \ + .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ + }, \ + .name = "tmra_7" \ + } +#endif /* TMRA_7_CONFIG */ +#endif /* BSP_USING_TMRA_7 */ + +#ifdef BSP_USING_TMRA_8 +#ifndef TMRA_8_CONFIG +#define TMRA_8_CONFIG \ + { \ + .tmr_handle = CM_TMRA_8, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_8, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_8_OVF, \ + .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ + }, \ + .name = "tmra_8" \ + } +#endif /* TMRA_8_CONFIG */ +#endif /* BSP_USING_TMRA_8 */ +#endif /* __TMR_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/tmr_capture_config.h new file mode 100644 index 00000000000..af95cc6347e --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/tmr_capture_config.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __IC_CONFIG_H__ +#define __IC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +#define IC1_NAME "ic1" +#define INPUT_CAPTURE_CFG_TMR6_1 \ + { \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ + } +#endif + +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +#define IC2_NAME "ic2" +#define INPUT_CAPTURE_CFG_TMR6_2 \ + { \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ + } +#endif + +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) +#define IC3_NAME "ic3" +#define INPUT_CAPTURE_CFG_TMR6_3 \ + { \ + .name = IC3_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ + } +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/uart_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/uart_config.h new file mode 100644 index 00000000000..35ec13718cb --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/uart_config.h @@ -0,0 +1,594 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_RX_CONFIG */ + +#ifndef UART1_RXTO_CONFIG +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ + } +#endif /* UART1_RXTO_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#endif /* UART1_TX_CPLT_CONFIG */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_RX_CONFIG */ + +#ifndef UART2_RXTO_CONFIG +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ + } +#endif /* UART2_RXTO_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#endif /* UART2_TX_CPLT_CONFIG */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ + } +#endif /* UART3_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART3_TX_CPLT_CONFIG +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ + } +#endif +#endif /* UART3_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ + } +#endif /* UART4_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART4_TX_CPLT_CONFIG +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ + } +#endif +#endif /* UART4_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART5_RX_IRQ_NUM, \ + .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART5_TX_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TI, \ + }, \ + } +#endif /* UART5_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART5_TX_CPLT_CONFIG +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ + } +#endif +#endif /* UART5_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART6_RX_IRQ_NUM, \ + .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART6_TX_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TI, \ + }, \ + } +#endif /* UART6_CONFIG */ + +#if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_DMA_RX_CONFIG +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .channel = UART6_RX_DMA_CHANNEL, \ + .clock = UART6_RX_DMA_CLOCK, \ + .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_RI, \ + .flag = UART6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART6_RX_DMA_IRQn, \ + .irq_prio = UART6_RX_DMA_INT_PRIO, \ + .int_src = UART6_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_RX_CONFIG */ + +#ifndef UART6_RXTO_CONFIG +#define UART6_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RTO, \ + }, \ + } +#endif /* UART6_RXTO_CONFIG */ +#endif /* BSP_UART6_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#endif /* UART6_TX_CPLT_CONFIG */ + +#if defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_DMA_TX_CONFIG +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .channel = UART6_TX_DMA_CHANNEL, \ + .clock = UART6_TX_DMA_CLOCK, \ + .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_TI, \ + .flag = UART6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART6_TX_DMA_IRQn, \ + .irq_prio = UART6_TX_DMA_INT_PRIO, \ + .int_src = UART6_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_TX_CONFIG */ +#endif /* BSP_UART6_TX_USING_DMA */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#ifndef UART7_CONFIG +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = CM_USART7, \ + .clock = FCG3_PERIPH_USART7, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART7_RX_IRQ_NUM, \ + .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART7_TX_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TI, \ + }, \ + } +#endif /* UART7_CONFIG */ + +#if defined(BSP_UART7_RX_USING_DMA) +#ifndef UART7_DMA_RX_CONFIG +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .channel = UART7_RX_DMA_CHANNEL, \ + .clock = UART7_RX_DMA_CLOCK, \ + .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_RI, \ + .flag = UART7_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART7_RX_DMA_IRQn, \ + .irq_prio = UART7_RX_DMA_INT_PRIO, \ + .int_src = UART7_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_RX_CONFIG */ + +#ifndef UART7_RXTO_CONFIG +#define UART7_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RTO, \ + }, \ + } +#endif /* UART7_RXTO_CONFIG */ +#endif /* BSP_UART7_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ + } +#endif +#endif /* UART7_TX_CPLT_CONFIG */ + +#if defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_DMA_TX_CONFIG +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .channel = UART7_TX_DMA_CHANNEL, \ + .clock = UART7_TX_DMA_CLOCK, \ + .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART7_TX_DMA_IRQn, \ + .irq_prio = UART7_TX_DMA_INT_PRIO, \ + .int_src = UART7_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_TX_CONFIG */ +#endif /* BSP_UART7_TX_USING_DMA */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART10) +#ifndef UART10_CONFIG +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = CM_USART10, \ + .clock = FCG3_PERIPH_USART10, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART10_RX_IRQ_NUM, \ + .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART10_TX_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TI, \ + }, \ + } +#endif /* UART10_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART10_TX_CPLT_CONFIG +#define UART10_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TCI, \ + }, \ + } +#endif +#endif /* UART10_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART10 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_app_conf.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_app_conf.h new file mode 100644 index 00000000000..c140af44ffd --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_app_conf.h @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __USB_APP_CONF_H__ +#define __USB_APP_CONF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "rtconfig.h" + +/* USB MODE CONFIGURATION */ +/* +USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment +(1) If only defined USB_FS_MODE: + MCU USBFS core work in full speed using internal PHY. +(2) If only defined USB_HS_MODE: + MCU USBHS core work in full speed using internal PHY. +(3) If both defined USB_HS_MODE && USB_HS_EXTERNAL_PHY + MCU USBHS core work in high speed using external PHY. +(4) Other combination: + Not support, forbid!! +*/ + +#if defined(BSP_USING_USBHS) +#define USB_HS_MODE +#endif +#if defined(BSP_USING_USBFS) +#define USB_FS_MODE +#endif +#if !defined(BSP_USING_USBHS) && !defined(BSP_USING_USBFS) +#define USB_FS_MODE +#endif + +#if defined(BSP_USING_USBD) +#define USE_DEVICE_MODE +#endif +#if defined(BSP_USING_USBH) +#define USE_HOST_MODE +#endif +#if !defined(BSP_USING_USBD) && !defined(BSP_USING_USBH) +#define USE_DEVICE_MODE +#endif + +#if defined(USB_HS_MODE) && defined(BSP_USING_USBHS_PHY_EXTERN) +#define USB_HS_EXTERNAL_PHY +#endif + +#ifndef USB_HS_MODE +#ifndef USB_FS_MODE +#error "USB_HS_MODE or USB_FS_MODE should be defined" +#endif +#endif + +#ifndef USE_DEVICE_MODE +#ifndef USE_HOST_MODE +#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" +#endif +#endif + +#if defined(BSP_USING_USBD) +/* USB DEVICE FIFO CONFIGURATION */ +#ifdef USB_FS_MODE +#define RX_FIFO_FS_SIZE (128U) +#define TX0_FIFO_FS_SIZE (32U) +#define TX1_FIFO_FS_SIZE (32U) +#define TX2_FIFO_FS_SIZE (32U) +#define TX3_FIFO_FS_SIZE (32U) +#define TX4_FIFO_FS_SIZE (32U) +#define TX5_FIFO_FS_SIZE (32U) +#define TX6_FIFO_FS_SIZE (32U) +#define TX7_FIFO_FS_SIZE (32U) +#define TX8_FIFO_FS_SIZE (32U) +#define TX9_FIFO_FS_SIZE (32U) +#define TX10_FIFO_FS_SIZE (32U) +#define TX11_FIFO_FS_SIZE (32U) +#define TX12_FIFO_FS_SIZE (32U) +#define TX13_FIFO_FS_SIZE (32U) +#define TX14_FIFO_FS_SIZE (32U) +#define TX15_FIFO_FS_SIZE (32U) + +#if ((RX_FIFO_FS_SIZE + \ + TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ + TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ + TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \ + TX15_FIFO_FS_SIZE) > 640U) +#error "The USB max FIFO size is 640 x 4 Bytes!" +#endif +#endif + +#ifdef USB_HS_MODE +#define RX_FIFO_HS_SIZE (512U) +#define TX0_FIFO_HS_SIZE (64U) +#define TX1_FIFO_HS_SIZE (64U) +#define TX2_FIFO_HS_SIZE (64U) +#define TX3_FIFO_HS_SIZE (64U) +#define TX4_FIFO_HS_SIZE (64U) +#define TX5_FIFO_HS_SIZE (64U) +#define TX6_FIFO_HS_SIZE (64U) +#define TX7_FIFO_HS_SIZE (64U) +#define TX8_FIFO_HS_SIZE (64U) +#define TX9_FIFO_HS_SIZE (64U) +#define TX10_FIFO_HS_SIZE (64U) +#define TX11_FIFO_HS_SIZE (64U) +#define TX12_FIFO_HS_SIZE (64U) +#define TX13_FIFO_HS_SIZE (64U) +#define TX14_FIFO_HS_SIZE (64U) +#define TX15_FIFO_HS_SIZE (64U) + +#if ((RX_FIFO_HS_SIZE + \ + TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ + TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ + TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \ + TX15_FIFO_HS_SIZE) > 2048U) +#error "The USB max FIFO size is 2048 x 4 Bytes!" +#endif +#endif + +#if defined(BSP_USING_USBD_VBUS_SENSING) +#define VBUS_SENSING_ENABLED +#endif +#endif + +#if defined(BSP_USING_USBH) +/* USB HOST FIFO CONFIGURATION */ +#ifdef USB_FS_MODE +#define RX_FIFO_FS_SIZE (128U) +#define TXH_NP_FS_FIFOSIZ (32U) +#define TXH_P_FS_FIFOSIZ (64U) + +#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U) +#error "The USB max FIFO size is 640 x 4 Bytes!" +#endif +#endif + +#ifdef USB_HS_MODE +#define RX_FIFO_HS_SIZE (512U) +#define TXH_NP_HS_FIFOSIZ (128U) +#define TXH_P_HS_FIFOSIZ (256U) + +#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U) +#error "The USB max FIFO size is 2048 x 4 Bytes!" +#endif +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_APP_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_bsp.h b/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_bsp.h new file mode 100644 index 00000000000..8efeff9b9ac --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/config/usb_config/usb_bsp.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __USB_BSP_H__ +#define __USB_BSP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "hc32_ll_utility.h" + +extern void usb_udelay(const uint32_t usec); +extern void usb_mdelay(const uint32_t msec); + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_BSP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/drv_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/drv_config.h new file mode 100644 index 00000000000..f938db9bcfe --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/drv_config.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dma_config.h" +#include "uart_config.h" +#include "spi_config.h" +#include "adc_config.h" +#include "dac_config.h" +#include "gpio_config.h" +#include "eth_config.h" +#include "can_config.h" +#include "sdio_config.h" +#include "pm_config.h" +#include "i2c_config.h" +#include "qspi_config.h" +#include "pulse_encoder_config.h" +#include "timer_config.h" +#include "tmr_capture_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f467_lqfp144/board/hc32f4xx_conf.h new file mode 100644 index 00000000000..1b7f563ce02 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/hc32f4xx_conf.h @@ -0,0 +1,171 @@ +/** + ******************************************************************************* + * @file hc32f4xx_conf.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2026-06-03 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_CONF_H__ +#define __HC32F4XX_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_ON) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_DMC_ENABLE (DDL_ON) +#define LL_DVP_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_ETH_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_ON) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_NFC_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F467_LQFP144 (12U) + +/** + * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to 0U. + */ +#define BSP_EV_HC32F4XX (BSP_EV_HC32F467_LQFP144) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to DDL_ON. + */ +#define BSP_24CXX_ENABLE (DDL_ON) +#define BSP_IS62WV51216_ENABLE (DDL_ON) +#define BSP_MT29F2G08AB_ENABLE (DDL_ON) +#define BSP_NT35510_ENABLE (DDL_ON) +#define BSP_OV5640_ENABLE (DDL_ON) +#define BSP_RTL8201_ENABLE (DDL_ON) +#define BSP_TCA9539_ENABLE (DDL_ON) +#define BSP_W25QXX_ENABLE (DDL_ON) +#define BSP_W9825G6KH_ENABLE (DDL_ON) +#define BSP_WM8988_ENABLE (DDL_ON) +#define BSP_XPT20XX_ENABLE (DDL_ON) + +/** + * @brief Ethernet Configuration. + */ +/* MAC ADDRESS */ +#define ETH_MAC_ADDR0 (0x02U) +#define ETH_MAC_ADDR1 (0x00U) +#define ETH_MAC_ADDR2 (0x00U) +#define ETH_MAC_ADDR3 (0x00U) +#define ETH_MAC_ADDR4 (0x00U) +#define ETH_MAC_ADDR5 (0x00U) + +#if defined(ETH_PHY_USING_RTL8201F) +/* PHY(RTL8201F) Address*/ +#define ETH_PHY_ADDR (0x01U) + +/* PHY Status Register */ +#define PHY_SR (0x00U) /*!< PHY status register */ +#define PHY_DUPLEX_STATUS (0x0100U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS (0x2000U) /*!< PHY Speed mask */ + +#endif + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.icf new file mode 100644 index 00000000000..182f74abf29 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.icf @@ -0,0 +1,51 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$/config/ide/IcfEditor/cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x000FFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x2005FFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.ld new file mode 100644 index 00000000000..fae84a731ff --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.ld @@ -0,0 +1,229 @@ +/****************************************************************************** + * Copyright (C) 2022-2025, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F467xG.ld */ +/* Abstract Linker script for HC32F467 Device with */ +/* 1MByte FLASH, 516KByte RAM */ +/* Version V1.0 */ +/* Date 2024-05-31 */ +/*****************************************************************************/ +/* OTP section(data sections are not flash multiplexed region) implementation. + You need to pay attention to the size of the specified OTP block. + Take two OTP blocks for example. */ +__OTP_DATA_BASE = 0x03000000; +__OTP_LOCK_BASE = 0x03001800; +/* OTP block 16 */ +__OTP_DATA_B16_START = 0x03000000; +__OTP_LOCK_B16_START = 0x03001840; +__OTP_DATA_B16_OFFSET = __OTP_DATA_B16_START - __OTP_DATA_BASE; +__OTP_LOCK_B16_OFFSET = __OTP_LOCK_B16_START - __OTP_LOCK_BASE; +/* OTP block 17 */ +__OTP_DATA_B17_START = 0x03000800; +__OTP_LOCK_B17_START = 0x03001844; +__OTP_DATA_B17_OFFSET = __OTP_DATA_B17_START - __OTP_DATA_BASE; +__OTP_LOCK_B17_OFFSET = __OTP_LOCK_B17_START - __OTP_LOCK_BASE; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 1M + OTP_DATA (rx): ORIGIN = 0x03000000, LENGTH = 6K + OTP_LOCK (rx): ORIGIN = 0x03001800, LENGTH = 728 + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data : + { + . = ALIGN(4); + . = ORIGIN(OTP_DATA) + __OTP_DATA_B16_OFFSET; + KEEP(*(.otp_b16_data*)) + . = ORIGIN(OTP_DATA) + __OTP_DATA_B17_OFFSET; + KEEP(*(.otp_b17_data*)) + . = ALIGN(4); + } >OTP_DATA + + .otp_lock : + { + . = ALIGN(4); + . = ORIGIN(OTP_LOCK) + __OTP_LOCK_B16_OFFSET; + KEEP(*(.otp_b16_lock*)) + . = ORIGIN(OTP_LOCK) + __OTP_LOCK_B17_OFFSET; + KEEP(*(.otp_b17_lock*)) + . = ALIGN(4); + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + .bss (NOLOAD): + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + . = ALIGN(4); + *(.noinit*) + . = ALIGN(4); + } >RAM + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.sct b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.sct new file mode 100644 index 00000000000..eaa6131f073 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/linker_scripts/link.sct @@ -0,0 +1,22 @@ +; **************************************************************** +; Scatter-Loading Description File +; **************************************************************** +LR_IROM1 0x00000000 0x00100000 { ; load region size_region + ER_IROM1 0x00000000 0x00100000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFE0000 UNINIT 0x00000008 { ; RW data + *(.bss.noinit) + } + RW_IRAM2 0x1FFE0008 0x0007FFF8 { ; RW data + .ANY (+RW +ZI) + .ANY (RAMCODE) + } + RW_IRAMB 0x200F0000 0x00001000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/fal_cfg.h new file mode 100644 index 00000000000..70e23ae31b5 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/fal_cfg.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +/* enable hc32f4 onchip flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_HC32F4 +/* enable SFUD flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_SFUD + +extern const struct fal_flash_dev hc32_onchip_flash; +extern struct fal_flash_dev ext_nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ + { \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ + } + +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, HC32_FLASH_SIZE, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \ + } +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/ports/nand_port.h b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/nand_port.h new file mode 100644 index 00000000000..feb919a12a3 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/nand_port.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-03-01 CDT first version + */ + +#ifndef __NAND_PORT_H__ +#define __NAND_PORT_H__ + +/******************** NAND chip information ***********************************/ +#define NAND_BYTES_PER_PAGE 2048UL +#define NAND_SPARE_AREA_SIZE 64UL +#define NAND_PAGES_PER_BLOCK 64UL +#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) +#define NAND_BLOCKS_PER_PLANE 1024UL +#define NAND_PLANE_PER_DEVICE 2UL +#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) +#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) + +/******************** EXMC_NFC configure **************************************/ +/* chip: EXMC_NFC_BANK0~7 */ +#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK1 + +/* density:2Gbit */ +#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT + +/* device width: 8-bit */ +#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT + +/* BankNum: 2BANKS */ +#define NAND_EXMC_NFC_BANK_NUMBER EXMC_NFC_2BANKS + +/* page size: 2KByte */ +#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE + +/* row address cycle: 3 */ +#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE + +/* ECC mode */ +#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC + +/* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */ +/* TS: ALE/CLE/CE setup time(min=10ns) */ +#define NAND_TS 1U + +/* TWP: WE# pulse width (min=10ns) */ +#define NAND_TWP 1U + +/* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */ +#define NAND_TRP 2U + +/* TTH: ALE/CLE/CE hold time (min=5ns) */ +#define NAND_TH 1U + +/* TWH: WE# pulse width HIGH (min=10ns) */ +#define NAND_TWH 1U + +/* TRH: RE# pulse width HIGH (min=7ns) */ +#define NAND_TRH 1U + +/* TRR: Ready to RE# LOW (min=20ns) */ +#define NAND_TRR 2U + +/* TWB: WE# HIGH to busy (max=100ns) */ +#define NAND_TWB 1U + +/* TWB: WE# HIGH to busy (max=100ns) */ +#define NAND_TRB 1U + +/* TCCS: Change read column and Change write column delay */ +#define NAND_TCCS 5U + +/* TWTR: WE# HIGH to RE# LOW (min=60ns) */ +#define NAND_TWTR 4U + +/* TRTW: RE# HIGH to WE# LOW (min=100ns) */ +#define NAND_TRTW 7U + +/* TADL: ALE to data start (min=70ns) */ +#define NAND_TADL 5U + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/ports/sdram_port.h b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/sdram_port.h new file mode 100644 index 00000000000..d7b1d670fa2 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/sdram_port.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2023-02-24 CDT first version + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +/* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */ +#define SDRAM_CHIP EXMC_DMC_CHIP0 +/* bank address */ +#define SDRAM_BANK_ADDR (0x80000000UL) +/* size(kbyte):8MB = 8*1024*1KBytes */ +#define SDRAM_SIZE (32UL * 1024UL * 1024UL) +/* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */ +#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 +/* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */ +#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT +/* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */ +#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM9 +/* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */ +#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM13 +/* cas latency clock number: 2, 3 */ +#define SDRAM_CAS_LATENCY 2UL +/* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */ +#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT + +/* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */ +#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD +/* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */ +#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL +/* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */ +#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED + +/* timing configuration(EXCLK clock frequency: 30MHz) for W9825G6KH*/ +/* refresh rate counter (EXCLK clock) */ +#define SDRAM_REFRESH_COUNT (450U) +/* TMDR: mode register command time (EXCLK clock) */ +#define SDRAM_TMDR 2U +/* TRAS: RAS to precharge delay time (EXCLK clock) */ +#define SDRAM_TRAS 2U +/* TRC: active bank x to active bank x delay time (EXCLK clock) */ +#define SDRAM_TRC 2U +/* TRCD: RAS to CAS minimum delay time (EXCLK clock) */ +#define SDRAM_TRCD_B 3U +#define SDRAM_TRCD_P 0U +/* TRFC: autorefresh command time (EXCLK clock) */ +#define SDRAM_TRFC_B 3U +#define SDRAM_TRFC_P 0U +/* TRP: precharge to RAS delay time (EXCLK clock) */ +#define SDRAM_TRP_B 3U +#define SDRAM_TRP_P 0U +/* TRRD: active bank x to active bank y delay time (EXCLK clock) */ +#define SDRAM_TRRD 1U +/* TWR: write to precharge delay time (EXCLK clock). */ +#define SDRAM_TWR 2U +/* TWTR: write to read delay time (EXCLK clock). */ +#define SDRAM_TWTR 1U +/* TXP: exit power-down command time (EXCLK clock). */ +#define SDRAM_TXP 1U +/* TXSR: exit self-refresh command time (EXCLK clock). */ +#define SDRAM_TXSR 5U +/* TESR: self-refresh command time (EXCLK clock). */ +#define SDRAM_TESR 5U + +/* memory mode register */ +#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) +#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) +#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) +#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) +#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) +#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/tca9539_port.h new file mode 100644 index 00000000000..c30841b77bc --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/tca9539_port.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2022-04-28 CDT first version + */ + +#ifndef __TCA9539_PORT_H__ +#define __TCA9539_PORT_H__ + +#include "tca9539.h" + +/** + * @defgroup HC32F467_EV_IO_Function_Sel Expand IO function definition + * @{ + */ +#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ +#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ +#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ +#define EIO_CAM_RST (TCA9539_IO_PIN3) /* Camera module reset, output */ +#define EIO_LCD_BKL (TCA9539_IO_PIN4) /* LCD back-light, output */ +#define EIO_CAM_STB (TCA9539_IO_PIN5) /* Camera module standby, output */ +#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ + +#define EIO_SDIO1_CD (TCA9539_IO_PIN0) /* SDIO1 card detect, input */ +#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */ +#define EIO_LIN_SLEEP (TCA9539_IO_PIN2) /* LIN PHY sleep, output */ +#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ +#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +/** + * @} + */ + +/** + * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition + * @{ + */ +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) +/** + * @} + */ + +/** + * @defgroup BSP CAN PHY STB port/pin definition + * @{ + */ +#define CAN_STB_PORT (TCA9539_IO_PORT1) +#define CAN_STB_PIN (EIO_CAN_STB) +/** + * @} + */ +/** + * @defgroup BSP_ETH_PortPin_Sel BSP ETH port/pin definition + * @{ + */ +#define ETH_RST_PORT (TCA9539_IO_PORT1) +#define ETH_RST_PIN (EIO_ETH_RST) +/** + * @} + */ +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/board/ports/usb_config.h b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/usb_config.h new file mode 100644 index 00000000000..e0640196076 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/board/ports/usb_config.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-03 CDT first version + */ + +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +/* ================ USB common Configuration ================ */ + +#ifdef __RTTHREAD__ +#include + +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else +#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#endif + +#ifndef CONFIG_USB_DBG_LEVEL +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +// #define CONFIG_USB_DCACHE_ENABLE + +/* data align size when use dma or use dcache */ +#ifdef CONFIG_USB_DCACHE_ENABLE +#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#else +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* use usb_memcpy default for high performance but cost more flash memory. + * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. +*/ +// #define CONFIG_USB_MEMCPY_DISABLE + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +/* enable advance desc register api */ +#define CONFIG_USBDEV_ADVANCE_DESC + +/* move ep0 setup handler from isr to thread */ +// #define CONFIG_USBDEV_EP0_THREAD + +#ifndef CONFIG_USBDEV_EP0_PRIO +#define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE +#define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE +#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS +#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME +#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#endif + +#define CONFIG_USBDEV_MTP_THREAD + +#ifndef CONFIG_USBDEV_MTP_PRIO +#define CONFIG_USBDEV_MTP_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MTP_STACKSIZE +#define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP +#define CONFIG_USBDEV_CDC_ECM_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +// #define CONFIG_USBDEV_SOF_ENABLE + +/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, + * the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. + * +*/ +//#define CONFIG_USB_HS + +/* ---------------- DWC2 Configuration ---------------- */ +/* enable dwc2 buffer dma mode for device +*/ +// #define CONFIG_USB_DWC2_DMA_ENABLE + +/* Defined FS Core device FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE (32) + +/* Defined FS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) + +/* Defined FS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (640) + +/* Defined HS Core Device FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE (1024) +#define CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE (0) + +/* Defined HS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE (512) +#define CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE (256) + +/* Defined HS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE (2048) + + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f467_lqfp144/bsp_compile_ci.bat new file mode 100644 index 00000000000..769eb4440a6 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/bsp_compile_ci.bat @@ -0,0 +1,127 @@ +scons --attach=devices.adc +scons -j4 +scons --attach=default + +scons --attach=devices.can +scons -j4 +scons --attach=default + +scons --attach=devices.crypto +scons -j4 +scons --attach=default + +scons --attach=devices.dac +scons -j4 +scons --attach=default + +scons --attach=devices.flash +scons -j4 +scons --attach=default + +scons --attach=devices.gpio +scons -j4 +scons --attach=default + +scons --attach=devices.clock_timer +scons -j4 +scons --attach=default + +scons --attach=devices.i2c +scons -j4 +scons --attach=default + +scons --attach=devices.input_capture +scons -j4 +scons --attach=default + +scons --attach=devices.pm +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr4 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.qspi +scons -j4 +scons --attach=default + +scons --attach=devices.rtc +scons -j4 +scons --attach=default + +scons --attach=devices.sdio +scons -j4 +scons --attach=default + +scons --attach=devices.soft_i2c +scons -j4 +scons --attach=default + +scons --attach=devices.spi +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v1 +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v2 +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_host +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_device +scons -j4 +scons --attach=default + +scons --attach=devices.usb_fs_host +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_swdt +scons -j4 +scons --attach=default + +scons --attach=devices.watchdog_wdt +scons -j4 +scons --attach=default + +scons --attach=peripheral.eth_rmii +scons -j4 +scons --attach=default + +scons --attach=peripheral.exmc_nand +scons -j4 +scons --attach=default + +scons --attach=peripheral.exmc_sdram +scons -j4 +scons --attach=default + +scons --attach=peripheral.spi_flash +scons -j4 +scons --attach=default diff --git a/bsp/hc32/ev_hc32f467_lqfp144/figures/board.jpg b/bsp/hc32/ev_hc32f467_lqfp144/figures/board.jpg new file mode 100644 index 00000000000..b6f6aa49b49 Binary files /dev/null and b/bsp/hc32/ev_hc32f467_lqfp144/figures/board.jpg differ diff --git a/bsp/hc32/ev_hc32f467_lqfp144/jlink/ev_hc32f467_lqfp144 Debug.launch b/bsp/hc32/ev_hc32f467_lqfp144/jlink/ev_hc32f467_lqfp144 Debug.launch new file mode 100644 index 00000000000..da92a552501 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/jlink/ev_hc32f467_lqfp144 Debug.launch @@ -0,0 +1,80 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/project.ewd b/bsp/hc32/ev_hc32f467_lqfp144/project.ewd new file mode 100644 index 00000000000..f3a41f97b9d --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/project.ewd @@ -0,0 +1,2974 @@ + + + 3 + + Debug + + ARM + + 0 + + C-SPY + 2 + + 32 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + CADI_ID + 2 + + 0 + 1 + 0 + + + + + + + + + CMSISDAP_ID + 2 + + 4 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F467_1M -FS00 -FL0100000 -FP0($$Device:HC32F467RGTI$FlashARM/HC32F467_1M.FLM) -FF1HC32F467_otp -FS13000000 -FL11800 -FP1($$Device:HC32F467RGTI$FlashARM/HC32F467_otp.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/project.uvprojx b/bsp/hc32/ev_hc32f467_lqfp144/project.uvprojx new file mode 100644 index 00000000000..4813c20acbc --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/project.uvprojx @@ -0,0 +1,1384 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + 0 + + + HC32F467RGTI + HDSC + HDSC.HC32F467.1.0.2 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM1(0x00000000,0x100000) IROM2(0x03000000,0x1800) IRAM1(0x1FFE0000,0x80000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE + + + CMSIS_AGDI(-S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F467_1M -FS00 -FL0100000 -FP0($$Device:HC32F467RGTI$FlashARM/HC32F467_1M.FLM) -FF1HC32F467_otp -FS13000000 -FL11800 -FP1($$Device:HC32F467RGTI$FlashARM/HC32F467_otp.FLM)) + 0 + $$Device:HC32F467RGTI$Device\Include\HC32F467RGTI.h + + + + + + + + + + ./packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f467/Source/ARM/sfr/HC32F467.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFE0000 + 0x80000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x03000000 + 0x1800 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFE0000 + 0x80000 + + + 0 + 0x200F0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + RT_USING_LIBC, __RTTHREAD__, __DEBUG, RT_USING_ARMLIBC, HC32F467, USE_DDL_DRIVER, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND + + ..\..\..\include;board\ports;.;packages\hc32-f4-series-latest\hc32f467\inc;..\..\..\components\libc\compilers\common\include;..\..\..\components\net\utest;..\..\..\components\drivers\include;board;..\platform\tca9539;packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f467\Include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m4;board\config\usb_config;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\components\drivers\phy;..\..\..\components\libc\posix\io\eventfd;..\libraries\hc32_drivers;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board\config;..\..\..\components\libc\posix\io\epoll;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;packages\hc32-f4-cmsis-latest\Include;applications;..\..\..\components\drivers\smp_call;..\..\..\libcpu\arm\common + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFE0000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + xtal32_fcm.c + 1 + applications\xtal32_fcm.c + + + + + CPU + + + atomic_arm.c + 1 + ..\..\..\libcpu\arm\common\atomic_arm.c + + + + + div0.c + 1 + ..\..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\..\libcpu\arm\common\showmem.c + + + + + context_rvds.S + 2 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + cpuport.c + 1 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + DeviceDrivers + + + device.c + 1 + ..\..\..\components\drivers\core\device.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dev_i2c_bit_ops.c + 1 + ..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dev_i2c_core.c + 1 + ..\..\..\components\drivers\i2c\dev_i2c_core.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dev_i2c_dev.c + 1 + ..\..\..\components\drivers\i2c\dev_i2c_dev.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + completion_comm.c + 1 + ..\..\..\components\drivers\ipc\completion_comm.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + completion_up.c + 1 + ..\..\..\components\drivers\ipc\completion_up.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + condvar.c + 1 + ..\..\..\components\drivers\ipc\condvar.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dataqueue.c + 1 + ..\..\..\components\drivers\ipc\dataqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + pipe.c + 1 + ..\..\..\components\drivers\ipc\pipe.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + ringblk_buf.c + 1 + ..\..\..\components\drivers\ipc\ringblk_buf.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + ringbuffer.c + 1 + ..\..\..\components\drivers\ipc\ringbuffer.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + waitqueue.c + 1 + ..\..\..\components\drivers\ipc\waitqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + workqueue.c + 1 + ..\..\..\components\drivers\ipc\workqueue.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + rt_inputcapture.c + 1 + ..\..\..\components\drivers\misc\rt_inputcapture.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dev_pin.c + 1 + ..\..\..\components\drivers\pin\dev_pin.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + dev_serial.c + 1 + ..\..\..\components\drivers\serial\dev_serial.c + + + + + + __RT_IPC_SOURCE__ + + + + + + + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + board_config.c + 1 + board\board_config.c + + + + + drv_common.c + 1 + ..\libraries\hc32_drivers\drv_common.c + + + + + drv_gpio.c + 1 + ..\libraries\hc32_drivers\drv_gpio.c + + + + + drv_i2c.c + 1 + ..\libraries\hc32_drivers\drv_i2c.c + + + + + drv_irq.c + 1 + ..\libraries\hc32_drivers\drv_irq.c + + + + + drv_soft_i2c.c + 1 + ..\libraries\hc32_drivers\drv_soft_i2c.c + + + + + drv_tmr_capture.c + 1 + ..\libraries\hc32_drivers\drv_tmr_capture.c + + + + + drv_usart.c + 1 + ..\libraries\hc32_drivers\drv_usart.c + + + + + Finsh + + + shell.c + 1 + ..\..\..\components\finsh\shell.c + + + + + msh.c + 1 + ..\..\..\components\finsh\msh.c + + + + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + + + + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + + + + + HC32F467-LL + + + hc32_ll.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll.c + + + + + hc32_ll_aos.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_aos.c + + + + + hc32_ll_clk.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_clk.c + + + + + hc32_ll_dma.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_dma.c + + + + + hc32_ll_efm.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_efm.c + + + + + hc32_ll_fcg.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_fcg.c + + + + + hc32_ll_gpio.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_gpio.c + + + + + hc32_ll_icg.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_icg.c + + + + + hc32_ll_interrupts.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_interrupts.c + + + + + hc32_ll_pwc.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_pwc.c + + + + + hc32_ll_rmu.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_rmu.c + + + + + hc32_ll_sram.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_sram.c + + + + + hc32_ll_utility.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_utility.c + + + + + hc32f467_ll_interrupts_share.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32f467_ll_interrupts_share.c + + + + + hc32_ll_usart.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_usart.c + + + + + hc32_ll_tmr0.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_tmr0.c + + + + + hc32_ll_i2c.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_i2c.c + + + + + hc32_ll_tmr6.c + 1 + packages\hc32-f4-series-latest\hc32f467\src\hc32_ll_tmr6.c + + + + + Kernel + + + clock.c + 1 + ..\..\..\src\clock.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + components.c + 1 + ..\..\..\src\components.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + cpu_up.c + 1 + ..\..\..\src\cpu_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + defunct.c + 1 + ..\..\..\src\defunct.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + idle.c + 1 + ..\..\..\src\idle.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + ipc.c + 1 + ..\..\..\src\ipc.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + irq.c + 1 + ..\..\..\src\irq.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + kservice.c + 1 + ..\..\..\src\kservice.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mem.c + 1 + ..\..\..\src\mem.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + mempool.c + 1 + ..\..\..\src\mempool.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + object.c + 1 + ..\..\..\src\object.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_comm.c + 1 + ..\..\..\src\scheduler_comm.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + scheduler_up.c + 1 + ..\..\..\src\scheduler_up.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + thread.c + 1 + ..\..\..\src\thread.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + timer.c + 1 + ..\..\..\src\timer.c + + + + + + __RT_KERNEL_SOURCE__ + + + + + + + + + + + Libc + + + syscall_mem.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + + + + + syscalls.c + 1 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + + + + + cctype.c + 1 + ..\..\..\components\libc\compilers\common\cctype.c + + + + + cstdlib.c + 1 + ..\..\..\components\libc\compilers\common\cstdlib.c + + + + + cstring.c + 1 + ..\..\..\components\libc\compilers\common\cstring.c + + + + + ctime.c + 1 + ..\..\..\components\libc\compilers\common\ctime.c + + + + + cunistd.c + 1 + ..\..\..\components\libc\compilers\common\cunistd.c + + + + + cwchar.c + 1 + ..\..\..\components\libc\compilers\common\cwchar.c + + + + + kerrno.c + 1 + ..\..\..\src\klibc\kerrno.c + + + + + kstdio.c + 1 + ..\..\..\src\klibc\kstdio.c + + + + + kstring.c + 1 + ..\..\..\src\klibc\kstring.c + + + + + rt_vsnprintf_tiny.c + 1 + ..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + + + Libraries + + + system_hc32f467.c + 1 + packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f467\Source\system_hc32f467.c + + + + + startup_hc32f467.s + 2 + packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f467\Source\ARM\startup_hc32f467.s + + + + + Platform + + + tca9539.c + 1 + ..\platform\tca9539\tca9539.c + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.h b/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.h new file mode 100644 index 00000000000..bfe181689b6 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.h @@ -0,0 +1,448 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 24 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart7" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define ARCH_USING_HW_ATOMIC_8 +#define ARCH_USING_HW_ATOMIC_16 +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_INPUT_CAPTURE +#define RT_INPUT_CAPTURE_RB_SIZE 100 +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +#define PKG_USING_HC32F4_CMSIS_DRIVER +#define PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_HC32F4_SERIES_DRIVER +#define PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_HC32 +#define SOC_SERIES_HC32F4 + +/* Hardware Drivers Config */ + +#define SOC_HC32F467RG + +/* On-chip Drivers */ + +#define BSP_USING_ON_CHIP_FLASH_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH +/* end of On-chip Drivers */ + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_TCA9539 +#define BSP_USING_EXT_IO +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART7 +#define BSP_USING_I2C +#define BSP_USING_I2C_HW +#define BSP_USING_I2C1 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.py b/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.py new file mode 100644 index 00000000000..0af49fd02b7 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + else: + EXEC_PATH = r'C:/Users/XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/hc32/ev_hc32f467_lqfp144/template.ewp b/bsp/hc32/ev_hc32f467_lqfp144/template.ewp new file mode 100644 index 00000000000..8e80bf1aec4 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/template.ewp @@ -0,0 +1,1927 @@ + + + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/template.eww b/bsp/hc32/ev_hc32f467_lqfp144/template.eww new file mode 100644 index 00000000000..c62178f07a5 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/template.uvoptx b/bsp/hc32/ev_hc32f467_lqfp144/template.uvoptx new file mode 100644 index 00000000000..8f16129428e --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/template.uvoptx @@ -0,0 +1,179 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"" -O206 -S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F467_1M -FS00 -FL0100000 -FP0($$Device:HC32F467RGTI$FlashARM/HC32F467_1M.FLM) -FF1HC32F467_otp -FS13000000 -FL11800 -FP1($$Device:HC32F467RGTI$FlashARM/HC32F467_otp.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f467_lqfp144/template.uvprojx b/bsp/hc32/ev_hc32f467_lqfp144/template.uvprojx new file mode 100644 index 00000000000..49e82b81f04 --- /dev/null +++ b/bsp/hc32/ev_hc32f467_lqfp144/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + 0 + + + HC32F467RGTI + HDSC + HDSC.HC32F467.1.0.2 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM1(0x00000000,0x100000) IROM2(0x03000000,0x1800) IRAM1(0x1FFE0000,0x80000) IRAM2(0x200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(8000000) ESEL ELITTLE + + + CMSIS_AGDI(-S0 -C0 -P00 -FO15 -FD1FFE0000 -FC4000 -FN2 -FF0HC32F467_1M -FS00 -FL0100000 -FP0($$Device:HC32F467RGTI$FlashARM/HC32F467_1M.FLM) -FF1HC32F467_otp -FS13000000 -FL11800 -FP1($$Device:HC32F467RGTI$FlashARM/HC32F467_otp.FLM)) + 0 + $$Device:HC32F467RGTI$Device\Include\HC32F467RGTI.h + + + + + + + + + + ./packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f467/Source/ARM/sfr/HC32F467.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFE0000 + 0x80000 + + + 1 + 0x0 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x100000 + + + 1 + 0x03000000 + 0x1800 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFE0000 + 0x80000 + + + 0 + 0x200F0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFE0000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml index 7ec37e6f4a7..a4c0a565b39 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f472_lqfp100/.ci/attachconfig/ci.attachconfig.yml @@ -29,11 +29,11 @@ devices.flash: - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SFUD=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f472_lqfp100/.config b/bsp/hc32/ev_hc32f472_lqfp100/.config index 7d500ddc0fd..0c3f6768347 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/.config +++ b/bsp/hc32/ev_hc32f472_lqfp100/.config @@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 # CONFIG_RT_USING_TIMER_SOFT is not set # CONFIG_RT_USING_CPU_USAGE_TRACER is not set diff --git a/bsp/hc32/ev_hc32f472_lqfp100/README.md b/bsp/hc32/ev_hc32f472_lqfp100/README.md index a348e2a89e6..2eab4ce544c 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/README.md +++ b/bsp/hc32/ev_hc32f472_lqfp100/README.md @@ -48,7 +48,7 @@ EV_F472_LQ100 开发板常用 **板载资源** 如下： | DAC | 支持 | | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1... PF8 ---> PIN：0，1...89 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | PM | 支持 | | diff --git a/bsp/hc32/ev_hc32f472_lqfp100/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f472_lqfp100/applications/xtal32_fcm.c index 0e356713230..a189bed9b8b 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/applications/xtal32_fcm.c +++ b/bsp/hc32/ev_hc32f472_lqfp100/applications/xtal32_fcm.c @@ -19,7 +19,7 @@ #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) -#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) /** * @brief This thread is used to monitor whether XTAL32 is stable. @@ -36,13 +36,13 @@ void xtal32_fcm_thread_entry(void *parameter) /* FCM config */ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); (void)FCM_StructInit(&stcFcmInit); - stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; - stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ - stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; - stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; - stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); - stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); (void)FCM_Init(&stcFcmInit); /* Enable FCM, to ensure xtal32 stable */ FCM_Cmd(ENABLE); diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig b/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig index 0c31a20cd01..965ab1b51b4 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/Kconfig @@ -704,27 +704,27 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_CLOCK_TIMER - bool "Enable Hw Timer" + bool "Enable Clock Timer" default n select RT_USING_CLOCK_TIME if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 - bool "Use Timer_a1 As The Hw Timer" + bool "Use Timer_a1 As The Clock Timer" default n config BSP_USING_TMRA_2 - bool "Use Timer_a2 As The Hw Timer" + bool "Use Timer_a2 As The Clock Timer" default n config BSP_USING_TMRA_3 - bool "Use Timer_a3 As The Hw Timer" + bool "Use Timer_a3 As The Clock Timer" default n config BSP_USING_TMRA_4 - bool "Use Timer_a4 As The Hw Timer" + bool "Use Timer_a4 As The Clock Timer" default n config BSP_USING_TMRA_5 - bool "Use Timer_a5 As The Hw Timer" + bool "Use Timer_a5 As The Clock Timer" default n config BSP_USING_TMRA_6 - bool "Use Timer_a6 As The Hw Timer" + bool "Use Timer_a6 As The Clock Timer" default n endif diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board.c b/bsp/hc32/ev_hc32f472_lqfp100/board/board.c index 2a65b3ac58c..350e7b3bf9f 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/board.c +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board.c @@ -14,9 +14,9 @@ #include "board_config.h" /* unlock/lock peripheral */ -#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ - LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) -#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG) +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG) /** System Base Configuration */ @@ -56,9 +56,9 @@ void SystemClock_Config(void) GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); (void)CLK_XtalStructInit(&stcXtalInit); /* Config Xtal and enable Xtal */ - stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; - stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; - stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; (void)CLK_XtalInit(&stcXtalInit); @@ -84,8 +84,8 @@ void SystemClock_Config(void) /* Xtal32 config */ GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); (void)CLK_Xtal32StructInit(&stcXtal32Init); - stcXtal32Init.u8State = CLK_XTAL32_ON; - stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; (void)CLK_Xtal32Init(&stcXtal32Init); #endif diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board.h b/bsp/hc32/ev_hc32f472_lqfp100/board/board.h index c38550b4c2f..be3095cc4cb 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/board.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board.h @@ -21,27 +21,27 @@ extern "C" { #endif -#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) -#define HC32_FLASH_WRITE_GRANULARITY (4) -#define HC32_FLASH_SIZE (512 * 1024) -#define HC32_FLASH_START_ADDRESS (0) -#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) +#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (512 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) -#define HC32_SRAM_SIZE (64) -#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024) +#define HC32_SRAM_SIZE (64) +#define HC32_SRAM_END (0x1FFF8000 + HC32_SRAM_SIZE * 1024) #ifdef __ARMCC_VERSION extern int Image$$RW_IRAM2$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) #elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) #else extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) +#define HEAP_BEGIN (&__bss_end) #endif -#define HEAP_END HC32_SRAM_END +#define HEAP_END HC32_SRAM_END void PeripheralRegister_Unlock(void); void PeripheralClock_Config(void); diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c index 8527affb4d4..2673409f751 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.c @@ -194,7 +194,7 @@ rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) #endif -#if defined (RT_USING_SPI) +#if defined(RT_USING_SPI) rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) { rt_err_t result = RT_EOK; @@ -208,17 +208,17 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) case (rt_uint32_t)CM_SPI1: GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinState = PIN_STAT_SET; - stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinDir = PIN_DIR_OUT; GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; - (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); - GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); break; @@ -342,24 +342,24 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) #endif #endif -#if defined (BSP_USING_INPUT_CAPTURE) +#if defined(BSP_USING_INPUT_CAPTURE) rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) { rt_err_t result = RT_EOK; switch ((rt_uint32_t)tmr_instance) { -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) case (rt_uint32_t)CM_TMR6_1: GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_1_FUNC); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) case (rt_uint32_t)CM_TMR6_2: GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_2_FUNC); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_10) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_10) case (rt_uint32_t)CM_TMR6_10: GPIO_SetFunc(INPUT_CAPTURE_TMR6_10_PORT, INPUT_CAPTURE_TMR6_10_PIN, INPUT_CAPTURE_TMR6_10_FUNC); break; @@ -373,7 +373,7 @@ rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) #endif #ifdef RT_USING_PM -#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) +#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) { @@ -401,8 +401,8 @@ rt_err_t rt_hw_qspi_board_init(void) (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; #ifndef BSP_QSPI_USING_SOFT_CS - (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); - GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); #endif (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h index 996a262f19e..2008695c321 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/board_config.h @@ -17,374 +17,374 @@ #include "hc32_ll.h" #include "drv_config.h" #if defined(RT_USING_CHERRYUSB) - #include "usb_config.h" +#include "usb_config.h" #endif /************************* XTAL port **********************/ -#define XTAL_PORT (GPIO_PORT_F) -#define XTAL_IN_PIN (GPIO_PIN_00) -#define XTAL_OUT_PIN (GPIO_PIN_01) +#define XTAL_PORT (GPIO_PORT_F) +#define XTAL_IN_PIN (GPIO_PIN_00) +#define XTAL_OUT_PIN (GPIO_PIN_01) /************************ USART port **********************/ #if defined(BSP_USING_UART1) - #define USART1_RX_PORT (GPIO_PORT_E) - #define USART1_RX_PIN (GPIO_PIN_03) - #define USART1_RX_FUNC (GPIO_FUNC_33) +#define USART1_RX_PORT (GPIO_PORT_E) +#define USART1_RX_PIN (GPIO_PIN_03) +#define USART1_RX_FUNC (GPIO_FUNC_33) - #define USART1_TX_PORT (GPIO_PORT_E) - #define USART1_TX_PIN (GPIO_PIN_04) - #define USART1_TX_FUNC (GPIO_FUNC_32) +#define USART1_TX_PORT (GPIO_PORT_E) +#define USART1_TX_PIN (GPIO_PIN_04) +#define USART1_TX_FUNC (GPIO_FUNC_32) #endif #if defined(BSP_USING_UART2) - #define USART2_RX_PORT (GPIO_PORT_F) - #define USART2_RX_PIN (GPIO_PIN_02) - #define USART2_RX_FUNC (GPIO_FUNC_35) +#define USART2_RX_PORT (GPIO_PORT_F) +#define USART2_RX_PIN (GPIO_PIN_02) +#define USART2_RX_FUNC (GPIO_FUNC_35) - #define USART2_TX_PORT (GPIO_PORT_C) - #define USART2_TX_PIN (GPIO_PIN_13) - #define USART2_TX_FUNC (GPIO_FUNC_34) +#define USART2_TX_PORT (GPIO_PORT_C) +#define USART2_TX_PIN (GPIO_PIN_13) +#define USART2_TX_FUNC (GPIO_FUNC_34) #endif #if defined(BSP_USING_UART5) - #define USART5_RX_PORT (GPIO_PORT_E) - #define USART5_RX_PIN (GPIO_PIN_05) - #define USART5_RX_FUNC (GPIO_FUNC_41) +#define USART5_RX_PORT (GPIO_PORT_E) +#define USART5_RX_PIN (GPIO_PIN_05) +#define USART5_RX_FUNC (GPIO_FUNC_41) - #define USART5_TX_PORT (GPIO_PORT_E) - #define USART5_TX_PIN (GPIO_PIN_06) - #define USART5_TX_FUNC (GPIO_FUNC_40) +#define USART5_TX_PORT (GPIO_PORT_E) +#define USART5_TX_PIN (GPIO_PIN_06) +#define USART5_TX_FUNC (GPIO_FUNC_40) #endif /************************ I2C port **********************/ #if defined(BSP_USING_I2C1) - #define I2C1_SDA_PORT (GPIO_PORT_B) - #define I2C1_SDA_PIN (GPIO_PIN_09) - #define I2C1_SDA_FUNC (GPIO_FUNC_54) +#define I2C1_SDA_PORT (GPIO_PORT_B) +#define I2C1_SDA_PIN (GPIO_PIN_09) +#define I2C1_SDA_FUNC (GPIO_FUNC_54) - #define I2C1_SCL_PORT (GPIO_PORT_B) - #define I2C1_SCL_PIN (GPIO_PIN_06) - #define I2C1_SCL_FUNC (GPIO_FUNC_55) +#define I2C1_SCL_PORT (GPIO_PORT_B) +#define I2C1_SCL_PIN (GPIO_PIN_06) +#define I2C1_SCL_FUNC (GPIO_FUNC_55) #endif // TODO, ch2/3 for test only #if defined(BSP_USING_I2C2) - #define I2C2_SDA_PORT (GPIO_PORT_A) - #define I2C2_SDA_PIN (GPIO_PIN_09) - #define I2C2_SDA_FUNC (GPIO_FUNC_56) +#define I2C2_SDA_PORT (GPIO_PORT_A) +#define I2C2_SDA_PIN (GPIO_PIN_09) +#define I2C2_SDA_FUNC (GPIO_FUNC_56) - #define I2C2_SCL_PORT (GPIO_PORT_A) - #define I2C2_SCL_PIN (GPIO_PIN_10) - #define I2C2_SCL_FUNC (GPIO_FUNC_57) +#define I2C2_SCL_PORT (GPIO_PORT_A) +#define I2C2_SCL_PIN (GPIO_PIN_10) +#define I2C2_SCL_FUNC (GPIO_FUNC_57) #endif #if defined(BSP_USING_I2C3) - #define I2C3_SDA_PORT (GPIO_PORT_A) - #define I2C3_SDA_PIN (GPIO_PIN_09) - #define I2C3_SDA_FUNC (GPIO_FUNC_58) +#define I2C3_SDA_PORT (GPIO_PORT_A) +#define I2C3_SDA_PIN (GPIO_PIN_09) +#define I2C3_SDA_FUNC (GPIO_FUNC_58) - #define I2C3_SCL_PORT (GPIO_PORT_A) - #define I2C3_SCL_PIN (GPIO_PIN_10) - #define I2C3_SCL_FUNC (GPIO_FUNC_59) +#define I2C3_SCL_PORT (GPIO_PORT_A) +#define I2C3_SCL_PIN (GPIO_PIN_10) +#define I2C3_SCL_FUNC (GPIO_FUNC_59) #endif /*********** ADC configure *********/ #if defined(BSP_USING_ADC1) - #define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */ - #define ADC1_CH_PIN (GPIO_PIN_00) +#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */ +#define ADC1_CH_PIN (GPIO_PIN_00) #endif #if defined(BSP_USING_ADC2) - #define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */ - #define ADC2_CH_PIN (GPIO_PIN_01) +#define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */ +#define ADC2_CH_PIN (GPIO_PIN_01) #endif #if defined(BSP_USING_ADC3) - #define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */ - #define ADC3_CH_PIN (GPIO_PIN_02) +#define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */ +#define ADC3_CH_PIN (GPIO_PIN_02) #endif /*********** DAC configure *********/ #if defined(BSP_USING_DAC1) - #define DAC1_CH1_PORT (GPIO_PORT_A) - #define DAC1_CH1_PIN (GPIO_PIN_04) - #define DAC1_CH2_PORT (GPIO_PORT_A) - #define DAC1_CH2_PIN (GPIO_PIN_05) +#define DAC1_CH1_PORT (GPIO_PORT_A) +#define DAC1_CH1_PIN (GPIO_PIN_04) +#define DAC1_CH2_PORT (GPIO_PORT_A) +#define DAC1_CH2_PIN (GPIO_PIN_05) #endif #if defined(BSP_USING_DAC2) - #define DAC2_CH1_PORT (GPIO_PORT_A) - #define DAC2_CH1_PIN (GPIO_PIN_06) - #define DAC2_CH2_PORT (GPIO_PORT_A) - #define DAC2_CH2_PIN (GPIO_PIN_07) +#define DAC2_CH1_PORT (GPIO_PORT_A) +#define DAC2_CH1_PIN (GPIO_PIN_06) +#define DAC2_CH2_PORT (GPIO_PORT_A) +#define DAC2_CH2_PIN (GPIO_PIN_07) #endif #if defined(BSP_USING_DAC3) - #define DAC3_CH1_PORT (GPIO_PORT_C) - #define DAC3_CH1_PIN (GPIO_PIN_04) - #define DAC3_CH2_PORT (GPIO_PORT_C) - #define DAC3_CH2_PIN (GPIO_PIN_05) +#define DAC3_CH1_PORT (GPIO_PORT_C) +#define DAC3_CH1_PIN (GPIO_PIN_04) +#define DAC3_CH2_PORT (GPIO_PORT_C) +#define DAC3_CH2_PIN (GPIO_PIN_05) #endif #if defined(BSP_USING_DAC4) - #define DAC4_CH1_PORT (GPIO_PORT_E) - #define DAC4_CH1_PIN (GPIO_PIN_07) - #define DAC4_CH2_PORT (GPIO_PORT_E) - #define DAC4_CH2_PIN (GPIO_PIN_08) +#define DAC4_CH1_PORT (GPIO_PORT_E) +#define DAC4_CH1_PIN (GPIO_PIN_07) +#define DAC4_CH2_PORT (GPIO_PORT_E) +#define DAC4_CH2_PIN (GPIO_PIN_08) #endif /*********** CAN configure *********/ #if defined(BSP_USING_CAN1) - #define CAN1_TX_PORT (GPIO_PORT_D) - #define CAN1_TX_PIN (GPIO_PIN_12) - #define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) +#define CAN1_TX_PORT (GPIO_PORT_D) +#define CAN1_TX_PIN (GPIO_PIN_12) +#define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) - #define CAN1_RX_PORT (GPIO_PORT_D) - #define CAN1_RX_PIN (GPIO_PIN_13) - #define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) +#define CAN1_RX_PORT (GPIO_PORT_D) +#define CAN1_RX_PIN (GPIO_PIN_13) +#define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) #endif #if defined(BSP_USING_CAN2) - #define CAN2_TX_PORT (GPIO_PORT_C) - #define CAN2_TX_PIN (GPIO_PIN_07) - #define CAN2_TX_PIN_FUNC (GPIO_FUNC_60) +#define CAN2_TX_PORT (GPIO_PORT_C) +#define CAN2_TX_PIN (GPIO_PIN_07) +#define CAN2_TX_PIN_FUNC (GPIO_FUNC_60) - #define CAN2_RX_PORT (GPIO_PORT_D) - #define CAN2_RX_PIN (GPIO_PIN_11) - #define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) +#define CAN2_RX_PORT (GPIO_PORT_D) +#define CAN2_RX_PIN (GPIO_PIN_11) +#define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) #endif #if defined(BSP_USING_CAN3) - #define CAN3_TX_PORT (GPIO_PORT_C) - #define CAN3_TX_PIN (GPIO_PIN_06) - #define CAN3_TX_PIN_FUNC (GPIO_FUNC_62) +#define CAN3_TX_PORT (GPIO_PORT_C) +#define CAN3_TX_PIN (GPIO_PIN_06) +#define CAN3_TX_PIN_FUNC (GPIO_FUNC_62) - #define CAN3_RX_PORT (GPIO_PORT_A) - #define CAN3_RX_PIN (GPIO_PIN_05) - #define CAN3_RX_PIN_FUNC (GPIO_FUNC_63) +#define CAN3_RX_PORT (GPIO_PORT_A) +#define CAN3_RX_PIN (GPIO_PIN_05) +#define CAN3_RX_PIN_FUNC (GPIO_FUNC_63) #endif /************************* SPI port ***********************/ #if defined(BSP_USING_SPI1) - #define SPI1_CS_PORT (GPIO_PORT_B) - #define SPI1_CS_PIN (GPIO_PIN_12) +#define SPI1_CS_PORT (GPIO_PORT_B) +#define SPI1_CS_PIN (GPIO_PIN_12) - #define SPI1_SCK_PORT (GPIO_PORT_B) - #define SPI1_SCK_PIN (GPIO_PIN_13) - #define SPI1_SCK_FUNC (GPIO_FUNC_6) +#define SPI1_SCK_PORT (GPIO_PORT_B) +#define SPI1_SCK_PIN (GPIO_PIN_13) +#define SPI1_SCK_FUNC (GPIO_FUNC_6) - #define SPI1_MOSI_PORT (GPIO_PORT_A) - #define SPI1_MOSI_PIN (GPIO_PIN_07) - #define SPI1_MOSI_FUNC (GPIO_FUNC_6) +#define SPI1_MOSI_PORT (GPIO_PORT_A) +#define SPI1_MOSI_PIN (GPIO_PIN_07) +#define SPI1_MOSI_FUNC (GPIO_FUNC_6) - #define SPI1_MISO_PORT (GPIO_PORT_B) - #define SPI1_MISO_PIN (GPIO_PIN_14) - #define SPI1_MISO_FUNC (GPIO_FUNC_6) +#define SPI1_MISO_PORT (GPIO_PORT_B) +#define SPI1_MISO_PIN (GPIO_PIN_14) +#define SPI1_MISO_FUNC (GPIO_FUNC_6) - #define SPI1_WP_PORT (GPIO_PORT_B) - #define SPI1_WP_PIN (GPIO_PIN_10) +#define SPI1_WP_PORT (GPIO_PORT_B) +#define SPI1_WP_PIN (GPIO_PIN_10) - #define SPI1_HOLD_PORT (GPIO_PORT_B) - #define SPI1_HOLD_PIN (GPIO_PIN_11) +#define SPI1_HOLD_PORT (GPIO_PORT_B) +#define SPI1_HOLD_PIN (GPIO_PIN_11) #endif /************************ RTC/PM *****************************/ #if defined(BSP_USING_RTC) || defined(RT_USING_PM) - #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) - #define XTAL32_PORT (GPIO_PORT_C) - #define XTAL32_IN_PIN (GPIO_PIN_14) - #define XTAL32_OUT_PIN (GPIO_PIN_15) - #endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) +#define XTAL32_PORT (GPIO_PORT_C) +#define XTAL32_IN_PIN (GPIO_PIN_14) +#define XTAL32_OUT_PIN (GPIO_PIN_15) +#endif #endif #if defined(RT_USING_PWM) /*********** PWM_TMRA configure *********/ - #if defined(BSP_USING_PWM_TMRA_1) - #if defined(BSP_USING_PWM_TMRA_1_CH1) - #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_00) - #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_15) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH2) - #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_01) - #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_15) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH3) - #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_02) - #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_15) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH4) - #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_03) - #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_15) - #endif - #endif - - #if defined(BSP_USING_PWM_TMRA_2) - #if defined(BSP_USING_PWM_TMRA_2_CH1) - #define PWM_TMRA_2_CH1_PORT (GPIO_PORT_C) - #define PWM_TMRA_2_CH1_PIN (GPIO_PIN_06) - #define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_16) - #endif - #if defined(BSP_USING_PWM_TMRA_2_CH2) - #define PWM_TMRA_2_CH2_PORT (GPIO_PORT_C) - #define PWM_TMRA_2_CH2_PIN (GPIO_PIN_07) - #define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_16) - #endif - #if defined(BSP_USING_PWM_TMRA_2_CH3) - #define PWM_TMRA_2_CH3_PORT (GPIO_PORT_C) - #define PWM_TMRA_2_CH3_PIN (GPIO_PIN_08) - #define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_16) - #endif - #if defined(BSP_USING_PWM_TMRA_2_CH4) - #define PWM_TMRA_2_CH4_PORT (GPIO_PORT_C) - #define PWM_TMRA_2_CH4_PIN (GPIO_PIN_09) - #define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_16) - #endif - #endif +#if defined(BSP_USING_PWM_TMRA_1) +#if defined(BSP_USING_PWM_TMRA_1_CH1) +#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_00) +#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_15) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH2) +#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_01) +#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_15) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH3) +#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_02) +#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_15) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH4) +#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_03) +#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_15) +#endif +#endif + +#if defined(BSP_USING_PWM_TMRA_2) +#if defined(BSP_USING_PWM_TMRA_2_CH1) +#define PWM_TMRA_2_CH1_PORT (GPIO_PORT_C) +#define PWM_TMRA_2_CH1_PIN (GPIO_PIN_06) +#define PWM_TMRA_2_CH1_PIN_FUNC (GPIO_FUNC_16) +#endif +#if defined(BSP_USING_PWM_TMRA_2_CH2) +#define PWM_TMRA_2_CH2_PORT (GPIO_PORT_C) +#define PWM_TMRA_2_CH2_PIN (GPIO_PIN_07) +#define PWM_TMRA_2_CH2_PIN_FUNC (GPIO_FUNC_16) +#endif +#if defined(BSP_USING_PWM_TMRA_2_CH3) +#define PWM_TMRA_2_CH3_PORT (GPIO_PORT_C) +#define PWM_TMRA_2_CH3_PIN (GPIO_PIN_08) +#define PWM_TMRA_2_CH3_PIN_FUNC (GPIO_FUNC_16) +#endif +#if defined(BSP_USING_PWM_TMRA_2_CH4) +#define PWM_TMRA_2_CH4_PORT (GPIO_PORT_C) +#define PWM_TMRA_2_CH4_PIN (GPIO_PIN_09) +#define PWM_TMRA_2_CH4_PIN_FUNC (GPIO_FUNC_16) +#endif +#endif /*********** PWM_TMR4 configure *********/ - #if defined(BSP_USING_PWM_TMR4_1) - #if defined(BSP_USING_PWM_TMR4_1_OUH) - #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_B) - #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_14) - #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OUL) - #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_B) - #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_15) - #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVH) - #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_D) - #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_08) - #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVL) - #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_D) - #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_09) - #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWH) - #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_D) - #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10) - #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_20) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWL) - #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_D) - #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_11) - #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_20) - #endif - #endif +#if defined(BSP_USING_PWM_TMR4_1) +#if defined(BSP_USING_PWM_TMR4_1_OUH) +#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_B) +#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_14) +#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OUL) +#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_B) +#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_15) +#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVH) +#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_D) +#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_08) +#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVL) +#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_D) +#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_09) +#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWH) +#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_D) +#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_10) +#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_20) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWL) +#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_D) +#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_11) +#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_20) +#endif +#endif /*********** PWM_TMR6 configure *********/ - #if defined(BSP_USING_PWM_TMR6_1) - #if defined(BSP_USING_PWM_TMR6_1_A) - #define PWM_TMR6_1_A_PORT (GPIO_PORT_A) - #define PWM_TMR6_1_A_PIN (GPIO_PIN_08) - #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_13) - #endif - #if defined(BSP_USING_PWM_TMR6_1_B) - #define PWM_TMR6_1_B_PORT (GPIO_PORT_C) - #define PWM_TMR6_1_B_PIN (GPIO_PIN_10) - #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_12) - #endif - #endif +#if defined(BSP_USING_PWM_TMR6_1) +#if defined(BSP_USING_PWM_TMR6_1_A) +#define PWM_TMR6_1_A_PORT (GPIO_PORT_A) +#define PWM_TMR6_1_A_PIN (GPIO_PIN_08) +#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_13) +#endif +#if defined(BSP_USING_PWM_TMR6_1_B) +#define PWM_TMR6_1_B_PORT (GPIO_PORT_C) +#define PWM_TMR6_1_B_PIN (GPIO_PIN_10) +#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_12) +#endif +#endif #endif #if defined(BSP_USING_INPUT_CAPTURE) - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) - #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A) - #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_00) - #define INPUT_CAPTURE_TMR6_1_FUNC (GPIO_FUNC_11) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) - #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B) - #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02) - #define INPUT_CAPTURE_TMR6_2_FUNC (GPIO_FUNC_12) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_10) - #define INPUT_CAPTURE_TMR6_10_PORT (GPIO_PORT_A) - #define INPUT_CAPTURE_TMR6_10_PIN (GPIO_PIN_12) - #define INPUT_CAPTURE_TMR6_10_FUNC (GPIO_FUNC_11) - #endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_A) +#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_00) +#define INPUT_CAPTURE_TMR6_1_FUNC (GPIO_FUNC_11) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_B) +#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_02) +#define INPUT_CAPTURE_TMR6_2_FUNC (GPIO_FUNC_12) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_10) +#define INPUT_CAPTURE_TMR6_10_PORT (GPIO_PORT_A) +#define INPUT_CAPTURE_TMR6_10_PIN (GPIO_PIN_12) +#define INPUT_CAPTURE_TMR6_10_FUNC (GPIO_FUNC_11) +#endif #endif #if defined(BSP_USING_QSPI) - #ifndef BSP_QSPI_USING_SOFT_CS +#ifndef BSP_QSPI_USING_SOFT_CS /* QSSN */ - #define QSPI_FLASH_CS_PORT (GPIO_PORT_B) - #define QSPI_FLASH_CS_PIN (GPIO_PIN_12) - #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_5) - #endif +#define QSPI_FLASH_CS_PORT (GPIO_PORT_B) +#define QSPI_FLASH_CS_PIN (GPIO_PIN_12) +#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_5) +#endif /* QSCK */ - #define QSPI_FLASH_SCK_PORT (GPIO_PORT_B) - #define QSPI_FLASH_SCK_PIN (GPIO_PIN_13) - #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_5) +#define QSPI_FLASH_SCK_PORT (GPIO_PORT_B) +#define QSPI_FLASH_SCK_PIN (GPIO_PIN_13) +#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_5) /* QSIO0 */ - #define QSPI_FLASH_IO0_PORT (GPIO_PORT_A) - #define QSPI_FLASH_IO0_PIN (GPIO_PIN_07) - #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_5) +#define QSPI_FLASH_IO0_PORT (GPIO_PORT_A) +#define QSPI_FLASH_IO0_PIN (GPIO_PIN_07) +#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_5) /* QSIO1 */ - #define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO1_PIN (GPIO_PIN_14) - #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_5) +#define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO1_PIN (GPIO_PIN_14) +#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_5) /* QSIO2 */ - #define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) - #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_4) +#define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) +#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_4) /* QSIO3 */ - #define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO3_PIN (GPIO_PIN_11) - #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_4) +#define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO3_PIN (GPIO_PIN_11) +#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_4) #endif /*********** TMRA_PULSE_ENCODER configure *********/ #if defined(RT_USING_PULSE_ENCODER) - #if defined(BSP_USING_TMRA_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) - #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_00) - #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_15) - #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_01) - #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_15) - #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ - #endif /* BSP_USING_TMRA_PULSE_ENCODER */ - - #if defined(BSP_USING_TMR6_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) - #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_03) - #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_11) - #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_07) - #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_14) - #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ - #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_00) +#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_15) +#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_01) +#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_15) +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#endif /* BSP_USING_TMRA_PULSE_ENCODER */ + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_03) +#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_11) +#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_07) +#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_14) +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#endif /* BSP_USING_TMR6_PULSE_ENCODER */ #endif /* RT_USING_PULSE_ENCODER */ #if defined(RT_USING_CHERRYUSB) - #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ - defined(BSP_USING_USBFS) || defined(RT_USING_USB) - #error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" - #endif +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(RT_USING_USB) +#error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" +#endif #endif #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) - #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) /* USBFS Core*/ - #define USBF_DP_PORT (GPIO_PORT_A) - #define USBF_DP_PIN (GPIO_PIN_12) - #define USBF_DM_PORT (GPIO_PORT_A) - #define USBF_DM_PIN (GPIO_PIN_11) - #define USBF_VBUS_PORT (GPIO_PORT_A) - #define USBF_VBUS_PIN (GPIO_PIN_09) - #define USBF_DRVVBUS_PORT (GPIO_PORT_C) - #define USBF_DRVVBUS_PIN (GPIO_PIN_09) - #endif +#define USBF_DP_PORT (GPIO_PORT_A) +#define USBF_DP_PIN (GPIO_PIN_12) +#define USBF_DM_PORT (GPIO_PORT_A) +#define USBF_DM_PIN (GPIO_PIN_11) +#define USBF_VBUS_PORT (GPIO_PORT_A) +#define USBF_VBUS_PIN (GPIO_PIN_09) +#define USBF_DRVVBUS_PORT (GPIO_PORT_C) +#define USBF_DRVVBUS_PIN (GPIO_PIN_09) +#endif #endif #endif diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/adc_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/adc_config.h index c88a0fdf665..45563945988 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/adc_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/adc_config.h @@ -20,42 +20,41 @@ extern "C" { #ifdef BSP_USING_ADC1 #ifndef ADC1_INIT_PARAMS -#define ADC1_INIT_PARAMS \ - { \ - .name = "adc1", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC1_INIT_PARAMS */ -#if defined (BSP_ADC1_USING_DMA) +#if defined(BSP_ADC1_USING_DMA) #ifndef ADC1_EOCA_DMA_CONFIG -#define ADC1_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC1_EOCA_DMA_INSTANCE, \ - .channel = ADC1_EOCA_DMA_CHANNEL, \ - .clock = ADC1_EOCA_DMA_CLOCK, \ - .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC1_EOCA, \ - .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC1_EOCA_DMA_IRQn, \ - .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ - .int_src = ADC1_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC1_EOCA_DMA_CONFIG */ #endif /* BSP_ADC1_USING_DMA */ @@ -63,42 +62,41 @@ extern "C" { #ifdef BSP_USING_ADC2 #ifndef ADC2_INIT_PARAMS -#define ADC2_INIT_PARAMS \ - { \ - .name = "adc2", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC2_INIT_PARAMS */ -#if defined (BSP_ADC2_USING_DMA) +#if defined(BSP_ADC2_USING_DMA) #ifndef ADC2_EOCA_DMA_CONFIG -#define ADC2_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC2_EOCA_DMA_INSTANCE, \ - .channel = ADC2_EOCA_DMA_CHANNEL, \ - .clock = ADC2_EOCA_DMA_CLOCK, \ - .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC2_EOCA, \ - .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC2_EOCA_DMA_IRQn, \ - .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ - .int_src = ADC2_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC2_EOCA_DMA_CONFIG */ #endif /* BSP_ADC2_USING_DMA */ @@ -106,42 +104,41 @@ extern "C" { #ifdef BSP_USING_ADC3 #ifndef ADC3_INIT_PARAMS -#define ADC3_INIT_PARAMS \ - { \ - .name = "adc3", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_EVT0, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_EVT0, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_TMR0_1_CMP_B, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC3_INIT_PARAMS */ -#if defined (BSP_ADC3_USING_DMA) +#if defined(BSP_ADC3_USING_DMA) #ifndef ADC3_EOCA_DMA_CONFIG -#define ADC3_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC3_EOCA_DMA_INSTANCE, \ - .channel = ADC3_EOCA_DMA_CHANNEL, \ - .clock = ADC3_EOCA_DMA_CLOCK, \ - .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC3_EOCA, \ - .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC3_EOCA_DMA_IRQn, \ - .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ - .int_src = ADC3_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC3_EOCA_DMA_CONFIG */ #endif /* BSP_ADC3_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/can_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/can_config.h index ae280903121..60c8dd5087b 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/can_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/can_config.h @@ -19,37 +19,37 @@ extern "C" { #endif #ifdef BSP_USING_CAN1 -#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) -#define CAN1_NAME ("can1") +#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN1_NAME ("can1") #ifndef CAN1_INIT_PARAMS -#define CAN1_INIT_PARAMS \ - { \ - .name = CAN1_NAME, \ - .single_trans_mode = RT_FALSE \ +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ } #endif /* CAN1_INIT_PARAMS */ #endif /* BSP_USING_CAN1 */ #ifdef BSP_USING_CAN2 -#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) -#define CAN2_NAME ("can2") +#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN2_NAME ("can2") #ifndef CAN2_INIT_PARAMS -#define CAN2_INIT_PARAMS \ - { \ - .name = CAN2_NAME, \ - .single_trans_mode = RT_FALSE \ +#define CAN2_INIT_PARAMS \ + { \ + .name = CAN2_NAME, \ + .single_trans_mode = RT_FALSE \ } #endif /* CAN2_INIT_PARAMS */ #endif /* BSP_USING_CAN2 */ #ifdef BSP_USING_CAN3 -#define CAN3_CLOCK_SEL (CAN_CLOCK_SRC_40M) -#define CAN3_NAME ("can3") +#define CAN3_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN3_NAME ("can3") #ifndef CAN3_INIT_PARAMS -#define CAN3_INIT_PARAMS \ - { \ - .name = CAN3_NAME, \ - .single_trans_mode = RT_FALSE \ +#define CAN3_INIT_PARAMS \ + { \ + .name = CAN3_NAME, \ + .single_trans_mode = RT_FALSE \ } #endif /* CAN3_INIT_PARAMS */ #endif /* BSP_USING_CAN3 */ @@ -63,76 +63,76 @@ extern "C" { The following bit time configures are based on CAN Clock 40M */ -#define CAN_BIT_TIME_CONFIG_1M_BAUD \ - { \ - .u32Prescaler = 2, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_800K_BAUD \ - { \ - .u32Prescaler = 2, \ - .u32TimeSeg1 = 20, \ - .u32TimeSeg2 = 5, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_500K_BAUD \ - { \ - .u32Prescaler = 4, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_250K_BAUD \ - { \ - .u32Prescaler = 8, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_125K_BAUD \ - { \ - .u32Prescaler = 16, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_100K_BAUD \ - { \ - .u32Prescaler = 20, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_50K_BAUD \ - { \ - .u32Prescaler = 40, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_20K_BAUD \ - { \ - .u32Prescaler = 100, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_10K_BAUD \ - { \ - .u32Prescaler = 200, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h index fb01e4061eb..32d238abba2 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/dac_config.h @@ -20,76 +20,76 @@ extern "C" { #ifdef BSP_USING_DAC1 #ifndef DAC1_INIT_PARAMS -#define DAC1_INIT_PARAMS \ - { \ - .name = "dac1", \ - .vref = 3300, \ - .data_align = DAC_DATA_ALIGN_RIGHT, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch2_output_enable = RT_TRUE, \ - .ch1_amp_enable = RT_TRUE, \ - .ch2_amp_enable = RT_TRUE, \ - .ch1_amp_gain = DAC_AMP_GAIN_1, \ - .ch2_amp_gain = DAC_AMP_GAIN_1, \ +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + .ch1_amp_gain = DAC_AMP_GAIN_1, \ + .ch2_amp_gain = DAC_AMP_GAIN_1, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ #ifdef BSP_USING_DAC2 #ifndef DAC2_INIT_PARAMS -#define DAC2_INIT_PARAMS \ - { \ - .name = "dac2", \ - .vref = 3300, \ - .data_align = DAC_DATA_ALIGN_RIGHT, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch2_output_enable = RT_TRUE, \ - .ch1_amp_enable = RT_TRUE, \ - .ch2_amp_enable = RT_TRUE, \ - .ch1_amp_gain = DAC_AMP_GAIN_1, \ - .ch2_amp_gain = DAC_AMP_GAIN_1, \ +#define DAC2_INIT_PARAMS \ + { \ + .name = "dac2", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + .ch1_amp_gain = DAC_AMP_GAIN_1, \ + .ch2_amp_gain = DAC_AMP_GAIN_1, \ } #endif /* DAC2_INIT_PARAMS */ #endif /* BSP_USING_DAC2 */ #ifdef BSP_USING_DAC3 #ifndef DAC3_INIT_PARAMS -#define DAC3_INIT_PARAMS \ - { \ - .name = "dac3", \ - .vref = 3300, \ - .data_align = DAC_DATA_ALIGN_RIGHT, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch2_output_enable = RT_TRUE, \ - .ch1_amp_enable = RT_TRUE, \ - .ch2_amp_enable = RT_TRUE, \ - .ch1_amp_gain = DAC_AMP_GAIN_1, \ - .ch2_amp_gain = DAC_AMP_GAIN_1, \ +#define DAC3_INIT_PARAMS \ + { \ + .name = "dac3", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + .ch1_amp_gain = DAC_AMP_GAIN_1, \ + .ch2_amp_gain = DAC_AMP_GAIN_1, \ } #endif /* DAC3_INIT_PARAMS */ #endif /* BSP_USING_DAC3 */ #ifdef BSP_USING_DAC4 #ifndef DAC4_INIT_PARAMS -#define DAC4_INIT_PARAMS \ - { \ - .name = "dac4", \ - .vref = 3300, \ - .data_align = DAC_DATA_ALIGN_RIGHT, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch2_output_enable = RT_TRUE, \ - .ch1_amp_enable = RT_TRUE, \ - .ch2_amp_enable = RT_TRUE, \ - .ch1_amp_gain = DAC_AMP_GAIN_1, \ - .ch2_amp_gain = DAC_AMP_GAIN_1, \ +#define DAC4_INIT_PARAMS \ + { \ + .name = "dac4", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + .ch1_amp_gain = DAC_AMP_GAIN_1, \ + .ch2_amp_gain = DAC_AMP_GAIN_1, \ } #endif /* DAC4_INIT_PARAMS */ #endif /* BSP_USING_DAC4 */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/dma_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/dma_config.h index b5202f3eb93..76bab92f27e 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/dma_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/dma_config.h @@ -21,248 +21,248 @@ extern "C" { /* DMA1 ch0 */ #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) -#define SPI1_RX_DMA_INSTANCE CM_DMA1 -#define SPI1_RX_DMA_CHANNEL DMA_CH0 -#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) -#define SPI3_RX_DMA_INSTANCE CM_DMA1 -#define SPI3_RX_DMA_CHANNEL DMA_CH0 -#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH0 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) -#define I2C1_TX_DMA_INSTANCE CM_DMA1 -#define I2C1_TX_DMA_CHANNEL DMA_CH0 -#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 -#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 #endif /* DMA1 ch1 */ #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) -#define SPI1_TX_DMA_INSTANCE CM_DMA1 -#define SPI1_TX_DMA_CHANNEL DMA_CH1 -#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) -#define SPI3_TX_DMA_INSTANCE CM_DMA1 -#define SPI3_TX_DMA_CHANNEL DMA_CH1 -#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH1 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) -#define I2C1_RX_DMA_INSTANCE CM_DMA1 -#define I2C1_RX_DMA_CHANNEL DMA_CH1 -#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 -#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 #endif /* DMA1 ch2 */ #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) -#define SPI2_RX_DMA_INSTANCE CM_DMA1 -#define SPI2_RX_DMA_CHANNEL DMA_CH2 -#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) -#define I2C2_TX_DMA_INSTANCE CM_DMA1 -#define I2C2_TX_DMA_CHANNEL DMA_CH2 -#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 -#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 #endif /* DMA1 ch3 */ #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) -#define SPI2_TX_DMA_INSTANCE CM_DMA1 -#define SPI2_TX_DMA_CHANNEL DMA_CH3 -#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) -#define I2C2_RX_DMA_INSTANCE CM_DMA1 -#define I2C2_RX_DMA_CHANNEL DMA_CH3 -#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 -#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) -#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 -#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 -#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 #endif /* DMA1 ch4 */ #if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) -#define UART5_RX_DMA_INSTANCE CM_DMA1 -#define UART5_RX_DMA_CHANNEL DMA_CH4 -#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4 -#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define UART5_RX_DMA_INSTANCE CM_DMA1 +#define UART5_RX_DMA_CHANNEL DMA_CH4 +#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART5_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART5_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define UART5_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define UART5_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) -#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 -#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 -#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 #endif /* DMA1 ch5 */ #if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) -#define UART5_TX_DMA_INSTANCE CM_DMA1 -#define UART5_TX_DMA_CHANNEL DMA_CH5 -#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5 -#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define UART5_TX_DMA_INSTANCE CM_DMA1 +#define UART5_TX_DMA_CHANNEL DMA_CH5 +#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART5_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART5_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define UART5_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define UART5_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 #elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) -#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 -#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 -#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 #endif /* DMA2 ch0 */ #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) -#define UART1_RX_DMA_INSTANCE CM_DMA2 -#define UART1_RX_DMA_CHANNEL DMA_CH0 -#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 -#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 #elif defined(BSP_QSPI_USING_DMA) && !defined(QSPI_DMA_INSTANCE) -#define QSPI_DMA_INSTANCE CM_DMA2 -#define QSPI_DMA_CHANNEL DMA_CH0 -#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define QSPI_DMA_TRIG_SELECT AOS_DMA2_0 -#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define QSPI_DMA_INSTANCE CM_DMA2 +#define QSPI_DMA_CHANNEL DMA_CH0 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA2_0 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define QSPI_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA2_TC0 #endif /* DMA2 ch1 */ #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) -#define UART1_TX_DMA_INSTANCE CM_DMA2 -#define UART1_TX_DMA_CHANNEL DMA_CH1 -#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 -#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 #endif /* DMA2 ch2 */ #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) -#define UART2_RX_DMA_INSTANCE CM_DMA2 -#define UART2_RX_DMA_CHANNEL DMA_CH2 -#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 -#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 #endif /* DMA2 ch3 */ #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) -#define UART2_TX_DMA_INSTANCE CM_DMA2 -#define UART2_TX_DMA_CHANNEL DMA_CH3 -#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 -#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM -#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO -#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 #endif /* DMA2 ch4 */ #if defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) -#define UART4_RX_DMA_INSTANCE CM_DMA2 -#define UART4_RX_DMA_CHANNEL DMA_CH4 -#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4 -#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM -#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO -#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#define UART4_RX_DMA_INSTANCE CM_DMA2 +#define UART4_RX_DMA_CHANNEL DMA_CH4 +#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART4_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART4_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART4_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART4_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 #endif /* DMA2 ch5 */ #if defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) -#define UART4_TX_DMA_INSTANCE CM_DMA2 -#define UART4_TX_DMA_CHANNEL DMA_CH5 -#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5 -#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM -#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO -#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#define UART4_TX_DMA_INSTANCE CM_DMA2 +#define UART4_TX_DMA_CHANNEL DMA_CH5 +#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART4_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART4_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART4_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART4_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/gpio_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/gpio_config.h index a0bbb41e1ab..bd3fd9cca2b 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/gpio_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/gpio_config.h @@ -23,146 +23,146 @@ extern "C" { #if defined(RT_USING_PIN) #ifndef EXTINT0_IRQ_CONFIG -#define EXTINT0_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT0_IRQ_NUM, \ - .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ0, \ +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT1_IRQ_CONFIG -#define EXTINT1_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT1_IRQ_NUM, \ - .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ1, \ +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT2_IRQ_CONFIG -#define EXTINT2_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT2_IRQ_NUM, \ - .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ2, \ +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ } #endif /* EXTINT2_IRQ_CONFIG */ #ifndef EXTINT3_IRQ_CONFIG -#define EXTINT3_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT3_IRQ_NUM, \ - .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ3, \ +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ } #endif /* EXTINT3_IRQ_CONFIG */ #ifndef EXTINT4_IRQ_CONFIG -#define EXTINT4_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT4_IRQ_NUM, \ - .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ4, \ +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ } #endif /* EXTINT4_IRQ_CONFIG */ #ifndef EXTINT5_IRQ_CONFIG -#define EXTINT5_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT5_IRQ_NUM, \ - .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ5, \ +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ } #endif /* EXTINT5_IRQ_CONFIG */ #ifndef EXTINT6_IRQ_CONFIG -#define EXTINT6_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT6_IRQ_NUM, \ - .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ6, \ +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ } #endif /* EXTINT6_IRQ_CONFIG */ #ifndef EXTINT7_IRQ_CONFIG -#define EXTINT7_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT7_IRQ_NUM, \ - .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ7, \ +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ } #endif /* EXTINT7_IRQ_CONFIG */ #ifndef EXTINT8_IRQ_CONFIG -#define EXTINT8_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT8_IRQ_NUM, \ - .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ8, \ +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ } #endif /* EXTINT8_IRQ_CONFIG */ #ifndef EXTINT9_IRQ_CONFIG -#define EXTINT9_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT9_IRQ_NUM, \ - .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ9, \ +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ } #endif /* EXTINT9_IRQ_CONFIG */ #ifndef EXTINT10_IRQ_CONFIG -#define EXTINT10_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT10_IRQ_NUM, \ - .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ10, \ +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ } #endif /* EXTINT10_IRQ_CONFIG */ #ifndef EXTINT11_IRQ_CONFIG -#define EXTINT11_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT11_IRQ_NUM, \ - .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ11, \ +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ } #endif /* EXTINT11_IRQ_CONFIG */ #ifndef EXTINT12_IRQ_CONFIG -#define EXTINT12_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT12_IRQ_NUM, \ - .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ12, \ +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ } #endif /* EXTINT12_IRQ_CONFIG */ #ifndef EXTINT13_IRQ_CONFIG -#define EXTINT13_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT13_IRQ_NUM, \ - .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ13, \ +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ } #endif /* EXTINT13_IRQ_CONFIG */ #ifndef EXTINT14_IRQ_CONFIG -#define EXTINT14_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT14_IRQ_NUM, \ - .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ14, \ +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ } #endif /* EXTINT14_IRQ_CONFIG */ #ifndef EXTINT15_IRQ_CONFIG -#define EXTINT15_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT15_IRQ_NUM, \ - .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ15, \ +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ } #endif /* EXTINT15_IRQ_CONFIG */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/i2c_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/i2c_config.h index 8f7c6b62967..d3912a6e280 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/i2c_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/i2c_config.h @@ -21,101 +21,97 @@ extern "C" { #if defined(BSP_USING_I2C1) #ifndef I2C1_CONFIG -#define I2C1_CONFIG \ - { \ - .name = "i2c1", \ - .Instance = CM_I2C1, \ - .clock = FCG1_PERIPH_I2C1, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C1_CONFIG */ #endif #if defined(BSP_I2C1_USING_DMA) #ifndef I2C1_TX_DMA_CONFIG -#define I2C1_TX_DMA_CONFIG \ - { \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .channel = I2C1_TX_DMA_CHANNEL, \ - .clock = I2C1_TX_DMA_CLOCK, \ - .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_TEI, \ - .flag = I2C1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_TX_DMA_IRQn, \ - .irq_prio = I2C1_TX_DMA_INT_PRIO, \ - .int_src = I2C1_TX_DMA_INT_SRC, \ - }, \ +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_TX_DMA_CONFIG */ #ifndef I2C1_RX_DMA_CONFIG -#define I2C1_RX_DMA_CONFIG \ - { \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .channel = I2C1_RX_DMA_CHANNEL, \ - .clock = I2C1_RX_DMA_CLOCK, \ - .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_RXI, \ - .flag = I2C1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_RX_DMA_IRQn, \ - .irq_prio = I2C1_RX_DMA_INT_PRIO, \ - .int_src = I2C1_RX_DMA_INT_SRC, \ - }, \ +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_RX_DMA_CONFIG */ #endif /* BSP_I2C1_USING_DMA */ #if defined(BSP_USING_I2C2) #ifndef I2C2_CONFIG -#define I2C2_CONFIG \ - { \ - .name = "i2c2", \ - .Instance = CM_I2C2, \ - .clock = FCG1_PERIPH_I2C2, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C2_CONFIG */ #if defined(BSP_I2C2_USING_DMA) #ifndef I2C2_TX_DMA_CONFIG -#define I2C2_TX_DMA_CONFIG \ - { \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .channel = I2C2_TX_DMA_CHANNEL, \ - .clock = I2C2_TX_DMA_CLOCK, \ - .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_TEI, \ - .flag = I2C2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_TX_DMA_IRQn, \ - .irq_prio = I2C2_TX_DMA_INT_PRIO, \ - .int_src = I2C2_TX_DMA_INT_SRC, \ - }, \ +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_TX_DMA_CONFIG */ #ifndef I2C2_RX_DMA_CONFIG -#define I2C2_RX_DMA_CONFIG \ - { \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .channel = I2C2_RX_DMA_CHANNEL, \ - .clock = I2C2_RX_DMA_CLOCK, \ - .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_RXI, \ - .flag = I2C2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_RX_DMA_IRQn, \ - .irq_prio = I2C2_RX_DMA_INT_PRIO, \ - .int_src = I2C2_RX_DMA_INT_SRC, \ - }, \ +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_RX_DMA_CONFIG */ #endif /* BSP_I2C2_USING_DMA */ @@ -123,50 +119,48 @@ extern "C" { #if defined(BSP_USING_I2C3) #ifndef I2C3_CONFIG -#define I2C3_CONFIG \ - { \ - .name = "i2c3", \ - .Instance = CM_I2C3, \ - .clock = FCG1_PERIPH_I2C3, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C3_CONFIG */ #if defined(BSP_I2C3_USING_DMA) #ifndef I2C3_TX_DMA_CONFIG -#define I2C3_TX_DMA_CONFIG \ - { \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .channel = I2C3_TX_DMA_CHANNEL, \ - .clock = I2C3_TX_DMA_CLOCK, \ - .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_TEI, \ - .flag = I2C3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_TX_DMA_IRQn, \ - .irq_prio = I2C3_TX_DMA_INT_PRIO, \ - .int_src = I2C3_TX_DMA_INT_SRC, \ - }, \ +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_TX_DMA_CONFIG */ #ifndef I2C3_RX_DMA_CONFIG -#define I2C3_RX_DMA_CONFIG \ - { \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .channel = I2C3_RX_DMA_CHANNEL, \ - .clock = I2C3_RX_DMA_CLOCK, \ - .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_RXI, \ - .flag = I2C3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_RX_DMA_IRQn, \ - .irq_prio = I2C3_RX_DMA_INT_PRIO, \ - .int_src = I2C3_RX_DMA_INT_SRC, \ - }, \ +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_RX_DMA_CONFIG */ #endif /* BSP_I2C3_USING_DMA */ @@ -174,50 +168,48 @@ extern "C" { #if defined(BSP_USING_I2C4) #ifndef I2C4_CONFIG -#define I2C4_CONFIG \ - { \ - .name = "i2c4", \ - .Instance = CM_I2C4, \ - .clock = FCG1_PERIPH_I2C4, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C4_CONFIG \ + { \ + .name = "i2c4", \ + .Instance = CM_I2C4, \ + .clock = FCG1_PERIPH_I2C4, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C4_CONFIG */ #if defined(BSP_I2C4_USING_DMA) #ifndef I2C4_TX_DMA_CONFIG -#define I2C4_TX_DMA_CONFIG \ - { \ - .Instance = I2C4_TX_DMA_INSTANCE, \ - .channel = I2C4_TX_DMA_CHANNEL, \ - .clock = I2C4_TX_DMA_CLOCK, \ - .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C4_TEI, \ - .flag = I2C4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C4_TX_DMA_IRQn, \ - .irq_prio = I2C4_TX_DMA_INT_PRIO, \ - .int_src = I2C4_TX_DMA_INT_SRC, \ - }, \ +#define I2C4_TX_DMA_CONFIG \ + { \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + .clock = I2C4_TX_DMA_CLOCK, \ + .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_TEI, \ + .flag = I2C4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_TX_DMA_IRQn, \ + .irq_prio = I2C4_TX_DMA_INT_PRIO, \ + .int_src = I2C4_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C4_TX_DMA_CONFIG */ #ifndef I2C4_RX_DMA_CONFIG -#define I2C4_RX_DMA_CONFIG \ - { \ - .Instance = I2C4_RX_DMA_INSTANCE, \ - .channel = I2C4_RX_DMA_CHANNEL, \ - .clock = I2C4_RX_DMA_CLOCK, \ - .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C4_RXI, \ - .flag = I2C4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C4_RX_DMA_IRQn, \ - .irq_prio = I2C4_RX_DMA_INT_PRIO, \ - .int_src = I2C4_RX_DMA_INT_SRC, \ - }, \ +#define I2C4_RX_DMA_CONFIG \ + { \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + .clock = I2C4_RX_DMA_CLOCK, \ + .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_RXI, \ + .flag = I2C4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_RX_DMA_IRQn, \ + .irq_prio = I2C4_RX_DMA_INT_PRIO, \ + .int_src = I2C4_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C4_RX_DMA_CONFIG */ #endif /* BSP_I2C4_USING_DMA */ @@ -225,50 +217,48 @@ extern "C" { #if defined(BSP_USING_I2C5) #ifndef I2C5_CONFIG -#define I2C5_CONFIG \ - { \ - .name = "i2c5", \ - .Instance = CM_I2C5, \ - .clock = FCG1_PERIPH_I2C5, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C5_CONFIG \ + { \ + .name = "i2c5", \ + .Instance = CM_I2C5, \ + .clock = FCG1_PERIPH_I2C5, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C5_CONFIG */ #if defined(BSP_I2C5_USING_DMA) #ifndef I2C5_TX_DMA_CONFIG -#define I2C5_TX_DMA_CONFIG \ - { \ - .Instance = I2C5_TX_DMA_INSTANCE, \ - .channel = I2C5_TX_DMA_CHANNEL, \ - .clock = I2C5_TX_DMA_CLOCK, \ - .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C5_TEI, \ - .flag = I2C5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C5_TX_DMA_IRQn, \ - .irq_prio = I2C5_TX_DMA_INT_PRIO, \ - .int_src = I2C5_TX_DMA_INT_SRC, \ - }, \ +#define I2C5_TX_DMA_CONFIG \ + { \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .channel = I2C5_TX_DMA_CHANNEL, \ + .clock = I2C5_TX_DMA_CLOCK, \ + .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_TEI, \ + .flag = I2C5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_TX_DMA_IRQn, \ + .irq_prio = I2C5_TX_DMA_INT_PRIO, \ + .int_src = I2C5_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C5_TX_DMA_CONFIG */ #ifndef I2C5_RX_DMA_CONFIG -#define I2C5_RX_DMA_CONFIG \ - { \ - .Instance = I2C5_RX_DMA_INSTANCE, \ - .channel = I2C5_RX_DMA_CHANNEL, \ - .clock = I2C5_RX_DMA_CLOCK, \ - .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C5_RXI, \ - .flag = I2C5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C5_RX_DMA_IRQn, \ - .irq_prio = I2C5_RX_DMA_INT_PRIO, \ - .int_src = I2C5_RX_DMA_INT_SRC, \ - }, \ +#define I2C5_RX_DMA_CONFIG \ + { \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .channel = I2C5_RX_DMA_CHANNEL, \ + .clock = I2C5_RX_DMA_CLOCK, \ + .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_RXI, \ + .flag = I2C5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_RX_DMA_IRQn, \ + .irq_prio = I2C5_RX_DMA_INT_PRIO, \ + .int_src = I2C5_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C5_RX_DMA_CONFIG */ #endif /* BSP_I2C5_USING_DMA */ @@ -276,50 +266,48 @@ extern "C" { #if defined(BSP_USING_I2C6) #ifndef I2C6_CONFIG -#define I2C6_CONFIG \ - { \ - .name = "i2c6", \ - .Instance = CM_I2C6, \ - .clock = FCG1_PERIPH_I2C6, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C6_CONFIG \ + { \ + .name = "i2c6", \ + .Instance = CM_I2C6, \ + .clock = FCG1_PERIPH_I2C6, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C6_CONFIG */ #if defined(BSP_I2C6_USING_DMA) #ifndef I2C6_TX_DMA_CONFIG -#define I2C6_TX_DMA_CONFIG \ - { \ - .Instance = I2C6_TX_DMA_INSTANCE, \ - .channel = I2C6_TX_DMA_CHANNEL, \ - .clock = I2C6_TX_DMA_CLOCK, \ - .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C6_TEI, \ - .flag = I2C6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C6_TX_DMA_IRQn, \ - .irq_prio = I2C6_TX_DMA_INT_PRIO, \ - .int_src = I2C6_TX_DMA_INT_SRC, \ - }, \ +#define I2C6_TX_DMA_CONFIG \ + { \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .channel = I2C6_TX_DMA_CHANNEL, \ + .clock = I2C6_TX_DMA_CLOCK, \ + .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_TEI, \ + .flag = I2C6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_TX_DMA_IRQn, \ + .irq_prio = I2C6_TX_DMA_INT_PRIO, \ + .int_src = I2C6_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C6_TX_DMA_CONFIG */ #ifndef I2C6_RX_DMA_CONFIG -#define I2C6_RX_DMA_CONFIG \ - { \ - .Instance = I2C6_RX_DMA_INSTANCE, \ - .channel = I2C6_RX_DMA_CHANNEL, \ - .clock = I2C6_RX_DMA_CLOCK, \ - .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C6_RXI, \ - .flag = I2C6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C6_RX_DMA_IRQn, \ - .irq_prio = I2C6_RX_DMA_INT_PRIO, \ - .int_src = I2C6_RX_DMA_INT_SRC, \ - }, \ +#define I2C6_RX_DMA_CONFIG \ + { \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .channel = I2C6_RX_DMA_CHANNEL, \ + .clock = I2C6_RX_DMA_CLOCK, \ + .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_RXI, \ + .flag = I2C6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_RX_DMA_IRQn, \ + .irq_prio = I2C6_RX_DMA_INT_PRIO, \ + .int_src = I2C6_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C6_RX_DMA_CONFIG */ #endif /* BSP_I2C6_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h index 48e1c60796f..519895d1367 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/irq_config.h @@ -18,324 +18,324 @@ extern "C" { #endif -#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn -#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn -#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn -#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn -#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn -#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn -#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn -#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn -#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn -#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn -#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn -#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn -#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn -#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn -#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn -#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn -#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT0_IRQ_NUM EXTINT_PORT_EIRQ0_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM EXTINT_PORT_EIRQ1_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM EXTINT_PORT_EIRQ2_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM EXTINT_PORT_EIRQ3_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM EXTINT_PORT_EIRQ4_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM EXTINT_PORT_EIRQ5_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM EXTINT_PORT_EIRQ6_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM EXTINT_PORT_EIRQ7_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM EXTINT_PORT_EIRQ8_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM EXTINT_PORT_EIRQ9_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM EXTINT_PORT_EIRQ10_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM EXTINT_PORT_EIRQ11_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM EXTINT_PORT_EIRQ12_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM EXTINT_PORT_EIRQ13_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM EXTINT_PORT_EIRQ14_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM EXTINT_PORT_EIRQ15_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch0 */ -#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn -#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH0_IRQ_NUM INT000_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch1 */ -#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn -#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH1_IRQ_NUM INT001_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch2 */ -#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn -#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH2_IRQ_NUM INT002_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch3 */ -#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn -#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH3_IRQ_NUM INT003_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch4 */ -#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn -#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH4_IRQ_NUM INT004_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch5 */ -#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn -#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH5_IRQ_NUM INT005_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch0 */ -#define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn -#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH0_IRQ_NUM INT006_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch1 */ -#define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn -#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH1_IRQ_NUM INT007_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch2 */ -#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn -#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH2_IRQ_NUM INT008_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch3 */ -#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn -#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH3_IRQ_NUM INT009_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch4 */ -#define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn -#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH4_IRQ_NUM INT010_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch5 */ -#define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn -#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH5_IRQ_NUM INT011_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_USING_UART1) -#define BSP_UART1_IRQ_NUM USART1_IRQn -#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_IRQ_NUM USART1_IRQn +#define BSP_UART1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM USART1_TCI_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) -#define BSP_UART2_IRQ_NUM USART2_IRQn -#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_IRQ_NUM USART2_IRQn +#define BSP_UART2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM USART2_TCI_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) -#define BSP_UART3_IRQ_NUM USART3_IRQn -#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_IRQ_NUM USART3_IRQn +#define BSP_UART3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART3 */ #if defined(BSP_USING_UART4) -#define BSP_UART4_IRQ_NUM USART4_IRQn -#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_IRQ_NUM USART4_IRQn +#define BSP_UART4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn -#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_CPLT_IRQ_NUM USART4_TCI_IRQn +#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_UART5) -#define BSP_UART5_IRQ_NUM USART5_IRQn -#define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_IRQ_NUM USART5_IRQn +#define BSP_UART5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if (defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA)) || \ defined(RT_USING_SERIAL_V2) -#define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn -#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_CPLT_IRQ_NUM USART5_TCI_IRQn +#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART5 */ #if defined(BSP_USING_UART6) -#define BSP_UART6_IRQ_NUM USART6_IRQn -#define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_IRQ_NUM USART6_IRQn +#define BSP_UART6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART6 */ #if defined(BSP_USING_SPI1) -#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn -#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI1_ERR_IRQ_NUM SPI1_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI2) -#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn -#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM SPI2_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI3) -#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn -#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI3_ERR_IRQ_NUM SPI3_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI4) -#define BSP_SPI4_ERR_IRQ_NUM SPI4_IRQn -#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI4_ERR_IRQ_NUM SPI4_IRQn +#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif -#if defined (BSP_USING_QSPI) -#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn -#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#if defined(BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM QSPI_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_QSPI */ #if defined(BSP_USING_TMRA_1) -#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn -#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_1_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_1 */ #if defined(BSP_USING_TMRA_2) -#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn -#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_2_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_2 */ #if defined(BSP_USING_TMRA_3) -#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn -#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_3_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_3 */ #if defined(BSP_USING_TMRA_4) -#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn -#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_4_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_4 */ #if defined(BSP_USING_TMRA_5) -#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn -#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_5_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_5 */ #if defined(BSP_USING_TMRA_6) -#define BSP_USING_TMRA_6_IRQ_NUM TMRA_6_OVF_UDF_IRQn -#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_6_IRQ_NUM TMRA_6_OVF_UDF_IRQn +#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_6 */ #if defined(BSP_USING_CAN1) -#define BSP_CAN1_IRQ_NUM CAN1_INT_IRQn -#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_CAN1_IRQ_NUM CAN1_INT_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_CAN1 */ #if defined(BSP_USING_CAN2) -#define BSP_CAN2_IRQ_NUM CAN2_INT_IRQn -#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_CAN2_IRQ_NUM CAN2_INT_IRQn +#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_CAN2 */ #if defined(BSP_USING_CAN3) -#define BSP_CAN3_IRQ_NUM CAN3_INT_IRQn -#define BSP_CAN3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_CAN3_IRQ_NUM CAN3_INT_IRQn +#define BSP_CAN3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_CAN3 */ #if defined(RT_USING_ALARM) -#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn -#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_RTC_ALARM_IRQ_NUM RTC_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* RT_USING_ALARM */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM TMRA_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_2) -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM TMRA_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_3) -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM TMRA_3_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_4) -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM TMRA_4_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_5) -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM TMRA_5_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_6) -#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM TMRA_6_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM TMRA_6_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM TMRA_6_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM TMRA_6_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM TMR6_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM TMR6_1_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_2) -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM TMR6_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM TMR6_2_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_3) -#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM TMR6_3_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM TMR6_3_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM TMR6_3_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM TMR6_3_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_4) -#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM TMR6_4_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM TMR6_4_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM TMR6_4_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM TMR6_4_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_5) -#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM TMR6_5_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM TMR6_5_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM TMR6_5_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM TMR6_5_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_6) -#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM TMR6_6_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM TMR6_6_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM TMR6_6_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM TMR6_6_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_6 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_7) -#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM TMR6_7_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM TMR6_7_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM TMR6_7_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM TMR6_7_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_7 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_8) -#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM TMR6_8_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM TMR6_8_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM TMR6_8_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM TMR6_8_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_8 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_9) -#define BSP_PULSE_ENCODER_TMR6_9_OVF_IRQ_NUM TMR6_9_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_9_UDF_IRQ_NUM TMR6_9_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_9_OVF_IRQ_NUM TMR6_9_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_9_UDF_IRQ_NUM TMR6_9_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_9 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_10) -#define BSP_PULSE_ENCODER_TMR6_10_OVF_IRQ_NUM TMR6_10_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_10_UDF_IRQ_NUM TMR6_10_OVF_UDF_IRQn -#define BSP_PULSE_ENCODER_TMR6_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_10_OVF_IRQ_NUM TMR6_10_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_10_UDF_IRQ_NUM TMR6_10_OVF_UDF_IRQn +#define BSP_PULSE_ENCODER_TMR6_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_10 */ #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) -#define BSP_USBFS_GLB_IRQ_NUM USBFS_GLB_IRQn -#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USBFS_GLB_IRQ_NUM USBFS_GLB_IRQn +#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_INPUT_CAPTURE) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_NUM (INT010_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_NUM (INT011_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_NUM (INT010_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_NUM (INT011_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #endif/* BSP_USING_INPUT_CAPTURE */ #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h index df1ee98de31..9cf973f2227 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pm_config.h @@ -22,18 +22,18 @@ extern "C" { extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); #ifndef PM_TICKLESS_TIMER_ENABLE_MASK -#define PM_TICKLESS_TIMER_ENABLE_MASK \ -( (1UL << PM_SLEEP_MODE_IDLE) | \ - (1UL << PM_SLEEP_MODE_DEEP)) +#define PM_TICKLESS_TIMER_ENABLE_MASK \ + ((1UL << PM_SLEEP_MODE_IDLE) | \ + (1UL << PM_SLEEP_MODE_DEEP)) #endif /** * @brief run mode config @ref pm_run_mode_config structure */ #ifndef PM_RUN_MODE_CFG -#define PM_RUN_MODE_CFG \ - { \ - .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ } #endif /* PM_RUN_MODE_CFG */ @@ -41,51 +41,51 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); * @brief sleep idle config @ref pm_sleep_mode_idle_config structure */ #ifndef PM_SLEEP_IDLE_CFG -#define PM_SLEEP_IDLE_CFG \ -{ \ - .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ -} +#define PM_SLEEP_IDLE_CFG \ + { \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ + } #endif /*PM_SLEEP_IDLE_CFG*/ /** * @brief sleep deep config @ref pm_sleep_mode_deep_config structure */ #ifndef PM_SLEEP_DEEP_CFG -#define PM_SLEEP_DEEP_CFG \ -{ \ - { \ - .u16Clock = PWC_STOP_CLK_KEEP, \ - .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ - .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ - }, \ - .pwc_stop_type = PWC_STOP_WFE_INT, \ -} +#define PM_SLEEP_DEEP_CFG \ + { \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ + } #endif /*PM_SLEEP_DEEP_CFG*/ /** * @brief sleep standby config @ref pm_sleep_mode_standby_config structure */ #ifndef PM_SLEEP_STANDBY_CFG -#define PM_SLEEP_STANDBY_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD1, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - }, \ -} +#define PM_SLEEP_STANDBY_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + }, \ + } #endif /*PM_SLEEP_STANDBY_CFG*/ /** * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure */ #ifndef PM_SLEEP_SHUTDOWN_CFG -#define PM_SLEEP_SHUTDOWN_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD3, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - }, \ -} +#define PM_SLEEP_SHUTDOWN_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + }, \ + } #endif /*PM_SLEEP_SHUTDOWN_CFG*/ #endif /* BSP_USING_PM */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pulse_encoder_config.h index 38463229628..df7da3f5153 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pulse_encoder_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pulse_encoder_config.h @@ -22,416 +22,384 @@ extern "C" { #ifdef BSP_USING_PULSE_ENCODER_TMRA_1 #ifndef PULSE_ENCODER_TMRA_1_CONFIG -#define PULSE_ENCODER_TMRA_1_CONFIG \ - { \ - .tmr_handler = CM_TMRA_1, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a1" \ +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ } #endif /* PULSE_ENCODER_TMRA_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_2 #ifndef PULSE_ENCODER_TMRA_2_CONFIG -#define PULSE_ENCODER_TMRA_2_CONFIG \ - { \ - .tmr_handler = CM_TMRA_2, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a2" \ +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ } #endif /* PULSE_ENCODER_TMRA_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_3 #ifndef PULSE_ENCODER_TMRA_3_CONFIG -#define PULSE_ENCODER_TMRA_3_CONFIG \ - { \ - .tmr_handler = CM_TMRA_3, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a3" \ +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ } #endif /* PULSE_ENCODER_TMRA_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_4 #ifndef PULSE_ENCODER_TMRA_4_CONFIG -#define PULSE_ENCODER_TMRA_4_CONFIG \ - { \ - .tmr_handler = CM_TMRA_4, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a4" \ +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ } #endif /* PULSE_ENCODER_TMRA_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_5 #ifndef PULSE_ENCODER_TMRA_5_CONFIG -#define PULSE_ENCODER_TMRA_5_CONFIG \ - { \ - .tmr_handler = CM_TMRA_5, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a5" \ +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ } #endif /* PULSE_ENCODER_TMRA_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_6 #ifndef PULSE_ENCODER_TMRA_6_CONFIG -#define PULSE_ENCODER_TMRA_6_CONFIG \ - { \ - .tmr_handler = CM_TMRA_6, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a6" \ +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ } #endif /* PULSE_ENCODER_TMRA_6_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_1 #ifndef PULSE_ENCODER_TMR6_1_CONFIG -#define PULSE_ENCODER_TMR6_1_CONFIG \ - { \ - .tmr_handler = CM_TMR6_1, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_61" \ +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ } #endif /* PULSE_ENCODER_TMR6_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_2 #ifndef PULSE_ENCODER_TMR6_2_CONFIG -#define PULSE_ENCODER_TMR6_2_CONFIG \ - { \ - .tmr_handler = CM_TMR6_2, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_62" \ +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ } #endif /* PULSE_ENCODER_TMR6_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_3 #ifndef PULSE_ENCODER_TMR6_3_CONFIG -#define PULSE_ENCODER_TMR6_3_CONFIG \ - { \ - .tmr_handler = CM_TMR6_3, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_63" \ +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ } #endif /* PULSE_ENCODER_TMR6_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_4 #ifndef PULSE_ENCODER_TMR6_4_CONFIG -#define PULSE_ENCODER_TMR6_4_CONFIG \ - { \ - .tmr_handler = CM_TMR6_4, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_4, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_64" \ +#define PULSE_ENCODER_TMR6_4_CONFIG \ + { \ + .tmr_handler = CM_TMR6_4, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_4, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_64" \ } #endif /* PULSE_ENCODER_TMR6_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_5 #ifndef PULSE_ENCODER_TMR6_5_CONFIG -#define PULSE_ENCODER_TMR6_5_CONFIG \ - { \ - .tmr_handler = CM_TMR6_5, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_5, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_65" \ +#define PULSE_ENCODER_TMR6_5_CONFIG \ + { \ + .tmr_handler = CM_TMR6_5, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_5, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_65" \ } #endif /* PULSE_ENCODER_TMR6_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_6 #ifndef PULSE_ENCODER_TMR6_6_CONFIG -#define PULSE_ENCODER_TMR6_6_CONFIG \ - { \ - .tmr_handler = CM_TMR6_6, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_6, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_66" \ +#define PULSE_ENCODER_TMR6_6_CONFIG \ + { \ + .tmr_handler = CM_TMR6_6, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_6, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_66" \ } #endif /* PULSE_ENCODER_TMR6_6_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_7 #ifndef PULSE_ENCODER_TMR6_7_CONFIG -#define PULSE_ENCODER_TMR6_7_CONFIG \ - { \ - .tmr_handler = CM_TMR6_7, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_7, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_67" \ +#define PULSE_ENCODER_TMR6_7_CONFIG \ + { \ + .tmr_handler = CM_TMR6_7, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_7, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_67" \ } #endif /* PULSE_ENCODER_TMR6_7_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_8 #ifndef PULSE_ENCODER_TMR6_8_CONFIG -#define PULSE_ENCODER_TMR6_8_CONFIG \ - { \ - .tmr_handler = CM_TMR6_8, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_8, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_68" \ +#define PULSE_ENCODER_TMR6_8_CONFIG \ + { \ + .tmr_handler = CM_TMR6_8, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_8, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_68" \ } #endif /* PULSE_ENCODER_TMR6_8_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_9 #ifndef PULSE_ENCODER_TMR6_9_CONFIG -#define PULSE_ENCODER_TMR6_9_CONFIG \ - { \ - .tmr_handler = CM_TMR6_9, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_9, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_9_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_9_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_9_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_9_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_9_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_9_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_69" \ +#define PULSE_ENCODER_TMR6_9_CONFIG \ + { \ + .tmr_handler = CM_TMR6_9, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_9, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_9_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_9_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_9_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_9_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_9_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_9_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_69" \ } #endif /* PULSE_ENCODER_TMR6_9_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_9 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_10 #ifndef PULSE_ENCODER_TMR6_10_CONFIG -#define PULSE_ENCODER_TMR6_10_CONFIG \ - { \ - .tmr_handler = CM_TMR6_10, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_10, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_10_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_10_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_10_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_10_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_10_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_10_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_6a" \ +#define PULSE_ENCODER_TMR6_10_CONFIG \ + { \ + .tmr_handler = CM_TMR6_10, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_10, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_10_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_10_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_10_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_10_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_10_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_10_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_6a" \ } #endif /* PULSE_ENCODER_TMR6_10_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_10 */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pwm_tmr_config.h index c77f7e6bbd3..c68b666fc40 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/pwm_tmr_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/pwm_tmr_config.h @@ -22,186 +22,162 @@ extern "C" { #ifdef BSP_USING_PWM_TMRA_1 #ifndef PWM_TMRA_1_CONFIG -#define PWM_TMRA_1_CONFIG \ - { \ - .name = "pwm_a1", \ - .instance = CM_TMRA_1, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_1_CONFIG */ #endif /* BSP_USING_PWM_TMRA_1 */ #ifdef BSP_USING_PWM_TMRA_2 #ifndef PWM_TMRA_2_CONFIG -#define PWM_TMRA_2_CONFIG \ - { \ - .name = "pwm_a2", \ - .instance = CM_TMRA_2, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_2_CONFIG */ #endif /* BSP_USING_PWM_TMRA_2 */ #ifdef BSP_USING_PWM_TMRA_3 #ifndef PWM_TMRA_3_CONFIG -#define PWM_TMRA_3_CONFIG \ - { \ - .name = "pwm_a3", \ - .instance = CM_TMRA_3, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_3_CONFIG */ #endif /* BSP_USING_PWM_TMRA_3 */ #ifdef BSP_USING_PWM_TMRA_4 #ifndef PWM_TMRA_4_CONFIG -#define PWM_TMRA_4_CONFIG \ - { \ - .name = "pwm_a4", \ - .instance = CM_TMRA_4, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_4_CONFIG */ #endif /* BSP_USING_PWM_TMRA_4 */ #ifdef BSP_USING_PWM_TMRA_5 #ifndef PWM_TMRA_5_CONFIG -#define PWM_TMRA_5_CONFIG \ - { \ - .name = "pwm_a5", \ - .instance = CM_TMRA_5, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_5_CONFIG */ #endif /* BSP_USING_PWM_TMRA_5 */ #ifdef BSP_USING_PWM_TMRA_6 #ifndef PWM_TMRA_6_CONFIG -#define PWM_TMRA_6_CONFIG \ - { \ - .name = "pwm_a6", \ - .instance = CM_TMRA_6, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_6_CONFIG */ #endif /* BSP_USING_PWM_TMRA_6 */ @@ -212,32 +188,29 @@ extern "C" { #ifdef BSP_USING_PWM_TMR4_1 #ifndef PWM_TMR4_1_CONFIG -#define PWM_TMR4_1_CONFIG \ - { \ - .name = "pwm_t41", \ - .instance = CM_TMR4, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_PEAK, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_1_CONFIG */ #endif /* BSP_USING_PWM_TMR4_1 */ @@ -248,471 +221,421 @@ extern "C" { #ifdef BSP_USING_PWM_TMR6_1 #ifndef PWM_TMR6_1_CONFIG -#define PWM_TMR6_1_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_1, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_1_CONFIG */ #endif /* BSP_USING_PWM_TMR6_1 */ #ifdef BSP_USING_PWM_TMR6_2 #ifndef PWM_TMR6_2_CONFIG -#define PWM_TMR6_2_CONFIG \ - { \ - .name = "pwm_t62", \ - .instance = CM_TMR6_2, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t62", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_2_CONFIG */ #endif /* BSP_USING_PWM_TMR6_2 */ #ifdef BSP_USING_PWM_TMR6_3 #ifndef PWM_TMR6_3_CONFIG -#define PWM_TMR6_3_CONFIG \ - { \ - .name = "pwm_t63", \ - .instance = CM_TMR6_3, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t63", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_3_CONFIG */ #endif /* BSP_USING_PWM_TMR6_3 */ #ifdef BSP_USING_PWM_TMR6_4 #ifndef PWM_TMR6_4_CONFIG -#define PWM_TMR6_4_CONFIG \ - { \ - .name = "pwm_t64", \ - .instance = CM_TMR6_4, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t64", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_4_CONFIG */ #endif /* BSP_USING_PWM_TMR6_4 */ #ifdef BSP_USING_PWM_TMR6_5 #ifndef PWM_TMR6_5_CONFIG -#define PWM_TMR6_5_CONFIG \ - { \ - .name = "pwm_t65", \ - .instance = CM_TMR6_5, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_5_CONFIG \ + { \ + .name = "pwm_t65", \ + .instance = CM_TMR6_5, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_5_CONFIG */ #endif /* BSP_USING_PWM_TMR6_5 */ #ifdef BSP_USING_PWM_TMR6_6 #ifndef PWM_TMR6_6_CONFIG -#define PWM_TMR6_6_CONFIG \ - { \ - .name = "pwm_t66", \ - .instance = CM_TMR6_6, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_6_CONFIG \ + { \ + .name = "pwm_t66", \ + .instance = CM_TMR6_6, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_6_CONFIG */ #endif /* BSP_USING_PWM_TMR6_6 */ #ifdef BSP_USING_PWM_TMR6_7 #ifndef PWM_TMR6_7_CONFIG -#define PWM_TMR6_7_CONFIG \ - { \ - .name = "pwm_t67", \ - .instance = CM_TMR6_7, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_7_CONFIG \ + { \ + .name = "pwm_t67", \ + .instance = CM_TMR6_7, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_7_CONFIG */ #endif /* BSP_USING_PWM_TMR6_7 */ #ifdef BSP_USING_PWM_TMR6_8 #ifndef PWM_TMR6_8_CONFIG -#define PWM_TMR6_8_CONFIG \ - { \ - .name = "pwm_t68", \ - .instance = CM_TMR6_8, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_8_CONFIG \ + { \ + .name = "pwm_t68", \ + .instance = CM_TMR6_8, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_8_CONFIG */ #endif /* BSP_USING_PWM_TMR6_8 */ #ifdef BSP_USING_PWM_TMR6_9 #ifndef PWM_TMR6_9_CONFIG -#define PWM_TMR6_9_CONFIG \ - { \ - .name = "pwm_t69", \ - .instance = CM_TMR6_9, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_9_CONFIG \ + { \ + .name = "pwm_t69", \ + .instance = CM_TMR6_9, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_9_CONFIG */ #endif /* BSP_USING_PWM_TMR6_9 */ #ifdef BSP_USING_PWM_TMR6_10 #ifndef PWM_TMR6_10_CONFIG -#define PWM_TMR6_10_CONFIG \ - { \ - .name = "pwm_t610", \ - .instance = CM_TMR6_10, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_DOWN, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_LOW, \ - .u32StopPolarity = TMR6_PWM_LOW, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ - .u32UdfPolarity = TMR6_PWM_LOW, \ - .u32OvfPolarity = TMR6_PWM_LOW, \ - } \ - }, \ +#define PWM_TMR6_10_CONFIG \ + { \ + .name = "pwm_t610", \ + .instance = CM_TMR6_10, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_DOWN, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_LOW, \ + .u32StopPolarity = TMR6_PWM_LOW, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HIGH, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HIGH, \ + .u32UdfPolarity = TMR6_PWM_LOW, \ + .u32OvfPolarity = TMR6_PWM_LOW, \ + } }, \ } #endif /* PWM_TMR6_10_CONFIG */ #endif /* BSP_USING_PWM_TMR6_10 */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/qspi_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/qspi_config.h index 71199a0c7ce..3c82140073c 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/qspi_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/qspi_config.h @@ -21,48 +21,46 @@ extern "C" { #ifdef BSP_USING_QSPI #ifndef QSPI_BUS_CONFIG -#define QSPI_BUS_CONFIG \ - { \ - .Instance = CM_QSPI, \ - .clock = FCG1_PERIPH_QSPI, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ - .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_QSPI_INTR, \ - }, \ +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ } #endif /* QSPI_BUS_CONFIG */ #ifndef QSPI_INIT_PARAMS -#define QSPI_INIT_PARAMS \ - { \ - .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ - .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ - .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ - .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ } #endif /* QSPI_INIT_PARAMS */ -#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH #ifdef BSP_QSPI_USING_DMA #ifndef QSPI_DMA_CONFIG -#define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .channel = QSPI_DMA_CHANNEL, \ - .clock = QSPI_DMA_CLOCK, \ - .trigger_select = QSPI_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_AOS_STRG, \ - .flag = QSPI_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = QSPI_DMA_IRQn, \ - .irq_prio = QSPI_DMA_INT_PRIO, \ - .int_src = QSPI_DMA_INT_SRC, \ - } \ +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ } #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/spi_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/spi_config.h index e49988e8fff..ae979d9b01f 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/spi_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/spi_config.h @@ -22,134 +22,127 @@ extern "C" { #ifdef BSP_USING_SPI1 #ifndef SPI1_BUS_CONFIG -#define SPI1_BUS_CONFIG \ - { \ - .Instance = CM_SPI1, \ - .bus_name = "spi1", \ - .clock = FCG1_PERIPH_SPI1, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI1_SPEI, \ - }, \ +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .clock = SPI1_TX_DMA_CLOCK, \ - .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPTI, \ - .flag = SPI1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_TX_DMA_IRQn, \ - .irq_prio = SPI1_TX_DMA_INT_PRIO, \ - .int_src = SPI1_TX_DMA_INT_SRC, \ - } \ +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .clock = SPI1_RX_DMA_CLOCK, \ - .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPRI, \ - .flag = SPI1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_RX_DMA_IRQn, \ - .irq_prio = SPI1_RX_DMA_INT_PRIO, \ - .int_src = SPI1_RX_DMA_INT_SRC, \ - } \ +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 #ifndef SPI2_BUS_CONFIG -#define SPI2_BUS_CONFIG \ - { \ - .Instance = CM_SPI2, \ - .bus_name = "spi2", \ - .clock = FCG1_PERIPH_SPI2, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI2_SPEI, \ - }, \ +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .channel = SPI2_TX_DMA_CHANNEL, \ - .clock = SPI2_TX_DMA_CLOCK, \ - .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPTI, \ - .flag = SPI2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_TX_DMA_IRQn, \ - .irq_prio = SPI2_TX_DMA_INT_PRIO, \ - .int_src = SPI2_TX_DMA_INT_SRC, \ - } \ +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .channel = SPI2_RX_DMA_CHANNEL, \ - .clock = SPI2_RX_DMA_CLOCK, \ - .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPRI, \ - .flag = SPI2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_RX_DMA_IRQn, \ - .irq_prio = SPI2_RX_DMA_INT_PRIO, \ - .int_src = SPI2_RX_DMA_INT_SRC, \ - } \ +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 #ifndef SPI3_BUS_CONFIG -#define SPI3_BUS_CONFIG \ - { \ - .Instance = CM_SPI3, \ - .bus_name = "spi3", \ - .clock = FCG1_PERIPH_SPI3, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI3_SPEI, \ - }, \ +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ @@ -157,98 +150,93 @@ extern "C" { #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .channel = SPI3_TX_DMA_CHANNEL, \ - .clock = SPI3_TX_DMA_CLOCK, \ - .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPTI, \ - .flag = SPI3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_TX_DMA_IRQn, \ - .irq_prio = SPI3_TX_DMA_INT_PRIO, \ - .int_src = SPI3_TX_DMA_INT_SRC, \ - } \ +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .channel = SPI3_RX_DMA_CHANNEL, \ - .clock = SPI3_RX_DMA_CLOCK, \ - .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPRI, \ - .flag = SPI3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_RX_DMA_IRQn, \ - .irq_prio = SPI3_RX_DMA_INT_PRIO, \ - .int_src = SPI3_RX_DMA_INT_SRC, \ - } \ +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ #ifdef BSP_USING_SPI4 #ifndef SPI4_BUS_CONFIG -#define SPI4_BUS_CONFIG \ - { \ - .Instance = CM_SPI4, \ - .bus_name = "spi4", \ - .clock = FCG1_PERIPH_SPI4, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI4_SPEI, \ - }, \ +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ } #endif /* SPI4_BUS_CONFIG */ #endif /* BSP_USING_SPI4 */ #ifdef BSP_SPI4_TX_USING_DMA #ifndef SPI4_TX_DMA_CONFIG -#define SPI4_TX_DMA_CONFIG \ - { \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .channel = SPI4_TX_DMA_CHANNEL, \ - .clock = SPI4_TX_DMA_CLOCK, \ - .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI4_SPTI, \ - .flag = SPI4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI4_TX_DMA_IRQn, \ - .irq_prio = SPI4_TX_DMA_INT_PRIO, \ - .int_src = SPI4_TX_DMA_INT_SRC, \ - } \ +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ #ifdef BSP_SPI4_RX_USING_DMA #ifndef SPI4_RX_DMA_CONFIG -#define SPI4_RX_DMA_CONFIG \ - { \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .channel = SPI4_RX_DMA_CHANNEL, \ - .clock = SPI4_RX_DMA_CLOCK, \ - .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI4_SPRI, \ - .flag = SPI4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI4_RX_DMA_IRQn, \ - .irq_prio = SPI4_RX_DMA_INT_PRIO, \ - .int_src = SPI4_RX_DMA_INT_SRC, \ - } \ +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/timer_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/timer_config.h index eb019f41ec6..1fdd2af5d67 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/timer_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/timer_config.h @@ -20,114 +20,108 @@ extern "C" { #ifdef BSP_USING_TMRA_1 #ifndef TMRA_1_CONFIG -#define TMRA_1_CONFIG \ - { \ - .tmr_handle = CM_TMRA_1, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_1, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_1_OVF, \ - .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ - }, \ - .name = "tmra_1" \ +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ } #endif /* TMRA_1_CONFIG */ #endif /* BSP_USING_TMRA_1 */ #ifdef BSP_USING_TMRA_2 #ifndef TMRA_2_CONFIG -#define TMRA_2_CONFIG \ - { \ - .tmr_handle = CM_TMRA_2, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_2, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_2_OVF, \ - .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ - }, \ - .name = "tmra_2" \ +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ } #endif /* TMRA_2_CONFIG */ #endif /* BSP_USING_TMRA_2 */ #ifdef BSP_USING_TMRA_3 #ifndef TMRA_3_CONFIG -#define TMRA_3_CONFIG \ - { \ - .tmr_handle = CM_TMRA_3, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_3, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_3_OVF, \ - .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ - }, \ - .name = "tmra_3" \ +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ } #endif /* TMRA_3_CONFIG */ #endif /* BSP_USING_TMRA_3 */ #ifdef BSP_USING_TMRA_4 #ifndef TMRA_4_CONFIG -#define TMRA_4_CONFIG \ - { \ - .tmr_handle = CM_TMRA_4, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_4, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_4_OVF, \ - .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ - }, \ - .name = "tmra_4" \ +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ } #endif /* TMRA_4_CONFIG */ #endif /* BSP_USING_TMRA_4 */ #ifdef BSP_USING_TMRA_5 #ifndef TMRA_5_CONFIG -#define TMRA_5_CONFIG \ - { \ - .tmr_handle = CM_TMRA_5, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_5, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_5_OVF, \ - .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ - }, \ - .name = "tmra_5" \ +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ } #endif /* TMRA_5_CONFIG */ #endif /* BSP_USING_TMRA_5 */ #ifdef BSP_USING_TMRA_6 #ifndef TMRA_6_CONFIG -#define TMRA_6_CONFIG \ - { \ - .tmr_handle = CM_TMRA_6, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_6, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_6_OVF, \ - .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ - }, \ - .name = "tmra_6" \ +#define TMRA_6_CONFIG \ + { \ + .tmr_handle = CM_TMRA_6, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_6, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_6_OVF, \ + .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ + }, \ + .name = "tmra_6" \ } #endif /* TMRA_6_CONFIG */ #endif /* BSP_USING_TMRA_6 */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/tmr_capture_config.h index 089d106ae87..2e626308b6c 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/tmr_capture_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/tmr_capture_config.h @@ -17,49 +17,49 @@ extern "C" { #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) #define IC1_NAME "ic1" -#define INPUT_CAPTURE_CFG_TMR6_1 \ -{ \ - .name = IC1_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_1 \ + { \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) #define IC2_NAME "ic2" -#define INPUT_CAPTURE_CFG_TMR6_2 \ -{ \ - .name = IC2_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_2 \ + { \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_10) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_10) #define IC10_NAME "ic10" -#define INPUT_CAPTURE_CFG_TMR6_10 \ -{ \ - .name = IC10_NAME, \ - .ch = TMR6_CH_B, \ - .clk_div = TMR6_CLK_DIV16, \ - .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_10 \ + { \ + .name = IC10_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_10_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_10_OVF_IRQ_PRIO, \ + } #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/uart_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/uart_config.h index c1ac81ae9eb..a660ea957e0 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/uart_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/uart_config.h @@ -22,90 +22,86 @@ extern "C" { #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = CM_USART1, \ - .clock = FCG3_PERIPH_USART1, \ - .irq_num = BSP_UART1_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART1_EI, \ - .rx_int_src = INT_SRC_USART1_RI, \ - .tx_int_src = INT_SRC_USART1_TI, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .irq_num = BSP_UART1_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART1_EI, \ + .rx_int_src = INT_SRC_USART1_RI, \ + .tx_int_src = INT_SRC_USART1_TI, \ } #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .clock = UART1_RX_DMA_CLOCK, \ - .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_RI, \ - .flag = UART1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_RX_DMA_IRQn, \ - .irq_prio = UART1_RX_DMA_INT_PRIO, \ - .int_src = UART1_RX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_RX_CONFIG */ #ifndef UART1_RXTO_CONFIG -#define UART1_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ } #endif /* UART1_RXTO_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #endif /* UART1_TX_CPLT_CONFIG */ #if defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .clock = UART1_TX_DMA_CLOCK, \ - .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_TI, \ - .flag = UART1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_TX_DMA_IRQn, \ - .irq_prio = UART1_TX_DMA_INT_PRIO, \ - .int_src = UART1_TX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -113,90 +109,86 @@ extern "C" { #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = CM_USART2, \ - .clock = FCG3_PERIPH_USART2, \ - .irq_num = BSP_UART2_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART2_EI, \ - .rx_int_src = INT_SRC_USART2_RI, \ - .tx_int_src = INT_SRC_USART2_TI, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .irq_num = BSP_UART2_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART2_EI, \ + .rx_int_src = INT_SRC_USART2_RI, \ + .tx_int_src = INT_SRC_USART2_TI, \ } #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .clock = UART2_RX_DMA_CLOCK, \ - .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_RI, \ - .flag = UART2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_RX_DMA_IRQn, \ - .irq_prio = UART2_RX_DMA_INT_PRIO, \ - .int_src = UART2_RX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_RX_CONFIG */ #ifndef UART2_RXTO_CONFIG -#define UART2_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ } #endif /* UART2_RXTO_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #endif /* UART2_TX_CPLT_CONFIG */ #if defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .clock = UART2_TX_DMA_CLOCK, \ - .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_TI, \ - .flag = UART2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_TX_DMA_IRQn, \ - .irq_prio = UART2_TX_DMA_INT_PRIO, \ - .int_src = UART2_TX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -204,28 +196,27 @@ extern "C" { #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = CM_USART3, \ - .clock = FCG3_PERIPH_USART3, \ - .irq_num = BSP_UART3_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART3_EI, \ - .rx_int_src = INT_SRC_USART3_RI, \ - .tx_int_src = INT_SRC_USART3_TI, \ +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .irq_num = BSP_UART3_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART3_EI, \ + .rx_int_src = INT_SRC_USART3_RI, \ + .tx_int_src = INT_SRC_USART3_TI, \ } #endif /* UART3_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART3_TX_CPLT_CONFIG -#define UART3_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TCI, \ - }, \ +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ } #endif #endif /* UART3_TX_CPLT_CONFIG */ @@ -233,90 +224,86 @@ extern "C" { #if defined(BSP_USING_UART4) #ifndef UART4_CONFIG -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = CM_USART4, \ - .clock = FCG3_PERIPH_USART4, \ - .irq_num = BSP_UART4_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART4_EI, \ - .rx_int_src = INT_SRC_USART4_RI, \ - .tx_int_src = INT_SRC_USART4_TI, \ +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .irq_num = BSP_UART4_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART4_EI, \ + .rx_int_src = INT_SRC_USART4_RI, \ + .tx_int_src = INT_SRC_USART4_TI, \ } #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .channel = UART4_RX_DMA_CHANNEL, \ - .clock = UART4_RX_DMA_CLOCK, \ - .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART4_RI, \ - .flag = UART4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART4_RX_DMA_IRQn, \ - .irq_prio = UART4_RX_DMA_INT_PRIO, \ - .int_src = UART4_RX_DMA_INT_SRC, \ - }, \ +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .clock = UART4_RX_DMA_CLOCK, \ + .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_RI, \ + .flag = UART4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART4_RX_DMA_IRQn, \ + .irq_prio = UART4_RX_DMA_INT_PRIO, \ + .int_src = UART4_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART4_DMA_RX_CONFIG */ #ifndef UART4_RXTO_CONFIG -#define UART4_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ +#define UART4_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ } #endif /* UART4_RXTO_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #endif /* UART4_TX_CPLT_CONFIG */ #if defined(BSP_UART4_TX_USING_DMA) #ifndef UART4_DMA_TX_CONFIG -#define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .channel = UART4_TX_DMA_CHANNEL, \ - .clock = UART4_TX_DMA_CLOCK, \ - .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART4_TI, \ - .flag = UART4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART4_TX_DMA_IRQn, \ - .irq_prio = UART4_TX_DMA_INT_PRIO, \ - .int_src = UART4_TX_DMA_INT_SRC, \ - }, \ +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .clock = UART4_TX_DMA_CLOCK, \ + .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_TI, \ + .flag = UART4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART4_TX_DMA_IRQn, \ + .irq_prio = UART4_TX_DMA_INT_PRIO, \ + .int_src = UART4_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART4_DMA_TX_CONFIG */ #endif /* BSP_UART4_TX_USING_DMA */ @@ -324,90 +311,86 @@ extern "C" { #if defined(BSP_USING_UART5) #ifndef UART5_CONFIG -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = CM_USART5, \ - .clock = FCG3_PERIPH_USART5, \ - .irq_num = BSP_UART5_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART5_EI, \ - .rx_int_src = INT_SRC_USART5_RI, \ - .tx_int_src = INT_SRC_USART5_TI, \ +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .irq_num = BSP_UART5_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART5_EI, \ + .rx_int_src = INT_SRC_USART5_RI, \ + .tx_int_src = INT_SRC_USART5_TI, \ } #endif /* UART5_CONFIG */ #if defined(BSP_UART5_RX_USING_DMA) #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .channel = UART5_RX_DMA_CHANNEL, \ - .clock = UART5_RX_DMA_CLOCK, \ - .trigger_select = UART5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART5_RI, \ - .flag = UART5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART5_RX_DMA_IRQn, \ - .irq_prio = UART5_RX_DMA_INT_PRIO, \ - .int_src = UART5_RX_DMA_INT_SRC, \ - }, \ +#define UART5_DMA_RX_CONFIG \ + { \ + .Instance = UART5_RX_DMA_INSTANCE, \ + .channel = UART5_RX_DMA_CHANNEL, \ + .clock = UART5_RX_DMA_CLOCK, \ + .trigger_select = UART5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART5_RI, \ + .flag = UART5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART5_RX_DMA_IRQn, \ + .irq_prio = UART5_RX_DMA_INT_PRIO, \ + .int_src = UART5_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART5_DMA_RX_CONFIG */ #ifndef UART5_RXTO_CONFIG -#define UART5_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ +#define UART5_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ } #endif /* UART5_RXTO_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA) #ifndef UART5_TX_CPLT_CONFIG -#define UART5_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TCI, \ - }, \ +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART5_TX_CPLT_CONFIG -#define UART5_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TCI, \ - }, \ +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ } #endif #endif /* UART5_TX_CPLT_CONFIG */ #if defined(BSP_UART5_TX_USING_DMA) #ifndef UART5_DMA_TX_CONFIG -#define UART5_DMA_TX_CONFIG \ - { \ - .Instance = UART5_TX_DMA_INSTANCE, \ - .channel = UART5_TX_DMA_CHANNEL, \ - .clock = UART5_TX_DMA_CLOCK, \ - .trigger_select = UART5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART5_TI, \ - .flag = UART5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART5_TX_DMA_IRQn, \ - .irq_prio = UART5_TX_DMA_INT_PRIO, \ - .int_src = UART5_TX_DMA_INT_SRC, \ - }, \ +#define UART5_DMA_TX_CONFIG \ + { \ + .Instance = UART5_TX_DMA_INSTANCE, \ + .channel = UART5_TX_DMA_CHANNEL, \ + .clock = UART5_TX_DMA_CLOCK, \ + .trigger_select = UART5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART5_TI, \ + .flag = UART5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART5_TX_DMA_IRQn, \ + .irq_prio = UART5_TX_DMA_INT_PRIO, \ + .int_src = UART5_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART5_DMA_TX_CONFIG */ #endif /* BSP_UART5_TX_USING_DMA */ @@ -415,28 +398,27 @@ extern "C" { #if defined(BSP_USING_UART6) #ifndef UART6_CONFIG -#define UART6_CONFIG \ - { \ - .name = "uart6", \ - .Instance = CM_USART6, \ - .clock = FCG3_PERIPH_USART6, \ - .irq_num = BSP_UART6_IRQ_NUM, \ - .rxerr_int_src = INT_SRC_USART6_EI, \ - .rx_int_src = INT_SRC_USART6_RI, \ - .tx_int_src = INT_SRC_USART6_TI, \ +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .irq_num = BSP_UART6_IRQ_NUM, \ + .rxerr_int_src = INT_SRC_USART6_EI, \ + .rx_int_src = INT_SRC_USART6_RI, \ + .tx_int_src = INT_SRC_USART6_TI, \ } #endif /* UART6_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART6_TX_CPLT_CONFIG -#define UART6_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TCI, \ - }, \ +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ } #endif #endif /* UART6_TX_CPLT_CONFIG */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/usb_config/usb_app_conf.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/usb_config/usb_app_conf.h index 45e9dc93db2..fbf7540ce07 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/usb_config/usb_app_conf.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/usb_config/usb_app_conf.h @@ -13,8 +13,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -40,30 +39,30 @@ extern "C" #endif #ifndef USB_FS_MODE -#error "USB_FS_MODE should be defined" +#error "USB_FS_MODE should be defined" #endif #ifndef USE_DEVICE_MODE #ifndef USE_HOST_MODE -#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" +#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" #endif #endif #if defined(BSP_USING_USBD) /* USB DEVICE FIFO CONFIGURATION */ #ifdef USB_FS_MODE -#define RX_FIFO_FS_SIZE (128U) -#define TX0_FIFO_FS_SIZE (32U) -#define TX1_FIFO_FS_SIZE (32U) -#define TX2_FIFO_FS_SIZE (32U) -#define TX3_FIFO_FS_SIZE (32U) -#define TX4_FIFO_FS_SIZE (32U) -#define TX5_FIFO_FS_SIZE (32U) - -#if ((RX_FIFO_FS_SIZE + \ +#define RX_FIFO_FS_SIZE (128U) +#define TX0_FIFO_FS_SIZE (32U) +#define TX1_FIFO_FS_SIZE (32U) +#define TX2_FIFO_FS_SIZE (32U) +#define TX3_FIFO_FS_SIZE (32U) +#define TX4_FIFO_FS_SIZE (32U) +#define TX5_FIFO_FS_SIZE (32U) + +#if ((RX_FIFO_FS_SIZE + \ TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ TX5_FIFO_FS_SIZE) > 320U) -#error "The USB max FIFO size is 320 x 4 Bytes!" +#error "The USB max FIFO size is 320 x 4 Bytes!" #endif #endif @@ -75,12 +74,12 @@ extern "C" #if defined(BSP_USING_USBH) /* USB HOST FIFO CONFIGURATION */ #ifdef USB_FS_MODE -#define RX_FIFO_FS_SIZE (128U) -#define TXH_NP_FS_FIFOSIZ (64U) -#define TXH_P_FS_FIFOSIZ (128U) +#define RX_FIFO_FS_SIZE (128U) +#define TXH_NP_FS_FIFOSIZ (64U) +#define TXH_P_FS_FIFOSIZ (128U) #if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 320U) -#error "The USB max FIFO size is 320 x 4 Bytes!" +#error "The USB max FIFO size is 320 x 4 Bytes!" #endif #endif diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/config/usb_config/usb_bsp.h b/bsp/hc32/ev_hc32f472_lqfp100/board/config/usb_config/usb_bsp.h index 550169bd6e6..ea132d46de5 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/config/usb_config/usb_bsp.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/config/usb_config/usb_bsp.h @@ -13,8 +13,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include "hc32_ll_utility.h" diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f472_lqfp100/board/hc32f4xx_conf.h index 3f993bea566..88dd371becd 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/hc32f4xx_conf.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/hc32f4xx_conf.h @@ -27,8 +27,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -48,62 +47,62 @@ extern "C" * Library. * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. */ -#define LL_ICG_ENABLE (DDL_ON) -#define LL_UTILITY_ENABLE (DDL_ON) -#define LL_PRINT_ENABLE (DDL_OFF) +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) -#define LL_ADC_ENABLE (DDL_ON) -#define LL_AES_ENABLE (DDL_ON) -#define LL_AOS_ENABLE (DDL_ON) -#define LL_CAN_ENABLE (DDL_ON) -#define LL_CLK_ENABLE (DDL_ON) -#define LL_CMP_ENABLE (DDL_ON) -#define LL_CRC_ENABLE (DDL_ON) -#define LL_CTC_ENABLE (DDL_ON) -#define LL_DAC_ENABLE (DDL_ON) -#define LL_DBGC_ENABLE (DDL_OFF) -#define LL_DCU_ENABLE (DDL_ON) -#define LL_DMA_ENABLE (DDL_ON) -#define LL_EFM_ENABLE (DDL_ON) -#define LL_EMB_ENABLE (DDL_ON) -#define LL_EVENT_PORT_ENABLE (DDL_OFF) -#define LL_FCG_ENABLE (DDL_ON) -#define LL_FCM_ENABLE (DDL_ON) -#define LL_FMAC_ENABLE (DDL_ON) -#define LL_GPIO_ENABLE (DDL_ON) -#define LL_HASH_ENABLE (DDL_ON) -#define LL_I2C_ENABLE (DDL_ON) -#define LL_INTERRUPTS_ENABLE (DDL_ON) -#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) -#define LL_KEYSCAN_ENABLE (DDL_ON) -#define LL_MAU_ENABLE (DDL_ON) -#define LL_MDIO_ENABLE (DDL_ON) -#define LL_MPU_ENABLE (DDL_ON) -#define LL_OTS_ENABLE (DDL_ON) -#define LL_PLA_ENABLE (DDL_ON) -#define LL_PWC_ENABLE (DDL_ON) -#define LL_QSPI_ENABLE (DDL_ON) -#define LL_RMU_ENABLE (DDL_ON) -#define LL_RTC_ENABLE (DDL_ON) -#define LL_SMC_ENABLE (DDL_ON) -#define LL_SPI_ENABLE (DDL_ON) -#define LL_SRAM_ENABLE (DDL_ON) -#define LL_SWDT_ENABLE (DDL_ON) -#define LL_TMR0_ENABLE (DDL_ON) -#define LL_TMR2_ENABLE (DDL_ON) -#define LL_TMR4_ENABLE (DDL_ON) -#define LL_TMR6_ENABLE (DDL_ON) -#define LL_TMRA_ENABLE (DDL_ON) -#define LL_TRNG_ENABLE (DDL_ON) -#define LL_USART_ENABLE (DDL_ON) -#define LL_USB_ENABLE (DDL_ON) -#define LL_VREF_ENABLE (DDL_ON) -#define LL_WDT_ENABLE (DDL_ON) +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MDIO_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PLA_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR2_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_ON) +#define LL_VREF_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) /** * @brief The following is a list of currently supported BSP boards. */ -#define BSP_EV_HC32F472_LQFP80 (9U) +#define BSP_EV_HC32F472_LQFP80 (9U) /** * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently @@ -112,19 +111,19 @@ extern "C" * @note If there is no supported BSP board or the BSP function is not used, * the value needs to be set to 0U. */ -#define BSP_EV_HC32F4XX (0U) +#define BSP_EV_HC32F4XX (0U) /** * @brief This is the list of BSP components to be used. * Select the components you need to use to DDL_ON. */ -#define BSP_24CXX_ENABLE (DDL_OFF) -#define BSP_GT9XX_ENABLE (DDL_OFF) -#define BSP_IS61LV6416_ENABLE (DDL_OFF) -#define BSP_NT35510_ENABLE (DDL_OFF) -#define BSP_TCA9539_ENABLE (DDL_OFF) -#define BSP_W25QXX_ENABLE (DDL_OFF) -#define BSP_INT_KEY_ENABLE (DDL_OFF) +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_GT9XX_ENABLE (DDL_OFF) +#define BSP_IS61LV6416_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_INT_KEY_ENABLE (DDL_OFF) /******************************************************************************* * Global variable definitions ('extern') diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/fal_cfg.h index f9e317953aa..9c7b101d305 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/ports/fal_cfg.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/fal_cfg.h @@ -24,20 +24,20 @@ extern const struct fal_flash_dev hc32_onchip_flash; extern struct fal_flash_dev ext_nor_flash0; /* flash device table */ -#define FAL_FLASH_DEV_TABLE \ -{ \ - &hc32_onchip_flash, \ - &ext_nor_flash0, \ -} +#define FAL_FLASH_DEV_TABLE \ + { \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ + } /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ -#define FAL_PART_TABLE \ -{ \ - {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 512 * 1024, 0}, \ - {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ -} +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 512 * 1024, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \ + } #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/tca9539_port.h index 1548ec16d75..4bdcaf54309 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/ports/tca9539_port.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/tca9539_port.h @@ -17,21 +17,21 @@ * @defgroup HC32F472_EV_IO_Function_Sel Expand IO function definition * @{ */ -#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ -#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */ -#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */ -#define EIO_RTCS_CTRST (TCA9539_IO_PIN5) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ -#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */ -#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */ +#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ +#define EIO_SCI_CD (TCA9539_IO_PIN1) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN2) /* Touch screen interrupt, input */ +#define EIO_RTCS_CTRST (TCA9539_IO_PIN5) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN6) /* LCD panel reset, output */ +#define EIO_LCD_BKL (TCA9539_IO_PIN7) /* LCD panel back light, output */ -#define EIO_LIN2_SLEEP (TCA9539_IO_PIN0) /* LIN1 PHY sleep, output */ -#define EIO_LIN1_SLEEP (TCA9539_IO_PIN1) /* LIN2 PHY sleep, output */ -#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */ -#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */ -#define EIO_CAN3_STB (TCA9539_IO_PIN4) /* CAN3 PHY standby, output */ -#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ -#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ -#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +#define EIO_LIN2_SLEEP (TCA9539_IO_PIN0) /* LIN1 PHY sleep, output */ +#define EIO_LIN1_SLEEP (TCA9539_IO_PIN1) /* LIN2 PHY sleep, output */ +#define EIO_CAN1_STB (TCA9539_IO_PIN2) /* CAN1 PHY standby, output */ +#define EIO_CAN2_STB (TCA9539_IO_PIN3) /* CAN2 PHY standby, output */ +#define EIO_CAN3_STB (TCA9539_IO_PIN4) /* CAN3 PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ /** * @} */ @@ -40,12 +40,12 @@ * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition * @{ */ -#define LED_RED_PORT (TCA9539_IO_PORT1) -#define LED_RED_PIN (EIO_LED_RED) -#define LED_YELLOW_PORT (TCA9539_IO_PORT1) -#define LED_YELLOW_PIN (EIO_LED_YELLOW) -#define LED_BLUE_PORT (TCA9539_IO_PORT1) -#define LED_BLUE_PIN (EIO_LED_BLUE) +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) /** * @} */ @@ -54,12 +54,12 @@ * @defgroup BSP_CAN_PortPin_Sel BSP CAN PHY STB port/pin definition * @{ */ -#define CAN1_STB_PORT (TCA9539_IO_PORT1) -#define CAN1_STB_PIN (EIO_CAN1_STB) -#define CAN2_STB_PORT (TCA9539_IO_PORT1) -#define CAN2_STB_PIN (EIO_CAN2_STB) -#define CAN3_STB_PORT (TCA9539_IO_PORT1) -#define CAN3_STB_PIN (EIO_CAN3_STB) +#define CAN1_STB_PORT (TCA9539_IO_PORT1) +#define CAN1_STB_PIN (EIO_CAN1_STB) +#define CAN2_STB_PORT (TCA9539_IO_PORT1) +#define CAN2_STB_PIN (EIO_CAN2_STB) +#define CAN3_STB_PORT (TCA9539_IO_PORT1) +#define CAN3_STB_PIN (EIO_CAN3_STB) /** * @} */ diff --git a/bsp/hc32/ev_hc32f472_lqfp100/board/ports/usb_config.h b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/usb_config.h index 723f0b19040..91c6a46fb48 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/board/ports/usb_config.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/board/ports/usb_config.h @@ -14,15 +14,15 @@ /* ================ USB common Configuration ================ */ #ifdef __RTTHREAD__ - #include +#include - #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) #else - #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) #endif #ifndef CONFIG_USB_DBG_LEVEL - #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO #endif /* Enable print with color */ @@ -32,9 +32,9 @@ /* data align size when use dma or use dcache */ #ifdef CONFIG_USB_DCACHE_ENABLE - #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 #else - #define CONFIG_USB_ALIGN_SIZE 4 +#define CONFIG_USB_ALIGN_SIZE 4 #endif /* attribute data into no cache ram */ @@ -49,7 +49,7 @@ /* Ep0 in and out transfer buffer */ #ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN - #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 #endif /* Send ep0 in data from user buffer instead of copying into ep0 reqdata @@ -70,31 +70,31 @@ // #define CONFIG_USBDEV_EP0_THREAD #ifndef CONFIG_USBDEV_EP0_PRIO - #define CONFIG_USBDEV_EP0_PRIO 4 +#define CONFIG_USBDEV_EP0_PRIO 4 #endif #ifndef CONFIG_USBDEV_EP0_STACKSIZE - #define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#define CONFIG_USBDEV_EP0_STACKSIZE 2048 #endif #ifndef CONFIG_USBDEV_MSC_MAX_LUN - #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#define CONFIG_USBDEV_MSC_MAX_LUN 1 #endif #ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE - #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 #endif #ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING - #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" #endif #ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING - #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" #endif #ifndef CONFIG_USBDEV_MSC_VERSION_STRING - #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" #endif /* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ @@ -104,50 +104,50 @@ // #define CONFIG_USBDEV_MSC_THREAD #ifndef CONFIG_USBDEV_MSC_PRIO - #define CONFIG_USBDEV_MSC_PRIO 4 +#define CONFIG_USBDEV_MSC_PRIO 4 #endif #ifndef CONFIG_USBDEV_MSC_STACKSIZE - #define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 #endif #ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE - #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 #endif #ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS - #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 #endif #ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME - #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 #endif #define CONFIG_USBDEV_MTP_THREAD #ifndef CONFIG_USBDEV_MTP_PRIO - #define CONFIG_USBDEV_MTP_PRIO 4 +#define CONFIG_USBDEV_MTP_PRIO 4 #endif #ifndef CONFIG_USBDEV_MTP_STACKSIZE - #define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#define CONFIG_USBDEV_MTP_STACKSIZE 4096 #endif #ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE - #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 #endif /* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ #ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE - #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 #endif #ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID - #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff #endif #ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC - #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" #endif #define CONFIG_USBDEV_RNDIS_USING_LWIP @@ -171,95 +171,95 @@ #define CONFIG_USBHOST_DEV_NAMELEN 16 #ifndef CONFIG_USBHOST_PSC_PRIO - #define CONFIG_USBHOST_PSC_PRIO 0 +#define CONFIG_USBHOST_PSC_PRIO 0 #endif #ifndef CONFIG_USBHOST_PSC_STACKSIZE - #define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 #endif //#define CONFIG_USBHOST_GET_STRING_DESC // #define CONFIG_USBHOST_MSOS_ENABLE #ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE - #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 #endif /* Ep0 max transfer buffer */ #ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN - #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 #endif #ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT - #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 #endif #ifndef CONFIG_USBHOST_MSC_TIMEOUT - #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) #endif #define CONFIG_USBHOST_BLUETOOTH_HCI_H4 // #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG #ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE - #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 #endif #ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE - #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 #endif /* ================ USB Device Port Configuration ================*/ #ifndef CONFIG_USBDEV_MAX_BUS - #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip #endif #ifndef CONFIG_USBDEV_EP_NUM - #define CONFIG_USBDEV_EP_NUM 8 +#define CONFIG_USBDEV_EP_NUM 8 #endif // #define CONFIG_USBDEV_SOF_ENABLE @@ -270,38 +270,38 @@ // #define CONFIG_USB_DWC2_DMA_ENABLE /* Defined FS Core device FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) -#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) /* Defined FS Core host FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) -#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) /* Defined FS Core total FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (320) +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (320) /* ================ USB Host Port Configuration ==================*/ #ifndef CONFIG_USBHOST_MAX_BUS - #define CONFIG_USBHOST_MAX_BUS 1 +#define CONFIG_USBHOST_MAX_BUS 1 #endif #ifndef CONFIG_USBHOST_PIPE_NUM - #define CONFIG_USBHOST_PIPE_NUM 10 +#define CONFIG_USBHOST_PIPE_NUM 10 #endif #ifndef usb_phyaddr2ramaddr - #define usb_phyaddr2ramaddr(addr) (addr) +#define usb_phyaddr2ramaddr(addr) (addr) #endif #ifndef usb_ramaddr2phyaddr - #define usb_ramaddr2phyaddr(addr) (addr) +#define usb_ramaddr2phyaddr(addr) (addr) #endif #endif diff --git a/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h b/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h index 920411e6a25..d6c03c6ab9b 100644 --- a/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h +++ b/bsp/hc32/ev_hc32f472_lqfp100/rtconfig.h @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 /* kservice options */ @@ -326,14 +326,6 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ - -/* HPMicro SDK */ - -/* end of HPMicro SDK */ - -/* FT32 HAL & SDK Drivers */ - -/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml index d4a7b92a9dc..9f5f2866382 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.ci/attachconfig/ci.attachconfig.yml @@ -29,11 +29,11 @@ devices.flash: - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SFUD=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/.config b/bsp/hc32/ev_hc32f4a0_lqfp176/.config index 3c6256cd6ad..231d5e21a61 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/.config +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/.config @@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md index bbe6eb75b4a..c7f76c2b8c2 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/README.md +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/README.md @@ -52,7 +52,7 @@ EV_F4A0_LQ176 开发板常用 **板载资源** 如下： | DAC | 支持 | | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | PM | 支持 | | diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/xtal32_fcm.c index c84a42fbc80..0f90b78297f 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/applications/xtal32_fcm.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/applications/xtal32_fcm.c @@ -18,8 +18,8 @@ #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) -#define XTAL32_FCM_THREAD_STACK_SIZE (1024) -#define XTAL32_FCM_UNIT (CM_FCM) +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM) /** * @brief This thread is used to monitor whether XTAL32 is stable. @@ -36,13 +36,13 @@ void xtal32_fcm_thread_entry(void *parameter) /* FCM config */ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); (void)FCM_StructInit(&stcFcmInit); - stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; - stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ - stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; - stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; - stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); - stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); /* Enable FCM, to ensure xtal32 stable */ FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig index 79cb785cbc0..a89de950045 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/Kconfig @@ -843,7 +843,7 @@ menu "On-chip Peripheral Drivers" bool default n config BSP_USING_USBFS - bool "Use USBFS Core " + bool "Use USBFS Core" default n if BSP_USING_USBFS choice @@ -877,7 +877,7 @@ menu "On-chip Peripheral Drivers" endif endif config BSP_USING_USBHS - bool "Use USBHS Core " + bool "Use USBHS Core" default n if BSP_USING_USBHS choice @@ -964,45 +964,45 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_CLOCK_TIMER - bool "Enable Hw Timer" + bool "Enable Clock Timer" default n select RT_USING_CLOCK_TIME if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 - bool "Use Timer_a1 As The Hw Timer" + bool "Use Timer_a1 As The Clock Timer" default n config BSP_USING_TMRA_2 - bool "Use Timer_a2 As The Hw Timer" + bool "Use Timer_a2 As The Clock Timer" default n config BSP_USING_TMRA_3 - bool "Use Timer_a3 As The Hw Timer" + bool "Use Timer_a3 As The Clock Timer" default n config BSP_USING_TMRA_4 - bool "Use Timer_a4 As The Hw Timer" + bool "Use Timer_a4 As The Clock Timer" default n config BSP_USING_TMRA_5 - bool "Use Timer_a5 As The Hw Timer" + bool "Use Timer_a5 As The Clock Timer" default n config BSP_USING_TMRA_6 - bool "Use Timer_a6 As The Hw Timer" + bool "Use Timer_a6 As The Clock Timer" default n config BSP_USING_TMRA_7 - bool "Use Timer_a7 As The Hw Timer" + bool "Use Timer_a7 As The Clock Timer" default n config BSP_USING_TMRA_8 - bool "Use Timer_a8 As The Hw Timer" + bool "Use Timer_a8 As The Clock Timer" default n config BSP_USING_TMRA_9 - bool "Use Timer_a9 As The Hw Timer" + bool "Use Timer_a9 As The Clock Timer" default n config BSP_USING_TMRA_10 - bool "Use Timer_a10 As The Hw Timer" + bool "Use Timer_a10 As The Clock Timer" default n config BSP_USING_TMRA_11 - bool "Use Timer_a11 As The Hw Timer" + bool "Use Timer_a11 As The Clock Timer" default n config BSP_USING_TMRA_12 - bool "Use Timer_a12 As The Hw Timer" + bool "Use Timer_a12 As The Clock Timer" default n endif menuconfig BSP_USING_INPUT_CAPTURE diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c index 18a1d51da3b..613e392f8d8 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.c @@ -13,9 +13,9 @@ #include "board_config.h" /* unlock/lock peripheral */ -#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ - LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) -#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) /** System Base Configuration */ @@ -51,17 +51,17 @@ void SystemClock_Config(void) /* PCLK1, PCLK4 Max 120MHz */ /* PCLK2, PCLK3 Max 60MHz */ /* EX BUS Max 120MHz */ - CLK_SetClockDiv(CLK_BUS_CLK_ALL, \ - (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \ - CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | CLK_HCLK_DIV1)); GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); (void)CLK_XtalStructInit(&stcXtalInit); /* Config Xtal and enable Xtal */ - stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; - stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; - stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; (void)CLK_XtalInit(&stcXtalInit); @@ -105,8 +105,8 @@ void SystemClock_Config(void) /* Xtal32 config */ GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); (void)CLK_Xtal32StructInit(&stcXtal32Init); - stcXtal32Init.u8State = CLK_XTAL32_ON; - stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; (void)CLK_Xtal32Init(&stcXtal32Init); #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h index ea804ffbdfa..d5b4daa383b 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board.h @@ -20,27 +20,27 @@ extern "C" { #endif -#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) -#define HC32_FLASH_WRITE_GRANULARITY (4) -#define HC32_FLASH_SIZE (2 * 1024 * 1024) -#define HC32_FLASH_START_ADDRESS (0) -#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) +#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (2 * 1024 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) -#define HC32_SRAM_SIZE (512) -#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) +#define HC32_SRAM_SIZE (512) +#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) #ifdef __ARMCC_VERSION extern int Image$$RW_IRAM2$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) #elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) #else extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) +#define HEAP_BEGIN (&__bss_end) #endif -#define HEAP_END HC32_SRAM_END +#define HEAP_END HC32_SRAM_END void PeripheralRegister_Unlock(void); void PeripheralClock_Config(void); diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c index 34e3d86602e..cf2915ac584 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.c @@ -176,7 +176,7 @@ rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) #endif -#if defined (RT_USING_SPI) +#if defined(RT_USING_SPI) rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) { rt_err_t result = RT_EOK; @@ -190,17 +190,17 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) case (rt_uint32_t)CM_SPI1: GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinState = PIN_STAT_SET; - stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinDir = PIN_DIR_OUT; GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; - (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); - GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); break; @@ -216,14 +216,14 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) #if defined(BSP_USING_ETH) /* PHY hardware reset time */ -#define PHY_HW_RST_DELAY (0x40U) +#define PHY_HW_RST_DELAY (0x40U) rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) { TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT); - TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); rt_thread_mdelay(PHY_HW_RST_DELAY); - TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); rt_thread_mdelay(PHY_HW_RST_DELAY); return RT_EOK; } @@ -231,39 +231,39 @@ rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx) { #if defined(ETH_INTERFACE_USING_RMII) - GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); - GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); - GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); - GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); - GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); + GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); + GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); GPIO_SetFunc(ETH_RMII_REF_CLK_PORT, ETH_RMII_REF_CLK_PIN, ETH_RMII_REF_CLK_FUNC); - GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); - GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); - GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); + GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); + GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); + GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); #else - GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); - GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); GPIO_SetFunc(ETH_MII_TX_CLK_PORT, ETH_MII_TX_CLK_PIN, ETH_MII_TX_CLK_FUNC); - GPIO_SetFunc(ETH_MII_TX_EN_PORT, ETH_MII_TX_EN_PIN, ETH_MII_TX_EN_FUNC); - GPIO_SetFunc(ETH_MII_TXD0_PORT, ETH_MII_TXD0_PIN, ETH_MII_TXD0_FUNC); - GPIO_SetFunc(ETH_MII_TXD1_PORT, ETH_MII_TXD1_PIN, ETH_MII_TXD1_FUNC); - GPIO_SetFunc(ETH_MII_TXD2_PORT, ETH_MII_TXD2_PIN, ETH_MII_TXD2_FUNC); - GPIO_SetFunc(ETH_MII_TXD3_PORT, ETH_MII_TXD3_PIN, ETH_MII_TXD3_FUNC); + GPIO_SetFunc(ETH_MII_TX_EN_PORT, ETH_MII_TX_EN_PIN, ETH_MII_TX_EN_FUNC); + GPIO_SetFunc(ETH_MII_TXD0_PORT, ETH_MII_TXD0_PIN, ETH_MII_TXD0_FUNC); + GPIO_SetFunc(ETH_MII_TXD1_PORT, ETH_MII_TXD1_PIN, ETH_MII_TXD1_FUNC); + GPIO_SetFunc(ETH_MII_TXD2_PORT, ETH_MII_TXD2_PIN, ETH_MII_TXD2_FUNC); + GPIO_SetFunc(ETH_MII_TXD3_PORT, ETH_MII_TXD3_PIN, ETH_MII_TXD3_FUNC); GPIO_SetFunc(ETH_MII_RX_CLK_PORT, ETH_MII_RX_CLK_PIN, ETH_MII_RX_CLK_FUNC); - GPIO_SetFunc(ETH_MII_RX_DV_PORT, ETH_MII_RX_DV_PIN, ETH_MII_RX_DV_FUNC); - GPIO_SetFunc(ETH_MII_RXD0_PORT, ETH_MII_RXD0_PIN, ETH_MII_RXD0_FUNC); - GPIO_SetFunc(ETH_MII_RXD1_PORT, ETH_MII_RXD1_PIN, ETH_MII_RXD1_FUNC); - GPIO_SetFunc(ETH_MII_RXD2_PORT, ETH_MII_RXD2_PIN, ETH_MII_RXD2_FUNC); - GPIO_SetFunc(ETH_MII_RXD3_PORT, ETH_MII_RXD3_PIN, ETH_MII_RXD3_FUNC); - GPIO_SetFunc(ETH_MII_RX_ER_PORT, ETH_MII_RX_ER_PIN, ETH_MII_RX_ER_FUNC); - GPIO_SetFunc(ETH_MII_CRS_PORT, ETH_MII_CRS_PIN, ETH_MII_CRS_FUNC); - GPIO_SetFunc(ETH_MII_COL_PORT, ETH_MII_COL_PIN, ETH_MII_COL_FUNC); + GPIO_SetFunc(ETH_MII_RX_DV_PORT, ETH_MII_RX_DV_PIN, ETH_MII_RX_DV_FUNC); + GPIO_SetFunc(ETH_MII_RXD0_PORT, ETH_MII_RXD0_PIN, ETH_MII_RXD0_FUNC); + GPIO_SetFunc(ETH_MII_RXD1_PORT, ETH_MII_RXD1_PIN, ETH_MII_RXD1_FUNC); + GPIO_SetFunc(ETH_MII_RXD2_PORT, ETH_MII_RXD2_PIN, ETH_MII_RXD2_FUNC); + GPIO_SetFunc(ETH_MII_RXD3_PORT, ETH_MII_RXD3_PIN, ETH_MII_RXD3_FUNC); + GPIO_SetFunc(ETH_MII_RX_ER_PORT, ETH_MII_RX_ER_PIN, ETH_MII_RX_ER_FUNC); + GPIO_SetFunc(ETH_MII_CRS_PORT, ETH_MII_CRS_PIN, ETH_MII_CRS_FUNC); + GPIO_SetFunc(ETH_MII_COL_PORT, ETH_MII_COL_PIN, ETH_MII_COL_FUNC); #endif return RT_EOK; } #endif -#if defined (RT_USING_SDIO) +#if defined(RT_USING_SDIO) rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) { rt_err_t result = RT_EOK; @@ -276,19 +276,19 @@ rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) /************************* Set pin drive capacity *************************/ (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; - (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); - GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); + GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC); - GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); - GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); - GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); - GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); + GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); + GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); + GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); + GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); break; #endif default: @@ -397,24 +397,24 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) #endif #endif -#if defined (BSP_USING_INPUT_CAPTURE) +#if defined(BSP_USING_INPUT_CAPTURE) rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) { rt_err_t result = RT_EOK; switch ((rt_uint32_t)tmr_instance) { -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) case (rt_uint32_t)CM_TMR6_1: GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) case (rt_uint32_t)CM_TMR6_2: GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) case (rt_uint32_t)CM_TMR6_3: GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC); break; @@ -427,7 +427,7 @@ rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) } #endif -#if defined (BSP_USING_SDRAM) +#if defined(BSP_USING_SDRAM) rt_err_t rt_hw_board_sdram_init(void) { rt_err_t result = RT_EOK; @@ -501,16 +501,16 @@ rt_err_t rt_hw_board_sdram_init(void) /* DMC_WE */ GPIO_SetFunc(SDRAM_WE_PORT, SDRAM_WE_PIN, SDRAM_WE_FUNC); /* DMC_DATA[0:15] */ - GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); - GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); - GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); - GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); - GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); - GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); - GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); - GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); - GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); - GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); + GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); + GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); + GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); + GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); + GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); + GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); + GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); + GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); + GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); + GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); GPIO_SetFunc(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, SDRAM_DATA10_FUNC); GPIO_SetFunc(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, SDRAM_DATA11_FUNC); GPIO_SetFunc(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, SDRAM_DATA12_FUNC); @@ -518,16 +518,16 @@ rt_err_t rt_hw_board_sdram_init(void) GPIO_SetFunc(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, SDRAM_DATA14_FUNC); GPIO_SetFunc(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, SDRAM_DATA15_FUNC); /* DMC_ADD[0:11]*/ - GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); - GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); - GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); - GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); - GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); - GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); - GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); - GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); - GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); - GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); + GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); + GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); + GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); + GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); + GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); + GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); + GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); + GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); + GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); + GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); GPIO_SetFunc(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, SDRAM_ADD10_FUNC); GPIO_SetFunc(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, SDRAM_ADD11_FUNC); @@ -614,14 +614,14 @@ rt_err_t rt_hw_usbhs_board_init(void) GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); - GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); - GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); - GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); - GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); - GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); - GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); - GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); - GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); #endif @@ -691,14 +691,14 @@ rt_err_t rt_hw_usbhs_board_init(uint8_t devmode) GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); - GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); - GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); - GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); - GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); - GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); - GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); - GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); - GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); #endif @@ -716,8 +716,8 @@ rt_err_t rt_hw_qspi_board_init(void) (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; #ifndef BSP_QSPI_USING_SOFT_CS - (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); - GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); #endif (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); @@ -758,7 +758,7 @@ rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void) } #endif -#if defined (BSP_USING_NAND) +#if defined(BSP_USING_NAND) rt_err_t rt_hw_board_nand_init(void) { rt_err_t result = RT_EOK; diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h index 31d26ab2354..43a20aaaa7b 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/board_config.h @@ -16,688 +16,688 @@ #include "hc32_ll.h" #include "drv_config.h" #if defined(RT_USING_CHERRYUSB) - #include "usb_config.h" +#include "usb_config.h" #endif /************************* XTAL port **********************/ -#define XTAL_PORT (GPIO_PORT_H) -#define XTAL_IN_PIN (GPIO_PIN_01) -#define XTAL_OUT_PIN (GPIO_PIN_00) +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_IN_PIN (GPIO_PIN_01) +#define XTAL_OUT_PIN (GPIO_PIN_00) /************************ USART port **********************/ #if defined(BSP_USING_UART1) - #define USART1_RX_PORT (GPIO_PORT_H) - #define USART1_RX_PIN (GPIO_PIN_13) - #define USART1_RX_FUNC (GPIO_FUNC_33) +#define USART1_RX_PORT (GPIO_PORT_H) +#define USART1_RX_PIN (GPIO_PIN_13) +#define USART1_RX_FUNC (GPIO_FUNC_33) - #define USART1_TX_PORT (GPIO_PORT_H) - #define USART1_TX_PIN (GPIO_PIN_15) - #define USART1_TX_FUNC (GPIO_FUNC_32) +#define USART1_TX_PORT (GPIO_PORT_H) +#define USART1_TX_PIN (GPIO_PIN_15) +#define USART1_TX_FUNC (GPIO_FUNC_32) #endif #if defined(BSP_USING_UART6) - #define USART6_RX_PORT (GPIO_PORT_H) - #define USART6_RX_PIN (GPIO_PIN_06) - #define USART6_RX_FUNC (GPIO_FUNC_37) +#define USART6_RX_PORT (GPIO_PORT_H) +#define USART6_RX_PIN (GPIO_PIN_06) +#define USART6_RX_FUNC (GPIO_FUNC_37) - #define USART6_TX_PORT (GPIO_PORT_E) - #define USART6_TX_PIN (GPIO_PIN_06) - #define USART6_TX_FUNC (GPIO_FUNC_36) +#define USART6_TX_PORT (GPIO_PORT_E) +#define USART6_TX_PIN (GPIO_PIN_06) +#define USART6_TX_FUNC (GPIO_FUNC_36) #endif /************************ I2C port **********************/ #if defined(BSP_USING_I2C1) - #define I2C1_SDA_PORT (GPIO_PORT_F) - #define I2C1_SDA_PIN (GPIO_PIN_10) - #define I2C1_SDA_FUNC (GPIO_FUNC_48) +#define I2C1_SDA_PORT (GPIO_PORT_F) +#define I2C1_SDA_PIN (GPIO_PIN_10) +#define I2C1_SDA_FUNC (GPIO_FUNC_48) - #define I2C1_SCL_PORT (GPIO_PORT_D) - #define I2C1_SCL_PIN (GPIO_PIN_03) - #define I2C1_SCL_FUNC (GPIO_FUNC_49) +#define I2C1_SCL_PORT (GPIO_PORT_D) +#define I2C1_SCL_PIN (GPIO_PIN_03) +#define I2C1_SCL_FUNC (GPIO_FUNC_49) #endif /*********** ADC configure *********/ #if defined(BSP_USING_ADC1) - #define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */ - #define ADC1_CH_PIN (GPIO_PIN_00) +#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */ +#define ADC1_CH_PIN (GPIO_PIN_00) #endif #if defined(BSP_USING_ADC2) - #define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */ - #define ADC2_CH_PIN (GPIO_PIN_01) +#define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */ +#define ADC2_CH_PIN (GPIO_PIN_01) #endif #if defined(BSP_USING_ADC3) - #define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */ - #define ADC3_CH_PIN (GPIO_PIN_02) +#define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */ +#define ADC3_CH_PIN (GPIO_PIN_02) #endif /*********** DAC configure *********/ #if defined(BSP_USING_DAC1) - #define DAC1_CH1_PORT (GPIO_PORT_A) - #define DAC1_CH1_PIN (GPIO_PIN_04) - #define DAC1_CH2_PORT (GPIO_PORT_A) - #define DAC1_CH2_PIN (GPIO_PIN_05) +#define DAC1_CH1_PORT (GPIO_PORT_A) +#define DAC1_CH1_PIN (GPIO_PIN_04) +#define DAC1_CH2_PORT (GPIO_PORT_A) +#define DAC1_CH2_PIN (GPIO_PIN_05) #endif #if defined(BSP_USING_DAC2) - #define DAC2_CH1_PORT (GPIO_PORT_C) - #define DAC2_CH1_PIN (GPIO_PIN_04) - #define DAC2_CH2_PORT (GPIO_PORT_C) - #define DAC2_CH2_PIN (GPIO_PIN_05) +#define DAC2_CH1_PORT (GPIO_PORT_C) +#define DAC2_CH1_PIN (GPIO_PIN_04) +#define DAC2_CH2_PORT (GPIO_PORT_C) +#define DAC2_CH2_PIN (GPIO_PIN_05) #endif /*********** CAN configure *********/ #if defined(BSP_USING_CAN1) - #define CAN1_TX_PORT (GPIO_PORT_D) - #define CAN1_TX_PIN (GPIO_PIN_05) - #define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) +#define CAN1_TX_PORT (GPIO_PORT_D) +#define CAN1_TX_PIN (GPIO_PIN_05) +#define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) - #define CAN1_RX_PORT (GPIO_PORT_D) - #define CAN1_RX_PIN (GPIO_PIN_04) - #define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) +#define CAN1_RX_PORT (GPIO_PORT_D) +#define CAN1_RX_PIN (GPIO_PIN_04) +#define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) #endif #if defined(BSP_USING_CAN2) - #define CAN2_TX_PORT (GPIO_PORT_D) - #define CAN2_TX_PIN (GPIO_PIN_07) - #define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) +#define CAN2_TX_PORT (GPIO_PORT_D) +#define CAN2_TX_PIN (GPIO_PIN_07) +#define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) - #define CAN2_RX_PORT (GPIO_PORT_D) - #define CAN2_RX_PIN (GPIO_PIN_06) - #define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) +#define CAN2_RX_PORT (GPIO_PORT_D) +#define CAN2_RX_PIN (GPIO_PIN_06) +#define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) #endif /************************* SPI port ***********************/ #if defined(BSP_USING_SPI1) - #define SPI1_CS_PORT (GPIO_PORT_C) - #define SPI1_CS_PIN (GPIO_PIN_07) +#define SPI1_CS_PORT (GPIO_PORT_C) +#define SPI1_CS_PIN (GPIO_PIN_07) - #define SPI1_SCK_PORT (GPIO_PORT_C) - #define SPI1_SCK_PIN (GPIO_PIN_06) - #define SPI1_SCK_FUNC (GPIO_FUNC_40) +#define SPI1_SCK_PORT (GPIO_PORT_C) +#define SPI1_SCK_PIN (GPIO_PIN_06) +#define SPI1_SCK_FUNC (GPIO_FUNC_40) - #define SPI1_MOSI_PORT (GPIO_PORT_B) - #define SPI1_MOSI_PIN (GPIO_PIN_13) - #define SPI1_MOSI_FUNC (GPIO_FUNC_41) +#define SPI1_MOSI_PORT (GPIO_PORT_B) +#define SPI1_MOSI_PIN (GPIO_PIN_13) +#define SPI1_MOSI_FUNC (GPIO_FUNC_41) - #define SPI1_MISO_PORT (GPIO_PORT_B) - #define SPI1_MISO_PIN (GPIO_PIN_12) - #define SPI1_MISO_FUNC (GPIO_FUNC_42) +#define SPI1_MISO_PORT (GPIO_PORT_B) +#define SPI1_MISO_PIN (GPIO_PIN_12) +#define SPI1_MISO_FUNC (GPIO_FUNC_42) - #define SPI1_WP_PORT (GPIO_PORT_B) - #define SPI1_WP_PIN (GPIO_PIN_10) +#define SPI1_WP_PORT (GPIO_PORT_B) +#define SPI1_WP_PIN (GPIO_PIN_10) - #define SPI1_HOLD_PORT (GPIO_PORT_B) - #define SPI1_HOLD_PIN (GPIO_PIN_02) +#define SPI1_HOLD_PORT (GPIO_PORT_B) +#define SPI1_HOLD_PIN (GPIO_PIN_02) #endif /************************* ETH port ***********************/ #if defined(BSP_USING_ETH) - #if defined(ETH_INTERFACE_USING_RMII) - #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) - #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) - #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) - - #define ETH_SMI_MDC_PORT (GPIO_PORT_C) - #define ETH_SMI_MDC_PIN (GPIO_PIN_01) - #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) - #define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) - #define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_TXD0_PORT (GPIO_PORT_G) - #define ETH_RMII_TXD0_PIN (GPIO_PIN_13) - #define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_TXD1_PORT (GPIO_PORT_G) - #define ETH_RMII_TXD1_PIN (GPIO_PIN_14) - #define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) - #define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) - #define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) - #define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) - #define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_RXD0_PORT (GPIO_PORT_C) - #define ETH_RMII_RXD0_PIN (GPIO_PIN_04) - #define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_RXD1_PORT (GPIO_PORT_C) - #define ETH_RMII_RXD1_PIN (GPIO_PIN_05) - #define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) - #else - #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) - #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) - #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) - - #define ETH_SMI_MDC_PORT (GPIO_PORT_C) - #define ETH_SMI_MDC_PIN (GPIO_PIN_01) - #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TX_CLK_PORT (GPIO_PORT_B) - #define ETH_MII_TX_CLK_PIN (GPIO_PIN_06) - #define ETH_MII_TX_CLK_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TX_EN_PORT (GPIO_PORT_G) - #define ETH_MII_TX_EN_PIN (GPIO_PIN_11) - #define ETH_MII_TX_EN_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD0_PORT (GPIO_PORT_G) - #define ETH_MII_TXD0_PIN (GPIO_PIN_13) - #define ETH_MII_TXD0_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD1_PORT (GPIO_PORT_G) - #define ETH_MII_TXD1_PIN (GPIO_PIN_14) - #define ETH_MII_TXD1_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD2_PORT (GPIO_PORT_B) - #define ETH_MII_TXD2_PIN (GPIO_PIN_09) - #define ETH_MII_TXD2_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD3_PORT (GPIO_PORT_B) - #define ETH_MII_TXD3_PIN (GPIO_PIN_08) - #define ETH_MII_TXD3_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RX_CLK_PORT (GPIO_PORT_A) - #define ETH_MII_RX_CLK_PIN (GPIO_PIN_01) - #define ETH_MII_RX_CLK_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RX_DV_PORT (GPIO_PORT_A) - #define ETH_MII_RX_DV_PIN (GPIO_PIN_07) - #define ETH_MII_RX_DV_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD0_PORT (GPIO_PORT_C) - #define ETH_MII_RXD0_PIN (GPIO_PIN_04) - #define ETH_MII_RXD0_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD1_PORT (GPIO_PORT_C) - #define ETH_MII_RXD1_PIN (GPIO_PIN_05) - #define ETH_MII_RXD1_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD2_PORT (GPIO_PORT_B) - #define ETH_MII_RXD2_PIN (GPIO_PIN_00) - #define ETH_MII_RXD2_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD3_PORT (GPIO_PORT_B) - #define ETH_MII_RXD3_PIN (GPIO_PIN_01) - #define ETH_MII_RXD3_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RX_ER_PORT (GPIO_PORT_I) - #define ETH_MII_RX_ER_PIN (GPIO_PIN_10) - #define ETH_MII_RX_ER_FUNC (GPIO_FUNC_11) - - #define ETH_MII_CRS_PORT (GPIO_PORT_H) - #define ETH_MII_CRS_PIN (GPIO_PIN_02) - #define ETH_MII_CRS_FUNC (GPIO_FUNC_11) - - #define ETH_MII_COL_PORT (GPIO_PORT_H) - #define ETH_MII_COL_PIN (GPIO_PIN_03) - #define ETH_MII_COL_FUNC (GPIO_FUNC_11) - #endif +#if defined(ETH_INTERFACE_USING_RMII) +#define ETH_SMI_MDIO_PORT (GPIO_PORT_A) +#define ETH_SMI_MDIO_PIN (GPIO_PIN_02) +#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + +#define ETH_SMI_MDC_PORT (GPIO_PORT_C) +#define ETH_SMI_MDC_PIN (GPIO_PIN_01) +#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) +#define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) +#define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TXD0_PORT (GPIO_PORT_G) +#define ETH_RMII_TXD0_PIN (GPIO_PIN_13) +#define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TXD1_PORT (GPIO_PORT_G) +#define ETH_RMII_TXD1_PIN (GPIO_PIN_14) +#define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) +#define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) +#define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) +#define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) +#define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_RXD0_PORT (GPIO_PORT_C) +#define ETH_RMII_RXD0_PIN (GPIO_PIN_04) +#define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_RXD1_PORT (GPIO_PORT_C) +#define ETH_RMII_RXD1_PIN (GPIO_PIN_05) +#define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) +#else +#define ETH_SMI_MDIO_PORT (GPIO_PORT_A) +#define ETH_SMI_MDIO_PIN (GPIO_PIN_02) +#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + +#define ETH_SMI_MDC_PORT (GPIO_PORT_C) +#define ETH_SMI_MDC_PIN (GPIO_PIN_01) +#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TX_CLK_PORT (GPIO_PORT_B) +#define ETH_MII_TX_CLK_PIN (GPIO_PIN_06) +#define ETH_MII_TX_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TX_EN_PORT (GPIO_PORT_G) +#define ETH_MII_TX_EN_PIN (GPIO_PIN_11) +#define ETH_MII_TX_EN_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD0_PORT (GPIO_PORT_G) +#define ETH_MII_TXD0_PIN (GPIO_PIN_13) +#define ETH_MII_TXD0_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD1_PORT (GPIO_PORT_G) +#define ETH_MII_TXD1_PIN (GPIO_PIN_14) +#define ETH_MII_TXD1_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD2_PORT (GPIO_PORT_B) +#define ETH_MII_TXD2_PIN (GPIO_PIN_09) +#define ETH_MII_TXD2_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD3_PORT (GPIO_PORT_B) +#define ETH_MII_TXD3_PIN (GPIO_PIN_08) +#define ETH_MII_TXD3_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_CLK_PORT (GPIO_PORT_A) +#define ETH_MII_RX_CLK_PIN (GPIO_PIN_01) +#define ETH_MII_RX_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_DV_PORT (GPIO_PORT_A) +#define ETH_MII_RX_DV_PIN (GPIO_PIN_07) +#define ETH_MII_RX_DV_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD0_PORT (GPIO_PORT_C) +#define ETH_MII_RXD0_PIN (GPIO_PIN_04) +#define ETH_MII_RXD0_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD1_PORT (GPIO_PORT_C) +#define ETH_MII_RXD1_PIN (GPIO_PIN_05) +#define ETH_MII_RXD1_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD2_PORT (GPIO_PORT_B) +#define ETH_MII_RXD2_PIN (GPIO_PIN_00) +#define ETH_MII_RXD2_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD3_PORT (GPIO_PORT_B) +#define ETH_MII_RXD3_PIN (GPIO_PIN_01) +#define ETH_MII_RXD3_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_ER_PORT (GPIO_PORT_I) +#define ETH_MII_RX_ER_PIN (GPIO_PIN_10) +#define ETH_MII_RX_ER_FUNC (GPIO_FUNC_11) + +#define ETH_MII_CRS_PORT (GPIO_PORT_H) +#define ETH_MII_CRS_PIN (GPIO_PIN_02) +#define ETH_MII_CRS_FUNC (GPIO_FUNC_11) + +#define ETH_MII_COL_PORT (GPIO_PORT_H) +#define ETH_MII_COL_PIN (GPIO_PIN_03) +#define ETH_MII_COL_FUNC (GPIO_FUNC_11) +#endif #endif /************************ NAND port **********************/ #if defined(BSP_USING_NAND) - #define NAND_CE_PORT (GPIO_PORT_C) /* PC02 - EXMC_CE0 */ - #define NAND_CE_PIN (GPIO_PIN_02) - #define NAND_CE_FUNC (GPIO_FUNC_12) - - #define NAND_RE_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ - #define NAND_RE_PIN (GPIO_PIN_11) - #define NAND_RE_FUNC (GPIO_FUNC_12) - - #define NAND_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ - #define NAND_WE_PIN (GPIO_PIN_00) - #define NAND_WE_FUNC (GPIO_FUNC_12) - - #define NAND_CLE_PORT (GPIO_PORT_I) /* PI12 - EXMC_CLE */ - #define NAND_CLE_PIN (GPIO_PIN_12) - #define NAND_CLE_FUNC (GPIO_FUNC_12) - - #define NAND_ALE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ - #define NAND_ALE_PIN (GPIO_PIN_03) - #define NAND_ALE_FUNC (GPIO_FUNC_12) - - #define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ - #define NAND_WP_PIN (GPIO_PIN_15) - #define NAND_WP_FUNC (GPIO_FUNC_12) - - #define NAND_RB_PORT (GPIO_PORT_G) /* PG06 - EXMC_RB0 */ - #define NAND_RB_PIN (GPIO_PIN_06) - #define NAND_RB_FUNC (GPIO_FUNC_12) - - #define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ - #define NAND_DATA0_PIN (GPIO_PIN_14) - #define NAND_DATA0_FUNC (GPIO_FUNC_12) - #define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ - #define NAND_DATA1_PIN (GPIO_PIN_15) - #define NAND_DATA1_FUNC (GPIO_FUNC_12) - #define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ - #define NAND_DATA2_PIN (GPIO_PIN_00) - #define NAND_DATA2_FUNC (GPIO_FUNC_12) - #define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ - #define NAND_DATA3_PIN (GPIO_PIN_01) - #define NAND_DATA3_FUNC (GPIO_FUNC_12) - #define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ - #define NAND_DATA4_PIN (GPIO_PIN_07) - #define NAND_DATA4_FUNC (GPIO_FUNC_12) - #define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ - #define NAND_DATA5_PIN (GPIO_PIN_08) - #define NAND_DATA5_FUNC (GPIO_FUNC_12) - #define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ - #define NAND_DATA6_PIN (GPIO_PIN_09) - #define NAND_DATA6_FUNC (GPIO_FUNC_12) - #define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ - #define NAND_DATA7_PIN (GPIO_PIN_10) - #define NAND_DATA7_FUNC (GPIO_FUNC_12) +#define NAND_CE_PORT (GPIO_PORT_C) /* PC02 - EXMC_CE0 */ +#define NAND_CE_PIN (GPIO_PIN_02) +#define NAND_CE_FUNC (GPIO_FUNC_12) + +#define NAND_RE_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ +#define NAND_RE_PIN (GPIO_PIN_11) +#define NAND_RE_FUNC (GPIO_FUNC_12) + +#define NAND_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ +#define NAND_WE_PIN (GPIO_PIN_00) +#define NAND_WE_FUNC (GPIO_FUNC_12) + +#define NAND_CLE_PORT (GPIO_PORT_I) /* PI12 - EXMC_CLE */ +#define NAND_CLE_PIN (GPIO_PIN_12) +#define NAND_CLE_FUNC (GPIO_FUNC_12) + +#define NAND_ALE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ +#define NAND_ALE_PIN (GPIO_PIN_03) +#define NAND_ALE_FUNC (GPIO_FUNC_12) + +#define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ +#define NAND_WP_PIN (GPIO_PIN_15) +#define NAND_WP_FUNC (GPIO_FUNC_12) + +#define NAND_RB_PORT (GPIO_PORT_G) /* PG06 - EXMC_RB0 */ +#define NAND_RB_PIN (GPIO_PIN_06) +#define NAND_RB_FUNC (GPIO_FUNC_12) + +#define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ +#define NAND_DATA0_PIN (GPIO_PIN_14) +#define NAND_DATA0_FUNC (GPIO_FUNC_12) +#define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ +#define NAND_DATA1_PIN (GPIO_PIN_15) +#define NAND_DATA1_FUNC (GPIO_FUNC_12) +#define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ +#define NAND_DATA2_PIN (GPIO_PIN_00) +#define NAND_DATA2_FUNC (GPIO_FUNC_12) +#define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ +#define NAND_DATA3_PIN (GPIO_PIN_01) +#define NAND_DATA3_FUNC (GPIO_FUNC_12) +#define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ +#define NAND_DATA4_PIN (GPIO_PIN_07) +#define NAND_DATA4_FUNC (GPIO_FUNC_12) +#define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ +#define NAND_DATA5_PIN (GPIO_PIN_08) +#define NAND_DATA5_FUNC (GPIO_FUNC_12) +#define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ +#define NAND_DATA6_PIN (GPIO_PIN_09) +#define NAND_DATA6_FUNC (GPIO_FUNC_12) +#define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ +#define NAND_DATA7_PIN (GPIO_PIN_10) +#define NAND_DATA7_FUNC (GPIO_FUNC_12) #endif /************************ SDIOC port **********************/ #if defined(BSP_USING_SDIO1) - #define SDIOC1_CK_PORT (GPIO_PORT_C) - #define SDIOC1_CK_PIN (GPIO_PIN_12) - #define SDIOC1_CK_FUNC (GPIO_FUNC_9) +#define SDIOC1_CK_PORT (GPIO_PORT_C) +#define SDIOC1_CK_PIN (GPIO_PIN_12) +#define SDIOC1_CK_FUNC (GPIO_FUNC_9) - #define SDIOC1_CMD_PORT (GPIO_PORT_D) - #define SDIOC1_CMD_PIN (GPIO_PIN_02) - #define SDIOC1_CMD_FUNC (GPIO_FUNC_9) +#define SDIOC1_CMD_PORT (GPIO_PORT_D) +#define SDIOC1_CMD_PIN (GPIO_PIN_02) +#define SDIOC1_CMD_FUNC (GPIO_FUNC_9) - #define SDIOC1_D0_PORT (GPIO_PORT_B) - #define SDIOC1_D0_PIN (GPIO_PIN_07) - #define SDIOC1_D0_FUNC (GPIO_FUNC_9) +#define SDIOC1_D0_PORT (GPIO_PORT_B) +#define SDIOC1_D0_PIN (GPIO_PIN_07) +#define SDIOC1_D0_FUNC (GPIO_FUNC_9) - #define SDIOC1_D1_PORT (GPIO_PORT_A) - #define SDIOC1_D1_PIN (GPIO_PIN_08) - #define SDIOC1_D1_FUNC (GPIO_FUNC_9) +#define SDIOC1_D1_PORT (GPIO_PORT_A) +#define SDIOC1_D1_PIN (GPIO_PIN_08) +#define SDIOC1_D1_FUNC (GPIO_FUNC_9) - #define SDIOC1_D2_PORT (GPIO_PORT_C) - #define SDIOC1_D2_PIN (GPIO_PIN_10) - #define SDIOC1_D2_FUNC (GPIO_FUNC_9) +#define SDIOC1_D2_PORT (GPIO_PORT_C) +#define SDIOC1_D2_PIN (GPIO_PIN_10) +#define SDIOC1_D2_FUNC (GPIO_FUNC_9) - #define SDIOC1_D3_PORT (GPIO_PORT_B) - #define SDIOC1_D3_PIN (GPIO_PIN_05) - #define SDIOC1_D3_FUNC (GPIO_FUNC_9) +#define SDIOC1_D3_PORT (GPIO_PORT_B) +#define SDIOC1_D3_PIN (GPIO_PIN_05) +#define SDIOC1_D3_FUNC (GPIO_FUNC_9) #endif /************************ SDRAM port **********************/ #if defined(BSP_USING_SDRAM) - #define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ - #define SDRAM_CKE_PIN (GPIO_PIN_03) - #define SDRAM_CKE_FUNC (GPIO_FUNC_12) - - #define SDRAM_CLK_PORT (GPIO_PORT_G) /* PD03 - EXMC_CLK */ - #define SDRAM_CLK_PIN (GPIO_PIN_08) - #define SDRAM_CLK_FUNC (GPIO_FUNC_12) - - #define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ - #define SDRAM_DQM0_PIN (GPIO_PIN_00) - #define SDRAM_DQM0_FUNC (GPIO_FUNC_12) - #define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ - #define SDRAM_DQM1_PIN (GPIO_PIN_01) - #define SDRAM_DQM1_FUNC (GPIO_FUNC_12) - - #define SDRAM_BA0_PORT (GPIO_PORT_D) /* PD11 - EXMC_ADD16 */ - #define SDRAM_BA0_PIN (GPIO_PIN_11) - #define SDRAM_BA0_FUNC (GPIO_FUNC_12) - #define SDRAM_BA1_PORT (GPIO_PORT_D) /* PD12 - EXMC_ADD17 */ - #define SDRAM_BA1_PIN (GPIO_PIN_12) - #define SDRAM_BA1_FUNC (GPIO_FUNC_12) - - #define SDRAM_CS_PORT (GPIO_PORT_G) /* PG09 - EXMC_CE1 */ - #define SDRAM_CS_PIN (GPIO_PIN_09) - #define SDRAM_CS_FUNC (GPIO_FUNC_12) - - #define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ - #define SDRAM_RAS_PIN (GPIO_PIN_11) - #define SDRAM_RAS_FUNC (GPIO_FUNC_12) - - #define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ - #define SDRAM_CAS_PIN (GPIO_PIN_15) - #define SDRAM_CAS_FUNC (GPIO_FUNC_12) - - #define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ - #define SDRAM_WE_PIN (GPIO_PIN_00) - #define SDRAM_WE_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ - #define SDRAM_ADD0_PIN (GPIO_PIN_00) - #define SDRAM_ADD0_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ - #define SDRAM_ADD1_PIN (GPIO_PIN_01) - #define SDRAM_ADD1_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ - #define SDRAM_ADD2_PIN (GPIO_PIN_02) - #define SDRAM_ADD2_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ - #define SDRAM_ADD3_PIN (GPIO_PIN_03) - #define SDRAM_ADD3_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ - #define SDRAM_ADD4_PIN (GPIO_PIN_04) - #define SDRAM_ADD4_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ - #define SDRAM_ADD5_PIN (GPIO_PIN_05) - #define SDRAM_ADD5_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ - #define SDRAM_ADD6_PIN (GPIO_PIN_12) - #define SDRAM_ADD6_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ - #define SDRAM_ADD7_PIN (GPIO_PIN_13) - #define SDRAM_ADD7_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ - #define SDRAM_ADD8_PIN (GPIO_PIN_14) - #define SDRAM_ADD8_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ - #define SDRAM_ADD9_PIN (GPIO_PIN_15) - #define SDRAM_ADD9_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ - #define SDRAM_ADD10_PIN (GPIO_PIN_00) - #define SDRAM_ADD10_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ - #define SDRAM_ADD11_PIN (GPIO_PIN_01) - #define SDRAM_ADD11_FUNC (GPIO_FUNC_12) - - #define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ - #define SDRAM_DATA0_PIN (GPIO_PIN_14) - #define SDRAM_DATA0_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ - #define SDRAM_DATA1_PIN (GPIO_PIN_15) - #define SDRAM_DATA1_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ - #define SDRAM_DATA2_PIN (GPIO_PIN_00) - #define SDRAM_DATA2_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ - #define SDRAM_DATA3_PIN (GPIO_PIN_01) - #define SDRAM_DATA3_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ - #define SDRAM_DATA4_PIN (GPIO_PIN_07) - #define SDRAM_DATA4_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ - #define SDRAM_DATA5_PIN (GPIO_PIN_08) - #define SDRAM_DATA5_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ - #define SDRAM_DATA6_PIN (GPIO_PIN_09) - #define SDRAM_DATA6_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ - #define SDRAM_DATA7_PIN (GPIO_PIN_10) - #define SDRAM_DATA7_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ - #define SDRAM_DATA8_PIN (GPIO_PIN_11) - #define SDRAM_DATA8_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ - #define SDRAM_DATA9_PIN (GPIO_PIN_12) - #define SDRAM_DATA9_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ - #define SDRAM_DATA10_PIN (GPIO_PIN_13) - #define SDRAM_DATA10_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ - #define SDRAM_DATA11_PIN (GPIO_PIN_14) - #define SDRAM_DATA11_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ - #define SDRAM_DATA12_PIN (GPIO_PIN_15) - #define SDRAM_DATA12_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ - #define SDRAM_DATA13_PIN (GPIO_PIN_08) - #define SDRAM_DATA13_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ - #define SDRAM_DATA14_PIN (GPIO_PIN_09) - #define SDRAM_DATA14_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ - #define SDRAM_DATA15_PIN (GPIO_PIN_10) - #define SDRAM_DATA15_FUNC (GPIO_FUNC_12) +#define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ +#define SDRAM_CKE_PIN (GPIO_PIN_03) +#define SDRAM_CKE_FUNC (GPIO_FUNC_12) + +#define SDRAM_CLK_PORT (GPIO_PORT_G) /* PD03 - EXMC_CLK */ +#define SDRAM_CLK_PIN (GPIO_PIN_08) +#define SDRAM_CLK_FUNC (GPIO_FUNC_12) + +#define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ +#define SDRAM_DQM0_PIN (GPIO_PIN_00) +#define SDRAM_DQM0_FUNC (GPIO_FUNC_12) +#define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ +#define SDRAM_DQM1_PIN (GPIO_PIN_01) +#define SDRAM_DQM1_FUNC (GPIO_FUNC_12) + +#define SDRAM_BA0_PORT (GPIO_PORT_D) /* PD11 - EXMC_ADD16 */ +#define SDRAM_BA0_PIN (GPIO_PIN_11) +#define SDRAM_BA0_FUNC (GPIO_FUNC_12) +#define SDRAM_BA1_PORT (GPIO_PORT_D) /* PD12 - EXMC_ADD17 */ +#define SDRAM_BA1_PIN (GPIO_PIN_12) +#define SDRAM_BA1_FUNC (GPIO_FUNC_12) + +#define SDRAM_CS_PORT (GPIO_PORT_G) /* PG09 - EXMC_CE1 */ +#define SDRAM_CS_PIN (GPIO_PIN_09) +#define SDRAM_CS_FUNC (GPIO_FUNC_12) + +#define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ +#define SDRAM_RAS_PIN (GPIO_PIN_11) +#define SDRAM_RAS_FUNC (GPIO_FUNC_12) + +#define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ +#define SDRAM_CAS_PIN (GPIO_PIN_15) +#define SDRAM_CAS_FUNC (GPIO_FUNC_12) + +#define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ +#define SDRAM_WE_PIN (GPIO_PIN_00) +#define SDRAM_WE_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ +#define SDRAM_ADD0_PIN (GPIO_PIN_00) +#define SDRAM_ADD0_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ +#define SDRAM_ADD1_PIN (GPIO_PIN_01) +#define SDRAM_ADD1_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ +#define SDRAM_ADD2_PIN (GPIO_PIN_02) +#define SDRAM_ADD2_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ +#define SDRAM_ADD3_PIN (GPIO_PIN_03) +#define SDRAM_ADD3_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ +#define SDRAM_ADD4_PIN (GPIO_PIN_04) +#define SDRAM_ADD4_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ +#define SDRAM_ADD5_PIN (GPIO_PIN_05) +#define SDRAM_ADD5_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ +#define SDRAM_ADD6_PIN (GPIO_PIN_12) +#define SDRAM_ADD6_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ +#define SDRAM_ADD7_PIN (GPIO_PIN_13) +#define SDRAM_ADD7_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ +#define SDRAM_ADD8_PIN (GPIO_PIN_14) +#define SDRAM_ADD8_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ +#define SDRAM_ADD9_PIN (GPIO_PIN_15) +#define SDRAM_ADD9_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ +#define SDRAM_ADD10_PIN (GPIO_PIN_00) +#define SDRAM_ADD10_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ +#define SDRAM_ADD11_PIN (GPIO_PIN_01) +#define SDRAM_ADD11_FUNC (GPIO_FUNC_12) + +#define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ +#define SDRAM_DATA0_PIN (GPIO_PIN_14) +#define SDRAM_DATA0_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ +#define SDRAM_DATA1_PIN (GPIO_PIN_15) +#define SDRAM_DATA1_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ +#define SDRAM_DATA2_PIN (GPIO_PIN_00) +#define SDRAM_DATA2_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ +#define SDRAM_DATA3_PIN (GPIO_PIN_01) +#define SDRAM_DATA3_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ +#define SDRAM_DATA4_PIN (GPIO_PIN_07) +#define SDRAM_DATA4_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ +#define SDRAM_DATA5_PIN (GPIO_PIN_08) +#define SDRAM_DATA5_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ +#define SDRAM_DATA6_PIN (GPIO_PIN_09) +#define SDRAM_DATA6_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ +#define SDRAM_DATA7_PIN (GPIO_PIN_10) +#define SDRAM_DATA7_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ +#define SDRAM_DATA8_PIN (GPIO_PIN_11) +#define SDRAM_DATA8_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ +#define SDRAM_DATA9_PIN (GPIO_PIN_12) +#define SDRAM_DATA9_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ +#define SDRAM_DATA10_PIN (GPIO_PIN_13) +#define SDRAM_DATA10_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ +#define SDRAM_DATA11_PIN (GPIO_PIN_14) +#define SDRAM_DATA11_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ +#define SDRAM_DATA12_PIN (GPIO_PIN_15) +#define SDRAM_DATA12_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ +#define SDRAM_DATA13_PIN (GPIO_PIN_08) +#define SDRAM_DATA13_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ +#define SDRAM_DATA14_PIN (GPIO_PIN_09) +#define SDRAM_DATA14_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ +#define SDRAM_DATA15_PIN (GPIO_PIN_10) +#define SDRAM_DATA15_FUNC (GPIO_FUNC_12) #endif /************************ RTC/PM *****************************/ #if defined(BSP_USING_RTC) || defined(RT_USING_PM) - #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) - #define XTAL32_PORT (GPIO_PORT_C) - #define XTAL32_IN_PIN (GPIO_PIN_15) - #define XTAL32_OUT_PIN (GPIO_PIN_14) - #endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) +#define XTAL32_PORT (GPIO_PORT_C) +#define XTAL32_IN_PIN (GPIO_PIN_15) +#define XTAL32_OUT_PIN (GPIO_PIN_14) +#endif #endif #if defined(RT_USING_PWM) /*********** PWM_TMRA configure *********/ - #if defined(BSP_USING_PWM_TMRA_1) - #if defined(BSP_USING_PWM_TMRA_1_CH1) - #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) - #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH2) - #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) - #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH3) - #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) - #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH4) - #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) - #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) - #endif - #endif +#if defined(BSP_USING_PWM_TMRA_1) +#if defined(BSP_USING_PWM_TMRA_1_CH1) +#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) +#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH2) +#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) +#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH3) +#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) +#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH4) +#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) +#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) +#endif +#endif /*********** PWM_TMR4 configure *********/ - #if defined(BSP_USING_PWM_TMR4_1) - #if defined(BSP_USING_PWM_TMR4_1_OUH) - #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) - #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OUL) - #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) - #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVH) - #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) - #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVL) - #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) - #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWH) - #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) - #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWL) - #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) - #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) - #endif - #endif +#if defined(BSP_USING_PWM_TMR4_1) +#if defined(BSP_USING_PWM_TMR4_1_OUH) +#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) +#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OUL) +#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) +#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVH) +#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) +#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVL) +#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) +#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWH) +#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) +#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWL) +#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) +#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) +#endif +#endif /*********** PWM_TMR6 configure *********/ - #if defined(BSP_USING_PWM_TMR6_1) - #if defined(BSP_USING_PWM_TMR6_1_A) - #define PWM_TMR6_1_A_PORT (GPIO_PORT_F) - #define PWM_TMR6_1_A_PIN (GPIO_PIN_13) - #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #endif - #if defined(BSP_USING_PWM_TMR6_1_B) - #define PWM_TMR6_1_B_PORT (GPIO_PORT_F) - #define PWM_TMR6_1_B_PIN (GPIO_PIN_14) - #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif - #endif +#if defined(BSP_USING_PWM_TMR6_1) +#if defined(BSP_USING_PWM_TMR6_1_A) +#define PWM_TMR6_1_A_PORT (GPIO_PORT_F) +#define PWM_TMR6_1_A_PIN (GPIO_PIN_13) +#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#endif +#if defined(BSP_USING_PWM_TMR6_1_B) +#define PWM_TMR6_1_B_PORT (GPIO_PORT_F) +#define PWM_TMR6_1_B_PIN (GPIO_PIN_14) +#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif +#endif #endif #if defined(BSP_USING_INPUT_CAPTURE) - #define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3) - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) - #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_B) - #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_09) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) - #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_E) - #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) - #define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) - #define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00) - #endif +#define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_B) +#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_09) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_E) +#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) +#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) +#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00) +#endif #endif #if defined(RT_USING_CHERRYUSB) - #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ - defined(BSP_USING_USBFS) || defined(BSP_USING_USBHS) || \ - defined(BSP_USING_USBHS_PHY_EMBED) || defined(BSP_USING_USBHS_PHY_EXTERN) || \ - defined(RT_USING_USB) - #error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" - #endif +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(BSP_USING_USBHS) || \ + defined(BSP_USING_USBHS_PHY_EMBED) || defined(BSP_USING_USBHS_PHY_EXTERN) || \ + defined(RT_USING_USB) +#error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" +#endif #endif #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) - #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) /* USBFS Core*/ - #define USBF_DP_PORT (GPIO_PORT_A) - #define USBF_DP_PIN (GPIO_PIN_12) - #define USBF_DM_PORT (GPIO_PORT_A) - #define USBF_DM_PIN (GPIO_PIN_11) - #define USBF_VBUS_PORT (GPIO_PORT_A) - #define USBF_VBUS_PIN (GPIO_PIN_09) - #define USBF_VBUS_FUNC (GPIO_FUNC_10) - #define USBF_DRVVBUS_PORT (GPIO_PORT_C) - #define USBF_DRVVBUS_PIN (GPIO_PIN_09) - #define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) - #endif - #if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) +#define USBF_DP_PORT (GPIO_PORT_A) +#define USBF_DP_PIN (GPIO_PIN_12) +#define USBF_DM_PORT (GPIO_PORT_A) +#define USBF_DM_PIN (GPIO_PIN_11) +#define USBF_VBUS_PORT (GPIO_PORT_A) +#define USBF_VBUS_PIN (GPIO_PIN_09) +#define USBF_VBUS_FUNC (GPIO_FUNC_10) +#define USBF_DRVVBUS_PORT (GPIO_PORT_C) +#define USBF_DRVVBUS_PIN (GPIO_PIN_09) +#define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) +#endif +#if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) /* USBHS Core*/ - #if defined(BSP_USING_USBHS_PHY_EMBED) || (defined(RT_USING_CHERRYUSB) && !defined(CONFIG_USB_HS)) - #define USBH_DP_PORT (GPIO_PORT_B) - #define USBH_DP_PIN (GPIO_PIN_15) - #define USBH_DP_FUNC (GPIO_FUNC_10) - #define USBH_DM_PORT (GPIO_PORT_B) - #define USBH_DM_PIN (GPIO_PIN_14) - #define USBH_DM_FUNC (GPIO_FUNC_10) - #define USBH_VBUS_PORT (GPIO_PORT_B) - #define USBH_VBUS_PIN (GPIO_PIN_13) - #define USBH_VBUS_FUNC (GPIO_FUNC_12) - #define USBH_DRVVBUS_PORT (GPIO_PORT_B) - #define USBH_DRVVBUS_PIN (GPIO_PIN_11) - #define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) - #else +#if defined(BSP_USING_USBHS_PHY_EMBED) || (defined(RT_USING_CHERRYUSB) && !defined(CONFIG_USB_HS)) +#define USBH_DP_PORT (GPIO_PORT_B) +#define USBH_DP_PIN (GPIO_PIN_15) +#define USBH_DP_FUNC (GPIO_FUNC_10) +#define USBH_DM_PORT (GPIO_PORT_B) +#define USBH_DM_PIN (GPIO_PIN_14) +#define USBH_DM_FUNC (GPIO_FUNC_10) +#define USBH_VBUS_PORT (GPIO_PORT_B) +#define USBH_VBUS_PIN (GPIO_PIN_13) +#define USBH_VBUS_FUNC (GPIO_FUNC_12) +#define USBH_DRVVBUS_PORT (GPIO_PORT_B) +#define USBH_DRVVBUS_PIN (GPIO_PIN_11) +#define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) +#else /* USBHS Core, external PHY */ - #define USBH_ULPI_CLK_PORT (GPIO_PORT_E) - #define USBH_ULPI_CLK_PIN (GPIO_PIN_12) - #define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_DIR_PORT (GPIO_PORT_C) - #define USBH_ULPI_DIR_PIN (GPIO_PIN_02) - #define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_NXT_PORT (GPIO_PORT_C) - #define USBH_ULPI_NXT_PIN (GPIO_PIN_03) - #define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_STP_PORT (GPIO_PORT_C) - #define USBH_ULPI_STP_PIN (GPIO_PIN_00) - #define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D0_PORT (GPIO_PORT_E) - #define USBH_ULPI_D0_PIN (GPIO_PIN_13) - #define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D1_PORT (GPIO_PORT_E) - #define USBH_ULPI_D1_PIN (GPIO_PIN_14) - #define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D2_PORT (GPIO_PORT_E) - #define USBH_ULPI_D2_PIN (GPIO_PIN_15) - #define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D3_PORT (GPIO_PORT_B) - #define USBH_ULPI_D3_PIN (GPIO_PIN_10) - #define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D4_PORT (GPIO_PORT_B) - #define USBH_ULPI_D4_PIN (GPIO_PIN_11) - #define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D5_PORT (GPIO_PORT_B) - #define USBH_ULPI_D5_PIN (GPIO_PIN_12) - #define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D6_PORT (GPIO_PORT_B) - #define USBH_ULPI_D6_PIN (GPIO_PIN_13) - #define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D7_PORT (GPIO_PORT_E) - #define USBH_ULPI_D7_PIN (GPIO_PIN_11) - #define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_CLK_PORT (GPIO_PORT_E) +#define USBH_ULPI_CLK_PIN (GPIO_PIN_12) +#define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_DIR_PORT (GPIO_PORT_C) +#define USBH_ULPI_DIR_PIN (GPIO_PIN_02) +#define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_NXT_PORT (GPIO_PORT_C) +#define USBH_ULPI_NXT_PIN (GPIO_PIN_03) +#define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_STP_PORT (GPIO_PORT_C) +#define USBH_ULPI_STP_PIN (GPIO_PIN_00) +#define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D0_PORT (GPIO_PORT_E) +#define USBH_ULPI_D0_PIN (GPIO_PIN_13) +#define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D1_PORT (GPIO_PORT_E) +#define USBH_ULPI_D1_PIN (GPIO_PIN_14) +#define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D2_PORT (GPIO_PORT_E) +#define USBH_ULPI_D2_PIN (GPIO_PIN_15) +#define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D3_PORT (GPIO_PORT_B) +#define USBH_ULPI_D3_PIN (GPIO_PIN_10) +#define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D4_PORT (GPIO_PORT_B) +#define USBH_ULPI_D4_PIN (GPIO_PIN_11) +#define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D5_PORT (GPIO_PORT_B) +#define USBH_ULPI_D5_PIN (GPIO_PIN_12) +#define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D6_PORT (GPIO_PORT_B) +#define USBH_ULPI_D6_PIN (GPIO_PIN_13) +#define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D7_PORT (GPIO_PORT_E) +#define USBH_ULPI_D7_PIN (GPIO_PIN_11) +#define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) /* 3300 reset */ - #define USB_3300_RESET_PORT (EIO_PORT1) - #define USB_3300_RESET_PIN (EIO_USB3300_RST) - #endif - #endif +#define USB_3300_RESET_PORT (EIO_PORT1) +#define USB_3300_RESET_PIN (EIO_USB3300_RST) +#endif +#endif #endif #if defined(BSP_USING_QSPI) - #ifndef BSP_QSPI_USING_SOFT_CS +#ifndef BSP_QSPI_USING_SOFT_CS /* QSSN */ - #define QSPI_FLASH_CS_PORT (GPIO_PORT_C) - #define QSPI_FLASH_CS_PIN (GPIO_PIN_07) - #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) - #endif +#define QSPI_FLASH_CS_PORT (GPIO_PORT_C) +#define QSPI_FLASH_CS_PIN (GPIO_PIN_07) +#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) +#endif /* QSCK */ - #define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) - #define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) - #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) +#define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) +#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) /* QSIO0 */ - #define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) - #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) +#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) /* QSIO1 */ - #define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) - #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) +#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) /* QSIO2 */ - #define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) - #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) +#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) /* QSIO3 */ - #define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) - #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) +#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) #endif /*********** TMRA_PULSE_ENCODER configure *********/ #if defined(RT_USING_PULSE_ENCODER) - #if defined(BSP_USING_TMRA_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) - #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) - #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) - #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) - #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) - #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ - #endif /* BSP_USING_TMRA_PULSE_ENCODER */ - - #if defined(BSP_USING_TMR6_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) - #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) - #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) - #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) - #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) - #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ - #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) +#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#endif /* BSP_USING_TMRA_PULSE_ENCODER */ + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#endif /* BSP_USING_TMR6_PULSE_ENCODER */ #endif /* RT_USING_PULSE_ENCODER */ #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h index 4d2de8f7a71..b3eaf9d343f 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/adc_config.h @@ -20,42 +20,41 @@ extern "C" { #ifdef BSP_USING_ADC1 #ifndef ADC1_INIT_PARAMS -#define ADC1_INIT_PARAMS \ - { \ - .name = "adc1", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_MAX, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC1_INIT_PARAMS */ -#if defined (BSP_ADC1_USING_DMA) +#if defined(BSP_ADC1_USING_DMA) #ifndef ADC1_EOCA_DMA_CONFIG -#define ADC1_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC1_EOCA_DMA_INSTANCE, \ - .channel = ADC1_EOCA_DMA_CHANNEL, \ - .clock = ADC1_EOCA_DMA_CLOCK, \ - .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC1_EOCA, \ - .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC1_EOCA_DMA_IRQn, \ - .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ - .int_src = ADC1_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC1_EOCA_DMA_CONFIG */ #endif /* BSP_ADC1_USING_DMA */ @@ -63,42 +62,41 @@ extern "C" { #ifdef BSP_USING_ADC2 #ifndef ADC2_INIT_PARAMS -#define ADC2_INIT_PARAMS \ - { \ - .name = "adc2", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_MAX, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC2_INIT_PARAMS */ -#if defined (BSP_ADC2_USING_DMA) +#if defined(BSP_ADC2_USING_DMA) #ifndef ADC2_EOCA_DMA_CONFIG -#define ADC2_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC2_EOCA_DMA_INSTANCE, \ - .channel = ADC2_EOCA_DMA_CHANNEL, \ - .clock = ADC2_EOCA_DMA_CLOCK, \ - .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC2_EOCA, \ - .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC2_EOCA_DMA_IRQn, \ - .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ - .int_src = ADC2_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC2_EOCA_DMA_CONFIG */ #endif /* BSP_ADC2_USING_DMA */ @@ -106,41 +104,40 @@ extern "C" { #ifdef BSP_USING_ADC3 #ifndef ADC3_INIT_PARAMS -#define ADC3_INIT_PARAMS \ - { \ - .name = "adc3", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_MAX, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC3_INIT_PARAMS */ -#if defined (BSP_ADC3_USING_DMA) +#if defined(BSP_ADC3_USING_DMA) #ifndef ADC3_EOCA_DMA_CONFIG -#define ADC3_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC3_EOCA_DMA_INSTANCE, \ - .channel = ADC3_EOCA_DMA_CHANNEL, \ - .clock = ADC3_EOCA_DMA_CLOCK, \ - .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC3_EOCA, \ - .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC3_EOCA_DMA_IRQn, \ - .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ - .int_src = ADC3_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC3_EOCA_DMA_CONFIG */ #endif /* BSP_ADC3_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h index 4d8cfb7de7f..9f30d75b333 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/can_config.h @@ -19,25 +19,25 @@ extern "C" { #endif #ifdef BSP_USING_CAN1 -#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) -#define CAN1_NAME ("can1") +#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN1_NAME ("can1") #ifndef CAN1_INIT_PARAMS -#define CAN1_INIT_PARAMS \ - { \ - .name = CAN1_NAME, \ - .single_trans_mode = RT_FALSE \ +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ } #endif /* CAN1_INIT_PARAMS */ #endif /* BSP_USING_CAN1 */ #ifdef BSP_USING_CAN2 -#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) -#define CAN2_NAME ("can2") +#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN2_NAME ("can2") #ifndef CAN2_INIT_PARAMS -#define CAN2_INIT_PARAMS \ - { \ - .name = CAN2_NAME, \ - .single_trans_mode = RT_FALSE \ +#define CAN2_INIT_PARAMS \ + { \ + .name = CAN2_NAME, \ + .single_trans_mode = RT_FALSE \ } #endif /* CAN2_INIT_PARAMS */ #endif /* BSP_USING_CAN2 */ @@ -51,76 +51,76 @@ extern "C" { The following bit time configures are based on CAN Clock 40M */ -#define CAN_BIT_TIME_CONFIG_1M_BAUD \ - { \ - .u32Prescaler = 2, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_800K_BAUD \ - { \ - .u32Prescaler = 2, \ - .u32TimeSeg1 = 20, \ - .u32TimeSeg2 = 5, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_500K_BAUD \ - { \ - .u32Prescaler = 4, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_250K_BAUD \ - { \ - .u32Prescaler = 8, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_125K_BAUD \ - { \ - .u32Prescaler = 16, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_100K_BAUD \ - { \ - .u32Prescaler = 20, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_50K_BAUD \ - { \ - .u32Prescaler = 40, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_20K_BAUD \ - { \ - .u32Prescaler = 100, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_10K_BAUD \ - { \ - .u32Prescaler = 200, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h index c4e155dc9a2..54a5fbfc0ef 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dac_config.h @@ -19,38 +19,38 @@ extern "C" { #ifdef BSP_USING_DAC1 #ifndef DAC1_INIT_PARAMS -#define DAC1_INIT_PARAMS \ - { \ - .name = "dac1", \ - .vref = 3300, \ - .data_align = DAC_DATA_ALIGN_RIGHT, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch2_output_enable = RT_TRUE, \ - .ch1_data_src = DAC_DATA_SRC_DATAREG, \ - .ch2_data_src = DAC_DATA_SRC_DATAREG, \ - .ch1_amp_enable = RT_TRUE, \ - .ch2_amp_enable = RT_TRUE, \ +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ #ifdef BSP_USING_DAC2 #ifndef DAC2_INIT_PARAMS -#define DAC2_INIT_PARAMS \ - { \ - .name = "dac2", \ - .vref = 3300, \ - .data_align = DAC_DATA_ALIGN_RIGHT, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch2_output_enable = RT_TRUE, \ - .ch1_data_src = DAC_DATA_SRC_DATAREG, \ - .ch2_data_src = DAC_DATA_SRC_DATAREG, \ - .ch1_amp_enable = RT_TRUE, \ - .ch2_amp_enable = RT_TRUE, \ +#define DAC2_INIT_PARAMS \ + { \ + .name = "dac2", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC2_INIT_PARAMS */ #endif /* BSP_USING_DAC2 */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h index 33e2460a9aa..dd692fdb4fd 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/dma_config.h @@ -20,398 +20,398 @@ extern "C" { /* DMA1 ch0 */ #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) -#define SPI1_RX_DMA_INSTANCE CM_DMA1 -#define SPI1_RX_DMA_CHANNEL DMA_CH0 -#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE) -#define SDIO1_RX_DMA_INSTANCE CM_DMA1 -#define SDIO1_RX_DMA_CHANNEL DMA_CH0 -#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SDIO1_RX_DMA_INSTANCE CM_DMA1 +#define SDIO1_RX_DMA_CHANNEL DMA_CH0 +#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) -#define I2C1_TX_DMA_INSTANCE CM_DMA1 -#define I2C1_TX_DMA_CHANNEL DMA_CH0 -#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 -#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 #endif /* DMA1 ch1 */ #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) -#define SPI1_TX_DMA_INSTANCE CM_DMA1 -#define SPI1_TX_DMA_CHANNEL DMA_CH1 -#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE) -#define SDIO1_TX_DMA_INSTANCE CM_DMA1 -#define SDIO1_TX_DMA_CHANNEL DMA_CH1 -#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SDIO1_TX_DMA_INSTANCE CM_DMA1 +#define SDIO1_TX_DMA_CHANNEL DMA_CH1 +#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) -#define I2C1_RX_DMA_INSTANCE CM_DMA1 -#define I2C1_RX_DMA_CHANNEL DMA_CH1 -#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 -#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 #endif /* DMA1 ch2 */ #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) -#define SPI2_RX_DMA_INSTANCE CM_DMA1 -#define SPI2_RX_DMA_CHANNEL DMA_CH2 -#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE) -#define SDIO2_RX_DMA_INSTANCE CM_DMA1 -#define SDIO2_RX_DMA_CHANNEL DMA_CH2 -#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define SDIO2_RX_DMA_INSTANCE CM_DMA1 +#define SDIO2_RX_DMA_CHANNEL DMA_CH2 +#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) -#define I2C2_TX_DMA_INSTANCE CM_DMA1 -#define I2C2_TX_DMA_CHANNEL DMA_CH2 -#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 -#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 #endif /* DMA1 ch3 */ #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) -#define SPI2_TX_DMA_INSTANCE CM_DMA1 -#define SPI2_TX_DMA_CHANNEL DMA_CH3 -#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE) -#define SDIO2_TX_DMA_INSTANCE CM_DMA1 -#define SDIO2_TX_DMA_CHANNEL DMA_CH3 -#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define SDIO2_TX_DMA_INSTANCE CM_DMA1 +#define SDIO2_TX_DMA_CHANNEL DMA_CH3 +#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE) -#define QSPI_DMA_INSTANCE CM_DMA1 -#define QSPI_DMA_CHANNEL DMA_CH3 -#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 -#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define QSPI_DMA_INSTANCE CM_DMA1 +#define QSPI_DMA_CHANNEL DMA_CH3 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) -#define I2C2_RX_DMA_INSTANCE CM_DMA1 -#define I2C2_RX_DMA_CHANNEL DMA_CH3 -#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 -#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) -#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 -#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 -#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 #endif /* DMA1 ch4 */ #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) -#define SPI3_RX_DMA_INSTANCE CM_DMA1 -#define SPI3_RX_DMA_CHANNEL DMA_CH4 -#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 -#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH4 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 #elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) -#define I2C3_TX_DMA_INSTANCE CM_DMA1 -#define I2C3_TX_DMA_CHANNEL DMA_CH4 -#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 -#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define I2C3_TX_DMA_INSTANCE CM_DMA1 +#define I2C3_TX_DMA_CHANNEL DMA_CH4 +#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 +#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) -#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 -#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 -#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 #endif /* DMA1 ch5 */ #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) -#define SPI3_TX_DMA_INSTANCE CM_DMA1 -#define SPI3_TX_DMA_CHANNEL DMA_CH5 -#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 -#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH5 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 #elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) -#define I2C3_RX_DMA_INSTANCE CM_DMA1 -#define I2C3_RX_DMA_CHANNEL DMA_CH5 -#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 -#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define I2C3_RX_DMA_INSTANCE CM_DMA1 +#define I2C3_RX_DMA_CHANNEL DMA_CH5 +#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 +#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 #elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) -#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 -#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 -#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 #endif /* DMA1 ch6 */ #if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) -#define SPI4_RX_DMA_INSTANCE CM_DMA1 -#define SPI4_RX_DMA_CHANNEL DMA_CH6 -#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 -#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM -#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO -#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#define SPI4_RX_DMA_INSTANCE CM_DMA1 +#define SPI4_RX_DMA_CHANNEL DMA_CH6 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 +#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 #elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE) -#define I2C4_TX_DMA_INSTANCE CM_DMA1 -#define I2C4_TX_DMA_CHANNEL DMA_CH6 -#define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6 -#define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM -#define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO -#define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#define I2C4_TX_DMA_INSTANCE CM_DMA1 +#define I2C4_TX_DMA_CHANNEL DMA_CH6 +#define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6 +#define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6 #endif /* DMA1 ch7 */ #if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) -#define SPI4_TX_DMA_INSTANCE CM_DMA1 -#define SPI4_TX_DMA_CHANNEL DMA_CH7 -#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 -#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM -#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO -#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#define SPI4_TX_DMA_INSTANCE CM_DMA1 +#define SPI4_TX_DMA_CHANNEL DMA_CH7 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 +#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 #elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE) -#define I2C4_RX_DMA_INSTANCE CM_DMA1 -#define I2C4_RX_DMA_CHANNEL DMA_CH7 -#define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7 -#define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM -#define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO -#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#define I2C4_RX_DMA_INSTANCE CM_DMA1 +#define I2C4_RX_DMA_CHANNEL DMA_CH7 +#define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7 +#define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7 #endif /* DMA1 ch8 */ #if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) -#define SPI5_TX_DMA_INSTANCE CM_DMA1 -#define SPI5_TX_DMA_CHANNEL DMA_CH8 -#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 -#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 -#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM -#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO -#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 +#define SPI5_TX_DMA_INSTANCE CM_DMA1 +#define SPI5_TX_DMA_CHANNEL DMA_CH8 +#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 +#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 +#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM +#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO +#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 #endif /* DMA1 ch9 */ #if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) -#define SPI6_TX_DMA_INSTANCE CM_DMA1 -#define SPI6_TX_DMA_CHANNEL DMA_CH9 -#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 -#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 -#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM -#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO -#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 +#define SPI6_TX_DMA_INSTANCE CM_DMA1 +#define SPI6_TX_DMA_CHANNEL DMA_CH9 +#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 +#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 +#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM +#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO +#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 #endif /* DMA2 ch0 */ #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) -#define UART1_RX_DMA_INSTANCE CM_DMA2 -#define UART1_RX_DMA_CHANNEL DMA_CH0 -#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 -#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 #elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE) -#define I2C5_TX_DMA_INSTANCE CM_DMA2 -#define I2C5_TX_DMA_CHANNEL DMA_CH0 -#define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0 -#define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define I2C5_TX_DMA_INSTANCE CM_DMA2 +#define I2C5_TX_DMA_CHANNEL DMA_CH0 +#define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0 +#define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 #endif /* DMA2 ch1 */ #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) -#define UART1_TX_DMA_INSTANCE CM_DMA2 -#define UART1_TX_DMA_CHANNEL DMA_CH1 -#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 -#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 #elif defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE) -#define I2C5_RX_DMA_INSTANCE CM_DMA2 -#define I2C5_RX_DMA_CHANNEL DMA_CH1 -#define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1 -#define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define I2C5_RX_DMA_INSTANCE CM_DMA2 +#define I2C5_RX_DMA_CHANNEL DMA_CH1 +#define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1 +#define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 #endif /* DMA2 ch2 */ #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) -#define UART2_RX_DMA_INSTANCE CM_DMA2 -#define UART2_RX_DMA_CHANNEL DMA_CH2 -#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 -#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 #elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE) -#define I2C6_TX_DMA_INSTANCE CM_DMA2 -#define I2C6_TX_DMA_CHANNEL DMA_CH2 -#define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2 -#define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define I2C6_TX_DMA_INSTANCE CM_DMA2 +#define I2C6_TX_DMA_CHANNEL DMA_CH2 +#define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2 +#define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 #endif /* DMA2 ch3 */ #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) -#define UART2_TX_DMA_INSTANCE CM_DMA2 -#define UART2_TX_DMA_CHANNEL DMA_CH3 -#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 -#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM -#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO -#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 #elif defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE) -#define I2C6_RX_DMA_INSTANCE CM_DMA2 -#define I2C6_RX_DMA_CHANNEL DMA_CH3 -#define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3 -#define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM -#define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO -#define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#define I2C6_RX_DMA_INSTANCE CM_DMA2 +#define I2C6_RX_DMA_CHANNEL DMA_CH3 +#define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3 +#define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3 #endif /* DMA2 ch4 */ #if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) -#define UART6_RX_DMA_INSTANCE CM_DMA2 -#define UART6_RX_DMA_CHANNEL DMA_CH4 -#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 -#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM -#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO -#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#define UART6_RX_DMA_INSTANCE CM_DMA2 +#define UART6_RX_DMA_CHANNEL DMA_CH4 +#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 #endif /* DMA2 ch5 */ #if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) -#define UART6_TX_DMA_INSTANCE CM_DMA2 -#define UART6_TX_DMA_CHANNEL DMA_CH5 -#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 -#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM -#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO -#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#define UART6_TX_DMA_INSTANCE CM_DMA2 +#define UART6_TX_DMA_CHANNEL DMA_CH5 +#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 #endif /* DMA2 ch6 */ #if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) -#define UART7_RX_DMA_INSTANCE CM_DMA2 -#define UART7_RX_DMA_CHANNEL DMA_CH6 -#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 -#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM -#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO -#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 +#define UART7_RX_DMA_INSTANCE CM_DMA2 +#define UART7_RX_DMA_CHANNEL DMA_CH6 +#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 +#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM +#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO +#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 #endif /* DMA2 ch7 */ #if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) -#define UART7_TX_DMA_INSTANCE CM_DMA2 -#define UART7_TX_DMA_CHANNEL DMA_CH7 -#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 -#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM -#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO -#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 +#define UART7_TX_DMA_INSTANCE CM_DMA2 +#define UART7_TX_DMA_CHANNEL DMA_CH7 +#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 +#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM +#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO +#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h index f28e5b19c74..7cd9b201c70 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/eth_config.h @@ -22,11 +22,11 @@ extern "C" { #if defined(BSP_USING_ETH) #ifndef ETH_IRQ_CONFIG -#define ETH_IRQ_CONFIG \ - { \ - .irq_num = BSP_ETH_IRQ_NUM, \ - .irq_prio = BSP_ETH_IRQ_PRIO, \ - .int_src = INT_SRC_ETH_GLB_INT, \ +#define ETH_IRQ_CONFIG \ + { \ + .irq_num = BSP_ETH_IRQ_NUM, \ + .irq_prio = BSP_ETH_IRQ_PRIO, \ + .int_src = INT_SRC_ETH_GLB_INT, \ } #endif /* ETH_IRQ_CONFIG */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h index ee17e1230de..9a2be5862fa 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/gpio_config.h @@ -22,146 +22,146 @@ extern "C" { #if defined(RT_USING_PIN) #ifndef EXTINT0_IRQ_CONFIG -#define EXTINT0_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT0_IRQ_NUM, \ - .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ0, \ +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT1_IRQ_CONFIG -#define EXTINT1_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT1_IRQ_NUM, \ - .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ1, \ +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT2_IRQ_CONFIG -#define EXTINT2_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT2_IRQ_NUM, \ - .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ2, \ +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ } #endif /* EXTINT2_IRQ_CONFIG */ #ifndef EXTINT3_IRQ_CONFIG -#define EXTINT3_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT3_IRQ_NUM, \ - .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ3, \ +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ } #endif /* EXTINT3_IRQ_CONFIG */ #ifndef EXTINT4_IRQ_CONFIG -#define EXTINT4_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT4_IRQ_NUM, \ - .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ4, \ +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ } #endif /* EXTINT4_IRQ_CONFIG */ #ifndef EXTINT5_IRQ_CONFIG -#define EXTINT5_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT5_IRQ_NUM, \ - .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ5, \ +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ } #endif /* EXTINT5_IRQ_CONFIG */ #ifndef EXTINT6_IRQ_CONFIG -#define EXTINT6_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT6_IRQ_NUM, \ - .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ6, \ +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ } #endif /* EXTINT6_IRQ_CONFIG */ #ifndef EXTINT7_IRQ_CONFIG -#define EXTINT7_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT7_IRQ_NUM, \ - .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ7, \ +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ } #endif /* EXTINT7_IRQ_CONFIG */ #ifndef EXTINT8_IRQ_CONFIG -#define EXTINT8_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT8_IRQ_NUM, \ - .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ8, \ +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ } #endif /* EXTINT8_IRQ_CONFIG */ #ifndef EXTINT9_IRQ_CONFIG -#define EXTINT9_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT9_IRQ_NUM, \ - .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ9, \ +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ } #endif /* EXTINT9_IRQ_CONFIG */ #ifndef EXTINT10_IRQ_CONFIG -#define EXTINT10_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT10_IRQ_NUM, \ - .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ10, \ +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ } #endif /* EXTINT10_IRQ_CONFIG */ #ifndef EXTINT11_IRQ_CONFIG -#define EXTINT11_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT11_IRQ_NUM, \ - .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ11, \ +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ } #endif /* EXTINT11_IRQ_CONFIG */ #ifndef EXTINT12_IRQ_CONFIG -#define EXTINT12_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT12_IRQ_NUM, \ - .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ12, \ +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ } #endif /* EXTINT12_IRQ_CONFIG */ #ifndef EXTINT13_IRQ_CONFIG -#define EXTINT13_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT13_IRQ_NUM, \ - .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ13, \ +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ } #endif /* EXTINT13_IRQ_CONFIG */ #ifndef EXTINT14_IRQ_CONFIG -#define EXTINT14_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT14_IRQ_NUM, \ - .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ14, \ +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ } #endif /* EXTINT14_IRQ_CONFIG */ #ifndef EXTINT15_IRQ_CONFIG -#define EXTINT15_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT15_IRQ_NUM, \ - .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ15, \ +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ } #endif /* EXTINT15_IRQ_CONFIG */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/i2c_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/i2c_config.h index 57fe15696ff..7eea731a079 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/i2c_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/i2c_config.h @@ -20,101 +20,97 @@ extern "C" { #if defined(BSP_USING_I2C1) #ifndef I2C1_CONFIG -#define I2C1_CONFIG \ - { \ - .name = "i2c1", \ - .Instance = CM_I2C1, \ - .clock = FCG1_PERIPH_I2C1, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C1_CONFIG */ #endif #if defined(BSP_I2C1_USING_DMA) #ifndef I2C1_TX_DMA_CONFIG -#define I2C1_TX_DMA_CONFIG \ - { \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .channel = I2C1_TX_DMA_CHANNEL, \ - .clock = I2C1_TX_DMA_CLOCK, \ - .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_TEI, \ - .flag = I2C1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_TX_DMA_IRQn, \ - .irq_prio = I2C1_TX_DMA_INT_PRIO, \ - .int_src = I2C1_TX_DMA_INT_SRC, \ - }, \ +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_TX_DMA_CONFIG */ #ifndef I2C1_RX_DMA_CONFIG -#define I2C1_RX_DMA_CONFIG \ - { \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .channel = I2C1_RX_DMA_CHANNEL, \ - .clock = I2C1_RX_DMA_CLOCK, \ - .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_RXI, \ - .flag = I2C1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_RX_DMA_IRQn, \ - .irq_prio = I2C1_RX_DMA_INT_PRIO, \ - .int_src = I2C1_RX_DMA_INT_SRC, \ - }, \ +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_RX_DMA_CONFIG */ #endif /* BSP_I2C1_USING_DMA */ #if defined(BSP_USING_I2C2) #ifndef I2C2_CONFIG -#define I2C2_CONFIG \ - { \ - .name = "i2c2", \ - .Instance = CM_I2C2, \ - .clock = FCG1_PERIPH_I2C2, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C2_CONFIG */ #if defined(BSP_I2C2_USING_DMA) #ifndef I2C2_TX_DMA_CONFIG -#define I2C2_TX_DMA_CONFIG \ - { \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .channel = I2C2_TX_DMA_CHANNEL, \ - .clock = I2C2_TX_DMA_CLOCK, \ - .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_TEI, \ - .flag = I2C2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_TX_DMA_IRQn, \ - .irq_prio = I2C2_TX_DMA_INT_PRIO, \ - .int_src = I2C2_TX_DMA_INT_SRC, \ - }, \ +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_TX_DMA_CONFIG */ #ifndef I2C2_RX_DMA_CONFIG -#define I2C2_RX_DMA_CONFIG \ - { \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .channel = I2C2_RX_DMA_CHANNEL, \ - .clock = I2C2_RX_DMA_CLOCK, \ - .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_RXI, \ - .flag = I2C2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_RX_DMA_IRQn, \ - .irq_prio = I2C2_RX_DMA_INT_PRIO, \ - .int_src = I2C2_RX_DMA_INT_SRC, \ - }, \ +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_RX_DMA_CONFIG */ #endif /* BSP_I2C2_USING_DMA */ @@ -122,50 +118,48 @@ extern "C" { #if defined(BSP_USING_I2C3) #ifndef I2C3_CONFIG -#define I2C3_CONFIG \ - { \ - .name = "i2c3", \ - .Instance = CM_I2C3, \ - .clock = FCG1_PERIPH_I2C3, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C3_CONFIG */ #if defined(BSP_I2C3_USING_DMA) #ifndef I2C3_TX_DMA_CONFIG -#define I2C3_TX_DMA_CONFIG \ - { \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .channel = I2C3_TX_DMA_CHANNEL, \ - .clock = I2C3_TX_DMA_CLOCK, \ - .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_TEI, \ - .flag = I2C3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_TX_DMA_IRQn, \ - .irq_prio = I2C3_TX_DMA_INT_PRIO, \ - .int_src = I2C3_TX_DMA_INT_SRC, \ - }, \ +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_TX_DMA_CONFIG */ #ifndef I2C3_RX_DMA_CONFIG -#define I2C3_RX_DMA_CONFIG \ - { \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .channel = I2C3_RX_DMA_CHANNEL, \ - .clock = I2C3_RX_DMA_CLOCK, \ - .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_RXI, \ - .flag = I2C3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_RX_DMA_IRQn, \ - .irq_prio = I2C3_RX_DMA_INT_PRIO, \ - .int_src = I2C3_RX_DMA_INT_SRC, \ - }, \ +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_RX_DMA_CONFIG */ #endif /* BSP_I2C3_USING_DMA */ @@ -173,50 +167,48 @@ extern "C" { #if defined(BSP_USING_I2C4) #ifndef I2C4_CONFIG -#define I2C4_CONFIG \ - { \ - .name = "i2c4", \ - .Instance = CM_I2C4, \ - .clock = FCG1_PERIPH_I2C4, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C4_CONFIG \ + { \ + .name = "i2c4", \ + .Instance = CM_I2C4, \ + .clock = FCG1_PERIPH_I2C4, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C4_CONFIG */ #if defined(BSP_I2C4_USING_DMA) #ifndef I2C4_TX_DMA_CONFIG -#define I2C4_TX_DMA_CONFIG \ - { \ - .Instance = I2C4_TX_DMA_INSTANCE, \ - .channel = I2C4_TX_DMA_CHANNEL, \ - .clock = I2C4_TX_DMA_CLOCK, \ - .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C4_TEI, \ - .flag = I2C4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C4_TX_DMA_IRQn, \ - .irq_prio = I2C4_TX_DMA_INT_PRIO, \ - .int_src = I2C4_TX_DMA_INT_SRC, \ - }, \ +#define I2C4_TX_DMA_CONFIG \ + { \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + .clock = I2C4_TX_DMA_CLOCK, \ + .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_TEI, \ + .flag = I2C4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_TX_DMA_IRQn, \ + .irq_prio = I2C4_TX_DMA_INT_PRIO, \ + .int_src = I2C4_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C4_TX_DMA_CONFIG */ #ifndef I2C4_RX_DMA_CONFIG -#define I2C4_RX_DMA_CONFIG \ - { \ - .Instance = I2C4_RX_DMA_INSTANCE, \ - .channel = I2C4_RX_DMA_CHANNEL, \ - .clock = I2C4_RX_DMA_CLOCK, \ - .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C4_RXI, \ - .flag = I2C4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C4_RX_DMA_IRQn, \ - .irq_prio = I2C4_RX_DMA_INT_PRIO, \ - .int_src = I2C4_RX_DMA_INT_SRC, \ - }, \ +#define I2C4_RX_DMA_CONFIG \ + { \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + .clock = I2C4_RX_DMA_CLOCK, \ + .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_RXI, \ + .flag = I2C4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_RX_DMA_IRQn, \ + .irq_prio = I2C4_RX_DMA_INT_PRIO, \ + .int_src = I2C4_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C4_RX_DMA_CONFIG */ #endif /* BSP_I2C4_USING_DMA */ @@ -224,50 +216,48 @@ extern "C" { #if defined(BSP_USING_I2C5) #ifndef I2C5_CONFIG -#define I2C5_CONFIG \ - { \ - .name = "i2c5", \ - .Instance = CM_I2C5, \ - .clock = FCG1_PERIPH_I2C5, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C5_CONFIG \ + { \ + .name = "i2c5", \ + .Instance = CM_I2C5, \ + .clock = FCG1_PERIPH_I2C5, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C5_CONFIG */ #if defined(BSP_I2C5_USING_DMA) #ifndef I2C5_TX_DMA_CONFIG -#define I2C5_TX_DMA_CONFIG \ - { \ - .Instance = I2C5_TX_DMA_INSTANCE, \ - .channel = I2C5_TX_DMA_CHANNEL, \ - .clock = I2C5_TX_DMA_CLOCK, \ - .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C5_TEI, \ - .flag = I2C5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C5_TX_DMA_IRQn, \ - .irq_prio = I2C5_TX_DMA_INT_PRIO, \ - .int_src = I2C5_TX_DMA_INT_SRC, \ - }, \ +#define I2C5_TX_DMA_CONFIG \ + { \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .channel = I2C5_TX_DMA_CHANNEL, \ + .clock = I2C5_TX_DMA_CLOCK, \ + .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_TEI, \ + .flag = I2C5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_TX_DMA_IRQn, \ + .irq_prio = I2C5_TX_DMA_INT_PRIO, \ + .int_src = I2C5_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C5_TX_DMA_CONFIG */ #ifndef I2C5_RX_DMA_CONFIG -#define I2C5_RX_DMA_CONFIG \ - { \ - .Instance = I2C5_RX_DMA_INSTANCE, \ - .channel = I2C5_RX_DMA_CHANNEL, \ - .clock = I2C5_RX_DMA_CLOCK, \ - .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C5_RXI, \ - .flag = I2C5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C5_RX_DMA_IRQn, \ - .irq_prio = I2C5_RX_DMA_INT_PRIO, \ - .int_src = I2C5_RX_DMA_INT_SRC, \ - }, \ +#define I2C5_RX_DMA_CONFIG \ + { \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .channel = I2C5_RX_DMA_CHANNEL, \ + .clock = I2C5_RX_DMA_CLOCK, \ + .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_RXI, \ + .flag = I2C5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_RX_DMA_IRQn, \ + .irq_prio = I2C5_RX_DMA_INT_PRIO, \ + .int_src = I2C5_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C5_RX_DMA_CONFIG */ #endif /* BSP_I2C5_USING_DMA */ @@ -275,50 +265,48 @@ extern "C" { #if defined(BSP_USING_I2C6) #ifndef I2C6_CONFIG -#define I2C6_CONFIG \ - { \ - .name = "i2c6", \ - .Instance = CM_I2C6, \ - .clock = FCG1_PERIPH_I2C6, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C6_CONFIG \ + { \ + .name = "i2c6", \ + .Instance = CM_I2C6, \ + .clock = FCG1_PERIPH_I2C6, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C6_CONFIG */ #if defined(BSP_I2C6_USING_DMA) #ifndef I2C6_TX_DMA_CONFIG -#define I2C6_TX_DMA_CONFIG \ - { \ - .Instance = I2C6_TX_DMA_INSTANCE, \ - .channel = I2C6_TX_DMA_CHANNEL, \ - .clock = I2C6_TX_DMA_CLOCK, \ - .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C6_TEI, \ - .flag = I2C6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C6_TX_DMA_IRQn, \ - .irq_prio = I2C6_TX_DMA_INT_PRIO, \ - .int_src = I2C6_TX_DMA_INT_SRC, \ - }, \ +#define I2C6_TX_DMA_CONFIG \ + { \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .channel = I2C6_TX_DMA_CHANNEL, \ + .clock = I2C6_TX_DMA_CLOCK, \ + .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_TEI, \ + .flag = I2C6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_TX_DMA_IRQn, \ + .irq_prio = I2C6_TX_DMA_INT_PRIO, \ + .int_src = I2C6_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C6_TX_DMA_CONFIG */ #ifndef I2C6_RX_DMA_CONFIG -#define I2C6_RX_DMA_CONFIG \ - { \ - .Instance = I2C6_RX_DMA_INSTANCE, \ - .channel = I2C6_RX_DMA_CHANNEL, \ - .clock = I2C6_RX_DMA_CLOCK, \ - .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C6_RXI, \ - .flag = I2C6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C6_RX_DMA_IRQn, \ - .irq_prio = I2C6_RX_DMA_INT_PRIO, \ - .int_src = I2C6_RX_DMA_INT_SRC, \ - }, \ +#define I2C6_RX_DMA_CONFIG \ + { \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .channel = I2C6_RX_DMA_CHANNEL, \ + .clock = I2C6_RX_DMA_CLOCK, \ + .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_RXI, \ + .flag = I2C6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_RX_DMA_IRQn, \ + .irq_prio = I2C6_RX_DMA_INT_PRIO, \ + .int_src = I2C6_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C6_RX_DMA_CONFIG */ #endif /* BSP_I2C6_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h index 9ceb83944b1..d5b36a81709 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/irq_config.h @@ -17,498 +17,498 @@ extern "C" { #endif -#define BSP_EXTINT0_IRQ_NUM INT022_IRQn -#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT1_IRQ_NUM INT023_IRQn -#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT2_IRQ_NUM INT024_IRQn -#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT3_IRQ_NUM INT025_IRQn -#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT4_IRQ_NUM INT026_IRQn -#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT5_IRQ_NUM INT027_IRQn -#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT6_IRQ_NUM INT028_IRQn -#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT7_IRQ_NUM INT029_IRQn -#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT8_IRQ_NUM INT030_IRQn -#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT9_IRQ_NUM INT031_IRQn -#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT10_IRQ_NUM INT032_IRQn -#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT11_IRQ_NUM INT033_IRQn -#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT12_IRQ_NUM INT034_IRQn -#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT13_IRQ_NUM INT035_IRQn -#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT14_IRQ_NUM INT036_IRQn -#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT15_IRQ_NUM INT037_IRQn -#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch0 */ -#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn -#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch1 */ -#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn -#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch2 */ -#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn -#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch3 */ -#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn -#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch4 */ -#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn -#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch5 */ -#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn -#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch6 */ -#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn -#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch7 */ -#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn -#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch8 */ -#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn -#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn +#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch9 */ -#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn -#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn +#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch0 */ -#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn -#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch1 */ -#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn -#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch2 */ -#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn -#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch3 */ -#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn -#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch4 */ -#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn -#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch5 */ -#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn -#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch6 */ -#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn -#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn +#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch7 */ -#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn -#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn +#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_USING_ETH) -#define BSP_ETH_IRQ_NUM INT104_IRQn -#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_ETH_IRQ_NUM INT104_IRQn +#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_UART1) -#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn -#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART1_RX_IRQ_NUM INT089_IRQn -#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART1_TX_IRQ_NUM INT088_IRQn -#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT089_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT088_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART1_RX_USING_DMA) -#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn -#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) -#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) -#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn -#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART2_RX_IRQ_NUM INT091_IRQn -#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART2_TX_IRQ_NUM INT090_IRQn -#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT091_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT090_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART2_RX_USING_DMA) -#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn -#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) -#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) -#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn -#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART3_RX_IRQ_NUM INT095_IRQn -#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART3_TX_IRQ_NUM INT094_IRQn -#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT095_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT094_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART3 */ #if defined(BSP_USING_UART4) -#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn -#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART4_RX_IRQ_NUM INT097_IRQn -#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART4_TX_IRQ_NUM INT096_IRQn -#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT097_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT096_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_UART5) -#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn -#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART5_RX_IRQ_NUM INT101_IRQn -#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART5_TX_IRQ_NUM INT100_IRQn -#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn +#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RX_IRQ_NUM INT101_IRQn +#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_IRQ_NUM INT100_IRQn +#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART5 */ #if defined(BSP_USING_UART6) -#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn -#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART6_RX_IRQ_NUM INT103_IRQn -#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART6_TX_IRQ_NUM INT102_IRQn -#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn +#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RX_IRQ_NUM INT103_IRQn +#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_IRQ_NUM INT102_IRQn +#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART6_RX_USING_DMA) -#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn -#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn +#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) -#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn -#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn -#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART6 */ #if defined(BSP_USING_UART7) -#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn -#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART7_RX_IRQ_NUM INT107_IRQn -#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART7_TX_IRQ_NUM INT106_IRQn -#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn +#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RX_IRQ_NUM INT107_IRQn +#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_IRQ_NUM INT106_IRQn +#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART7_RX_USING_DMA) -#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn -#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn +#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) -#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn -#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn -#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #elif defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) -#define BSP_SPI1_ERR_IRQ_NUM INT009_IRQn -#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_SPI2_ERR_IRQ_NUM INT016_IRQn -#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI1_ERR_IRQ_NUM INT009_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM INT016_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART7 */ #if defined(BSP_USING_SPI3) -#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn -#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI4) -#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn -#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn +#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI5) -#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn -#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn +#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI6) -#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn -#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn +#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_UART8) -#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn -#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART8_RX_IRQ_NUM INT109_IRQn -#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART8_TX_IRQ_NUM INT108_IRQn -#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn +#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RX_IRQ_NUM INT109_IRQn +#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_IRQ_NUM INT108_IRQn +#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(RT_USING_SERIAL_V2) -#define BSP_UART8_TX_CPLT_IRQ_NUM INT001_IRQn -#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_CPLT_IRQ_NUM INT001_IRQn +#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART8 */ #if defined(BSP_USING_UART9) -#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn -#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART9_RX_IRQ_NUM INT110_IRQn -#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART9_TX_IRQ_NUM INT111_IRQn -#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn +#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RX_IRQ_NUM INT110_IRQn +#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_TX_IRQ_NUM INT111_IRQn +#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART9 */ #if defined(BSP_USING_UART10) -#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn -#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART10_RX_IRQ_NUM INT114_IRQn -#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART10_TX_IRQ_NUM INT113_IRQn -#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn +#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RX_IRQ_NUM INT114_IRQn +#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_IRQ_NUM INT113_IRQn +#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART10 */ #if defined(BSP_USING_CAN1) -#define BSP_CAN1_IRQ_NUM INT092_IRQn -#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_CAN1_IRQ_NUM INT092_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_CAN1 */ #if defined(BSP_USING_CAN2) -#define BSP_CAN2_IRQ_NUM INT093_IRQn -#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_CAN2_IRQ_NUM INT093_IRQn +#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_CAN2 */ #if defined(BSP_USING_SDIO1) -#define BSP_SDIO1_IRQ_NUM INT004_IRQn -#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SDIO1_IRQ_NUM INT004_IRQn +#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_SDIO1 */ #if defined(BSP_USING_SDIO2) -#define BSP_SDIO2_IRQ_NUM INT005_IRQn -#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SDIO2_IRQ_NUM INT005_IRQn +#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_SDIO2 */ #if defined(RT_USING_ALARM) -#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn -#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* RT_USING_ALARM */ #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) -#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn -#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn +#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBFS */ #if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) -#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn -#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn +#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBHS */ -#if defined (BSP_USING_QSPI) -#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn -#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#if defined(BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_QSPI */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_2) -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_3) -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_4) -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_5) -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_6) -#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn -#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn -#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_7) -#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn -#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn -#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_7 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_8) -#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn -#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn -#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_8 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_9) -#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM INT098_IRQn -#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM INT099_IRQn -#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM INT098_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM INT099_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_9 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_10) -#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM INT100_IRQn -#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM INT101_IRQn -#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM INT100_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM INT101_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_10 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_11) -#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM INT102_IRQn -#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM INT103_IRQn -#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_11 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_12) -#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM INT102_IRQn -#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM INT103_IRQn -#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_12 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_2) -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_3) -#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn -#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn -#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_4) -#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM INT068_IRQn -#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM INT069_IRQn -#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM INT068_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM INT069_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_5) -#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM INT074_IRQn -#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM INT075_IRQn -#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_6) -#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM INT076_IRQn -#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM INT077_IRQn -#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_6 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_7) -#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM INT080_IRQn -#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM INT081_IRQn -#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_7 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_8) -#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM INT082_IRQn -#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM INT083_IRQn -#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_8 */ #if defined(BSP_USING_TMRA_1) -#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn -#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_1 */ #if defined(BSP_USING_TMRA_2) -#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn -#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_2 */ #if defined(BSP_USING_TMRA_3) -#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn -#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_3 */ #if defined(BSP_USING_TMRA_4) -#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn -#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_4 */ #if defined(BSP_USING_TMRA_5) -#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn -#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_5 */ #if defined(BSP_USING_TMRA_6) -#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn -#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn +#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_6 */ #if defined(BSP_USING_TMRA_7) -#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn -#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn +#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_7 */ #if defined(BSP_USING_TMRA_8) -#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn -#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn +#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_8 */ #if defined(BSP_USING_TMRA_9) -#define BSP_USING_TMRA_9_IRQ_NUM INT098_IRQn -#define BSP_USING_TMRA_9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_9_IRQ_NUM INT098_IRQn +#define BSP_USING_TMRA_9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_9 */ #if defined(BSP_USING_TMRA_10) -#define BSP_USING_TMRA_10_IRQ_NUM INT099_IRQn -#define BSP_USING_TMRA_10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_10_IRQ_NUM INT099_IRQn +#define BSP_USING_TMRA_10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_10 */ #if defined(BSP_USING_TMRA_11) -#define BSP_USING_TMRA_11_IRQ_NUM INT100_IRQn -#define BSP_USING_TMRA_11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_11_IRQ_NUM INT100_IRQn +#define BSP_USING_TMRA_11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_11 */ #if defined(BSP_USING_TMRA_12) -#define BSP_USING_TMRA_12_IRQ_NUM INT101_IRQn -#define BSP_USING_TMRA_12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_12_IRQ_NUM INT101_IRQn +#define BSP_USING_TMRA_12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_12 */ #if defined(BSP_USING_INPUT_CAPTURE) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pm_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pm_config.h index bdfd289f007..ccc45e96c97 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pm_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pm_config.h @@ -22,16 +22,16 @@ extern "C" { extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); #ifndef PM_TICKLESS_TIMER_ENABLE_MASK -#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL) +#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL) #endif /** * @brief run mode config @ref pm_run_mode_config structure */ #ifndef PM_RUN_MODE_CFG -#define PM_RUN_MODE_CFG \ - { \ - .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ } #endif /* PM_RUN_MODE_CFG */ @@ -39,54 +39,54 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); * @brief sleep idle config @ref pm_sleep_mode_idle_config structure */ #ifndef PM_SLEEP_IDLE_CFG -#define PM_SLEEP_IDLE_CFG \ -{ \ - .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ -} +#define PM_SLEEP_IDLE_CFG \ + { \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ + } #endif /*PM_SLEEP_IDLE_CFG*/ /** * @brief sleep deep config @ref pm_sleep_mode_deep_config structure */ #ifndef PM_SLEEP_DEEP_CFG -#define PM_SLEEP_DEEP_CFG \ -{ \ - { \ - .u16Clock = PWC_STOP_CLK_KEEP, \ - .u8StopDrv = PWC_STOP_DRV_HIGH, \ - .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ - .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ - }, \ - .pwc_stop_type = PWC_STOP_WFE_INT, \ -} +#define PM_SLEEP_DEEP_CFG \ + { \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ + } #endif /*PM_SLEEP_DEEP_CFG*/ /** * @brief sleep standby config @ref pm_sleep_mode_standby_config structure */ #ifndef PM_SLEEP_STANDBY_CFG -#define PM_SLEEP_STANDBY_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD1, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ - }, \ -} +#define PM_SLEEP_STANDBY_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } #endif /*PM_SLEEP_STANDBY_CFG*/ /** * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure */ #ifndef PM_SLEEP_SHUTDOWN_CFG -#define PM_SLEEP_SHUTDOWN_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD3, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ - }, \ -} +#define PM_SLEEP_SHUTDOWN_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } #endif /*PM_SLEEP_SHUTDOWN_CFG*/ #endif /* BSP_USING_PM */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pulse_encoder_config.h index 1db10b6d14c..aaa9fea6ba4 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pulse_encoder_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pulse_encoder_config.h @@ -21,520 +21,480 @@ extern "C" { #ifdef BSP_USING_PULSE_ENCODER_TMRA_1 #ifndef PULSE_ENCODER_TMRA_1_CONFIG -#define PULSE_ENCODER_TMRA_1_CONFIG \ - { \ - .tmr_handler = CM_TMRA_1, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a1" \ +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ } #endif /* PULSE_ENCODER_TMRA_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_2 #ifndef PULSE_ENCODER_TMRA_2_CONFIG -#define PULSE_ENCODER_TMRA_2_CONFIG \ - { \ - .tmr_handler = CM_TMRA_2, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a2" \ +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ } #endif /* PULSE_ENCODER_TMRA_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_3 #ifndef PULSE_ENCODER_TMRA_3_CONFIG -#define PULSE_ENCODER_TMRA_3_CONFIG \ - { \ - .tmr_handler = CM_TMRA_3, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a3" \ +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ } #endif /* PULSE_ENCODER_TMRA_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_4 #ifndef PULSE_ENCODER_TMRA_4_CONFIG -#define PULSE_ENCODER_TMRA_4_CONFIG \ - { \ - .tmr_handler = CM_TMRA_4, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a4" \ +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ } #endif /* PULSE_ENCODER_TMRA_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_5 #ifndef PULSE_ENCODER_TMRA_5_CONFIG -#define PULSE_ENCODER_TMRA_5_CONFIG \ - { \ - .tmr_handler = CM_TMRA_5, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a5" \ +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ } #endif /* PULSE_ENCODER_TMRA_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_6 #ifndef PULSE_ENCODER_TMRA_6_CONFIG -#define PULSE_ENCODER_TMRA_6_CONFIG \ - { \ - .tmr_handler = CM_TMRA_6, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a6" \ +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ } #endif /* PULSE_ENCODER_TMRA_6_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_7 #ifndef PULSE_ENCODER_TMRA_7_CONFIG -#define PULSE_ENCODER_TMRA_7_CONFIG \ - { \ - .tmr_handler = CM_TMRA_7, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_7, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a7" \ +#define PULSE_ENCODER_TMRA_7_CONFIG \ + { \ + .tmr_handler = CM_TMRA_7, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_7, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a7" \ } #endif /* PULSE_ENCODER_TMRA_7_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_8 #ifndef PULSE_ENCODER_TMRA_8_CONFIG -#define PULSE_ENCODER_TMRA_8_CONFIG \ - { \ - .tmr_handler = CM_TMRA_8, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_8, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a8" \ +#define PULSE_ENCODER_TMRA_8_CONFIG \ + { \ + .tmr_handler = CM_TMRA_8, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_8, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a8" \ } #endif /* PULSE_ENCODER_TMRA_8_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_9 #ifndef PULSE_ENCODER_TMRA_9_CONFIG -#define PULSE_ENCODER_TMRA_9_CONFIG \ - { \ - .tmr_handler = CM_TMRA_9, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_9, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_9_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_9_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a9" \ +#define PULSE_ENCODER_TMRA_9_CONFIG \ + { \ + .tmr_handler = CM_TMRA_9, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_9, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_9_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_9_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a9" \ } #endif /* PULSE_ENCODER_TMRA_9_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_10 #ifndef PULSE_ENCODER_TMRA_10_CONFIG -#define PULSE_ENCODER_TMRA_10_CONFIG \ - { \ - .tmr_handler = CM_TMRA_10, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_10, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_10_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_10_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a10" \ +#define PULSE_ENCODER_TMRA_10_CONFIG \ + { \ + .tmr_handler = CM_TMRA_10, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_10, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_10_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_10_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a10" \ } #endif /* PULSE_ENCODER_TMRA_10_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_11 #ifndef PULSE_ENCODER_TMRA_11_CONFIG -#define PULSE_ENCODER_TMRA_11_CONFIG \ - { \ - .tmr_handler = CM_TMRA_11, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_11, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_11_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_11_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a11" \ +#define PULSE_ENCODER_TMRA_11_CONFIG \ + { \ + .tmr_handler = CM_TMRA_11, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_11, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_11_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_11_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a11" \ } #endif /* PULSE_ENCODER_TMRA_11_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_12 #ifndef PULSE_ENCODER_TMRA_12_CONFIG -#define PULSE_ENCODER_TMRA_12_CONFIG \ - { \ - .tmr_handler = CM_TMRA_12, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_12, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_12_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_12_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a12" \ +#define PULSE_ENCODER_TMRA_12_CONFIG \ + { \ + .tmr_handler = CM_TMRA_12, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_12, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_12_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_12_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a12" \ } #endif /* PULSE_ENCODER_TMRA_12_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_1 #ifndef PULSE_ENCODER_TMR6_1_CONFIG -#define PULSE_ENCODER_TMR6_1_CONFIG \ - { \ - .tmr_handler = CM_TMR6_1, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_61" \ +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ } #endif /* PULSE_ENCODER_TMR6_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_2 #ifndef PULSE_ENCODER_TMR6_2_CONFIG -#define PULSE_ENCODER_TMR6_2_CONFIG \ - { \ - .tmr_handler = CM_TMR6_2, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_62" \ +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ } #endif /* PULSE_ENCODER_TMR6_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_3 #ifndef PULSE_ENCODER_TMR6_3_CONFIG -#define PULSE_ENCODER_TMR6_3_CONFIG \ - { \ - .tmr_handler = CM_TMR6_3, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_63" \ +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ } #endif /* PULSE_ENCODER_TMR6_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_4 #ifndef PULSE_ENCODER_TMR6_4_CONFIG -#define PULSE_ENCODER_TMR6_4_CONFIG \ - { \ - .tmr_handler = CM_TMR6_4, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_4, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_64" \ +#define PULSE_ENCODER_TMR6_4_CONFIG \ + { \ + .tmr_handler = CM_TMR6_4, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_4, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_64" \ } #endif /* PULSE_ENCODER_TMR6_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_5 #ifndef PULSE_ENCODER_TMR6_5_CONFIG -#define PULSE_ENCODER_TMR6_5_CONFIG \ - { \ - .tmr_handler = CM_TMR6_5, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_5, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_65" \ +#define PULSE_ENCODER_TMR6_5_CONFIG \ + { \ + .tmr_handler = CM_TMR6_5, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_5, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_65" \ } #endif /* PULSE_ENCODER_TMR6_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_6 #ifndef PULSE_ENCODER_TMR6_6_CONFIG -#define PULSE_ENCODER_TMR6_6_CONFIG \ - { \ - .tmr_handler = CM_TMR6_6, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_6, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_66" \ +#define PULSE_ENCODER_TMR6_6_CONFIG \ + { \ + .tmr_handler = CM_TMR6_6, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_6, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_66" \ } #endif /* PULSE_ENCODER_TMR6_6_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_7 #ifndef PULSE_ENCODER_TMR6_7_CONFIG -#define PULSE_ENCODER_TMR6_7_CONFIG \ - { \ - .tmr_handler = CM_TMR6_7, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_7, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_67" \ +#define PULSE_ENCODER_TMR6_7_CONFIG \ + { \ + .tmr_handler = CM_TMR6_7, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_7, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_67" \ } #endif /* PULSE_ENCODER_TMR6_7_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_8 #ifndef PULSE_ENCODER_TMR6_8_CONFIG -#define PULSE_ENCODER_TMR6_8_CONFIG \ - { \ - .tmr_handler = CM_TMR6_8, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_8, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_68" \ +#define PULSE_ENCODER_TMR6_8_CONFIG \ + { \ + .tmr_handler = CM_TMR6_8, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_8, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_68" \ } #endif /* PULSE_ENCODER_TMR6_8_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pwm_tmr_config.h index da87f320f8b..93918cd0366 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pwm_tmr_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/pwm_tmr_config.h @@ -21,372 +21,324 @@ extern "C" { #ifdef BSP_USING_PWM_TMRA_1 #ifndef PWM_TMRA_1_CONFIG -#define PWM_TMRA_1_CONFIG \ - { \ - .name = "pwm_a1", \ - .instance = CM_TMRA_1, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_1_CONFIG */ #endif /* BSP_USING_PWM_TMRA_1 */ #ifdef BSP_USING_PWM_TMRA_2 #ifndef PWM_TMRA_2_CONFIG -#define PWM_TMRA_2_CONFIG \ - { \ - .name = "pwm_a2", \ - .instance = CM_TMRA_2, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_2_CONFIG */ #endif /* BSP_USING_PWM_TMRA_2 */ #ifdef BSP_USING_PWM_TMRA_3 #ifndef PWM_TMRA_3_CONFIG -#define PWM_TMRA_3_CONFIG \ - { \ - .name = "pwm_a3", \ - .instance = CM_TMRA_3, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_3_CONFIG */ #endif /* BSP_USING_PWM_TMRA_3 */ #ifdef BSP_USING_PWM_TMRA_4 #ifndef PWM_TMRA_4_CONFIG -#define PWM_TMRA_4_CONFIG \ - { \ - .name = "pwm_a4", \ - .instance = CM_TMRA_4, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_4_CONFIG */ #endif /* BSP_USING_PWM_TMRA_4 */ #ifdef BSP_USING_PWM_TMRA_5 #ifndef PWM_TMRA_5_CONFIG -#define PWM_TMRA_5_CONFIG \ - { \ - .name = "pwm_a5", \ - .instance = CM_TMRA_5, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_5_CONFIG */ #endif /* BSP_USING_PWM_TMRA_5 */ #ifdef BSP_USING_PWM_TMRA_6 #ifndef PWM_TMRA_6_CONFIG -#define PWM_TMRA_6_CONFIG \ - { \ - .name = "pwm_a6", \ - .instance = CM_TMRA_6, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_6_CONFIG */ #endif /* BSP_USING_PWM_TMRA_6 */ #ifdef BSP_USING_PWM_TMRA_7 #ifndef PWM_TMRA_7_CONFIG -#define PWM_TMRA_7_CONFIG \ - { \ - .name = "pwm_a7", \ - .instance = CM_TMRA_7, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_7_CONFIG \ + { \ + .name = "pwm_a7", \ + .instance = CM_TMRA_7, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_7_CONFIG */ #endif /* BSP_USING_PWM_TMRA_7 */ #ifdef BSP_USING_PWM_TMRA_8 #ifndef PWM_TMRA_8_CONFIG -#define PWM_TMRA_8_CONFIG \ - { \ - .name = "pwm_a8", \ - .instance = CM_TMRA_8, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_8_CONFIG \ + { \ + .name = "pwm_a8", \ + .instance = CM_TMRA_8, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_8_CONFIG */ #endif /* BSP_USING_PWM_TMRA_8 */ #ifdef BSP_USING_PWM_TMRA_9 #ifndef PWM_TMRA_9_CONFIG -#define PWM_TMRA_9_CONFIG \ - { \ - .name = "pwm_a9", \ - .instance = CM_TMRA_9, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_9_CONFIG \ + { \ + .name = "pwm_a9", \ + .instance = CM_TMRA_9, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_9_CONFIG */ #endif /* BSP_USING_PWM_TMRA_9 */ #ifdef BSP_USING_PWM_TMRA_10 #ifndef PWM_TMRA_10_CONFIG -#define PWM_TMRA_10_CONFIG \ - { \ - .name = "pwm_a10", \ - .instance = CM_TMRA_10, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_10_CONFIG \ + { \ + .name = "pwm_a10", \ + .instance = CM_TMRA_10, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_10_CONFIG */ #endif /* BSP_USING_PWM_TMRA_10 */ #ifdef BSP_USING_PWM_TMRA_11 #ifndef PWM_TMRA_11_CONFIG -#define PWM_TMRA_11_CONFIG \ - { \ - .name = "pwm_a11", \ - .instance = CM_TMRA_11, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_11_CONFIG \ + { \ + .name = "pwm_a11", \ + .instance = CM_TMRA_11, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_11_CONFIG */ #endif /* BSP_USING_PWM_TMRA_11 */ #ifdef BSP_USING_PWM_TMRA_12 #ifndef PWM_TMRA_12_CONFIG -#define PWM_TMRA_12_CONFIG \ - { \ - .name = "pwm_a12", \ - .instance = CM_TMRA_12, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_12_CONFIG \ + { \ + .name = "pwm_a12", \ + .instance = CM_TMRA_12, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_12_CONFIG */ #endif /* BSP_USING_PWM_TMRA_12 */ @@ -397,96 +349,87 @@ extern "C" { #ifdef BSP_USING_PWM_TMR4_1 #ifndef PWM_TMR4_1_CONFIG -#define PWM_TMR4_1_CONFIG \ - { \ - .name = "pwm_t41", \ - .instance = CM_TMR4_1, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_1_CONFIG */ #endif /* BSP_USING_PWM_TMR4_1 */ #ifdef BSP_USING_PWM_TMR4_2 #ifndef PWM_TMR4_2_CONFIG -#define PWM_TMR4_2_CONFIG \ - { \ - .name = "pwm_t42", \ - .instance = CM_TMR4_2, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_2_CONFIG */ #endif /* BSP_USING_PWM_TMR4_2 */ #ifdef BSP_USING_PWM_TMR4_3 #ifndef PWM_TMR4_3_CONFIG -#define PWM_TMR4_3_CONFIG \ - { \ - .name = "pwm_t43", \ - .instance = CM_TMR4_3, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_3_CONFIG */ #endif /* BSP_USING_PWM_TMR4_3 */ @@ -497,377 +440,337 @@ extern "C" { #ifdef BSP_USING_PWM_TMR6_1 #ifndef PWM_TMR6_1_CONFIG -#define PWM_TMR6_1_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_1, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_1_CONFIG */ #endif /* BSP_USING_PWM_TMR6_1 */ #ifdef BSP_USING_PWM_TMR6_2 #ifndef PWM_TMR6_2_CONFIG -#define PWM_TMR6_2_CONFIG \ - { \ - .name = "pwm_t62", \ - .instance = CM_TMR6_2, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t62", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_2_CONFIG */ #endif /* BSP_USING_PWM_TMR6_2 */ #ifdef BSP_USING_PWM_TMR6_3 #ifndef PWM_TMR6_3_CONFIG -#define PWM_TMR6_3_CONFIG \ - { \ - .name = "pwm_t63", \ - .instance = CM_TMR6_3, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t63", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_3_CONFIG */ #endif /* BSP_USING_PWM_TMR6_3 */ #ifdef BSP_USING_PWM_TMR6_4 #ifndef PWM_TMR6_4_CONFIG -#define PWM_TMR6_4_CONFIG \ - { \ - .name = "pwm_t64", \ - .instance = CM_TMR6_4, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t64", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_4_CONFIG */ #endif /* BSP_USING_PWM_TMR6_4 */ #ifdef BSP_USING_PWM_TMR6_5 #ifndef PWM_TMR6_5_CONFIG -#define PWM_TMR6_5_CONFIG \ - { \ - .name = "pwm_t65", \ - .instance = CM_TMR6_5, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_5_CONFIG \ + { \ + .name = "pwm_t65", \ + .instance = CM_TMR6_5, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_5_CONFIG */ #endif /* BSP_USING_PWM_TMR6_5 */ #ifdef BSP_USING_PWM_TMR6_6 #ifndef PWM_TMR6_6_CONFIG -#define PWM_TMR6_6_CONFIG \ - { \ - .name = "pwm_t66", \ - .instance = CM_TMR6_6, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_6_CONFIG \ + { \ + .name = "pwm_t66", \ + .instance = CM_TMR6_6, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_6_CONFIG */ #endif /* BSP_USING_PWM_TMR6_6 */ #ifdef BSP_USING_PWM_TMR6_7 #ifndef PWM_TMR6_7_CONFIG -#define PWM_TMR6_7_CONFIG \ - { \ - .name = "pwm_t67", \ - .instance = CM_TMR6_7, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_7_CONFIG \ + { \ + .name = "pwm_t67", \ + .instance = CM_TMR6_7, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_7_CONFIG */ #endif /* BSP_USING_PWM_TMR6_7 */ #ifdef BSP_USING_PWM_TMR6_8 #ifndef PWM_TMR6_8_CONFIG -#define PWM_TMR6_8_CONFIG \ - { \ - .name = "pwm_t68", \ - .instance = CM_TMR6_8, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_8_CONFIG \ + { \ + .name = "pwm_t68", \ + .instance = CM_TMR6_8, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_8_CONFIG */ #endif /* BSP_USING_PWM_TMR6_8 */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/qspi_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/qspi_config.h index b8e74bfae19..929bf0a5a91 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/qspi_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/qspi_config.h @@ -20,48 +20,46 @@ extern "C" { #ifdef BSP_USING_QSPI #ifndef QSPI_BUS_CONFIG -#define QSPI_BUS_CONFIG \ - { \ - .Instance = CM_QSPI, \ - .clock = FCG1_PERIPH_QSPI, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ - .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_QSPI_INTR, \ - }, \ +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ } #endif /* QSPI_BUS_CONFIG */ #ifndef QSPI_INIT_PARAMS -#define QSPI_INIT_PARAMS \ - { \ - .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ - .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ - .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ - .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ } #endif /* QSPI_INIT_PARAMS */ -#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH #ifdef BSP_QSPI_USING_DMA #ifndef QSPI_DMA_CONFIG -#define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .channel = QSPI_DMA_CHANNEL, \ - .clock = QSPI_DMA_CLOCK, \ - .trigger_select = QSPI_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_AOS_STRG, \ - .flag = QSPI_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = QSPI_DMA_IRQn, \ - .irq_prio = QSPI_DMA_INT_PRIO, \ - .int_src = QSPI_DMA_INT_SRC, \ - } \ +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ } #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/sdio_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/sdio_config.h index 8d1d1bf8977..d4219976138 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/sdio_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/sdio_config.h @@ -21,66 +21,60 @@ extern "C" { #if defined(BSP_USING_SDIO1) #ifndef SDIO1_BUS_CONFIG -#define SDIO1_BUS_CONFIG \ - { \ - .name = "sdio1", \ - .instance = CM_SDIOC1, \ - .clock = FCG1_PERIPH_SDIOC1, \ - .irq_config = \ - { \ - .irq_num = BSP_SDIO1_IRQ_NUM, \ - .irq_prio = BSP_SDIO1_IRQ_PRIO, \ - .int_src = INT_SRC_SDIOC1_SD, \ - }, \ - .dma_rx = \ - { \ - .Instance = SDIO1_RX_DMA_INSTANCE, \ - .channel = SDIO1_RX_DMA_CHANNEL, \ - .clock = SDIO1_RX_DMA_CLOCK, \ - .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC1_DMAR, \ - }, \ - .dma_tx = \ - { \ - .Instance = SDIO1_TX_DMA_INSTANCE, \ - .channel = SDIO1_TX_DMA_CHANNEL, \ - .clock = SDIO1_TX_DMA_CLOCK, \ - .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC1_DMAW, \ - }, \ +#define SDIO1_BUS_CONFIG \ + { \ + .name = "sdio1", \ + .instance = CM_SDIOC1, \ + .clock = FCG1_PERIPH_SDIOC1, \ + .irq_config = { \ + .irq_num = BSP_SDIO1_IRQ_NUM, \ + .irq_prio = BSP_SDIO1_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC1_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO1_RX_DMA_INSTANCE, \ + .channel = SDIO1_RX_DMA_CHANNEL, \ + .clock = SDIO1_RX_DMA_CLOCK, \ + .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO1_TX_DMA_INSTANCE, \ + .channel = SDIO1_TX_DMA_CHANNEL, \ + .clock = SDIO1_TX_DMA_CLOCK, \ + .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAW, \ + }, \ } #endif /* SDIO1_BUS_CONFIG */ #endif /* BSP_USING_SDIO1 */ #if defined(BSP_USING_SDIO2) #ifndef SDIO2_BUS_CONFIG -#define SDIO2_BUS_CONFIG \ - { \ - .name = "sdio2", \ - .instance = CM_SDIOC2, \ - .clock = FCG1_PERIPH_SDIOC2, \ - .irq_config = \ - { \ - .irq_num = BSP_SDIO2_IRQ_NUM, \ - .irq_prio = BSP_SDIO2_IRQ_PRIO, \ - .int_src = INT_SRC_SDIOC2_SD, \ - }, \ - .dma_rx = \ - { \ - .Instance = SDIO2_RX_DMA_INSTANCE, \ - .channel = SDIO2_RX_DMA_CHANNEL, \ - .clock = SDIO2_RX_DMA_CLOCK, \ - .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC2_DMAR, \ - }, \ - .dma_tx = \ - { \ - .Instance = SDIO2_TX_DMA_INSTANCE, \ - .channel = SDIO2_TX_DMA_CHANNEL, \ - .clock = SDIO2_TX_DMA_CLOCK, \ - .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC2_DMAW, \ - }, \ +#define SDIO2_BUS_CONFIG \ + { \ + .name = "sdio2", \ + .instance = CM_SDIOC2, \ + .clock = FCG1_PERIPH_SDIOC2, \ + .irq_config = { \ + .irq_num = BSP_SDIO2_IRQ_NUM, \ + .irq_prio = BSP_SDIO2_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC2_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO2_RX_DMA_INSTANCE, \ + .channel = SDIO2_RX_DMA_CHANNEL, \ + .clock = SDIO2_RX_DMA_CLOCK, \ + .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO2_TX_DMA_INSTANCE, \ + .channel = SDIO2_TX_DMA_CHANNEL, \ + .clock = SDIO2_TX_DMA_CLOCK, \ + .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAW, \ + }, \ } #endif /* SDIO2_BUS_CONFIG */ #endif /* BSP_USING_SDIO2 */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h index a839686bd3c..13e6acc6905 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/spi_config.h @@ -21,134 +21,127 @@ extern "C" { #ifdef BSP_USING_SPI1 #ifndef SPI1_BUS_CONFIG -#define SPI1_BUS_CONFIG \ - { \ - .Instance = CM_SPI1, \ - .bus_name = "spi1", \ - .clock = FCG1_PERIPH_SPI1, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI1_SPEI, \ - }, \ +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .clock = SPI1_TX_DMA_CLOCK, \ - .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPTI, \ - .flag = SPI1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_TX_DMA_IRQn, \ - .irq_prio = SPI1_TX_DMA_INT_PRIO, \ - .int_src = SPI1_TX_DMA_INT_SRC, \ - } \ +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .clock = SPI1_RX_DMA_CLOCK, \ - .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPRI, \ - .flag = SPI1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_RX_DMA_IRQn, \ - .irq_prio = SPI1_RX_DMA_INT_PRIO, \ - .int_src = SPI1_RX_DMA_INT_SRC, \ - } \ +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 #ifndef SPI2_BUS_CONFIG -#define SPI2_BUS_CONFIG \ - { \ - .Instance = CM_SPI2, \ - .bus_name = "spi2", \ - .clock = FCG1_PERIPH_SPI2, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI2_SPEI, \ - }, \ +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .channel = SPI2_TX_DMA_CHANNEL, \ - .clock = SPI2_TX_DMA_CLOCK, \ - .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPTI, \ - .flag = SPI2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_TX_DMA_IRQn, \ - .irq_prio = SPI2_TX_DMA_INT_PRIO, \ - .int_src = SPI2_TX_DMA_INT_SRC, \ - } \ +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .channel = SPI2_RX_DMA_CHANNEL, \ - .clock = SPI2_RX_DMA_CLOCK, \ - .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPRI, \ - .flag = SPI2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_RX_DMA_IRQn, \ - .irq_prio = SPI2_RX_DMA_INT_PRIO, \ - .int_src = SPI2_RX_DMA_INT_SRC, \ - } \ +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 #ifndef SPI3_BUS_CONFIG -#define SPI3_BUS_CONFIG \ - { \ - .Instance = CM_SPI3, \ - .bus_name = "spi3", \ - .clock = FCG1_PERIPH_SPI3, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI3_SPEI, \ - }, \ +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ @@ -156,214 +149,203 @@ extern "C" { #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .channel = SPI3_TX_DMA_CHANNEL, \ - .clock = SPI3_TX_DMA_CLOCK, \ - .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPTI, \ - .flag = SPI3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_TX_DMA_IRQn, \ - .irq_prio = SPI3_TX_DMA_INT_PRIO, \ - .int_src = SPI3_TX_DMA_INT_SRC, \ - } \ +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .channel = SPI3_RX_DMA_CHANNEL, \ - .clock = SPI3_RX_DMA_CLOCK, \ - .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPRI, \ - .flag = SPI3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_RX_DMA_IRQn, \ - .irq_prio = SPI3_RX_DMA_INT_PRIO, \ - .int_src = SPI3_RX_DMA_INT_SRC, \ - } \ +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ #ifdef BSP_USING_SPI4 #ifndef SPI4_BUS_CONFIG -#define SPI4_BUS_CONFIG \ - { \ - .Instance = CM_SPI4, \ - .bus_name = "spi4", \ - .clock = FCG1_PERIPH_SPI4, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI4_SPEI, \ - }, \ +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ } #endif /* SPI4_BUS_CONFIG */ #endif /* BSP_USING_SPI4 */ #ifdef BSP_SPI4_TX_USING_DMA #ifndef SPI4_TX_DMA_CONFIG -#define SPI4_TX_DMA_CONFIG \ - { \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .channel = SPI4_TX_DMA_CHANNEL, \ - .clock = SPI4_TX_DMA_CLOCK, \ - .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI4_SPTI, \ - .flag = SPI4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI4_TX_DMA_IRQn, \ - .irq_prio = SPI4_TX_DMA_INT_PRIO, \ - .int_src = SPI4_TX_DMA_INT_SRC, \ - } \ +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ #ifdef BSP_SPI4_RX_USING_DMA #ifndef SPI4_RX_DMA_CONFIG -#define SPI4_RX_DMA_CONFIG \ - { \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .channel = SPI4_RX_DMA_CHANNEL, \ - .clock = SPI4_RX_DMA_CLOCK, \ - .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI4_SPRI, \ - .flag = SPI4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI4_RX_DMA_IRQn, \ - .irq_prio = SPI4_RX_DMA_INT_PRIO, \ - .int_src = SPI4_RX_DMA_INT_SRC, \ - } \ +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ #ifdef BSP_USING_SPI5 #ifndef SPI5_BUS_CONFIG -#define SPI5_BUS_CONFIG \ - { \ - .Instance = CM_SPI5, \ - .bus_name = "spi5", \ - .clock = FCG1_PERIPH_SPI5, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI5_SPEI, \ - }, \ +#define SPI5_BUS_CONFIG \ + { \ + .Instance = CM_SPI5, \ + .bus_name = "spi5", \ + .clock = FCG1_PERIPH_SPI5, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI5_SPEI, \ + }, \ } #endif /* SPI5_BUS_CONFIG */ #endif /* BSP_USING_SPI5 */ #ifdef BSP_SPI5_TX_USING_DMA #ifndef SPI5_TX_DMA_CONFIG -#define SPI5_TX_DMA_CONFIG \ - { \ - .Instance = SPI5_TX_DMA_INSTANCE, \ - .channel = SPI5_TX_DMA_CHANNEL, \ - .clock = SPI5_TX_DMA_CLOCK, \ - .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI5_SPTI, \ - .flag = SPI5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI5_TX_DMA_IRQn, \ - .irq_prio = SPI5_TX_DMA_INT_PRIO, \ - .int_src = SPI5_TX_DMA_INT_SRC, \ - } \ +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .clock = SPI5_TX_DMA_CLOCK, \ + .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPTI, \ + .flag = SPI5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI5_TX_DMA_CONFIG */ #endif /* BSP_SPI5_TX_USING_DMA */ #ifdef BSP_SPI5_RX_USING_DMA #ifndef SPI5_RX_DMA_CONFIG -#define SPI5_RX_DMA_CONFIG \ - { \ - .Instance = SPI5_RX_DMA_INSTANCE, \ - .channel = SPI5_RX_DMA_CHANNEL, \ - .clock = SPI5_RX_DMA_CLOCK, \ - .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI5_SPRI, \ - .flag = SPI5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI5_RX_DMA_IRQn, \ - .irq_prio = SPI5_RX_DMA_INT_PRIO, \ - .int_src = SPI5_RX_DMA_INT_SRC, \ - } \ +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .clock = SPI5_RX_DMA_CLOCK, \ + .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPRI, \ + .flag = SPI5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI5_RX_DMA_CONFIG */ #endif /* BSP_SPI5_RX_USING_DMA */ #ifdef BSP_USING_SPI6 #ifndef SPI6_BUS_CONFIG -#define SPI6_BUS_CONFIG \ - { \ - .Instance = CM_SPI6, \ - .bus_name = "spi6", \ - .clock = FCG1_PERIPH_SPI6, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI6_SPEI, \ - }, \ +#define SPI6_BUS_CONFIG \ + { \ + .Instance = CM_SPI6, \ + .bus_name = "spi6", \ + .clock = FCG1_PERIPH_SPI6, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI6_SPEI, \ + }, \ } #endif /* SPI6_BUS_CONFIG */ #endif /* BSP_USING_SPI6 */ #ifdef BSP_SPI6_TX_USING_DMA #ifndef SPI6_TX_DMA_CONFIG -#define SPI6_TX_DMA_CONFIG \ - { \ - .Instance = SPI6_TX_DMA_INSTANCE, \ - .channel = SPI6_TX_DMA_CHANNEL, \ - .clock = SPI6_TX_DMA_CLOCK, \ - .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI6_SPTI, \ - .flag = SPI6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI6_TX_DMA_IRQn, \ - .irq_prio = SPI6_TX_DMA_INT_PRIO, \ - .int_src = SPI6_TX_DMA_INT_SRC, \ - } \ +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .clock = SPI6_TX_DMA_CLOCK, \ + .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPTI, \ + .flag = SPI6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI6_TX_DMA_CONFIG */ #endif /* BSP_SPI6_TX_USING_DMA */ #ifdef BSP_SPI6_RX_USING_DMA #ifndef SPI6_RX_DMA_CONFIG -#define SPI6_RX_DMA_CONFIG \ - { \ - .Instance = SPI6_RX_DMA_INSTANCE, \ - .channel = SPI6_RX_DMA_CHANNEL, \ - .clock = SPI6_RX_DMA_CLOCK, \ - .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI6_SPRI, \ - .flag = SPI6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI6_RX_DMA_IRQn, \ - .irq_prio = SPI6_RX_DMA_INT_PRIO, \ - .int_src = SPI6_RX_DMA_INT_SRC, \ - } \ +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .clock = SPI6_RX_DMA_CLOCK, \ + .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPRI, \ + .flag = SPI6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI6_RX_DMA_CONFIG */ #endif /* BSP_SPI6_RX_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/timer_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/timer_config.h index 553ffc86293..414a64a3652 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/timer_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/timer_config.h @@ -19,228 +19,216 @@ extern "C" { #ifdef BSP_USING_TMRA_1 #ifndef TMRA_1_CONFIG -#define TMRA_1_CONFIG \ - { \ - .tmr_handle = CM_TMRA_1, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_1, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_1_OVF, \ - .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ - }, \ - .name = "tmra_1" \ +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ } #endif /* TMRA_1_CONFIG */ #endif /* BSP_USING_TMRA_1 */ #ifdef BSP_USING_TMRA_2 #ifndef TMRA_2_CONFIG -#define TMRA_2_CONFIG \ - { \ - .tmr_handle = CM_TMRA_2, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_2, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_2_OVF, \ - .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ - }, \ - .name = "tmra_2" \ +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ } #endif /* TMRA_2_CONFIG */ #endif /* BSP_USING_TMRA_2 */ #ifdef BSP_USING_TMRA_3 #ifndef TMRA_3_CONFIG -#define TMRA_3_CONFIG \ - { \ - .tmr_handle = CM_TMRA_3, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_3, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_3_OVF, \ - .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ - }, \ - .name = "tmra_3" \ +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ } #endif /* TMRA_3_CONFIG */ #endif /* BSP_USING_TMRA_3 */ #ifdef BSP_USING_TMRA_4 #ifndef TMRA_4_CONFIG -#define TMRA_4_CONFIG \ - { \ - .tmr_handle = CM_TMRA_4, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_4, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_4_OVF, \ - .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ - }, \ - .name = "tmra_4" \ +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ } #endif /* TMRA_4_CONFIG */ #endif /* BSP_USING_TMRA_4 */ #ifdef BSP_USING_TMRA_5 #ifndef TMRA_5_CONFIG -#define TMRA_5_CONFIG \ - { \ - .tmr_handle = CM_TMRA_5, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_5, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_5_OVF, \ - .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ - }, \ - .name = "tmra_5" \ +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ } #endif /* TMRA_5_CONFIG */ #endif /* BSP_USING_TMRA_5 */ #ifdef BSP_USING_TMRA_6 #ifndef TMRA_6_CONFIG -#define TMRA_6_CONFIG \ - { \ - .tmr_handle = CM_TMRA_6, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_6, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_6_OVF, \ - .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ - }, \ - .name = "tmra_6" \ +#define TMRA_6_CONFIG \ + { \ + .tmr_handle = CM_TMRA_6, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_6, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_6_OVF, \ + .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ + }, \ + .name = "tmra_6" \ } #endif /* TMRA_6_CONFIG */ #endif /* BSP_USING_TMRA_6 */ #ifdef BSP_USING_TMRA_7 #ifndef TMRA_7_CONFIG -#define TMRA_7_CONFIG \ - { \ - .tmr_handle = CM_TMRA_7, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_7, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_7_OVF, \ - .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ - }, \ - .name = "tmra_7" \ +#define TMRA_7_CONFIG \ + { \ + .tmr_handle = CM_TMRA_7, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_7, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_7_OVF, \ + .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ + }, \ + .name = "tmra_7" \ } #endif /* TMRA_7_CONFIG */ #endif /* BSP_USING_TMRA_7 */ #ifdef BSP_USING_TMRA_8 #ifndef TMRA_8_CONFIG -#define TMRA_8_CONFIG \ - { \ - .tmr_handle = CM_TMRA_8, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_8, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_8_OVF, \ - .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ - }, \ - .name = "tmra_8" \ +#define TMRA_8_CONFIG \ + { \ + .tmr_handle = CM_TMRA_8, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_8, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_8_OVF, \ + .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ + }, \ + .name = "tmra_8" \ } #endif /* TMRA_8_CONFIG */ #endif /* BSP_USING_TMRA_8 */ #ifdef BSP_USING_TMRA_9 #ifndef TMRA_9_CONFIG -#define TMRA_9_CONFIG \ - { \ - .tmr_handle = CM_TMRA_9, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_9, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_9_OVF, \ - .enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \ - }, \ - .name = "tmra_9" \ +#define TMRA_9_CONFIG \ + { \ + .tmr_handle = CM_TMRA_9, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_9, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_9_OVF, \ + .enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \ + }, \ + .name = "tmra_9" \ } #endif /* TMRA_9_CONFIG */ #endif /* BSP_USING_TMRA_9 */ #ifdef BSP_USING_TMRA_10 #ifndef TMRA_10_CONFIG -#define TMRA_10_CONFIG \ - { \ - .tmr_handle = CM_TMRA_10, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_10, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_10_OVF, \ - .enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \ - }, \ - .name = "tmra_10" \ +#define TMRA_10_CONFIG \ + { \ + .tmr_handle = CM_TMRA_10, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_10, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_10_OVF, \ + .enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \ + }, \ + .name = "tmra_10" \ } #endif /* TMRA_10_CONFIG */ #endif /* BSP_USING_TMRA_10 */ #ifdef BSP_USING_TMRA_11 #ifndef TMRA_11_CONFIG -#define TMRA_11_CONFIG \ - { \ - .tmr_handle = CM_TMRA_11, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_11, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_11_OVF, \ - .enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \ - }, \ - .name = "tmra_11" \ +#define TMRA_11_CONFIG \ + { \ + .tmr_handle = CM_TMRA_11, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_11, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_11_OVF, \ + .enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \ + }, \ + .name = "tmra_11" \ } #endif /* TMRA_11_CONFIG */ #endif /* BSP_USING_TMRA_11 */ #ifdef BSP_USING_TMRA_12 #ifndef TMRA_12_CONFIG -#define TMRA_12_CONFIG \ - { \ - .tmr_handle = CM_TMRA_12, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_12, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_12_OVF, \ - .enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \ - }, \ - .name = "tmra_12" \ +#define TMRA_12_CONFIG \ + { \ + .tmr_handle = CM_TMRA_12, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_12, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_12_OVF, \ + .enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \ + }, \ + .name = "tmra_12" \ } #endif /* TMRA_12_CONFIG */ #endif /* BSP_USING_TMRA_12 */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tmr_capture_config.h index 65d4d8eed54..ba231bec707 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tmr_capture_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/tmr_capture_config.h @@ -17,49 +17,49 @@ extern "C" { #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) #define IC1_NAME "ic1" -#define INPUT_CAPTURE_CFG_TMR6_1 \ -{ \ - .name = IC1_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_1 \ + { \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) #define IC2_NAME "ic2" -#define INPUT_CAPTURE_CFG_TMR6_2 \ -{ \ - .name = IC2_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_2 \ + { \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) #define IC3_NAME "ic3" -#define INPUT_CAPTURE_CFG_TMR6_3 \ -{ \ - .name = IC3_NAME, \ - .ch = TMR6_CH_B, \ - .clk_div = TMR6_CLK_DIV16, \ - .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_3 \ + { \ + .name = IC3_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ + } #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h index e69b988d002..41ce84ae289 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/uart_config.h @@ -21,110 +21,102 @@ extern "C" { #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = CM_USART1, \ - .clock = FCG3_PERIPH_USART1, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_RX_IRQ_NUM, \ - .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_TX_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TI, \ - }, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ } #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .clock = UART1_RX_DMA_CLOCK, \ - .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_RI, \ - .flag = UART1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_RX_DMA_IRQn, \ - .irq_prio = UART1_RX_DMA_INT_PRIO, \ - .int_src = UART1_RX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_RX_CONFIG */ #ifndef UART1_RXTO_CONFIG -#define UART1_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_RTO, \ - }, \ +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ } #endif /* UART1_RXTO_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #endif /* UART1_TX_CPLT_CONFIG */ #if defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .clock = UART1_TX_DMA_CLOCK, \ - .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_TI, \ - .flag = UART1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_TX_DMA_IRQn, \ - .irq_prio = UART1_TX_DMA_INT_PRIO, \ - .int_src = UART1_TX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -132,110 +124,102 @@ extern "C" { #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = CM_USART2, \ - .clock = FCG3_PERIPH_USART2, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_RX_IRQ_NUM, \ - .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_TX_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TI, \ - }, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ } #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .clock = UART2_RX_DMA_CLOCK, \ - .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_RI, \ - .flag = UART2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_RX_DMA_IRQn, \ - .irq_prio = UART2_RX_DMA_INT_PRIO, \ - .int_src = UART2_RX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_RX_CONFIG */ #ifndef UART2_RXTO_CONFIG -#define UART2_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_RTO, \ - }, \ +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ } #endif /* UART2_RXTO_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #endif /* UART2_TX_CPLT_CONFIG */ #if defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .clock = UART2_TX_DMA_CLOCK, \ - .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_TI, \ - .flag = UART2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_TX_DMA_IRQn, \ - .irq_prio = UART2_TX_DMA_INT_PRIO, \ - .int_src = UART2_TX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -243,42 +227,38 @@ extern "C" { #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = CM_USART3, \ - .clock = FCG3_PERIPH_USART3, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_RX_IRQ_NUM, \ - .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_TX_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TI, \ - }, \ +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ } #endif /* UART3_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART3_TX_CPLT_CONFIG -#define UART3_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TCI, \ - }, \ +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ } #endif #endif /* UART3_TX_CPLT_CONFIG */ @@ -286,42 +266,38 @@ extern "C" { #if defined(BSP_USING_UART4) #ifndef UART4_CONFIG -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = CM_USART4, \ - .clock = FCG3_PERIPH_USART4, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_RX_IRQ_NUM, \ - .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_TX_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TI, \ - }, \ +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ } #endif /* UART4_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #endif /* UART4_TX_CPLT_CONFIG */ @@ -329,42 +305,38 @@ extern "C" { #if defined(BSP_USING_UART5) #ifndef UART5_CONFIG -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = CM_USART5, \ - .clock = FCG3_PERIPH_USART5, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART5_RX_IRQ_NUM, \ - .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART5_TX_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TI, \ - }, \ +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART5_RX_IRQ_NUM, \ + .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART5_TX_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TI, \ + }, \ } #endif /* UART5_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART5_TX_CPLT_CONFIG -#define UART5_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TCI, \ - }, \ +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ } #endif #endif /* UART5_TX_CPLT_CONFIG */ @@ -372,110 +344,102 @@ extern "C" { #if defined(BSP_USING_UART6) #ifndef UART6_CONFIG -#define UART6_CONFIG \ - { \ - .name = "uart6", \ - .Instance = CM_USART6, \ - .clock = FCG3_PERIPH_USART6, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART6_RX_IRQ_NUM, \ - .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART6_TX_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TI, \ - }, \ +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART6_RX_IRQ_NUM, \ + .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART6_TX_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TI, \ + }, \ } #endif /* UART6_CONFIG */ #if defined(BSP_UART6_RX_USING_DMA) #ifndef UART6_DMA_RX_CONFIG -#define UART6_DMA_RX_CONFIG \ - { \ - .Instance = UART6_RX_DMA_INSTANCE, \ - .channel = UART6_RX_DMA_CHANNEL, \ - .clock = UART6_RX_DMA_CLOCK, \ - .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART6_RI, \ - .flag = UART6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART6_RX_DMA_IRQn, \ - .irq_prio = UART6_RX_DMA_INT_PRIO, \ - .int_src = UART6_RX_DMA_INT_SRC, \ - }, \ +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .channel = UART6_RX_DMA_CHANNEL, \ + .clock = UART6_RX_DMA_CLOCK, \ + .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_RI, \ + .flag = UART6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART6_RX_DMA_IRQn, \ + .irq_prio = UART6_RX_DMA_INT_PRIO, \ + .int_src = UART6_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART6_DMA_RX_CONFIG */ #ifndef UART6_RXTO_CONFIG -#define UART6_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_RTO, \ - }, \ +#define UART6_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RTO, \ + }, \ } #endif /* UART6_RXTO_CONFIG */ #endif /* BSP_UART6_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) #ifndef UART6_TX_CPLT_CONFIG -#define UART6_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TCI, \ - }, \ +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART6_TX_CPLT_CONFIG -#define UART6_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TCI, \ - }, \ +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ } #endif #endif /* UART6_TX_CPLT_CONFIG */ #if defined(BSP_UART6_TX_USING_DMA) #ifndef UART6_DMA_TX_CONFIG -#define UART6_DMA_TX_CONFIG \ - { \ - .Instance = UART6_TX_DMA_INSTANCE, \ - .channel = UART6_TX_DMA_CHANNEL, \ - .clock = UART6_TX_DMA_CLOCK, \ - .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART6_TI, \ - .flag = UART6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART6_TX_DMA_IRQn, \ - .irq_prio = UART6_TX_DMA_INT_PRIO, \ - .int_src = UART6_TX_DMA_INT_SRC, \ - }, \ +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .channel = UART6_TX_DMA_CHANNEL, \ + .clock = UART6_TX_DMA_CLOCK, \ + .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_TI, \ + .flag = UART6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART6_TX_DMA_IRQn, \ + .irq_prio = UART6_TX_DMA_INT_PRIO, \ + .int_src = UART6_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART6_DMA_TX_CONFIG */ #endif /* BSP_UART6_TX_USING_DMA */ @@ -483,110 +447,102 @@ extern "C" { #if defined(BSP_USING_UART7) #ifndef UART7_CONFIG -#define UART7_CONFIG \ - { \ - .name = "uart7", \ - .Instance = CM_USART7, \ - .clock = FCG3_PERIPH_USART7, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART7_RX_IRQ_NUM, \ - .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART7_TX_IRQ_NUM, \ - .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_TI, \ - }, \ +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = CM_USART7, \ + .clock = FCG3_PERIPH_USART7, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART7_RX_IRQ_NUM, \ + .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART7_TX_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TI, \ + }, \ } #endif /* UART7_CONFIG */ #if defined(BSP_UART7_RX_USING_DMA) #ifndef UART7_DMA_RX_CONFIG -#define UART7_DMA_RX_CONFIG \ - { \ - .Instance = UART7_RX_DMA_INSTANCE, \ - .channel = UART7_RX_DMA_CHANNEL, \ - .clock = UART7_RX_DMA_CLOCK, \ - .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART7_RI, \ - .flag = UART7_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART7_RX_DMA_IRQn, \ - .irq_prio = UART7_RX_DMA_INT_PRIO, \ - .int_src = UART7_RX_DMA_INT_SRC, \ - }, \ +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .channel = UART7_RX_DMA_CHANNEL, \ + .clock = UART7_RX_DMA_CLOCK, \ + .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_RI, \ + .flag = UART7_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART7_RX_DMA_IRQn, \ + .irq_prio = UART7_RX_DMA_INT_PRIO, \ + .int_src = UART7_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART7_DMA_RX_CONFIG */ #ifndef UART7_RXTO_CONFIG -#define UART7_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_RTO, \ - }, \ +#define UART7_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RTO, \ + }, \ } #endif /* UART7_RXTO_CONFIG */ #endif /* BSP_UART7_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) #ifndef UART7_TX_CPLT_CONFIG -#define UART7_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_TCI, \ - }, \ +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART7_TX_CPLT_CONFIG -#define UART7_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_TCI, \ - }, \ +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ } #endif #endif /* UART7_TX_CPLT_CONFIG */ #if defined(BSP_UART7_TX_USING_DMA) #ifndef UART7_DMA_TX_CONFIG -#define UART7_DMA_TX_CONFIG \ - { \ - .Instance = UART7_TX_DMA_INSTANCE, \ - .channel = UART7_TX_DMA_CHANNEL, \ - .clock = UART7_TX_DMA_CLOCK, \ - .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART7_TI, \ - .flag = UART1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART7_TX_DMA_IRQn, \ - .irq_prio = UART7_TX_DMA_INT_PRIO, \ - .int_src = UART7_TX_DMA_INT_SRC, \ - }, \ +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .channel = UART7_TX_DMA_CHANNEL, \ + .clock = UART7_TX_DMA_CLOCK, \ + .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART7_TX_DMA_IRQn, \ + .irq_prio = UART7_TX_DMA_INT_PRIO, \ + .int_src = UART7_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART7_DMA_TX_CONFIG */ #endif /* BSP_UART7_TX_USING_DMA */ @@ -594,42 +550,38 @@ extern "C" { #if defined(BSP_USING_UART8) #ifndef UART8_CONFIG -#define UART8_CONFIG \ - { \ - .name = "uart8", \ - .Instance = CM_USART8, \ - .clock = FCG3_PERIPH_USART8, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART8_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART8_RX_IRQ_NUM, \ - .irq_prio = BSP_UART8_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART8_TX_IRQ_NUM, \ - .irq_prio = BSP_UART8_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_TI, \ - }, \ +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .Instance = CM_USART8, \ + .clock = FCG3_PERIPH_USART8, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART8_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART8_RX_IRQ_NUM, \ + .irq_prio = BSP_UART8_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART8_TX_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TI, \ + }, \ } #endif /* UART8_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART8_TX_CPLT_CONFIG -#define UART8_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_TCI, \ - }, \ +#define UART8_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TCI, \ + }, \ } #endif #endif /* UART8_TX_CPLT_CONFIG */ @@ -637,42 +589,38 @@ extern "C" { #if defined(BSP_USING_UART9) #ifndef UART9_CONFIG -#define UART9_CONFIG \ - { \ - .name = "uart9", \ - .Instance = CM_USART9, \ - .clock = FCG3_PERIPH_USART9, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART9_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART9_RX_IRQ_NUM, \ - .irq_prio = BSP_UART9_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART9_TX_IRQ_NUM, \ - .irq_prio = BSP_UART9_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_TI, \ - }, \ +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .Instance = CM_USART9, \ + .clock = FCG3_PERIPH_USART9, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART9_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART9_RX_IRQ_NUM, \ + .irq_prio = BSP_UART9_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART9_TX_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TI, \ + }, \ } #endif /* UART9_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART9_TX_CPLT_CONFIG -#define UART9_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_TCI, \ - }, \ +#define UART9_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TCI, \ + }, \ } #endif #endif /* UART9_TX_CPLT_CONFIG */ @@ -680,42 +628,38 @@ extern "C" { #if defined(BSP_USING_UART10) #ifndef UART10_CONFIG -#define UART10_CONFIG \ - { \ - .name = "uart10", \ - .Instance = CM_USART10, \ - .clock = FCG3_PERIPH_USART10, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART10_RX_IRQ_NUM, \ - .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART10_TX_IRQ_NUM, \ - .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_TI, \ - }, \ +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = CM_USART10, \ + .clock = FCG3_PERIPH_USART10, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART10_RX_IRQ_NUM, \ + .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART10_TX_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TI, \ + }, \ } #endif /* UART10_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART10_TX_CPLT_CONFIG -#define UART10_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_TCI, \ - }, \ +#define UART10_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TCI, \ + }, \ } #endif #endif /* UART10_TX_CPLT_CONFIG */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/usb_config/usb_app_conf.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/usb_config/usb_app_conf.h index 2781afa72f4..53c20e1b517 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/usb_config/usb_app_conf.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/usb_config/usb_app_conf.h @@ -13,8 +13,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -61,71 +60,71 @@ USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment #ifndef USB_HS_MODE #ifndef USB_FS_MODE -#error "USB_HS_MODE or USB_FS_MODE should be defined" +#error "USB_HS_MODE or USB_FS_MODE should be defined" #endif #endif #ifndef USE_DEVICE_MODE #ifndef USE_HOST_MODE -#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" +#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" #endif #endif #if defined(BSP_USING_USBD) /* USB DEVICE FIFO CONFIGURATION */ #ifdef USB_FS_MODE -#define RX_FIFO_FS_SIZE (128U) -#define TX0_FIFO_FS_SIZE (32U) -#define TX1_FIFO_FS_SIZE (32U) -#define TX2_FIFO_FS_SIZE (32U) -#define TX3_FIFO_FS_SIZE (32U) -#define TX4_FIFO_FS_SIZE (32U) -#define TX5_FIFO_FS_SIZE (32U) -#define TX6_FIFO_FS_SIZE (32U) -#define TX7_FIFO_FS_SIZE (32U) -#define TX8_FIFO_FS_SIZE (32U) -#define TX9_FIFO_FS_SIZE (32U) -#define TX10_FIFO_FS_SIZE (32U) -#define TX11_FIFO_FS_SIZE (32U) -#define TX12_FIFO_FS_SIZE (32U) -#define TX13_FIFO_FS_SIZE (32U) -#define TX14_FIFO_FS_SIZE (32U) -#define TX15_FIFO_FS_SIZE (32U) - -#if ((RX_FIFO_FS_SIZE + \ - TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ - TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ +#define RX_FIFO_FS_SIZE (128U) +#define TX0_FIFO_FS_SIZE (32U) +#define TX1_FIFO_FS_SIZE (32U) +#define TX2_FIFO_FS_SIZE (32U) +#define TX3_FIFO_FS_SIZE (32U) +#define TX4_FIFO_FS_SIZE (32U) +#define TX5_FIFO_FS_SIZE (32U) +#define TX6_FIFO_FS_SIZE (32U) +#define TX7_FIFO_FS_SIZE (32U) +#define TX8_FIFO_FS_SIZE (32U) +#define TX9_FIFO_FS_SIZE (32U) +#define TX10_FIFO_FS_SIZE (32U) +#define TX11_FIFO_FS_SIZE (32U) +#define TX12_FIFO_FS_SIZE (32U) +#define TX13_FIFO_FS_SIZE (32U) +#define TX14_FIFO_FS_SIZE (32U) +#define TX15_FIFO_FS_SIZE (32U) + +#if ((RX_FIFO_FS_SIZE + \ + TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ + TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \ TX15_FIFO_FS_SIZE) > 640U) -#error "The USB max FIFO size is 640 x 4 Bytes!" +#error "The USB max FIFO size is 640 x 4 Bytes!" #endif #endif #ifdef USB_HS_MODE -#define RX_FIFO_HS_SIZE (512U) -#define TX0_FIFO_HS_SIZE (64U) -#define TX1_FIFO_HS_SIZE (64U) -#define TX2_FIFO_HS_SIZE (64U) -#define TX3_FIFO_HS_SIZE (64U) -#define TX4_FIFO_HS_SIZE (64U) -#define TX5_FIFO_HS_SIZE (64U) -#define TX6_FIFO_HS_SIZE (64U) -#define TX7_FIFO_HS_SIZE (64U) -#define TX8_FIFO_HS_SIZE (64U) -#define TX9_FIFO_HS_SIZE (64U) -#define TX10_FIFO_HS_SIZE (64U) -#define TX11_FIFO_HS_SIZE (64U) -#define TX12_FIFO_HS_SIZE (64U) -#define TX13_FIFO_HS_SIZE (64U) -#define TX14_FIFO_HS_SIZE (64U) -#define TX15_FIFO_HS_SIZE (64U) - -#if ((RX_FIFO_HS_SIZE + \ - TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ - TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ +#define RX_FIFO_HS_SIZE (512U) +#define TX0_FIFO_HS_SIZE (64U) +#define TX1_FIFO_HS_SIZE (64U) +#define TX2_FIFO_HS_SIZE (64U) +#define TX3_FIFO_HS_SIZE (64U) +#define TX4_FIFO_HS_SIZE (64U) +#define TX5_FIFO_HS_SIZE (64U) +#define TX6_FIFO_HS_SIZE (64U) +#define TX7_FIFO_HS_SIZE (64U) +#define TX8_FIFO_HS_SIZE (64U) +#define TX9_FIFO_HS_SIZE (64U) +#define TX10_FIFO_HS_SIZE (64U) +#define TX11_FIFO_HS_SIZE (64U) +#define TX12_FIFO_HS_SIZE (64U) +#define TX13_FIFO_HS_SIZE (64U) +#define TX14_FIFO_HS_SIZE (64U) +#define TX15_FIFO_HS_SIZE (64U) + +#if ((RX_FIFO_HS_SIZE + \ + TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ + TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \ TX15_FIFO_HS_SIZE) > 2048U) -#error "The USB max FIFO size is 2048 x 4 Bytes!" +#error "The USB max FIFO size is 2048 x 4 Bytes!" #endif #endif @@ -137,22 +136,22 @@ USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment #if defined(BSP_USING_USBH) /* USB HOST FIFO CONFIGURATION */ #ifdef USB_FS_MODE -#define RX_FIFO_FS_SIZE (128U) -#define TXH_NP_FS_FIFOSIZ (32U) -#define TXH_P_FS_FIFOSIZ (64U) +#define RX_FIFO_FS_SIZE (128U) +#define TXH_NP_FS_FIFOSIZ (32U) +#define TXH_P_FS_FIFOSIZ (64U) #if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U) -#error "The USB max FIFO size is 640 x 4 Bytes!" +#error "The USB max FIFO size is 640 x 4 Bytes!" #endif #endif #ifdef USB_HS_MODE -#define RX_FIFO_HS_SIZE (512U) -#define TXH_NP_HS_FIFOSIZ (128U) -#define TXH_P_HS_FIFOSIZ (256U) +#define RX_FIFO_HS_SIZE (512U) +#define TXH_NP_HS_FIFOSIZ (128U) +#define TXH_P_HS_FIFOSIZ (256U) #if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U) -#error "The USB max FIFO size is 2048 x 4 Bytes!" +#error "The USB max FIFO size is 2048 x 4 Bytes!" #endif #endif #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/usb_config/usb_bsp.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/usb_config/usb_bsp.h index 76b5b37d81c..0df0dfbeda3 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/usb_config/usb_bsp.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/config/usb_config/usb_bsp.h @@ -13,8 +13,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include "hc32_ll_utility.h" diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h index d762176f47b..40dee6cbc22 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/hc32f4xx_conf.h @@ -27,8 +27,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -48,66 +47,66 @@ extern "C" * Library. * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. */ -#define LL_ICG_ENABLE (DDL_ON) -#define LL_UTILITY_ENABLE (DDL_ON) -#define LL_PRINT_ENABLE (DDL_OFF) - -#define LL_ADC_ENABLE (DDL_ON) -#define LL_AES_ENABLE (DDL_ON) -#define LL_AOS_ENABLE (DDL_ON) -#define LL_CAN_ENABLE (DDL_ON) -#define LL_CLK_ENABLE (DDL_ON) -#define LL_CMP_ENABLE (DDL_ON) -#define LL_CRC_ENABLE (DDL_ON) -#define LL_CTC_ENABLE (DDL_ON) -#define LL_DAC_ENABLE (DDL_ON) -#define LL_DBGC_ENABLE (DDL_OFF) -#define LL_DCU_ENABLE (DDL_ON) -#define LL_DMA_ENABLE (DDL_ON) -#define LL_DMC_ENABLE (DDL_ON) -#define LL_DVP_ENABLE (DDL_ON) -#define LL_EFM_ENABLE (DDL_ON) -#define LL_EMB_ENABLE (DDL_ON) -#define LL_ETH_ENABLE (DDL_ON) -#define LL_EVENT_PORT_ENABLE (DDL_OFF) -#define LL_FCG_ENABLE (DDL_ON) -#define LL_FCM_ENABLE (DDL_ON) -#define LL_FMAC_ENABLE (DDL_ON) -#define LL_GPIO_ENABLE (DDL_ON) -#define LL_HASH_ENABLE (DDL_ON) -#define LL_HRPWM_ENABLE (DDL_ON) -#define LL_I2C_ENABLE (DDL_ON) -#define LL_I2S_ENABLE (DDL_ON) -#define LL_INTERRUPTS_ENABLE (DDL_ON) -#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) -#define LL_KEYSCAN_ENABLE (DDL_ON) -#define LL_MAU_ENABLE (DDL_ON) -#define LL_MPU_ENABLE (DDL_ON) -#define LL_NFC_ENABLE (DDL_ON) -#define LL_OTS_ENABLE (DDL_ON) -#define LL_PWC_ENABLE (DDL_ON) -#define LL_QSPI_ENABLE (DDL_ON) -#define LL_RMU_ENABLE (DDL_ON) -#define LL_RTC_ENABLE (DDL_ON) -#define LL_SDIOC_ENABLE (DDL_ON) -#define LL_SMC_ENABLE (DDL_ON) -#define LL_SPI_ENABLE (DDL_ON) -#define LL_SRAM_ENABLE (DDL_ON) -#define LL_SWDT_ENABLE (DDL_ON) -#define LL_TMR0_ENABLE (DDL_ON) -#define LL_TMR2_ENABLE (DDL_ON) -#define LL_TMR4_ENABLE (DDL_ON) -#define LL_TMR6_ENABLE (DDL_ON) -#define LL_TMRA_ENABLE (DDL_ON) -#define LL_TRNG_ENABLE (DDL_ON) -#define LL_USART_ENABLE (DDL_ON) -#define LL_USB_ENABLE (DDL_ON) -#define LL_WDT_ENABLE (DDL_ON) +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_DMC_ENABLE (DDL_ON) +#define LL_DVP_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_ETH_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_HRPWM_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_NFC_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR2_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) /** * @brief The following is a list of currently supported BSP boards. */ -#define BSP_EV_HC32F4A0_LQFP176 (1U) +#define BSP_EV_HC32F4A0_LQFP176 (1U) /** * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently @@ -116,42 +115,42 @@ extern "C" * @note If there is no supported BSP board or the BSP function is not used, * the value needs to be set to 0U. */ -#define BSP_EV_HC32F4XX (0U) +#define BSP_EV_HC32F4XX (0U) /** * @brief This is the list of BSP components to be used. * Select the components you need to use to DDL_ON. */ -#define BSP_24CXX_ENABLE (DDL_OFF) -#define BSP_GT9XX_ENABLE (DDL_OFF) -#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF) -#define BSP_IS62WV51216_ENABLE (DDL_OFF) -#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) -#define BSP_NT35510_ENABLE (DDL_OFF) -#define BSP_OV5640_ENABLE (DDL_OFF) -#define BSP_TCA9539_ENABLE (DDL_OFF) -#define BSP_W25QXX_ENABLE (DDL_OFF) -#define BSP_WM8731_ENABLE (DDL_OFF) +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_GT9XX_ENABLE (DDL_OFF) +#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF) +#define BSP_IS62WV51216_ENABLE (DDL_OFF) +#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_OV5640_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_WM8731_ENABLE (DDL_OFF) /** * @brief Ethernet and PHY Configuration. */ /* MAC ADDRESS */ -#define ETH_MAC_ADDR0 (0x02U) -#define ETH_MAC_ADDR1 (0x00U) -#define ETH_MAC_ADDR2 (0x00U) -#define ETH_MAC_ADDR3 (0x00U) -#define ETH_MAC_ADDR4 (0x00U) -#define ETH_MAC_ADDR5 (0x00U) - -#if defined (ETH_PHY_USING_RTL8201F) +#define ETH_MAC_ADDR0 (0x02U) +#define ETH_MAC_ADDR1 (0x00U) +#define ETH_MAC_ADDR2 (0x00U) +#define ETH_MAC_ADDR3 (0x00U) +#define ETH_MAC_ADDR4 (0x00U) +#define ETH_MAC_ADDR5 (0x00U) + +#if defined(ETH_PHY_USING_RTL8201F) /* PHY(RTL8201F) Address*/ -#define ETH_PHY_ADDR (0x01U) +#define ETH_PHY_ADDR (0x01U) /* PHY Status Register */ -#define PHY_SR (0x00U) /*!< PHY status register */ -#define PHY_DUPLEX_STATUS (0x0100U) /*!< PHY Duplex mask */ -#define PHY_SPEED_STATUS (0x2000U) /*!< PHY Speed mask */ +#define PHY_SR (0x00U) /*!< PHY status register */ +#define PHY_DUPLEX_STATUS (0x0100U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS (0x2000U) /*!< PHY Speed mask */ #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/fal_cfg.h index 5d8fbbe9e63..9a8de41f9c2 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/fal_cfg.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/fal_cfg.h @@ -23,20 +23,20 @@ extern const struct fal_flash_dev hc32_onchip_flash; extern struct fal_flash_dev ext_nor_flash0; /* flash device table */ -#define FAL_FLASH_DEV_TABLE \ -{ \ - &hc32_onchip_flash, \ - &ext_nor_flash0, \ -} +#define FAL_FLASH_DEV_TABLE \ + { \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ + } /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ -#define FAL_PART_TABLE \ -{ \ - {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0}, \ - {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ -} +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \ + } #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/nand_port.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/nand_port.h index 34b62b6fa3b..976376d5e11 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/nand_port.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/nand_port.h @@ -12,72 +12,75 @@ #define __NAND_PORT_H__ /******************** NAND chip information ***********************************/ -#define NAND_BYTES_PER_PAGE 2048UL -#define NAND_SPARE_AREA_SIZE 64UL -#define NAND_PAGES_PER_BLOCK 64UL -#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) -#define NAND_BLOCKS_PER_PLANE 1024UL -#define NAND_PLANE_PER_DEVICE 2UL -#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) -#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) +#define NAND_BYTES_PER_PAGE 2048UL +#define NAND_SPARE_AREA_SIZE 64UL +#define NAND_PAGES_PER_BLOCK 64UL +#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) +#define NAND_BLOCKS_PER_PLANE 1024UL +#define NAND_PLANE_PER_DEVICE 2UL +#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) +#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) /******************** EXMC_NFC configure **************************************/ /* chip: EXMC_NFC_BANK0~7 */ -#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0 +#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0 /* density:2Gbit */ -#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT +#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT /* device width: 8-bit */ -#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT +#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT + +/* BankNum: 1BANK */ +#define NAND_EXMC_NFC_BANK_NUMBER EXMC_NFC_1BANK /* page size: 2KByte */ -#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE +#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE /* row address cycle: 3 */ -#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE +#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE /* ECC mode */ -#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC +#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC /* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */ /* TS: ALE/CLE/CE setup time(min=10ns) */ -#define NAND_TS 1U +#define NAND_TS 1U /* TWP: WE# pulse width (min=10ns) */ -#define NAND_TWP 1U +#define NAND_TWP 1U /* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */ -#define NAND_TRP 2U +#define NAND_TRP 2U /* TTH: ALE/CLE/CE hold time (min=5ns) */ -#define NAND_TH 1U +#define NAND_TH 1U /* TWH: WE# pulse width HIGH (min=10ns) */ -#define NAND_TWH 1U +#define NAND_TWH 1U /* TRH: RE# pulse width HIGH (min=7ns) */ -#define NAND_TRH 1U +#define NAND_TRH 1U /* TRR: Ready to RE# LOW (min=20ns) */ -#define NAND_TRR 2U +#define NAND_TRR 2U /* TWB: WE# HIGH to busy (max=100ns) */ -#define NAND_TWB 1U +#define NAND_TWB 1U /* TWB: WE# HIGH to busy (max=100ns) */ -#define NAND_TRB 1U +#define NAND_TRB 1U /* TCCS: Change read column and Change write column delay */ -#define NAND_TCCS 5U +#define NAND_TCCS 5U /* TWTR: WE# HIGH to RE# LOW (min=60ns) */ -#define NAND_TWTR 4U +#define NAND_TWTR 4U /* TRTW: RE# HIGH to WE# LOW (min=100ns) */ -#define NAND_TRTW 7U +#define NAND_TRTW 7U /* TADL: ALE to data start (min=70ns) */ -#define NAND_TADL 5U +#define NAND_TADL 5U #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/sdram_port.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/sdram_port.h index 7b9ebd04aba..615d6a695d0 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/sdram_port.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/sdram_port.h @@ -14,73 +14,73 @@ /* parameters for sdram peripheral */ /* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */ -#define SDRAM_CHIP EXMC_DMC_CHIP1 +#define SDRAM_CHIP EXMC_DMC_CHIP1 /* bank address */ -#define SDRAM_BANK_ADDR (0x80000000UL) +#define SDRAM_BANK_ADDR (0x80000000UL) /* size(kbyte):8MB = 8*1024*1KBytes */ -#define SDRAM_SIZE (8UL * 1024UL * 1024UL) +#define SDRAM_SIZE (8UL * 1024UL * 1024UL) /* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */ -#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 +#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 /* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */ -#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT +#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT /* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */ -#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM8 +#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM8 /* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */ -#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM12 +#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM12 /* cas latency clock number: 2, 3 */ -#define SDRAM_CAS_LATENCY 2UL +#define SDRAM_CAS_LATENCY 2UL /* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */ -#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT +#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT /* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */ -#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD +#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD /* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */ -#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL +#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL /* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */ -#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED +#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED /* timing configuration(EXCLK clock frequency: 30MHz) for IS42S16400J-7TLI */ /* refresh rate counter (EXCLK clock) */ -#define SDRAM_REFRESH_COUNT (450U) +#define SDRAM_REFRESH_COUNT (450U) /* TMDR: mode register command time (EXCLK clock) */ -#define SDRAM_TMDR 2U +#define SDRAM_TMDR 2U /* TRAS: RAS to precharge delay time (EXCLK clock) */ -#define SDRAM_TRAS 2U +#define SDRAM_TRAS 2U /* TRC: active bank x to active bank x delay time (EXCLK clock) */ -#define SDRAM_TRC 2U +#define SDRAM_TRC 2U /* TRCD: RAS to CAS minimum delay time (EXCLK clock) */ -#define SDRAM_TRCD_B 3U -#define SDRAM_TRCD_P 0U +#define SDRAM_TRCD_B 3U +#define SDRAM_TRCD_P 0U /* TRFC: autorefresh command time (EXCLK clock) */ -#define SDRAM_TRFC_B 3U -#define SDRAM_TRFC_P 0U +#define SDRAM_TRFC_B 3U +#define SDRAM_TRFC_P 0U /* TRP: precharge to RAS delay time (EXCLK clock) */ -#define SDRAM_TRP_B 3U -#define SDRAM_TRP_P 0U +#define SDRAM_TRP_B 3U +#define SDRAM_TRP_P 0U /* TRRD: active bank x to active bank y delay time (EXCLK clock) */ -#define SDRAM_TRRD 1U +#define SDRAM_TRRD 1U /* TWR: write to precharge delay time (EXCLK clock). */ -#define SDRAM_TWR 2U +#define SDRAM_TWR 2U /* TWTR: write to read delay time (EXCLK clock). */ -#define SDRAM_TWTR 1U +#define SDRAM_TWTR 1U /* TXP: exit power-down command time (EXCLK clock). */ -#define SDRAM_TXP 1U +#define SDRAM_TXP 1U /* TXSR: exit self-refresh command time (EXCLK clock). */ -#define SDRAM_TXSR 5U +#define SDRAM_TXSR 5U /* TESR: self-refresh command time (EXCLK clock). */ -#define SDRAM_TESR 5U +#define SDRAM_TESR 5U /* memory mode register */ -#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) -#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) -#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) -#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) -#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) -#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) +#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) +#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) +#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) +#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) +#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) +#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539_port.h index 74efa2c51eb..5a9d886e043 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539_port.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/tca9539_port.h @@ -17,23 +17,23 @@ * @defgroup HC32F4A0_EV_IO_Function_Sel Expand IO function definition * @{ */ -#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ -#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ -#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */ -#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */ -#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */ -#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */ -#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ -#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ +#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ +#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ +#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */ +#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */ +#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */ +#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ -#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */ -#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */ -#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ -#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ -#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ -#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ -#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ -#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */ +#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */ +#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ +#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ +#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ /** * @} */ @@ -42,12 +42,12 @@ * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition * @{ */ -#define LED_RED_PORT (TCA9539_IO_PORT1) -#define LED_RED_PIN (EIO_LED_RED) -#define LED_YELLOW_PORT (TCA9539_IO_PORT1) -#define LED_YELLOW_PIN (EIO_LED_YELLOW) -#define LED_BLUE_PORT (TCA9539_IO_PORT1) -#define LED_BLUE_PIN (EIO_LED_BLUE) +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) /** * @} */ @@ -56,8 +56,8 @@ * @defgroup BSP CAN PHY STB port/pin definition * @{ */ -#define CAN_STB_PORT (TCA9539_IO_PORT1) -#define CAN_STB_PIN (EIO_CAN_STB) +#define CAN_STB_PORT (TCA9539_IO_PORT1) +#define CAN_STB_PIN (EIO_CAN_STB) /** * @} */ @@ -65,8 +65,8 @@ * @defgroup BSP_ETH_PortPin_Sel BSP ETH port/pin definition * @{ */ -#define ETH_RST_PORT (TCA9539_IO_PORT1) -#define ETH_RST_PIN (EIO_ETH_RST) +#define ETH_RST_PORT (TCA9539_IO_PORT1) +#define ETH_RST_PIN (EIO_ETH_RST) /** * @} */ diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/usb_config.h b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/usb_config.h index dd239502be3..3a4dd5aab4a 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/usb_config.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/board/ports/usb_config.h @@ -14,15 +14,15 @@ /* ================ USB common Configuration ================ */ #ifdef __RTTHREAD__ - #include +#include - #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) #else - #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) #endif #ifndef CONFIG_USB_DBG_LEVEL - #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO #endif /* Enable print with color */ @@ -32,9 +32,9 @@ /* data align size when use dma or use dcache */ #ifdef CONFIG_USB_DCACHE_ENABLE - #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 #else - #define CONFIG_USB_ALIGN_SIZE 4 +#define CONFIG_USB_ALIGN_SIZE 4 #endif /* attribute data into no cache ram */ @@ -49,7 +49,7 @@ /* Ep0 in and out transfer buffer */ #ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN - #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 #endif /* Send ep0 in data from user buffer instead of copying into ep0 reqdata @@ -70,31 +70,31 @@ // #define CONFIG_USBDEV_EP0_THREAD #ifndef CONFIG_USBDEV_EP0_PRIO - #define CONFIG_USBDEV_EP0_PRIO 4 +#define CONFIG_USBDEV_EP0_PRIO 4 #endif #ifndef CONFIG_USBDEV_EP0_STACKSIZE - #define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#define CONFIG_USBDEV_EP0_STACKSIZE 2048 #endif #ifndef CONFIG_USBDEV_MSC_MAX_LUN - #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#define CONFIG_USBDEV_MSC_MAX_LUN 1 #endif #ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE - #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 #endif #ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING - #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" #endif #ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING - #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" #endif #ifndef CONFIG_USBDEV_MSC_VERSION_STRING - #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" #endif /* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ @@ -104,50 +104,50 @@ // #define CONFIG_USBDEV_MSC_THREAD #ifndef CONFIG_USBDEV_MSC_PRIO - #define CONFIG_USBDEV_MSC_PRIO 4 +#define CONFIG_USBDEV_MSC_PRIO 4 #endif #ifndef CONFIG_USBDEV_MSC_STACKSIZE - #define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 #endif #ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE - #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 #endif #ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS - #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 #endif #ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME - #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 #endif #define CONFIG_USBDEV_MTP_THREAD #ifndef CONFIG_USBDEV_MTP_PRIO - #define CONFIG_USBDEV_MTP_PRIO 4 +#define CONFIG_USBDEV_MTP_PRIO 4 #endif #ifndef CONFIG_USBDEV_MTP_STACKSIZE - #define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#define CONFIG_USBDEV_MTP_STACKSIZE 4096 #endif #ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE - #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 #endif /* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ #ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE - #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 #endif #ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID - #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff #endif #ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC - #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" #endif #define CONFIG_USBDEV_RNDIS_USING_LWIP @@ -171,95 +171,95 @@ #define CONFIG_USBHOST_DEV_NAMELEN 16 #ifndef CONFIG_USBHOST_PSC_PRIO - #define CONFIG_USBHOST_PSC_PRIO 0 +#define CONFIG_USBHOST_PSC_PRIO 0 #endif #ifndef CONFIG_USBHOST_PSC_STACKSIZE - #define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 #endif //#define CONFIG_USBHOST_GET_STRING_DESC // #define CONFIG_USBHOST_MSOS_ENABLE #ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE - #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 #endif /* Ep0 max transfer buffer */ #ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN - #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 #endif #ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT - #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 #endif #ifndef CONFIG_USBHOST_MSC_TIMEOUT - #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) #endif #define CONFIG_USBHOST_BLUETOOTH_HCI_H4 // #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG #ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE - #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 #endif #ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE - #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 #endif /* ================ USB Device Port Configuration ================*/ #ifndef CONFIG_USBDEV_MAX_BUS - #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip #endif #ifndef CONFIG_USBDEV_EP_NUM - #define CONFIG_USBDEV_EP_NUM 8 +#define CONFIG_USBDEV_EP_NUM 8 #endif // #define CONFIG_USBDEV_SOF_ENABLE @@ -276,76 +276,76 @@ // #define CONFIG_USB_DWC2_DMA_ENABLE /* Defined FS Core device FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) -#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE (32) /* Defined FS Core host FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) -#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) /* Defined FS Core total FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (640) +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (640) /* Defined HS Core Device FIFO Size in words 32-bits */ -#define CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE (1024) -#define CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE (1024) +#define CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE (0) /* Defined HS Core host FIFO Size in words 32-bits */ -#define CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE (512) -#define CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE (256) +#define CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE (512) +#define CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE (256) /* Defined HS Core total FIFO Size in words 32-bits */ -#define CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE (2048) +#define CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE (2048) /* ================ USB Host Port Configuration ==================*/ #ifndef CONFIG_USBHOST_MAX_BUS - #define CONFIG_USBHOST_MAX_BUS 1 +#define CONFIG_USBHOST_MAX_BUS 1 #endif #ifndef CONFIG_USBHOST_PIPE_NUM - #define CONFIG_USBHOST_PIPE_NUM 10 +#define CONFIG_USBHOST_PIPE_NUM 10 #endif #ifndef usb_phyaddr2ramaddr - #define usb_phyaddr2ramaddr(addr) (addr) +#define usb_phyaddr2ramaddr(addr) (addr) #endif #ifndef usb_ramaddr2phyaddr - #define usb_ramaddr2phyaddr(addr) (addr) +#define usb_ramaddr2phyaddr(addr) (addr) #endif #endif diff --git a/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h index 692061461c1..bd47c55a816 100644 --- a/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h +++ b/bsp/hc32/ev_hc32f4a0_lqfp176/rtconfig.h @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 @@ -329,14 +329,6 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ - -/* HPMicro SDK */ - -/* end of HPMicro SDK */ - -/* FT32 HAL & SDK Drivers */ - -/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f4a2_lqfp176/.ci/attachconfig/ci.attachconfig.yml new file mode 100644 index 00000000000..9f5f2866382 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/.ci/attachconfig/ci.attachconfig.yml @@ -0,0 +1,195 @@ +# ------ device CI ------ +devices.adc: + kconfig: + - CONFIG_BSP_USING_ADC=y + - CONFIG_BSP_USING_ADC1=y + - CONFIG_BSP_ADC1_USING_DMA=y +devices.can: + kconfig: + - CONFIG_BSP_USING_CAN=y + - CONFIG_BSP_USING_CAN1=y + - CONFIG_RT_CAN_USING_CANFD=y + - CONFIG_RT_CAN_USING_HDR=y +devices.crypto: + kconfig: + - CONFIG_BSP_USING_HWCRYPTO=y + - CONFIG_BSP_USING_UQID=y + - CONFIG_BSP_USING_RNG=y + - CONFIG_BSP_USING_CRC=y + - CONFIG_BSP_USING_AES=y + - CONFIG_BSP_USING_HASH=y +devices.dac: + kconfig: + - CONFIG_BSP_USING_DAC=y + - CONFIG_BSP_USING_DAC1=y +devices.flash: + kconfig: + - CONFIG_BSP_USING_ON_CHIP_FLASH=y + - CONFIG_RT_USING_FAL=y + - CONFIG_RT_USING_SPI=y + - CONFIG_RT_USING_SFUD=y +devices.gpio: + kconfig: + - CONFIG_BSP_USING_GPIO=y +devices.clock_timer: + kconfig: + - CONFIG_BSP_USING_CLOCK_TIMER=y + - CONFIG_BSP_USING_TMRA_1=y +devices.i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1=y + - CONFIG_BSP_I2C1_TX_USING_DMA=y + - CONFIG_BSP_I2C1_RX_USING_DMA=y +devices.input_capture: + kconfig: + - CONFIG_BSP_USING_INPUT_CAPTURE=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6=y + - CONFIG_BSP_USING_INPUT_CAPTURE_TMR6_1=y +devices.pm: + kconfig: + - CONFIG_BSP_USING_PM=y + - CONFIG_IDLE_THREAD_STACK_SIZE=512 +devices.pulse_encoder_tmr6: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMR6_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMR6_1=y +devices.pulse_encoder_tmra: + kconfig: + - CONFIG_BSP_USING_PULSE_ENCODER=y + - CONFIG_BSP_USING_TMRA_PULSE_ENCODER=y + - CONFIG_BSP_USING_PULSE_ENCODER_TMRA_1=y +devices.pwm_tmr4: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR4=y + - CONFIG_BSP_USING_PWM_TMR4_1=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUH=y + - CONFIG_BSP_USING_PWM_TMR4_1_OUL=y +devices.pwm_tmr6: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMR6=y + - CONFIG_BSP_USING_PWM_TMR6_1=y + - CONFIG_BSP_USING_PWM_TMR6_1_A=y + - CONFIG_BSP_USING_PWM_TMR6_1_B=y +devices.pwm_tmra: + kconfig: + - CONFIG_BSP_USING_PWM=y + - CONFIG_BSP_USING_PWM_TMRA=y + - CONFIG_BSP_USING_PWM_TMRA_1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH1=y + - CONFIG_BSP_USING_PWM_TMRA_1_CH2=y +devices.qspi: + kconfig: + - CONFIG_BSP_USING_QSPI=y + - CONFIG_BSP_QSPI_USING_DMA=y + - CONFIG_BSP_QSPI_USING_SOFT_CS=y +devices.rtc: + kconfig: + - CONFIG_BSP_USING_RTC=y + - CONFIG_RT_USING_ALARM=y +devices.sdio: + kconfig: + - CONFIG_BSP_USING_SDIO=y + - CONFIG_BSP_USING_SDIO1=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.soft_i2c: + kconfig: + - CONFIG_BSP_USING_I2C=y + - CONFIG_BSP_USING_I2C1_SW=y +devices.spi: + kconfig: + - CONFIG_BSP_USING_SPI=y + - CONFIG_BSP_USING_SPI1=y + - CONFIG_BSP_SPI1_TX_USING_DMA=y + - CONFIG_BSP_SPI1_RX_USING_DMA=y + - CONFIG_BSP_SPI_USING_DMA=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.uart_v1: + kconfig: + - CONFIG_RT_USING_SERIAL_V1=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.uart_v2: + kconfig: + - CONFIG_RT_USING_SERIAL_V2=y + - CONFIG_BSP_USING_UART=y + - CONFIG_BSP_USING_UART1=y + - CONFIG_RT_SERIAL_USING_DMA=y + - CONFIG_BSP_UART1_RX_USING_DMA=y + - CONFIG_BSP_UART1_TX_USING_DMA=y +devices.usb_hs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBD_HS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_hs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBHS=y + - CONFIG_BSP_USING_USBH_HS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.usb_fs_device: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBD=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBD_FS=y + - CONFIG_RT_USB_DEVICE_MSTORAGE=y +devices.usb_fs_host: + kconfig: + - CONFIG_BSP_USING_USB=y + - CONFIG_BSP_USING_USBH=y + - CONFIG_BSP_USING_USBFS=y + - CONFIG_BSP_USING_USBH_FS=y + - CONFIG_RT_USBH_MSTORAGE=y + - CONFIG_RT_USING_DFS=y + - CONFIG_RT_USING_DFS_ELMFAT=y +devices.watchdog_swdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_SWDT=y +devices.watchdog_wdt: + kconfig: + - CONFIG_BSP_USING_WDT_TMR=y + - CONFIG_BSP_USING_WDT=y + +# ------ peripheral CI ------ +peripheral.eth_mii: + kconfig: + - CONFIG_BSP_USING_ETH=y + - CONFIG_ETH_INTERFACE_USING_MII=y + - CONFIG_RT_USING_LWIP212=y + - CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +peripheral.eth_rmii: + kconfig: + - CONFIG_BSP_USING_ETH=y + - CONFIG_ETH_INTERFACE_USING_RMII=y + - CONFIG_ETH_PHY_USING_INTERRUPT_MODE=y + - CONFIG_RT_USING_LWIP212=y + - CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +peripheral.exmc_nand: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_NAND=y + - CONFIG_FINSH_USING_MSH=y +peripheral.exmc_sdram: + kconfig: + - CONFIG_BSP_USING_EXMC=y + - CONFIG_BSP_USING_SDRAM=y + - CONFIG_FINSH_USING_MSH=y +peripheral.spi_flash: + kconfig: + - CONFIG_BSP_USING_SPI_FLASH=y diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/.config b/bsp/hc32/ev_hc32f4a2_lqfp176/.config new file mode 100644 index 00000000000..178f1f9a13a --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/.config @@ -0,0 +1,1486 @@ + +# +# RT-Thread Kernel +# + +# +# klibc options +# + +# +# rt_vsnprintf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSNPRINTF is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_LONGLONG is not set +# CONFIG_RT_KLIBC_USING_VSNPRINTF_STANDARD is not set +# end of rt_vsnprintf options + +# +# rt_vsscanf options +# +# CONFIG_RT_KLIBC_USING_LIBC_VSSCANF is not set +# end of rt_vsscanf options + +# +# rt_memset options +# +# CONFIG_RT_KLIBC_USING_USER_MEMSET is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMSET is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMSET is not set +# end of rt_memset options + +# +# rt_memcpy options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCPY is not set +# CONFIG_RT_KLIBC_USING_TINY_MEMCPY is not set +# end of rt_memcpy options + +# +# rt_memmove options +# +# CONFIG_RT_KLIBC_USING_USER_MEMMOVE is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMMOVE is not set +# end of rt_memmove options + +# +# rt_memcmp options +# +# CONFIG_RT_KLIBC_USING_USER_MEMCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_MEMCMP is not set +# end of rt_memcmp options + +# +# rt_strstr options +# +# CONFIG_RT_KLIBC_USING_USER_STRSTR is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRSTR is not set +# end of rt_strstr options + +# +# rt_strcasecmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCASECMP is not set +# end of rt_strcasecmp options + +# +# rt_strncpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCPY is not set +# end of rt_strncpy options + +# +# rt_strcpy options +# +# CONFIG_RT_KLIBC_USING_USER_STRCPY is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCPY is not set +# end of rt_strcpy options + +# +# rt_strncmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRNCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRNCMP is not set +# end of rt_strncmp options + +# +# rt_strcmp options +# +# CONFIG_RT_KLIBC_USING_USER_STRCMP is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRCMP is not set +# end of rt_strcmp options + +# +# rt_strlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRLEN is not set +# CONFIG_RT_KLIBC_USING_LIBC_STRLEN is not set +# end of rt_strlen options + +# +# rt_strnlen options +# +# CONFIG_RT_KLIBC_USING_USER_STRNLEN is not set +# end of rt_strnlen options +# end of klibc options + +CONFIG_RT_NAME_MAX=24 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_NANO is not set +# CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_CPUS_NR=1 +CONFIG_RT_ALIGN_SIZE=8 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +# CONFIG_RT_USING_HOOKLIST is not set +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=512 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +# CONFIG_RT_USING_TIMER_ALL_SOFT is not set +# CONFIG_RT_USING_CPU_USAGE_TRACER is not set + +# +# kservice options +# +# CONFIG_RT_USING_TINY_FFS is not set +# end of kservice options + +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_ASSERT=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +# CONFIG_RT_DEBUGING_AUTO_INIT is not set +# CONFIG_RT_USING_CI_ACTION is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set +# CONFIG_RT_USING_SIGNALS is not set +# end of Inter-Thread communication + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMHEAP is not set +CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +# CONFIG_RT_USING_SLAB_AS_HEAP is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP=y +# end of Memory Management + +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +# CONFIG_RT_USING_THREADSAFE_PRINTF is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_USING_CONSOLE_OUTPUT_CTL=y +CONFIG_RT_VER_NUM=0x50300 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_BACKTRACE_LEVEL_MAX_NR=32 +# end of RT-Thread Kernel + +CONFIG_RT_USING_HW_ATOMIC=y +CONFIG_ARCH_USING_HW_ATOMIC_8=y +CONFIG_ARCH_USING_HW_ATOMIC_16=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +# CONFIG_FINSH_USING_WORD_OPERATION is not set +# CONFIG_FINSH_USING_FUNC_EXT is not set +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 +CONFIG_FINSH_USING_OPTION_COMPLETION=y + +# +# DFS: device virtual file system +# +# CONFIG_RT_USING_DFS is not set +# end of DFS: device virtual file system + +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=2048 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_SERIAL_BYPASS is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_CLOCK_TIME is not set +CONFIG_RT_USING_I2C=y +# CONFIG_RT_I2C_DEBUG is not set +CONFIG_RT_USING_I2C_BITOPS=y +# CONFIG_RT_I2C_BITOPS_DEBUG is not set +# CONFIG_RT_USING_SOFT_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PHY_V2 is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_NULL is not set +# CONFIG_RT_USING_ZERO is not set +# CONFIG_RT_USING_RANDOM is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_RPMSG is not set +# CONFIG_RT_USING_BLK is not set +# CONFIG_RT_USING_REGULATOR is not set +# CONFIG_RT_USING_POWER_SUPPLY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_CHERRYUSB is not set +# end of Device Drivers + +# +# C/C++ and POSIX layer +# + +# +# ISO-ANSI C layer +# + +# +# Timezone and Daylight Saving Time +# +# CONFIG_RT_LIBC_USING_FULL_TZ_DST is not set +CONFIG_RT_LIBC_USING_LIGHT_TZ_DST=y +CONFIG_RT_LIBC_TZ_DEFAULT_HOUR=8 +CONFIG_RT_LIBC_TZ_DEFAULT_MIN=0 +CONFIG_RT_LIBC_TZ_DEFAULT_SEC=0 +# end of Timezone and Daylight Saving Time +# end of ISO-ANSI C layer + +# +# POSIX (Portable Operating System Interface) layer +# +# CONFIG_RT_USING_POSIX_FS is not set +# CONFIG_RT_USING_POSIX_DELAY is not set +# CONFIG_RT_USING_POSIX_CLOCK is not set +# CONFIG_RT_USING_POSIX_TIMER is not set +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# end of Interprocess Communication (IPC) +# end of POSIX (Portable Operating System Interface) layer + +# CONFIG_RT_USING_CPLUSPLUS is not set +# end of C/C++ and POSIX layer + +# +# Network +# +# CONFIG_RT_USING_SAL is not set +# CONFIG_RT_USING_NETDEV is not set +# CONFIG_RT_USING_LWIP is not set +# CONFIG_RT_USING_AT is not set +# end of Network + +# +# Memory protection +# +# CONFIG_RT_USING_MEM_PROTECTION is not set +# CONFIG_RT_USING_HW_STACK_GUARD is not set +# end of Memory protection + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set +# CONFIG_RT_USING_RT_LINK is not set +# end of Utilities + +# +# Using USB legacy version +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set +# end of Using USB legacy version + +# CONFIG_RT_USING_FDT is not set +# CONFIG_RT_USING_RUST is not set +# end of RT-Thread Components + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set +# end of RT-Thread Utestcases + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set +# CONFIG_PKG_USING_WIFI_HOST_DRIVER is not set +# CONFIG_PKG_USING_ESP_HOSTED is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set +# end of Marvell WiFi + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# end of Wiced WiFi + +# CONFIG_PKG_USING_RW007 is not set + +# +# CYW43012 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43012 is not set +# end of CYW43012 WiFi + +# +# BL808 WiFi +# +# CONFIG_PKG_USING_WLAN_BL808 is not set +# end of BL808 WiFi + +# +# CYW43439 WiFi +# +# CONFIG_PKG_USING_WLAN_CYW43439 is not set +# end of CYW43439 WiFi +# end of Wi-Fi + +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# end of IoT Cloud + +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_BT_CYW43012 is not set +# CONFIG_PKG_USING_CYW43XX is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set +# CONFIG_PKG_USING_MATTER_ADAPTATION_LAYER is not set +# CONFIG_PKG_USING_LHC_MODBUS is not set +# CONFIG_PKG_USING_QMODBUS is not set +# CONFIG_PKG_USING_PNET is not set +# CONFIG_PKG_USING_OPENER is not set +# CONFIG_PKG_USING_FREEMQTT is not set +# end of IoT - internet of things + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set +# end of security packages + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set +# CONFIG_PKG_USING_RYAN_JSON is not set +# end of JSON: JavaScript Object Notation, a lightweight data-interchange format + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# end of XML: Extensible Markup Language + +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set +# end of language packages + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set +# end of LVGL: powerful and easy-to-use embedded GUI library + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# end of u8g2: a monochrome graphic library + +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set +# end of multimedia packages + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set +# CONFIG_PKG_USING_ZDEBUG is not set +# CONFIG_PKG_USING_RVBACKTRACE is not set +# CONFIG_PKG_USING_HPATCHLITE is not set +# CONFIG_PKG_USING_THREAD_METRIC is not set +# end of tools packages + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# end of enhanced kernel services + +# CONFIG_PKG_USING_AUNITY is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set +# end of acceleration: Assembly language or algorithmic acceleration packages + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_CORE is not set +# CONFIG_PKG_USING_CMSIS_NN is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set +# end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# end of Micrium: Micrium software products porting for RT-Thread + +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_LITEOS_SDK is not set +# CONFIG_PKG_USING_TZ_DATABASE is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FILEX is not set +# CONFIG_PKG_USING_LEVELX is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_RPMSG_LITE is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set +# CONFIG_PKG_USING_TASK_MSG_BUS is not set +# CONFIG_PKG_USING_UART_FRAMEWORK is not set +# CONFIG_PKG_USING_SFDB is not set +# CONFIG_PKG_USING_RTP is not set +# CONFIG_PKG_USING_REB is not set +# CONFIG_PKG_USING_RMP is not set +# CONFIG_PKG_USING_R_RHEALSTONE is not set +# CONFIG_PKG_USING_HEARTBEAT is not set +# CONFIG_PKG_USING_MICRO_ROS_RTTHREAD_PACKAGE is not set +# end of system packages + +# +# peripheral libraries and drivers +# + +# +# HAL & SDK Drivers +# + +# +# STM32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_STM32F0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F1_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F2_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32F7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32G4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32H7RS_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L0_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L4_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32L5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32U5_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_STM32WL_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WL_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32WB_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_HAL_DRIVER is not set +# CONFIG_PKG_USING_STM32MP1_M4_CMSIS_DRIVER is not set +# end of STM32 HAL & SDK Drivers + +# +# Infineon HAL Packages +# +# CONFIG_PKG_USING_INFINEON_CAT1CM0P is not set +# CONFIG_PKG_USING_INFINEON_CMSIS is not set +# CONFIG_PKG_USING_INFINEON_CORE_LIB is not set +# CONFIG_PKG_USING_INFINEON_MTB_HAL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_MTB_PDL_CAT1 is not set +# CONFIG_PKG_USING_INFINEON_RETARGET_IO is not set +# CONFIG_PKG_USING_INFINEON_CAPSENSE is not set +# CONFIG_PKG_USING_INFINEON_CSDIDAC is not set +# CONFIG_PKG_USING_INFINEON_SERIAL_FLASH is not set +# CONFIG_PKG_USING_INFINEON_USBDEV is not set +# end of Infineon HAL Packages + +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_ESP_IDF is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# end of Kendryte SDK + +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_MM32 is not set + +# +# WCH HAL & SDK Drivers +# +# CONFIG_PKG_USING_CH32V20x_SDK is not set +# CONFIG_PKG_USING_CH32V307_SDK is not set +# end of WCH HAL & SDK Drivers + +# +# AT32 HAL & SDK Drivers +# +# CONFIG_PKG_USING_AT32A403A_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A403A_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32A423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F45x_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F402_405_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F403A_407_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F413_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F415_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F421_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F423_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F425_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32F435_437_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_HAL_DRIVER is not set +# CONFIG_PKG_USING_AT32M412_416_CMSIS_DRIVER is not set +# end of AT32 HAL & SDK Drivers + +# +# HC32 DDL Drivers +# +# CONFIG_PKG_USING_HC32F3_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_HC32F3_SERIES_DRIVER is not set +CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER=y +CONFIG_PKG_HC32F4_CMSIS_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32-f4-cmsis" +CONFIG_PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION=y +CONFIG_PKG_HC32F4_CMSIS_DRIVER_VER="latest" +CONFIG_PKG_USING_HC32F4_SERIES_DRIVER=y +CONFIG_PKG_HC32F4_SERIES_DRIVER_PATH="/packages/peripherals/hal-sdk/hc32/hc32-f4-series" +CONFIG_PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION=y +CONFIG_PKG_HC32F4_SERIES_DRIVER_VER="latest" +# end of HC32 DDL Drivers + +# +# NXP HAL & SDK Drivers +# +# CONFIG_PKG_USING_NXP_MCX_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NXP_MCX_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC_DRIVER is not set +# CONFIG_PKG_USING_NXP_LPC55S_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6SX_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMX6UL_DRIVER is not set +# CONFIG_PKG_USING_NXP_IMXRT_DRIVER is not set +# end of NXP HAL & SDK Drivers + +# +# NUVOTON Drivers +# +# CONFIG_PKG_USING_NUVOTON_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_SERIES_DRIVER is not set +# CONFIG_PKG_USING_NUVOTON_ARM926_LIB is not set +# end of NUVOTON Drivers + +# +# GD32 Drivers +# +# CONFIG_PKG_USING_GD32_ARM_CMSIS_DRIVER is not set +# CONFIG_PKG_USING_GD32_ARM_SERIES_DRIVER is not set +# end of GD32 Drivers +# end of HAL & SDK Drivers + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_MAX31855 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90382 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90394 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set +# CONFIG_PKG_USING_P3T1755 is not set +# CONFIG_PKG_USING_QMI8658 is not set +# CONFIG_PKG_USING_ICM20948 is not set +# end of sensors drivers + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set +# CONFIG_PKG_USING_CST812T is not set +# end of touch drivers + +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set +# CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_VS1003 is not set +# CONFIG_PKG_USING_X9555 is not set +# CONFIG_PKG_USING_SYSTEM_RUN_LED is not set +# CONFIG_PKG_USING_BT_MX01 is not set +# CONFIG_PKG_USING_RGPOWER is not set +# CONFIG_PKG_USING_BT_MX02 is not set +# CONFIG_PKG_USING_GC9A01 is not set +# CONFIG_PKG_USING_IK485 is not set +# CONFIG_PKG_USING_SERVO is not set +# CONFIG_PKG_USING_SEAN_WS2812B is not set +# CONFIG_PKG_USING_IC74HC165 is not set +# CONFIG_PKG_USING_IST8310 is not set +# CONFIG_PKG_USING_ST7789_SPI is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set +# end of peripheral libraries and drivers + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set +# CONFIG_PKG_USING_R_TINYMAIX is not set +# CONFIG_PKG_USING_LLMCHAT is not set +# end of AI packages + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_APID is not set +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set +# CONFIG_PKG_USING_CMSIS_DSP is not set +# end of Signal Processing and Control Algorithm Packages + +# +# miscellaneous packages +# + +# +# project laboratory +# +# end of project laboratory + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# end of samples: kernel and components samples + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_TINYSQUARE is not set +# end of entertainment: terminal games and other interesting software packages + +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_RALARAM is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LIBCRC is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set +# CONFIG_PKG_USING_DRMP is not set +# end of miscellaneous packages + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects and Demos +# +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_SKETCH_LOADER_DEMO is not set +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_RTDUINO_SENSORFUSION_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_NINEINONE_SENSOR_SHIELD is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set +# end of Projects and Demos + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_JARZEBSKI_MPU6050 is not set +# end of Sensors + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_TFT_ESPI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set +# end of Display + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set +# end of Timing + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set +# CONFIG_PKG_USING_ARDUINO_TENSORFLOW_LITE_MICRO is not set +# CONFIG_PKG_USING_ARDUINO_RUNNINGMEDIAN is not set +# end of Data Processing + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set +# end of Communication + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# end of Device Control + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# end of Other + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set +# end of Signal IO + +# +# Uncategorized +# +# end of Arduino libraries +# end of RT-Thread online packages + +CONFIG_SOC_FAMILY_HC32=y +CONFIG_SOC_SERIES_HC32F4=y + +# +# Hardware Drivers Config +# +CONFIG_SOC_HC32F4A2SI=y + +# +# On-chip Drivers +# +CONFIG_BSP_USING_ON_CHIP_FLASH_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_DCODE_CACHE=y +CONFIG_BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH=y +# end of On-chip Drivers + +# +# Onboard Peripheral Drivers +# +# CONFIG_BSP_USING_ETH is not set +# CONFIG_BSP_USING_EXMC is not set +# CONFIG_BSP_USING_SPI_FLASH is not set +CONFIG_BSP_USING_TCA9539=y +CONFIG_BSP_USING_EXT_IO=y +# end of Onboard Peripheral Drivers + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +# CONFIG_BSP_UART1_RX_USING_DMA is not set +# CONFIG_BSP_UART1_TX_USING_DMA is not set +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_UART10 is not set +CONFIG_BSP_USING_I2C=y +# CONFIG_BSP_USING_I2C1_SW is not set +CONFIG_BSP_USING_I2C_HW=y +CONFIG_BSP_USING_I2C1=y +# CONFIG_BSP_I2C1_TX_USING_DMA is not set +# CONFIG_BSP_I2C1_RX_USING_DMA is not set +# CONFIG_BSP_USING_I2C2 is not set +# CONFIG_BSP_USING_I2C3 is not set +# CONFIG_BSP_USING_I2C4 is not set +# CONFIG_BSP_USING_I2C5 is not set +# CONFIG_BSP_USING_I2C6 is not set +# CONFIG_BSP_USING_ON_CHIP_FLASH is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_ADC is not set +# CONFIG_BSP_USING_DAC is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_WDT_TMR is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_SDIO is not set +# CONFIG_BSP_USING_PM is not set +# CONFIG_BSP_USING_HWCRYPTO is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_USB is not set +# CONFIG_BSP_USING_QSPI is not set +# CONFIG_BSP_USING_PULSE_ENCODER is not set +# CONFIG_BSP_USING_CLOCK_TIMER is not set +# CONFIG_BSP_USING_INPUT_CAPTURE is not set +# end of On-chip Peripheral Drivers + +# +# Board extended module Drivers +# +# end of Hardware Drivers Config diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/.cproject b/bsp/hc32/ev_hc32f4a2_lqfp176/.cproject new file mode 100644 index 00000000000..8166ace7254 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/.cproject @@ -0,0 +1,224 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/.gitignore b/bsp/hc32/ev_hc32f4a2_lqfp176/.gitignore new file mode 100644 index 00000000000..7221bde019d --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/.project b/bsp/hc32/ev_hc32f4a2_lqfp176/.project new file mode 100644 index 00000000000..f0d0cef7e21 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/.project @@ -0,0 +1,78 @@ + + + ev_hc32f4a2_lqfp176 + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + rt-thread + 2 + virtual:/virtual + + + rt-thread/bsp + 2 + virtual:/virtual + + + rt-thread/components + 2 + $%7BPARENT-3-PROJECT_LOC%7D/components + + + rt-thread/include + 2 + $%7BPARENT-3-PROJECT_LOC%7D/include + + + rt-thread/libcpu + 2 + $%7BPARENT-3-PROJECT_LOC%7D/libcpu + + + rt-thread/src + 2 + $%7BPARENT-3-PROJECT_LOC%7D/src + + + rt-thread/bsp/hc32 + 2 + virtual:/virtual + + + rt-thread/bsp/hc32/libraries + 2 + $%7BPARENT-1-PROJECT_LOC%7D/libraries + + + rt-thread/bsp/hc32/platform + 2 + PARENT-1-PROJECT_LOC/platform + + + rt-thread/bsp/hc32/tests + 2 + PARENT-1-PROJECT_LOC/tests + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/Kconfig b/bsp/hc32/ev_hc32f4a2_lqfp176/Kconfig new file mode 100644 index 00000000000..73238d3a13b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/Kconfig @@ -0,0 +1,12 @@ +mainmenu "RT-Thread Configuration" + +BSP_DIR := . + +RTT_DIR := ../../.. + +PKGS_DIR := packages + +source "$(RTT_DIR)/Kconfig" +osource "$PKGS_DIR/Kconfig" +rsource "../libraries/Kconfig" +rsource "board/Kconfig" diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/README.md b/bsp/hc32/ev_hc32f4a2_lqfp176/README.md new file mode 100644 index 00000000000..df815c6e8db --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/README.md @@ -0,0 +1,142 @@ +# XHSC EV_F4A2_LQ176 开发板 BSP 说明 + +## 简介 + +本文档为小华半导体为 EV_F4A2_LQ176 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +EV_F4A2_LQ176 是 XHSC 官方推出的开发板，搭载 HC32F4A2SITB 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F4A2SITB 的芯片性能。 + +开发板外观如下图所示： + + ![board](figures/board.jpg) + +EV_F4A2_LQ176 开发板常用 **板载资源** 如下： + +- MCU：HC32F4A2SITB，主频240MHz，2048KB FLASH，512KB RAM +- 外部RAM：IS62WV51216(SRAM，1MB) IS42S16400J(SDRAM，8MB) +- 外部FLASH: MT29F2G08AB(Nand，256MB) W25Q64(SPI NOR，8MB) +- 常用外设 + - LED：3 个，User LED(LED0、LED1、LED2)。 + - 按键：11 个，矩阵键盘(K1~K9)、WAKEUP(K10)、RESET(K11)。 +- 常用接口：SD卡接口、以太网接口、LCD接口、USB FS/HS接口、DVP接口、3.5mm耳机接口、Line in接口、CAN接口、LIN接口。 +- 调试接口：板载DAP调试器（含USB转串口）、标准JTAG/SWD。 + +开发板更多详细信息请参考小华半导体半导体[EV_F4A2_LQ176](https://www.xhsc.com.cn) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ETH | 支持 | RTL8201F | +| Nand | 支持 | MT29F2G08AB | +| SDRAM | 支持 | IS42S16400J | +| USB 转串口 | 支持 | 使用 UART1 | + +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| ADC | 支持 | | +| CAN | 支持 | | +| Crypto | 支持 | AES，CRC，HASH，RNG | +| DAC | 支持 | | +| FLASH | 支持 | | +| GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 | +| CLOCK_TIMER | 支持 | | +| I2C | 支持 | 软件、硬件 I2C | +| InputCapture | 支持 | | +| PM | 支持 | | +| PulseEncoder | 支持 | | +| PWM | 支持 | | +| QSPI | 支持 | | +| RTC | 支持 | 闹钟精度为1分钟 | +| SDIO | 支持 | | +| SPI | 支持 | | +| UART V1 & V2 | 支持 | | +| USB | 支持 | USBFS/HS Core， device/host模式 | +| WDT | 支持 | | + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用Type-A to MircoUSB线连接开发板和PC供电。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用板载 DAP 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上LED的运行效果，绿色LED11会周期性闪烁。 + +USB虚拟COM端口默认连接串口1，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.1.0 build Apr 24 2022 13:32:39 + 2006 - 2022 Copyright by RT-Thread team +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 1 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +| 板载外设 | 模式 | 协议栈 | 注意事项 | +| :------: | :----: | :------------: | :----------------------------------------------------------- | +| USB | device | ALL | 由于协议栈的设计，当配置为CDC设备时，打开USB虚拟串口，需使能流控的DTR信号。（如使用SSCOM串口助手打开USB虚拟串口时，勾选DTR选框） | +| USB | device | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需先通过J14连接到主机（如PC），再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | ALL | ALL | 由于main()函数中的LED闪烁示例，使用的是USBFS主机的供电控制管脚，因而当配置为使用USBFS Core时，需要将main()函数中的LED示例代码手动屏蔽。 | +| USB | host | ALL | 为确保USB主机对外供电充足，建议通过J35外接5V电源供电，并短接J32的EXT跳帽。 | +| USB | host | ALL | 由于外部PHY管脚复用的原因，当配置使用USBHS Core并且使用外部PHY时，需通过J14先连接好OTG线，再复位MCU运行程序；或者将J24跳帽先短接，再复位MCU运行程序。 | +| USB | host | RTT legacy USB | 目前仅实现并测试了对U盘的支持。 | +| USB | host | RTT legacy USB | 若配置为U盘主机模式，出现部分U盘无法识别或者写入失败时，可以尝试将RTT抽象层中rt_udisk_run()函数的rt_usbh_storage_reset()操作注释掉，测试是否可以获得更好的兼容性。 | +| USB | ALL | ALL | 由于管脚复用的原因，当配置使用USBHS Core时，无法同时使用板载SPI FLASH。 | +| USB | ALL | ALL | CherryUSB 与 RTT legacy USB 组件不可同时使用;
CherryUSB与 ”On-Chip Peripheral Driver---> []Enable USB“ 不可同时使能及配置。 | +| USB | ALL | RTT legacy USB | 通过“board/config/usb_config/usb_app_conf.h” 进行应用个性化配置（主要为FIFO分配） | +| USB | ALL | CherryUSB | 通过“board/ports/usb_config.h”进行应用个性化配置（如FIFO分配、是否使用DMA[Device]、是否使用高速PHY等） | + +## 联系人信息 + +维护人: + +- [小华半导体MCU](https://www.xhsc.com.cn)，邮箱： \ No newline at end of file diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/SConscript b/bsp/hc32/ev_hc32f4a2_lqfp176/SConscript new file mode 100644 index 00000000000..20f7689c53c --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/SConstruct b/bsp/hc32/ev_hc32f4a2_lqfp176/SConstruct new file mode 100644 index 00000000000..6d2a0ea7e9c --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/SConstruct @@ -0,0 +1,83 @@ +import os +import sys +import rtconfig + +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../../..') + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +def bsp_pkg_check(): + import subprocess + + check_paths = [ + os.path.join("packages", "hc32-f4-cmsis-latest"), + os.path.join("packages", "hc32-f4-series-latest") + ] + + need_update = not all(os.path.exists(p) for p in check_paths) + + if need_update: + print("\n===============================================================================") + print("Dependency packages missing, please running 'pkgs --update'...") + print("If no packages are fetched, run 'pkgs --upgrade' first, then 'pkgs --update'...") + print("===============================================================================") + exit(1) + +RegisterPreBuildingAction(bsp_pkg_check) + +TARGET = 'rtthread.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM in ['iccarm']: + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map rtthread.map') + +Export('RTT_ROOT') +Export('rtconfig') + +SDK_ROOT = os.path.abspath('./') + +if os.path.exists(SDK_ROOT + '/libraries'): + libraries_path_prefix = SDK_ROOT + '/libraries' +else: + libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries' + +SDK_LIB = libraries_path_prefix +Export('SDK_LIB') + +# prepare building environment +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +rtconfig.BSP_LIBRARY_TYPE = None + +# include drivers +objs.extend(SConscript(os.path.join(libraries_path_prefix, 'hc32_drivers', 'SConscript'))) + +# include platform +platform_path_prefix = os.path.dirname(SDK_ROOT) + '/platform' +objs.extend(SConscript(os.path.join(platform_path_prefix, 'SConscript'))) + +# include tests +test_path_prefix = os.path.dirname(SDK_ROOT) + '/tests' +objs.extend(SConscript(os.path.join(test_path_prefix, 'SConscript'))) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/applications/SConscript b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/SConscript new file mode 100644 index 00000000000..9bb9abae897 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/SConscript @@ -0,0 +1,15 @@ +from building import * +import os + +cwd = GetCurrentDir() +src = Glob('*.c') +CPPPATH = [cwd] + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +list = os.listdir(cwd) +for item in list: + if os.path.isfile(os.path.join(cwd, item, 'SConscript')): + group = group + SConscript(os.path.join(item, 'SConscript')) + +Return('group') diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/applications/main.c b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/main.c new file mode 100644 index 00000000000..492100b7a8a --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/main.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#include +#include +#include + +/* defined the LED_GREEN pin: PC9 */ +#define LED_GREEN_PIN GET_PIN(C, 9) + + +int main(void) +{ + /* set LED_GREEN_PIN pin mode to output */ + rt_pin_mode(LED_GREEN_PIN, PIN_MODE_OUTPUT); + + while (1) + { + rt_pin_write(LED_GREEN_PIN, PIN_HIGH); + rt_thread_mdelay(500); + rt_pin_write(LED_GREEN_PIN, PIN_LOW); + rt_thread_mdelay(500); + } +} + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/xtal32_fcm.c new file mode 100644 index 00000000000..8a8b81ce84a --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/applications/xtal32_fcm.c @@ -0,0 +1,99 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +#include +#include +#include + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM) + +/** + * @brief This thread is used to monitor whether XTAL32 is stable. + * This thread only runs once after the system starts. + * When stability is detected or 2s times out, the thread will end. + * (When a timeout occurs it will be prompted via rt_kprintf) + */ +void xtal32_fcm_thread_entry(void *parameter) +{ + stc_fcm_init_t stcFcmInit; + uint32_t u32TimeOut = 0UL; + uint32_t u32Time = 200UL; /* 200*10ms = 2s */ + + /* FCM config */ + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); + (void)FCM_StructInit(&stcFcmInit); + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); + /* Enable FCM, to ensure xtal32 stable */ + FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); + + while (1) + { + if (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_END)) + { + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_END); + if ((SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR)) || (SET == FCM_GetStatus(XTAL32_FCM_UNIT, FCM_FLAG_OVF))) + { + FCM_ClearStatus(XTAL32_FCM_UNIT, FCM_FLAG_ERR | FCM_FLAG_OVF); + } + else + { + (void)FCM_DeInit(XTAL32_FCM_UNIT); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + /* XTAL32 stabled */ + break; + } + } + u32TimeOut++; + if (u32TimeOut > u32Time) + { + (void)FCM_DeInit(XTAL32_FCM_UNIT); + FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, DISABLE); + rt_kprintf("Error: XTAL32 still unstable, timeout.\n"); + break; + } + rt_thread_mdelay(10); + } +} + +int xtal32_fcm_thread_create(void) +{ + rt_thread_t tid; + + tid = rt_thread_create("xtal32_fcm", xtal32_fcm_thread_entry, RT_NULL, + XTAL32_FCM_THREAD_STACK_SIZE, RT_THREAD_PRIORITY_MAX - 2, 10); + if (tid != RT_NULL) + { + rt_thread_startup(tid); + } + else + { + rt_kprintf("create xtal32_fcm thread err!"); + } + return RT_EOK; +} +INIT_APP_EXPORT(xtal32_fcm_thread_create); + +#endif + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a2_lqfp176/board/Kconfig new file mode 100644 index 00000000000..450edc974ab --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/Kconfig @@ -0,0 +1,1042 @@ +menu "Hardware Drivers Config" + +config SOC_HC32F4A2SI + bool + select SOC_SERIES_HC32F4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "On-chip Drivers" + menuconfig BSP_USING_ON_CHIP_FLASH_CACHE + bool "Enable on-chip Flash Cache" + default y + if BSP_USING_ON_CHIP_FLASH_CACHE + config BSP_USING_ON_CHIP_FLASH_ICODE_CACHE + bool "Enable on-chip Flash ICODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_DCODE_CACHE + bool "Enable on-chip Flash DCODE Cache" + default y + config BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH + bool "Enable on-chip Flash ICODE Prefetch" + default y + endif +endmenu + +menu "Onboard Peripheral Drivers" + menuconfig BSP_USING_ETH + bool "Enable Ethernet" + default n + select RT_USING_LWIP + select RT_LWIP_USING_HW_CHECKSUM + + if BSP_USING_ETH + choice + prompt "Select ETH PHY type" + default ETH_PHY_USING_RTL8201F + + config ETH_PHY_USING_RTL8201F + bool "ETH PHY USING RTL8201F" + select BSP_USING_I2C + select BSP_USING_I2C1 + select BSP_USING_TCA9539 + endchoice + + choice + prompt "Select ETH Communication Interface" + default ETH_INTERFACE_USING_MII + + config ETH_INTERFACE_USING_MII + bool "ETH Communication USING MII" + config ETH_INTERFACE_USING_RMII + bool "ETH Communication USING RMII" + endchoice + + menuconfig ETH_PHY_USING_INTERRUPT_MODE + bool "Enable ETH PHY interrupt mode" + default n + if ETH_PHY_USING_INTERRUPT_MODE + config ETH_PHY_INTERRUPT_PIN + int "ETH PHY Interrupt pin number" + range 1 176 + default 16 + endif + endif + + config BSP_USING_EXMC + bool "Enable EXMC" + default n + if BSP_USING_EXMC + choice + prompt "Using SDRAM or NAND" + default BSP_USING_NAND + + config BSP_USING_NAND + bool "Using NAND (MT29F2G08AB)" + select RT_USING_MTD_NAND + + config BSP_USING_SDRAM + bool "Using SDRAM (IS42S16400J7TLI)" + endchoice + endif + + config BSP_USING_SPI_FLASH + bool "Enable SPI FLASH (w25q64 spi1)" + select BSP_USING_SPI + select BSP_USING_SPI1 + select BSP_USING_ON_CHIP_FLASH + select RT_USING_SFUD + select RT_USING_DFS + select RT_USING_FAL + select RT_USING_MTD_NOR + default n + + config BSP_USING_TCA9539 + bool "Enable TCA9539" + select BSP_USING_I2C + select BSP_USING_I2C1 + default n + + config BSP_USING_EXT_IO + bool + default y + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + select BSP_USING_TCA9539 + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + menuconfig BSP_USING_UART1 + bool "Enable UART1" + default y + if BSP_USING_UART1 + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_RX_BUFSIZE + int "Set UART1 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART1_TX_BUFSIZE + int "Set UART1 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + + config BSP_UART1_DMA_PING_BUFSIZE + int "Set UART1 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART1_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART2 + bool "Enable UART2" + default n + if BSP_USING_UART2 + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_RX_BUFSIZE + int "Set UART2 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_TX_BUFSIZE + int "Set UART2 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART2_DMA_PING_BUFSIZE + int "Set UART2 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART2_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART3 + bool "Enable UART3" + default n + if BSP_USING_UART3 + config BSP_UART3_RX_BUFSIZE + int "Set UART3 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART3_TX_BUFSIZE + int "Set UART3 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART4 + bool "Enable UART4" + default n + if BSP_USING_UART4 + config BSP_UART4_RX_BUFSIZE + int "Set UART4 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART4_TX_BUFSIZE + int "Set UART4 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART5 + bool "Enable UART5" + default n + if BSP_USING_UART5 + config BSP_UART5_RX_BUFSIZE + int "Set UART5 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART5_TX_BUFSIZE + int "Set UART5 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART6 + bool "Enable UART6" + default n + if BSP_USING_UART6 + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_RX_BUFSIZE + int "Set UART6 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_TX_BUFSIZE + int "Set UART6 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART6_DMA_PING_BUFSIZE + int "Set UART6 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART6_RX_USING_DMA + default 64 + endif + + menuconfig BSP_USING_UART7 + bool "Enable UART7" + default n + if BSP_USING_UART7 + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_RX_BUFSIZE + int "Set UART7 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART7_TX_BUFSIZE + int "Set UART7 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART7_DMA_PING_BUFSIZE + int "Set UART7 RX DMA ping-pong buffer size" + range 32 65535 + depends on RT_USING_SERIAL_V2 && BSP_UART7_RX_USING_DMA + default 64 + endif + + + menuconfig BSP_USING_UART8 + bool "Enable UART8" + default n + if BSP_USING_UART8 + config BSP_UART8_RX_BUFSIZE + int "Set UART8 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART8_TX_BUFSIZE + int "Set UART8 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART9 + bool "Enable UART9" + default n + if BSP_USING_UART9 + config BSP_UART9_RX_BUFSIZE + int "Set UART9 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART9_TX_BUFSIZE + int "Set UART9 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + + menuconfig BSP_USING_UART10 + bool "Enable UART10" + default n + if BSP_USING_UART10 + config BSP_UART10_RX_BUFSIZE + int "Set UART10 RX buffer size" + range 64 65535 + depends on RT_USING_SERIAL_V2 + default 256 + + config BSP_UART10_TX_BUFSIZE + int "Set UART10 TX buffer size" + range 0 65535 + depends on RT_USING_SERIAL_V2 + default 0 + endif + endif + + menuconfig BSP_USING_I2C + bool "Enable I2C BUS" + default n + select RT_USING_I2C + + if BSP_USING_I2C + menuconfig BSP_USING_I2C1_SW + bool "Enable I2C1 BUS (software simulation)" + default n + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1_SW + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 176 + default 8 # PA8 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 23 # PB7 + endif + endif + + if BSP_USING_I2C + config BSP_I2C_USING_DMA + bool + default n + config BSP_USING_I2C_HW + bool + default n + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C1 + config BSP_I2C1_USING_DMA + bool + default n + config BSP_I2C1_TX_USING_DMA + bool "Enable I2C1 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + config BSP_I2C1_RX_USING_DMA + bool "Enable I2C1 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C1_USING_DMA + endif + + menuconfig BSP_USING_I2C2 + bool "Enable I2C2 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C2 + config BSP_I2C2_USING_DMA + bool + default n + config BSP_I2C2_TX_USING_DMA + bool "Enable I2C2 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + config BSP_I2C2_RX_USING_DMA + bool "Enable I2C2 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C2_USING_DMA + endif + + menuconfig BSP_USING_I2C3 + bool "Enable I2C3 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C3 + config BSP_I2C3_USING_DMA + bool + default n + config BSP_I2C3_TX_USING_DMA + bool "Enable I2C3 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C3_USING_DMA + config BSP_I2C3_RX_USING_DMA + bool "Enable I2C3 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C3_USING_DMA + endif + + menuconfig BSP_USING_I2C4 + bool "Enable I2C4 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C4 + config BSP_I2C4_USING_DMA + bool + default n + config BSP_I2C4_TX_USING_DMA + bool "Enable I2C4 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C4_USING_DMA + config BSP_I2C4_RX_USING_DMA + bool "Enable I2C4 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C4_USING_DMA + endif + + menuconfig BSP_USING_I2C5 + bool "Enable I2C5 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C5 + config BSP_I2C5_USING_DMA + bool + default n + config BSP_I2C5_TX_USING_DMA + bool "Enable I2C5 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C5_USING_DMA + config BSP_I2C5_RX_USING_DMA + bool "Enable I2C5 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C5_USING_DMA + endif + + menuconfig BSP_USING_I2C6 + bool "Enable I2C6 BUS" + default n + select BSP_USING_I2C_HW + if BSP_USING_I2C6 + config BSP_I2C6_USING_DMA + bool + default n + config BSP_I2C6_TX_USING_DMA + bool "Enable I2C6 TX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C6_USING_DMA + config BSP_I2C6_RX_USING_DMA + bool "Enable I2C6 RX DMA" + default n + select BSP_I2C_USING_DMA + select BSP_I2C6_USING_DMA + endif + endif + + config BSP_USING_ON_CHIP_FLASH + bool "Enable on-chip FLASH" + default n + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_SPI_USING_DMA + bool + default n + + menuconfig BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + if BSP_USING_SPI1 + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI1_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + if BSP_USING_SPI2 + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI2_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + if BSP_USING_SPI3 + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI3_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_SPI4 + bool "Enable SPI4 BUS" + default n + if BSP_USING_SPI4 + config BSP_SPI4_TX_USING_DMA + bool "Enable SPI4 TX DMA" + select BSP_SPI_USING_DMA + default n + config BSP_SPI4_RX_USING_DMA + bool "Enable SPI4 RX DMA" + select BSP_SPI_USING_DMA + select BSP_SPI4_TX_USING_DMA + default n + endif + endif + + menuconfig BSP_USING_ADC + bool "Enable ADC" + default n + select RT_USING_ADC + if BSP_USING_ADC + menuconfig BSP_USING_ADC1 + bool "Enable ADC1" + default n + if BSP_USING_ADC1 + config BSP_ADC1_USING_DMA + bool "using adc1 dma" + default n + endif + menuconfig BSP_USING_ADC2 + bool "Enable ADC2" + default n + if BSP_USING_ADC2 + config BSP_ADC2_USING_DMA + bool "using adc2 dma" + default n + endif + menuconfig BSP_USING_ADC3 + bool "Enable ADC3" + default n + if BSP_USING_ADC3 + config BSP_ADC3_USING_DMA + bool "using adc3 dma" + default n + endif + endif + + menuconfig BSP_USING_DAC + bool "Enable DAC" + default n + select RT_USING_DAC + if BSP_USING_DAC + config BSP_USING_DAC1 + bool "using dac1" + default n + config BSP_USING_DAC2 + bool "using dac2" + default n + endif + + menuconfig BSP_USING_CAN + bool "Enable CAN" + default n + select RT_USING_CAN + select RT_CAN_USING_HDR + select BSP_USING_TCA9539 + if BSP_USING_CAN + config BSP_USING_CAN1 + bool "using can1" + default n + config BSP_USING_CAN2 + bool "using can2" + default n + endif + + menuconfig BSP_USING_WDT_TMR + bool "Enable Watchdog Timer" + default n + select RT_USING_WDT + if BSP_USING_WDT_TMR + choice + prompt "Select SWDT/WDT" + default BSP_USING_SWDT + + config BSP_USING_SWDT + bool "SWDT(3.72hour(max))" + config BSP_USING_WDT + bool "WDT(10.7s(max))" + endchoice + + config BSP_WDT_CONTINUE_COUNT + bool "Low Power Mode Keeps Counting" + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + default n + if BSP_USING_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_XTAL32 + + config BSP_RTC_USING_XTAL32 + bool "RTC USING XTAL32" + + config BSP_RTC_USING_LRC + bool "RTC USING LRC" + endchoice + endif + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + default n + select RT_USING_SDIO + select RT_USING_DFS + if BSP_USING_SDIO + config BSP_USING_SDIO1 + bool "Enable SDIO1" + default n + config BSP_USING_SDIO2 + bool "Enable SDIO2" + default n + endif + + menuconfig BSP_USING_PM + bool "Enable PM" + default n + select RT_USING_PM + if BSP_USING_PM + choice + prompt "Select WKTM Clock Src" + default BSP_USING_WKTM_LRC + + config BSP_USING_WKTM_XTAL32 + bool "Using Xtal32" + config BSP_USING_WKTM_LRC + bool "Using LRC" + if BSP_RTC_USING_XTAL32 + config BSP_USING_WKTM_64HZ + bool "Using 64HZ(Note:must use XTAL32 and run RTC)" + endif + endchoice + endif + + menuconfig BSP_USING_HWCRYPTO + bool "Using Hardware Crypto drivers" + default n + select RT_USING_HWCRYPTO + if BSP_USING_HWCRYPTO + config BSP_USING_UQID + bool "Enable UQID (unique id)" + default n + + config BSP_USING_RNG + bool "Using Hardware RNG" + default n + select RT_HWCRYPTO_USING_RNG + + config BSP_USING_CRC + bool "Using Hardware CRC" + default n + select RT_HWCRYPTO_USING_CRC + + config BSP_USING_AES + bool "Using Hardware AES" + default n + select RT_HWCRYPTO_USING_AES + if BSP_USING_AES + choice + prompt "Select AES Mode" + default BSP_USING_AES_ECB + + config BSP_USING_AES_ECB + bool "ECB mode" + select RT_HWCRYPTO_USING_AES_ECB + endchoice + endif + + config BSP_USING_HASH + bool "Using Hardware Hash" + default n + select RT_HWCRYPTO_USING_SHA2 + if BSP_USING_HASH + choice + prompt "Select Hash Mode" + default BSP_USING_SHA2_256 + + config BSP_USING_SHA2_256 + bool "SHA2_256 Mode" + select RT_HWCRYPTO_USING_SHA2_256 + endchoice + endif + + endif + + menuconfig BSP_USING_PWM + bool "Enable output PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM_TMRA + bool "Enable timerA output PWM" + default n + if BSP_USING_PWM_TMRA + menuconfig BSP_USING_PWM_TMRA_1 + bool "Enable timerA-1 output PWM" + default n + if BSP_USING_PWM_TMRA_1 + config BSP_USING_PWM_TMRA_1_CH1 + bool "Enable timerA-1 channel1" + default n + config BSP_USING_PWM_TMRA_1_CH2 + bool "Enable timerA-1 channel2" + default n + config BSP_USING_PWM_TMRA_1_CH3 + bool "Enable timerA-1 channel3" + default n + config BSP_USING_PWM_TMRA_1_CH4 + bool "Enable timerA-1 channel4" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR4 + bool "Enable timer4 output PWM" + default n + if BSP_USING_PWM_TMR4 + menuconfig BSP_USING_PWM_TMR4_1 + bool "Enable timer4-1 output PWM" + default n + if BSP_USING_PWM_TMR4_1 + config BSP_USING_PWM_TMR4_1_OUH + bool "Enable TMR4_1_OUH channel1" + default n + config BSP_USING_PWM_TMR4_1_OUL + bool "Enable TMR4_1_OUL channel2" + default n + config BSP_USING_PWM_TMR4_1_OVH + bool "Enable TMR4_1_OVH channel3" + default n + config BSP_USING_PWM_TMR4_1_OVL + bool "Enable TMR4_1_OVL channel4" + default n + config BSP_USING_PWM_TMR4_1_OWH + bool "Enable TMR4_1_OWH channel5" + default n + config BSP_USING_PWM_TMR4_1_OWL + bool "Enable TMR4_1_OWL channel6" + default n + endif + endif + menuconfig BSP_USING_PWM_TMR6 + bool "Enable timer6 output PWM" + default n + if BSP_USING_PWM_TMR6 + menuconfig BSP_USING_PWM_TMR6_1 + bool "Enable timer6-1 output PWM" + default n + if BSP_USING_PWM_TMR6_1 + config BSP_USING_PWM_TMR6_1_A + bool "Enable TMR6_1_A channel1" + default n + config BSP_USING_PWM_TMR6_1_B + bool "Enable TMR6_1_B channel2" + default n + endif + endif + endif + + menuconfig BSP_USING_USB + bool "Enable USB" + default n + depends on !RT_USING_CHERRYUSB + if BSP_USING_USB + config BSP_USING_USBD + bool + default n + config BSP_USING_USBH + bool + default n + config BSP_USING_USBFS + bool "Use USBFS Core" + default n + if BSP_USING_USBFS + choice + prompt "Select USB Mode" + default BSP_USING_USBD_FS + + config BSP_USING_USBD_FS + bool "USB Device Mode" + select BSP_USING_USBD + select RT_USING_USB_DEVICE + + config BSP_USING_USBH_FS + bool "USB Host Mode" + select BSP_USING_USBH + select RT_USING_USB_HOST + endchoice + if BSP_USING_USBD_FS + config BSP_USING_USBD_VBUS_SENSING + bool "Enable VBUS Sensing for Device" + default y + endif + if BSP_USING_USBH_FS + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers for Host" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + endif + config BSP_USING_USBHS + bool "Use USBHS Core" + default n + if BSP_USING_USBHS + choice + prompt "Select USB Mode" + default BSP_USING_USBH_HS + + config BSP_USING_USBD_HS + bool "USB Device Mode" + select BSP_USING_USBD + select RT_USING_USB_DEVICE + depends on !BSP_USING_USBD_FS + + config BSP_USING_USBH_HS + bool "USB Host Mode" + select BSP_USING_USBH + select RT_USING_USB_HOST + depends on !BSP_USING_USBH_FS + endchoice + choice + prompt "Select USB PHY" + default BSP_USING_USBHS_PHY_EMBED + + config BSP_USING_USBHS_PHY_EMBED + bool "Use USBHS Embedded PHY" + + config BSP_USING_USBHS_PHY_EXTERN + bool "Use USBHS External PHY" + select BSP_USING_I2C1 + select BSP_USING_TCA9539 + endchoice + if BSP_USING_USBD_HS + config BSP_USING_USBD_VBUS_SENSING + bool "Enable VBUS Sensing for Device" + default y + endif + if BSP_USING_USBH_HS + menuconfig RT_USBH_MSTORAGE + bool "Enable Udisk Drivers for Host" + default n + if RT_USBH_MSTORAGE + config UDISK_MOUNTPOINT + string "Udisk mount dir" + default "/" + endif + endif + endif + endif + + menuconfig BSP_USING_QSPI + bool "Enable QSPI BUS" + select RT_USING_QSPI + select RT_USING_SPI + default n + if BSP_USING_QSPI + config BSP_QSPI_USING_DMA + bool "Enable QSPI DMA support" + default n + config BSP_QSPI_USING_SOFT_CS + bool "Enable QSPI Soft CS Pin" + default n + endif + + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + default n + select RT_USING_PULSE_ENCODER + if BSP_USING_PULSE_ENCODER + menuconfig BSP_USING_TMRA_PULSE_ENCODER + bool "Use TIMERA As The Pulse Encoder" + default n + if BSP_USING_TMRA_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMRA_1 + bool "Use TIMERA_1 As The Pulse Encoder" + default n + endif + menuconfig BSP_USING_TMR6_PULSE_ENCODER + bool "Use TIMER6 As The Pulse Encoder" + default n + if BSP_USING_TMR6_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER_TMR6_1 + bool "Use TIMER6_1 As The Pulse Encoder" + default n + endif + endif + + menuconfig BSP_USING_CLOCK_TIMER + bool "Enable Clock Timer" + default n + select RT_USING_CLOCK_TIME + if BSP_USING_CLOCK_TIMER + config BSP_USING_TMRA_1 + bool "Use Timer_a1 As The Clock Timer" + default n + config BSP_USING_TMRA_2 + bool "Use Timer_a2 As The Clock Timer" + default n + config BSP_USING_TMRA_3 + bool "Use Timer_a3 As The Clock Timer" + default n + config BSP_USING_TMRA_4 + bool "Use Timer_a4 As The Clock Timer" + default n + config BSP_USING_TMRA_5 + bool "Use Timer_a5 As The Clock Timer" + default n + config BSP_USING_TMRA_6 + bool "Use Timer_a6 As The Clock Timer" + default n + config BSP_USING_TMRA_7 + bool "Use Timer_a7 As The Clock Timer" + default n + config BSP_USING_TMRA_8 + bool "Use Timer_a8 As The Clock Timer" + default n + config BSP_USING_TMRA_9 + bool "Use Timer_a9 As The Clock Timer" + default n + config BSP_USING_TMRA_10 + bool "Use Timer_a10 As The Clock Timer" + default n + config BSP_USING_TMRA_11 + bool "Use Timer_a11 As The Clock Timer" + default n + config BSP_USING_TMRA_12 + bool "Use Timer_a12 As The Clock Timer" + default n + endif + menuconfig BSP_USING_INPUT_CAPTURE + bool "Enable Input Capture" + default n + select RT_USING_INPUT_CAPTURE + if BSP_USING_INPUT_CAPTURE + menuconfig BSP_USING_INPUT_CAPTURE_TMR6 + bool "Use Timer6 As The Input Capture" + default n + if BSP_USING_INPUT_CAPTURE_TMR6 + config BSP_USING_INPUT_CAPTURE_TMR6_1 + bool "unit 1" + config BSP_USING_INPUT_CAPTURE_TMR6_2 + bool "unit 2" + config BSP_USING_INPUT_CAPTURE_TMR6_3 + bool "unit 3" + config BSP_USING_INPUT_CAPTURE_TMR6_4 + bool "unit 4" + config BSP_USING_INPUT_CAPTURE_TMR6_5 + bool "unit 5" + config BSP_USING_INPUT_CAPTURE_TMR6_6 + bool "unit 6" + config BSP_USING_INPUT_CAPTURE_TMR6_7 + bool "unit 7" + config BSP_USING_INPUT_CAPTURE_TMR6_8 + bool "unit 8" + endif + endif +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/SConscript b/bsp/hc32/ev_hc32f4a2_lqfp176/board/SConscript new file mode 100644 index 00000000000..e6c4a9bbb37 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/SConscript @@ -0,0 +1,20 @@ +import os +from building import * + +cwd = GetCurrentDir() + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +path = [cwd] +path += [cwd + '/ports'] +path += [cwd + '/config'] +path += [cwd + '/config/usb_config'] + +CPPDEFINES = ['HC32F4A2', '__DEBUG'] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.c b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.c new file mode 100644 index 00000000000..ed8986a9183 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.c @@ -0,0 +1,141 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#include "board.h" +#include "board_config.h" + +/* unlock/lock peripheral */ +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) + +/** System Base Configuration +*/ +void SystemBase_Config(void) +{ +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_CACHE) + EFM_ICacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_DCODE_CACHE) + EFM_DCacheCmd(ENABLE); +#endif +#if defined(BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH) + EFM_PrefetchCmd(ENABLE); +#endif + /* Reset the VBAT area */ + PWC_VBAT_Reset(); +} + +/** System Clock Configuration +*/ +void SystemClock_Config(void) +{ + stc_clock_xtal_init_t stcXtalInit; + stc_clock_pll_init_t stcPLLHInit; +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + stc_clock_pllx_init_t stcPLLAInit; +#endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + stc_clock_xtal32_init_t stcXtal32Init; +#endif + + /* PCLK0, HCLK Max 240MHz */ + /* PCLK1, PCLK4 Max 120MHz */ + /* PCLK2, PCLK3 Max 60MHz */ + /* EX BUS Max 120MHz */ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | + CLK_HCLK_DIV1)); + + GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); + (void)CLK_XtalStructInit(&stcXtalInit); + /* Config Xtal and enable Xtal */ + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; + (void)CLK_XtalInit(&stcXtalInit); + + (void)CLK_PLLStructInit(&stcPLLHInit); + /* VCO = (8/1)*120 = 960MHz*/ + stcPLLHInit.u8PLLState = CLK_PLL_ON; + stcPLLHInit.PLLCFGR = 0UL; + stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLL_SRC_XTAL; + (void)CLK_PLLInit(&stcPLLHInit); + + /* Highspeed SRAM set to 0 Read/Write wait cycle */ + SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE0, SRAM_WAIT_CYCLE0); + /* SRAM1_2_3_4_backup set to 1 Read/Write wait cycle */ + SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE1, SRAM_WAIT_CYCLE1); + /* 0-wait @ 40MHz */ + (void)EFM_SetWaitCycle(EFM_WAIT_CYCLE5); + /* 4 cycles for 200 ~ 250MHz */ + GPIO_SetReadWaitCycle(GPIO_RD_WAIT4); + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + /* PLLX for USB */ + (void)CLK_PLLxStructInit(&stcPLLAInit); + /* VCO = (8/2)*120 = 480MHz*/ + stcPLLAInit.u8PLLState = CLK_PLL_ON; + stcPLLAInit.PLLCFGR = 0UL; + stcPLLAInit.PLLCFGR_f.PLLM = 2UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLP = 10UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLAInit.PLLCFGR_f.PLLR = 4UL - 1UL; + (void)CLK_PLLxInit(&stcPLLAInit); +#endif + +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) + /* Xtal32 config */ + GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); + (void)CLK_Xtal32StructInit(&stcXtal32Init); + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; + (void)CLK_Xtal32Init(&stcXtal32Init); +#endif +} + +/** Peripheral Clock Configuration +*/ +void PeripheralClock_Config(void) +{ +#if defined(BSP_USING_CAN1) + CLK_SetCANClockSrc(CLK_CAN1, CLK_CANCLK_SYSCLK_DIV6); +#endif +#if defined(BSP_USING_CAN2) + CLK_SetCANClockSrc(CLK_CAN2, CLK_CANCLK_SYSCLK_DIV6); +#endif + +#if defined(RT_USING_ADC) + CLK_SetPeriClockSrc(CLK_PERIPHCLK_PCLK); +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) + CLK_SetUSBClockSrc(CLK_USBCLK_PLLXP); +#endif +} + +/** Peripheral Registers Unlock +*/ +void PeripheralRegister_Unlock(void) +{ + LL_PERIPH_WE(EXAMPLE_PERIPH_WE); +} + +/*@}*/ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.h new file mode 100644 index 00000000000..20946d3d6c1 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board.h @@ -0,0 +1,54 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ll.h" +#include "drv_gpio.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (2 * 1024 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) + +#define HC32_SRAM_SIZE (512) +#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) + +#ifdef __ARMCC_VERSION +extern int Image$$RW_IRAM2$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#elif __ICCARM__ +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#define HEAP_END HC32_SRAM_END + +void PeripheralRegister_Unlock(void); +void PeripheralClock_Config(void); +void SystemBase_Config(void); +void SystemClock_Config(void); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.c new file mode 100644 index 00000000000..ad66bc7fcd3 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.c @@ -0,0 +1,824 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#include +#include "board_config.h" +#include "tca9539_port.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)CM_USART1: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, USART1_RX_FUNC); + GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, USART1_TX_FUNC); + break; +#endif +#if defined(BSP_USING_UART6) + case (rt_uint32_t)CM_USART6: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART6_RX_PORT, USART6_RX_PIN, USART6_RX_FUNC); + GPIO_SetFunc(USART6_TX_PORT, USART6_TX_PIN, USART6_TX_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_I2C) +rt_err_t rt_hw_board_i2c_init(CM_I2C_TypeDef *I2Cx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + (void)GPIO_StructInit(&stcGpioInit); + + switch ((rt_uint32_t)I2Cx) + { +#if defined(BSP_USING_I2C1) + case (rt_uint32_t)CM_I2C1: + /* Configure I2C1 SDA/SCL pin. */ + GPIO_SetFunc(I2C1_SDA_PORT, I2C1_SDA_PIN, I2C1_SDA_FUNC); + GPIO_SetFunc(I2C1_SCL_PORT, I2C1_SCL_PIN, I2C1_SCL_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(RT_USING_ADC) +rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)ADCx) + { +#if defined(BSP_USING_ADC1) + case (rt_uint32_t)CM_ADC1: + (void)GPIO_Init(ADC1_CH_PORT, ADC1_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC2) + case (rt_uint32_t)CM_ADC2: + (void)GPIO_Init(ADC2_CH_PORT, ADC2_CH_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_ADC3) + case (rt_uint32_t)CM_ADC3: + (void)GPIO_Init(ADC3_CH_PORT, ADC3_CH_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_DAC) +#if defined(BSP_USING_DAC2) +void EthPhyDisable(void) +{ + TCA9539_WritePin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(ETH_RST_PORT, ETH_RST_PIN, TCA9539_DIR_OUT); +} +#endif +rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinAttr = PIN_ATTR_ANALOG; + switch ((rt_uint32_t)DACx) + { +#if defined(BSP_USING_DAC1) + case (rt_uint32_t)CM_DAC1: + (void)GPIO_Init(DAC1_CH1_PORT, DAC1_CH1_PIN, &stcGpioInit); + (void)GPIO_Init(DAC1_CH2_PORT, DAC1_CH2_PIN, &stcGpioInit); + break; +#endif +#if defined(BSP_USING_DAC2) + case (rt_uint32_t)CM_DAC2: + (void)GPIO_Init(DAC2_CH1_PORT, DAC2_CH1_PIN, &stcGpioInit); + (void)GPIO_Init(DAC2_CH2_PORT, DAC2_CH2_PIN, &stcGpioInit); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_CAN) +void CanPhyEnable(void) +{ + TCA9539_WritePin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_PIN_RESET); + TCA9539_ConfigPin(CAN_STB_PORT, CAN_STB_PIN, TCA9539_DIR_OUT); +} +rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)CANx) + { +#if defined(BSP_USING_CAN1) + case (rt_uint32_t)CM_CAN1: + GPIO_SetFunc(CAN1_TX_PORT, CAN1_TX_PIN, CAN1_TX_PIN_FUNC); + GPIO_SetFunc(CAN1_RX_PORT, CAN1_RX_PIN, CAN1_RX_PIN_FUNC); + break; +#endif +#if defined(BSP_USING_CAN2) + case (rt_uint32_t)CM_CAN2: + GPIO_SetFunc(CAN2_TX_PORT, CAN2_TX_PIN, CAN2_TX_PIN_FUNC); + GPIO_SetFunc(CAN2_RX_PORT, CAN2_RX_PIN, CAN2_RX_PIN_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + + +#if defined(RT_USING_SPI) +rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) +{ + rt_err_t result = RT_EOK; +#if defined(BSP_USING_SPI1) + stc_gpio_init_t stcGpioInit; +#endif + + switch ((rt_uint32_t)CM_SPIx) + { +#if defined(BSP_USING_SPI1) + case (rt_uint32_t)CM_SPI1: + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STAT_SET; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); + GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); + GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_ETH) +/* PHY hardware reset time */ +#define PHY_HW_RST_DELAY (0x40U) + +rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) +{ + TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); + rt_thread_mdelay(PHY_HW_RST_DELAY); + return RT_EOK; +} + +rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx) +{ +#if defined(ETH_INTERFACE_USING_RMII) + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); + GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); + GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); + GPIO_SetFunc(ETH_RMII_REF_CLK_PORT, ETH_RMII_REF_CLK_PIN, ETH_RMII_REF_CLK_FUNC); + GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); + GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); + GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); +#else + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_MII_TX_CLK_PORT, ETH_MII_TX_CLK_PIN, ETH_MII_TX_CLK_FUNC); + GPIO_SetFunc(ETH_MII_TX_EN_PORT, ETH_MII_TX_EN_PIN, ETH_MII_TX_EN_FUNC); + GPIO_SetFunc(ETH_MII_TXD0_PORT, ETH_MII_TXD0_PIN, ETH_MII_TXD0_FUNC); + GPIO_SetFunc(ETH_MII_TXD1_PORT, ETH_MII_TXD1_PIN, ETH_MII_TXD1_FUNC); + GPIO_SetFunc(ETH_MII_TXD2_PORT, ETH_MII_TXD2_PIN, ETH_MII_TXD2_FUNC); + GPIO_SetFunc(ETH_MII_TXD3_PORT, ETH_MII_TXD3_PIN, ETH_MII_TXD3_FUNC); + GPIO_SetFunc(ETH_MII_RX_CLK_PORT, ETH_MII_RX_CLK_PIN, ETH_MII_RX_CLK_FUNC); + GPIO_SetFunc(ETH_MII_RX_DV_PORT, ETH_MII_RX_DV_PIN, ETH_MII_RX_DV_FUNC); + GPIO_SetFunc(ETH_MII_RXD0_PORT, ETH_MII_RXD0_PIN, ETH_MII_RXD0_FUNC); + GPIO_SetFunc(ETH_MII_RXD1_PORT, ETH_MII_RXD1_PIN, ETH_MII_RXD1_FUNC); + GPIO_SetFunc(ETH_MII_RXD2_PORT, ETH_MII_RXD2_PIN, ETH_MII_RXD2_FUNC); + GPIO_SetFunc(ETH_MII_RXD3_PORT, ETH_MII_RXD3_PIN, ETH_MII_RXD3_FUNC); + GPIO_SetFunc(ETH_MII_RX_ER_PORT, ETH_MII_RX_ER_PIN, ETH_MII_RX_ER_FUNC); + GPIO_SetFunc(ETH_MII_CRS_PORT, ETH_MII_CRS_PIN, ETH_MII_CRS_FUNC); + GPIO_SetFunc(ETH_MII_COL_PORT, ETH_MII_COL_PIN, ETH_MII_COL_FUNC); +#endif + return RT_EOK; +} +#endif + +#if defined(RT_USING_SDIO) +rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + switch ((rt_uint32_t)SDIOCx) + { +#if defined(BSP_USING_SDIO1) + case (rt_uint32_t)CM_SDIOC1: + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); + + GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); + GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC); + GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); + GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); + GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); + GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_PWM) +#if defined(BSP_USING_PWM_TMRA) +rt_err_t rt_hw_board_pwm_tmra_init(CM_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PWM_TMRA_1) + case (rt_uint32_t)CM_TMRA_1: +#ifdef BSP_USING_PWM_TMRA_1_CH1 + GPIO_SetFunc(PWM_TMRA_1_CH1_PORT, PWM_TMRA_1_CH1_PIN, PWM_TMRA_1_CH1_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH2 + GPIO_SetFunc(PWM_TMRA_1_CH2_PORT, PWM_TMRA_1_CH2_PIN, PWM_TMRA_1_CH2_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH3 + GPIO_SetFunc(PWM_TMRA_1_CH3_PORT, PWM_TMRA_1_CH3_PIN, PWM_TMRA_1_CH3_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMRA_1_CH4 + GPIO_SetFunc(PWM_TMRA_1_CH4_PORT, PWM_TMRA_1_CH4_PIN, PWM_TMRA_1_CH4_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR4) +rt_err_t rt_hw_board_pwm_tmr4_init(CM_TMR4_TypeDef *TMR4x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR4x) + { +#if defined(BSP_USING_PWM_TMR4_1) + case (rt_uint32_t)CM_TMR4_1: +#ifdef BSP_USING_PWM_TMR4_1_OUH + GPIO_SetFunc(PWM_TMR4_1_OUH_PORT, PWM_TMR4_1_OUH_PIN, PWM_TMR4_1_OUH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OUL + GPIO_SetFunc(PWM_TMR4_1_OUL_PORT, PWM_TMR4_1_OUL_PIN, PWM_TMR4_1_OUL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVH + GPIO_SetFunc(PWM_TMR4_1_OVH_PORT, PWM_TMR4_1_OVH_PIN, PWM_TMR4_1_OVH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OVL + GPIO_SetFunc(PWM_TMR4_1_OVL_PORT, PWM_TMR4_1_OVL_PIN, PWM_TMR4_1_OVL_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWH + GPIO_SetFunc(PWM_TMR4_1_OWH_PORT, PWM_TMR4_1_OWH_PIN, PWM_TMR4_1_OWH_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR4_1_OWL + GPIO_SetFunc(PWM_TMR4_1_OWL_PORT, PWM_TMR4_1_OWL_PIN, PWM_TMR4_1_OWL_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(BSP_USING_PWM_TMR6) +rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) +{ + rt_err_t result = RT_EOK; + switch ((rt_uint32_t)TMR6x) + { +#if defined(BSP_USING_PWM_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: +#ifdef BSP_USING_PWM_TMR6_1_A + GPIO_SetFunc(PWM_TMR6_1_A_PORT, PWM_TMR6_1_A_PIN, PWM_TMR6_1_A_PIN_FUNC); +#endif +#ifdef BSP_USING_PWM_TMR6_1_B + GPIO_SetFunc(PWM_TMR6_1_B_PORT, PWM_TMR6_1_B_PIN, PWM_TMR6_1_B_PIN_FUNC); +#endif + break; +#endif + + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif +#endif + +#if defined(BSP_USING_INPUT_CAPTURE) +rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)tmr_instance) + { +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) + case (rt_uint32_t)CM_TMR6_1: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) + case (rt_uint32_t)CM_TMR6_2: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) + case (rt_uint32_t)CM_TMR6_3: + GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC); + break; +#endif + default: + result = -RT_ERROR; + break; + } + return result; +} +#endif + +#if defined(BSP_USING_SDRAM) +rt_err_t rt_hw_board_sdram_init(void) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + /* DMC_CKE */ + (void)GPIO_Init(SDRAM_CKE_PORT, SDRAM_CKE_PIN, &stcGpioInit); + /* DMC_CLK */ + (void)GPIO_Init(SDRAM_CLK_PORT, SDRAM_CLK_PIN, &stcGpioInit); + /* DMC_LDQM && DMC_UDQM */ + (void)GPIO_Init(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, &stcGpioInit); + /* DMC_BA[0:1] */ + (void)GPIO_Init(SDRAM_BA0_PORT, SDRAM_BA0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_BA1_PORT, SDRAM_BA1_PIN, &stcGpioInit); + /* DMC_CAS && DMC_RAS */ + (void)GPIO_Init(SDRAM_CAS_PORT, SDRAM_CAS_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_RAS_PORT, SDRAM_RAS_PIN, &stcGpioInit); + /* DMC_WE */ + (void)GPIO_Init(SDRAM_WE_PORT, SDRAM_WE_PIN, &stcGpioInit); + /* DMC_DATA[0:15] */ + (void)GPIO_Init(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, &stcGpioInit); + /* DMC_ADD[0:11]*/ + (void)GPIO_Init(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, &stcGpioInit); + (void)GPIO_Init(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* DMC_CKE */ + GPIO_SetFunc(SDRAM_CKE_PORT, SDRAM_CKE_PIN, SDRAM_CKE_FUNC); + /* DMC_CLK */ + GPIO_SetFunc(SDRAM_CLK_PORT, SDRAM_CLK_PIN, SDRAM_CLK_FUNC); + /* DMC_LDQM && DMC_UDQM */ + GPIO_SetFunc(SDRAM_DQM0_PORT, SDRAM_DQM0_PIN, SDRAM_DQM0_FUNC); + GPIO_SetFunc(SDRAM_DQM1_PORT, SDRAM_DQM1_PIN, SDRAM_DQM1_FUNC); + /* DMC_BA[0:1] */ + GPIO_SetFunc(SDRAM_BA0_PORT, SDRAM_BA0_PIN, SDRAM_BA0_FUNC); + GPIO_SetFunc(SDRAM_BA1_PORT, SDRAM_BA1_PIN, SDRAM_BA1_FUNC); + /* DMC_CS */ + GPIO_SetFunc(SDRAM_CS_PORT, SDRAM_CS_PIN, SDRAM_CS_FUNC); + /* DMC_CAS && DMC_RAS */ + GPIO_SetFunc(SDRAM_CAS_PORT, SDRAM_CAS_PIN, SDRAM_CAS_FUNC); + GPIO_SetFunc(SDRAM_RAS_PORT, SDRAM_RAS_PIN, SDRAM_RAS_FUNC); + /* DMC_WE */ + GPIO_SetFunc(SDRAM_WE_PORT, SDRAM_WE_PIN, SDRAM_WE_FUNC); + /* DMC_DATA[0:15] */ + GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); + GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); + GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); + GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); + GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); + GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); + GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); + GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); + GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); + GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); + GPIO_SetFunc(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, SDRAM_DATA10_FUNC); + GPIO_SetFunc(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, SDRAM_DATA11_FUNC); + GPIO_SetFunc(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, SDRAM_DATA12_FUNC); + GPIO_SetFunc(SDRAM_DATA13_PORT, SDRAM_DATA13_PIN, SDRAM_DATA13_FUNC); + GPIO_SetFunc(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, SDRAM_DATA14_FUNC); + GPIO_SetFunc(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, SDRAM_DATA15_FUNC); + /* DMC_ADD[0:11]*/ + GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); + GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); + GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); + GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); + GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); + GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); + GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); + GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); + GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); + GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); + GPIO_SetFunc(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, SDRAM_ADD10_FUNC); + GPIO_SetFunc(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, SDRAM_ADD11_FUNC); + + return result; +} +#endif + +#ifdef RT_USING_PM +void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode) +{ + switch (run_mode) + { + case PM_RUN_MODE_HIGH_SPEED: + case PM_RUN_MODE_NORMAL_SPEED: + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_PLL); + break; + + case PM_RUN_MODE_LOW_SPEED: + /* Ensure that system clock less than 8M */ + CLK_SetSysClockSrc(CLK_SYSCLK_SRC_XTAL); + + default: + break; + } +} +#endif + +#if defined(BSP_USING_USBFS) +rt_err_t rt_hw_usbfs_board_init(void) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); +#if defined(BSP_USING_USBD_FS) + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ +#endif +#if defined(BSP_USING_USBH_FS) + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ +#endif + return RT_EOK; +} +#endif + +#if defined(BSP_USING_USBHS) +rt_err_t rt_hw_usbhs_board_init(void) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + +#if defined(BSP_USING_USBHS_PHY_EMBED) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); +#if defined(BSP_USING_USBD_HS) + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); +#endif +#if defined(BSP_USING_USBH_HS) + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ +#endif +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + + return RT_EOK; +} +#endif + +#if defined(RT_USING_CHERRYUSB) +rt_err_t rt_hw_usbfs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBF_DM_PORT, USBF_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBF_DP_PORT, USBF_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBF_VBUS_PORT, USBF_VBUS_PIN, USBF_VBUS_FUNC); /* VBUS */ + } + else + { + GPIO_SetFunc(USBF_DRVVBUS_PORT, USBF_DRVVBUS_PIN, USBF_DRVVBUS_FUNC); /* DRV VBUS */ + } + return RT_EOK; +} + +rt_err_t rt_hw_usbhs_board_init(uint8_t devmode) +{ + stc_gpio_init_t stcGpioCfg; + (void)GPIO_StructInit(&stcGpioCfg); + +#if !defined(CONFIG_USB_HS) + /* USBHS work in embedded PHY */ + stcGpioCfg.u16PinAttr = PIN_ATTR_ANALOG; + (void)GPIO_Init(USBH_DM_PORT, USBH_DM_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_DP_PORT, USBH_DP_PIN, &stcGpioCfg); + if (0U != devmode) + { + GPIO_SetFunc(USBH_VBUS_PORT, USBH_VBUS_PIN, USBH_VBUS_FUNC); + } + else + { + GPIO_OutputCmd(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN, ENABLE); + GPIO_SetPins(USBH_DRVVBUS_PORT, USBH_DRVVBUS_PIN); /* DRV VBUS with GPIO funciton */ + } +#else + /* Reset 3300 */ + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_SET); + TCA9539_ConfigPin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_DIR_OUT); + + (void)GPIO_StructInit(&stcGpioCfg); + /* High drive capability */ + stcGpioCfg.u16PinDrv = PIN_HIGH_DRV; + (void)GPIO_Init(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, &stcGpioCfg); + (void)GPIO_Init(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, &stcGpioCfg); + + GPIO_SetFunc(USBH_ULPI_CLK_PORT, USBH_ULPI_CLK_PIN, USBH_ULPI_CLK_FUNC); + GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); + GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); + GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + + TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); +#endif + + return RT_EOK; +} +#endif + + +#if defined(BSP_USING_QSPI) +rt_err_t rt_hw_qspi_board_init(void) +{ + stc_gpio_init_t stcGpioInit; + + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; +#ifndef BSP_QSPI_USING_SOFT_CS + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); +#endif + (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, &stcGpioInit); + (void)GPIO_Init(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, QSPI_FLASH_SCK_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, QSPI_FLASH_IO0_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO1_PORT, QSPI_FLASH_IO1_PIN, QSPI_FLASH_IO1_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO2_PORT, QSPI_FLASH_IO2_PIN, QSPI_FLASH_IO2_FUNC); + GPIO_SetFunc(QSPI_FLASH_IO3_PORT, QSPI_FLASH_IO3_PIN, QSPI_FLASH_IO3_FUNC); + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmra_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_A_PORT, PULSE_ENCODER_TMRA_1_A_PIN, PULSE_ENCODER_TMRA_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMRA_1_B_PORT, PULSE_ENCODER_TMRA_1_B_PIN, PULSE_ENCODER_TMRA_1_B_PIN_FUNC); +#endif + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void) +{ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_A_PORT, PULSE_ENCODER_TMR6_1_A_PIN, PULSE_ENCODER_TMR6_1_A_PIN_FUNC); + GPIO_SetFunc(PULSE_ENCODER_TMR6_1_B_PORT, PULSE_ENCODER_TMR6_1_B_PIN, PULSE_ENCODER_TMR6_1_B_PIN_FUNC); +#endif + + return RT_EOK; +} +#endif + +#if defined(BSP_USING_NAND) +rt_err_t rt_hw_board_nand_init(void) +{ + rt_err_t result = RT_EOK; + stc_gpio_init_t stcGpioInit; + + /************************* Set pin drive capacity *************************/ + (void)GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinDrv = PIN_HIGH_DRV; + + /* NFC_CE */ + (void)GPIO_Init(NAND_CE_PORT, NAND_CE_PIN, &stcGpioInit); + /* NFC_RE */ + (void)GPIO_Init(NAND_RE_PORT, NAND_RE_PIN, &stcGpioInit); + /* NFC_WE */ + (void)GPIO_Init(NAND_WE_PORT, NAND_WE_PIN, &stcGpioInit); + /* NFC_CLE */ + (void)GPIO_Init(NAND_CLE_PORT, NAND_CLE_PIN, &stcGpioInit); + /* NFC_ALE */ + (void)GPIO_Init(NAND_ALE_PORT, NAND_ALE_PIN, &stcGpioInit); + /* NFC_WP */ + (void)GPIO_Init(NAND_WP_PORT, NAND_WP_PIN, &stcGpioInit); + GPIO_SetPins(NAND_WP_PORT, NAND_WP_PIN); + + /* NFC_DATA[0:7] */ + (void)GPIO_Init(NAND_DATA0_PORT, NAND_DATA0_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA1_PORT, NAND_DATA1_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA2_PORT, NAND_DATA2_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA3_PORT, NAND_DATA3_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA4_PORT, NAND_DATA4_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA5_PORT, NAND_DATA5_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA6_PORT, NAND_DATA6_PIN, &stcGpioInit); + (void)GPIO_Init(NAND_DATA7_PORT, NAND_DATA7_PIN, &stcGpioInit); + /* NFC_RB */ + (void)GPIO_Init(NAND_RB_PORT, NAND_RB_PIN, &stcGpioInit); + + /************************** Set EXMC pin function *************************/ + /* NFC_CE */ + GPIO_SetFunc(NAND_CE_PORT, NAND_CE_PIN, NAND_CE_FUNC); + /* NFC_RE */ + GPIO_SetFunc(NAND_RE_PORT, NAND_RE_PIN, NAND_RE_FUNC); + /* NFC_WE */ + GPIO_SetFunc(NAND_WE_PORT, NAND_WE_PIN, NAND_WE_FUNC); + /* NFC_CLE */ + GPIO_SetFunc(NAND_CLE_PORT, NAND_CLE_PIN, NAND_CLE_FUNC); + /* NFC_ALE */ + GPIO_SetFunc(NAND_ALE_PORT, NAND_ALE_PIN, NAND_ALE_FUNC); + /* NFC_WP */ + GPIO_SetFunc(NAND_WP_PORT, NAND_WP_PIN, NAND_WP_FUNC); + /* NFC_RB */ + GPIO_SetFunc(NAND_RB_PORT, NAND_RB_PIN, NAND_RB_FUNC); + /* NFC_DATA[0:7] */ + GPIO_SetFunc(NAND_DATA0_PORT, NAND_DATA0_PIN, NAND_DATA0_FUNC); + GPIO_SetFunc(NAND_DATA1_PORT, NAND_DATA1_PIN, NAND_DATA1_FUNC); + GPIO_SetFunc(NAND_DATA2_PORT, NAND_DATA2_PIN, NAND_DATA2_FUNC); + GPIO_SetFunc(NAND_DATA3_PORT, NAND_DATA3_PIN, NAND_DATA3_FUNC); + GPIO_SetFunc(NAND_DATA4_PORT, NAND_DATA4_PIN, NAND_DATA4_FUNC); + GPIO_SetFunc(NAND_DATA5_PORT, NAND_DATA5_PIN, NAND_DATA5_FUNC); + GPIO_SetFunc(NAND_DATA6_PORT, NAND_DATA6_PIN, NAND_DATA6_FUNC); + GPIO_SetFunc(NAND_DATA7_PORT, NAND_DATA7_PIN, NAND_DATA7_FUNC); + + return result; +} +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.h new file mode 100644 index 00000000000..76176341773 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/board_config.h @@ -0,0 +1,704 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ll.h" +#include "drv_config.h" +#if defined(RT_USING_CHERRYUSB) +#include "usb_config.h" +#endif + +/************************* XTAL port **********************/ +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_IN_PIN (GPIO_PIN_01) +#define XTAL_OUT_PIN (GPIO_PIN_00) + +/************************ USART port **********************/ +#if defined(BSP_USING_UART1) +#define USART1_RX_PORT (GPIO_PORT_H) +#define USART1_RX_PIN (GPIO_PIN_13) +#define USART1_RX_FUNC (GPIO_FUNC_33) + +#define USART1_TX_PORT (GPIO_PORT_H) +#define USART1_TX_PIN (GPIO_PIN_15) +#define USART1_TX_FUNC (GPIO_FUNC_32) +#endif + +#if defined(BSP_USING_UART6) +#define USART6_RX_PORT (GPIO_PORT_H) +#define USART6_RX_PIN (GPIO_PIN_06) +#define USART6_RX_FUNC (GPIO_FUNC_37) + +#define USART6_TX_PORT (GPIO_PORT_E) +#define USART6_TX_PIN (GPIO_PIN_06) +#define USART6_TX_FUNC (GPIO_FUNC_36) +#endif + +/************************ I2C port **********************/ +#if defined(BSP_USING_I2C1) +#define I2C1_SDA_PORT (GPIO_PORT_F) +#define I2C1_SDA_PIN (GPIO_PIN_10) +#define I2C1_SDA_FUNC (GPIO_FUNC_48) + +#define I2C1_SCL_PORT (GPIO_PORT_D) +#define I2C1_SCL_PIN (GPIO_PIN_03) +#define I2C1_SCL_FUNC (GPIO_FUNC_49) +#endif + +/*********** ADC configure *********/ +#if defined(BSP_USING_ADC1) +#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */ +#define ADC1_CH_PIN (GPIO_PIN_00) +#endif + +#if defined(BSP_USING_ADC2) +#define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */ +#define ADC2_CH_PIN (GPIO_PIN_01) +#endif + +#if defined(BSP_USING_ADC3) +#define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */ +#define ADC3_CH_PIN (GPIO_PIN_02) +#endif + +/*********** DAC configure *********/ +#if defined(BSP_USING_DAC1) +#define DAC1_CH1_PORT (GPIO_PORT_A) +#define DAC1_CH1_PIN (GPIO_PIN_04) +#define DAC1_CH2_PORT (GPIO_PORT_A) +#define DAC1_CH2_PIN (GPIO_PIN_05) +#endif + +#if defined(BSP_USING_DAC2) +#define DAC2_CH1_PORT (GPIO_PORT_C) +#define DAC2_CH1_PIN (GPIO_PIN_04) +#define DAC2_CH2_PORT (GPIO_PORT_C) +#define DAC2_CH2_PIN (GPIO_PIN_05) +#endif + +/*********** CAN configure *********/ +#if defined(BSP_USING_CAN1) +#define CAN1_TX_PORT (GPIO_PORT_D) +#define CAN1_TX_PIN (GPIO_PIN_05) +#define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) + +#define CAN1_RX_PORT (GPIO_PORT_D) +#define CAN1_RX_PIN (GPIO_PIN_04) +#define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) +#endif + +#if defined(BSP_USING_CAN2) +#define CAN2_TX_PORT (GPIO_PORT_D) +#define CAN2_TX_PIN (GPIO_PIN_07) +#define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) + +#define CAN2_RX_PORT (GPIO_PORT_D) +#define CAN2_RX_PIN (GPIO_PIN_06) +#define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) +#endif + +/************************* SPI port ***********************/ +#if defined(BSP_USING_SPI1) +#define SPI1_CS_PORT (GPIO_PORT_C) +#define SPI1_CS_PIN (GPIO_PIN_07) + +#define SPI1_SCK_PORT (GPIO_PORT_C) +#define SPI1_SCK_PIN (GPIO_PIN_06) +#define SPI1_SCK_FUNC (GPIO_FUNC_40) + +#define SPI1_MOSI_PORT (GPIO_PORT_B) +#define SPI1_MOSI_PIN (GPIO_PIN_13) +#define SPI1_MOSI_FUNC (GPIO_FUNC_41) + +#define SPI1_MISO_PORT (GPIO_PORT_B) +#define SPI1_MISO_PIN (GPIO_PIN_12) +#define SPI1_MISO_FUNC (GPIO_FUNC_42) + +#define SPI1_WP_PORT (GPIO_PORT_B) +#define SPI1_WP_PIN (GPIO_PIN_10) + +#define SPI1_HOLD_PORT (GPIO_PORT_B) +#define SPI1_HOLD_PIN (GPIO_PIN_02) +#endif + +/************************* ETH port ***********************/ + +#if defined(BSP_USING_ETH) +#if defined(ETH_INTERFACE_USING_RMII) +#define ETH_SMI_MDIO_PORT (GPIO_PORT_A) +#define ETH_SMI_MDIO_PIN (GPIO_PIN_02) +#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + +#define ETH_SMI_MDC_PORT (GPIO_PORT_C) +#define ETH_SMI_MDC_PIN (GPIO_PIN_01) +#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) +#define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) +#define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TXD0_PORT (GPIO_PORT_G) +#define ETH_RMII_TXD0_PIN (GPIO_PIN_13) +#define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TXD1_PORT (GPIO_PORT_G) +#define ETH_RMII_TXD1_PIN (GPIO_PIN_14) +#define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) +#define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) +#define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) +#define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) +#define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_RXD0_PORT (GPIO_PORT_C) +#define ETH_RMII_RXD0_PIN (GPIO_PIN_04) +#define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_RXD1_PORT (GPIO_PORT_C) +#define ETH_RMII_RXD1_PIN (GPIO_PIN_05) +#define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) +#else +#define ETH_SMI_MDIO_PORT (GPIO_PORT_A) +#define ETH_SMI_MDIO_PIN (GPIO_PIN_02) +#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + +#define ETH_SMI_MDC_PORT (GPIO_PORT_C) +#define ETH_SMI_MDC_PIN (GPIO_PIN_01) +#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TX_CLK_PORT (GPIO_PORT_B) +#define ETH_MII_TX_CLK_PIN (GPIO_PIN_06) +#define ETH_MII_TX_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TX_EN_PORT (GPIO_PORT_G) +#define ETH_MII_TX_EN_PIN (GPIO_PIN_11) +#define ETH_MII_TX_EN_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD0_PORT (GPIO_PORT_G) +#define ETH_MII_TXD0_PIN (GPIO_PIN_13) +#define ETH_MII_TXD0_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD1_PORT (GPIO_PORT_G) +#define ETH_MII_TXD1_PIN (GPIO_PIN_14) +#define ETH_MII_TXD1_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD2_PORT (GPIO_PORT_B) +#define ETH_MII_TXD2_PIN (GPIO_PIN_09) +#define ETH_MII_TXD2_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD3_PORT (GPIO_PORT_B) +#define ETH_MII_TXD3_PIN (GPIO_PIN_08) +#define ETH_MII_TXD3_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_CLK_PORT (GPIO_PORT_A) +#define ETH_MII_RX_CLK_PIN (GPIO_PIN_01) +#define ETH_MII_RX_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_DV_PORT (GPIO_PORT_A) +#define ETH_MII_RX_DV_PIN (GPIO_PIN_07) +#define ETH_MII_RX_DV_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD0_PORT (GPIO_PORT_C) +#define ETH_MII_RXD0_PIN (GPIO_PIN_04) +#define ETH_MII_RXD0_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD1_PORT (GPIO_PORT_C) +#define ETH_MII_RXD1_PIN (GPIO_PIN_05) +#define ETH_MII_RXD1_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD2_PORT (GPIO_PORT_B) +#define ETH_MII_RXD2_PIN (GPIO_PIN_00) +#define ETH_MII_RXD2_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD3_PORT (GPIO_PORT_B) +#define ETH_MII_RXD3_PIN (GPIO_PIN_01) +#define ETH_MII_RXD3_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_ER_PORT (GPIO_PORT_I) +#define ETH_MII_RX_ER_PIN (GPIO_PIN_10) +#define ETH_MII_RX_ER_FUNC (GPIO_FUNC_11) + +#define ETH_MII_CRS_PORT (GPIO_PORT_H) +#define ETH_MII_CRS_PIN (GPIO_PIN_02) +#define ETH_MII_CRS_FUNC (GPIO_FUNC_11) + +#define ETH_MII_COL_PORT (GPIO_PORT_H) +#define ETH_MII_COL_PIN (GPIO_PIN_03) +#define ETH_MII_COL_FUNC (GPIO_FUNC_11) +#endif +#endif + +/************************ NAND port **********************/ +#if defined(BSP_USING_NAND) +#define NAND_CE_PORT (GPIO_PORT_C) /* PC02 - EXMC_CE0 */ +#define NAND_CE_PIN (GPIO_PIN_02) +#define NAND_CE_FUNC (GPIO_FUNC_12) + +#define NAND_RE_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ +#define NAND_RE_PIN (GPIO_PIN_11) +#define NAND_RE_FUNC (GPIO_FUNC_12) + +#define NAND_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ +#define NAND_WE_PIN (GPIO_PIN_00) +#define NAND_WE_FUNC (GPIO_FUNC_12) + +#define NAND_CLE_PORT (GPIO_PORT_I) /* PI12 - EXMC_CLE */ +#define NAND_CLE_PIN (GPIO_PIN_12) +#define NAND_CLE_FUNC (GPIO_FUNC_12) + +#define NAND_ALE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ +#define NAND_ALE_PIN (GPIO_PIN_03) +#define NAND_ALE_FUNC (GPIO_FUNC_12) + +#define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ +#define NAND_WP_PIN (GPIO_PIN_15) +#define NAND_WP_FUNC (GPIO_FUNC_12) + +#define NAND_RB_PORT (GPIO_PORT_G) /* PG06 - EXMC_RB0 */ +#define NAND_RB_PIN (GPIO_PIN_06) +#define NAND_RB_FUNC (GPIO_FUNC_12) + +#define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ +#define NAND_DATA0_PIN (GPIO_PIN_14) +#define NAND_DATA0_FUNC (GPIO_FUNC_12) +#define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ +#define NAND_DATA1_PIN (GPIO_PIN_15) +#define NAND_DATA1_FUNC (GPIO_FUNC_12) +#define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ +#define NAND_DATA2_PIN (GPIO_PIN_00) +#define NAND_DATA2_FUNC (GPIO_FUNC_12) +#define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ +#define NAND_DATA3_PIN (GPIO_PIN_01) +#define NAND_DATA3_FUNC (GPIO_FUNC_12) +#define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ +#define NAND_DATA4_PIN (GPIO_PIN_07) +#define NAND_DATA4_FUNC (GPIO_FUNC_12) +#define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ +#define NAND_DATA5_PIN (GPIO_PIN_08) +#define NAND_DATA5_FUNC (GPIO_FUNC_12) +#define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ +#define NAND_DATA6_PIN (GPIO_PIN_09) +#define NAND_DATA6_FUNC (GPIO_FUNC_12) +#define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ +#define NAND_DATA7_PIN (GPIO_PIN_10) +#define NAND_DATA7_FUNC (GPIO_FUNC_12) +#endif + +/************************ SDIOC port **********************/ +#if defined(BSP_USING_SDIO1) +#define SDIOC1_CK_PORT (GPIO_PORT_C) +#define SDIOC1_CK_PIN (GPIO_PIN_12) +#define SDIOC1_CK_FUNC (GPIO_FUNC_9) + +#define SDIOC1_CMD_PORT (GPIO_PORT_D) +#define SDIOC1_CMD_PIN (GPIO_PIN_02) +#define SDIOC1_CMD_FUNC (GPIO_FUNC_9) + +#define SDIOC1_D0_PORT (GPIO_PORT_B) +#define SDIOC1_D0_PIN (GPIO_PIN_07) +#define SDIOC1_D0_FUNC (GPIO_FUNC_9) + +#define SDIOC1_D1_PORT (GPIO_PORT_A) +#define SDIOC1_D1_PIN (GPIO_PIN_08) +#define SDIOC1_D1_FUNC (GPIO_FUNC_9) + +#define SDIOC1_D2_PORT (GPIO_PORT_C) +#define SDIOC1_D2_PIN (GPIO_PIN_10) +#define SDIOC1_D2_FUNC (GPIO_FUNC_9) + +#define SDIOC1_D3_PORT (GPIO_PORT_B) +#define SDIOC1_D3_PIN (GPIO_PIN_05) +#define SDIOC1_D3_FUNC (GPIO_FUNC_9) +#endif + +/************************ SDRAM port **********************/ +#if defined(BSP_USING_SDRAM) +#define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ +#define SDRAM_CKE_PIN (GPIO_PIN_03) +#define SDRAM_CKE_FUNC (GPIO_FUNC_12) + +#define SDRAM_CLK_PORT (GPIO_PORT_G) /* PD03 - EXMC_CLK */ +#define SDRAM_CLK_PIN (GPIO_PIN_08) +#define SDRAM_CLK_FUNC (GPIO_FUNC_12) + +#define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ +#define SDRAM_DQM0_PIN (GPIO_PIN_00) +#define SDRAM_DQM0_FUNC (GPIO_FUNC_12) +#define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ +#define SDRAM_DQM1_PIN (GPIO_PIN_01) +#define SDRAM_DQM1_FUNC (GPIO_FUNC_12) + +#define SDRAM_BA0_PORT (GPIO_PORT_D) /* PD11 - EXMC_ADD16 */ +#define SDRAM_BA0_PIN (GPIO_PIN_11) +#define SDRAM_BA0_FUNC (GPIO_FUNC_12) +#define SDRAM_BA1_PORT (GPIO_PORT_D) /* PD12 - EXMC_ADD17 */ +#define SDRAM_BA1_PIN (GPIO_PIN_12) +#define SDRAM_BA1_FUNC (GPIO_FUNC_12) + +#define SDRAM_CS_PORT (GPIO_PORT_G) /* PG09 - EXMC_CE1 */ +#define SDRAM_CS_PIN (GPIO_PIN_09) +#define SDRAM_CS_FUNC (GPIO_FUNC_12) + +#define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ +#define SDRAM_RAS_PIN (GPIO_PIN_11) +#define SDRAM_RAS_FUNC (GPIO_FUNC_12) + +#define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ +#define SDRAM_CAS_PIN (GPIO_PIN_15) +#define SDRAM_CAS_FUNC (GPIO_FUNC_12) + +#define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ +#define SDRAM_WE_PIN (GPIO_PIN_00) +#define SDRAM_WE_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ +#define SDRAM_ADD0_PIN (GPIO_PIN_00) +#define SDRAM_ADD0_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ +#define SDRAM_ADD1_PIN (GPIO_PIN_01) +#define SDRAM_ADD1_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ +#define SDRAM_ADD2_PIN (GPIO_PIN_02) +#define SDRAM_ADD2_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ +#define SDRAM_ADD3_PIN (GPIO_PIN_03) +#define SDRAM_ADD3_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ +#define SDRAM_ADD4_PIN (GPIO_PIN_04) +#define SDRAM_ADD4_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ +#define SDRAM_ADD5_PIN (GPIO_PIN_05) +#define SDRAM_ADD5_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ +#define SDRAM_ADD6_PIN (GPIO_PIN_12) +#define SDRAM_ADD6_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ +#define SDRAM_ADD7_PIN (GPIO_PIN_13) +#define SDRAM_ADD7_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ +#define SDRAM_ADD8_PIN (GPIO_PIN_14) +#define SDRAM_ADD8_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ +#define SDRAM_ADD9_PIN (GPIO_PIN_15) +#define SDRAM_ADD9_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ +#define SDRAM_ADD10_PIN (GPIO_PIN_00) +#define SDRAM_ADD10_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ +#define SDRAM_ADD11_PIN (GPIO_PIN_01) +#define SDRAM_ADD11_FUNC (GPIO_FUNC_12) + +#define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ +#define SDRAM_DATA0_PIN (GPIO_PIN_14) +#define SDRAM_DATA0_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ +#define SDRAM_DATA1_PIN (GPIO_PIN_15) +#define SDRAM_DATA1_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ +#define SDRAM_DATA2_PIN (GPIO_PIN_00) +#define SDRAM_DATA2_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ +#define SDRAM_DATA3_PIN (GPIO_PIN_01) +#define SDRAM_DATA3_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ +#define SDRAM_DATA4_PIN (GPIO_PIN_07) +#define SDRAM_DATA4_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ +#define SDRAM_DATA5_PIN (GPIO_PIN_08) +#define SDRAM_DATA5_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ +#define SDRAM_DATA6_PIN (GPIO_PIN_09) +#define SDRAM_DATA6_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ +#define SDRAM_DATA7_PIN (GPIO_PIN_10) +#define SDRAM_DATA7_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ +#define SDRAM_DATA8_PIN (GPIO_PIN_11) +#define SDRAM_DATA8_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ +#define SDRAM_DATA9_PIN (GPIO_PIN_12) +#define SDRAM_DATA9_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ +#define SDRAM_DATA10_PIN (GPIO_PIN_13) +#define SDRAM_DATA10_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ +#define SDRAM_DATA11_PIN (GPIO_PIN_14) +#define SDRAM_DATA11_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ +#define SDRAM_DATA12_PIN (GPIO_PIN_15) +#define SDRAM_DATA12_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ +#define SDRAM_DATA13_PIN (GPIO_PIN_08) +#define SDRAM_DATA13_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ +#define SDRAM_DATA14_PIN (GPIO_PIN_09) +#define SDRAM_DATA14_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ +#define SDRAM_DATA15_PIN (GPIO_PIN_10) +#define SDRAM_DATA15_FUNC (GPIO_FUNC_12) +#endif + +/************************ RTC/PM *****************************/ +#if defined(BSP_USING_RTC) || defined(RT_USING_PM) +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) +#define XTAL32_PORT (GPIO_PORT_C) +#define XTAL32_IN_PIN (GPIO_PIN_15) +#define XTAL32_OUT_PIN (GPIO_PIN_14) +#endif +#endif + +#if defined(RT_USING_PWM) + /*********** PWM_TMRA configure *********/ +#if defined(BSP_USING_PWM_TMRA_1) +#if defined(BSP_USING_PWM_TMRA_1_CH1) +#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) +#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH2) +#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) +#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH3) +#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) +#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH4) +#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) +#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) +#endif +#endif + + /*********** PWM_TMR4 configure *********/ +#if defined(BSP_USING_PWM_TMR4_1) +#if defined(BSP_USING_PWM_TMR4_1_OUH) +#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) +#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OUL) +#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) +#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVH) +#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) +#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVL) +#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) +#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWH) +#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) +#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWL) +#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) +#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) +#endif +#endif + + /*********** PWM_TMR6 configure *********/ +#if defined(BSP_USING_PWM_TMR6_1) +#if defined(BSP_USING_PWM_TMR6_1_A) +#define PWM_TMR6_1_A_PORT (GPIO_PORT_F) +#define PWM_TMR6_1_A_PIN (GPIO_PIN_13) +#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#endif +#if defined(BSP_USING_PWM_TMR6_1_B) +#define PWM_TMR6_1_B_PORT (GPIO_PORT_F) +#define PWM_TMR6_1_B_PIN (GPIO_PIN_14) +#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif +#endif + +#endif + +#if defined(BSP_USING_INPUT_CAPTURE) +#define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_B) +#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_09) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_E) +#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) +#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) +#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00) +#endif +#endif + +#if defined(RT_USING_CHERRYUSB) +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(BSP_USING_USBHS) || \ + defined(BSP_USING_USBHS_PHY_EMBED) || defined(BSP_USING_USBHS_PHY_EXTERN) || \ + defined(RT_USING_USB) +#error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" +#endif +#endif + +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) + /* USBFS Core*/ +#define USBF_DP_PORT (GPIO_PORT_A) +#define USBF_DP_PIN (GPIO_PIN_12) +#define USBF_DM_PORT (GPIO_PORT_A) +#define USBF_DM_PIN (GPIO_PIN_11) +#define USBF_VBUS_PORT (GPIO_PORT_A) +#define USBF_VBUS_PIN (GPIO_PIN_09) +#define USBF_VBUS_FUNC (GPIO_FUNC_10) +#define USBF_DRVVBUS_PORT (GPIO_PORT_C) +#define USBF_DRVVBUS_PIN (GPIO_PIN_09) +#define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) +#endif +#if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) + /* USBHS Core*/ +#if defined(BSP_USING_USBHS_PHY_EMBED) || (defined(RT_USING_CHERRYUSB) && !defined(CONFIG_USB_HS)) +#define USBH_DP_PORT (GPIO_PORT_B) +#define USBH_DP_PIN (GPIO_PIN_15) +#define USBH_DP_FUNC (GPIO_FUNC_10) +#define USBH_DM_PORT (GPIO_PORT_B) +#define USBH_DM_PIN (GPIO_PIN_14) +#define USBH_DM_FUNC (GPIO_FUNC_10) +#define USBH_VBUS_PORT (GPIO_PORT_B) +#define USBH_VBUS_PIN (GPIO_PIN_13) +#define USBH_VBUS_FUNC (GPIO_FUNC_12) +#define USBH_DRVVBUS_PORT (GPIO_PORT_B) +#define USBH_DRVVBUS_PIN (GPIO_PIN_11) +#define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) +#else + /* USBHS Core, external PHY */ +#define USBH_ULPI_CLK_PORT (GPIO_PORT_E) +#define USBH_ULPI_CLK_PIN (GPIO_PIN_12) +#define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_DIR_PORT (GPIO_PORT_C) +#define USBH_ULPI_DIR_PIN (GPIO_PIN_02) +#define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_NXT_PORT (GPIO_PORT_C) +#define USBH_ULPI_NXT_PIN (GPIO_PIN_03) +#define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_STP_PORT (GPIO_PORT_C) +#define USBH_ULPI_STP_PIN (GPIO_PIN_00) +#define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D0_PORT (GPIO_PORT_E) +#define USBH_ULPI_D0_PIN (GPIO_PIN_13) +#define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D1_PORT (GPIO_PORT_E) +#define USBH_ULPI_D1_PIN (GPIO_PIN_14) +#define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D2_PORT (GPIO_PORT_E) +#define USBH_ULPI_D2_PIN (GPIO_PIN_15) +#define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D3_PORT (GPIO_PORT_B) +#define USBH_ULPI_D3_PIN (GPIO_PIN_10) +#define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D4_PORT (GPIO_PORT_B) +#define USBH_ULPI_D4_PIN (GPIO_PIN_11) +#define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D5_PORT (GPIO_PORT_B) +#define USBH_ULPI_D5_PIN (GPIO_PIN_12) +#define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D6_PORT (GPIO_PORT_B) +#define USBH_ULPI_D6_PIN (GPIO_PIN_13) +#define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D7_PORT (GPIO_PORT_E) +#define USBH_ULPI_D7_PIN (GPIO_PIN_11) +#define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) + /* 3300 reset */ +#define USB_3300_RESET_PORT (EIO_PORT1) +#define USB_3300_RESET_PIN (EIO_USB3300_RST) +#endif +#endif +#endif + +#if defined(BSP_USING_QSPI) +#ifndef BSP_QSPI_USING_SOFT_CS + /* QSSN */ +#define QSPI_FLASH_CS_PORT (GPIO_PORT_C) +#define QSPI_FLASH_CS_PIN (GPIO_PIN_07) +#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) +#endif + /* QSCK */ +#define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) +#define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) +#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) + /* QSIO0 */ +#define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) +#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) + /* QSIO1 */ +#define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) +#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) + /* QSIO2 */ +#define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) +#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) + /* QSIO3 */ +#define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) +#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) +#endif + +/*********** TMRA_PULSE_ENCODER configure *********/ +#if defined(RT_USING_PULSE_ENCODER) +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) +#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#endif /* BSP_USING_TMRA_PULSE_ENCODER */ + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#endif /* RT_USING_PULSE_ENCODER */ + +#endif + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/adc_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/adc_config.h new file mode 100644 index 00000000000..bb03bb98d88 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/adc_config.h @@ -0,0 +1,150 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __ADC_CONFIG_H__ +#define __ADC_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_ADC1 +#ifndef ADC1_INIT_PARAMS +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC1_INIT_PARAMS */ + +#if defined(BSP_ADC1_USING_DMA) +#ifndef ADC1_EOCA_DMA_CONFIG +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC1_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC1_USING_DMA */ +#endif /* BSP_USING_ADC1 */ + +#ifdef BSP_USING_ADC2 +#ifndef ADC2_INIT_PARAMS +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC2_INIT_PARAMS */ + +#if defined(BSP_ADC2_USING_DMA) +#ifndef ADC2_EOCA_DMA_CONFIG +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC2_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC2_USING_DMA */ +#endif /* BSP_USING_ADC2 */ + +#ifdef BSP_USING_ADC3 +#ifndef ADC3_INIT_PARAMS +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ + } +#endif /* ADC3_INIT_PARAMS */ +#if defined(BSP_ADC3_USING_DMA) +#ifndef ADC3_EOCA_DMA_CONFIG +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ + } +#endif /* ADC3_EOCA_DMA_CONFIG */ +#endif /* BSP_ADC3_USING_DMA */ +#endif /* BSP_USING_ADC3 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __ADC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/can_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/can_config.h new file mode 100644 index 00000000000..4c18c1ed160 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/can_config.h @@ -0,0 +1,130 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __CAN_CONFIG_H__ +#define __CAN_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_CAN1 +#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN1_NAME ("can1") +#ifndef CAN1_INIT_PARAMS +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN1_INIT_PARAMS */ +#endif /* BSP_USING_CAN1 */ + +#ifdef BSP_USING_CAN2 +#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN2_NAME ("can2") +#ifndef CAN2_INIT_PARAMS +#define CAN2_INIT_PARAMS \ + { \ + .name = CAN2_NAME, \ + .single_trans_mode = RT_FALSE \ + } +#endif /* CAN2_INIT_PARAMS */ +#endif /* BSP_USING_CAN2 */ + +/* Bit time config + Restrictions: u32TimeSeg1 >= u32TimeSeg2 + 1, u32TimeSeg2 >= u32SJW. + + Baudrate = CANClock/(u32Prescaler*(u32TimeSeg1 + u32TimeSeg2)) + TQ = u32Prescaler / CANClock. + Bit time = (u32TimeSeg2 + u32TimeSeg2) x TQ. + + The following bit time configures are based on CAN Clock 40M +*/ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ + } + +#ifdef __cplusplus +} +#endif + +#endif /* __CAN_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dac_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dac_config.h new file mode 100644 index 00000000000..20017c130b8 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dac_config.h @@ -0,0 +1,62 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __DAC_CONFIG_H__ +#define __DAC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_DAC1 +#ifndef DAC1_INIT_PARAMS +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + } +#endif /* DAC1_INIT_PARAMS */ +#endif /* BSP_USING_DAC1 */ + +#ifdef BSP_USING_DAC2 +#ifndef DAC2_INIT_PARAMS +#define DAC2_INIT_PARAMS \ + { \ + .name = "dac2", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ + } +#endif /* DAC2_INIT_PARAMS */ +#endif /* BSP_USING_DAC2 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DAC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dma_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dma_config.h new file mode 100644 index 00000000000..d019a582ee1 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/dma_config.h @@ -0,0 +1,423 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __DMA_CONFIG_H__ +#define __DMA_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* DMA1 ch0 */ +#if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE) +#define SDIO1_RX_DMA_INSTANCE CM_DMA1 +#define SDIO1_RX_DMA_CHANNEL DMA_CH0 +#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#endif + +/* DMA1 ch1 */ +#if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE) +#define SDIO1_TX_DMA_INSTANCE CM_DMA1 +#define SDIO1_TX_DMA_CHANNEL DMA_CH1 +#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#endif + +/* DMA1 ch2 */ +#if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE) +#define SDIO2_RX_DMA_INSTANCE CM_DMA1 +#define SDIO2_RX_DMA_CHANNEL DMA_CH2 +#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#endif + +/* DMA1 ch3 */ +#if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE) +#define SDIO2_TX_DMA_INSTANCE CM_DMA1 +#define SDIO2_TX_DMA_CHANNEL DMA_CH3 +#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE) +#define QSPI_DMA_INSTANCE CM_DMA1 +#define QSPI_DMA_CHANNEL DMA_CH3 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) +#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 +#endif + +/* DMA1 ch4 */ +#if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH4 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) +#define I2C3_TX_DMA_INSTANCE CM_DMA1 +#define I2C3_TX_DMA_CHANNEL DMA_CH4 +#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 +#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) +#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 +#endif + +/* DMA1 ch5 */ +#if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH5 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) +#define I2C3_RX_DMA_INSTANCE CM_DMA1 +#define I2C3_RX_DMA_CHANNEL DMA_CH5 +#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 +#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) +#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 +#endif + +/* DMA1 ch6 */ +#if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) +#define SPI4_RX_DMA_INSTANCE CM_DMA1 +#define SPI4_RX_DMA_CHANNEL DMA_CH6 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 +#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE) +#define I2C4_TX_DMA_INSTANCE CM_DMA1 +#define I2C4_TX_DMA_CHANNEL DMA_CH6 +#define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6 +#define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#endif + +/* DMA1 ch7 */ +#if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) +#define SPI4_TX_DMA_INSTANCE CM_DMA1 +#define SPI4_TX_DMA_CHANNEL DMA_CH7 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 +#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE) +#define I2C4_RX_DMA_INSTANCE CM_DMA1 +#define I2C4_RX_DMA_CHANNEL DMA_CH7 +#define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7 +#define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#endif + +/* DMA1 ch8 */ +#if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) +#define SPI5_TX_DMA_INSTANCE CM_DMA1 +#define SPI5_TX_DMA_CHANNEL DMA_CH8 +#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 +#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 +#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM +#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO +#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 +#endif + +/* DMA1 ch9 */ +#if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) +#define SPI6_TX_DMA_INSTANCE CM_DMA1 +#define SPI6_TX_DMA_CHANNEL DMA_CH9 +#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 +#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 +#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM +#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO +#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 +#endif + +/* DMA2 ch0 */ +#if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE) +#define I2C5_TX_DMA_INSTANCE CM_DMA2 +#define I2C5_TX_DMA_CHANNEL DMA_CH0 +#define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0 +#define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#endif + +/* DMA2 ch1 */ +#if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#elif defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE) +#define I2C5_RX_DMA_INSTANCE CM_DMA2 +#define I2C5_RX_DMA_CHANNEL DMA_CH1 +#define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1 +#define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#endif + +/* DMA2 ch2 */ +#if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE) +#define I2C6_TX_DMA_INSTANCE CM_DMA2 +#define I2C6_TX_DMA_CHANNEL DMA_CH2 +#define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2 +#define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#endif + +/* DMA2 ch3 */ +#if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#elif defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE) +#define I2C6_RX_DMA_INSTANCE CM_DMA2 +#define I2C6_RX_DMA_CHANNEL DMA_CH3 +#define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3 +#define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#endif + +/* DMA2 ch4 */ +#if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) +#define UART6_RX_DMA_INSTANCE CM_DMA2 +#define UART6_RX_DMA_CHANNEL DMA_CH4 +#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#endif + +/* DMA2 ch5 */ +#if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) +#define UART6_TX_DMA_INSTANCE CM_DMA2 +#define UART6_TX_DMA_CHANNEL DMA_CH5 +#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#endif + +/* DMA2 ch6 */ +#if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) +#define UART7_RX_DMA_INSTANCE CM_DMA2 +#define UART7_RX_DMA_CHANNEL DMA_CH6 +#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 +#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM +#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO +#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 +#endif + +/* DMA2 ch7 */ +#if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) +#define UART7_TX_DMA_INSTANCE CM_DMA2 +#define UART7_TX_DMA_CHANNEL DMA_CH7 +#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 +#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM +#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO +#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 +#endif + + +#ifdef __cplusplus +} +#endif + + +#endif /* __DMA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/eth_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/eth_config.h new file mode 100644 index 00000000000..d09aecfa6de --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/eth_config.h @@ -0,0 +1,40 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __ETH_CONFIG_H__ +#define __ETH_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_ETH) + +#ifndef ETH_IRQ_CONFIG +#define ETH_IRQ_CONFIG \ + { \ + .irq_num = BSP_ETH_IRQ_NUM, \ + .irq_prio = BSP_ETH_IRQ_PRIO, \ + .int_src = INT_SRC_ETH_GLB_INT, \ + } +#endif /* ETH_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __ETH_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/gpio_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/gpio_config.h new file mode 100644 index 00000000000..1f1f7f516f5 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/gpio_config.h @@ -0,0 +1,175 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __GPIO_CONFIG_H__ +#define __GPIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(RT_USING_PIN) + +#ifndef EXTINT0_IRQ_CONFIG +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT1_IRQ_CONFIG +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ + } +#endif /* EXTINT1_IRQ_CONFIG */ + +#ifndef EXTINT2_IRQ_CONFIG +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ + } +#endif /* EXTINT2_IRQ_CONFIG */ + +#ifndef EXTINT3_IRQ_CONFIG +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ + } +#endif /* EXTINT3_IRQ_CONFIG */ + +#ifndef EXTINT4_IRQ_CONFIG +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ + } +#endif /* EXTINT4_IRQ_CONFIG */ + +#ifndef EXTINT5_IRQ_CONFIG +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ + } +#endif /* EXTINT5_IRQ_CONFIG */ + +#ifndef EXTINT6_IRQ_CONFIG +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ + } +#endif /* EXTINT6_IRQ_CONFIG */ + +#ifndef EXTINT7_IRQ_CONFIG +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ + } +#endif /* EXTINT7_IRQ_CONFIG */ + +#ifndef EXTINT8_IRQ_CONFIG +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ + } +#endif /* EXTINT8_IRQ_CONFIG */ + +#ifndef EXTINT9_IRQ_CONFIG +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ + } +#endif /* EXTINT9_IRQ_CONFIG */ + +#ifndef EXTINT10_IRQ_CONFIG +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ + } +#endif /* EXTINT10_IRQ_CONFIG */ + +#ifndef EXTINT11_IRQ_CONFIG +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ + } +#endif /* EXTINT11_IRQ_CONFIG */ + +#ifndef EXTINT12_IRQ_CONFIG +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ + } +#endif /* EXTINT12_IRQ_CONFIG */ + +#ifndef EXTINT13_IRQ_CONFIG +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ + } +#endif /* EXTINT13_IRQ_CONFIG */ + +#ifndef EXTINT14_IRQ_CONFIG +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ + } +#endif /* EXTINT14_IRQ_CONFIG */ + +#ifndef EXTINT15_IRQ_CONFIG +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ + } +#endif /* EXTINT15_IRQ_CONFIG */ + +#endif + + +#ifdef __cplusplus +} +#endif + +#endif /* __GPIO_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/i2c_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/i2c_config.h new file mode 100644 index 00000000000..0ea71117aa2 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/i2c_config.h @@ -0,0 +1,319 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __I2C_CONFIG_H__ +#define __I2C_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_I2C1) +#ifndef I2C1_CONFIG +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C1_CONFIG */ +#endif + +#if defined(BSP_I2C1_USING_DMA) +#ifndef I2C1_TX_DMA_CONFIG +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_TX_DMA_CONFIG */ + +#ifndef I2C1_RX_DMA_CONFIG +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C1_RX_DMA_CONFIG */ +#endif /* BSP_I2C1_USING_DMA */ + +#if defined(BSP_USING_I2C2) +#ifndef I2C2_CONFIG +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C2_CONFIG */ + +#if defined(BSP_I2C2_USING_DMA) +#ifndef I2C2_TX_DMA_CONFIG +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_TX_DMA_CONFIG */ + +#ifndef I2C2_RX_DMA_CONFIG +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C2_RX_DMA_CONFIG */ +#endif /* BSP_I2C2_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C3) +#ifndef I2C3_CONFIG +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C3_CONFIG */ + +#if defined(BSP_I2C3_USING_DMA) +#ifndef I2C3_TX_DMA_CONFIG +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_TX_DMA_CONFIG */ + +#ifndef I2C3_RX_DMA_CONFIG +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C3_RX_DMA_CONFIG */ +#endif /* BSP_I2C3_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C4) +#ifndef I2C4_CONFIG +#define I2C4_CONFIG \ + { \ + .name = "i2c4", \ + .Instance = CM_I2C4, \ + .clock = FCG1_PERIPH_I2C4, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C4_CONFIG */ + +#if defined(BSP_I2C4_USING_DMA) +#ifndef I2C4_TX_DMA_CONFIG +#define I2C4_TX_DMA_CONFIG \ + { \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + .clock = I2C4_TX_DMA_CLOCK, \ + .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_TEI, \ + .flag = I2C4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_TX_DMA_IRQn, \ + .irq_prio = I2C4_TX_DMA_INT_PRIO, \ + .int_src = I2C4_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C4_TX_DMA_CONFIG */ + +#ifndef I2C4_RX_DMA_CONFIG +#define I2C4_RX_DMA_CONFIG \ + { \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + .clock = I2C4_RX_DMA_CLOCK, \ + .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_RXI, \ + .flag = I2C4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_RX_DMA_IRQn, \ + .irq_prio = I2C4_RX_DMA_INT_PRIO, \ + .int_src = I2C4_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C4_RX_DMA_CONFIG */ +#endif /* BSP_I2C4_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C5) +#ifndef I2C5_CONFIG +#define I2C5_CONFIG \ + { \ + .name = "i2c5", \ + .Instance = CM_I2C5, \ + .clock = FCG1_PERIPH_I2C5, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C5_CONFIG */ + +#if defined(BSP_I2C5_USING_DMA) +#ifndef I2C5_TX_DMA_CONFIG +#define I2C5_TX_DMA_CONFIG \ + { \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .channel = I2C5_TX_DMA_CHANNEL, \ + .clock = I2C5_TX_DMA_CLOCK, \ + .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_TEI, \ + .flag = I2C5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_TX_DMA_IRQn, \ + .irq_prio = I2C5_TX_DMA_INT_PRIO, \ + .int_src = I2C5_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C5_TX_DMA_CONFIG */ + +#ifndef I2C5_RX_DMA_CONFIG +#define I2C5_RX_DMA_CONFIG \ + { \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .channel = I2C5_RX_DMA_CHANNEL, \ + .clock = I2C5_RX_DMA_CLOCK, \ + .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_RXI, \ + .flag = I2C5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_RX_DMA_IRQn, \ + .irq_prio = I2C5_RX_DMA_INT_PRIO, \ + .int_src = I2C5_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C5_RX_DMA_CONFIG */ +#endif /* BSP_I2C5_USING_DMA */ +#endif + +#if defined(BSP_USING_I2C6) +#ifndef I2C6_CONFIG +#define I2C6_CONFIG \ + { \ + .name = "i2c6", \ + .Instance = CM_I2C6, \ + .clock = FCG1_PERIPH_I2C6, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ + } +#endif /* I2C6_CONFIG */ + +#if defined(BSP_I2C6_USING_DMA) +#ifndef I2C6_TX_DMA_CONFIG +#define I2C6_TX_DMA_CONFIG \ + { \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .channel = I2C6_TX_DMA_CHANNEL, \ + .clock = I2C6_TX_DMA_CLOCK, \ + .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_TEI, \ + .flag = I2C6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_TX_DMA_IRQn, \ + .irq_prio = I2C6_TX_DMA_INT_PRIO, \ + .int_src = I2C6_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C6_TX_DMA_CONFIG */ + +#ifndef I2C6_RX_DMA_CONFIG +#define I2C6_RX_DMA_CONFIG \ + { \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .channel = I2C6_RX_DMA_CHANNEL, \ + .clock = I2C6_RX_DMA_CLOCK, \ + .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_RXI, \ + .flag = I2C6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_RX_DMA_IRQn, \ + .irq_prio = I2C6_RX_DMA_INT_PRIO, \ + .int_src = I2C6_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* I2C6_RX_DMA_CONFIG */ +#endif /* BSP_I2C6_USING_DMA */ +#endif + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/irq_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/irq_config.h new file mode 100644 index 00000000000..60cd84be1df --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/irq_config.h @@ -0,0 +1,518 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __IRQ_CONFIG_H__ +#define __IRQ_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA1 ch0 */ +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch1 */ +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch2 */ +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch3 */ +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch4 */ +#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch5 */ +#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch6 */ +#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch7 */ +#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch8 */ +#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn +#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA1 ch9 */ +#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn +#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +/* DMA2 ch0 */ +#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch1 */ +#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch2 */ +#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch3 */ +#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch4 */ +#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch5 */ +#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch6 */ +#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn +#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +/* DMA2 ch7 */ +#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn +#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_USING_ETH) +#define BSP_ETH_IRQ_NUM INT104_IRQn +#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART1) +#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT089_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT088_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART1_RX_USING_DMA) +#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT091_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT090_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART2_RX_USING_DMA) +#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT095_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT094_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT097_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT096_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn +#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RX_IRQ_NUM INT101_IRQn +#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_IRQ_NUM INT100_IRQn +#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn +#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RX_IRQ_NUM INT103_IRQn +#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_IRQ_NUM INT102_IRQn +#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART6_RX_USING_DMA) +#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn +#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn +#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RX_IRQ_NUM INT107_IRQn +#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_IRQ_NUM INT106_IRQn +#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT + +#if defined(BSP_UART7_RX_USING_DMA) +#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn +#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#elif defined(RT_USING_SERIAL_V2) +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#elif defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) +#define BSP_SPI1_ERR_IRQ_NUM INT009_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM INT016_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_SPI3) +#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI4) +#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn +#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI5) +#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn +#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_SPI6) +#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn +#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif + +#if defined(BSP_USING_UART8) +#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn +#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RX_IRQ_NUM INT109_IRQn +#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_IRQ_NUM INT108_IRQn +#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#if defined(RT_USING_SERIAL_V2) +#define BSP_UART8_TX_CPLT_IRQ_NUM INT001_IRQn +#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn +#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RX_IRQ_NUM INT110_IRQn +#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_TX_IRQ_NUM INT111_IRQn +#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn +#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RX_IRQ_NUM INT114_IRQn +#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_IRQ_NUM INT113_IRQn +#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_UART10 */ + +#if defined(BSP_USING_CAN1) +#define BSP_CAN1_IRQ_NUM INT092_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_CAN1 */ + +#if defined(BSP_USING_CAN2) +#define BSP_CAN2_IRQ_NUM INT093_IRQn +#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_CAN2 */ + +#if defined(BSP_USING_SDIO1) +#define BSP_SDIO1_IRQ_NUM INT004_IRQn +#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_SDIO1 */ + +#if defined(BSP_USING_SDIO2) +#define BSP_SDIO2_IRQ_NUM INT005_IRQn +#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_SDIO2 */ + +#if defined(RT_USING_ALARM) +#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* RT_USING_ALARM */ + + +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) +#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn +#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_USBFS */ + +#if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) +#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn +#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_USBHS */ + +#if defined(BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif /* BSP_USING_QSPI */ + +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_2) +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_3) +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_4) +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_5) +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_6) +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_7) +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_7 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_8) +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_8 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_9) +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM INT098_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM INT099_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_9 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_10) +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM INT100_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM INT101_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_10 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_11) +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_11 */ +#if defined(BSP_USING_PULSE_ENCODER_TMRA_12) +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMRA_12 */ + +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_2) +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_3) +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_4) +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM INT068_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM INT069_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_4 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_5) +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_5 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_6) +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_6 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_7) +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_7 */ +#if defined(BSP_USING_PULSE_ENCODER_TMR6_8) +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_PULSE_ENCODER_TMR6_8 */ + +#if defined(BSP_USING_TMRA_1) +#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_1 */ +#if defined(BSP_USING_TMRA_2) +#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_2 */ +#if defined(BSP_USING_TMRA_3) +#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_3 */ +#if defined(BSP_USING_TMRA_4) +#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_4 */ +#if defined(BSP_USING_TMRA_5) +#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_5 */ +#if defined(BSP_USING_TMRA_6) +#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn +#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_6 */ +#if defined(BSP_USING_TMRA_7) +#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn +#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_7 */ +#if defined(BSP_USING_TMRA_8) +#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn +#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_8 */ +#if defined(BSP_USING_TMRA_9) +#define BSP_USING_TMRA_9_IRQ_NUM INT098_IRQn +#define BSP_USING_TMRA_9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_9 */ +#if defined(BSP_USING_TMRA_10) +#define BSP_USING_TMRA_10_IRQ_NUM INT099_IRQn +#define BSP_USING_TMRA_10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_10 */ +#if defined(BSP_USING_TMRA_11) +#define BSP_USING_TMRA_11_IRQ_NUM INT100_IRQn +#define BSP_USING_TMRA_11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_11 */ +#if defined(BSP_USING_TMRA_12) +#define BSP_USING_TMRA_12_IRQ_NUM INT101_IRQn +#define BSP_USING_TMRA_12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#endif/* BSP_USING_TMRA_12 */ + +#if defined(BSP_USING_INPUT_CAPTURE) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IRQ_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pm_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pm_config.h new file mode 100644 index 00000000000..7fd6ac9d4e1 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pm_config.h @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + * 2026-06-24 CDT delete PM_TICKLESS_TIMER_ENABLE_MASK for unsupport pm tickless timer + */ + +#ifndef __PM_CONFIG_H__ +#define __PM_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PM +extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); + +/** + * @brief run mode config @ref pm_run_mode_config structure + */ +#ifndef PM_RUN_MODE_CFG +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ + } +#endif /* PM_RUN_MODE_CFG */ + +/** + * @brief sleep idle config @ref pm_sleep_mode_idle_config structure + */ +#ifndef PM_SLEEP_IDLE_CFG +#define PM_SLEEP_IDLE_CFG \ + { \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ + } +#endif /*PM_SLEEP_IDLE_CFG*/ + +/** + * @brief sleep deep config @ref pm_sleep_mode_deep_config structure + */ +#ifndef PM_SLEEP_DEEP_CFG +#define PM_SLEEP_DEEP_CFG \ + { \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ + } +#endif /*PM_SLEEP_DEEP_CFG*/ + +/** + * @brief sleep standby config @ref pm_sleep_mode_standby_config structure + */ +#ifndef PM_SLEEP_STANDBY_CFG +#define PM_SLEEP_STANDBY_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } +#endif /*PM_SLEEP_STANDBY_CFG*/ + +/** + * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure + */ +#ifndef PM_SLEEP_SHUTDOWN_CFG +#define PM_SLEEP_SHUTDOWN_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } +#endif /*PM_SLEEP_SHUTDOWN_CFG*/ + +#endif /* BSP_USING_PM */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PM_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pulse_encoder_config.h new file mode 100644 index 00000000000..559d4f693c2 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pulse_encoder_config.h @@ -0,0 +1,504 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __PULSE_ENCODER_CONFIG_H__ +#define __PULSE_ENCODER_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(RT_USING_PULSE_ENCODER) + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_1 +#ifndef PULSE_ENCODER_TMRA_1_CONFIG +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ + } +#endif /* PULSE_ENCODER_TMRA_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_2 +#ifndef PULSE_ENCODER_TMRA_2_CONFIG +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ + } +#endif /* PULSE_ENCODER_TMRA_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_3 +#ifndef PULSE_ENCODER_TMRA_3_CONFIG +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ + } +#endif /* PULSE_ENCODER_TMRA_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_4 +#ifndef PULSE_ENCODER_TMRA_4_CONFIG +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ + } +#endif /* PULSE_ENCODER_TMRA_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_5 +#ifndef PULSE_ENCODER_TMRA_5_CONFIG +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ + } +#endif /* PULSE_ENCODER_TMRA_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_6 +#ifndef PULSE_ENCODER_TMRA_6_CONFIG +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ + } +#endif /* PULSE_ENCODER_TMRA_6_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_7 +#ifndef PULSE_ENCODER_TMRA_7_CONFIG +#define PULSE_ENCODER_TMRA_7_CONFIG \ + { \ + .tmr_handler = CM_TMRA_7, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_7, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a7" \ + } +#endif /* PULSE_ENCODER_TMRA_7_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_8 +#ifndef PULSE_ENCODER_TMRA_8_CONFIG +#define PULSE_ENCODER_TMRA_8_CONFIG \ + { \ + .tmr_handler = CM_TMRA_8, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_8, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a8" \ + } +#endif /* PULSE_ENCODER_TMRA_8_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_9 +#ifndef PULSE_ENCODER_TMRA_9_CONFIG +#define PULSE_ENCODER_TMRA_9_CONFIG \ + { \ + .tmr_handler = CM_TMRA_9, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_9, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_9_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_9_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a9" \ + } +#endif /* PULSE_ENCODER_TMRA_9_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_10 +#ifndef PULSE_ENCODER_TMRA_10_CONFIG +#define PULSE_ENCODER_TMRA_10_CONFIG \ + { \ + .tmr_handler = CM_TMRA_10, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_10, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_10_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_10_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a10" \ + } +#endif /* PULSE_ENCODER_TMRA_10_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_11 +#ifndef PULSE_ENCODER_TMRA_11_CONFIG +#define PULSE_ENCODER_TMRA_11_CONFIG \ + { \ + .tmr_handler = CM_TMRA_11, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_11, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_11_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_11_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a11" \ + } +#endif /* PULSE_ENCODER_TMRA_11_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMRA_12 +#ifndef PULSE_ENCODER_TMRA_12_CONFIG +#define PULSE_ENCODER_TMRA_12_CONFIG \ + { \ + .tmr_handler = CM_TMRA_12, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_12, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_12_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_12_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a12" \ + } +#endif /* PULSE_ENCODER_TMRA_12_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_1 +#ifndef PULSE_ENCODER_TMR6_1_CONFIG +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ + } +#endif /* PULSE_ENCODER_TMR6_1_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_2 +#ifndef PULSE_ENCODER_TMR6_2_CONFIG +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ + } +#endif /* PULSE_ENCODER_TMR6_2_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_3 +#ifndef PULSE_ENCODER_TMR6_3_CONFIG +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ + } +#endif /* PULSE_ENCODER_TMR6_3_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_4 +#ifndef PULSE_ENCODER_TMR6_4_CONFIG +#define PULSE_ENCODER_TMR6_4_CONFIG \ + { \ + .tmr_handler = CM_TMR6_4, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_4, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_64" \ + } +#endif /* PULSE_ENCODER_TMR6_4_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_5 +#ifndef PULSE_ENCODER_TMR6_5_CONFIG +#define PULSE_ENCODER_TMR6_5_CONFIG \ + { \ + .tmr_handler = CM_TMR6_5, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_5, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_65" \ + } +#endif /* PULSE_ENCODER_TMR6_5_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_6 +#ifndef PULSE_ENCODER_TMR6_6_CONFIG +#define PULSE_ENCODER_TMR6_6_CONFIG \ + { \ + .tmr_handler = CM_TMR6_6, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_6, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_66" \ + } +#endif /* PULSE_ENCODER_TMR6_6_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_7 +#ifndef PULSE_ENCODER_TMR6_7_CONFIG +#define PULSE_ENCODER_TMR6_7_CONFIG \ + { \ + .tmr_handler = CM_TMR6_7, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_7, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_67" \ + } +#endif /* PULSE_ENCODER_TMR6_7_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */ + +#ifdef BSP_USING_PULSE_ENCODER_TMR6_8 +#ifndef PULSE_ENCODER_TMR6_8_CONFIG +#define PULSE_ENCODER_TMR6_8_CONFIG \ + { \ + .tmr_handler = CM_TMR6_8, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_8, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_68" \ + } +#endif /* PULSE_ENCODER_TMR6_8_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */ + +#endif /* RT_USING_PULSE_ENCODER */ + +#endif /* __PULSE_ENCODER_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pwm_tmr_config.h new file mode 100644 index 00000000000..9050e54b72b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/pwm_tmr_config.h @@ -0,0 +1,784 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __PWM_TMR_CONFIG_H__ +#define __PWM_TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PWM_TMRA + +#ifdef BSP_USING_PWM_TMRA_1 +#ifndef PWM_TMRA_1_CONFIG +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_1_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_1 */ + +#ifdef BSP_USING_PWM_TMRA_2 +#ifndef PWM_TMRA_2_CONFIG +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_2_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_2 */ + +#ifdef BSP_USING_PWM_TMRA_3 +#ifndef PWM_TMRA_3_CONFIG +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_3_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_3 */ + +#ifdef BSP_USING_PWM_TMRA_4 +#ifndef PWM_TMRA_4_CONFIG +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_4_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_4 */ + +#ifdef BSP_USING_PWM_TMRA_5 +#ifndef PWM_TMRA_5_CONFIG +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_5_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_5 */ + +#ifdef BSP_USING_PWM_TMRA_6 +#ifndef PWM_TMRA_6_CONFIG +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_6_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_6 */ + +#ifdef BSP_USING_PWM_TMRA_7 +#ifndef PWM_TMRA_7_CONFIG +#define PWM_TMRA_7_CONFIG \ + { \ + .name = "pwm_a7", \ + .instance = CM_TMRA_7, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_7_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_7 */ + +#ifdef BSP_USING_PWM_TMRA_8 +#ifndef PWM_TMRA_8_CONFIG +#define PWM_TMRA_8_CONFIG \ + { \ + .name = "pwm_a8", \ + .instance = CM_TMRA_8, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_8_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_8 */ + +#ifdef BSP_USING_PWM_TMRA_9 +#ifndef PWM_TMRA_9_CONFIG +#define PWM_TMRA_9_CONFIG \ + { \ + .name = "pwm_a9", \ + .instance = CM_TMRA_9, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_9_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_9 */ + +#ifdef BSP_USING_PWM_TMRA_10 +#ifndef PWM_TMRA_10_CONFIG +#define PWM_TMRA_10_CONFIG \ + { \ + .name = "pwm_a10", \ + .instance = CM_TMRA_10, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_10_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_10 */ + +#ifdef BSP_USING_PWM_TMRA_11 +#ifndef PWM_TMRA_11_CONFIG +#define PWM_TMRA_11_CONFIG \ + { \ + .name = "pwm_a11", \ + .instance = CM_TMRA_11, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_11_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_11 */ + +#ifdef BSP_USING_PWM_TMRA_12 +#ifndef PWM_TMRA_12_CONFIG +#define PWM_TMRA_12_CONFIG \ + { \ + .name = "pwm_a12", \ + .instance = CM_TMRA_12, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ + } +#endif /* PWM_TMRA_12_CONFIG */ +#endif /* BSP_USING_PWM_TMRA_12 */ + +#endif /* BSP_USING_PWM_TMRA */ + +#ifdef BSP_USING_PWM_TMR4 + +#ifdef BSP_USING_PWM_TMR4_1 +#ifndef PWM_TMR4_1_CONFIG +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ + } +#endif /* PWM_TMR4_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_1 */ + +#ifdef BSP_USING_PWM_TMR4_2 +#ifndef PWM_TMR4_2_CONFIG +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ + } +#endif /* PWM_TMR4_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_2 */ + +#ifdef BSP_USING_PWM_TMR4_3 +#ifndef PWM_TMR4_3_CONFIG +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ + } +#endif /* PWM_TMR4_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR4_3 */ + +#endif /* BSP_USING_PWM_TMR4 */ + +#ifdef BSP_USING_PWM_TMR6 + +#ifdef BSP_USING_PWM_TMR6_1 +#ifndef PWM_TMR6_1_CONFIG +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_1_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_1 */ +#ifdef BSP_USING_PWM_TMR6_2 +#ifndef PWM_TMR6_2_CONFIG +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t62", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_2_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_2 */ +#ifdef BSP_USING_PWM_TMR6_3 +#ifndef PWM_TMR6_3_CONFIG +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t63", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_3_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_3 */ +#ifdef BSP_USING_PWM_TMR6_4 +#ifndef PWM_TMR6_4_CONFIG +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t64", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_4_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_4 */ +#ifdef BSP_USING_PWM_TMR6_5 +#ifndef PWM_TMR6_5_CONFIG +#define PWM_TMR6_5_CONFIG \ + { \ + .name = "pwm_t65", \ + .instance = CM_TMR6_5, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_5_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_5 */ +#ifdef BSP_USING_PWM_TMR6_6 +#ifndef PWM_TMR6_6_CONFIG +#define PWM_TMR6_6_CONFIG \ + { \ + .name = "pwm_t66", \ + .instance = CM_TMR6_6, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_6_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_6 */ +#ifdef BSP_USING_PWM_TMR6_7 +#ifndef PWM_TMR6_7_CONFIG +#define PWM_TMR6_7_CONFIG \ + { \ + .name = "pwm_t67", \ + .instance = CM_TMR6_7, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_7_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_7 */ +#ifdef BSP_USING_PWM_TMR6_8 +#ifndef PWM_TMR6_8_CONFIG +#define PWM_TMR6_8_CONFIG \ + { \ + .name = "pwm_t68", \ + .instance = CM_TMR6_8, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ + } +#endif /* PWM_TMR6_8_CONFIG */ +#endif /* BSP_USING_PWM_TMR6_8 */ + +#endif /* BSP_USING_PWM_TMR6 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PWM_TMRA_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/qspi_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/qspi_config.h new file mode 100644 index 00000000000..ed80f5450df --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/qspi_config.h @@ -0,0 +1,72 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __QSPI_CONFIG_H__ +#define __QSPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_QSPI +#ifndef QSPI_BUS_CONFIG +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ + } +#endif /* QSPI_BUS_CONFIG */ + +#ifndef QSPI_INIT_PARAMS +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ + } +#endif /* QSPI_INIT_PARAMS */ + +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH + +#ifdef BSP_QSPI_USING_DMA +#ifndef QSPI_DMA_CONFIG +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ + } +#endif /* QSPI_DMA_CONFIG */ +#endif /* BSP_QSPI_USING_DMA */ +#endif /* BSP_USING_SPI1 */ + +#ifdef __cplusplus +} +#endif + +#endif /*__QSPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/sdio_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/sdio_config.h new file mode 100644 index 00000000000..0f97158759b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/sdio_config.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __SDIO_CONFIG_H__ +#define __SDIO_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_SDIO1) +#ifndef SDIO1_BUS_CONFIG +#define SDIO1_BUS_CONFIG \ + { \ + .name = "sdio1", \ + .instance = CM_SDIOC1, \ + .clock = FCG1_PERIPH_SDIOC1, \ + .irq_config = { \ + .irq_num = BSP_SDIO1_IRQ_NUM, \ + .irq_prio = BSP_SDIO1_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC1_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO1_RX_DMA_INSTANCE, \ + .channel = SDIO1_RX_DMA_CHANNEL, \ + .clock = SDIO1_RX_DMA_CLOCK, \ + .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO1_TX_DMA_INSTANCE, \ + .channel = SDIO1_TX_DMA_CHANNEL, \ + .clock = SDIO1_TX_DMA_CLOCK, \ + .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAW, \ + }, \ + } +#endif /* SDIO1_BUS_CONFIG */ +#endif /* BSP_USING_SDIO1 */ + +#if defined(BSP_USING_SDIO2) +#ifndef SDIO2_BUS_CONFIG +#define SDIO2_BUS_CONFIG \ + { \ + .name = "sdio2", \ + .instance = CM_SDIOC2, \ + .clock = FCG1_PERIPH_SDIOC2, \ + .irq_config = { \ + .irq_num = BSP_SDIO2_IRQ_NUM, \ + .irq_prio = BSP_SDIO2_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC2_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO2_RX_DMA_INSTANCE, \ + .channel = SDIO2_RX_DMA_CHANNEL, \ + .clock = SDIO2_RX_DMA_CLOCK, \ + .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO2_TX_DMA_INSTANCE, \ + .channel = SDIO2_TX_DMA_CHANNEL, \ + .clock = SDIO2_TX_DMA_CLOCK, \ + .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAW, \ + }, \ + } +#endif /* SDIO2_BUS_CONFIG */ +#endif /* BSP_USING_SDIO2 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/spi_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/spi_config.h new file mode 100644 index 00000000000..13889d4ca4e --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/spi_config.h @@ -0,0 +1,358 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __SPI_CONFIG_H__ +#define __SPI_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = CM_SPI5, \ + .bus_name = "spi5", \ + .clock = FCG1_PERIPH_SPI5, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI5_SPEI, \ + }, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .clock = SPI5_TX_DMA_CLOCK, \ + .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPTI, \ + .flag = SPI5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .clock = SPI5_RX_DMA_CLOCK, \ + .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPRI, \ + .flag = SPI5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .Instance = CM_SPI6, \ + .bus_name = "spi6", \ + .clock = FCG1_PERIPH_SPI6, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI6_SPEI, \ + }, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .clock = SPI6_TX_DMA_CLOCK, \ + .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPTI, \ + .flag = SPI6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ + +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .clock = SPI6_RX_DMA_CLOCK, \ + .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPRI, \ + .flag = SPI6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + + +#ifdef __cplusplus +} +#endif + +#endif /*__SPI_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/timer_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/timer_config.h new file mode 100644 index 00000000000..4c072a2e6fa --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/timer_config.h @@ -0,0 +1,235 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __TMR_CONFIG_H__ +#define __TMR_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_TMRA_1 +#ifndef TMRA_1_CONFIG +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ + } +#endif /* TMRA_1_CONFIG */ +#endif /* BSP_USING_TMRA_1 */ + +#ifdef BSP_USING_TMRA_2 +#ifndef TMRA_2_CONFIG +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ + } +#endif /* TMRA_2_CONFIG */ +#endif /* BSP_USING_TMRA_2 */ + +#ifdef BSP_USING_TMRA_3 +#ifndef TMRA_3_CONFIG +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ + } +#endif /* TMRA_3_CONFIG */ +#endif /* BSP_USING_TMRA_3 */ + +#ifdef BSP_USING_TMRA_4 +#ifndef TMRA_4_CONFIG +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ + } +#endif /* TMRA_4_CONFIG */ +#endif /* BSP_USING_TMRA_4 */ + +#ifdef BSP_USING_TMRA_5 +#ifndef TMRA_5_CONFIG +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ + } +#endif /* TMRA_5_CONFIG */ +#endif /* BSP_USING_TMRA_5 */ + +#ifdef BSP_USING_TMRA_6 +#ifndef TMRA_6_CONFIG +#define TMRA_6_CONFIG \ + { \ + .tmr_handle = CM_TMRA_6, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_6, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_6_OVF, \ + .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ + }, \ + .name = "tmra_6" \ + } +#endif /* TMRA_6_CONFIG */ +#endif /* BSP_USING_TMRA_6 */ + +#ifdef BSP_USING_TMRA_7 +#ifndef TMRA_7_CONFIG +#define TMRA_7_CONFIG \ + { \ + .tmr_handle = CM_TMRA_7, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_7, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_7_OVF, \ + .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ + }, \ + .name = "tmra_7" \ + } +#endif /* TMRA_7_CONFIG */ +#endif /* BSP_USING_TMRA_7 */ + +#ifdef BSP_USING_TMRA_8 +#ifndef TMRA_8_CONFIG +#define TMRA_8_CONFIG \ + { \ + .tmr_handle = CM_TMRA_8, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_8, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_8_OVF, \ + .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ + }, \ + .name = "tmra_8" \ + } +#endif /* TMRA_8_CONFIG */ +#endif /* BSP_USING_TMRA_8 */ + +#ifdef BSP_USING_TMRA_9 +#ifndef TMRA_9_CONFIG +#define TMRA_9_CONFIG \ + { \ + .tmr_handle = CM_TMRA_9, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_9, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_9_OVF, \ + .enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \ + }, \ + .name = "tmra_9" \ + } +#endif /* TMRA_9_CONFIG */ +#endif /* BSP_USING_TMRA_9 */ + +#ifdef BSP_USING_TMRA_10 +#ifndef TMRA_10_CONFIG +#define TMRA_10_CONFIG \ + { \ + .tmr_handle = CM_TMRA_10, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_10, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_10_OVF, \ + .enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \ + }, \ + .name = "tmra_10" \ + } +#endif /* TMRA_10_CONFIG */ +#endif /* BSP_USING_TMRA_10 */ + +#ifdef BSP_USING_TMRA_11 +#ifndef TMRA_11_CONFIG +#define TMRA_11_CONFIG \ + { \ + .tmr_handle = CM_TMRA_11, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_11, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_11_OVF, \ + .enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \ + }, \ + .name = "tmra_11" \ + } +#endif /* TMRA_11_CONFIG */ +#endif /* BSP_USING_TMRA_11 */ + +#ifdef BSP_USING_TMRA_12 +#ifndef TMRA_12_CONFIG +#define TMRA_12_CONFIG \ + { \ + .tmr_handle = CM_TMRA_12, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_12, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_12_OVF, \ + .enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \ + }, \ + .name = "tmra_12" \ + } +#endif /* TMRA_12_CONFIG */ +#endif /* BSP_USING_TMRA_12 */ +#endif /* __TMR_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/tmr_capture_config.h new file mode 100644 index 00000000000..821538c1cbb --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/tmr_capture_config.h @@ -0,0 +1,69 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __IC_CONFIG_H__ +#define __IC_CONFIG_H__ + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +#define IC1_NAME "ic1" +#define INPUT_CAPTURE_CFG_TMR6_1 \ + { \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ + } +#endif + +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +#define IC2_NAME "ic2" +#define INPUT_CAPTURE_CFG_TMR6_2 \ + { \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ + } +#endif + +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) +#define IC3_NAME "ic3" +#define INPUT_CAPTURE_CFG_TMR6_3 \ + { \ + .name = IC3_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ + } +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __IC_CONFIG_H__ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/uart_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/uart_config.h new file mode 100644 index 00000000000..573ae0fde07 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/uart_config.h @@ -0,0 +1,672 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __UART_CONFIG_H__ +#define __UART_CONFIG_H__ + +#include +#include "irq_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + + +#if defined(BSP_USING_UART1) +#ifndef UART1_CONFIG +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ + } +#endif /* UART1_CONFIG */ + +#if defined(BSP_UART1_RX_USING_DMA) +#ifndef UART1_DMA_RX_CONFIG +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_RX_CONFIG */ + +#ifndef UART1_RXTO_CONFIG +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ + } +#endif /* UART1_RXTO_CONFIG */ +#endif /* BSP_UART1_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART1_TX_CPLT_CONFIG +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ + } +#endif +#endif /* UART1_TX_CPLT_CONFIG */ + +#if defined(BSP_UART1_TX_USING_DMA) +#ifndef UART1_DMA_TX_CONFIG +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART1_DMA_TX_CONFIG */ +#endif /* BSP_UART1_TX_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +#ifndef UART2_CONFIG +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ + } +#endif /* UART2_CONFIG */ + +#if defined(BSP_UART2_RX_USING_DMA) +#ifndef UART2_DMA_RX_CONFIG +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_RX_CONFIG */ + +#ifndef UART2_RXTO_CONFIG +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ + } +#endif /* UART2_RXTO_CONFIG */ +#endif /* BSP_UART2_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART2_TX_CPLT_CONFIG +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ + } +#endif +#endif /* UART2_TX_CPLT_CONFIG */ + +#if defined(BSP_UART2_TX_USING_DMA) +#ifndef UART2_DMA_TX_CONFIG +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART2_DMA_TX_CONFIG */ +#endif /* BSP_UART2_TX_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +#ifndef UART3_CONFIG +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ + } +#endif /* UART3_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART3_TX_CPLT_CONFIG +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ + } +#endif +#endif /* UART3_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +#ifndef UART4_CONFIG +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ + } +#endif /* UART4_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART4_TX_CPLT_CONFIG +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ + } +#endif +#endif /* UART4_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +#ifndef UART5_CONFIG +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART5_RX_IRQ_NUM, \ + .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART5_TX_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TI, \ + }, \ + } +#endif /* UART5_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART5_TX_CPLT_CONFIG +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ + } +#endif +#endif /* UART5_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +#ifndef UART6_CONFIG +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART6_RX_IRQ_NUM, \ + .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART6_TX_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TI, \ + }, \ + } +#endif /* UART6_CONFIG */ + +#if defined(BSP_UART6_RX_USING_DMA) +#ifndef UART6_DMA_RX_CONFIG +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .channel = UART6_RX_DMA_CHANNEL, \ + .clock = UART6_RX_DMA_CLOCK, \ + .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_RI, \ + .flag = UART6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART6_RX_DMA_IRQn, \ + .irq_prio = UART6_RX_DMA_INT_PRIO, \ + .int_src = UART6_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_RX_CONFIG */ + +#ifndef UART6_RXTO_CONFIG +#define UART6_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RTO, \ + }, \ + } +#endif /* UART6_RXTO_CONFIG */ +#endif /* BSP_UART6_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART6_TX_CPLT_CONFIG +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ + } +#endif +#endif /* UART6_TX_CPLT_CONFIG */ + +#if defined(BSP_UART6_TX_USING_DMA) +#ifndef UART6_DMA_TX_CONFIG +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .channel = UART6_TX_DMA_CHANNEL, \ + .clock = UART6_TX_DMA_CLOCK, \ + .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_TI, \ + .flag = UART6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART6_TX_DMA_IRQn, \ + .irq_prio = UART6_TX_DMA_INT_PRIO, \ + .int_src = UART6_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART6_DMA_TX_CONFIG */ +#endif /* BSP_UART6_TX_USING_DMA */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +#ifndef UART7_CONFIG +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = CM_USART7, \ + .clock = FCG3_PERIPH_USART7, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART7_RX_IRQ_NUM, \ + .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART7_TX_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TI, \ + }, \ + } +#endif /* UART7_CONFIG */ + +#if defined(BSP_UART7_RX_USING_DMA) +#ifndef UART7_DMA_RX_CONFIG +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .channel = UART7_RX_DMA_CHANNEL, \ + .clock = UART7_RX_DMA_CLOCK, \ + .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_RI, \ + .flag = UART7_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART7_RX_DMA_IRQn, \ + .irq_prio = UART7_RX_DMA_INT_PRIO, \ + .int_src = UART7_RX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_RX_CONFIG */ + +#ifndef UART7_RXTO_CONFIG +#define UART7_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RTO, \ + }, \ + } +#endif /* UART7_RXTO_CONFIG */ +#endif /* BSP_UART7_RX_USING_DMA */ + +#if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ + } +#endif +#elif defined(RT_USING_SERIAL_V2) +#ifndef UART7_TX_CPLT_CONFIG +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ + } +#endif +#endif /* UART7_TX_CPLT_CONFIG */ + +#if defined(BSP_UART7_TX_USING_DMA) +#ifndef UART7_DMA_TX_CONFIG +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .channel = UART7_TX_DMA_CHANNEL, \ + .clock = UART7_TX_DMA_CLOCK, \ + .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART7_TX_DMA_IRQn, \ + .irq_prio = UART7_TX_DMA_INT_PRIO, \ + .int_src = UART7_TX_DMA_INT_SRC, \ + }, \ + } +#endif /* UART7_DMA_TX_CONFIG */ +#endif /* BSP_UART7_TX_USING_DMA */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART8) +#ifndef UART8_CONFIG +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .Instance = CM_USART8, \ + .clock = FCG3_PERIPH_USART8, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART8_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART8_RX_IRQ_NUM, \ + .irq_prio = BSP_UART8_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART8_TX_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TI, \ + }, \ + } +#endif /* UART8_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART8_TX_CPLT_CONFIG +#define UART8_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TCI, \ + }, \ + } +#endif +#endif /* UART8_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +#ifndef UART9_CONFIG +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .Instance = CM_USART9, \ + .clock = FCG3_PERIPH_USART9, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART9_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART9_RX_IRQ_NUM, \ + .irq_prio = BSP_UART9_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART9_TX_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TI, \ + }, \ + } +#endif /* UART9_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART9_TX_CPLT_CONFIG +#define UART9_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TCI, \ + }, \ + } +#endif +#endif /* UART9_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +#ifndef UART10_CONFIG +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = CM_USART10, \ + .clock = FCG3_PERIPH_USART10, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART10_RX_IRQ_NUM, \ + .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART10_TX_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TI, \ + }, \ + } +#endif /* UART10_CONFIG */ + +#if defined(RT_USING_SERIAL_V2) +#ifndef UART10_TX_CPLT_CONFIG +#define UART10_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TCI, \ + }, \ + } +#endif +#endif /* UART10_TX_CPLT_CONFIG */ +#endif /* BSP_USING_UART10 */ + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_app_conf.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_app_conf.h new file mode 100644 index 00000000000..7eab518e482 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_app_conf.h @@ -0,0 +1,167 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __USB_APP_CONF_H__ +#define __USB_APP_CONF_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "rtconfig.h" + +/* USB MODE CONFIGURATION */ +/* +USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment +(1) If only defined USB_FS_MODE: + MCU USBFS core work in full speed using internal PHY. +(2) If only defined USB_HS_MODE: + MCU USBHS core work in full speed using internal PHY. +(3) If both defined USB_HS_MODE && USB_HS_EXTERNAL_PHY + MCU USBHS core work in high speed using external PHY. +(4) Other combination: + Not support, forbid!! +*/ + +#if defined(BSP_USING_USBHS) +#define USB_HS_MODE +#endif +#if defined(BSP_USING_USBFS) +#define USB_FS_MODE +#endif +#if !defined(BSP_USING_USBHS) && !defined(BSP_USING_USBFS) +#define USB_FS_MODE +#endif + +#if defined(BSP_USING_USBD) +#define USE_DEVICE_MODE +#endif +#if defined(BSP_USING_USBH) +#define USE_HOST_MODE +#endif +#if !defined(BSP_USING_USBD) && !defined(BSP_USING_USBH) +#define USE_DEVICE_MODE +#endif + +#if defined(USB_HS_MODE) && defined(BSP_USING_USBHS_PHY_EXTERN) +#define USB_HS_EXTERNAL_PHY +#endif + +#ifndef USB_HS_MODE +#ifndef USB_FS_MODE +#error "USB_HS_MODE or USB_FS_MODE should be defined" +#endif +#endif + +#ifndef USE_DEVICE_MODE +#ifndef USE_HOST_MODE +#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" +#endif +#endif + +#if defined(BSP_USING_USBD) +/* USB DEVICE FIFO CONFIGURATION */ +#ifdef USB_FS_MODE +#define RX_FIFO_FS_SIZE (128U) +#define TX0_FIFO_FS_SIZE (32U) +#define TX1_FIFO_FS_SIZE (32U) +#define TX2_FIFO_FS_SIZE (32U) +#define TX3_FIFO_FS_SIZE (32U) +#define TX4_FIFO_FS_SIZE (32U) +#define TX5_FIFO_FS_SIZE (32U) +#define TX6_FIFO_FS_SIZE (32U) +#define TX7_FIFO_FS_SIZE (32U) +#define TX8_FIFO_FS_SIZE (32U) +#define TX9_FIFO_FS_SIZE (32U) +#define TX10_FIFO_FS_SIZE (32U) +#define TX11_FIFO_FS_SIZE (32U) +#define TX12_FIFO_FS_SIZE (32U) +#define TX13_FIFO_FS_SIZE (32U) +#define TX14_FIFO_FS_SIZE (32U) +#define TX15_FIFO_FS_SIZE (32U) + +#if ((RX_FIFO_FS_SIZE + \ + TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ + TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ + TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \ + TX15_FIFO_FS_SIZE) > 640U) +#error "The USB max FIFO size is 640 x 4 Bytes!" +#endif +#endif + +#ifdef USB_HS_MODE +#define RX_FIFO_HS_SIZE (512U) +#define TX0_FIFO_HS_SIZE (64U) +#define TX1_FIFO_HS_SIZE (64U) +#define TX2_FIFO_HS_SIZE (64U) +#define TX3_FIFO_HS_SIZE (64U) +#define TX4_FIFO_HS_SIZE (64U) +#define TX5_FIFO_HS_SIZE (64U) +#define TX6_FIFO_HS_SIZE (64U) +#define TX7_FIFO_HS_SIZE (64U) +#define TX8_FIFO_HS_SIZE (64U) +#define TX9_FIFO_HS_SIZE (64U) +#define TX10_FIFO_HS_SIZE (64U) +#define TX11_FIFO_HS_SIZE (64U) +#define TX12_FIFO_HS_SIZE (64U) +#define TX13_FIFO_HS_SIZE (64U) +#define TX14_FIFO_HS_SIZE (64U) +#define TX15_FIFO_HS_SIZE (64U) + +#if ((RX_FIFO_HS_SIZE + \ + TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ + TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ + TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \ + TX15_FIFO_HS_SIZE) > 2048U) +#error "The USB max FIFO size is 2048 x 4 Bytes!" +#endif +#endif + +#if defined(BSP_USING_USBD_VBUS_SENSING) +#define VBUS_SENSING_ENABLED +#endif +#endif + +#if defined(BSP_USING_USBH) +/* USB HOST FIFO CONFIGURATION */ +#ifdef USB_FS_MODE +#define RX_FIFO_FS_SIZE (128U) +#define TXH_NP_FS_FIFOSIZ (32U) +#define TXH_P_FS_FIFOSIZ (64U) + +#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U) +#error "The USB max FIFO size is 640 x 4 Bytes!" +#endif +#endif + +#ifdef USB_HS_MODE +#define RX_FIFO_HS_SIZE (512U) +#define TXH_NP_HS_FIFOSIZ (128U) +#define TXH_P_HS_FIFOSIZ (256U) + +#if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U) +#error "The USB max FIFO size is 2048 x 4 Bytes!" +#endif +#endif +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_APP_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_bsp.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_bsp.h new file mode 100644 index 00000000000..6295a2453bf --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/config/usb_config/usb_bsp.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __USB_BSP_H__ +#define __USB_BSP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +#include "hc32_ll_utility.h" + +extern void usb_udelay(const uint32_t usec); +extern void usb_mdelay(const uint32_t msec); + +/** + * @} + */ + +/** + * @} + */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __USB_BSP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/drv_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/drv_config.h new file mode 100644 index 00000000000..978dbbea3c3 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/drv_config.h @@ -0,0 +1,41 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __DRV_CONFIG_H__ +#define __DRV_CONFIG_H__ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#include "dma_config.h" +#include "uart_config.h" +#include "spi_config.h" +#include "adc_config.h" +#include "dac_config.h" +#include "gpio_config.h" +#include "eth_config.h" +#include "can_config.h" +#include "sdio_config.h" +#include "pm_config.h" +#include "i2c_config.h" +#include "qspi_config.h" +#include "pulse_encoder_config.h" +#include "timer_config.h" +#include "tmr_capture_config.h" + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/hc32f4xx_conf.h new file mode 100644 index 00000000000..42cf806c1f8 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/hc32f4xx_conf.h @@ -0,0 +1,173 @@ +/** + ******************************************************************************* + * @file hc32f4xx_conf.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2026-05-27 CDT First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2022-2023, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4XX_CONF_H__ +#define __HC32F4XX_CONF_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note LL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note LL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_DMC_ENABLE (DDL_ON) +#define LL_DVP_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_ETH_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_HRPWM_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_NFC_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR2_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F4A2_LQFP176 (1U) + +/** + * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to 0U. + */ +#define BSP_EV_HC32F4XX (0U) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to DDL_ON. + */ +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_GT9XX_ENABLE (DDL_OFF) +#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF) +#define BSP_IS62WV51216_ENABLE (DDL_OFF) +#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_OV5640_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_WM8731_ENABLE (DDL_OFF) + +/** + * @brief Ethernet and PHY Configuration. + */ +/* MAC ADDRESS */ +#define ETH_MAC_ADDR0 (0x02U) +#define ETH_MAC_ADDR1 (0x00U) +#define ETH_MAC_ADDR2 (0x00U) +#define ETH_MAC_ADDR3 (0x00U) +#define ETH_MAC_ADDR4 (0x00U) +#define ETH_MAC_ADDR5 (0x00U) + +#if defined(ETH_PHY_USING_RTL8201F) +/* PHY(RTL8201F) Address*/ +#define ETH_PHY_ADDR (0x01U) + +/* PHY Status Register */ +#define PHY_SR (0x00U) /*!< PHY status register */ +#define PHY_DUPLEX_STATUS (0x0100U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS (0x2000U) /*!< PHY Speed mask */ + +#endif + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4XX_CONF_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.icf b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.icf new file mode 100644 index 00000000000..e81ccd061fa --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.icf @@ -0,0 +1,102 @@ +/***************************************************************************//** + * \file HC32F4A2.icf + * \version 1.0 + * + * \brief Linker file for the IAR compiler. + * +******************************************************************************** +* \copyright + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause +*******************************************************************************/ +/*###ICF### Section handled by ICF editor, don't touch! *****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +// Check that necessary symbols have been passed to linker via command line interface +if((!isdefinedsymbol(_LINK_RAM_)) && (!isdefinedsymbol(_LINK_FLASH_))) { + error "Link location not defined or not supported!"; +} + +/******************************************************************************* + * Memory address and size definitions + ******************************************************************************/ +define symbol ram1_base_address = 0x1FFE0000; +define symbol ram1_end_address = 0x2005FFFF; + +if(isdefinedsymbol(_LINK_RAM_)) { + define symbol ram_start_reserve = 0x20000; + define symbol rom1_base_address = ram1_base_address; + define symbol rom1_end_address = rom1_base_address + ram_start_reserve - 0x01; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; + define symbol rom3_base_address = 0x0; + define symbol rom3_end_address = 0x0; +} else { + define symbol ram_start_reserve = 0x0; + define symbol rom1_base_address = 0x0; + define symbol rom3_base_address = 0x03000000; + define symbol rom3_end_address = 0x030017FF; + define symbol rom1_end_address = 0x001FFFFF; + define symbol rom2_base_address = 0x0; + define symbol rom2_end_address = 0x0; +} + +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = rom1_base_address; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = rom1_base_address; +define symbol __ICFEDIT_region_IROM1_end__ = rom1_end_address; +define symbol __ICFEDIT_region_IROM2_start__ = rom2_base_address; +define symbol __ICFEDIT_region_IROM2_end__ = rom2_end_address; +define symbol __ICFEDIT_region_IROM3_start__ = rom3_base_address; +define symbol __ICFEDIT_region_IROM3_end__ = rom3_end_address; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = ram1_base_address + ram_start_reserve; +define symbol __ICFEDIT_region_IRAM1_end__ = ram1_end_address; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2000; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +/******************************************************************************* + * Memory definitions + ******************************************************************************/ +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region OTP_region = mem:[from __ICFEDIT_region_IROM3_start__ to __ICFEDIT_region_IROM3_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in OTP_region { readonly section .otp_data }; +place in RAM_region { readwrite, + block CSTACK, block HEAP }; diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.ld b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.ld new file mode 100644 index 00000000000..b364e25999b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.ld @@ -0,0 +1,294 @@ +/****************************************************************************** + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by XHSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ +/*****************************************************************************/ +/* File HC32F4A2xI.ld */ +/* Abstract Linker script for HC32F4A2 Device with */ +/* 2MByte FLASH, 516KByte RAM */ +/* Version V1.0 */ +/* Date 2026-05-27 */ +/*****************************************************************************/ +/* OTP section(data sections are not flash multiplexed region) implementation. + You need to pay attention to the size of the specified OTP block. + Take two OTP blocks for example. */ +__OTP_DATA_BASE = 0x03000000; +__OTP_LOCK_BASE = 0x03001800; +/* OTP block 16 */ +__OTP_DATA_B16_START = 0x03000000; +__OTP_LOCK_B16_START = 0x03001840; +__OTP_DATA_B16_OFFSET = __OTP_DATA_B16_START - __OTP_DATA_BASE; +__OTP_LOCK_B16_OFFSET = __OTP_LOCK_B16_START - __OTP_LOCK_BASE; +/* OTP block 17 */ +__OTP_DATA_B17_START = 0x03000800; +__OTP_LOCK_B17_START = 0x03001844; +__OTP_DATA_B17_OFFSET = __OTP_DATA_B17_START - __OTP_DATA_BASE; +__OTP_LOCK_B17_OFFSET = __OTP_LOCK_B17_START - __OTP_LOCK_BASE; + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M + OTP_DATA (rx): ORIGIN = 0x03000000, LENGTH = 6K + OTP_LOCK (rx): ORIGIN = 0x03001800, LENGTH = 728 + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + _stext = .; + KEEP(*(.isr_vector)) /* Startup code */ + . = ALIGN(4); + *(.text) /* remaining code */ + *(.text.*) /* remaining code */ + *(.rodata) /* read-only data (constants) */ + *(.rodata*) + *(.glue_7) + *(.glue_7t) + *(.gnu.linkonce.t*) + + /* section information for finsh shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + . = ALIGN(4); + + /* section information for initial. */ + . = ALIGN(4); + __rt_init_start = .; + KEEP(*(SORT(.rti_fn*))) + __rt_init_end = .; + . = ALIGN(4); + + /* section for CherryUSB. */ + . = ALIGN(4); + __usbh_class_info_start__ = .; + KEEP(*(.usbh_class_info)) + __usbh_class_info_end__ = .; + + . = ALIGN(4); + _etext = .; + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_data : + { + . = ALIGN(4); + . = ORIGIN(OTP_DATA) + __OTP_DATA_B16_OFFSET; + KEEP(*(.otp_b16_data*)) + . = ORIGIN(OTP_DATA) + __OTP_DATA_B17_OFFSET; + KEEP(*(.otp_b17_data*)) + . = ALIGN(4); + } >OTP_DATA + + .otp_lock : + { + . = ALIGN(4); + . = ORIGIN(OTP_LOCK) + __OTP_LOCK_B16_OFFSET; + KEEP(*(.otp_b16_lock*)) + . = ORIGIN(OTP_LOCK) + __OTP_LOCK_B17_OFFSET; + KEEP(*(.otp_b17_lock*)) + . = ALIGN(4); + } >OTP_LOCK + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + *(.gnu.linkonce.d*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + __bss_start = .; + .bss __StackTop (NOLOAD): + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + . = ALIGN(4); + *(.noinit*) + . = ALIGN(4); + } >RAM + __bss_end = .; + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") + + /* Stabs debugging sections. */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + /* DWARF debug sections. + * Symbols in the DWARF debugging sections are relative to the beginning + * of the section so we begin them at 0. */ + /* DWARF 1 */ + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + /* GNU DWARF 1 extensions */ + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + /* DWARF 1.1 and DWARF 2 */ + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + /* DWARF 2 */ + .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + /* SGI/MIPS DWARF 2 extensions */ + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.sct b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.sct new file mode 100644 index 00000000000..0bf7fc8eb14 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/linker_scripts/link.sct @@ -0,0 +1,22 @@ +; **************************************************************** +; Scatter-Loading Description File +; **************************************************************** +LR_IROM1 0x00000000 0x00200000 { ; load region size_region + ER_IROM1 0x00000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + .ANY (+XO) + } + RW_IRAM1 0x1FFE0000 UNINIT 0x00000008 { ; RW data + *(.bss.noinit) + } + RW_IRAM2 0x1FFE0008 0x0007FFF8 { ; RW data + .ANY (+RW +ZI) + .ANY (RAMCODE) + } + RW_IRAMB 0x200F0000 0x00001000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/fal_cfg.h new file mode 100644 index 00000000000..2b9c730df5e --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/fal_cfg.h @@ -0,0 +1,42 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef _FAL_CFG_H_ +#define _FAL_CFG_H_ + +#include +#include + +/* enable hc32f4 onchip flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_HC32F4 +/* enable SFUD flash driver sample */ +#define FAL_FLASH_PORT_DRIVER_SFUD + +extern const struct fal_flash_dev hc32_onchip_flash; +extern struct fal_flash_dev ext_nor_flash0; + +/* flash device table */ +#define FAL_FLASH_DEV_TABLE \ + { \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ + } + +/* ====================== Partition Configuration ========================== */ +#ifdef FAL_PART_HAS_TABLE_CFG +/* partition table */ +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \ + } +#endif /* FAL_PART_HAS_TABLE_CFG */ + +#endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/nand_port.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/nand_port.h new file mode 100644 index 00000000000..9162d9d771f --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/nand_port.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __NAND_PORT_H__ +#define __NAND_PORT_H__ + +/******************** NAND chip information ***********************************/ +#define NAND_BYTES_PER_PAGE 2048UL +#define NAND_SPARE_AREA_SIZE 64UL +#define NAND_PAGES_PER_BLOCK 64UL +#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) +#define NAND_BLOCKS_PER_PLANE 1024UL +#define NAND_PLANE_PER_DEVICE 2UL +#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) +#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) + +/******************** EXMC_NFC configure **************************************/ +/* chip: EXMC_NFC_BANK0~7 */ +#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0 + +/* density:2Gbit */ +#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT + +/* device width: 8-bit */ +#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT + +/* BankNum: 1BANK */ +#define NAND_EXMC_NFC_BANK_NUMBER EXMC_NFC_1BANK + +/* page size: 2KByte */ +#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE + +/* row address cycle: 3 */ +#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE + +/* ECC mode */ +#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC + +/* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */ +/* TS: ALE/CLE/CE setup time(min=10ns) */ +#define NAND_TS 1U + +/* TWP: WE# pulse width (min=10ns) */ +#define NAND_TWP 1U + +/* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */ +#define NAND_TRP 2U + +/* TTH: ALE/CLE/CE hold time (min=5ns) */ +#define NAND_TH 1U + +/* TWH: WE# pulse width HIGH (min=10ns) */ +#define NAND_TWH 1U + +/* TRH: RE# pulse width HIGH (min=7ns) */ +#define NAND_TRH 1U + +/* TRR: Ready to RE# LOW (min=20ns) */ +#define NAND_TRR 2U + +/* TWB: WE# HIGH to busy (max=100ns) */ +#define NAND_TWB 1U + +/* TWB: WE# HIGH to busy (max=100ns) */ +#define NAND_TRB 1U + +/* TCCS: Change read column and Change write column delay */ +#define NAND_TCCS 5U + +/* TWTR: WE# HIGH to RE# LOW (min=60ns) */ +#define NAND_TWTR 4U + +/* TRTW: RE# HIGH to WE# LOW (min=100ns) */ +#define NAND_TRTW 7U + +/* TADL: ALE to data start (min=70ns) */ +#define NAND_TADL 5U + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/sdram_port.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/sdram_port.h new file mode 100644 index 00000000000..acbbce1ff8c --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/sdram_port.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __SDRAM_PORT_H__ +#define __SDRAM_PORT_H__ + +/* parameters for sdram peripheral */ + +/* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */ +#define SDRAM_CHIP EXMC_DMC_CHIP1 +/* bank address */ +#define SDRAM_BANK_ADDR (0x80000000UL) +/* size(kbyte):8MB = 8*1024*1KBytes */ +#define SDRAM_SIZE (8UL * 1024UL * 1024UL) +/* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */ +#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 +/* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */ +#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT +/* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */ +#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM8 +/* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */ +#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM12 +/* cas latency clock number: 2, 3 */ +#define SDRAM_CAS_LATENCY 2UL +/* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */ +#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT + +/* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */ +#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD +/* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */ +#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL +/* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */ +#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED + +/* timing configuration(EXCLK clock frequency: 30MHz) for IS42S16400J-7TLI */ +/* refresh rate counter (EXCLK clock) */ +#define SDRAM_REFRESH_COUNT (450U) +/* TMDR: mode register command time (EXCLK clock) */ +#define SDRAM_TMDR 2U +/* TRAS: RAS to precharge delay time (EXCLK clock) */ +#define SDRAM_TRAS 2U +/* TRC: active bank x to active bank x delay time (EXCLK clock) */ +#define SDRAM_TRC 2U +/* TRCD: RAS to CAS minimum delay time (EXCLK clock) */ +#define SDRAM_TRCD_B 3U +#define SDRAM_TRCD_P 0U +/* TRFC: autorefresh command time (EXCLK clock) */ +#define SDRAM_TRFC_B 3U +#define SDRAM_TRFC_P 0U +/* TRP: precharge to RAS delay time (EXCLK clock) */ +#define SDRAM_TRP_B 3U +#define SDRAM_TRP_P 0U +/* TRRD: active bank x to active bank y delay time (EXCLK clock) */ +#define SDRAM_TRRD 1U +/* TWR: write to precharge delay time (EXCLK clock). */ +#define SDRAM_TWR 2U +/* TWTR: write to read delay time (EXCLK clock). */ +#define SDRAM_TWTR 1U +/* TXP: exit power-down command time (EXCLK clock). */ +#define SDRAM_TXP 1U +/* TXSR: exit self-refresh command time (EXCLK clock). */ +#define SDRAM_TXSR 5U +/* TESR: self-refresh command time (EXCLK clock). */ +#define SDRAM_TESR 5U + +/* memory mode register */ +#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) +#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) +#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) +#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) +#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) +#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/tca9539_port.h new file mode 100644 index 00000000000..47e2883afe6 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/tca9539_port.h @@ -0,0 +1,73 @@ +/* + * Copyright (C) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef __TCA9539_PORT_H__ +#define __TCA9539_PORT_H__ + +#include "tca9539.h" + +/** + * @defgroup HC32F4A2_EV_IO_Function_Sel Expand IO function definition + * @{ + */ +#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ +#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ +#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */ +#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */ +#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */ +#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ + +#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */ +#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */ +#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ +#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ +#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +/** + * @} + */ + +/** + * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition + * @{ + */ +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) +/** + * @} + */ + +/** + * @defgroup BSP CAN PHY STB port/pin definition + * @{ + */ +#define CAN_STB_PORT (TCA9539_IO_PORT1) +#define CAN_STB_PIN (EIO_CAN_STB) +/** + * @} + */ +/** + * @defgroup BSP_ETH_PortPin_Sel BSP ETH port/pin definition + * @{ + */ +#define ETH_RST_PORT (TCA9539_IO_PORT1) +#define ETH_RST_PIN (EIO_ETH_RST) +/** + * @} + */ +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/usb_config.h b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/usb_config.h new file mode 100644 index 00000000000..44476b2f65e --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/board/ports/usb_config.h @@ -0,0 +1,342 @@ +/* + * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-05-27 CDT first version + */ + +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +/* ================ USB common Configuration ================ */ + +#ifdef __RTTHREAD__ +#include + +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#else +#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#endif + +#ifndef CONFIG_USB_DBG_LEVEL +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#endif + +/* Enable print with color */ +#define CONFIG_USB_PRINTF_COLOR_ENABLE + +// #define CONFIG_USB_DCACHE_ENABLE + +/* data align size when use dma or use dcache */ +#ifdef CONFIG_USB_DCACHE_ENABLE +#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#else +#define CONFIG_USB_ALIGN_SIZE 4 +#endif + +/* attribute data into no cache ram */ +#define USB_NOCACHE_RAM_SECTION __attribute__((section(".noncacheable"))) + +/* use usb_memcpy default for high performance but cost more flash memory. + * And, arm libc has a bug that memcpy() may cause data misalignment when the size is not a multiple of 4. +*/ +// #define CONFIG_USB_MEMCPY_DISABLE + +/* ================= USB Device Stack Configuration ================ */ + +/* Ep0 in and out transfer buffer */ +#ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#endif + +/* Send ep0 in data from user buffer instead of copying into ep0 reqdata + * Please note that user buffer must be aligned with CONFIG_USB_ALIGN_SIZE +*/ +// #define CONFIG_USBDEV_EP0_INDATA_NO_COPY + +/* Check if the input descriptor is correct */ +// #define CONFIG_USBDEV_DESC_CHECK + +/* Enable test mode */ +// #define CONFIG_USBDEV_TEST_MODE + +/* enable advance desc register api */ +#define CONFIG_USBDEV_ADVANCE_DESC + +/* move ep0 setup handler from isr to thread */ +// #define CONFIG_USBDEV_EP0_THREAD + +#ifndef CONFIG_USBDEV_EP0_PRIO +#define CONFIG_USBDEV_EP0_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_EP0_STACKSIZE +#define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_LUN +#define CONFIG_USBDEV_MSC_MAX_LUN 1 +#endif + +#ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#endif + +#ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#endif + +#ifndef CONFIG_USBDEV_MSC_VERSION_STRING +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#endif + +/* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ +// #define CONFIG_USBDEV_MSC_POLLING + +/* move msc read & write from isr to thread */ +// #define CONFIG_USBDEV_MSC_THREAD + +#ifndef CONFIG_USBDEV_MSC_PRIO +#define CONFIG_USBDEV_MSC_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MSC_STACKSIZE +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE +#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS +#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#endif + +#ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME +#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#endif + +#define CONFIG_USBDEV_MTP_THREAD + +#ifndef CONFIG_USBDEV_MTP_PRIO +#define CONFIG_USBDEV_MTP_PRIO 4 +#endif + +#ifndef CONFIG_USBDEV_MTP_STACKSIZE +#define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#endif + +/* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ +#ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#endif + +#ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#endif + +#define CONFIG_USBDEV_RNDIS_USING_LWIP +#define CONFIG_USBDEV_CDC_ECM_USING_LWIP + +/* ================ USB HOST Stack Configuration ================== */ + +#define CONFIG_USBHOST_MAX_RHPORTS 1 +#define CONFIG_USBHOST_MAX_EXTHUBS 1 +#define CONFIG_USBHOST_MAX_EHPORTS 4 +#define CONFIG_USBHOST_MAX_INTERFACES 8 +#define CONFIG_USBHOST_MAX_INTF_ALTSETTINGS 8 +#define CONFIG_USBHOST_MAX_ENDPOINTS 4 + +#define CONFIG_USBHOST_MAX_CDC_ACM_CLASS 4 +#define CONFIG_USBHOST_MAX_HID_CLASS 4 +#define CONFIG_USBHOST_MAX_MSC_CLASS 2 +#define CONFIG_USBHOST_MAX_AUDIO_CLASS 1 +#define CONFIG_USBHOST_MAX_VIDEO_CLASS 1 + +#define CONFIG_USBHOST_DEV_NAMELEN 16 + +#ifndef CONFIG_USBHOST_PSC_PRIO +#define CONFIG_USBHOST_PSC_PRIO 0 +#endif +#ifndef CONFIG_USBHOST_PSC_STACKSIZE +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#endif + +//#define CONFIG_USBHOST_GET_STRING_DESC + +// #define CONFIG_USBHOST_MSOS_ENABLE +#ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#endif + +/* Ep0 max transfer buffer */ +#ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#endif + +#ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#endif + +#ifndef CONFIG_USBHOST_MSC_TIMEOUT +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#endif + +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#endif + +/* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, + * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. + */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#endif +/* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ +#ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#endif + +#define CONFIG_USBHOST_BLUETOOTH_HCI_H4 +// #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG + +#ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#endif +#ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#endif + +/* ================ USB Device Port Configuration ================*/ + +#ifndef CONFIG_USBDEV_MAX_BUS +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#endif + +#ifndef CONFIG_USBDEV_EP_NUM +#define CONFIG_USBDEV_EP_NUM 8 +#endif + +// #define CONFIG_USBDEV_SOF_ENABLE + +/* When your chip hardware supports high-speed and wants to initialize it in high-speed mode, + * the relevant IP will configure the internal or external high-speed PHY according to CONFIG_USB_HS. + * +*/ +//#define CONFIG_USB_HS + +/* ---------------- DWC2 Configuration ---------------- */ +/* enable dwc2 buffer dma mode for device +*/ +// #define CONFIG_USB_DWC2_DMA_ENABLE + +/* Defined FS Core device FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE (32) + +/* Defined FS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) + +/* Defined FS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (640) + +/* Defined HS Core Device FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE (1024) +#define CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE (0) + +/* Defined HS Core host FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE (512) +#define CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE (256) + +/* Defined HS Core total FIFO Size in words 32-bits */ +#define CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE (2048) + + +/* ================ USB Host Port Configuration ==================*/ +#ifndef CONFIG_USBHOST_MAX_BUS +#define CONFIG_USBHOST_MAX_BUS 1 +#endif + +#ifndef CONFIG_USBHOST_PIPE_NUM +#define CONFIG_USBHOST_PIPE_NUM 10 +#endif + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/bsp_compile_ci.bat b/bsp/hc32/ev_hc32f4a2_lqfp176/bsp_compile_ci.bat new file mode 100644 index 00000000000..c0cd921b13b --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/bsp_compile_ci.bat @@ -0,0 +1,132 @@ +scons --attach=devices.adc +scons -j4 +scons --attach=default + +scons --attach=devices.can +scons -j4 +scons --attach=default + +scons --attach=devices.crypto +scons -j4 +scons --attach=default + +scons --attach=devices.dac +scons -j4 +scons --attach=default + +scons --attach=devices.flash +scons -j4 +scons --attach=default + +scons --attach=devices.gpio +scons -j4 +scons --attach=default + +scons --attach=devices.clock_timer +scons -j4 +scons --attach=default + +scons --attach=devices.i2c +scons -j4 +scons --attach=default + +scons --attach=devices.input_capture +scons -j4 +scons --attach=default + +scons --attach=devices.pm +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pulse_encoder_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr4 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmr6 +scons -j4 +scons --attach=default + +scons --attach=devices.pwm_tmra +scons -j4 +scons --attach=default + +scons --attach=devices.qspi +scons -j4 +scons --attach=default + +scons --attach=devices.rtc +scons -j4 +scons --attach=default + +scons --attach=devices.sdio +scons -j4 +scons --attach=default + +scons --attach=devices.soft_i2c +scons -j4 +scons --attach=default + +scons --attach=devices.spi +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v1 +scons -j4 +scons --attach=default + +scons --attach=devices.uart_v2 +scons -j4 +scons --attach=default + +scons --attach=devices.usb_hs_device +scons -j4 +scons --attach=default + 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$TOOLKIT_DIR$\plugins\rtos\embOS\embOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\FreeRtos\FreeRtosArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\HWRTOSplugin\HWRTOSplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\Mbed\MbedArmPlugin2.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\OpenRTOS\OpenRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\RemedyRtosViewer\RemedyRtosViewer.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SafeRTOS\SafeRTOSPlugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\SMX\smxAwareIarArm8BE.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\ThreadX\ThreadXArmPlugin.ENU.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\TI-RTOS\tirtosplugin.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-286-KA-CSpy.ewplugin + 0 + + + $TOOLKIT_DIR$\plugins\rtos\uCOS-II\uCOS-II-KA-CSpy.ewplugin + 0 + + + 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00000000000..b1b8fca00b4 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/project.ewp @@ -0,0 +1,2298 @@ + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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+ + + DeviceDrivers + + $PROJ_DIR$\..\..\..\components\drivers\core\device.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_bit_ops.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_core.c + + + $PROJ_DIR$\..\..\..\components\drivers\i2c\dev_i2c_dev.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_comm.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\completion_up.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\condvar.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\dataqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\pipe.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringblk_buf.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\ringbuffer.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\waitqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\ipc\workqueue.c + + + $PROJ_DIR$\..\..\..\components\drivers\pin\dev_pin.c + + + $PROJ_DIR$\..\..\..\components\drivers\serial\dev_serial.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\board_config.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_common.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_gpio.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_i2c.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_irq.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_soft_i2c.c + + + $PROJ_DIR$\..\libraries\hc32_drivers\drv_usart.c + + + + Finsh + + $PROJ_DIR$\..\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\..\components\finsh\msh_parse.c + + + $PROJ_DIR$\..\..\..\components\finsh\cmd.c + + + + HC32F4A2-LL + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_aos.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_clk.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_dma.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_efm.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_fcg.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_gpio.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_icg.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_interrupts.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_pwc.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_rmu.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_sram.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_utility.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32f4a2_ll_interrupts_share.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_usart.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_tmr0.c + + + $PROJ_DIR$\packages\hc32-f4-series-latest\hc32f4a2\src\hc32_ll_i2c.c + + + + Kernel + + $PROJ_DIR$\..\..\..\src\clock.c + + + $PROJ_DIR$\..\..\..\src\components.c + + + $PROJ_DIR$\..\..\..\src\cpu_up.c + + + $PROJ_DIR$\..\..\..\src\defunct.c + + + $PROJ_DIR$\..\..\..\src\idle.c + + + $PROJ_DIR$\..\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\..\src\irq.c + + + $PROJ_DIR$\..\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\..\src\mem.c + + + $PROJ_DIR$\..\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\..\src\object.c + + + $PROJ_DIR$\..\..\..\src\scheduler_comm.c + + + $PROJ_DIR$\..\..\..\src\scheduler_up.c + + + $PROJ_DIR$\..\..\..\src\thread.c + + + $PROJ_DIR$\..\..\..\src\timer.c + + + + Libc + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cctype.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstdlib.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cstring.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\ctime.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cunistd.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\common\cwchar.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscall_write.c + + + $PROJ_DIR$\..\..\..\components\libc\compilers\dlib\syscalls.c + + + $PROJ_DIR$\..\..\..\src\klibc\kerrno.c + + + $PROJ_DIR$\..\..\..\src\klibc\kstdio.c + + + $PROJ_DIR$\..\..\..\src\klibc\kstring.c + + + $PROJ_DIR$\..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + $PROJ_DIR$\..\..\..\src\klibc\rt_vsscanf.c + + + + Libraries + + $PROJ_DIR$\packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f4a2\Source\system_hc32f4a2.c + + + $PROJ_DIR$\packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f4a2\Source\IAR\startup_hc32f4a2.s + + + + Platform + + $PROJ_DIR$\..\platform\tca9539\tca9539.c + + + + utc_UTest + + + utestcases + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/project.eww b/bsp/hc32/ev_hc32f4a2_lqfp176/project.eww new file mode 100644 index 00000000000..c2cb02eb1e8 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/project.uvoptx b/bsp/hc32/ev_hc32f4a2_lqfp176/project.uvoptx new file mode 100644 index 00000000000..5c85161ee63 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/project.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2 -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM)) + + + 0 + JL2CM3 + -U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/project.uvprojx b/bsp/hc32/ev_hc32f4a2_lqfp176/project.uvprojx new file mode 100644 index 00000000000..b14b2030b43 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/project.uvprojx @@ -0,0 +1,1351 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F4A2SITB + HDSC + HDSC.HC32F4A2.1.0.8 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM(0x00000000,0x200000) IRAM(0x1FFE0000,0x80000) IRAM2(0X200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(240000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2 -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM)) + 0 + $$Device:HC32F4A2SITB$Device\Include\HC32F4A2SITB.h + + + + + + + + + + ./packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f4a2/Source/ARM/sfr/HC32F4A2.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL 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__CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, HC32F4A2, RT_USING_ARMLIBC, __DEBUG + + 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..\..\..\src\klibc\rt_vsnprintf_tiny.c + + + + + rt_vsscanf.c + 1 + ..\..\..\src\klibc\rt_vsscanf.c + + + + + Libraries + + + system_hc32f4a2.c + 1 + packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f4a2\Source\system_hc32f4a2.c + + + + + startup_hc32f4a2.s + 2 + packages\hc32-f4-cmsis-latest\Device\HDSC\hc32f4a2\Source\ARM\startup_hc32f4a2.s + + + + + Platform + + + tca9539.c + 1 + ..\platform\tca9539\tca9539.c + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.h b/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.h new file mode 100644 index 00000000000..26d583f8724 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.h @@ -0,0 +1,446 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* RT-Thread Kernel */ + +/* klibc options */ + +/* rt_vsnprintf options */ + +/* end of rt_vsnprintf options */ + +/* rt_vsscanf options */ + +/* end of rt_vsscanf options */ + +/* rt_memset options */ + +/* end of rt_memset options */ + +/* rt_memcpy options */ + +/* end of rt_memcpy options */ + +/* rt_memmove options */ + +/* end of rt_memmove options */ + +/* rt_memcmp options */ + +/* end of rt_memcmp options */ + +/* rt_strstr options */ + +/* end of rt_strstr options */ + +/* rt_strcasecmp options */ + +/* end of rt_strcasecmp options */ + +/* rt_strncpy options */ + +/* end of rt_strncpy options */ + +/* rt_strcpy options */ + +/* end of rt_strcpy options */ + +/* rt_strncmp options */ + +/* end of rt_strncmp options */ + +/* rt_strcmp options */ + +/* end of rt_strcmp options */ + +/* rt_strlen options */ + +/* end of rt_strlen options */ + +/* rt_strnlen options */ + +/* end of rt_strnlen options */ +/* end of klibc options */ +#define RT_NAME_MAX 24 +#define RT_CPUS_NR 1 +#define RT_ALIGN_SIZE 8 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 512 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 + +/* kservice options */ + +/* end of kservice options */ +#define RT_USING_DEBUG +#define RT_DEBUGING_ASSERT +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE +/* end of Inter-Thread communication */ + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_HEAP +/* end of Memory Management */ +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_USING_CONSOLE_OUTPUT_CTL +#define RT_VER_NUM 0x50300 +#define RT_BACKTRACE_LEVEL_MAX_NR 32 +/* end of RT-Thread Kernel */ +#define RT_USING_HW_ATOMIC +#define ARCH_USING_HW_ATOMIC_8 +#define ARCH_USING_HW_ATOMIC_16 +#define RT_USING_CPU_FFS +#define ARCH_ARM +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 +#define FINSH_USING_OPTION_COMPLETION + +/* DFS: device virtual file system */ + +/* end of DFS: device virtual file system */ + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_I2C +#define RT_USING_I2C_BITOPS +#define RT_USING_PIN +/* end of Device Drivers */ + +/* C/C++ and POSIX layer */ + +/* ISO-ANSI C layer */ + +/* Timezone and Daylight Saving Time */ + +#define RT_LIBC_USING_LIGHT_TZ_DST +#define RT_LIBC_TZ_DEFAULT_HOUR 8 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 +/* end of Timezone and Daylight Saving Time */ +/* end of ISO-ANSI C layer */ + +/* POSIX (Portable Operating System Interface) layer */ + + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + +/* end of Interprocess Communication (IPC) */ +/* end of POSIX (Portable Operating System Interface) layer */ +/* end of C/C++ and POSIX layer */ + +/* Network */ + +/* end of Network */ + +/* Memory protection */ + +/* end of Memory protection */ + +/* Utilities */ + +/* end of Utilities */ + +/* Using USB legacy version */ + +/* end of Using USB legacy version */ +/* end of RT-Thread Components */ + +/* RT-Thread Utestcases */ + +/* end of RT-Thread Utestcases */ + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + +/* end of Marvell WiFi */ + +/* Wiced WiFi */ + +/* end of Wiced WiFi */ + +/* CYW43012 WiFi */ + +/* end of CYW43012 WiFi */ + +/* BL808 WiFi */ + +/* end of BL808 WiFi */ + +/* CYW43439 WiFi */ + +/* end of CYW43439 WiFi */ +/* end of Wi-Fi */ + +/* IoT Cloud */ + +/* end of IoT Cloud */ +/* end of IoT - internet of things */ + +/* security packages */ + +/* end of security packages */ + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* end of JSON: JavaScript Object Notation, a lightweight data-interchange format */ + +/* XML: Extensible Markup Language */ + +/* end of XML: Extensible Markup Language */ +/* end of language packages */ + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + +/* end of LVGL: powerful and easy-to-use embedded GUI library */ + +/* u8g2: a monochrome graphic library */ + +/* end of u8g2: a monochrome graphic library */ +/* end of multimedia packages */ + +/* tools packages */ + +/* end of tools packages */ + +/* system packages */ + +/* enhanced kernel services */ + +/* end of enhanced kernel services */ + +/* acceleration: Assembly language or algorithmic acceleration packages */ + +/* end of acceleration: Assembly language or algorithmic acceleration packages */ + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* end of CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + +/* Micrium: Micrium software products porting for RT-Thread */ + +/* end of Micrium: Micrium software products porting for RT-Thread */ +/* end of system packages */ + +/* peripheral libraries and drivers */ + +/* HAL & SDK Drivers */ + +/* STM32 HAL & SDK Drivers */ + +/* end of STM32 HAL & SDK Drivers */ + +/* Infineon HAL Packages */ + +/* end of Infineon HAL Packages */ + +/* Kendryte SDK */ + +/* end of Kendryte SDK */ + +/* WCH HAL & SDK Drivers */ + +/* end of WCH HAL & SDK Drivers */ + +/* AT32 HAL & SDK Drivers */ + +/* end of AT32 HAL & SDK Drivers */ + +/* HC32 DDL Drivers */ + +#define PKG_USING_HC32F4_CMSIS_DRIVER +#define PKG_USING_HC32F4_CMSIS_DRIVER_LATEST_VERSION +#define PKG_USING_HC32F4_SERIES_DRIVER +#define PKG_USING_HC32F4_SERIES_DRIVER_LATEST_VERSION +/* end of HC32 DDL Drivers */ + +/* NXP HAL & SDK Drivers */ + +/* end of NXP HAL & SDK Drivers */ + +/* NUVOTON Drivers */ + +/* end of NUVOTON Drivers */ + +/* GD32 Drivers */ + +/* end of GD32 Drivers */ +/* end of HAL & SDK Drivers */ + +/* sensors drivers */ + +/* end of sensors drivers */ + +/* touch drivers */ + +/* end of touch drivers */ +/* end of peripheral libraries and drivers */ + +/* AI packages */ + +/* end of AI packages */ + +/* Signal Processing and Control Algorithm Packages */ + +/* end of Signal Processing and Control Algorithm Packages */ + +/* miscellaneous packages */ + +/* project laboratory */ + +/* end of project laboratory */ + +/* samples: kernel and components samples */ + +/* end of samples: kernel and components samples */ + +/* entertainment: terminal games and other interesting software packages */ + +/* end of entertainment: terminal games and other interesting software packages */ +/* end of miscellaneous packages */ + +/* Arduino libraries */ + + +/* Projects and Demos */ + +/* end of Projects and Demos */ + +/* Sensors */ + +/* end of Sensors */ + +/* Display */ + +/* end of Display */ + +/* Timing */ + +/* end of Timing */ + +/* Data Processing */ + +/* end of Data Processing */ + +/* Data Storage */ + +/* Communication */ + +/* end of Communication */ + +/* Device Control */ + +/* end of Device Control */ + +/* Other */ + +/* end of Other */ + +/* Signal IO */ + +/* end of Signal IO */ + +/* Uncategorized */ + +/* end of Arduino libraries */ +/* end of RT-Thread online packages */ +#define SOC_FAMILY_HC32 +#define SOC_SERIES_HC32F4 + +/* Hardware Drivers Config */ + +#define SOC_HC32F4A2SI + +/* On-chip Drivers */ + +#define BSP_USING_ON_CHIP_FLASH_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_DCODE_CACHE +#define BSP_USING_ON_CHIP_FLASH_ICODE_PREFETCH +/* end of On-chip Drivers */ + +/* Onboard Peripheral Drivers */ + +#define BSP_USING_TCA9539 +#define BSP_USING_EXT_IO +/* end of Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +#define BSP_USING_I2C +#define BSP_USING_I2C_HW +#define BSP_USING_I2C1 +/* end of On-chip Peripheral Drivers */ + +/* Board extended module Drivers */ + +/* end of Hardware Drivers Config */ + +#endif diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.py b/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.py new file mode 100644 index 00000000000..0af49fd02b7 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/rtconfig.py @@ -0,0 +1,150 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='gcc' + +# bsp lib config +BSP_LIBRARY_TYPE = None + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + else: + EXEC_PATH = r'C:/Users/XXYYZZ' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'C:/Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iccarm' + EXEC_PATH = r'C:/Program Files (x86)/IAR Systems/Embedded Workbench 8.4' + +BUILD = 'debug' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + CXX = PREFIX + 'g++' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -Dgcc' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.ld' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2 -g' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + CXX = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu Cortex-M4.fp ' + CFLAGS = '-c ' + DEVICE + ' --apcs=interwork --c99' + AFLAGS = DEVICE + ' --apcs=interwork ' + LFLAGS = DEVICE + r' --scatter "board\linker_scripts\link.sct" --info sizes --info totals --info unused --info veneers --list rtthread.map --strict' + CFLAGS += ' -I' + EXEC_PATH + '/ARM/ARMCC/include' + LFLAGS += ' --libpath=' + EXEC_PATH + '/ARM/ARMCC/lib' + + CFLAGS += ' -D__MICROLIB ' + AFLAGS += ' --pd "__MICROLIB SETA 1" ' + LFLAGS += ' --library_type=microlib ' + EXEC_PATH += '/ARM/ARMCC/bin/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + CXXFLAGS = CFLAGS + CFLAGS += ' -std=c99' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iccarm': + # toolchains + CC = 'iccarm' + CXX = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = '-Dewarm' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=VFPv4_sp' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' --silent' + + AFLAGS = DEVICE + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu VFPv4_sp' + AFLAGS += ' -S' + + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --entry __iar_program_start' + + CXXFLAGS = CFLAGS + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = 'ielftool --bin $TARGET rtthread.bin' + +def dist_handle(BSP_ROOT, dist_dir): + import sys + cwd_path = os.getcwd() + sys.path.append(os.path.join(os.path.dirname(BSP_ROOT), 'tools')) + from sdk_dist import dist_do_building + dist_do_building(BSP_ROOT, dist_dir) diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/template.ewp b/bsp/hc32/ev_hc32f4a2_lqfp176/template.ewp new file mode 100644 index 00000000000..8283992a555 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/template.ewp @@ -0,0 +1,1927 @@ + + + + 2 + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/template.eww b/bsp/hc32/ev_hc32f4a2_lqfp176/template.eww new file mode 100644 index 00000000000..bd036bb4c98 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvoptx b/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvoptx new file mode 100644 index 00000000000..5c85161ee63 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvoptx @@ -0,0 +1,189 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 8000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\keil\List\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 3 + + + + + + + + + + + BIN\CMSIS_AGDI.dll + + + + 0 + CMSIS_AGDI + -X"Any" -UAny -O206 -S0 -C0 -P00 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO65554 -TC10000000 -TT10000000 -TP20 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM) + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2 -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM)) + + + 0 + JL2CM3 + -U261009725 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -TO18 -TC10000000 -TP21 -TDS8000 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO15 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2_2M.FLM -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM) + + + + + 0 + + + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + 1 + 0 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvprojx b/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvprojx new file mode 100644 index 00000000000..6e4e85d5eb5 --- /dev/null +++ b/bsp/hc32/ev_hc32f4a2_lqfp176/template.uvprojx @@ -0,0 +1,390 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060750::V5.06 update 6 (build 750)::ARMCC + 0 + + + HC32F4A2SITB + HDSC + HDSC.HC32F4A2.1.0.8 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM(0x00000000,0x200000) IRAM(0x1FFE0000,0x80000) IRAM2(0X200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(240000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A2 -FS00 -FL0200000 -FP0($$Device:HC32F4A2SITB$FlashARM\HC32F4A2_2M.FLM)) + 0 + $$Device:HC32F4A2SITB$Device\Include\HC32F4A2SITB.h + + + + + + + + + + ./packages/hc32-f4-cmsis-latest/Device/HDSC/hc32f4a2/Source/ARM/sfr/HC32F4A2.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rt-thread + 1 + 0 + 1 + 1 + 0 + .\build\keil\List\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 0 + 1 + 0 + 8 + 0 + 1 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFE0000 + 0x80000 + + + 1 + 0x0 + 0x200000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x200000 + + + 1 + 0x03000000 + 0x1800 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1FFE0000 + 0x80000 + + + 0 + 0x200F0000 + 0x1000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFE0000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + + + + + + + + diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml b/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml index e5798b47293..66e9f4c0b4b 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/.ci/attachconfig/ci.attachconfig.yml @@ -29,11 +29,11 @@ devices.flash: - CONFIG_RT_USING_SPI=y - CONFIG_RT_USING_SFUD=y devices.gpio: - kconfig: + kconfig: - CONFIG_BSP_USING_GPIO=y -devices.hwtimer: +devices.clock_timer: kconfig: - - CONFIG_BSP_USING_HWTIMER=y + - CONFIG_BSP_USING_CLOCK_TIMER=y - CONFIG_BSP_USING_TMRA_1=y devices.i2c: kconfig: diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/.config b/bsp/hc32/ev_hc32f4a8_lqfp176/.config index ada89e85af5..580adf9517f 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/.config +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/.config @@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/README.md b/bsp/hc32/ev_hc32f4a8_lqfp176/README.md index 65d551688a7..a9354c0e4e6 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/README.md +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/README.md @@ -52,7 +52,7 @@ EV_F4A8_LQ176 开发板常用 **板载资源** 如下： | DAC | 支持 | | | FLASH | 支持 | | | GPIO | 支持 | PA0，PA1...PI13 ---> PIN：0，1...141 | -| HwTimer | 支持 | | +| CLOCK_TIMER | 支持 | | | I2C | 支持 | 软件、硬件 I2C | | InputCapture | 支持 | | | MCAN | 支持 | | diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/applications/xtal32_fcm.c b/bsp/hc32/ev_hc32f4a8_lqfp176/applications/xtal32_fcm.c index 11df23379ba..61e25e56030 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/applications/xtal32_fcm.c +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/applications/xtal32_fcm.c @@ -18,8 +18,8 @@ #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) -#define XTAL32_FCM_THREAD_STACK_SIZE (1024) -#define XTAL32_FCM_UNIT (CM_FCM1) +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM1) /** * @brief This thread is used to monitor whether XTAL32 is stable. @@ -36,13 +36,13 @@ void xtal32_fcm_thread_entry(void *parameter) /* FCM config */ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); (void)FCM_StructInit(&stcFcmInit); - stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; - stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ - stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; - stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; - stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); - stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); /* Enable FCM, to ensure xtal32 stable */ FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig b/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig index 9d0e00a67cf..b54cb335182 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/Kconfig @@ -962,45 +962,45 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_CLOCK_TIMER - bool "Enable Hw Timer" + bool "Enable Clock Timer" default n select RT_USING_CLOCK_TIME if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 - bool "Use Timer_a1 As The Hw Timer" + bool "Use Timer_a1 As The Clock Timer" default n config BSP_USING_TMRA_2 - bool "Use Timer_a2 As The Hw Timer" + bool "Use Timer_a2 As The Clock Timer" default n config BSP_USING_TMRA_3 - bool "Use Timer_a3 As The Hw Timer" + bool "Use Timer_a3 As The Clock Timer" default n config BSP_USING_TMRA_4 - bool "Use Timer_a4 As The Hw Timer" + bool "Use Timer_a4 As The Clock Timer" default n config BSP_USING_TMRA_5 - bool "Use Timer_a5 As The Hw Timer" + bool "Use Timer_a5 As The Clock Timer" default n config BSP_USING_TMRA_6 - bool "Use Timer_a6 As The Hw Timer" + bool "Use Timer_a6 As The Clock Timer" default n config BSP_USING_TMRA_7 - bool "Use Timer_a7 As The Hw Timer" + bool "Use Timer_a7 As The Clock Timer" default n config BSP_USING_TMRA_8 - bool "Use Timer_a8 As The Hw Timer" + bool "Use Timer_a8 As The Clock Timer" default n config BSP_USING_TMRA_9 - bool "Use Timer_a9 As The Hw Timer" + bool "Use Timer_a9 As The Clock Timer" default n config BSP_USING_TMRA_10 - bool "Use Timer_a10 As The Hw Timer" + bool "Use Timer_a10 As The Clock Timer" default n config BSP_USING_TMRA_11 - bool "Use Timer_a11 As The Hw Timer" + bool "Use Timer_a11 As The Clock Timer" default n config BSP_USING_TMRA_12 - bool "Use Timer_a12 As The Hw Timer" + bool "Use Timer_a12 As The Clock Timer" default n endif menuconfig BSP_USING_INPUT_CAPTURE diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.c b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.c index 4a2e0ccce65..c326bc49566 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.c +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.c @@ -13,9 +13,9 @@ #include "board_config.h" /* unlock/lock peripheral */ -#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ - LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) -#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) /** System Base Configuration */ @@ -51,17 +51,17 @@ void SystemClock_Config(void) /* PCLK1, PCLK4 Max 120MHz */ /* PCLK2, PCLK3 Max 60MHz */ /* EX BUS Max 120MHz */ - CLK_SetClockDiv(CLK_BUS_CLK_ALL, \ - (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \ - CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 | \ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV4 | CLK_HCLK_DIV1)); GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); (void)CLK_XtalStructInit(&stcXtalInit); /* Config Xtal and enable Xtal */ - stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; - stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; - stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; (void)CLK_XtalInit(&stcXtalInit); @@ -105,8 +105,8 @@ void SystemClock_Config(void) /* Xtal32 config */ GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); (void)CLK_Xtal32StructInit(&stcXtal32Init); - stcXtal32Init.u8State = CLK_XTAL32_ON; - stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; (void)CLK_Xtal32Init(&stcXtal32Init); #endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.h index 125fbcd9b8c..905674bce47 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board.h @@ -20,27 +20,27 @@ extern "C" { #endif -#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) -#define HC32_FLASH_WRITE_GRANULARITY (16) -#define HC32_FLASH_SIZE (2 * 1024 * 1024) -#define HC32_FLASH_START_ADDRESS (0) -#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) +#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (16) +#define HC32_FLASH_SIZE (2 * 1024 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) -#define HC32_SRAM_SIZE (512) -#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) +#define HC32_SRAM_SIZE (512) +#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) #ifdef __ARMCC_VERSION extern int Image$$RW_IRAM2$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) #elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) #else extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) +#define HEAP_BEGIN (&__bss_end) #endif -#define HEAP_END HC32_SRAM_END +#define HEAP_END HC32_SRAM_END void PeripheralRegister_Unlock(void); void PeripheralClock_Config(void); diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c index 9aa7eb65d2a..e5c8ef58114 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.c @@ -145,12 +145,12 @@ rt_err_t rt_hw_board_dac_init(CM_DAC_TypeDef *DACx) #if defined(RT_USING_CAN) void CanPhyEnable(void) { -#if defined(BSP_USING_CAN1) || defined (BSP_USING_MCAN1) +#if defined(BSP_USING_CAN1) || defined(BSP_USING_MCAN1) TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_SET); TCA9539_ConfigPin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_DIR_OUT); TCA9539_WritePin(CAN1_STB_PORT, CAN1_STB_PIN, TCA9539_PIN_RESET); #endif -#if defined(BSP_USING_CAN2) || defined (BSP_USING_MCAN2) +#if defined(BSP_USING_CAN2) || defined(BSP_USING_MCAN2) TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_SET); TCA9539_ConfigPin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_DIR_OUT); TCA9539_WritePin(CAN2_STB_PORT, CAN2_STB_PIN, TCA9539_PIN_RESET); @@ -213,7 +213,7 @@ rt_err_t rt_hw_board_mcan_init(CM_MCAN_TypeDef *MCANx) #endif -#if defined (RT_USING_SPI) +#if defined(RT_USING_SPI) rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) { rt_err_t result = RT_EOK; @@ -227,17 +227,17 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) case (rt_uint32_t)CM_SPI1: GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinState = PIN_STAT_SET; - stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinDir = PIN_DIR_OUT; GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; - (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); - GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); break; @@ -253,14 +253,14 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) #if defined(BSP_USING_ETH) /* PHY hardware reset time */ -#define PHY_HW_RST_DELAY (0x40U) +#define PHY_HW_RST_DELAY (0x40U) rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) { TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT); - TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); rt_thread_mdelay(PHY_HW_RST_DELAY); - TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); rt_thread_mdelay(PHY_HW_RST_DELAY); return RT_EOK; } @@ -268,39 +268,39 @@ rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx) { #if defined(ETH_INTERFACE_USING_RMII) - GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); - GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); - GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); - GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); - GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); + GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); + GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); GPIO_SetFunc(ETH_RMII_REF_CLK_PORT, ETH_RMII_REF_CLK_PIN, ETH_RMII_REF_CLK_FUNC); - GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); - GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); - GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); + GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); + GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); + GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); #else - GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); - GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); GPIO_SetFunc(ETH_MII_TX_CLK_PORT, ETH_MII_TX_CLK_PIN, ETH_MII_TX_CLK_FUNC); - GPIO_SetFunc(ETH_MII_TX_EN_PORT, ETH_MII_TX_EN_PIN, ETH_MII_TX_EN_FUNC); - GPIO_SetFunc(ETH_MII_TXD0_PORT, ETH_MII_TXD0_PIN, ETH_MII_TXD0_FUNC); - GPIO_SetFunc(ETH_MII_TXD1_PORT, ETH_MII_TXD1_PIN, ETH_MII_TXD1_FUNC); - GPIO_SetFunc(ETH_MII_TXD2_PORT, ETH_MII_TXD2_PIN, ETH_MII_TXD2_FUNC); - GPIO_SetFunc(ETH_MII_TXD3_PORT, ETH_MII_TXD3_PIN, ETH_MII_TXD3_FUNC); + GPIO_SetFunc(ETH_MII_TX_EN_PORT, ETH_MII_TX_EN_PIN, ETH_MII_TX_EN_FUNC); + GPIO_SetFunc(ETH_MII_TXD0_PORT, ETH_MII_TXD0_PIN, ETH_MII_TXD0_FUNC); + GPIO_SetFunc(ETH_MII_TXD1_PORT, ETH_MII_TXD1_PIN, ETH_MII_TXD1_FUNC); + GPIO_SetFunc(ETH_MII_TXD2_PORT, ETH_MII_TXD2_PIN, ETH_MII_TXD2_FUNC); + GPIO_SetFunc(ETH_MII_TXD3_PORT, ETH_MII_TXD3_PIN, ETH_MII_TXD3_FUNC); GPIO_SetFunc(ETH_MII_RX_CLK_PORT, ETH_MII_RX_CLK_PIN, ETH_MII_RX_CLK_FUNC); - GPIO_SetFunc(ETH_MII_RX_DV_PORT, ETH_MII_RX_DV_PIN, ETH_MII_RX_DV_FUNC); - GPIO_SetFunc(ETH_MII_RXD0_PORT, ETH_MII_RXD0_PIN, ETH_MII_RXD0_FUNC); - GPIO_SetFunc(ETH_MII_RXD1_PORT, ETH_MII_RXD1_PIN, ETH_MII_RXD1_FUNC); - GPIO_SetFunc(ETH_MII_RXD2_PORT, ETH_MII_RXD2_PIN, ETH_MII_RXD2_FUNC); - GPIO_SetFunc(ETH_MII_RXD3_PORT, ETH_MII_RXD3_PIN, ETH_MII_RXD3_FUNC); - GPIO_SetFunc(ETH_MII_RX_ER_PORT, ETH_MII_RX_ER_PIN, ETH_MII_RX_ER_FUNC); - GPIO_SetFunc(ETH_MII_CRS_PORT, ETH_MII_CRS_PIN, ETH_MII_CRS_FUNC); - GPIO_SetFunc(ETH_MII_COL_PORT, ETH_MII_COL_PIN, ETH_MII_COL_FUNC); + GPIO_SetFunc(ETH_MII_RX_DV_PORT, ETH_MII_RX_DV_PIN, ETH_MII_RX_DV_FUNC); + GPIO_SetFunc(ETH_MII_RXD0_PORT, ETH_MII_RXD0_PIN, ETH_MII_RXD0_FUNC); + GPIO_SetFunc(ETH_MII_RXD1_PORT, ETH_MII_RXD1_PIN, ETH_MII_RXD1_FUNC); + GPIO_SetFunc(ETH_MII_RXD2_PORT, ETH_MII_RXD2_PIN, ETH_MII_RXD2_FUNC); + GPIO_SetFunc(ETH_MII_RXD3_PORT, ETH_MII_RXD3_PIN, ETH_MII_RXD3_FUNC); + GPIO_SetFunc(ETH_MII_RX_ER_PORT, ETH_MII_RX_ER_PIN, ETH_MII_RX_ER_FUNC); + GPIO_SetFunc(ETH_MII_CRS_PORT, ETH_MII_CRS_PIN, ETH_MII_CRS_FUNC); + GPIO_SetFunc(ETH_MII_COL_PORT, ETH_MII_COL_PIN, ETH_MII_COL_FUNC); #endif return RT_EOK; } #endif -#if defined (RT_USING_SDIO) +#if defined(RT_USING_SDIO) rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) { rt_err_t result = RT_EOK; @@ -313,19 +313,19 @@ rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) /************************* Set pin drive capacity *************************/ (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; - (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); - GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); + GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC); - GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); - GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); - GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); - GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); + GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); + GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); + GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); + GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); break; #endif default: @@ -434,24 +434,24 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) #endif #endif -#if defined (BSP_USING_INPUT_CAPTURE) +#if defined(BSP_USING_INPUT_CAPTURE) rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) { rt_err_t result = RT_EOK; switch ((rt_uint32_t)tmr_instance) { -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) case (rt_uint32_t)CM_TMR6_1: GPIO_SetFunc(INPUT_CAPTURE_TMR6_1_PORT, INPUT_CAPTURE_TMR6_1_PIN, INPUT_CAPTURE_TMR6_FUNC); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) case (rt_uint32_t)CM_TMR6_2: GPIO_SetFunc(INPUT_CAPTURE_TMR6_2_PORT, INPUT_CAPTURE_TMR6_2_PIN, INPUT_CAPTURE_TMR6_FUNC); break; #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) case (rt_uint32_t)CM_TMR6_3: GPIO_SetFunc(INPUT_CAPTURE_TMR6_3_PORT, INPUT_CAPTURE_TMR6_3_PIN, INPUT_CAPTURE_TMR6_FUNC); break; @@ -464,7 +464,7 @@ rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance) } #endif -#if defined (BSP_USING_SDRAM) +#if defined(BSP_USING_SDRAM) rt_err_t rt_hw_board_sdram_init(void) { rt_err_t result = RT_EOK; @@ -539,16 +539,16 @@ rt_err_t rt_hw_board_sdram_init(void) /* DMC_WE */ GPIO_SetFunc(SDRAM_WE_PORT, SDRAM_WE_PIN, SDRAM_WE_FUNC); /* DMC_DATA[0:15] */ - GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); - GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); - GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); - GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); - GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); - GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); - GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); - GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); - GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); - GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); + GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); + GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); + GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); + GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); + GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); + GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); + GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); + GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); + GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); + GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); GPIO_SetFunc(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, SDRAM_DATA10_FUNC); GPIO_SetFunc(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, SDRAM_DATA11_FUNC); GPIO_SetFunc(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, SDRAM_DATA12_FUNC); @@ -556,16 +556,16 @@ rt_err_t rt_hw_board_sdram_init(void) GPIO_SetFunc(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, SDRAM_DATA14_FUNC); GPIO_SetFunc(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, SDRAM_DATA15_FUNC); /* DMC_ADD[0:12]*/ - GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); - GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); - GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); - GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); - GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); - GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); - GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); - GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); - GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); - GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); + GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); + GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); + GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); + GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); + GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); + GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); + GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); + GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); + GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); + GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); GPIO_SetFunc(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, SDRAM_ADD10_FUNC); GPIO_SetFunc(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, SDRAM_ADD11_FUNC); GPIO_SetFunc(SDRAM_ADD12_PORT, SDRAM_ADD12_PIN, SDRAM_ADD12_FUNC); @@ -653,14 +653,14 @@ rt_err_t rt_hw_usbhs_board_init(void) GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); - GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); - GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); - GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); - GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); - GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); - GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); - GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); - GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); #endif @@ -730,14 +730,14 @@ rt_err_t rt_hw_usbhs_board_init(uint8_t devmode) GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); - GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); - GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); - GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); - GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); - GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); - GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); - GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); - GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); #endif @@ -754,8 +754,8 @@ rt_err_t rt_hw_qspi_board_init(void) (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; #ifndef BSP_QSPI_USING_SOFT_CS - (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); - GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); #endif (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); @@ -796,7 +796,7 @@ rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void) } #endif -#if defined (BSP_USING_NAND) +#if defined(BSP_USING_NAND) rt_err_t rt_hw_board_nand_init(void) { rt_err_t result = RT_EOK; diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.h index 4997929780e..8f8924c20f0 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/board_config.h @@ -16,712 +16,712 @@ #include "hc32_ll.h" #include "drv_config.h" #if defined(RT_USING_CHERRYUSB) - #include "usb_config.h" +#include "usb_config.h" #endif /************************* XTAL port **********************/ -#define XTAL_PORT (GPIO_PORT_H) -#define XTAL_IN_PIN (GPIO_PIN_01) -#define XTAL_OUT_PIN (GPIO_PIN_00) +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_IN_PIN (GPIO_PIN_01) +#define XTAL_OUT_PIN (GPIO_PIN_00) /************************ USART port **********************/ #if defined(BSP_USING_UART1) - #define USART1_RX_PORT (GPIO_PORT_H) - #define USART1_RX_PIN (GPIO_PIN_13) - #define USART1_RX_FUNC (GPIO_FUNC_33) +#define USART1_RX_PORT (GPIO_PORT_H) +#define USART1_RX_PIN (GPIO_PIN_13) +#define USART1_RX_FUNC (GPIO_FUNC_33) - #define USART1_TX_PORT (GPIO_PORT_H) - #define USART1_TX_PIN (GPIO_PIN_15) - #define USART1_TX_FUNC (GPIO_FUNC_32) +#define USART1_TX_PORT (GPIO_PORT_H) +#define USART1_TX_PIN (GPIO_PIN_15) +#define USART1_TX_FUNC (GPIO_FUNC_32) #endif #if defined(BSP_USING_UART6) - #define USART6_RX_PORT (GPIO_PORT_D) - #define USART6_RX_PIN (GPIO_PIN_06) - #define USART6_RX_FUNC (GPIO_FUNC_37) +#define USART6_RX_PORT (GPIO_PORT_D) +#define USART6_RX_PIN (GPIO_PIN_06) +#define USART6_RX_FUNC (GPIO_FUNC_37) - #define USART6_TX_PORT (GPIO_PORT_E) - #define USART6_TX_PIN (GPIO_PIN_06) - #define USART6_TX_FUNC (GPIO_FUNC_36) +#define USART6_TX_PORT (GPIO_PORT_E) +#define USART6_TX_PIN (GPIO_PIN_06) +#define USART6_TX_FUNC (GPIO_FUNC_36) #endif /************************ I2C port **********************/ #if defined(BSP_USING_I2C1) - #define I2C1_SDA_PORT (GPIO_PORT_F) - #define I2C1_SDA_PIN (GPIO_PIN_10) - #define I2C1_SDA_FUNC (GPIO_FUNC_48) +#define I2C1_SDA_PORT (GPIO_PORT_F) +#define I2C1_SDA_PIN (GPIO_PIN_10) +#define I2C1_SDA_FUNC (GPIO_FUNC_48) - #define I2C1_SCL_PORT (GPIO_PORT_D) - #define I2C1_SCL_PIN (GPIO_PIN_03) - #define I2C1_SCL_FUNC (GPIO_FUNC_49) +#define I2C1_SCL_PORT (GPIO_PORT_D) +#define I2C1_SCL_PIN (GPIO_PIN_03) +#define I2C1_SCL_FUNC (GPIO_FUNC_49) #endif /*********** ADC configure *********/ #if defined(BSP_USING_ADC1) - #define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */ - #define ADC1_CH_PIN (GPIO_PIN_00) +#define ADC1_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN10 */ +#define ADC1_CH_PIN (GPIO_PIN_00) #endif #if defined(BSP_USING_ADC2) - #define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */ - #define ADC2_CH_PIN (GPIO_PIN_01) +#define ADC2_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN11 */ +#define ADC2_CH_PIN (GPIO_PIN_01) #endif #if defined(BSP_USING_ADC3) - #define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */ - #define ADC3_CH_PIN (GPIO_PIN_02) +#define ADC3_CH_PORT (GPIO_PORT_C) /* Default ADC123_IN12 */ +#define ADC3_CH_PIN (GPIO_PIN_02) #endif /*********** DAC configure *********/ #if defined(BSP_USING_DAC1) - #define DAC1_CH1_PORT (GPIO_PORT_A) - #define DAC1_CH1_PIN (GPIO_PIN_04) - #define DAC1_CH2_PORT (GPIO_PORT_A) - #define DAC1_CH2_PIN (GPIO_PIN_05) +#define DAC1_CH1_PORT (GPIO_PORT_A) +#define DAC1_CH1_PIN (GPIO_PIN_04) +#define DAC1_CH2_PORT (GPIO_PORT_A) +#define DAC1_CH2_PIN (GPIO_PIN_05) #endif #if defined(BSP_USING_DAC2) - #define DAC2_CH1_PORT (GPIO_PORT_C) - #define DAC2_CH1_PIN (GPIO_PIN_04) - #define DAC2_CH2_PORT (GPIO_PORT_C) - #define DAC2_CH2_PIN (GPIO_PIN_05) +#define DAC2_CH1_PORT (GPIO_PORT_C) +#define DAC2_CH1_PIN (GPIO_PIN_04) +#define DAC2_CH2_PORT (GPIO_PORT_C) +#define DAC2_CH2_PIN (GPIO_PIN_05) #endif /*********** CAN/MCAN configure *********/ #if defined(BSP_USING_CAN1) - #define CAN1_TX_PORT (GPIO_PORT_I) - #define CAN1_TX_PIN (GPIO_PIN_12) - #define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) +#define CAN1_TX_PORT (GPIO_PORT_I) +#define CAN1_TX_PIN (GPIO_PIN_12) +#define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) - #define CAN1_RX_PORT (GPIO_PORT_G) - #define CAN1_RX_PIN (GPIO_PIN_07) - #define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) +#define CAN1_RX_PORT (GPIO_PORT_G) +#define CAN1_RX_PIN (GPIO_PIN_07) +#define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) #endif #if defined(BSP_USING_CAN2) - #define CAN2_TX_PORT (GPIO_PORT_G) - #define CAN2_TX_PIN (GPIO_PIN_09) - #define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) +#define CAN2_TX_PORT (GPIO_PORT_G) +#define CAN2_TX_PIN (GPIO_PIN_09) +#define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) - #define CAN2_RX_PORT (GPIO_PORT_I) - #define CAN2_RX_PIN (GPIO_PIN_03) - #define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) +#define CAN2_RX_PORT (GPIO_PORT_I) +#define CAN2_RX_PIN (GPIO_PIN_03) +#define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) #endif #if defined(BSP_USING_MCAN1) - #define MCAN1_TX_PORT (GPIO_PORT_I) - #define MCAN1_TX_PIN (GPIO_PIN_12) - #define MCAN1_TX_PIN_FUNC (GPIO_FUNC_28) +#define MCAN1_TX_PORT (GPIO_PORT_I) +#define MCAN1_TX_PIN (GPIO_PIN_12) +#define MCAN1_TX_PIN_FUNC (GPIO_FUNC_28) - #define MCAN1_RX_PORT (GPIO_PORT_G) - #define MCAN1_RX_PIN (GPIO_PIN_07) - #define MCAN1_RX_PIN_FUNC (GPIO_FUNC_29) +#define MCAN1_RX_PORT (GPIO_PORT_G) +#define MCAN1_RX_PIN (GPIO_PIN_07) +#define MCAN1_RX_PIN_FUNC (GPIO_FUNC_29) #endif #if defined(BSP_USING_MCAN2) - #define MCAN2_TX_PORT (GPIO_PORT_G) - #define MCAN2_TX_PIN (GPIO_PIN_09) - #define MCAN2_TX_PIN_FUNC (GPIO_FUNC_30) +#define MCAN2_TX_PORT (GPIO_PORT_G) +#define MCAN2_TX_PIN (GPIO_PIN_09) +#define MCAN2_TX_PIN_FUNC (GPIO_FUNC_30) - #define MCAN2_RX_PORT (GPIO_PORT_I) - #define MCAN2_RX_PIN (GPIO_PIN_03) - #define MCAN2_RX_PIN_FUNC (GPIO_FUNC_31) +#define MCAN2_RX_PORT (GPIO_PORT_I) +#define MCAN2_RX_PIN (GPIO_PIN_03) +#define MCAN2_RX_PIN_FUNC (GPIO_FUNC_31) #endif /************************* SPI port ***********************/ #if defined(BSP_USING_SPI1) - #define SPI1_CS_PORT (GPIO_PORT_C) - #define SPI1_CS_PIN (GPIO_PIN_07) +#define SPI1_CS_PORT (GPIO_PORT_C) +#define SPI1_CS_PIN (GPIO_PIN_07) - #define SPI1_SCK_PORT (GPIO_PORT_C) - #define SPI1_SCK_PIN (GPIO_PIN_06) - #define SPI1_SCK_FUNC (GPIO_FUNC_40) +#define SPI1_SCK_PORT (GPIO_PORT_C) +#define SPI1_SCK_PIN (GPIO_PIN_06) +#define SPI1_SCK_FUNC (GPIO_FUNC_40) - #define SPI1_MOSI_PORT (GPIO_PORT_B) - #define SPI1_MOSI_PIN (GPIO_PIN_13) - #define SPI1_MOSI_FUNC (GPIO_FUNC_41) +#define SPI1_MOSI_PORT (GPIO_PORT_B) +#define SPI1_MOSI_PIN (GPIO_PIN_13) +#define SPI1_MOSI_FUNC (GPIO_FUNC_41) - #define SPI1_MISO_PORT (GPIO_PORT_B) - #define SPI1_MISO_PIN (GPIO_PIN_12) - #define SPI1_MISO_FUNC (GPIO_FUNC_42) +#define SPI1_MISO_PORT (GPIO_PORT_B) +#define SPI1_MISO_PIN (GPIO_PIN_12) +#define SPI1_MISO_FUNC (GPIO_FUNC_42) - #define SPI1_WP_PORT (GPIO_PORT_B) - #define SPI1_WP_PIN (GPIO_PIN_10) +#define SPI1_WP_PORT (GPIO_PORT_B) +#define SPI1_WP_PIN (GPIO_PIN_10) - #define SPI1_HOLD_PORT (GPIO_PORT_B) - #define SPI1_HOLD_PIN (GPIO_PIN_02) +#define SPI1_HOLD_PORT (GPIO_PORT_B) +#define SPI1_HOLD_PIN (GPIO_PIN_02) #endif /************************* ETH port ***********************/ #if defined(BSP_USING_ETH) - #if defined(ETH_INTERFACE_USING_RMII) - #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) - #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) - #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) - - #define ETH_SMI_MDC_PORT (GPIO_PORT_C) - #define ETH_SMI_MDC_PIN (GPIO_PIN_01) - #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) - #define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) - #define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_TXD0_PORT (GPIO_PORT_G) - #define ETH_RMII_TXD0_PIN (GPIO_PIN_13) - #define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_TXD1_PORT (GPIO_PORT_G) - #define ETH_RMII_TXD1_PIN (GPIO_PIN_14) - #define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) - #define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) - #define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) - #define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) - #define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_RXD0_PORT (GPIO_PORT_C) - #define ETH_RMII_RXD0_PIN (GPIO_PIN_04) - #define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_RXD1_PORT (GPIO_PORT_C) - #define ETH_RMII_RXD1_PIN (GPIO_PIN_05) - #define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) - #else - #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) - #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) - #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) - - #define ETH_SMI_MDC_PORT (GPIO_PORT_C) - #define ETH_SMI_MDC_PIN (GPIO_PIN_01) - #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TX_CLK_PORT (GPIO_PORT_B) - #define ETH_MII_TX_CLK_PIN (GPIO_PIN_06) - #define ETH_MII_TX_CLK_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TX_EN_PORT (GPIO_PORT_G) - #define ETH_MII_TX_EN_PIN (GPIO_PIN_11) - #define ETH_MII_TX_EN_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD0_PORT (GPIO_PORT_G) - #define ETH_MII_TXD0_PIN (GPIO_PIN_13) - #define ETH_MII_TXD0_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD1_PORT (GPIO_PORT_G) - #define ETH_MII_TXD1_PIN (GPIO_PIN_14) - #define ETH_MII_TXD1_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD2_PORT (GPIO_PORT_B) - #define ETH_MII_TXD2_PIN (GPIO_PIN_09) - #define ETH_MII_TXD2_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD3_PORT (GPIO_PORT_B) - #define ETH_MII_TXD3_PIN (GPIO_PIN_08) - #define ETH_MII_TXD3_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RX_CLK_PORT (GPIO_PORT_A) - #define ETH_MII_RX_CLK_PIN (GPIO_PIN_01) - #define ETH_MII_RX_CLK_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RX_DV_PORT (GPIO_PORT_A) - #define ETH_MII_RX_DV_PIN (GPIO_PIN_07) - #define ETH_MII_RX_DV_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD0_PORT (GPIO_PORT_C) - #define ETH_MII_RXD0_PIN (GPIO_PIN_04) - #define ETH_MII_RXD0_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD1_PORT (GPIO_PORT_C) - #define ETH_MII_RXD1_PIN (GPIO_PIN_05) - #define ETH_MII_RXD1_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD2_PORT (GPIO_PORT_B) - #define ETH_MII_RXD2_PIN (GPIO_PIN_00) - #define ETH_MII_RXD2_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD3_PORT (GPIO_PORT_B) - #define ETH_MII_RXD3_PIN (GPIO_PIN_01) - #define ETH_MII_RXD3_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RX_ER_PORT (GPIO_PORT_I) - #define ETH_MII_RX_ER_PIN (GPIO_PIN_10) - #define ETH_MII_RX_ER_FUNC (GPIO_FUNC_11) - - #define ETH_MII_CRS_PORT (GPIO_PORT_H) - #define ETH_MII_CRS_PIN (GPIO_PIN_02) - #define ETH_MII_CRS_FUNC (GPIO_FUNC_11) - - #define ETH_MII_COL_PORT (GPIO_PORT_H) - #define ETH_MII_COL_PIN (GPIO_PIN_03) - #define ETH_MII_COL_FUNC (GPIO_FUNC_11) - #endif +#if defined(ETH_INTERFACE_USING_RMII) +#define ETH_SMI_MDIO_PORT (GPIO_PORT_A) +#define ETH_SMI_MDIO_PIN (GPIO_PIN_02) +#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + +#define ETH_SMI_MDC_PORT (GPIO_PORT_C) +#define ETH_SMI_MDC_PIN (GPIO_PIN_01) +#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) +#define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) +#define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TXD0_PORT (GPIO_PORT_G) +#define ETH_RMII_TXD0_PIN (GPIO_PIN_13) +#define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TXD1_PORT (GPIO_PORT_G) +#define ETH_RMII_TXD1_PIN (GPIO_PIN_14) +#define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) +#define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) +#define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) +#define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) +#define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_RXD0_PORT (GPIO_PORT_C) +#define ETH_RMII_RXD0_PIN (GPIO_PIN_04) +#define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_RXD1_PORT (GPIO_PORT_C) +#define ETH_RMII_RXD1_PIN (GPIO_PIN_05) +#define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) +#else +#define ETH_SMI_MDIO_PORT (GPIO_PORT_A) +#define ETH_SMI_MDIO_PIN (GPIO_PIN_02) +#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + +#define ETH_SMI_MDC_PORT (GPIO_PORT_C) +#define ETH_SMI_MDC_PIN (GPIO_PIN_01) +#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TX_CLK_PORT (GPIO_PORT_B) +#define ETH_MII_TX_CLK_PIN (GPIO_PIN_06) +#define ETH_MII_TX_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TX_EN_PORT (GPIO_PORT_G) +#define ETH_MII_TX_EN_PIN (GPIO_PIN_11) +#define ETH_MII_TX_EN_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD0_PORT (GPIO_PORT_G) +#define ETH_MII_TXD0_PIN (GPIO_PIN_13) +#define ETH_MII_TXD0_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD1_PORT (GPIO_PORT_G) +#define ETH_MII_TXD1_PIN (GPIO_PIN_14) +#define ETH_MII_TXD1_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD2_PORT (GPIO_PORT_B) +#define ETH_MII_TXD2_PIN (GPIO_PIN_09) +#define ETH_MII_TXD2_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD3_PORT (GPIO_PORT_B) +#define ETH_MII_TXD3_PIN (GPIO_PIN_08) +#define ETH_MII_TXD3_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_CLK_PORT (GPIO_PORT_A) +#define ETH_MII_RX_CLK_PIN (GPIO_PIN_01) +#define ETH_MII_RX_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_DV_PORT (GPIO_PORT_A) +#define ETH_MII_RX_DV_PIN (GPIO_PIN_07) +#define ETH_MII_RX_DV_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD0_PORT (GPIO_PORT_C) +#define ETH_MII_RXD0_PIN (GPIO_PIN_04) +#define ETH_MII_RXD0_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD1_PORT (GPIO_PORT_C) +#define ETH_MII_RXD1_PIN (GPIO_PIN_05) +#define ETH_MII_RXD1_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD2_PORT (GPIO_PORT_B) +#define ETH_MII_RXD2_PIN (GPIO_PIN_00) +#define ETH_MII_RXD2_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD3_PORT (GPIO_PORT_B) +#define ETH_MII_RXD3_PIN (GPIO_PIN_01) +#define ETH_MII_RXD3_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_ER_PORT (GPIO_PORT_I) +#define ETH_MII_RX_ER_PIN (GPIO_PIN_10) +#define ETH_MII_RX_ER_FUNC (GPIO_FUNC_11) + +#define ETH_MII_CRS_PORT (GPIO_PORT_H) +#define ETH_MII_CRS_PIN (GPIO_PIN_02) +#define ETH_MII_CRS_FUNC (GPIO_FUNC_11) + +#define ETH_MII_COL_PORT (GPIO_PORT_H) +#define ETH_MII_COL_PIN (GPIO_PIN_03) +#define ETH_MII_COL_FUNC (GPIO_FUNC_11) +#endif #endif /************************ NAND port **********************/ #if defined(BSP_USING_NAND) - #define NAND_CE_PORT (GPIO_PORT_D) /* PD07 - EXMC_SMC_NFC_CS0 */ - #define NAND_CE_PIN (GPIO_PIN_07) - #define NAND_CE_FUNC (GPIO_FUNC_21) - - #define NAND_RE_PORT (GPIO_PORT_D) /* PD04 - EXMC_SMC_OE_NFC_RE */ - #define NAND_RE_PIN (GPIO_PIN_04) - #define NAND_RE_FUNC (GPIO_FUNC_21) - - #define NAND_WE_PORT (GPIO_PORT_D) /* PD05 - EXMC_SMC_NFC_WE */ - #define NAND_WE_PIN (GPIO_PIN_05) - #define NAND_WE_FUNC (GPIO_FUNC_21) - - #define NAND_CLE_PORT (GPIO_PORT_D) /* PD11 - EXMC_ADD16_DMC_BA0_NFC_CLE */ - #define NAND_CLE_PIN (GPIO_PIN_11) - #define NAND_CLE_FUNC (GPIO_FUNC_21) - - #define NAND_ALE_PORT (GPIO_PORT_D) /* PD12 - EXMC_ADD17_DMC_BA1_NFC_ALE */ - #define NAND_ALE_PIN (GPIO_PIN_12) - #define NAND_ALE_FUNC (GPIO_FUNC_21) - - #define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ - #define NAND_WP_PIN (GPIO_PIN_15) - #define NAND_WP_FUNC (GPIO_FUNC_12) - - #define NAND_RB_PORT (GPIO_PORT_G) /* PG06 - EXMC_RB0 */ - #define NAND_RB_PIN (GPIO_PIN_06) - #define NAND_RB_FUNC (GPIO_FUNC_12) - - #define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ - #define NAND_DATA0_PIN (GPIO_PIN_14) - #define NAND_DATA0_FUNC (GPIO_FUNC_12) - #define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ - #define NAND_DATA1_PIN (GPIO_PIN_15) - #define NAND_DATA1_FUNC (GPIO_FUNC_12) - #define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ - #define NAND_DATA2_PIN (GPIO_PIN_00) - #define NAND_DATA2_FUNC (GPIO_FUNC_12) - #define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ - #define NAND_DATA3_PIN (GPIO_PIN_01) - #define NAND_DATA3_FUNC (GPIO_FUNC_12) - #define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ - #define NAND_DATA4_PIN (GPIO_PIN_07) - #define NAND_DATA4_FUNC (GPIO_FUNC_12) - #define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ - #define NAND_DATA5_PIN (GPIO_PIN_08) - #define NAND_DATA5_FUNC (GPIO_FUNC_12) - #define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ - #define NAND_DATA6_PIN (GPIO_PIN_09) - #define NAND_DATA6_FUNC (GPIO_FUNC_12) - #define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ - #define NAND_DATA7_PIN (GPIO_PIN_10) - #define NAND_DATA7_FUNC (GPIO_FUNC_12) +#define NAND_CE_PORT (GPIO_PORT_D) /* PD07 - EXMC_SMC_NFC_CS0 */ +#define NAND_CE_PIN (GPIO_PIN_07) +#define NAND_CE_FUNC (GPIO_FUNC_21) + +#define NAND_RE_PORT (GPIO_PORT_D) /* PD04 - EXMC_SMC_OE_NFC_RE */ +#define NAND_RE_PIN (GPIO_PIN_04) +#define NAND_RE_FUNC (GPIO_FUNC_21) + +#define NAND_WE_PORT (GPIO_PORT_D) /* PD05 - EXMC_SMC_NFC_WE */ +#define NAND_WE_PIN (GPIO_PIN_05) +#define NAND_WE_FUNC (GPIO_FUNC_21) + +#define NAND_CLE_PORT (GPIO_PORT_D) /* PD11 - EXMC_ADD16_DMC_BA0_NFC_CLE */ +#define NAND_CLE_PIN (GPIO_PIN_11) +#define NAND_CLE_FUNC (GPIO_FUNC_21) + +#define NAND_ALE_PORT (GPIO_PORT_D) /* PD12 - EXMC_ADD17_DMC_BA1_NFC_ALE */ +#define NAND_ALE_PIN (GPIO_PIN_12) +#define NAND_ALE_FUNC (GPIO_FUNC_21) + +#define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ +#define NAND_WP_PIN (GPIO_PIN_15) +#define NAND_WP_FUNC (GPIO_FUNC_12) + +#define NAND_RB_PORT (GPIO_PORT_G) /* PG06 - EXMC_RB0 */ +#define NAND_RB_PIN (GPIO_PIN_06) +#define NAND_RB_FUNC (GPIO_FUNC_12) + +#define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ +#define NAND_DATA0_PIN (GPIO_PIN_14) +#define NAND_DATA0_FUNC (GPIO_FUNC_12) +#define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ +#define NAND_DATA1_PIN (GPIO_PIN_15) +#define NAND_DATA1_FUNC (GPIO_FUNC_12) +#define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ +#define NAND_DATA2_PIN (GPIO_PIN_00) +#define NAND_DATA2_FUNC (GPIO_FUNC_12) +#define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ +#define NAND_DATA3_PIN (GPIO_PIN_01) +#define NAND_DATA3_FUNC (GPIO_FUNC_12) +#define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ +#define NAND_DATA4_PIN (GPIO_PIN_07) +#define NAND_DATA4_FUNC (GPIO_FUNC_12) +#define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ +#define NAND_DATA5_PIN (GPIO_PIN_08) +#define NAND_DATA5_FUNC (GPIO_FUNC_12) +#define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ +#define NAND_DATA6_PIN (GPIO_PIN_09) +#define NAND_DATA6_FUNC (GPIO_FUNC_12) +#define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ +#define NAND_DATA7_PIN (GPIO_PIN_10) +#define NAND_DATA7_FUNC (GPIO_FUNC_12) #endif /************************ SDIOC port **********************/ #if defined(BSP_USING_SDIO1) - #define SDIOC1_CK_PORT (GPIO_PORT_C) - #define SDIOC1_CK_PIN (GPIO_PIN_12) - #define SDIOC1_CK_FUNC (GPIO_FUNC_9) +#define SDIOC1_CK_PORT (GPIO_PORT_C) +#define SDIOC1_CK_PIN (GPIO_PIN_12) +#define SDIOC1_CK_FUNC (GPIO_FUNC_9) - #define SDIOC1_CMD_PORT (GPIO_PORT_D) - #define SDIOC1_CMD_PIN (GPIO_PIN_02) - #define SDIOC1_CMD_FUNC (GPIO_FUNC_9) +#define SDIOC1_CMD_PORT (GPIO_PORT_D) +#define SDIOC1_CMD_PIN (GPIO_PIN_02) +#define SDIOC1_CMD_FUNC (GPIO_FUNC_9) - #define SDIOC1_D0_PORT (GPIO_PORT_B) - #define SDIOC1_D0_PIN (GPIO_PIN_07) - #define SDIOC1_D0_FUNC (GPIO_FUNC_9) +#define SDIOC1_D0_PORT (GPIO_PORT_B) +#define SDIOC1_D0_PIN (GPIO_PIN_07) +#define SDIOC1_D0_FUNC (GPIO_FUNC_9) - #define SDIOC1_D1_PORT (GPIO_PORT_A) - #define SDIOC1_D1_PIN (GPIO_PIN_08) - #define SDIOC1_D1_FUNC (GPIO_FUNC_9) +#define SDIOC1_D1_PORT (GPIO_PORT_A) +#define SDIOC1_D1_PIN (GPIO_PIN_08) +#define SDIOC1_D1_FUNC (GPIO_FUNC_9) - #define SDIOC1_D2_PORT (GPIO_PORT_C) - #define SDIOC1_D2_PIN (GPIO_PIN_10) - #define SDIOC1_D2_FUNC (GPIO_FUNC_9) +#define SDIOC1_D2_PORT (GPIO_PORT_C) +#define SDIOC1_D2_PIN (GPIO_PIN_10) +#define SDIOC1_D2_FUNC (GPIO_FUNC_9) - #define SDIOC1_D3_PORT (GPIO_PORT_B) - #define SDIOC1_D3_PIN (GPIO_PIN_05) - #define SDIOC1_D3_FUNC (GPIO_FUNC_9) +#define SDIOC1_D3_PORT (GPIO_PORT_B) +#define SDIOC1_D3_PIN (GPIO_PIN_05) +#define SDIOC1_D3_FUNC (GPIO_FUNC_9) #endif /************************ SDRAM port **********************/ #if defined(BSP_USING_SDRAM) - #define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_DMC_CKE */ - #define SDRAM_CKE_PIN (GPIO_PIN_03) - #define SDRAM_CKE_FUNC (GPIO_FUNC_21) - - #define SDRAM_CLK_PORT (GPIO_PORT_G) /* PG08 - EXMC_DMC_CLK */ - #define SDRAM_CLK_PIN (GPIO_PIN_08) - #define SDRAM_CLK_FUNC (GPIO_FUNC_21) - - #define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ - #define SDRAM_DQM0_PIN (GPIO_PIN_00) - #define SDRAM_DQM0_FUNC (GPIO_FUNC_21) - #define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ - #define SDRAM_DQM1_PIN (GPIO_PIN_01) - #define SDRAM_DQM1_FUNC (GPIO_FUNC_21) - - #define SDRAM_BA0_PORT (GPIO_PORT_G) /* PG04 - EXMC_ADD14_DMC_BA0 */ - #define SDRAM_BA0_PIN (GPIO_PIN_04) - #define SDRAM_BA0_FUNC (GPIO_FUNC_21) - #define SDRAM_BA1_PORT (GPIO_PORT_G) /* PG05 - EXMC_ADD15_DMC_BA1 */ - #define SDRAM_BA1_PIN (GPIO_PIN_05) - #define SDRAM_BA1_FUNC (GPIO_FUNC_21) - - #define SDRAM_CS_PORT (GPIO_PORT_C) /* PC02 - EXMC_DMC_CS0 */ - #define SDRAM_CS_PIN (GPIO_PIN_02) - #define SDRAM_CS_FUNC (GPIO_FUNC_21) - - #define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_DMC_RAS */ - #define SDRAM_RAS_PIN (GPIO_PIN_11) - #define SDRAM_RAS_FUNC (GPIO_FUNC_21) - - #define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_DMC_CAS*/ - #define SDRAM_CAS_PIN (GPIO_PIN_15) - #define SDRAM_CAS_FUNC (GPIO_FUNC_21) - - #define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_DMC_WE */ - #define SDRAM_WE_PIN (GPIO_PIN_00) - #define SDRAM_WE_FUNC (GPIO_FUNC_21) - - #define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ - #define SDRAM_ADD0_PIN (GPIO_PIN_00) - #define SDRAM_ADD0_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ - #define SDRAM_ADD1_PIN (GPIO_PIN_01) - #define SDRAM_ADD1_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ - #define SDRAM_ADD2_PIN (GPIO_PIN_02) - #define SDRAM_ADD2_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ - #define SDRAM_ADD3_PIN (GPIO_PIN_03) - #define SDRAM_ADD3_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ - #define SDRAM_ADD4_PIN (GPIO_PIN_04) - #define SDRAM_ADD4_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ - #define SDRAM_ADD5_PIN (GPIO_PIN_05) - #define SDRAM_ADD5_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ - #define SDRAM_ADD6_PIN (GPIO_PIN_12) - #define SDRAM_ADD6_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ - #define SDRAM_ADD7_PIN (GPIO_PIN_13) - #define SDRAM_ADD7_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ - #define SDRAM_ADD8_PIN (GPIO_PIN_14) - #define SDRAM_ADD8_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ - #define SDRAM_ADD9_PIN (GPIO_PIN_15) - #define SDRAM_ADD9_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ - #define SDRAM_ADD10_PIN (GPIO_PIN_00) - #define SDRAM_ADD10_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ - #define SDRAM_ADD11_PIN (GPIO_PIN_01) - #define SDRAM_ADD11_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD12_PORT (GPIO_PORT_G) /* PG02 - EXMC_ADD12 */ - #define SDRAM_ADD12_PIN (GPIO_PIN_02) - #define SDRAM_ADD12_FUNC (GPIO_FUNC_12) - - #define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ - #define SDRAM_DATA0_PIN (GPIO_PIN_14) - #define SDRAM_DATA0_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ - #define SDRAM_DATA1_PIN (GPIO_PIN_15) - #define SDRAM_DATA1_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ - #define SDRAM_DATA2_PIN (GPIO_PIN_00) - #define SDRAM_DATA2_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ - #define SDRAM_DATA3_PIN (GPIO_PIN_01) - #define SDRAM_DATA3_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ - #define SDRAM_DATA4_PIN (GPIO_PIN_07) - #define SDRAM_DATA4_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ - #define SDRAM_DATA5_PIN (GPIO_PIN_08) - #define SDRAM_DATA5_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ - #define SDRAM_DATA6_PIN (GPIO_PIN_09) - #define SDRAM_DATA6_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ - #define SDRAM_DATA7_PIN (GPIO_PIN_10) - #define SDRAM_DATA7_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ - #define SDRAM_DATA8_PIN (GPIO_PIN_11) - #define SDRAM_DATA8_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ - #define SDRAM_DATA9_PIN (GPIO_PIN_12) - #define SDRAM_DATA9_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ - #define SDRAM_DATA10_PIN (GPIO_PIN_13) - #define SDRAM_DATA10_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ - #define SDRAM_DATA11_PIN (GPIO_PIN_14) - #define SDRAM_DATA11_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ - #define SDRAM_DATA12_PIN (GPIO_PIN_15) - #define SDRAM_DATA12_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ - #define SDRAM_DATA13_PIN (GPIO_PIN_08) - #define SDRAM_DATA13_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ - #define SDRAM_DATA14_PIN (GPIO_PIN_09) - #define SDRAM_DATA14_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ - #define SDRAM_DATA15_PIN (GPIO_PIN_10) - #define SDRAM_DATA15_FUNC (GPIO_FUNC_12) +#define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_DMC_CKE */ +#define SDRAM_CKE_PIN (GPIO_PIN_03) +#define SDRAM_CKE_FUNC (GPIO_FUNC_21) + +#define SDRAM_CLK_PORT (GPIO_PORT_G) /* PG08 - EXMC_DMC_CLK */ +#define SDRAM_CLK_PIN (GPIO_PIN_08) +#define SDRAM_CLK_FUNC (GPIO_FUNC_21) + +#define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ +#define SDRAM_DQM0_PIN (GPIO_PIN_00) +#define SDRAM_DQM0_FUNC (GPIO_FUNC_21) +#define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ +#define SDRAM_DQM1_PIN (GPIO_PIN_01) +#define SDRAM_DQM1_FUNC (GPIO_FUNC_21) + +#define SDRAM_BA0_PORT (GPIO_PORT_G) /* PG04 - EXMC_ADD14_DMC_BA0 */ +#define SDRAM_BA0_PIN (GPIO_PIN_04) +#define SDRAM_BA0_FUNC (GPIO_FUNC_21) +#define SDRAM_BA1_PORT (GPIO_PORT_G) /* PG05 - EXMC_ADD15_DMC_BA1 */ +#define SDRAM_BA1_PIN (GPIO_PIN_05) +#define SDRAM_BA1_FUNC (GPIO_FUNC_21) + +#define SDRAM_CS_PORT (GPIO_PORT_C) /* PC02 - EXMC_DMC_CS0 */ +#define SDRAM_CS_PIN (GPIO_PIN_02) +#define SDRAM_CS_FUNC (GPIO_FUNC_21) + +#define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_DMC_RAS */ +#define SDRAM_RAS_PIN (GPIO_PIN_11) +#define SDRAM_RAS_FUNC (GPIO_FUNC_21) + +#define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_DMC_CAS*/ +#define SDRAM_CAS_PIN (GPIO_PIN_15) +#define SDRAM_CAS_FUNC (GPIO_FUNC_21) + +#define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_DMC_WE */ +#define SDRAM_WE_PIN (GPIO_PIN_00) +#define SDRAM_WE_FUNC (GPIO_FUNC_21) + +#define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ +#define SDRAM_ADD0_PIN (GPIO_PIN_00) +#define SDRAM_ADD0_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ +#define SDRAM_ADD1_PIN (GPIO_PIN_01) +#define SDRAM_ADD1_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ +#define SDRAM_ADD2_PIN (GPIO_PIN_02) +#define SDRAM_ADD2_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ +#define SDRAM_ADD3_PIN (GPIO_PIN_03) +#define SDRAM_ADD3_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ +#define SDRAM_ADD4_PIN (GPIO_PIN_04) +#define SDRAM_ADD4_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ +#define SDRAM_ADD5_PIN (GPIO_PIN_05) +#define SDRAM_ADD5_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ +#define SDRAM_ADD6_PIN (GPIO_PIN_12) +#define SDRAM_ADD6_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ +#define SDRAM_ADD7_PIN (GPIO_PIN_13) +#define SDRAM_ADD7_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ +#define SDRAM_ADD8_PIN (GPIO_PIN_14) +#define SDRAM_ADD8_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ +#define SDRAM_ADD9_PIN (GPIO_PIN_15) +#define SDRAM_ADD9_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ +#define SDRAM_ADD10_PIN (GPIO_PIN_00) +#define SDRAM_ADD10_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ +#define SDRAM_ADD11_PIN (GPIO_PIN_01) +#define SDRAM_ADD11_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD12_PORT (GPIO_PORT_G) /* PG02 - EXMC_ADD12 */ +#define SDRAM_ADD12_PIN (GPIO_PIN_02) +#define SDRAM_ADD12_FUNC (GPIO_FUNC_12) + +#define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ +#define SDRAM_DATA0_PIN (GPIO_PIN_14) +#define SDRAM_DATA0_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ +#define SDRAM_DATA1_PIN (GPIO_PIN_15) +#define SDRAM_DATA1_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ +#define SDRAM_DATA2_PIN (GPIO_PIN_00) +#define SDRAM_DATA2_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ +#define SDRAM_DATA3_PIN (GPIO_PIN_01) +#define SDRAM_DATA3_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ +#define SDRAM_DATA4_PIN (GPIO_PIN_07) +#define SDRAM_DATA4_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ +#define SDRAM_DATA5_PIN (GPIO_PIN_08) +#define SDRAM_DATA5_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ +#define SDRAM_DATA6_PIN (GPIO_PIN_09) +#define SDRAM_DATA6_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ +#define SDRAM_DATA7_PIN (GPIO_PIN_10) +#define SDRAM_DATA7_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ +#define SDRAM_DATA8_PIN (GPIO_PIN_11) +#define SDRAM_DATA8_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ +#define SDRAM_DATA9_PIN (GPIO_PIN_12) +#define SDRAM_DATA9_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ +#define SDRAM_DATA10_PIN (GPIO_PIN_13) +#define SDRAM_DATA10_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ +#define SDRAM_DATA11_PIN (GPIO_PIN_14) +#define SDRAM_DATA11_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ +#define SDRAM_DATA12_PIN (GPIO_PIN_15) +#define SDRAM_DATA12_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ +#define SDRAM_DATA13_PIN (GPIO_PIN_08) +#define SDRAM_DATA13_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ +#define SDRAM_DATA14_PIN (GPIO_PIN_09) +#define SDRAM_DATA14_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ +#define SDRAM_DATA15_PIN (GPIO_PIN_10) +#define SDRAM_DATA15_FUNC (GPIO_FUNC_12) #endif /************************ RTC/PM *****************************/ #if defined(BSP_USING_RTC) || defined(RT_USING_PM) - #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) - #define XTAL32_PORT (GPIO_PORT_C) - #define XTAL32_IN_PIN (GPIO_PIN_15) - #define XTAL32_OUT_PIN (GPIO_PIN_14) - #endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) +#define XTAL32_PORT (GPIO_PORT_C) +#define XTAL32_IN_PIN (GPIO_PIN_15) +#define XTAL32_OUT_PIN (GPIO_PIN_14) +#endif #endif #if defined(RT_USING_PWM) /*********** PWM_TMRA configure *********/ - #if defined(BSP_USING_PWM_TMRA_1) - #if defined(BSP_USING_PWM_TMRA_1_CH1) - #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) - #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH2) - #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) - #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH3) - #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) - #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH4) - #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) - #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) - #endif - #endif +#if defined(BSP_USING_PWM_TMRA_1) +#if defined(BSP_USING_PWM_TMRA_1_CH1) +#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) +#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH2) +#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) +#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH3) +#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) +#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH4) +#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) +#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) +#endif +#endif /*********** PWM_TMR4 configure *********/ - #if defined(BSP_USING_PWM_TMR4_1) - #if defined(BSP_USING_PWM_TMR4_1_OUH) - #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) - #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OUL) - #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) - #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVH) - #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) - #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVL) - #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) - #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWH) - #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) - #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWL) - #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) - #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) - #endif - #endif +#if defined(BSP_USING_PWM_TMR4_1) +#if defined(BSP_USING_PWM_TMR4_1_OUH) +#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) +#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OUL) +#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) +#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVH) +#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) +#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVL) +#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) +#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWH) +#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) +#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWL) +#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) +#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) +#endif +#endif /*********** PWM_TMR6 configure *********/ - #if defined(BSP_USING_PWM_TMR6_1) - #if defined(BSP_USING_PWM_TMR6_1_A) - #define PWM_TMR6_1_A_PORT (GPIO_PORT_F) - #define PWM_TMR6_1_A_PIN (GPIO_PIN_13) - #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #endif - #if defined(BSP_USING_PWM_TMR6_1_B) - #define PWM_TMR6_1_B_PORT (GPIO_PORT_F) - #define PWM_TMR6_1_B_PIN (GPIO_PIN_14) - #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif - #endif +#if defined(BSP_USING_PWM_TMR6_1) +#if defined(BSP_USING_PWM_TMR6_1_A) +#define PWM_TMR6_1_A_PORT (GPIO_PORT_F) +#define PWM_TMR6_1_A_PIN (GPIO_PIN_13) +#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#endif +#if defined(BSP_USING_PWM_TMR6_1_B) +#define PWM_TMR6_1_B_PORT (GPIO_PORT_F) +#define PWM_TMR6_1_B_PIN (GPIO_PIN_14) +#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif +#endif #endif #if defined(BSP_USING_INPUT_CAPTURE) - #define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3) - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) - #define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_B) - #define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_09) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) - #define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_E) - #define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) - #endif - #if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) - #define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) - #define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00) - #endif +#define INPUT_CAPTURE_TMR6_FUNC (GPIO_FUNC_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +#define INPUT_CAPTURE_TMR6_1_PORT (GPIO_PORT_B) +#define INPUT_CAPTURE_TMR6_1_PIN (GPIO_PIN_09) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +#define INPUT_CAPTURE_TMR6_2_PORT (GPIO_PORT_E) +#define INPUT_CAPTURE_TMR6_2_PIN (GPIO_PIN_07) +#endif +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) +#define INPUT_CAPTURE_TMR6_3_PORT (GPIO_PORT_A) +#define INPUT_CAPTURE_TMR6_3_PIN (GPIO_PIN_00) +#endif #endif #if defined(RT_USING_CHERRYUSB) - #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ - defined(BSP_USING_USBFS) || defined(BSP_USING_USBHS) || \ - defined(BSP_USING_USBHS_PHY_EMBED) || defined(BSP_USING_USBHS_PHY_EXTERN) || \ - defined(RT_USING_USB) - #error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" - #endif +#if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || \ + defined(BSP_USING_USBFS) || defined(BSP_USING_USBHS) || \ + defined(BSP_USING_USBHS_PHY_EMBED) || defined(BSP_USING_USBHS_PHY_EXTERN) || \ + defined(RT_USING_USB) +#error "When using CherryUSB, Please donot Enable 'On-Chip Peripheral Driver---> []Enable USB' or using USB legacy version!" +#endif #endif #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) || defined(RT_USING_CHERRYUSB) - #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) +#if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) /* USBFS Core*/ - #define USBF_DP_PORT (GPIO_PORT_A) - #define USBF_DP_PIN (GPIO_PIN_12) - #define USBF_DM_PORT (GPIO_PORT_A) - #define USBF_DM_PIN (GPIO_PIN_11) - #define USBF_VBUS_PORT (GPIO_PORT_A) - #define USBF_VBUS_PIN (GPIO_PIN_09) - #define USBF_VBUS_FUNC (GPIO_FUNC_10) - #define USBF_DRVVBUS_PORT (GPIO_PORT_C) - #define USBF_DRVVBUS_PIN (GPIO_PIN_09) - #define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) - #endif - #if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) +#define USBF_DP_PORT (GPIO_PORT_A) +#define USBF_DP_PIN (GPIO_PIN_12) +#define USBF_DM_PORT (GPIO_PORT_A) +#define USBF_DM_PIN (GPIO_PIN_11) +#define USBF_VBUS_PORT (GPIO_PORT_A) +#define USBF_VBUS_PIN (GPIO_PIN_09) +#define USBF_VBUS_FUNC (GPIO_FUNC_10) +#define USBF_DRVVBUS_PORT (GPIO_PORT_C) +#define USBF_DRVVBUS_PIN (GPIO_PIN_09) +#define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) +#endif +#if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) /* USBHS Core*/ - #if defined(BSP_USING_USBHS_PHY_EMBED) || (defined(RT_USING_CHERRYUSB) && !defined(CONFIG_USB_HS)) - #define USBH_DP_PORT (GPIO_PORT_B) - #define USBH_DP_PIN (GPIO_PIN_15) - #define USBH_DP_FUNC (GPIO_FUNC_10) - #define USBH_DM_PORT (GPIO_PORT_B) - #define USBH_DM_PIN (GPIO_PIN_14) - #define USBH_DM_FUNC (GPIO_FUNC_10) - #define USBH_VBUS_PORT (GPIO_PORT_B) - #define USBH_VBUS_PIN (GPIO_PIN_13) - #define USBH_VBUS_FUNC (GPIO_FUNC_12) - #define USBH_DRVVBUS_PORT (GPIO_PORT_B) - #define USBH_DRVVBUS_PIN (GPIO_PIN_11) - #define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) - #else +#if defined(BSP_USING_USBHS_PHY_EMBED) || (defined(RT_USING_CHERRYUSB) && !defined(CONFIG_USB_HS)) +#define USBH_DP_PORT (GPIO_PORT_B) +#define USBH_DP_PIN (GPIO_PIN_15) +#define USBH_DP_FUNC (GPIO_FUNC_10) +#define USBH_DM_PORT (GPIO_PORT_B) +#define USBH_DM_PIN (GPIO_PIN_14) +#define USBH_DM_FUNC (GPIO_FUNC_10) +#define USBH_VBUS_PORT (GPIO_PORT_B) +#define USBH_VBUS_PIN (GPIO_PIN_13) +#define USBH_VBUS_FUNC (GPIO_FUNC_12) +#define USBH_DRVVBUS_PORT (GPIO_PORT_B) +#define USBH_DRVVBUS_PIN (GPIO_PIN_11) +#define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) +#else /* USBHS Core, external PHY */ - #define USBH_ULPI_CLK_PORT (GPIO_PORT_E) - #define USBH_ULPI_CLK_PIN (GPIO_PIN_12) - #define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_DIR_PORT (GPIO_PORT_C) - #define USBH_ULPI_DIR_PIN (GPIO_PIN_02) - #define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_NXT_PORT (GPIO_PORT_C) - #define USBH_ULPI_NXT_PIN (GPIO_PIN_03) - #define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_STP_PORT (GPIO_PORT_C) - #define USBH_ULPI_STP_PIN (GPIO_PIN_00) - #define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D0_PORT (GPIO_PORT_E) - #define USBH_ULPI_D0_PIN (GPIO_PIN_13) - #define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D1_PORT (GPIO_PORT_E) - #define USBH_ULPI_D1_PIN (GPIO_PIN_14) - #define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D2_PORT (GPIO_PORT_E) - #define USBH_ULPI_D2_PIN (GPIO_PIN_15) - #define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D3_PORT (GPIO_PORT_B) - #define USBH_ULPI_D3_PIN (GPIO_PIN_10) - #define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D4_PORT (GPIO_PORT_B) - #define USBH_ULPI_D4_PIN (GPIO_PIN_11) - #define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D5_PORT (GPIO_PORT_B) - #define USBH_ULPI_D5_PIN (GPIO_PIN_12) - #define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D6_PORT (GPIO_PORT_B) - #define USBH_ULPI_D6_PIN (GPIO_PIN_13) - #define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D7_PORT (GPIO_PORT_E) - #define USBH_ULPI_D7_PIN (GPIO_PIN_11) - #define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_CLK_PORT (GPIO_PORT_E) +#define USBH_ULPI_CLK_PIN (GPIO_PIN_12) +#define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_DIR_PORT (GPIO_PORT_C) +#define USBH_ULPI_DIR_PIN (GPIO_PIN_02) +#define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_NXT_PORT (GPIO_PORT_C) +#define USBH_ULPI_NXT_PIN (GPIO_PIN_03) +#define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_STP_PORT (GPIO_PORT_C) +#define USBH_ULPI_STP_PIN (GPIO_PIN_00) +#define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D0_PORT (GPIO_PORT_E) +#define USBH_ULPI_D0_PIN (GPIO_PIN_13) +#define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D1_PORT (GPIO_PORT_E) +#define USBH_ULPI_D1_PIN (GPIO_PIN_14) +#define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D2_PORT (GPIO_PORT_E) +#define USBH_ULPI_D2_PIN (GPIO_PIN_15) +#define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D3_PORT (GPIO_PORT_B) +#define USBH_ULPI_D3_PIN (GPIO_PIN_10) +#define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D4_PORT (GPIO_PORT_B) +#define USBH_ULPI_D4_PIN (GPIO_PIN_11) +#define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D5_PORT (GPIO_PORT_B) +#define USBH_ULPI_D5_PIN (GPIO_PIN_12) +#define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D6_PORT (GPIO_PORT_B) +#define USBH_ULPI_D6_PIN (GPIO_PIN_13) +#define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D7_PORT (GPIO_PORT_E) +#define USBH_ULPI_D7_PIN (GPIO_PIN_11) +#define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) /* 3300 reset */ - #define USB_3300_RESET_PORT (EIO_PORT1) - #define USB_3300_RESET_PIN (EIO_USB3300_RST) - #endif - #endif +#define USB_3300_RESET_PORT (EIO_PORT1) +#define USB_3300_RESET_PIN (EIO_USB3300_RST) +#endif +#endif #endif #if defined(BSP_USING_QSPI) - #ifndef BSP_QSPI_USING_SOFT_CS +#ifndef BSP_QSPI_USING_SOFT_CS /* QSSN */ - #define QSPI_FLASH_CS_PORT (GPIO_PORT_C) - #define QSPI_FLASH_CS_PIN (GPIO_PIN_07) - #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) - #endif +#define QSPI_FLASH_CS_PORT (GPIO_PORT_C) +#define QSPI_FLASH_CS_PIN (GPIO_PIN_07) +#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) +#endif /* QSCK */ - #define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) - #define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) - #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) +#define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) +#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) /* QSIO0 */ - #define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) - #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) +#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) /* QSIO1 */ - #define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) - #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) +#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) /* QSIO2 */ - #define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) - #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) +#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) /* QSIO3 */ - #define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) - #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) +#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) #endif /*********** TMRA_PULSE_ENCODER configure *********/ #if defined(RT_USING_PULSE_ENCODER) - #if defined(BSP_USING_TMRA_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) - #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) - #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) - #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) - #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) - #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ - #endif /* BSP_USING_TMRA_PULSE_ENCODER */ - - #if defined(BSP_USING_TMR6_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) - #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) - #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) - #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) - #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) - #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ - #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) +#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#endif /* BSP_USING_TMRA_PULSE_ENCODER */ + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#endif /* BSP_USING_TMR6_PULSE_ENCODER */ #endif /* RT_USING_PULSE_ENCODER */ #endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/adc_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/adc_config.h index 4d2de8f7a71..b3eaf9d343f 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/adc_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/adc_config.h @@ -20,42 +20,41 @@ extern "C" { #ifdef BSP_USING_ADC1 #ifndef ADC1_INIT_PARAMS -#define ADC1_INIT_PARAMS \ - { \ - .name = "adc1", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_MAX, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC1_INIT_PARAMS */ -#if defined (BSP_ADC1_USING_DMA) +#if defined(BSP_ADC1_USING_DMA) #ifndef ADC1_EOCA_DMA_CONFIG -#define ADC1_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC1_EOCA_DMA_INSTANCE, \ - .channel = ADC1_EOCA_DMA_CHANNEL, \ - .clock = ADC1_EOCA_DMA_CLOCK, \ - .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC1_EOCA, \ - .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC1_EOCA_DMA_IRQn, \ - .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ - .int_src = ADC1_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC1_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC1_EOCA_DMA_INSTANCE, \ + .channel = ADC1_EOCA_DMA_CHANNEL, \ + .clock = ADC1_EOCA_DMA_CLOCK, \ + .trigger_select = ADC1_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC1_EOCA, \ + .flag = ADC1_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC1_EOCA_DMA_IRQn, \ + .irq_prio = ADC1_EOCA_DMA_INT_PRIO, \ + .int_src = ADC1_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC1_EOCA_DMA_CONFIG */ #endif /* BSP_ADC1_USING_DMA */ @@ -63,42 +62,41 @@ extern "C" { #ifdef BSP_USING_ADC2 #ifndef ADC2_INIT_PARAMS -#define ADC2_INIT_PARAMS \ - { \ - .name = "adc2", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_MAX, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC2_INIT_PARAMS */ -#if defined (BSP_ADC2_USING_DMA) +#if defined(BSP_ADC2_USING_DMA) #ifndef ADC2_EOCA_DMA_CONFIG -#define ADC2_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC2_EOCA_DMA_INSTANCE, \ - .channel = ADC2_EOCA_DMA_CHANNEL, \ - .clock = ADC2_EOCA_DMA_CLOCK, \ - .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC2_EOCA, \ - .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC2_EOCA_DMA_IRQn, \ - .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ - .int_src = ADC2_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC2_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC2_EOCA_DMA_INSTANCE, \ + .channel = ADC2_EOCA_DMA_CHANNEL, \ + .clock = ADC2_EOCA_DMA_CLOCK, \ + .trigger_select = ADC2_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC2_EOCA, \ + .flag = ADC2_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC2_EOCA_DMA_IRQn, \ + .irq_prio = ADC2_EOCA_DMA_INT_PRIO, \ + .int_src = ADC2_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC2_EOCA_DMA_CONFIG */ #endif /* BSP_ADC2_USING_DMA */ @@ -106,41 +104,40 @@ extern "C" { #ifdef BSP_USING_ADC3 #ifndef ADC3_INIT_PARAMS -#define ADC3_INIT_PARAMS \ - { \ - .name = "adc3", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_MAX, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC3_INIT_PARAMS */ -#if defined (BSP_ADC3_USING_DMA) +#if defined(BSP_ADC3_USING_DMA) #ifndef ADC3_EOCA_DMA_CONFIG -#define ADC3_EOCA_DMA_CONFIG \ - { \ - .Instance = ADC3_EOCA_DMA_INSTANCE, \ - .channel = ADC3_EOCA_DMA_CHANNEL, \ - .clock = ADC3_EOCA_DMA_CLOCK, \ - .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_ADC3_EOCA, \ - .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = ADC3_EOCA_DMA_IRQn, \ - .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ - .int_src = ADC3_EOCA_DMA_INT_SRC, \ - }, \ +#define ADC3_EOCA_DMA_CONFIG \ + { \ + .Instance = ADC3_EOCA_DMA_INSTANCE, \ + .channel = ADC3_EOCA_DMA_CHANNEL, \ + .clock = ADC3_EOCA_DMA_CLOCK, \ + .trigger_select = ADC3_EOCA_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_ADC3_EOCA, \ + .flag = ADC3_EOCA_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = ADC3_EOCA_DMA_IRQn, \ + .irq_prio = ADC3_EOCA_DMA_INT_PRIO, \ + .int_src = ADC3_EOCA_DMA_INT_SRC, \ + }, \ } #endif /* ADC3_EOCA_DMA_CONFIG */ #endif /* BSP_ADC3_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/can_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/can_config.h index 4d8cfb7de7f..9f30d75b333 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/can_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/can_config.h @@ -19,25 +19,25 @@ extern "C" { #endif #ifdef BSP_USING_CAN1 -#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) -#define CAN1_NAME ("can1") +#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN1_NAME ("can1") #ifndef CAN1_INIT_PARAMS -#define CAN1_INIT_PARAMS \ - { \ - .name = CAN1_NAME, \ - .single_trans_mode = RT_FALSE \ +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ } #endif /* CAN1_INIT_PARAMS */ #endif /* BSP_USING_CAN1 */ #ifdef BSP_USING_CAN2 -#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) -#define CAN2_NAME ("can2") +#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN2_NAME ("can2") #ifndef CAN2_INIT_PARAMS -#define CAN2_INIT_PARAMS \ - { \ - .name = CAN2_NAME, \ - .single_trans_mode = RT_FALSE \ +#define CAN2_INIT_PARAMS \ + { \ + .name = CAN2_NAME, \ + .single_trans_mode = RT_FALSE \ } #endif /* CAN2_INIT_PARAMS */ #endif /* BSP_USING_CAN2 */ @@ -51,76 +51,76 @@ extern "C" { The following bit time configures are based on CAN Clock 40M */ -#define CAN_BIT_TIME_CONFIG_1M_BAUD \ - { \ - .u32Prescaler = 2, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_800K_BAUD \ - { \ - .u32Prescaler = 2, \ - .u32TimeSeg1 = 20, \ - .u32TimeSeg2 = 5, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_500K_BAUD \ - { \ - .u32Prescaler = 4, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_250K_BAUD \ - { \ - .u32Prescaler = 8, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_125K_BAUD \ - { \ - .u32Prescaler = 16, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_100K_BAUD \ - { \ - .u32Prescaler = 20, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_50K_BAUD \ - { \ - .u32Prescaler = 40, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_20K_BAUD \ - { \ - .u32Prescaler = 100, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_10K_BAUD \ - { \ - .u32Prescaler = 200, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dac_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dac_config.h index c4e155dc9a2..54a5fbfc0ef 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dac_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dac_config.h @@ -19,38 +19,38 @@ extern "C" { #ifdef BSP_USING_DAC1 #ifndef DAC1_INIT_PARAMS -#define DAC1_INIT_PARAMS \ - { \ - .name = "dac1", \ - .vref = 3300, \ - .data_align = DAC_DATA_ALIGN_RIGHT, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch2_output_enable = RT_TRUE, \ - .ch1_data_src = DAC_DATA_SRC_DATAREG, \ - .ch2_data_src = DAC_DATA_SRC_DATAREG, \ - .ch1_amp_enable = RT_TRUE, \ - .ch2_amp_enable = RT_TRUE, \ +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ #ifdef BSP_USING_DAC2 #ifndef DAC2_INIT_PARAMS -#define DAC2_INIT_PARAMS \ - { \ - .name = "dac2", \ - .vref = 3300, \ - .data_align = DAC_DATA_ALIGN_RIGHT, \ - .dac_adp_enable = RT_FALSE, \ - .dac_adp_sel = DAC_ADP_SEL_ALL, \ - .ch1_output_enable = RT_TRUE, \ - .ch2_output_enable = RT_TRUE, \ - .ch1_data_src = DAC_DATA_SRC_DATAREG, \ - .ch2_data_src = DAC_DATA_SRC_DATAREG, \ - .ch1_amp_enable = RT_TRUE, \ - .ch2_amp_enable = RT_TRUE, \ +#define DAC2_INIT_PARAMS \ + { \ + .name = "dac2", \ + .vref = 3300, \ + .data_align = DAC_DATA_ALIGN_RIGHT, \ + .dac_adp_enable = RT_FALSE, \ + .dac_adp_sel = DAC_ADP_SEL_ALL, \ + .ch1_output_enable = RT_TRUE, \ + .ch2_output_enable = RT_TRUE, \ + .ch1_data_src = DAC_DATA_SRC_DATAREG, \ + .ch2_data_src = DAC_DATA_SRC_DATAREG, \ + .ch1_amp_enable = RT_TRUE, \ + .ch2_amp_enable = RT_TRUE, \ } #endif /* DAC2_INIT_PARAMS */ #endif /* BSP_USING_DAC2 */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dma_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dma_config.h index 74bacab9739..4e6843381ae 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dma_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/dma_config.h @@ -20,506 +20,506 @@ extern "C" { /* DMA1 ch0 */ #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) -#define SPI1_RX_DMA_INSTANCE CM_DMA1 -#define SPI1_RX_DMA_CHANNEL DMA_CH0 -#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE) -#define SDIO1_RX_DMA_INSTANCE CM_DMA1 -#define SDIO1_RX_DMA_CHANNEL DMA_CH0 -#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SDIO1_RX_DMA_INSTANCE CM_DMA1 +#define SDIO1_RX_DMA_CHANNEL DMA_CH0 +#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) -#define I2C1_TX_DMA_INSTANCE CM_DMA1 -#define I2C1_TX_DMA_CHANNEL DMA_CH0 -#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 -#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_UART3_RX_USING_DMA) && !defined(UART3_RX_DMA_INSTANCE) -#define UART3_RX_DMA_INSTANCE CM_DMA1 -#define UART3_RX_DMA_CHANNEL DMA_CH0 -#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART3_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define UART3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define UART3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define UART3_RX_DMA_INSTANCE CM_DMA1 +#define UART3_RX_DMA_CHANNEL DMA_CH0 +#define UART3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART3_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define UART3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART3_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define UART3_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define UART3_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #endif /* DMA1 ch1 */ #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) -#define SPI1_TX_DMA_INSTANCE CM_DMA1 -#define SPI1_TX_DMA_CHANNEL DMA_CH1 -#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE) -#define SDIO1_TX_DMA_INSTANCE CM_DMA1 -#define SDIO1_TX_DMA_CHANNEL DMA_CH1 -#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SDIO1_TX_DMA_INSTANCE CM_DMA1 +#define SDIO1_TX_DMA_CHANNEL DMA_CH1 +#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) -#define I2C1_RX_DMA_INSTANCE CM_DMA1 -#define I2C1_RX_DMA_CHANNEL DMA_CH1 -#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 -#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_UART3_TX_USING_DMA) && !defined(UART3_TX_DMA_INSTANCE) -#define UART3_TX_DMA_INSTANCE CM_DMA1 -#define UART3_TX_DMA_CHANNEL DMA_CH1 -#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART3_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define UART3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define UART3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define UART3_TX_DMA_INSTANCE CM_DMA1 +#define UART3_TX_DMA_CHANNEL DMA_CH1 +#define UART3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART3_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define UART3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART3_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define UART3_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define UART3_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #endif /* DMA1 ch2 */ #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) -#define SPI2_RX_DMA_INSTANCE CM_DMA1 -#define SPI2_RX_DMA_CHANNEL DMA_CH2 -#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE) -#define SDIO2_RX_DMA_INSTANCE CM_DMA1 -#define SDIO2_RX_DMA_CHANNEL DMA_CH2 -#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define SDIO2_RX_DMA_INSTANCE CM_DMA1 +#define SDIO2_RX_DMA_CHANNEL DMA_CH2 +#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) -#define I2C2_TX_DMA_INSTANCE CM_DMA1 -#define I2C2_TX_DMA_CHANNEL DMA_CH2 -#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 -#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_UART4_RX_USING_DMA) && !defined(UART4_RX_DMA_INSTANCE) -#define UART4_RX_DMA_INSTANCE CM_DMA1 -#define UART4_RX_DMA_CHANNEL DMA_CH2 -#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART4_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define UART4_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define UART4_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define UART4_RX_DMA_INSTANCE CM_DMA1 +#define UART4_RX_DMA_CHANNEL DMA_CH2 +#define UART4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART4_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define UART4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART4_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define UART4_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define UART4_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #endif /* DMA1 ch3 */ #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) -#define SPI2_TX_DMA_INSTANCE CM_DMA1 -#define SPI2_TX_DMA_CHANNEL DMA_CH3 -#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE) -#define SDIO2_TX_DMA_INSTANCE CM_DMA1 -#define SDIO2_TX_DMA_CHANNEL DMA_CH3 -#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define SDIO2_TX_DMA_INSTANCE CM_DMA1 +#define SDIO2_TX_DMA_CHANNEL DMA_CH3 +#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE) -#define QSPI_DMA_INSTANCE CM_DMA1 -#define QSPI_DMA_CHANNEL DMA_CH3 -#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 -#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define QSPI_DMA_INSTANCE CM_DMA1 +#define QSPI_DMA_CHANNEL DMA_CH3 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) -#define I2C2_RX_DMA_INSTANCE CM_DMA1 -#define I2C2_RX_DMA_CHANNEL DMA_CH3 -#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 -#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_ADC1_USING_DMA) && !defined(ADC1_EOCA_DMA_INSTANCE) -#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 -#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 -#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define ADC1_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC1_EOCA_DMA_CHANNEL DMA_CH3 +#define ADC1_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC1_EOCA_DMA_TRIG_SELECT AOS_DMA1_3 +#define ADC1_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define ADC1_EOCA_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define ADC1_EOCA_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define ADC1_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_UART4_TX_USING_DMA) && !defined(UART4_TX_DMA_INSTANCE) -#define UART4_TX_DMA_INSTANCE CM_DMA1 -#define UART4_TX_DMA_CHANNEL DMA_CH3 -#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART4_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define UART4_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define UART4_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define UART4_TX_DMA_INSTANCE CM_DMA1 +#define UART4_TX_DMA_CHANNEL DMA_CH3 +#define UART4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART4_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define UART4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART4_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define UART4_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define UART4_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #endif /* DMA1 ch4 */ #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) -#define SPI3_RX_DMA_INSTANCE CM_DMA1 -#define SPI3_RX_DMA_CHANNEL DMA_CH4 -#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 -#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH4 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 #elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) -#define I2C3_TX_DMA_INSTANCE CM_DMA1 -#define I2C3_TX_DMA_CHANNEL DMA_CH4 -#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 -#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define I2C3_TX_DMA_INSTANCE CM_DMA1 +#define I2C3_TX_DMA_CHANNEL DMA_CH4 +#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 +#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 #elif defined(BSP_ADC2_USING_DMA) && !defined(ADC2_EOCA_DMA_INSTANCE) -#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 -#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 -#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define ADC2_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC2_EOCA_DMA_CHANNEL DMA_CH4 +#define ADC2_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC2_EOCA_DMA_TRIG_SELECT AOS_DMA1_4 +#define ADC2_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define ADC2_EOCA_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define ADC2_EOCA_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define ADC2_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC4 #elif defined(BSP_UART8_RX_USING_DMA) && !defined(UART8_RX_DMA_INSTANCE) -#define UART8_RX_DMA_INSTANCE CM_DMA1 -#define UART8_RX_DMA_CHANNEL DMA_CH4 -#define UART8_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART8_RX_DMA_TRIG_SELECT AOS_DMA1_4 -#define UART8_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define UART8_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define UART8_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define UART8_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define UART8_RX_DMA_INSTANCE CM_DMA1 +#define UART8_RX_DMA_CHANNEL DMA_CH4 +#define UART8_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART8_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define UART8_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART8_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define UART8_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define UART8_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 #endif /* DMA1 ch5 */ #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) -#define SPI3_TX_DMA_INSTANCE CM_DMA1 -#define SPI3_TX_DMA_CHANNEL DMA_CH5 -#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 -#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH5 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 #elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) -#define I2C3_RX_DMA_INSTANCE CM_DMA1 -#define I2C3_RX_DMA_CHANNEL DMA_CH5 -#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 -#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define I2C3_RX_DMA_INSTANCE CM_DMA1 +#define I2C3_RX_DMA_CHANNEL DMA_CH5 +#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 +#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 #elif defined(BSP_ADC3_USING_DMA) && !defined(ADC3_EOCA_DMA_INSTANCE) -#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 -#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 -#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 -#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define ADC3_EOCA_DMA_INSTANCE CM_DMA1 +#define ADC3_EOCA_DMA_CHANNEL DMA_CH5 +#define ADC3_EOCA_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define ADC3_EOCA_DMA_TRIG_SELECT AOS_DMA1_5 +#define ADC3_EOCA_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define ADC3_EOCA_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define ADC3_EOCA_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define ADC3_EOCA_DMA_INT_SRC INT_SRC_DMA1_TC5 #elif defined(BSP_UART8_TX_USING_DMA) && !defined(UART8_TX_DMA_INSTANCE) -#define UART8_TX_DMA_INSTANCE CM_DMA1 -#define UART8_TX_DMA_CHANNEL DMA_CH5 -#define UART8_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART8_TX_DMA_TRIG_SELECT AOS_DMA1_5 -#define UART8_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define UART8_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define UART8_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define UART8_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define UART8_TX_DMA_INSTANCE CM_DMA1 +#define UART8_TX_DMA_CHANNEL DMA_CH5 +#define UART8_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART8_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define UART8_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART8_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define UART8_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define UART8_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 #endif /* DMA1 ch6 */ #if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) -#define SPI4_RX_DMA_INSTANCE CM_DMA1 -#define SPI4_RX_DMA_CHANNEL DMA_CH6 -#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 -#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM -#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO -#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#define SPI4_RX_DMA_INSTANCE CM_DMA1 +#define SPI4_RX_DMA_CHANNEL DMA_CH6 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 +#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 #elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE) -#define I2C4_TX_DMA_INSTANCE CM_DMA1 -#define I2C4_TX_DMA_CHANNEL DMA_CH6 -#define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6 -#define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM -#define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO -#define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#define I2C4_TX_DMA_INSTANCE CM_DMA1 +#define I2C4_TX_DMA_CHANNEL DMA_CH6 +#define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6 +#define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6 #elif defined(BSP_UART9_RX_USING_DMA) && !defined(UART9_RX_DMA_INSTANCE) -#define UART9_RX_DMA_INSTANCE CM_DMA1 -#define UART9_RX_DMA_CHANNEL DMA_CH6 -#define UART9_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART9_RX_DMA_TRIG_SELECT AOS_DMA1_6 -#define UART9_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define UART9_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM -#define UART9_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO -#define UART9_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#define UART9_RX_DMA_INSTANCE CM_DMA1 +#define UART9_RX_DMA_CHANNEL DMA_CH6 +#define UART9_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART9_RX_DMA_TRIG_SELECT AOS_DMA1_6 +#define UART9_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART9_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define UART9_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define UART9_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 #endif /* DMA1 ch7 */ #if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) -#define SPI4_TX_DMA_INSTANCE CM_DMA1 -#define SPI4_TX_DMA_CHANNEL DMA_CH7 -#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 -#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM -#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO -#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#define SPI4_TX_DMA_INSTANCE CM_DMA1 +#define SPI4_TX_DMA_CHANNEL DMA_CH7 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 +#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 #elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE) -#define I2C4_RX_DMA_INSTANCE CM_DMA1 -#define I2C4_RX_DMA_CHANNEL DMA_CH7 -#define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7 -#define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM -#define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO -#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#define I2C4_RX_DMA_INSTANCE CM_DMA1 +#define I2C4_RX_DMA_CHANNEL DMA_CH7 +#define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7 +#define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7 #elif defined(BSP_UART9_TX_USING_DMA) && !defined(UART9_TX_DMA_INSTANCE) -#define UART9_TX_DMA_INSTANCE CM_DMA1 -#define UART9_TX_DMA_CHANNEL DMA_CH7 -#define UART9_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define UART9_TX_DMA_TRIG_SELECT AOS_DMA1_7 -#define UART9_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define UART9_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM -#define UART9_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO -#define UART9_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#define UART9_TX_DMA_INSTANCE CM_DMA1 +#define UART9_TX_DMA_CHANNEL DMA_CH7 +#define UART9_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define UART9_TX_DMA_TRIG_SELECT AOS_DMA1_7 +#define UART9_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART9_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define UART9_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define UART9_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 #endif /* DMA1 ch8 */ #if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) -#define SPI5_TX_DMA_INSTANCE CM_DMA1 -#define SPI5_TX_DMA_CHANNEL DMA_CH8 -#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 -#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 -#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM -#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO -#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 +#define SPI5_TX_DMA_INSTANCE CM_DMA1 +#define SPI5_TX_DMA_CHANNEL DMA_CH8 +#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 +#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 +#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM +#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO +#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 #endif /* DMA1 ch9 */ #if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) -#define SPI6_TX_DMA_INSTANCE CM_DMA1 -#define SPI6_TX_DMA_CHANNEL DMA_CH9 -#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 -#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 -#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM -#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO -#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 +#define SPI6_TX_DMA_INSTANCE CM_DMA1 +#define SPI6_TX_DMA_CHANNEL DMA_CH9 +#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 +#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 +#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM +#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO +#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 #endif /* DMA2 ch0 */ #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) -#define UART1_RX_DMA_INSTANCE CM_DMA2 -#define UART1_RX_DMA_CHANNEL DMA_CH0 -#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 -#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 #elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE) -#define I2C5_TX_DMA_INSTANCE CM_DMA2 -#define I2C5_TX_DMA_CHANNEL DMA_CH0 -#define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0 -#define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define I2C5_TX_DMA_INSTANCE CM_DMA2 +#define I2C5_TX_DMA_CHANNEL DMA_CH0 +#define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0 +#define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 #endif /* DMA2 ch1 */ #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) -#define UART1_TX_DMA_INSTANCE CM_DMA2 -#define UART1_TX_DMA_CHANNEL DMA_CH1 -#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 -#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 #elif defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE) -#define I2C5_RX_DMA_INSTANCE CM_DMA2 -#define I2C5_RX_DMA_CHANNEL DMA_CH1 -#define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1 -#define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define I2C5_RX_DMA_INSTANCE CM_DMA2 +#define I2C5_RX_DMA_CHANNEL DMA_CH1 +#define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1 +#define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 #endif /* DMA2 ch2 */ #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) -#define UART2_RX_DMA_INSTANCE CM_DMA2 -#define UART2_RX_DMA_CHANNEL DMA_CH2 -#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 -#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 #elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE) -#define I2C6_TX_DMA_INSTANCE CM_DMA2 -#define I2C6_TX_DMA_CHANNEL DMA_CH2 -#define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2 -#define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define I2C6_TX_DMA_INSTANCE CM_DMA2 +#define I2C6_TX_DMA_CHANNEL DMA_CH2 +#define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2 +#define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 #endif /* DMA2 ch3 */ #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) -#define UART2_TX_DMA_INSTANCE CM_DMA2 -#define UART2_TX_DMA_CHANNEL DMA_CH3 -#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 -#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM -#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO -#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 #elif defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE) -#define I2C6_RX_DMA_INSTANCE CM_DMA2 -#define I2C6_RX_DMA_CHANNEL DMA_CH3 -#define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3 -#define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM -#define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO -#define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#define I2C6_RX_DMA_INSTANCE CM_DMA2 +#define I2C6_RX_DMA_CHANNEL DMA_CH3 +#define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3 +#define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3 #endif /* DMA2 ch4 */ #if defined(BSP_UART5_RX_USING_DMA) && !defined(UART5_RX_DMA_INSTANCE) -#define UART5_RX_DMA_INSTANCE CM_DMA2 -#define UART5_RX_DMA_CHANNEL DMA_CH4 -#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART5_RX_DMA_TRIG_SELECT AOS_DMA2_4 -#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define UART5_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM -#define UART5_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO -#define UART5_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#define UART5_RX_DMA_INSTANCE CM_DMA2 +#define UART5_RX_DMA_CHANNEL DMA_CH4 +#define UART5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART5_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART5_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART5_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART5_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 #elif defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) -#define UART6_RX_DMA_INSTANCE CM_DMA2 -#define UART6_RX_DMA_CHANNEL DMA_CH4 -#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 -#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM -#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO -#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#define UART6_RX_DMA_INSTANCE CM_DMA2 +#define UART6_RX_DMA_CHANNEL DMA_CH4 +#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 #endif /* DMA2 ch5 */ #if defined(BSP_UART5_TX_USING_DMA) && !defined(UART5_TX_DMA_INSTANCE) -#define UART5_TX_DMA_INSTANCE CM_DMA2 -#define UART5_TX_DMA_CHANNEL DMA_CH5 -#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART5_TX_DMA_TRIG_SELECT AOS_DMA2_5 -#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define UART5_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM -#define UART5_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO -#define UART5_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#define UART5_TX_DMA_INSTANCE CM_DMA2 +#define UART5_TX_DMA_CHANNEL DMA_CH5 +#define UART5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART5_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART5_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART5_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART5_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 #elif defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) -#define UART6_TX_DMA_INSTANCE CM_DMA2 -#define UART6_TX_DMA_CHANNEL DMA_CH5 -#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 -#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM -#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO -#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#define UART6_TX_DMA_INSTANCE CM_DMA2 +#define UART6_TX_DMA_CHANNEL DMA_CH5 +#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 #endif /* DMA2 ch6 */ #if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) -#define UART7_RX_DMA_INSTANCE CM_DMA2 -#define UART7_RX_DMA_CHANNEL DMA_CH6 -#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 -#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM -#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO -#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 +#define UART7_RX_DMA_INSTANCE CM_DMA2 +#define UART7_RX_DMA_CHANNEL DMA_CH6 +#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 +#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM +#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO +#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 #elif defined(BSP_UART10_RX_USING_DMA) && !defined(UART10_RX_DMA_INSTANCE) -#define UART10_RX_DMA_INSTANCE CM_DMA2 -#define UART10_RX_DMA_CHANNEL DMA_CH6 -#define UART10_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART10_RX_DMA_TRIG_SELECT AOS_DMA2_6 -#define UART10_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define UART10_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM -#define UART10_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO -#define UART10_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 +#define UART10_RX_DMA_INSTANCE CM_DMA2 +#define UART10_RX_DMA_CHANNEL DMA_CH6 +#define UART10_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART10_RX_DMA_TRIG_SELECT AOS_DMA2_6 +#define UART10_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART10_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM +#define UART10_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO +#define UART10_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 #endif /* DMA2 ch7 */ #if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) -#define UART7_TX_DMA_INSTANCE CM_DMA2 -#define UART7_TX_DMA_CHANNEL DMA_CH7 -#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 -#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM -#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO -#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 +#define UART7_TX_DMA_INSTANCE CM_DMA2 +#define UART7_TX_DMA_CHANNEL DMA_CH7 +#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 +#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM +#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO +#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 #elif defined(BSP_UART10_TX_USING_DMA) && !defined(UART10_TX_DMA_INSTANCE) -#define UART10_TX_DMA_INSTANCE CM_DMA2 -#define UART10_TX_DMA_CHANNEL DMA_CH7 -#define UART10_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART10_TX_DMA_TRIG_SELECT AOS_DMA2_7 -#define UART10_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define UART10_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM -#define UART10_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO -#define UART10_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 +#define UART10_TX_DMA_INSTANCE CM_DMA2 +#define UART10_TX_DMA_CHANNEL DMA_CH7 +#define UART10_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART10_TX_DMA_TRIG_SELECT AOS_DMA2_7 +#define UART10_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART10_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM +#define UART10_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO +#define UART10_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 #endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/eth_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/eth_config.h index f28e5b19c74..7cd9b201c70 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/eth_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/eth_config.h @@ -22,11 +22,11 @@ extern "C" { #if defined(BSP_USING_ETH) #ifndef ETH_IRQ_CONFIG -#define ETH_IRQ_CONFIG \ - { \ - .irq_num = BSP_ETH_IRQ_NUM, \ - .irq_prio = BSP_ETH_IRQ_PRIO, \ - .int_src = INT_SRC_ETH_GLB_INT, \ +#define ETH_IRQ_CONFIG \ + { \ + .irq_num = BSP_ETH_IRQ_NUM, \ + .irq_prio = BSP_ETH_IRQ_PRIO, \ + .int_src = INT_SRC_ETH_GLB_INT, \ } #endif /* ETH_IRQ_CONFIG */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/gpio_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/gpio_config.h index ee17e1230de..9a2be5862fa 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/gpio_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/gpio_config.h @@ -22,146 +22,146 @@ extern "C" { #if defined(RT_USING_PIN) #ifndef EXTINT0_IRQ_CONFIG -#define EXTINT0_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT0_IRQ_NUM, \ - .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ0, \ +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT1_IRQ_CONFIG -#define EXTINT1_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT1_IRQ_NUM, \ - .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ1, \ +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT2_IRQ_CONFIG -#define EXTINT2_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT2_IRQ_NUM, \ - .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ2, \ +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ } #endif /* EXTINT2_IRQ_CONFIG */ #ifndef EXTINT3_IRQ_CONFIG -#define EXTINT3_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT3_IRQ_NUM, \ - .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ3, \ +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ } #endif /* EXTINT3_IRQ_CONFIG */ #ifndef EXTINT4_IRQ_CONFIG -#define EXTINT4_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT4_IRQ_NUM, \ - .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ4, \ +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ } #endif /* EXTINT4_IRQ_CONFIG */ #ifndef EXTINT5_IRQ_CONFIG -#define EXTINT5_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT5_IRQ_NUM, \ - .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ5, \ +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ } #endif /* EXTINT5_IRQ_CONFIG */ #ifndef EXTINT6_IRQ_CONFIG -#define EXTINT6_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT6_IRQ_NUM, \ - .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ6, \ +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ } #endif /* EXTINT6_IRQ_CONFIG */ #ifndef EXTINT7_IRQ_CONFIG -#define EXTINT7_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT7_IRQ_NUM, \ - .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ7, \ +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ } #endif /* EXTINT7_IRQ_CONFIG */ #ifndef EXTINT8_IRQ_CONFIG -#define EXTINT8_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT8_IRQ_NUM, \ - .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ8, \ +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ } #endif /* EXTINT8_IRQ_CONFIG */ #ifndef EXTINT9_IRQ_CONFIG -#define EXTINT9_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT9_IRQ_NUM, \ - .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ9, \ +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ } #endif /* EXTINT9_IRQ_CONFIG */ #ifndef EXTINT10_IRQ_CONFIG -#define EXTINT10_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT10_IRQ_NUM, \ - .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ10, \ +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ } #endif /* EXTINT10_IRQ_CONFIG */ #ifndef EXTINT11_IRQ_CONFIG -#define EXTINT11_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT11_IRQ_NUM, \ - .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ11, \ +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ } #endif /* EXTINT11_IRQ_CONFIG */ #ifndef EXTINT12_IRQ_CONFIG -#define EXTINT12_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT12_IRQ_NUM, \ - .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ12, \ +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ } #endif /* EXTINT12_IRQ_CONFIG */ #ifndef EXTINT13_IRQ_CONFIG -#define EXTINT13_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT13_IRQ_NUM, \ - .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ13, \ +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ } #endif /* EXTINT13_IRQ_CONFIG */ #ifndef EXTINT14_IRQ_CONFIG -#define EXTINT14_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT14_IRQ_NUM, \ - .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ14, \ +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ } #endif /* EXTINT14_IRQ_CONFIG */ #ifndef EXTINT15_IRQ_CONFIG -#define EXTINT15_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT15_IRQ_NUM, \ - .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ15, \ +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ } #endif /* EXTINT15_IRQ_CONFIG */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/i2c_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/i2c_config.h index 57fe15696ff..7eea731a079 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/i2c_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/i2c_config.h @@ -20,101 +20,97 @@ extern "C" { #if defined(BSP_USING_I2C1) #ifndef I2C1_CONFIG -#define I2C1_CONFIG \ - { \ - .name = "i2c1", \ - .Instance = CM_I2C1, \ - .clock = FCG1_PERIPH_I2C1, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C1_CONFIG */ #endif #if defined(BSP_I2C1_USING_DMA) #ifndef I2C1_TX_DMA_CONFIG -#define I2C1_TX_DMA_CONFIG \ - { \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .channel = I2C1_TX_DMA_CHANNEL, \ - .clock = I2C1_TX_DMA_CLOCK, \ - .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_TEI, \ - .flag = I2C1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_TX_DMA_IRQn, \ - .irq_prio = I2C1_TX_DMA_INT_PRIO, \ - .int_src = I2C1_TX_DMA_INT_SRC, \ - }, \ +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_TX_DMA_CONFIG */ #ifndef I2C1_RX_DMA_CONFIG -#define I2C1_RX_DMA_CONFIG \ - { \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .channel = I2C1_RX_DMA_CHANNEL, \ - .clock = I2C1_RX_DMA_CLOCK, \ - .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_RXI, \ - .flag = I2C1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_RX_DMA_IRQn, \ - .irq_prio = I2C1_RX_DMA_INT_PRIO, \ - .int_src = I2C1_RX_DMA_INT_SRC, \ - }, \ +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_RX_DMA_CONFIG */ #endif /* BSP_I2C1_USING_DMA */ #if defined(BSP_USING_I2C2) #ifndef I2C2_CONFIG -#define I2C2_CONFIG \ - { \ - .name = "i2c2", \ - .Instance = CM_I2C2, \ - .clock = FCG1_PERIPH_I2C2, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C2_CONFIG */ #if defined(BSP_I2C2_USING_DMA) #ifndef I2C2_TX_DMA_CONFIG -#define I2C2_TX_DMA_CONFIG \ - { \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .channel = I2C2_TX_DMA_CHANNEL, \ - .clock = I2C2_TX_DMA_CLOCK, \ - .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_TEI, \ - .flag = I2C2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_TX_DMA_IRQn, \ - .irq_prio = I2C2_TX_DMA_INT_PRIO, \ - .int_src = I2C2_TX_DMA_INT_SRC, \ - }, \ +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_TX_DMA_CONFIG */ #ifndef I2C2_RX_DMA_CONFIG -#define I2C2_RX_DMA_CONFIG \ - { \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .channel = I2C2_RX_DMA_CHANNEL, \ - .clock = I2C2_RX_DMA_CLOCK, \ - .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_RXI, \ - .flag = I2C2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_RX_DMA_IRQn, \ - .irq_prio = I2C2_RX_DMA_INT_PRIO, \ - .int_src = I2C2_RX_DMA_INT_SRC, \ - }, \ +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_RX_DMA_CONFIG */ #endif /* BSP_I2C2_USING_DMA */ @@ -122,50 +118,48 @@ extern "C" { #if defined(BSP_USING_I2C3) #ifndef I2C3_CONFIG -#define I2C3_CONFIG \ - { \ - .name = "i2c3", \ - .Instance = CM_I2C3, \ - .clock = FCG1_PERIPH_I2C3, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C3_CONFIG */ #if defined(BSP_I2C3_USING_DMA) #ifndef I2C3_TX_DMA_CONFIG -#define I2C3_TX_DMA_CONFIG \ - { \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .channel = I2C3_TX_DMA_CHANNEL, \ - .clock = I2C3_TX_DMA_CLOCK, \ - .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_TEI, \ - .flag = I2C3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_TX_DMA_IRQn, \ - .irq_prio = I2C3_TX_DMA_INT_PRIO, \ - .int_src = I2C3_TX_DMA_INT_SRC, \ - }, \ +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_TX_DMA_CONFIG */ #ifndef I2C3_RX_DMA_CONFIG -#define I2C3_RX_DMA_CONFIG \ - { \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .channel = I2C3_RX_DMA_CHANNEL, \ - .clock = I2C3_RX_DMA_CLOCK, \ - .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_RXI, \ - .flag = I2C3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_RX_DMA_IRQn, \ - .irq_prio = I2C3_RX_DMA_INT_PRIO, \ - .int_src = I2C3_RX_DMA_INT_SRC, \ - }, \ +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_RX_DMA_CONFIG */ #endif /* BSP_I2C3_USING_DMA */ @@ -173,50 +167,48 @@ extern "C" { #if defined(BSP_USING_I2C4) #ifndef I2C4_CONFIG -#define I2C4_CONFIG \ - { \ - .name = "i2c4", \ - .Instance = CM_I2C4, \ - .clock = FCG1_PERIPH_I2C4, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C4_CONFIG \ + { \ + .name = "i2c4", \ + .Instance = CM_I2C4, \ + .clock = FCG1_PERIPH_I2C4, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C4_CONFIG */ #if defined(BSP_I2C4_USING_DMA) #ifndef I2C4_TX_DMA_CONFIG -#define I2C4_TX_DMA_CONFIG \ - { \ - .Instance = I2C4_TX_DMA_INSTANCE, \ - .channel = I2C4_TX_DMA_CHANNEL, \ - .clock = I2C4_TX_DMA_CLOCK, \ - .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C4_TEI, \ - .flag = I2C4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C4_TX_DMA_IRQn, \ - .irq_prio = I2C4_TX_DMA_INT_PRIO, \ - .int_src = I2C4_TX_DMA_INT_SRC, \ - }, \ +#define I2C4_TX_DMA_CONFIG \ + { \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + .clock = I2C4_TX_DMA_CLOCK, \ + .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_TEI, \ + .flag = I2C4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_TX_DMA_IRQn, \ + .irq_prio = I2C4_TX_DMA_INT_PRIO, \ + .int_src = I2C4_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C4_TX_DMA_CONFIG */ #ifndef I2C4_RX_DMA_CONFIG -#define I2C4_RX_DMA_CONFIG \ - { \ - .Instance = I2C4_RX_DMA_INSTANCE, \ - .channel = I2C4_RX_DMA_CHANNEL, \ - .clock = I2C4_RX_DMA_CLOCK, \ - .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C4_RXI, \ - .flag = I2C4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C4_RX_DMA_IRQn, \ - .irq_prio = I2C4_RX_DMA_INT_PRIO, \ - .int_src = I2C4_RX_DMA_INT_SRC, \ - }, \ +#define I2C4_RX_DMA_CONFIG \ + { \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + .clock = I2C4_RX_DMA_CLOCK, \ + .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_RXI, \ + .flag = I2C4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_RX_DMA_IRQn, \ + .irq_prio = I2C4_RX_DMA_INT_PRIO, \ + .int_src = I2C4_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C4_RX_DMA_CONFIG */ #endif /* BSP_I2C4_USING_DMA */ @@ -224,50 +216,48 @@ extern "C" { #if defined(BSP_USING_I2C5) #ifndef I2C5_CONFIG -#define I2C5_CONFIG \ - { \ - .name = "i2c5", \ - .Instance = CM_I2C5, \ - .clock = FCG1_PERIPH_I2C5, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C5_CONFIG \ + { \ + .name = "i2c5", \ + .Instance = CM_I2C5, \ + .clock = FCG1_PERIPH_I2C5, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C5_CONFIG */ #if defined(BSP_I2C5_USING_DMA) #ifndef I2C5_TX_DMA_CONFIG -#define I2C5_TX_DMA_CONFIG \ - { \ - .Instance = I2C5_TX_DMA_INSTANCE, \ - .channel = I2C5_TX_DMA_CHANNEL, \ - .clock = I2C5_TX_DMA_CLOCK, \ - .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C5_TEI, \ - .flag = I2C5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C5_TX_DMA_IRQn, \ - .irq_prio = I2C5_TX_DMA_INT_PRIO, \ - .int_src = I2C5_TX_DMA_INT_SRC, \ - }, \ +#define I2C5_TX_DMA_CONFIG \ + { \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .channel = I2C5_TX_DMA_CHANNEL, \ + .clock = I2C5_TX_DMA_CLOCK, \ + .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_TEI, \ + .flag = I2C5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_TX_DMA_IRQn, \ + .irq_prio = I2C5_TX_DMA_INT_PRIO, \ + .int_src = I2C5_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C5_TX_DMA_CONFIG */ #ifndef I2C5_RX_DMA_CONFIG -#define I2C5_RX_DMA_CONFIG \ - { \ - .Instance = I2C5_RX_DMA_INSTANCE, \ - .channel = I2C5_RX_DMA_CHANNEL, \ - .clock = I2C5_RX_DMA_CLOCK, \ - .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C5_RXI, \ - .flag = I2C5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C5_RX_DMA_IRQn, \ - .irq_prio = I2C5_RX_DMA_INT_PRIO, \ - .int_src = I2C5_RX_DMA_INT_SRC, \ - }, \ +#define I2C5_RX_DMA_CONFIG \ + { \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .channel = I2C5_RX_DMA_CHANNEL, \ + .clock = I2C5_RX_DMA_CLOCK, \ + .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_RXI, \ + .flag = I2C5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_RX_DMA_IRQn, \ + .irq_prio = I2C5_RX_DMA_INT_PRIO, \ + .int_src = I2C5_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C5_RX_DMA_CONFIG */ #endif /* BSP_I2C5_USING_DMA */ @@ -275,50 +265,48 @@ extern "C" { #if defined(BSP_USING_I2C6) #ifndef I2C6_CONFIG -#define I2C6_CONFIG \ - { \ - .name = "i2c6", \ - .Instance = CM_I2C6, \ - .clock = FCG1_PERIPH_I2C6, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C6_CONFIG \ + { \ + .name = "i2c6", \ + .Instance = CM_I2C6, \ + .clock = FCG1_PERIPH_I2C6, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C6_CONFIG */ #if defined(BSP_I2C6_USING_DMA) #ifndef I2C6_TX_DMA_CONFIG -#define I2C6_TX_DMA_CONFIG \ - { \ - .Instance = I2C6_TX_DMA_INSTANCE, \ - .channel = I2C6_TX_DMA_CHANNEL, \ - .clock = I2C6_TX_DMA_CLOCK, \ - .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C6_TEI, \ - .flag = I2C6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C6_TX_DMA_IRQn, \ - .irq_prio = I2C6_TX_DMA_INT_PRIO, \ - .int_src = I2C6_TX_DMA_INT_SRC, \ - }, \ +#define I2C6_TX_DMA_CONFIG \ + { \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .channel = I2C6_TX_DMA_CHANNEL, \ + .clock = I2C6_TX_DMA_CLOCK, \ + .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_TEI, \ + .flag = I2C6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_TX_DMA_IRQn, \ + .irq_prio = I2C6_TX_DMA_INT_PRIO, \ + .int_src = I2C6_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C6_TX_DMA_CONFIG */ #ifndef I2C6_RX_DMA_CONFIG -#define I2C6_RX_DMA_CONFIG \ - { \ - .Instance = I2C6_RX_DMA_INSTANCE, \ - .channel = I2C6_RX_DMA_CHANNEL, \ - .clock = I2C6_RX_DMA_CLOCK, \ - .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C6_RXI, \ - .flag = I2C6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C6_RX_DMA_IRQn, \ - .irq_prio = I2C6_RX_DMA_INT_PRIO, \ - .int_src = I2C6_RX_DMA_INT_SRC, \ - }, \ +#define I2C6_RX_DMA_CONFIG \ + { \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .channel = I2C6_RX_DMA_CHANNEL, \ + .clock = I2C6_RX_DMA_CLOCK, \ + .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_RXI, \ + .flag = I2C6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_RX_DMA_IRQn, \ + .irq_prio = I2C6_RX_DMA_INT_PRIO, \ + .int_src = I2C6_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C6_RX_DMA_CONFIG */ #endif /* BSP_I2C6_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/irq_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/irq_config.h index 85ea6124400..90c44898529 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/irq_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/irq_config.h @@ -17,582 +17,582 @@ extern "C" { #endif -#define BSP_EXTINT0_IRQ_NUM INT022_IRQn -#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT1_IRQ_NUM INT023_IRQn -#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT2_IRQ_NUM INT024_IRQn -#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT3_IRQ_NUM INT025_IRQn -#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT4_IRQ_NUM INT026_IRQn -#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT5_IRQ_NUM INT027_IRQn -#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT6_IRQ_NUM INT028_IRQn -#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT7_IRQ_NUM INT029_IRQn -#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT8_IRQ_NUM INT030_IRQn -#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT9_IRQ_NUM INT031_IRQn -#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT10_IRQ_NUM INT032_IRQn -#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT11_IRQ_NUM INT033_IRQn -#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT12_IRQ_NUM INT034_IRQn -#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT13_IRQ_NUM INT035_IRQn -#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT14_IRQ_NUM INT036_IRQn -#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT15_IRQ_NUM INT037_IRQn -#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch0 */ -#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn -#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch1 */ -#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn -#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch2 */ -#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn -#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch3 */ -#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn -#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch4 */ -#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn -#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch5 */ -#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn -#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch6 */ -#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn -#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch7 */ -#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn -#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch8 */ -#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn -#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn +#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch9 */ -#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn -#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn +#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch0 */ -#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn -#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch1 */ -#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn -#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch2 */ -#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn -#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch3 */ -#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn -#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch4 */ -#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn -#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch5 */ -#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn -#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch6 */ -#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn -#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn +#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch7 */ -#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn -#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn +#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_USING_ETH) -#define BSP_ETH_IRQ_NUM INT104_IRQn -#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_ETH_IRQ_NUM INT104_IRQn +#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_UART1) -#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn -#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART1_RX_IRQ_NUM INT089_IRQn -#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART1_TX_IRQ_NUM INT088_IRQn -#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT089_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT088_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART1_RX_USING_DMA) -#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn -#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) -#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) -#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn -#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART2_RX_IRQ_NUM INT091_IRQn -#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART2_TX_IRQ_NUM INT090_IRQn -#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT091_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT090_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART2_RX_USING_DMA) -#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn -#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) -#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) -#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn -#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART3_RX_IRQ_NUM INT095_IRQn -#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART3_TX_IRQ_NUM INT094_IRQn -#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT095_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT094_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART3_RX_USING_DMA) -#define BSP_UART3_RXTO_IRQ_NUM INT068_IRQn -#define BSP_UART3_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RXTO_IRQ_NUM INT068_IRQn +#define BSP_UART3_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA) -#define BSP_UART3_TX_CPLT_IRQ_NUM INT092_IRQn -#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_CPLT_IRQ_NUM INT092_IRQn +#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART3_TX_CPLT_IRQ_NUM INT092_IRQn -#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_CPLT_IRQ_NUM INT092_IRQn +#define BSP_UART3_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART3 */ #if defined(BSP_USING_UART4) -#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn -#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART4_RX_IRQ_NUM INT097_IRQn -#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART4_TX_IRQ_NUM INT096_IRQn -#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT097_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT096_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART4_RX_USING_DMA) -#define BSP_UART4_RXTO_IRQ_NUM INT069_IRQn -#define BSP_UART4_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RXTO_IRQ_NUM INT069_IRQn +#define BSP_UART4_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA) -#define BSP_UART4_TX_CPLT_IRQ_NUM INT093_IRQn -#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_CPLT_IRQ_NUM INT093_IRQn +#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART4_TX_CPLT_IRQ_NUM INT093_IRQn -#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_CPLT_IRQ_NUM INT093_IRQn +#define BSP_UART4_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_UART5) -#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn -#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART5_RX_IRQ_NUM INT101_IRQn -#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART5_TX_IRQ_NUM INT100_IRQn -#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn +#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RX_IRQ_NUM INT101_IRQn +#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_IRQ_NUM INT100_IRQn +#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART5_RX_USING_DMA) -#define BSP_UART5_RXTO_IRQ_NUM INT070_IRQn -#define BSP_UART5_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RXTO_IRQ_NUM INT070_IRQn +#define BSP_UART5_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA) -#define BSP_UART5_TX_CPLT_IRQ_NUM INT098_IRQn -#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_CPLT_IRQ_NUM INT098_IRQn +#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART5_TX_CPLT_IRQ_NUM INT098_IRQn -#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_CPLT_IRQ_NUM INT098_IRQn +#define BSP_UART5_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART5 */ #if defined(BSP_USING_UART6) -#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn -#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART6_RX_IRQ_NUM INT103_IRQn -#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART6_TX_IRQ_NUM INT102_IRQn -#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn +#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RX_IRQ_NUM INT103_IRQn +#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_IRQ_NUM INT102_IRQn +#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART6_RX_USING_DMA) -#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn -#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn +#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) -#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn -#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn -#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART6 */ #if defined(BSP_USING_UART7) -#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn -#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART7_RX_IRQ_NUM INT107_IRQn -#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART7_TX_IRQ_NUM INT106_IRQn -#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn +#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RX_IRQ_NUM INT107_IRQn +#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_IRQ_NUM INT106_IRQn +#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART7_RX_USING_DMA) -#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn -#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn +#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) -#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn -#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn -#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #elif defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) -#define BSP_SPI1_ERR_IRQ_NUM INT009_IRQn -#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_SPI2_ERR_IRQ_NUM INT016_IRQn -#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI1_ERR_IRQ_NUM INT009_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM INT016_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART7 */ #if defined(BSP_USING_SPI3) -#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn -#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI4) -#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn -#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn +#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI5) -#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn -#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn +#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI6) -#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn -#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn +#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_UART8) -#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn -#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART8_RX_IRQ_NUM INT109_IRQn -#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART8_TX_IRQ_NUM INT108_IRQn -#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn +#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RX_IRQ_NUM INT109_IRQn +#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_IRQ_NUM INT108_IRQn +#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART8_RX_USING_DMA) -#define BSP_UART8_RXTO_IRQ_NUM INT071_IRQn -#define BSP_UART8_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RXTO_IRQ_NUM INT071_IRQn +#define BSP_UART8_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART8_TX_USING_DMA) -#define BSP_UART8_TX_CPLT_IRQ_NUM INT107_IRQn -#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_CPLT_IRQ_NUM INT107_IRQn +#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART8_TX_CPLT_IRQ_NUM INT107_IRQn -#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_CPLT_IRQ_NUM INT107_IRQn +#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART8 */ #if defined(BSP_USING_UART9) -#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn -#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART9_RX_IRQ_NUM INT110_IRQn -#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART9_TX_IRQ_NUM INT111_IRQn -#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn +#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RX_IRQ_NUM INT110_IRQn +#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_TX_IRQ_NUM INT111_IRQn +#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART9_RX_USING_DMA) -#define BSP_UART9_RXTO_IRQ_NUM INT072_IRQn -#define BSP_UART9_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RXTO_IRQ_NUM INT072_IRQn +#define BSP_UART9_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART9_TX_USING_DMA) -#define BSP_UART9_TX_CPLT_IRQ_NUM INT113_IRQn -#define BSP_UART9_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_TX_CPLT_IRQ_NUM INT113_IRQn +#define BSP_UART9_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART9_TX_CPLT_IRQ_NUM INT113_IRQn -#define BSP_UART9_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_TX_CPLT_IRQ_NUM INT113_IRQn +#define BSP_UART9_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART9 */ #if defined(BSP_USING_UART10) -#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn -#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART10_RX_IRQ_NUM INT114_IRQn -#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART10_TX_IRQ_NUM INT113_IRQn -#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn +#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RX_IRQ_NUM INT114_IRQn +#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_IRQ_NUM INT113_IRQn +#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART10_RX_USING_DMA) -#define BSP_UART10_RXTO_IRQ_NUM INT073_IRQn -#define BSP_UART10_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RXTO_IRQ_NUM INT073_IRQn +#define BSP_UART10_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART10_TX_USING_DMA) -#define BSP_UART10_TX_CPLT_IRQ_NUM INT112_IRQn -#define BSP_UART10_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_CPLT_IRQ_NUM INT112_IRQn +#define BSP_UART10_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART10_TX_CPLT_IRQ_NUM INT112_IRQn -#define BSP_UART10_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_CPLT_IRQ_NUM INT112_IRQn +#define BSP_UART10_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART10 */ #if defined(BSP_USING_CAN1) -#define BSP_CAN1_IRQ_NUM INT092_IRQn -#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_CAN1_IRQ_NUM INT092_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_CAN1 */ #if defined(BSP_USING_CAN2) -#define BSP_CAN2_IRQ_NUM INT093_IRQn -#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_CAN2_IRQ_NUM INT093_IRQn +#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_CAN2 */ #if defined(BSP_USING_MCAN1) -#define BSP_MCAN1_INT0_IRQ_NUM INT124_IRQn -#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_MCAN1_INT0_IRQ_NUM INT124_IRQn +#define BSP_MCAN1_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN1 */ #if defined(BSP_USING_MCAN2) -#define BSP_MCAN2_INT0_IRQ_NUM INT126_IRQn -#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_MCAN2_INT0_IRQ_NUM INT126_IRQn +#define BSP_MCAN2_INT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_MCAN2 */ #if defined(BSP_USING_SDIO1) -#define BSP_SDIO1_IRQ_NUM INT004_IRQn -#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SDIO1_IRQ_NUM INT004_IRQn +#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_SDIO1 */ #if defined(BSP_USING_SDIO2) -#define BSP_SDIO2_IRQ_NUM INT005_IRQn -#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SDIO2_IRQ_NUM INT005_IRQn +#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_SDIO2 */ #if defined(RT_USING_ALARM) -#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn -#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* RT_USING_ALARM */ #if defined(BSP_USING_USBFS) || defined(RT_USING_CHERRYUSB) -#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn -#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn +#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBFS */ #if defined(BSP_USING_USBHS) || defined(RT_USING_CHERRYUSB) -#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn -#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn +#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBHS */ -#if defined (BSP_USING_QSPI) -#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn -#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#if defined(BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_QSPI */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_2) -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_3) -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_4) -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_5) -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_6) -#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn -#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn -#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_7) -#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn -#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn -#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_7 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_8) -#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn -#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn -#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_8 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_9) -#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM INT098_IRQn -#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM INT099_IRQn -#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM INT098_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM INT099_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_9 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_10) -#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM INT100_IRQn -#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM INT101_IRQn -#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM INT100_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM INT101_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_10 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_11) -#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM INT102_IRQn -#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM INT103_IRQn -#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_11 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_12) -#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM INT102_IRQn -#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM INT103_IRQn -#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_12 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_2) -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_3) -#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn -#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn -#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_4) -#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM INT068_IRQn -#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM INT069_IRQn -#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM INT068_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM INT069_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_5) -#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM INT074_IRQn -#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM INT075_IRQn -#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_6) -#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM INT076_IRQn -#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM INT077_IRQn -#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_6 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_7) -#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM INT080_IRQn -#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM INT081_IRQn -#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_7 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_8) -#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM INT082_IRQn -#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM INT083_IRQn -#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_8 */ #if defined(BSP_USING_TMRA_1) -#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn -#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_1 */ #if defined(BSP_USING_TMRA_2) -#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn -#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_2 */ #if defined(BSP_USING_TMRA_3) -#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn -#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_3 */ #if defined(BSP_USING_TMRA_4) -#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn -#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_4 */ #if defined(BSP_USING_TMRA_5) -#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn -#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_5 */ #if defined(BSP_USING_TMRA_6) -#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn -#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn +#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_6 */ #if defined(BSP_USING_TMRA_7) -#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn -#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn +#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_7 */ #if defined(BSP_USING_TMRA_8) -#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn -#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn +#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_8 */ #if defined(BSP_USING_TMRA_9) -#define BSP_USING_TMRA_9_IRQ_NUM INT098_IRQn -#define BSP_USING_TMRA_9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_9_IRQ_NUM INT098_IRQn +#define BSP_USING_TMRA_9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_9 */ #if defined(BSP_USING_TMRA_10) -#define BSP_USING_TMRA_10_IRQ_NUM INT099_IRQn -#define BSP_USING_TMRA_10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_10_IRQ_NUM INT099_IRQn +#define BSP_USING_TMRA_10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_10 */ #if defined(BSP_USING_TMRA_11) -#define BSP_USING_TMRA_11_IRQ_NUM INT100_IRQn -#define BSP_USING_TMRA_11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_11_IRQ_NUM INT100_IRQn +#define BSP_USING_TMRA_11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_11 */ #if defined(BSP_USING_TMRA_12) -#define BSP_USING_TMRA_12_IRQ_NUM INT101_IRQn -#define BSP_USING_TMRA_12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_12_IRQ_NUM INT101_IRQn +#define BSP_USING_TMRA_12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_12 */ #if defined(BSP_USING_INPUT_CAPTURE) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) - -#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) -#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn) -#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM (INT012_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM (INT013_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM (INT014_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM (INT015_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) + +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM (INT016_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM (INT017_IRQn) +#define BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO (DDL_IRQ_PRIO_DEFAULT) #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/mcan_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/mcan_config.h index 41d85d7ebdd..2a3dd41a2ed 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/mcan_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/mcan_config.h @@ -31,56 +31,56 @@ extern "C" { */ #ifdef RT_CAN_USING_CANFD -#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS -#define MCAN_TOTAL_FILTER_NUM (64U) -#define MCAN_STD_FILTER_NUM (32U) /* Each standard filter element size is 4 bytes */ -#define MCAN_EXT_FILTER_NUM (32U) /* Each extended filter element size is 8 bytes */ -#define MCAN_TX_FIFO_NUM (11U) -#define MCAN_RX_FIFO_NUM (12U) -#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */ +#define MCAN_FD_SEL MCAN_FD_ISO_FD_BRS +#define MCAN_TOTAL_FILTER_NUM (64U) +#define MCAN_STD_FILTER_NUM (32U) /* Each standard filter element size is 4 bytes */ +#define MCAN_EXT_FILTER_NUM (32U) /* Each extended filter element size is 8 bytes */ +#define MCAN_TX_FIFO_NUM (11U) +#define MCAN_RX_FIFO_NUM (12U) +#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_64BYTE) /* Each FIFO element size is 64+8 bytes */ #else -#define MCAN_FD_SEL MCAN_FD_CLASSICAL -#define MCAN_TOTAL_FILTER_NUM (64U) -#define MCAN_STD_FILTER_NUM (32U) /* Each standard filter element size is 4 bytes */ -#define MCAN_EXT_FILTER_NUM (32U) /* Each extended filter element size is 8 bytes */ -#define MCAN_TX_FIFO_NUM (32U) -#define MCAN_RX_FIFO_NUM (64U) -#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */ +#define MCAN_FD_SEL MCAN_FD_CLASSICAL +#define MCAN_TOTAL_FILTER_NUM (64U) +#define MCAN_STD_FILTER_NUM (32U) /* Each standard filter element size is 4 bytes */ +#define MCAN_EXT_FILTER_NUM (32U) /* Each extended filter element size is 8 bytes */ +#define MCAN_TX_FIFO_NUM (32U) +#define MCAN_RX_FIFO_NUM (64U) +#define MCAN_DATA_FIELD_SIZE (MCAN_DATA_SIZE_8BYTE) /* Each FIFO element size is 8+8 bytes */ #endif #ifdef BSP_USING_MCAN1 -#define MCAN1_NAME ("mcan1") -#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL) -#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ +#define MCAN1_NAME ("mcan1") +#define MCAN1_WORK_MODE (RT_CAN_MODE_NORMAL) +#define MCAN1_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ -#define MCAN1_FD_SEL MCAN_FD_SEL +#define MCAN1_FD_SEL MCAN_FD_SEL -#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM -#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM +#define MCAN1_STD_FILTER_NUM MCAN_STD_FILTER_NUM +#define MCAN1_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM -#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM -#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN1_RX_FIFO0_NUM MCAN_RX_FIFO_NUM +#define MCAN1_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM -#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U) +#define MCAN1_TX_FIFO_NUM MCAN_TX_FIFO_NUM +#define MCAN1_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN1_TX_NOTIFICATION_BUF ((1UL << MCAN1_TX_FIFO_NUM) - 1U) #endif /* BSP_USING_MCAN1 */ #ifdef BSP_USING_MCAN2 -#define MCAN2_NAME ("mcan2") -#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL) -#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ +#define MCAN2_NAME ("mcan2") +#define MCAN2_WORK_MODE (RT_CAN_MODE_NORMAL) +#define MCAN2_TX_PRIV_MODE RT_CAN_MODE_NOPRIV /* RT_CAN_MODE_NOPRIV: Tx FIFO mode; RT_CAN_MODE_PRIV: Tx priority mode */ -#define MCAN2_FD_SEL MCAN_FD_SEL -#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM -#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM +#define MCAN2_FD_SEL MCAN_FD_SEL +#define MCAN2_STD_FILTER_NUM MCAN_STD_FILTER_NUM +#define MCAN2_EXT_FILTER_NUM MCAN_EXT_FILTER_NUM -#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM -#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN2_RX_FIFO0_NUM MCAN_RX_FIFO_NUM +#define MCAN2_RX_FIFO0_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM -#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE -#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U) +#define MCAN2_TX_FIFO_NUM MCAN_TX_FIFO_NUM +#define MCAN2_TX_FIFO_DATA_FIELD_SIZE MCAN_DATA_FIELD_SIZE +#define MCAN2_TX_NOTIFICATION_BUF ((1UL << MCAN2_TX_FIFO_NUM) - 1U) #endif /* BSP_USING_MCAN2 */ /***********************************************************************************************/ @@ -101,154 +101,154 @@ extern "C" { 2. For the corresponding function of u32TdcFilter, please refer to the reference manual for details(TDCR.TDCF). The u32TdcFilter can be get from PSR.TDCV. */ -#define MCAN_FD_CFG_500K_1M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 32, \ - .u32DataTimeSeg2 = 8, \ - .u32DataSyncJumpWidth = 8, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 32, \ - .u32TdcFilter = 32 + 1, \ +#define MCAN_FD_CFG_500K_1M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 32, \ + .u32DataTimeSeg2 = 8, \ + .u32DataSyncJumpWidth = 8, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 32, \ + .u32TdcFilter = 32 + 1, \ } -#define MCAN_FD_CFG_500K_2M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 16, \ - .u32DataTimeSeg2 = 4, \ - .u32DataSyncJumpWidth = 4, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 16, \ - .u32TdcFilter = 16 + 1, \ +#define MCAN_FD_CFG_500K_2M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 16, \ + .u32DataTimeSeg2 = 4, \ + .u32DataSyncJumpWidth = 4, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 16, \ + .u32TdcFilter = 16 + 1, \ } -#define MCAN_FD_CFG_500K_4M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 8, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 8, \ - .u32TdcFilter = 8 + 1, \ +#define MCAN_FD_CFG_500K_4M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 8, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 8, \ + .u32TdcFilter = 8 + 1, \ } -#define MCAN_FD_CFG_500K_5M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 6, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 6, \ - .u32TdcFilter = 6 + 1, \ +#define MCAN_FD_CFG_500K_5M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 6, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 6, \ + .u32TdcFilter = 6 + 1, \ } -#define MCAN_FD_CFG_500K_8M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 64, \ - .u32NominalTimeSeg2 = 16, \ - .u32NominalSyncJumpWidth = 16, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 4, \ - .u32DataTimeSeg2 = 1, \ - .u32DataSyncJumpWidth = 1, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 4, \ - .u32TdcFilter = 4 + 1, \ +#define MCAN_FD_CFG_500K_8M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 64, \ + .u32NominalTimeSeg2 = 16, \ + .u32NominalSyncJumpWidth = 16, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 4, \ + .u32DataTimeSeg2 = 1, \ + .u32DataSyncJumpWidth = 1, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 4, \ + .u32TdcFilter = 4 + 1, \ } -#define MCAN_FD_CFG_1M_1M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 32, \ - .u32DataTimeSeg2 = 8, \ - .u32DataSyncJumpWidth = 8, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 2*32, \ - .u32TdcFilter = 2*32 + 1, \ +#define MCAN_FD_CFG_1M_1M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 32, \ + .u32DataTimeSeg2 = 8, \ + .u32DataSyncJumpWidth = 8, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 2 * 32, \ + .u32TdcFilter = 2 * 32 + 1, \ } -#define MCAN_FD_CFG_1M_2M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 16, \ - .u32DataTimeSeg2 = 4, \ - .u32DataSyncJumpWidth = 4, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 16, \ - .u32TdcFilter = 16 + 1, \ +#define MCAN_FD_CFG_1M_2M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 16, \ + .u32DataTimeSeg2 = 4, \ + .u32DataSyncJumpWidth = 4, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 16, \ + .u32TdcFilter = 16 + 1, \ } -#define MCAN_FD_CFG_1M_4M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 8, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 8, \ - .u32TdcFilter = 8 + 1, \ +#define MCAN_FD_CFG_1M_4M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 8, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 8, \ + .u32TdcFilter = 8 + 1, \ } -#define MCAN_FD_CFG_1M_5M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 6, \ - .u32DataTimeSeg2 = 2, \ - .u32DataSyncJumpWidth = 2, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 6, \ - .u32TdcFilter = 6 + 1, \ +#define MCAN_FD_CFG_1M_5M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 6, \ + .u32DataTimeSeg2 = 2, \ + .u32DataSyncJumpWidth = 2, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 6, \ + .u32TdcFilter = 6 + 1, \ } -#define MCAN_FD_CFG_1M_8M \ - { \ - .u32NominalPrescaler = 1, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ - .u32DataPrescaler = 1, \ - .u32DataTimeSeg1 = 4, \ - .u32DataTimeSeg2 = 1, \ - .u32DataSyncJumpWidth = 1, \ - .u32TDC = MCAN_FD_TDC_ENABLE, \ - .u32SspOffset = 4, \ - .u32TdcFilter = 4 + 1, \ +#define MCAN_FD_CFG_1M_8M \ + { \ + .u32NominalPrescaler = 1, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ + .u32DataPrescaler = 1, \ + .u32DataTimeSeg1 = 4, \ + .u32DataTimeSeg2 = 1, \ + .u32DataSyncJumpWidth = 1, \ + .u32TDC = MCAN_FD_TDC_ENABLE, \ + .u32SspOffset = 4, \ + .u32TdcFilter = 4 + 1, \ } /* @@ -260,95 +260,95 @@ extern "C" { SamplePoint(%) = 16 / (16 + 4) = 80% The following bit rate configurations are based on the max MCAN Clock(40MHz). */ -#define MCAN_CC_CFG_1M \ - { \ - .u32NominalPrescaler = 2, \ - .u32NominalTimeSeg1 = 16, \ - .u32NominalTimeSeg2 = 4, \ - .u32NominalSyncJumpWidth = 4, \ +#define MCAN_CC_CFG_1M \ + { \ + .u32NominalPrescaler = 2, \ + .u32NominalTimeSeg1 = 16, \ + .u32NominalTimeSeg2 = 4, \ + .u32NominalSyncJumpWidth = 4, \ } -#define MCAN_CC_CFG_800K \ - { \ - .u32NominalPrescaler = 2, \ - .u32NominalTimeSeg1 = 20, \ - .u32NominalTimeSeg2 = 5, \ - .u32NominalSyncJumpWidth = 5, \ +#define MCAN_CC_CFG_800K \ + { \ + .u32NominalPrescaler = 2, \ + .u32NominalTimeSeg1 = 20, \ + .u32NominalTimeSeg2 = 5, \ + .u32NominalSyncJumpWidth = 5, \ } -#define MCAN_CC_CFG_500K \ - { \ - .u32NominalPrescaler = 4, \ - .u32NominalTimeSeg1 = 16, \ - .u32NominalTimeSeg2 = 4, \ - .u32NominalSyncJumpWidth = 4, \ +#define MCAN_CC_CFG_500K \ + { \ + .u32NominalPrescaler = 4, \ + .u32NominalTimeSeg1 = 16, \ + .u32NominalTimeSeg2 = 4, \ + .u32NominalSyncJumpWidth = 4, \ } -#define MCAN_CC_CFG_250K \ - { \ - .u32NominalPrescaler = 4, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_250K \ + { \ + .u32NominalPrescaler = 4, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_125K \ - { \ - .u32NominalPrescaler = 8, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_125K \ + { \ + .u32NominalPrescaler = 8, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_100K \ - { \ - .u32NominalPrescaler = 10, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_100K \ + { \ + .u32NominalPrescaler = 10, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_50K \ - { \ - .u32NominalPrescaler = 20, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_50K \ + { \ + .u32NominalPrescaler = 20, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_20K \ - { \ - .u32NominalPrescaler = 50, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_20K \ + { \ + .u32NominalPrescaler = 50, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } -#define MCAN_CC_CFG_10K \ - { \ - .u32NominalPrescaler = 100, \ - .u32NominalTimeSeg1 = 32, \ - .u32NominalTimeSeg2 = 8, \ - .u32NominalSyncJumpWidth = 8, \ +#define MCAN_CC_CFG_10K \ + { \ + .u32NominalPrescaler = 100, \ + .u32NominalTimeSeg1 = 32, \ + .u32NominalTimeSeg2 = 8, \ + .u32NominalSyncJumpWidth = 8, \ } #ifdef RT_CAN_USING_CANFD -#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M -#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M -#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M +#define MCAN1_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M +#define MCAN1_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M +#define MCAN1_DATA_BAUD_RATE CANFD_DATA_BAUD_4M -#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M -#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M -#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M +#define MCAN2_BAUD_RATE_CFG MCAN_FD_CFG_1M_4M +#define MCAN2_NOMINAL_BAUD_RATE CANFD_DATA_BAUD_1M +#define MCAN2_DATA_BAUD_RATE CANFD_DATA_BAUD_4M #else -#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M -#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud -#define MCAN1_DATA_BAUD_RATE 0 +#define MCAN1_BAUD_RATE_CFG MCAN_CC_CFG_1M +#define MCAN1_NOMINAL_BAUD_RATE CAN1MBaud +#define MCAN1_DATA_BAUD_RATE 0 -#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M -#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud -#define MCAN2_DATA_BAUD_RATE 0 +#define MCAN2_BAUD_RATE_CFG MCAN_CC_CFG_1M +#define MCAN2_NOMINAL_BAUD_RATE CAN1MBaud +#define MCAN2_DATA_BAUD_RATE 0 #endif /* #ifdef RT_CAN_USING_CANFD */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pm_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pm_config.h index bdfd289f007..ccc45e96c97 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pm_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pm_config.h @@ -22,16 +22,16 @@ extern "C" { extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); #ifndef PM_TICKLESS_TIMER_ENABLE_MASK -#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL) +#define PM_TICKLESS_TIMER_ENABLE_MASK (0UL) #endif /** * @brief run mode config @ref pm_run_mode_config structure */ #ifndef PM_RUN_MODE_CFG -#define PM_RUN_MODE_CFG \ - { \ - .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ } #endif /* PM_RUN_MODE_CFG */ @@ -39,54 +39,54 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); * @brief sleep idle config @ref pm_sleep_mode_idle_config structure */ #ifndef PM_SLEEP_IDLE_CFG -#define PM_SLEEP_IDLE_CFG \ -{ \ - .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ -} +#define PM_SLEEP_IDLE_CFG \ + { \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ + } #endif /*PM_SLEEP_IDLE_CFG*/ /** * @brief sleep deep config @ref pm_sleep_mode_deep_config structure */ #ifndef PM_SLEEP_DEEP_CFG -#define PM_SLEEP_DEEP_CFG \ -{ \ - { \ - .u16Clock = PWC_STOP_CLK_KEEP, \ - .u8StopDrv = PWC_STOP_DRV_HIGH, \ - .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ - .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ - }, \ - .pwc_stop_type = PWC_STOP_WFE_INT, \ -} +#define PM_SLEEP_DEEP_CFG \ + { \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ + } #endif /*PM_SLEEP_DEEP_CFG*/ /** * @brief sleep standby config @ref pm_sleep_mode_standby_config structure */ #ifndef PM_SLEEP_STANDBY_CFG -#define PM_SLEEP_STANDBY_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD1, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ - }, \ -} +#define PM_SLEEP_STANDBY_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } #endif /*PM_SLEEP_STANDBY_CFG*/ /** * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure */ #ifndef PM_SLEEP_SHUTDOWN_CFG -#define PM_SLEEP_SHUTDOWN_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD3, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ - }, \ -} +#define PM_SLEEP_SHUTDOWN_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } #endif /*PM_SLEEP_SHUTDOWN_CFG*/ #endif /* BSP_USING_PM */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pulse_encoder_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pulse_encoder_config.h index 1db10b6d14c..aaa9fea6ba4 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pulse_encoder_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pulse_encoder_config.h @@ -21,520 +21,480 @@ extern "C" { #ifdef BSP_USING_PULSE_ENCODER_TMRA_1 #ifndef PULSE_ENCODER_TMRA_1_CONFIG -#define PULSE_ENCODER_TMRA_1_CONFIG \ - { \ - .tmr_handler = CM_TMRA_1, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a1" \ +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ } #endif /* PULSE_ENCODER_TMRA_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_2 #ifndef PULSE_ENCODER_TMRA_2_CONFIG -#define PULSE_ENCODER_TMRA_2_CONFIG \ - { \ - .tmr_handler = CM_TMRA_2, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a2" \ +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ } #endif /* PULSE_ENCODER_TMRA_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_3 #ifndef PULSE_ENCODER_TMRA_3_CONFIG -#define PULSE_ENCODER_TMRA_3_CONFIG \ - { \ - .tmr_handler = CM_TMRA_3, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a3" \ +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ } #endif /* PULSE_ENCODER_TMRA_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_4 #ifndef PULSE_ENCODER_TMRA_4_CONFIG -#define PULSE_ENCODER_TMRA_4_CONFIG \ - { \ - .tmr_handler = CM_TMRA_4, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a4" \ +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ } #endif /* PULSE_ENCODER_TMRA_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_5 #ifndef PULSE_ENCODER_TMRA_5_CONFIG -#define PULSE_ENCODER_TMRA_5_CONFIG \ - { \ - .tmr_handler = CM_TMRA_5, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a5" \ +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ } #endif /* PULSE_ENCODER_TMRA_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_6 #ifndef PULSE_ENCODER_TMRA_6_CONFIG -#define PULSE_ENCODER_TMRA_6_CONFIG \ - { \ - .tmr_handler = CM_TMRA_6, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a6" \ +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ } #endif /* PULSE_ENCODER_TMRA_6_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_7 #ifndef PULSE_ENCODER_TMRA_7_CONFIG -#define PULSE_ENCODER_TMRA_7_CONFIG \ - { \ - .tmr_handler = CM_TMRA_7, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_7, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a7" \ +#define PULSE_ENCODER_TMRA_7_CONFIG \ + { \ + .tmr_handler = CM_TMRA_7, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_7, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a7" \ } #endif /* PULSE_ENCODER_TMRA_7_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_8 #ifndef PULSE_ENCODER_TMRA_8_CONFIG -#define PULSE_ENCODER_TMRA_8_CONFIG \ - { \ - .tmr_handler = CM_TMRA_8, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_8, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a8" \ +#define PULSE_ENCODER_TMRA_8_CONFIG \ + { \ + .tmr_handler = CM_TMRA_8, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_8, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a8" \ } #endif /* PULSE_ENCODER_TMRA_8_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_9 #ifndef PULSE_ENCODER_TMRA_9_CONFIG -#define PULSE_ENCODER_TMRA_9_CONFIG \ - { \ - .tmr_handler = CM_TMRA_9, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_9, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_9_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_9_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a9" \ +#define PULSE_ENCODER_TMRA_9_CONFIG \ + { \ + .tmr_handler = CM_TMRA_9, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_9, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_9_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_9_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a9" \ } #endif /* PULSE_ENCODER_TMRA_9_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_10 #ifndef PULSE_ENCODER_TMRA_10_CONFIG -#define PULSE_ENCODER_TMRA_10_CONFIG \ - { \ - .tmr_handler = CM_TMRA_10, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_10, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_10_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_10_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a10" \ +#define PULSE_ENCODER_TMRA_10_CONFIG \ + { \ + .tmr_handler = CM_TMRA_10, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_10, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_10_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_10_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a10" \ } #endif /* PULSE_ENCODER_TMRA_10_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_11 #ifndef PULSE_ENCODER_TMRA_11_CONFIG -#define PULSE_ENCODER_TMRA_11_CONFIG \ - { \ - .tmr_handler = CM_TMRA_11, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_11, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_11_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_11_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a11" \ +#define PULSE_ENCODER_TMRA_11_CONFIG \ + { \ + .tmr_handler = CM_TMRA_11, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_11, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_11_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_11_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a11" \ } #endif /* PULSE_ENCODER_TMRA_11_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_12 #ifndef PULSE_ENCODER_TMRA_12_CONFIG -#define PULSE_ENCODER_TMRA_12_CONFIG \ - { \ - .tmr_handler = CM_TMRA_12, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_12, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_12_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_12_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a12" \ +#define PULSE_ENCODER_TMRA_12_CONFIG \ + { \ + .tmr_handler = CM_TMRA_12, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_12, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_12_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_12_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a12" \ } #endif /* PULSE_ENCODER_TMRA_12_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_1 #ifndef PULSE_ENCODER_TMR6_1_CONFIG -#define PULSE_ENCODER_TMR6_1_CONFIG \ - { \ - .tmr_handler = CM_TMR6_1, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_61" \ +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ } #endif /* PULSE_ENCODER_TMR6_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_2 #ifndef PULSE_ENCODER_TMR6_2_CONFIG -#define PULSE_ENCODER_TMR6_2_CONFIG \ - { \ - .tmr_handler = CM_TMR6_2, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_62" \ +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ } #endif /* PULSE_ENCODER_TMR6_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_3 #ifndef PULSE_ENCODER_TMR6_3_CONFIG -#define PULSE_ENCODER_TMR6_3_CONFIG \ - { \ - .tmr_handler = CM_TMR6_3, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_63" \ +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ } #endif /* PULSE_ENCODER_TMR6_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_4 #ifndef PULSE_ENCODER_TMR6_4_CONFIG -#define PULSE_ENCODER_TMR6_4_CONFIG \ - { \ - .tmr_handler = CM_TMR6_4, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_4, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_64" \ +#define PULSE_ENCODER_TMR6_4_CONFIG \ + { \ + .tmr_handler = CM_TMR6_4, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_4, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_64" \ } #endif /* PULSE_ENCODER_TMR6_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_5 #ifndef PULSE_ENCODER_TMR6_5_CONFIG -#define PULSE_ENCODER_TMR6_5_CONFIG \ - { \ - .tmr_handler = CM_TMR6_5, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_5, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_65" \ +#define PULSE_ENCODER_TMR6_5_CONFIG \ + { \ + .tmr_handler = CM_TMR6_5, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_5, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_65" \ } #endif /* PULSE_ENCODER_TMR6_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_6 #ifndef PULSE_ENCODER_TMR6_6_CONFIG -#define PULSE_ENCODER_TMR6_6_CONFIG \ - { \ - .tmr_handler = CM_TMR6_6, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_6, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_66" \ +#define PULSE_ENCODER_TMR6_6_CONFIG \ + { \ + .tmr_handler = CM_TMR6_6, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_6, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_66" \ } #endif /* PULSE_ENCODER_TMR6_6_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_7 #ifndef PULSE_ENCODER_TMR6_7_CONFIG -#define PULSE_ENCODER_TMR6_7_CONFIG \ - { \ - .tmr_handler = CM_TMR6_7, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_7, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_67" \ +#define PULSE_ENCODER_TMR6_7_CONFIG \ + { \ + .tmr_handler = CM_TMR6_7, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_7, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_67" \ } #endif /* PULSE_ENCODER_TMR6_7_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_8 #ifndef PULSE_ENCODER_TMR6_8_CONFIG -#define PULSE_ENCODER_TMR6_8_CONFIG \ - { \ - .tmr_handler = CM_TMR6_8, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_8, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_68" \ +#define PULSE_ENCODER_TMR6_8_CONFIG \ + { \ + .tmr_handler = CM_TMR6_8, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_8, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_68" \ } #endif /* PULSE_ENCODER_TMR6_8_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pwm_tmr_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pwm_tmr_config.h index da87f320f8b..93918cd0366 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pwm_tmr_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/pwm_tmr_config.h @@ -21,372 +21,324 @@ extern "C" { #ifdef BSP_USING_PWM_TMRA_1 #ifndef PWM_TMRA_1_CONFIG -#define PWM_TMRA_1_CONFIG \ - { \ - .name = "pwm_a1", \ - .instance = CM_TMRA_1, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_1_CONFIG */ #endif /* BSP_USING_PWM_TMRA_1 */ #ifdef BSP_USING_PWM_TMRA_2 #ifndef PWM_TMRA_2_CONFIG -#define PWM_TMRA_2_CONFIG \ - { \ - .name = "pwm_a2", \ - .instance = CM_TMRA_2, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_2_CONFIG */ #endif /* BSP_USING_PWM_TMRA_2 */ #ifdef BSP_USING_PWM_TMRA_3 #ifndef PWM_TMRA_3_CONFIG -#define PWM_TMRA_3_CONFIG \ - { \ - .name = "pwm_a3", \ - .instance = CM_TMRA_3, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_3_CONFIG */ #endif /* BSP_USING_PWM_TMRA_3 */ #ifdef BSP_USING_PWM_TMRA_4 #ifndef PWM_TMRA_4_CONFIG -#define PWM_TMRA_4_CONFIG \ - { \ - .name = "pwm_a4", \ - .instance = CM_TMRA_4, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_4_CONFIG */ #endif /* BSP_USING_PWM_TMRA_4 */ #ifdef BSP_USING_PWM_TMRA_5 #ifndef PWM_TMRA_5_CONFIG -#define PWM_TMRA_5_CONFIG \ - { \ - .name = "pwm_a5", \ - .instance = CM_TMRA_5, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_5_CONFIG */ #endif /* BSP_USING_PWM_TMRA_5 */ #ifdef BSP_USING_PWM_TMRA_6 #ifndef PWM_TMRA_6_CONFIG -#define PWM_TMRA_6_CONFIG \ - { \ - .name = "pwm_a6", \ - .instance = CM_TMRA_6, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_6_CONFIG */ #endif /* BSP_USING_PWM_TMRA_6 */ #ifdef BSP_USING_PWM_TMRA_7 #ifndef PWM_TMRA_7_CONFIG -#define PWM_TMRA_7_CONFIG \ - { \ - .name = "pwm_a7", \ - .instance = CM_TMRA_7, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_7_CONFIG \ + { \ + .name = "pwm_a7", \ + .instance = CM_TMRA_7, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_7_CONFIG */ #endif /* BSP_USING_PWM_TMRA_7 */ #ifdef BSP_USING_PWM_TMRA_8 #ifndef PWM_TMRA_8_CONFIG -#define PWM_TMRA_8_CONFIG \ - { \ - .name = "pwm_a8", \ - .instance = CM_TMRA_8, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_8_CONFIG \ + { \ + .name = "pwm_a8", \ + .instance = CM_TMRA_8, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_8_CONFIG */ #endif /* BSP_USING_PWM_TMRA_8 */ #ifdef BSP_USING_PWM_TMRA_9 #ifndef PWM_TMRA_9_CONFIG -#define PWM_TMRA_9_CONFIG \ - { \ - .name = "pwm_a9", \ - .instance = CM_TMRA_9, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_9_CONFIG \ + { \ + .name = "pwm_a9", \ + .instance = CM_TMRA_9, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_9_CONFIG */ #endif /* BSP_USING_PWM_TMRA_9 */ #ifdef BSP_USING_PWM_TMRA_10 #ifndef PWM_TMRA_10_CONFIG -#define PWM_TMRA_10_CONFIG \ - { \ - .name = "pwm_a10", \ - .instance = CM_TMRA_10, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_10_CONFIG \ + { \ + .name = "pwm_a10", \ + .instance = CM_TMRA_10, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_10_CONFIG */ #endif /* BSP_USING_PWM_TMRA_10 */ #ifdef BSP_USING_PWM_TMRA_11 #ifndef PWM_TMRA_11_CONFIG -#define PWM_TMRA_11_CONFIG \ - { \ - .name = "pwm_a11", \ - .instance = CM_TMRA_11, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_11_CONFIG \ + { \ + .name = "pwm_a11", \ + .instance = CM_TMRA_11, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_11_CONFIG */ #endif /* BSP_USING_PWM_TMRA_11 */ #ifdef BSP_USING_PWM_TMRA_12 #ifndef PWM_TMRA_12_CONFIG -#define PWM_TMRA_12_CONFIG \ - { \ - .name = "pwm_a12", \ - .instance = CM_TMRA_12, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_12_CONFIG \ + { \ + .name = "pwm_a12", \ + .instance = CM_TMRA_12, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_12_CONFIG */ #endif /* BSP_USING_PWM_TMRA_12 */ @@ -397,96 +349,87 @@ extern "C" { #ifdef BSP_USING_PWM_TMR4_1 #ifndef PWM_TMR4_1_CONFIG -#define PWM_TMR4_1_CONFIG \ - { \ - .name = "pwm_t41", \ - .instance = CM_TMR4_1, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_1_CONFIG */ #endif /* BSP_USING_PWM_TMR4_1 */ #ifdef BSP_USING_PWM_TMR4_2 #ifndef PWM_TMR4_2_CONFIG -#define PWM_TMR4_2_CONFIG \ - { \ - .name = "pwm_t42", \ - .instance = CM_TMR4_2, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_2_CONFIG */ #endif /* BSP_USING_PWM_TMR4_2 */ #ifdef BSP_USING_PWM_TMR4_3 #ifndef PWM_TMR4_3_CONFIG -#define PWM_TMR4_3_CONFIG \ - { \ - .name = "pwm_t43", \ - .instance = CM_TMR4_3, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_3_CONFIG */ #endif /* BSP_USING_PWM_TMR4_3 */ @@ -497,377 +440,337 @@ extern "C" { #ifdef BSP_USING_PWM_TMR6_1 #ifndef PWM_TMR6_1_CONFIG -#define PWM_TMR6_1_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_1, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_1_CONFIG */ #endif /* BSP_USING_PWM_TMR6_1 */ #ifdef BSP_USING_PWM_TMR6_2 #ifndef PWM_TMR6_2_CONFIG -#define PWM_TMR6_2_CONFIG \ - { \ - .name = "pwm_t62", \ - .instance = CM_TMR6_2, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t62", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_2_CONFIG */ #endif /* BSP_USING_PWM_TMR6_2 */ #ifdef BSP_USING_PWM_TMR6_3 #ifndef PWM_TMR6_3_CONFIG -#define PWM_TMR6_3_CONFIG \ - { \ - .name = "pwm_t63", \ - .instance = CM_TMR6_3, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t63", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_3_CONFIG */ #endif /* BSP_USING_PWM_TMR6_3 */ #ifdef BSP_USING_PWM_TMR6_4 #ifndef PWM_TMR6_4_CONFIG -#define PWM_TMR6_4_CONFIG \ - { \ - .name = "pwm_t64", \ - .instance = CM_TMR6_4, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t64", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_4_CONFIG */ #endif /* BSP_USING_PWM_TMR6_4 */ #ifdef BSP_USING_PWM_TMR6_5 #ifndef PWM_TMR6_5_CONFIG -#define PWM_TMR6_5_CONFIG \ - { \ - .name = "pwm_t65", \ - .instance = CM_TMR6_5, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_5_CONFIG \ + { \ + .name = "pwm_t65", \ + .instance = CM_TMR6_5, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_5_CONFIG */ #endif /* BSP_USING_PWM_TMR6_5 */ #ifdef BSP_USING_PWM_TMR6_6 #ifndef PWM_TMR6_6_CONFIG -#define PWM_TMR6_6_CONFIG \ - { \ - .name = "pwm_t66", \ - .instance = CM_TMR6_6, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_6_CONFIG \ + { \ + .name = "pwm_t66", \ + .instance = CM_TMR6_6, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_6_CONFIG */ #endif /* BSP_USING_PWM_TMR6_6 */ #ifdef BSP_USING_PWM_TMR6_7 #ifndef PWM_TMR6_7_CONFIG -#define PWM_TMR6_7_CONFIG \ - { \ - .name = "pwm_t67", \ - .instance = CM_TMR6_7, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_7_CONFIG \ + { \ + .name = "pwm_t67", \ + .instance = CM_TMR6_7, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_7_CONFIG */ #endif /* BSP_USING_PWM_TMR6_7 */ #ifdef BSP_USING_PWM_TMR6_8 #ifndef PWM_TMR6_8_CONFIG -#define PWM_TMR6_8_CONFIG \ - { \ - .name = "pwm_t68", \ - .instance = CM_TMR6_8, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_8_CONFIG \ + { \ + .name = "pwm_t68", \ + .instance = CM_TMR6_8, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_8_CONFIG */ #endif /* BSP_USING_PWM_TMR6_8 */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/qspi_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/qspi_config.h index 7d628143eec..6d7c7f395eb 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/qspi_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/qspi_config.h @@ -21,54 +21,52 @@ extern "C" { #ifdef BSP_USING_QSPI #ifndef QSPI_BUS_CONFIG -#define QSPI_BUS_CONFIG \ - { \ - .Instance = CM_QSPI, \ - .clock = FCG1_PERIPH_QSPI, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ - .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_QSPI_INTR, \ - }, \ +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ } #endif /* QSPI_BUS_CONFIG */ #ifndef QSPI_INIT_PARAMS -#define QSPI_INIT_PARAMS \ - { \ - .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ - .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ - .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ - .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ } #endif /* QSPI_INIT_PARAMS */ -#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH #ifdef BSP_QSPI_USING_DMA #ifndef QSPI_DMA_CONFIG -#define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .channel = QSPI_DMA_CHANNEL, \ - .clock = QSPI_DMA_CLOCK, \ - .trigger_select = QSPI_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_AOS_STRG, \ - .flag = QSPI_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = QSPI_DMA_IRQn, \ - .irq_prio = QSPI_DMA_INT_PRIO, \ - .int_src = QSPI_DMA_INT_SRC, \ - } \ +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ } #endif /* QSPI_DMA_CONFIG */ /* unit: half-word, DMA data width of QSPI transmitting is 16bit */ #ifndef QSPI_DMA_TX_BUFSIZE -#define QSPI_DMA_TX_BUFSIZE 256 +#define QSPI_DMA_TX_BUFSIZE 256 #endif /* QSPI_DMA_TX_BUFSIZE */ #endif /* BSP_QSPI_USING_DMA */ #endif /* BSP_USING_QSPI */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/sdio_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/sdio_config.h index 9d86a6d36e1..009b23607c0 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/sdio_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/sdio_config.h @@ -22,66 +22,60 @@ extern "C" { #if defined(BSP_USING_SDIO1) #ifndef SDIO1_BUS_CONFIG -#define SDIO1_BUS_CONFIG \ - { \ - .name = "sdio1", \ - .instance = CM_SDIOC1, \ - .clock = FCG1_PERIPH_SDIOC1, \ - .irq_config = \ - { \ - .irq_num = BSP_SDIO1_IRQ_NUM, \ - .irq_prio = BSP_SDIO1_IRQ_PRIO, \ - .int_src = INT_SRC_SDIOC1_SD, \ - }, \ - .dma_rx = \ - { \ - .Instance = SDIO1_RX_DMA_INSTANCE, \ - .channel = SDIO1_RX_DMA_CHANNEL, \ - .clock = SDIO1_RX_DMA_CLOCK, \ - .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC1_DMAR, \ - }, \ - .dma_tx = \ - { \ - .Instance = SDIO1_TX_DMA_INSTANCE, \ - .channel = SDIO1_TX_DMA_CHANNEL, \ - .clock = SDIO1_TX_DMA_CLOCK, \ - .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC1_DMAW, \ - }, \ +#define SDIO1_BUS_CONFIG \ + { \ + .name = "sdio1", \ + .instance = CM_SDIOC1, \ + .clock = FCG1_PERIPH_SDIOC1, \ + .irq_config = { \ + .irq_num = BSP_SDIO1_IRQ_NUM, \ + .irq_prio = BSP_SDIO1_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC1_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO1_RX_DMA_INSTANCE, \ + .channel = SDIO1_RX_DMA_CHANNEL, \ + .clock = SDIO1_RX_DMA_CLOCK, \ + .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO1_TX_DMA_INSTANCE, \ + .channel = SDIO1_TX_DMA_CHANNEL, \ + .clock = SDIO1_TX_DMA_CLOCK, \ + .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAW, \ + }, \ } #endif /* SDIO1_BUS_CONFIG */ #endif /* BSP_USING_SDIO1 */ #if defined(BSP_USING_SDIO2) #ifndef SDIO2_BUS_CONFIG -#define SDIO2_BUS_CONFIG \ - { \ - .name = "sdio2", \ - .instance = CM_SDIOC2, \ - .clock = FCG1_PERIPH_SDIOC2, \ - .irq_config = \ - { \ - .irq_num = BSP_SDIO2_IRQ_NUM, \ - .irq_prio = BSP_SDIO2_IRQ_PRIO, \ - .int_src = INT_SRC_SDIOC2_SD, \ - }, \ - .dma_rx = \ - { \ - .Instance = SDIO2_RX_DMA_INSTANCE, \ - .channel = SDIO2_RX_DMA_CHANNEL, \ - .clock = SDIO2_RX_DMA_CLOCK, \ - .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC2_DMAR, \ - }, \ - .dma_tx = \ - { \ - .Instance = SDIO2_TX_DMA_INSTANCE, \ - .channel = SDIO2_TX_DMA_CHANNEL, \ - .clock = SDIO2_TX_DMA_CLOCK, \ - .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC2_DMAW, \ - }, \ +#define SDIO2_BUS_CONFIG \ + { \ + .name = "sdio2", \ + .instance = CM_SDIOC2, \ + .clock = FCG1_PERIPH_SDIOC2, \ + .irq_config = { \ + .irq_num = BSP_SDIO2_IRQ_NUM, \ + .irq_prio = BSP_SDIO2_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC2_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO2_RX_DMA_INSTANCE, \ + .channel = SDIO2_RX_DMA_CHANNEL, \ + .clock = SDIO2_RX_DMA_CLOCK, \ + .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO2_TX_DMA_INSTANCE, \ + .channel = SDIO2_TX_DMA_CHANNEL, \ + .clock = SDIO2_TX_DMA_CLOCK, \ + .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAW, \ + }, \ } #endif /* SDIO2_BUS_CONFIG */ #endif /* BSP_USING_SDIO2 */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/spi_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/spi_config.h index a839686bd3c..13e6acc6905 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/spi_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/spi_config.h @@ -21,134 +21,127 @@ extern "C" { #ifdef BSP_USING_SPI1 #ifndef SPI1_BUS_CONFIG -#define SPI1_BUS_CONFIG \ - { \ - .Instance = CM_SPI1, \ - .bus_name = "spi1", \ - .clock = FCG1_PERIPH_SPI1, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI1_SPEI, \ - }, \ +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .clock = SPI1_TX_DMA_CLOCK, \ - .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPTI, \ - .flag = SPI1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_TX_DMA_IRQn, \ - .irq_prio = SPI1_TX_DMA_INT_PRIO, \ - .int_src = SPI1_TX_DMA_INT_SRC, \ - } \ +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .clock = SPI1_RX_DMA_CLOCK, \ - .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPRI, \ - .flag = SPI1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_RX_DMA_IRQn, \ - .irq_prio = SPI1_RX_DMA_INT_PRIO, \ - .int_src = SPI1_RX_DMA_INT_SRC, \ - } \ +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 #ifndef SPI2_BUS_CONFIG -#define SPI2_BUS_CONFIG \ - { \ - .Instance = CM_SPI2, \ - .bus_name = "spi2", \ - .clock = FCG1_PERIPH_SPI2, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI2_SPEI, \ - }, \ +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .channel = SPI2_TX_DMA_CHANNEL, \ - .clock = SPI2_TX_DMA_CLOCK, \ - .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPTI, \ - .flag = SPI2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_TX_DMA_IRQn, \ - .irq_prio = SPI2_TX_DMA_INT_PRIO, \ - .int_src = SPI2_TX_DMA_INT_SRC, \ - } \ +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .channel = SPI2_RX_DMA_CHANNEL, \ - .clock = SPI2_RX_DMA_CLOCK, \ - .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPRI, \ - .flag = SPI2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_RX_DMA_IRQn, \ - .irq_prio = SPI2_RX_DMA_INT_PRIO, \ - .int_src = SPI2_RX_DMA_INT_SRC, \ - } \ +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 #ifndef SPI3_BUS_CONFIG -#define SPI3_BUS_CONFIG \ - { \ - .Instance = CM_SPI3, \ - .bus_name = "spi3", \ - .clock = FCG1_PERIPH_SPI3, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI3_SPEI, \ - }, \ +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ @@ -156,214 +149,203 @@ extern "C" { #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .channel = SPI3_TX_DMA_CHANNEL, \ - .clock = SPI3_TX_DMA_CLOCK, \ - .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPTI, \ - .flag = SPI3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_TX_DMA_IRQn, \ - .irq_prio = SPI3_TX_DMA_INT_PRIO, \ - .int_src = SPI3_TX_DMA_INT_SRC, \ - } \ +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .channel = SPI3_RX_DMA_CHANNEL, \ - .clock = SPI3_RX_DMA_CLOCK, \ - .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPRI, \ - .flag = SPI3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_RX_DMA_IRQn, \ - .irq_prio = SPI3_RX_DMA_INT_PRIO, \ - .int_src = SPI3_RX_DMA_INT_SRC, \ - } \ +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ #ifdef BSP_USING_SPI4 #ifndef SPI4_BUS_CONFIG -#define SPI4_BUS_CONFIG \ - { \ - .Instance = CM_SPI4, \ - .bus_name = "spi4", \ - .clock = FCG1_PERIPH_SPI4, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI4_SPEI, \ - }, \ +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ } #endif /* SPI4_BUS_CONFIG */ #endif /* BSP_USING_SPI4 */ #ifdef BSP_SPI4_TX_USING_DMA #ifndef SPI4_TX_DMA_CONFIG -#define SPI4_TX_DMA_CONFIG \ - { \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .channel = SPI4_TX_DMA_CHANNEL, \ - .clock = SPI4_TX_DMA_CLOCK, \ - .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI4_SPTI, \ - .flag = SPI4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI4_TX_DMA_IRQn, \ - .irq_prio = SPI4_TX_DMA_INT_PRIO, \ - .int_src = SPI4_TX_DMA_INT_SRC, \ - } \ +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ #ifdef BSP_SPI4_RX_USING_DMA #ifndef SPI4_RX_DMA_CONFIG -#define SPI4_RX_DMA_CONFIG \ - { \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .channel = SPI4_RX_DMA_CHANNEL, \ - .clock = SPI4_RX_DMA_CLOCK, \ - .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI4_SPRI, \ - .flag = SPI4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI4_RX_DMA_IRQn, \ - .irq_prio = SPI4_RX_DMA_INT_PRIO, \ - .int_src = SPI4_RX_DMA_INT_SRC, \ - } \ +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ #ifdef BSP_USING_SPI5 #ifndef SPI5_BUS_CONFIG -#define SPI5_BUS_CONFIG \ - { \ - .Instance = CM_SPI5, \ - .bus_name = "spi5", \ - .clock = FCG1_PERIPH_SPI5, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI5_SPEI, \ - }, \ +#define SPI5_BUS_CONFIG \ + { \ + .Instance = CM_SPI5, \ + .bus_name = "spi5", \ + .clock = FCG1_PERIPH_SPI5, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI5_SPEI, \ + }, \ } #endif /* SPI5_BUS_CONFIG */ #endif /* BSP_USING_SPI5 */ #ifdef BSP_SPI5_TX_USING_DMA #ifndef SPI5_TX_DMA_CONFIG -#define SPI5_TX_DMA_CONFIG \ - { \ - .Instance = SPI5_TX_DMA_INSTANCE, \ - .channel = SPI5_TX_DMA_CHANNEL, \ - .clock = SPI5_TX_DMA_CLOCK, \ - .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI5_SPTI, \ - .flag = SPI5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI5_TX_DMA_IRQn, \ - .irq_prio = SPI5_TX_DMA_INT_PRIO, \ - .int_src = SPI5_TX_DMA_INT_SRC, \ - } \ +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .clock = SPI5_TX_DMA_CLOCK, \ + .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPTI, \ + .flag = SPI5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI5_TX_DMA_CONFIG */ #endif /* BSP_SPI5_TX_USING_DMA */ #ifdef BSP_SPI5_RX_USING_DMA #ifndef SPI5_RX_DMA_CONFIG -#define SPI5_RX_DMA_CONFIG \ - { \ - .Instance = SPI5_RX_DMA_INSTANCE, \ - .channel = SPI5_RX_DMA_CHANNEL, \ - .clock = SPI5_RX_DMA_CLOCK, \ - .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI5_SPRI, \ - .flag = SPI5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI5_RX_DMA_IRQn, \ - .irq_prio = SPI5_RX_DMA_INT_PRIO, \ - .int_src = SPI5_RX_DMA_INT_SRC, \ - } \ +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .clock = SPI5_RX_DMA_CLOCK, \ + .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPRI, \ + .flag = SPI5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI5_RX_DMA_CONFIG */ #endif /* BSP_SPI5_RX_USING_DMA */ #ifdef BSP_USING_SPI6 #ifndef SPI6_BUS_CONFIG -#define SPI6_BUS_CONFIG \ - { \ - .Instance = CM_SPI6, \ - .bus_name = "spi6", \ - .clock = FCG1_PERIPH_SPI6, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI6_SPEI, \ - }, \ +#define SPI6_BUS_CONFIG \ + { \ + .Instance = CM_SPI6, \ + .bus_name = "spi6", \ + .clock = FCG1_PERIPH_SPI6, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI6_SPEI, \ + }, \ } #endif /* SPI6_BUS_CONFIG */ #endif /* BSP_USING_SPI6 */ #ifdef BSP_SPI6_TX_USING_DMA #ifndef SPI6_TX_DMA_CONFIG -#define SPI6_TX_DMA_CONFIG \ - { \ - .Instance = SPI6_TX_DMA_INSTANCE, \ - .channel = SPI6_TX_DMA_CHANNEL, \ - .clock = SPI6_TX_DMA_CLOCK, \ - .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI6_SPTI, \ - .flag = SPI6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI6_TX_DMA_IRQn, \ - .irq_prio = SPI6_TX_DMA_INT_PRIO, \ - .int_src = SPI6_TX_DMA_INT_SRC, \ - } \ +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .clock = SPI6_TX_DMA_CLOCK, \ + .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPTI, \ + .flag = SPI6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI6_TX_DMA_CONFIG */ #endif /* BSP_SPI6_TX_USING_DMA */ #ifdef BSP_SPI6_RX_USING_DMA #ifndef SPI6_RX_DMA_CONFIG -#define SPI6_RX_DMA_CONFIG \ - { \ - .Instance = SPI6_RX_DMA_INSTANCE, \ - .channel = SPI6_RX_DMA_CHANNEL, \ - .clock = SPI6_RX_DMA_CLOCK, \ - .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI6_SPRI, \ - .flag = SPI6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI6_RX_DMA_IRQn, \ - .irq_prio = SPI6_RX_DMA_INT_PRIO, \ - .int_src = SPI6_RX_DMA_INT_SRC, \ - } \ +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .clock = SPI6_RX_DMA_CLOCK, \ + .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPRI, \ + .flag = SPI6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI6_RX_DMA_CONFIG */ #endif /* BSP_SPI6_RX_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/timer_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/timer_config.h index 553ffc86293..414a64a3652 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/timer_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/timer_config.h @@ -19,228 +19,216 @@ extern "C" { #ifdef BSP_USING_TMRA_1 #ifndef TMRA_1_CONFIG -#define TMRA_1_CONFIG \ - { \ - .tmr_handle = CM_TMRA_1, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_1, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_1_OVF, \ - .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ - }, \ - .name = "tmra_1" \ +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ } #endif /* TMRA_1_CONFIG */ #endif /* BSP_USING_TMRA_1 */ #ifdef BSP_USING_TMRA_2 #ifndef TMRA_2_CONFIG -#define TMRA_2_CONFIG \ - { \ - .tmr_handle = CM_TMRA_2, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_2, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_2_OVF, \ - .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ - }, \ - .name = "tmra_2" \ +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ } #endif /* TMRA_2_CONFIG */ #endif /* BSP_USING_TMRA_2 */ #ifdef BSP_USING_TMRA_3 #ifndef TMRA_3_CONFIG -#define TMRA_3_CONFIG \ - { \ - .tmr_handle = CM_TMRA_3, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_3, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_3_OVF, \ - .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ - }, \ - .name = "tmra_3" \ +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ } #endif /* TMRA_3_CONFIG */ #endif /* BSP_USING_TMRA_3 */ #ifdef BSP_USING_TMRA_4 #ifndef TMRA_4_CONFIG -#define TMRA_4_CONFIG \ - { \ - .tmr_handle = CM_TMRA_4, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_4, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_4_OVF, \ - .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ - }, \ - .name = "tmra_4" \ +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ } #endif /* TMRA_4_CONFIG */ #endif /* BSP_USING_TMRA_4 */ #ifdef BSP_USING_TMRA_5 #ifndef TMRA_5_CONFIG -#define TMRA_5_CONFIG \ - { \ - .tmr_handle = CM_TMRA_5, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_5, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_5_OVF, \ - .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ - }, \ - .name = "tmra_5" \ +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ } #endif /* TMRA_5_CONFIG */ #endif /* BSP_USING_TMRA_5 */ #ifdef BSP_USING_TMRA_6 #ifndef TMRA_6_CONFIG -#define TMRA_6_CONFIG \ - { \ - .tmr_handle = CM_TMRA_6, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_6, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_6_OVF, \ - .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ - }, \ - .name = "tmra_6" \ +#define TMRA_6_CONFIG \ + { \ + .tmr_handle = CM_TMRA_6, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_6, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_6_OVF, \ + .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ + }, \ + .name = "tmra_6" \ } #endif /* TMRA_6_CONFIG */ #endif /* BSP_USING_TMRA_6 */ #ifdef BSP_USING_TMRA_7 #ifndef TMRA_7_CONFIG -#define TMRA_7_CONFIG \ - { \ - .tmr_handle = CM_TMRA_7, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_7, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_7_OVF, \ - .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ - }, \ - .name = "tmra_7" \ +#define TMRA_7_CONFIG \ + { \ + .tmr_handle = CM_TMRA_7, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_7, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_7_OVF, \ + .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ + }, \ + .name = "tmra_7" \ } #endif /* TMRA_7_CONFIG */ #endif /* BSP_USING_TMRA_7 */ #ifdef BSP_USING_TMRA_8 #ifndef TMRA_8_CONFIG -#define TMRA_8_CONFIG \ - { \ - .tmr_handle = CM_TMRA_8, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_8, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_8_OVF, \ - .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ - }, \ - .name = "tmra_8" \ +#define TMRA_8_CONFIG \ + { \ + .tmr_handle = CM_TMRA_8, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_8, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_8_OVF, \ + .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ + }, \ + .name = "tmra_8" \ } #endif /* TMRA_8_CONFIG */ #endif /* BSP_USING_TMRA_8 */ #ifdef BSP_USING_TMRA_9 #ifndef TMRA_9_CONFIG -#define TMRA_9_CONFIG \ - { \ - .tmr_handle = CM_TMRA_9, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_9, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_9_OVF, \ - .enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \ - }, \ - .name = "tmra_9" \ +#define TMRA_9_CONFIG \ + { \ + .tmr_handle = CM_TMRA_9, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_9, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_9_OVF, \ + .enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \ + }, \ + .name = "tmra_9" \ } #endif /* TMRA_9_CONFIG */ #endif /* BSP_USING_TMRA_9 */ #ifdef BSP_USING_TMRA_10 #ifndef TMRA_10_CONFIG -#define TMRA_10_CONFIG \ - { \ - .tmr_handle = CM_TMRA_10, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_10, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_10_OVF, \ - .enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \ - }, \ - .name = "tmra_10" \ +#define TMRA_10_CONFIG \ + { \ + .tmr_handle = CM_TMRA_10, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_10, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_10_OVF, \ + .enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \ + }, \ + .name = "tmra_10" \ } #endif /* TMRA_10_CONFIG */ #endif /* BSP_USING_TMRA_10 */ #ifdef BSP_USING_TMRA_11 #ifndef TMRA_11_CONFIG -#define TMRA_11_CONFIG \ - { \ - .tmr_handle = CM_TMRA_11, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_11, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_11_OVF, \ - .enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \ - }, \ - .name = "tmra_11" \ +#define TMRA_11_CONFIG \ + { \ + .tmr_handle = CM_TMRA_11, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_11, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_11_OVF, \ + .enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \ + }, \ + .name = "tmra_11" \ } #endif /* TMRA_11_CONFIG */ #endif /* BSP_USING_TMRA_11 */ #ifdef BSP_USING_TMRA_12 #ifndef TMRA_12_CONFIG -#define TMRA_12_CONFIG \ - { \ - .tmr_handle = CM_TMRA_12, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_12, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_12_OVF, \ - .enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \ - }, \ - .name = "tmra_12" \ +#define TMRA_12_CONFIG \ + { \ + .tmr_handle = CM_TMRA_12, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_12, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_12_OVF, \ + .enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \ + }, \ + .name = "tmra_12" \ } #endif /* TMRA_12_CONFIG */ #endif /* BSP_USING_TMRA_12 */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/tmr_capture_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/tmr_capture_config.h index 65d4d8eed54..ba231bec707 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/tmr_capture_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/tmr_capture_config.h @@ -17,49 +17,49 @@ extern "C" { #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) #define IC1_NAME "ic1" -#define INPUT_CAPTURE_CFG_TMR6_1 \ -{ \ - .name = IC1_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_1 \ + { \ + .name = IC1_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_PWMA_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_1_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_1_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) #define IC2_NAME "ic2" -#define INPUT_CAPTURE_CFG_TMR6_2 \ -{ \ - .name = IC2_NAME, \ - .ch = TMR6_CH_A, \ - .clk_div = TMR6_CLK_DIV32, \ - .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_2 \ + { \ + .name = IC2_NAME, \ + .ch = TMR6_CH_A, \ + .clk_div = TMR6_CLK_DIV32, \ + .first_edge = TMR6_CAPT_COND_TRIGB_RISING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_2_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_2_OVF_IRQ_PRIO, \ + } #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) #define IC3_NAME "ic3" -#define INPUT_CAPTURE_CFG_TMR6_3 \ -{ \ - .name = IC3_NAME, \ - .ch = TMR6_CH_B, \ - .clk_div = TMR6_CLK_DIV16, \ - .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ - .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ - .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ - .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ - .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ -} +#define INPUT_CAPTURE_CFG_TMR6_3 \ + { \ + .name = IC3_NAME, \ + .ch = TMR6_CH_B, \ + .clk_div = TMR6_CLK_DIV16, \ + .first_edge = TMR6_CAPT_COND_TRIGC_FALLING, \ + .irq_num_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_NUM, \ + .irq_prio_cap = BSP_INPUT_CAPTURE_TMR6_3_CAP_IRQ_PRIO, \ + .irq_num_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_NUM, \ + .irq_prio_ovf = BSP_INPUT_CAPTURE_TMR6_3_OVF_IRQ_PRIO, \ + } #endif #ifdef __cplusplus diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/uart_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/uart_config.h index 52c27bb53a4..0eceb4c52ae 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/uart_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/uart_config.h @@ -21,110 +21,102 @@ extern "C" { #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = CM_USART1, \ - .clock = FCG3_PERIPH_USART1, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_RX_IRQ_NUM, \ - .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_TX_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TI, \ - }, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ } #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .clock = UART1_RX_DMA_CLOCK, \ - .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_RI, \ - .flag = UART1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_RX_DMA_IRQn, \ - .irq_prio = UART1_RX_DMA_INT_PRIO, \ - .int_src = UART1_RX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_RX_CONFIG */ #ifndef UART1_RXTO_CONFIG -#define UART1_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_RTO, \ - }, \ +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ } #endif /* UART1_RXTO_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #endif /* UART1_TX_CPLT_CONFIG */ #if defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .clock = UART1_TX_DMA_CLOCK, \ - .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_TI, \ - .flag = UART1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_TX_DMA_IRQn, \ - .irq_prio = UART1_TX_DMA_INT_PRIO, \ - .int_src = UART1_TX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -132,110 +124,102 @@ extern "C" { #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = CM_USART2, \ - .clock = FCG3_PERIPH_USART2, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_RX_IRQ_NUM, \ - .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_TX_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TI, \ - }, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ } #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .clock = UART2_RX_DMA_CLOCK, \ - .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_RI, \ - .flag = UART2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_RX_DMA_IRQn, \ - .irq_prio = UART2_RX_DMA_INT_PRIO, \ - .int_src = UART2_RX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_RX_CONFIG */ #ifndef UART2_RXTO_CONFIG -#define UART2_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_RTO, \ - }, \ +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ } #endif /* UART2_RXTO_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #endif /* UART2_TX_CPLT_CONFIG */ #if defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .clock = UART2_TX_DMA_CLOCK, \ - .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_TI, \ - .flag = UART2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_TX_DMA_IRQn, \ - .irq_prio = UART2_TX_DMA_INT_PRIO, \ - .int_src = UART2_TX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -243,110 +227,102 @@ extern "C" { #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = CM_USART3, \ - .clock = FCG3_PERIPH_USART3, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_RX_IRQ_NUM, \ - .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_TX_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TI, \ - }, \ +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ } #endif /* UART3_CONFIG */ #if defined(BSP_UART3_RX_USING_DMA) #ifndef UART3_DMA_RX_CONFIG -#define UART3_DMA_RX_CONFIG \ - { \ - .Instance = UART3_RX_DMA_INSTANCE, \ - .channel = UART3_RX_DMA_CHANNEL, \ - .clock = UART3_RX_DMA_CLOCK, \ - .trigger_select = UART3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART3_RI, \ - .flag = UART3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART3_RX_DMA_IRQn, \ - .irq_prio = UART3_RX_DMA_INT_PRIO, \ - .int_src = UART3_RX_DMA_INT_SRC, \ - }, \ +#define UART3_DMA_RX_CONFIG \ + { \ + .Instance = UART3_RX_DMA_INSTANCE, \ + .channel = UART3_RX_DMA_CHANNEL, \ + .clock = UART3_RX_DMA_CLOCK, \ + .trigger_select = UART3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART3_RI, \ + .flag = UART3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART3_RX_DMA_IRQn, \ + .irq_prio = UART3_RX_DMA_INT_PRIO, \ + .int_src = UART3_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART3_DMA_RX_CONFIG */ #ifndef UART3_RXTO_CONFIG -#define UART3_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_3, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_3, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART3_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_RTO, \ - }, \ +#define UART3_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_3, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_3, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART3_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RTO, \ + }, \ } #endif /* UART3_RXTO_CONFIG */ #endif /* BSP_UART3_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART3_TX_USING_DMA) #ifndef UART3_TX_CPLT_CONFIG -#define UART3_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TCI, \ - }, \ +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART3_TX_CPLT_CONFIG -#define UART3_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TCI, \ - }, \ +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ } #endif #endif /* UART3_TX_CPLT_CONFIG */ #if defined(BSP_UART3_TX_USING_DMA) #ifndef UART3_DMA_TX_CONFIG -#define UART3_DMA_TX_CONFIG \ - { \ - .Instance = UART3_TX_DMA_INSTANCE, \ - .channel = UART3_TX_DMA_CHANNEL, \ - .clock = UART3_TX_DMA_CLOCK, \ - .trigger_select = UART3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART3_TI, \ - .flag = UART3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART3_TX_DMA_IRQn, \ - .irq_prio = UART3_TX_DMA_INT_PRIO, \ - .int_src = UART3_TX_DMA_INT_SRC, \ - }, \ +#define UART3_DMA_TX_CONFIG \ + { \ + .Instance = UART3_TX_DMA_INSTANCE, \ + .channel = UART3_TX_DMA_CHANNEL, \ + .clock = UART3_TX_DMA_CLOCK, \ + .trigger_select = UART3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART3_TI, \ + .flag = UART3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART3_TX_DMA_IRQn, \ + .irq_prio = UART3_TX_DMA_INT_PRIO, \ + .int_src = UART3_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART3_DMA_TX_CONFIG */ #endif /* BSP_UART3_TX_USING_DMA */ @@ -354,110 +330,102 @@ extern "C" { #if defined(BSP_USING_UART4) #ifndef UART4_CONFIG -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = CM_USART4, \ - .clock = FCG3_PERIPH_USART4, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_RX_IRQ_NUM, \ - .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_TX_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TI, \ - }, \ +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ } #endif /* UART4_CONFIG */ #if defined(BSP_UART4_RX_USING_DMA) #ifndef UART4_DMA_RX_CONFIG -#define UART4_DMA_RX_CONFIG \ - { \ - .Instance = UART4_RX_DMA_INSTANCE, \ - .channel = UART4_RX_DMA_CHANNEL, \ - .clock = UART4_RX_DMA_CLOCK, \ - .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART4_RI, \ - .flag = UART4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART4_RX_DMA_IRQn, \ - .irq_prio = UART4_RX_DMA_INT_PRIO, \ - .int_src = UART4_RX_DMA_INT_SRC, \ - }, \ +#define UART4_DMA_RX_CONFIG \ + { \ + .Instance = UART4_RX_DMA_INSTANCE, \ + .channel = UART4_RX_DMA_CHANNEL, \ + .clock = UART4_RX_DMA_CLOCK, \ + .trigger_select = UART4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_RI, \ + .flag = UART4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART4_RX_DMA_IRQn, \ + .irq_prio = UART4_RX_DMA_INT_PRIO, \ + .int_src = UART4_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART4_DMA_RX_CONFIG */ #ifndef UART4_RXTO_CONFIG -#define UART4_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_3, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_3, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART4_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_RTO, \ - }, \ +#define UART4_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_3, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_3, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART4_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RTO, \ + }, \ } #endif /* UART4_RXTO_CONFIG */ #endif /* BSP_UART4_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART4_TX_USING_DMA) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #endif /* UART4_TX_CPLT_CONFIG */ #if defined(BSP_UART4_TX_USING_DMA) #ifndef UART4_DMA_TX_CONFIG -#define UART4_DMA_TX_CONFIG \ - { \ - .Instance = UART4_TX_DMA_INSTANCE, \ - .channel = UART4_TX_DMA_CHANNEL, \ - .clock = UART4_TX_DMA_CLOCK, \ - .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART4_TI, \ - .flag = UART4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART4_TX_DMA_IRQn, \ - .irq_prio = UART4_TX_DMA_INT_PRIO, \ - .int_src = UART4_TX_DMA_INT_SRC, \ - }, \ +#define UART4_DMA_TX_CONFIG \ + { \ + .Instance = UART4_TX_DMA_INSTANCE, \ + .channel = UART4_TX_DMA_CHANNEL, \ + .clock = UART4_TX_DMA_CLOCK, \ + .trigger_select = UART4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART4_TI, \ + .flag = UART4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART4_TX_DMA_IRQn, \ + .irq_prio = UART4_TX_DMA_INT_PRIO, \ + .int_src = UART4_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART4_DMA_TX_CONFIG */ #endif /* BSP_UART4_TX_USING_DMA */ @@ -465,110 +433,102 @@ extern "C" { #if defined(BSP_USING_UART5) #ifndef UART5_CONFIG -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = CM_USART5, \ - .clock = FCG3_PERIPH_USART5, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART5_RX_IRQ_NUM, \ - .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART5_TX_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TI, \ - }, \ +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART5_RX_IRQ_NUM, \ + .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART5_TX_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TI, \ + }, \ } #endif /* UART5_CONFIG */ #if defined(BSP_UART5_RX_USING_DMA) #ifndef UART5_DMA_RX_CONFIG -#define UART5_DMA_RX_CONFIG \ - { \ - .Instance = UART5_RX_DMA_INSTANCE, \ - .channel = UART5_RX_DMA_CHANNEL, \ - .clock = UART5_RX_DMA_CLOCK, \ - .trigger_select = UART5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART5_RI, \ - .flag = UART5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART5_RX_DMA_IRQn, \ - .irq_prio = UART5_RX_DMA_INT_PRIO, \ - .int_src = UART5_RX_DMA_INT_SRC, \ - }, \ +#define UART5_DMA_RX_CONFIG \ + { \ + .Instance = UART5_RX_DMA_INSTANCE, \ + .channel = UART5_RX_DMA_CHANNEL, \ + .clock = UART5_RX_DMA_CLOCK, \ + .trigger_select = UART5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART5_RI, \ + .flag = UART5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART5_RX_DMA_IRQn, \ + .irq_prio = UART5_RX_DMA_INT_PRIO, \ + .int_src = UART5_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART5_DMA_RX_CONFIG */ #ifndef UART5_RXTO_CONFIG -#define UART5_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_4, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_4, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART5_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART5_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_RTO, \ - }, \ +#define UART5_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_4, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_4, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART5_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART5_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_RTO, \ + }, \ } #endif /* UART5_RXTO_CONFIG */ #endif /* BSP_UART5_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART5_TX_USING_DMA) #ifndef UART5_TX_CPLT_CONFIG -#define UART5_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TCI, \ - }, \ +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART5_TX_CPLT_CONFIG -#define UART5_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TCI, \ - }, \ +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ } #endif #endif /* UART5_TX_CPLT_CONFIG */ #if defined(BSP_UART5_TX_USING_DMA) #ifndef UART5_DMA_TX_CONFIG -#define UART5_DMA_TX_CONFIG \ - { \ - .Instance = UART5_TX_DMA_INSTANCE, \ - .channel = UART5_TX_DMA_CHANNEL, \ - .clock = UART5_TX_DMA_CLOCK, \ - .trigger_select = UART5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART5_TI, \ - .flag = UART5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART5_TX_DMA_IRQn, \ - .irq_prio = UART5_TX_DMA_INT_PRIO, \ - .int_src = UART5_TX_DMA_INT_SRC, \ - }, \ +#define UART5_DMA_TX_CONFIG \ + { \ + .Instance = UART5_TX_DMA_INSTANCE, \ + .channel = UART5_TX_DMA_CHANNEL, \ + .clock = UART5_TX_DMA_CLOCK, \ + .trigger_select = UART5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART5_TI, \ + .flag = UART5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART5_TX_DMA_IRQn, \ + .irq_prio = UART5_TX_DMA_INT_PRIO, \ + .int_src = UART5_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART5_DMA_TX_CONFIG */ #endif /* BSP_UART5_TX_USING_DMA */ @@ -576,110 +536,102 @@ extern "C" { #if defined(BSP_USING_UART6) #ifndef UART6_CONFIG -#define UART6_CONFIG \ - { \ - .name = "uart6", \ - .Instance = CM_USART6, \ - .clock = FCG3_PERIPH_USART6, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART6_RX_IRQ_NUM, \ - .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART6_TX_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TI, \ - }, \ +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART6_RX_IRQ_NUM, \ + .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART6_TX_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TI, \ + }, \ } #endif /* UART6_CONFIG */ #if defined(BSP_UART6_RX_USING_DMA) #ifndef UART6_DMA_RX_CONFIG -#define UART6_DMA_RX_CONFIG \ - { \ - .Instance = UART6_RX_DMA_INSTANCE, \ - .channel = UART6_RX_DMA_CHANNEL, \ - .clock = UART6_RX_DMA_CLOCK, \ - .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART6_RI, \ - .flag = UART6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART6_RX_DMA_IRQn, \ - .irq_prio = UART6_RX_DMA_INT_PRIO, \ - .int_src = UART6_RX_DMA_INT_SRC, \ - }, \ +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .channel = UART6_RX_DMA_CHANNEL, \ + .clock = UART6_RX_DMA_CLOCK, \ + .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_RI, \ + .flag = UART6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART6_RX_DMA_IRQn, \ + .irq_prio = UART6_RX_DMA_INT_PRIO, \ + .int_src = UART6_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART6_DMA_RX_CONFIG */ #ifndef UART6_RXTO_CONFIG -#define UART6_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_RTO, \ - }, \ +#define UART6_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RTO, \ + }, \ } #endif /* UART6_RXTO_CONFIG */ #endif /* BSP_UART6_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) #ifndef UART6_TX_CPLT_CONFIG -#define UART6_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TCI, \ - }, \ +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART6_TX_CPLT_CONFIG -#define UART6_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TCI, \ - }, \ +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ } #endif #endif /* UART6_TX_CPLT_CONFIG */ #if defined(BSP_UART6_TX_USING_DMA) #ifndef UART6_DMA_TX_CONFIG -#define UART6_DMA_TX_CONFIG \ - { \ - .Instance = UART6_TX_DMA_INSTANCE, \ - .channel = UART6_TX_DMA_CHANNEL, \ - .clock = UART6_TX_DMA_CLOCK, \ - .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART6_TI, \ - .flag = UART6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART6_TX_DMA_IRQn, \ - .irq_prio = UART6_TX_DMA_INT_PRIO, \ - .int_src = UART6_TX_DMA_INT_SRC, \ - }, \ +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .channel = UART6_TX_DMA_CHANNEL, \ + .clock = UART6_TX_DMA_CLOCK, \ + .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_TI, \ + .flag = UART6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART6_TX_DMA_IRQn, \ + .irq_prio = UART6_TX_DMA_INT_PRIO, \ + .int_src = UART6_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART6_DMA_TX_CONFIG */ #endif /* BSP_UART6_TX_USING_DMA */ @@ -687,110 +639,102 @@ extern "C" { #if defined(BSP_USING_UART7) #ifndef UART7_CONFIG -#define UART7_CONFIG \ - { \ - .name = "uart7", \ - .Instance = CM_USART7, \ - .clock = FCG3_PERIPH_USART7, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART7_RX_IRQ_NUM, \ - .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART7_TX_IRQ_NUM, \ - .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_TI, \ - }, \ +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = CM_USART7, \ + .clock = FCG3_PERIPH_USART7, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART7_RX_IRQ_NUM, \ + .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART7_TX_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TI, \ + }, \ } #endif /* UART7_CONFIG */ #if defined(BSP_UART7_RX_USING_DMA) #ifndef UART7_DMA_RX_CONFIG -#define UART7_DMA_RX_CONFIG \ - { \ - .Instance = UART7_RX_DMA_INSTANCE, \ - .channel = UART7_RX_DMA_CHANNEL, \ - .clock = UART7_RX_DMA_CLOCK, \ - .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART7_RI, \ - .flag = UART7_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART7_RX_DMA_IRQn, \ - .irq_prio = UART7_RX_DMA_INT_PRIO, \ - .int_src = UART7_RX_DMA_INT_SRC, \ - }, \ +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .channel = UART7_RX_DMA_CHANNEL, \ + .clock = UART7_RX_DMA_CLOCK, \ + .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_RI, \ + .flag = UART7_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART7_RX_DMA_IRQn, \ + .irq_prio = UART7_RX_DMA_INT_PRIO, \ + .int_src = UART7_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART7_DMA_RX_CONFIG */ #ifndef UART7_RXTO_CONFIG -#define UART7_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_RTO, \ - }, \ +#define UART7_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RTO, \ + }, \ } #endif /* UART7_RXTO_CONFIG */ #endif /* BSP_UART7_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) #ifndef UART7_TX_CPLT_CONFIG -#define UART7_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_TCI, \ - }, \ +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART7_TX_CPLT_CONFIG -#define UART7_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_TCI, \ - }, \ +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ } #endif #endif /* UART7_TX_CPLT_CONFIG */ #if defined(BSP_UART7_TX_USING_DMA) #ifndef UART7_DMA_TX_CONFIG -#define UART7_DMA_TX_CONFIG \ - { \ - .Instance = UART7_TX_DMA_INSTANCE, \ - .channel = UART7_TX_DMA_CHANNEL, \ - .clock = UART7_TX_DMA_CLOCK, \ - .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART7_TI, \ - .flag = UART7_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART7_TX_DMA_IRQn, \ - .irq_prio = UART7_TX_DMA_INT_PRIO, \ - .int_src = UART7_TX_DMA_INT_SRC, \ - }, \ +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .channel = UART7_TX_DMA_CHANNEL, \ + .clock = UART7_TX_DMA_CLOCK, \ + .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_TI, \ + .flag = UART7_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART7_TX_DMA_IRQn, \ + .irq_prio = UART7_TX_DMA_INT_PRIO, \ + .int_src = UART7_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART7_DMA_TX_CONFIG */ #endif /* BSP_UART7_TX_USING_DMA */ @@ -798,110 +742,102 @@ extern "C" { #if defined(BSP_USING_UART8) #ifndef UART8_CONFIG -#define UART8_CONFIG \ - { \ - .name = "uart8", \ - .Instance = CM_USART8, \ - .clock = FCG3_PERIPH_USART8, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART8_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART8_RX_IRQ_NUM, \ - .irq_prio = BSP_UART8_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART8_TX_IRQ_NUM, \ - .irq_prio = BSP_UART8_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_TI, \ - }, \ +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .Instance = CM_USART8, \ + .clock = FCG3_PERIPH_USART8, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART8_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART8_RX_IRQ_NUM, \ + .irq_prio = BSP_UART8_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART8_TX_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TI, \ + }, \ } #endif /* UART8_CONFIG */ #if defined(BSP_UART8_RX_USING_DMA) #ifndef UART8_DMA_RX_CONFIG -#define UART8_DMA_RX_CONFIG \ - { \ - .Instance = UART8_RX_DMA_INSTANCE, \ - .channel = UART8_RX_DMA_CHANNEL, \ - .clock = UART8_RX_DMA_CLOCK, \ - .trigger_select = UART8_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART8_RI, \ - .flag = UART8_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART8_RX_DMA_IRQn, \ - .irq_prio = UART8_RX_DMA_INT_PRIO, \ - .int_src = UART8_RX_DMA_INT_SRC, \ - }, \ +#define UART8_DMA_RX_CONFIG \ + { \ + .Instance = UART8_RX_DMA_INSTANCE, \ + .channel = UART8_RX_DMA_CHANNEL, \ + .clock = UART8_RX_DMA_CLOCK, \ + .trigger_select = UART8_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART8_RI, \ + .flag = UART8_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART8_RX_DMA_IRQn, \ + .irq_prio = UART8_RX_DMA_INT_PRIO, \ + .int_src = UART8_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART8_DMA_RX_CONFIG */ #ifndef UART8_RXTO_CONFIG -#define UART8_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_4, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_4, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART8_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART8_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_RTO, \ - }, \ +#define UART8_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_4, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_4, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART8_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART8_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_RTO, \ + }, \ } #endif /* UART8_RXTO_CONFIG */ #endif /* BSP_UART8_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART8_TX_USING_DMA) #ifndef UART8_TX_CPLT_CONFIG -#define UART8_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_TCI, \ - }, \ +#define UART8_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART8_TX_CPLT_CONFIG -#define UART8_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_TCI, \ - }, \ +#define UART8_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TCI, \ + }, \ } #endif #endif /* UART8_TX_CPLT_CONFIG */ #if defined(BSP_UART8_TX_USING_DMA) #ifndef UART8_DMA_TX_CONFIG -#define UART8_DMA_TX_CONFIG \ - { \ - .Instance = UART8_TX_DMA_INSTANCE, \ - .channel = UART8_TX_DMA_CHANNEL, \ - .clock = UART8_TX_DMA_CLOCK, \ - .trigger_select = UART8_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART8_TI, \ - .flag = UART8_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART8_TX_DMA_IRQn, \ - .irq_prio = UART8_TX_DMA_INT_PRIO, \ - .int_src = UART8_TX_DMA_INT_SRC, \ - }, \ +#define UART8_DMA_TX_CONFIG \ + { \ + .Instance = UART8_TX_DMA_INSTANCE, \ + .channel = UART8_TX_DMA_CHANNEL, \ + .clock = UART8_TX_DMA_CLOCK, \ + .trigger_select = UART8_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART8_TI, \ + .flag = UART8_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART8_TX_DMA_IRQn, \ + .irq_prio = UART8_TX_DMA_INT_PRIO, \ + .int_src = UART8_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART8_DMA_TX_CONFIG */ #endif /* BSP_UART8_TX_USING_DMA */ @@ -909,110 +845,102 @@ extern "C" { #if defined(BSP_USING_UART9) #ifndef UART9_CONFIG -#define UART9_CONFIG \ - { \ - .name = "uart9", \ - .Instance = CM_USART9, \ - .clock = FCG3_PERIPH_USART9, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART9_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART9_RX_IRQ_NUM, \ - .irq_prio = BSP_UART9_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART9_TX_IRQ_NUM, \ - .irq_prio = BSP_UART9_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_TI, \ - }, \ +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .Instance = CM_USART9, \ + .clock = FCG3_PERIPH_USART9, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART9_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART9_RX_IRQ_NUM, \ + .irq_prio = BSP_UART9_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART9_TX_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TI, \ + }, \ } #endif /* UART9_CONFIG */ #if defined(BSP_UART9_RX_USING_DMA) #ifndef UART9_DMA_RX_CONFIG -#define UART9_DMA_RX_CONFIG \ - { \ - .Instance = UART9_RX_DMA_INSTANCE, \ - .channel = UART9_RX_DMA_CHANNEL, \ - .clock = UART9_RX_DMA_CLOCK, \ - .trigger_select = UART9_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART9_RI, \ - .flag = UART9_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART9_RX_DMA_IRQn, \ - .irq_prio = UART9_RX_DMA_INT_PRIO, \ - .int_src = UART9_RX_DMA_INT_SRC, \ - }, \ +#define UART9_DMA_RX_CONFIG \ + { \ + .Instance = UART9_RX_DMA_INSTANCE, \ + .channel = UART9_RX_DMA_CHANNEL, \ + .clock = UART9_RX_DMA_CLOCK, \ + .trigger_select = UART9_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART9_RI, \ + .flag = UART9_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART9_RX_DMA_IRQn, \ + .irq_prio = UART9_RX_DMA_INT_PRIO, \ + .int_src = UART9_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART9_DMA_RX_CONFIG */ #ifndef UART9_RXTO_CONFIG -#define UART9_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_5, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_5, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART9_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART9_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_RTO, \ - }, \ +#define UART9_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_5, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_5, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART9_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART9_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_RTO, \ + }, \ } #endif /* UART9_RXTO_CONFIG */ #endif /* BSP_UART9_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART9_TX_USING_DMA) #ifndef UART9_TX_CPLT_CONFIG -#define UART9_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_TCI, \ - }, \ +#define UART9_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART9_TX_CPLT_CONFIG -#define UART9_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_TCI, \ - }, \ +#define UART9_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TCI, \ + }, \ } #endif #endif /* UART9_TX_CPLT_CONFIG */ #if defined(BSP_UART9_TX_USING_DMA) #ifndef UART9_DMA_TX_CONFIG -#define UART9_DMA_TX_CONFIG \ - { \ - .Instance = UART9_TX_DMA_INSTANCE, \ - .channel = UART9_TX_DMA_CHANNEL, \ - .clock = UART9_TX_DMA_CLOCK, \ - .trigger_select = UART9_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART9_TI, \ - .flag = UART9_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART9_TX_DMA_IRQn, \ - .irq_prio = UART9_TX_DMA_INT_PRIO, \ - .int_src = UART9_TX_DMA_INT_SRC, \ - }, \ +#define UART9_DMA_TX_CONFIG \ + { \ + .Instance = UART9_TX_DMA_INSTANCE, \ + .channel = UART9_TX_DMA_CHANNEL, \ + .clock = UART9_TX_DMA_CLOCK, \ + .trigger_select = UART9_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART9_TI, \ + .flag = UART9_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART9_TX_DMA_IRQn, \ + .irq_prio = UART9_TX_DMA_INT_PRIO, \ + .int_src = UART9_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART9_DMA_TX_CONFIG */ #endif /* BSP_UART9_TX_USING_DMA */ @@ -1020,110 +948,102 @@ extern "C" { #if defined(BSP_USING_UART10) #ifndef UART10_CONFIG -#define UART10_CONFIG \ - { \ - .name = "uart10", \ - .Instance = CM_USART10, \ - .clock = FCG3_PERIPH_USART10, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART10_RX_IRQ_NUM, \ - .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART10_TX_IRQ_NUM, \ - .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_TI, \ - }, \ +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = CM_USART10, \ + .clock = FCG3_PERIPH_USART10, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART10_RX_IRQ_NUM, \ + .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART10_TX_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TI, \ + }, \ } #endif /* UART10_CONFIG */ #if defined(BSP_UART10_RX_USING_DMA) #ifndef UART10_DMA_RX_CONFIG -#define UART10_DMA_RX_CONFIG \ - { \ - .Instance = UART10_RX_DMA_INSTANCE, \ - .channel = UART10_RX_DMA_CHANNEL, \ - .clock = UART10_RX_DMA_CLOCK, \ - .trigger_select = UART10_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART10_RI, \ - .flag = UART10_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART10_RX_DMA_IRQn, \ - .irq_prio = UART10_RX_DMA_INT_PRIO, \ - .int_src = UART10_RX_DMA_INT_SRC, \ - }, \ +#define UART10_DMA_RX_CONFIG \ + { \ + .Instance = UART10_RX_DMA_INSTANCE, \ + .channel = UART10_RX_DMA_CHANNEL, \ + .clock = UART10_RX_DMA_CLOCK, \ + .trigger_select = UART10_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART10_RI, \ + .flag = UART10_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART10_RX_DMA_IRQn, \ + .irq_prio = UART10_RX_DMA_INT_PRIO, \ + .int_src = UART10_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART10_DMA_RX_CONFIG */ #ifndef UART10_RXTO_CONFIG -#define UART10_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_5, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_5, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART10_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART10_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_RTO, \ - }, \ +#define UART10_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_5, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_5, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART10_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART10_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_RTO, \ + }, \ } #endif /* UART10_RXTO_CONFIG */ #endif /* BSP_UART10_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART10_TX_USING_DMA) #ifndef UART10_TX_CPLT_CONFIG -#define UART10_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_TCI, \ - }, \ +#define UART10_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART10_TX_CPLT_CONFIG -#define UART10_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_TCI, \ - }, \ +#define UART10_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TCI, \ + }, \ } #endif #endif /* UART10_TX_CPLT_CONFIG */ #if defined(BSP_UART10_TX_USING_DMA) #ifndef UART10_DMA_TX_CONFIG -#define UART10_DMA_TX_CONFIG \ - { \ - .Instance = UART10_TX_DMA_INSTANCE, \ - .channel = UART10_TX_DMA_CHANNEL, \ - .clock = UART10_TX_DMA_CLOCK, \ - .trigger_select = UART10_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART10_TI, \ - .flag = UART10_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART10_TX_DMA_IRQn, \ - .irq_prio = UART10_TX_DMA_INT_PRIO, \ - .int_src = UART10_TX_DMA_INT_SRC, \ - }, \ +#define UART10_DMA_TX_CONFIG \ + { \ + .Instance = UART10_TX_DMA_INSTANCE, \ + .channel = UART10_TX_DMA_CHANNEL, \ + .clock = UART10_TX_DMA_CLOCK, \ + .trigger_select = UART10_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART10_TI, \ + .flag = UART10_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART10_TX_DMA_IRQn, \ + .irq_prio = UART10_TX_DMA_INT_PRIO, \ + .int_src = UART10_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART10_DMA_TX_CONFIG */ #endif /* BSP_UART10_TX_USING_DMA */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/usb_config/usb_app_conf.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/usb_config/usb_app_conf.h index 2781afa72f4..53c20e1b517 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/usb_config/usb_app_conf.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/usb_config/usb_app_conf.h @@ -13,8 +13,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -61,71 +60,71 @@ USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment #ifndef USB_HS_MODE #ifndef USB_FS_MODE -#error "USB_HS_MODE or USB_FS_MODE should be defined" +#error "USB_HS_MODE or USB_FS_MODE should be defined" #endif #endif #ifndef USE_DEVICE_MODE #ifndef USE_HOST_MODE -#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" +#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" #endif #endif #if defined(BSP_USING_USBD) /* USB DEVICE FIFO CONFIGURATION */ #ifdef USB_FS_MODE -#define RX_FIFO_FS_SIZE (128U) -#define TX0_FIFO_FS_SIZE (32U) -#define TX1_FIFO_FS_SIZE (32U) -#define TX2_FIFO_FS_SIZE (32U) -#define TX3_FIFO_FS_SIZE (32U) -#define TX4_FIFO_FS_SIZE (32U) -#define TX5_FIFO_FS_SIZE (32U) -#define TX6_FIFO_FS_SIZE (32U) -#define TX7_FIFO_FS_SIZE (32U) -#define TX8_FIFO_FS_SIZE (32U) -#define TX9_FIFO_FS_SIZE (32U) -#define TX10_FIFO_FS_SIZE (32U) -#define TX11_FIFO_FS_SIZE (32U) -#define TX12_FIFO_FS_SIZE (32U) -#define TX13_FIFO_FS_SIZE (32U) -#define TX14_FIFO_FS_SIZE (32U) -#define TX15_FIFO_FS_SIZE (32U) - -#if ((RX_FIFO_FS_SIZE + \ - TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ - TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ +#define RX_FIFO_FS_SIZE (128U) +#define TX0_FIFO_FS_SIZE (32U) +#define TX1_FIFO_FS_SIZE (32U) +#define TX2_FIFO_FS_SIZE (32U) +#define TX3_FIFO_FS_SIZE (32U) +#define TX4_FIFO_FS_SIZE (32U) +#define TX5_FIFO_FS_SIZE (32U) +#define TX6_FIFO_FS_SIZE (32U) +#define TX7_FIFO_FS_SIZE (32U) +#define TX8_FIFO_FS_SIZE (32U) +#define TX9_FIFO_FS_SIZE (32U) +#define TX10_FIFO_FS_SIZE (32U) +#define TX11_FIFO_FS_SIZE (32U) +#define TX12_FIFO_FS_SIZE (32U) +#define TX13_FIFO_FS_SIZE (32U) +#define TX14_FIFO_FS_SIZE (32U) +#define TX15_FIFO_FS_SIZE (32U) + +#if ((RX_FIFO_FS_SIZE + \ + TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ + TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \ TX15_FIFO_FS_SIZE) > 640U) -#error "The USB max FIFO size is 640 x 4 Bytes!" +#error "The USB max FIFO size is 640 x 4 Bytes!" #endif #endif #ifdef USB_HS_MODE -#define RX_FIFO_HS_SIZE (512U) -#define TX0_FIFO_HS_SIZE (64U) -#define TX1_FIFO_HS_SIZE (64U) -#define TX2_FIFO_HS_SIZE (64U) -#define TX3_FIFO_HS_SIZE (64U) -#define TX4_FIFO_HS_SIZE (64U) -#define TX5_FIFO_HS_SIZE (64U) -#define TX6_FIFO_HS_SIZE (64U) -#define TX7_FIFO_HS_SIZE (64U) -#define TX8_FIFO_HS_SIZE (64U) -#define TX9_FIFO_HS_SIZE (64U) -#define TX10_FIFO_HS_SIZE (64U) -#define TX11_FIFO_HS_SIZE (64U) -#define TX12_FIFO_HS_SIZE (64U) -#define TX13_FIFO_HS_SIZE (64U) -#define TX14_FIFO_HS_SIZE (64U) -#define TX15_FIFO_HS_SIZE (64U) - -#if ((RX_FIFO_HS_SIZE + \ - TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ - TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ +#define RX_FIFO_HS_SIZE (512U) +#define TX0_FIFO_HS_SIZE (64U) +#define TX1_FIFO_HS_SIZE (64U) +#define TX2_FIFO_HS_SIZE (64U) +#define TX3_FIFO_HS_SIZE (64U) +#define TX4_FIFO_HS_SIZE (64U) +#define TX5_FIFO_HS_SIZE (64U) +#define TX6_FIFO_HS_SIZE (64U) +#define TX7_FIFO_HS_SIZE (64U) +#define TX8_FIFO_HS_SIZE (64U) +#define TX9_FIFO_HS_SIZE (64U) +#define TX10_FIFO_HS_SIZE (64U) +#define TX11_FIFO_HS_SIZE (64U) +#define TX12_FIFO_HS_SIZE (64U) +#define TX13_FIFO_HS_SIZE (64U) +#define TX14_FIFO_HS_SIZE (64U) +#define TX15_FIFO_HS_SIZE (64U) + +#if ((RX_FIFO_HS_SIZE + \ + TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ + TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \ TX15_FIFO_HS_SIZE) > 2048U) -#error "The USB max FIFO size is 2048 x 4 Bytes!" +#error "The USB max FIFO size is 2048 x 4 Bytes!" #endif #endif @@ -137,22 +136,22 @@ USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment #if defined(BSP_USING_USBH) /* USB HOST FIFO CONFIGURATION */ #ifdef USB_FS_MODE -#define RX_FIFO_FS_SIZE (128U) -#define TXH_NP_FS_FIFOSIZ (32U) -#define TXH_P_FS_FIFOSIZ (64U) +#define RX_FIFO_FS_SIZE (128U) +#define TXH_NP_FS_FIFOSIZ (32U) +#define TXH_P_FS_FIFOSIZ (64U) #if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U) -#error "The USB max FIFO size is 640 x 4 Bytes!" +#error "The USB max FIFO size is 640 x 4 Bytes!" #endif #endif #ifdef USB_HS_MODE -#define RX_FIFO_HS_SIZE (512U) -#define TXH_NP_HS_FIFOSIZ (128U) -#define TXH_P_HS_FIFOSIZ (256U) +#define RX_FIFO_HS_SIZE (512U) +#define TXH_NP_HS_FIFOSIZ (128U) +#define TXH_P_HS_FIFOSIZ (256U) #if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U) -#error "The USB max FIFO size is 2048 x 4 Bytes!" +#error "The USB max FIFO size is 2048 x 4 Bytes!" #endif #endif #endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/usb_config/usb_bsp.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/usb_config/usb_bsp.h index 76b5b37d81c..0df0dfbeda3 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/usb_config/usb_bsp.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/config/usb_config/usb_bsp.h @@ -13,8 +13,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include "hc32_ll_utility.h" diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/hc32f4xx_conf.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/hc32f4xx_conf.h index 7227ae289f0..1c88c721bfc 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/hc32f4xx_conf.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/hc32f4xx_conf.h @@ -27,8 +27,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -48,67 +47,67 @@ extern "C" * Library. * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. */ -#define LL_ICG_ENABLE (DDL_ON) -#define LL_UTILITY_ENABLE (DDL_ON) -#define LL_PRINT_ENABLE (DDL_OFF) - -#define LL_ADC_ENABLE (DDL_ON) -#define LL_AOS_ENABLE (DDL_ON) -#define LL_CAN_ENABLE (DDL_ON) -#define LL_CLK_ENABLE (DDL_ON) -#define LL_CMP_ENABLE (DDL_ON) -#define LL_CRC_ENABLE (DDL_ON) -#define LL_CTC_ENABLE (DDL_ON) -#define LL_DAC_ENABLE (DDL_ON) -#define LL_DBGC_ENABLE (DDL_OFF) -#define LL_DCU_ENABLE (DDL_ON) -#define LL_DMA_ENABLE (DDL_ON) -#define LL_DMC_ENABLE (DDL_ON) -#define LL_DVP_ENABLE (DDL_ON) -#define LL_EFM_ENABLE (DDL_ON) -#define LL_EMB_ENABLE (DDL_ON) -#define LL_ERMU_ENABLE (DDL_ON) -#define LL_ETH_ENABLE (DDL_ON) -#define LL_EVENT_PORT_ENABLE (DDL_OFF) -#define LL_FCG_ENABLE (DDL_ON) -#define LL_FCM_ENABLE (DDL_ON) -#define LL_FMAC_ENABLE (DDL_ON) -#define LL_GPIO_ENABLE (DDL_ON) -#define LL_HASH_ENABLE (DDL_ON) -#define LL_I2C_ENABLE (DDL_ON) -#define LL_I2S_ENABLE (DDL_ON) -#define LL_INTERRUPTS_ENABLE (DDL_ON) -#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) -#define LL_KEYSCAN_ENABLE (DDL_ON) -#define LL_MAU_ENABLE (DDL_ON) -#define LL_MCAN_ENABLE (DDL_ON) -#define LL_MPU_ENABLE (DDL_ON) -#define LL_NFC_ENABLE (DDL_ON) -#define LL_OTS_ENABLE (DDL_ON) -#define LL_PWC_ENABLE (DDL_ON) -#define LL_QSPI_ENABLE (DDL_ON) -#define LL_RMU_ENABLE (DDL_ON) -#define LL_RTC_ENABLE (DDL_ON) -#define LL_SDIOC_ENABLE (DDL_ON) -#define LL_SKE_ENABLE (DDL_ON) -#define LL_SMC_ENABLE (DDL_ON) -#define LL_SPI_ENABLE (DDL_ON) -#define LL_SRAM_ENABLE (DDL_ON) -#define LL_SWDT_ENABLE (DDL_ON) -#define LL_TMR0_ENABLE (DDL_ON) -#define LL_TMR2_ENABLE (DDL_ON) -#define LL_TMR4_ENABLE (DDL_ON) -#define LL_TMR6_ENABLE (DDL_ON) -#define LL_TMRA_ENABLE (DDL_ON) -#define LL_TRNG_ENABLE (DDL_ON) -#define LL_USART_ENABLE (DDL_ON) -#define LL_USB_ENABLE (DDL_ON) -#define LL_WDT_ENABLE (DDL_ON) +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_DMC_ENABLE (DDL_ON) +#define LL_DVP_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_ERMU_ENABLE (DDL_ON) +#define LL_ETH_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MCAN_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_NFC_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SKE_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR2_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) /** * @brief The following is a list of currently supported BSP boards. */ -#define BSP_EV_HC32F4A8_LQFP176 (11U) +#define BSP_EV_HC32F4A8_LQFP176 (11U) /** * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently @@ -117,43 +116,43 @@ extern "C" * @note If there is no supported BSP board or the BSP function is not used, * the value needs to be set to 0U. */ -#define BSP_EV_HC32F4XX (0U) +#define BSP_EV_HC32F4XX (0U) /** * @brief This is the list of BSP components to be used. * Select the components you need to use to DDL_ON. */ -#define BSP_24CXX_ENABLE (DDL_OFF) -#define BSP_XPT20XX_ENABLE (DDL_OFF) -#define BSP_W9825G6KH_ENABLE (DDL_OFF) -#define BSP_IS62WV51216_ENABLE (DDL_OFF) -#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) -#define BSP_NT35510_ENABLE (DDL_OFF) -#define BSP_OV5640_ENABLE (DDL_OFF) -#define BSP_RTL8201_ENABLE (DDL_OFF) -#define BSP_TCA9539_ENABLE (DDL_OFF) -#define BSP_W25QXX_ENABLE (DDL_OFF) -#define BSP_WM8988_ENABLE (DDL_OFF) +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_XPT20XX_ENABLE (DDL_OFF) +#define BSP_W9825G6KH_ENABLE (DDL_OFF) +#define BSP_IS62WV51216_ENABLE (DDL_OFF) +#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_OV5640_ENABLE (DDL_OFF) +#define BSP_RTL8201_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_WM8988_ENABLE (DDL_OFF) /** * @brief Ethernet and PHY Configuration. */ /* MAC ADDRESS */ -#define ETH_MAC_ADDR0 (0x02U) -#define ETH_MAC_ADDR1 (0x00U) -#define ETH_MAC_ADDR2 (0x00U) -#define ETH_MAC_ADDR3 (0x00U) -#define ETH_MAC_ADDR4 (0x00U) -#define ETH_MAC_ADDR5 (0x00U) - -#if defined (ETH_PHY_USING_RTL8201F) +#define ETH_MAC_ADDR0 (0x02U) +#define ETH_MAC_ADDR1 (0x00U) +#define ETH_MAC_ADDR2 (0x00U) +#define ETH_MAC_ADDR3 (0x00U) +#define ETH_MAC_ADDR4 (0x00U) +#define ETH_MAC_ADDR5 (0x00U) + +#if defined(ETH_PHY_USING_RTL8201F) /* PHY(RTL8201F) Address*/ -#define ETH_PHY_ADDR (0x01U) +#define ETH_PHY_ADDR (0x01U) /* PHY Status Register */ -#define PHY_SR (0x00U) /*!< PHY status register */ -#define PHY_DUPLEX_STATUS (0x0100U) /*!< PHY Duplex mask */ -#define PHY_SPEED_STATUS (0x2000U) /*!< PHY Speed mask */ +#define PHY_SR (0x00U) /*!< PHY status register */ +#define PHY_DUPLEX_STATUS (0x0100U) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS (0x2000U) /*!< PHY Speed mask */ #endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/fal_cfg.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/fal_cfg.h index 5d8fbbe9e63..9a8de41f9c2 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/fal_cfg.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/fal_cfg.h @@ -23,20 +23,20 @@ extern const struct fal_flash_dev hc32_onchip_flash; extern struct fal_flash_dev ext_nor_flash0; /* flash device table */ -#define FAL_FLASH_DEV_TABLE \ -{ \ - &hc32_onchip_flash, \ - &ext_nor_flash0, \ -} +#define FAL_FLASH_DEV_TABLE \ + { \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ + } /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ -#define FAL_PART_TABLE \ -{ \ - {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0}, \ - {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ -} +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \ + } #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/nand_port.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/nand_port.h index 72c413d13da..f8dc6634e9e 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/nand_port.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/nand_port.h @@ -13,72 +13,75 @@ #define __NAND_PORT_H__ /******************** NAND chip information ***********************************/ -#define NAND_BYTES_PER_PAGE 2048UL -#define NAND_SPARE_AREA_SIZE 64UL -#define NAND_PAGES_PER_BLOCK 64UL -#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) -#define NAND_BLOCKS_PER_PLANE 1024UL -#define NAND_PLANE_PER_DEVICE 2UL -#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) -#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) +#define NAND_BYTES_PER_PAGE 2048UL +#define NAND_SPARE_AREA_SIZE 64UL +#define NAND_PAGES_PER_BLOCK 64UL +#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) +#define NAND_BLOCKS_PER_PLANE 1024UL +#define NAND_PLANE_PER_DEVICE 2UL +#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) +#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) /******************** EXMC_NFC configure **************************************/ /* chip: EXMC_NFC_BANK0~7 */ -#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0 +#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0 /* density:2Gbit */ -#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT +#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT /* device width: 8-bit */ -#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT +#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT + +/* BankNum: 1BANK */ +#define NAND_EXMC_NFC_BANK_NUMBER EXMC_NFC_1BANK /* page size: 2KByte */ -#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE +#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE /* row address cycle: 3 */ -#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE +#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE /* ECC mode */ -#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC +#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC /* timing configuration(EXCLK clock frequency: 60MHz@3.3V) */ /* TS: ALE/CLE/CE setup time(min=10ns) */ -#define NAND_TS 1U +#define NAND_TS 1U /* TWP: WE# pulse width (min=10ns) */ -#define NAND_TWP 1U +#define NAND_TWP 1U /* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */ -#define NAND_TRP 2U +#define NAND_TRP 2U /* TTH: ALE/CLE/CE hold time (min=5ns) */ -#define NAND_TH 1U +#define NAND_TH 1U /* TWH: WE# pulse width HIGH (min=10ns) */ -#define NAND_TWH 1U +#define NAND_TWH 1U /* TRH: RE# pulse width HIGH (min=7ns) */ -#define NAND_TRH 1U +#define NAND_TRH 1U /* TRR: Ready to RE# LOW (min=20ns) */ -#define NAND_TRR 2U +#define NAND_TRR 2U /* TWB: WE# HIGH to busy (max=100ns) */ -#define NAND_TWB 1U +#define NAND_TWB 1U /* TWB: WE# HIGH to busy (max=100ns) */ -#define NAND_TRB 1U +#define NAND_TRB 1U /* TCCS: Change read column and Change write column delay */ -#define NAND_TCCS 5U +#define NAND_TCCS 5U /* TWTR: WE# HIGH to RE# LOW (min=60ns) */ -#define NAND_TWTR 4U +#define NAND_TWTR 4U /* TRTW: RE# HIGH to WE# LOW (min=100ns) */ -#define NAND_TRTW 7U +#define NAND_TRTW 7U /* TADL: ALE to data start (min=70ns) */ -#define NAND_TADL 5U +#define NAND_TADL 5U #endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/sdram_port.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/sdram_port.h index f3c42af3bbd..0ec1e29b1d0 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/sdram_port.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/sdram_port.h @@ -15,73 +15,73 @@ /* parameters for sdram peripheral */ /* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */ -#define SDRAM_CHIP EXMC_DMC_CHIP0 +#define SDRAM_CHIP EXMC_DMC_CHIP0 /* bank address */ -#define SDRAM_BANK_ADDR (0x80000000UL) +#define SDRAM_BANK_ADDR (0x80000000UL) /* size(kbyte):32MB = 32*1024*1KBytes */ -#define SDRAM_SIZE (32UL * 1024UL * 1024UL) +#define SDRAM_SIZE (32UL * 1024UL * 1024UL) /* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */ -#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 +#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 /* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */ -#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT +#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT /* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */ -#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM9 +#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM9 /* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */ -#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM13 +#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM13 /* cas latency clock number: 2, 3 */ -#define SDRAM_CAS_LATENCY 2UL +#define SDRAM_CAS_LATENCY 2UL /* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */ -#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT +#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT /* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */ -#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD +#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD /* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */ -#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL +#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL /* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */ -#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED +#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED /* timing configuration(EXCLK clock frequency: 60MHz) */ /* refresh rate counter (EXCLK clock) */ -#define SDRAM_REFRESH_COUNT (900U) +#define SDRAM_REFRESH_COUNT (900U) /* TMDR: mode register command time (EXCLK clock) */ -#define SDRAM_TMDR 2U +#define SDRAM_TMDR 2U /* TRAS: RAS to precharge delay time (EXCLK clock) */ -#define SDRAM_TRAS 3U +#define SDRAM_TRAS 3U /* TRC: active bank x to active bank x delay time (EXCLK clock) */ -#define SDRAM_TRC 4U +#define SDRAM_TRC 4U /* TRCD: RAS to CAS minimum delay time (EXCLK clock) */ -#define SDRAM_TRCD_B 3U -#define SDRAM_TRCD_P 0U +#define SDRAM_TRCD_B 3U +#define SDRAM_TRCD_P 0U /* TRFC: autorefresh command time (EXCLK clock) */ -#define SDRAM_TRFC_B 4U -#define SDRAM_TRFC_P 0U +#define SDRAM_TRFC_B 4U +#define SDRAM_TRFC_P 0U /* TRP: precharge to RAS delay time (EXCLK clock) */ -#define SDRAM_TRP_B 3U -#define SDRAM_TRP_P 0U +#define SDRAM_TRP_B 3U +#define SDRAM_TRP_P 0U /* TRRD: active bank x to active bank y delay time (EXCLK clock) */ -#define SDRAM_TRRD 2U +#define SDRAM_TRRD 2U /* TWR: write to precharge delay time (EXCLK clock). */ -#define SDRAM_TWR 2U +#define SDRAM_TWR 2U /* TWTR: write to read delay time (EXCLK clock). */ -#define SDRAM_TWTR 1U +#define SDRAM_TWTR 1U /* TXP: exit power-down command time (EXCLK clock). */ -#define SDRAM_TXP 1U +#define SDRAM_TXP 1U /* TXSR: exit self-refresh command time (EXCLK clock). */ -#define SDRAM_TXSR 5U +#define SDRAM_TXSR 5U /* TESR: self-refresh command time (EXCLK clock). */ -#define SDRAM_TESR 5U +#define SDRAM_TESR 5U /* memory mode register */ -#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) -#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) -#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) -#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) -#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) -#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) +#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) +#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) +#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) +#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) +#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) +#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) #endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/tca9539_port.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/tca9539_port.h index b5761c43c9e..968648888f2 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/tca9539_port.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/tca9539_port.h @@ -17,23 +17,23 @@ * @defgroup HC32F4A8_EV_IO_Function_Sel Expand IO function definition * @{ */ -#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ -#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ -#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */ -#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */ -#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */ -#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */ -#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ -#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ +#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ +#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ +#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */ +#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */ +#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */ +#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ -#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */ -#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */ -#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ -#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ -#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ -#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ -#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ -#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */ +#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */ +#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ +#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ +#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ /** * @} */ @@ -42,12 +42,12 @@ * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition * @{ */ -#define LED_RED_PORT (TCA9539_IO_PORT1) -#define LED_RED_PIN (EIO_LED_RED) -#define LED_YELLOW_PORT (TCA9539_IO_PORT1) -#define LED_YELLOW_PIN (EIO_LED_YELLOW) -#define LED_BLUE_PORT (TCA9539_IO_PORT1) -#define LED_BLUE_PIN (EIO_LED_BLUE) +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) /** * @} */ @@ -56,10 +56,10 @@ * @defgroup BSP CAN PHY STB port/pin definition * @{ */ -#define CAN1_STB_PORT (TCA9539_IO_PORT1) -#define CAN1_STB_PIN (TCA9539_IO_PIN4) -#define CAN2_STB_PORT (TCA9539_IO_PORT1) -#define CAN2_STB_PIN (TCA9539_IO_PIN5) +#define CAN1_STB_PORT (TCA9539_IO_PORT1) +#define CAN1_STB_PIN (TCA9539_IO_PIN4) +#define CAN2_STB_PORT (TCA9539_IO_PORT1) +#define CAN2_STB_PIN (TCA9539_IO_PIN5) /** * @} */ @@ -67,8 +67,8 @@ * @defgroup BSP_ETH_PortPin_Sel BSP ETH port/pin definition * @{ */ -#define ETH_RST_PORT (TCA9539_IO_PORT1) -#define ETH_RST_PIN (EIO_ETH_RST) +#define ETH_RST_PORT (TCA9539_IO_PORT1) +#define ETH_RST_PIN (EIO_ETH_RST) /** * @} */ diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/usb_config.h b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/usb_config.h index dd239502be3..3a4dd5aab4a 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/usb_config.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/board/ports/usb_config.h @@ -14,15 +14,15 @@ /* ================ USB common Configuration ================ */ #ifdef __RTTHREAD__ - #include +#include - #define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) +#define CONFIG_USB_PRINTF(...) rt_kprintf(__VA_ARGS__) #else - #define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) +#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__) #endif #ifndef CONFIG_USB_DBG_LEVEL - #define CONFIG_USB_DBG_LEVEL USB_DBG_INFO +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO #endif /* Enable print with color */ @@ -32,9 +32,9 @@ /* data align size when use dma or use dcache */ #ifdef CONFIG_USB_DCACHE_ENABLE - #define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 +#define CONFIG_USB_ALIGN_SIZE 32 // 32 or 64 #else - #define CONFIG_USB_ALIGN_SIZE 4 +#define CONFIG_USB_ALIGN_SIZE 4 #endif /* attribute data into no cache ram */ @@ -49,7 +49,7 @@ /* Ep0 in and out transfer buffer */ #ifndef CONFIG_USBDEV_REQUEST_BUFFER_LEN - #define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 512 #endif /* Send ep0 in data from user buffer instead of copying into ep0 reqdata @@ -70,31 +70,31 @@ // #define CONFIG_USBDEV_EP0_THREAD #ifndef CONFIG_USBDEV_EP0_PRIO - #define CONFIG_USBDEV_EP0_PRIO 4 +#define CONFIG_USBDEV_EP0_PRIO 4 #endif #ifndef CONFIG_USBDEV_EP0_STACKSIZE - #define CONFIG_USBDEV_EP0_STACKSIZE 2048 +#define CONFIG_USBDEV_EP0_STACKSIZE 2048 #endif #ifndef CONFIG_USBDEV_MSC_MAX_LUN - #define CONFIG_USBDEV_MSC_MAX_LUN 1 +#define CONFIG_USBDEV_MSC_MAX_LUN 1 #endif #ifndef CONFIG_USBDEV_MSC_MAX_BUFSIZE - #define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 +#define CONFIG_USBDEV_MSC_MAX_BUFSIZE 512 #endif #ifndef CONFIG_USBDEV_MSC_MANUFACTURER_STRING - #define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" +#define CONFIG_USBDEV_MSC_MANUFACTURER_STRING "" #endif #ifndef CONFIG_USBDEV_MSC_PRODUCT_STRING - #define CONFIG_USBDEV_MSC_PRODUCT_STRING "" +#define CONFIG_USBDEV_MSC_PRODUCT_STRING "" #endif #ifndef CONFIG_USBDEV_MSC_VERSION_STRING - #define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" +#define CONFIG_USBDEV_MSC_VERSION_STRING "0.01" #endif /* move msc read & write from isr to while(1), you should call usbd_msc_polling in while(1) */ @@ -104,50 +104,50 @@ // #define CONFIG_USBDEV_MSC_THREAD #ifndef CONFIG_USBDEV_MSC_PRIO - #define CONFIG_USBDEV_MSC_PRIO 4 +#define CONFIG_USBDEV_MSC_PRIO 4 #endif #ifndef CONFIG_USBDEV_MSC_STACKSIZE - #define CONFIG_USBDEV_MSC_STACKSIZE 2048 +#define CONFIG_USBDEV_MSC_STACKSIZE 2048 #endif #ifndef CONFIG_USBDEV_MTP_MAX_BUFSIZE - #define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 +#define CONFIG_USBDEV_MTP_MAX_BUFSIZE 2048 #endif #ifndef CONFIG_USBDEV_MTP_MAX_OBJECTS - #define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 +#define CONFIG_USBDEV_MTP_MAX_OBJECTS 256 #endif #ifndef CONFIG_USBDEV_MTP_MAX_PATHNAME - #define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 +#define CONFIG_USBDEV_MTP_MAX_PATHNAME 256 #endif #define CONFIG_USBDEV_MTP_THREAD #ifndef CONFIG_USBDEV_MTP_PRIO - #define CONFIG_USBDEV_MTP_PRIO 4 +#define CONFIG_USBDEV_MTP_PRIO 4 #endif #ifndef CONFIG_USBDEV_MTP_STACKSIZE - #define CONFIG_USBDEV_MTP_STACKSIZE 4096 +#define CONFIG_USBDEV_MTP_STACKSIZE 4096 #endif #ifndef CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE - #define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 +#define CONFIG_USBDEV_RNDIS_RESP_BUFFER_SIZE 156 #endif /* rndis transfer buffer size, must be a multiple of (1536 + 44)*/ #ifndef CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE - #define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 +#define CONFIG_USBDEV_RNDIS_ETH_MAX_FRAME_SIZE 1580 #endif #ifndef CONFIG_USBDEV_RNDIS_VENDOR_ID - #define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff +#define CONFIG_USBDEV_RNDIS_VENDOR_ID 0x0000ffff #endif #ifndef CONFIG_USBDEV_RNDIS_VENDOR_DESC - #define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" +#define CONFIG_USBDEV_RNDIS_VENDOR_DESC "CherryUSB" #endif #define CONFIG_USBDEV_RNDIS_USING_LWIP @@ -171,95 +171,95 @@ #define CONFIG_USBHOST_DEV_NAMELEN 16 #ifndef CONFIG_USBHOST_PSC_PRIO - #define CONFIG_USBHOST_PSC_PRIO 0 +#define CONFIG_USBHOST_PSC_PRIO 0 #endif #ifndef CONFIG_USBHOST_PSC_STACKSIZE - #define CONFIG_USBHOST_PSC_STACKSIZE 2048 +#define CONFIG_USBHOST_PSC_STACKSIZE 2048 #endif //#define CONFIG_USBHOST_GET_STRING_DESC // #define CONFIG_USBHOST_MSOS_ENABLE #ifndef CONFIG_USBHOST_MSOS_VENDOR_CODE - #define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 +#define CONFIG_USBHOST_MSOS_VENDOR_CODE 0x00 #endif /* Ep0 max transfer buffer */ #ifndef CONFIG_USBHOST_REQUEST_BUFFER_LEN - #define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 +#define CONFIG_USBHOST_REQUEST_BUFFER_LEN 512 #endif #ifndef CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT - #define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 +#define CONFIG_USBHOST_CONTROL_TRANSFER_TIMEOUT 500 #endif #ifndef CONFIG_USBHOST_MSC_TIMEOUT - #define CONFIG_USBHOST_MSC_TIMEOUT 5000 +#define CONFIG_USBHOST_MSC_TIMEOUT 5000 #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_RNDIS_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_RNDIS_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_CDC_NCM_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE (2048) #endif /* This parameter affects usb performance, and depends on (TCP_WND)tcp eceive windows size, * you can change to 2K ~ 16K and must be larger than TCP RX windows size in order to avoid being overflow. */ #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE - #define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) +#define CONFIG_USBHOST_RTL8152_ETH_MAX_RX_SIZE (2048) #endif /* Because lwip do not support multi pbuf at a time, so increasing this variable has no performance improvement */ #ifndef CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE - #define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) +#define CONFIG_USBHOST_RTL8152_ETH_MAX_TX_SIZE (2048) #endif #define CONFIG_USBHOST_BLUETOOTH_HCI_H4 // #define CONFIG_USBHOST_BLUETOOTH_HCI_LOG #ifndef CONFIG_USBHOST_BLUETOOTH_TX_SIZE - #define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 +#define CONFIG_USBHOST_BLUETOOTH_TX_SIZE 2048 #endif #ifndef CONFIG_USBHOST_BLUETOOTH_RX_SIZE - #define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 +#define CONFIG_USBHOST_BLUETOOTH_RX_SIZE 2048 #endif /* ================ USB Device Port Configuration ================*/ #ifndef CONFIG_USBDEV_MAX_BUS - #define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip +#define CONFIG_USBDEV_MAX_BUS 1 // for now, bus num must be 1 except hpm ip #endif #ifndef CONFIG_USBDEV_EP_NUM - #define CONFIG_USBDEV_EP_NUM 8 +#define CONFIG_USBDEV_EP_NUM 8 #endif // #define CONFIG_USBDEV_SOF_ENABLE @@ -276,76 +276,76 @@ // #define CONFIG_USB_DWC2_DMA_ENABLE /* Defined FS Core device FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) -#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX13_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE (32) /* Defined FS Core host FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) -#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) -#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) +#define CONFIG_USB_FS_CORE_HOST_RX_FIFO_SIZE (128) +#define CONFIG_USB_FS_CORE_HOST_NP_FIFO_SIZE (32) +#define CONFIG_USB_FS_CORE_HOST_PE_FIFO_SIZE (64) /* Defined FS Core total FIFO Size in words 32-bits */ -#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (640) +#define CONFIG_USB_FS_CORE_TOTAL_FIFO_SIZE (640) /* Defined HS Core Device FIFO Size in words 32-bits */ -#define CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE (1024) -#define CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE (0) -#define CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE (1024) +#define CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE (0) +#define CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE (0) /* Defined HS Core host FIFO Size in words 32-bits */ -#define CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE (512) -#define CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE (128) -#define CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE (256) +#define CONFIG_USB_HS_CORE_HOST_RX_FIFO_SIZE (512) +#define CONFIG_USB_HS_CORE_HOST_NP_FIFO_SIZE (128) +#define CONFIG_USB_HS_CORE_HOST_PE_FIFO_SIZE (256) /* Defined HS Core total FIFO Size in words 32-bits */ -#define CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE (2048) +#define CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE (2048) /* ================ USB Host Port Configuration ==================*/ #ifndef CONFIG_USBHOST_MAX_BUS - #define CONFIG_USBHOST_MAX_BUS 1 +#define CONFIG_USBHOST_MAX_BUS 1 #endif #ifndef CONFIG_USBHOST_PIPE_NUM - #define CONFIG_USBHOST_PIPE_NUM 10 +#define CONFIG_USBHOST_PIPE_NUM 10 #endif #ifndef usb_phyaddr2ramaddr - #define usb_phyaddr2ramaddr(addr) (addr) +#define usb_phyaddr2ramaddr(addr) (addr) #endif #ifndef usb_ramaddr2phyaddr - #define usb_ramaddr2phyaddr(addr) (addr) +#define usb_ramaddr2phyaddr(addr) (addr) #endif #endif diff --git a/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.h b/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.h index cd2e4633170..c2c6505d670 100644 --- a/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.h +++ b/bsp/hc32/ev_hc32f4a8_lqfp176/rtconfig.h @@ -72,7 +72,7 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 @@ -329,14 +329,6 @@ /* GD32 Drivers */ /* end of GD32 Drivers */ - -/* HPMicro SDK */ - -/* end of HPMicro SDK */ - -/* FT32 HAL & SDK Drivers */ - -/* end of FT32 HAL & SDK Drivers */ /* end of HAL & SDK Drivers */ /* sensors drivers */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/.config b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.config index 3ca5d90a636..d919cbe6e00 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/.config +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/.config @@ -125,7 +125,7 @@ CONFIG_RT_HOOK_USING_FUNC_PTR=y # CONFIG_RT_USING_HOOKLIST is not set CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_IDLE_THREAD_STACK_SIZE=512 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/xtal32_fcm.c b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/xtal32_fcm.c index c84a42fbc80..0f90b78297f 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/xtal32_fcm.c +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/applications/xtal32_fcm.c @@ -18,8 +18,8 @@ #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) -#define XTAL32_FCM_THREAD_STACK_SIZE (1024) -#define XTAL32_FCM_UNIT (CM_FCM) +#define XTAL32_FCM_THREAD_STACK_SIZE (1024) +#define XTAL32_FCM_UNIT (CM_FCM) /** * @brief This thread is used to monitor whether XTAL32 is stable. @@ -36,13 +36,13 @@ void xtal32_fcm_thread_entry(void *parameter) /* FCM config */ FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_FCM, ENABLE); (void)FCM_StructInit(&stcFcmInit); - stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; - stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ - stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; - stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; + stcFcmInit.u32RefClock = FCM_REF_CLK_MRC; + stcFcmInit.u32RefClockDiv = FCM_REF_CLK_DIV8192; /* ~1ms cycle */ + stcFcmInit.u32RefClockEdge = FCM_REF_CLK_RISING; + stcFcmInit.u32TargetClock = FCM_TARGET_CLK_XTAL32; stcFcmInit.u32TargetClockDiv = FCM_TARGET_CLK_DIV1; - stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); - stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); + stcFcmInit.u16LowerLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 96UL / 100UL); + stcFcmInit.u16UpperLimit = (uint16_t)((XTAL32_VALUE / (MRC_VALUE / 8192U)) * 104UL / 100UL); (void)FCM_Init(XTAL32_FCM_UNIT, &stcFcmInit); /* Enable FCM, to ensure xtal32 stable */ FCM_Cmd(XTAL32_FCM_UNIT, ENABLE); diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig index 6c91f7e6603..b449422c990 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/Kconfig @@ -910,45 +910,45 @@ menu "On-chip Peripheral Drivers" endif menuconfig BSP_USING_CLOCK_TIMER - bool "Enable Hw Timer" + bool "Enable Clock Timer" default n select RT_USING_CLOCK_TIME if BSP_USING_CLOCK_TIMER config BSP_USING_TMRA_1 - bool "Use Timer_a1 As The Hw Timer" + bool "Use Timer_a1 As The Clock Timer" default n config BSP_USING_TMRA_2 - bool "Use Timer_a2 As The Hw Timer" + bool "Use Timer_a2 As The Clock Timer" default n config BSP_USING_TMRA_3 - bool "Use Timer_a3 As The Hw Timer" + bool "Use Timer_a3 As The Clock Timer" default n config BSP_USING_TMRA_4 - bool "Use Timer_a4 As The Hw Timer" + bool "Use Timer_a4 As The Clock Timer" default n config BSP_USING_TMRA_5 - bool "Use Timer_a5 As The Hw Timer" + bool "Use Timer_a5 As The Clock Timer" default n config BSP_USING_TMRA_6 - bool "Use Timer_a6 As The Hw Timer" + bool "Use Timer_a6 As The Clock Timer" default n config BSP_USING_TMRA_7 - bool "Use Timer_a7 As The Hw Timer" + bool "Use Timer_a7 As The Clock Timer" default n config BSP_USING_TMRA_8 - bool "Use Timer_a8 As The Hw Timer" + bool "Use Timer_a8 As The Clock Timer" default n config BSP_USING_TMRA_9 - bool "Use Timer_a9 As The Hw Timer" + bool "Use Timer_a9 As The Clock Timer" default n config BSP_USING_TMRA_10 - bool "Use Timer_a10 As The Hw Timer" + bool "Use Timer_a10 As The Clock Timer" default n config BSP_USING_TMRA_11 - bool "Use Timer_a11 As The Hw Timer" + bool "Use Timer_a11 As The Clock Timer" default n config BSP_USING_TMRA_12 - bool "Use Timer_a12 As The Hw Timer" + bool "Use Timer_a12 As The Clock Timer" default n endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c index c254a68b6ee..de9153e5b12 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.c @@ -12,16 +12,16 @@ #include "board_config.h" /* unlock/lock peripheral */ -#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ - LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) -#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) +#define EXAMPLE_PERIPH_WE (LL_PERIPH_GPIO | LL_PERIPH_EFM | LL_PERIPH_FCG | \ + LL_PERIPH_PWC_CLK_RMU | LL_PERIPH_SRAM | LL_PERIPH_LVD) +#define EXAMPLE_PERIPH_WP (LL_PERIPH_EFM | LL_PERIPH_FCG | LL_PERIPH_SRAM) #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) /** * @brief Switch clock stable time * @note Approx. 30us */ -#define CLK_SYSCLK_SW_STB (HCLK_VALUE / 50000UL) +#define CLK_SYSCLK_SW_STB (HCLK_VALUE / 50000UL) /** * @brief Clk delay function * @param [in] u32Delay count @@ -72,17 +72,17 @@ void SystemClock_Config(void) /* PCLK1, PCLK4 Max 120MHz */ /* PCLK2, PCLK3 Max 60MHz */ /* EX BUS Max 120MHz */ - CLK_SetClockDiv(CLK_BUS_CLK_ALL, \ - (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \ - CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \ + CLK_SetClockDiv(CLK_BUS_CLK_ALL, + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | CLK_HCLK_DIV1)); GPIO_AnalogCmd(XTAL_PORT, XTAL_IN_PIN | XTAL_OUT_PIN, ENABLE); (void)CLK_XtalStructInit(&stcXtalInit); /* Config Xtal and enable Xtal */ - stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; - stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; - stcXtalInit.u8State = CLK_XTAL_ON; + stcXtalInit.u8Mode = CLK_XTAL_MD_OSC; + stcXtalInit.u8Drv = CLK_XTAL_DRV_ULOW; + stcXtalInit.u8State = CLK_XTAL_ON; stcXtalInit.u8StableTime = CLK_XTAL_STB_2MS; (void)CLK_XtalInit(&stcXtalInit); @@ -126,8 +126,8 @@ void SystemClock_Config(void) /* Xtal32 config */ GPIO_AnalogCmd(XTAL32_PORT, XTAL32_IN_PIN | XTAL32_OUT_PIN, ENABLE); (void)CLK_Xtal32StructInit(&stcXtal32Init); - stcXtal32Init.u8State = CLK_XTAL32_ON; - stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; + stcXtal32Init.u8State = CLK_XTAL32_ON; + stcXtal32Init.u8Drv = CLK_XTAL32_DRV_HIGH; stcXtal32Init.u8Filter = CLK_XTAL32_FILTER_RUN_MD; (void)CLK_Xtal32Init(&stcXtal32Init); #endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h index ea804ffbdfa..d5b4daa383b 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board.h @@ -20,27 +20,27 @@ extern "C" { #endif -#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) -#define HC32_FLASH_WRITE_GRANULARITY (4) -#define HC32_FLASH_SIZE (2 * 1024 * 1024) -#define HC32_FLASH_START_ADDRESS (0) -#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) +#define HC32_FLASH_ERASE_GRANULARITY (8 * 1024) +#define HC32_FLASH_WRITE_GRANULARITY (4) +#define HC32_FLASH_SIZE (2 * 1024 * 1024) +#define HC32_FLASH_START_ADDRESS (0) +#define HC32_FLASH_END_ADDRESS (HC32_FLASH_START_ADDRESS + HC32_FLASH_SIZE) -#define HC32_SRAM_SIZE (512) -#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) +#define HC32_SRAM_SIZE (512) +#define HC32_SRAM_END (0x1FFE0000 + HC32_SRAM_SIZE * 1024) #ifdef __ARMCC_VERSION extern int Image$$RW_IRAM2$$ZI$$Limit; -#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) +#define HEAP_BEGIN (&Image$$RW_IRAM2$$ZI$$Limit) #elif __ICCARM__ -#pragma section="HEAP" -#define HEAP_BEGIN (__segment_end("HEAP")) +#pragma section = "HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) #else extern int __bss_end; -#define HEAP_BEGIN (&__bss_end) +#define HEAP_BEGIN (&__bss_end) #endif -#define HEAP_END HC32_SRAM_END +#define HEAP_END HC32_SRAM_END void PeripheralRegister_Unlock(void); void PeripheralClock_Config(void); diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.c b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.c index c1d4d1f192e..28d03b6f78a 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.c +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.c @@ -169,7 +169,7 @@ rt_err_t rt_hw_board_can_init(CM_CAN_TypeDef *CANx) #endif -#if defined (RT_USING_SPI) +#if defined(RT_USING_SPI) rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) { rt_err_t result = RT_EOK; @@ -183,17 +183,17 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) case (rt_uint32_t)CM_SPI1: GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinState = PIN_STAT_SET; - stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinDir = PIN_DIR_OUT; GPIO_Init(SPI1_WP_PORT, SPI1_WP_PIN, &stcGpioInit); GPIO_Init(SPI1_HOLD_PORT, SPI1_HOLD_PIN, &stcGpioInit); (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; stcGpioInit.u16PinInputType = PIN_IN_TYPE_CMOS; - (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); + (void)GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioInit); (void)GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioInit); - GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_FUNC); GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_FUNC); GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_FUNC); break; @@ -209,14 +209,14 @@ rt_err_t rt_hw_spi_board_init(CM_SPI_TypeDef *CM_SPIx) #if defined(BSP_USING_ETH) /* PHY hardware reset time */ -#define PHY_HW_RST_DELAY (0x40U) +#define PHY_HW_RST_DELAY (0x40U) rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) { TCA9539_ConfigPin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_DIR_OUT); - TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_RESET); rt_thread_mdelay(PHY_HW_RST_DELAY); - TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); + TCA9539_WritePin(TCA9539_IO_PORT1, EIO_ETH_RST, TCA9539_PIN_SET); rt_thread_mdelay(PHY_HW_RST_DELAY); return RT_EOK; } @@ -224,39 +224,39 @@ rt_err_t rt_hw_eth_phy_reset(CM_ETH_TypeDef *CM_ETHx) rt_err_t rt_hw_eth_board_init(CM_ETH_TypeDef *CM_ETHx) { #if defined(ETH_INTERFACE_USING_RMII) - GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); - GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); - GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); - GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); - GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_RMII_TX_EN_PORT, ETH_RMII_TX_EN_PIN, ETH_RMII_TX_EN_FUNC); + GPIO_SetFunc(ETH_RMII_TXD0_PORT, ETH_RMII_TXD0_PIN, ETH_RMII_TXD0_FUNC); + GPIO_SetFunc(ETH_RMII_TXD1_PORT, ETH_RMII_TXD1_PIN, ETH_RMII_TXD1_FUNC); GPIO_SetFunc(ETH_RMII_REF_CLK_PORT, ETH_RMII_REF_CLK_PIN, ETH_RMII_REF_CLK_FUNC); - GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); - GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); - GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); + GPIO_SetFunc(ETH_RMII_CRS_DV_PORT, ETH_RMII_CRS_DV_PIN, ETH_RMII_CRS_DV_FUNC); + GPIO_SetFunc(ETH_RMII_RXD0_PORT, ETH_RMII_RXD0_PIN, ETH_RMII_RXD0_FUNC); + GPIO_SetFunc(ETH_RMII_RXD1_PORT, ETH_RMII_RXD1_PIN, ETH_RMII_RXD1_FUNC); #else - GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); - GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); + GPIO_SetFunc(ETH_SMI_MDIO_PORT, ETH_SMI_MDIO_PIN, ETH_SMI_MDIO_FUNC); + GPIO_SetFunc(ETH_SMI_MDC_PORT, ETH_SMI_MDC_PIN, ETH_SMI_MDC_FUNC); GPIO_SetFunc(ETH_MII_TX_CLK_PORT, ETH_MII_TX_CLK_PIN, ETH_MII_TX_CLK_FUNC); - GPIO_SetFunc(ETH_MII_TX_EN_PORT, ETH_MII_TX_EN_PIN, ETH_MII_TX_EN_FUNC); - GPIO_SetFunc(ETH_MII_TXD0_PORT, ETH_MII_TXD0_PIN, ETH_MII_TXD0_FUNC); - GPIO_SetFunc(ETH_MII_TXD1_PORT, ETH_MII_TXD1_PIN, ETH_MII_TXD1_FUNC); - GPIO_SetFunc(ETH_MII_TXD2_PORT, ETH_MII_TXD2_PIN, ETH_MII_TXD2_FUNC); - GPIO_SetFunc(ETH_MII_TXD3_PORT, ETH_MII_TXD3_PIN, ETH_MII_TXD3_FUNC); + GPIO_SetFunc(ETH_MII_TX_EN_PORT, ETH_MII_TX_EN_PIN, ETH_MII_TX_EN_FUNC); + GPIO_SetFunc(ETH_MII_TXD0_PORT, ETH_MII_TXD0_PIN, ETH_MII_TXD0_FUNC); + GPIO_SetFunc(ETH_MII_TXD1_PORT, ETH_MII_TXD1_PIN, ETH_MII_TXD1_FUNC); + GPIO_SetFunc(ETH_MII_TXD2_PORT, ETH_MII_TXD2_PIN, ETH_MII_TXD2_FUNC); + GPIO_SetFunc(ETH_MII_TXD3_PORT, ETH_MII_TXD3_PIN, ETH_MII_TXD3_FUNC); GPIO_SetFunc(ETH_MII_RX_CLK_PORT, ETH_MII_RX_CLK_PIN, ETH_MII_RX_CLK_FUNC); - GPIO_SetFunc(ETH_MII_RX_DV_PORT, ETH_MII_RX_DV_PIN, ETH_MII_RX_DV_FUNC); - GPIO_SetFunc(ETH_MII_RXD0_PORT, ETH_MII_RXD0_PIN, ETH_MII_RXD0_FUNC); - GPIO_SetFunc(ETH_MII_RXD1_PORT, ETH_MII_RXD1_PIN, ETH_MII_RXD1_FUNC); - GPIO_SetFunc(ETH_MII_RXD2_PORT, ETH_MII_RXD2_PIN, ETH_MII_RXD2_FUNC); - GPIO_SetFunc(ETH_MII_RXD3_PORT, ETH_MII_RXD3_PIN, ETH_MII_RXD3_FUNC); - GPIO_SetFunc(ETH_MII_RX_ER_PORT, ETH_MII_RX_ER_PIN, ETH_MII_RX_ER_FUNC); - GPIO_SetFunc(ETH_MII_CRS_PORT, ETH_MII_CRS_PIN, ETH_MII_CRS_FUNC); - GPIO_SetFunc(ETH_MII_COL_PORT, ETH_MII_COL_PIN, ETH_MII_COL_FUNC); + GPIO_SetFunc(ETH_MII_RX_DV_PORT, ETH_MII_RX_DV_PIN, ETH_MII_RX_DV_FUNC); + GPIO_SetFunc(ETH_MII_RXD0_PORT, ETH_MII_RXD0_PIN, ETH_MII_RXD0_FUNC); + GPIO_SetFunc(ETH_MII_RXD1_PORT, ETH_MII_RXD1_PIN, ETH_MII_RXD1_FUNC); + GPIO_SetFunc(ETH_MII_RXD2_PORT, ETH_MII_RXD2_PIN, ETH_MII_RXD2_FUNC); + GPIO_SetFunc(ETH_MII_RXD3_PORT, ETH_MII_RXD3_PIN, ETH_MII_RXD3_FUNC); + GPIO_SetFunc(ETH_MII_RX_ER_PORT, ETH_MII_RX_ER_PIN, ETH_MII_RX_ER_FUNC); + GPIO_SetFunc(ETH_MII_CRS_PORT, ETH_MII_CRS_PIN, ETH_MII_CRS_FUNC); + GPIO_SetFunc(ETH_MII_COL_PORT, ETH_MII_COL_PIN, ETH_MII_COL_FUNC); #endif return RT_EOK; } #endif -#if defined (RT_USING_SDIO) +#if defined(RT_USING_SDIO) rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) { rt_err_t result = RT_EOK; @@ -269,19 +269,19 @@ rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx) /************************* Set pin drive capacity *************************/ (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; - (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_CK_PORT, SDIOC1_CK_PIN, &stcGpioInit); (void)GPIO_Init(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); - (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D0_PORT, SDIOC1_D0_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D1_PORT, SDIOC1_D1_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D2_PORT, SDIOC1_D2_PIN, &stcGpioInit); + (void)GPIO_Init(SDIOC1_D3_PORT, SDIOC1_D3_PIN, &stcGpioInit); - GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); + GPIO_SetFunc(SDIOC1_CK_PORT, SDIOC1_CK_PIN, SDIOC1_CK_FUNC); GPIO_SetFunc(SDIOC1_CMD_PORT, SDIOC1_CMD_PIN, SDIOC1_CMD_FUNC); - GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); - GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); - GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); - GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); + GPIO_SetFunc(SDIOC1_D0_PORT, SDIOC1_D0_PIN, SDIOC1_D0_FUNC); + GPIO_SetFunc(SDIOC1_D1_PORT, SDIOC1_D1_PIN, SDIOC1_D1_FUNC); + GPIO_SetFunc(SDIOC1_D2_PORT, SDIOC1_D2_PIN, SDIOC1_D2_FUNC); + GPIO_SetFunc(SDIOC1_D3_PORT, SDIOC1_D3_PIN, SDIOC1_D3_FUNC); break; #endif default: @@ -390,7 +390,7 @@ rt_err_t rt_hw_board_pwm_tmr6_init(CM_TMR6_TypeDef *TMR6x) #endif #endif -#if defined (BSP_USING_SDRAM) +#if defined(BSP_USING_SDRAM) rt_err_t rt_hw_board_sdram_init(void) { rt_err_t result = RT_EOK; @@ -464,16 +464,16 @@ rt_err_t rt_hw_board_sdram_init(void) /* DMC_WE */ GPIO_SetFunc(SDRAM_WE_PORT, SDRAM_WE_PIN, SDRAM_WE_FUNC); /* DMC_DATA[0:15] */ - GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); - GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); - GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); - GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); - GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); - GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); - GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); - GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); - GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); - GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); + GPIO_SetFunc(SDRAM_DATA0_PORT, SDRAM_DATA0_PIN, SDRAM_DATA0_FUNC); + GPIO_SetFunc(SDRAM_DATA1_PORT, SDRAM_DATA1_PIN, SDRAM_DATA1_FUNC); + GPIO_SetFunc(SDRAM_DATA2_PORT, SDRAM_DATA2_PIN, SDRAM_DATA2_FUNC); + GPIO_SetFunc(SDRAM_DATA3_PORT, SDRAM_DATA3_PIN, SDRAM_DATA3_FUNC); + GPIO_SetFunc(SDRAM_DATA4_PORT, SDRAM_DATA4_PIN, SDRAM_DATA4_FUNC); + GPIO_SetFunc(SDRAM_DATA5_PORT, SDRAM_DATA5_PIN, SDRAM_DATA5_FUNC); + GPIO_SetFunc(SDRAM_DATA6_PORT, SDRAM_DATA6_PIN, SDRAM_DATA6_FUNC); + GPIO_SetFunc(SDRAM_DATA7_PORT, SDRAM_DATA7_PIN, SDRAM_DATA7_FUNC); + GPIO_SetFunc(SDRAM_DATA8_PORT, SDRAM_DATA8_PIN, SDRAM_DATA8_FUNC); + GPIO_SetFunc(SDRAM_DATA9_PORT, SDRAM_DATA9_PIN, SDRAM_DATA9_FUNC); GPIO_SetFunc(SDRAM_DATA10_PORT, SDRAM_DATA10_PIN, SDRAM_DATA10_FUNC); GPIO_SetFunc(SDRAM_DATA11_PORT, SDRAM_DATA11_PIN, SDRAM_DATA11_FUNC); GPIO_SetFunc(SDRAM_DATA12_PORT, SDRAM_DATA12_PIN, SDRAM_DATA12_FUNC); @@ -481,16 +481,16 @@ rt_err_t rt_hw_board_sdram_init(void) GPIO_SetFunc(SDRAM_DATA14_PORT, SDRAM_DATA14_PIN, SDRAM_DATA14_FUNC); GPIO_SetFunc(SDRAM_DATA15_PORT, SDRAM_DATA15_PIN, SDRAM_DATA15_FUNC); /* DMC_ADD[0:11]*/ - GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); - GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); - GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); - GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); - GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); - GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); - GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); - GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); - GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); - GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); + GPIO_SetFunc(SDRAM_ADD0_PORT, SDRAM_ADD0_PIN, SDRAM_ADD0_FUNC); + GPIO_SetFunc(SDRAM_ADD1_PORT, SDRAM_ADD1_PIN, SDRAM_ADD1_FUNC); + GPIO_SetFunc(SDRAM_ADD2_PORT, SDRAM_ADD2_PIN, SDRAM_ADD2_FUNC); + GPIO_SetFunc(SDRAM_ADD3_PORT, SDRAM_ADD3_PIN, SDRAM_ADD3_FUNC); + GPIO_SetFunc(SDRAM_ADD4_PORT, SDRAM_ADD4_PIN, SDRAM_ADD4_FUNC); + GPIO_SetFunc(SDRAM_ADD5_PORT, SDRAM_ADD5_PIN, SDRAM_ADD5_FUNC); + GPIO_SetFunc(SDRAM_ADD6_PORT, SDRAM_ADD6_PIN, SDRAM_ADD6_FUNC); + GPIO_SetFunc(SDRAM_ADD7_PORT, SDRAM_ADD7_PIN, SDRAM_ADD7_FUNC); + GPIO_SetFunc(SDRAM_ADD8_PORT, SDRAM_ADD8_PIN, SDRAM_ADD8_FUNC); + GPIO_SetFunc(SDRAM_ADD9_PORT, SDRAM_ADD9_PIN, SDRAM_ADD9_FUNC); GPIO_SetFunc(SDRAM_ADD10_PORT, SDRAM_ADD10_PIN, SDRAM_ADD10_FUNC); GPIO_SetFunc(SDRAM_ADD11_PORT, SDRAM_ADD11_PIN, SDRAM_ADD11_FUNC); @@ -568,14 +568,14 @@ rt_err_t rt_hw_usb_board_init(void) GPIO_SetFunc(USBH_ULPI_DIR_PORT, USBH_ULPI_DIR_PIN, USBH_ULPI_DIR_FUNC); GPIO_SetFunc(USBH_ULPI_NXT_PORT, USBH_ULPI_NXT_PIN, USBH_ULPI_NXT_FUNC); GPIO_SetFunc(USBH_ULPI_STP_PORT, USBH_ULPI_STP_PIN, USBH_ULPI_STP_FUNC); - GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); - GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); - GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); - GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); - GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); - GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); - GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); - GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); + GPIO_SetFunc(USBH_ULPI_D0_PORT, USBH_ULPI_D0_PIN, USBH_ULPI_D0_FUNC); + GPIO_SetFunc(USBH_ULPI_D1_PORT, USBH_ULPI_D1_PIN, USBH_ULPI_D1_FUNC); + GPIO_SetFunc(USBH_ULPI_D2_PORT, USBH_ULPI_D2_PIN, USBH_ULPI_D2_FUNC); + GPIO_SetFunc(USBH_ULPI_D3_PORT, USBH_ULPI_D3_PIN, USBH_ULPI_D3_FUNC); + GPIO_SetFunc(USBH_ULPI_D4_PORT, USBH_ULPI_D4_PIN, USBH_ULPI_D4_FUNC); + GPIO_SetFunc(USBH_ULPI_D5_PORT, USBH_ULPI_D5_PIN, USBH_ULPI_D5_FUNC); + GPIO_SetFunc(USBH_ULPI_D6_PORT, USBH_ULPI_D6_PIN, USBH_ULPI_D6_FUNC); + GPIO_SetFunc(USBH_ULPI_D7_PORT, USBH_ULPI_D7_PIN, USBH_ULPI_D7_FUNC); TCA9539_WritePin(TCA9539_IO_PORT1, USB_3300_RESET_PIN, TCA9539_PIN_RESET); #endif @@ -593,8 +593,8 @@ rt_err_t rt_hw_qspi_board_init(void) (void)GPIO_StructInit(&stcGpioInit); stcGpioInit.u16PinDrv = PIN_HIGH_DRV; #ifndef BSP_QSPI_USING_SOFT_CS - (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); - GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); + (void)GPIO_Init(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, &stcGpioInit); + GPIO_SetFunc(QSPI_FLASH_CS_PORT, QSPI_FLASH_CS_PIN, QSPI_FLASH_CS_FUNC); #endif (void)GPIO_Init(QSPI_FLASH_SCK_PORT, QSPI_FLASH_SCK_PIN, &stcGpioInit); (void)GPIO_Init(QSPI_FLASH_IO0_PORT, QSPI_FLASH_IO0_PIN, &stcGpioInit); @@ -635,7 +635,7 @@ rt_err_t rt_hw_board_pulse_encoder_tmr6_init(void) } #endif -#if defined (BSP_USING_NAND) +#if defined(BSP_USING_NAND) rt_err_t rt_hw_board_nand_init(void) { rt_err_t result = RT_EOK; diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.h index 13a33752bf4..3eaf0f01883 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/board_config.h @@ -18,660 +18,660 @@ /************************* XTAL port **********************/ -#define XTAL_PORT (GPIO_PORT_H) -#define XTAL_IN_PIN (GPIO_PIN_01) -#define XTAL_OUT_PIN (GPIO_PIN_00) +#define XTAL_PORT (GPIO_PORT_H) +#define XTAL_IN_PIN (GPIO_PIN_01) +#define XTAL_OUT_PIN (GPIO_PIN_00) /************************ USART port **********************/ #if defined(BSP_USING_UART1) - #define USART1_RX_PORT (GPIO_PORT_A) - #define USART1_RX_PIN (GPIO_PIN_10) - #define USART1_RX_FUNC (GPIO_FUNC_20) +#define USART1_RX_PORT (GPIO_PORT_A) +#define USART1_RX_PIN (GPIO_PIN_10) +#define USART1_RX_FUNC (GPIO_FUNC_20) - #define USART1_TX_PORT (GPIO_PORT_A) - #define USART1_TX_PIN (GPIO_PIN_09) - #define USART1_TX_FUNC (GPIO_FUNC_20) +#define USART1_TX_PORT (GPIO_PORT_A) +#define USART1_TX_PIN (GPIO_PIN_09) +#define USART1_TX_FUNC (GPIO_FUNC_20) #endif #if defined(BSP_USING_UART6) - #define USART6_RX_PORT (GPIO_PORT_H) - #define USART6_RX_PIN (GPIO_PIN_06) - #define USART6_RX_FUNC (GPIO_FUNC_37) +#define USART6_RX_PORT (GPIO_PORT_H) +#define USART6_RX_PIN (GPIO_PIN_06) +#define USART6_RX_FUNC (GPIO_FUNC_37) - #define USART6_TX_PORT (GPIO_PORT_E) - #define USART6_TX_PIN (GPIO_PIN_06) - #define USART6_TX_FUNC (GPIO_FUNC_36) +#define USART6_TX_PORT (GPIO_PORT_E) +#define USART6_TX_PIN (GPIO_PIN_06) +#define USART6_TX_FUNC (GPIO_FUNC_36) #endif /************************ I2C port **********************/ #if defined(BSP_USING_I2C1) - #define I2C1_SDA_PORT (GPIO_PORT_F) - #define I2C1_SDA_PIN (GPIO_PIN_10) - #define I2C1_SDA_FUNC (GPIO_FUNC_48) +#define I2C1_SDA_PORT (GPIO_PORT_F) +#define I2C1_SDA_PIN (GPIO_PIN_10) +#define I2C1_SDA_FUNC (GPIO_FUNC_48) - #define I2C1_SCL_PORT (GPIO_PORT_D) - #define I2C1_SCL_PIN (GPIO_PIN_03) - #define I2C1_SCL_FUNC (GPIO_FUNC_49) +#define I2C1_SCL_PORT (GPIO_PORT_D) +#define I2C1_SCL_PIN (GPIO_PIN_03) +#define I2C1_SCL_FUNC (GPIO_FUNC_49) #endif /*********** ADC configure *********/ #if defined(BSP_USING_ADC1) - #define ADC1_CH_PORT (GPIO_PORT_C) - #define ADC1_CH_PIN (GPIO_PIN_00) +#define ADC1_CH_PORT (GPIO_PORT_C) +#define ADC1_CH_PIN (GPIO_PIN_00) #endif #if defined(BSP_USING_ADC2) - #define ADC2_CH_PORT (GPIO_PORT_C) - #define ADC2_CH_PIN (GPIO_PIN_01) +#define ADC2_CH_PORT (GPIO_PORT_C) +#define ADC2_CH_PIN (GPIO_PIN_01) #endif #if defined(BSP_USING_ADC3) - #define ADC3_CH_PORT (GPIO_PORT_C) - #define ADC3_CH_PIN (GPIO_PIN_02) +#define ADC3_CH_PORT (GPIO_PORT_C) +#define ADC3_CH_PIN (GPIO_PIN_02) #endif /*********** DAC configure *********/ #if defined(BSP_USING_DAC1) - #define DAC1_CH1_PORT (GPIO_PORT_A) - #define DAC1_CH1_PIN (GPIO_PIN_04) - #define DAC1_CH2_PORT (GPIO_PORT_A) - #define DAC1_CH2_PIN (GPIO_PIN_05) +#define DAC1_CH1_PORT (GPIO_PORT_A) +#define DAC1_CH1_PIN (GPIO_PIN_04) +#define DAC1_CH2_PORT (GPIO_PORT_A) +#define DAC1_CH2_PIN (GPIO_PIN_05) #endif #if defined(BSP_USING_DAC2) - #define DAC2_CH1_PORT (GPIO_PORT_C) - #define DAC2_CH1_PIN (GPIO_PIN_04) - #define DAC2_CH2_PORT (GPIO_PORT_C) - #define DAC2_CH2_PIN (GPIO_PIN_05) +#define DAC2_CH1_PORT (GPIO_PORT_C) +#define DAC2_CH1_PIN (GPIO_PIN_04) +#define DAC2_CH2_PORT (GPIO_PORT_C) +#define DAC2_CH2_PIN (GPIO_PIN_05) #endif /*********** CAN configure *********/ #if defined(BSP_USING_CAN1) - #define CAN1_TX_PORT (GPIO_PORT_D) - #define CAN1_TX_PIN (GPIO_PIN_05) - #define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) +#define CAN1_TX_PORT (GPIO_PORT_D) +#define CAN1_TX_PIN (GPIO_PIN_05) +#define CAN1_TX_PIN_FUNC (GPIO_FUNC_60) - #define CAN1_RX_PORT (GPIO_PORT_D) - #define CAN1_RX_PIN (GPIO_PIN_04) - #define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) +#define CAN1_RX_PORT (GPIO_PORT_D) +#define CAN1_RX_PIN (GPIO_PIN_04) +#define CAN1_RX_PIN_FUNC (GPIO_FUNC_61) #endif #if defined(BSP_USING_CAN2) - #define CAN2_TX_PORT (GPIO_PORT_D) - #define CAN2_TX_PIN (GPIO_PIN_07) - #define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) +#define CAN2_TX_PORT (GPIO_PORT_D) +#define CAN2_TX_PIN (GPIO_PIN_07) +#define CAN2_TX_PIN_FUNC (GPIO_FUNC_62) - #define CAN2_RX_PORT (GPIO_PORT_D) - #define CAN2_RX_PIN (GPIO_PIN_06) - #define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) +#define CAN2_RX_PORT (GPIO_PORT_D) +#define CAN2_RX_PIN (GPIO_PIN_06) +#define CAN2_RX_PIN_FUNC (GPIO_FUNC_63) #endif /************************* SPI port ***********************/ #if defined(BSP_USING_SPI1) - #define SPI1_CS_PORT (GPIO_PORT_A) - #define SPI1_CS_PIN (GPIO_PIN_04) +#define SPI1_CS_PORT (GPIO_PORT_A) +#define SPI1_CS_PIN (GPIO_PIN_04) - #define SPI1_SCK_PORT (GPIO_PORT_A) - #define SPI1_SCK_PIN (GPIO_PIN_05) - #define SPI1_SCK_FUNC (GPIO_FUNC_40) +#define SPI1_SCK_PORT (GPIO_PORT_A) +#define SPI1_SCK_PIN (GPIO_PIN_05) +#define SPI1_SCK_FUNC (GPIO_FUNC_40) - #define SPI1_MOSI_PORT (GPIO_PORT_A) - #define SPI1_MOSI_PIN (GPIO_PIN_07) - #define SPI1_MOSI_FUNC (GPIO_FUNC_41) +#define SPI1_MOSI_PORT (GPIO_PORT_A) +#define SPI1_MOSI_PIN (GPIO_PIN_07) +#define SPI1_MOSI_FUNC (GPIO_FUNC_41) - #define SPI1_MISO_PORT (GPIO_PORT_A) - #define SPI1_MISO_PIN (GPIO_PIN_06) - #define SPI1_MISO_FUNC (GPIO_FUNC_42) +#define SPI1_MISO_PORT (GPIO_PORT_A) +#define SPI1_MISO_PIN (GPIO_PIN_06) +#define SPI1_MISO_FUNC (GPIO_FUNC_42) - #define SPI1_WP_PORT (GPIO_PORT_B) - #define SPI1_WP_PIN (GPIO_PIN_10) +#define SPI1_WP_PORT (GPIO_PORT_B) +#define SPI1_WP_PIN (GPIO_PIN_10) - #define SPI1_HOLD_PORT (GPIO_PORT_B) - #define SPI1_HOLD_PIN (GPIO_PIN_02) +#define SPI1_HOLD_PORT (GPIO_PORT_B) +#define SPI1_HOLD_PIN (GPIO_PIN_02) #endif /************************* ETH port ***********************/ #if defined(BSP_USING_ETH) - #if defined(ETH_INTERFACE_USING_RMII) - #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) - #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) - #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) - - #define ETH_SMI_MDC_PORT (GPIO_PORT_C) - #define ETH_SMI_MDC_PIN (GPIO_PIN_01) - #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) - #define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) - #define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_TXD0_PORT (GPIO_PORT_G) - #define ETH_RMII_TXD0_PIN (GPIO_PIN_13) - #define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_TXD1_PORT (GPIO_PORT_G) - #define ETH_RMII_TXD1_PIN (GPIO_PIN_14) - #define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) - #define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) - #define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) - #define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) - #define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_RXD0_PORT (GPIO_PORT_C) - #define ETH_RMII_RXD0_PIN (GPIO_PIN_04) - #define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) - - #define ETH_RMII_RXD1_PORT (GPIO_PORT_C) - #define ETH_RMII_RXD1_PIN (GPIO_PIN_05) - #define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) - #else - #define ETH_SMI_MDIO_PORT (GPIO_PORT_A) - #define ETH_SMI_MDIO_PIN (GPIO_PIN_02) - #define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) - - #define ETH_SMI_MDC_PORT (GPIO_PORT_C) - #define ETH_SMI_MDC_PIN (GPIO_PIN_01) - #define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TX_CLK_PORT (GPIO_PORT_B) - #define ETH_MII_TX_CLK_PIN (GPIO_PIN_06) - #define ETH_MII_TX_CLK_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TX_EN_PORT (GPIO_PORT_G) - #define ETH_MII_TX_EN_PIN (GPIO_PIN_11) - #define ETH_MII_TX_EN_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD0_PORT (GPIO_PORT_G) - #define ETH_MII_TXD0_PIN (GPIO_PIN_13) - #define ETH_MII_TXD0_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD1_PORT (GPIO_PORT_G) - #define ETH_MII_TXD1_PIN (GPIO_PIN_14) - #define ETH_MII_TXD1_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD2_PORT (GPIO_PORT_B) - #define ETH_MII_TXD2_PIN (GPIO_PIN_09) - #define ETH_MII_TXD2_FUNC (GPIO_FUNC_11) - - #define ETH_MII_TXD3_PORT (GPIO_PORT_B) - #define ETH_MII_TXD3_PIN (GPIO_PIN_08) - #define ETH_MII_TXD3_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RX_CLK_PORT (GPIO_PORT_A) - #define ETH_MII_RX_CLK_PIN (GPIO_PIN_01) - #define ETH_MII_RX_CLK_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RX_DV_PORT (GPIO_PORT_A) - #define ETH_MII_RX_DV_PIN (GPIO_PIN_07) - #define ETH_MII_RX_DV_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD0_PORT (GPIO_PORT_C) - #define ETH_MII_RXD0_PIN (GPIO_PIN_04) - #define ETH_MII_RXD0_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD1_PORT (GPIO_PORT_C) - #define ETH_MII_RXD1_PIN (GPIO_PIN_05) - #define ETH_MII_RXD1_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD2_PORT (GPIO_PORT_B) - #define ETH_MII_RXD2_PIN (GPIO_PIN_00) - #define ETH_MII_RXD2_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RXD3_PORT (GPIO_PORT_B) - #define ETH_MII_RXD3_PIN (GPIO_PIN_01) - #define ETH_MII_RXD3_FUNC (GPIO_FUNC_11) - - #define ETH_MII_RX_ER_PORT (GPIO_PORT_I) - #define ETH_MII_RX_ER_PIN (GPIO_PIN_10) - #define ETH_MII_RX_ER_FUNC (GPIO_FUNC_11) - - #define ETH_MII_CRS_PORT (GPIO_PORT_H) - #define ETH_MII_CRS_PIN (GPIO_PIN_02) - #define ETH_MII_CRS_FUNC (GPIO_FUNC_11) - - #define ETH_MII_COL_PORT (GPIO_PORT_H) - #define ETH_MII_COL_PIN (GPIO_PIN_03) - #define ETH_MII_COL_FUNC (GPIO_FUNC_11) - #endif +#if defined(ETH_INTERFACE_USING_RMII) +#define ETH_SMI_MDIO_PORT (GPIO_PORT_A) +#define ETH_SMI_MDIO_PIN (GPIO_PIN_02) +#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + +#define ETH_SMI_MDC_PORT (GPIO_PORT_C) +#define ETH_SMI_MDC_PIN (GPIO_PIN_01) +#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TX_EN_PORT (GPIO_PORT_G) +#define ETH_RMII_TX_EN_PIN (GPIO_PIN_11) +#define ETH_RMII_TX_EN_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TXD0_PORT (GPIO_PORT_G) +#define ETH_RMII_TXD0_PIN (GPIO_PIN_13) +#define ETH_RMII_TXD0_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_TXD1_PORT (GPIO_PORT_G) +#define ETH_RMII_TXD1_PIN (GPIO_PIN_14) +#define ETH_RMII_TXD1_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_REF_CLK_PORT (GPIO_PORT_A) +#define ETH_RMII_REF_CLK_PIN (GPIO_PIN_01) +#define ETH_RMII_REF_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_CRS_DV_PORT (GPIO_PORT_A) +#define ETH_RMII_CRS_DV_PIN (GPIO_PIN_07) +#define ETH_RMII_CRS_DV_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_RXD0_PORT (GPIO_PORT_C) +#define ETH_RMII_RXD0_PIN (GPIO_PIN_04) +#define ETH_RMII_RXD0_FUNC (GPIO_FUNC_11) + +#define ETH_RMII_RXD1_PORT (GPIO_PORT_C) +#define ETH_RMII_RXD1_PIN (GPIO_PIN_05) +#define ETH_RMII_RXD1_FUNC (GPIO_FUNC_11) +#else +#define ETH_SMI_MDIO_PORT (GPIO_PORT_A) +#define ETH_SMI_MDIO_PIN (GPIO_PIN_02) +#define ETH_SMI_MDIO_FUNC (GPIO_FUNC_11) + +#define ETH_SMI_MDC_PORT (GPIO_PORT_C) +#define ETH_SMI_MDC_PIN (GPIO_PIN_01) +#define ETH_SMI_MDC_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TX_CLK_PORT (GPIO_PORT_B) +#define ETH_MII_TX_CLK_PIN (GPIO_PIN_06) +#define ETH_MII_TX_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TX_EN_PORT (GPIO_PORT_G) +#define ETH_MII_TX_EN_PIN (GPIO_PIN_11) +#define ETH_MII_TX_EN_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD0_PORT (GPIO_PORT_G) +#define ETH_MII_TXD0_PIN (GPIO_PIN_13) +#define ETH_MII_TXD0_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD1_PORT (GPIO_PORT_G) +#define ETH_MII_TXD1_PIN (GPIO_PIN_14) +#define ETH_MII_TXD1_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD2_PORT (GPIO_PORT_B) +#define ETH_MII_TXD2_PIN (GPIO_PIN_09) +#define ETH_MII_TXD2_FUNC (GPIO_FUNC_11) + +#define ETH_MII_TXD3_PORT (GPIO_PORT_B) +#define ETH_MII_TXD3_PIN (GPIO_PIN_08) +#define ETH_MII_TXD3_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_CLK_PORT (GPIO_PORT_A) +#define ETH_MII_RX_CLK_PIN (GPIO_PIN_01) +#define ETH_MII_RX_CLK_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_DV_PORT (GPIO_PORT_A) +#define ETH_MII_RX_DV_PIN (GPIO_PIN_07) +#define ETH_MII_RX_DV_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD0_PORT (GPIO_PORT_C) +#define ETH_MII_RXD0_PIN (GPIO_PIN_04) +#define ETH_MII_RXD0_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD1_PORT (GPIO_PORT_C) +#define ETH_MII_RXD1_PIN (GPIO_PIN_05) +#define ETH_MII_RXD1_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD2_PORT (GPIO_PORT_B) +#define ETH_MII_RXD2_PIN (GPIO_PIN_00) +#define ETH_MII_RXD2_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RXD3_PORT (GPIO_PORT_B) +#define ETH_MII_RXD3_PIN (GPIO_PIN_01) +#define ETH_MII_RXD3_FUNC (GPIO_FUNC_11) + +#define ETH_MII_RX_ER_PORT (GPIO_PORT_I) +#define ETH_MII_RX_ER_PIN (GPIO_PIN_10) +#define ETH_MII_RX_ER_FUNC (GPIO_FUNC_11) + +#define ETH_MII_CRS_PORT (GPIO_PORT_H) +#define ETH_MII_CRS_PIN (GPIO_PIN_02) +#define ETH_MII_CRS_FUNC (GPIO_FUNC_11) + +#define ETH_MII_COL_PORT (GPIO_PORT_H) +#define ETH_MII_COL_PIN (GPIO_PIN_03) +#define ETH_MII_COL_FUNC (GPIO_FUNC_11) +#endif #endif /************************ NAND port **********************/ #if defined(BSP_USING_NAND) - #define NAND_CE_PORT (GPIO_PORT_C) /* PC02 - EXMC_CE0 */ - #define NAND_CE_PIN (GPIO_PIN_02) - #define NAND_CE_FUNC (GPIO_FUNC_12) - - #define NAND_RE_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ - #define NAND_RE_PIN (GPIO_PIN_11) - #define NAND_RE_FUNC (GPIO_FUNC_12) - - #define NAND_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ - #define NAND_WE_PIN (GPIO_PIN_00) - #define NAND_WE_FUNC (GPIO_FUNC_12) - - #define NAND_CLE_PORT (GPIO_PORT_I) /* PI12 - EXMC_CLE */ - #define NAND_CLE_PIN (GPIO_PIN_12) - #define NAND_CLE_FUNC (GPIO_FUNC_12) - - #define NAND_ALE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ - #define NAND_ALE_PIN (GPIO_PIN_03) - #define NAND_ALE_FUNC (GPIO_FUNC_12) - - #define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ - #define NAND_WP_PIN (GPIO_PIN_15) - #define NAND_WP_FUNC (GPIO_FUNC_12) - - #define NAND_RB_PORT (GPIO_PORT_G) /* PG06 - EXMC_RB0 */ - #define NAND_RB_PIN (GPIO_PIN_06) - #define NAND_RB_FUNC (GPIO_FUNC_12) - - #define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ - #define NAND_DATA0_PIN (GPIO_PIN_14) - #define NAND_DATA0_FUNC (GPIO_FUNC_12) - #define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ - #define NAND_DATA1_PIN (GPIO_PIN_15) - #define NAND_DATA1_FUNC (GPIO_FUNC_12) - #define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ - #define NAND_DATA2_PIN (GPIO_PIN_00) - #define NAND_DATA2_FUNC (GPIO_FUNC_12) - #define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ - #define NAND_DATA3_PIN (GPIO_PIN_01) - #define NAND_DATA3_FUNC (GPIO_FUNC_12) - #define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ - #define NAND_DATA4_PIN (GPIO_PIN_07) - #define NAND_DATA4_FUNC (GPIO_FUNC_12) - #define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ - #define NAND_DATA5_PIN (GPIO_PIN_08) - #define NAND_DATA5_FUNC (GPIO_FUNC_12) - #define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ - #define NAND_DATA6_PIN (GPIO_PIN_09) - #define NAND_DATA6_FUNC (GPIO_FUNC_12) - #define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ - #define NAND_DATA7_PIN (GPIO_PIN_10) - #define NAND_DATA7_FUNC (GPIO_FUNC_12) +#define NAND_CE_PORT (GPIO_PORT_C) /* PC02 - EXMC_CE0 */ +#define NAND_CE_PIN (GPIO_PIN_02) +#define NAND_CE_FUNC (GPIO_FUNC_12) + +#define NAND_RE_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ +#define NAND_RE_PIN (GPIO_PIN_11) +#define NAND_RE_FUNC (GPIO_FUNC_12) + +#define NAND_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ +#define NAND_WE_PIN (GPIO_PIN_00) +#define NAND_WE_FUNC (GPIO_FUNC_12) + +#define NAND_CLE_PORT (GPIO_PORT_I) /* PI12 - EXMC_CLE */ +#define NAND_CLE_PIN (GPIO_PIN_12) +#define NAND_CLE_FUNC (GPIO_FUNC_12) + +#define NAND_ALE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ +#define NAND_ALE_PIN (GPIO_PIN_03) +#define NAND_ALE_FUNC (GPIO_FUNC_12) + +#define NAND_WP_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ +#define NAND_WP_PIN (GPIO_PIN_15) +#define NAND_WP_FUNC (GPIO_FUNC_12) + +#define NAND_RB_PORT (GPIO_PORT_G) /* PG06 - EXMC_RB0 */ +#define NAND_RB_PIN (GPIO_PIN_06) +#define NAND_RB_FUNC (GPIO_FUNC_12) + +#define NAND_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ +#define NAND_DATA0_PIN (GPIO_PIN_14) +#define NAND_DATA0_FUNC (GPIO_FUNC_12) +#define NAND_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ +#define NAND_DATA1_PIN (GPIO_PIN_15) +#define NAND_DATA1_FUNC (GPIO_FUNC_12) +#define NAND_DATA2_PORT (GPIO_PORT_D) /* PD0 - EXMC_DATA2 */ +#define NAND_DATA2_PIN (GPIO_PIN_00) +#define NAND_DATA2_FUNC (GPIO_FUNC_12) +#define NAND_DATA3_PORT (GPIO_PORT_D) /* PD1 - EXMC_DATA3 */ +#define NAND_DATA3_PIN (GPIO_PIN_01) +#define NAND_DATA3_FUNC (GPIO_FUNC_12) +#define NAND_DATA4_PORT (GPIO_PORT_E) /* PE7 - EXMC_DATA4 */ +#define NAND_DATA4_PIN (GPIO_PIN_07) +#define NAND_DATA4_FUNC (GPIO_FUNC_12) +#define NAND_DATA5_PORT (GPIO_PORT_E) /* PE8 - EXMC_DATA5 */ +#define NAND_DATA5_PIN (GPIO_PIN_08) +#define NAND_DATA5_FUNC (GPIO_FUNC_12) +#define NAND_DATA6_PORT (GPIO_PORT_E) /* PE9 - EXMC_DATA6 */ +#define NAND_DATA6_PIN (GPIO_PIN_09) +#define NAND_DATA6_FUNC (GPIO_FUNC_12) +#define NAND_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ +#define NAND_DATA7_PIN (GPIO_PIN_10) +#define NAND_DATA7_FUNC (GPIO_FUNC_12) #endif /************************ SDIOC port **********************/ #if defined(BSP_USING_SDIO1) - #define SDIOC1_CK_PORT (GPIO_PORT_C) - #define SDIOC1_CK_PIN (GPIO_PIN_12) - #define SDIOC1_CK_FUNC (GPIO_FUNC_9) +#define SDIOC1_CK_PORT (GPIO_PORT_C) +#define SDIOC1_CK_PIN (GPIO_PIN_12) +#define SDIOC1_CK_FUNC (GPIO_FUNC_9) - #define SDIOC1_CMD_PORT (GPIO_PORT_D) - #define SDIOC1_CMD_PIN (GPIO_PIN_02) - #define SDIOC1_CMD_FUNC (GPIO_FUNC_9) +#define SDIOC1_CMD_PORT (GPIO_PORT_D) +#define SDIOC1_CMD_PIN (GPIO_PIN_02) +#define SDIOC1_CMD_FUNC (GPIO_FUNC_9) - #define SDIOC1_D0_PORT (GPIO_PORT_C) - #define SDIOC1_D0_PIN (GPIO_PIN_08) - #define SDIOC1_D0_FUNC (GPIO_FUNC_9) +#define SDIOC1_D0_PORT (GPIO_PORT_C) +#define SDIOC1_D0_PIN (GPIO_PIN_08) +#define SDIOC1_D0_FUNC (GPIO_FUNC_9) - #define SDIOC1_D1_PORT (GPIO_PORT_C) - #define SDIOC1_D1_PIN (GPIO_PIN_09) - #define SDIOC1_D1_FUNC (GPIO_FUNC_9) +#define SDIOC1_D1_PORT (GPIO_PORT_C) +#define SDIOC1_D1_PIN (GPIO_PIN_09) +#define SDIOC1_D1_FUNC (GPIO_FUNC_9) - #define SDIOC1_D2_PORT (GPIO_PORT_C) - #define SDIOC1_D2_PIN (GPIO_PIN_10) - #define SDIOC1_D2_FUNC (GPIO_FUNC_9) +#define SDIOC1_D2_PORT (GPIO_PORT_C) +#define SDIOC1_D2_PIN (GPIO_PIN_10) +#define SDIOC1_D2_FUNC (GPIO_FUNC_9) - #define SDIOC1_D3_PORT (GPIO_PORT_C) - #define SDIOC1_D3_PIN (GPIO_PIN_11) - #define SDIOC1_D3_FUNC (GPIO_FUNC_9) +#define SDIOC1_D3_PORT (GPIO_PORT_C) +#define SDIOC1_D3_PIN (GPIO_PIN_11) +#define SDIOC1_D3_FUNC (GPIO_FUNC_9) #endif /************************ SDRAM port **********************/ #if defined(BSP_USING_SDRAM) - #define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ - #define SDRAM_CKE_PIN (GPIO_PIN_03) - #define SDRAM_CKE_FUNC (GPIO_FUNC_12) - - #define SDRAM_CLK_PORT (GPIO_PORT_G) /* PD03 - EXMC_CLK */ - #define SDRAM_CLK_PIN (GPIO_PIN_08) - #define SDRAM_CLK_FUNC (GPIO_FUNC_12) - - #define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ - #define SDRAM_DQM0_PIN (GPIO_PIN_00) - #define SDRAM_DQM0_FUNC (GPIO_FUNC_12) - #define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ - #define SDRAM_DQM1_PIN (GPIO_PIN_01) - #define SDRAM_DQM1_FUNC (GPIO_FUNC_12) - - #define SDRAM_BA0_PORT (GPIO_PORT_D) /* PD11 - EXMC_ADD16 */ - #define SDRAM_BA0_PIN (GPIO_PIN_11) - #define SDRAM_BA0_FUNC (GPIO_FUNC_12) - #define SDRAM_BA1_PORT (GPIO_PORT_D) /* PD12 - EXMC_ADD17 */ - #define SDRAM_BA1_PIN (GPIO_PIN_12) - #define SDRAM_BA1_FUNC (GPIO_FUNC_12) - - #define SDRAM_CS_PORT (GPIO_PORT_G) /* PG09 - EXMC_CE1 */ - #define SDRAM_CS_PIN (GPIO_PIN_09) - #define SDRAM_CS_FUNC (GPIO_FUNC_12) - - #define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ - #define SDRAM_RAS_PIN (GPIO_PIN_11) - #define SDRAM_RAS_FUNC (GPIO_FUNC_12) - - #define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ - #define SDRAM_CAS_PIN (GPIO_PIN_15) - #define SDRAM_CAS_FUNC (GPIO_FUNC_12) - - #define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ - #define SDRAM_WE_PIN (GPIO_PIN_00) - #define SDRAM_WE_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ - #define SDRAM_ADD0_PIN (GPIO_PIN_00) - #define SDRAM_ADD0_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ - #define SDRAM_ADD1_PIN (GPIO_PIN_01) - #define SDRAM_ADD1_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ - #define SDRAM_ADD2_PIN (GPIO_PIN_02) - #define SDRAM_ADD2_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ - #define SDRAM_ADD3_PIN (GPIO_PIN_03) - #define SDRAM_ADD3_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ - #define SDRAM_ADD4_PIN (GPIO_PIN_04) - #define SDRAM_ADD4_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ - #define SDRAM_ADD5_PIN (GPIO_PIN_05) - #define SDRAM_ADD5_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ - #define SDRAM_ADD6_PIN (GPIO_PIN_12) - #define SDRAM_ADD6_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ - #define SDRAM_ADD7_PIN (GPIO_PIN_13) - #define SDRAM_ADD7_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ - #define SDRAM_ADD8_PIN (GPIO_PIN_14) - #define SDRAM_ADD8_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ - #define SDRAM_ADD9_PIN (GPIO_PIN_15) - #define SDRAM_ADD9_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ - #define SDRAM_ADD10_PIN (GPIO_PIN_00) - #define SDRAM_ADD10_FUNC (GPIO_FUNC_12) - - #define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ - #define SDRAM_ADD11_PIN (GPIO_PIN_01) - #define SDRAM_ADD11_FUNC (GPIO_FUNC_12) - - #define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ - #define SDRAM_DATA0_PIN (GPIO_PIN_14) - #define SDRAM_DATA0_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ - #define SDRAM_DATA1_PIN (GPIO_PIN_15) - #define SDRAM_DATA1_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ - #define SDRAM_DATA2_PIN (GPIO_PIN_00) - #define SDRAM_DATA2_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ - #define SDRAM_DATA3_PIN (GPIO_PIN_01) - #define SDRAM_DATA3_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ - #define SDRAM_DATA4_PIN (GPIO_PIN_07) - #define SDRAM_DATA4_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ - #define SDRAM_DATA5_PIN (GPIO_PIN_08) - #define SDRAM_DATA5_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ - #define SDRAM_DATA6_PIN (GPIO_PIN_09) - #define SDRAM_DATA6_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ - #define SDRAM_DATA7_PIN (GPIO_PIN_10) - #define SDRAM_DATA7_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ - #define SDRAM_DATA8_PIN (GPIO_PIN_11) - #define SDRAM_DATA8_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ - #define SDRAM_DATA9_PIN (GPIO_PIN_12) - #define SDRAM_DATA9_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ - #define SDRAM_DATA10_PIN (GPIO_PIN_13) - #define SDRAM_DATA10_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ - #define SDRAM_DATA11_PIN (GPIO_PIN_14) - #define SDRAM_DATA11_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ - #define SDRAM_DATA12_PIN (GPIO_PIN_15) - #define SDRAM_DATA12_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ - #define SDRAM_DATA13_PIN (GPIO_PIN_08) - #define SDRAM_DATA13_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ - #define SDRAM_DATA14_PIN (GPIO_PIN_09) - #define SDRAM_DATA14_FUNC (GPIO_FUNC_12) - #define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ - #define SDRAM_DATA15_PIN (GPIO_PIN_10) - #define SDRAM_DATA15_FUNC (GPIO_FUNC_12) +#define SDRAM_CKE_PORT (GPIO_PORT_C) /* PC03 - EXMC_ALE */ +#define SDRAM_CKE_PIN (GPIO_PIN_03) +#define SDRAM_CKE_FUNC (GPIO_FUNC_12) + +#define SDRAM_CLK_PORT (GPIO_PORT_G) /* PD03 - EXMC_CLK */ +#define SDRAM_CLK_PIN (GPIO_PIN_08) +#define SDRAM_CLK_FUNC (GPIO_FUNC_12) + +#define SDRAM_DQM0_PORT (GPIO_PORT_E) /* PE00 - EXMC_CE4 */ +#define SDRAM_DQM0_PIN (GPIO_PIN_00) +#define SDRAM_DQM0_FUNC (GPIO_FUNC_12) +#define SDRAM_DQM1_PORT (GPIO_PORT_E) /* PE01 - EXMC_CE5 */ +#define SDRAM_DQM1_PIN (GPIO_PIN_01) +#define SDRAM_DQM1_FUNC (GPIO_FUNC_12) + +#define SDRAM_BA0_PORT (GPIO_PORT_D) /* PD11 - EXMC_ADD16 */ +#define SDRAM_BA0_PIN (GPIO_PIN_11) +#define SDRAM_BA0_FUNC (GPIO_FUNC_12) +#define SDRAM_BA1_PORT (GPIO_PORT_D) /* PD12 - EXMC_ADD17 */ +#define SDRAM_BA1_PIN (GPIO_PIN_12) +#define SDRAM_BA1_FUNC (GPIO_FUNC_12) + +#define SDRAM_CS_PORT (GPIO_PORT_G) /* PG09 - EXMC_CE1 */ +#define SDRAM_CS_PIN (GPIO_PIN_09) +#define SDRAM_CS_FUNC (GPIO_FUNC_12) + +#define SDRAM_RAS_PORT (GPIO_PORT_F) /* PF11 - EXMC_OE */ +#define SDRAM_RAS_PIN (GPIO_PIN_11) +#define SDRAM_RAS_FUNC (GPIO_FUNC_12) + +#define SDRAM_CAS_PORT (GPIO_PORT_G) /* PG15 - EXMC_BAA */ +#define SDRAM_CAS_PIN (GPIO_PIN_15) +#define SDRAM_CAS_FUNC (GPIO_FUNC_12) + +#define SDRAM_WE_PORT (GPIO_PORT_C) /* PC00 - EXMC_WE */ +#define SDRAM_WE_PIN (GPIO_PIN_00) +#define SDRAM_WE_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD0_PORT (GPIO_PORT_F) /* PF00 - EXMC_ADD0 */ +#define SDRAM_ADD0_PIN (GPIO_PIN_00) +#define SDRAM_ADD0_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD1_PORT (GPIO_PORT_F) /* PF01 - EXMC_ADD1 */ +#define SDRAM_ADD1_PIN (GPIO_PIN_01) +#define SDRAM_ADD1_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD2_PORT (GPIO_PORT_F) /* PF02 - EXMC_ADD2 */ +#define SDRAM_ADD2_PIN (GPIO_PIN_02) +#define SDRAM_ADD2_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD3_PORT (GPIO_PORT_F) /* PF03 - EXMC_ADD3 */ +#define SDRAM_ADD3_PIN (GPIO_PIN_03) +#define SDRAM_ADD3_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD4_PORT (GPIO_PORT_F) /* PF04 - EXMC_ADD4 */ +#define SDRAM_ADD4_PIN (GPIO_PIN_04) +#define SDRAM_ADD4_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD5_PORT (GPIO_PORT_F) /* PF05 - EXMC_ADD5 */ +#define SDRAM_ADD5_PIN (GPIO_PIN_05) +#define SDRAM_ADD5_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD6_PORT (GPIO_PORT_F) /* PF12 - EXMC_ADD6 */ +#define SDRAM_ADD6_PIN (GPIO_PIN_12) +#define SDRAM_ADD6_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD7_PORT (GPIO_PORT_F) /* PF13 - EXMC_ADD7 */ +#define SDRAM_ADD7_PIN (GPIO_PIN_13) +#define SDRAM_ADD7_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD8_PORT (GPIO_PORT_F) /* PF14 - EXMC_ADD8 */ +#define SDRAM_ADD8_PIN (GPIO_PIN_14) +#define SDRAM_ADD8_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD9_PORT (GPIO_PORT_F) /* PF15 - EXMC_ADD9 */ +#define SDRAM_ADD9_PIN (GPIO_PIN_15) +#define SDRAM_ADD9_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD10_PORT (GPIO_PORT_G) /* PG00 - EXMC_ADD10 */ +#define SDRAM_ADD10_PIN (GPIO_PIN_00) +#define SDRAM_ADD10_FUNC (GPIO_FUNC_12) + +#define SDRAM_ADD11_PORT (GPIO_PORT_G) /* PG01 - EXMC_ADD11 */ +#define SDRAM_ADD11_PIN (GPIO_PIN_01) +#define SDRAM_ADD11_FUNC (GPIO_FUNC_12) + +#define SDRAM_DATA0_PORT (GPIO_PORT_D) /* PD14 - EXMC_DATA0 */ +#define SDRAM_DATA0_PIN (GPIO_PIN_14) +#define SDRAM_DATA0_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA1_PORT (GPIO_PORT_D) /* PD15 - EXMC_DATA1 */ +#define SDRAM_DATA1_PIN (GPIO_PIN_15) +#define SDRAM_DATA1_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA2_PORT (GPIO_PORT_D) /* PD00 - EXMC_DATA2 */ +#define SDRAM_DATA2_PIN (GPIO_PIN_00) +#define SDRAM_DATA2_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA3_PORT (GPIO_PORT_D) /* PD01 - EXMC_DATA3 */ +#define SDRAM_DATA3_PIN (GPIO_PIN_01) +#define SDRAM_DATA3_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA4_PORT (GPIO_PORT_E) /* PE07 - EXMC_DATA4 */ +#define SDRAM_DATA4_PIN (GPIO_PIN_07) +#define SDRAM_DATA4_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA5_PORT (GPIO_PORT_E) /* PE08 - EXMC_DATA5 */ +#define SDRAM_DATA5_PIN (GPIO_PIN_08) +#define SDRAM_DATA5_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA6_PORT (GPIO_PORT_E) /* PE09 - EXMC_DATA6 */ +#define SDRAM_DATA6_PIN (GPIO_PIN_09) +#define SDRAM_DATA6_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA7_PORT (GPIO_PORT_E) /* PE10 - EXMC_DATA7 */ +#define SDRAM_DATA7_PIN (GPIO_PIN_10) +#define SDRAM_DATA7_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA8_PORT (GPIO_PORT_E) /* PE11 - EXMC_DATA8 */ +#define SDRAM_DATA8_PIN (GPIO_PIN_11) +#define SDRAM_DATA8_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA9_PORT (GPIO_PORT_E) /* PE12 - EXMC_DATA9 */ +#define SDRAM_DATA9_PIN (GPIO_PIN_12) +#define SDRAM_DATA9_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA10_PORT (GPIO_PORT_E) /* PE13 - EXMC_DATA10 */ +#define SDRAM_DATA10_PIN (GPIO_PIN_13) +#define SDRAM_DATA10_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA11_PORT (GPIO_PORT_E) /* PE14 - EXMC_DATA11 */ +#define SDRAM_DATA11_PIN (GPIO_PIN_14) +#define SDRAM_DATA11_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA12_PORT (GPIO_PORT_E) /* PE15 - EXMC_DATA12 */ +#define SDRAM_DATA12_PIN (GPIO_PIN_15) +#define SDRAM_DATA12_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA13_PORT (GPIO_PORT_D) /* PD08 - EXMC_DATA13 */ +#define SDRAM_DATA13_PIN (GPIO_PIN_08) +#define SDRAM_DATA13_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA14_PORT (GPIO_PORT_D) /* PD09 - EXMC_DATA14 */ +#define SDRAM_DATA14_PIN (GPIO_PIN_09) +#define SDRAM_DATA14_FUNC (GPIO_FUNC_12) +#define SDRAM_DATA15_PORT (GPIO_PORT_D) /* PD10 - EXMC_DATA15 */ +#define SDRAM_DATA15_PIN (GPIO_PIN_10) +#define SDRAM_DATA15_FUNC (GPIO_FUNC_12) #endif /************************ RTC/PM *****************************/ #if defined(BSP_USING_RTC) || defined(RT_USING_PM) - #if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) - #define XTAL32_PORT (GPIO_PORT_C) - #define XTAL32_IN_PIN (GPIO_PIN_15) - #define XTAL32_OUT_PIN (GPIO_PIN_14) - #endif +#if defined(BSP_RTC_USING_XTAL32) || defined(RT_USING_PM) +#define XTAL32_PORT (GPIO_PORT_C) +#define XTAL32_IN_PIN (GPIO_PIN_15) +#define XTAL32_OUT_PIN (GPIO_PIN_14) +#endif #endif #if defined(RT_USING_PWM) /*********** PWM_TMRA configure *********/ - #if defined(BSP_USING_PWM_TMRA_1) - #if defined(BSP_USING_PWM_TMRA_1_CH1) - #define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) - #define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH2) - #define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) - #define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH3) - #define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) - #define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) - #endif - #if defined(BSP_USING_PWM_TMRA_1_CH4) - #define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) - #define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) - #define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) - #endif - #endif +#if defined(BSP_USING_PWM_TMRA_1) +#if defined(BSP_USING_PWM_TMRA_1_CH1) +#define PWM_TMRA_1_CH1_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH1_PIN (GPIO_PIN_08) +#define PWM_TMRA_1_CH1_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH2) +#define PWM_TMRA_1_CH2_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH2_PIN (GPIO_PIN_09) +#define PWM_TMRA_1_CH2_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH3) +#define PWM_TMRA_1_CH3_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH3_PIN (GPIO_PIN_10) +#define PWM_TMRA_1_CH3_PIN_FUNC (GPIO_FUNC_4) +#endif +#if defined(BSP_USING_PWM_TMRA_1_CH4) +#define PWM_TMRA_1_CH4_PORT (GPIO_PORT_A) +#define PWM_TMRA_1_CH4_PIN (GPIO_PIN_11) +#define PWM_TMRA_1_CH4_PIN_FUNC (GPIO_FUNC_4) +#endif +#endif /*********** PWM_TMR4 configure *********/ - #if defined(BSP_USING_PWM_TMR4_1) - #if defined(BSP_USING_PWM_TMR4_1_OUH) - #define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) - #define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OUL) - #define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) - #define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVH) - #define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) - #define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OVL) - #define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) - #define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWH) - #define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) - #define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) - #endif - #if defined(BSP_USING_PWM_TMR4_1_OWL) - #define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) - #define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) - #define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) - #endif - #endif +#if defined(BSP_USING_PWM_TMR4_1) +#if defined(BSP_USING_PWM_TMR4_1_OUH) +#define PWM_TMR4_1_OUH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUH_PIN (GPIO_PIN_09) +#define PWM_TMR4_1_OUH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OUL) +#define PWM_TMR4_1_OUL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OUL_PIN (GPIO_PIN_08) +#define PWM_TMR4_1_OUL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVH) +#define PWM_TMR4_1_OVH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVH_PIN (GPIO_PIN_11) +#define PWM_TMR4_1_OVH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OVL) +#define PWM_TMR4_1_OVL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OVL_PIN (GPIO_PIN_10) +#define PWM_TMR4_1_OVL_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWH) +#define PWM_TMR4_1_OWH_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWH_PIN (GPIO_PIN_13) +#define PWM_TMR4_1_OWH_PIN_FUNC (GPIO_FUNC_2) +#endif +#if defined(BSP_USING_PWM_TMR4_1_OWL) +#define PWM_TMR4_1_OWL_PORT (GPIO_PORT_E) +#define PWM_TMR4_1_OWL_PIN (GPIO_PIN_12) +#define PWM_TMR4_1_OWL_PIN_FUNC (GPIO_FUNC_2) +#endif +#endif /*********** PWM_TMR6 configure *********/ - #if defined(BSP_USING_PWM_TMR6_1) - #if defined(BSP_USING_PWM_TMR6_1_A) - #define PWM_TMR6_1_A_PORT (GPIO_PORT_F) - #define PWM_TMR6_1_A_PIN (GPIO_PIN_13) - #define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #endif - #if defined(BSP_USING_PWM_TMR6_1_B) - #define PWM_TMR6_1_B_PORT (GPIO_PORT_F) - #define PWM_TMR6_1_B_PIN (GPIO_PIN_14) - #define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif - #endif +#if defined(BSP_USING_PWM_TMR6_1) +#if defined(BSP_USING_PWM_TMR6_1_A) +#define PWM_TMR6_1_A_PORT (GPIO_PORT_F) +#define PWM_TMR6_1_A_PIN (GPIO_PIN_13) +#define PWM_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#endif +#if defined(BSP_USING_PWM_TMR6_1_B) +#define PWM_TMR6_1_B_PORT (GPIO_PORT_F) +#define PWM_TMR6_1_B_PIN (GPIO_PIN_14) +#define PWM_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif +#endif #endif #if defined(BSP_USING_USBD) || defined(BSP_USING_USBH) - #if defined(BSP_USING_USBFS) +#if defined(BSP_USING_USBFS) /* USBFS Core*/ - #define USBF_DP_PORT (GPIO_PORT_A) - #define USBF_DP_PIN (GPIO_PIN_12) - #define USBF_DP_FUNC (GPIO_FUNC_10) - #define USBF_DM_PORT (GPIO_PORT_A) - #define USBF_DM_PIN (GPIO_PIN_11) - #define USBF_DM_FUNC (GPIO_FUNC_10) - #define USBF_VBUS_PORT (GPIO_PORT_A) - #define USBF_VBUS_PIN (GPIO_PIN_09) - #define USBF_VBUS_FUNC (GPIO_FUNC_10) - #define USBF_DRVVBUS_PORT (GPIO_PORT_C) - #define USBF_DRVVBUS_PIN (GPIO_PIN_09) - #define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) - #elif defined(BSP_USING_USBHS) +#define USBF_DP_PORT (GPIO_PORT_A) +#define USBF_DP_PIN (GPIO_PIN_12) +#define USBF_DP_FUNC (GPIO_FUNC_10) +#define USBF_DM_PORT (GPIO_PORT_A) +#define USBF_DM_PIN (GPIO_PIN_11) +#define USBF_DM_FUNC (GPIO_FUNC_10) +#define USBF_VBUS_PORT (GPIO_PORT_A) +#define USBF_VBUS_PIN (GPIO_PIN_09) +#define USBF_VBUS_FUNC (GPIO_FUNC_10) +#define USBF_DRVVBUS_PORT (GPIO_PORT_C) +#define USBF_DRVVBUS_PIN (GPIO_PIN_09) +#define USBF_DRVVBUS_FUNC (GPIO_FUNC_10) +#elif defined(BSP_USING_USBHS) /* USBHS Core*/ - #if defined(BSP_USING_USBHS_PHY_EMBED) - #define USBH_DP_PORT (GPIO_PORT_B) - #define USBH_DP_PIN (GPIO_PIN_15) - #define USBH_DP_FUNC (GPIO_FUNC_10) - #define USBH_DM_PORT (GPIO_PORT_B) - #define USBH_DM_PIN (GPIO_PIN_14) - #define USBH_DM_FUNC (GPIO_FUNC_10) - #define USBH_VBUS_PORT (GPIO_PORT_B) - #define USBH_VBUS_PIN (GPIO_PIN_13) - #define USBH_VBUS_FUNC (GPIO_FUNC_12) - #define USBH_DRVVBUS_PORT (GPIO_PORT_B) - #define USBH_DRVVBUS_PIN (GPIO_PIN_11) - #define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) - #else +#if defined(BSP_USING_USBHS_PHY_EMBED) +#define USBH_DP_PORT (GPIO_PORT_B) +#define USBH_DP_PIN (GPIO_PIN_15) +#define USBH_DP_FUNC (GPIO_FUNC_10) +#define USBH_DM_PORT (GPIO_PORT_B) +#define USBH_DM_PIN (GPIO_PIN_14) +#define USBH_DM_FUNC (GPIO_FUNC_10) +#define USBH_VBUS_PORT (GPIO_PORT_B) +#define USBH_VBUS_PIN (GPIO_PIN_13) +#define USBH_VBUS_FUNC (GPIO_FUNC_12) +#define USBH_DRVVBUS_PORT (GPIO_PORT_B) +#define USBH_DRVVBUS_PIN (GPIO_PIN_11) +#define USBH_DRVVBUS_FUNC (GPIO_FUNC_10) +#else /* USBHS Core, external PHY */ - #define USBH_ULPI_CLK_PORT (GPIO_PORT_E) - #define USBH_ULPI_CLK_PIN (GPIO_PIN_12) - #define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_DIR_PORT (GPIO_PORT_C) - #define USBH_ULPI_DIR_PIN (GPIO_PIN_02) - #define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_NXT_PORT (GPIO_PORT_C) - #define USBH_ULPI_NXT_PIN (GPIO_PIN_03) - #define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_STP_PORT (GPIO_PORT_C) - #define USBH_ULPI_STP_PIN (GPIO_PIN_00) - #define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D0_PORT (GPIO_PORT_E) - #define USBH_ULPI_D0_PIN (GPIO_PIN_13) - #define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D1_PORT (GPIO_PORT_E) - #define USBH_ULPI_D1_PIN (GPIO_PIN_14) - #define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D2_PORT (GPIO_PORT_E) - #define USBH_ULPI_D2_PIN (GPIO_PIN_15) - #define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D3_PORT (GPIO_PORT_B) - #define USBH_ULPI_D3_PIN (GPIO_PIN_10) - #define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D4_PORT (GPIO_PORT_B) - #define USBH_ULPI_D4_PIN (GPIO_PIN_11) - #define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D5_PORT (GPIO_PORT_B) - #define USBH_ULPI_D5_PIN (GPIO_PIN_12) - #define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D6_PORT (GPIO_PORT_B) - #define USBH_ULPI_D6_PIN (GPIO_PIN_13) - #define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) - #define USBH_ULPI_D7_PORT (GPIO_PORT_E) - #define USBH_ULPI_D7_PIN (GPIO_PIN_11) - #define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_CLK_PORT (GPIO_PORT_E) +#define USBH_ULPI_CLK_PIN (GPIO_PIN_12) +#define USBH_ULPI_CLK_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_DIR_PORT (GPIO_PORT_C) +#define USBH_ULPI_DIR_PIN (GPIO_PIN_02) +#define USBH_ULPI_DIR_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_NXT_PORT (GPIO_PORT_C) +#define USBH_ULPI_NXT_PIN (GPIO_PIN_03) +#define USBH_ULPI_NXT_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_STP_PORT (GPIO_PORT_C) +#define USBH_ULPI_STP_PIN (GPIO_PIN_00) +#define USBH_ULPI_STP_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D0_PORT (GPIO_PORT_E) +#define USBH_ULPI_D0_PIN (GPIO_PIN_13) +#define USBH_ULPI_D0_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D1_PORT (GPIO_PORT_E) +#define USBH_ULPI_D1_PIN (GPIO_PIN_14) +#define USBH_ULPI_D1_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D2_PORT (GPIO_PORT_E) +#define USBH_ULPI_D2_PIN (GPIO_PIN_15) +#define USBH_ULPI_D2_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D3_PORT (GPIO_PORT_B) +#define USBH_ULPI_D3_PIN (GPIO_PIN_10) +#define USBH_ULPI_D3_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D4_PORT (GPIO_PORT_B) +#define USBH_ULPI_D4_PIN (GPIO_PIN_11) +#define USBH_ULPI_D4_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D5_PORT (GPIO_PORT_B) +#define USBH_ULPI_D5_PIN (GPIO_PIN_12) +#define USBH_ULPI_D5_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D6_PORT (GPIO_PORT_B) +#define USBH_ULPI_D6_PIN (GPIO_PIN_13) +#define USBH_ULPI_D6_FUNC (GPIO_FUNC_10) +#define USBH_ULPI_D7_PORT (GPIO_PORT_E) +#define USBH_ULPI_D7_PIN (GPIO_PIN_11) +#define USBH_ULPI_D7_FUNC (GPIO_FUNC_10) /* 3300 reset */ - #define USB_3300_RESET_PORT (EIO_PORT1) - #define USB_3300_RESET_PIN (EIO_USB3300_RST) - #endif - #endif +#define USB_3300_RESET_PORT (EIO_PORT1) +#define USB_3300_RESET_PIN (EIO_USB3300_RST) +#endif +#endif #endif #if defined(BSP_USING_QSPI) - #ifndef BSP_QSPI_USING_SOFT_CS +#ifndef BSP_QSPI_USING_SOFT_CS /* QSSN */ - #define QSPI_FLASH_CS_PORT (GPIO_PORT_C) - #define QSPI_FLASH_CS_PIN (GPIO_PIN_07) - #define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) - #endif +#define QSPI_FLASH_CS_PORT (GPIO_PORT_C) +#define QSPI_FLASH_CS_PIN (GPIO_PIN_07) +#define QSPI_FLASH_CS_FUNC (GPIO_FUNC_18) +#endif /* QSCK */ - #define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) - #define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) - #define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_SCK_PORT (GPIO_PORT_C) +#define QSPI_FLASH_SCK_PIN (GPIO_PIN_06) +#define QSPI_FLASH_SCK_FUNC (GPIO_FUNC_18) /* QSIO0 */ - #define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) - #define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO0_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO0_PIN (GPIO_PIN_13) +#define QSPI_FLASH_IO0_FUNC (GPIO_FUNC_18) /* QSIO1 */ - #define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) - #define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO1_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO1_PIN (GPIO_PIN_12) +#define QSPI_FLASH_IO1_FUNC (GPIO_FUNC_18) /* QSIO2 */ - #define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) - #define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO2_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO2_PIN (GPIO_PIN_10) +#define QSPI_FLASH_IO2_FUNC (GPIO_FUNC_18) /* QSIO3 */ - #define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) - #define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) - #define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) +#define QSPI_FLASH_IO3_PORT (GPIO_PORT_B) +#define QSPI_FLASH_IO3_PIN (GPIO_PIN_02) +#define QSPI_FLASH_IO3_FUNC (GPIO_FUNC_18) #endif /*********** TMRA_PULSE_ENCODER configure *********/ #if defined(RT_USING_PULSE_ENCODER) - #if defined(BSP_USING_TMRA_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) - #define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) - #define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) - #define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) - #define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) - #define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) - #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ - #endif /* BSP_USING_TMRA_PULSE_ENCODER */ - - #if defined(BSP_USING_TMR6_PULSE_ENCODER) - #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) - #define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) - #define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) - #define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) - #define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) - #define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) - #define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) - #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ - #endif /* BSP_USING_TMR6_PULSE_ENCODER */ +#if defined(BSP_USING_TMRA_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMRA_1) +#define PULSE_ENCODER_TMRA_1_A_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_A_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMRA_1_A_PIN_FUNC (GPIO_FUNC_4) +#define PULSE_ENCODER_TMRA_1_B_PORT (GPIO_PORT_A) +#define PULSE_ENCODER_TMRA_1_B_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMRA_1_B_PIN_FUNC (GPIO_FUNC_4) +#endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ +#endif /* BSP_USING_TMRA_PULSE_ENCODER */ + +#if defined(BSP_USING_TMR6_PULSE_ENCODER) +#if defined(BSP_USING_PULSE_ENCODER_TMR6_1) +#define PULSE_ENCODER_TMR6_1_A_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_A_PIN (GPIO_PIN_09) +#define PULSE_ENCODER_TMR6_1_A_PIN_FUNC (GPIO_FUNC_3) +#define PULSE_ENCODER_TMR6_1_B_PORT (GPIO_PORT_B) +#define PULSE_ENCODER_TMR6_1_B_PIN (GPIO_PIN_08) +#define PULSE_ENCODER_TMR6_1_B_PIN_FUNC (GPIO_FUNC_3) +#endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ +#endif /* BSP_USING_TMR6_PULSE_ENCODER */ #endif /* RT_USING_PULSE_ENCODER */ #endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/adc_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/adc_config.h index 9374d2e9ab4..12af5fa334f 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/adc_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/adc_config.h @@ -20,69 +20,69 @@ extern "C" { #ifdef BSP_USING_ADC1 #ifndef ADC1_INIT_PARAMS -#define ADC1_INIT_PARAMS \ - { \ - .name = "adc1", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_MAX, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC1_INIT_PARAMS \ + { \ + .name = "adc1", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC1_INIT_PARAMS */ #endif /* BSP_USING_ADC1 */ #ifdef BSP_USING_ADC2 #ifndef ADC2_INIT_PARAMS -#define ADC2_INIT_PARAMS \ - { \ - .name = "adc2", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_MAX, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC2_INIT_PARAMS \ + { \ + .name = "adc2", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC2_INIT_PARAMS */ #endif /* BSP_USING_ADC2 */ #ifdef BSP_USING_ADC3 #ifndef ADC3_INIT_PARAMS -#define ADC3_INIT_PARAMS \ - { \ - .name = "adc3", \ - .vref = 3300, \ - .resolution = ADC_RESOLUTION_12BIT, \ - .data_align = ADC_DATAALIGN_RIGHT, \ - .eoc_poll_time_max = 100, \ - .hard_trig_enable = RT_FALSE, \ - .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ - .internal_trig0_comtrg0_enable = RT_FALSE, \ - .internal_trig0_comtrg1_enable = RT_FALSE, \ - .internal_trig0_sel = EVT_SRC_MAX, \ - .internal_trig1_comtrg0_enable = RT_FALSE, \ - .internal_trig1_comtrg1_enable = RT_FALSE, \ - .internal_trig1_sel = EVT_SRC_MAX, \ - .continue_conv_mode_enable = RT_FALSE, \ - .data_reg_auto_clear = RT_TRUE, \ +#define ADC3_INIT_PARAMS \ + { \ + .name = "adc3", \ + .vref = 3300, \ + .resolution = ADC_RESOLUTION_12BIT, \ + .data_align = ADC_DATAALIGN_RIGHT, \ + .eoc_poll_time_max = 100, \ + .hard_trig_enable = RT_FALSE, \ + .hard_trig_src = ADC_HARDTRIG_ADTRG_PIN, \ + .internal_trig0_comtrg0_enable = RT_FALSE, \ + .internal_trig0_comtrg1_enable = RT_FALSE, \ + .internal_trig0_sel = EVT_SRC_MAX, \ + .internal_trig1_comtrg0_enable = RT_FALSE, \ + .internal_trig1_comtrg1_enable = RT_FALSE, \ + .internal_trig1_sel = EVT_SRC_MAX, \ + .continue_conv_mode_enable = RT_FALSE, \ + .data_reg_auto_clear = RT_TRUE, \ } #endif /* ADC3_INIT_PARAMS */ #endif /* BSP_USING_ADC3 */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/can_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/can_config.h index 81ab895cfb3..0557210653b 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/can_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/can_config.h @@ -19,31 +19,31 @@ extern "C" { #endif #ifdef BSP_USING_CAN1 -#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN1_CLOCK_SEL (CAN_CLOCK_SRC_40M) #ifdef RT_CAN_USING_CANFD -#define CAN1_CANFD_MODE (CAN_FD_MD_ISO) +#define CAN1_CANFD_MODE (CAN_FD_MD_ISO) #endif -#define CAN1_NAME ("can1") +#define CAN1_NAME ("can1") #ifndef CAN1_INIT_PARAMS -#define CAN1_INIT_PARAMS \ - { \ - .name = CAN1_NAME, \ - .single_trans_mode = RT_FALSE \ +#define CAN1_INIT_PARAMS \ + { \ + .name = CAN1_NAME, \ + .single_trans_mode = RT_FALSE \ } #endif /* CAN1_INIT_PARAMS */ #endif /* BSP_USING_CAN1 */ #ifdef BSP_USING_CAN2 -#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) +#define CAN2_CLOCK_SEL (CAN_CLOCK_SRC_40M) #ifdef RT_CAN_USING_CANFD -#define CAN2_CANFD_MODE (CAN_FD_MD_ISO) +#define CAN2_CANFD_MODE (CAN_FD_MD_ISO) #endif -#define CAN2_NAME ("can2") +#define CAN2_NAME ("can2") #ifndef CAN2_INIT_PARAMS -#define CAN2_INIT_PARAMS \ - { \ - .name = CAN2_NAME, \ - .single_trans_mode = RT_FALSE \ +#define CAN2_INIT_PARAMS \ + { \ + .name = CAN2_NAME, \ + .single_trans_mode = RT_FALSE \ } #endif /* CAN2_INIT_PARAMS */ #endif /* BSP_USING_CAN2 */ @@ -57,76 +57,76 @@ extern "C" { The following bit time configures are based on CAN Clock 40M */ -#define CAN_BIT_TIME_CONFIG_1M_BAUD \ - { \ - .u32Prescaler = 2, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_1M_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_800K_BAUD \ - { \ - .u32Prescaler = 2, \ - .u32TimeSeg1 = 20, \ - .u32TimeSeg2 = 5, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_800K_BAUD \ + { \ + .u32Prescaler = 2, \ + .u32TimeSeg1 = 20, \ + .u32TimeSeg2 = 5, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_500K_BAUD \ - { \ - .u32Prescaler = 4, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_500K_BAUD \ + { \ + .u32Prescaler = 4, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_250K_BAUD \ - { \ - .u32Prescaler = 8, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_250K_BAUD \ + { \ + .u32Prescaler = 8, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_125K_BAUD \ - { \ - .u32Prescaler = 16, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_125K_BAUD \ + { \ + .u32Prescaler = 16, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_100K_BAUD \ - { \ - .u32Prescaler = 20, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_100K_BAUD \ + { \ + .u32Prescaler = 20, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_50K_BAUD \ - { \ - .u32Prescaler = 40, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_50K_BAUD \ + { \ + .u32Prescaler = 40, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_20K_BAUD \ - { \ - .u32Prescaler = 100, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_20K_BAUD \ + { \ + .u32Prescaler = 100, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } -#define CAN_BIT_TIME_CONFIG_10K_BAUD \ - { \ - .u32Prescaler = 200, \ - .u32TimeSeg1 = 16, \ - .u32TimeSeg2 = 4, \ - .u32SJW = 4 \ +#define CAN_BIT_TIME_CONFIG_10K_BAUD \ + { \ + .u32Prescaler = 200, \ + .u32TimeSeg1 = 16, \ + .u32TimeSeg2 = 4, \ + .u32SJW = 4 \ } #ifdef __cplusplus diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dac_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dac_config.h index f697eba881d..1201181e674 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dac_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dac_config.h @@ -19,18 +19,18 @@ extern "C" { #ifdef BSP_USING_DAC1 #ifndef DAC1_INIT_PARAMS -#define DAC1_INIT_PARAMS \ - { \ - .name = "dac1", \ +#define DAC1_INIT_PARAMS \ + { \ + .name = "dac1", \ } #endif /* DAC1_INIT_PARAMS */ #endif /* BSP_USING_DAC1 */ #ifdef BSP_USING_DAC2 #ifndef DAC2_INIT_PARAMS -#define DAC2_INIT_PARAMS \ - { \ - .name = "dac2", \ +#define DAC2_INIT_PARAMS \ + { \ + .name = "dac2", \ } #endif /* DAC2_INIT_PARAMS */ #endif /* BSP_USING_DAC2 */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dma_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dma_config.h index a6249a0bd5c..995ab98c7ef 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dma_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/dma_config.h @@ -20,371 +20,371 @@ extern "C" { /* DMA1 ch0 */ #if defined(BSP_SPI1_RX_USING_DMA) && !defined(SPI1_RX_DMA_INSTANCE) -#define SPI1_RX_DMA_INSTANCE CM_DMA1 -#define SPI1_RX_DMA_CHANNEL DMA_CH0 -#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SPI1_RX_DMA_INSTANCE CM_DMA1 +#define SPI1_RX_DMA_CHANNEL DMA_CH0 +#define SPI1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SPI1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SPI1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SPI1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SPI1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_USING_SDIO1) && !defined(SDIO1_RX_DMA_INSTANCE) -#define SDIO1_RX_DMA_INSTANCE CM_DMA1 -#define SDIO1_RX_DMA_CHANNEL DMA_CH0 -#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 -#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define SDIO1_RX_DMA_INSTANCE CM_DMA1 +#define SDIO1_RX_DMA_CHANNEL DMA_CH0 +#define SDIO1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_RX_DMA_TRIG_SELECT AOS_DMA1_0 +#define SDIO1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define SDIO1_RX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define SDIO1_RX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define SDIO1_RX_DMA_INT_SRC INT_SRC_DMA1_TC0 #elif defined(BSP_I2C1_TX_USING_DMA) && !defined(I2C1_TX_DMA_INSTANCE) -#define I2C1_TX_DMA_INSTANCE CM_DMA1 -#define I2C1_TX_DMA_CHANNEL DMA_CH0 -#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 -#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM -#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO -#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 +#define I2C1_TX_DMA_INSTANCE CM_DMA1 +#define I2C1_TX_DMA_CHANNEL DMA_CH0 +#define I2C1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_TX_DMA_TRIG_SELECT AOS_DMA1_0 +#define I2C1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C1_TX_DMA_IRQn BSP_DMA1_CH0_IRQ_NUM +#define I2C1_TX_DMA_INT_PRIO BSP_DMA1_CH0_IRQ_PRIO +#define I2C1_TX_DMA_INT_SRC INT_SRC_DMA1_TC0 #endif /* DMA1 ch1 */ #if defined(BSP_SPI1_TX_USING_DMA) && !defined(SPI1_TX_DMA_INSTANCE) -#define SPI1_TX_DMA_INSTANCE CM_DMA1 -#define SPI1_TX_DMA_CHANNEL DMA_CH1 -#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SPI1_TX_DMA_INSTANCE CM_DMA1 +#define SPI1_TX_DMA_CHANNEL DMA_CH1 +#define SPI1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SPI1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SPI1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SPI1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SPI1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_USING_SDIO1) && !defined(SDIO1_TX_DMA_INSTANCE) -#define SDIO1_TX_DMA_INSTANCE CM_DMA1 -#define SDIO1_TX_DMA_CHANNEL DMA_CH1 -#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 -#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define SDIO1_TX_DMA_INSTANCE CM_DMA1 +#define SDIO1_TX_DMA_CHANNEL DMA_CH1 +#define SDIO1_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO1_TX_DMA_TRIG_SELECT AOS_DMA1_1 +#define SDIO1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define SDIO1_TX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define SDIO1_TX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define SDIO1_TX_DMA_INT_SRC INT_SRC_DMA1_TC1 #elif defined(BSP_I2C1_RX_USING_DMA) && !defined(I2C1_RX_DMA_INSTANCE) -#define I2C1_RX_DMA_INSTANCE CM_DMA1 -#define I2C1_RX_DMA_CHANNEL DMA_CH1 -#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 -#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM -#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO -#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 +#define I2C1_RX_DMA_INSTANCE CM_DMA1 +#define I2C1_RX_DMA_CHANNEL DMA_CH1 +#define I2C1_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C1_RX_DMA_TRIG_SELECT AOS_DMA1_1 +#define I2C1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C1_RX_DMA_IRQn BSP_DMA1_CH1_IRQ_NUM +#define I2C1_RX_DMA_INT_PRIO BSP_DMA1_CH1_IRQ_PRIO +#define I2C1_RX_DMA_INT_SRC INT_SRC_DMA1_TC1 #endif /* DMA1 ch2 */ #if defined(BSP_SPI2_RX_USING_DMA) && !defined(SPI2_RX_DMA_INSTANCE) -#define SPI2_RX_DMA_INSTANCE CM_DMA1 -#define SPI2_RX_DMA_CHANNEL DMA_CH2 -#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define SPI2_RX_DMA_INSTANCE CM_DMA1 +#define SPI2_RX_DMA_CHANNEL DMA_CH2 +#define SPI2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SPI2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SPI2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SPI2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SPI2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_USING_SDIO2) && !defined(SDIO2_RX_DMA_INSTANCE) -#define SDIO2_RX_DMA_INSTANCE CM_DMA1 -#define SDIO2_RX_DMA_CHANNEL DMA_CH2 -#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 -#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define SDIO2_RX_DMA_INSTANCE CM_DMA1 +#define SDIO2_RX_DMA_CHANNEL DMA_CH2 +#define SDIO2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_RX_DMA_TRIG_SELECT AOS_DMA1_2 +#define SDIO2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define SDIO2_RX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define SDIO2_RX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define SDIO2_RX_DMA_INT_SRC INT_SRC_DMA1_TC2 #elif defined(BSP_I2C2_TX_USING_DMA) && !defined(I2C2_TX_DMA_INSTANCE) -#define I2C2_TX_DMA_INSTANCE CM_DMA1 -#define I2C2_TX_DMA_CHANNEL DMA_CH2 -#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 -#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM -#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO -#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 +#define I2C2_TX_DMA_INSTANCE CM_DMA1 +#define I2C2_TX_DMA_CHANNEL DMA_CH2 +#define I2C2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_TX_DMA_TRIG_SELECT AOS_DMA1_2 +#define I2C2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C2_TX_DMA_IRQn BSP_DMA1_CH2_IRQ_NUM +#define I2C2_TX_DMA_INT_PRIO BSP_DMA1_CH2_IRQ_PRIO +#define I2C2_TX_DMA_INT_SRC INT_SRC_DMA1_TC2 #endif /* DMA1 ch3 */ #if defined(BSP_SPI2_TX_USING_DMA) && !defined(SPI2_TX_DMA_INSTANCE) -#define SPI2_TX_DMA_INSTANCE CM_DMA1 -#define SPI2_TX_DMA_CHANNEL DMA_CH3 -#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define SPI2_TX_DMA_INSTANCE CM_DMA1 +#define SPI2_TX_DMA_CHANNEL DMA_CH3 +#define SPI2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SPI2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SPI2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SPI2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SPI2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_USING_SDIO2) && !defined(SDIO2_TX_DMA_INSTANCE) -#define SDIO2_TX_DMA_INSTANCE CM_DMA1 -#define SDIO2_TX_DMA_CHANNEL DMA_CH3 -#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 -#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define SDIO2_TX_DMA_INSTANCE CM_DMA1 +#define SDIO2_TX_DMA_CHANNEL DMA_CH3 +#define SDIO2_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SDIO2_TX_DMA_TRIG_SELECT AOS_DMA1_3 +#define SDIO2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define SDIO2_TX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define SDIO2_TX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define SDIO2_TX_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_USING_QSPI) && !defined(QSPI_DMA_INSTANCE) -#define QSPI_DMA_INSTANCE CM_DMA1 -#define QSPI_DMA_CHANNEL DMA_CH3 -#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 -#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define QSPI_DMA_INSTANCE CM_DMA1 +#define QSPI_DMA_CHANNEL DMA_CH3 +#define QSPI_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define QSPI_DMA_TRIG_SELECT AOS_DMA1_3 +#define QSPI_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define QSPI_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define QSPI_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define QSPI_DMA_INT_SRC INT_SRC_DMA1_TC3 #elif defined(BSP_I2C2_RX_USING_DMA) && !defined(I2C2_RX_DMA_INSTANCE) -#define I2C2_RX_DMA_INSTANCE CM_DMA1 -#define I2C2_RX_DMA_CHANNEL DMA_CH3 -#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 -#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM -#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO -#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 +#define I2C2_RX_DMA_INSTANCE CM_DMA1 +#define I2C2_RX_DMA_CHANNEL DMA_CH3 +#define I2C2_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C2_RX_DMA_TRIG_SELECT AOS_DMA1_3 +#define I2C2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C2_RX_DMA_IRQn BSP_DMA1_CH3_IRQ_NUM +#define I2C2_RX_DMA_INT_PRIO BSP_DMA1_CH3_IRQ_PRIO +#define I2C2_RX_DMA_INT_SRC INT_SRC_DMA1_TC3 #endif /* DMA1 ch4 */ #if defined(BSP_SPI3_RX_USING_DMA) && !defined(SPI3_RX_DMA_INSTANCE) -#define SPI3_RX_DMA_INSTANCE CM_DMA1 -#define SPI3_RX_DMA_CHANNEL DMA_CH4 -#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 -#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define SPI3_RX_DMA_INSTANCE CM_DMA1 +#define SPI3_RX_DMA_CHANNEL DMA_CH4 +#define SPI3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_RX_DMA_TRIG_SELECT AOS_DMA1_4 +#define SPI3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define SPI3_RX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define SPI3_RX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define SPI3_RX_DMA_INT_SRC INT_SRC_DMA1_TC4 #elif defined(BSP_I2C3_TX_USING_DMA) && !defined(I2C3_TX_DMA_INSTANCE) -#define I2C3_TX_DMA_INSTANCE CM_DMA1 -#define I2C3_TX_DMA_CHANNEL DMA_CH4 -#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 -#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM -#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO -#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 +#define I2C3_TX_DMA_INSTANCE CM_DMA1 +#define I2C3_TX_DMA_CHANNEL DMA_CH4 +#define I2C3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_TX_DMA_TRIG_SELECT AOS_DMA1_4 +#define I2C3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define I2C3_TX_DMA_IRQn BSP_DMA1_CH4_IRQ_NUM +#define I2C3_TX_DMA_INT_PRIO BSP_DMA1_CH4_IRQ_PRIO +#define I2C3_TX_DMA_INT_SRC INT_SRC_DMA1_TC4 #endif /* DMA1 ch5 */ #if defined(BSP_SPI3_TX_USING_DMA) && !defined(SPI3_TX_DMA_INSTANCE) -#define SPI3_TX_DMA_INSTANCE CM_DMA1 -#define SPI3_TX_DMA_CHANNEL DMA_CH5 -#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 -#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define SPI3_TX_DMA_INSTANCE CM_DMA1 +#define SPI3_TX_DMA_CHANNEL DMA_CH5 +#define SPI3_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI3_TX_DMA_TRIG_SELECT AOS_DMA1_5 +#define SPI3_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define SPI3_TX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define SPI3_TX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define SPI3_TX_DMA_INT_SRC INT_SRC_DMA1_TC5 #elif defined(BSP_I2C3_RX_USING_DMA) && !defined(I2C3_RX_DMA_INSTANCE) -#define I2C3_RX_DMA_INSTANCE CM_DMA1 -#define I2C3_RX_DMA_CHANNEL DMA_CH5 -#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 -#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM -#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO -#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 +#define I2C3_RX_DMA_INSTANCE CM_DMA1 +#define I2C3_RX_DMA_CHANNEL DMA_CH5 +#define I2C3_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C3_RX_DMA_TRIG_SELECT AOS_DMA1_5 +#define I2C3_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define I2C3_RX_DMA_IRQn BSP_DMA1_CH5_IRQ_NUM +#define I2C3_RX_DMA_INT_PRIO BSP_DMA1_CH5_IRQ_PRIO +#define I2C3_RX_DMA_INT_SRC INT_SRC_DMA1_TC5 #endif /* DMA1 ch6 */ #if defined(BSP_SPI4_RX_USING_DMA) && !defined(SPI4_RX_DMA_INSTANCE) -#define SPI4_RX_DMA_INSTANCE CM_DMA1 -#define SPI4_RX_DMA_CHANNEL DMA_CH6 -#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 -#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM -#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO -#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#define SPI4_RX_DMA_INSTANCE CM_DMA1 +#define SPI4_RX_DMA_CHANNEL DMA_CH6 +#define SPI4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_RX_DMA_TRIG_SELECT AOS_DMA1_6 +#define SPI4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define SPI4_RX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define SPI4_RX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define SPI4_RX_DMA_INT_SRC INT_SRC_DMA1_TC6 #elif defined(BSP_I2C4_TX_USING_DMA) && !defined(I2C4_TX_DMA_INSTANCE) -#define I2C4_TX_DMA_INSTANCE CM_DMA1 -#define I2C4_TX_DMA_CHANNEL DMA_CH6 -#define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6 -#define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM -#define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO -#define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6 +#define I2C4_TX_DMA_INSTANCE CM_DMA1 +#define I2C4_TX_DMA_CHANNEL DMA_CH6 +#define I2C4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_TX_DMA_TRIG_SELECT AOS_DMA1_6 +#define I2C4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define I2C4_TX_DMA_IRQn BSP_DMA1_CH6_IRQ_NUM +#define I2C4_TX_DMA_INT_PRIO BSP_DMA1_CH6_IRQ_PRIO +#define I2C4_TX_DMA_INT_SRC INT_SRC_DMA1_TC6 #endif /* DMA1 ch7 */ #if defined(BSP_SPI4_TX_USING_DMA) && !defined(SPI4_TX_DMA_INSTANCE) -#define SPI4_TX_DMA_INSTANCE CM_DMA1 -#define SPI4_TX_DMA_CHANNEL DMA_CH7 -#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 -#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM -#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO -#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#define SPI4_TX_DMA_INSTANCE CM_DMA1 +#define SPI4_TX_DMA_CHANNEL DMA_CH7 +#define SPI4_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI4_TX_DMA_TRIG_SELECT AOS_DMA1_7 +#define SPI4_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define SPI4_TX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define SPI4_TX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define SPI4_TX_DMA_INT_SRC INT_SRC_DMA1_TC7 #elif defined(BSP_I2C4_RX_USING_DMA) && !defined(I2C4_RX_DMA_INSTANCE) -#define I2C4_RX_DMA_INSTANCE CM_DMA1 -#define I2C4_RX_DMA_CHANNEL DMA_CH7 -#define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7 -#define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM -#define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO -#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7 +#define I2C4_RX_DMA_INSTANCE CM_DMA1 +#define I2C4_RX_DMA_CHANNEL DMA_CH7 +#define I2C4_RX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define I2C4_RX_DMA_TRIG_SELECT AOS_DMA1_7 +#define I2C4_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define I2C4_RX_DMA_IRQn BSP_DMA1_CH7_IRQ_NUM +#define I2C4_RX_DMA_INT_PRIO BSP_DMA1_CH7_IRQ_PRIO +#define I2C4_RX_DMA_INT_SRC INT_SRC_DMA1_TC7 #endif /* DMA1 ch8 */ #if defined(BSP_SPI5_TX_USING_DMA) && !defined(SPI5_TX_DMA_INSTANCE) -#define SPI5_TX_DMA_INSTANCE CM_DMA1 -#define SPI5_TX_DMA_CHANNEL DMA_CH8 -#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 -#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 -#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM -#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO -#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 +#define SPI5_TX_DMA_INSTANCE CM_DMA1 +#define SPI5_TX_DMA_CHANNEL DMA_CH8 +#define SPI5_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI5_TX_DMA_TRIG_SELECT AOS_DMA1_8 +#define SPI5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH8 +#define SPI5_TX_DMA_IRQn BSP_DMA1_CH8_IRQ_NUM +#define SPI5_TX_DMA_INT_PRIO BSP_DMA1_CH8_IRQ_PRIO +#define SPI5_TX_DMA_INT_SRC INT_SRC_DMA1_TC8 #endif /* DMA1 ch9 */ #if defined(BSP_SPI6_TX_USING_DMA) && !defined(SPI6_TX_DMA_INSTANCE) -#define SPI6_TX_DMA_INSTANCE CM_DMA1 -#define SPI6_TX_DMA_CHANNEL DMA_CH9 -#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) -#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 -#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 -#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM -#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO -#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 +#define SPI6_TX_DMA_INSTANCE CM_DMA1 +#define SPI6_TX_DMA_CHANNEL DMA_CH9 +#define SPI6_TX_DMA_CLOCK (PWC_FCG0_DMA1 | PWC_FCG0_AOS) +#define SPI6_TX_DMA_TRIG_SELECT AOS_DMA1_9 +#define SPI6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH9 +#define SPI6_TX_DMA_IRQn BSP_DMA1_CH9_IRQ_NUM +#define SPI6_TX_DMA_INT_PRIO BSP_DMA1_CH9_IRQ_PRIO +#define SPI6_TX_DMA_INT_SRC INT_SRC_DMA1_TC9 #endif /* DMA2 ch0 */ #if defined(BSP_UART1_RX_USING_DMA) && !defined(UART1_RX_DMA_INSTANCE) -#define UART1_RX_DMA_INSTANCE CM_DMA2 -#define UART1_RX_DMA_CHANNEL DMA_CH0 -#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 -#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define UART1_RX_DMA_INSTANCE CM_DMA2 +#define UART1_RX_DMA_CHANNEL DMA_CH0 +#define UART1_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_RX_DMA_TRIG_SELECT AOS_DMA2_0 +#define UART1_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define UART1_RX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define UART1_RX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define UART1_RX_DMA_INT_SRC INT_SRC_DMA2_TC0 #elif defined(BSP_I2C5_TX_USING_DMA) && !defined(I2C5_TX_DMA_INSTANCE) -#define I2C5_TX_DMA_INSTANCE CM_DMA2 -#define I2C5_TX_DMA_CHANNEL DMA_CH0 -#define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0 -#define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 -#define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM -#define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO -#define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 +#define I2C5_TX_DMA_INSTANCE CM_DMA2 +#define I2C5_TX_DMA_CHANNEL DMA_CH0 +#define I2C5_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_TX_DMA_TRIG_SELECT AOS_DMA2_0 +#define I2C5_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH0 +#define I2C5_TX_DMA_IRQn BSP_DMA2_CH0_IRQ_NUM +#define I2C5_TX_DMA_INT_PRIO BSP_DMA2_CH0_IRQ_PRIO +#define I2C5_TX_DMA_INT_SRC INT_SRC_DMA2_TC0 #endif /* DMA2 ch1 */ #if defined(BSP_UART1_TX_USING_DMA) && !defined(UART1_TX_DMA_INSTANCE) -#define UART1_TX_DMA_INSTANCE CM_DMA2 -#define UART1_TX_DMA_CHANNEL DMA_CH1 -#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 -#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define UART1_TX_DMA_INSTANCE CM_DMA2 +#define UART1_TX_DMA_CHANNEL DMA_CH1 +#define UART1_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART1_TX_DMA_TRIG_SELECT AOS_DMA2_1 +#define UART1_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define UART1_TX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define UART1_TX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define UART1_TX_DMA_INT_SRC INT_SRC_DMA2_TC1 #elif defined(BSP_I2C5_RX_USING_DMA) && !defined(I2C5_RX_DMA_INSTANCE) -#define I2C5_RX_DMA_INSTANCE CM_DMA2 -#define I2C5_RX_DMA_CHANNEL DMA_CH1 -#define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1 -#define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 -#define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM -#define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO -#define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 +#define I2C5_RX_DMA_INSTANCE CM_DMA2 +#define I2C5_RX_DMA_CHANNEL DMA_CH1 +#define I2C5_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C5_RX_DMA_TRIG_SELECT AOS_DMA2_1 +#define I2C5_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH1 +#define I2C5_RX_DMA_IRQn BSP_DMA2_CH1_IRQ_NUM +#define I2C5_RX_DMA_INT_PRIO BSP_DMA2_CH1_IRQ_PRIO +#define I2C5_RX_DMA_INT_SRC INT_SRC_DMA2_TC1 #endif /* DMA2 ch2 */ #if defined(BSP_UART2_RX_USING_DMA) && !defined(UART2_RX_DMA_INSTANCE) -#define UART2_RX_DMA_INSTANCE CM_DMA2 -#define UART2_RX_DMA_CHANNEL DMA_CH2 -#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 -#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define UART2_RX_DMA_INSTANCE CM_DMA2 +#define UART2_RX_DMA_CHANNEL DMA_CH2 +#define UART2_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_RX_DMA_TRIG_SELECT AOS_DMA2_2 +#define UART2_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define UART2_RX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define UART2_RX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define UART2_RX_DMA_INT_SRC INT_SRC_DMA2_TC2 #elif defined(BSP_I2C6_TX_USING_DMA) && !defined(I2C6_TX_DMA_INSTANCE) -#define I2C6_TX_DMA_INSTANCE CM_DMA2 -#define I2C6_TX_DMA_CHANNEL DMA_CH2 -#define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2 -#define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 -#define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM -#define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO -#define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 +#define I2C6_TX_DMA_INSTANCE CM_DMA2 +#define I2C6_TX_DMA_CHANNEL DMA_CH2 +#define I2C6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_TX_DMA_TRIG_SELECT AOS_DMA2_2 +#define I2C6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH2 +#define I2C6_TX_DMA_IRQn BSP_DMA2_CH2_IRQ_NUM +#define I2C6_TX_DMA_INT_PRIO BSP_DMA2_CH2_IRQ_PRIO +#define I2C6_TX_DMA_INT_SRC INT_SRC_DMA2_TC2 #endif /* DMA2 ch3 */ #if defined(BSP_UART2_TX_USING_DMA) && !defined(UART2_TX_DMA_INSTANCE) -#define UART2_TX_DMA_INSTANCE CM_DMA2 -#define UART2_TX_DMA_CHANNEL DMA_CH3 -#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 -#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM -#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO -#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#define UART2_TX_DMA_INSTANCE CM_DMA2 +#define UART2_TX_DMA_CHANNEL DMA_CH3 +#define UART2_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART2_TX_DMA_TRIG_SELECT AOS_DMA2_3 +#define UART2_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define UART2_TX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define UART2_TX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define UART2_TX_DMA_INT_SRC INT_SRC_DMA2_TC3 #elif defined(BSP_I2C6_RX_USING_DMA) && !defined(I2C6_RX_DMA_INSTANCE) -#define I2C6_RX_DMA_INSTANCE CM_DMA2 -#define I2C6_RX_DMA_CHANNEL DMA_CH3 -#define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3 -#define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 -#define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM -#define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO -#define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3 +#define I2C6_RX_DMA_INSTANCE CM_DMA2 +#define I2C6_RX_DMA_CHANNEL DMA_CH3 +#define I2C6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define I2C6_RX_DMA_TRIG_SELECT AOS_DMA2_3 +#define I2C6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH3 +#define I2C6_RX_DMA_IRQn BSP_DMA2_CH3_IRQ_NUM +#define I2C6_RX_DMA_INT_PRIO BSP_DMA2_CH3_IRQ_PRIO +#define I2C6_RX_DMA_INT_SRC INT_SRC_DMA2_TC3 #endif /* DMA2 ch4 */ #if defined(BSP_UART6_RX_USING_DMA) && !defined(UART6_RX_DMA_INSTANCE) -#define UART6_RX_DMA_INSTANCE CM_DMA2 -#define UART6_RX_DMA_CHANNEL DMA_CH4 -#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 -#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 -#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM -#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO -#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 +#define UART6_RX_DMA_INSTANCE CM_DMA2 +#define UART6_RX_DMA_CHANNEL DMA_CH4 +#define UART6_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_RX_DMA_TRIG_SELECT AOS_DMA2_4 +#define UART6_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH4 +#define UART6_RX_DMA_IRQn BSP_DMA2_CH4_IRQ_NUM +#define UART6_RX_DMA_INT_PRIO BSP_DMA2_CH4_IRQ_PRIO +#define UART6_RX_DMA_INT_SRC INT_SRC_DMA2_TC4 #endif /* DMA2 ch5 */ #if defined(BSP_UART6_TX_USING_DMA) && !defined(UART6_TX_DMA_INSTANCE) -#define UART6_TX_DMA_INSTANCE CM_DMA2 -#define UART6_TX_DMA_CHANNEL DMA_CH5 -#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 -#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 -#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM -#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO -#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 +#define UART6_TX_DMA_INSTANCE CM_DMA2 +#define UART6_TX_DMA_CHANNEL DMA_CH5 +#define UART6_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART6_TX_DMA_TRIG_SELECT AOS_DMA2_5 +#define UART6_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH5 +#define UART6_TX_DMA_IRQn BSP_DMA2_CH5_IRQ_NUM +#define UART6_TX_DMA_INT_PRIO BSP_DMA2_CH5_IRQ_PRIO +#define UART6_TX_DMA_INT_SRC INT_SRC_DMA2_TC5 #endif /* DMA2 ch6 */ #if defined(BSP_UART7_RX_USING_DMA) && !defined(UART7_RX_DMA_INSTANCE) -#define UART7_RX_DMA_INSTANCE CM_DMA2 -#define UART7_RX_DMA_CHANNEL DMA_CH6 -#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 -#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 -#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM -#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO -#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 +#define UART7_RX_DMA_INSTANCE CM_DMA2 +#define UART7_RX_DMA_CHANNEL DMA_CH6 +#define UART7_RX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_RX_DMA_TRIG_SELECT AOS_DMA2_6 +#define UART7_RX_DMA_TRANS_FLAG DMA_FLAG_TC_CH6 +#define UART7_RX_DMA_IRQn BSP_DMA2_CH6_IRQ_NUM +#define UART7_RX_DMA_INT_PRIO BSP_DMA2_CH6_IRQ_PRIO +#define UART7_RX_DMA_INT_SRC INT_SRC_DMA2_TC6 #endif /* DMA2 ch7 */ #if defined(BSP_UART7_TX_USING_DMA) && !defined(UART7_TX_DMA_INSTANCE) -#define UART7_TX_DMA_INSTANCE CM_DMA2 -#define UART7_TX_DMA_CHANNEL DMA_CH7 -#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) -#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 -#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 -#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM -#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO -#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 +#define UART7_TX_DMA_INSTANCE CM_DMA2 +#define UART7_TX_DMA_CHANNEL DMA_CH7 +#define UART7_TX_DMA_CLOCK (PWC_FCG0_DMA2 | PWC_FCG0_AOS) +#define UART7_TX_DMA_TRIG_SELECT AOS_DMA2_7 +#define UART7_TX_DMA_TRANS_FLAG DMA_FLAG_TC_CH7 +#define UART7_TX_DMA_IRQn BSP_DMA2_CH7_IRQ_NUM +#define UART7_TX_DMA_INT_PRIO BSP_DMA2_CH7_IRQ_PRIO +#define UART7_TX_DMA_INT_SRC INT_SRC_DMA2_TC7 #endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/eth_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/eth_config.h index f28e5b19c74..7cd9b201c70 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/eth_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/eth_config.h @@ -22,11 +22,11 @@ extern "C" { #if defined(BSP_USING_ETH) #ifndef ETH_IRQ_CONFIG -#define ETH_IRQ_CONFIG \ - { \ - .irq_num = BSP_ETH_IRQ_NUM, \ - .irq_prio = BSP_ETH_IRQ_PRIO, \ - .int_src = INT_SRC_ETH_GLB_INT, \ +#define ETH_IRQ_CONFIG \ + { \ + .irq_num = BSP_ETH_IRQ_NUM, \ + .irq_prio = BSP_ETH_IRQ_PRIO, \ + .int_src = INT_SRC_ETH_GLB_INT, \ } #endif /* ETH_IRQ_CONFIG */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/gpio_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/gpio_config.h index ee17e1230de..9a2be5862fa 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/gpio_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/gpio_config.h @@ -22,146 +22,146 @@ extern "C" { #if defined(RT_USING_PIN) #ifndef EXTINT0_IRQ_CONFIG -#define EXTINT0_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT0_IRQ_NUM, \ - .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ0, \ +#define EXTINT0_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT0_IRQ_NUM, \ + .irq_prio = BSP_EXTINT0_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ0, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT1_IRQ_CONFIG -#define EXTINT1_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT1_IRQ_NUM, \ - .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ1, \ +#define EXTINT1_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT1_IRQ_NUM, \ + .irq_prio = BSP_EXTINT1_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ1, \ } #endif /* EXTINT1_IRQ_CONFIG */ #ifndef EXTINT2_IRQ_CONFIG -#define EXTINT2_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT2_IRQ_NUM, \ - .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ2, \ +#define EXTINT2_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT2_IRQ_NUM, \ + .irq_prio = BSP_EXTINT2_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ2, \ } #endif /* EXTINT2_IRQ_CONFIG */ #ifndef EXTINT3_IRQ_CONFIG -#define EXTINT3_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT3_IRQ_NUM, \ - .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ3, \ +#define EXTINT3_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT3_IRQ_NUM, \ + .irq_prio = BSP_EXTINT3_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ3, \ } #endif /* EXTINT3_IRQ_CONFIG */ #ifndef EXTINT4_IRQ_CONFIG -#define EXTINT4_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT4_IRQ_NUM, \ - .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ4, \ +#define EXTINT4_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT4_IRQ_NUM, \ + .irq_prio = BSP_EXTINT4_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ4, \ } #endif /* EXTINT4_IRQ_CONFIG */ #ifndef EXTINT5_IRQ_CONFIG -#define EXTINT5_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT5_IRQ_NUM, \ - .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ5, \ +#define EXTINT5_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT5_IRQ_NUM, \ + .irq_prio = BSP_EXTINT5_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ5, \ } #endif /* EXTINT5_IRQ_CONFIG */ #ifndef EXTINT6_IRQ_CONFIG -#define EXTINT6_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT6_IRQ_NUM, \ - .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ6, \ +#define EXTINT6_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT6_IRQ_NUM, \ + .irq_prio = BSP_EXTINT6_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ6, \ } #endif /* EXTINT6_IRQ_CONFIG */ #ifndef EXTINT7_IRQ_CONFIG -#define EXTINT7_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT7_IRQ_NUM, \ - .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ7, \ +#define EXTINT7_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT7_IRQ_NUM, \ + .irq_prio = BSP_EXTINT7_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ7, \ } #endif /* EXTINT7_IRQ_CONFIG */ #ifndef EXTINT8_IRQ_CONFIG -#define EXTINT8_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT8_IRQ_NUM, \ - .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ8, \ +#define EXTINT8_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT8_IRQ_NUM, \ + .irq_prio = BSP_EXTINT8_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ8, \ } #endif /* EXTINT8_IRQ_CONFIG */ #ifndef EXTINT9_IRQ_CONFIG -#define EXTINT9_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT9_IRQ_NUM, \ - .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ9, \ +#define EXTINT9_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT9_IRQ_NUM, \ + .irq_prio = BSP_EXTINT9_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ9, \ } #endif /* EXTINT9_IRQ_CONFIG */ #ifndef EXTINT10_IRQ_CONFIG -#define EXTINT10_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT10_IRQ_NUM, \ - .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ10, \ +#define EXTINT10_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT10_IRQ_NUM, \ + .irq_prio = BSP_EXTINT10_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ10, \ } #endif /* EXTINT10_IRQ_CONFIG */ #ifndef EXTINT11_IRQ_CONFIG -#define EXTINT11_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT11_IRQ_NUM, \ - .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ11, \ +#define EXTINT11_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT11_IRQ_NUM, \ + .irq_prio = BSP_EXTINT11_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ11, \ } #endif /* EXTINT11_IRQ_CONFIG */ #ifndef EXTINT12_IRQ_CONFIG -#define EXTINT12_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT12_IRQ_NUM, \ - .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ12, \ +#define EXTINT12_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT12_IRQ_NUM, \ + .irq_prio = BSP_EXTINT12_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ12, \ } #endif /* EXTINT12_IRQ_CONFIG */ #ifndef EXTINT13_IRQ_CONFIG -#define EXTINT13_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT13_IRQ_NUM, \ - .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ13, \ +#define EXTINT13_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT13_IRQ_NUM, \ + .irq_prio = BSP_EXTINT13_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ13, \ } #endif /* EXTINT13_IRQ_CONFIG */ #ifndef EXTINT14_IRQ_CONFIG -#define EXTINT14_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT14_IRQ_NUM, \ - .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ14, \ +#define EXTINT14_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT14_IRQ_NUM, \ + .irq_prio = BSP_EXTINT14_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ14, \ } #endif /* EXTINT14_IRQ_CONFIG */ #ifndef EXTINT15_IRQ_CONFIG -#define EXTINT15_IRQ_CONFIG \ - { \ - .irq_num = BSP_EXTINT15_IRQ_NUM, \ - .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ - .int_src = INT_SRC_PORT_EIRQ15, \ +#define EXTINT15_IRQ_CONFIG \ + { \ + .irq_num = BSP_EXTINT15_IRQ_NUM, \ + .irq_prio = BSP_EXTINT15_IRQ_PRIO, \ + .int_src = INT_SRC_PORT_EIRQ15, \ } #endif /* EXTINT15_IRQ_CONFIG */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/i2c_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/i2c_config.h index 57fe15696ff..7eea731a079 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/i2c_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/i2c_config.h @@ -20,101 +20,97 @@ extern "C" { #if defined(BSP_USING_I2C1) #ifndef I2C1_CONFIG -#define I2C1_CONFIG \ - { \ - .name = "i2c1", \ - .Instance = CM_I2C1, \ - .clock = FCG1_PERIPH_I2C1, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C1_CONFIG \ + { \ + .name = "i2c1", \ + .Instance = CM_I2C1, \ + .clock = FCG1_PERIPH_I2C1, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C1_CONFIG */ #endif #if defined(BSP_I2C1_USING_DMA) #ifndef I2C1_TX_DMA_CONFIG -#define I2C1_TX_DMA_CONFIG \ - { \ - .Instance = I2C1_TX_DMA_INSTANCE, \ - .channel = I2C1_TX_DMA_CHANNEL, \ - .clock = I2C1_TX_DMA_CLOCK, \ - .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_TEI, \ - .flag = I2C1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_TX_DMA_IRQn, \ - .irq_prio = I2C1_TX_DMA_INT_PRIO, \ - .int_src = I2C1_TX_DMA_INT_SRC, \ - }, \ +#define I2C1_TX_DMA_CONFIG \ + { \ + .Instance = I2C1_TX_DMA_INSTANCE, \ + .channel = I2C1_TX_DMA_CHANNEL, \ + .clock = I2C1_TX_DMA_CLOCK, \ + .trigger_select = I2C1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_TEI, \ + .flag = I2C1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_TX_DMA_IRQn, \ + .irq_prio = I2C1_TX_DMA_INT_PRIO, \ + .int_src = I2C1_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_TX_DMA_CONFIG */ #ifndef I2C1_RX_DMA_CONFIG -#define I2C1_RX_DMA_CONFIG \ - { \ - .Instance = I2C1_RX_DMA_INSTANCE, \ - .channel = I2C1_RX_DMA_CHANNEL, \ - .clock = I2C1_RX_DMA_CLOCK, \ - .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C1_RXI, \ - .flag = I2C1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C1_RX_DMA_IRQn, \ - .irq_prio = I2C1_RX_DMA_INT_PRIO, \ - .int_src = I2C1_RX_DMA_INT_SRC, \ - }, \ +#define I2C1_RX_DMA_CONFIG \ + { \ + .Instance = I2C1_RX_DMA_INSTANCE, \ + .channel = I2C1_RX_DMA_CHANNEL, \ + .clock = I2C1_RX_DMA_CLOCK, \ + .trigger_select = I2C1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C1_RXI, \ + .flag = I2C1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C1_RX_DMA_IRQn, \ + .irq_prio = I2C1_RX_DMA_INT_PRIO, \ + .int_src = I2C1_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C1_RX_DMA_CONFIG */ #endif /* BSP_I2C1_USING_DMA */ #if defined(BSP_USING_I2C2) #ifndef I2C2_CONFIG -#define I2C2_CONFIG \ - { \ - .name = "i2c2", \ - .Instance = CM_I2C2, \ - .clock = FCG1_PERIPH_I2C2, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C2_CONFIG \ + { \ + .name = "i2c2", \ + .Instance = CM_I2C2, \ + .clock = FCG1_PERIPH_I2C2, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C2_CONFIG */ #if defined(BSP_I2C2_USING_DMA) #ifndef I2C2_TX_DMA_CONFIG -#define I2C2_TX_DMA_CONFIG \ - { \ - .Instance = I2C2_TX_DMA_INSTANCE, \ - .channel = I2C2_TX_DMA_CHANNEL, \ - .clock = I2C2_TX_DMA_CLOCK, \ - .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_TEI, \ - .flag = I2C2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_TX_DMA_IRQn, \ - .irq_prio = I2C2_TX_DMA_INT_PRIO, \ - .int_src = I2C2_TX_DMA_INT_SRC, \ - }, \ +#define I2C2_TX_DMA_CONFIG \ + { \ + .Instance = I2C2_TX_DMA_INSTANCE, \ + .channel = I2C2_TX_DMA_CHANNEL, \ + .clock = I2C2_TX_DMA_CLOCK, \ + .trigger_select = I2C2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_TEI, \ + .flag = I2C2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_TX_DMA_IRQn, \ + .irq_prio = I2C2_TX_DMA_INT_PRIO, \ + .int_src = I2C2_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_TX_DMA_CONFIG */ #ifndef I2C2_RX_DMA_CONFIG -#define I2C2_RX_DMA_CONFIG \ - { \ - .Instance = I2C2_RX_DMA_INSTANCE, \ - .channel = I2C2_RX_DMA_CHANNEL, \ - .clock = I2C2_RX_DMA_CLOCK, \ - .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C2_RXI, \ - .flag = I2C2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C2_RX_DMA_IRQn, \ - .irq_prio = I2C2_RX_DMA_INT_PRIO, \ - .int_src = I2C2_RX_DMA_INT_SRC, \ - }, \ +#define I2C2_RX_DMA_CONFIG \ + { \ + .Instance = I2C2_RX_DMA_INSTANCE, \ + .channel = I2C2_RX_DMA_CHANNEL, \ + .clock = I2C2_RX_DMA_CLOCK, \ + .trigger_select = I2C2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C2_RXI, \ + .flag = I2C2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C2_RX_DMA_IRQn, \ + .irq_prio = I2C2_RX_DMA_INT_PRIO, \ + .int_src = I2C2_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C2_RX_DMA_CONFIG */ #endif /* BSP_I2C2_USING_DMA */ @@ -122,50 +118,48 @@ extern "C" { #if defined(BSP_USING_I2C3) #ifndef I2C3_CONFIG -#define I2C3_CONFIG \ - { \ - .name = "i2c3", \ - .Instance = CM_I2C3, \ - .clock = FCG1_PERIPH_I2C3, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C3_CONFIG \ + { \ + .name = "i2c3", \ + .Instance = CM_I2C3, \ + .clock = FCG1_PERIPH_I2C3, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C3_CONFIG */ #if defined(BSP_I2C3_USING_DMA) #ifndef I2C3_TX_DMA_CONFIG -#define I2C3_TX_DMA_CONFIG \ - { \ - .Instance = I2C3_TX_DMA_INSTANCE, \ - .channel = I2C3_TX_DMA_CHANNEL, \ - .clock = I2C3_TX_DMA_CLOCK, \ - .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_TEI, \ - .flag = I2C3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_TX_DMA_IRQn, \ - .irq_prio = I2C3_TX_DMA_INT_PRIO, \ - .int_src = I2C3_TX_DMA_INT_SRC, \ - }, \ +#define I2C3_TX_DMA_CONFIG \ + { \ + .Instance = I2C3_TX_DMA_INSTANCE, \ + .channel = I2C3_TX_DMA_CHANNEL, \ + .clock = I2C3_TX_DMA_CLOCK, \ + .trigger_select = I2C3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_TEI, \ + .flag = I2C3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_TX_DMA_IRQn, \ + .irq_prio = I2C3_TX_DMA_INT_PRIO, \ + .int_src = I2C3_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_TX_DMA_CONFIG */ #ifndef I2C3_RX_DMA_CONFIG -#define I2C3_RX_DMA_CONFIG \ - { \ - .Instance = I2C3_RX_DMA_INSTANCE, \ - .channel = I2C3_RX_DMA_CHANNEL, \ - .clock = I2C3_RX_DMA_CLOCK, \ - .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C3_RXI, \ - .flag = I2C3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C3_RX_DMA_IRQn, \ - .irq_prio = I2C3_RX_DMA_INT_PRIO, \ - .int_src = I2C3_RX_DMA_INT_SRC, \ - }, \ +#define I2C3_RX_DMA_CONFIG \ + { \ + .Instance = I2C3_RX_DMA_INSTANCE, \ + .channel = I2C3_RX_DMA_CHANNEL, \ + .clock = I2C3_RX_DMA_CLOCK, \ + .trigger_select = I2C3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C3_RXI, \ + .flag = I2C3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C3_RX_DMA_IRQn, \ + .irq_prio = I2C3_RX_DMA_INT_PRIO, \ + .int_src = I2C3_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C3_RX_DMA_CONFIG */ #endif /* BSP_I2C3_USING_DMA */ @@ -173,50 +167,48 @@ extern "C" { #if defined(BSP_USING_I2C4) #ifndef I2C4_CONFIG -#define I2C4_CONFIG \ - { \ - .name = "i2c4", \ - .Instance = CM_I2C4, \ - .clock = FCG1_PERIPH_I2C4, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C4_CONFIG \ + { \ + .name = "i2c4", \ + .Instance = CM_I2C4, \ + .clock = FCG1_PERIPH_I2C4, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C4_CONFIG */ #if defined(BSP_I2C4_USING_DMA) #ifndef I2C4_TX_DMA_CONFIG -#define I2C4_TX_DMA_CONFIG \ - { \ - .Instance = I2C4_TX_DMA_INSTANCE, \ - .channel = I2C4_TX_DMA_CHANNEL, \ - .clock = I2C4_TX_DMA_CLOCK, \ - .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C4_TEI, \ - .flag = I2C4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C4_TX_DMA_IRQn, \ - .irq_prio = I2C4_TX_DMA_INT_PRIO, \ - .int_src = I2C4_TX_DMA_INT_SRC, \ - }, \ +#define I2C4_TX_DMA_CONFIG \ + { \ + .Instance = I2C4_TX_DMA_INSTANCE, \ + .channel = I2C4_TX_DMA_CHANNEL, \ + .clock = I2C4_TX_DMA_CLOCK, \ + .trigger_select = I2C4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_TEI, \ + .flag = I2C4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_TX_DMA_IRQn, \ + .irq_prio = I2C4_TX_DMA_INT_PRIO, \ + .int_src = I2C4_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C4_TX_DMA_CONFIG */ #ifndef I2C4_RX_DMA_CONFIG -#define I2C4_RX_DMA_CONFIG \ - { \ - .Instance = I2C4_RX_DMA_INSTANCE, \ - .channel = I2C4_RX_DMA_CHANNEL, \ - .clock = I2C4_RX_DMA_CLOCK, \ - .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C4_RXI, \ - .flag = I2C4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C4_RX_DMA_IRQn, \ - .irq_prio = I2C4_RX_DMA_INT_PRIO, \ - .int_src = I2C4_RX_DMA_INT_SRC, \ - }, \ +#define I2C4_RX_DMA_CONFIG \ + { \ + .Instance = I2C4_RX_DMA_INSTANCE, \ + .channel = I2C4_RX_DMA_CHANNEL, \ + .clock = I2C4_RX_DMA_CLOCK, \ + .trigger_select = I2C4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C4_RXI, \ + .flag = I2C4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C4_RX_DMA_IRQn, \ + .irq_prio = I2C4_RX_DMA_INT_PRIO, \ + .int_src = I2C4_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C4_RX_DMA_CONFIG */ #endif /* BSP_I2C4_USING_DMA */ @@ -224,50 +216,48 @@ extern "C" { #if defined(BSP_USING_I2C5) #ifndef I2C5_CONFIG -#define I2C5_CONFIG \ - { \ - .name = "i2c5", \ - .Instance = CM_I2C5, \ - .clock = FCG1_PERIPH_I2C5, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C5_CONFIG \ + { \ + .name = "i2c5", \ + .Instance = CM_I2C5, \ + .clock = FCG1_PERIPH_I2C5, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C5_CONFIG */ #if defined(BSP_I2C5_USING_DMA) #ifndef I2C5_TX_DMA_CONFIG -#define I2C5_TX_DMA_CONFIG \ - { \ - .Instance = I2C5_TX_DMA_INSTANCE, \ - .channel = I2C5_TX_DMA_CHANNEL, \ - .clock = I2C5_TX_DMA_CLOCK, \ - .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C5_TEI, \ - .flag = I2C5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C5_TX_DMA_IRQn, \ - .irq_prio = I2C5_TX_DMA_INT_PRIO, \ - .int_src = I2C5_TX_DMA_INT_SRC, \ - }, \ +#define I2C5_TX_DMA_CONFIG \ + { \ + .Instance = I2C5_TX_DMA_INSTANCE, \ + .channel = I2C5_TX_DMA_CHANNEL, \ + .clock = I2C5_TX_DMA_CLOCK, \ + .trigger_select = I2C5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_TEI, \ + .flag = I2C5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_TX_DMA_IRQn, \ + .irq_prio = I2C5_TX_DMA_INT_PRIO, \ + .int_src = I2C5_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C5_TX_DMA_CONFIG */ #ifndef I2C5_RX_DMA_CONFIG -#define I2C5_RX_DMA_CONFIG \ - { \ - .Instance = I2C5_RX_DMA_INSTANCE, \ - .channel = I2C5_RX_DMA_CHANNEL, \ - .clock = I2C5_RX_DMA_CLOCK, \ - .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C5_RXI, \ - .flag = I2C5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C5_RX_DMA_IRQn, \ - .irq_prio = I2C5_RX_DMA_INT_PRIO, \ - .int_src = I2C5_RX_DMA_INT_SRC, \ - }, \ +#define I2C5_RX_DMA_CONFIG \ + { \ + .Instance = I2C5_RX_DMA_INSTANCE, \ + .channel = I2C5_RX_DMA_CHANNEL, \ + .clock = I2C5_RX_DMA_CLOCK, \ + .trigger_select = I2C5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C5_RXI, \ + .flag = I2C5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C5_RX_DMA_IRQn, \ + .irq_prio = I2C5_RX_DMA_INT_PRIO, \ + .int_src = I2C5_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C5_RX_DMA_CONFIG */ #endif /* BSP_I2C5_USING_DMA */ @@ -275,50 +265,48 @@ extern "C" { #if defined(BSP_USING_I2C6) #ifndef I2C6_CONFIG -#define I2C6_CONFIG \ - { \ - .name = "i2c6", \ - .Instance = CM_I2C6, \ - .clock = FCG1_PERIPH_I2C6, \ - .baudrate = 100000UL, \ - .timeout = 10000UL, \ +#define I2C6_CONFIG \ + { \ + .name = "i2c6", \ + .Instance = CM_I2C6, \ + .clock = FCG1_PERIPH_I2C6, \ + .baudrate = 100000UL, \ + .timeout = 10000UL, \ } #endif /* I2C6_CONFIG */ #if defined(BSP_I2C6_USING_DMA) #ifndef I2C6_TX_DMA_CONFIG -#define I2C6_TX_DMA_CONFIG \ - { \ - .Instance = I2C6_TX_DMA_INSTANCE, \ - .channel = I2C6_TX_DMA_CHANNEL, \ - .clock = I2C6_TX_DMA_CLOCK, \ - .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C6_TEI, \ - .flag = I2C6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C6_TX_DMA_IRQn, \ - .irq_prio = I2C6_TX_DMA_INT_PRIO, \ - .int_src = I2C6_TX_DMA_INT_SRC, \ - }, \ +#define I2C6_TX_DMA_CONFIG \ + { \ + .Instance = I2C6_TX_DMA_INSTANCE, \ + .channel = I2C6_TX_DMA_CHANNEL, \ + .clock = I2C6_TX_DMA_CLOCK, \ + .trigger_select = I2C6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_TEI, \ + .flag = I2C6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_TX_DMA_IRQn, \ + .irq_prio = I2C6_TX_DMA_INT_PRIO, \ + .int_src = I2C6_TX_DMA_INT_SRC, \ + }, \ } #endif /* I2C6_TX_DMA_CONFIG */ #ifndef I2C6_RX_DMA_CONFIG -#define I2C6_RX_DMA_CONFIG \ - { \ - .Instance = I2C6_RX_DMA_INSTANCE, \ - .channel = I2C6_RX_DMA_CHANNEL, \ - .clock = I2C6_RX_DMA_CLOCK, \ - .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_I2C6_RXI, \ - .flag = I2C6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = I2C6_RX_DMA_IRQn, \ - .irq_prio = I2C6_RX_DMA_INT_PRIO, \ - .int_src = I2C6_RX_DMA_INT_SRC, \ - }, \ +#define I2C6_RX_DMA_CONFIG \ + { \ + .Instance = I2C6_RX_DMA_INSTANCE, \ + .channel = I2C6_RX_DMA_CHANNEL, \ + .clock = I2C6_RX_DMA_CLOCK, \ + .trigger_select = I2C6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_I2C6_RXI, \ + .flag = I2C6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = I2C6_RX_DMA_IRQn, \ + .irq_prio = I2C6_RX_DMA_INT_PRIO, \ + .int_src = I2C6_RX_DMA_INT_SRC, \ + }, \ } #endif /* I2C6_RX_DMA_CONFIG */ #endif /* BSP_I2C6_USING_DMA */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/irq_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/irq_config.h index 65d3a046778..3127f6ae38b 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/irq_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/irq_config.h @@ -17,481 +17,481 @@ extern "C" { #endif -#define BSP_EXTINT0_IRQ_NUM INT022_IRQn -#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT1_IRQ_NUM INT023_IRQn -#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT2_IRQ_NUM INT024_IRQn -#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT3_IRQ_NUM INT025_IRQn -#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT4_IRQ_NUM INT026_IRQn -#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT5_IRQ_NUM INT027_IRQn -#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT6_IRQ_NUM INT028_IRQn -#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT7_IRQ_NUM INT029_IRQn -#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT8_IRQ_NUM INT030_IRQn -#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT9_IRQ_NUM INT031_IRQn -#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT10_IRQ_NUM INT032_IRQn -#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT11_IRQ_NUM INT033_IRQn -#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT12_IRQ_NUM INT034_IRQn -#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT13_IRQ_NUM INT035_IRQn -#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT14_IRQ_NUM INT036_IRQn -#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_EXTINT15_IRQ_NUM INT037_IRQn -#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT0_IRQ_NUM INT022_IRQn +#define BSP_EXTINT0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT1_IRQ_NUM INT023_IRQn +#define BSP_EXTINT1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT2_IRQ_NUM INT024_IRQn +#define BSP_EXTINT2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT3_IRQ_NUM INT025_IRQn +#define BSP_EXTINT3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT4_IRQ_NUM INT026_IRQn +#define BSP_EXTINT4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT5_IRQ_NUM INT027_IRQn +#define BSP_EXTINT5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT6_IRQ_NUM INT028_IRQn +#define BSP_EXTINT6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT7_IRQ_NUM INT029_IRQn +#define BSP_EXTINT7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT8_IRQ_NUM INT030_IRQn +#define BSP_EXTINT8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT9_IRQ_NUM INT031_IRQn +#define BSP_EXTINT9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT10_IRQ_NUM INT032_IRQn +#define BSP_EXTINT10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT11_IRQ_NUM INT033_IRQn +#define BSP_EXTINT11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT12_IRQ_NUM INT034_IRQn +#define BSP_EXTINT12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT13_IRQ_NUM INT035_IRQn +#define BSP_EXTINT13_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT14_IRQ_NUM INT036_IRQn +#define BSP_EXTINT14_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_EXTINT15_IRQ_NUM INT037_IRQn +#define BSP_EXTINT15_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch0 */ -#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn -#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH0_IRQ_NUM INT038_IRQn +#define BSP_DMA1_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch1 */ -#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn -#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH1_IRQ_NUM INT039_IRQn +#define BSP_DMA1_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch2 */ -#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn -#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH2_IRQ_NUM INT040_IRQn +#define BSP_DMA1_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch3 */ -#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn -#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH3_IRQ_NUM INT041_IRQn +#define BSP_DMA1_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch4 */ -#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn -#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH4_IRQ_NUM INT042_IRQn +#define BSP_DMA1_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch5 */ -#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn -#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH5_IRQ_NUM INT043_IRQn +#define BSP_DMA1_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch6 */ -#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn -#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH6_IRQ_NUM INT018_IRQn +#define BSP_DMA1_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch7 */ -#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn -#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH7_IRQ_NUM INT019_IRQn +#define BSP_DMA1_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch8 */ -#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn -#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH8_IRQ_NUM INT020_IRQn +#define BSP_DMA1_CH8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA1 ch9 */ -#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn -#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA1_CH9_IRQ_NUM INT021_IRQn +#define BSP_DMA1_CH9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch0 */ -#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn -#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH0_IRQ_NUM INT044_IRQn +#define BSP_DMA2_CH0_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch1 */ -#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn -#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH1_IRQ_NUM INT045_IRQn +#define BSP_DMA2_CH1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch2 */ -#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn -#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH2_IRQ_NUM INT046_IRQn +#define BSP_DMA2_CH2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch3 */ -#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn -#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH3_IRQ_NUM INT047_IRQn +#define BSP_DMA2_CH3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch4 */ -#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn -#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH4_IRQ_NUM INT048_IRQn +#define BSP_DMA2_CH4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch5 */ -#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn -#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH5_IRQ_NUM INT049_IRQn +#define BSP_DMA2_CH5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch6 */ -#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn -#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH6_IRQ_NUM INT020_IRQn +#define BSP_DMA2_CH6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT /* DMA2 ch7 */ -#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn -#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_DMA2_CH7_IRQ_NUM INT021_IRQn +#define BSP_DMA2_CH7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_USING_ETH) -#define BSP_ETH_IRQ_NUM INT104_IRQn -#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_ETH_IRQ_NUM INT104_IRQn +#define BSP_ETH_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_UART1) -#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn -#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART1_RX_IRQ_NUM INT089_IRQn -#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART1_TX_IRQ_NUM INT088_IRQn -#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RXERR_IRQ_NUM INT010_IRQn +#define BSP_UART1_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RX_IRQ_NUM INT089_IRQn +#define BSP_UART1_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_IRQ_NUM INT088_IRQn +#define BSP_UART1_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART1_RX_USING_DMA) -#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn -#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_RXTO_IRQ_NUM INT006_IRQn +#define BSP_UART1_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) -#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn -#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART1_TX_CPLT_IRQ_NUM INT086_IRQn +#define BSP_UART1_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART1 */ #if defined(BSP_USING_UART2) -#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn -#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART2_RX_IRQ_NUM INT091_IRQn -#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART2_TX_IRQ_NUM INT090_IRQn -#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RXERR_IRQ_NUM INT011_IRQn +#define BSP_UART2_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RX_IRQ_NUM INT091_IRQn +#define BSP_UART2_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_IRQ_NUM INT090_IRQn +#define BSP_UART2_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART2_RX_USING_DMA) -#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn -#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_RXTO_IRQ_NUM INT007_IRQn +#define BSP_UART2_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) -#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn -#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART2_TX_CPLT_IRQ_NUM INT087_IRQn +#define BSP_UART2_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART2 */ #if defined(BSP_USING_UART3) -#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn -#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART3_RX_IRQ_NUM INT095_IRQn -#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART3_TX_IRQ_NUM INT094_IRQn -#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RXERR_IRQ_NUM INT012_IRQn +#define BSP_UART3_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_RX_IRQ_NUM INT095_IRQn +#define BSP_UART3_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART3_TX_IRQ_NUM INT094_IRQn +#define BSP_UART3_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART3 */ #if defined(BSP_USING_UART4) -#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn -#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART4_RX_IRQ_NUM INT097_IRQn -#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART4_TX_IRQ_NUM INT096_IRQn -#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RXERR_IRQ_NUM INT013_IRQn +#define BSP_UART4_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_RX_IRQ_NUM INT097_IRQn +#define BSP_UART4_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART4_TX_IRQ_NUM INT096_IRQn +#define BSP_UART4_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART4 */ #if defined(BSP_USING_UART5) -#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn -#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART5_RX_IRQ_NUM INT101_IRQn -#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART5_TX_IRQ_NUM INT100_IRQn -#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RXERR_IRQ_NUM INT014_IRQn +#define BSP_UART5_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_RX_IRQ_NUM INT101_IRQn +#define BSP_UART5_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART5_TX_IRQ_NUM INT100_IRQn +#define BSP_UART5_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART5 */ #if defined(BSP_USING_UART6) -#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn -#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART6_RX_IRQ_NUM INT103_IRQn -#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART6_TX_IRQ_NUM INT102_IRQn -#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RXERR_IRQ_NUM INT015_IRQn +#define BSP_UART6_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RX_IRQ_NUM INT103_IRQn +#define BSP_UART6_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_IRQ_NUM INT102_IRQn +#define BSP_UART6_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART6_RX_USING_DMA) -#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn -#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_RXTO_IRQ_NUM INT008_IRQn +#define BSP_UART6_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) -#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn -#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn -#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART6_TX_CPLT_IRQ_NUM INT099_IRQn +#define BSP_UART6_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART6 */ #if defined(BSP_USING_UART7) -#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn -#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART7_RX_IRQ_NUM INT107_IRQn -#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART7_TX_IRQ_NUM INT106_IRQn -#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RXERR_IRQ_NUM INT016_IRQn +#define BSP_UART7_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RX_IRQ_NUM INT107_IRQn +#define BSP_UART7_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_IRQ_NUM INT106_IRQn +#define BSP_UART7_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(BSP_UART7_RX_USING_DMA) -#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn -#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_RXTO_IRQ_NUM INT009_IRQn +#define BSP_UART7_RXTO_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) -#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn -#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #elif defined(RT_USING_SERIAL_V2) -#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn -#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART7_TX_CPLT_IRQ_NUM INT105_IRQn +#define BSP_UART7_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #elif defined(BSP_USING_SPI1) || defined(BSP_USING_SPI2) -#define BSP_SPI1_ERR_IRQ_NUM INT009_IRQn -#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_SPI2_ERR_IRQ_NUM INT016_IRQn -#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI1_ERR_IRQ_NUM INT009_IRQn +#define BSP_SPI1_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI2_ERR_IRQ_NUM INT016_IRQn +#define BSP_SPI2_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART7 */ #if defined(BSP_USING_SPI3) -#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn -#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI3_ERR_IRQ_NUM INT092_IRQn +#define BSP_SPI3_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI4) -#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn -#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI4_ERR_IRQ_NUM INT093_IRQn +#define BSP_SPI4_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI5) -#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn -#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI5_ERR_IRQ_NUM INT098_IRQn +#define BSP_SPI5_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_SPI6) -#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn -#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SPI6_ERR_IRQ_NUM INT099_IRQn +#define BSP_SPI6_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #if defined(BSP_USING_UART8) -#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn -#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART8_RX_IRQ_NUM INT109_IRQn -#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART8_TX_IRQ_NUM INT108_IRQn -#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RXERR_IRQ_NUM INT017_IRQn +#define BSP_UART8_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_RX_IRQ_NUM INT109_IRQn +#define BSP_UART8_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_IRQ_NUM INT108_IRQn +#define BSP_UART8_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #if defined(RT_USING_SERIAL_V2) -#define BSP_UART8_TX_CPLT_IRQ_NUM INT001_IRQn -#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART8_TX_CPLT_IRQ_NUM INT001_IRQn +#define BSP_UART8_TX_CPLT_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif #endif /* BSP_USING_UART8 */ #if defined(BSP_USING_UART9) -#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn -#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART9_RX_IRQ_NUM INT110_IRQn -#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART9_TX_IRQ_NUM INT111_IRQn -#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RXERR_IRQ_NUM INT112_IRQn +#define BSP_UART9_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_RX_IRQ_NUM INT110_IRQn +#define BSP_UART9_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART9_TX_IRQ_NUM INT111_IRQn +#define BSP_UART9_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART9 */ #if defined(BSP_USING_UART10) -#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn -#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART10_RX_IRQ_NUM INT114_IRQn -#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_UART10_TX_IRQ_NUM INT113_IRQn -#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RXERR_IRQ_NUM INT115_IRQn +#define BSP_UART10_RXERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_RX_IRQ_NUM INT114_IRQn +#define BSP_UART10_RX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_UART10_TX_IRQ_NUM INT113_IRQn +#define BSP_UART10_TX_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_UART10 */ #if defined(BSP_USING_CAN1) -#define BSP_CAN1_IRQ_NUM INT092_IRQn -#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_CAN1_IRQ_NUM INT092_IRQn +#define BSP_CAN1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_CAN1 */ #if defined(BSP_USING_CAN2) -#define BSP_CAN2_IRQ_NUM INT093_IRQn -#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_CAN2_IRQ_NUM INT093_IRQn +#define BSP_CAN2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_CAN2 */ #if defined(BSP_USING_SDIO1) -#define BSP_SDIO1_IRQ_NUM INT004_IRQn -#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SDIO1_IRQ_NUM INT004_IRQn +#define BSP_SDIO1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_SDIO1 */ #if defined(BSP_USING_SDIO2) -#define BSP_SDIO2_IRQ_NUM INT005_IRQn -#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_SDIO2_IRQ_NUM INT005_IRQn +#define BSP_SDIO2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_SDIO2 */ #if defined(RT_USING_ALARM) -#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn -#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_RTC_ALARM_IRQ_NUM INT050_IRQn +#define BSP_RTC_ALARM_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* RT_USING_ALARM */ #if defined(BSP_USING_USBFS) -#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn -#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USBFS_GLB_IRQ_NUM INT003_IRQn +#define BSP_USBFS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBFS */ #if defined(BSP_USING_USBHS) -#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn -#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USBHS_GLB_IRQ_NUM INT000_IRQn +#define BSP_USBHS_GLB_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_USBHS */ -#if defined (BSP_USING_QSPI) -#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn -#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#if defined(BSP_USING_QSPI) +#define BSP_QSPI_ERR_IRQ_NUM INT002_IRQn +#define BSP_QSPI_ERR_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif /* BSP_USING_QSPI */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn -#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_2) -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn -#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_3) -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn -#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_4) -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn -#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_5) -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn -#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM INT092_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM INT093_IRQn +#define BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_6) -#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn -#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn -#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM INT094_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM INT095_IRQn +#define BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_6 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_7) -#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn -#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn -#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_7 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_8) -#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn -#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn -#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM INT096_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM INT097_IRQn +#define BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_8 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_9) -#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM INT098_IRQn -#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM INT099_IRQn -#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM INT098_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM INT099_IRQn +#define BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_9 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_10) -#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM INT100_IRQn -#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM INT101_IRQn -#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM INT100_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM INT101_IRQn +#define BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_10 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_11) -#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM INT102_IRQn -#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM INT103_IRQn -#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_11 */ #if defined(BSP_USING_PULSE_ENCODER_TMRA_12) -#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM INT102_IRQn -#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM INT103_IRQn -#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM INT102_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM INT103_IRQn +#define BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMRA_12 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_1) -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn -#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM INT056_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM INT057_IRQn +#define BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_1 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_2) -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn -#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM INT058_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM INT059_IRQn +#define BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_2 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_3) -#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn -#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn -#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM INT062_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM INT063_IRQn +#define BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_3 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_4) -#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM INT068_IRQn -#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM INT069_IRQn -#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM INT068_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM INT069_IRQn +#define BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_4 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_5) -#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM INT074_IRQn -#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM INT075_IRQn -#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM INT074_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM INT075_IRQn +#define BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_5 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_6) -#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM INT076_IRQn -#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM INT077_IRQn -#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM INT076_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM INT077_IRQn +#define BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_6 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_7) -#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM INT080_IRQn -#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM INT081_IRQn -#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM INT080_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM INT081_IRQn +#define BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_7 */ #if defined(BSP_USING_PULSE_ENCODER_TMR6_8) -#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM INT082_IRQn -#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT -#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM INT083_IRQn -#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM INT082_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM INT083_IRQn +#define BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_PULSE_ENCODER_TMR6_8 */ #if defined(BSP_USING_TMRA_1) -#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn -#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_1_IRQ_NUM INT074_IRQn +#define BSP_USING_TMRA_1_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_1 */ #if defined(BSP_USING_TMRA_2) -#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn -#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_2_IRQ_NUM INT075_IRQn +#define BSP_USING_TMRA_2_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_2 */ #if defined(BSP_USING_TMRA_3) -#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn -#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_3_IRQ_NUM INT080_IRQn +#define BSP_USING_TMRA_3_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_3 */ #if defined(BSP_USING_TMRA_4) -#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn -#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_4_IRQ_NUM INT081_IRQn +#define BSP_USING_TMRA_4_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_4 */ #if defined(BSP_USING_TMRA_5) -#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn -#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_5_IRQ_NUM INT092_IRQn +#define BSP_USING_TMRA_5_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_5 */ #if defined(BSP_USING_TMRA_6) -#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn -#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_6_IRQ_NUM INT093_IRQn +#define BSP_USING_TMRA_6_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_6 */ #if defined(BSP_USING_TMRA_7) -#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn -#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_7_IRQ_NUM INT094_IRQn +#define BSP_USING_TMRA_7_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_7 */ #if defined(BSP_USING_TMRA_8) -#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn -#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_8_IRQ_NUM INT095_IRQn +#define BSP_USING_TMRA_8_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_8 */ #if defined(BSP_USING_TMRA_9) -#define BSP_USING_TMRA_9_IRQ_NUM INT098_IRQn -#define BSP_USING_TMRA_9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_9_IRQ_NUM INT098_IRQn +#define BSP_USING_TMRA_9_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_9 */ #if defined(BSP_USING_TMRA_10) -#define BSP_USING_TMRA_10_IRQ_NUM INT099_IRQn -#define BSP_USING_TMRA_10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_10_IRQ_NUM INT099_IRQn +#define BSP_USING_TMRA_10_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_10 */ #if defined(BSP_USING_TMRA_11) -#define BSP_USING_TMRA_11_IRQ_NUM INT100_IRQn -#define BSP_USING_TMRA_11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_11_IRQ_NUM INT100_IRQn +#define BSP_USING_TMRA_11_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_11 */ #if defined(BSP_USING_TMRA_12) -#define BSP_USING_TMRA_12_IRQ_NUM INT101_IRQn -#define BSP_USING_TMRA_12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT +#define BSP_USING_TMRA_12_IRQ_NUM INT101_IRQn +#define BSP_USING_TMRA_12_IRQ_PRIO DDL_IRQ_PRIO_DEFAULT #endif/* BSP_USING_TMRA_12 */ #ifdef __cplusplus } diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h index 3779fdbec50..88631e375aa 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pm_config.h @@ -21,18 +21,18 @@ extern "C" { extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); #ifndef PM_TICKLESS_TIMER_ENABLE_MASK -#define PM_TICKLESS_TIMER_ENABLE_MASK \ -( (1UL << PM_SLEEP_MODE_IDLE) | \ - (1UL << PM_SLEEP_MODE_DEEP)) +#define PM_TICKLESS_TIMER_ENABLE_MASK \ + ((1UL << PM_SLEEP_MODE_IDLE) | \ + (1UL << PM_SLEEP_MODE_DEEP)) #endif /** * @brief run mode config @ref pm_run_mode_config structure */ #ifndef PM_RUN_MODE_CFG -#define PM_RUN_MODE_CFG \ - { \ - .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ +#define PM_RUN_MODE_CFG \ + { \ + .sys_clk_cfg = rt_hw_board_pm_sysclk_cfg \ } #endif /* PM_RUN_MODE_CFG */ @@ -40,54 +40,54 @@ extern void rt_hw_board_pm_sysclk_cfg(uint8_t run_mode); * @brief sleep idle config @ref pm_sleep_mode_idle_config structure */ #ifndef PM_SLEEP_IDLE_CFG -#define PM_SLEEP_IDLE_CFG \ -{ \ - .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ -} +#define PM_SLEEP_IDLE_CFG \ + { \ + .pwc_sleep_type = PWC_SLEEP_WFE_INT, \ + } #endif /*PM_SLEEP_IDLE_CFG*/ /** * @brief sleep deep config @ref pm_sleep_mode_deep_config structure */ #ifndef PM_SLEEP_DEEP_CFG -#define PM_SLEEP_DEEP_CFG \ -{ \ - { \ - .u16Clock = PWC_STOP_CLK_KEEP, \ - .u8StopDrv = PWC_STOP_DRV_HIGH, \ - .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ - .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ - }, \ - .pwc_stop_type = PWC_STOP_WFE_INT, \ -} +#define PM_SLEEP_DEEP_CFG \ + { \ + { \ + .u16Clock = PWC_STOP_CLK_KEEP, \ + .u8StopDrv = PWC_STOP_DRV_HIGH, \ + .u16ExBusHold = PWC_STOP_EXBUS_HIZ, \ + .u16FlashWait = PWC_STOP_FLASH_WAIT_ON, \ + }, \ + .pwc_stop_type = PWC_STOP_WFE_INT, \ + } #endif /*PM_SLEEP_DEEP_CFG*/ /** * @brief sleep standby config @ref pm_sleep_mode_standby_config structure */ #ifndef PM_SLEEP_STANDBY_CFG -#define PM_SLEEP_STANDBY_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD1, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ - }, \ -} +#define PM_SLEEP_STANDBY_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD1, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } #endif /*PM_SLEEP_STANDBY_CFG*/ /** * @brief sleep shutdown config @ref pm_sleep_mode_shutdown_config structure */ #ifndef PM_SLEEP_SHUTDOWN_CFG -#define PM_SLEEP_SHUTDOWN_CFG \ -{ \ - { \ - .u8Mode = PWC_PD_MD3, \ - .u8IOState = PWC_PD_IO_KEEP1, \ - .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ - }, \ -} +#define PM_SLEEP_SHUTDOWN_CFG \ + { \ + { \ + .u8Mode = PWC_PD_MD3, \ + .u8IOState = PWC_PD_IO_KEEP1, \ + .u8VcapCtrl = PWC_PD_VCAP_0P047UF, \ + }, \ + } #endif /*PM_SLEEP_SHUTDOWN_CFG*/ #endif /* BSP_USING_PM */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pulse_encoder_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pulse_encoder_config.h index 1db10b6d14c..aaa9fea6ba4 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pulse_encoder_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pulse_encoder_config.h @@ -21,520 +21,480 @@ extern "C" { #ifdef BSP_USING_PULSE_ENCODER_TMRA_1 #ifndef PULSE_ENCODER_TMRA_1_CONFIG -#define PULSE_ENCODER_TMRA_1_CONFIG \ - { \ - .tmr_handler = CM_TMRA_1, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a1" \ +#define PULSE_ENCODER_TMRA_1_CONFIG \ + { \ + .tmr_handler = CM_TMRA_1, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_1, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a1" \ } #endif /* PULSE_ENCODER_TMRA_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_2 #ifndef PULSE_ENCODER_TMRA_2_CONFIG -#define PULSE_ENCODER_TMRA_2_CONFIG \ - { \ - .tmr_handler = CM_TMRA_2, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a2" \ +#define PULSE_ENCODER_TMRA_2_CONFIG \ + { \ + .tmr_handler = CM_TMRA_2, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_2, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a2" \ } #endif /* PULSE_ENCODER_TMRA_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_3 #ifndef PULSE_ENCODER_TMRA_3_CONFIG -#define PULSE_ENCODER_TMRA_3_CONFIG \ - { \ - .tmr_handler = CM_TMRA_3, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a3" \ +#define PULSE_ENCODER_TMRA_3_CONFIG \ + { \ + .tmr_handler = CM_TMRA_3, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_3, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a3" \ } #endif /* PULSE_ENCODER_TMRA_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_4 #ifndef PULSE_ENCODER_TMRA_4_CONFIG -#define PULSE_ENCODER_TMRA_4_CONFIG \ - { \ - .tmr_handler = CM_TMRA_4, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a4" \ +#define PULSE_ENCODER_TMRA_4_CONFIG \ + { \ + .tmr_handler = CM_TMRA_4, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_4, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a4" \ } #endif /* PULSE_ENCODER_TMRA_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_5 #ifndef PULSE_ENCODER_TMRA_5_CONFIG -#define PULSE_ENCODER_TMRA_5_CONFIG \ - { \ - .tmr_handler = CM_TMRA_5, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a5" \ +#define PULSE_ENCODER_TMRA_5_CONFIG \ + { \ + .tmr_handler = CM_TMRA_5, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_5, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a5" \ } #endif /* PULSE_ENCODER_TMRA_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_6 #ifndef PULSE_ENCODER_TMRA_6_CONFIG -#define PULSE_ENCODER_TMRA_6_CONFIG \ - { \ - .tmr_handler = CM_TMRA_6, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a6" \ +#define PULSE_ENCODER_TMRA_6_CONFIG \ + { \ + .tmr_handler = CM_TMRA_6, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_6, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a6" \ } #endif /* PULSE_ENCODER_TMRA_6_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_6 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_7 #ifndef PULSE_ENCODER_TMRA_7_CONFIG -#define PULSE_ENCODER_TMRA_7_CONFIG \ - { \ - .tmr_handler = CM_TMRA_7, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_7, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a7" \ +#define PULSE_ENCODER_TMRA_7_CONFIG \ + { \ + .tmr_handler = CM_TMRA_7, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_7, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a7" \ } #endif /* PULSE_ENCODER_TMRA_7_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_7 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_8 #ifndef PULSE_ENCODER_TMRA_8_CONFIG -#define PULSE_ENCODER_TMRA_8_CONFIG \ - { \ - .tmr_handler = CM_TMRA_8, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_8, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a8" \ +#define PULSE_ENCODER_TMRA_8_CONFIG \ + { \ + .tmr_handler = CM_TMRA_8, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_8, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a8" \ } #endif /* PULSE_ENCODER_TMRA_8_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_8 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_9 #ifndef PULSE_ENCODER_TMRA_9_CONFIG -#define PULSE_ENCODER_TMRA_9_CONFIG \ - { \ - .tmr_handler = CM_TMRA_9, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_9, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_9_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_9_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a9" \ +#define PULSE_ENCODER_TMRA_9_CONFIG \ + { \ + .tmr_handler = CM_TMRA_9, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_9, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_9_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_9_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_9_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_9_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a9" \ } #endif /* PULSE_ENCODER_TMRA_9_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_9 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_10 #ifndef PULSE_ENCODER_TMRA_10_CONFIG -#define PULSE_ENCODER_TMRA_10_CONFIG \ - { \ - .tmr_handler = CM_TMRA_10, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_10, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_10_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_10_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a10" \ +#define PULSE_ENCODER_TMRA_10_CONFIG \ + { \ + .tmr_handler = CM_TMRA_10, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_10, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_10_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_10_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_10_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_10_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a10" \ } #endif /* PULSE_ENCODER_TMRA_10_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_10 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_11 #ifndef PULSE_ENCODER_TMRA_11_CONFIG -#define PULSE_ENCODER_TMRA_11_CONFIG \ - { \ - .tmr_handler = CM_TMRA_11, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_11, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_11_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_11_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a11" \ +#define PULSE_ENCODER_TMRA_11_CONFIG \ + { \ + .tmr_handler = CM_TMRA_11, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_11, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_11_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_11_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_11_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_11_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a11" \ } #endif /* PULSE_ENCODER_TMRA_11_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_11 */ #ifdef BSP_USING_PULSE_ENCODER_TMRA_12 #ifndef PULSE_ENCODER_TMRA_12_CONFIG -#define PULSE_ENCODER_TMRA_12_CONFIG \ - { \ - .tmr_handler = CM_TMRA_12, \ - .u32PeriphClock = FCG2_PERIPH_TMRA_12, \ - .hw_count = \ - { \ - .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ - .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMRA_12_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMRA_12_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_a12" \ +#define PULSE_ENCODER_TMRA_12_CONFIG \ + { \ + .tmr_handler = CM_TMRA_12, \ + .u32PeriphClock = FCG2_PERIPH_TMRA_12, \ + .hw_count = { \ + .u16CountUpCond = TMRA_CNT_UP_COND_CLKA_HIGH_CLKB_RISING, \ + .u16CountDownCond = TMRA_CNT_DOWN_COND_CLKB_HIGH_CLKA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMRA_12_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMRA_12_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMRA_12_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMRA_12_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_a12" \ } #endif /* PULSE_ENCODER_TMRA_12_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMRA_12 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_1 #ifndef PULSE_ENCODER_TMR6_1_CONFIG -#define PULSE_ENCODER_TMR6_1_CONFIG \ - { \ - .tmr_handler = CM_TMR6_1, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_61" \ +#define PULSE_ENCODER_TMR6_1_CONFIG \ + { \ + .tmr_handler = CM_TMR6_1, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_1, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_1_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_1_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_1_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_1_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_61" \ } #endif /* PULSE_ENCODER_TMR6_1_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_1 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_2 #ifndef PULSE_ENCODER_TMR6_2_CONFIG -#define PULSE_ENCODER_TMR6_2_CONFIG \ - { \ - .tmr_handler = CM_TMR6_2, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_62" \ +#define PULSE_ENCODER_TMR6_2_CONFIG \ + { \ + .tmr_handler = CM_TMR6_2, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_2, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_2_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_2_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_2_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_2_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_62" \ } #endif /* PULSE_ENCODER_TMR6_2_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_2 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_3 #ifndef PULSE_ENCODER_TMR6_3_CONFIG -#define PULSE_ENCODER_TMR6_3_CONFIG \ - { \ - .tmr_handler = CM_TMR6_3, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_63" \ +#define PULSE_ENCODER_TMR6_3_CONFIG \ + { \ + .tmr_handler = CM_TMR6_3, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_3, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_3_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_3_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_3_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_3_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_63" \ } #endif /* PULSE_ENCODER_TMR6_3_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_3 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_4 #ifndef PULSE_ENCODER_TMR6_4_CONFIG -#define PULSE_ENCODER_TMR6_4_CONFIG \ - { \ - .tmr_handler = CM_TMR6_4, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_4, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_64" \ +#define PULSE_ENCODER_TMR6_4_CONFIG \ + { \ + .tmr_handler = CM_TMR6_4, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_4, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_4_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_4_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_4_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_4_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_64" \ } #endif /* PULSE_ENCODER_TMR6_4_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_4 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_5 #ifndef PULSE_ENCODER_TMR6_5_CONFIG -#define PULSE_ENCODER_TMR6_5_CONFIG \ - { \ - .tmr_handler = CM_TMR6_5, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_5, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_65" \ +#define PULSE_ENCODER_TMR6_5_CONFIG \ + { \ + .tmr_handler = CM_TMR6_5, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_5, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_5_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_5_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_5_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_5_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_65" \ } #endif /* PULSE_ENCODER_TMR6_5_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_5 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_6 #ifndef PULSE_ENCODER_TMR6_6_CONFIG -#define PULSE_ENCODER_TMR6_6_CONFIG \ - { \ - .tmr_handler = CM_TMR6_6, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_6, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_66" \ +#define PULSE_ENCODER_TMR6_6_CONFIG \ + { \ + .tmr_handler = CM_TMR6_6, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_6, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_6_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_6_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_6_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_6_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_66" \ } #endif /* PULSE_ENCODER_TMR6_6_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_6 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_7 #ifndef PULSE_ENCODER_TMR6_7_CONFIG -#define PULSE_ENCODER_TMR6_7_CONFIG \ - { \ - .tmr_handler = CM_TMR6_7, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_7, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_67" \ +#define PULSE_ENCODER_TMR6_7_CONFIG \ + { \ + .tmr_handler = CM_TMR6_7, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_7, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_7_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_7_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_7_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_7_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_67" \ } #endif /* PULSE_ENCODER_TMR6_7_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_7 */ #ifdef BSP_USING_PULSE_ENCODER_TMR6_8 #ifndef PULSE_ENCODER_TMR6_8_CONFIG -#define PULSE_ENCODER_TMR6_8_CONFIG \ - { \ - .tmr_handler = CM_TMR6_8, \ - .u32PeriphClock = FCG2_PERIPH_TMR6_8, \ - .hw_count = \ - { \ - .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ - .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ - }, \ - .isr = \ - { \ - .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ - .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ - .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ - .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ - .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ - .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ - }, \ - .u32PeriodValue = 1000UL, \ - .name = "pulse_68" \ +#define PULSE_ENCODER_TMR6_8_CONFIG \ + { \ + .tmr_handler = CM_TMR6_8, \ + .u32PeriphClock = FCG2_PERIPH_TMR6_8, \ + .hw_count = { \ + .u32CountUpCond = TMR6_CNT_UP_COND_PWMA_HIGH_PWMB_RISING, \ + .u32CountDownCond = TMR6_CNT_DOWN_COND_PWMB_HIGH_PWMA_RISING, \ + }, \ + .isr = { \ + .enIntSrc_Ovf = INT_SRC_TMR6_8_OVF, \ + .enIRQn_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_NUM, \ + .u8Int_Prio_Ovf = BSP_PULSE_ENCODER_TMR6_8_OVF_IRQ_PRIO, \ + .enIntSrc_Udf = INT_SRC_TMR6_8_UDF, \ + .enIRQn_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_NUM, \ + .u8Int_Prio_Udf = BSP_PULSE_ENCODER_TMR6_8_UDF_IRQ_PRIO, \ + }, \ + .u32PeriodValue = 1000UL, \ + .name = "pulse_68" \ } #endif /* PULSE_ENCODER_TMR6_8_CONFIG */ #endif /* BSP_USING_PULSE_ENCODER_TMR6_8 */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pwm_tmr_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pwm_tmr_config.h index da87f320f8b..93918cd0366 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pwm_tmr_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/pwm_tmr_config.h @@ -21,372 +21,324 @@ extern "C" { #ifdef BSP_USING_PWM_TMRA_1 #ifndef PWM_TMRA_1_CONFIG -#define PWM_TMRA_1_CONFIG \ - { \ - .name = "pwm_a1", \ - .instance = CM_TMRA_1, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_1_CONFIG \ + { \ + .name = "pwm_a1", \ + .instance = CM_TMRA_1, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_1_CONFIG */ #endif /* BSP_USING_PWM_TMRA_1 */ #ifdef BSP_USING_PWM_TMRA_2 #ifndef PWM_TMRA_2_CONFIG -#define PWM_TMRA_2_CONFIG \ - { \ - .name = "pwm_a2", \ - .instance = CM_TMRA_2, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_2_CONFIG \ + { \ + .name = "pwm_a2", \ + .instance = CM_TMRA_2, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_2_CONFIG */ #endif /* BSP_USING_PWM_TMRA_2 */ #ifdef BSP_USING_PWM_TMRA_3 #ifndef PWM_TMRA_3_CONFIG -#define PWM_TMRA_3_CONFIG \ - { \ - .name = "pwm_a3", \ - .instance = CM_TMRA_3, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_3_CONFIG \ + { \ + .name = "pwm_a3", \ + .instance = CM_TMRA_3, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_3_CONFIG */ #endif /* BSP_USING_PWM_TMRA_3 */ #ifdef BSP_USING_PWM_TMRA_4 #ifndef PWM_TMRA_4_CONFIG -#define PWM_TMRA_4_CONFIG \ - { \ - .name = "pwm_a4", \ - .instance = CM_TMRA_4, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_4_CONFIG \ + { \ + .name = "pwm_a4", \ + .instance = CM_TMRA_4, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_4_CONFIG */ #endif /* BSP_USING_PWM_TMRA_4 */ #ifdef BSP_USING_PWM_TMRA_5 #ifndef PWM_TMRA_5_CONFIG -#define PWM_TMRA_5_CONFIG \ - { \ - .name = "pwm_a5", \ - .instance = CM_TMRA_5, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_5_CONFIG \ + { \ + .name = "pwm_a5", \ + .instance = CM_TMRA_5, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_5_CONFIG */ #endif /* BSP_USING_PWM_TMRA_5 */ #ifdef BSP_USING_PWM_TMRA_6 #ifndef PWM_TMRA_6_CONFIG -#define PWM_TMRA_6_CONFIG \ - { \ - .name = "pwm_a6", \ - .instance = CM_TMRA_6, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_6_CONFIG \ + { \ + .name = "pwm_a6", \ + .instance = CM_TMRA_6, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_6_CONFIG */ #endif /* BSP_USING_PWM_TMRA_6 */ #ifdef BSP_USING_PWM_TMRA_7 #ifndef PWM_TMRA_7_CONFIG -#define PWM_TMRA_7_CONFIG \ - { \ - .name = "pwm_a7", \ - .instance = CM_TMRA_7, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_7_CONFIG \ + { \ + .name = "pwm_a7", \ + .instance = CM_TMRA_7, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_7_CONFIG */ #endif /* BSP_USING_PWM_TMRA_7 */ #ifdef BSP_USING_PWM_TMRA_8 #ifndef PWM_TMRA_8_CONFIG -#define PWM_TMRA_8_CONFIG \ - { \ - .name = "pwm_a8", \ - .instance = CM_TMRA_8, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_8_CONFIG \ + { \ + .name = "pwm_a8", \ + .instance = CM_TMRA_8, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_8_CONFIG */ #endif /* BSP_USING_PWM_TMRA_8 */ #ifdef BSP_USING_PWM_TMRA_9 #ifndef PWM_TMRA_9_CONFIG -#define PWM_TMRA_9_CONFIG \ - { \ - .name = "pwm_a9", \ - .instance = CM_TMRA_9, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_9_CONFIG \ + { \ + .name = "pwm_a9", \ + .instance = CM_TMRA_9, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_9_CONFIG */ #endif /* BSP_USING_PWM_TMRA_9 */ #ifdef BSP_USING_PWM_TMRA_10 #ifndef PWM_TMRA_10_CONFIG -#define PWM_TMRA_10_CONFIG \ - { \ - .name = "pwm_a10", \ - .instance = CM_TMRA_10, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_10_CONFIG \ + { \ + .name = "pwm_a10", \ + .instance = CM_TMRA_10, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_10_CONFIG */ #endif /* BSP_USING_PWM_TMRA_10 */ #ifdef BSP_USING_PWM_TMRA_11 #ifndef PWM_TMRA_11_CONFIG -#define PWM_TMRA_11_CONFIG \ - { \ - .name = "pwm_a11", \ - .instance = CM_TMRA_11, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_11_CONFIG \ + { \ + .name = "pwm_a11", \ + .instance = CM_TMRA_11, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_11_CONFIG */ #endif /* BSP_USING_PWM_TMRA_11 */ #ifdef BSP_USING_PWM_TMRA_12 #ifndef PWM_TMRA_12_CONFIG -#define PWM_TMRA_12_CONFIG \ - { \ - .name = "pwm_a12", \ - .instance = CM_TMRA_12, \ - .channel = 0, \ - .stcTmraInit = \ - { \ - .u8CountSrc = TMRA_CNT_SRC_SW, \ - .u32PeriodValue = 0xFFFF, \ - .sw_count = \ - { \ - .u8ClockDiv = TMRA_CLK_DIV1, \ - .u8CountMode = TMRA_MD_SAWTOOTH, \ - .u8CountDir = TMRA_DIR_DOWN, \ - }, \ - .u8CountReload = TMRA_CNT_RELOAD_ENABLE\ - }, \ - .stcPwmInit = \ - { \ - .u32CompareValue = 0x0000, \ - .u16StartPolarity = TMRA_PWM_LOW, \ - .u16StopPolarity = TMRA_PWM_LOW, \ - .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ - .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ - }, \ +#define PWM_TMRA_12_CONFIG \ + { \ + .name = "pwm_a12", \ + .instance = CM_TMRA_12, \ + .channel = 0, \ + .stcTmraInit = { \ + .u8CountSrc = TMRA_CNT_SRC_SW, \ + .u32PeriodValue = 0xFFFF, \ + .sw_count = { \ + .u8ClockDiv = TMRA_CLK_DIV1, \ + .u8CountMode = TMRA_MD_SAWTOOTH, \ + .u8CountDir = TMRA_DIR_DOWN, \ + }, \ + .u8CountReload = TMRA_CNT_RELOAD_ENABLE }, \ + .stcPwmInit = { \ + .u32CompareValue = 0x0000, \ + .u16StartPolarity = TMRA_PWM_LOW, \ + .u16StopPolarity = TMRA_PWM_LOW, \ + .u16CompareMatchPolarity = TMRA_PWM_HIGH, \ + .u16PeriodMatchPolarity = TMRA_PWM_LOW, \ + }, \ } #endif /* PWM_TMRA_12_CONFIG */ #endif /* BSP_USING_PWM_TMRA_12 */ @@ -397,96 +349,87 @@ extern "C" { #ifdef BSP_USING_PWM_TMR4_1 #ifndef PWM_TMR4_1_CONFIG -#define PWM_TMR4_1_CONFIG \ - { \ - .name = "pwm_t41", \ - .instance = CM_TMR4_1, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_1_CONFIG \ + { \ + .name = "pwm_t41", \ + .instance = CM_TMR4_1, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_1_CONFIG */ #endif /* BSP_USING_PWM_TMR4_1 */ #ifdef BSP_USING_PWM_TMR4_2 #ifndef PWM_TMR4_2_CONFIG -#define PWM_TMR4_2_CONFIG \ - { \ - .name = "pwm_t42", \ - .instance = CM_TMR4_2, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_2_CONFIG \ + { \ + .name = "pwm_t42", \ + .instance = CM_TMR4_2, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_2_CONFIG */ #endif /* BSP_USING_PWM_TMR4_2 */ #ifdef BSP_USING_PWM_TMR4_3 #ifndef PWM_TMR4_3_CONFIG -#define PWM_TMR4_3_CONFIG \ - { \ - .name = "pwm_t43", \ - .instance = CM_TMR4_3, \ - .channel = 0, \ - .stcTmr4Init = \ - { \ - .u16ClockDiv = TMR4_CLK_DIV1, \ - .u16PeriodValue = 0xFFFFU, \ - .u16CountMode = TMR4_MD_SAWTOOTH, \ - .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK,\ - }, \ - .stcTmr4OcInit = \ - { \ - .u16CompareValue = 0x0000, \ - .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ - .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED,\ - .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ - .u16BufLinkTransObject = 0U, \ - }, \ - .stcTmr4PwmInit = \ - { \ - .u16Mode = TMR4_PWM_MD_THROUGH, \ - .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ - .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD,\ - }, \ +#define PWM_TMR4_3_CONFIG \ + { \ + .name = "pwm_t43", \ + .instance = CM_TMR4_3, \ + .channel = 0, \ + .stcTmr4Init = { \ + .u16ClockDiv = TMR4_CLK_DIV1, \ + .u16PeriodValue = 0xFFFFU, \ + .u16CountMode = TMR4_MD_SAWTOOTH, \ + .u16ClockSrc = TMR4_CLK_SRC_INTERNCLK, \ + }, \ + .stcTmr4OcInit = { \ + .u16CompareValue = 0x0000, \ + .u16OcInvalidPolarity = TMR4_OC_INVD_LOW, \ + .u16CompareModeBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16CompareValueBufCond = TMR4_OC_BUF_COND_IMMED, \ + .u16BufLinkTransObject = 0U, \ + }, \ + .stcTmr4PwmInit = { \ + .u16Mode = TMR4_PWM_MD_THROUGH, \ + .u16ClockDiv = TMR4_PWM_CLK_DIV1, \ + .u16Polarity = TMR4_PWM_OXH_HOLD_OXL_HOLD, \ + }, \ } #endif /* PWM_TMR4_3_CONFIG */ #endif /* BSP_USING_PWM_TMR4_3 */ @@ -497,377 +440,337 @@ extern "C" { #ifdef BSP_USING_PWM_TMR6_1 #ifndef PWM_TMR6_1_CONFIG -#define PWM_TMR6_1_CONFIG \ - { \ - .name = "pwm_t61", \ - .instance = CM_TMR6_1, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_1_CONFIG \ + { \ + .name = "pwm_t61", \ + .instance = CM_TMR6_1, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_1_CONFIG */ #endif /* BSP_USING_PWM_TMR6_1 */ #ifdef BSP_USING_PWM_TMR6_2 #ifndef PWM_TMR6_2_CONFIG -#define PWM_TMR6_2_CONFIG \ - { \ - .name = "pwm_t62", \ - .instance = CM_TMR6_2, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_2_CONFIG \ + { \ + .name = "pwm_t62", \ + .instance = CM_TMR6_2, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_2_CONFIG */ #endif /* BSP_USING_PWM_TMR6_2 */ #ifdef BSP_USING_PWM_TMR6_3 #ifndef PWM_TMR6_3_CONFIG -#define PWM_TMR6_3_CONFIG \ - { \ - .name = "pwm_t63", \ - .instance = CM_TMR6_3, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_3_CONFIG \ + { \ + .name = "pwm_t63", \ + .instance = CM_TMR6_3, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_3_CONFIG */ #endif /* BSP_USING_PWM_TMR6_3 */ #ifdef BSP_USING_PWM_TMR6_4 #ifndef PWM_TMR6_4_CONFIG -#define PWM_TMR6_4_CONFIG \ - { \ - .name = "pwm_t64", \ - .instance = CM_TMR6_4, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_4_CONFIG \ + { \ + .name = "pwm_t64", \ + .instance = CM_TMR6_4, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_4_CONFIG */ #endif /* BSP_USING_PWM_TMR6_4 */ #ifdef BSP_USING_PWM_TMR6_5 #ifndef PWM_TMR6_5_CONFIG -#define PWM_TMR6_5_CONFIG \ - { \ - .name = "pwm_t65", \ - .instance = CM_TMR6_5, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_5_CONFIG \ + { \ + .name = "pwm_t65", \ + .instance = CM_TMR6_5, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_5_CONFIG */ #endif /* BSP_USING_PWM_TMR6_5 */ #ifdef BSP_USING_PWM_TMR6_6 #ifndef PWM_TMR6_6_CONFIG -#define PWM_TMR6_6_CONFIG \ - { \ - .name = "pwm_t66", \ - .instance = CM_TMR6_6, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_6_CONFIG \ + { \ + .name = "pwm_t66", \ + .instance = CM_TMR6_6, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_6_CONFIG */ #endif /* BSP_USING_PWM_TMR6_6 */ #ifdef BSP_USING_PWM_TMR6_7 #ifndef PWM_TMR6_7_CONFIG -#define PWM_TMR6_7_CONFIG \ - { \ - .name = "pwm_t67", \ - .instance = CM_TMR6_7, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_7_CONFIG \ + { \ + .name = "pwm_t67", \ + .instance = CM_TMR6_7, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_7_CONFIG */ #endif /* BSP_USING_PWM_TMR6_7 */ #ifdef BSP_USING_PWM_TMR6_8 #ifndef PWM_TMR6_8_CONFIG -#define PWM_TMR6_8_CONFIG \ - { \ - .name = "pwm_t68", \ - .instance = CM_TMR6_8, \ - .channel = 0, \ - .stcTmr6Init = \ - { \ - .u8CountSrc = TMR6_CNT_SRC_SW, \ - .sw_count = \ - { \ - .u32ClockDiv = TMR6_CLK_DIV1, \ - .u32CountMode = TMR6_MD_SAWTOOTH, \ - .u32CountDir = TMR6_CNT_UP, \ - }, \ - .u32PeriodValue = 0xFFFF, \ - .u32CountReload = TMR6_CNT_RELOAD_ON, \ - }, \ - .stcPwmInit = \ - { \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - }, \ - { \ - .u32CompareValue = 0x0000, \ - .u32StartPolarity = TMR6_PWM_HIGH, \ - .u32StopPolarity = TMR6_PWM_HIGH, \ - .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ - .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ - .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ - .u32UdfPolarity = TMR6_PWM_HOLD, \ - .u32OvfPolarity = TMR6_PWM_HIGH, \ - } \ - }, \ +#define PWM_TMR6_8_CONFIG \ + { \ + .name = "pwm_t68", \ + .instance = CM_TMR6_8, \ + .channel = 0, \ + .stcTmr6Init = { \ + .u8CountSrc = TMR6_CNT_SRC_SW, \ + .sw_count = { \ + .u32ClockDiv = TMR6_CLK_DIV1, \ + .u32CountMode = TMR6_MD_SAWTOOTH, \ + .u32CountDir = TMR6_CNT_UP, \ + }, \ + .u32PeriodValue = 0xFFFF, \ + .u32CountReload = TMR6_CNT_RELOAD_ON, \ + }, \ + .stcPwmInit = { { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + }, \ + { \ + .u32CompareValue = 0x0000, \ + .u32StartPolarity = TMR6_PWM_HIGH, \ + .u32StopPolarity = TMR6_PWM_HIGH, \ + .u32CountUpMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountDownMatchAPolarity = TMR6_PWM_HOLD, \ + .u32CountUpMatchBPolarity = TMR6_PWM_LOW, \ + .u32CountDownMatchBPolarity = TMR6_PWM_HOLD, \ + .u32UdfPolarity = TMR6_PWM_HOLD, \ + .u32OvfPolarity = TMR6_PWM_HIGH, \ + } }, \ } #endif /* PWM_TMR6_8_CONFIG */ #endif /* BSP_USING_PWM_TMR6_8 */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/qspi_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/qspi_config.h index b8e74bfae19..929bf0a5a91 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/qspi_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/qspi_config.h @@ -20,48 +20,46 @@ extern "C" { #ifdef BSP_USING_QSPI #ifndef QSPI_BUS_CONFIG -#define QSPI_BUS_CONFIG \ - { \ - .Instance = CM_QSPI, \ - .clock = FCG1_PERIPH_QSPI, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ - .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_QSPI_INTR, \ - }, \ +#define QSPI_BUS_CONFIG \ + { \ + .Instance = CM_QSPI, \ + .clock = FCG1_PERIPH_QSPI, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_QSPI_ERR_IRQ_NUM, \ + .irq_prio = BSP_QSPI_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_QSPI_INTR, \ + }, \ } #endif /* QSPI_BUS_CONFIG */ #ifndef QSPI_INIT_PARAMS -#define QSPI_INIT_PARAMS \ - { \ - .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ - .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ - .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ - .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ +#define QSPI_INIT_PARAMS \ + { \ + .u32PrefetchMode = QSPI_PREFETCH_MD_INVD, \ + .u32SetupTime = QSPI_QSSN_SETUP_ADVANCE_QSCK0P5, \ + .u32ReleaseTime = QSPI_QSSN_RELEASE_DELAY_QSCK32, \ + .u32IntervalTime = QSPI_QSSN_INTERVAL_QSCK1, \ } #endif /* QSPI_INIT_PARAMS */ -#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH +#define QSPI_WP_PIN_LEVEL QSPI_WP_PIN_HIGH #ifdef BSP_QSPI_USING_DMA #ifndef QSPI_DMA_CONFIG -#define QSPI_DMA_CONFIG \ - { \ - .Instance = QSPI_DMA_INSTANCE, \ - .channel = QSPI_DMA_CHANNEL, \ - .clock = QSPI_DMA_CLOCK, \ - .trigger_select = QSPI_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_AOS_STRG, \ - .flag = QSPI_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = QSPI_DMA_IRQn, \ - .irq_prio = QSPI_DMA_INT_PRIO, \ - .int_src = QSPI_DMA_INT_SRC, \ - } \ +#define QSPI_DMA_CONFIG \ + { \ + .Instance = QSPI_DMA_INSTANCE, \ + .channel = QSPI_DMA_CHANNEL, \ + .clock = QSPI_DMA_CLOCK, \ + .trigger_select = QSPI_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_AOS_STRG, \ + .flag = QSPI_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = QSPI_DMA_IRQn, \ + .irq_prio = QSPI_DMA_INT_PRIO, \ + .int_src = QSPI_DMA_INT_SRC, \ + } \ } #endif /* QSPI_DMA_CONFIG */ #endif /* BSP_QSPI_USING_DMA */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/sdio_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/sdio_config.h index 8d1d1bf8977..d4219976138 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/sdio_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/sdio_config.h @@ -21,66 +21,60 @@ extern "C" { #if defined(BSP_USING_SDIO1) #ifndef SDIO1_BUS_CONFIG -#define SDIO1_BUS_CONFIG \ - { \ - .name = "sdio1", \ - .instance = CM_SDIOC1, \ - .clock = FCG1_PERIPH_SDIOC1, \ - .irq_config = \ - { \ - .irq_num = BSP_SDIO1_IRQ_NUM, \ - .irq_prio = BSP_SDIO1_IRQ_PRIO, \ - .int_src = INT_SRC_SDIOC1_SD, \ - }, \ - .dma_rx = \ - { \ - .Instance = SDIO1_RX_DMA_INSTANCE, \ - .channel = SDIO1_RX_DMA_CHANNEL, \ - .clock = SDIO1_RX_DMA_CLOCK, \ - .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC1_DMAR, \ - }, \ - .dma_tx = \ - { \ - .Instance = SDIO1_TX_DMA_INSTANCE, \ - .channel = SDIO1_TX_DMA_CHANNEL, \ - .clock = SDIO1_TX_DMA_CLOCK, \ - .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC1_DMAW, \ - }, \ +#define SDIO1_BUS_CONFIG \ + { \ + .name = "sdio1", \ + .instance = CM_SDIOC1, \ + .clock = FCG1_PERIPH_SDIOC1, \ + .irq_config = { \ + .irq_num = BSP_SDIO1_IRQ_NUM, \ + .irq_prio = BSP_SDIO1_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC1_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO1_RX_DMA_INSTANCE, \ + .channel = SDIO1_RX_DMA_CHANNEL, \ + .clock = SDIO1_RX_DMA_CLOCK, \ + .trigger_select = SDIO1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO1_TX_DMA_INSTANCE, \ + .channel = SDIO1_TX_DMA_CHANNEL, \ + .clock = SDIO1_TX_DMA_CLOCK, \ + .trigger_select = SDIO1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC1_DMAW, \ + }, \ } #endif /* SDIO1_BUS_CONFIG */ #endif /* BSP_USING_SDIO1 */ #if defined(BSP_USING_SDIO2) #ifndef SDIO2_BUS_CONFIG -#define SDIO2_BUS_CONFIG \ - { \ - .name = "sdio2", \ - .instance = CM_SDIOC2, \ - .clock = FCG1_PERIPH_SDIOC2, \ - .irq_config = \ - { \ - .irq_num = BSP_SDIO2_IRQ_NUM, \ - .irq_prio = BSP_SDIO2_IRQ_PRIO, \ - .int_src = INT_SRC_SDIOC2_SD, \ - }, \ - .dma_rx = \ - { \ - .Instance = SDIO2_RX_DMA_INSTANCE, \ - .channel = SDIO2_RX_DMA_CHANNEL, \ - .clock = SDIO2_RX_DMA_CLOCK, \ - .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC2_DMAR, \ - }, \ - .dma_tx = \ - { \ - .Instance = SDIO2_TX_DMA_INSTANCE, \ - .channel = SDIO2_TX_DMA_CHANNEL, \ - .clock = SDIO2_TX_DMA_CLOCK, \ - .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SDIOC2_DMAW, \ - }, \ +#define SDIO2_BUS_CONFIG \ + { \ + .name = "sdio2", \ + .instance = CM_SDIOC2, \ + .clock = FCG1_PERIPH_SDIOC2, \ + .irq_config = { \ + .irq_num = BSP_SDIO2_IRQ_NUM, \ + .irq_prio = BSP_SDIO2_IRQ_PRIO, \ + .int_src = INT_SRC_SDIOC2_SD, \ + }, \ + .dma_rx = { \ + .Instance = SDIO2_RX_DMA_INSTANCE, \ + .channel = SDIO2_RX_DMA_CHANNEL, \ + .clock = SDIO2_RX_DMA_CLOCK, \ + .trigger_select = SDIO2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAR, \ + }, \ + .dma_tx = { \ + .Instance = SDIO2_TX_DMA_INSTANCE, \ + .channel = SDIO2_TX_DMA_CHANNEL, \ + .clock = SDIO2_TX_DMA_CLOCK, \ + .trigger_select = SDIO2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SDIOC2_DMAW, \ + }, \ } #endif /* SDIO2_BUS_CONFIG */ #endif /* BSP_USING_SDIO2 */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/spi_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/spi_config.h index a839686bd3c..13e6acc6905 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/spi_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/spi_config.h @@ -21,134 +21,127 @@ extern "C" { #ifdef BSP_USING_SPI1 #ifndef SPI1_BUS_CONFIG -#define SPI1_BUS_CONFIG \ - { \ - .Instance = CM_SPI1, \ - .bus_name = "spi1", \ - .clock = FCG1_PERIPH_SPI1, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI1_SPEI, \ - }, \ +#define SPI1_BUS_CONFIG \ + { \ + .Instance = CM_SPI1, \ + .bus_name = "spi1", \ + .clock = FCG1_PERIPH_SPI1, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI1_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI1_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI1_SPEI, \ + }, \ } #endif /* SPI1_BUS_CONFIG */ #endif /* BSP_USING_SPI1 */ #ifdef BSP_SPI1_TX_USING_DMA #ifndef SPI1_TX_DMA_CONFIG -#define SPI1_TX_DMA_CONFIG \ - { \ - .Instance = SPI1_TX_DMA_INSTANCE, \ - .channel = SPI1_TX_DMA_CHANNEL, \ - .clock = SPI1_TX_DMA_CLOCK, \ - .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPTI, \ - .flag = SPI1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_TX_DMA_IRQn, \ - .irq_prio = SPI1_TX_DMA_INT_PRIO, \ - .int_src = SPI1_TX_DMA_INT_SRC, \ - } \ +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .clock = SPI1_TX_DMA_CLOCK, \ + .trigger_select = SPI1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPTI, \ + .flag = SPI1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_TX_DMA_CONFIG */ #endif /* BSP_SPI1_TX_USING_DMA */ #ifdef BSP_SPI1_RX_USING_DMA #ifndef SPI1_RX_DMA_CONFIG -#define SPI1_RX_DMA_CONFIG \ - { \ - .Instance = SPI1_RX_DMA_INSTANCE, \ - .channel = SPI1_RX_DMA_CHANNEL, \ - .clock = SPI1_RX_DMA_CLOCK, \ - .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI1_SPRI, \ - .flag = SPI1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI1_RX_DMA_IRQn, \ - .irq_prio = SPI1_RX_DMA_INT_PRIO, \ - .int_src = SPI1_RX_DMA_INT_SRC, \ - } \ +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .clock = SPI1_RX_DMA_CLOCK, \ + .trigger_select = SPI1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI1_SPRI, \ + .flag = SPI1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI1_RX_DMA_CONFIG */ #endif /* BSP_SPI1_RX_USING_DMA */ #ifdef BSP_USING_SPI2 #ifndef SPI2_BUS_CONFIG -#define SPI2_BUS_CONFIG \ - { \ - .Instance = CM_SPI2, \ - .bus_name = "spi2", \ - .clock = FCG1_PERIPH_SPI2, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI2_SPEI, \ - }, \ +#define SPI2_BUS_CONFIG \ + { \ + .Instance = CM_SPI2, \ + .bus_name = "spi2", \ + .clock = FCG1_PERIPH_SPI2, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI2_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI2_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI2_SPEI, \ + }, \ } #endif /* SPI2_BUS_CONFIG */ #endif /* BSP_USING_SPI2 */ #ifdef BSP_SPI2_TX_USING_DMA #ifndef SPI2_TX_DMA_CONFIG -#define SPI2_TX_DMA_CONFIG \ - { \ - .Instance = SPI2_TX_DMA_INSTANCE, \ - .channel = SPI2_TX_DMA_CHANNEL, \ - .clock = SPI2_TX_DMA_CLOCK, \ - .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPTI, \ - .flag = SPI2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_TX_DMA_IRQn, \ - .irq_prio = SPI2_TX_DMA_INT_PRIO, \ - .int_src = SPI2_TX_DMA_INT_SRC, \ - } \ +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .clock = SPI2_TX_DMA_CLOCK, \ + .trigger_select = SPI2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPTI, \ + .flag = SPI2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_TX_DMA_CONFIG */ #endif /* BSP_SPI2_TX_USING_DMA */ #ifdef BSP_SPI2_RX_USING_DMA #ifndef SPI2_RX_DMA_CONFIG -#define SPI2_RX_DMA_CONFIG \ - { \ - .Instance = SPI2_RX_DMA_INSTANCE, \ - .channel = SPI2_RX_DMA_CHANNEL, \ - .clock = SPI2_RX_DMA_CLOCK, \ - .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI2_SPRI, \ - .flag = SPI2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI2_RX_DMA_IRQn, \ - .irq_prio = SPI2_RX_DMA_INT_PRIO, \ - .int_src = SPI2_RX_DMA_INT_SRC, \ - } \ +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .clock = SPI2_RX_DMA_CLOCK, \ + .trigger_select = SPI2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI2_SPRI, \ + .flag = SPI2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI2_RX_DMA_CONFIG */ #endif /* BSP_SPI2_RX_USING_DMA */ #ifdef BSP_USING_SPI3 #ifndef SPI3_BUS_CONFIG -#define SPI3_BUS_CONFIG \ - { \ - .Instance = CM_SPI3, \ - .bus_name = "spi3", \ - .clock = FCG1_PERIPH_SPI3, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI3_SPEI, \ - }, \ +#define SPI3_BUS_CONFIG \ + { \ + .Instance = CM_SPI3, \ + .bus_name = "spi3", \ + .clock = FCG1_PERIPH_SPI3, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI3_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI3_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI3_SPEI, \ + }, \ } #endif /* SPI3_BUS_CONFIG */ #endif /* BSP_USING_SPI3 */ @@ -156,214 +149,203 @@ extern "C" { #ifdef BSP_SPI3_TX_USING_DMA #ifndef SPI3_TX_DMA_CONFIG -#define SPI3_TX_DMA_CONFIG \ - { \ - .Instance = SPI3_TX_DMA_INSTANCE, \ - .channel = SPI3_TX_DMA_CHANNEL, \ - .clock = SPI3_TX_DMA_CLOCK, \ - .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPTI, \ - .flag = SPI3_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_TX_DMA_IRQn, \ - .irq_prio = SPI3_TX_DMA_INT_PRIO, \ - .int_src = SPI3_TX_DMA_INT_SRC, \ - } \ +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .clock = SPI3_TX_DMA_CLOCK, \ + .trigger_select = SPI3_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPTI, \ + .flag = SPI3_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_TX_DMA_CONFIG */ #endif /* BSP_SPI3_TX_USING_DMA */ #ifdef BSP_SPI3_RX_USING_DMA #ifndef SPI3_RX_DMA_CONFIG -#define SPI3_RX_DMA_CONFIG \ - { \ - .Instance = SPI3_RX_DMA_INSTANCE, \ - .channel = SPI3_RX_DMA_CHANNEL, \ - .clock = SPI3_RX_DMA_CLOCK, \ - .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI3_SPRI, \ - .flag = SPI3_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI3_RX_DMA_IRQn, \ - .irq_prio = SPI3_RX_DMA_INT_PRIO, \ - .int_src = SPI3_RX_DMA_INT_SRC, \ - } \ +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .clock = SPI3_RX_DMA_CLOCK, \ + .trigger_select = SPI3_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI3_SPRI, \ + .flag = SPI3_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI3_RX_DMA_CONFIG */ #endif /* BSP_SPI3_RX_USING_DMA */ #ifdef BSP_USING_SPI4 #ifndef SPI4_BUS_CONFIG -#define SPI4_BUS_CONFIG \ - { \ - .Instance = CM_SPI4, \ - .bus_name = "spi4", \ - .clock = FCG1_PERIPH_SPI4, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI4_SPEI, \ - }, \ +#define SPI4_BUS_CONFIG \ + { \ + .Instance = CM_SPI4, \ + .bus_name = "spi4", \ + .clock = FCG1_PERIPH_SPI4, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI4_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI4_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI4_SPEI, \ + }, \ } #endif /* SPI4_BUS_CONFIG */ #endif /* BSP_USING_SPI4 */ #ifdef BSP_SPI4_TX_USING_DMA #ifndef SPI4_TX_DMA_CONFIG -#define SPI4_TX_DMA_CONFIG \ - { \ - .Instance = SPI4_TX_DMA_INSTANCE, \ - .channel = SPI4_TX_DMA_CHANNEL, \ - .clock = SPI4_TX_DMA_CLOCK, \ - .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI4_SPTI, \ - .flag = SPI4_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI4_TX_DMA_IRQn, \ - .irq_prio = SPI4_TX_DMA_INT_PRIO, \ - .int_src = SPI4_TX_DMA_INT_SRC, \ - } \ +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .clock = SPI4_TX_DMA_CLOCK, \ + .trigger_select = SPI4_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPTI, \ + .flag = SPI4_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI4_TX_DMA_CONFIG */ #endif /* BSP_SPI4_TX_USING_DMA */ #ifdef BSP_SPI4_RX_USING_DMA #ifndef SPI4_RX_DMA_CONFIG -#define SPI4_RX_DMA_CONFIG \ - { \ - .Instance = SPI4_RX_DMA_INSTANCE, \ - .channel = SPI4_RX_DMA_CHANNEL, \ - .clock = SPI4_RX_DMA_CLOCK, \ - .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI4_SPRI, \ - .flag = SPI4_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI4_RX_DMA_IRQn, \ - .irq_prio = SPI4_RX_DMA_INT_PRIO, \ - .int_src = SPI4_RX_DMA_INT_SRC, \ - } \ +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .clock = SPI4_RX_DMA_CLOCK, \ + .trigger_select = SPI4_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI4_SPRI, \ + .flag = SPI4_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI4_RX_DMA_CONFIG */ #endif /* BSP_SPI4_RX_USING_DMA */ #ifdef BSP_USING_SPI5 #ifndef SPI5_BUS_CONFIG -#define SPI5_BUS_CONFIG \ - { \ - .Instance = CM_SPI5, \ - .bus_name = "spi5", \ - .clock = FCG1_PERIPH_SPI5, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI5_SPEI, \ - }, \ +#define SPI5_BUS_CONFIG \ + { \ + .Instance = CM_SPI5, \ + .bus_name = "spi5", \ + .clock = FCG1_PERIPH_SPI5, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI5_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI5_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI5_SPEI, \ + }, \ } #endif /* SPI5_BUS_CONFIG */ #endif /* BSP_USING_SPI5 */ #ifdef BSP_SPI5_TX_USING_DMA #ifndef SPI5_TX_DMA_CONFIG -#define SPI5_TX_DMA_CONFIG \ - { \ - .Instance = SPI5_TX_DMA_INSTANCE, \ - .channel = SPI5_TX_DMA_CHANNEL, \ - .clock = SPI5_TX_DMA_CLOCK, \ - .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI5_SPTI, \ - .flag = SPI5_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI5_TX_DMA_IRQn, \ - .irq_prio = SPI5_TX_DMA_INT_PRIO, \ - .int_src = SPI5_TX_DMA_INT_SRC, \ - } \ +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .clock = SPI5_TX_DMA_CLOCK, \ + .trigger_select = SPI5_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPTI, \ + .flag = SPI5_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI5_TX_DMA_CONFIG */ #endif /* BSP_SPI5_TX_USING_DMA */ #ifdef BSP_SPI5_RX_USING_DMA #ifndef SPI5_RX_DMA_CONFIG -#define SPI5_RX_DMA_CONFIG \ - { \ - .Instance = SPI5_RX_DMA_INSTANCE, \ - .channel = SPI5_RX_DMA_CHANNEL, \ - .clock = SPI5_RX_DMA_CLOCK, \ - .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI5_SPRI, \ - .flag = SPI5_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI5_RX_DMA_IRQn, \ - .irq_prio = SPI5_RX_DMA_INT_PRIO, \ - .int_src = SPI5_RX_DMA_INT_SRC, \ - } \ +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .clock = SPI5_RX_DMA_CLOCK, \ + .trigger_select = SPI5_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI5_SPRI, \ + .flag = SPI5_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI5_RX_DMA_CONFIG */ #endif /* BSP_SPI5_RX_USING_DMA */ #ifdef BSP_USING_SPI6 #ifndef SPI6_BUS_CONFIG -#define SPI6_BUS_CONFIG \ - { \ - .Instance = CM_SPI6, \ - .bus_name = "spi6", \ - .clock = FCG1_PERIPH_SPI6, \ - .timeout = 5000UL, \ - .err_irq.irq_config = \ - { \ - .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ - .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ - .int_src = INT_SRC_SPI6_SPEI, \ - }, \ +#define SPI6_BUS_CONFIG \ + { \ + .Instance = CM_SPI6, \ + .bus_name = "spi6", \ + .clock = FCG1_PERIPH_SPI6, \ + .timeout = 5000UL, \ + .err_irq.irq_config = { \ + .irq_num = BSP_SPI6_ERR_IRQ_NUM, \ + .irq_prio = BSP_SPI6_ERR_IRQ_PRIO, \ + .int_src = INT_SRC_SPI6_SPEI, \ + }, \ } #endif /* SPI6_BUS_CONFIG */ #endif /* BSP_USING_SPI6 */ #ifdef BSP_SPI6_TX_USING_DMA #ifndef SPI6_TX_DMA_CONFIG -#define SPI6_TX_DMA_CONFIG \ - { \ - .Instance = SPI6_TX_DMA_INSTANCE, \ - .channel = SPI6_TX_DMA_CHANNEL, \ - .clock = SPI6_TX_DMA_CLOCK, \ - .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI6_SPTI, \ - .flag = SPI6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI6_TX_DMA_IRQn, \ - .irq_prio = SPI6_TX_DMA_INT_PRIO, \ - .int_src = SPI6_TX_DMA_INT_SRC, \ - } \ +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .clock = SPI6_TX_DMA_CLOCK, \ + .trigger_select = SPI6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPTI, \ + .flag = SPI6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ } #endif /* SPI6_TX_DMA_CONFIG */ #endif /* BSP_SPI6_TX_USING_DMA */ #ifdef BSP_SPI6_RX_USING_DMA #ifndef SPI6_RX_DMA_CONFIG -#define SPI6_RX_DMA_CONFIG \ - { \ - .Instance = SPI6_RX_DMA_INSTANCE, \ - .channel = SPI6_RX_DMA_CHANNEL, \ - .clock = SPI6_RX_DMA_CLOCK, \ - .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_SPI6_SPRI, \ - .flag = SPI6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = SPI6_RX_DMA_IRQn, \ - .irq_prio = SPI6_RX_DMA_INT_PRIO, \ - .int_src = SPI6_RX_DMA_INT_SRC, \ - } \ +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .clock = SPI6_RX_DMA_CLOCK, \ + .trigger_select = SPI6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_SPI6_SPRI, \ + .flag = SPI6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ } #endif /* SPI6_RX_DMA_CONFIG */ #endif /* BSP_SPI6_RX_USING_DMA */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/timer_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/timer_config.h index 553ffc86293..414a64a3652 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/timer_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/timer_config.h @@ -19,228 +19,216 @@ extern "C" { #ifdef BSP_USING_TMRA_1 #ifndef TMRA_1_CONFIG -#define TMRA_1_CONFIG \ - { \ - .tmr_handle = CM_TMRA_1, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_1, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_1_OVF, \ - .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ - }, \ - .name = "tmra_1" \ +#define TMRA_1_CONFIG \ + { \ + .tmr_handle = CM_TMRA_1, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_1, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_1_OVF, \ + .enIRQn = BSP_USING_TMRA_1_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_1_IRQ_PRIO, \ + }, \ + .name = "tmra_1" \ } #endif /* TMRA_1_CONFIG */ #endif /* BSP_USING_TMRA_1 */ #ifdef BSP_USING_TMRA_2 #ifndef TMRA_2_CONFIG -#define TMRA_2_CONFIG \ - { \ - .tmr_handle = CM_TMRA_2, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_2, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_2_OVF, \ - .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ - }, \ - .name = "tmra_2" \ +#define TMRA_2_CONFIG \ + { \ + .tmr_handle = CM_TMRA_2, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_2, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_2_OVF, \ + .enIRQn = BSP_USING_TMRA_2_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_2_IRQ_PRIO, \ + }, \ + .name = "tmra_2" \ } #endif /* TMRA_2_CONFIG */ #endif /* BSP_USING_TMRA_2 */ #ifdef BSP_USING_TMRA_3 #ifndef TMRA_3_CONFIG -#define TMRA_3_CONFIG \ - { \ - .tmr_handle = CM_TMRA_3, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_3, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_3_OVF, \ - .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ - }, \ - .name = "tmra_3" \ +#define TMRA_3_CONFIG \ + { \ + .tmr_handle = CM_TMRA_3, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_3, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_3_OVF, \ + .enIRQn = BSP_USING_TMRA_3_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_3_IRQ_PRIO, \ + }, \ + .name = "tmra_3" \ } #endif /* TMRA_3_CONFIG */ #endif /* BSP_USING_TMRA_3 */ #ifdef BSP_USING_TMRA_4 #ifndef TMRA_4_CONFIG -#define TMRA_4_CONFIG \ - { \ - .tmr_handle = CM_TMRA_4, \ - .clock_source = CLK_BUS_PCLK0, \ - .clock = FCG2_PERIPH_TMRA_4, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_4_OVF, \ - .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ - }, \ - .name = "tmra_4" \ +#define TMRA_4_CONFIG \ + { \ + .tmr_handle = CM_TMRA_4, \ + .clock_source = CLK_BUS_PCLK0, \ + .clock = FCG2_PERIPH_TMRA_4, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_4_OVF, \ + .enIRQn = BSP_USING_TMRA_4_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_4_IRQ_PRIO, \ + }, \ + .name = "tmra_4" \ } #endif /* TMRA_4_CONFIG */ #endif /* BSP_USING_TMRA_4 */ #ifdef BSP_USING_TMRA_5 #ifndef TMRA_5_CONFIG -#define TMRA_5_CONFIG \ - { \ - .tmr_handle = CM_TMRA_5, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_5, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_5_OVF, \ - .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ - }, \ - .name = "tmra_5" \ +#define TMRA_5_CONFIG \ + { \ + .tmr_handle = CM_TMRA_5, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_5, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_5_OVF, \ + .enIRQn = BSP_USING_TMRA_5_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_5_IRQ_PRIO, \ + }, \ + .name = "tmra_5" \ } #endif /* TMRA_5_CONFIG */ #endif /* BSP_USING_TMRA_5 */ #ifdef BSP_USING_TMRA_6 #ifndef TMRA_6_CONFIG -#define TMRA_6_CONFIG \ - { \ - .tmr_handle = CM_TMRA_6, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_6, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_6_OVF, \ - .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ - }, \ - .name = "tmra_6" \ +#define TMRA_6_CONFIG \ + { \ + .tmr_handle = CM_TMRA_6, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_6, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_6_OVF, \ + .enIRQn = BSP_USING_TMRA_6_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_6_IRQ_PRIO, \ + }, \ + .name = "tmra_6" \ } #endif /* TMRA_6_CONFIG */ #endif /* BSP_USING_TMRA_6 */ #ifdef BSP_USING_TMRA_7 #ifndef TMRA_7_CONFIG -#define TMRA_7_CONFIG \ - { \ - .tmr_handle = CM_TMRA_7, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_7, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_7_OVF, \ - .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ - }, \ - .name = "tmra_7" \ +#define TMRA_7_CONFIG \ + { \ + .tmr_handle = CM_TMRA_7, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_7, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_7_OVF, \ + .enIRQn = BSP_USING_TMRA_7_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_7_IRQ_PRIO, \ + }, \ + .name = "tmra_7" \ } #endif /* TMRA_7_CONFIG */ #endif /* BSP_USING_TMRA_7 */ #ifdef BSP_USING_TMRA_8 #ifndef TMRA_8_CONFIG -#define TMRA_8_CONFIG \ - { \ - .tmr_handle = CM_TMRA_8, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_8, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_8_OVF, \ - .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ - }, \ - .name = "tmra_8" \ +#define TMRA_8_CONFIG \ + { \ + .tmr_handle = CM_TMRA_8, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_8, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_8_OVF, \ + .enIRQn = BSP_USING_TMRA_8_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_8_IRQ_PRIO, \ + }, \ + .name = "tmra_8" \ } #endif /* TMRA_8_CONFIG */ #endif /* BSP_USING_TMRA_8 */ #ifdef BSP_USING_TMRA_9 #ifndef TMRA_9_CONFIG -#define TMRA_9_CONFIG \ - { \ - .tmr_handle = CM_TMRA_9, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_9, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_9_OVF, \ - .enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \ - }, \ - .name = "tmra_9" \ +#define TMRA_9_CONFIG \ + { \ + .tmr_handle = CM_TMRA_9, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_9, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_9_OVF, \ + .enIRQn = BSP_USING_TMRA_9_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_9_IRQ_PRIO, \ + }, \ + .name = "tmra_9" \ } #endif /* TMRA_9_CONFIG */ #endif /* BSP_USING_TMRA_9 */ #ifdef BSP_USING_TMRA_10 #ifndef TMRA_10_CONFIG -#define TMRA_10_CONFIG \ - { \ - .tmr_handle = CM_TMRA_10, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_10, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_10_OVF, \ - .enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \ - }, \ - .name = "tmra_10" \ +#define TMRA_10_CONFIG \ + { \ + .tmr_handle = CM_TMRA_10, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_10, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_10_OVF, \ + .enIRQn = BSP_USING_TMRA_10_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_10_IRQ_PRIO, \ + }, \ + .name = "tmra_10" \ } #endif /* TMRA_10_CONFIG */ #endif /* BSP_USING_TMRA_10 */ #ifdef BSP_USING_TMRA_11 #ifndef TMRA_11_CONFIG -#define TMRA_11_CONFIG \ - { \ - .tmr_handle = CM_TMRA_11, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_11, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_11_OVF, \ - .enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \ - }, \ - .name = "tmra_11" \ +#define TMRA_11_CONFIG \ + { \ + .tmr_handle = CM_TMRA_11, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_11, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_11_OVF, \ + .enIRQn = BSP_USING_TMRA_11_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_11_IRQ_PRIO, \ + }, \ + .name = "tmra_11" \ } #endif /* TMRA_11_CONFIG */ #endif /* BSP_USING_TMRA_11 */ #ifdef BSP_USING_TMRA_12 #ifndef TMRA_12_CONFIG -#define TMRA_12_CONFIG \ - { \ - .tmr_handle = CM_TMRA_12, \ - .clock_source = CLK_BUS_PCLK1, \ - .clock = FCG2_PERIPH_TMRA_12, \ - .flag = TMRA_FLAG_OVF, \ - .isr = \ - { \ - .enIntSrc = INT_SRC_TMRA_12_OVF, \ - .enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \ - .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \ - }, \ - .name = "tmra_12" \ +#define TMRA_12_CONFIG \ + { \ + .tmr_handle = CM_TMRA_12, \ + .clock_source = CLK_BUS_PCLK1, \ + .clock = FCG2_PERIPH_TMRA_12, \ + .flag = TMRA_FLAG_OVF, \ + .isr = { \ + .enIntSrc = INT_SRC_TMRA_12_OVF, \ + .enIRQn = BSP_USING_TMRA_12_IRQ_NUM, \ + .u8Int_Prio = BSP_USING_TMRA_12_IRQ_PRIO, \ + }, \ + .name = "tmra_12" \ } #endif /* TMRA_12_CONFIG */ #endif /* BSP_USING_TMRA_12 */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/uart_config.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/uart_config.h index e69b988d002..41ce84ae289 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/uart_config.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/uart_config.h @@ -21,110 +21,102 @@ extern "C" { #if defined(BSP_USING_UART1) #ifndef UART1_CONFIG -#define UART1_CONFIG \ - { \ - .name = "uart1", \ - .Instance = CM_USART1, \ - .clock = FCG3_PERIPH_USART1, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_RX_IRQ_NUM, \ - .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART1_TX_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TI, \ - }, \ +#define UART1_CONFIG \ + { \ + .name = "uart1", \ + .Instance = CM_USART1, \ + .clock = FCG3_PERIPH_USART1, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART1_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART1_RX_IRQ_NUM, \ + .irq_prio = BSP_UART1_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART1_TX_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TI, \ + }, \ } #endif /* UART1_CONFIG */ #if defined(BSP_UART1_RX_USING_DMA) #ifndef UART1_DMA_RX_CONFIG -#define UART1_DMA_RX_CONFIG \ - { \ - .Instance = UART1_RX_DMA_INSTANCE, \ - .channel = UART1_RX_DMA_CHANNEL, \ - .clock = UART1_RX_DMA_CLOCK, \ - .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_RI, \ - .flag = UART1_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_RX_DMA_IRQn, \ - .irq_prio = UART1_RX_DMA_INT_PRIO, \ - .int_src = UART1_RX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_RX_CONFIG \ + { \ + .Instance = UART1_RX_DMA_INSTANCE, \ + .channel = UART1_RX_DMA_CHANNEL, \ + .clock = UART1_RX_DMA_CLOCK, \ + .trigger_select = UART1_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_RI, \ + .flag = UART1_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_RX_DMA_IRQn, \ + .irq_prio = UART1_RX_DMA_INT_PRIO, \ + .int_src = UART1_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_RX_CONFIG */ #ifndef UART1_RXTO_CONFIG -#define UART1_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_RTO, \ - }, \ +#define UART1_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART1_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART1_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_RTO, \ + }, \ } #endif /* UART1_RXTO_CONFIG */ #endif /* BSP_UART1_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART1_TX_CPLT_CONFIG -#define UART1_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART1_TCI, \ - }, \ +#define UART1_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART1_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART1_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART1_TCI, \ + }, \ } #endif #endif /* UART1_TX_CPLT_CONFIG */ #if defined(BSP_UART1_TX_USING_DMA) #ifndef UART1_DMA_TX_CONFIG -#define UART1_DMA_TX_CONFIG \ - { \ - .Instance = UART1_TX_DMA_INSTANCE, \ - .channel = UART1_TX_DMA_CHANNEL, \ - .clock = UART1_TX_DMA_CLOCK, \ - .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART1_TI, \ - .flag = UART1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART1_TX_DMA_IRQn, \ - .irq_prio = UART1_TX_DMA_INT_PRIO, \ - .int_src = UART1_TX_DMA_INT_SRC, \ - }, \ +#define UART1_DMA_TX_CONFIG \ + { \ + .Instance = UART1_TX_DMA_INSTANCE, \ + .channel = UART1_TX_DMA_CHANNEL, \ + .clock = UART1_TX_DMA_CLOCK, \ + .trigger_select = UART1_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART1_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART1_TX_DMA_IRQn, \ + .irq_prio = UART1_TX_DMA_INT_PRIO, \ + .int_src = UART1_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART1_DMA_TX_CONFIG */ #endif /* BSP_UART1_TX_USING_DMA */ @@ -132,110 +124,102 @@ extern "C" { #if defined(BSP_USING_UART2) #ifndef UART2_CONFIG -#define UART2_CONFIG \ - { \ - .name = "uart2", \ - .Instance = CM_USART2, \ - .clock = FCG3_PERIPH_USART2, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_RX_IRQ_NUM, \ - .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART2_TX_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TI, \ - }, \ +#define UART2_CONFIG \ + { \ + .name = "uart2", \ + .Instance = CM_USART2, \ + .clock = FCG3_PERIPH_USART2, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART2_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART2_RX_IRQ_NUM, \ + .irq_prio = BSP_UART2_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART2_TX_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TI, \ + }, \ } #endif /* UART2_CONFIG */ #if defined(BSP_UART2_RX_USING_DMA) #ifndef UART2_DMA_RX_CONFIG -#define UART2_DMA_RX_CONFIG \ - { \ - .Instance = UART2_RX_DMA_INSTANCE, \ - .channel = UART2_RX_DMA_CHANNEL, \ - .clock = UART2_RX_DMA_CLOCK, \ - .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_RI, \ - .flag = UART2_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_RX_DMA_IRQn, \ - .irq_prio = UART2_RX_DMA_INT_PRIO, \ - .int_src = UART2_RX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_RX_CONFIG \ + { \ + .Instance = UART2_RX_DMA_INSTANCE, \ + .channel = UART2_RX_DMA_CHANNEL, \ + .clock = UART2_RX_DMA_CLOCK, \ + .trigger_select = UART2_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_RI, \ + .flag = UART2_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_RX_DMA_IRQn, \ + .irq_prio = UART2_RX_DMA_INT_PRIO, \ + .int_src = UART2_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_RX_CONFIG */ #ifndef UART2_RXTO_CONFIG -#define UART2_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_1, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_1, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_RTO, \ - }, \ +#define UART2_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_1, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_1, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART2_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART2_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_RTO, \ + }, \ } #endif /* UART2_RXTO_CONFIG */ #endif /* BSP_UART2_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART2_TX_CPLT_CONFIG -#define UART2_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART2_TCI, \ - }, \ +#define UART2_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART2_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART2_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART2_TCI, \ + }, \ } #endif #endif /* UART2_TX_CPLT_CONFIG */ #if defined(BSP_UART2_TX_USING_DMA) #ifndef UART2_DMA_TX_CONFIG -#define UART2_DMA_TX_CONFIG \ - { \ - .Instance = UART2_TX_DMA_INSTANCE, \ - .channel = UART2_TX_DMA_CHANNEL, \ - .clock = UART2_TX_DMA_CLOCK, \ - .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART2_TI, \ - .flag = UART2_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART2_TX_DMA_IRQn, \ - .irq_prio = UART2_TX_DMA_INT_PRIO, \ - .int_src = UART2_TX_DMA_INT_SRC, \ - }, \ +#define UART2_DMA_TX_CONFIG \ + { \ + .Instance = UART2_TX_DMA_INSTANCE, \ + .channel = UART2_TX_DMA_CHANNEL, \ + .clock = UART2_TX_DMA_CLOCK, \ + .trigger_select = UART2_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART2_TI, \ + .flag = UART2_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART2_TX_DMA_IRQn, \ + .irq_prio = UART2_TX_DMA_INT_PRIO, \ + .int_src = UART2_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART2_DMA_TX_CONFIG */ #endif /* BSP_UART2_TX_USING_DMA */ @@ -243,42 +227,38 @@ extern "C" { #if defined(BSP_USING_UART3) #ifndef UART3_CONFIG -#define UART3_CONFIG \ - { \ - .name = "uart3", \ - .Instance = CM_USART3, \ - .clock = FCG3_PERIPH_USART3, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_RX_IRQ_NUM, \ - .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART3_TX_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TI, \ - }, \ +#define UART3_CONFIG \ + { \ + .name = "uart3", \ + .Instance = CM_USART3, \ + .clock = FCG3_PERIPH_USART3, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART3_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART3_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART3_RX_IRQ_NUM, \ + .irq_prio = BSP_UART3_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART3_TX_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TI, \ + }, \ } #endif /* UART3_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART3_TX_CPLT_CONFIG -#define UART3_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART3_TCI, \ - }, \ +#define UART3_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART3_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART3_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART3_TCI, \ + }, \ } #endif #endif /* UART3_TX_CPLT_CONFIG */ @@ -286,42 +266,38 @@ extern "C" { #if defined(BSP_USING_UART4) #ifndef UART4_CONFIG -#define UART4_CONFIG \ - { \ - .name = "uart4", \ - .Instance = CM_USART4, \ - .clock = FCG3_PERIPH_USART4, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_RX_IRQ_NUM, \ - .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART4_TX_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TI, \ - }, \ +#define UART4_CONFIG \ + { \ + .name = "uart4", \ + .Instance = CM_USART4, \ + .clock = FCG3_PERIPH_USART4, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART4_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART4_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART4_RX_IRQ_NUM, \ + .irq_prio = BSP_UART4_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART4_TX_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TI, \ + }, \ } #endif /* UART4_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART4_TX_CPLT_CONFIG -#define UART4_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART4_TCI, \ - }, \ +#define UART4_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART4_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART4_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART4_TCI, \ + }, \ } #endif #endif /* UART4_TX_CPLT_CONFIG */ @@ -329,42 +305,38 @@ extern "C" { #if defined(BSP_USING_UART5) #ifndef UART5_CONFIG -#define UART5_CONFIG \ - { \ - .name = "uart5", \ - .Instance = CM_USART5, \ - .clock = FCG3_PERIPH_USART5, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART5_RX_IRQ_NUM, \ - .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART5_TX_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TI, \ - }, \ +#define UART5_CONFIG \ + { \ + .name = "uart5", \ + .Instance = CM_USART5, \ + .clock = FCG3_PERIPH_USART5, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART5_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART5_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART5_RX_IRQ_NUM, \ + .irq_prio = BSP_UART5_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART5_TX_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TI, \ + }, \ } #endif /* UART5_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART5_TX_CPLT_CONFIG -#define UART5_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART5_TCI, \ - }, \ +#define UART5_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART5_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART5_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART5_TCI, \ + }, \ } #endif #endif /* UART5_TX_CPLT_CONFIG */ @@ -372,110 +344,102 @@ extern "C" { #if defined(BSP_USING_UART6) #ifndef UART6_CONFIG -#define UART6_CONFIG \ - { \ - .name = "uart6", \ - .Instance = CM_USART6, \ - .clock = FCG3_PERIPH_USART6, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART6_RX_IRQ_NUM, \ - .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART6_TX_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TI, \ - }, \ +#define UART6_CONFIG \ + { \ + .name = "uart6", \ + .Instance = CM_USART6, \ + .clock = FCG3_PERIPH_USART6, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART6_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART6_RX_IRQ_NUM, \ + .irq_prio = BSP_UART6_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART6_TX_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TI, \ + }, \ } #endif /* UART6_CONFIG */ #if defined(BSP_UART6_RX_USING_DMA) #ifndef UART6_DMA_RX_CONFIG -#define UART6_DMA_RX_CONFIG \ - { \ - .Instance = UART6_RX_DMA_INSTANCE, \ - .channel = UART6_RX_DMA_CHANNEL, \ - .clock = UART6_RX_DMA_CLOCK, \ - .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART6_RI, \ - .flag = UART6_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART6_RX_DMA_IRQn, \ - .irq_prio = UART6_RX_DMA_INT_PRIO, \ - .int_src = UART6_RX_DMA_INT_SRC, \ - }, \ +#define UART6_DMA_RX_CONFIG \ + { \ + .Instance = UART6_RX_DMA_INSTANCE, \ + .channel = UART6_RX_DMA_CHANNEL, \ + .clock = UART6_RX_DMA_CLOCK, \ + .trigger_select = UART6_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_RI, \ + .flag = UART6_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART6_RX_DMA_IRQn, \ + .irq_prio = UART6_RX_DMA_INT_PRIO, \ + .int_src = UART6_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART6_DMA_RX_CONFIG */ #ifndef UART6_RXTO_CONFIG -#define UART6_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_A, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_RTO, \ - }, \ +#define UART6_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_A, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART6_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART6_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_RTO, \ + }, \ } #endif /* UART6_RXTO_CONFIG */ #endif /* BSP_UART6_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART6_TX_USING_DMA) #ifndef UART6_TX_CPLT_CONFIG -#define UART6_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TCI, \ - }, \ +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART6_TX_CPLT_CONFIG -#define UART6_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART6_TCI, \ - }, \ +#define UART6_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART6_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART6_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART6_TCI, \ + }, \ } #endif #endif /* UART6_TX_CPLT_CONFIG */ #if defined(BSP_UART6_TX_USING_DMA) #ifndef UART6_DMA_TX_CONFIG -#define UART6_DMA_TX_CONFIG \ - { \ - .Instance = UART6_TX_DMA_INSTANCE, \ - .channel = UART6_TX_DMA_CHANNEL, \ - .clock = UART6_TX_DMA_CLOCK, \ - .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART6_TI, \ - .flag = UART6_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART6_TX_DMA_IRQn, \ - .irq_prio = UART6_TX_DMA_INT_PRIO, \ - .int_src = UART6_TX_DMA_INT_SRC, \ - }, \ +#define UART6_DMA_TX_CONFIG \ + { \ + .Instance = UART6_TX_DMA_INSTANCE, \ + .channel = UART6_TX_DMA_CHANNEL, \ + .clock = UART6_TX_DMA_CLOCK, \ + .trigger_select = UART6_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART6_TI, \ + .flag = UART6_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART6_TX_DMA_IRQn, \ + .irq_prio = UART6_TX_DMA_INT_PRIO, \ + .int_src = UART6_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART6_DMA_TX_CONFIG */ #endif /* BSP_UART6_TX_USING_DMA */ @@ -483,110 +447,102 @@ extern "C" { #if defined(BSP_USING_UART7) #ifndef UART7_CONFIG -#define UART7_CONFIG \ - { \ - .name = "uart7", \ - .Instance = CM_USART7, \ - .clock = FCG3_PERIPH_USART7, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART7_RX_IRQ_NUM, \ - .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART7_TX_IRQ_NUM, \ - .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_TI, \ - }, \ +#define UART7_CONFIG \ + { \ + .name = "uart7", \ + .Instance = CM_USART7, \ + .clock = FCG3_PERIPH_USART7, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART7_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART7_RX_IRQ_NUM, \ + .irq_prio = BSP_UART7_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART7_TX_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TI, \ + }, \ } #endif /* UART7_CONFIG */ #if defined(BSP_UART7_RX_USING_DMA) #ifndef UART7_DMA_RX_CONFIG -#define UART7_DMA_RX_CONFIG \ - { \ - .Instance = UART7_RX_DMA_INSTANCE, \ - .channel = UART7_RX_DMA_CHANNEL, \ - .clock = UART7_RX_DMA_CLOCK, \ - .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART7_RI, \ - .flag = UART7_RX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART7_RX_DMA_IRQn, \ - .irq_prio = UART7_RX_DMA_INT_PRIO, \ - .int_src = UART7_RX_DMA_INT_SRC, \ - }, \ +#define UART7_DMA_RX_CONFIG \ + { \ + .Instance = UART7_RX_DMA_INSTANCE, \ + .channel = UART7_RX_DMA_CHANNEL, \ + .clock = UART7_RX_DMA_CLOCK, \ + .trigger_select = UART7_RX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_RI, \ + .flag = UART7_RX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART7_RX_DMA_IRQn, \ + .irq_prio = UART7_RX_DMA_INT_PRIO, \ + .int_src = UART7_RX_DMA_INT_SRC, \ + }, \ } #endif /* UART7_DMA_RX_CONFIG */ #ifndef UART7_RXTO_CONFIG -#define UART7_RXTO_CONFIG \ - { \ - .TMR0_Instance = CM_TMR0_2, \ - .channel = TMR0_CH_B, \ - .clock = FCG2_PERIPH_TMR0_2, \ - .timeout_bits = 20UL, \ - .irq_config = \ - { \ - .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ - .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_RTO, \ - }, \ +#define UART7_RXTO_CONFIG \ + { \ + .TMR0_Instance = CM_TMR0_2, \ + .channel = TMR0_CH_B, \ + .clock = FCG2_PERIPH_TMR0_2, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq_num = BSP_UART7_RXTO_IRQ_NUM, \ + .irq_prio = BSP_UART7_RXTO_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_RTO, \ + }, \ } #endif /* UART7_RXTO_CONFIG */ #endif /* BSP_UART7_RX_USING_DMA */ #if defined(RT_USING_SERIAL_V1) && defined(BSP_UART7_TX_USING_DMA) #ifndef UART7_TX_CPLT_CONFIG -#define UART7_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_TCI, \ - }, \ +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ } #endif #elif defined(RT_USING_SERIAL_V2) #ifndef UART7_TX_CPLT_CONFIG -#define UART7_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART7_TCI, \ - }, \ +#define UART7_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART7_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART7_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART7_TCI, \ + }, \ } #endif #endif /* UART7_TX_CPLT_CONFIG */ #if defined(BSP_UART7_TX_USING_DMA) #ifndef UART7_DMA_TX_CONFIG -#define UART7_DMA_TX_CONFIG \ - { \ - .Instance = UART7_TX_DMA_INSTANCE, \ - .channel = UART7_TX_DMA_CHANNEL, \ - .clock = UART7_TX_DMA_CLOCK, \ - .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ - .trigger_event = EVT_SRC_USART7_TI, \ - .flag = UART1_TX_DMA_TRANS_FLAG, \ - .irq_config = \ - { \ - .irq_num = UART7_TX_DMA_IRQn, \ - .irq_prio = UART7_TX_DMA_INT_PRIO, \ - .int_src = UART7_TX_DMA_INT_SRC, \ - }, \ +#define UART7_DMA_TX_CONFIG \ + { \ + .Instance = UART7_TX_DMA_INSTANCE, \ + .channel = UART7_TX_DMA_CHANNEL, \ + .clock = UART7_TX_DMA_CLOCK, \ + .trigger_select = UART7_TX_DMA_TRIG_SELECT, \ + .trigger_event = EVT_SRC_USART7_TI, \ + .flag = UART1_TX_DMA_TRANS_FLAG, \ + .irq_config = { \ + .irq_num = UART7_TX_DMA_IRQn, \ + .irq_prio = UART7_TX_DMA_INT_PRIO, \ + .int_src = UART7_TX_DMA_INT_SRC, \ + }, \ } #endif /* UART7_DMA_TX_CONFIG */ #endif /* BSP_UART7_TX_USING_DMA */ @@ -594,42 +550,38 @@ extern "C" { #if defined(BSP_USING_UART8) #ifndef UART8_CONFIG -#define UART8_CONFIG \ - { \ - .name = "uart8", \ - .Instance = CM_USART8, \ - .clock = FCG3_PERIPH_USART8, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART8_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART8_RX_IRQ_NUM, \ - .irq_prio = BSP_UART8_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART8_TX_IRQ_NUM, \ - .irq_prio = BSP_UART8_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_TI, \ - }, \ +#define UART8_CONFIG \ + { \ + .name = "uart8", \ + .Instance = CM_USART8, \ + .clock = FCG3_PERIPH_USART8, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART8_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART8_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART8_RX_IRQ_NUM, \ + .irq_prio = BSP_UART8_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART8_TX_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TI, \ + }, \ } #endif /* UART8_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART8_TX_CPLT_CONFIG -#define UART8_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART8_TCI, \ - }, \ +#define UART8_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART8_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART8_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART8_TCI, \ + }, \ } #endif #endif /* UART8_TX_CPLT_CONFIG */ @@ -637,42 +589,38 @@ extern "C" { #if defined(BSP_USING_UART9) #ifndef UART9_CONFIG -#define UART9_CONFIG \ - { \ - .name = "uart9", \ - .Instance = CM_USART9, \ - .clock = FCG3_PERIPH_USART9, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART9_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART9_RX_IRQ_NUM, \ - .irq_prio = BSP_UART9_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART9_TX_IRQ_NUM, \ - .irq_prio = BSP_UART9_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_TI, \ - }, \ +#define UART9_CONFIG \ + { \ + .name = "uart9", \ + .Instance = CM_USART9, \ + .clock = FCG3_PERIPH_USART9, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART9_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART9_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART9_RX_IRQ_NUM, \ + .irq_prio = BSP_UART9_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART9_TX_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TI, \ + }, \ } #endif /* UART9_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART9_TX_CPLT_CONFIG -#define UART9_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART9_TCI, \ - }, \ +#define UART9_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART9_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART9_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART9_TCI, \ + }, \ } #endif #endif /* UART9_TX_CPLT_CONFIG */ @@ -680,42 +628,38 @@ extern "C" { #if defined(BSP_USING_UART10) #ifndef UART10_CONFIG -#define UART10_CONFIG \ - { \ - .name = "uart10", \ - .Instance = CM_USART10, \ - .clock = FCG3_PERIPH_USART10, \ - .rxerr_irq.irq_config = \ - { \ - .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ - .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_EI, \ - }, \ - .rx_irq.irq_config = \ - { \ - .irq_num = BSP_UART10_RX_IRQ_NUM, \ - .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_RI, \ - }, \ - .tx_irq.irq_config = \ - { \ - .irq_num = BSP_UART10_TX_IRQ_NUM, \ - .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_TI, \ - }, \ +#define UART10_CONFIG \ + { \ + .name = "uart10", \ + .Instance = CM_USART10, \ + .clock = FCG3_PERIPH_USART10, \ + .rxerr_irq.irq_config = { \ + .irq_num = BSP_UART10_RXERR_IRQ_NUM, \ + .irq_prio = BSP_UART10_RXERR_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_EI, \ + }, \ + .rx_irq.irq_config = { \ + .irq_num = BSP_UART10_RX_IRQ_NUM, \ + .irq_prio = BSP_UART10_RX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_RI, \ + }, \ + .tx_irq.irq_config = { \ + .irq_num = BSP_UART10_TX_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TI, \ + }, \ } #endif /* UART10_CONFIG */ #if defined(RT_USING_SERIAL_V2) #ifndef UART10_TX_CPLT_CONFIG -#define UART10_TX_CPLT_CONFIG \ - { \ - .irq_config = \ - { \ - .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ - .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ - .int_src = INT_SRC_USART10_TCI, \ - }, \ +#define UART10_TX_CPLT_CONFIG \ + { \ + .irq_config = { \ + .irq_num = BSP_UART10_TX_CPLT_IRQ_NUM, \ + .irq_prio = BSP_UART10_TX_CPLT_IRQ_PRIO, \ + .int_src = INT_SRC_USART10_TCI, \ + }, \ } #endif #endif /* UART10_TX_CPLT_CONFIG */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_app_conf.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_app_conf.h index 2781afa72f4..53c20e1b517 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_app_conf.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_app_conf.h @@ -13,8 +13,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -61,71 +60,71 @@ USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment #ifndef USB_HS_MODE #ifndef USB_FS_MODE -#error "USB_HS_MODE or USB_FS_MODE should be defined" +#error "USB_HS_MODE or USB_FS_MODE should be defined" #endif #endif #ifndef USE_DEVICE_MODE #ifndef USE_HOST_MODE -#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" +#error "USE_DEVICE_MODE or USE_HOST_MODE should be defined" #endif #endif #if defined(BSP_USING_USBD) /* USB DEVICE FIFO CONFIGURATION */ #ifdef USB_FS_MODE -#define RX_FIFO_FS_SIZE (128U) -#define TX0_FIFO_FS_SIZE (32U) -#define TX1_FIFO_FS_SIZE (32U) -#define TX2_FIFO_FS_SIZE (32U) -#define TX3_FIFO_FS_SIZE (32U) -#define TX4_FIFO_FS_SIZE (32U) -#define TX5_FIFO_FS_SIZE (32U) -#define TX6_FIFO_FS_SIZE (32U) -#define TX7_FIFO_FS_SIZE (32U) -#define TX8_FIFO_FS_SIZE (32U) -#define TX9_FIFO_FS_SIZE (32U) -#define TX10_FIFO_FS_SIZE (32U) -#define TX11_FIFO_FS_SIZE (32U) -#define TX12_FIFO_FS_SIZE (32U) -#define TX13_FIFO_FS_SIZE (32U) -#define TX14_FIFO_FS_SIZE (32U) -#define TX15_FIFO_FS_SIZE (32U) - -#if ((RX_FIFO_FS_SIZE + \ - TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ - TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ +#define RX_FIFO_FS_SIZE (128U) +#define TX0_FIFO_FS_SIZE (32U) +#define TX1_FIFO_FS_SIZE (32U) +#define TX2_FIFO_FS_SIZE (32U) +#define TX3_FIFO_FS_SIZE (32U) +#define TX4_FIFO_FS_SIZE (32U) +#define TX5_FIFO_FS_SIZE (32U) +#define TX6_FIFO_FS_SIZE (32U) +#define TX7_FIFO_FS_SIZE (32U) +#define TX8_FIFO_FS_SIZE (32U) +#define TX9_FIFO_FS_SIZE (32U) +#define TX10_FIFO_FS_SIZE (32U) +#define TX11_FIFO_FS_SIZE (32U) +#define TX12_FIFO_FS_SIZE (32U) +#define TX13_FIFO_FS_SIZE (32U) +#define TX14_FIFO_FS_SIZE (32U) +#define TX15_FIFO_FS_SIZE (32U) + +#if ((RX_FIFO_FS_SIZE + \ + TX0_FIFO_FS_SIZE + TX1_FIFO_FS_SIZE + TX2_FIFO_FS_SIZE + TX3_FIFO_FS_SIZE + TX4_FIFO_FS_SIZE + \ + TX5_FIFO_FS_SIZE + TX6_FIFO_FS_SIZE + TX7_FIFO_FS_SIZE + TX8_FIFO_FS_SIZE + TX9_FIFO_FS_SIZE + \ TX10_FIFO_FS_SIZE + TX11_FIFO_FS_SIZE + TX12_FIFO_FS_SIZE + TX13_FIFO_FS_SIZE + TX14_FIFO_FS_SIZE + \ TX15_FIFO_FS_SIZE) > 640U) -#error "The USB max FIFO size is 640 x 4 Bytes!" +#error "The USB max FIFO size is 640 x 4 Bytes!" #endif #endif #ifdef USB_HS_MODE -#define RX_FIFO_HS_SIZE (512U) -#define TX0_FIFO_HS_SIZE (64U) -#define TX1_FIFO_HS_SIZE (64U) -#define TX2_FIFO_HS_SIZE (64U) -#define TX3_FIFO_HS_SIZE (64U) -#define TX4_FIFO_HS_SIZE (64U) -#define TX5_FIFO_HS_SIZE (64U) -#define TX6_FIFO_HS_SIZE (64U) -#define TX7_FIFO_HS_SIZE (64U) -#define TX8_FIFO_HS_SIZE (64U) -#define TX9_FIFO_HS_SIZE (64U) -#define TX10_FIFO_HS_SIZE (64U) -#define TX11_FIFO_HS_SIZE (64U) -#define TX12_FIFO_HS_SIZE (64U) -#define TX13_FIFO_HS_SIZE (64U) -#define TX14_FIFO_HS_SIZE (64U) -#define TX15_FIFO_HS_SIZE (64U) - -#if ((RX_FIFO_HS_SIZE + \ - TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ - TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ +#define RX_FIFO_HS_SIZE (512U) +#define TX0_FIFO_HS_SIZE (64U) +#define TX1_FIFO_HS_SIZE (64U) +#define TX2_FIFO_HS_SIZE (64U) +#define TX3_FIFO_HS_SIZE (64U) +#define TX4_FIFO_HS_SIZE (64U) +#define TX5_FIFO_HS_SIZE (64U) +#define TX6_FIFO_HS_SIZE (64U) +#define TX7_FIFO_HS_SIZE (64U) +#define TX8_FIFO_HS_SIZE (64U) +#define TX9_FIFO_HS_SIZE (64U) +#define TX10_FIFO_HS_SIZE (64U) +#define TX11_FIFO_HS_SIZE (64U) +#define TX12_FIFO_HS_SIZE (64U) +#define TX13_FIFO_HS_SIZE (64U) +#define TX14_FIFO_HS_SIZE (64U) +#define TX15_FIFO_HS_SIZE (64U) + +#if ((RX_FIFO_HS_SIZE + \ + TX0_FIFO_HS_SIZE + TX1_FIFO_HS_SIZE + TX2_FIFO_HS_SIZE + TX3_FIFO_HS_SIZE + TX4_FIFO_HS_SIZE + \ + TX5_FIFO_HS_SIZE + TX6_FIFO_HS_SIZE + TX7_FIFO_HS_SIZE + TX8_FIFO_HS_SIZE + TX9_FIFO_HS_SIZE + \ TX10_FIFO_HS_SIZE + TX11_FIFO_HS_SIZE + TX12_FIFO_HS_SIZE + TX13_FIFO_HS_SIZE + TX14_FIFO_HS_SIZE + \ TX15_FIFO_HS_SIZE) > 2048U) -#error "The USB max FIFO size is 2048 x 4 Bytes!" +#error "The USB max FIFO size is 2048 x 4 Bytes!" #endif #endif @@ -137,22 +136,22 @@ USB_FS_MODE, USB_HS_MODE, USB_HS_EXTERNAL_PHY defined comment #if defined(BSP_USING_USBH) /* USB HOST FIFO CONFIGURATION */ #ifdef USB_FS_MODE -#define RX_FIFO_FS_SIZE (128U) -#define TXH_NP_FS_FIFOSIZ (32U) -#define TXH_P_FS_FIFOSIZ (64U) +#define RX_FIFO_FS_SIZE (128U) +#define TXH_NP_FS_FIFOSIZ (32U) +#define TXH_P_FS_FIFOSIZ (64U) #if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 640U) -#error "The USB max FIFO size is 640 x 4 Bytes!" +#error "The USB max FIFO size is 640 x 4 Bytes!" #endif #endif #ifdef USB_HS_MODE -#define RX_FIFO_HS_SIZE (512U) -#define TXH_NP_HS_FIFOSIZ (128U) -#define TXH_P_HS_FIFOSIZ (256U) +#define RX_FIFO_HS_SIZE (512U) +#define TXH_NP_HS_FIFOSIZ (128U) +#define TXH_P_HS_FIFOSIZ (256U) #if ((RX_FIFO_FS_SIZE + TXH_NP_FS_FIFOSIZ + TXH_P_FS_FIFOSIZ) > 2048U) -#error "The USB max FIFO size is 2048 x 4 Bytes!" +#error "The USB max FIFO size is 2048 x 4 Bytes!" #endif #endif #endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_bsp.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_bsp.h index 76b5b37d81c..0df0dfbeda3 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_bsp.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/config/usb_config/usb_bsp.h @@ -13,8 +13,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif #include "hc32_ll_utility.h" diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/hc32f4xx_conf.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/hc32f4xx_conf.h index 7d733e221a2..b4087921b35 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/hc32f4xx_conf.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/hc32f4xx_conf.h @@ -27,8 +27,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -48,66 +47,66 @@ extern "C" * Library. * @note LL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. */ -#define LL_ICG_ENABLE (DDL_ON) -#define LL_UTILITY_ENABLE (DDL_ON) -#define LL_PRINT_ENABLE (DDL_OFF) - -#define LL_ADC_ENABLE (DDL_ON) -#define LL_AES_ENABLE (DDL_ON) -#define LL_AOS_ENABLE (DDL_ON) -#define LL_CAN_ENABLE (DDL_ON) -#define LL_CLK_ENABLE (DDL_ON) -#define LL_CMP_ENABLE (DDL_ON) -#define LL_CRC_ENABLE (DDL_ON) -#define LL_CTC_ENABLE (DDL_ON) -#define LL_DAC_ENABLE (DDL_ON) -#define LL_DBGC_ENABLE (DDL_OFF) -#define LL_DCU_ENABLE (DDL_ON) -#define LL_DMA_ENABLE (DDL_ON) -#define LL_DMC_ENABLE (DDL_ON) -#define LL_DVP_ENABLE (DDL_ON) -#define LL_EFM_ENABLE (DDL_ON) -#define LL_EMB_ENABLE (DDL_ON) -#define LL_ETH_ENABLE (DDL_ON) -#define LL_EVENT_PORT_ENABLE (DDL_OFF) -#define LL_FCG_ENABLE (DDL_ON) -#define LL_FCM_ENABLE (DDL_ON) -#define LL_FMAC_ENABLE (DDL_ON) -#define LL_GPIO_ENABLE (DDL_ON) -#define LL_HASH_ENABLE (DDL_ON) -#define LL_HRPWM_ENABLE (DDL_ON) -#define LL_I2C_ENABLE (DDL_ON) -#define LL_I2S_ENABLE (DDL_ON) -#define LL_INTERRUPTS_ENABLE (DDL_ON) -#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) -#define LL_KEYSCAN_ENABLE (DDL_ON) -#define LL_MAU_ENABLE (DDL_ON) -#define LL_MPU_ENABLE (DDL_ON) -#define LL_NFC_ENABLE (DDL_ON) -#define LL_OTS_ENABLE (DDL_ON) -#define LL_PWC_ENABLE (DDL_ON) -#define LL_QSPI_ENABLE (DDL_ON) -#define LL_RMU_ENABLE (DDL_ON) -#define LL_RTC_ENABLE (DDL_ON) -#define LL_SDIOC_ENABLE (DDL_ON) -#define LL_SMC_ENABLE (DDL_ON) -#define LL_SPI_ENABLE (DDL_ON) -#define LL_SRAM_ENABLE (DDL_ON) -#define LL_SWDT_ENABLE (DDL_ON) -#define LL_TMR0_ENABLE (DDL_ON) -#define LL_TMR2_ENABLE (DDL_ON) -#define LL_TMR4_ENABLE (DDL_ON) -#define LL_TMR6_ENABLE (DDL_ON) -#define LL_TMRA_ENABLE (DDL_ON) -#define LL_TRNG_ENABLE (DDL_ON) -#define LL_USART_ENABLE (DDL_ON) -#define LL_USB_ENABLE (DDL_ON) -#define LL_WDT_ENABLE (DDL_ON) +#define LL_ICG_ENABLE (DDL_ON) +#define LL_UTILITY_ENABLE (DDL_ON) +#define LL_PRINT_ENABLE (DDL_OFF) + +#define LL_ADC_ENABLE (DDL_ON) +#define LL_AES_ENABLE (DDL_ON) +#define LL_AOS_ENABLE (DDL_ON) +#define LL_CAN_ENABLE (DDL_ON) +#define LL_CLK_ENABLE (DDL_ON) +#define LL_CMP_ENABLE (DDL_ON) +#define LL_CRC_ENABLE (DDL_ON) +#define LL_CTC_ENABLE (DDL_ON) +#define LL_DAC_ENABLE (DDL_ON) +#define LL_DBGC_ENABLE (DDL_OFF) +#define LL_DCU_ENABLE (DDL_ON) +#define LL_DMA_ENABLE (DDL_ON) +#define LL_DMC_ENABLE (DDL_ON) +#define LL_DVP_ENABLE (DDL_ON) +#define LL_EFM_ENABLE (DDL_ON) +#define LL_EMB_ENABLE (DDL_ON) +#define LL_ETH_ENABLE (DDL_ON) +#define LL_EVENT_PORT_ENABLE (DDL_OFF) +#define LL_FCG_ENABLE (DDL_ON) +#define LL_FCM_ENABLE (DDL_ON) +#define LL_FMAC_ENABLE (DDL_ON) +#define LL_GPIO_ENABLE (DDL_ON) +#define LL_HASH_ENABLE (DDL_ON) +#define LL_HRPWM_ENABLE (DDL_ON) +#define LL_I2C_ENABLE (DDL_ON) +#define LL_I2S_ENABLE (DDL_ON) +#define LL_INTERRUPTS_ENABLE (DDL_ON) +#define LL_INTERRUPTS_SHARE_ENABLE (DDL_ON) +#define LL_KEYSCAN_ENABLE (DDL_ON) +#define LL_MAU_ENABLE (DDL_ON) +#define LL_MPU_ENABLE (DDL_ON) +#define LL_NFC_ENABLE (DDL_ON) +#define LL_OTS_ENABLE (DDL_ON) +#define LL_PWC_ENABLE (DDL_ON) +#define LL_QSPI_ENABLE (DDL_ON) +#define LL_RMU_ENABLE (DDL_ON) +#define LL_RTC_ENABLE (DDL_ON) +#define LL_SDIOC_ENABLE (DDL_ON) +#define LL_SMC_ENABLE (DDL_ON) +#define LL_SPI_ENABLE (DDL_ON) +#define LL_SRAM_ENABLE (DDL_ON) +#define LL_SWDT_ENABLE (DDL_ON) +#define LL_TMR0_ENABLE (DDL_ON) +#define LL_TMR2_ENABLE (DDL_ON) +#define LL_TMR4_ENABLE (DDL_ON) +#define LL_TMR6_ENABLE (DDL_ON) +#define LL_TMRA_ENABLE (DDL_ON) +#define LL_TRNG_ENABLE (DDL_ON) +#define LL_USART_ENABLE (DDL_ON) +#define LL_USB_ENABLE (DDL_ON) +#define LL_WDT_ENABLE (DDL_ON) /** * @brief The following is a list of currently supported BSP boards. */ -#define BSP_EV_HC32F4A0_LQFP176 (1U) +#define BSP_EV_HC32F4A0_LQFP176 (1U) /** * @brief The macro BSP_EV_HC32F4XX is used to specify the BSP board currently @@ -116,72 +115,72 @@ extern "C" * @note If there is no supported BSP board or the BSP function is not used, * the value needs to be set to 0U. */ -#define BSP_EV_HC32F4XX (BSP_EV_HC32F4A0_LQFP176) +#define BSP_EV_HC32F4XX (BSP_EV_HC32F4A0_LQFP176) /** * @brief This is the list of BSP components to be used. * Select the components you need to use to DDL_ON. */ -#define BSP_24CXX_ENABLE (DDL_OFF) -#define BSP_GT9XX_ENABLE (DDL_OFF) -#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF) -#define BSP_IS62WV51216_ENABLE (DDL_OFF) -#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) -#define BSP_NT35510_ENABLE (DDL_OFF) -#define BSP_OV5640_ENABLE (DDL_OFF) -#define BSP_TCA9539_ENABLE (DDL_OFF) -#define BSP_W25QXX_ENABLE (DDL_OFF) -#define BSP_WM8731_ENABLE (DDL_OFF) +#define BSP_24CXX_ENABLE (DDL_OFF) +#define BSP_GT9XX_ENABLE (DDL_OFF) +#define BSP_IS42S16400J7TLI_ENABLE (DDL_OFF) +#define BSP_IS62WV51216_ENABLE (DDL_OFF) +#define BSP_MT29F2G08AB_ENABLE (DDL_OFF) +#define BSP_NT35510_ENABLE (DDL_OFF) +#define BSP_OV5640_ENABLE (DDL_OFF) +#define BSP_TCA9539_ENABLE (DDL_OFF) +#define BSP_W25QXX_ENABLE (DDL_OFF) +#define BSP_WM8731_ENABLE (DDL_OFF) /** * @brief Ethernet and PHY Configuration. */ /* MAC ADDRESS */ -#define ETH_MAC_ADDR0 (0x02U) -#define ETH_MAC_ADDR1 (0x00U) -#define ETH_MAC_ADDR2 (0x00U) -#define ETH_MAC_ADDR3 (0x00U) -#define ETH_MAC_ADDR4 (0x00U) -#define ETH_MAC_ADDR5 (0x00U) +#define ETH_MAC_ADDR0 (0x02U) +#define ETH_MAC_ADDR1 (0x00U) +#define ETH_MAC_ADDR2 (0x00U) +#define ETH_MAC_ADDR3 (0x00U) +#define ETH_MAC_ADDR4 (0x00U) +#define ETH_MAC_ADDR5 (0x00U) /* Common PHY Registers */ -#define PHY_BCR (0x00U) /*!< Basic Control Register */ -#define PHY_BSR (0x01U) /*!< Basic Status Register */ - -#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */ -#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */ -#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */ - -#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */ -#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */ -#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */ -#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */ -#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */ - -#if defined (ETH_PHY_USING_RTL8201F) +#define PHY_BCR (0x00U) /*!< Basic Control Register */ +#define PHY_BSR (0x01U) /*!< Basic Status Register */ + +#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */ +#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */ +#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */ + +#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */ +#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */ +#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */ +#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */ +#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */ + +#if defined(ETH_PHY_USING_RTL8201F) /* PHY(RTL8201F) Address*/ -#define ETH_PHY_ADDR (0x00U) +#define ETH_PHY_ADDR (0x00U) /* PHY Configuration delay(ms) */ -#define ETH_PHY_RST_DELAY (0x0080UL) -#define ETH_PHY_CONFIG_DELAY (0x0800UL) -#define ETH_PHY_RD_TIMEOUT (0x0005UL) -#define ETH_PHY_WR_TIMEOUT (0x0005UL) +#define ETH_PHY_RST_DELAY (0x0080UL) +#define ETH_PHY_CONFIG_DELAY (0x0800UL) +#define ETH_PHY_RD_TIMEOUT (0x0005UL) +#define ETH_PHY_WR_TIMEOUT (0x0005UL) /* PHY Status Register */ -#define PHY_SR (PHY_BCR) /*!< PHY status register */ +#define PHY_SR (PHY_BCR) /*!< PHY status register */ -#define PHY_DUPLEX_STATUS (PHY_FULLDUPLEX_10M) /*!< PHY Duplex mask */ -#define PHY_SPEED_STATUS (PHY_HALFDUPLEX_100M) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS (PHY_FULLDUPLEX_10M) /*!< PHY Duplex mask */ +#define PHY_SPEED_STATUS (PHY_HALFDUPLEX_100M) /*!< PHY Speed mask */ #endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal_cfg.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal_cfg.h index 5d8fbbe9e63..9a8de41f9c2 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal_cfg.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/fal_cfg.h @@ -23,20 +23,20 @@ extern const struct fal_flash_dev hc32_onchip_flash; extern struct fal_flash_dev ext_nor_flash0; /* flash device table */ -#define FAL_FLASH_DEV_TABLE \ -{ \ - &hc32_onchip_flash, \ - &ext_nor_flash0, \ -} +#define FAL_FLASH_DEV_TABLE \ + { \ + &hc32_onchip_flash, \ + &ext_nor_flash0, \ + } /* ====================== Partition Configuration ========================== */ #ifdef FAL_PART_HAS_TABLE_CFG /* partition table */ -#define FAL_PART_TABLE \ -{ \ - {FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0}, \ - {FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0}, \ -} +#define FAL_PART_TABLE \ + { \ + { FAL_PART_MAGIC_WROD, "app", "onchip_flash", 0, 2 * 1024 * 1024, 0 }, \ + { FAL_PART_MAGIC_WROD, "filesystem", "w25q64", 0, 8 * 1024 * 1024, 0 }, \ + } #endif /* FAL_PART_HAS_TABLE_CFG */ #endif /* _FAL_CFG_H_ */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h index 34b62b6fa3b..976376d5e11 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/nand_port.h @@ -12,72 +12,75 @@ #define __NAND_PORT_H__ /******************** NAND chip information ***********************************/ -#define NAND_BYTES_PER_PAGE 2048UL -#define NAND_SPARE_AREA_SIZE 64UL -#define NAND_PAGES_PER_BLOCK 64UL -#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) -#define NAND_BLOCKS_PER_PLANE 1024UL -#define NAND_PLANE_PER_DEVICE 2UL -#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) -#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) +#define NAND_BYTES_PER_PAGE 2048UL +#define NAND_SPARE_AREA_SIZE 64UL +#define NAND_PAGES_PER_BLOCK 64UL +#define NAND_BYTES_PER_BLOCK (NAND_PAGES_PER_BLOCK * NAND_BYTES_PER_PAGE) +#define NAND_BLOCKS_PER_PLANE 1024UL +#define NAND_PLANE_PER_DEVICE 2UL +#define NAND_DEVICE_BLOCKS (NAND_BLOCKS_PER_PLANE * NAND_PLANE_PER_DEVICE) +#define NAND_DEVICE_PAGES (NAND_DEVICE_BLOCKS * NAND_PAGES_PER_BLOCK) /******************** EXMC_NFC configure **************************************/ /* chip: EXMC_NFC_BANK0~7 */ -#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0 +#define NAND_EXMC_NFC_BANK EXMC_NFC_BANK0 /* density:2Gbit */ -#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT +#define NAND_EXMC_NFC_BANK_CAPACITY EXMC_NFC_BANK_CAPACITY_2GBIT /* device width: 8-bit */ -#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT +#define NAND_EXMC_NFC_MEMORY_WIDTH EXMC_NFC_MEMORY_WIDTH_8BIT + +/* BankNum: 1BANK */ +#define NAND_EXMC_NFC_BANK_NUMBER EXMC_NFC_1BANK /* page size: 2KByte */ -#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE +#define NAND_EXMC_NFC_PAGE_SIZE EXMC_NFC_PAGE_SIZE_2KBYTE /* row address cycle: 3 */ -#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE +#define NAND_EXMC_NFC_ROW_ADDR_CYCLE EXMC_NFC_3_ROW_ADDR_CYCLE /* ECC mode */ -#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC +#define NAND_EXMC_NFC_ECC_MD EXMC_NFC_1BIT_ECC /* timing configuration(EXCLK clock frequency: 60MHz@3.3V) for MT29F2G08AB */ /* TS: ALE/CLE/CE setup time(min=10ns) */ -#define NAND_TS 1U +#define NAND_TS 1U /* TWP: WE# pulse width (min=10ns) */ -#define NAND_TWP 1U +#define NAND_TWP 1U /* TRP: RE# pulse width (MT29F2G08AB min=10ns and EXMC t_data_s min=24ns) */ -#define NAND_TRP 2U +#define NAND_TRP 2U /* TTH: ALE/CLE/CE hold time (min=5ns) */ -#define NAND_TH 1U +#define NAND_TH 1U /* TWH: WE# pulse width HIGH (min=10ns) */ -#define NAND_TWH 1U +#define NAND_TWH 1U /* TRH: RE# pulse width HIGH (min=7ns) */ -#define NAND_TRH 1U +#define NAND_TRH 1U /* TRR: Ready to RE# LOW (min=20ns) */ -#define NAND_TRR 2U +#define NAND_TRR 2U /* TWB: WE# HIGH to busy (max=100ns) */ -#define NAND_TWB 1U +#define NAND_TWB 1U /* TWB: WE# HIGH to busy (max=100ns) */ -#define NAND_TRB 1U +#define NAND_TRB 1U /* TCCS: Change read column and Change write column delay */ -#define NAND_TCCS 5U +#define NAND_TCCS 5U /* TWTR: WE# HIGH to RE# LOW (min=60ns) */ -#define NAND_TWTR 4U +#define NAND_TWTR 4U /* TRTW: RE# HIGH to WE# LOW (min=100ns) */ -#define NAND_TRTW 7U +#define NAND_TRTW 7U /* TADL: ALE to data start (min=70ns) */ -#define NAND_TADL 5U +#define NAND_TADL 5U #endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/sdram_port.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/sdram_port.h index 48f54370556..b0b46e01cd4 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/sdram_port.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/sdram_port.h @@ -16,73 +16,73 @@ /* parameters for sdram peripheral */ /* chip#0/1/2/3: EXMC_DMC_CHIP0/1/2/3 */ -#define SDRAM_CHIP EXMC_DMC_CHIP1 +#define SDRAM_CHIP EXMC_DMC_CHIP1 /* bank address */ -#define SDRAM_BANK_ADDR (0x80000000UL) +#define SDRAM_BANK_ADDR (0x80000000UL) /* size(kbyte):8MB = 8*1024*1KBytes */ -#define SDRAM_SIZE (8UL * 1024UL * 1024UL) +#define SDRAM_SIZE (8UL * 1024UL * 1024UL) /* auto precharge pin: EXMC_DMC_AUTO_PRECHARGE_A8/10 */ -#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 +#define SDRAM_AUTO_PRECHARGE_PIN EXMC_DMC_AUTO_PRECHARGE_A10 /* data width: EXMC_DMC_MEMORY_WIDTH_16BIT, EXMC_DMC_MEMORY_WIDTH_32BIT */ -#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT +#define SDRAM_DATA_WIDTH EXMC_DMC_MEMORY_WIDTH_16BIT /* column bit numbers: EXMC_DMC_COLUMN_BITS_NUM8/9/10/11/12 */ -#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM8 +#define SDRAM_COLUMN_BITS EXMC_DMC_COLUMN_BITS_NUM8 /* row bit numbers: EXMC_DMC_ROW_BITS_NUM11/12/13/14/15/16 */ -#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM12 +#define SDRAM_ROW_BITS EXMC_DMC_ROW_BITS_NUM12 /* cas latency clock number: 2, 3 */ -#define SDRAM_CAS_LATENCY 2UL +#define SDRAM_CAS_LATENCY 2UL /* burst length: EXMC_DMC_BURST_1BEAT/2BEAT/4BEAT/8BEAT/16BEAT */ -#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT +#define SDRAM_BURST_LENGTH EXMC_DMC_BURST_1BEAT /* operating mode: SDRAM_MODEREG_OPERATING_MODE_STANDARD */ -#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD +#define SDRAM_MODEREG_OPERATING_MODE SDRAM_MODEREG_OPERATING_MODE_STANDARD /* burst type: SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL/INTERLEAVED */ -#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL +#define SDRAM_MODEREG_BURST_TYPE SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL /* write burst mode: SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED/SINGLE */ -#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED +#define SDRAM_MODEREG_WRITEBURST_MODE SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED /* timing configuration(EXCLK clock frequency: 30MHz) for IS42S16400J-7TLI */ /* refresh rate counter (EXCLK clock) */ -#define SDRAM_REFRESH_COUNT (450U) +#define SDRAM_REFRESH_COUNT (450U) /* TMDR: mode register command time (EXCLK clock) */ -#define SDRAM_TMDR 2U +#define SDRAM_TMDR 2U /* TRAS: RAS to precharge delay time (EXCLK clock) */ -#define SDRAM_TRAS 2U +#define SDRAM_TRAS 2U /* TRC: active bank x to active bank x delay time (EXCLK clock) */ -#define SDRAM_TRC 2U +#define SDRAM_TRC 2U /* TRCD: RAS to CAS minimum delay time (EXCLK clock) */ -#define SDRAM_TRCD_B 3U -#define SDRAM_TRCD_P 0U +#define SDRAM_TRCD_B 3U +#define SDRAM_TRCD_P 0U /* TRFC: autorefresh command time (EXCLK clock) */ -#define SDRAM_TRFC_B 3U -#define SDRAM_TRFC_P 0U +#define SDRAM_TRFC_B 3U +#define SDRAM_TRFC_P 0U /* TRP: precharge to RAS delay time (EXCLK clock) */ -#define SDRAM_TRP_B 3U -#define SDRAM_TRP_P 0U +#define SDRAM_TRP_B 3U +#define SDRAM_TRP_P 0U /* TRRD: active bank x to active bank y delay time (EXCLK clock) */ -#define SDRAM_TRRD 1U +#define SDRAM_TRRD 1U /* TWR: write to precharge delay time (EXCLK clock). */ -#define SDRAM_TWR 2U +#define SDRAM_TWR 2U /* TWTR: write to read delay time (EXCLK clock). */ -#define SDRAM_TWTR 1U +#define SDRAM_TWTR 1U /* TXP: exit power-down command time (EXCLK clock). */ -#define SDRAM_TXP 1U +#define SDRAM_TXP 1U /* TXSR: exit self-refresh command time (EXCLK clock). */ -#define SDRAM_TXSR 5U +#define SDRAM_TXSR 5U /* TESR: self-refresh command time (EXCLK clock). */ -#define SDRAM_TESR 5U +#define SDRAM_TESR 5U /* memory mode register */ -#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) -#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) -#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) -#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) -#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) -#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) -#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) -#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) -#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) -#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) -#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) +#define SDRAM_MODEREG_BURST_LENGTH_1 (0x0000U) +#define SDRAM_MODEREG_BURST_LENGTH_2 (0x0001U) +#define SDRAM_MODEREG_BURST_LENGTH_4 (0x0002U) +#define SDRAM_MODEREG_BURST_LENGTH_8 (0x0004U) +#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL (0x0000U) +#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED (0x0008U) +#define SDRAM_MODEREG_CAS_LATENCY_2 (0x0020U) +#define SDRAM_MODEREG_CAS_LATENCY_3 (0x0030U) +#define SDRAM_MODEREG_OPERATING_MODE_STANDARD (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED (0x0000U) +#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE (0x0200U) #endif diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539_port.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539_port.h index bcd6657ade0..e10a5b9f974 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539_port.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/board/ports/tca9539_port.h @@ -17,23 +17,23 @@ * @defgroup HC32F4A0_EV_IO_Function_Sel Expand IO function definition * @{ */ -#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ -#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ -#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */ -#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */ -#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */ -#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */ -#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ -#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ +#define EIO_USBFS_OC (TCA9539_IO_PIN0) /* USBFS over-current, input */ +#define EIO_USBHS_OC (TCA9539_IO_PIN1) /* USBHS over-current, input */ +#define EIO_SDIC1_CD (TCA9539_IO_PIN2) /* SDIC1 card detect, input */ +#define EIO_SCI_CD (TCA9539_IO_PIN3) /* Smart card detect, input */ +#define EIO_TOUCH_INT (TCA9539_IO_PIN4) /* Touch screen interrupt, input */ +#define EIO_LIN_SLEEP (TCA9539_IO_PIN5) /* LIN PHY sleep, output */ +#define EIO_RTCS_CTRST (TCA9539_IO_PIN6) /* 'CS' for Resistor touch panel or 'Reset' for Cap touch panel, output */ +#define EIO_LCD_RST (TCA9539_IO_PIN7) /* LCD panel reset, output */ -#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */ -#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */ -#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ -#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ -#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ -#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ -#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ -#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ +#define EIO_CAM_RST (TCA9539_IO_PIN0) /* Camera module reset, output */ +#define EIO_CAM_STB (TCA9539_IO_PIN1) /* Camera module standby, output */ +#define EIO_USB3300_RST (TCA9539_IO_PIN2) /* USBHS PHY USB3300 reset, output */ +#define EIO_ETH_RST (TCA9539_IO_PIN3) /* ETH PHY reset, output */ +#define EIO_CAN_STB (TCA9539_IO_PIN4) /* CAN PHY standby, output */ +#define EIO_LED_RED (TCA9539_IO_PIN5) /* Red LED, output */ +#define EIO_LED_YELLOW (TCA9539_IO_PIN6) /* Yellow LED, output */ +#define EIO_LED_BLUE (TCA9539_IO_PIN7) /* Blue LED, output */ /** * @} */ @@ -42,12 +42,12 @@ * @defgroup BSP_LED_PortPin_Sel BSP LED port/pin definition * @{ */ -#define LED_RED_PORT (TCA9539_IO_PORT1) -#define LED_RED_PIN (EIO_LED_RED) -#define LED_YELLOW_PORT (TCA9539_IO_PORT1) -#define LED_YELLOW_PIN (EIO_LED_YELLOW) -#define LED_BLUE_PORT (TCA9539_IO_PORT1) -#define LED_BLUE_PIN (EIO_LED_BLUE) +#define LED_RED_PORT (TCA9539_IO_PORT1) +#define LED_RED_PIN (EIO_LED_RED) +#define LED_YELLOW_PORT (TCA9539_IO_PORT1) +#define LED_YELLOW_PIN (EIO_LED_YELLOW) +#define LED_BLUE_PORT (TCA9539_IO_PORT1) +#define LED_BLUE_PIN (EIO_LED_BLUE) /** * @} */ @@ -56,8 +56,8 @@ * @defgroup BSP CAN PHY STB port/pin definition * @{ */ -#define CAN_STB_PORT (TCA9539_IO_PORT1) -#define CAN_STB_PIN (EIO_CAN_STB) +#define CAN_STB_PORT (TCA9539_IO_PORT1) +#define CAN_STB_PIN (EIO_CAN_STB) /** * @} */ diff --git a/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h b/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h index 8d502df1467..5348607e2d9 100644 --- a/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h +++ b/bsp/hc32/lckfb-hc32f4a0-lqfp100/rtconfig.h @@ -61,20 +61,20 @@ /* end of rt_strnlen options */ /* end of klibc options */ -#define RT_NAME_MAX 12 -#define RT_CPUS_NR 1 +#define RT_NAME_MAX 24 +#define RT_CPUS_NR 1 #define RT_ALIGN_SIZE 8 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 -#define RT_TICK_PER_SECOND 1000 +#define RT_TICK_PER_SECOND 1000 #define RT_USING_OVERFLOW_CHECK #define RT_USING_HOOK #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 256 +#define IDLE_THREAD_STACK_SIZE 512 #define RT_USING_TIMER_SOFT -#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_PRIO 4 #define RT_TIMER_THREAD_STACK_SIZE 512 /* kservice options */ @@ -103,10 +103,10 @@ /* end of Memory Management */ #define RT_USING_DEVICE #define RT_USING_CONSOLE -#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_USING_CONSOLE_OUTPUT_CTL -#define RT_VER_NUM 0x50300 +#define RT_VER_NUM 0x50300 #define RT_BACKTRACE_LEVEL_MAX_NR 32 /* end of RT-Thread Kernel */ #define RT_USING_HW_ATOMIC @@ -122,12 +122,12 @@ #define RT_USING_COMPONENTS_INIT #define RT_USING_USER_MAIN #define RT_MAIN_THREAD_STACK_SIZE 2048 -#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_MAIN_THREAD_PRIORITY 10 #define RT_USING_MSH #define RT_USING_FINSH #define FINSH_USING_MSH -#define FINSH_THREAD_NAME "tshell" -#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 #define FINSH_THREAD_STACK_SIZE 4096 #define FINSH_USING_HISTORY #define FINSH_HISTORY_LINES 5 @@ -148,7 +148,7 @@ #define RT_UNAMED_PIPE_NUMBER 64 #define RT_USING_SYSTEM_WORKQUEUE #define RT_SYSTEM_WORKQUEUE_STACKSIZE 2048 -#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 #define RT_USING_SERIAL #define RT_USING_SERIAL_V1 #define RT_SERIAL_USING_DMA @@ -166,8 +166,8 @@ #define RT_LIBC_USING_LIGHT_TZ_DST #define RT_LIBC_TZ_DEFAULT_HOUR 8 -#define RT_LIBC_TZ_DEFAULT_MIN 0 -#define RT_LIBC_TZ_DEFAULT_SEC 0 +#define RT_LIBC_TZ_DEFAULT_MIN 0 +#define RT_LIBC_TZ_DEFAULT_SEC 0 /* end of Timezone and Daylight Saving Time */ /* end of ISO-ANSI C layer */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.c b/bsp/hc32/libraries/hc32_drivers/drv_adc.c index e4de8623d9e..0c732c8db45 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_adc.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.c @@ -10,6 +10,8 @@ * 2022-06-14 CDT fix a bug of internal trigger * 2024-02-20 CDT support HC32F448 * add function for associating with the dma + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-05 CDT support HC32F467 */ #include @@ -17,8 +19,8 @@ #include #include -#define DBG_TAG "drv.adc" -#define DBG_LVL DBG_INFO +#define DBG_TAG "drv.adc" +#define DBG_LVL DBG_INFO #include #ifdef BSP_USING_ADC @@ -44,25 +46,24 @@ enum #endif }; -static adc_device _g_adc_dev_array[] = -{ +static adc_device _g_adc_dev_array[] = { #ifdef BSP_USING_ADC1 { - {0}, + { 0 }, CM_ADC1, ADC1_INIT_PARAMS, }, #endif #ifdef BSP_USING_ADC2 { - {0}, + { 0 }, CM_ADC2, ADC2_INIT_PARAMS, }, #endif #ifdef BSP_USING_ADC3 { - {0}, + { 0 }, CM_ADC3, ADC3_INIT_PARAMS, }, @@ -87,7 +88,7 @@ static void _adc_internal_trigger0_set(adc_device *p_adc_dev) case (rt_uint32_t)CM_ADC2: u32TriggerSel = AOS_ADC2_0; break; -#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) || defined(HC32F467) case (rt_uint32_t)CM_ADC3: u32TriggerSel = AOS_ADC3_0; break; @@ -118,7 +119,7 @@ static void _adc_internal_trigger1_set(adc_device *p_adc_dev) case (rt_uint32_t)CM_ADC2: u32TriggerSel = AOS_ADC2_1; break; -#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) || defined(HC32F467) case (rt_uint32_t)CM_ADC3: u32TriggerSel = AOS_ADC3_1; break; @@ -176,8 +177,7 @@ static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt rt_ret = LL_OK; break; } - } - while ((rt_tick_get() - start_time) < p_adc_dev->init.eoc_poll_time_max); + } while ((rt_tick_get() - start_time) < p_adc_dev->init.eoc_poll_time_max); if (rt_ret == LL_OK) { @@ -215,6 +215,10 @@ static rt_err_t _adc_convert(struct rt_adc_device *device, rt_int8_t channel, rt (void)DMA_ChCmd(adc_eoca_dma->Instance, adc_eoca_dma->channel, DISABLE); rt_ret = -RT_ETIMEOUT; } + else + { + rt_ret = LL_OK; + } if (adc_dev_priv->ops->dma_trig_stop != RT_NULL) { adc_dev_priv->ops->dma_trig_stop(); @@ -263,8 +267,7 @@ static rt_int16_t _adc_get_vref(struct rt_adc_device *device) return vref; } -static struct rt_adc_ops _g_adc_ops = -{ +static struct rt_adc_ops _g_adc_ops = { _adc_enable, _adc_convert, _adc_get_resolution, @@ -286,17 +289,17 @@ static void _adc_clock_enable(void) static void hc32_adc_get_dma_info(void) { -#ifdef BSP_ADC1_USING_DMA +#ifdef BSP_ADC1_USING_DMA static struct dma_config adc1_eoca_dma = ADC1_EOCA_DMA_CONFIG; _g_adc_dev_array[ADC1_INDEX].init.adc_eoca_dma = &adc1_eoca_dma; #endif -#ifdef BSP_ADC2_USING_DMA +#ifdef BSP_ADC2_USING_DMA static struct dma_config adc2_eoca_dma = ADC2_EOCA_DMA_CONFIG; _g_adc_dev_array[ADC2_INDEX].init.adc_eoca_dma = &adc2_eoca_dma; #endif -#ifdef BSP_ADC3_USING_DMA +#ifdef BSP_ADC3_USING_DMA static struct dma_config adc3_eoca_dma = ADC3_EOCA_DMA_CONFIG; _g_adc_dev_array[ADC3_INDEX].init.adc_eoca_dma = &adc3_eoca_dma; #endif @@ -310,13 +313,13 @@ static void hc32_adc_dma_config(adc_device *p_adc_dev) FCG_Fcg0PeriphClockCmd(p_adc_dev->init.adc_eoca_dma->clock, ENABLE); (void)DMA_StructInit(&stcDmaInit); - stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32BlockSize = 1UL; stcDmaInit.u32TransCount = 1UL; - stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT; - stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT; + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX; - stcDmaInit.u32SrcAddr = (uint32_t)RT_NULL; - stcDmaInit.u32DestAddr = (uint32_t)RT_NULL; + stcDmaInit.u32SrcAddr = (uint32_t)RT_NULL; + stcDmaInit.u32DestAddr = (uint32_t)RT_NULL; if (LL_OK != DMA_Init(p_adc_dev->init.adc_eoca_dma->Instance, p_adc_dev->init.adc_eoca_dma->channel, &stcDmaInit)) { rt_kprintf("[%s:%d]ADC DMA init error!\n", __func__, __LINE__); @@ -333,7 +336,7 @@ extern rt_err_t rt_hw_board_adc_init(CM_ADC_TypeDef *ADCx); int rt_hw_adc_init(void) { int ret = RT_EOK, i = 0; - stc_adc_init_t stcAdcInit = {0}; + stc_adc_init_t stcAdcInit = { 0 }; int32_t ll_ret = 0; _adc_clock_enable(); @@ -355,20 +358,21 @@ int rt_hw_adc_init(void) ADC_TriggerCmd(_g_adc_dev_array[i].instance, ADC_SEQ_A, (en_functional_state_t)_g_adc_dev_array[i].init.hard_trig_enable); ADC_TriggerConfig(_g_adc_dev_array[i].instance, ADC_SEQ_A, _g_adc_dev_array[i].init.hard_trig_src); - if (_g_adc_dev_array[i].init.hard_trig_enable && _g_adc_dev_array[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN) - { - _adc_internal_trigger0_set(&_g_adc_dev_array[i]); - _adc_internal_trigger1_set(&_g_adc_dev_array[i]); - } if (_g_adc_dev_array[i].init.adc_eoca_dma != RT_NULL) { hc32_adc_dma_config(&_g_adc_dev_array[i]); } + if (_g_adc_dev_array[i].init.hard_trig_enable && _g_adc_dev_array[i].init.hard_trig_src != ADC_HARDTRIG_ADTRG_PIN) + { + _adc_internal_trigger0_set(&_g_adc_dev_array[i]); + _adc_internal_trigger1_set(&_g_adc_dev_array[i]); + } + rt_hw_board_adc_init((void *)_g_adc_dev_array[i].instance); - ret = rt_hw_adc_register(&_g_adc_dev_array[i].rt_adc, \ - (const char *)_g_adc_dev_array[i].init.name, \ + ret = rt_hw_adc_register(&_g_adc_dev_array[i].rt_adc, + (const char *)_g_adc_dev_array[i].init.name, &_g_adc_ops, (void *)_g_adc_dev_array[i].instance); if (ret != RT_EOK) { diff --git a/bsp/hc32/libraries/hc32_drivers/drv_adc.h b/bsp/hc32/libraries/hc32_drivers/drv_adc.h index 17ec7654d31..34fc78dc482 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_adc.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_adc.h @@ -25,8 +25,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif @@ -73,7 +72,7 @@ struct adc_dev_priv_params /******************************************************************************* * Global pre-processor symbols/macros ('#define') ******************************************************************************/ -#define ADC_USING_EOCA_DMA_FLAG (1U) +#define ADC_USING_EOCA_DMA_FLAG (1U) /******************************************************************************* * Global variable definitions ('extern') diff --git a/bsp/hc32/libraries/hc32_drivers/drv_can.c b/bsp/hc32/libraries/hc32_drivers/drv_can.c index 9135661fa3a..4ed40ad3097 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_can.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_can.c @@ -9,6 +9,8 @@ * 2022-06-07 xiaoxiaolisunny add hc32f460 series * 2022-06-08 CDT fix a bug of RT_CAN_CMD_SET_FILTER * 2022-06-15 lianghongquan fix bug, CAN_FILTER_COUNT, RT_CAN_CMD_SET_FILTER, interrupt setup and processing. + * 2026-05-27 CDT support HC32F4A2. + * 2026-06-24 CDT Added _can_sendmsg_nonblocking. */ #include "drv_can.h" @@ -16,90 +18,90 @@ #include #if defined(BSP_USING_CAN) -#define LOG_TAG "drv_can" +#define LOG_TAG "drv_can" #if defined(BSP_USING_CAN1) || defined(BSP_USING_CAN2) || defined(BSP_USING_CAN3) -#if defined(RT_CAN_USING_CANFD) && defined(HC32F460) - #error "Selected mcu does not support canfd!" +#if defined(RT_CAN_USING_CANFD) && (defined(HC32F460) || defined(HC32F467)) +#error "Selected mcu does not support canfd!" #endif -#define TSEG1_MIN_FOR_CAN2_0 (2U) -#define TSEG1_MAX_FOR_CAN2_0 (65U) -#define TSEG2_MIN_FOR_CAN2_0 (1U) -#define TSEG2_MAX_FOR_CAN2_0 (8U) -#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8) - #define TSJW_MIN_FOR_CAN2_0 (1U) - #define TSJW_MAX_FOR_CAN2_0 (16U) +#define TSEG1_MIN_FOR_CAN2_0 (2U) +#define TSEG1_MAX_FOR_CAN2_0 (65U) +#define TSEG2_MIN_FOR_CAN2_0 (1U) +#define TSEG2_MAX_FOR_CAN2_0 (8U) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F4A8) || defined(HC32F467) +#define TSJW_MIN_FOR_CAN2_0 (1U) +#define TSJW_MAX_FOR_CAN2_0 (16U) #elif defined(HC32F460) - #define TSJW_MIN_FOR_CAN2_0 (1U) - #define TSJW_MAX_FOR_CAN2_0 (8U) +#define TSJW_MIN_FOR_CAN2_0 (1U) +#define TSJW_MAX_FOR_CAN2_0 (8U) #endif -#define NUM_TQ_MIN_FOR_CAN2_0 (8U) -#define NUM_TQ_MAX_FOR_CAN2_0 (TSEG1_MAX_FOR_CAN2_0 + TSEG2_MAX_FOR_CAN2_0) +#define NUM_TQ_MIN_FOR_CAN2_0 (8U) +#define NUM_TQ_MAX_FOR_CAN2_0 (TSEG1_MAX_FOR_CAN2_0 + TSEG2_MAX_FOR_CAN2_0) -#define CAN_BIT_TIMING_CAN2_0 (1U << 0) +#define CAN_BIT_TIMING_CAN2_0 (1U << 0) -#define IS_VALID_PRIV_MODE(mode) ((mode == RT_CAN_MODE_PRIV) || (mode == RT_CAN_MODE_NOPRIV)) -#define IS_VALID_WORK_MODE(mode) (mode <= RT_CAN_MODE_LOOPBACKANLISTEN) -#define IS_VALID_BAUD_RATE_CAN2_0(baud) (baud == (CAN10kBaud) || baud == (CAN20kBaud) || \ - baud == (CAN50kBaud) || baud == (CAN100kBaud) || \ - baud == (CAN125kBaud) || baud == (CAN250kBaud) || \ - baud == (CAN500kBaud) || baud == (CAN800kBaud) || \ - baud == (CAN1MBaud)) +#define IS_VALID_PRIV_MODE(mode) ((mode == RT_CAN_MODE_PRIV) || (mode == RT_CAN_MODE_NOPRIV)) +#define IS_VALID_WORK_MODE(mode) (mode <= RT_CAN_MODE_LOOPBACKANLISTEN) +#define IS_VALID_BAUD_RATE_CAN2_0(baud) (baud == (CAN10kBaud) || baud == (CAN20kBaud) || \ + baud == (CAN50kBaud) || baud == (CAN100kBaud) || \ + baud == (CAN125kBaud) || baud == (CAN250kBaud) || \ + baud == (CAN500kBaud) || baud == (CAN800kBaud) || \ + baud == (CAN1MBaud)) #if defined(RT_CAN_USING_CANFD) -#define TSEG1_MIN_FOR_CANFD_ARBITRATION (2U) -#define TSEG1_MAX_FOR_CANFD_ARBITRATION (65U) -#define TSEG2_MIN_FOR_CANFD_ARBITRATION (1U) -#define TSEG2_MAX_FOR_CANFD_ARBITRATION (32U) -#define TSJW_MIN_FOR_CANFD_ARBITRATION (1U) -#define TSJW_MAX_FOR_CANFD_ARBITRATION (16U) - -#define TSEG1_MIN_FOR_CANFD_DATA (2U) -#define TSEG1_MAX_FOR_CANFD_DATA (17U) -#define TSEG2_MIN_FOR_CANFD_DATA (1U) -#define TSEG2_MAX_FOR_CANFD_DATA (8U) -#define TSJW_MIN_FOR_CANFD_DATA (1U) -#define TSJW_MAX_FOR_CANFD_DATA (8U) - -#define NUM_TQ_MIN_FOR_CANFD_ARBITRATION (8U) -#define NUM_TQ_MAX_FOR_CANFD_ARBITRATION (TSEG1_MAX_FOR_CANFD_ARBITRATION + TSEG2_MAX_FOR_CANFD_ARBITRATION) -#define NUM_TQ_MIN_FOR_CANFD_DATA (8U) -#define NUM_TQ_MAX_FOR_CANFD_DATA (TSEG1_MAX_FOR_CANFD_DATA + TSEG2_MAX_FOR_CANFD_DATA) - -#define IS_VALID_BAUD_RATE_CANFD_ARBITRATION(baud) IS_VALID_BAUD_RATE_CAN2_0(baud) -#define IS_VALID_BAUD_RATE_CANFD_DATA(baud) (baud == (CAN10kBaud) || baud == (CAN20kBaud) || \ - baud == (CAN50kBaud) || baud == (CAN100kBaud) || \ - baud == (CAN125kBaud) || baud == (CAN250kBaud) || \ - baud == (CAN500kBaud) || baud == (CAN800kBaud) || \ - baud == (CAN1MBaud) || \ - baud == (CANFD_DATA_BAUD_2M) || \ - baud == (CANFD_DATA_BAUD_4M) || \ - baud == (CANFD_DATA_BAUD_5M) || \ - baud == (CANFD_DATA_BAUD_8M)) -#define IS_CAN_FRAME(frame) ((frame) == CAN_FRAME_CLASSIC || \ - (frame) == CAN_FRAME_ISO_FD || \ - (frame) == CAN_FRAME_NON_ISO_FD) - -#define CAN_BIT_TIMING_CANFD_ARBITRATION (1U << 1) -#define CAN_BIT_TIMING_CANFD_DATA (1U << 2) -#define CAN_BIT_TIMING_TABLE_NUM (3U) +#define TSEG1_MIN_FOR_CANFD_ARBITRATION (2U) +#define TSEG1_MAX_FOR_CANFD_ARBITRATION (65U) +#define TSEG2_MIN_FOR_CANFD_ARBITRATION (1U) +#define TSEG2_MAX_FOR_CANFD_ARBITRATION (32U) +#define TSJW_MIN_FOR_CANFD_ARBITRATION (1U) +#define TSJW_MAX_FOR_CANFD_ARBITRATION (16U) + +#define TSEG1_MIN_FOR_CANFD_DATA (2U) +#define TSEG1_MAX_FOR_CANFD_DATA (17U) +#define TSEG2_MIN_FOR_CANFD_DATA (1U) +#define TSEG2_MAX_FOR_CANFD_DATA (8U) +#define TSJW_MIN_FOR_CANFD_DATA (1U) +#define TSJW_MAX_FOR_CANFD_DATA (8U) + +#define NUM_TQ_MIN_FOR_CANFD_ARBITRATION (8U) +#define NUM_TQ_MAX_FOR_CANFD_ARBITRATION (TSEG1_MAX_FOR_CANFD_ARBITRATION + TSEG2_MAX_FOR_CANFD_ARBITRATION) +#define NUM_TQ_MIN_FOR_CANFD_DATA (8U) +#define NUM_TQ_MAX_FOR_CANFD_DATA (TSEG1_MAX_FOR_CANFD_DATA + TSEG2_MAX_FOR_CANFD_DATA) + +#define IS_VALID_BAUD_RATE_CANFD_ARBITRATION(baud) IS_VALID_BAUD_RATE_CAN2_0(baud) +#define IS_VALID_BAUD_RATE_CANFD_DATA(baud) (baud == (CAN10kBaud) || baud == (CAN20kBaud) || \ + baud == (CAN50kBaud) || baud == (CAN100kBaud) || \ + baud == (CAN125kBaud) || baud == (CAN250kBaud) || \ + baud == (CAN500kBaud) || baud == (CAN800kBaud) || \ + baud == (CAN1MBaud) || \ + baud == (CANFD_DATA_BAUD_2M) || \ + baud == (CANFD_DATA_BAUD_4M) || \ + baud == (CANFD_DATA_BAUD_5M) || \ + baud == (CANFD_DATA_BAUD_8M)) +#define IS_CAN_FRAME(frame) ((frame) == CAN_FRAME_CLASSIC || \ + (frame) == CAN_FRAME_ISO_FD || \ + (frame) == CAN_FRAME_NON_ISO_FD) + +#define CAN_BIT_TIMING_CANFD_ARBITRATION (1U << 1) +#define CAN_BIT_TIMING_CANFD_DATA (1U << 2) +#define CAN_BIT_TIMING_TABLE_NUM (3U) #endif -#define NUM_PRESCALE_MAX (256U) -#if defined(HC32F4A0) || defined(HC32F4A8) - #define CAN_FILTER_COUNT (16U) - #define CAN1_INT_SRC (INT_SRC_CAN1_HOST) - #define CAN2_INT_SRC (INT_SRC_CAN2_HOST) -#elif defined (HC32F460) - #define CAN_FILTER_COUNT (8U) - #define CAN1_INT_SRC (INT_SRC_CAN_INT) -#elif defined (HC32F472) - #define CAN_FILTER_COUNT (16U) - #define CAN1_INT_SRC (INT_SRC_CAN1_HOST) - #define CAN2_INT_SRC (INT_SRC_CAN2_HOST) - #define CAN3_INT_SRC (INT_SRC_CAN3_HOST) +#define NUM_PRESCALE_MAX (256U) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) +#define CAN_FILTER_COUNT (16U) +#define CAN1_INT_SRC (INT_SRC_CAN1_HOST) +#define CAN2_INT_SRC (INT_SRC_CAN2_HOST) +#elif defined(HC32F460) +#define CAN_FILTER_COUNT (8U) +#define CAN1_INT_SRC (INT_SRC_CAN_INT) +#elif defined(HC32F472) +#define CAN_FILTER_COUNT (16U) +#define CAN1_INT_SRC (INT_SRC_CAN1_HOST) +#define CAN2_INT_SRC (INT_SRC_CAN2_HOST) +#define CAN3_INT_SRC (INT_SRC_CAN3_HOST) #endif @@ -145,17 +147,16 @@ typedef struct } can_bit_timing_table_t; #ifndef RT_CAN_USING_CANFD -static const struct can_baud_rate_tab _g_baudrate_tab[] = -{ - {CAN1MBaud, CAN_BIT_TIME_CONFIG_1M_BAUD}, - {CAN800kBaud, CAN_BIT_TIME_CONFIG_800K_BAUD}, - {CAN500kBaud, CAN_BIT_TIME_CONFIG_500K_BAUD}, - {CAN250kBaud, CAN_BIT_TIME_CONFIG_250K_BAUD}, - {CAN125kBaud, CAN_BIT_TIME_CONFIG_125K_BAUD}, - {CAN100kBaud, CAN_BIT_TIME_CONFIG_100K_BAUD}, - {CAN50kBaud, CAN_BIT_TIME_CONFIG_50K_BAUD}, - {CAN20kBaud, CAN_BIT_TIME_CONFIG_20K_BAUD}, - {CAN10kBaud, CAN_BIT_TIME_CONFIG_10K_BAUD}, +static const struct can_baud_rate_tab _g_baudrate_tab[] = { + { CAN1MBaud, CAN_BIT_TIME_CONFIG_1M_BAUD }, + { CAN800kBaud, CAN_BIT_TIME_CONFIG_800K_BAUD }, + { CAN500kBaud, CAN_BIT_TIME_CONFIG_500K_BAUD }, + { CAN250kBaud, CAN_BIT_TIME_CONFIG_250K_BAUD }, + { CAN125kBaud, CAN_BIT_TIME_CONFIG_125K_BAUD }, + { CAN100kBaud, CAN_BIT_TIME_CONFIG_100K_BAUD }, + { CAN50kBaud, CAN_BIT_TIME_CONFIG_50K_BAUD }, + { CAN20kBaud, CAN_BIT_TIME_CONFIG_20K_BAUD }, + { CAN10kBaud, CAN_BIT_TIME_CONFIG_10K_BAUD }, }; #endif @@ -168,8 +169,7 @@ typedef struct } can_device; #ifdef RT_CAN_USING_CANFD -static const can_bit_timing_table_t _g_can_bit_timing_tbl[CAN_BIT_TIMING_TABLE_NUM] = -{ +static const can_bit_timing_table_t _g_can_bit_timing_tbl[CAN_BIT_TIMING_TABLE_NUM] = { { .tq_min = NUM_TQ_MIN_FOR_CAN2_0, .tq_max = NUM_TQ_MAX_FOR_CAN2_0, @@ -205,54 +205,52 @@ static const can_bit_timing_table_t _g_can_bit_timing_tbl[CAN_BIT_TIMING_TABLE_N } }; -static const struct canfd_baud_rate_tab _g_baudrate_fd[] = -{ - {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 1U, 64U, 16U, 16U}, - {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 1U, 32U, 8U, 8U}, - {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 1U, 16U, 4U, 4U}, - {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 8U, 2U, 2U}, - {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 4U, 1U, 1U}, - {CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 3U, 1U, 1U}, - {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 2U, 64U, 16U, 16U}, - {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 1U, 64U, 16U, 16U}, - {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 2U, 16U, 4U, 4U}, - {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 16U, 4U, 4U}, - {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 8U, 2U, 2U}, - {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 6U, 2U, 2U}, - {CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 4U, 1U, 1U}, - {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 4U, 64U, 16U}, - {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 2U, 64U, 16U}, - {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 4U, 16U, 4U, 4U}, - {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 2U, 16U, 4U, 4U}, - {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 16U, 4U, 4U}, - {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 12U, 4U, 4U}, - {CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 8U, 2U, 2U}, +static const struct canfd_baud_rate_tab _g_baudrate_fd[] = { + { CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 1U, 64U, 16U, 16U }, + { CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 1U, 32U, 8U, 8U }, + { CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 1U, 16U, 4U, 4U }, + { CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 8U, 2U, 2U }, + { CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 4U, 1U, 1U }, + { CAN_CLOCK_SRC_20M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 3U, 1U, 1U }, + { CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 2U, 64U, 16U, 16U }, + { CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 1U, 64U, 16U, 16U }, + { CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 2U, 16U, 4U, 4U }, + { CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 1U, 16U, 4U, 4U }, + { CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 8U, 2U, 2U }, + { CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 6U, 2U, 2U }, + { CAN_CLOCK_SRC_40M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 4U, 1U, 1U }, + { CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_250K, 4U, 64U, 16U }, + { CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_ARBITRATION, CANFD_ARBITRATION_BAUD_500K, 2U, 64U, 16U }, + { CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_1M, 4U, 16U, 4U, 4U }, + { CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_2M, 2U, 16U, 4U, 4U }, + { CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_4M, 1U, 16U, 4U, 4U }, + { CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_5M, 1U, 12U, 4U, 4U }, + { CAN_CLOCK_SRC_80M, CAN_BIT_TIMING_CANFD_DATA, CANFD_DATA_BAUD_8M, 1U, 8U, 2U, 2U }, }; #endif -static can_device _g_can_dev_array[] = -{ +static can_device _g_can_dev_array[] = { #ifdef BSP_USING_CAN1 { - {0}, + { 0 }, CAN1_INIT_PARAMS, -#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F4A8) || defined(HC32F467) .instance = CM_CAN1, -#elif defined (HC32F460) +#elif defined(HC32F460) .instance = CM_CAN, #endif }, #endif #ifdef BSP_USING_CAN2 { - {0}, + { 0 }, CAN2_INIT_PARAMS, .instance = CM_CAN2, }, #endif #ifdef BSP_USING_CAN3 { - {0}, + { 0 }, CAN3_INIT_PARAMS, .instance = CM_CAN3, }, @@ -435,7 +433,7 @@ static uint32_t _get_can_clk_src(CM_CAN_TypeDef *CANx) } static rt_bool_t _get_can_bit_timing_default(uint32_t can_clk, rt_uint32_t baud, rt_uint32_t option, - stc_can_bit_time_config_t *p_stc_bit_cfg) + stc_can_bit_time_config_t *p_stc_bit_cfg) { rt_uint32_t len, index; rt_bool_t found = RT_FALSE; @@ -443,9 +441,8 @@ static rt_bool_t _get_can_bit_timing_default(uint32_t can_clk, rt_uint32_t baud, len = sizeof(_g_baudrate_fd) / sizeof(_g_baudrate_fd[0]); for (index = 0; index < len; index++) { - if ((_g_baudrate_fd[index].clk_src == can_clk) && \ - ((_g_baudrate_fd[index].phase & option) == option) \ - ) + if ((_g_baudrate_fd[index].clk_src == can_clk) && + ((_g_baudrate_fd[index].phase & option) == option)) { if (_g_baudrate_fd[index].baud == baud) { @@ -484,7 +481,7 @@ static inline void _get_can_bit_timing_fd(stc_canfd_config_t *p_ll_time, struct } static rt_err_t _get_can_closest_prescaler(uint32_t num_tq_mul_prescaler, uint32_t start_prescaler, - uint32_t max_tq, uint32_t min_tq) + uint32_t max_tq, uint32_t min_tq) { rt_bool_t has_found = RT_FALSE; uint32_t prescaler = start_prescaler; @@ -559,8 +556,8 @@ static rt_err_t _calc_can_bit_timing(CM_CAN_TypeDef *CANx, int option, uint32_t while (!has_found) { current_prescaler = _get_can_closest_prescaler(num_tq_mul_prescaler, start_prescaler, - tbl->tq_max, - tbl->tq_min); + tbl->tq_max, + tbl->tq_min); if ((current_prescaler < start_prescaler) || (current_prescaler > NUM_PRESCALE_MAX)) { break; @@ -606,8 +603,7 @@ static rt_err_t _calc_can_bit_timing(CM_CAN_TypeDef *CANx, int option, uint32_t p_stc_bit_cfg->u32Prescaler = current_prescaler; status = RT_EOK; } - } - while (RT_FALSE); + } while (RT_FALSE); return status; } @@ -673,7 +669,7 @@ static rt_err_t _config_can_filter(can_device *p_can_dev, void *arg) static rt_err_t _config_can_work_mode(can_device *p_can_dev, void *arg) { rt_err_t rt_ret = RT_EOK; - rt_uint32_t argval = (rt_uint32_t) arg; + rt_uint32_t argval = (rt_uint32_t)arg; if (argval == p_can_dev->rt_can.config.mode) { @@ -691,7 +687,7 @@ static rt_err_t _config_can_work_mode(can_device *p_can_dev, void *arg) static rt_err_t _config_can_priv_mode(can_device *p_can_dev, void *arg) { rt_err_t rt_ret = RT_EOK; - rt_uint32_t argval = (rt_uint32_t) arg; + rt_uint32_t argval = (rt_uint32_t)arg; RT_ASSERT(IS_VALID_PRIV_MODE(argval)); p_can_dev->rt_can.config.privmode = argval; @@ -779,15 +775,15 @@ static rt_err_t _canfd_control(can_device *p_can_dev, int cmd, void *arg) switch (cmd) { case RT_CAN_CMD_SET_BAUD: - argval = (rt_uint32_t) arg; + argval = (rt_uint32_t)arg; RT_ASSERT(IS_VALID_BAUD_RATE_CANFD_ARBITRATION(argval)); if (p_can_dev->rt_can.config.baud_rate == argval) { break; } - timing_stat = _calc_can_bit_timing(p_can_dev->instance, \ - CAN_BIT_TIMING_CANFD_ARBITRATION, \ - argval, \ + timing_stat = _calc_can_bit_timing(p_can_dev->instance, + CAN_BIT_TIMING_CANFD_ARBITRATION, + argval, &p_can_dev->ll_init.stcBitCfg); if (timing_stat != RT_EOK) { @@ -797,7 +793,7 @@ static rt_err_t _canfd_control(can_device *p_can_dev, int cmd, void *arg) p_can_dev->rt_can.config.baud_rate = argval; break; case RT_CAN_CMD_SET_CANFD: - argval = (rt_uint32_t) arg; + argval = (rt_uint32_t)arg; if (p_can_dev->rt_can.config.enable_canfd == argval) { break; @@ -816,15 +812,15 @@ static rt_err_t _canfd_control(can_device *p_can_dev, int cmd, void *arg) #endif break; case RT_CAN_CMD_SET_BAUD_FD: - argval = (rt_uint32_t) arg; + argval = (rt_uint32_t)arg; RT_ASSERT(IS_VALID_BAUD_RATE_CANFD_DATA(argval)); if (p_can_dev->rt_can.config.baud_rate_fd == argval) { break; } - timing_stat = _calc_can_bit_timing(p_can_dev->instance, \ - CAN_BIT_TIMING_CANFD_DATA, \ - argval, \ + timing_stat = _calc_can_bit_timing(p_can_dev->instance, + CAN_BIT_TIMING_CANFD_DATA, + argval, &p_can_dev->ll_init.pstcCanFd->stcBitCfg); if (timing_stat != RT_EOK) { @@ -866,17 +862,17 @@ static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg { RT_ASSERT(IS_VALID_BAUD_RATE_CANFD_ARBITRATION(cfg->baud_rate)); RT_ASSERT(IS_VALID_BAUD_RATE_CANFD_DATA(cfg->baud_rate_fd)); - rt_ret = _calc_can_bit_timing(p_can_dev->instance, \ - CAN_BIT_TIMING_CANFD_ARBITRATION, \ - cfg->baud_rate, \ + rt_ret = _calc_can_bit_timing(p_can_dev->instance, + CAN_BIT_TIMING_CANFD_ARBITRATION, + cfg->baud_rate, &p_can_dev->ll_init.stcBitCfg); if (rt_ret != RT_EOK) { return rt_ret; } - rt_ret = _calc_can_bit_timing(p_can_dev->instance, \ - CAN_BIT_TIMING_CANFD_DATA, \ - cfg->baud_rate_fd, \ + rt_ret = _calc_can_bit_timing(p_can_dev->instance, + CAN_BIT_TIMING_CANFD_DATA, + cfg->baud_rate_fd, &p_can_dev->ll_init.pstcCanFd->stcBitCfg); if (rt_ret != RT_EOK) { @@ -898,7 +894,7 @@ static rt_err_t _can_config(struct rt_can_device *can, struct can_configure *cfg /* restore unmodifiable member */ if ((p_can_dev->rt_can.parent.open_flag & RT_DEVICE_OFLAG_OPEN) == RT_DEVICE_OFLAG_OPEN) { - p_can_dev->rt_can.config.msgboxsz = pre_config.msgboxsz; + p_can_dev->rt_can.config.msgboxsz = pre_config.msgboxsz; p_can_dev->rt_can.config.ticks = pre_config.ticks; } #ifdef RT_CAN_USING_HDR @@ -938,7 +934,7 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) case RT_CAN_CMD_GET_STATUS: { struct rt_can_status *rt_can_stat = (struct rt_can_status *)arg; - stc_can_error_info_t stcErr = {0}; + stc_can_error_info_t stcErr = { 0 }; CAN_GetErrorInfo(p_can_dev->instance, &stcErr); rt_can_stat->rcverrcnt = stcErr.u8RxErrorCount; rt_can_stat->snderrcnt = stcErr.u8TxErrorCount; @@ -954,17 +950,17 @@ static rt_err_t _can_control(struct rt_can_device *can, int cmd, void *arg) #endif default: return -(RT_EINVAL); - } return RT_EOK; } static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_uint32_t box_num) { - struct rt_can_msg *pmsg = (struct rt_can_msg *) buf; - stc_can_tx_frame_t stc_tx_frame = {0}; + struct rt_can_msg *pmsg = (struct rt_can_msg *)buf; + stc_can_tx_frame_t stc_tx_frame = { 0 }; int32_t ll_ret; + (void)box_num; RT_ASSERT(can != RT_NULL); can_device *p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can); RT_ASSERT(p_can_dev); @@ -1008,6 +1004,11 @@ static rt_ssize_t _can_sendmsg(struct rt_can_device *can, const void *buf, rt_ui return RT_EOK; } +rt_ssize_t _can_sendmsg_nonblocking(struct rt_can_device *can, const void *buf) +{ + return _can_sendmsg(can, buf, 0); +} + static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t fifo) { int32_t ll_ret; @@ -1018,7 +1019,7 @@ static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t can_device *p_can_dev = (can_device *)rt_container_of(can, can_device, rt_can); RT_ASSERT(p_can_dev); - pmsg = (struct rt_can_msg *) buf; + pmsg = (struct rt_can_msg *)buf; /* get data */ ll_ret = CAN_GetRxFrame(p_can_dev->instance, &ll_rx_frame); if (ll_ret != LL_OK) @@ -1058,12 +1059,12 @@ static rt_ssize_t _can_recvmsg(struct rt_can_device *can, void *buf, rt_uint32_t return RT_EOK; } -static const struct rt_can_ops _can_ops = -{ +static const struct rt_can_ops _can_ops = { _can_config, _can_control, _can_sendmsg, _can_recvmsg, + _can_sendmsg_nonblocking, }; rt_inline void _isr_can_rx(can_device *p_can_dev) @@ -1140,11 +1141,14 @@ rt_inline void _isr_can_tx(can_device *p_can_dev) if (need_check_single_trans) { - if ((CAN_GetStatus(p_can_dev->instance, CAN_FLAG_BUS_ERR) != SET) \ - || (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST) != SET)) + if ((CAN_GetStatus(p_can_dev->instance, CAN_FLAG_BUS_ERR) != SET) && (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST) != SET)) { is_tx_done = RT_TRUE; } + else + { + rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_TX_FAIL); + } } if (is_tx_done) { @@ -1153,7 +1157,6 @@ rt_inline void _isr_can_tx(can_device *p_can_dev) if (CAN_GetStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST) == SET) { - rt_hw_can_isr(&p_can_dev->rt_can, RT_CAN_EVENT_TX_FAIL); CAN_ClearStatus(p_can_dev->instance, CAN_FLAG_ARBITR_LOST); } } @@ -1266,7 +1269,7 @@ void CAN3_Handler(void) static void _enable_can_clock(void) { #if defined(BSP_USING_CAN1) -#if defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F4A8) || defined(HC32F467) FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN1, ENABLE); #elif defined(HC32F460) FCG_Fcg1PeriphClockCmd(FCG1_PERIPH_CAN, ENABLE); @@ -1329,7 +1332,7 @@ static void _init_ll_struct_filter(can_device *p_can_dev) static void _init_default_cfg(can_device *p_can_dev) { - struct can_configure rt_can_config = CANDEFAULTCONFIG; + struct can_configure rt_can_config = CANDEFAULTCONFIG; rt_can_config.privmode = RT_CAN_MODE_NOPRIV; rt_can_config.ticks = 50; @@ -1368,7 +1371,7 @@ int rt_hw_can_init(void) /* register CAN device */ rt_hw_board_can_init(_g_can_dev_array[i].instance); - rt_hw_can_register(&_g_can_dev_array[i].rt_can, \ + rt_hw_can_register(&_g_can_dev_array[i].rt_can, _g_can_dev_array[i].init.name, &_can_ops, &_g_can_dev_array[i]); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_can.h b/bsp/hc32/libraries/hc32_drivers/drv_can.h index 713b2211db8..d3b36aa4b96 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_can.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_can.h @@ -26,25 +26,25 @@ extern "C" { * but in range [CAN_SAMPLEPOINT_MIN/1000,CAN_SAMPLEPOINT_MAX/1000] * this may not match with your application */ -#define CAN_SAMPLEPOINT_MIN (750U) -#define CAN_SAMPLEPOINT_MAX (800U) +#define CAN_SAMPLEPOINT_MIN (750U) +#define CAN_SAMPLEPOINT_MAX (800U) -#define CAN_CLOCK_SRC_20M (20*1000*1000UL) -#define CAN_CLOCK_SRC_40M (40*1000*1000UL) -#define CAN_CLOCK_SRC_80M (80*1000*1000UL) +#define CAN_CLOCK_SRC_20M (20 * 1000 * 1000UL) +#define CAN_CLOCK_SRC_40M (40 * 1000 * 1000UL) +#define CAN_CLOCK_SRC_80M (80 * 1000 * 1000UL) -#define CANFD_ARBITRATION_BAUD_250K (250*1000UL) -#define CANFD_ARBITRATION_BAUD_500K (500*1000UL) +#define CANFD_ARBITRATION_BAUD_250K (250 * 1000UL) +#define CANFD_ARBITRATION_BAUD_500K (500 * 1000UL) -#define CANFD_DATA_BAUD_1M (1*1000*1000UL) -#define CANFD_DATA_BAUD_2M (2*1000*1000UL) -#define CANFD_DATA_BAUD_4M (4*1000*1000UL) -#define CANFD_DATA_BAUD_5M (5*1000*1000UL) -#define CANFD_DATA_BAUD_8M (8*1000*1000UL) +#define CANFD_DATA_BAUD_1M (1 * 1000 * 1000UL) +#define CANFD_DATA_BAUD_2M (2 * 1000 * 1000UL) +#define CANFD_DATA_BAUD_4M (4 * 1000 * 1000UL) +#define CANFD_DATA_BAUD_5M (5 * 1000 * 1000UL) +#define CANFD_DATA_BAUD_8M (8 * 1000 * 1000UL) -#define CAN_FRAME_CLASSIC (0x0U) -#define CAN_FRAME_ISO_FD (0x2U) -#define CAN_FRAME_NON_ISO_FD (0x4U) +#define CAN_FRAME_CLASSIC (0x0U) +#define CAN_FRAME_ISO_FD (0x2U) +#define CAN_FRAME_NON_ISO_FD (0x4U) /* hc32 can device */ struct can_dev_init_params diff --git a/bsp/hc32/libraries/hc32_drivers/drv_common.c b/bsp/hc32/libraries/hc32_drivers/drv_common.c index f286c5dc1bf..ac90919cd2e 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_common.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_common.c @@ -10,20 +10,20 @@ #include "board.h" -#define DBG_TAG "drv_common" -#define DBG_LVL DBG_INFO +#define DBG_TAG "drv_common" +#define DBG_LVL DBG_INFO #include #ifdef RT_USING_PIN - #include +#include #endif #ifdef RT_USING_SERIAL - #ifdef RT_USING_SERIAL_V2 - #include - #else - #include - #endif /* RT_USING_SERIAL */ +#ifdef RT_USING_SERIAL_V2 +#include +#else +#include +#endif /* RT_USING_SERIAL */ #endif /* RT_USING_SERIAL_V2 */ #ifdef RT_USING_FINSH @@ -61,7 +61,7 @@ void SysTick_Handler(void) /** * Configures the SysTick for OS tick. */ -void SysTick_Configuration(void) +void SysTick_Configuration(void) { rt_uint32_t cnts; stc_clock_freq_t stcClkFreq; @@ -117,7 +117,6 @@ void rt_hw_us_delay(rt_uint32_t us) do { now = SysTick->VAL; - delta = start > now ? start - now : reload + start - now; - } - while (delta < us_tick * us); + delta = start > now ? start - now : reload + start - now; + } while (delta < us_tick * us); } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_common.h b/bsp/hc32/libraries/hc32_drivers/drv_common.h index ee672ab6fdd..c38f1c67543 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_common.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_common.h @@ -18,9 +18,9 @@ extern "C" { void _Error_Handler(char *s, int num); #ifndef Error_Handler -#define Error_Handler() _Error_Handler(__FILE__, __LINE__) +#define Error_Handler() _Error_Handler(__FILE__, __LINE__) #endif -void SysTick_Configuration(void); +void SysTick_Configuration(void); #ifdef __cplusplus } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_crypto.c b/bsp/hc32/libraries/hc32_drivers/drv_crypto.c index 720ddd25728..bcd33ec2a2c 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_crypto.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_crypto.c @@ -8,13 +8,15 @@ * 2023-02-10 CDT first version * 2024-06-11 CDT Fix compiler warning * 2025-07-29 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include "board.h" #if defined(BSP_USING_HWCRYPTO) // #define DRV_DEBUG -#define LOG_TAG "drv_crypto" +#define LOG_TAG "drv_crypto" #include struct hc32_hwcrypto_device @@ -25,10 +27,10 @@ struct hc32_hwcrypto_device #if defined(BSP_USING_CRC) -#define DEFAULT_CRC16_CCITT_POLY (0x1021) /*!< X^16 + X^12 + X^5 + 1 */ -#define DEFAULT_CRC32_POLY (0x04C11DB7) /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X + 1 */ +#define DEFAULT_CRC16_CCITT_POLY (0x1021) /*!< X^16 + X^12 + X^5 + 1 */ +#define DEFAULT_CRC32_POLY (0x04C11DB7) /*!< X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X + 1 */ -static struct hwcrypto_crc_cfg crc_cfgbk = {0}; +static struct hwcrypto_crc_cfg crc_cfgbk = { 0 }; static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, rt_size_t length) { @@ -66,7 +68,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r stcCrcInit.u32RefIn = CRC_REFIN_ENABLE; stcCrcInit.u32RefOut = CRC_REFOUT_ENABLE; break; - default : + default: LOG_E("crc flag parameter error."); goto _exit; } @@ -89,12 +91,12 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r case 32U: stcCrcInit.u32Protocol = CRC_CRC32; break; - default : + default: LOG_E("crc width only support 16/32."); goto _exit; } -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || \ - defined(HC32F334) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || \ + defined(HC32F334) || defined(HC32F467) stcCrcInit.u32InitValue = ctx->crc_cfg.last_val; #elif defined(HC32F4A8) stcCrcInit.u64InitValue = ctx->crc_cfg.last_val; @@ -107,8 +109,8 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r LOG_D("CRC_Init."); rt_memcpy(&crc_cfgbk, &ctx->crc_cfg, sizeof(struct hwcrypto_crc_cfg)); } -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A8) - if (16U == ctx->crc_cfg.width) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) + if (16U == ctx->crc_cfg.width) { (void)CRC_CRC16_AccumulateData(CRC_DATA_WIDTH_8BIT, in, length, (uint16_t *)&result); } @@ -117,7 +119,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r (void)CRC_CRC32_AccumulateData(CRC_DATA_WIDTH_8BIT, in, length, &result); } #elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) - if (16U == ctx->crc_cfg.width) + if (16U == ctx->crc_cfg.width) { result = CRC_CRC16_AccumulateData(CRC_DATA_WIDTH_8BIT, in, length); } @@ -132,8 +134,7 @@ static rt_uint32_t _crc_update(struct hwcrypto_crc *ctx, const rt_uint8_t *in, r return result; } -static const struct hwcrypto_crc_ops crc_ops = -{ +static const struct hwcrypto_crc_ops crc_ops = { .update = _crc_update, }; #endif /* BSP_USING_CRC */ @@ -151,15 +152,14 @@ static rt_uint32_t _rng_rand(struct hwcrypto_rng *ctx) return gen_random; } -static const struct hwcrypto_rng_ops rng_ops = -{ +static const struct hwcrypto_rng_ops rng_ops = { .update = _rng_rand, }; #endif /* BSP_USING_RNG */ #if defined(BSP_USING_HASH) -#define HASH_SHA256_MSG_DIGEST_SIZE (32U) +#define HASH_SHA256_MSG_DIGEST_SIZE (32U) static const rt_uint8_t *hash_in = RT_NULL; static rt_size_t hash_length = 0; @@ -178,7 +178,7 @@ static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt hash_in = in; hash_length = length; break; - default : + default: LOG_E("not support hash type: %x", ctx->parent.type); result = -RT_ERROR; break; @@ -186,7 +186,7 @@ static rt_err_t _hash_update(struct hwcrypto_hash *ctx, const rt_uint8_t *in, rt rt_mutex_release(&hc32_hw_dev->mutex); - return result; + return result; } static rt_err_t _hash_finish(struct hwcrypto_hash *ctx, rt_uint8_t *out, rt_size_t length) @@ -218,7 +218,7 @@ static rt_err_t _hash_finish(struct hwcrypto_hash *ctx, rt_uint8_t *out, rt_size } break; - default : + default: LOG_E("not support hash type: %x", ctx->parent.type); result = -RT_ERROR; break; @@ -230,21 +230,20 @@ static rt_err_t _hash_finish(struct hwcrypto_hash *ctx, rt_uint8_t *out, rt_size return result; } -static const struct hwcrypto_hash_ops hash_ops = -{ +static const struct hwcrypto_hash_ops hash_ops = { .update = _hash_update, - .finish = _hash_finish + .finish = _hash_finish }; #endif /* BSP_USING_HASH */ #if defined(BSP_USING_AES) -#if defined (HC32F4A8) -#define AES_KEY_SIZE_16BYTE (16U) -#define AES_KEY_SIZE_24BYTE (24U) -#define AES_KEY_SIZE_32BYTE (32U) -static stc_ske_init_t stcSkeInit = {0}; -static int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, \ +#if defined(HC32F4A8) +#define AES_KEY_SIZE_16BYTE (16U) +#define AES_KEY_SIZE_24BYTE (24U) +#define AES_KEY_SIZE_32BYTE (32U) +static stc_ske_init_t stcSkeInit = { 0 }; +static int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSize, const uint8_t *pu8Key, uint8_t u8KeySize, uint8_t *pu8Ciphertext) { int32_t i32Ret = LL_ERR_INVD_PARAM; @@ -265,15 +264,15 @@ static int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSiz stcSkeInit.u32Alg = SKE_ALG_AES_256; } stcSkeInit.u32Crypto = SKE_CRYPTO_ENCRYPT; - stcSkeInit.pu8Key = pu8Key; + stcSkeInit.pu8Key = pu8Key; /* Initialize SKE */ i32Ret = SKE_Init(&stcSkeInit); - stcCrypto.u32Alg = stcSkeInit.u32Alg; - stcCrypto.u32Mode = stcSkeInit.u32Mode; + stcCrypto.u32Alg = stcSkeInit.u32Alg; + stcCrypto.u32Mode = stcSkeInit.u32Mode; stcCrypto.u32CryptoSize = u32PlaintextSize; /* Encrypt blocks */ - stcCrypto.pu8In = pu8Plaintext; + stcCrypto.pu8In = pu8Plaintext; stcCrypto.pu8Out = pu8Ciphertext; i32Ret = SKE_CryptoBlocks(&stcCrypto); } @@ -281,7 +280,7 @@ static int32_t AES_Encrypt(const uint8_t *pu8Plaintext, uint32_t u32PlaintextSiz return i32Ret; } -static int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, \ +static int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextSize, const uint8_t *pu8Key, uint8_t u8KeySize, uint8_t *pu8Plaintext) { int32_t i32Ret = LL_ERR_INVD_PARAM; @@ -302,15 +301,15 @@ static int32_t AES_Decrypt(const uint8_t *pu8Ciphertext, uint32_t u32CiphertextS stcSkeInit.u32Alg = SKE_ALG_AES_256; } stcSkeInit.u32Crypto = SKE_CRYPTO_DECRYPT; - stcSkeInit.pu8Key = pu8Key; + stcSkeInit.pu8Key = pu8Key; /* Initialize SKE */ i32Ret = SKE_Init(&stcSkeInit); - stcCrypto.u32Alg = stcSkeInit.u32Alg; - stcCrypto.u32Mode = stcSkeInit.u32Mode; + stcCrypto.u32Alg = stcSkeInit.u32Alg; + stcCrypto.u32Mode = stcSkeInit.u32Mode; stcCrypto.u32CryptoSize = u32CiphertextSize; /* Decrypt blocks */ - stcCrypto.pu8In = pu8Ciphertext; + stcCrypto.pu8In = pu8Ciphertext; stcCrypto.pu8Out = pu8Plaintext; i32Ret = SKE_CryptoBlocks(&stcCrypto); } @@ -325,7 +324,7 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx, struct hwcrypto_symm struct hc32_hwcrypto_device *hc32_hw_dev = (struct hc32_hwcrypto_device *)ctx->parent.device->user_data; rt_mutex_take(&hc32_hw_dev->mutex, RT_WAITING_FOREVER); -#if defined (HC32F4A8) +#if defined(HC32F4A8) SKE_StructInit(&stcSkeInit); switch (ctx->parent.type) { @@ -345,23 +344,24 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx, struct hwcrypto_symm case HWCRYPTO_TYPE_AES_OFB: stcSkeInit.u32Mode = SKE_MD_OFB; break; - default : + default: LOG_E("not support cryp type: %x", ctx->parent.type); break; } stcSkeInit.pu8Iv = ctx->iv; #endif -#if defined (HC32F460) +#if defined(HC32F460) if (ctx->key_bitlen != (AES_KEY_SIZE_16BYTE * 8U)) { LOG_E("not support key bitlen: %d", ctx->key_bitlen); result = -RT_ERROR; goto _exit; } -#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) - if (ctx->key_bitlen != (AES_KEY_SIZE_16BYTE * 8U) && ctx->key_bitlen != (AES_KEY_SIZE_24BYTE * 8U) && \ - ctx->key_bitlen != (AES_KEY_SIZE_32BYTE * 8U)) +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F467) + if (ctx->key_bitlen != (AES_KEY_SIZE_16BYTE * 8U) && ctx->key_bitlen != (AES_KEY_SIZE_24BYTE * 8U) && + ctx->key_bitlen != (AES_KEY_SIZE_32BYTE * 8U)) { LOG_E("not support key bitlen: %d", ctx->key_bitlen); result = -RT_ERROR; @@ -405,8 +405,7 @@ static rt_err_t _cryp_crypt(struct hwcrypto_symmetric *ctx, struct hwcrypto_symm return result; } -static const struct hwcrypto_symmetric_ops cryp_ops = -{ +static const struct hwcrypto_symmetric_ops cryp_ops = { .crypt = _cryp_crypt }; #endif @@ -472,7 +471,8 @@ static rt_err_t _crypto_create(struct rt_hwcrypto_ctx *ctx) case HWCRYPTO_TYPE_RC4: case HWCRYPTO_TYPE_GCM: { -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || \ + defined(HC32F467) /* Enable AES peripheral clock. */ FCG_Fcg0PeriphClockCmd(PWC_FCG0_AES, ENABLE); #elif defined(HC32F4A8) @@ -527,7 +527,8 @@ static void _crypto_destroy(struct rt_hwcrypto_ctx *ctx) case HWCRYPTO_TYPE_3DES: case HWCRYPTO_TYPE_RC4: case HWCRYPTO_TYPE_GCM: -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || \ + defined(HC32F467) AES_DeInit(); FCG_Fcg0PeriphClockCmd(PWC_FCG0_AES, DISABLE); #elif defined(HC32F4A8) @@ -616,8 +617,7 @@ static void _crypto_reset(struct rt_hwcrypto_ctx *ctx) } } -static const struct rt_hwcrypto_ops _ops = -{ +static const struct rt_hwcrypto_ops _ops = { .create = _crypto_create, .destroy = _crypto_destroy, .copy = _crypto_clone, @@ -630,7 +630,7 @@ static int rt_hw_crypto_device_init(void) #if defined(BSP_USING_UQID) stc_efm_unique_id_t pstcUID; - rt_uint32_t cpuid[3] = {0}; + rt_uint32_t cpuid[3] = { 0 }; EFM_GetUID(&pstcUID); cpuid[0] = pstcUID.u32UniqueID0; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_dac.c b/bsp/hc32/libraries/hc32_drivers/drv_dac.c index e2ef22abf49..98cdeb41406 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_dac.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_dac.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2023-05-12 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-05 CDT Support HC32F467 */ #include @@ -20,10 +22,10 @@ #include "board_config.h" /* DAC features */ -#define DAC_CHANNEL_ID_MAX (DAC_CH2 + 1U) -#define DAC_RESOLUTION (12) -#define DAC_LEFT_ALIGNED_DATA_MASK (0xFFF0U) -#define DAC_RIGHT_ALIGNED_DATA_MASK (0xFFFU) +#define DAC_CHANNEL_ID_MAX (DAC_CH2 + 1U) +#define DAC_RESOLUTION (12) +#define DAC_LEFT_ALIGNED_DATA_MASK (0xFFF0U) +#define DAC_RIGHT_ALIGNED_DATA_MASK (0xFFFU) typedef struct { @@ -32,14 +34,13 @@ typedef struct struct dac_dev_init_params init; } dac_device; -static dac_device _g_dac_dev_array[] = -{ +static dac_device _g_dac_dev_array[] = { #ifdef BSP_USING_DAC1 { - {0}, -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) + { 0 }, +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) || defined(HC32F472) || defined(HC32F4A8) || defined(HC32F334) CM_DAC1, -#elif defined (HC32F448) +#elif defined(HC32F448) CM_DAC, #endif DAC1_INIT_PARAMS, @@ -47,21 +48,21 @@ static dac_device _g_dac_dev_array[] = #endif #ifdef BSP_USING_DAC2 { - {0}, + { 0 }, CM_DAC2, DAC2_INIT_PARAMS, }, #endif #ifdef BSP_USING_DAC3 { - {0}, + { 0 }, CM_DAC3, DAC3_INIT_PARAMS, }, #endif #ifdef BSP_USING_DAC4 { - {0}, + { 0 }, CM_DAC4, DAC4_INIT_PARAMS, }, @@ -74,10 +75,10 @@ static rt_uint16_t _dac_get_channel(rt_uint32_t channel) switch (channel) { - case 1: + case 1: ll_channel = DAC_CH1; break; - case 2: + case 2: ll_channel = DAC_CH2; break; default: @@ -137,20 +138,19 @@ static rt_err_t _dac_set_value(struct rt_dac_device *device, rt_uint32_t channel return RT_EOK; } -static const struct rt_dac_ops g_dac_ops = -{ +static const struct rt_dac_ops g_dac_ops = { .disabled = _dac_disabled, - .enabled = _dac_enabled, - .convert = _dac_set_value, + .enabled = _dac_enabled, + .convert = _dac_set_value, .get_resolution = _dac_get_resolution, }; static void _dac_clock_enable(void) { #if defined(BSP_USING_DAC1) -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) || defined(HC32F472) || defined(HC32F4A8) || defined(HC32F334) FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_DAC1, ENABLE); -#elif defined (HC32F448) +#elif defined(HC32F448) FCG_Fcg3PeriphClockCmd(FCG3_PERIPH_DAC, ENABLE); #endif #endif @@ -171,7 +171,7 @@ int rt_hw_dac_init(void) int result = RT_EOK; rt_err_t ret; int i = 0; - stc_dac_init_t stcDacInit = {0}; + stc_dac_init_t stcDacInit = { 0 }; int32_t ll_ret = 0; _dac_clock_enable(); @@ -180,17 +180,17 @@ int rt_hw_dac_init(void) { DAC_DeInit(_g_dac_dev_array[i].instance); stcDacInit.enOutput = (en_functional_state_t)_g_dac_dev_array[i].init.ch1_output_enable; -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) || defined(HC32F448) || defined(HC32F4A8) stcDacInit.u16Src = _g_dac_dev_array[i].init.ch1_data_src; #endif ll_ret = DAC_Init((void *)_g_dac_dev_array[i].instance, DAC_CH1, &stcDacInit); -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F460) -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F460) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) || defined(HC32F448) || defined(HC32F4A8) stcDacInit.u16Src = _g_dac_dev_array[i].init.ch2_data_src; #endif stcDacInit.enOutput = _g_dac_dev_array[i].init.ch2_output_enable; ll_ret = DAC_Init((void *)_g_dac_dev_array[i].instance, DAC_CH2, &stcDacInit); -#elif defined (HC32F334) +#elif defined(HC32F334) if (CM_DAC1 == (void *)_g_dac_dev_array[i].instance) { stcDacInit.enOutput = (en_functional_state_t)_g_dac_dev_array[i].init.ch2_output_enable; @@ -208,22 +208,22 @@ int rt_hw_dac_init(void) DAC_ADCPrioConfig(_g_dac_dev_array[i].instance, _g_dac_dev_array[i].init.dac_adp_sel, ENABLE); DAC_ADCPrioCmd(_g_dac_dev_array[i].instance, (en_functional_state_t)_g_dac_dev_array[i].init.dac_adp_enable); -#if defined (HC32F472) +#if defined(HC32F472) DAC_SetAmpGain(_g_dac_dev_array[i].instance, DAC_CH1, _g_dac_dev_array[i].init.ch1_amp_gain); DAC_SetAmpGain(_g_dac_dev_array[i].instance, DAC_CH2, _g_dac_dev_array[i].init.ch2_amp_gain); #endif DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH1, (en_functional_state_t)_g_dac_dev_array[i].init.ch1_amp_enable); -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F460) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F460) DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH2, _g_dac_dev_array[i].init.ch2_amp_enable); -#elif defined (HC32F334) +#elif defined(HC32F334) if (CM_DAC1 == (void *)_g_dac_dev_array[i].instance) { DAC_AMPCmd(_g_dac_dev_array[i].instance, DAC_CH2, (en_functional_state_t)_g_dac_dev_array[i].init.ch2_amp_enable); } #endif rt_hw_board_dac_init(_g_dac_dev_array[i].instance); - ret = rt_hw_dac_register(&_g_dac_dev_array[i].rt_dac, \ - (const char *)_g_dac_dev_array[i].init.name, \ + ret = rt_hw_dac_register(&_g_dac_dev_array[i].rt_dac, + (const char *)_g_dac_dev_array[i].init.name, &g_dac_ops, (void *)_g_dac_dev_array[i].instance); if (ret == RT_EOK) { diff --git a/bsp/hc32/libraries/hc32_drivers/drv_dac.h b/bsp/hc32/libraries/hc32_drivers/drv_dac.h index 8918b63fd27..f1c86f0f9fa 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_dac.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_dac.h @@ -18,8 +18,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -36,13 +35,13 @@ struct dac_dev_init_params This parameter can be a value of @ref DAC_ADP_SELECT */ rt_bool_t ch1_output_enable; rt_bool_t ch2_output_enable; -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) || defined(HC32F448) || defined(HC32F4A8) uint16_t ch1_data_src; uint16_t ch2_data_src; #endif rt_bool_t ch1_amp_enable; rt_bool_t ch2_amp_enable; -#if defined (HC32F472) +#if defined(HC32F472) uint16_t ch1_amp_gain; uint16_t ch2_amp_gain; #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_dma.h b/bsp/hc32/libraries/hc32_drivers/drv_dma.h index 88656f0c145..994704d083b 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_dma.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_dma.h @@ -23,14 +23,14 @@ extern "C" { struct dma_config { - CM_DMA_TypeDef *Instance; - rt_uint32_t channel; - rt_uint32_t clock; - rt_uint32_t trigger_select; - en_event_src_t trigger_event; - rt_uint32_t flag; - struct hc32_irq_config irq_config; - func_ptr_t irq_callback; + CM_DMA_TypeDef *Instance; + rt_uint32_t channel; + rt_uint32_t clock; + rt_uint32_t trigger_select; + en_event_src_t trigger_event; + rt_uint32_t flag; + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; }; #ifdef __cplusplus diff --git a/bsp/hc32/libraries/hc32_drivers/drv_eth.c b/bsp/hc32/libraries/hc32_drivers/drv_eth.c index 1e52125efb1..9cc6a3be413 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_eth.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_eth.c @@ -24,10 +24,10 @@ * Local pre-processor symbols/macros ('#define') ******************************************************************************/ //#define DRV_DEBUG -#define LOG_TAG "drv.eth" +#define LOG_TAG "drv.eth" #include -#define MAX_ADDR_LEN 6 +#define MAX_ADDR_LEN 6 /******************************************************************************* * Local type definitions ('typedef') @@ -35,26 +35,26 @@ struct hc32_eth { /* inherit from ethernet device */ - struct eth_device parent; + struct eth_device parent; #if !(defined(ETH_PHY_USING_INTERRUPT_MODE)) - rt_timer_t poll_link_timer; + rt_timer_t poll_link_timer; #endif /* interface address info, hw address */ - rt_uint8_t dev_addr[MAX_ADDR_LEN]; + rt_uint8_t dev_addr[MAX_ADDR_LEN]; /* ETH_Speed */ - rt_uint32_t eth_speed; + rt_uint32_t eth_speed; /* ETH_Duplex_Mode */ - rt_uint32_t eth_mode; + rt_uint32_t eth_mode; /* eth irq */ - struct hc32_irq_config irq_config; - func_ptr_t irq_callback; + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; }; /* eth phy status */ enum { - ETH_PHY_LINK = 0x01U, - ETH_PHY_100M = 0x02U, + ETH_PHY_LINK = 0x01U, + ETH_PHY_100M = 0x02U, ETH_PHY_FULL_DUPLEX = 0x04U, }; @@ -77,10 +77,9 @@ static stc_eth_handle_t EthHandle; static stc_eth_dma_desc_t *EthDmaTxDscrTab, *EthDmaRxDscrTab; /* Ethernet Transmit,Receive Buffer */ static rt_uint8_t *EthTxBuff, *EthRxBuff; -static struct hc32_eth hc32_eth_device = -{ - .irq_config = ETH_IRQ_CONFIG, - .irq_callback = eth_global_irq_handle, +static struct hc32_eth hc32_eth_device = { + .irq_config = ETH_IRQ_CONFIG, + .irq_callback = eth_global_irq_handle, }; /******************************************************************************* @@ -108,9 +107,9 @@ static rt_err_t rt_hc32_eth_init(rt_device_t dev) EthHandle.stcCommInit.au8MacAddr[5] = hc32_eth_device.dev_addr[5]; EthHandle.stcCommInit.u32ReceiveMode = ETH_RX_MD_INT; #if defined(ETH_INTERFACE_USING_RMII) - EthHandle.stcCommInit.u32Interface = ETH_MAC_IF_RMII; + EthHandle.stcCommInit.u32Interface = ETH_MAC_IF_RMII; #else - EthHandle.stcCommInit.u32Interface = ETH_MAC_IF_MII; + EthHandle.stcCommInit.u32Interface = ETH_MAC_IF_MII; #endif #if defined(RT_LWIP_USING_HW_CHECKSUM) EthHandle.stcCommInit.u32ChecksumMode = ETH_MAC_CHECKSUM_MD_HW; @@ -190,7 +189,7 @@ static rt_err_t rt_hc32_eth_control(rt_device_t dev, int cmd, void *args) } break; - default : + default: break; } @@ -231,7 +230,7 @@ rt_err_t rt_hc32_eth_tx(rt_device_t dev, struct pbuf *p) while ((byteCnt + bufferOffset) > ETH_TX_BUF_SIZE) { /* Copy data to Tx buffer*/ - SMEMCPY((uint8_t *) & (txBuffer[bufferOffset]), (uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (ETH_TX_BUF_SIZE - bufferOffset)); + SMEMCPY((uint8_t *)&(txBuffer[bufferOffset]), (uint8_t *)&(((uint8_t *)q->payload)[payloadOffset]), (ETH_TX_BUF_SIZE - bufferOffset)); /* Point to next descriptor */ DmaTxDesc = (stc_eth_dma_desc_t *)(DmaTxDesc->u32Buf2NextDescAddr); /* Check if the buffer is available */ @@ -248,7 +247,7 @@ rt_err_t rt_hc32_eth_tx(rt_device_t dev, struct pbuf *p) bufferOffset = 0UL; } /* Copy the remaining bytes */ - SMEMCPY((uint8_t *) & (txBuffer[bufferOffset]), (uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), byteCnt); + SMEMCPY((uint8_t *)&(txBuffer[bufferOffset]), (uint8_t *)&(((uint8_t *)q->payload)[payloadOffset]), byteCnt); bufferOffset = bufferOffset + byteCnt; frameLength = frameLength + byteCnt; } @@ -311,7 +310,7 @@ struct pbuf *rt_hc32_eth_rx(rt_device_t dev) while ((byteCnt + bufferOffset) > ETH_RX_BUF_SIZE) { /* Copy data to pbuf */ - SMEMCPY((uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (uint8_t *) & (rxBuffer[bufferOffset]), (ETH_RX_BUF_SIZE - bufferOffset)); + SMEMCPY((uint8_t *)&(((uint8_t *)q->payload)[payloadOffset]), (uint8_t *)&(rxBuffer[bufferOffset]), (ETH_RX_BUF_SIZE - bufferOffset)); /* Point to next descriptor */ DmaRxDesc = (stc_eth_dma_desc_t *)(DmaRxDesc->u32Buf2NextDescAddr); rxBuffer = (uint8_t *)(DmaRxDesc->u32Buf1Addr); @@ -320,7 +319,7 @@ struct pbuf *rt_hc32_eth_rx(rt_device_t dev) bufferOffset = 0UL; } /* Copy remaining data in pbuf */ - SMEMCPY((uint8_t *) & (((uint8_t *)q->payload)[payloadOffset]), (uint8_t *) & (rxBuffer[bufferOffset]), byteCnt); + SMEMCPY((uint8_t *)&(((uint8_t *)q->payload)[payloadOffset]), (uint8_t *)&(rxBuffer[bufferOffset]), byteCnt); bufferOffset = bufferOffset + byteCnt; } } @@ -378,12 +377,12 @@ static void hc32_phy_link_change(void) { static rt_uint8_t phy_status = 0; rt_uint8_t phy_status_new = 0; -#if defined (ETH_PHY_USING_RTL8201F) +#if defined(ETH_PHY_USING_RTL8201F) uint16_t u16RegVal = 0U; uint16_t u16Page = 0U; #endif -#if defined (ETH_PHY_USING_RTL8201F) +#if defined(ETH_PHY_USING_RTL8201F) /* Switch page */ (void)ETH_PHY_ReadReg(ETH_PHY_ADDR, PHY_PSR, &u16Page); if (u16Page != PHY_PAGE_ADDR_0) @@ -460,7 +459,7 @@ static void hc32_phy_link_change(void) #if defined(ETH_PHY_USING_INTERRUPT_MODE) static void eth_phy_irq_handler(void *args) { -#if defined (ETH_PHY_USING_RTL8201F) +#if defined(ETH_PHY_USING_RTL8201F) rt_uint16_t status = 0; ETH_PHY_ReadReg(ETH_PHY_ADDR, PHY_IISDR, &status); @@ -505,7 +504,7 @@ static void hc32_phy_monitor_thread(void *parameter) ETH_PHY_WriteReg(ETH_PHY_ADDR, PHY_BASIC_CONTROL_REG, PHY_AUTO_NEGOTIATION_MASK); hc32_phy_link_change(); -#if defined (ETH_PHY_USING_RTL8201F) +#if defined(ETH_PHY_USING_RTL8201F) /* Configure PHY LED mode */ u16RegVal = PHY_PAGE_ADDR_7; (void)ETH_PHY_WriteReg(ETH_PHY_ADDR, PHY_PSR, u16RegVal); @@ -533,7 +532,7 @@ static void hc32_phy_monitor_thread(void *parameter) rt_pin_attach_irq(ETH_PHY_INTERRUPT_PIN, PIN_IRQ_MODE_FALLING, eth_phy_irq_handler, (void *)"callbackargs"); rt_pin_irq_enable(ETH_PHY_INTERRUPT_PIN, PIN_IRQ_ENABLE); -#if defined (ETH_PHY_USING_RTL8201F) +#if defined(ETH_PHY_USING_RTL8201F) /* Configure PHY to generate an interrupt when Eth Link state changes */ u16RegVal = PHY_PAGE_ADDR_7; (void)ETH_PHY_WriteReg(ETH_PHY_ADDR, PHY_PSR, u16RegVal); @@ -546,7 +545,7 @@ static void hc32_phy_monitor_thread(void *parameter) #endif #else hc32_eth_device.poll_link_timer = rt_timer_create("eth_phy_link", (void (*)(void *))hc32_phy_link_change, - NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC); + NULL, RT_TICK_PER_SECOND, RT_TIMER_FLAG_PERIODIC); if (!hc32_eth_device.poll_link_timer || rt_timer_start(hc32_eth_device.poll_link_timer) != RT_EOK) { LOG_E("Start eth phy link change detection timer failed"); @@ -592,7 +591,7 @@ static int rt_hw_hc32_eth_init(void) } hc32_eth_device.eth_speed = ETH_MAC_SPEED_100M; - hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_FULL; + hc32_eth_device.eth_mode = ETH_MAC_DUPLEX_MD_FULL; /* 00-80 uid */ hc32_eth_device.dev_addr[0] = 0x02; hc32_eth_device.dev_addr[1] = 0x80; @@ -602,15 +601,15 @@ static int rt_hw_hc32_eth_init(void) hc32_eth_device.dev_addr[4] = (rt_uint8_t)READ_REG32(CM_EFM->UQID2); hc32_eth_device.dev_addr[5] = (rt_uint8_t)(READ_REG32(CM_EFM->UQID2) >> 8U); - hc32_eth_device.parent.parent.init = rt_hc32_eth_init; - hc32_eth_device.parent.parent.open = rt_hc32_eth_open; - hc32_eth_device.parent.parent.close = rt_hc32_eth_close; - hc32_eth_device.parent.parent.read = rt_hc32_eth_read; - hc32_eth_device.parent.parent.write = rt_hc32_eth_write; - hc32_eth_device.parent.parent.control = rt_hc32_eth_control; + hc32_eth_device.parent.parent.init = rt_hc32_eth_init; + hc32_eth_device.parent.parent.open = rt_hc32_eth_open; + hc32_eth_device.parent.parent.close = rt_hc32_eth_close; + hc32_eth_device.parent.parent.read = rt_hc32_eth_read; + hc32_eth_device.parent.parent.write = rt_hc32_eth_write; + hc32_eth_device.parent.parent.control = rt_hc32_eth_control; hc32_eth_device.parent.parent.user_data = RT_NULL; - hc32_eth_device.parent.eth_rx = rt_hc32_eth_rx; - hc32_eth_device.parent.eth_tx = rt_hc32_eth_tx; + hc32_eth_device.parent.eth_rx = rt_hc32_eth_rx; + hc32_eth_device.parent.eth_tx = rt_hc32_eth_tx; /* register eth device */ state = eth_device_init(&(hc32_eth_device.parent), "e0"); if (RT_EOK == state) diff --git a/bsp/hc32/libraries/hc32_drivers/drv_eth.h b/bsp/hc32/libraries/hc32_drivers/drv_eth.h index c5a74d43e9c..086765944ab 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_eth.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_eth.h @@ -25,52 +25,52 @@ extern "C" { /* The PHY basic control register */ -#define PHY_BASIC_CONTROL_REG 0x00U -#define PHY_RESET_MASK (1<<15) -#define PHY_AUTO_NEGOTIATION_MASK (1<<12) +#define PHY_BASIC_CONTROL_REG 0x00U +#define PHY_RESET_MASK (1 << 15) +#define PHY_AUTO_NEGOTIATION_MASK (1 << 12) /* The PHY basic status register */ -#define PHY_BASIC_STATUS_REG 0x01U -#define PHY_LINKED_STATUS_MASK (1<<2) -#define PHY_AUTONEGO_COMPLETE_MASK (1<<5) +#define PHY_BASIC_STATUS_REG 0x01U +#define PHY_LINKED_STATUS_MASK (1 << 2) +#define PHY_AUTONEGO_COMPLETE_MASK (1 << 5) /* The PHY ID one register */ -#define PHY_ID1_REG 0x02U +#define PHY_ID1_REG 0x02U -#if defined (ETH_PHY_USING_RTL8201F) +#if defined(ETH_PHY_USING_RTL8201F) /* Extended PHY Registers */ -#define PHY_PSMR (0x18U) /*!< Power Saving Mode Register */ -#define PHY_IISDR (0x1EU) /*!< Interrupt Indicators and SNR Display Register */ -#define PHY_PSR (0x1FU) /*!< Page Select Register */ -#define PHY_P7_RMSR (0x10U) /*!< RMII Mode Setting Register */ -#define PHY_P7_IWLFR (0x13U) /*!< Interrupt, WOL Enable, and LED Function Registers */ +#define PHY_PSMR (0x18U) /*!< Power Saving Mode Register */ +#define PHY_IISDR (0x1EU) /*!< Interrupt Indicators and SNR Display Register */ +#define PHY_PSR (0x1FU) /*!< Page Select Register */ +#define PHY_P7_RMSR (0x10U) /*!< RMII Mode Setting Register */ +#define PHY_P7_IWLFR (0x13U) /*!< Interrupt, WOL Enable, and LED Function Registers */ /* The following parameters will return to default values after a software reset */ -#define PHY_EN_PWR_SAVE (0x8000U) /*!< Enable Power Saving Mode */ - -#define PHY_FLAG_AUTO_NEGO_ERROR (0x8000U) /*!< Auto-Negotiation Error Interrupt Flag */ -#define PHY_FLAG_SPEED_MODE_CHANGE (0x4000U) /*!< Speed Mode Change Interrupt Flag */ -#define PHY_FLAG_DUPLEX_MODE_CHANGE (0x2000U) /*!< Duplex Mode Change Interrupt Flag */ -#define PHY_FLAG_LINK_STATUS_CHANGE (0x0800U) /*!< Link Status Change Interrupt Flag */ - -#define PHY_PAGE_ADDR_0 (0x0000U) /*!< Page Address 0 (default) */ -#define PHY_PAGE_ADDR_7 (0x0007U) /*!< Page Address 7 */ - -#define PHY_RMII_CLK_DIR (0x1000U) /*!< TXC direction in RMII Mode */ -#define PHY_RMII_MODE (0x0008U) /*!< RMII Mode or MII Mode */ -#define PHY_RMII_RXDV_CRSDV (0x0004U) /*!< CRS_DV or RXDV select */ - -#define PHY_INT_LINK_CHANGE (0x2000U) /*!< Link Change Interrupt Mask */ -#define PHY_INT_DUPLEX_CHANGE (0x1000U) /*!< Duplex Change Interrupt Mask */ -#define PHY_INT_AUTO_NEGO_ERROR (0x0800U) /*!< Auto-Negotiation Error Interrupt Mask */ -#define PHY_LED_WOL_SELECT (0x0400U) /*!< LED and Wake-On-LAN Function Selection */ -#define PHY_LED_SELECT (0x0030U) /*!< Traditional LED Function Selection. */ -#define PHY_LED_SELECT_00 (0x0000U) /*!< LED0: ACT(all) LED1: LINK(100) */ -#define PHY_LED_SELECT_01 (0x0010U) /*!< LED0: LINK(ALL)/ACT(all) LED1: LINK(100) */ -#define PHY_LED_SELECT_10 (0x0020U) /*!< LED0: LINK(10)/ACT(all) LED1: LINK(100) */ -#define PHY_LED_SELECT_11 (0x0030U) /*!< LED0: LINK(10)/ACT(10) LED1: LINK(100)/ACT(100) */ -#define PHY_EN_10M_LED_FUNC (0x0001U) /*!< Enable 10M LPI LED Function */ +#define PHY_EN_PWR_SAVE (0x8000U) /*!< Enable Power Saving Mode */ + +#define PHY_FLAG_AUTO_NEGO_ERROR (0x8000U) /*!< Auto-Negotiation Error Interrupt Flag */ +#define PHY_FLAG_SPEED_MODE_CHANGE (0x4000U) /*!< Speed Mode Change Interrupt Flag */ +#define PHY_FLAG_DUPLEX_MODE_CHANGE (0x2000U) /*!< Duplex Mode Change Interrupt Flag */ +#define PHY_FLAG_LINK_STATUS_CHANGE (0x0800U) /*!< Link Status Change Interrupt Flag */ + +#define PHY_PAGE_ADDR_0 (0x0000U) /*!< Page Address 0 (default) */ +#define PHY_PAGE_ADDR_7 (0x0007U) /*!< Page Address 7 */ + +#define PHY_RMII_CLK_DIR (0x1000U) /*!< TXC direction in RMII Mode */ +#define PHY_RMII_MODE (0x0008U) /*!< RMII Mode or MII Mode */ +#define PHY_RMII_RXDV_CRSDV (0x0004U) /*!< CRS_DV or RXDV select */ + +#define PHY_INT_LINK_CHANGE (0x2000U) /*!< Link Change Interrupt Mask */ +#define PHY_INT_DUPLEX_CHANGE (0x1000U) /*!< Duplex Change Interrupt Mask */ +#define PHY_INT_AUTO_NEGO_ERROR (0x0800U) /*!< Auto-Negotiation Error Interrupt Mask */ +#define PHY_LED_WOL_SELECT (0x0400U) /*!< LED and Wake-On-LAN Function Selection */ +#define PHY_LED_SELECT (0x0030U) /*!< Traditional LED Function Selection. */ +#define PHY_LED_SELECT_00 (0x0000U) /*!< LED0: ACT(all) LED1: LINK(100) */ +#define PHY_LED_SELECT_01 (0x0010U) /*!< LED0: LINK(ALL)/ACT(all) LED1: LINK(100) */ +#define PHY_LED_SELECT_10 (0x0020U) /*!< LED0: LINK(10)/ACT(all) LED1: LINK(100) */ +#define PHY_LED_SELECT_11 (0x0030U) /*!< LED0: LINK(10)/ACT(10) LED1: LINK(100)/ACT(100) */ +#define PHY_EN_10M_LED_FUNC (0x0001U) /*!< Enable 10M LPI LED Function */ #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_flash/drv_flash_f4.c b/bsp/hc32/libraries/hc32_drivers/drv_flash/drv_flash_f4.c index 30c02cee549..48bb75aaa5c 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_flash/drv_flash_f4.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_flash/drv_flash_f4.c @@ -9,6 +9,8 @@ * 2024-06-14 CDT Fixed sector number calculation * 2024-06-18 CDT Support HC32F460,HC32F448,HC32F472 * 2025-07-16 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include "board.h" @@ -18,11 +20,11 @@ #include "drv_flash.h" #if defined(RT_USING_FAL) - #include "fal.h" +#include "fal.h" #endif //#define DRV_DEBUG -#define LOG_TAG "drv.flash" +#define LOG_TAG "drv.flash" #include /** @@ -81,7 +83,8 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) rt_err_t result = RT_EOK; rt_uint32_t newAddr = addr, offsetVal = 0; rt_uint32_t index = 0, u32Cnt = 0; -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) rt_uint32_t FirstSector = 0, NumOfSectors = 0; #endif @@ -101,7 +104,8 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) } /* EFM_FWMC write enable */ EFM_FWMC_Cmd(ENABLE); -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) /* calculate sector information */ FirstSector = addr / EFM_SECTOR_SIZE, NumOfSectors = GetSectorNum(addr, size); @@ -144,7 +148,8 @@ int hc32_flash_write(rt_uint32_t addr, const rt_uint8_t *buf, size_t size) } __exit: -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) /* Sectors enable write protection */ EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, DISABLE); #endif @@ -170,7 +175,8 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size) rt_err_t result = RT_EOK; rt_uint32_t NumOfSectors = 0; rt_uint32_t SectorVal = 0, u32Addr = addr; -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) rt_uint32_t FirstSector = 0; #endif @@ -188,10 +194,11 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size) EFM_FWMC_Cmd(ENABLE); /* calculate sector information */ NumOfSectors = GetSectorNum(addr, size); -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) FirstSector = addr / EFM_SECTOR_SIZE, /* Sectors disable write protection */ - EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, ENABLE); + EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, ENABLE); #endif /* Erase sector */ for (SectorVal = 0U; SectorVal < NumOfSectors; SectorVal++) @@ -203,7 +210,8 @@ int hc32_flash_erase(rt_uint32_t addr, size_t size) } u32Addr += EFM_SECTOR_SIZE; } -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) /* Sectors enable write protection */ EFM_SequenceSectorOperateCmd(FirstSector, NumOfSectors, DISABLE); #endif @@ -223,13 +231,12 @@ static int fal_flash_read(long offset, rt_uint8_t *buf, size_t size); static int fal_flash_write(long offset, const rt_uint8_t *buf, size_t size); static int fal_flash_erase(long offset, size_t size); -const struct fal_flash_dev hc32_onchip_flash = -{ - .name = "onchip_flash", - .addr = HC32_FLASH_START_ADDRESS, - .len = HC32_FLASH_SIZE, - .blk_size = HC32_FLASH_ERASE_GRANULARITY, - .ops = {NULL, fal_flash_read, fal_flash_write, fal_flash_erase}, +const struct fal_flash_dev hc32_onchip_flash = { + .name = "onchip_flash", + .addr = HC32_FLASH_START_ADDRESS, + .len = HC32_FLASH_SIZE, + .blk_size = HC32_FLASH_ERASE_GRANULARITY, + .ops = { NULL, fal_flash_read, fal_flash_write, fal_flash_erase }, .write_gran = HC32_FLASH_WRITE_GRANULARITY }; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c index a7217ec9e15..4f676dd17b8 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_gpio.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_gpio.c @@ -9,6 +9,8 @@ * 2023-10-09 CDT support HC32F448 * 2024-06-12 CDT support external interrupt for HC32F448/HC32F472 * 2025-07-16 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include @@ -20,31 +22,31 @@ #if defined(BSP_USING_GPIO) -#define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F)) -#define PIN_NUM(port, pin) (((((port) & 0x0F) << 4) | ((pin) & 0x0F))) -#define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) & 0x0F)) -#define GPIO_PIN(pin) ((uint16_t)(0x01U << GPIO_PIN_INDEX(pin))) - -#if defined (HC32F4A0) || defined (HC32F4A8) - #define PIN_MAX_NUM ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1) -#elif defined (HC32F460) - #define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1) -#elif defined (HC32F448) - #define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1) -#elif defined (HC32F472) - #define PIN_MAX_NUM ((GPIO_PORT_F * 16) + (__CLZ(__RBIT(GPIO_PIN_08))) + 1) -#elif defined (HC32F334) - #define PIN_MAX_NUM ((GPIO_PORT_F * 16) + (__CLZ(__RBIT(GPIO_PIN_03))) + 1) +#define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F)) +#define PIN_NUM(port, pin) (((((port) & 0x0F) << 4) | ((pin) & 0x0F))) +#define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) & 0x0F)) +#define GPIO_PIN(pin) ((uint16_t)(0x01U << GPIO_PIN_INDEX(pin))) + +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) +#define PIN_MAX_NUM ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1) +#elif defined(HC32F460) +#define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1) +#elif defined(HC32F448) +#define PIN_MAX_NUM ((GPIO_PORT_H * 16) + (__CLZ(__RBIT(GPIO_PIN_02))) + 1) +#elif defined(HC32F472) +#define PIN_MAX_NUM ((GPIO_PORT_F * 16) + (__CLZ(__RBIT(GPIO_PIN_08))) + 1) +#elif defined(HC32F334) +#define PIN_MAX_NUM ((GPIO_PORT_F * 16) + (__CLZ(__RBIT(GPIO_PIN_03))) + 1) #endif -#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) #ifndef HC32_PIN_CONFIG -#define HC32_PIN_CONFIG(pin, callback, config) \ - { \ - .pinbit = pin, \ - .irq_callback = callback, \ - .irq_config = config, \ +#define HC32_PIN_CONFIG(pin, callback, config) \ + { \ + .pinbit = pin, \ + .irq_callback = callback, \ + .irq_config = config, \ } #endif /* HC32_PIN_CONFIG */ @@ -65,18 +67,17 @@ static void extint13_irq_handler(void); static void extint14_irq_handler(void); static void extint15_irq_handler(void); -static struct hc32_pin_irq_map pin_irq_map[] = -{ - HC32_PIN_CONFIG(GPIO_PIN_00, extint0_irq_handler, EXTINT0_IRQ_CONFIG), - HC32_PIN_CONFIG(GPIO_PIN_01, extint1_irq_handler, EXTINT1_IRQ_CONFIG), - HC32_PIN_CONFIG(GPIO_PIN_02, extint2_irq_handler, EXTINT2_IRQ_CONFIG), - HC32_PIN_CONFIG(GPIO_PIN_03, extint3_irq_handler, EXTINT3_IRQ_CONFIG), - HC32_PIN_CONFIG(GPIO_PIN_04, extint4_irq_handler, EXTINT4_IRQ_CONFIG), - HC32_PIN_CONFIG(GPIO_PIN_05, extint5_irq_handler, EXTINT5_IRQ_CONFIG), - HC32_PIN_CONFIG(GPIO_PIN_06, extint6_irq_handler, EXTINT6_IRQ_CONFIG), - HC32_PIN_CONFIG(GPIO_PIN_07, extint7_irq_handler, EXTINT7_IRQ_CONFIG), - HC32_PIN_CONFIG(GPIO_PIN_08, extint8_irq_handler, EXTINT8_IRQ_CONFIG), - HC32_PIN_CONFIG(GPIO_PIN_09, extint9_irq_handler, EXTINT9_IRQ_CONFIG), +static struct hc32_pin_irq_map pin_irq_map[] = { + HC32_PIN_CONFIG(GPIO_PIN_00, extint0_irq_handler, EXTINT0_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_01, extint1_irq_handler, EXTINT1_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_02, extint2_irq_handler, EXTINT2_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_03, extint3_irq_handler, EXTINT3_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_04, extint4_irq_handler, EXTINT4_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_05, extint5_irq_handler, EXTINT5_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_06, extint6_irq_handler, EXTINT6_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_07, extint7_irq_handler, EXTINT7_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_08, extint8_irq_handler, EXTINT8_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_09, extint9_irq_handler, EXTINT9_IRQ_CONFIG), HC32_PIN_CONFIG(GPIO_PIN_10, extint10_irq_handler, EXTINT10_IRQ_CONFIG), HC32_PIN_CONFIG(GPIO_PIN_11, extint11_irq_handler, EXTINT11_IRQ_CONFIG), HC32_PIN_CONFIG(GPIO_PIN_12, extint12_irq_handler, EXTINT12_IRQ_CONFIG), @@ -85,24 +86,23 @@ static struct hc32_pin_irq_map pin_irq_map[] = HC32_PIN_CONFIG(GPIO_PIN_15, extint15_irq_handler, EXTINT15_IRQ_CONFIG), }; -struct rt_pin_irq_hdr pin_irq_hdr_tab[] = -{ - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, - {-1, 0, RT_NULL, RT_NULL}, +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = { + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, + { -1, 0, RT_NULL, RT_NULL }, }; static void pin_irq_handler(rt_uint16_t pinbit) @@ -232,7 +232,7 @@ static void extint15_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void EXTINT00_SWINT16_Handler(void) { extint0_irq_handler(); @@ -327,25 +327,25 @@ static void hc32_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mo switch (mode) { case PIN_MODE_OUTPUT: - stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinDir = PIN_DIR_OUT; stcGpioInit.u16PinOutputType = PIN_OUT_TYPE_CMOS; break; case PIN_MODE_INPUT: - stcGpioInit.u16PinDir = PIN_DIR_IN; + stcGpioInit.u16PinDir = PIN_DIR_IN; break; case PIN_MODE_INPUT_PULLUP: - stcGpioInit.u16PinDir = PIN_DIR_IN; - stcGpioInit.u16PullUp = PIN_PU_ON; + stcGpioInit.u16PinDir = PIN_DIR_IN; + stcGpioInit.u16PullUp = PIN_PU_ON; break; case PIN_MODE_INPUT_PULLDOWN: - stcGpioInit.u16PinDir = PIN_DIR_IN; - stcGpioInit.u16PullUp = PIN_PU_OFF; -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) + stcGpioInit.u16PinDir = PIN_DIR_IN; + stcGpioInit.u16PullUp = PIN_PU_OFF; +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) stcGpioInit.u16PullDown = PIN_PD_ON; #endif break; case PIN_MODE_OUTPUT_OD: - stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinDir = PIN_DIR_OUT; stcGpioInit.u16PinOutputType = PIN_OUT_TYPE_NMOS; break; default: @@ -356,13 +356,13 @@ static void hc32_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mo static void hc32_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value) { - uint8_t gpio_port; + uint8_t gpio_port; uint16_t gpio_pin; if (pin < PIN_MAX_NUM) { gpio_port = GPIO_PORT(pin); - gpio_pin = GPIO_PIN(pin); + gpio_pin = GPIO_PIN(pin); if (PIN_LOW == value) { GPIO_ResetPins(gpio_port, gpio_pin); @@ -376,14 +376,14 @@ static void hc32_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t v static rt_ssize_t hc32_pin_read(struct rt_device *device, rt_base_t pin) { - uint8_t gpio_port; + uint8_t gpio_port; uint16_t gpio_pin; int value = PIN_LOW; if (pin < PIN_MAX_NUM) { gpio_port = GPIO_PORT(pin); - gpio_pin = GPIO_PIN(pin); + gpio_pin = GPIO_PIN(pin); if (PIN_RESET == GPIO_ReadInputPins(gpio_port, gpio_pin)) { value = PIN_LOW; @@ -418,10 +418,10 @@ static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_base_t pin, } level = rt_hw_interrupt_disable(); - if (pin_irq_hdr_tab[irqindex].pin == pin && - pin_irq_hdr_tab[irqindex].hdr == hdr && - pin_irq_hdr_tab[irqindex].mode == mode && - pin_irq_hdr_tab[irqindex].args == args) + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) { rt_hw_interrupt_enable(level); return RT_EOK; @@ -431,8 +431,8 @@ static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_base_t pin, rt_hw_interrupt_enable(level); return -RT_EBUSY; } - pin_irq_hdr_tab[irqindex].pin = pin; - pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; pin_irq_hdr_tab[irqindex].mode = mode; pin_irq_hdr_tab[irqindex].args = args; rt_hw_interrupt_enable(level); @@ -461,8 +461,8 @@ static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_base_t pin) rt_hw_interrupt_enable(level); return RT_EOK; } - pin_irq_hdr_tab[irqindex].pin = -1; - pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; pin_irq_hdr_tab[irqindex].mode = 0; pin_irq_hdr_tab[irqindex].args = RT_NULL; rt_hw_interrupt_enable(level); @@ -486,7 +486,7 @@ static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_ rt_base_t level; rt_int32_t irqindex = -1; stc_extint_init_t stcExtIntInit; - uint8_t gpio_port; + uint8_t gpio_port; uint16_t gpio_pin; if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled))) @@ -499,9 +499,9 @@ static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_ return -RT_ENOSYS; } - irq_map = &pin_irq_map[irqindex]; + irq_map = &pin_irq_map[irqindex]; gpio_port = GPIO_PORT(pin); - gpio_pin = GPIO_PIN(pin); + gpio_pin = GPIO_PIN(pin); if (enabled == PIN_IRQ_ENABLE) { level = rt_hw_interrupt_disable(); @@ -582,8 +582,7 @@ static rt_base_t hc32_pin_get(const char *name) return pin; } -static const struct rt_pin_ops hc32_pin_ops = -{ +static const struct rt_pin_ops hc32_pin_ops = { hc32_pin_mode, hc32_pin_write, hc32_pin_read, diff --git a/bsp/hc32/libraries/hc32_drivers/drv_gpio.h b/bsp/hc32/libraries/hc32_drivers/drv_gpio.h index bdfe69a524e..26aa98dbcf6 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_gpio.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_gpio.h @@ -16,14 +16,14 @@ #if defined(RT_USING_PIN) -#define __HC_PORT(port) GPIO_PORT_##port -#define GET_PIN(PORT, PIN) (rt_base_t)(((rt_uint16_t)__HC_PORT(PORT) * 16) + PIN) +#define __HC_PORT(port) GPIO_PORT_##port +#define GET_PIN(PORT, PIN) (rt_base_t)(((rt_uint16_t)__HC_PORT(PORT) * 16) + PIN) struct hc32_pin_irq_map { - rt_uint16_t pinbit; - func_ptr_t irq_callback; - struct hc32_irq_config irq_config; + rt_uint16_t pinbit; + func_ptr_t irq_callback; + struct hc32_irq_config irq_config; }; int rt_hw_pin_init(void); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_i2c.c b/bsp/hc32/libraries/hc32_drivers/drv_i2c.c index 008ef0f9266..ac576fc2ed2 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_i2c.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_i2c.c @@ -29,15 +29,15 @@ * Local pre-processor symbols/macros ('#define') ******************************************************************************/ #ifndef HC32_I2C_DEBUG - #define I2C_PRINT_DBG(fmt, args...) - #define I2C_PRINT_ERR(fmt, args...) rt_kprintf(fmt, ##args); +#define I2C_PRINT_DBG(fmt, args...) +#define I2C_PRINT_ERR(fmt, args...) rt_kprintf(fmt, ##args); #else - #define I2C_PRINT_DBG(fmt, args...) rt_kprintf(fmt, ##args); - #define I2C_PRINT_ERR(fmt, args...) rt_kprintf(fmt, ##args); +#define I2C_PRINT_DBG(fmt, args...) rt_kprintf(fmt, ##args); +#define I2C_PRINT_ERR(fmt, args...) rt_kprintf(fmt, ##args); #endif -#define I2C_TIMEOUT ((uint32_t)0x10000) -#define FCG_I2C_CLK FCG_Fcg1PeriphClockCmd +#define I2C_TIMEOUT ((uint32_t)0x10000) +#define FCG_I2C_CLK FCG_Fcg1PeriphClockCmd /******************************************************************************* * Global variable definitions (declared in header file with 'extern') @@ -69,8 +69,7 @@ enum #endif }; -static struct hc32_i2c_config i2c_config[] = -{ +static struct hc32_i2c_config i2c_config[] = { #ifdef BSP_USING_I2C1 I2C1_CONFIG, #endif @@ -92,7 +91,7 @@ static struct hc32_i2c_config i2c_config[] = }; static void hc32_i2c_dma_configure(struct rt_i2c_bus_device *bus); -static struct hc32_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = {0}; +static struct hc32_i2c i2c_objs[sizeof(i2c_config) / sizeof(i2c_config[0])] = { 0 }; /******************************************************************************* * Function implementation - global ('extern') and local ('static') @@ -269,14 +268,14 @@ static void hc32_i2c_dma_configure(struct rt_i2c_bus_device *bus) FCG_Fcg0PeriphClockCmd(i2c_obj->config->i2c_tx_dma->clock, ENABLE); (void)DMA_StructInit(&stcDmaInit); - stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32BlockSize = 1UL; stcDmaInit.u32TransCount = 0UL; - stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; /* Configure TX */ - stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC; + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC; stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX; - stcDmaInit.u32SrcAddr = (uint32_t)NULL; - stcDmaInit.u32DestAddr = (uint32_t)(&i2c_obj->config->Instance->DTR); + stcDmaInit.u32SrcAddr = (uint32_t)NULL; + stcDmaInit.u32DestAddr = (uint32_t)(&i2c_obj->config->Instance->DTR); if (LL_OK != DMA_Init(i2c_obj->config->i2c_tx_dma->Instance, i2c_obj->config->i2c_tx_dma->channel, &stcDmaInit)) { I2C_PRINT_ERR("[%s:%d]I2C TX DMA init error!\n", __func__, __LINE__); @@ -291,14 +290,14 @@ static void hc32_i2c_dma_configure(struct rt_i2c_bus_device *bus) /* DMA/AOS FCG enable */ FCG_Fcg0PeriphClockCmd(i2c_obj->config->i2c_rx_dma->clock, ENABLE); (void)DMA_StructInit(&stcDmaInit); - stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32BlockSize = 1UL; stcDmaInit.u32TransCount = 0UL; - stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; /* Configure RX */ - stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_INC; - stcDmaInit.u32SrcAddr = (uint32_t)(&i2c_obj->config->Instance->DRR); - stcDmaInit.u32DestAddr = (uint32_t)NULL; + stcDmaInit.u32SrcAddr = (uint32_t)(&i2c_obj->config->Instance->DRR); + stcDmaInit.u32DestAddr = (uint32_t)NULL; if (LL_OK != DMA_Init(i2c_obj->config->i2c_rx_dma->Instance, i2c_obj->config->i2c_rx_dma->channel, &stcDmaInit)) { I2C_PRINT_ERR("[%s:%d]I2C RX DMA init error!\n", __func__, __LINE__); @@ -546,8 +545,7 @@ static rt_ssize_t hc32_i2c_master_xfer(struct rt_i2c_bus_device *bus, return ret; } -static const struct rt_i2c_bus_device_ops hc32_i2c_ops = -{ +static const struct rt_i2c_bus_device_ops hc32_i2c_ops = { .master_xfer = hc32_i2c_master_xfer, RT_NULL, RT_NULL diff --git a/bsp/hc32/libraries/hc32_drivers/drv_i2c.h b/bsp/hc32/libraries/hc32_drivers/drv_i2c.h index 402fe7ed254..d4c555000c5 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_i2c.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_i2c.h @@ -20,8 +20,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -29,27 +28,27 @@ extern "C" ******************************************************************************/ struct hc32_i2c_config { - const char *name; - CM_I2C_TypeDef *Instance; - rt_uint32_t clock; - rt_uint32_t baudrate; - rt_uint32_t timeout; - struct dma_config *i2c_tx_dma; - struct dma_config *i2c_rx_dma; + const char *name; + CM_I2C_TypeDef *Instance; + rt_uint32_t clock; + rt_uint32_t baudrate; + rt_uint32_t timeout; + struct dma_config *i2c_tx_dma; + struct dma_config *i2c_rx_dma; }; struct hc32_i2c { - struct hc32_i2c_config *config; - struct rt_i2c_bus_device i2c_bus; - rt_uint8_t i2c_dma_flag; + struct hc32_i2c_config *config; + struct rt_i2c_bus_device i2c_bus; + rt_uint8_t i2c_dma_flag; }; /******************************************************************************* * Global pre-processor symbols/macros ('#define') ******************************************************************************/ -#define I2C_USING_TX_DMA_FLAG (1U) -#define I2C_USING_RX_DMA_FLAG (1U << 1) +#define I2C_USING_TX_DMA_FLAG (1U) +#define I2C_USING_RX_DMA_FLAG (1U << 1) #ifdef __cplusplus } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_irq.c b/bsp/hc32/libraries/hc32_drivers/drv_irq.c index 501717d5d37..e72919f5ebf 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_irq.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_irq.c @@ -8,6 +8,7 @@ * 2022-04-28 CDT first version * 2024-06-07 CDT Modify the IRQ install implementation for F448/F472 * 2025-07-16 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 */ /******************************************************************************* @@ -23,9 +24,9 @@ /******************************************************************************* * Local pre-processor symbols/macros ('#define') ******************************************************************************/ -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) /* Interrupt registration max number */ - #define HC32_INT_REG_MAX_NUM (16U) +#define HC32_INT_REG_MAX_NUM (16U) #endif /******************************************************************************* @@ -52,7 +53,7 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, RT_ASSERT(RT_NULL != irq_config); -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) if (irq_config->irq_num < HC32_INT_REG_MAX_NUM) { RT_ASSERT(RT_NULL != irq_hdr); @@ -63,17 +64,17 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, INTC_IntSrcCmd(irq_config->int_src, ENABLE); goto nvic_config; } - stcIrqSignConfig.enIRQn = irq_config->irq_num; - stcIrqSignConfig.enIntSrc = irq_config->int_src; + stcIrqSignConfig.enIRQn = irq_config->irq_num; + stcIrqSignConfig.enIntSrc = irq_config->int_src; stcIrqSignConfig.pfnCallback = irq_hdr; if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig)) -#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) - stcIrqSignConfig.enIRQn = irq_config->irq_num; - stcIrqSignConfig.enIntSrc = irq_config->int_src; + nvic_config: +#elif defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) + stcIrqSignConfig.enIRQn = irq_config->irq_num; + stcIrqSignConfig.enIntSrc = irq_config->int_src; stcIrqSignConfig.pfnCallback = irq_hdr; if (LL_OK == INTC_IrqSignIn(&stcIrqSignConfig)) #endif -nvic_config: { NVIC_ClearPendingIRQ(irq_config->irq_num); NVIC_SetPriority(irq_config->irq_num, irq_config->irq_prio); @@ -88,7 +89,7 @@ rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, result = RT_EOK; } - return result; + return result; } /******************************************************************************* diff --git a/bsp/hc32/libraries/hc32_drivers/drv_irq.h b/bsp/hc32/libraries/hc32_drivers/drv_irq.h index 8d0b5c4857a..758b3d83daa 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_irq.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_irq.h @@ -19,8 +19,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -28,9 +27,9 @@ extern "C" ******************************************************************************/ struct hc32_irq_config { - IRQn_Type irq_num; - uint32_t irq_prio; - en_int_src_t int_src; + IRQn_Type irq_num; + uint32_t irq_prio; + en_int_src_t int_src; }; /******************************************************************************* diff --git a/bsp/hc32/libraries/hc32_drivers/drv_log.h b/bsp/hc32/libraries/hc32_drivers/drv_log.h index 9ba03385608..5eeec562c44 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_log.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_log.h @@ -13,15 +13,15 @@ */ #ifndef LOG_TAG - #define DBG_TAG "drv" +#define DBG_TAG "drv" #else - #define DBG_TAG LOG_TAG +#define DBG_TAG LOG_TAG #endif /* LOG_TAG */ #ifdef DRV_DEBUG - #define DBG_LVL DBG_LOG +#define DBG_LVL DBG_LOG #else - #define DBG_LVL DBG_INFO +#define DBG_LVL DBG_INFO #endif /* DRV_DEBUG */ #include diff --git a/bsp/hc32/libraries/hc32_drivers/drv_mcan.c b/bsp/hc32/libraries/hc32_drivers/drv_mcan.c index 5dc0217c1f9..01de0aba577 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_mcan.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_mcan.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-xx-xx CDT first version + * 2026-06-24 CDT Added _can_sendmsg_nonblocking. Fixed comments. */ #include "drv_mcan.h" @@ -13,7 +14,7 @@ #include #if defined(BSP_USING_MCAN) -#define LOG_TAG "drv_mcan" +#define LOG_TAG "drv_mcan" /**************************************************************************************** * Type definitions for MCAN RT driver @@ -49,86 +50,83 @@ typedef struct mcan_baud_rate_struct * Parameter validity check ****************************************************************************************/ #if defined(BSP_USING_MCAN1) || defined(BSP_USING_MCAN2) -#define IS_RT_CAN_WORK_MODE(mode) ((mode) <= RT_CAN_MODE_LOOPBACKANLISTEN) -#define IS_RT_CAN_PRIV_MODE(mode) (((mode) == RT_CAN_MODE_PRIV) || ((mode) == RT_CAN_MODE_NOPRIV)) -#define IS_MCAN_FD_MODE(mode) (((mode) >= MCAN_FD_ARG_MIN) && ((mode) <= MCAN_FD_ARG_MAX)) - -#define IS_MCAN_CC_BAUD_RATE(baud) ((baud) == (CAN10kBaud) || \ - (baud) == (CAN20kBaud) || \ - (baud) == (CAN50kBaud) || \ - (baud) == (CAN100kBaud) || \ - (baud) == (CAN125kBaud) || \ - (baud) == (CAN250kBaud) || \ - (baud) == (CAN500kBaud) || \ - (baud) == (CAN800kBaud) || \ - (baud) == (CAN1MBaud)) - -#define IS_MCAN_NOMINAL_BAUD_RATE(baud) ((baud) == (CAN500kBaud) || \ - (baud) == (CAN1MBaud)) - -#define IS_MCAN_DATA_BAUD_RATE(baud) ((baud) == (CANFD_DATA_BAUD_1M) || \ - (baud) == (CANFD_DATA_BAUD_2M) || \ - (baud) == (CANFD_DATA_BAUD_4M) || \ - (baud) == (CANFD_DATA_BAUD_5M) || \ - (baud) == (CANFD_DATA_BAUD_8M)) - -#define IS_CAN_VALID_ID(ide, id) ((((ide) == 0) && ((id) <= MCAN_STD_ID_MASK)) || \ - (((ide) == 1) && ((id) <= MCAN_EXT_ID_MASK))) +#define IS_RT_CAN_WORK_MODE(mode) ((mode) <= RT_CAN_MODE_LOOPBACKANLISTEN) +#define IS_RT_CAN_PRIV_MODE(mode) (((mode) == RT_CAN_MODE_PRIV) || ((mode) == RT_CAN_MODE_NOPRIV)) +#define IS_MCAN_FD_MODE(mode) (((mode) >= MCAN_FD_ARG_MIN) && ((mode) <= MCAN_FD_ARG_MAX)) + +#define IS_MCAN_CC_BAUD_RATE(baud) ((baud) == (CAN10kBaud) || \ + (baud) == (CAN20kBaud) || \ + (baud) == (CAN50kBaud) || \ + (baud) == (CAN100kBaud) || \ + (baud) == (CAN125kBaud) || \ + (baud) == (CAN250kBaud) || \ + (baud) == (CAN500kBaud) || \ + (baud) == (CAN800kBaud) || \ + (baud) == (CAN1MBaud)) + +#define IS_MCAN_NOMINAL_BAUD_RATE(baud) ((baud) == (CAN500kBaud) || \ + (baud) == (CAN1MBaud)) + +#define IS_MCAN_DATA_BAUD_RATE(baud) ((baud) == (CANFD_DATA_BAUD_1M) || \ + (baud) == (CANFD_DATA_BAUD_2M) || \ + (baud) == (CANFD_DATA_BAUD_4M) || \ + (baud) == (CANFD_DATA_BAUD_5M) || \ + (baud) == (CANFD_DATA_BAUD_8M)) + +#define IS_CAN_VALID_ID(ide, id) ((((ide) == 0) && ((id) <= MCAN_STD_ID_MASK)) || \ + (((ide) == 1) && ((id) <= MCAN_EXT_ID_MASK))) /**************************************************************************************** * Interrupt definitions ****************************************************************************************/ -#define MCAN_RX_INT (MCAN_INT_RX_FIFO0_NEW_MSG | MCAN_INT_RX_FIFO1_NEW_MSG | MCAN_INT_RX_BUF_NEW_MSG) -#define MCAN_TX_INT (MCAN_INT_TX_CPLT) -#define MCAN_ERR_INT (MCAN_INT_ARB_PHASE_ERROR | MCAN_INT_DATA_PHASE_ERROR | MCAN_INT_ERR_LOG_OVF | \ - MCAN_INT_ERR_PASSIVE | MCAN_INT_ERR_WARNING | MCAN_INT_BUS_OFF) -#define MCAN_INT0_SEL (MCAN_RX_INT | MCAN_TX_INT | MCAN_ERR_INT) +#define MCAN_RX_INT (MCAN_INT_RX_FIFO0_NEW_MSG | MCAN_INT_RX_FIFO1_NEW_MSG | MCAN_INT_RX_BUF_NEW_MSG) +#define MCAN_TX_INT (MCAN_INT_TX_CPLT) +#define MCAN_ERR_INT (MCAN_INT_ARB_PHASE_ERROR | MCAN_INT_DATA_PHASE_ERROR | MCAN_INT_ERR_LOG_OVF | \ + MCAN_INT_ERR_PASSIVE | MCAN_INT_ERR_WARNING | MCAN_INT_BUS_OFF) +#define MCAN_INT0_SEL (MCAN_RX_INT | MCAN_TX_INT | MCAN_ERR_INT) /**************************************************************************************** * Baud rate(bit timing) configuration based on 80MHz clock ****************************************************************************************/ #if defined(RT_CAN_USING_CANFD) -static const mcan_baud_rate_t m_mcan_fd_baud_rate[] = -{ - {CAN500kBaud, CANFD_DATA_BAUD_1M, MCAN_FD_CFG_500K_1M}, - {CAN500kBaud, CANFD_DATA_BAUD_2M, MCAN_FD_CFG_500K_2M}, - {CAN500kBaud, CANFD_DATA_BAUD_4M, MCAN_FD_CFG_500K_4M}, - {CAN500kBaud, CANFD_DATA_BAUD_5M, MCAN_FD_CFG_500K_5M}, - {CAN500kBaud, CANFD_DATA_BAUD_8M, MCAN_FD_CFG_500K_8M}, - {CAN1MBaud, CANFD_DATA_BAUD_1M, MCAN_FD_CFG_1M_1M}, - {CAN1MBaud, CANFD_DATA_BAUD_2M, MCAN_FD_CFG_1M_2M}, - {CAN1MBaud, CANFD_DATA_BAUD_4M, MCAN_FD_CFG_1M_4M}, - {CAN1MBaud, CANFD_DATA_BAUD_5M, MCAN_FD_CFG_1M_5M}, - {CAN1MBaud, CANFD_DATA_BAUD_8M, MCAN_FD_CFG_1M_8M}, +static const mcan_baud_rate_t m_mcan_fd_baud_rate[] = { + { CAN500kBaud, CANFD_DATA_BAUD_1M, MCAN_FD_CFG_500K_1M }, + { CAN500kBaud, CANFD_DATA_BAUD_2M, MCAN_FD_CFG_500K_2M }, + { CAN500kBaud, CANFD_DATA_BAUD_4M, MCAN_FD_CFG_500K_4M }, + { CAN500kBaud, CANFD_DATA_BAUD_5M, MCAN_FD_CFG_500K_5M }, + { CAN500kBaud, CANFD_DATA_BAUD_8M, MCAN_FD_CFG_500K_8M }, + { CAN1MBaud, CANFD_DATA_BAUD_1M, MCAN_FD_CFG_1M_1M }, + { CAN1MBaud, CANFD_DATA_BAUD_2M, MCAN_FD_CFG_1M_2M }, + { CAN1MBaud, CANFD_DATA_BAUD_4M, MCAN_FD_CFG_1M_4M }, + { CAN1MBaud, CANFD_DATA_BAUD_5M, MCAN_FD_CFG_1M_5M }, + { CAN1MBaud, CANFD_DATA_BAUD_8M, MCAN_FD_CFG_1M_8M }, }; #else -static const mcan_baud_rate_t m_mcan_cc_baud_rate[] = -{ - {CAN1MBaud, 0, MCAN_CC_CFG_1M}, - {CAN800kBaud, 0, MCAN_CC_CFG_800K}, - {CAN500kBaud, 0, MCAN_CC_CFG_500K}, - {CAN250kBaud, 0, MCAN_CC_CFG_250K}, - {CAN125kBaud, 0, MCAN_CC_CFG_125K}, - {CAN100kBaud, 0, MCAN_CC_CFG_100K}, - {CAN50kBaud, 0, MCAN_CC_CFG_50K}, - {CAN20kBaud, 0, MCAN_CC_CFG_20K}, - {CAN10kBaud, 0, MCAN_CC_CFG_10K}, +static const mcan_baud_rate_t m_mcan_cc_baud_rate[] = { + { CAN1MBaud, 0, MCAN_CC_CFG_1M }, + { CAN800kBaud, 0, MCAN_CC_CFG_800K }, + { CAN500kBaud, 0, MCAN_CC_CFG_500K }, + { CAN250kBaud, 0, MCAN_CC_CFG_250K }, + { CAN125kBaud, 0, MCAN_CC_CFG_125K }, + { CAN100kBaud, 0, MCAN_CC_CFG_100K }, + { CAN50kBaud, 0, MCAN_CC_CFG_50K }, + { CAN20kBaud, 0, MCAN_CC_CFG_20K }, + { CAN10kBaud, 0, MCAN_CC_CFG_10K }, }; #endif /**************************************************************************************** * Constants ****************************************************************************************/ -static const uint8_t m_mcan_data_size[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; +static const uint8_t m_mcan_data_size[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64 }; -static const rt_uint32_t m_mcan_tx_priv_mode[] = {MCAN_TX_FIFO_MD, MCAN_TX_QUEUE_MD}; +static const rt_uint32_t m_mcan_tx_priv_mode[] = { MCAN_TX_FIFO_MD, MCAN_TX_QUEUE_MD }; -static const rt_uint32_t m_mcan_work_mode[] = {MCAN_MD_NORMAL, MCAN_MD_BUS_MON, MCAN_MD_EXTERN_LOOPBACK, MCAN_MD_INTERN_LOOPBACK}; +static const rt_uint32_t m_mcan_work_mode[] = { MCAN_MD_NORMAL, MCAN_MD_BUS_MON, MCAN_MD_EXTERN_LOOPBACK, MCAN_MD_INTERN_LOOPBACK }; #if defined(RT_CAN_USING_CANFD) -static const rt_uint32_t m_mcan_fd_mode[] = {MCAN_FRAME_CLASSIC, MCAN_FRAME_ISO_FD_NO_BRS, MCAN_FRAME_ISO_FD_BRS, \ - MCAN_FRAME_NON_ISO_FD_NO_BRS, MCAN_FRAME_NON_ISO_FD_BRS - }; +static const rt_uint32_t m_mcan_fd_mode[] = { MCAN_FRAME_CLASSIC, MCAN_FRAME_ISO_FD_NO_BRS, MCAN_FRAME_ISO_FD_BRS, + MCAN_FRAME_NON_ISO_FD_NO_BRS, MCAN_FRAME_NON_ISO_FD_BRS }; #endif /**************************************************************************************** @@ -145,40 +143,35 @@ enum MCAN_DEV_CNT, }; -static hc32_mcan_driver_t m_mcan_driver_list[] = -{ +static hc32_mcan_driver_t m_mcan_driver_list[] = { #if defined(BSP_USING_MCAN1) - { - { - .name = MCAN1_NAME, - .instance = CM_MCAN1, - .init_para = {.stcBitTime = MCAN1_BAUD_RATE_CFG}, - .int0_sel = MCAN_INT0_SEL, - .int0_cfg = {BSP_MCAN1_INT0_IRQ_NUM, BSP_MCAN1_INT0_IRQ_PRIO, INT_SRC_MCAN1_INT0}, - } - }, + { { + .name = MCAN1_NAME, + .instance = CM_MCAN1, + .init_para = { .stcBitTime = MCAN1_BAUD_RATE_CFG }, + .int0_sel = MCAN_INT0_SEL, + .int0_cfg = { BSP_MCAN1_INT0_IRQ_NUM, BSP_MCAN1_INT0_IRQ_PRIO, INT_SRC_MCAN1_INT0 }, + } }, #endif #if defined(BSP_USING_MCAN2) - { - { - .name = MCAN2_NAME, - .instance = CM_MCAN2, - .init_para = {.stcBitTime = MCAN2_BAUD_RATE_CFG}, - .int0_sel = MCAN_INT0_SEL, - .int0_cfg = {BSP_MCAN2_INT0_IRQ_NUM, BSP_MCAN2_INT0_IRQ_PRIO, INT_SRC_MCAN2_INT0}, - } - }, + { { + .name = MCAN2_NAME, + .instance = CM_MCAN2, + .init_para = { .stcBitTime = MCAN2_BAUD_RATE_CFG }, + .int0_sel = MCAN_INT0_SEL, + .int0_cfg = { BSP_MCAN2_INT0_IRQ_NUM, BSP_MCAN2_INT0_IRQ_PRIO, INT_SRC_MCAN2_INT0 }, + } }, #endif }; #if defined(BSP_USING_MCAN1) - static stc_mcan_filter_t m_mcan1_std_filters[MCAN1_STD_FILTER_NUM]; - static stc_mcan_filter_t m_mcan1_ext_filters[MCAN1_EXT_FILTER_NUM]; +static stc_mcan_filter_t m_mcan1_std_filters[MCAN1_STD_FILTER_NUM]; +static stc_mcan_filter_t m_mcan1_ext_filters[MCAN1_EXT_FILTER_NUM]; #endif #if defined(BSP_USING_MCAN2) - static stc_mcan_filter_t m_mcan2_std_filters[MCAN2_STD_FILTER_NUM]; - static stc_mcan_filter_t m_mcan2_ext_filters[MCAN2_EXT_FILTER_NUM]; +static stc_mcan_filter_t m_mcan2_std_filters[MCAN2_STD_FILTER_NUM]; +static stc_mcan_filter_t m_mcan2_ext_filters[MCAN2_EXT_FILTER_NUM]; #endif /**************************************************************************************** @@ -186,56 +179,63 @@ static hc32_mcan_driver_t m_mcan_driver_list[] = ****************************************************************************************/ /** * @brief Configure CAN controller - * @param [in/out] can CAN device pointer + * @param [inout] device CAN device pointer * @param [in] cfg CAN configuration pointer - * @retval RT_EOK for valid configuration - * @retval -RT_ERROR for invalid configuration + * @retval RT_EOK No error + * @retval An error code on failure */ static rt_err_t mcan_configure(struct rt_can_device *device, struct can_configure *cfg); /** * @brief Control/Get CAN state * including:interrupt, mode, priority, baudrate, filter, status - * @param [in/out] can CAN device pointer + * @param [inout] device CAN device pointer * @param [in] cmd Control command - * @param [in/out] arg Argument pointer - * @retval RT_EOK for valid control command and arg - * @retval -RT_ERROR for invalid control command or arg + * @param [inout] arg Argument pointer + * @retval RT_EOK No error + * @retval An error code on failure */ static rt_err_t mcan_control(struct rt_can_device *device, int cmd, void *arg); /** * @brief Send out CAN message - * @param [in] can CAN device pointer + * @param [inout] device CAN device pointer * @param [in] buf CAN message buffer * @param [in] boxno Mailbox number, it is not used in this porting * @retval RT_EOK No error - * @retval -RT_ETIMEOUT timeout happened - * @retval -RT_EFULL Transmission buffer is full + * @retval An error code on failure */ static rt_ssize_t mcan_sendmsg(struct rt_can_device *device, const void *buf, rt_uint32_t boxno); +/** + * @brief Send out CAN message non-blocking + * @param [inout] device CAN device pointer + * @param [in] buf CAN message buffer + * @retval RT_EOK No error + * @retval An error code on failure + */ +static rt_ssize_t mcan_sendmsg_nonblocking(struct rt_can_device *device, const void *buf); + /** * @brief Receive message from CAN * @param [in] can CAN device pointer * @param [out] buf CAN receive buffer * @param [in] boxno Mailbox Number, it is not used in this porting - * @retval RT_EOK no error - * @retval -RT_ERROR Error happened during reading receive FIFO - * @retval -RT_EMPTY no data in receive FIFO + * @retval RT_EOK No error + * @retval An error code on failure */ static rt_ssize_t mcan_recvmsg(struct rt_can_device *device, void *buf, rt_uint32_t boxno); #if defined(RT_CAN_USING_CANFD) - static void mcan_copy_bt_to_cfg(struct can_configure *cfg, const stc_mcan_bit_time_config_t *ll_bt); +static void mcan_copy_bt_to_cfg(struct can_configure *cfg, const stc_mcan_bit_time_config_t *ll_bt); #endif -static const struct rt_can_ops m_mcan_ops = -{ +static const struct rt_can_ops m_mcan_ops = { mcan_configure, mcan_control, mcan_sendmsg, mcan_recvmsg, + mcan_sendmsg_nonblocking, }; /**************************************************************************************** @@ -288,8 +288,8 @@ static rt_err_t mcan_configure(struct rt_can_device *device, struct can_configur len = sizeof(m_mcan_fd_baud_rate) / sizeof(m_mcan_fd_baud_rate[0]); for (i = 0; i < len; i++) { - if ((cfg->baud_rate == m_mcan_fd_baud_rate[i].baud_rate) && \ - (cfg->baud_rate_fd == m_mcan_fd_baud_rate[i].baud_rate_fd)) + if ((cfg->baud_rate == m_mcan_fd_baud_rate[i].baud_rate) && + (cfg->baud_rate_fd == m_mcan_fd_baud_rate[i].baud_rate_fd)) { hard->init_para.stcBitTime = m_mcan_fd_baud_rate[i].ll_bt; mcan_copy_bt_to_cfg(cfg, &m_mcan_fd_baud_rate[i].ll_bt); @@ -330,6 +330,10 @@ static rt_err_t mcan_configure(struct rt_can_device *device, struct can_configur return -RT_ERROR; } } + else + { + return -RT_ERROR; + } hard->init_para.stcFilter.pstcStdFilterList = std_filters; hard->init_para.stcFilter.pstcExtFilterList = ext_filters; @@ -434,14 +438,14 @@ static rt_err_t mcan_control_set_filter(hc32_mcan_driver_t *driver, int cmd, voi } /* rt filter mode: 0 - list; 1 - mask */ - static const rt_uint32_t mcan_filter_type[] = {MCAN_FILTER_RANGE, MCAN_FILTER_MASK}; - static const rt_uint32_t mcan_filter_config[] = {MCAN_FILTER_TO_RX_FIFO0, MCAN_FILTER_TO_RX_FIFO1}; + static const rt_uint32_t mcan_filter_type[] = { MCAN_FILTER_RANGE, MCAN_FILTER_MASK }; + static const rt_uint32_t mcan_filter_config[] = { MCAN_FILTER_TO_RX_FIFO0, MCAN_FILTER_TO_RX_FIFO1 }; /* rt CAN filter to MCAN LL driver filter */ - ll_filter.u32IdType = device_filter->items[i].ide; - ll_filter.u32FilterType = mcan_filter_type[device_filter->items[i].mode]; + ll_filter.u32IdType = device_filter->items[i].ide; + ll_filter.u32FilterType = mcan_filter_type[device_filter->items[i].mode]; ll_filter.u32FilterConfig = mcan_filter_config[device_filter->items[i].rxfifo]; - ll_filter.u32FilterId1 = device_filter->items[i].id; - ll_filter.u32FilterId2 = device_filter->items[i].mask; + ll_filter.u32FilterId1 = device_filter->items[i].id; + ll_filter.u32FilterId2 = device_filter->items[i].mask; if (device_filter->items[i].ide == RT_CAN_STDID) { @@ -556,8 +560,8 @@ static rt_err_t mcan_control_set_fd(hc32_mcan_driver_t *driver, int cmd, void *a len = sizeof(m_mcan_fd_baud_rate) / sizeof(m_mcan_fd_baud_rate[0]); for (i = 0; i < len; i++) { - if ((argval == m_mcan_fd_baud_rate[i].baud_rate) && \ - (driver->can_device.config.baud_rate_fd == m_mcan_fd_baud_rate[i].baud_rate_fd)) + if ((argval == m_mcan_fd_baud_rate[i].baud_rate) && + (driver->can_device.config.baud_rate_fd == m_mcan_fd_baud_rate[i].baud_rate_fd)) { cfg->baud_rate = argval; cfg->baud_rate_fd = driver->can_device.config.baud_rate_fd; @@ -580,8 +584,8 @@ static rt_err_t mcan_control_set_fd(hc32_mcan_driver_t *driver, int cmd, void *a len = sizeof(m_mcan_fd_baud_rate) / sizeof(m_mcan_fd_baud_rate[0]); for (i = 0; i < len; i++) { - if ((argval == m_mcan_fd_baud_rate[i].baud_rate_fd) && \ - (driver->can_device.config.baud_rate == m_mcan_fd_baud_rate[i].baud_rate)) + if ((argval == m_mcan_fd_baud_rate[i].baud_rate_fd) && + (driver->can_device.config.baud_rate == m_mcan_fd_baud_rate[i].baud_rate)) { cfg->baud_rate_fd = argval; cfg->baud_rate = driver->can_device.config.baud_rate; @@ -724,7 +728,7 @@ static rt_ssize_t mcan_sendmsg(struct rt_can_device *device, const void *buf, rt { hc32_mcan_driver_t *driver; hc32_mcan_config_t *hard; - stc_mcan_tx_msg_t ll_tx_msg = {0}; + stc_mcan_tx_msg_t ll_tx_msg = { 0 }; struct rt_can_msg *tx_msg; RT_ASSERT(device); @@ -746,7 +750,7 @@ static rt_ssize_t mcan_sendmsg(struct rt_can_device *device, const void *buf, rt #endif /* rt CAN Tx message to MCAN LL driver Tx message */ - ll_tx_msg.ID = tx_msg->id; + ll_tx_msg.ID = tx_msg->id; ll_tx_msg.IDE = tx_msg->ide; ll_tx_msg.RTR = tx_msg->rtr; ll_tx_msg.DLC = tx_msg->len; @@ -763,6 +767,11 @@ static rt_ssize_t mcan_sendmsg(struct rt_can_device *device, const void *buf, rt return RT_EOK; } +static rt_ssize_t mcan_sendmsg_nonblocking(struct rt_can_device *device, const void *buf) +{ + return mcan_sendmsg(device, buf, 0); +} + /**************************************************************************************** * mcan receive message ****************************************************************************************/ @@ -770,7 +779,7 @@ static rt_ssize_t mcan_recvmsg(struct rt_can_device *device, void *buf, rt_uint3 { hc32_mcan_driver_t *driver; hc32_mcan_config_t *hard; - stc_mcan_rx_msg_t ll_rx_msg = {0}; + stc_mcan_rx_msg_t ll_rx_msg = { 0 }; struct rt_can_msg *rx_msg; rt_uint32_t rx_location; @@ -801,10 +810,10 @@ static rt_ssize_t mcan_recvmsg(struct rt_can_device *device, void *buf, rt_uint3 } /* MCAN LL driver Rx message to rt CAN Rx message */ - rx_msg->id = ll_rx_msg.ID; - rx_msg->ide = ll_rx_msg.IDE; - rx_msg->rtr = ll_rx_msg.RTR; - rx_msg->len = ll_rx_msg.DLC; + rx_msg->id = ll_rx_msg.ID; + rx_msg->ide = ll_rx_msg.IDE; + rx_msg->rtr = ll_rx_msg.RTR; + rx_msg->len = ll_rx_msg.DLC; rx_msg->priv = 0; #if defined(RT_CAN_USING_HDR) /* Hardware filter messages are valid */ @@ -814,7 +823,7 @@ static rt_ssize_t mcan_recvmsg(struct rt_can_device *device, void *buf, rt_uint3 #if defined(RT_CAN_USING_CANFD) rx_msg->fd_frame = ll_rx_msg.FDF; - rx_msg->brs = ll_rx_msg.BRS; + rx_msg->brs = ll_rx_msg.BRS; #endif if (rx_msg->len > 0) @@ -1034,28 +1043,28 @@ static void mcan_set_init_para(void) #else hard_init->u32FrameFormat = MCAN_FRAME_CLASSIC; #endif - hard_init->u32Mode = m_mcan_work_mode[device->config.mode]; - hard_init->u32AutoRetx = MCAN_AUTO_RETX_ENABLE; - hard_init->u32TxPause = MCAN_TX_PAUSE_DISABLE; + hard_init->u32Mode = m_mcan_work_mode[device->config.mode]; + hard_init->u32AutoRetx = MCAN_AUTO_RETX_ENABLE; + hard_init->u32TxPause = MCAN_TX_PAUSE_DISABLE; hard_init->u32ProtocolException = MCAN_PROTOCOL_EXP_ENABLE; /* Message RAM */ - hard_init->stcMsgRam.u32AddrOffset = 0U; - hard_init->stcMsgRam.u32StdFilterNum = MCAN1_STD_FILTER_NUM; - hard_init->stcMsgRam.u32ExtFilterNum = MCAN1_EXT_FILTER_NUM; - hard_init->stcMsgRam.u32RxFifo0Num = MCAN1_RX_FIFO0_NUM; - hard_init->stcMsgRam.u32RxFifo0DataSize = MCAN1_RX_FIFO0_DATA_FIELD_SIZE; - hard_init->stcMsgRam.u32RxFifo1Num = 0U; - hard_init->stcMsgRam.u32RxFifo1DataSize = 0U; - hard_init->stcMsgRam.u32RxBufferNum = 0U; - hard_init->stcMsgRam.u32RxBufferDataSize = 0U; - hard_init->stcMsgRam.u32TxEventNum = 0U; - hard_init->stcMsgRam.u32TxBufferNum = 0U; - hard_init->stcMsgRam.u32TxFifoQueueNum = MCAN1_TX_FIFO_NUM; - hard_init->stcMsgRam.u32TxFifoQueueMode = m_mcan_tx_priv_mode[device->config.privmode]; - hard_init->stcMsgRam.u32TxDataSize = MCAN1_TX_FIFO_DATA_FIELD_SIZE; + hard_init->stcMsgRam.u32AddrOffset = 0U; + hard_init->stcMsgRam.u32StdFilterNum = MCAN1_STD_FILTER_NUM; + hard_init->stcMsgRam.u32ExtFilterNum = MCAN1_EXT_FILTER_NUM; + hard_init->stcMsgRam.u32RxFifo0Num = MCAN1_RX_FIFO0_NUM; + hard_init->stcMsgRam.u32RxFifo0DataSize = MCAN1_RX_FIFO0_DATA_FIELD_SIZE; + hard_init->stcMsgRam.u32RxFifo1Num = 0U; + hard_init->stcMsgRam.u32RxFifo1DataSize = 0U; + hard_init->stcMsgRam.u32RxBufferNum = 0U; + hard_init->stcMsgRam.u32RxBufferDataSize = 0U; + hard_init->stcMsgRam.u32TxEventNum = 0U; + hard_init->stcMsgRam.u32TxBufferNum = 0U; + hard_init->stcMsgRam.u32TxFifoQueueNum = MCAN1_TX_FIFO_NUM; + hard_init->stcMsgRam.u32TxFifoQueueMode = m_mcan_tx_priv_mode[device->config.privmode]; + hard_init->stcMsgRam.u32TxDataSize = MCAN1_TX_FIFO_DATA_FIELD_SIZE; /* Acceptance filter */ - hard_init->stcFilter.pstcStdFilterList = m_mcan1_std_filters; - hard_init->stcFilter.pstcExtFilterList = m_mcan1_ext_filters; + hard_init->stcFilter.pstcStdFilterList = m_mcan1_std_filters; + hard_init->stcFilter.pstcExtFilterList = m_mcan1_ext_filters; hard_init->stcFilter.u32StdFilterConfigNum = hard_init->stcMsgRam.u32StdFilterNum; hard_init->stcFilter.u32ExtFilterConfigNum = hard_init->stcMsgRam.u32ExtFilterNum; #endif @@ -1076,28 +1085,28 @@ static void mcan_set_init_para(void) #else hard_init->u32FrameFormat = MCAN_FRAME_CLASSIC; #endif - hard_init->u32Mode = m_mcan_work_mode[device->config.mode]; - hard_init->u32AutoRetx = MCAN_AUTO_RETX_ENABLE; - hard_init->u32TxPause = MCAN_TX_PAUSE_DISABLE; + hard_init->u32Mode = m_mcan_work_mode[device->config.mode]; + hard_init->u32AutoRetx = MCAN_AUTO_RETX_ENABLE; + hard_init->u32TxPause = MCAN_TX_PAUSE_DISABLE; hard_init->u32ProtocolException = MCAN_PROTOCOL_EXP_ENABLE; /* Message RAM */ - hard_init->stcMsgRam.u32AddrOffset = 0U; - hard_init->stcMsgRam.u32StdFilterNum = MCAN2_STD_FILTER_NUM; - hard_init->stcMsgRam.u32ExtFilterNum = MCAN2_EXT_FILTER_NUM; - hard_init->stcMsgRam.u32RxFifo0Num = MCAN2_RX_FIFO0_NUM; - hard_init->stcMsgRam.u32RxFifo0DataSize = MCAN2_RX_FIFO0_DATA_FIELD_SIZE; - hard_init->stcMsgRam.u32RxFifo1Num = 0U; - hard_init->stcMsgRam.u32RxFifo1DataSize = 0U; - hard_init->stcMsgRam.u32RxBufferNum = 0U; - hard_init->stcMsgRam.u32RxBufferDataSize = 0U; - hard_init->stcMsgRam.u32TxEventNum = 0U; - hard_init->stcMsgRam.u32TxBufferNum = 0U; - hard_init->stcMsgRam.u32TxFifoQueueNum = MCAN2_TX_FIFO_NUM; - hard_init->stcMsgRam.u32TxFifoQueueMode = m_mcan_tx_priv_mode[device->config.privmode]; - hard_init->stcMsgRam.u32TxDataSize = MCAN2_TX_FIFO_DATA_FIELD_SIZE; + hard_init->stcMsgRam.u32AddrOffset = 0U; + hard_init->stcMsgRam.u32StdFilterNum = MCAN2_STD_FILTER_NUM; + hard_init->stcMsgRam.u32ExtFilterNum = MCAN2_EXT_FILTER_NUM; + hard_init->stcMsgRam.u32RxFifo0Num = MCAN2_RX_FIFO0_NUM; + hard_init->stcMsgRam.u32RxFifo0DataSize = MCAN2_RX_FIFO0_DATA_FIELD_SIZE; + hard_init->stcMsgRam.u32RxFifo1Num = 0U; + hard_init->stcMsgRam.u32RxFifo1DataSize = 0U; + hard_init->stcMsgRam.u32RxBufferNum = 0U; + hard_init->stcMsgRam.u32RxBufferDataSize = 0U; + hard_init->stcMsgRam.u32TxEventNum = 0U; + hard_init->stcMsgRam.u32TxBufferNum = 0U; + hard_init->stcMsgRam.u32TxFifoQueueNum = MCAN2_TX_FIFO_NUM; + hard_init->stcMsgRam.u32TxFifoQueueMode = m_mcan_tx_priv_mode[device->config.privmode]; + hard_init->stcMsgRam.u32TxDataSize = MCAN2_TX_FIFO_DATA_FIELD_SIZE; /* Acceptance filter */ - hard_init->stcFilter.pstcStdFilterList = m_mcan2_std_filters; - hard_init->stcFilter.pstcExtFilterList = m_mcan2_ext_filters; + hard_init->stcFilter.pstcStdFilterList = m_mcan2_std_filters; + hard_init->stcFilter.pstcExtFilterList = m_mcan2_ext_filters; hard_init->stcFilter.u32StdFilterConfigNum = hard_init->stcMsgRam.u32StdFilterNum; hard_init->stcFilter.u32ExtFilterConfigNum = hard_init->stcMsgRam.u32ExtFilterNum; #endif @@ -1183,9 +1192,9 @@ static int rt_hw_mcan_init(void) if (i > 0) { - hard->init_para.stcMsgRam.u32AddrOffset = \ - m_mcan_driver_list[i - 1].mcan.init_para.stcMsgRam.u32AddrOffset + \ - m_mcan_driver_list[i - 1].mcan.init_para.stcMsgRam.u32AllocatedSize; + hard->init_para.stcMsgRam.u32AddrOffset = + m_mcan_driver_list[i - 1].mcan.init_para.stcMsgRam.u32AddrOffset + + m_mcan_driver_list[i - 1].mcan.init_para.stcMsgRam.u32AllocatedSize; } init_can_cfg(&m_mcan_driver_list[i]); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_mcan.h b/bsp/hc32/libraries/hc32_drivers/drv_mcan.h index f19c0ee3555..41451900e5e 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_mcan.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_mcan.h @@ -18,14 +18,14 @@ extern "C" { #include "drv_can.h" /* The arguments of RT command RT_CAN_CMD_SET_CANFD */ -#define MCAN_FD_CLASSICAL 0 /* CAN classical */ -#define MCAN_FD_ISO_FD_NO_BRS 1 /* ISO CAN FD without BRS */ -#define MCAN_FD_ISO_FD_BRS 2 /* ISO CAN FD with BRS */ -#define MCAN_FD_NON_ISO_FD_NO_BRS 3 /* non-ISO CAN FD without BRS */ -#define MCAN_FD_NON_ISO_FD_BRS 4 /* non-ISO CAN FD with BRS */ - -#define MCAN_FD_ARG_MIN MCAN_FD_ISO_FD_NO_BRS -#define MCAN_FD_ARG_MAX MCAN_FD_NON_ISO_FD_BRS +#define MCAN_FD_CLASSICAL 0 /* CAN classical */ +#define MCAN_FD_ISO_FD_NO_BRS 1 /* ISO CAN FD without BRS */ +#define MCAN_FD_ISO_FD_BRS 2 /* ISO CAN FD with BRS */ +#define MCAN_FD_NON_ISO_FD_NO_BRS 3 /* non-ISO CAN FD without BRS */ +#define MCAN_FD_NON_ISO_FD_BRS 4 /* non-ISO CAN FD with BRS */ + +#define MCAN_FD_ARG_MIN MCAN_FD_ISO_FD_NO_BRS +#define MCAN_FD_ARG_MAX MCAN_FD_NON_ISO_FD_BRS #ifdef __cplusplus } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_nand.c b/bsp/hc32/libraries/hc32_drivers/drv_nand.c index d7dccd7f7a7..aca407f77e8 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_nand.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_nand.c @@ -6,7 +6,9 @@ * Change Logs: * Date Author Notes * 2023-03-01 CDT first version - * 2042-12-24 CDT fix compiler warning + * 2024-12-24 CDT fix compiler warning + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-05 CDT support HC32F467 */ @@ -16,8 +18,8 @@ #include -#if defined (BSP_USING_EXMC) -#if defined (BSP_USING_NAND) +#if defined(BSP_USING_EXMC) +#if defined(BSP_USING_NAND) #include "drv_nand.h" #include "board_config.h" @@ -44,27 +46,27 @@ struct rthw_nand #include /* Nand status */ -#define NAND_BUSY 0x00000000U -#define NAND_FAIL 0x00000001U -#define NAND_READY 0x00000040U -#define NAND_VALID_ADDRESS 0x00000100U -#define NAND_INVALID_ADDRESS 0x00000200U -#define NAND_TIMEOUT_ERROR 0x00000400U - -#define NAND_ERASE_TIMEOUT 2000000UL -#define NAND_READ_TIMEOUT 2000000UL -#define NAND_WRITE_TIMEOUT 2000000UL -#define NAND_RESET_TIMEOUT 2000000UL - -#define NAND_ECC_SECTOR_SIZE 512UL -#define NAND_ECC_CODE_SIZE ((NAND_EXMC_NFC_ECC_MD == EXMC_NFC_1BIT_ECC) ? 3UL : 8UL) -#define NAND_SPARE_FREE_SIZE (NAND_SPARE_AREA_SIZE - (NAND_BYTES_PER_PAGE / NAND_ECC_SECTOR_SIZE) * NAND_ECC_CODE_SIZE) +#define NAND_BUSY 0x00000000U +#define NAND_FAIL 0x00000001U +#define NAND_READY 0x00000040U +#define NAND_VALID_ADDRESS 0x00000100U +#define NAND_INVALID_ADDRESS 0x00000200U +#define NAND_TIMEOUT_ERROR 0x00000400U + +#define NAND_ERASE_TIMEOUT 2000000UL +#define NAND_READ_TIMEOUT 2000000UL +#define NAND_WRITE_TIMEOUT 2000000UL +#define NAND_RESET_TIMEOUT 2000000UL + +#define NAND_ECC_SECTOR_SIZE 512UL +#define NAND_ECC_CODE_SIZE ((NAND_EXMC_NFC_ECC_MD == EXMC_NFC_1BIT_ECC) ? 3UL : 8UL) +#define NAND_SPARE_FREE_SIZE (NAND_SPARE_AREA_SIZE - (NAND_BYTES_PER_PAGE / NAND_ECC_SECTOR_SIZE) * NAND_ECC_CODE_SIZE) /******************************************************************************* * Global variable definitions (declared in header file with 'extern') ******************************************************************************/ -#if defined (BSP_USING_NAND) - extern rt_err_t rt_hw_board_nand_init(void); +#if defined(BSP_USING_NAND) +extern rt_err_t rt_hw_board_nand_init(void); #endif /******************************************************************************* @@ -84,7 +86,7 @@ static rt_err_t _nand_verify_clock_frequency(void) { rt_err_t ret = RT_EOK; -#if defined (HC32F4A0) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) /* EXCLK max frequency for Nand: 60MHz */ if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > (60 * 1000000)) { @@ -101,7 +103,7 @@ static rt_err_t _nand_init(struct rt_mtd_nand_device *device) rt_err_t ret = -RT_ERROR; stc_exmc_nfc_init_t nfc_init_params; struct rthw_nand *hw_nand = (struct rthw_nand *)device; - rt_uint16_t oob_free = (rt_uint16_t)(NAND_SPARE_AREA_SIZE - \ + rt_uint16_t oob_free = (rt_uint16_t)(NAND_SPARE_AREA_SIZE - (NAND_BYTES_PER_PAGE / NAND_ECC_SECTOR_SIZE) * NAND_ECC_CODE_SIZE); RT_ASSERT(device != RT_NULL); @@ -128,7 +130,7 @@ static rt_err_t _nand_init(struct rt_mtd_nand_device *device) nfc_init_params.u32OpenPage = EXMC_NFC_OPEN_PAGE_DISABLE; nfc_init_params.stcBaseConfig.u32CapacitySize = NAND_EXMC_NFC_BANK_CAPACITY; nfc_init_params.stcBaseConfig.u32MemoryWidth = NAND_EXMC_NFC_MEMORY_WIDTH; - nfc_init_params.stcBaseConfig.u32BankNum = EXMC_NFC_1BANK; + nfc_init_params.stcBaseConfig.u32BankNum = NAND_EXMC_NFC_BANK_NUMBER; nfc_init_params.stcBaseConfig.u32PageSize = NAND_EXMC_NFC_PAGE_SIZE; nfc_init_params.stcBaseConfig.u32WriteProtect = EXMC_NFC_WR_PROTECT_DISABLE; nfc_init_params.stcBaseConfig.u32EccMode = NAND_EXMC_NFC_ECC_MD; @@ -157,8 +159,8 @@ static rt_err_t _nand_init(struct rt_mtd_nand_device *device) if (LL_OK == EXMC_NFC_Reset(hw_nand->nfc_bank, NAND_RESET_TIMEOUT)) { EXMC_NFC_ReadId(hw_nand->nfc_bank, 0UL, au8DevId, sizeof(au8DevId), NAND_READ_TIMEOUT); - hw_nand->id = (((rt_uint32_t)au8DevId[3]) << 24 | ((rt_uint32_t)au8DevId[2]) << 16 | \ - ((rt_uint32_t)au8DevId[1]) << 8 | (rt_uint32_t)au8DevId[0]); + hw_nand->id = (((rt_uint32_t)au8DevId[3]) << 24 | ((rt_uint32_t)au8DevId[2]) << 16 | + ((rt_uint32_t)au8DevId[1]) << 8 | (rt_uint32_t)au8DevId[0]); LOG_D("Nand Flash ID = 0x%02X,0x%02X,0x%02X,0x%02X", au8DevId[0], au8DevId[1], au8DevId[2], au8DevId[3]); @@ -187,8 +189,7 @@ static rt_err_t _nand_wait_ready(rt_uint32_t nfc_bank, rt_uint32_t timeout) } status = EXMC_NFC_ReadStatus(nfc_bank); - } - while (0UL == (status & NAND_READY)); + } while (0UL == (status & NAND_READY)); if (RT_ETIMEOUT != ret) { @@ -215,7 +216,7 @@ rt_err_t _nand_erase_block(struct rt_mtd_nand_device *device, rt_uint32_t block) rt_mutex_take(&hw_nand->lock, RT_WAITING_FOREVER); - if (LL_OK == EXMC_NFC_EraseBlock(hw_nand->nfc_bank, block_num, NAND_ERASE_TIMEOUT)) + if (LL_OK == EXMC_NFC_EraseBlock(hw_nand->nfc_bank, block_num, NAND_ERASE_TIMEOUT)) { if (_nand_wait_ready(hw_nand->nfc_bank, NAND_ERASE_TIMEOUT) == RT_EOK) { @@ -249,8 +250,8 @@ static rt_err_t _nand_read_id(struct rt_mtd_nand_device *device) RT_ASSERT(device != RT_NULL); EXMC_NFC_ReadId(hw_nand->nfc_bank, 0UL, device_id, sizeof(device_id), NAND_READ_TIMEOUT); - hw_nand->id = (((rt_uint32_t)device_id[3]) << 24 | ((rt_uint32_t)device_id[2]) << 16 | \ - ((rt_uint32_t)device_id[1]) << 8 | (rt_uint32_t)device_id[0]); + hw_nand->id = (((rt_uint32_t)device_id[3]) << 24 | ((rt_uint32_t)device_id[2]) << 16 | + ((rt_uint32_t)device_id[1]) << 8 | (rt_uint32_t)device_id[0]); LOG_D("Nand Flash ID: Manufacturer ID = 0x%02X, Device ID=[0x%02X,0x%02X,0x%02X]", device_id[0], device_id[1], device_id[2], device_id[3]); @@ -410,8 +411,7 @@ rt_err_t _nand_move_page(struct rt_mtd_nand_device *device, rt_off_t src_page, r return (RT_MTD_EOK); } -static const struct rt_mtd_nand_driver_ops _ops = -{ +static const struct rt_mtd_nand_driver_ops _ops = { _nand_read_id, _nand_read_page, _nand_write_page, @@ -434,14 +434,14 @@ int rt_hw_nand_init(void) } rt_mutex_init(&_hw_nand.lock, "nand", RT_IPC_FLAG_PRIO); - nand_dev->page_size = NAND_BYTES_PER_PAGE; + nand_dev->page_size = NAND_BYTES_PER_PAGE; nand_dev->pages_per_block = NAND_PAGES_PER_BLOCK; - nand_dev->plane_num = NAND_PLANE_PER_DEVICE; - nand_dev->oob_size = NAND_SPARE_AREA_SIZE; - nand_dev->oob_free = (rt_uint16_t)(NAND_SPARE_AREA_SIZE - (NAND_BYTES_PER_PAGE / NAND_ECC_SECTOR_SIZE) * NAND_ECC_CODE_SIZE); - nand_dev->block_total = NAND_DEVICE_BLOCKS; - nand_dev->block_start = 0; - nand_dev->block_end = nand_dev->block_total - 1UL; + nand_dev->plane_num = NAND_PLANE_PER_DEVICE; + nand_dev->oob_size = NAND_SPARE_AREA_SIZE; + nand_dev->oob_free = (rt_uint16_t)(NAND_SPARE_AREA_SIZE - (NAND_BYTES_PER_PAGE / NAND_ECC_SECTOR_SIZE) * NAND_ECC_CODE_SIZE); + nand_dev->block_total = NAND_DEVICE_BLOCKS; + nand_dev->block_start = 0; + nand_dev->block_end = nand_dev->block_total - 1UL; nand_dev->ops = &_ops; result = rt_mtd_nand_register_device("nand", nand_dev); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pm.c b/bsp/hc32/libraries/hc32_drivers/drv_pm.c index cc84e14200a..b7960395e02 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_pm.c @@ -7,6 +7,9 @@ * Date Author Notes * 2023-06-12 CDT first version * 2024-06-14 CDT Move common function SysTick_Configuration to _pm_run + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-04 CDT Support HC32F467 + * 2026-06-24 CDT rt_system_pm_init parameter timer_mask change to 0 for unsupport pm tickless timer */ #include @@ -19,13 +22,13 @@ #if defined(BSP_USING_PM) -#define LOG_TAG "drv_pm" +#define LOG_TAG "drv_pm" #include -#define IS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) +#define IS_PWC_UNLOCKED() ((CM_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) -typedef void (* run_switch_func_type)(void); -typedef void (* sleep_enter_func_type)(void); +typedef void (*run_switch_func_type)(void); +typedef void (*sleep_enter_func_type)(void); static void _sleep_enter_idle(void); static void _sleep_enter_deep(void); static void _sleep_enter_standby(void); @@ -33,16 +36,14 @@ static void _sleep_enter_shutdown(void); static void _run_switch_high_to_low(void); static void _run_switch_low_to_high(void); -static run_switch_func_type _run_switch_func[PM_RUN_MODE_MAX][PM_RUN_MODE_MAX] = -{ - {RT_NULL, RT_NULL, RT_NULL, _run_switch_high_to_low}, - {RT_NULL, RT_NULL, RT_NULL, _run_switch_high_to_low}, - {RT_NULL, RT_NULL, RT_NULL, RT_NULL}, - {_run_switch_low_to_high, _run_switch_low_to_high, RT_NULL, RT_NULL}, +static run_switch_func_type _run_switch_func[PM_RUN_MODE_MAX][PM_RUN_MODE_MAX] = { + { RT_NULL, RT_NULL, RT_NULL, _run_switch_high_to_low }, + { RT_NULL, RT_NULL, RT_NULL, _run_switch_high_to_low }, + { RT_NULL, RT_NULL, RT_NULL, RT_NULL }, + { _run_switch_low_to_high, _run_switch_low_to_high, RT_NULL, RT_NULL }, }; -static sleep_enter_func_type _sleep_enter_func[PM_SLEEP_MODE_MAX] = -{ +static sleep_enter_func_type _sleep_enter_func[PM_SLEEP_MODE_MAX] = { RT_NULL, _sleep_enter_idle, RT_NULL, @@ -72,7 +73,7 @@ static void _sleep_enter_deep(void) (void)PWC_STOP_Config(&sleep_deep_cfg.cfg); -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F467) || defined(HC32F448) || defined(HC32F4A8) if (PWC_PWRC2_DVS == (READ_REG8(CM_PWC->PWRC2) & PWC_PWRC2_DVS)) { CLR_REG8_BIT(CM_PWC->PWRC1, PWC_PWRC1_STPDAS); @@ -128,7 +129,7 @@ static void _run_switch_high_to_low(void) st_run_mode_cfg.sys_clk_cfg(PM_RUN_MODE_LOW_SPEED); -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F467) || defined(HC32F448) || defined(HC32F4A8) PWC_HighSpeedToLowSpeed(); #endif } @@ -137,7 +138,7 @@ static void _run_switch_low_to_high(void) { struct pm_run_mode_config st_run_mode_cfg = PM_RUN_MODE_CFG; -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F467) || defined(HC32F448) || defined(HC32F4A8) PWC_LowSpeedToHighSpeed(); #endif @@ -220,8 +221,7 @@ static rt_tick_t _timer_get_tick(struct rt_pm *pm) */ int rt_hw_pm_init(void) { - static const struct rt_pm_ops _ops = - { + static const struct rt_pm_ops _ops = { _pm_sleep, _pm_run, _pm_wakeup_timer_start, @@ -229,9 +229,8 @@ int rt_hw_pm_init(void) _timer_get_tick, }; - rt_uint8_t timer_mask = PM_TICKLESS_TIMER_ENABLE_MASK; /* initialize system pm module */ - rt_system_pm_init(&_ops, timer_mask, RT_NULL); + rt_system_pm_init(&_ops, 0U, RT_NULL); return 0; } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pm.h b/bsp/hc32/libraries/hc32_drivers/drv_pm.h index cba3d8f0669..2205cd666e2 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pm.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_pm.h @@ -19,8 +19,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* * @defgroup sleep_mode_map @@ -37,7 +36,7 @@ extern "C" /******************************************************************************* * Global type definitions ('typedef') ******************************************************************************/ -typedef void (* run_mode_init_func)(uint8_t run_mode); +typedef void (*run_mode_init_func)(uint8_t run_mode); /** * @brief run mode config @ref PM_RUN_MODE_CFG @@ -89,45 +88,45 @@ struct pm_sleep_mode_shutdown_config /******************************************************************************* * Global pre-processor symbols/macros ('#define') ******************************************************************************/ -#if defined(HC32F4A0) || defined(HC32F4A8) -#define PM_CHECK_EFM() ((EFM_GetStatus(EFM_FLAG_RDY) == SET) && (EFM_GetStatus(EFM_FLAG_RDY1) == SET)) -#elif defined(HC32F460) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) -#define PM_CHECK_EFM() ((EFM_GetStatus(EFM_FLAG_RDY) == SET)) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) +#define PM_CHECK_EFM() ((EFM_GetStatus(EFM_FLAG_RDY) == SET) && (EFM_GetStatus(EFM_FLAG_RDY1) == SET)) +#elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) || defined(HC32F334) || defined(HC32F467) +#define PM_CHECK_EFM() ((EFM_GetStatus(EFM_FLAG_RDY) == SET)) #endif -#define PM_CHECK_XTAL() ((CM_CMU->XTALSTDCR & CLK_XTALSTD_ON) == 0) +#define PM_CHECK_XTAL() ((CM_CMU->XTALSTDCR & CLK_XTALSTD_ON) == 0) #if defined(HC32F334) -#define PM_CHECK_DMA() (DMA_GetTransStatus(CM_DMA, DMA_STAT_TRANS_DMA) == RESET) -#elif defined(HC32F4A0) || defined(HC32F4A8) || defined(HC32F460) || defined (HC32F448) || defined (HC32F472) -#define PM_CHECK_DMA() \ -( (DMA_GetTransStatus(CM_DMA1, DMA_STAT_TRANS_DMA) == RESET) && \ - (DMA_GetTransStatus(CM_DMA2, DMA_STAT_TRANS_DMA) == RESET)) +#define PM_CHECK_DMA() (DMA_GetTransStatus(CM_DMA, DMA_STAT_TRANS_DMA) == RESET) +#elif defined(HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F460) || defined(HC32F448) || defined(HC32F472) +#define PM_CHECK_DMA() \ + ((DMA_GetTransStatus(CM_DMA1, DMA_STAT_TRANS_DMA) == RESET) && \ + (DMA_GetTransStatus(CM_DMA2, DMA_STAT_TRANS_DMA) == RESET)) #endif #define PM_CHECK_SWDT() \ -( ((CM_ICG->ICG0 & ICG_SWDT_RST_START) != ICG_SWDT_RST_START) || \ - ((CM_ICG->ICG0 & ICG_SWDT_LPM_CNT_STOP) == ICG_SWDT_LPM_CNT_STOP)) -#define PM_CHECK_PVD() \ -( ((CM_PWC->PVDCR1 & (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS)) != (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS)) && \ - ((CM_PWC->PVDCR1 & (PWC_PVDCR1_PVD2IRE | PWC_PVDCR1_PVD2IRS)) != (PWC_PVDCR1_PVD2IRE | PWC_PVDCR1_PVD2IRS))) -#define PM_SLEEP_SHUTDOWN_CHECK() \ -( PM_CHECK_EFM() && \ - PM_CHECK_XTAL() && \ - PM_CHECK_SWDT() && \ - PM_CHECK_PVD()) -#define PM_SLEEP_DEEP_CHECK() \ -( PM_CHECK_EFM() && \ - PM_CHECK_XTAL() && \ - PM_CHECK_DMA()) + (((CM_ICG->ICG0 & ICG_SWDT_RST_START) != ICG_SWDT_RST_START) || \ + ((CM_ICG->ICG0 & ICG_SWDT_LPM_CNT_STOP) == ICG_SWDT_LPM_CNT_STOP)) +#define PM_CHECK_PVD() \ + (((CM_PWC->PVDCR1 & (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS)) != (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS)) && \ + ((CM_PWC->PVDCR1 & (PWC_PVDCR1_PVD2IRE | PWC_PVDCR1_PVD2IRS)) != (PWC_PVDCR1_PVD2IRE | PWC_PVDCR1_PVD2IRS))) +#define PM_SLEEP_SHUTDOWN_CHECK() \ + (PM_CHECK_EFM() && \ + PM_CHECK_XTAL() && \ + PM_CHECK_SWDT() && \ + PM_CHECK_PVD()) +#define PM_SLEEP_DEEP_CHECK() \ + (PM_CHECK_EFM() && \ + PM_CHECK_XTAL() && \ + PM_CHECK_DMA()) /* * please make sure the state of the peripherals meet the requirements of entering the specified sleep mode, * otherwise system may not entering the right sleep mode or something unexpected may happen. * PM_SLEEP_CHECK is a demo of requirements and may not be comprehensive, * please refer user manual to know all the requirements in detail. */ -#define PM_SLEEP_CHECK(mode) \ -( (mode == PM_SLEEP_MODE_STANDBY && PM_SLEEP_SHUTDOWN_CHECK()) || \ -( (mode == PM_SLEEP_MODE_SHUTDOWN && PM_SLEEP_SHUTDOWN_CHECK()) || \ - (mode == PM_SLEEP_MODE_DEEP && PM_SLEEP_DEEP_CHECK())|| \ - (mode <= PM_SLEEP_MODE_IDLE))) +#define PM_SLEEP_CHECK(mode) \ + ((mode == PM_SLEEP_MODE_STANDBY && PM_SLEEP_SHUTDOWN_CHECK()) || \ + ((mode == PM_SLEEP_MODE_SHUTDOWN && PM_SLEEP_SHUTDOWN_CHECK()) || \ + (mode == PM_SLEEP_MODE_DEEP && PM_SLEEP_DEEP_CHECK()) || \ + (mode <= PM_SLEEP_MODE_IDLE))) /******************************************************************************* * Global function prototypes (definition in C source) ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c b/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c index fc825d52648..6f4a555769e 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_pulse_encoder.c @@ -16,7 +16,7 @@ #include "drv_irq.h" // #define DRV_DEBUG -#define LOG_TAG "drv_pulse_encoder" +#define LOG_TAG "drv_pulse_encoder" #include #if defined(BSP_USING_TMRA_PULSE_ENCODER) @@ -25,7 +25,7 @@ !defined(BSP_USING_PULSE_ENCODER_TMRA_4) && !defined(BSP_USING_PULSE_ENCODER_TMRA_5) && !defined(BSP_USING_PULSE_ENCODER_TMRA_6) && \ !defined(BSP_USING_PULSE_ENCODER_TMRA_7) && !defined(BSP_USING_PULSE_ENCODER_TMRA_8) && !defined(BSP_USING_PULSE_ENCODER_TMRA_9) && \ !defined(BSP_USING_PULSE_ENCODER_TMRA_10) && !defined(BSP_USING_PULSE_ENCODER_TMRA_11) && !defined(BSP_USING_PULSE_ENCODER_TMRA_12) - #error "Please define at least one BSP_USING_PULSE_ENCODERx" +#error "Please define at least one BSP_USING_PULSE_ENCODERx" /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif @@ -95,8 +95,7 @@ struct hc32_pulse_encoder_tmra_device char *name; }; -static struct hc32_pulse_encoder_tmra_device hc32_pulse_encoder_tmra_obj[] = -{ +static struct hc32_pulse_encoder_tmra_device hc32_pulse_encoder_tmra_obj[] = { #ifdef BSP_USING_PULSE_ENCODER_TMRA_1 PULSE_ENCODER_TMRA_1_CONFIG, #endif @@ -146,7 +145,7 @@ static void TMRA_1_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMRA_1_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_1_INDEX].tmr_handler; @@ -173,7 +172,7 @@ static void TMRA_2_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMRA_2_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_2_INDEX].tmr_handler; @@ -200,7 +199,7 @@ static void TMRA_3_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMRA_3_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_3_INDEX].tmr_handler; @@ -227,7 +226,7 @@ static void TMRA_4_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMRA_4_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_4_INDEX].tmr_handler; @@ -254,7 +253,7 @@ static void TMRA_5_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMRA_5_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_5_INDEX].tmr_handler; @@ -281,7 +280,7 @@ static void TMRA_6_Udf_callback(void) TMRA_ClearStatus(hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].tmr_handler, TMRA_FLAG_UDF); hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) +#if defined(HC32F472) void TMRA_6_Ovf_Udf_Handler(void) { CM_TMRA_TypeDef *tmr_handler = hc32_pulse_encoder_tmra_obj[PULSE_ENCODER_TMRA_6_INDEX].tmr_handler; @@ -445,7 +444,7 @@ rt_err_t _tmra_pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder) (void)TMRA_StructInit(&stcTmraInit); /* Initializes position-count unit. */ stcTmraInit.u8CountSrc = TMRA_CNT_SRC_HW; - stcTmraInit.hw_count.u16CountUpCond = hc32_device->hw_count.u16CountUpCond; + stcTmraInit.hw_count.u16CountUpCond = hc32_device->hw_count.u16CountUpCond; stcTmraInit.hw_count.u16CountDownCond = hc32_device->hw_count.u16CountDownCond; stcTmraInit.u32PeriodValue = hc32_device->u32PeriodValue; (void)TMRA_Init(hc32_device->tmr_handler, &stcTmraInit); @@ -522,8 +521,7 @@ rt_err_t _tmra_pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encod return result; } -static const struct rt_pulse_encoder_ops _tmra_ops = -{ +static const struct rt_pulse_encoder_ops _tmra_ops = { .init = _tmra_pulse_encoder_init, .get_count = _tmra_pulse_encoder_get_count, .clear_count = _tmra_pulse_encoder_clear_count, @@ -538,7 +536,7 @@ static const struct rt_pulse_encoder_ops _tmra_ops = !defined(BSP_USING_PULSE_ENCODER_TMR6_4) && !defined(BSP_USING_PULSE_ENCODER_TMR6_5) && !defined(BSP_USING_PULSE_ENCODER_TMR6_6) && \ !defined(BSP_USING_PULSE_ENCODER_TMR6_7) && !defined(BSP_USING_PULSE_ENCODER_TMR6_8) && !defined(BSP_USING_PULSE_ENCODER_TMR6_9) && \ !defined(BSP_USING_PULSE_ENCODER_TMR6_10) - #error "Please define at least one BSP_USING_PULSE_ENCODERx" +#error "Please define at least one BSP_USING_PULSE_ENCODERx" /* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ #endif @@ -602,8 +600,7 @@ struct hc32_pulse_encoder_tmr6_device char *name; }; -static struct hc32_pulse_encoder_tmr6_device hc32_pulse_encoder_tmr6_obj[] = -{ +static struct hc32_pulse_encoder_tmr6_device hc32_pulse_encoder_tmr6_obj[] = { #ifdef BSP_USING_PULSE_ENCODER_TMR6_1 PULSE_ENCODER_TMR6_1_CONFIG, #endif @@ -647,7 +644,7 @@ void TMR6_1_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMR6_1_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_1_INDEX].tmr_handler; @@ -674,7 +671,7 @@ void TMR6_2_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMR6_2_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_2_INDEX].tmr_handler; @@ -701,7 +698,7 @@ void TMR6_3_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) || defined (HC32F334) +#if defined(HC32F472) || defined(HC32F334) void TMR6_3_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_3_INDEX].tmr_handler; @@ -728,7 +725,7 @@ void TMR6_4_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) || defined (HC32F334) +#if defined(HC32F472) || defined(HC32F334) void TMR6_4_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_4_INDEX].tmr_handler; @@ -755,7 +752,7 @@ void TMR6_5_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) || defined (HC32F334) +#if defined(HC32F472) || defined(HC32F334) void TMR6_5_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_5_INDEX].tmr_handler; @@ -782,7 +779,7 @@ void TMR6_6_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) || defined (HC32F334) +#if defined(HC32F472) || defined(HC32F334) void TMR6_6_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_6_INDEX].tmr_handler; @@ -809,7 +806,7 @@ void TMR6_7_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) +#if defined(HC32F472) void TMR6_7_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_7_INDEX].tmr_handler; @@ -836,7 +833,7 @@ void TMR6_8_Udf_callback(void) TMR6_ClearStatus(hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].tmr_handler, TMR6_FLAG_UDF); hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].Over_Under_Flowcount--; } -#if defined (HC32F472) +#if defined(HC32F472) void TMR6_8_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_8_INDEX].tmr_handler; @@ -853,7 +850,7 @@ void TMR6_8_Ovf_Udf_Handler(void) #endif #ifdef BSP_USING_PULSE_ENCODER_TMR6_9 -#if defined (HC32F472) +#if defined(HC32F472) void TMR6_9_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_9_INDEX].tmr_handler; @@ -872,7 +869,7 @@ void TMR6_9_Ovf_Udf_Handler(void) #endif #ifdef BSP_USING_PULSE_ENCODER_TMR6_10 -#if defined (HC32F472) +#if defined(HC32F472) void TMR6_10_Ovf_Udf_Handler(void) { CM_TMR6_TypeDef *tmr_handler = hc32_pulse_encoder_tmr6_obj[PULSE_ENCODER_TMR6_10_INDEX].tmr_handler; @@ -944,7 +941,7 @@ rt_err_t _tmr6_pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder) (void)TMR6_StructInit(&stcTmr6Init); /* Initializes position-count unit. */ stcTmr6Init.u8CountSrc = TMR6_CNT_SRC_HW; - stcTmr6Init.hw_count.u32CountUpCond = hc32_device->hw_count.u32CountUpCond; + stcTmr6Init.hw_count.u32CountUpCond = hc32_device->hw_count.u32CountUpCond; stcTmr6Init.hw_count.u32CountDownCond = hc32_device->hw_count.u32CountDownCond; stcTmr6Init.u32PeriodValue = hc32_device->u32PeriodValue; (void)TMR6_Init(hc32_device->tmr_handler, &stcTmr6Init); @@ -1021,8 +1018,7 @@ rt_err_t _tmr6_pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encod return result; } -static const struct rt_pulse_encoder_ops _tmr6_ops = -{ +static const struct rt_pulse_encoder_ops _tmr6_ops = { .init = _tmr6_pulse_encoder_init, .get_count = _tmr6_pulse_encoder_get_count, .clear_count = _tmr6_pulse_encoder_clear_count, diff --git a/bsp/hc32/libraries/hc32_drivers/drv_pwm.c b/bsp/hc32/libraries/hc32_drivers/drv_pwm.c index bfad2524123..ac8278d08d1 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_pwm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_pwm.c @@ -9,6 +9,8 @@ * 2023-02-22 CDT support HC32F4A0 * 2024-11-20 CDT support HC32F448 * 2025-01-03 CDT support HC32F472 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ #include @@ -20,15 +22,16 @@ #if defined(BSP_USING_PWM) // #define DRV_DEBUG -#define LOG_TAG "drv_pwm" +#define LOG_TAG "drv_pwm" #include #if defined(BSP_USING_PWM_TMRA) #if defined(HC32F460) || defined(HC32F448) - #define TMRA_CHANNEL_NUM_MAX 8U -#elif defined(HC32F4A0) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) - #define TMRA_CHANNEL_NUM_MAX 4U +#define TMRA_CHANNEL_NUM_MAX 8U +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) +#define TMRA_CHANNEL_NUM_MAX 4U #endif enum @@ -84,8 +87,7 @@ struct hc32_pwm_tmra stc_tmra_pwm_init_t stcPwmInit; }; -static struct hc32_pwm_tmra g_pwm_tmra_array[] = -{ +static struct hc32_pwm_tmra g_pwm_tmra_array[] = { #ifdef BSP_USING_PWM_TMRA_1 PWM_TMRA_1_CONFIG, #endif @@ -129,7 +131,8 @@ static rt_uint32_t tmra_get_clk_notdiv(CM_TMRA_TypeDef *TMRAx) rt_uint32_t u32clkFreq; rt_uint32_t u32BusName; -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) switch ((rt_uint32_t)TMRAx) { case (rt_uint32_t)CM_TMRA_1: @@ -297,7 +300,7 @@ static rt_err_t tmra_pwm_set_period(struct rt_device_pwm *device, struct rt_pwm_ return -RT_ERROR; } period_value = configuration->period * (rt_uint64_t)u32clkFreq / (rt_uint64_t)1000000000; - period_value = period_value > 1 ? period_value - 1 : 1; + period_value = period_value > 1 ? period_value - 1 : 1; TMRA_SetPeriodValue(TMRAx, period_value); /* setting PeriodValue maybe change the div,so we need to recalculate the CompareValue */ @@ -306,7 +309,8 @@ static rt_err_t tmra_pwm_set_period(struct rt_device_pwm *device, struct rt_pwm_ if (pwm->channel & (0x01UL << i)) { compare_value = (*(compare_value_channelx + i)) * (rt_uint64_t)u32clkFreq / (rt_uint64_t)1000000000; - compare_value = compare_value >= period_value ? period_value : compare_value > 1 ? compare_value - 1 : compare_value; + compare_value = compare_value >= period_value ? period_value : compare_value > 1 ? compare_value - 1 + : compare_value; TMRA_SetCompareValue(TMRAx, i, compare_value); tmra_duyt100or0_output(TMRAx, i, compare_value + 1); } @@ -326,7 +330,8 @@ static rt_err_t tmra_pwm_set_pulse(struct rt_device_pwm *device, struct rt_pwm_c u32clkFreq = tmra_get_clk_bydiv(TMRAx); period_value = TMRA_GetPeriodValue(TMRAx) + 1; compare_value = configuration->pulse * (rt_uint64_t)u32clkFreq / (rt_uint64_t)1000000000; - compare_value = compare_value > period_value ? period_value - 1 : compare_value > 1 ? compare_value - 1 : compare_value; + compare_value = compare_value > period_value ? period_value - 1 : compare_value > 1 ? compare_value - 1 + : compare_value; TMRA_SetCompareValue(TMRAx, configuration->channel, compare_value); tmra_duyt100or0_output(TMRAx, configuration->channel, compare_value + 1); @@ -651,7 +656,8 @@ static rt_err_t _tmra_pwm_control(struct rt_device_pwm *device, int cmd, void *a { struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; - if (!configuration->channel) return -RT_EINVAL; + if (!configuration->channel) + return -RT_EINVAL; configuration->channel = (configuration->channel - 1) % TMRA_CHANNEL_NUM_MAX; @@ -674,18 +680,18 @@ static rt_err_t _tmra_pwm_control(struct rt_device_pwm *device, int cmd, void *a } } -static struct rt_pwm_ops _tmra_ops = -{ +static struct rt_pwm_ops _tmra_ops = { _tmra_pwm_control }; #endif /* BSP_USING_PWM_TMRA */ #if defined(BSP_USING_PWM_TMR4) -#if defined (HC32F4A8) || defined (HC32F472) || defined (HC32F4A0) || defined (HC32F460) - #define TMR4_CHANNEL_NUM_MAX 6U -#elif defined (HC32F448) || defined (HC32F334) - #define TMR4_CHANNEL_NUM_MAX 8U +#if defined(HC32F4A8) || defined(HC32F472) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || \ + defined(HC32F467) +#define TMR4_CHANNEL_NUM_MAX 6U +#elif defined(HC32F448) || defined(HC32F334) +#define TMR4_CHANNEL_NUM_MAX 8U #endif enum @@ -715,8 +721,7 @@ struct hc32_pwm_tmr4 stc_tmr4_pwm_init_t stcTmr4PwmInit; }; -static struct hc32_pwm_tmr4 g_pwm_tmr4_array[] = -{ +static struct hc32_pwm_tmr4 g_pwm_tmr4_array[] = { #ifdef BSP_USING_PWM_TMR4_1 PWM_TMR4_1_CONFIG, #endif @@ -730,8 +735,9 @@ static struct hc32_pwm_tmr4 g_pwm_tmr4_array[] = static rt_uint32_t tmr4_get_clk_notdiv(CM_TMR4_TypeDef *TMR4x) { - rt_uint32_t u32clkFreq; -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) + rt_uint32_t u32clkFreq = 0UL; +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) u32clkFreq = CLK_GetBusClockFreq(CLK_BUS_PCLK0); #elif defined(HC32F460) u32clkFreq = CLK_GetBusClockFreq(CLK_BUS_PCLK1); @@ -870,7 +876,7 @@ static rt_err_t tmr4_pwm_set_period(struct rt_device_pwm *device, struct rt_pwm_ return -RT_ERROR; } period_value = configuration->period * (rt_uint64_t)u32clkFreq / (rt_uint64_t)1000000000; - period_value = period_value > 1 ? period_value - 1 : 1; + period_value = period_value > 1 ? period_value - 1 : 1; TMR4_SetPeriodValue(TMR4x, period_value); for (rt_uint32_t i = 0; i < TMR4_CHANNEL_NUM_MAX; i++) @@ -878,7 +884,8 @@ static rt_err_t tmr4_pwm_set_period(struct rt_device_pwm *device, struct rt_pwm_ if (pwm->channel & (0x01UL << i)) { compare_value = (*(compare_value_channelx + i)) * (rt_uint64_t)u32clkFreq / (rt_uint64_t)1000000000; - compare_value = compare_value >= period_value ? period_value : compare_value > 1 ? compare_value - 1 : compare_value; + compare_value = compare_value >= period_value ? period_value : compare_value > 1 ? compare_value - 1 + : compare_value; TMR4_OC_SetCompareValue(TMR4x, i, compare_value); } } @@ -915,11 +922,13 @@ static rt_err_t tmr4_pwm_set_pulse(struct rt_device_pwm *device, struct rt_pwm_c u32clkFreq = tmr4_get_clk_bydiv(TMR4x); period_value = TMR4_GetPeriodValue(TMR4x) + 1; - compare_value = (rt_uint64_t)configuration->pulse * u32clkFreq / (rt_uint64_t)1000000000;; - compare_value = compare_value > period_value ? period_value - 1 : compare_value > 1 ? compare_value - 1 : compare_value; + compare_value = (rt_uint64_t)configuration->pulse * u32clkFreq / (rt_uint64_t)1000000000; + ; + compare_value = compare_value > period_value ? period_value - 1 : compare_value > 1 ? compare_value - 1 + : compare_value; TMR4_OC_SetCompareValue(TMR4x, configuration->channel, compare_value); - *(compare_value_channelx + configuration->channel) = configuration->pulse; + *(compare_value_channelx + configuration->channel) = configuration->pulse; return RT_EOK; } @@ -935,7 +944,7 @@ static rt_err_t tmr4_pwm_set(struct rt_device_pwm *device, struct rt_pwm_configu static void enable_tmr4_unit_clk(void) { #ifdef BSP_USING_PWM_TMR4_1 -#if defined(HC32F472) || defined (HC32F334) +#if defined(HC32F472) || defined(HC32F334) FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR4, ENABLE); #else FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR4_1, ENABLE); @@ -963,13 +972,15 @@ static rt_err_t pwm_tmr4_init(struct hc32_pwm_tmr4 *device) { TMR4_OC_Init(TMR4x, i, &device->stcTmr4OcInit); TMR4_PWM_Init(TMR4x, (i >> 1), &device->stcTmr4PwmInit); -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) TMR4_PWM_SetPortOutputMode(TMR4x, i, TMR4_PWM_PIN_OUTPUT_NORMAL); #endif tmr4_pwm_set_cmpmode(TMR4x, i); } } -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) TMR4_PWM_MainOutputCmd(TMR4x, ENABLE); #endif TMR4_Start(TMR4x); @@ -998,7 +1009,7 @@ static void pwm_tmr4_get_channel(void) #ifdef BSP_USING_PWM_TMR4_1_OWL g_pwm_tmr4_array[PWM_TMR4_1_INDEX].channel |= (1 << 5); #endif -#if defined (HC32F448) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F334) #ifdef BSP_USING_PWM_TMR4_1_OXH g_pwm_tmr4_array[PWM_TMR4_1_INDEX].channel |= (1 << 6); #endif @@ -1053,7 +1064,8 @@ static rt_err_t _tmr4_pwm_control(struct rt_device_pwm *device, int cmd, void *a { struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; - if (!configuration->channel) return -RT_EPERM; + if (!configuration->channel) + return -RT_EPERM; configuration->channel = (configuration->channel - 1) % TMR4_CHANNEL_NUM_MAX; @@ -1076,8 +1088,7 @@ static rt_err_t _tmr4_pwm_control(struct rt_device_pwm *device, int cmd, void *a } } -static struct rt_pwm_ops _tmr4_ops = -{ +static struct rt_pwm_ops _tmr4_ops = { _tmr4_pwm_control }; @@ -1085,7 +1096,7 @@ static struct rt_pwm_ops _tmr4_ops = #if defined(BSP_USING_PWM_TMR6) -#define TMR6_CHANNEL_NUM_MAX 2U +#define TMR6_CHANNEL_NUM_MAX 2U enum { @@ -1133,8 +1144,7 @@ struct hc32_pwm_tmr6 rt_bool_t complementary[TMR6_CHANNEL_NUM_MAX]; }; -static struct hc32_pwm_tmr6 g_pwm_tmr6_array[] = -{ +static struct hc32_pwm_tmr6 g_pwm_tmr6_array[] = { #ifdef BSP_USING_PWM_TMR6_1 PWM_TMR6_1_CONFIG, #endif @@ -1207,7 +1217,8 @@ static rt_uint32_t tmr6_get_clk_bydiv(CM_TMR6_TypeDef *TMR6x) case (TMR6_CLK_DIV1024): u32clkFreq /= 1024; break; -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) case (TMR6_CLK_DIV32): u32clkFreq /= 32; break; @@ -1228,7 +1239,8 @@ static void tmr6_duyt100or0_output(CM_TMR6_TypeDef *TMR6x, rt_uint32_t channel, { if (compare_value <= 1) { -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_OVF, TMR6_PWM_LOW); #elif defined(HC32F460) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_MATCH_PERIOD, TMR6_PWM_LOW); @@ -1236,7 +1248,8 @@ static void tmr6_duyt100or0_output(CM_TMR6_TypeDef *TMR6x, rt_uint32_t channel, } else { -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_OVF, TMR6_PWM_HIGH); #elif defined(HC32F460) TMR6_PWM_SetPolarity(TMR6x, channel, TMR6_STAT_MATCH_PERIOD, TMR6_PWM_HIGH); @@ -1337,7 +1350,8 @@ static rt_err_t tmr6_pwm_set_period(struct rt_device_pwm *device, struct rt_pwm_ if (pwm->channel & (0x01UL << i)) { compare_value = (pwm_init_t + i)->u32CompareValue * (rt_uint64_t)u32clkFreq / (rt_uint64_t)1000000000; - compare_value = compare_value >= period_value ? period_value : compare_value > 1 ? compare_value - 1 : compare_value; + compare_value = compare_value >= period_value ? period_value : compare_value > 1 ? compare_value - 1 + : compare_value; TMR6_SetCompareValue(TMR6x, i, compare_value); tmr6_duyt100or0_output(TMR6x, i, compare_value + 1); } @@ -1357,7 +1371,8 @@ static rt_err_t tmr6_pwm_set_pulse(struct rt_device_pwm *device, struct rt_pwm_c period_value = TMR6_GetPeriodValue(TMR6x, TMR6_PERIOD_REG_A) + 1; compare_value = configuration->pulse * (rt_uint64_t)u32clkFreq / (rt_uint64_t)1000000000; - compare_value = compare_value > period_value ? period_value - 1 : compare_value > 1 ? compare_value - 1 : compare_value; + compare_value = compare_value > period_value ? period_value - 1 : compare_value > 1 ? compare_value - 1 + : compare_value; TMR6_SetCompareValue(TMR6x, configuration->channel, compare_value); tmr6_duyt100or0_output(TMR6x, configuration->channel, compare_value + 1); @@ -1516,7 +1531,8 @@ static rt_err_t _tmr6_pwm_control(struct rt_device_pwm *device, int cmd, void *a { struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; - if (!configuration->channel) return -RT_EINVAL; + if (!configuration->channel) + return -RT_EINVAL; configuration->channel = (configuration->channel - 1) % TMR6_CHANNEL_NUM_MAX; @@ -1539,8 +1555,7 @@ static rt_err_t _tmr6_pwm_control(struct rt_device_pwm *device, int cmd, void *a } } -static struct rt_pwm_ops _tmr6_ops = -{ +static struct rt_pwm_ops _tmr6_ops = { _tmr6_pwm_control }; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_qspi.c b/bsp/hc32/libraries/hc32_drivers/drv_qspi.c index 3e9708c0113..ee17e406f47 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_qspi.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_qspi.c @@ -11,6 +11,8 @@ * 2024-02-29 CDT Support multi line write/read * 2024-04-18 CDT support HC32F472 * 2025-04-14 CDT support HC32F4A8 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-10 CDT support HC32F467 */ /******************************************************************************* @@ -34,37 +36,37 @@ * Local pre-processor symbols/macros ('#define') ******************************************************************************/ // #define DRV_DEBUG -#define LOG_TAG "drv.qspi" +#define LOG_TAG "drv.qspi" #include /* QSPI read/write function */ -#define QSPI_READ_FUNC (0U) -#define QSPI_WRITE_FUNC (1U) +#define QSPI_READ_FUNC (0U) +#define QSPI_WRITE_FUNC (1U) /* QSPI direct communication line */ -#define QSPI_DIRECT_COMM_LINE_ONE (0U) -#define QSPI_DIRECT_COMM_LINE_MULTI (1U) +#define QSPI_DIRECT_COMM_LINE_ONE (0U) +#define QSPI_DIRECT_COMM_LINE_MULTI (1U) -#define QSPI_BASE_BLK_SIZE (0x4000000UL) -#define QSPI_MAX_FLASH_ADDR (0xFC000000UL) +#define QSPI_BASE_BLK_SIZE (0x4000000UL) +#define QSPI_MAX_FLASH_ADDR (0xFC000000UL) /* QSPI max division */ -#define QSPI_MAX_DIV_VAL (0x3FU) /* Div64 */ +#define QSPI_MAX_DIV_VAL (0x3FU) /* Div64 */ /* QSPI read instruction */ -#define QSPI_3LINE_STD_RD (0x03U) -#define QSPI_3LINE_FAST_RD (0x0BU) -#define QSPI_3LINE_DUAL_OUTPUT_FAST_RD (0x3BU) -#define QSPI_3LINE_DUAL_IO_FAST_RD (0xBBU) -#define QSPI_3LINE_QUAD_OUTPUT_FAST_RD (0x6BU) -#define QSPI_3LINE_QUAD_IO_FAST_RD (0xEBU) - -#define QSPI_4LINE_STD_RD (0x13U) -#define QSPI_4LINE_FAST_RD (0x0CU) -#define QSPI_4LINE_DUAL_OUTPUT_FAST_RD (0x3CU) -#define QSPI_4LINE_DUAL_IO_FAST_RD (0xBCU) -#define QSPI_4LINE_QUAD_OUTPUT_FAST_RD (0x6CU) -#define QSPI_4LINE_QUAD_IO_FAST_RD (0xECU) +#define QSPI_3LINE_STD_RD (0x03U) +#define QSPI_3LINE_FAST_RD (0x0BU) +#define QSPI_3LINE_DUAL_OUTPUT_FAST_RD (0x3BU) +#define QSPI_3LINE_DUAL_IO_FAST_RD (0xBBU) +#define QSPI_3LINE_QUAD_OUTPUT_FAST_RD (0x6BU) +#define QSPI_3LINE_QUAD_IO_FAST_RD (0xEBU) + +#define QSPI_4LINE_STD_RD (0x13U) +#define QSPI_4LINE_FAST_RD (0x0CU) +#define QSPI_4LINE_DUAL_OUTPUT_FAST_RD (0x3CU) +#define QSPI_4LINE_DUAL_IO_FAST_RD (0xBCU) +#define QSPI_4LINE_QUAD_OUTPUT_FAST_RD (0x6CU) +#define QSPI_4LINE_QUAD_IO_FAST_RD (0xECU) /******************************************************************************* * Global variable definitions (declared in header file with 'extern') @@ -80,12 +82,19 @@ static void qspi_err_irq_handler(void); * Local variable definitions ('static') ******************************************************************************/ #ifndef BSP_QSPI_USING_SOFT_CS -static const uint8_t qspi_rom_cmd_list[] = -{ - QSPI_3LINE_STD_RD, QSPI_3LINE_FAST_RD, QSPI_3LINE_DUAL_OUTPUT_FAST_RD, - QSPI_3LINE_DUAL_IO_FAST_RD, QSPI_3LINE_QUAD_OUTPUT_FAST_RD, QSPI_3LINE_QUAD_IO_FAST_RD, - QSPI_4LINE_STD_RD, QSPI_4LINE_FAST_RD, QSPI_4LINE_DUAL_OUTPUT_FAST_RD, - QSPI_4LINE_DUAL_IO_FAST_RD, QSPI_4LINE_QUAD_OUTPUT_FAST_RD, QSPI_4LINE_QUAD_IO_FAST_RD, +static const uint8_t qspi_rom_cmd_list[] = { + QSPI_3LINE_STD_RD, + QSPI_3LINE_FAST_RD, + QSPI_3LINE_DUAL_OUTPUT_FAST_RD, + QSPI_3LINE_DUAL_IO_FAST_RD, + QSPI_3LINE_QUAD_OUTPUT_FAST_RD, + QSPI_3LINE_QUAD_IO_FAST_RD, + QSPI_4LINE_STD_RD, + QSPI_4LINE_FAST_RD, + QSPI_4LINE_DUAL_OUTPUT_FAST_RD, + QSPI_4LINE_DUAL_IO_FAST_RD, + QSPI_4LINE_QUAD_OUTPUT_FAST_RD, + QSPI_4LINE_QUAD_IO_FAST_RD, }; #endif @@ -130,9 +139,9 @@ static int hc32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configur /* qspi port init */ rt_hw_qspi_board_init(); /* Init QSPI */ - stcQspiInit.u32ReadMode = QSPI_RD_MD_STD_RD; - stcQspiInit.u32DummyCycle = QSPI_DUMMY_CYCLE4; - stcQspiInit.u32AddrWidth = QSPI_ADDR_WIDTH_24BIT; + stcQspiInit.u32ReadMode = QSPI_RD_MD_STD_RD; + stcQspiInit.u32DummyCycle = QSPI_DUMMY_CYCLE4; + stcQspiInit.u32AddrWidth = QSPI_ADDR_WIDTH_24BIT; (void)QSPI_Init(&stcQspiInit); QSPI_SetWpPinLevel(QSPI_WP_PIN_LEVEL); /* Enable error interrupt */ @@ -149,7 +158,7 @@ static int hc32_qspi_init(struct rt_qspi_device *device, struct rt_qspi_configur FCG_Fcg0PeriphClockCmd(qspi_dma->clock, ENABLE); /* Config Dma */ DMA_StructInit(&stcDmaInit); - stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; /* Init Dma */ if (LL_OK != DMA_Init(qspi_dma->Instance, qspi_dma->channel, &stcDmaInit)) { @@ -216,7 +225,7 @@ static int32_t hc32_qspi_check_direct_comm_param(struct rt_qspi_message *message if (message->address.size != 0) { if (((message->address.qspi_lines > 2) && (message->address.qspi_lines != 4)) || - ((message->address.size % 8) != 0)) + ((message->address.size % 8) != 0)) { return LL_ERR_INVD_PARAM; } @@ -259,13 +268,13 @@ static int32_t hc32_qspi_send_cmd(struct hc32_qspi_bus *qspi_bus, struct rt_qspi if ((QSPI_READ_FUNC == u8Func) && (LL_OK == hc32_qspi_search_rom_cmd(u8Instr))) { if ((message->instruction.qspi_lines != 1) || - ((message->address.qspi_lines != 1) && (message->address.qspi_lines != 2) && (message->address.qspi_lines != 4)) || - ((message->qspi_data_lines != 1) && (message->qspi_data_lines != 2) && (message->qspi_data_lines != 4))) + ((message->address.qspi_lines != 1) && (message->address.qspi_lines != 2) && (message->address.qspi_lines != 4)) || + ((message->qspi_data_lines != 1) && (message->qspi_data_lines != 2) && (message->qspi_data_lines != 4))) { return LL_ERR_INVD_PARAM; } if (((message->address.qspi_lines == 2) && ((message->qspi_data_lines == 1) || (message->qspi_data_lines == 4))) || - ((message->address.qspi_lines == 4) && ((message->qspi_data_lines == 1) || (message->qspi_data_lines == 2)))) + ((message->address.qspi_lines == 4) && ((message->qspi_data_lines == 1) || (message->qspi_data_lines == 2)))) { return LL_ERR_INVD_PARAM; } @@ -312,7 +321,7 @@ static int32_t hc32_qspi_send_cmd(struct hc32_qspi_bus *qspi_bus, struct rt_qspi else #endif { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS if (LL_OK != hc32_qspi_check_direct_comm_param(message, QSPI_DIRECT_COMM_LINE_ONE)) { @@ -328,7 +337,7 @@ static int32_t hc32_qspi_send_cmd(struct hc32_qspi_bus *qspi_bus, struct rt_qspi /* Set custom read mode */ QSPI_SetReadMode(QSPI_RD_MD_CUSTOM_FAST_RD); #endif -#elif defined (HC32F448) || defined (HC32F4A8) +#elif defined(HC32F448) || defined(HC32F4A8) if (LL_OK != hc32_qspi_check_direct_comm_param(message, QSPI_DIRECT_COMM_LINE_MULTI)) { return LL_ERR_INVD_PARAM; @@ -347,11 +356,10 @@ static void hc32_qspi_word_to_byte(uint32_t u32Word, uint8_t *pu8Byte, uint8_t u do { pu8Byte[u8Count++] = (uint8_t)(u32Word >> (u32ByteNum * 8U)) & 0xFFU; - } - while ((u32ByteNum--) != 0UL); + } while ((u32ByteNum--) != 0UL); } -#if defined (HC32F448) || defined (HC32F4A8) +#if defined(HC32F448) || defined(HC32F4A8) static rt_uint32_t hc32_qspi_get_dcom_protocol_line(rt_uint8_t protocol_line) { rt_uint32_t dcom_protocol_line; @@ -376,38 +384,38 @@ static rt_uint32_t hc32_qspi_get_dcom_protocol_line(rt_uint8_t protocol_line) static void hc32_qspi_write_direct_comm_value(rt_uint8_t protocol_line, rt_uint8_t value) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) (void)protocol_line; QSPI_WriteDirectCommValue(value); -#elif defined (HC32F448) || defined (HC32F4A8) +#elif defined(HC32F448) || defined(HC32F4A8) QSPI_WriteDirectCommValue(hc32_qspi_get_dcom_protocol_line(protocol_line), value); #endif } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS static void hc32_qspi_set_trans_protocol(uint32_t u32Line) { stc_qspi_custom_mode_t stcCustomMode; - stcCustomMode.u8InstrCode = 0U; + stcCustomMode.u8InstrCode = 0U; switch (u32Line) { case 2: - stcCustomMode.u32InstrProtocol = QSPI_INSTR_PROTOCOL_2LINE; - stcCustomMode.u32AddrProtocol = QSPI_ADDR_PROTOCOL_2LINE; - stcCustomMode.u32DataProtocol = QSPI_DATA_PROTOCOL_2LINE; + stcCustomMode.u32InstrProtocol = QSPI_INSTR_PROTOCOL_2LINE; + stcCustomMode.u32AddrProtocol = QSPI_ADDR_PROTOCOL_2LINE; + stcCustomMode.u32DataProtocol = QSPI_DATA_PROTOCOL_2LINE; break; case 4: - stcCustomMode.u32InstrProtocol = QSPI_INSTR_PROTOCOL_4LINE; - stcCustomMode.u32AddrProtocol = QSPI_ADDR_PROTOCOL_4LINE; - stcCustomMode.u32DataProtocol = QSPI_DATA_PROTOCOL_4LINE; + stcCustomMode.u32InstrProtocol = QSPI_INSTR_PROTOCOL_4LINE; + stcCustomMode.u32AddrProtocol = QSPI_ADDR_PROTOCOL_4LINE; + stcCustomMode.u32DataProtocol = QSPI_DATA_PROTOCOL_4LINE; break; case 1: default: - stcCustomMode.u32InstrProtocol = QSPI_INSTR_PROTOCOL_1LINE; - stcCustomMode.u32AddrProtocol = QSPI_ADDR_PROTOCOL_1LINE; - stcCustomMode.u32DataProtocol = QSPI_DATA_PROTOCOL_1LINE; + stcCustomMode.u32InstrProtocol = QSPI_INSTR_PROTOCOL_1LINE; + stcCustomMode.u32AddrProtocol = QSPI_ADDR_PROTOCOL_1LINE; + stcCustomMode.u32DataProtocol = QSPI_DATA_PROTOCOL_1LINE; break; } QSPI_CustomReadConfig(&stcCustomMode); @@ -430,25 +438,25 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q rt_uint32_t src_addr; #endif -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS /* Enter direct communication mode */ SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif -#elif defined (HC32F448) || defined (HC32F4A8) +#elif defined(HC32F448) || defined(HC32F4A8) /* Enter direct communication mode */ SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif if (0UL != u32InstrLen) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->instruction.qspi_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif #endif hc32_qspi_write_direct_comm_value(message->instruction.qspi_lines, u8Instr); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif @@ -456,7 +464,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q } if ((NULL != pu8Addr) && (0UL != u32AddrLen)) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->address.qspi_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -466,7 +474,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q { hc32_qspi_write_direct_comm_value(message->address.qspi_lines, pu8Addr[u32Count]); } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif @@ -474,7 +482,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q } if ((NULL != pu8WriteBuf) && (0UL != u32BufLen)) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->qspi_data_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -486,14 +494,14 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q AOS_SetTriggerEventSrc(qspi_dma->trigger_select, qspi_dma->trigger_event); /* Config Dma */ DMA_StructInit(&stcDmaInit); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) - stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; -#elif defined (HC32F448) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; +#elif defined(HC32F448) || defined(HC32F4A8) rt_uint16_t dcom_line = (rt_uint16_t)hc32_qspi_get_dcom_protocol_line(message->qspi_data_lines); - stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT; + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT; #endif - stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC; - stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX; + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC; + stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX; DMA_Init(qspi_dma->Instance, qspi_dma->channel, &stcDmaInit); while (u32BufLen != 0U) { @@ -508,9 +516,9 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q u32BufLen = 0U; } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) src_addr = (rt_uint32_t)&pu8WriteBuf[u32TxIndex]; -#elif defined (HC32F448) || defined (HC32F4A8) +#elif defined(HC32F448) || defined(HC32F4A8) if (u32DmaTransSize > qspi_bus->config->dma_tx_buf_size) { LOG_E("qspi dma transmit size over buffer size!"); @@ -533,7 +541,7 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q u32TimeoutCnt = 0U; /* Wait DMA transfer completed */ while ((RESET == DMA_GetTransCompleteStatus(qspi_dma->Instance, qspi_dma->flag)) && - (u32TimeoutCnt < qspi_bus->config->timeout)) + (u32TimeoutCnt < qspi_bus->config->timeout)) { rt_thread_mdelay(1); u32TimeoutCnt++; @@ -552,19 +560,19 @@ static int32_t hc32_qspi_write_instr(struct hc32_qspi_bus *qspi_bus, struct rt_q } #endif -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS /* Exit direct communication mode */ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif #endif } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS /* Exit direct communication mode */ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif -#elif defined (HC32F448) || defined (HC32F4A8) +#elif defined(HC32F448) || defined(HC32F4A8) /* Exit direct communication mode */ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif @@ -585,18 +593,18 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs uint32_t u32RxIndex = 0U; rt_uint32_t u32TimeoutCnt; #endif -#if defined (HC32F448) || defined (HC32F4A8) +#if defined(HC32F448) || defined(HC32F4A8) rt_uint32_t u32ReadMd; #endif -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS /* Enter direct communication mode */ SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif -#elif defined (HC32F448) || defined (HC32F4A8) +#elif defined(HC32F448) || defined(HC32F4A8) if ((message->instruction.qspi_lines == 4) || (message->address.qspi_lines == 4) || - (message->qspi_data_lines == 4)) + (message->qspi_data_lines == 4)) { u32ReadMd = READ_REG32_BIT(CM_QSPI->CR, QSPI_CR_MDSEL); QSPI_SetReadMode(QSPI_RD_MD_QUAD_IO_FAST_RD); @@ -606,14 +614,14 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs #endif if (0UL != u32InstrLen) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->instruction.qspi_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif #endif hc32_qspi_write_direct_comm_value(message->instruction.qspi_lines, u8Instr); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif @@ -621,7 +629,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs } if ((NULL != pu8Addr) && (0UL != u32AddrLen)) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->address.qspi_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -631,7 +639,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs { hc32_qspi_write_direct_comm_value(message->address.qspi_lines, pu8Addr[u32Count]); } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif @@ -639,7 +647,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs } if ((NULL != pu8ReadBuf) && (0UL != u32BufLen)) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS hc32_qspi_set_trans_protocol(message->qspi_data_lines); SET_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); @@ -651,9 +659,9 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs AOS_SetTriggerEventSrc(qspi_dma->trigger_select, qspi_dma->trigger_event); /* Config Dma */ DMA_StructInit(&stcDmaInit); - stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; - stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; - stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_INC; + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; + stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_INC; DMA_Init(qspi_dma->Instance, qspi_dma->channel, &stcDmaInit); while (u32BufLen != 0U) { @@ -677,7 +685,7 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs u32TimeoutCnt = 0U; /* Wait DMA transfer completed */ while ((RESET == DMA_GetTransCompleteStatus(qspi_dma->Instance, qspi_dma->flag)) && - (u32TimeoutCnt < qspi_bus->config->timeout)) + (u32TimeoutCnt < qspi_bus->config->timeout)) { rt_thread_mdelay(1); u32TimeoutCnt++; @@ -696,21 +704,21 @@ static int32_t hc32_qspi_read_instr(struct hc32_qspi_bus *qspi_bus, struct rt_qs } #endif -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifdef BSP_QSPI_USING_SOFT_CS /* Exit direct communication mode */ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif #endif } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) #ifndef BSP_QSPI_USING_SOFT_CS /* Exit direct communication mode */ CLR_REG32_BIT(CM_QSPI->CR, QSPI_CR_DCOME); #endif -#elif defined (HC32F448) || defined (HC32F4A8) +#elif defined(HC32F448) || defined(HC32F4A8) if ((message->instruction.qspi_lines == 4) || (message->address.qspi_lines == 4) || - (message->qspi_data_lines == 4)) + (message->qspi_data_lines == 4)) { QSPI_SetReadMode(u32ReadMd); } @@ -802,9 +810,9 @@ static int32_t hc32_qspi_read(struct hc32_qspi_bus *qspi_bus, struct rt_qspi_mes AOS_SetTriggerEventSrc(qspi_dma->trigger_select, qspi_dma->trigger_event); /* Config Dma */ DMA_StructInit(&stcDmaInit); - stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; - stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC; - stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_INC; + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC; + stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_INC; DMA_Init(qspi_dma->Instance, qspi_dma->channel, &stcDmaInit); while (length != 0) { @@ -841,7 +849,7 @@ static int32_t hc32_qspi_read(struct hc32_qspi_bus *qspi_bus, struct rt_qspi_mes u32TimeoutCnt = 0U; /* Wait DMA transfer completed */ while ((RESET == DMA_GetTransCompleteStatus(qspi_dma->Instance, qspi_dma->flag)) && - (u32TimeoutCnt < qspi_bus->config->timeout)) + (u32TimeoutCnt < qspi_bus->config->timeout)) { rt_thread_mdelay(1); u32TimeoutCnt++; @@ -995,8 +1003,7 @@ static rt_err_t qspi_configure(struct rt_spi_device *device, struct rt_spi_confi return hc32_qspi_init(qspi_device, &qspi_device->config); } -static const struct rt_spi_ops hc32_qspi_ops = -{ +static const struct rt_spi_ops hc32_qspi_ops = { .configure = qspi_configure, .xfer = qspixfer, }; @@ -1019,7 +1026,7 @@ static void qspi_err_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F448) || defined (HC32F472) +#if defined(HC32F448) || defined(HC32F472) void QSPI_Handler(void) { qspi_err_irq_handler(); @@ -1061,9 +1068,9 @@ rt_err_t rt_hw_qspi_bus_attach_device(const char *bus_name, const char *device_n result = RT_ENOMEM; goto __exit; } - qspi_device->enter_qspi_mode = enter_qspi_mode; - qspi_device->exit_qspi_mode = exit_qspi_mode; - qspi_device->config.qspi_dl_width = data_line_width; + qspi_device->enter_qspi_mode = enter_qspi_mode; + qspi_device->exit_qspi_mode = exit_qspi_mode; + qspi_device->config.qspi_dl_width = data_line_width; cs_pin->pin = pin; #ifdef BSP_QSPI_USING_SOFT_CS @@ -1085,7 +1092,7 @@ rt_err_t rt_hw_qspi_bus_attach_device(const char *bus_name, const char *device_n } } - return result; + return result; } static void hc32_get_qspi_info(void) @@ -1094,8 +1101,8 @@ static void hc32_get_qspi_info(void) qspi_config.err_irq.irq_callback = qspi_err_irq_handler; #ifdef BSP_QSPI_USING_DMA static struct dma_config qspi_dma = QSPI_DMA_CONFIG; - qspi_config.dma_qspi = &qspi_dma; -#if defined (HC32F448) || defined (HC32F4A8) + qspi_config.dma_qspi = &qspi_dma; +#if defined(HC32F448) || defined(HC32F4A8) qspi_config.dma_tx_buf_size = QSPI_DMA_TX_BUFSIZE; qspi_config.dma_tx_buf = rt_malloc(qspi_config.dma_tx_buf_size << 1); #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_qspi.h b/bsp/hc32/libraries/hc32_drivers/drv_qspi.h index 60389ea9c5d..88cdf1da4b2 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_qspi.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_qspi.h @@ -28,28 +28,28 @@ struct hc32_hw_qspi_cs struct hc32_qspi_irq_config { struct hc32_irq_config irq_config; - func_ptr_t irq_callback; + func_ptr_t irq_callback; }; struct hc32_qspi_config { - CM_QSPI_TypeDef *Instance; - rt_uint32_t clock; - rt_uint32_t timeout; + CM_QSPI_TypeDef *Instance; + rt_uint32_t clock; + rt_uint32_t timeout; struct hc32_qspi_irq_config err_irq; #ifdef BSP_QSPI_USING_DMA - struct dma_config *dma_qspi; -#if defined (HC32F448) || defined (HC32F4A8) - rt_uint16_t *dma_tx_buf; - rt_uint16_t dma_tx_buf_size; /* unit: half-word, DMA data width of QSPI transmitting is 16bit */ + struct dma_config *dma_qspi; +#if defined(HC32F448) || defined(HC32F4A8) + rt_uint16_t *dma_tx_buf; + rt_uint16_t dma_tx_buf_size; /* unit: half-word, DMA data width of QSPI transmitting is 16bit */ #endif #endif }; struct hc32_qspi_bus { - struct hc32_qspi_config *config; - char *bus_name; + struct hc32_qspi_config *config; + char *bus_name; }; rt_err_t rt_hw_qspi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin, rt_uint8_t data_line_width, void (*enter_qspi_mode)(), void (*exit_qspi_mode)()); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_rtc.c b/bsp/hc32/libraries/hc32_drivers/drv_rtc.c index 6896fb675c6..cb90cbe4d77 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_rtc.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_rtc.c @@ -10,6 +10,8 @@ * 2022-06-10 xiaoxiaolisunny re-add this file for F460 * 2023-02-14 CDT add alarm(precision is 1 minute) * 2024-06-07 CDT Add support for F448/F472 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-09 CDT support HC32F467, fix local time calculation bug */ #include @@ -19,19 +21,18 @@ #if defined(BSP_USING_RTC) //#define DRV_DEBUG -#define LOG_TAG "drv.rtc" +#define LOG_TAG "drv.rtc" #include -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) /* BACKUP REG: 96~127 for RTC used */ -#define RTC_BACKUP_DATA_SIZE (32U) -#define RTC_BACKUP_REG_OFFSET (128U - RTC_BACKUP_DATA_SIZE) - -static const uint8_t m_au8BackupWriteData[RTC_BACKUP_DATA_SIZE] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, - 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, - 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, - 31 - }; +#define RTC_BACKUP_DATA_SIZE (32U) +#define RTC_BACKUP_REG_OFFSET (128U - RTC_BACKUP_DATA_SIZE) + +static const uint8_t m_au8BackupWriteData[RTC_BACKUP_DATA_SIZE] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, + 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, + 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, + 31 }; static uint8_t m_au8BackupReadData[RTC_BACKUP_DATA_SIZE]; #endif @@ -40,27 +41,26 @@ static rt_rtc_dev_t rtc_dev; #ifdef RT_USING_ALARM struct stc_hc32_alarm_irq { - struct hc32_irq_config irq_config; - func_ptr_t irq_callback; + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; }; static void _rtc_alarm_irq_handler(void); -#define RTC_ALARM_IRQ_CONFIG \ - { \ - .irq_num = BSP_RTC_ALARM_IRQ_NUM, \ - .irq_prio = BSP_RTC_ALARM_IRQ_PRIO, \ - .int_src = INT_SRC_RTC_ALM, \ +#define RTC_ALARM_IRQ_CONFIG \ + { \ + .irq_num = BSP_RTC_ALARM_IRQ_NUM, \ + .irq_prio = BSP_RTC_ALARM_IRQ_PRIO, \ + .int_src = INT_SRC_RTC_ALM, \ } -static struct stc_hc32_alarm_irq hc32_alarm_irq = -{ - .irq_config = RTC_ALARM_IRQ_CONFIG, - .irq_callback = _rtc_alarm_irq_handler, +static struct stc_hc32_alarm_irq hc32_alarm_irq = { + .irq_config = RTC_ALARM_IRQ_CONFIG, + .irq_callback = _rtc_alarm_irq_handler, }; #endif -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void _bakup_reg_write(void) { uint8_t u8Num; @@ -112,10 +112,9 @@ static int32_t _hc32_rtc_rw_check(void) static rt_err_t _rtc_get_timeval(struct timeval *tv) { - - stc_rtc_time_t stcRtcTime = {0}; - stc_rtc_date_t stcRtcDate = {0}; - struct tm tm_new = {0}; + stc_rtc_time_t stcRtcTime = { 0 }; + stc_rtc_date_t stcRtcDate = { 0 }; + struct tm tm_new = { 0 }; if (LL_OK != RTC_GetTime(RTC_DATA_FMT_DEC, &stcRtcTime)) { @@ -126,11 +125,11 @@ static rt_err_t _rtc_get_timeval(struct timeval *tv) return -RT_ERROR; } - tm_new.tm_sec = stcRtcTime.u8Second; - tm_new.tm_min = stcRtcTime.u8Minute; + tm_new.tm_sec = stcRtcTime.u8Second; + tm_new.tm_min = stcRtcTime.u8Minute; tm_new.tm_hour = stcRtcTime.u8Hour; tm_new.tm_mday = stcRtcDate.u8Day; - tm_new.tm_mon = stcRtcDate.u8Month - 1; + tm_new.tm_mon = stcRtcDate.u8Month - 1; tm_new.tm_year = stcRtcDate.u8Year + 100; tv->tv_sec = timegm(&tm_new); @@ -140,9 +139,9 @@ static rt_err_t _rtc_get_timeval(struct timeval *tv) static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) { - stc_rtc_time_t stcRtcTime = {0}; - stc_rtc_date_t stcRtcDate = {0}; - struct tm tm_set = {0}; + stc_rtc_time_t stcRtcTime = { 0 }; + stc_rtc_date_t stcRtcDate = { 0 }; + struct tm tm_set = { 0 }; gmtime_r(&time_stamp, &tm_set); @@ -151,12 +150,12 @@ static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) return -RT_ERROR; } - stcRtcTime.u8Second = tm_set.tm_sec ; - stcRtcTime.u8Minute = tm_set.tm_min ; - stcRtcTime.u8Hour = tm_set.tm_hour; - stcRtcDate.u8Day = tm_set.tm_mday; - stcRtcDate.u8Month = tm_set.tm_mon + 1; - stcRtcDate.u8Year = tm_set.tm_year - 100; + stcRtcTime.u8Second = tm_set.tm_sec; + stcRtcTime.u8Minute = tm_set.tm_min; + stcRtcTime.u8Hour = tm_set.tm_hour; + stcRtcDate.u8Day = tm_set.tm_mday; + stcRtcDate.u8Month = tm_set.tm_mon + 1; + stcRtcDate.u8Year = tm_set.tm_year - 100; stcRtcDate.u8Weekday = tm_set.tm_wday; if (LL_OK != RTC_SetTime(RTC_DATA_FMT_DEC, &stcRtcTime)) @@ -172,30 +171,30 @@ static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) return RT_EOK; } -#if defined(HC32F4A0) || defined(HC32F460) - #if defined(BSP_RTC_USING_XTAL32) - #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) - #else - #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_LRC) - #endif +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F467) +#if defined(BSP_RTC_USING_XTAL32) +#define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) +#else +#define RTC_CLK_SRC_SEL (RTC_CLK_SRC_LRC) +#endif #elif defined(HC32F448) || defined(HC32F4A8) - #if defined(BSP_RTC_USING_XTAL32) - #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) - #elif defined(BSP_RTC_USING_XTAL_DIV) - #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL_DIV) - #else - #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_LRC) - #endif -#elif defined(HC32F472) || defined (HC32F334) - #if defined(BSP_RTC_USING_XTAL32) - #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) - #elif defined(BSP_RTC_USING_XTAL_DIV) - #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL_DIV) - #elif defined(BSP_RTC_USING_EXTCLK) - #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_EXTCLK) - #else - #define RTC_CLK_SRC_SEL (RTC_CLK_SRC_LRC) - #endif +#if defined(BSP_RTC_USING_XTAL32) +#define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) +#elif defined(BSP_RTC_USING_XTAL_DIV) +#define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL_DIV) +#else +#define RTC_CLK_SRC_SEL (RTC_CLK_SRC_LRC) +#endif +#elif defined(HC32F472) || defined(HC32F334) +#if defined(BSP_RTC_USING_XTAL32) +#define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL32) +#elif defined(BSP_RTC_USING_XTAL_DIV) +#define RTC_CLK_SRC_SEL (RTC_CLK_SRC_XTAL_DIV) +#elif defined(BSP_RTC_USING_EXTCLK) +#define RTC_CLK_SRC_SEL (RTC_CLK_SRC_EXTCLK) +#else +#define RTC_CLK_SRC_SEL (RTC_CLK_SRC_LRC) +#endif #endif #if defined(HC32F4A8) @@ -217,9 +216,9 @@ static rt_err_t _rtc_init(void) #if defined(HC32F4A8) if ((SET == VBAT_PowerDownCheck()) || (LL_OK != _bakup_reg_check()) || (LL_OK != _hc32_rtc_rw_check())) -#elif defined(HC32F4A0) +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) if ((LL_OK != _bakup_reg_check()) || (LL_OK != _hc32_rtc_rw_check())) -#elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) || defined (HC32F334) +#elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) || defined(HC32F334) if (DISABLE == RTC_GetCounterState()) #endif { @@ -246,7 +245,7 @@ static rt_err_t _rtc_init(void) /* Startup RTC count */ RTC_Cmd(ENABLE); -#if defined(HC32F4A0) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) /* Write sequence flag to backup register */ _bakup_reg_write(); #endif @@ -266,7 +265,7 @@ static rt_err_t _rtc_get_secs(time_t *sec) struct timeval tv; _rtc_get_timeval(&tv); - *(time_t *) sec = tv.tv_sec; + *(time_t *)sec = tv.tv_sec; LOG_D("RTC: get rtc_time %d", *sec); return RT_EOK; @@ -297,7 +296,7 @@ static void _rtc_alarm_irq_handler(void) rt_interrupt_leave(); } -#if defined(HC32F448) || defined(HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void RTC_Handler(void) { if (RTC_GetStatus(RTC_FLAG_ALARM) != RESET) @@ -332,8 +331,19 @@ static rt_err_t _rtc_get_alarm(struct rt_rtc_wkalarm *alarm) stc_rtc_alarm_t stcRtcAlarm; RTC_GetAlarm(RTC_DATA_FMT_DEC, &stcRtcAlarm); alarm->tm_hour = stcRtcAlarm.u8AlarmHour; - alarm->tm_min = stcRtcAlarm.u8AlarmMinute; - alarm->tm_sec = 0; /* alarms precision is 1 minute */ + alarm->tm_min = stcRtcAlarm.u8AlarmMinute; + alarm->tm_sec = 0; /* alarms precision is 1 minute */ +#ifdef RT_ALARM_USING_LOCAL_TIME + alarm->tm_hour += RT_LIBC_TZ_DEFAULT_HOUR; + if (alarm->tm_hour < 0) + { + alarm->tm_hour += 24; + } + else if (alarm->tm_hour > 23) + { + alarm->tm_hour -= 24; + } +#endif LOG_D("GET_ALARM %d:%d:%d", alarm->tm_hour, alarm->tm_min, alarm->tm_sec); return RT_EOK; @@ -354,10 +364,21 @@ static rt_err_t _rtc_set_alarm(struct rt_rtc_wkalarm *alarm) { RTC_AlarmCmd(DISABLE); /* Configuration alarm time: precision is 1 minute */ - stcRtcAlarm.u8AlarmHour = alarm->tm_hour; - stcRtcAlarm.u8AlarmMinute = alarm->tm_min; +#ifdef RT_ALARM_USING_LOCAL_TIME + alarm->tm_hour -= RT_LIBC_TZ_DEFAULT_HOUR; + if (alarm->tm_hour < 0) + { + alarm->tm_hour += 24; + } + else if (alarm->tm_hour > 23) + { + alarm->tm_hour -= 24; + } +#endif + stcRtcAlarm.u8AlarmHour = alarm->tm_hour; + stcRtcAlarm.u8AlarmMinute = alarm->tm_min; stcRtcAlarm.u8AlarmWeekday = RTC_ALARM_WEEKDAY_EVERYDAY; - stcRtcAlarm.u8AlarmAmPm = RTC_HOUR_24H; + stcRtcAlarm.u8AlarmAmPm = RTC_HOUR_24H; RTC_ClearStatus(RTC_FLAG_ALARM); (void)RTC_SetAlarm(RTC_DATA_FMT_DEC, &stcRtcAlarm); hc32_rtc_alarm_enable(); @@ -368,7 +389,6 @@ static rt_err_t _rtc_set_alarm(struct rt_rtc_wkalarm *alarm) { hc32_rtc_alarm_disable(); } - } else { @@ -382,8 +402,7 @@ static rt_err_t _rtc_set_alarm(struct rt_rtc_wkalarm *alarm) #endif } -const static struct rt_rtc_ops _ops = -{ +const static struct rt_rtc_ops _ops = { _rtc_init, _rtc_get_secs, _rtc_set_secs, diff --git a/bsp/hc32/libraries/hc32_drivers/drv_sdio.c b/bsp/hc32/libraries/hc32_drivers/drv_sdio.c index 85375e5832f..6bea7d2afbc 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_sdio.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_sdio.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2023-02-14 CDT first version + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ @@ -46,15 +48,15 @@ struct rthw_sdio #include #ifndef SDIO_BUFF_SIZE - #define SDIO_BUFF_SIZE (4096) +#define SDIO_BUFF_SIZE (4096) #endif #ifndef SDIO_ALIGN_LEN - #define SDIO_ALIGN_LEN (4) +#define SDIO_ALIGN_LEN (4) #endif #ifndef SDIO_MAX_FREQ - #define SDIO_MAX_FREQ (50*1000*1000) +#define SDIO_MAX_FREQ (50 * 1000 * 1000) #endif #define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&(_sdio)->mutex, RT_WAITING_FOREVER) @@ -69,11 +71,11 @@ extern rt_err_t rt_hw_board_sdio_init(CM_SDIOC_TypeDef *SDIOCx); * Local function prototypes ('static') ******************************************************************************/ #ifdef BSP_USING_SDIO1 - static void _sdio1_handler(void); +static void _sdio1_handler(void); #endif #ifdef BSP_USING_SDIO2 - static void _sdio2_handler(void); +static void _sdio2_handler(void); #endif /******************************************************************************* @@ -89,8 +91,7 @@ enum #endif }; -static struct hc32_sdio_config _sdio_config[] = -{ +static struct hc32_sdio_config _sdio_config[] = { #ifdef BSP_USING_SDIO1 SDIO1_BUS_CONFIG, #endif /* BSP_USING_SDIO1 */ @@ -99,8 +100,7 @@ static struct hc32_sdio_config _sdio_config[] = #endif /* BSP_USING_SDIO2 */ }; -static const func_ptr_t _sdio_irq_handler[] = -{ +static const func_ptr_t _sdio_irq_handler[] = { #ifdef BSP_USING_SDIO1 _sdio1_handler, #endif /* BSP_USING_SDIO1 */ @@ -110,17 +110,14 @@ static const func_ptr_t _sdio_irq_handler[] = }; #ifdef BSP_USING_SDIO1 - rt_align(SDIO_ALIGN_LEN) - static rt_uint8_t _sdio1_cache_buf[SDIO_BUFF_SIZE]; +rt_align(SDIO_ALIGN_LEN) static rt_uint8_t _sdio1_cache_buf[SDIO_BUFF_SIZE]; #endif #ifdef BSP_USING_SDIO2 - rt_align(SDIO_ALIGN_LEN) - static rt_uint8_t _sdio2_cache_buf[SDIO_BUFF_SIZE]; +rt_align(SDIO_ALIGN_LEN) static rt_uint8_t _sdio2_cache_buf[SDIO_BUFF_SIZE]; #endif -static rt_uint8_t *const _sdio_cache_buf[] = -{ +static rt_uint8_t * const _sdio_cache_buf[] = { #ifdef BSP_USING_SDIO1 _sdio1_cache_buf, #endif /* BSP_USING_SDIO1 */ @@ -129,7 +126,7 @@ static rt_uint8_t *const _sdio_cache_buf[] = #endif /* BSP_USING_SDIO2 */ }; -static struct rt_mmcsd_host *_sdio_host[sizeof(_sdio_config) / sizeof(_sdio_config[0])] = {0}; +static struct rt_mmcsd_host *_sdio_host[sizeof(_sdio_config) / sizeof(_sdio_config[0])] = { 0 }; /******************************************************************************* * Function implementation - global ('extern') and local ('static') @@ -210,9 +207,9 @@ static void _sdio_wait_completed(struct rthw_sdio *sdio) else if (resp_type(cmd) == RESP_R2) { LOG_D("R2"); - (void)SDIOC_GetResponse(instance, SDIOC_RESP_REG_BIT0_31, &response[0]); - (void)SDIOC_GetResponse(instance, SDIOC_RESP_REG_BIT32_63, &response[1]); - (void)SDIOC_GetResponse(instance, SDIOC_RESP_REG_BIT64_95, &response[2]); + (void)SDIOC_GetResponse(instance, SDIOC_RESP_REG_BIT0_31, &response[0]); + (void)SDIOC_GetResponse(instance, SDIOC_RESP_REG_BIT32_63, &response[1]); + (void)SDIOC_GetResponse(instance, SDIOC_RESP_REG_BIT64_95, &response[2]); (void)SDIOC_GetResponse(instance, SDIOC_RESP_REG_BIT96_127, &response[3]); cmd->resp[0] = (response[3] << 8) + ((response[2] >> 24) & 0xFF); @@ -235,7 +232,7 @@ static void _sdio_wait_completed(struct rthw_sdio *sdio) LOG_D("[%s cmd err] sta=0x%08X, %s%s%s%s cmd %d arg:0x%08X", __func__, status, - status & SDIOC_INT_FLAG_CCE ? "Command CRC Error " : "", + status & SDIOC_INT_FLAG_CCE ? "Command CRC Error " : "", status & SDIOC_INT_FLAG_CEBE ? "Command End Bit Error" : "", status & SDIOC_INT_FLAG_CTOE ? "Command Timeout Error" : "", status == 0 ? "NULL" : "", @@ -252,7 +249,7 @@ static void _sdio_wait_completed(struct rthw_sdio *sdio) LOG_D("[%s dat err] sta=0x%08X, %s%s%s%s cmd %d arg:0x%08X rw:%c len:%d blksize:%d", __func__, status, - status & SDIOC_INT_FLAG_DCE ? "Data CRC Error " : "", + status & SDIOC_INT_FLAG_DCE ? "Data CRC Error " : "", status & SDIOC_INT_FLAG_DEBE ? "Data End Bit Error" : "", status & SDIOC_INT_FLAG_DTOE ? "Data Timeout Error" : "", status == 0 ? "NULL" : "", @@ -284,21 +281,35 @@ static void _sdio_wait_completed(struct rthw_sdio *sdio) */ static void _sdio_transfer_by_dma(struct rthw_sdio *sdio, struct sdio_pkg *pkg) { - struct rt_mmcsd_data *data = pkg->cmd->data; + struct rt_mmcsd_data *data = NULL; + + if ((NULL == sdio) || (NULL == pkg)) + { + LOG_E("%s function arguments error: %s %s", + __func__, + (sdio == NULL ? "sdio is NULL" : ""), + (pkg == NULL ? "pkg is NULL" : "")); + return; + } - if ((NULL == sdio) || (NULL == pkg) || (NULL == pkg->buf) || (NULL == pkg->cmd) || (NULL == pkg->cmd->data)) + if ((NULL == pkg->buf) || (NULL == pkg->cmd)) { - LOG_E("%s function arguments error: %s %s %s %s %s", + LOG_E("%s function arguments error: %s %s", __func__, - (sdio == RT_NULL ? "sdio is NULL" : ""), - (pkg == RT_NULL ? "pkg is NULL" : ""), - (sdio ? (pkg->buf == RT_NULL ? "pkg->buf is NULL" : "") : ""), - (sdio ? (pkg->cmd == RT_NULL ? "pkg->cmd is NULL" : "") : ""), - (sdio ? (pkg->cmd->data == RT_NULL ? "pkg->cmd->data is NULL" : "") : "") - ); + (pkg->buf == NULL ? "pkg->buf is NULL" : ""), + (pkg->cmd == NULL ? "pkg->cmd is NULL" : "")); return; } + if ((NULL == pkg->cmd->data)) + { + LOG_E("%s function arguments error: %s", + __func__, + (pkg->cmd->data == NULL ? "pkg->cmd->data is NULL" : "")); + } + + data = pkg->cmd->data; + if (data->flags & DATA_DIR_WRITE) { sdio->des.txconfig(sdio->config->dma_tx.Instance, sdio->config->dma_tx.channel, pkg); @@ -352,7 +363,7 @@ static void _sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) stcCmdConfig.u32Argument = cmd->arg; /* config command type */ - stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdConfig.u16CmdType = SDIOC_CMD_TYPE_NORMAL; /* config response type */ stcCmdConfig.u16ResponseType = _sdio_get_cmd_resptype(resp_type(cmd)); @@ -360,12 +371,12 @@ static void _sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) if (data != RT_NULL) { /* config data */ - stcDataConfig.u16BlockSize = data->blksize; - stcDataConfig.u16BlockCount = data->blks; - stcDataConfig.u16TransDir = (data->flags & DATA_DIR_READ) ? SDIOC_TRANS_DIR_TO_HOST : SDIOC_TRANS_DIR_TO_CARD; - stcDataConfig.u16AutoCmd12 = SDIOC_AUTO_SEND_CMD12_DISABLE; + stcDataConfig.u16BlockSize = data->blksize; + stcDataConfig.u16BlockCount = data->blks; + stcDataConfig.u16TransDir = (data->flags & DATA_DIR_READ) ? SDIOC_TRANS_DIR_TO_HOST : SDIOC_TRANS_DIR_TO_CARD; + stcDataConfig.u16AutoCmd12 = SDIOC_AUTO_SEND_CMD12_DISABLE; stcDataConfig.u16DataTimeout = SDIOC_DATA_TIMEOUT_CLK_2E27; - stcDataConfig.u16TransMode = (data->blks > 1U) ? SDIOC_TRANS_MD_MULTI : SDIOC_TRANS_MD_SINGLE; + stcDataConfig.u16TransMode = (data->blks > 1U) ? SDIOC_TRANS_MD_MULTI : SDIOC_TRANS_MD_SINGLE; ret = SDIOC_ConfigData(instance, &stcDataConfig); if (ret != 0) { @@ -375,7 +386,8 @@ static void _sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg) /* transfer config */ _sdio_transfer_by_dma(sdio, pkg); - stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE;; + stcCmdConfig.u16DataLine = SDIOC_DATA_LINE_ENABLE; + ; } else { @@ -407,20 +419,26 @@ static void _sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) rt_uint32_t mask; struct sdio_pkg pkg; struct rt_mmcsd_data *data; - struct rthw_sdio *sdio = host->private_data; + struct rthw_sdio *sdio = NULL; - if ((NULL == host) || (NULL == req) || (NULL == sdio) || (NULL == sdio->config)) + if ((NULL == host) || (NULL == req)) { - LOG_E("%s function arguments error: %s %s %s %s", + LOG_E("%s function arguments error: %s %s %s", __func__, (host == RT_NULL ? "host is NULL" : ""), - (req == RT_NULL ? "req is NULL" : ""), - (sdio == RT_NULL ? "sdio is NULL" : ""), - (sdio ? (sdio->config == RT_NULL ? "sdio->config is NULL" : "") : "") - ); + (req == RT_NULL ? "req is NULL" : "")); + return; + } + if (NULL == host->private_data) + { + LOG_E("%s function arguments error: %s", + __func__, + (host->private_data == RT_NULL ? "host->private_data is NULL" : "")); return; } + sdio = host->private_data; + RTHW_SDIO_LOCK(sdio); if (req->cmd != RT_NULL) @@ -495,20 +513,25 @@ static void _sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_c rt_uint32_t clk; rt_uint16_t clk_div; rt_uint32_t clk_src; - struct rthw_sdio *sdio = host->private_data; + struct rthw_sdio *sdio = NULL; CM_SDIOC_TypeDef *instance; - if ((NULL == host) || (NULL == io_cfg) || (NULL == sdio) || (NULL == sdio->config)) + if ((NULL == host) || (NULL == io_cfg)) { LOG_E("%s function arguments error: %s %s %s %s", __func__, - (host == RT_NULL ? "host is NULL" : ""), - (io_cfg == RT_NULL ? "io_cfg is NULL" : ""), - (sdio == RT_NULL ? "sdio_des is NULL" : ""), - (sdio ? (sdio->config == RT_NULL ? "sdio->config is NULL" : "") : "") - ); + (host == RT_NULL ? "host is NULL" : ""), + (io_cfg == RT_NULL ? "io_cfg is NULL" : "")); return; } + if (NULL == host->private_data) + { + LOG_E("%s function arguments error: %s", + __func__, + (host->private_data == RT_NULL ? "host->private_data is NULL" : "")); + return; + } + sdio = host->private_data; instance = sdio->config->instance; @@ -667,8 +690,7 @@ static rt_int32_t _sdio_get_card_status(struct rt_mmcsd_host *host) return (rt_int32_t)SDIOC_GetHostStatus(sdio->config->instance, SDIOC_HOST_FLAG_CIN); } -static const struct rt_mmcsd_host_ops _mmcsd_host_ops = -{ +static const struct rt_mmcsd_host_ops _mmcsd_host_ops = { _sdio_request, _sdio_iocfg, _sdio_get_card_status, @@ -682,12 +704,12 @@ static const struct rt_mmcsd_host_ops _mmcsd_host_ops = */ static rt_uint32_t _sdio_clock_get(CM_SDIOC_TypeDef *SDIOCx) { - rt_uint32_t clk; + rt_uint32_t clk = 0UL; (void)SDIOCx; -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) clk = CLK_GetBusClockFreq(CLK_BUS_PCLK1); -#elif defined (HC32F460) +#elif defined(HC32F460) clk = CLK_GetBusClockFreq(CLK_BUS_EXCLK); #endif @@ -716,7 +738,7 @@ static void _sdio_dma_init(struct hc32_sdio_config *config) /* Configure DMA_RX Transfer */ stcDmaInit.u32SrcAddr = (uint32_t)(&config->instance->BUF0); stcDmaInit.u32DestAddr = 0UL; - stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_INC; if (LL_OK != DMA_Init(config->dma_rx.Instance, config->dma_rx.channel, &stcDmaInit)) { @@ -727,7 +749,7 @@ static void _sdio_dma_init(struct hc32_sdio_config *config) /* Configure DMA_TX Transfer */ stcDmaInit.u32SrcAddr = 0UL; stcDmaInit.u32DestAddr = (uint32_t)(&config->instance->BUF0); - stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC; + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_INC; stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX; if (LL_OK != DMA_Init(config->dma_tx.Instance, config->dma_tx.channel, &stcDmaInit)) { @@ -896,7 +918,7 @@ static rt_err_t _sdio_verify_bus_clock_frequency(struct hc32_sdio_config *config { rt_err_t ret = RT_EOK; -#if defined (HC32F4A0) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) rt_uint32_t pclk1; rt_uint32_t exlck; @@ -941,22 +963,21 @@ static rt_err_t _sdio_clock_enable(struct hc32_sdio_config *config) * @retval rt_mmcsd_host */ static struct rt_mmcsd_host *_sdio_host_create(struct hc32_sdio_config *config, - uint8_t *cache_buf, - const struct hc32_sdio_des *sdio_des) + uint8_t *cache_buf, + const struct hc32_sdio_des *sdio_des) { struct rt_mmcsd_host *host; struct rthw_sdio *sdio = RT_NULL; - if ((config == RT_NULL) || (cache_buf == RT_NULL) || \ - (sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL)) + if ((config == RT_NULL) || (cache_buf == RT_NULL) || + (sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL)) { LOG_E("function arguments error: %s %s %s %s %s", (config == RT_NULL ? "config is NULL" : ""), (cache_buf == RT_NULL ? "cache_buf is NULL" : ""), (sdio_des == RT_NULL ? "sdio_des is NULL" : ""), (sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""), - (sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "") - ); + (sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "")); return RT_NULL; } @@ -1019,9 +1040,8 @@ int rt_hw_sdio_init(void) struct hc32_sdio_config *sdio_config; rt_size_t obj_num = sizeof(_sdio_config) / sizeof(struct hc32_sdio_config); - const struct hc32_sdio_des sdio_des = - { - .clk_get = _sdio_clock_get, + const struct hc32_sdio_des sdio_des = { + .clk_get = _sdio_clock_get, .rxconfig = _sdio_dma_rxconfig, .txconfig = _sdio_dma_txconfig, }; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_sdio.h b/bsp/hc32/libraries/hc32_drivers/drv_sdio.h index 8d5589e7498..dc13829fe6e 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_sdio.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_sdio.h @@ -43,7 +43,7 @@ typedef rt_uint32_t (*sdio_clk_get)(CM_SDIOC_TypeDef *sdio_instance); /* hc32 sdio des */ struct hc32_sdio_des { - sdio_clk_get clk_get; + sdio_clk_get clk_get; sdio_txconfig txconfig; sdio_rxconfig rxconfig; }; @@ -51,12 +51,12 @@ struct hc32_sdio_des /* hc32 sdio configure */ struct hc32_sdio_config { - const char *name; - CM_SDIOC_TypeDef *instance; - rt_uint32_t clock; + const char *name; + CM_SDIOC_TypeDef *instance; + rt_uint32_t clock; struct hc32_irq_config irq_config; - struct dma_config dma_rx; - struct dma_config dma_tx; + struct dma_config dma_rx; + struct dma_config dma_tx; }; /******************************************************************************* diff --git a/bsp/hc32/libraries/hc32_drivers/drv_sdram.c b/bsp/hc32/libraries/hc32_drivers/drv_sdram.c index 06be7642b93..0076f273f72 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_sdram.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_sdram.c @@ -9,6 +9,8 @@ * 2024-02-20 CDT modify exclk clock max frequency to 40MHz for HC32F4A0 * add t_rcd_p/t_rfc_p/t_rp_p configuration * 2024-12-24 CDT modify sample clock to EXMC_DMC_SAMPLE_CLK_EXTCLK for HC32F4A0 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-05 CDT support HC32F467 */ @@ -39,8 +41,8 @@ /******************************************************************************* * Global variable definitions (declared in header file with 'extern') ******************************************************************************/ -#if defined (BSP_USING_SDRAM) - rt_err_t rt_hw_board_sdram_init(void); +#if defined(BSP_USING_SDRAM) +rt_err_t rt_hw_board_sdram_init(void); #endif /******************************************************************************* @@ -51,7 +53,7 @@ * Local variable definitions ('static') ******************************************************************************/ #ifdef RT_USING_MEMHEAP_AS_HEAP - static struct rt_memheap _system_heap; +static struct rt_memheap _system_heap; #endif /******************************************************************************* @@ -84,7 +86,7 @@ static rt_int32_t _sdram_verify_clock_frequency(void) { rt_int32_t ret = RT_EOK; -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) /* EXCLK max frequency for SDRAM */ if (CLK_GetBusClockFreq(CLK_BUS_EXCLK) > EXMC_EXCLK_DMC_MAX_FREQ) { @@ -124,36 +126,36 @@ static rt_int32_t _sdram_init(void) /* configure DMC width && refresh period & chip & timing. */ (void)EXMC_DMC_StructInit(&stcDmcInit); -#if defined (HC32F4A0) - stcDmcInit.u32SampleClock = EXMC_DMC_SAMPLE_CLK_EXTCLK; +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) + stcDmcInit.u32SampleClock = EXMC_DMC_SAMPLE_CLK_EXTCLK; #endif - stcDmcInit.u32RefreshPeriod = SDRAM_REFRESH_COUNT; - stcDmcInit.u32ColumnBitsNumber = SDRAM_COLUMN_BITS; - stcDmcInit.u32RowBitsNumber = SDRAM_ROW_BITS; - stcDmcInit.u32MemBurst = SDRAM_BURST_LENGTH; - stcDmcInit.u32AutoRefreshChips = EXMC_DMC_AUTO_REFRESH_4CHIPS; - stcDmcInit.stcTimingConfig.u8CASL = SDRAM_CAS_LATENCY; - stcDmcInit.stcTimingConfig.u8DQSS = 0U; - stcDmcInit.stcTimingConfig.u8MRD = SDRAM_TMDR; - stcDmcInit.stcTimingConfig.u8RAS = SDRAM_TRAS; - stcDmcInit.stcTimingConfig.u8RC = SDRAM_TRC; + stcDmcInit.u32RefreshPeriod = SDRAM_REFRESH_COUNT; + stcDmcInit.u32ColumnBitsNumber = SDRAM_COLUMN_BITS; + stcDmcInit.u32RowBitsNumber = SDRAM_ROW_BITS; + stcDmcInit.u32MemBurst = SDRAM_BURST_LENGTH; + stcDmcInit.u32AutoRefreshChips = EXMC_DMC_AUTO_REFRESH_4CHIPS; + stcDmcInit.stcTimingConfig.u8CASL = SDRAM_CAS_LATENCY; + stcDmcInit.stcTimingConfig.u8DQSS = 0U; + stcDmcInit.stcTimingConfig.u8MRD = SDRAM_TMDR; + stcDmcInit.stcTimingConfig.u8RAS = SDRAM_TRAS; + stcDmcInit.stcTimingConfig.u8RC = SDRAM_TRC; stcDmcInit.stcTimingConfig.u8RCD_B = SDRAM_TRCD_B; stcDmcInit.stcTimingConfig.u8RCD_P = SDRAM_TRCD_P; stcDmcInit.stcTimingConfig.u8RFC_B = SDRAM_TRFC_B; stcDmcInit.stcTimingConfig.u8RFC_P = SDRAM_TRFC_P; - stcDmcInit.stcTimingConfig.u8RP_B = SDRAM_TRP_B; - stcDmcInit.stcTimingConfig.u8RP_P = SDRAM_TRP_P; - stcDmcInit.stcTimingConfig.u8RRD = SDRAM_TRRD; - stcDmcInit.stcTimingConfig.u8WR = SDRAM_TWR; - stcDmcInit.stcTimingConfig.u8WTR = SDRAM_TWTR; - stcDmcInit.stcTimingConfig.u8XP = SDRAM_TXP; - stcDmcInit.stcTimingConfig.u8XSR = SDRAM_TXSR; - stcDmcInit.stcTimingConfig.u8ESR = SDRAM_TESR; + stcDmcInit.stcTimingConfig.u8RP_B = SDRAM_TRP_B; + stcDmcInit.stcTimingConfig.u8RP_P = SDRAM_TRP_P; + stcDmcInit.stcTimingConfig.u8RRD = SDRAM_TRRD; + stcDmcInit.stcTimingConfig.u8WR = SDRAM_TWR; + stcDmcInit.stcTimingConfig.u8WTR = SDRAM_TWTR; + stcDmcInit.stcTimingConfig.u8XP = SDRAM_TXP; + stcDmcInit.stcTimingConfig.u8XSR = SDRAM_TXSR; + stcDmcInit.stcTimingConfig.u8ESR = SDRAM_TESR; (void)EXMC_DMC_Init(&stcDmcInit); /* configure DMC address space. */ - stcCsConfig.u32AddrMatch = (SDRAM_BANK_ADDR >> 24); - stcCsConfig.u32AddrMask = EXMC_DMC_ADDR_MASK_128MB; + stcCsConfig.u32AddrMatch = (SDRAM_BANK_ADDR >> 24); + stcCsConfig.u32AddrMask = EXMC_DMC_ADDR_MASK_128MB; stcCsConfig.u32AddrDecodeMode = EXMC_DMC_CS_DECODE_ROWBANKCOL; (void)EXMC_DMC_ChipConfig(SDRAM_CHIP, &stcCsConfig); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_sdram.h b/bsp/hc32/libraries/hc32_drivers/drv_sdram.h index 5afd35dab88..debdd83222c 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_sdram.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_sdram.h @@ -27,10 +27,10 @@ extern "C" { /******************************************************************************* * Global pre-processor symbols/macros ('#define') ******************************************************************************/ -#if defined (HC32F4A0) -#define EXMC_EXCLK_DMC_MAX_FREQ (40UL * 1000000UL) -#elif defined (HC32F4A8) -#define EXMC_EXCLK_DMC_MAX_FREQ (120UL * 1000000UL) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) +#define EXMC_EXCLK_DMC_MAX_FREQ (40UL * 1000000UL) +#elif defined(HC32F4A8) +#define EXMC_EXCLK_DMC_MAX_FREQ (120UL * 1000000UL) #endif /******************************************************************************* diff --git a/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.c b/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.c index cbf6c76b9bb..1472b36c466 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.c @@ -27,7 +27,7 @@ * Local pre-processor symbols/macros ('#define') ******************************************************************************/ //#define DRV_DEBUG -#define LOG_TAG "drv.i2c" +#define LOG_TAG "drv.i2c" #include /******************************************************************************* @@ -42,8 +42,7 @@ * Local variable definitions ('static') ******************************************************************************/ -static const struct hc32_soft_i2c_config soft_i2c_config[] = -{ +static const struct hc32_soft_i2c_config soft_i2c_config[] = { #ifdef BSP_USING_I2C1_SW I2C1_BUS_CONFIG, #endif @@ -78,10 +77,10 @@ static void hc32_i2c_gpio_init(struct hc32_soft_i2c *i2c) { struct hc32_soft_i2c_config *cfg = (struct hc32_soft_i2c_config *)i2c->ops.data; - rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT_OD); - rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT_OD); - rt_pin_write(cfg->scl_pin, PIN_HIGH); - rt_pin_write(cfg->sda_pin, PIN_HIGH); + rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT_OD); + rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT_OD); + rt_pin_write(cfg->scl_pin, PIN_HIGH); + rt_pin_write(cfg->sda_pin, PIN_HIGH); } static void hc32_i2c_pin_init(void) @@ -191,17 +190,16 @@ static void hc32_udelay(rt_uint32_t us) } } -static const struct rt_i2c_bit_ops hc32_bit_ops_default = -{ - .data = RT_NULL, +static const struct rt_i2c_bit_ops hc32_bit_ops_default = { + .data = RT_NULL, .pin_init = hc32_i2c_pin_init, - .set_sda = hc32_set_sda, - .set_scl = hc32_set_scl, - .get_sda = hc32_get_sda, - .get_scl = hc32_get_scl, - .udelay = hc32_udelay, + .set_sda = hc32_set_sda, + .set_scl = hc32_set_scl, + .get_sda = hc32_get_sda, + .get_scl = hc32_get_scl, + .udelay = hc32_udelay, .delay_us = 1, - .timeout = 100, + .timeout = 100, .i2c_pin_init_flag = RT_FALSE }; @@ -242,8 +240,8 @@ int hc32_soft_i2c_init(void) for (rt_size_t i = 0; i < obj_num; i++) { - i2c_obj[i].ops = hc32_bit_ops_default; - i2c_obj[i].ops.data = (void *)&soft_i2c_config[i]; + i2c_obj[i].ops = hc32_bit_ops_default; + i2c_obj[i].ops.data = (void *)&soft_i2c_config[i]; i2c_obj[i].i2c_bus.priv = &i2c_obj[i].ops; result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c_bus, soft_i2c_config[i].bus_name); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.h b/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.h index a16b9d0d37f..52abc577642 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_soft_i2c.h @@ -18,8 +18,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -29,66 +28,66 @@ struct hc32_soft_i2c_config { rt_uint16_t scl_pin; rt_uint16_t sda_pin; - const char *bus_name; + const char *bus_name; }; struct hc32_soft_i2c { - struct rt_i2c_bit_ops ops; + struct rt_i2c_bit_ops ops; struct rt_i2c_bus_device i2c_bus; }; #ifdef BSP_USING_I2C1_SW -#define I2C1_BUS_CONFIG \ - { \ - .scl_pin = BSP_I2C1_SCL_PIN, \ - .sda_pin = BSP_I2C1_SDA_PIN, \ - .bus_name = "i2c1_sw", \ +#define I2C1_BUS_CONFIG \ + { \ + .scl_pin = BSP_I2C1_SCL_PIN, \ + .sda_pin = BSP_I2C1_SDA_PIN, \ + .bus_name = "i2c1_sw", \ } #endif #ifdef BSP_USING_I2C2_SW -#define I2C2_BUS_CONFIG \ - { \ - .scl_pin = BSP_I2C2_SCL_PIN, \ - .sda_pin = BSP_I2C2_SDA_PIN, \ - .bus_name = "i2c2_sw", \ +#define I2C2_BUS_CONFIG \ + { \ + .scl_pin = BSP_I2C2_SCL_PIN, \ + .sda_pin = BSP_I2C2_SDA_PIN, \ + .bus_name = "i2c2_sw", \ } #endif #ifdef BSP_USING_I2C3_SW -#define I2C3_BUS_CONFIG \ - { \ - .scl_pin = BSP_I2C3_SCL_PIN, \ - .sda_pin = BSP_I2C3_SDA_PIN, \ - .bus_name = "i2c3_sw", \ +#define I2C3_BUS_CONFIG \ + { \ + .scl_pin = BSP_I2C3_SCL_PIN, \ + .sda_pin = BSP_I2C3_SDA_PIN, \ + .bus_name = "i2c3_sw", \ } #endif #ifdef BSP_USING_I2C4_SW -#define I2C4_BUS_CONFIG \ - { \ - .scl_pin = BSP_I2C4_SCL_PIN, \ - .sda_pin = BSP_I2C4_SDA_PIN, \ - .bus_name = "i2c4_sw", \ +#define I2C4_BUS_CONFIG \ + { \ + .scl_pin = BSP_I2C4_SCL_PIN, \ + .sda_pin = BSP_I2C4_SDA_PIN, \ + .bus_name = "i2c4_sw", \ } #endif #ifdef BSP_USING_I2C5_SW -#define I2C5_BUS_CONFIG \ - { \ - .scl_pin = BSP_I2C5_SCL_PIN, \ - .sda_pin = BSP_I2C5_SDA_PIN, \ - .bus_name = "i2c5_sw", \ +#define I2C5_BUS_CONFIG \ + { \ + .scl_pin = BSP_I2C5_SCL_PIN, \ + .sda_pin = BSP_I2C5_SDA_PIN, \ + .bus_name = "i2c5_sw", \ } #endif #ifdef BSP_USING_I2C6_SW -#define I2C6_BUS_CONFIG \ - { \ - .scl_pin = BSP_I2C6_SCL_PIN, \ - .sda_pin = BSP_I2C6_SDA_PIN, \ - .bus_name = "i2c6_sw", \ +#define I2C6_BUS_CONFIG \ + { \ + .scl_pin = BSP_I2C6_SCL_PIN, \ + .sda_pin = BSP_I2C6_SDA_PIN, \ + .bus_name = "i2c6_sw", \ } #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_spi.c b/bsp/hc32/libraries/hc32_drivers/drv_spi.c index 2e4209106d4..e52144702cd 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_spi.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_spi.c @@ -11,6 +11,9 @@ * 2024-04-16 CDT Support HC32F472 * 2025-04-09 CDT Support HC32F4A8 * 2025-07-18 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-04 CDT Support HC32F467 + * 2026-07-10 CDT Fix SPI clock division value configuration */ /******************************************************************************* @@ -35,18 +38,16 @@ * Local pre-processor symbols/macros ('#define') ******************************************************************************/ // #define DRV_DEBUG -#define LOG_TAG "drv.spi" +#define LOG_TAG "drv.spi" #include /* SPI max division */ -#if defined(HC32F4A0) || defined(HC32F460) - #define SPI_MAX_DIV_VAL (0x7U) /* Div256 */ -#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) - #define SPI_MAX_DIV_VAL (0x39U) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F467) +#define SPI_MAX_DIV_CFG_VAL (0x7U) /* Div256 */ #endif #ifdef BSP_SPI_USING_DMA - #define DMA_CH_REG(reg_base, ch) (*(__IO uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) +#define DMA_CH_REG(reg_base, ch) (*(__IO uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) #endif /******************************************************************************* @@ -83,8 +84,7 @@ enum #endif }; -static struct hc32_spi_config spi_config[] = -{ +static struct hc32_spi_config spi_config[] = { #ifdef BSP_USING_SPI1 SPI1_BUS_CONFIG, #endif @@ -105,7 +105,7 @@ static struct hc32_spi_config spi_config[] = #endif }; -static struct hc32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; +static struct hc32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = { 0 }; /******************************************************************************* * Function implementation - global ('extern') and local ('static') @@ -126,7 +126,7 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat SPI_StructInit(&stcSpiInit); if ((cfg->mode & RT_SPI_SLAVE) && - ((RT_SPI_MODE_0 == (cfg->mode & RT_SPI_MODE_3)) || (RT_SPI_MODE_2 == (cfg->mode & RT_SPI_MODE_3)))) + ((RT_SPI_MODE_0 == (cfg->mode & RT_SPI_MODE_3)) || (RT_SPI_MODE_2 == (cfg->mode & RT_SPI_MODE_3)))) { return -RT_EINVAL; } @@ -203,24 +203,57 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat } /* Get BUS clock */ u32BusFreq = CLK_GetBusClockFreq(CLK_BUS_PCLK1); +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F467) while (cfg->max_hz < u32BusFreq / (1UL << (u32Cnt + 1U))) { u32Cnt++; - if (u32Cnt >= SPI_MAX_DIV_VAL) /* Div256 */ + if (u32Cnt >= SPI_MAX_DIV_CFG_VAL) /* Div256 */ { break; } } -#if defined(HC32F4A0) || defined(HC32F460) stcSpiInit.u32BaudRatePrescaler = (u32Cnt << SPI_CFG2_MBR_POS); -#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined (HC32F334) - if (u32Cnt <= 15U) - { - stcSpiInit.u32BaudRatePrescaler = (u32Cnt << SPI_CFG1_CLKDIV_POS); - } - else - { - stcSpiInit.u32BaudRatePrescaler = (((7U + ((u32Cnt - 15U) & 0x07U)) << SPI_CFG1_CLKDIV_POS) | ((1U + ((u32Cnt - 15U) >> 3U)) << SPI_CFG2_MBR_POS)); +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined(HC32F334) + u32Cnt = 2UL; + rt_uint32_t u32DIVArray[] = { SPI_BR_CLK_DIV2, SPI_BR_CLK_DIV4, SPI_BR_CLK_DIV6, + SPI_BR_CLK_DIV8, SPI_BR_CLK_DIV10, SPI_BR_CLK_DIV12, + SPI_BR_CLK_DIV14, SPI_BR_CLK_DIV16, SPI_BR_CLK_DIV18, + SPI_BR_CLK_DIV20, SPI_BR_CLK_DIV22, SPI_BR_CLK_DIV24, + SPI_BR_CLK_DIV26, SPI_BR_CLK_DIV28, SPI_BR_CLK_DIV30, + SPI_BR_CLK_DIV32, SPI_BR_CLK_DIV36, SPI_BR_CLK_DIV40, + SPI_BR_CLK_DIV44, SPI_BR_CLK_DIV48, SPI_BR_CLK_DIV52, + SPI_BR_CLK_DIV56, SPI_BR_CLK_DIV60, SPI_BR_CLK_DIV64, + SPI_BR_CLK_DIV72, SPI_BR_CLK_DIV80, SPI_BR_CLK_DIV88, + SPI_BR_CLK_DIV96, SPI_BR_CLK_DIV104, SPI_BR_CLK_DIV112, + SPI_BR_CLK_DIV120, SPI_BR_CLK_DIV128, SPI_BR_CLK_DIV144, + SPI_BR_CLK_DIV160, SPI_BR_CLK_DIV176, SPI_BR_CLK_DIV192, + SPI_BR_CLK_DIV208, SPI_BR_CLK_DIV224, SPI_BR_CLK_DIV240, + SPI_BR_CLK_DIV256 }; + rt_uint32_t *u32DIVArrayPtr = u32DIVArray; + stcSpiInit.u32BaudRatePrescaler = *u32DIVArrayPtr; + while (cfg->max_hz < u32BusFreq / u32Cnt) + { + if (u32Cnt < 32UL) + { + u32Cnt += 2UL; + } + else if (u32Cnt < 64UL) + { + u32Cnt += 4UL; + } + else if (u32Cnt < 128UL) + { + u32Cnt += 8UL; + } + else if (u32Cnt < 256UL) + { + u32Cnt += 16UL; + } + else + { + break; + } + stcSpiInit.u32BaudRatePrescaler = *++u32DIVArrayPtr; } #endif /* slave limit */ @@ -242,7 +275,7 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX) { struct dma_config *spi_dma; - stc_dma_init_t stcDmaInit; + stc_dma_init_t stcDmaInit; /* Get spi dma_rx */ spi_dma = spi_drv->config->dma_rx; @@ -251,9 +284,9 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat AOS_SetTriggerEventSrc(spi_dma->trigger_select, spi_dma->trigger_event); /* Config Dma */ DMA_StructInit(&stcDmaInit); - stcDmaInit.u32BlockSize = 1UL; - stcDmaInit.u32SrcAddr = (uint32_t)(&spi_instance->DR); - stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; + stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32SrcAddr = (uint32_t)(&spi_instance->DR); + stcDmaInit.u32SrcAddrInc = DMA_SRC_ADDR_FIX; if (8 == cfg->data_width) { stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; @@ -277,7 +310,7 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) { struct dma_config *spi_dma; - stc_dma_init_t stcDmaInit; + stc_dma_init_t stcDmaInit; /* Get spi dma_tx */ spi_dma = spi_drv->config->dma_tx; @@ -285,9 +318,10 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat AOS_SetTriggerEventSrc(spi_dma->trigger_select, spi_dma->trigger_event); /* Config Dma */ DMA_StructInit(&stcDmaInit); - stcDmaInit.u32BlockSize = 1UL; - stcDmaInit.u32DestAddr = (uint32_t)(&spi_instance->DR);; - stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX; + stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32DestAddr = (uint32_t)(&spi_instance->DR); + ; + stcDmaInit.u32DestAddrInc = DMA_DEST_ADDR_FIX; if (8 == cfg->data_width) { stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; @@ -311,7 +345,7 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat #endif /* Enable error interrupt */ -#if defined (HC32F448) || defined (HC32F472) +#if defined(HC32F448) || defined(HC32F472) INTC_IntSrcCmd(spi_drv->config->err_irq.irq_config.int_src, ENABLE); #endif NVIC_EnableIRQ(spi_drv->config->err_irq.irq_config.irq_num); @@ -324,12 +358,12 @@ static rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configurat static void hc32_spi_enable(CM_SPI_TypeDef *SPIx) { /* Check if the SPI is already enabled */ -#if defined (HC32F460) || defined (HC32F4A0) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) if ((SPIx->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) { SPI_Cmd(SPIx, ENABLE); } -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined(HC32F334) if ((SPIx->CR & SPI_CR_SPE) != SPI_CR_SPE) { SPI_Cmd(SPIx, ENABLE); @@ -341,7 +375,7 @@ static void hc32_spi_enable(CM_SPI_TypeDef *SPIx) static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) { -#if defined (HC32F460) || defined (HC32F4A0) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) if (SPI_SEND_ONLY == u32Mode) { SET_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); @@ -350,7 +384,7 @@ static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) { CLR_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); } -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined(HC32F334) if (SPI_SEND_ONLY == u32Mode) { SET_REG32_BIT(SPIx->CR, SPI_CR_TXMDS); @@ -367,9 +401,9 @@ static void hc32_spi_set_trans_mode(CM_SPI_TypeDef *SPIx, uint32_t u32Mode) #ifdef BSP_SPI_USING_DMA static uint32_t hc32_spi_get_trans_mode(CM_SPI_TypeDef *SPIx) { -#if defined (HC32F460) || defined (HC32F4A0) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) return READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || defined(HC32F334) return READ_REG32_BIT(SPIx->CR, SPI_CR_TXMDS); #else #error "Please select first the target HC32xxxx device used in your application." @@ -413,7 +447,7 @@ static rt_err_t hc32_spi_configure(struct rt_spi_device *device, RT_ASSERT(device != RT_NULL); RT_ASSERT(configuration != RT_NULL); - struct hc32_spi *spi_drv = rt_container_of(device->bus, struct hc32_spi, spi_bus); + struct hc32_spi *spi_drv = rt_container_of(device->bus, struct hc32_spi, spi_bus); spi_drv->cfg = configuration; return hc32_spi_init(spi_drv, configuration); @@ -488,7 +522,7 @@ static int32_t hc32_spi_dma_trans(struct hc32_spi_config *spi_config, const uint DmaFlag = spi_config->dma_tx->flag; } while ((RESET == DMA_GetTransCompleteStatus(DmaInstance, DmaFlag)) && - (u32TimeoutCnt < spi_config->timeout)) + (u32TimeoutCnt < spi_config->timeout)) { rt_thread_mdelay(1); u32TimeoutCnt++; @@ -515,7 +549,7 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(message != RT_NULL); - struct hc32_spi *spi_drv = rt_container_of(device->bus, struct hc32_spi, spi_bus); + struct hc32_spi *spi_drv = rt_container_of(device->bus, struct hc32_spi, spi_bus); CM_SPI_TypeDef *spi_instance = spi_drv->config->Instance; if (message->cs_take && !(device->config.mode & RT_SPI_NO_CS) && (device->cs_pin != PIN_NONE)) @@ -530,20 +564,20 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess LOG_D("%s sendbuf: %X, recvbuf: %X, length: %d", spi_drv->config->bus_name, (uint32_t)message->send_buf, (uint32_t)message->recv_buf, message->length); - message_length = message->length; - recv_buf = message->recv_buf; - send_buf = message->send_buf; + message_length = message->length; + recv_buf = message->recv_buf; + send_buf = message->send_buf; while (message_length) { if (message_length > 65535) { - send_length = 65535; - message_length = message_length - 65535; + send_length = 65535; + message_length = message_length - 65535; } else { - send_length = message_length; - message_length = 0; + send_length = message_length; + message_length = 0; } /* calculate the start address */ @@ -616,7 +650,7 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess { u32TimeoutCnt = 0U; while ((RESET == SPI_GetStatus(spi_instance, SPI_FLAG_IDLE)) && - (u32TimeoutCnt < spi_drv->config->timeout)) + (u32TimeoutCnt < spi_drv->config->timeout)) { rt_thread_mdelay(1); u32TimeoutCnt++; @@ -645,10 +679,9 @@ static rt_ssize_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_mess return message->length; } -static const struct rt_spi_ops hc32_spi_ops = -{ - .configure = hc32_spi_configure, - .xfer = hc32_spi_xfer, +static const struct rt_spi_ops hc32_spi_ops = { + .configure = hc32_spi_configure, + .xfer = hc32_spi_xfer, }; /** @@ -710,12 +743,12 @@ static void hc32_spi1_err_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F448) ||defined (HC32F472) +#if defined(HC32F448) || defined(HC32F472) void SPI1_Handler(void) { hc32_spi1_err_irq_handler(); } -#elif defined (HC32F334) +#elif defined(HC32F334) void SPI_Handler(void) { hc32_spi1_err_irq_handler(); @@ -733,7 +766,7 @@ static void hc32_spi2_err_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F448) ||defined (HC32F472) +#if defined(HC32F448) || defined(HC32F472) void SPI2_Handler(void) { hc32_spi2_err_irq_handler(); @@ -751,7 +784,7 @@ static void hc32_spi3_err_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F448) ||defined (HC32F472) +#if defined(HC32F448) || defined(HC32F472) void SPI3_Handler(void) { hc32_spi3_err_irq_handler(); @@ -769,7 +802,7 @@ static void hc32_spi4_err_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F472) +#if defined(HC32F472) void SPI4_Handler(void) { hc32_spi4_err_irq_handler(); @@ -829,7 +862,7 @@ static void hc32_get_spi_callback(void) } /** - * @brief This function gets dma witch spi used infomation include unit, + * @brief This function gets dma witch spi used information include unit, * channel, interrupt etc. * @param None * @retval None @@ -839,67 +872,67 @@ static void hc32_get_dma_info(void) #ifdef BSP_SPI1_RX_USING_DMA spi_bus_obj[SPI1_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG; - spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx; + spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx; #endif #ifdef BSP_SPI1_TX_USING_DMA spi_bus_obj[SPI1_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG; - spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx; + spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx; #endif #ifdef BSP_SPI2_RX_USING_DMA spi_bus_obj[SPI2_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG; - spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx; + spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx; #endif #ifdef BSP_SPI2_TX_USING_DMA spi_bus_obj[SPI2_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG; - spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx; + spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx; #endif #ifdef BSP_SPI3_RX_USING_DMA spi_bus_obj[SPI3_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG; - spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx; + spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx; #endif #ifdef BSP_SPI3_TX_USING_DMA spi_bus_obj[SPI3_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG; - spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx; + spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx; #endif #ifdef BSP_SPI4_RX_USING_DMA spi_bus_obj[SPI4_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG; - spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx; + spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx; #endif #ifdef BSP_SPI4_TX_USING_DMA spi_bus_obj[SPI4_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG; - spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx; + spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx; #endif #ifdef BSP_SPI5_RX_USING_DMA spi_bus_obj[SPI5_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG; - spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx; + spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx; #endif #ifdef BSP_SPI5_TX_USING_DMA spi_bus_obj[SPI5_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG; - spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx; + spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx; #endif #ifdef BSP_SPI6_RX_USING_DMA spi_bus_obj[SPI6_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG; - spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx; + spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx; #endif #ifdef BSP_SPI6_TX_USING_DMA spi_bus_obj[SPI6_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG; - spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx; + spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx; #endif } @@ -913,9 +946,9 @@ static int hc32_hw_spi_bus_init(void) spi_bus_obj[i].config = &spi_config[i]; spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; /* register the handle */ -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) hc32_install_irq_handler(&spi_config[i].err_irq.irq_config, spi_config[i].err_irq.irq_callback, RT_FALSE); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) INTC_IntSrcCmd(spi_config[i].err_irq.irq_config.int_src, DISABLE); NVIC_DisableIRQ(spi_config[i].err_irq.irq_config.irq_num); #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_spi.h b/bsp/hc32/libraries/hc32_drivers/drv_spi.h index 5ac5ade8cdf..3db6b03b44e 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_spi.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_spi.h @@ -27,28 +27,28 @@ extern "C" { struct hc32_spi_irq_config { struct hc32_irq_config irq_config; - func_ptr_t irq_callback; + func_ptr_t irq_callback; }; struct hc32_spi_config { - CM_SPI_TypeDef *Instance; - char *bus_name; - rt_uint32_t clock; - rt_uint32_t timeout; - struct hc32_spi_irq_config err_irq; + CM_SPI_TypeDef *Instance; + char *bus_name; + rt_uint32_t clock; + rt_uint32_t timeout; + struct hc32_spi_irq_config err_irq; #ifdef BSP_SPI_USING_DMA - struct dma_config *dma_rx; - struct dma_config *dma_tx; + struct dma_config *dma_rx; + struct dma_config *dma_tx; #endif }; struct hc32_spi { - struct hc32_spi_config *config; + struct hc32_spi_config *config; struct rt_spi_configuration *cfg; - struct rt_spi_bus spi_bus; - rt_uint16_t spi_dma_flag; + struct rt_spi_bus spi_bus; + rt_uint16_t spi_dma_flag; }; rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_base_t cs_pin); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_timer.c b/bsp/hc32/libraries/hc32_drivers/drv_timer.c index 2db13325c70..bb78a3882c9 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_timer.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_timer.c @@ -8,13 +8,15 @@ * 2023-06-21 CDT first version * 2024-02-20 CDT support HC32F448 * 2024-06-17 CDT support HC32F472 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ #include #include "drv_config.h" // #define DRV_DEBUG -#define LOG_TAG "drv.clock_timer" +#define LOG_TAG "drv.clock_timer" #include #ifdef BSP_USING_CLOCK_TIMER @@ -73,15 +75,14 @@ struct hc32_clock_timer en_int_src_t enIntSrc; IRQn_Type enIRQn; rt_uint8_t u8Int_Prio; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) func_ptr_t irq_callback; #endif } isr; char *name; }; -static struct hc32_clock_timer hc32_clock_timer_obj[] = -{ +static struct hc32_clock_timer hc32_clock_timer_obj[] = { #ifdef BSP_USING_TMRA_1 TMRA_1_CONFIG, #endif @@ -144,22 +145,22 @@ static void _timer_init(struct rt_clock_timer_device *timer, rt_uint32_t state) /* TIMERA configuration */ (void)TMRA_StructInit(&stcTmraInit); stcTmraInit.sw_count.u8ClockDiv = TMRA_CLK_DIV32; - stcTmraInit.u32PeriodValue = timer->info->maxcnt; + stcTmraInit.u32PeriodValue = timer->info->maxcnt; (void)TMRA_Init(tmr_device->tmr_handle, &stcTmraInit); TMRA_IntCmd(tmr_device->tmr_handle, TMRA_INT_OVF, ENABLE); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_TRUE); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) hc32_install_irq_handler(&irq_config, NULL, RT_TRUE); #endif } else /* close */ { TMRA_DeInit(tmr_device->tmr_handle); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) hc32_install_irq_handler(&irq_config, tmr_device->isr.irq_callback, RT_FALSE); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) hc32_install_irq_handler(&irq_config, NULL, RT_FALSE); #endif FCG_Fcg2PeriphClockCmd(tmr_device->clock, DISABLE); @@ -251,7 +252,7 @@ static void TMRA_1_callback(void) rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_1_INDEX].time_device); } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMRA_1_Ovf_Udf_Handler(void) { TMRA_1_callback(); @@ -266,7 +267,7 @@ static void TMRA_2_callback(void) rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_2_INDEX].time_device); } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMRA_2_Ovf_Udf_Handler(void) { TMRA_2_callback(); @@ -281,7 +282,7 @@ static void TMRA_3_callback(void) rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_3_INDEX].time_device); } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMRA_3_Ovf_Udf_Handler(void) { TMRA_3_callback(); @@ -296,7 +297,7 @@ static void TMRA_4_callback(void) rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_4_INDEX].time_device); } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMRA_4_Ovf_Udf_Handler(void) { TMRA_4_callback(); @@ -311,7 +312,7 @@ static void TMRA_5_callback(void) rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_5_INDEX].time_device); } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void TMRA_5_Ovf_Udf_Handler(void) { TMRA_5_callback(); @@ -326,7 +327,7 @@ static void TMRA_6_callback(void) rt_clock_timer_isr(&hc32_clock_timer_obj[TMRA_6_INDEX].time_device); } -#if defined (HC32F472) +#if defined(HC32F472) void TMRA_6_Ovf_Udf_Handler(void) { TMRA_6_callback(); @@ -389,13 +390,13 @@ void tmra_get_info_callback(void) /* Div = 32 */ for (rt_uint8_t i = 0; i < sizeof(_info) / sizeof(_info[0]); i++) { - _info[i].maxcnt = CLK_GetBusClockFreq(hc32_clock_timer_obj[i].clock_source) / 32U / 1000U; /* Period = 1ms */ + _info[i].maxcnt = CLK_GetBusClockFreq(hc32_clock_timer_obj[i].clock_source) / 32U / 1000U; /* Period = 1ms */ _info[i].maxfreq = CLK_GetBusClockFreq(hc32_clock_timer_obj[i].clock_source) / 32U; _info[i].minfreq = CLK_GetBusClockFreq(hc32_clock_timer_obj[i].clock_source) / 32U / _info[i].maxcnt; _info[i].cntmode = CLOCK_TIMER_CNTMODE_UP; } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) #ifdef BSP_USING_TMRA_1 hc32_clock_timer_obj[TMRA_1_INDEX].isr.irq_callback = TMRA_1_callback; #endif @@ -435,8 +436,7 @@ void tmra_get_info_callback(void) #endif } -static const struct rt_clock_timer_ops _ops = -{ +static const struct rt_clock_timer_ops _ops = { .init = _timer_init, .start = _timer_start, .stop = _timer_stop, @@ -453,9 +453,9 @@ static int rt_hw_clock_timer_init(void) for (i = 0; i < sizeof(hc32_clock_timer_obj) / sizeof(hc32_clock_timer_obj[0]); i++) { hc32_clock_timer_obj[i].time_device.info = &_info[i]; - hc32_clock_timer_obj[i].time_device.ops = &_ops; + hc32_clock_timer_obj[i].time_device.ops = &_ops; if (rt_clock_timer_register(&hc32_clock_timer_obj[i].time_device, - hc32_clock_timer_obj[i].name, &hc32_clock_timer_obj[i].tmr_handle) == RT_EOK) + hc32_clock_timer_obj[i].name, &hc32_clock_timer_obj[i].tmr_handle) == RT_EOK) { LOG_D("%s register success", hc32_clock_timer_obj[i].name); } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c b/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c index 16b70b13a02..e5a130bb991 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.c @@ -6,15 +6,13 @@ * Change Logs: * Date Author Notes * 2025-01-10 CDT first version + * 2026-05-27 CDT support HC32F4A2 */ #include #if defined(BSP_USING_INPUT_CAPTURE) -#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) || defined(BSP_USING_INPUT_CAPTURE_TMR6_2) || defined(BSP_USING_INPUT_CAPTURE_TMR6_3) \ -|| defined(BSP_USING_INPUT_CAPTURE_TMR6_4) || defined(BSP_USING_INPUT_CAPTURE_TMR6_5) || defined(BSP_USING_INPUT_CAPTURE_TMR6_6) \ -|| defined(BSP_USING_INPUT_CAPTURE_TMR6_7) || defined(BSP_USING_INPUT_CAPTURE_TMR6_8) || defined(BSP_USING_INPUT_CAPTURE_TMR6_9) \ -|| defined(BSP_USING_INPUT_CAPTURE_TMR6_10) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) || defined(BSP_USING_INPUT_CAPTURE_TMR6_2) || defined(BSP_USING_INPUT_CAPTURE_TMR6_3) || defined(BSP_USING_INPUT_CAPTURE_TMR6_4) || defined(BSP_USING_INPUT_CAPTURE_TMR6_5) || defined(BSP_USING_INPUT_CAPTURE_TMR6_6) || defined(BSP_USING_INPUT_CAPTURE_TMR6_7) || defined(BSP_USING_INPUT_CAPTURE_TMR6_8) || defined(BSP_USING_INPUT_CAPTURE_TMR6_9) || defined(BSP_USING_INPUT_CAPTURE_TMR6_10) #include #include @@ -25,15 +23,15 @@ /* Private typedef --------------------------------------------------------------*/ typedef struct { - struct rt_inputcapture_device parent; + struct rt_inputcapture_device parent; struct tmr_capture_dev_init_params init_params; uint32_t clk; void *tmr_instance; - __IO uint32_t cur_cnt; - __IO uint32_t ovf_cnt; - __IO rt_bool_t input_data_level; - __IO rt_bool_t is_first_edge; - __IO rt_bool_t is_open; + __IO uint32_t cur_cnt; + __IO uint32_t ovf_cnt; + __IO rt_bool_t input_data_level; + __IO rt_bool_t is_first_edge; + __IO rt_bool_t is_open; uint32_t cond; en_int_src_t int_src_cap; en_int_src_t int_src_ovf; @@ -81,132 +79,143 @@ static rt_err_t _tmr_capture_init(struct rt_inputcapture_device *inputcapture); static rt_err_t _tmr_capture_open(struct rt_inputcapture_device *inputcapture); static rt_err_t _tmr_capture_close(struct rt_inputcapture_device *inputcapture); static rt_err_t _tmr_capture_get_pulsewidth(struct rt_inputcapture_device *inputcapture, rt_uint32_t *pulsewidth_us); -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) - static void _tmr6_1_isr_ovf(void); - static void _tmr6_1_isr_cap(void); +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +static void _tmr6_1_isr_ovf(void); +static void _tmr6_1_isr_cap(void); #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) - static void _tmr6_2_isr_ovf(void); - static void _tmr6_2_isr_cap(void); +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +static void _tmr6_2_isr_ovf(void); +static void _tmr6_2_isr_cap(void); #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) - static void _tmr6_3_isr_ovf(void); - static void _tmr6_3_isr_cap(void); +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) +static void _tmr6_3_isr_ovf(void); +static void _tmr6_3_isr_cap(void); #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_4) - static void _tmr6_4_isr_ovf(void); - static void _tmr6_4_isr_cap(void); +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_4) +static void _tmr6_4_isr_ovf(void); +static void _tmr6_4_isr_cap(void); #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_5) - static void _tmr6_5_isr_ovf(void); - static void _tmr6_5_isr_cap(void); +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_5) +static void _tmr6_5_isr_ovf(void); +static void _tmr6_5_isr_cap(void); #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_6) - static void _tmr6_6_isr_ovf(void); - static void _tmr6_6_isr_cap(void); +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_6) +static void _tmr6_6_isr_ovf(void); +static void _tmr6_6_isr_cap(void); #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_7) - static void _tmr6_7_isr_ovf(void); - static void _tmr6_7_isr_cap(void); +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_7) +static void _tmr6_7_isr_ovf(void); +static void _tmr6_7_isr_cap(void); #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_8) - static void _tmr6_8_isr_ovf(void); - static void _tmr6_8_isr_cap(void); +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_8) +static void _tmr6_8_isr_ovf(void); +static void _tmr6_8_isr_cap(void); #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_9) - static void _tmr6_9_isr_ovf(void); - static void _tmr6_9_isr_cap(void); +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_9) +static void _tmr6_9_isr_ovf(void); +static void _tmr6_9_isr_cap(void); #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_10) - static void _tmr6_10_isr_ovf(void); - static void _tmr6_10_isr_cap(void); +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_10) +static void _tmr6_10_isr_ovf(void); +static void _tmr6_10_isr_cap(void); #endif /* Private define ---------------------------------------------------------------*/ -#define TMR6_INSTANCE_MIN ((uint32_t)CM_TMR6_1) -#if defined (HC32F4A0) || defined (HC32F4A8) - #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_8) -#elif defined (HC32F460) - #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_3) -#elif defined (HC32F334) - #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_4) -#elif defined (HC32F448) - #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_2) -#elif defined (HC32F472) - #define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_10) -#endif -#define TMR6_INSTANCE_ADDR_ALIGN (0x400UL) -#define TMR6_PERIOD_VALUE_MAX (0xFFFFUL) -#define IS_TMR6_UNIT(x) (((x) >= TMR6_INSTANCE_MIN && (x) <= TMR6_INSTANCE_MAX) && ((x) % TMR6_INSTANCE_ADDR_ALIGN) == 0U) - -#if defined (BSP_USING_INPUT_CAPTURE_TMR6) - #define IS_CAPTURE_COND_RASING_EDGE(bit_pos) ((bit_pos) % 2U == 0U) - #if defined (HC32F4A0) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F472) - #define VALID_CAPTURE_COND (TMR6_CAPT_COND_ALL & (~(TMR6_CAPT_COND_EVT0 | TMR6_CAPT_COND_EVT1 | TMR6_CAPT_COND_EVT2 | TMR6_CAPT_COND_EVT3))) - #elif defined (HC32F460) || defined (HC32F448) - #define VALID_CAPTURE_COND (TMR6_CAPT_COND_ALL & (~(TMR6_CAPT_COND_EVT0 | TMR6_CAPT_COND_EVT1))) - #endif -#endif - -#define TMR6_ISR_OVF(U,N) \ -static void _tmr6_##U##_isr_ovf(void)\ -{\ - g_tmr_capturers[N].ovf_cnt++;\ - TMR6_ClearStatus(CM_TMR6_##U, TMR6_FLAG_OVF);\ -} +#define TMR6_INSTANCE_MIN ((uint32_t)CM_TMR6_1) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) +#define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_8) +#elif defined(HC32F460) || defined(HC32F467) +#define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_3) +#elif defined(HC32F334) +#define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_4) +#elif defined(HC32F448) +#define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_2) +#elif defined(HC32F472) +#define TMR6_INSTANCE_MAX ((uint32_t)CM_TMR6_10) +#endif +#define TMR6_INSTANCE_ADDR_ALIGN (0x400UL) +#define TMR6_PERIOD_VALUE_MAX (0xFFFFUL) +#define IS_TMR6_UNIT(x) (((x) >= TMR6_INSTANCE_MIN && (x) <= TMR6_INSTANCE_MAX) && ((x) % TMR6_INSTANCE_ADDR_ALIGN) == 0U) -#define TMR6_ISR_CAP(U,N) \ -static void _tmr6_##U##_isr_cap(void)\ -{\ - _tmr6_irq_cap_handler(&g_tmr_capturers[N]);\ -} +#if defined(BSP_USING_INPUT_CAPTURE_TMR6) +#define IS_CAPTURE_COND_RASING_EDGE(bit_pos) ((bit_pos) % 2U == 0U) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F334) || defined(HC32F472) || defined(HC32F467) +#define VALID_CAPTURE_COND (TMR6_CAPT_COND_ALL & (~(TMR6_CAPT_COND_EVT0 | TMR6_CAPT_COND_EVT1 | TMR6_CAPT_COND_EVT2 | TMR6_CAPT_COND_EVT3))) +#elif defined(HC32F460) || defined(HC32F448) +#define VALID_CAPTURE_COND (TMR6_CAPT_COND_ALL & (~(TMR6_CAPT_COND_EVT0 | TMR6_CAPT_COND_EVT1))) +#endif +#endif -#define TMR6_CAPTURE_CFG(U) \ -{ {0}, INPUT_CAPTURE_CFG_TMR6_##U, 0, (CM_TMR6_##U), 0, 0, 0, 0, 0, 0, \ - INT_SRC_TMR6_##U##_GCMP_A, INT_SRC_TMR6_##U##_OVF, _tmr6_##U##_isr_cap, _tmr6_##U##_isr_ovf, \ -} +#define TMR6_ISR_OVF(U, N) \ + static void _tmr6_##U##_isr_ovf(void) \ + { \ + g_tmr_capturers[N].ovf_cnt++; \ + TMR6_ClearStatus(CM_TMR6_##U, TMR6_FLAG_OVF); \ + } + +#define TMR6_ISR_CAP(U, N) \ + static void _tmr6_##U##_isr_cap(void) \ + { \ + _tmr6_irq_cap_handler(&g_tmr_capturers[N]); \ + } + +#define TMR6_CAPTURE_CFG(U) \ + { \ + { 0 }, \ + INPUT_CAPTURE_CFG_TMR6_##U, \ + 0, \ + (CM_TMR6_##U), \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + 0, \ + INT_SRC_TMR6_##U##_GCMP_A, \ + INT_SRC_TMR6_##U##_OVF, \ + _tmr6_##U##_isr_cap, \ + _tmr6_##U##_isr_ovf, \ + } /* Private variables ------------------------------------------------------------*/ -static tmr_capture_t g_tmr_capturers[] = -{ -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) +static tmr_capture_t g_tmr_capturers[] = { +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) TMR6_CAPTURE_CFG(1), #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) TMR6_CAPTURE_CFG(2), #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) TMR6_CAPTURE_CFG(3), #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_4) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_4) TMR6_CAPTURE_CFG(4), #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_5) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_5) TMR6_CAPTURE_CFG(5), #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_6) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_6) TMR6_CAPTURE_CFG(6), #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_7) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_7) TMR6_CAPTURE_CFG(7), #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_8) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_8) TMR6_CAPTURE_CFG(8), #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_9) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_9) TMR6_CAPTURE_CFG(9), #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_10) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_10) TMR6_CAPTURE_CFG(10), #endif }; -static struct rt_inputcapture_ops tmr_capture_ops = -{ - .init = _tmr_capture_init, - .open = _tmr_capture_open, - .close = _tmr_capture_close, - .get_pulsewidth = _tmr_capture_get_pulsewidth, +static struct rt_inputcapture_ops tmr_capture_ops = { + .init = _tmr_capture_init, + .open = _tmr_capture_open, + .close = _tmr_capture_close, + .get_pulsewidth = _tmr_capture_get_pulsewidth, }; /* Functions define ------------------------------------------------------------*/ @@ -218,65 +227,65 @@ static void _tmr6_irq_cap_handler(tmr_capture_t *p_capture) } else { - p_capture->cur_cnt = TMR6_GetCompareValue((CM_TMR6_TypeDef *)p_capture->tmr_instance, \ - p_capture->init_params.ch); + p_capture->cur_cnt = TMR6_GetCompareValue((CM_TMR6_TypeDef *)p_capture->tmr_instance, + p_capture->init_params.ch); rt_interrupt_enter(); rt_hw_inputcapture_isr(&p_capture->parent, p_capture->input_data_level); rt_interrupt_leave(); p_capture->input_data_level = !p_capture->input_data_level; } p_capture->ovf_cnt = 0; - TMR6_ClearStatus((CM_TMR6_TypeDef *)p_capture->tmr_instance, \ + TMR6_ClearStatus((CM_TMR6_TypeDef *)p_capture->tmr_instance, TMR6_FLAG_MATCH_A << p_capture->init_params.ch); } -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_1) - TMR6_ISR_OVF(1, TMR_CAPTURE_IDX_TMR6_1) - TMR6_ISR_CAP(1, TMR_CAPTURE_IDX_TMR6_1) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_1) +TMR6_ISR_OVF(1, TMR_CAPTURE_IDX_TMR6_1) +TMR6_ISR_CAP(1, TMR_CAPTURE_IDX_TMR6_1) #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_2) - TMR6_ISR_OVF(2, TMR_CAPTURE_IDX_TMR6_2) - TMR6_ISR_CAP(2, TMR_CAPTURE_IDX_TMR6_2) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_2) +TMR6_ISR_OVF(2, TMR_CAPTURE_IDX_TMR6_2) +TMR6_ISR_CAP(2, TMR_CAPTURE_IDX_TMR6_2) #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_3) - TMR6_ISR_OVF(3, TMR_CAPTURE_IDX_TMR6_3) - TMR6_ISR_CAP(3, TMR_CAPTURE_IDX_TMR6_3) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_3) +TMR6_ISR_OVF(3, TMR_CAPTURE_IDX_TMR6_3) +TMR6_ISR_CAP(3, TMR_CAPTURE_IDX_TMR6_3) #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_4) - TMR6_ISR_OVF(4, TMR_CAPTURE_IDX_TMR6_4) - TMR6_ISR_CAP(4, TMR_CAPTURE_IDX_TMR6_4) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_4) +TMR6_ISR_OVF(4, TMR_CAPTURE_IDX_TMR6_4) +TMR6_ISR_CAP(4, TMR_CAPTURE_IDX_TMR6_4) #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_5) - TMR6_ISR_OVF(5, TMR_CAPTURE_IDX_TMR6_5) - TMR6_ISR_CAP(5, TMR_CAPTURE_IDX_TMR6_5) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_5) +TMR6_ISR_OVF(5, TMR_CAPTURE_IDX_TMR6_5) +TMR6_ISR_CAP(5, TMR_CAPTURE_IDX_TMR6_5) #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_6) - TMR6_ISR_OVF(6, TMR_CAPTURE_IDX_TMR6_6) - TMR6_ISR_CAP(6, TMR_CAPTURE_IDX_TMR6_6) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_6) +TMR6_ISR_OVF(6, TMR_CAPTURE_IDX_TMR6_6) +TMR6_ISR_CAP(6, TMR_CAPTURE_IDX_TMR6_6) #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_7) - TMR6_ISR_OVF(7, TMR_CAPTURE_IDX_TMR6_7) - TMR6_ISR_CAP(7, TMR_CAPTURE_IDX_TMR6_7) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_7) +TMR6_ISR_OVF(7, TMR_CAPTURE_IDX_TMR6_7) +TMR6_ISR_CAP(7, TMR_CAPTURE_IDX_TMR6_7) #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_8) - TMR6_ISR_OVF(8, TMR_CAPTURE_IDX_TMR6_8) - TMR6_ISR_CAP(8, TMR_CAPTURE_IDX_TMR6_8) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_8) +TMR6_ISR_OVF(8, TMR_CAPTURE_IDX_TMR6_8) +TMR6_ISR_CAP(8, TMR_CAPTURE_IDX_TMR6_8) #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_9) - TMR6_ISR_OVF(9, TMR_CAPTURE_IDX_TMR6_9) - TMR6_ISR_CAP(9, TMR_CAPTURE_IDX_TMR6_9) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_9) +TMR6_ISR_OVF(9, TMR_CAPTURE_IDX_TMR6_9) +TMR6_ISR_CAP(9, TMR_CAPTURE_IDX_TMR6_9) #endif -#if defined (BSP_USING_INPUT_CAPTURE_TMR6_10) - TMR6_ISR_OVF(10, TMR_CAPTURE_IDX_TMR6_10) - TMR6_ISR_CAP(10, TMR_CAPTURE_IDX_TMR6_10) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6_10) +TMR6_ISR_OVF(10, TMR_CAPTURE_IDX_TMR6_10) +TMR6_ISR_CAP(10, TMR_CAPTURE_IDX_TMR6_10) #endif static void _tmr_irq_init_cap(tmr_capture_t *p_capture) { stc_irq_signin_config_t stcIrq; stcIrq.pfnCallback = p_capture->isr_cap; - stcIrq.enIntSrc = (en_int_src_t)((uint32_t)p_capture->int_src_cap + p_capture->init_params.ch); - stcIrq.enIRQn = p_capture->init_params.irq_num_cap; + stcIrq.enIntSrc = (en_int_src_t)((uint32_t)p_capture->int_src_cap + p_capture->init_params.ch); + stcIrq.enIRQn = p_capture->init_params.irq_num_cap; (void)INTC_IrqSignIn(&stcIrq); NVIC_ClearPendingIRQ(stcIrq.enIRQn); NVIC_SetPriority(stcIrq.enIRQn, p_capture->init_params.irq_prio_cap); @@ -287,7 +296,7 @@ static void _tmr_irq_init_ovf(tmr_capture_t *p_capture) stc_irq_signin_config_t stcIrq; stcIrq.pfnCallback = p_capture->isr_ovf; stcIrq.enIntSrc = (en_int_src_t)(p_capture->int_src_ovf); - stcIrq.enIRQn = p_capture->init_params.irq_num_ovf; + stcIrq.enIRQn = p_capture->init_params.irq_num_ovf; (void)INTC_IrqSignIn(&stcIrq); NVIC_ClearPendingIRQ(stcIrq.enIRQn); NVIC_SetPriority(stcIrq.enIRQn, p_capture->init_params.irq_prio_ovf); @@ -332,7 +341,7 @@ static void _tmr_capture_assert_params(tmr_capture_t *p_capture) RT_ASSERT(p_init_params->first_edge != 0U); RT_ASSERT(_is_one_cond(p_init_params->first_edge)); RT_ASSERT((p_init_params->first_edge | VALID_CAPTURE_COND) == VALID_CAPTURE_COND); -#if defined (BSP_USING_INPUT_CAPTURE_TMR6) +#if defined(BSP_USING_INPUT_CAPTURE_TMR6) RT_ASSERT((p_init_params->ch == TMR6_CH_A) || (p_init_params->ch == TMR6_CH_B)); #endif } @@ -342,7 +351,7 @@ static void _tmr_capture_init_tmr6(tmr_capture_t *p_capture, CM_TMR6_TypeDef *in uint32_t unit = ((uint32_t)p_capture->tmr_instance - (uint32_t)CM_TMR6_1) / TMR6_INSTANCE_ADDR_ALIGN; FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR6_1 << unit, ENABLE); -#if defined (HC32F460) +#if defined(HC32F460) if (instance != CM_TMR6_1) { FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR6_1, ENABLE); @@ -358,7 +367,7 @@ static void _tmr_capture_init_tmr6(tmr_capture_t *p_capture, CM_TMR6_TypeDef *in uint32_t pin; uint32_t bit_pos = _get_capture_cond_bit_pos(init_params->first_edge); -#if defined (HC32F4A0) || defined (HC32F4A8) || defined (HC32F334) || defined (HC32F448) || defined (HC32F472) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F334) || defined(HC32F448) || defined(HC32F472) || defined(HC32F467) if (bit_pos <= TMR6_HCPAR_HCPA3_POS) { pin = TMR6_IO_PWMA + (bit_pos / 2U); @@ -367,7 +376,7 @@ static void _tmr_capture_init_tmr6(tmr_capture_t *p_capture, CM_TMR6_TypeDef *in { pin = TMR6_INPUT_TRIGA + (bit_pos - TMR6_HCPAR_HCPA16_POS) / 2U; } -#elif defined (HC32F460) +#elif defined(HC32F460) pin = TMR6_IO_PWMA + (bit_pos - TMR6_HCPAR_HCPA4_POS) / 2U; #endif TMR6_SetFilterClockDiv(instance, pin, TMR6_FILTER_CLK_DIV16); @@ -407,8 +416,7 @@ static rt_err_t _tmr_capture_init(struct rt_inputcapture_device *inputcapture) } #endif break; - } - while (0); + } while (0); return ret; } @@ -442,8 +450,7 @@ static rt_err_t _tmr_capture_open(struct rt_inputcapture_device *inputcapture) break; } #endif - } - while (0); + } while (0); return ret; } @@ -455,7 +462,7 @@ static rt_err_t _tmr_capture_close(struct rt_inputcapture_device *inputcapture) RT_ASSERT(inputcapture != (void *)RT_NULL); - p_capture = (tmr_capture_t *)(void *) inputcapture; + p_capture = (tmr_capture_t *)(void *)inputcapture; NVIC_DisableIRQ(p_capture->init_params.irq_num_ovf); NVIC_DisableIRQ(p_capture->init_params.irq_num_cap); do @@ -468,8 +475,7 @@ static rt_err_t _tmr_capture_close(struct rt_inputcapture_device *inputcapture) break; } #endif - } - while (0); + } while (0); p_capture->is_open = RT_FALSE; return ret; @@ -498,7 +504,7 @@ int tmr_capture_device_init(void) _tmr_capture_assert_params(&g_tmr_capturers[i]); #endif g_tmr_capturers[i].parent.ops = &tmr_capture_ops; - rt_device_inputcapture_register(&g_tmr_capturers[i].parent, \ + rt_device_inputcapture_register(&g_tmr_capturers[i].parent, g_tmr_capturers[i].init_params.name, &g_tmr_capturers[i]); } diff --git a/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.h b/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.h index 7c855d15d12..b20403bc5cf 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_tmr_capture.h @@ -27,9 +27,9 @@ struct tmr_capture_dev_init_params uint8_t clk_div; uint32_t first_edge; IRQn_Type irq_num_cap; - uint32_t irq_prio_cap; + uint32_t irq_prio_cap; IRQn_Type irq_num_ovf; - uint32_t irq_prio_ovf; + uint32_t irq_prio_ovf; }; extern rt_err_t rt_hw_board_input_capture_init(uint32_t *tmr_instance); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart.c b/bsp/hc32/libraries/hc32_drivers/drv_usart.c index 5e6883a2c1a..0b0ac0120ed 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart.c @@ -9,6 +9,8 @@ * 2023-10-09 CDT support HC32F448 * 2024-04-15 CDT support HC32F472 * 2025-07-16 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ /******************************************************************************* @@ -20,10 +22,10 @@ #ifdef RT_USING_SERIAL -#if defined (BSP_USING_UART1) || defined (BSP_USING_UART2) || defined (BSP_USING_UART3) || \ - defined (BSP_USING_UART4) || defined (BSP_USING_UART5) || defined (BSP_USING_UART6) || \ - defined (BSP_USING_UART7) || defined (BSP_USING_UART8) || defined (BSP_USING_UART9) || \ - defined (BSP_USING_UART10) +#if defined(BSP_USING_UART1) || defined(BSP_USING_UART2) || defined(BSP_USING_UART3) || \ + defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) || \ + defined(BSP_USING_UART7) || defined(BSP_USING_UART8) || defined(BSP_USING_UART9) || \ + defined(BSP_USING_UART10) #include "drv_usart.h" #include "board_config.h" @@ -35,29 +37,31 @@ /******************************************************************************* * Local pre-processor symbols/macros ('#define') ******************************************************************************/ -#define DMA_CH_REG(reg_base, ch) \ +#define DMA_CH_REG(reg_base, ch) \ (*(volatile uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) -#define DMA_TRANS_SET_CNT(unit, ch) \ - (READ_REG32(DMA_CH_REG((unit)->DTCTL0,(ch))) >> DMA_DTCTL_CNT_POS) +#define DMA_TRANS_SET_CNT(unit, ch) \ + (READ_REG32(DMA_CH_REG((unit)->DTCTL0, (ch))) >> DMA_DTCTL_CNT_POS) -#define DMA_TRANS_CNT(unit, ch) \ +#define DMA_TRANS_CNT(unit, ch) \ (READ_REG32(DMA_CH_REG((unit)->MONDTCTL0, (ch))) >> DMA_DTCTL_CNT_POS) -#define UART_BAUDRATE_ERR_MAX (0.025F) +#define UART_BAUDRATE_ERR_MAX (0.025F) -#if defined (HC32F460) - #define FCG_USART_CLK FCG_Fcg1PeriphClockCmd -#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) - #define FCG_USART_CLK FCG_Fcg3PeriphClockCmd +#if defined(HC32F460) +#define FCG_USART_CLK FCG_Fcg1PeriphClockCmd +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || \ + defined(HC32F4A8) || defined(HC32F334) || defined(HC32F467) +#define FCG_USART_CLK FCG_Fcg3PeriphClockCmd #endif -#define FCG_TMR0_CLK FCG_Fcg2PeriphClockCmd -#define FCG_DMA_CLK FCG_Fcg0PeriphClockCmd -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) - #define USART_MAX_CLK_DIV USART_CLK_DIV64 -#elif defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) - #define USART_MAX_CLK_DIV USART_CLK_DIV1024 +#define FCG_TMR0_CLK FCG_Fcg2PeriphClockCmd +#define FCG_DMA_CLK FCG_Fcg0PeriphClockCmd +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || \ + defined(HC32F467) +#define USART_MAX_CLK_DIV USART_CLK_DIV64 +#elif defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) +#define USART_MAX_CLK_DIV USART_CLK_DIV1024 #endif /******************************************************************************* @@ -69,7 +73,7 @@ extern rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx); * Local function prototypes ('static') ******************************************************************************/ #ifdef RT_SERIAL_USING_DMA - static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); #endif /******************************************************************************* @@ -109,8 +113,7 @@ enum #endif }; -static struct hc32_uart_config uart_config[] = -{ +static struct hc32_uart_config uart_config[] = { #ifdef BSP_USING_UART1 UART1_CONFIG, #endif @@ -143,7 +146,7 @@ static struct hc32_uart_config uart_config[] = #endif }; -static struct hc32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; +static struct hc32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = { 0 }; /******************************************************************************* * Function implementation - global ('extern') and local ('static') @@ -161,15 +164,15 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co uart_init.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; uart_init.u32Baudrate = cfg->baud_rate; uart_init.u32ClockSrc = USART_CLK_SRC_INTERNCLK; -#if defined (HC32F4A0) - if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ - (CM_USART6 == uart->config->Instance) || (CM_USART7 == uart->config->Instance)) -#elif defined (HC32F460) || defined (HC32F334) - if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ - (CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance)) -#elif defined (HC32F448) || defined (HC32F472) - if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ - (CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance)) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) + if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || + (CM_USART6 == uart->config->Instance) || (CM_USART7 == uart->config->Instance)) +#elif defined(HC32F460) || defined(HC32F334) + if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || + (CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance)) +#elif defined(HC32F448) || defined(HC32F472) + if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || + (CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance)) #endif { uart_init.u32CKOutput = USART_CK_OUTPUT_ENABLE; @@ -225,7 +228,8 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co { uart_init.u32FirstBit = USART_FIRST_BIT_MSB; } -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) switch (cfg->flowcontrol) { case RT_SERIAL_FLOWCONTROL_NONE: @@ -260,7 +264,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co USART_UART_Init(uart->config->Instance, &uart_init, NULL); for (u32Div = 0UL; u32Div <= USART_MAX_CLK_DIV; u32Div++) { -#if defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) if (u32Div == (USART_CLK_DIV64 + 1U)) { u32Div = USART_CLK_DIV128; @@ -268,7 +272,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co #endif USART_SetClockDiv(uart->config->Instance, u32Div); if ((LL_OK == USART_SetBaudrate(uart->config->Instance, uart_init.u32Baudrate, &f32Error)) && - ((-UART_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= UART_BAUDRATE_ERR_MAX))) + ((-UART_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= UART_BAUDRATE_ERR_MAX))) { i32Ret = LL_OK; break; @@ -280,9 +284,9 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co } /* Enable error interrupt */ -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE); INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); INTC_IntSrcCmd(uart->config->rxerr_int_src, ENABLE); @@ -308,20 +312,20 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg case RT_DEVICE_CTRL_CLR_INT: if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num); INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); #endif } else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num); USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE); INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) USART_FuncCmd(uart->config->Instance, USART_INT_TX_EMPTY, DISABLE); #endif } @@ -339,7 +343,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg break; /* Enable interrupt */ case RT_DEVICE_CTRL_SET_INT: -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) { hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE); @@ -352,7 +356,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE); USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE); } -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) /* NVIC config */ if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) { @@ -397,7 +401,8 @@ static int hc32_putc(struct rt_serial_device *serial, char c) else { /* Polling mode. */ - while (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY) != SET); + while (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY) != SET) + ; } USART_WriteData(uart->config->Instance, c); @@ -504,9 +509,9 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) RT_ASSERT(RT_NULL != uart->config->Instance); TMR0_Instance = uart->config->rx_timeout->TMR0_Instance; - ch = uart->config->rx_timeout->channel; - rtb = uart->config->rx_timeout->timeout_bits; -#if defined (HC32F460) || defined (HC32F334) + ch = uart->config->rx_timeout->channel; + rtb = uart->config->rx_timeout->timeout_bits; +#if defined(HC32F460) || defined(HC32F334) if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance)) { RT_ASSERT(TMR0_CH_A == ch); @@ -515,7 +520,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { RT_ASSERT(TMR0_CH_B == ch); } -#elif defined (HC32F4A0) +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) if ((CM_USART1 == uart->config->Instance) || (CM_USART6 == uart->config->Instance)) { RT_ASSERT(TMR0_CH_A == ch); @@ -524,7 +529,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { RT_ASSERT(TMR0_CH_B == ch); } -#elif defined (HC32F448) || defined (HC32F472) +#elif defined(HC32F448) || defined(HC32F472) if ((CM_USART1 == uart->config->Instance) || (CM_USART4 == uart->config->Instance)) { RT_ASSERT(TMR0_CH_A == ch); @@ -533,9 +538,9 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { RT_ASSERT(TMR0_CH_B == ch); } -#elif defined (HC32F4A8) +#elif defined(HC32F4A8) if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance) || (CM_USART5 == uart->config->Instance) || - (CM_USART6 == uart->config->Instance) || (CM_USART9 == uart->config->Instance)) + (CM_USART6 == uart->config->Instance) || (CM_USART9 == uart->config->Instance)) { RT_ASSERT(TMR0_CH_A == ch); } @@ -546,7 +551,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) } #endif -#if defined (HC32F4A8) +#if defined(HC32F4A8) if ((CM_TMR0_4 == uart->config->rx_timeout->TMR0_Instance) || (CM_TMR0_5 == uart->config->rx_timeout->TMR0_Instance)) { FCG_Fcg3PeriphClockCmd(uart->config->rx_timeout->clock, ENABLE); @@ -555,7 +560,8 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE); } -#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F334) || \ + defined(HC32F467) FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE); #endif @@ -572,8 +578,8 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { alpha = 5UL; } - else if ((TMR0_CLK_DIV4 == stcTmr0Init.u32ClockDiv) || \ - (TMR0_CLK_DIV8 == stcTmr0Init.u32ClockDiv) || \ + else if ((TMR0_CLK_DIV4 == stcTmr0Init.u32ClockDiv) || + (TMR0_CLK_DIV8 == stcTmr0Init.u32ClockDiv) || (TMR0_CLK_DIV16 == stcTmr0Init.u32ClockDiv)) { alpha = 3UL; @@ -583,7 +589,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) alpha = 2UL; } /* TMR0_CMPAR calculation formula: CMPAR = (RTB / (2 ^ CKDIVA)) - alpha */ - ckdiv = 1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS); + ckdiv = 1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS); cmp_val = ((rtb + ckdiv - 1UL) / ckdiv) - alpha; DDL_ASSERT(cmp_val <= 0xFFFFUL); stcTmr0Init.u16CompareValue = (uint16_t)(cmp_val); @@ -593,7 +599,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) /* Clear compare flag */ TMR0_ClearStatus(TMR0_Instance, (uint32_t)(0x1UL << (ch * TMR0_STFLR_CMFB_POS))); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) NVIC_EnableIRQ(uart->config->rx_timeout->irq_config.irq_num); #endif USART_ClearStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT); @@ -608,7 +614,7 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) struct dma_config *uart_dma; RT_ASSERT(RT_NULL != serial); - RT_ASSERT(RT_NULL == ((serial->config.bufsz) & ((RT_ALIGN_SIZE) - 1))); + RT_ASSERT(RT_NULL == ((serial->config.bufsz) & ((RT_ALIGN_SIZE)-1))); uart = rt_container_of(serial, struct hc32_uart, serial); RT_ASSERT(RT_NULL != uart->config->Instance); @@ -621,7 +627,7 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance); RT_ASSERT(RT_NULL != rx_fifo); -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); #endif @@ -634,39 +640,39 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) /* Initialize DMA */ DMA_StructInit(&dma_init); - dma_init.u32IntEn = DMA_INT_ENABLE; - dma_init.u32SrcAddr = (uint32_t)(&uart->config->Instance->RDR); - dma_init.u32DestAddr = (uint32_t)rx_fifo->buffer; - dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; - dma_init.u32BlockSize = 1UL; - dma_init.u32TransCount = trans_count; - dma_init.u32SrcAddrInc = DMA_SRC_ADDR_FIX; + dma_init.u32IntEn = DMA_INT_ENABLE; + dma_init.u32SrcAddr = (uint32_t)(&uart->config->Instance->RDR); + dma_init.u32DestAddr = (uint32_t)rx_fifo->buffer; + dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; + dma_init.u32BlockSize = 1UL; + dma_init.u32TransCount = trans_count; + dma_init.u32SrcAddrInc = DMA_SRC_ADDR_FIX; dma_init.u32DestAddrInc = DMA_DEST_ADDR_INC; DMA_Init(uart_dma->Instance, uart_dma->channel, &dma_init); /* Initialize LLP */ - llp_init.u32State = DMA_LLP_ENABLE; - llp_init.u32Mode = DMA_LLP_WAIT; - llp_init.u32Addr = (uint32_t)&uart->config->llp_desc; + llp_init.u32State = DMA_LLP_ENABLE; + llp_init.u32Mode = DMA_LLP_WAIT; + llp_init.u32Addr = (uint32_t)&uart->config->llp_desc; DMA_LlpInit(uart_dma->Instance, uart_dma->channel, &llp_init); /* Configure LLP descriptor */ - uart->config->llp_desc[0U].SARx = dma_init.u32SrcAddr; - uart->config->llp_desc[0U].DARx = dma_init.u32DestAddr + ((serial->config.bufsz <= 1U) ? 0U : dma_init.u32TransCount); - uart->config->llp_desc[0U].DTCTLx = (((serial->config.bufsz <= 1U) ? dma_init.u32TransCount : (serial->config.bufsz - dma_init.u32TransCount)) << DMA_DTCTL_CNT_POS) | \ + uart->config->llp_desc[0U].SARx = dma_init.u32SrcAddr; + uart->config->llp_desc[0U].DARx = dma_init.u32DestAddr + ((serial->config.bufsz <= 1U) ? 0U : dma_init.u32TransCount); + uart->config->llp_desc[0U].DTCTLx = (((serial->config.bufsz <= 1U) ? dma_init.u32TransCount : (serial->config.bufsz - dma_init.u32TransCount)) << DMA_DTCTL_CNT_POS) | (dma_init.u32BlockSize << DMA_DTCTL_BLKSIZE_POS); - uart->config->llp_desc[0U].LLPx = (serial->config.bufsz <= 1U) ? (uint32_t)&uart->config->llp_desc[0U] : (uint32_t)&uart->config->llp_desc[1U]; - uart->config->llp_desc[0U].CHCTLx = (dma_init.u32SrcAddrInc | dma_init.u32DestAddrInc | dma_init.u32DataWidth | \ - llp_init.u32State | llp_init.u32Mode | dma_init.u32IntEn); + uart->config->llp_desc[0U].LLPx = (serial->config.bufsz <= 1U) ? (uint32_t)&uart->config->llp_desc[0U] : (uint32_t)&uart->config->llp_desc[1U]; + uart->config->llp_desc[0U].CHCTLx = (dma_init.u32SrcAddrInc | dma_init.u32DestAddrInc | dma_init.u32DataWidth | + llp_init.u32State | llp_init.u32Mode | dma_init.u32IntEn); if (serial->config.bufsz > 1UL) { - uart->config->llp_desc[1U].SARx = dma_init.u32SrcAddr; - uart->config->llp_desc[1U].DARx = dma_init.u32DestAddr; + uart->config->llp_desc[1U].SARx = dma_init.u32SrcAddr; + uart->config->llp_desc[1U].DARx = dma_init.u32DestAddr; uart->config->llp_desc[1U].DTCTLx = (dma_init.u32TransCount << DMA_DTCTL_CNT_POS) | (dma_init.u32BlockSize << DMA_DTCTL_BLKSIZE_POS); - uart->config->llp_desc[1U].LLPx = (uint32_t)&uart->config->llp_desc[0U]; - uart->config->llp_desc[1U].CHCTLx = (dma_init.u32SrcAddrInc | dma_init.u32DestAddrInc | dma_init.u32DataWidth | \ - llp_init.u32State | llp_init.u32Mode | dma_init.u32IntEn); + uart->config->llp_desc[1U].LLPx = (uint32_t)&uart->config->llp_desc[0U]; + uart->config->llp_desc[1U].CHCTLx = (dma_init.u32SrcAddrInc | dma_init.u32DestAddrInc | dma_init.u32DataWidth | + llp_init.u32State | llp_init.u32Mode | dma_init.u32IntEn); } /* Enable DMA interrupt */ @@ -687,13 +693,13 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) /* Initialize DMA */ DMA_StructInit(&dma_init); - dma_init.u32IntEn = DMA_INT_DISABLE; - dma_init.u32SrcAddr = 0UL; - dma_init.u32DestAddr = (uint32_t)(&uart->config->Instance->TDR); - dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; - dma_init.u32BlockSize = 1UL; - dma_init.u32TransCount = 0UL; - dma_init.u32SrcAddrInc = DMA_SRC_ADDR_INC; + dma_init.u32IntEn = DMA_INT_DISABLE; + dma_init.u32SrcAddr = 0UL; + dma_init.u32DestAddr = (uint32_t)(&uart->config->Instance->TDR); + dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; + dma_init.u32BlockSize = 1UL; + dma_init.u32TransCount = 0UL; + dma_init.u32SrcAddrInc = DMA_SRC_ADDR_INC; dma_init.u32DestAddrInc = DMA_DEST_ADDR_FIX; DMA_Init(uart_dma->Instance, uart_dma->channel, &dma_init); @@ -705,10 +711,10 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) } } -#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \ - defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) || defined (BSP_UART6_RX_USING_DMA) || \ - defined (BSP_UART7_RX_USING_DMA) || defined (BSP_UART8_RX_USING_DMA) || defined (BSP_UART9_RX_USING_DMA) || \ - defined (BSP_UART10_RX_USING_DMA) +#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \ + defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART5_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || \ + defined(BSP_UART7_RX_USING_DMA) || defined(BSP_UART8_RX_USING_DMA) || defined(BSP_UART9_RX_USING_DMA) || \ + defined(BSP_UART10_RX_USING_DMA) static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart) { rt_base_t level; @@ -765,10 +771,10 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart) } #endif -#if defined (BSP_UART1_TX_USING_DMA) || defined (BSP_UART2_TX_USING_DMA) || defined (BSP_UART3_TX_USING_DMA) || \ - defined (BSP_UART4_TX_USING_DMA) || defined (BSP_UART5_TX_USING_DMA) || defined (BSP_UART6_TX_USING_DMA) || \ - defined (BSP_UART7_TX_USING_DMA) || defined (BSP_UART8_TX_USING_DMA) || defined (BSP_UART9_TX_USING_DMA) || \ - defined (BSP_UART10_TX_USING_DMA) +#if defined(BSP_UART1_TX_USING_DMA) || defined(BSP_UART2_TX_USING_DMA) || defined(BSP_UART3_TX_USING_DMA) || \ + defined(BSP_UART4_TX_USING_DMA) || defined(BSP_UART5_TX_USING_DMA) || defined(BSP_UART6_TX_USING_DMA) || \ + defined(BSP_UART7_TX_USING_DMA) || defined(BSP_UART8_TX_USING_DMA) || defined(BSP_UART9_TX_USING_DMA) || \ + defined(BSP_UART10_TX_USING_DMA) static void hc32_uart_tc_irq_handler(struct hc32_uart *uart) { RT_ASSERT(uart != RT_NULL); @@ -783,49 +789,49 @@ static void hc32_uart_tc_irq_handler(struct hc32_uart *uart) #endif #endif -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) static void hc32_usart_handler(struct hc32_uart *uart) { RT_ASSERT(RT_NULL != uart); -#if defined (RT_SERIAL_USING_DMA) - if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT)) && \ - (ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && \ - (ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src))) +#if defined(RT_SERIAL_USING_DMA) + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT)) && + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && + (ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src))) { -#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \ - defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) +#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \ + defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART5_RX_USING_DMA) hc32_uart_rxto_irq_handler(uart); #endif } #endif - if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_FULL)) && \ - (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && \ - (ENABLE == INTC_GetIntSrcState(uart->config->rx_int_src))) + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_FULL)) && + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && + (ENABLE == INTC_GetIntSrcState(uart->config->rx_int_src))) { hc32_uart_rx_irq_handler(uart); } - if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY)) && \ - (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_TX_EMPTY)) && \ - (ENABLE == INTC_GetIntSrcState(uart->config->tx_int_src))) + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY)) && + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_TX_EMPTY)) && + (ENABLE == INTC_GetIntSrcState(uart->config->tx_int_src))) { hc32_uart_tx_irq_handler(uart); } - if ((SET == USART_GetStatus(uart->config->Instance, (USART_FLAG_OVERRUN | \ - USART_FLAG_FRAME_ERR | USART_FLAG_PARITY_ERR))) && \ - (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && \ - (ENABLE == INTC_GetIntSrcState(uart->config->rxerr_int_src))) + if ((SET == USART_GetStatus(uart->config->Instance, (USART_FLAG_OVERRUN | + USART_FLAG_FRAME_ERR | USART_FLAG_PARITY_ERR))) && + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && + (ENABLE == INTC_GetIntSrcState(uart->config->rxerr_int_src))) { hc32_uart_rxerr_irq_handler(uart); } } #endif -#if defined (BSP_USING_UART1) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART1) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart1_rx_irq_handler(void) { /* enter interrupt */ @@ -860,8 +866,8 @@ static void hc32_uart1_rxerr_irq_handler(void) } #endif -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART1_TX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART1_TX_USING_DMA) static void hc32_uart1_tc_irq_handler(void) { /* enter interrupt */ @@ -873,7 +879,7 @@ static void hc32_uart1_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART1_TxComplete_Handler(void) { hc32_uart1_tc_irq_handler(); @@ -881,8 +887,8 @@ void USART1_TxComplete_Handler(void) #endif #endif /* BSP_UART1_TX_USING_DMA */ -#if defined (BSP_UART1_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_UART1_RX_USING_DMA) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart1_rxto_irq_handler(void) { /* enter interrupt */ @@ -908,7 +914,7 @@ static void hc32_uart1_dma_rx_irq_handler(void) #endif /* BSP_UART1_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART1_Handler(void) { /* enter interrupt */ @@ -922,8 +928,8 @@ void USART1_Handler(void) #endif #endif /* BSP_USING_UART1 */ -#if defined (BSP_USING_UART2) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART2) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart2_rx_irq_handler(void) { /* enter interrupt */ @@ -958,8 +964,8 @@ static void hc32_uart2_rxerr_irq_handler(void) } #endif -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART2_TX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART2_TX_USING_DMA) static void hc32_uart2_tc_irq_handler(void) { /* enter interrupt */ @@ -971,7 +977,7 @@ static void hc32_uart2_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART2_TxComplete_Handler(void) { hc32_uart2_tc_irq_handler(); @@ -979,8 +985,8 @@ void USART2_TxComplete_Handler(void) #endif #endif /* BSP_UART2_TX_USING_DMA */ -#if defined (BSP_UART2_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_UART2_RX_USING_DMA) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart2_rxto_irq_handler(void) { /* enter interrupt */ @@ -1006,7 +1012,7 @@ static void hc32_uart2_dma_rx_irq_handler(void) #endif /* BSP_UART2_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART2_Handler(void) { /* enter interrupt */ @@ -1020,8 +1026,8 @@ void USART2_Handler(void) #endif #endif /* BSP_USING_UART2 */ -#if defined (BSP_USING_UART3) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART3) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart3_rx_irq_handler(void) { /* enter interrupt */ @@ -1055,8 +1061,8 @@ static void hc32_uart3_rxerr_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART3_TX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART3_TX_USING_DMA) static void hc32_uart3_tc_irq_handler(void) { /* enter interrupt */ @@ -1069,7 +1075,7 @@ static void hc32_uart3_tc_irq_handler(void) } #endif /* BSP_UART3_TX_USING_DMA */ -#if defined (BSP_UART3_RX_USING_DMA) +#if defined(BSP_UART3_RX_USING_DMA) static void hc32_uart3_rxto_irq_handler(void) { /* enter interrupt */ @@ -1090,13 +1096,12 @@ static void hc32_uart3_dma_rx_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); - } #endif /* BSP_UART3_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#endif /* HC32F460, HC32F4A0, HC32F4A8 */ +#endif /* HC32F460, HC32F4A0, HC32F4A2, HC32F4A8, HC32F467 */ -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART3_Handler(void) { /* enter interrupt */ @@ -1110,8 +1115,8 @@ void USART3_Handler(void) #endif #endif /* BSP_USING_UART3 */ -#if defined (BSP_USING_UART4) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART4) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart4_rx_irq_handler(void) { /* enter interrupt */ @@ -1146,8 +1151,8 @@ static void hc32_uart4_rxerr_irq_handler(void) } #endif -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART4_TX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART4_TX_USING_DMA) static void hc32_uart4_tc_irq_handler(void) { /* enter interrupt */ @@ -1159,7 +1164,7 @@ static void hc32_uart4_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART4_TxComplete_Handler(void) { hc32_uart4_tc_irq_handler(); @@ -1167,8 +1172,8 @@ void USART4_TxComplete_Handler(void) #endif #endif /* BSP_UART4_TX_USING_DMA */ -#if defined (BSP_UART4_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A8) +#if defined(BSP_UART4_RX_USING_DMA) +#if defined(HC32F460) || defined(HC32F4A8) static void hc32_uart4_rxto_irq_handler(void) { /* enter interrupt */ @@ -1194,7 +1199,7 @@ static void hc32_uart4_dma_rx_irq_handler(void) #endif /* BSP_UART4_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART4_Handler(void) { /* enter interrupt */ @@ -1208,8 +1213,8 @@ void USART4_Handler(void) #endif #endif /* BSP_USING_UART4 */ -#if defined (BSP_USING_UART5) -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART5) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart5_rx_irq_handler(void) { /* enter interrupt */ @@ -1244,8 +1249,8 @@ static void hc32_uart5_rxerr_irq_handler(void) } #endif -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART5_TX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART5_TX_USING_DMA) static void hc32_uart5_tc_irq_handler(void) { /* enter interrupt */ @@ -1257,7 +1262,7 @@ static void hc32_uart5_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F448) || defined (HC32F472) +#if defined(HC32F448) || defined(HC32F472) void USART5_TxComplete_Handler(void) { hc32_uart5_tc_irq_handler(); @@ -1265,8 +1270,8 @@ void USART5_TxComplete_Handler(void) #endif #endif /* BSP_UART5_TX_USING_DMA */ -#if defined (BSP_UART5_RX_USING_DMA) -#if defined (HC32F4A8) +#if defined(BSP_UART5_RX_USING_DMA) +#if defined(HC32F4A8) static void hc32_uart5_rxto_irq_handler(void) { /* enter interrupt */ @@ -1292,7 +1297,7 @@ static void hc32_uart5_dma_rx_irq_handler(void) #endif /* BSP_UART5_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#if defined (HC32F448) || defined (HC32F472) +#if defined(HC32F448) || defined(HC32F472) void USART5_Handler(void) { /* enter interrupt */ @@ -1306,8 +1311,8 @@ void USART5_Handler(void) #endif #endif /* BSP_USING_UART5 */ -#if defined (BSP_USING_UART6) -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART6) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart6_rx_irq_handler(void) { /* enter interrupt */ @@ -1341,8 +1346,8 @@ static void hc32_uart6_rxerr_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART6_TX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART6_TX_USING_DMA) static void hc32_uart6_tc_irq_handler(void) { /* enter interrupt */ @@ -1355,7 +1360,7 @@ static void hc32_uart6_tc_irq_handler(void) } #endif /* BSP_UART6_TX_USING_DMA */ -#if defined (BSP_UART6_RX_USING_DMA) +#if defined(BSP_UART6_RX_USING_DMA) static void hc32_uart6_rxto_irq_handler(void) { /* enter interrupt */ @@ -1379,9 +1384,9 @@ static void hc32_uart6_dma_rx_irq_handler(void) } #endif /* BSP_UART6_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#endif /* HC32F4A0, HC32F4A8 */ +#endif /* HC32F4A0, HC32F4A2, HC32F4A8, HC32F467 */ -#if defined (HC32F448) || defined (HC32F472) +#if defined(HC32F448) || defined(HC32F472) void USART6_Handler(void) { /* enter interrupt */ @@ -1395,7 +1400,7 @@ void USART6_Handler(void) #endif #endif /* BSP_USING_UART6 */ -#if defined (BSP_USING_UART7) +#if defined(BSP_USING_UART7) static void hc32_uart7_rx_irq_handler(void) { /* enter interrupt */ @@ -1429,8 +1434,8 @@ static void hc32_uart7_rxerr_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART7_TX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART7_TX_USING_DMA) static void hc32_uart7_tc_irq_handler(void) { /* enter interrupt */ @@ -1443,7 +1448,7 @@ static void hc32_uart7_tc_irq_handler(void) } #endif /* BSP_UART7_TX_USING_DMA */ -#if defined (BSP_UART7_RX_USING_DMA) +#if defined(BSP_UART7_RX_USING_DMA) static void hc32_uart7_rxto_irq_handler(void) { /* enter interrupt */ @@ -1469,7 +1474,7 @@ static void hc32_uart7_dma_rx_irq_handler(void) #endif /* RT_SERIAL_USING_DMA */ #endif /* BSP_USING_UART7 */ -#if defined (BSP_USING_UART8) +#if defined(BSP_USING_UART8) static void hc32_uart8_rx_irq_handler(void) { /* enter interrupt */ @@ -1503,8 +1508,8 @@ static void hc32_uart8_rxerr_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART8_TX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART8_TX_USING_DMA) static void hc32_uart8_tc_irq_handler(void) { /* enter interrupt */ @@ -1517,7 +1522,7 @@ static void hc32_uart8_tc_irq_handler(void) } #endif /* BSP_UART8_TX_USING_DMA */ -#if defined (BSP_UART8_RX_USING_DMA) +#if defined(BSP_UART8_RX_USING_DMA) static void hc32_uart8_rxto_irq_handler(void) { /* enter interrupt */ @@ -1543,7 +1548,7 @@ static void hc32_uart8_dma_rx_irq_handler(void) #endif /* RT_SERIAL_USING_DMA */ #endif /* BSP_USING_UART8 */ -#if defined (BSP_USING_UART9) +#if defined(BSP_USING_UART9) static void hc32_uart9_rx_irq_handler(void) { /* enter interrupt */ @@ -1577,8 +1582,8 @@ static void hc32_uart9_rxerr_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART9_TX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART9_TX_USING_DMA) static void hc32_uart9_tc_irq_handler(void) { /* enter interrupt */ @@ -1591,7 +1596,7 @@ static void hc32_uart9_tc_irq_handler(void) } #endif /* BSP_UART9_TX_USING_DMA */ -#if defined (BSP_UART9_RX_USING_DMA) +#if defined(BSP_UART9_RX_USING_DMA) static void hc32_uart9_rxto_irq_handler(void) { /* enter interrupt */ @@ -1617,7 +1622,7 @@ static void hc32_uart9_dma_rx_irq_handler(void) #endif /* RT_SERIAL_USING_DMA */ #endif /* BSP_USING_UART9 */ -#if defined (BSP_USING_UART10) +#if defined(BSP_USING_UART10) static void hc32_uart10_rx_irq_handler(void) { /* enter interrupt */ @@ -1651,8 +1656,8 @@ static void hc32_uart10_rxerr_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART10_TX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART10_TX_USING_DMA) static void hc32_uart10_tc_irq_handler(void) { /* enter interrupt */ @@ -1665,7 +1670,7 @@ static void hc32_uart10_tc_irq_handler(void) } #endif /* BSP_UART10_TX_USING_DMA */ -#if defined (BSP_UART10_RX_USING_DMA) +#if defined(BSP_UART10_RX_USING_DMA) static void hc32_uart10_rxto_irq_handler(void) { /* enter interrupt */ @@ -1706,7 +1711,7 @@ static void hc32_uart_get_dma_info(void) static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG; uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler; #endif uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout; @@ -1729,7 +1734,7 @@ static void hc32_uart_get_dma_info(void) static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; static struct hc32_uart_rxto uart2_rx_timeout = UART2_RXTO_CONFIG; uart2_dma_rx.irq_callback = hc32_uart2_dma_rx_irq_handler; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) uart2_rx_timeout.irq_callback = hc32_uart2_rxto_irq_handler; #endif uart_config[UART2_INDEX].rx_timeout = &uart2_rx_timeout; @@ -1773,7 +1778,7 @@ static void hc32_uart_get_dma_info(void) static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG; uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler; -#if defined (HC32F460) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A8) uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler; #endif uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout; @@ -1796,7 +1801,7 @@ static void hc32_uart_get_dma_info(void) static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; static struct hc32_uart_rxto uart5_rx_timeout = UART5_RXTO_CONFIG; uart5_dma_rx.irq_callback = hc32_uart5_dma_rx_irq_handler; -#if defined (HC32F4A8) +#if defined(HC32F4A8) uart5_rx_timeout.irq_callback = hc32_uart5_rxto_irq_handler; #endif uart_config[UART5_INDEX].rx_timeout = &uart5_rx_timeout; @@ -1918,7 +1923,7 @@ static void hc32_uart_get_dma_info(void) #endif } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) /** * @brief This function gets uart irq handle. * @param None @@ -1979,8 +1984,7 @@ static void hc32_get_uart_callback(void) } #endif -static const struct rt_uart_ops hc32_uart_ops = -{ +static const struct rt_uart_ops hc32_uart_ops = { .configure = hc32_configure, .control = hc32_control, .putc = hc32_putc, @@ -1995,16 +1999,16 @@ int rt_hw_usart_init(void) struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; hc32_uart_get_dma_info(); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) hc32_get_uart_callback(); #endif for (int i = 0; i < obj_num; i++) { /* init UART object */ - uart_obj[i].serial.ops = &hc32_uart_ops; + uart_obj[i].serial.ops = &hc32_uart_ops; uart_obj[i].serial.config = config; uart_obj[i].config = &uart_config[i]; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) /* register the handle */ hc32_install_irq_handler(&uart_config[i].rxerr_irq.irq_config, uart_config[i].rxerr_irq.irq_callback, RT_FALSE); #endif @@ -2012,7 +2016,7 @@ int rt_hw_usart_init(void) if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) { hc32_install_irq_handler(&uart_config[i].dma_rx->irq_config, uart_config[i].dma_rx->irq_callback, RT_FALSE); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) hc32_install_irq_handler(&uart_config[i].rx_timeout->irq_config, uart_config[i].rx_timeout->irq_callback, RT_FALSE); #endif } @@ -2024,7 +2028,7 @@ int rt_hw_usart_init(void) /* register UART device */ result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, - (RT_DEVICE_FLAG_RDWR | + (RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_INT_TX | uart_obj[i].uart_dma_flag), diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart.h b/bsp/hc32/libraries/hc32_drivers/drv_usart.h index 2b9b0cd319c..0fd59551f2a 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart.h @@ -21,8 +21,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -31,48 +30,48 @@ extern "C" struct hc32_uart_irq_config { struct hc32_irq_config irq_config; - func_ptr_t irq_callback; + func_ptr_t irq_callback; }; /* HC32 config Rx timeout */ struct hc32_uart_rxto { - CM_TMR0_TypeDef *TMR0_Instance; - rt_uint32_t channel; - rt_uint32_t clock; - rt_size_t timeout_bits; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) - struct hc32_irq_config irq_config; - func_ptr_t irq_callback; + CM_TMR0_TypeDef *TMR0_Instance; + rt_uint32_t channel; + rt_uint32_t clock; + rt_size_t timeout_bits; +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; #endif }; /* HC32 config uart class */ struct hc32_uart_config { - const char *name; - CM_USART_TypeDef *Instance; - rt_uint32_t clock; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) + const char *name; + CM_USART_TypeDef *Instance; + rt_uint32_t clock; +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) struct hc32_uart_irq_config rxerr_irq; struct hc32_uart_irq_config rx_irq; struct hc32_uart_irq_config tx_irq; -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) - IRQn_Type irq_num; - en_int_src_t rxerr_int_src; - en_int_src_t tx_int_src; - en_int_src_t rx_int_src; +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) + IRQn_Type irq_num; + en_int_src_t rxerr_int_src; + en_int_src_t tx_int_src; + en_int_src_t rx_int_src; #ifdef RT_SERIAL_USING_DMA - en_int_src_t rxto_int_src; + en_int_src_t rxto_int_src; #endif #endif #ifdef RT_SERIAL_USING_DMA - struct hc32_uart_rxto *rx_timeout; - stc_dma_llp_descriptor_t llp_desc[2U]; - struct dma_config *dma_rx; + struct hc32_uart_rxto *rx_timeout; + stc_dma_llp_descriptor_t llp_desc[2U]; + struct dma_config *dma_rx; struct hc32_uart_irq_config *tc_irq; - struct dma_config *dma_tx; + struct dma_config *dma_tx; #endif }; @@ -81,9 +80,9 @@ struct hc32_uart { struct hc32_uart_config *config; #ifdef RT_SERIAL_USING_DMA - rt_size_t dma_rx_remaining_cnt; + rt_size_t dma_rx_remaining_cnt; #endif - rt_uint16_t uart_dma_flag; + rt_uint16_t uart_dma_flag; struct rt_serial_device serial; }; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c index 7d6d5adfd52..8f0d911507a 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.c @@ -9,6 +9,8 @@ * 2024-02-06 CDT support HC32F448 * 2024-04-15 CDT support HC32F472 * 2025-07-16 CDT Support HC32F334 + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ /******************************************************************************* @@ -20,10 +22,10 @@ #ifdef RT_USING_SERIAL_V2 -#if defined (BSP_USING_UART1) || defined (BSP_USING_UART2) || defined (BSP_USING_UART3) || \ - defined (BSP_USING_UART4) || defined (BSP_USING_UART5) || defined (BSP_USING_UART6) || \ - defined (BSP_USING_UART7) || defined (BSP_USING_UART8) || defined (BSP_USING_UART9) || \ - defined (BSP_USING_UART10) +#if defined(BSP_USING_UART1) || defined(BSP_USING_UART2) || defined(BSP_USING_UART3) || \ + defined(BSP_USING_UART4) || defined(BSP_USING_UART5) || defined(BSP_USING_UART6) || \ + defined(BSP_USING_UART7) || defined(BSP_USING_UART8) || defined(BSP_USING_UART9) || \ + defined(BSP_USING_UART10) #include "drv_usart_v2.h" #include "board_config.h" @@ -35,31 +37,32 @@ /******************************************************************************* * Local pre-processor symbols/macros ('#define') ******************************************************************************/ -#define DMA_CH_REG(reg_base, ch) \ +#define DMA_CH_REG(reg_base, ch) \ (*(volatile uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) -#define DMA_TRANS_SET_CNT(unit, ch) \ - (READ_REG32(DMA_CH_REG((unit)->DTCTL0,(ch))) >> DMA_DTCTL_CNT_POS) +#define DMA_TRANS_SET_CNT(unit, ch) \ + (READ_REG32(DMA_CH_REG((unit)->DTCTL0, (ch))) >> DMA_DTCTL_CNT_POS) -#define DMA_TRANS_CNT(unit, ch) \ +#define DMA_TRANS_CNT(unit, ch) \ (READ_REG32(DMA_CH_REG((unit)->MONDTCTL0, (ch))) >> DMA_DTCTL_CNT_POS) -#define UART_BAUDRATE_ERR_MAX (0.025F) +#define UART_BAUDRATE_ERR_MAX (0.025F) -#if defined (HC32F460) - #define FCG_USART_CLK FCG_Fcg1PeriphClockCmd +#if defined(HC32F460) +#define FCG_USART_CLK FCG_Fcg1PeriphClockCmd -#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) - #define FCG_USART_CLK FCG_Fcg3PeriphClockCmd +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) +#define FCG_USART_CLK FCG_Fcg3PeriphClockCmd #endif -#define FCG_TMR0_CLK FCG_Fcg2PeriphClockCmd -#define FCG_DMA_CLK FCG_Fcg0PeriphClockCmd -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) - #define USART_MAX_CLK_DIV USART_CLK_DIV64 -#elif defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) - #define USART_MAX_CLK_DIV USART_CLK_DIV1024 +#define FCG_TMR0_CLK FCG_Fcg2PeriphClockCmd +#define FCG_DMA_CLK FCG_Fcg0PeriphClockCmd +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) +#define USART_MAX_CLK_DIV USART_CLK_DIV64 +#elif defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) +#define USART_MAX_CLK_DIV USART_CLK_DIV1024 #endif /******************************************************************************* @@ -71,7 +74,7 @@ extern rt_err_t rt_hw_board_uart_init(CM_USART_TypeDef *USARTx); * Local function prototypes ('static') ******************************************************************************/ #ifdef RT_SERIAL_USING_DMA - static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); #endif /******************************************************************************* @@ -111,8 +114,7 @@ enum #endif }; -static struct hc32_uart_config uart_config[] = -{ +static struct hc32_uart_config uart_config[] = { #ifdef BSP_USING_UART1 UART1_CONFIG, #endif @@ -145,7 +147,7 @@ static struct hc32_uart_config uart_config[] = #endif }; -static struct hc32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0}; +static struct hc32_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = { 0 }; /******************************************************************************* * Function implementation - global ('extern') and local ('static') @@ -163,15 +165,15 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co uart_init.u32OverSampleBit = USART_OVER_SAMPLE_8BIT; uart_init.u32Baudrate = cfg->baud_rate; uart_init.u32ClockSrc = USART_CLK_SRC_INTERNCLK; -#if defined (HC32F4A0) - if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ - (CM_USART6 == uart->config->Instance) || (CM_USART7 == uart->config->Instance)) -#elif defined (HC32F460) || defined (HC32F334) - if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ - (CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance)) -#elif defined (HC32F448) || defined (HC32F472) - if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || \ - (CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance)) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) + if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || + (CM_USART6 == uart->config->Instance) || (CM_USART7 == uart->config->Instance)) +#elif defined(HC32F460) || defined(HC32F334) + if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || + (CM_USART3 == uart->config->Instance) || (CM_USART4 == uart->config->Instance)) +#elif defined(HC32F448) || defined(HC32F472) + if ((CM_USART1 == uart->config->Instance) || (CM_USART2 == uart->config->Instance) || + (CM_USART4 == uart->config->Instance) || (CM_USART5 == uart->config->Instance)) #endif { uart_init.u32CKOutput = USART_CK_OUTPUT_ENABLE; @@ -227,7 +229,8 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co { uart_init.u32FirstBit = USART_FIRST_BIT_MSB; } -#if defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) switch (cfg->flowcontrol) { case RT_SERIAL_FLOWCONTROL_NONE: @@ -259,7 +262,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co USART_UART_Init(uart->config->Instance, &uart_init, NULL); for (u32Div = 0UL; u32Div <= USART_MAX_CLK_DIV; u32Div++) { -#if defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) if (u32Div == (USART_CLK_DIV64 + 1U)) { u32Div = USART_CLK_DIV128; @@ -267,7 +270,7 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co #endif USART_SetClockDiv(uart->config->Instance, u32Div); if ((LL_OK == USART_SetBaudrate(uart->config->Instance, uart_init.u32Baudrate, &f32Error)) && - ((-UART_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= UART_BAUDRATE_ERR_MAX))) + ((-UART_BAUDRATE_ERR_MAX <= f32Error) && (f32Error <= UART_BAUDRATE_ERR_MAX))) { i32Ret = LL_OK; break; @@ -279,9 +282,9 @@ static rt_err_t hc32_configure(struct rt_serial_device *serial, struct serial_co } /* Enable error interrupt */ -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) NVIC_EnableIRQ(uart->config->rxerr_irq.irq_config.irq_num); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) INTC_IntSrcCmd(uart->config->tx_int_src, ENABLE); INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); INTC_IntSrcCmd(uart->config->rxerr_int_src, ENABLE); @@ -331,22 +334,22 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg case RT_DEVICE_CTRL_CLR_INT: if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) NVIC_DisableIRQ(uart->config->rx_irq.irq_config.irq_num); INTC_IrqSignOut(uart->config->rx_irq.irq_config.irq_num); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); #endif } else if (RT_DEVICE_FLAG_INT_TX == ctrl_arg) { -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) NVIC_DisableIRQ(uart->config->tx_irq.irq_config.irq_num); NVIC_DisableIRQ(uart->config->tc_irq.irq_config.irq_num); USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE); INTC_IrqSignOut(uart->config->tx_irq.irq_config.irq_num); INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num); -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) NVIC_DisableIRQ(uart->config->tc_irq.irq_config.irq_num); INTC_IrqSignOut(uart->config->tc_irq.irq_config.irq_num); USART_FuncCmd(uart->config->Instance, (USART_INT_TX_EMPTY | USART_INT_TX_CPLT), DISABLE); @@ -366,7 +369,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg break; /* Enable interrupt */ case RT_DEVICE_CTRL_SET_INT: -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) { hc32_install_irq_handler(&uart->config->rx_irq.irq_config, uart->config->rx_irq.irq_callback, RT_TRUE); @@ -381,7 +384,7 @@ static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg USART_FuncCmd(uart->config->Instance, USART_TX, DISABLE); USART_FuncCmd(uart->config->Instance, USART_TX | USART_INT_TX_EMPTY, ENABLE); } -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) /* NVIC config */ if (RT_DEVICE_FLAG_INT_RX == ctrl_arg) { @@ -435,7 +438,8 @@ static int hc32_putc(struct rt_serial_device *serial, char c) RT_ASSERT(RT_NULL != uart->config->Instance); /* Polling mode. */ - while (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_CPLT) != SET); + while (USART_GetStatus(uart->config->Instance, USART_FLAG_TX_CPLT) != SET) + ; USART_WriteData(uart->config->Instance, c); return 1; @@ -458,10 +462,10 @@ static int hc32_getc(struct rt_serial_device *serial) return ch; } -static rt_ssize_t hc32_transmit(struct rt_serial_device *serial, - rt_uint8_t *buf, - rt_size_t size, - rt_uint32_t tx_flag) +static rt_ssize_t hc32_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + rt_uint32_t tx_flag) { struct hc32_uart *uart; #ifdef RT_SERIAL_USING_DMA @@ -574,9 +578,9 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) RT_ASSERT(RT_NULL != uart->config->Instance); TMR0_Instance = uart->config->rx_timeout->TMR0_Instance; - ch = uart->config->rx_timeout->channel; - rtb = uart->config->rx_timeout->timeout_bits; -#if defined (HC32F460) || defined (HC32F334) + ch = uart->config->rx_timeout->channel; + rtb = uart->config->rx_timeout->timeout_bits; +#if defined(HC32F460) || defined(HC32F334) if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance)) { RT_ASSERT(TMR0_CH_A == ch); @@ -585,7 +589,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { RT_ASSERT(TMR0_CH_B == ch); } -#elif defined (HC32F4A0) +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) if ((CM_USART1 == uart->config->Instance) || (CM_USART6 == uart->config->Instance)) { RT_ASSERT(TMR0_CH_A == ch); @@ -594,7 +598,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { RT_ASSERT(TMR0_CH_B == ch); } -#elif defined (HC32F448) || defined (HC32F472) +#elif defined(HC32F448) || defined(HC32F472) if ((CM_USART1 == uart->config->Instance) || (CM_USART4 == uart->config->Instance)) { RT_ASSERT(TMR0_CH_A == ch); @@ -603,9 +607,9 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { RT_ASSERT(TMR0_CH_B == ch); } -#elif defined (HC32F4A8) +#elif defined(HC32F4A8) if ((CM_USART1 == uart->config->Instance) || (CM_USART3 == uart->config->Instance) || (CM_USART5 == uart->config->Instance) || - (CM_USART6 == uart->config->Instance) || (CM_USART9 == uart->config->Instance)) + (CM_USART6 == uart->config->Instance) || (CM_USART9 == uart->config->Instance)) { RT_ASSERT(TMR0_CH_A == ch); } @@ -616,7 +620,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) } #endif -#if defined (HC32F4A8) +#if defined(HC32F4A8) if ((CM_TMR0_4 == uart->config->rx_timeout->TMR0_Instance) || (CM_TMR0_5 == uart->config->rx_timeout->TMR0_Instance)) { FCG_Fcg3PeriphClockCmd(uart->config->rx_timeout->clock, ENABLE); @@ -625,7 +629,8 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE); } -#elif defined (HC32F460) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || \ + defined(HC32F334) || defined(HC32F467) FCG_TMR0_CLK(uart->config->rx_timeout->clock, ENABLE); #endif @@ -642,8 +647,8 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) { alpha = 5UL; } - else if ((TMR0_CLK_DIV4 == stcTmr0Init.u32ClockDiv) || \ - (TMR0_CLK_DIV8 == stcTmr0Init.u32ClockDiv) || \ + else if ((TMR0_CLK_DIV4 == stcTmr0Init.u32ClockDiv) || + (TMR0_CLK_DIV8 == stcTmr0Init.u32ClockDiv) || (TMR0_CLK_DIV16 == stcTmr0Init.u32ClockDiv)) { alpha = 3UL; @@ -653,7 +658,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) alpha = 2UL; } /* TMR0_CMPAR calculation formula: CMPAR = (RTB / (2 ^ CKDIVA)) - alpha */ - ckdiv = 1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS); + ckdiv = 1UL << (stcTmr0Init.u32ClockDiv >> TMR0_BCONR_CKDIVA_POS); cmp_val = ((rtb + ckdiv - 1UL) / ckdiv) - alpha; DDL_ASSERT(cmp_val <= 0xFFFFUL); stcTmr0Init.u16CompareValue = (uint16_t)(cmp_val); @@ -663,7 +668,7 @@ static void hc32_uart_rx_timeout(struct rt_serial_device *serial) /* Clear compare flag */ TMR0_ClearStatus(TMR0_Instance, (uint32_t)(0x1UL << (ch * TMR0_STFLR_CMFB_POS))); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) NVIC_EnableIRQ(uart->config->rx_timeout->irq_config.irq_num); #endif USART_ClearStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT); @@ -678,7 +683,7 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) struct dma_config *uart_dma; RT_ASSERT(RT_NULL != serial); - RT_ASSERT(RT_NULL == ((serial->config.dma_ping_bufsz) & ((RT_ALIGN_SIZE) - 1))); + RT_ASSERT(RT_NULL == ((serial->config.dma_ping_bufsz) & ((RT_ALIGN_SIZE)-1))); uart = rt_container_of(serial, struct hc32_uart, serial); RT_ASSERT(RT_NULL != uart->config->Instance); @@ -692,7 +697,7 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) RT_ASSERT(RT_NULL != uart->config->dma_rx->Instance); RT_ASSERT(RT_NULL != ptr); -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) INTC_IntSrcCmd(uart->config->rx_int_src, DISABLE); #endif @@ -705,39 +710,39 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) /* Initialize DMA */ DMA_StructInit(&dma_init); - dma_init.u32IntEn = DMA_INT_ENABLE; - dma_init.u32SrcAddr = (uint32_t)(&uart->config->Instance->RDR); - dma_init.u32DestAddr = (uint32_t)ptr; - dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; - dma_init.u32BlockSize = 1UL; - dma_init.u32TransCount = trans_count; - dma_init.u32SrcAddrInc = DMA_SRC_ADDR_FIX; + dma_init.u32IntEn = DMA_INT_ENABLE; + dma_init.u32SrcAddr = (uint32_t)(&uart->config->Instance->RDR); + dma_init.u32DestAddr = (uint32_t)ptr; + dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; + dma_init.u32BlockSize = 1UL; + dma_init.u32TransCount = trans_count; + dma_init.u32SrcAddrInc = DMA_SRC_ADDR_FIX; dma_init.u32DestAddrInc = DMA_DEST_ADDR_INC; DMA_Init(uart_dma->Instance, uart_dma->channel, &dma_init); /* Initialize LLP */ - llp_init.u32State = DMA_LLP_ENABLE; - llp_init.u32Mode = DMA_LLP_WAIT; - llp_init.u32Addr = (uint32_t)&uart->config->llp_desc; + llp_init.u32State = DMA_LLP_ENABLE; + llp_init.u32Mode = DMA_LLP_WAIT; + llp_init.u32Addr = (uint32_t)&uart->config->llp_desc; DMA_LlpInit(uart_dma->Instance, uart_dma->channel, &llp_init); /* Configure LLP descriptor */ - uart->config->llp_desc[0U].SARx = dma_init.u32SrcAddr; - uart->config->llp_desc[0U].DARx = dma_init.u32DestAddr + ((serial->config.dma_ping_bufsz <= 1UL) ? 0UL : dma_init.u32TransCount); - uart->config->llp_desc[0U].DTCTLx = (((serial->config.dma_ping_bufsz <= 1U) ? dma_init.u32TransCount : (serial->config.dma_ping_bufsz - dma_init.u32TransCount)) << DMA_DTCTL_CNT_POS) | \ + uart->config->llp_desc[0U].SARx = dma_init.u32SrcAddr; + uart->config->llp_desc[0U].DARx = dma_init.u32DestAddr + ((serial->config.dma_ping_bufsz <= 1UL) ? 0UL : dma_init.u32TransCount); + uart->config->llp_desc[0U].DTCTLx = (((serial->config.dma_ping_bufsz <= 1U) ? dma_init.u32TransCount : (serial->config.dma_ping_bufsz - dma_init.u32TransCount)) << DMA_DTCTL_CNT_POS) | (dma_init.u32BlockSize << DMA_DTCTL_BLKSIZE_POS); - uart->config->llp_desc[0U].LLPx = (serial->config.dma_ping_bufsz <= 1U) ? (uint32_t)&uart->config->llp_desc[0U] : (uint32_t)&uart->config->llp_desc[1U]; - uart->config->llp_desc[0U].CHCTLx = (dma_init.u32SrcAddrInc | dma_init.u32DestAddrInc | dma_init.u32DataWidth | \ - llp_init.u32State | llp_init.u32Mode | dma_init.u32IntEn); + uart->config->llp_desc[0U].LLPx = (serial->config.dma_ping_bufsz <= 1U) ? (uint32_t)&uart->config->llp_desc[0U] : (uint32_t)&uart->config->llp_desc[1U]; + uart->config->llp_desc[0U].CHCTLx = (dma_init.u32SrcAddrInc | dma_init.u32DestAddrInc | dma_init.u32DataWidth | + llp_init.u32State | llp_init.u32Mode | dma_init.u32IntEn); if (serial->config.dma_ping_bufsz > 1UL) { - uart->config->llp_desc[1U].SARx = dma_init.u32SrcAddr; - uart->config->llp_desc[1U].DARx = dma_init.u32DestAddr; + uart->config->llp_desc[1U].SARx = dma_init.u32SrcAddr; + uart->config->llp_desc[1U].DARx = dma_init.u32DestAddr; uart->config->llp_desc[1U].DTCTLx = (dma_init.u32TransCount << DMA_DTCTL_CNT_POS) | (dma_init.u32BlockSize << DMA_DTCTL_BLKSIZE_POS); - uart->config->llp_desc[1U].LLPx = (uint32_t)&uart->config->llp_desc[0U]; - uart->config->llp_desc[1U].CHCTLx = (dma_init.u32SrcAddrInc | dma_init.u32DestAddrInc | dma_init.u32DataWidth | \ - llp_init.u32State | llp_init.u32Mode | dma_init.u32IntEn); + uart->config->llp_desc[1U].LLPx = (uint32_t)&uart->config->llp_desc[0U]; + uart->config->llp_desc[1U].CHCTLx = (dma_init.u32SrcAddrInc | dma_init.u32DestAddrInc | dma_init.u32DataWidth | + llp_init.u32State | llp_init.u32Mode | dma_init.u32IntEn); } /* Enable DMA interrupt */ @@ -758,13 +763,13 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) /* Initialize DMA */ DMA_StructInit(&dma_init); - dma_init.u32IntEn = DMA_INT_DISABLE; - dma_init.u32SrcAddr = 0UL; - dma_init.u32DestAddr = (uint32_t)(&uart->config->Instance->TDR); - dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; - dma_init.u32BlockSize = 1UL; - dma_init.u32TransCount = 0UL; - dma_init.u32SrcAddrInc = DMA_SRC_ADDR_INC; + dma_init.u32IntEn = DMA_INT_DISABLE; + dma_init.u32SrcAddr = 0UL; + dma_init.u32DestAddr = (uint32_t)(&uart->config->Instance->TDR); + dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; + dma_init.u32BlockSize = 1UL; + dma_init.u32TransCount = 0UL; + dma_init.u32SrcAddrInc = DMA_SRC_ADDR_INC; dma_init.u32DestAddrInc = DMA_DEST_ADDR_FIX; DMA_Init(uart_dma->Instance, uart_dma->channel, &dma_init); @@ -776,10 +781,10 @@ static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) } } -#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \ - defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) || defined (BSP_UART6_RX_USING_DMA) || \ - defined (BSP_UART7_RX_USING_DMA) || defined (BSP_UART8_RX_USING_DMA) || defined (BSP_UART9_RX_USING_DMA) || \ - defined (BSP_UART10_RX_USING_DMA) +#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \ + defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART5_RX_USING_DMA) || defined(BSP_UART6_RX_USING_DMA) || \ + defined(BSP_UART7_RX_USING_DMA) || defined(BSP_UART8_RX_USING_DMA) || defined(BSP_UART9_RX_USING_DMA) || \ + defined(BSP_UART10_RX_USING_DMA) static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart) { rt_base_t level; @@ -837,49 +842,49 @@ static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart) #endif #endif -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) static void hc32_usart_handler(struct hc32_uart *uart) { RT_ASSERT(RT_NULL != uart); -#if defined (RT_SERIAL_USING_DMA) - if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT)) && \ - (ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && \ - (ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src))) +#if defined(RT_SERIAL_USING_DMA) + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_TIMEOUT)) && + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_RX_TIMEOUT)) && + (ENABLE == INTC_GetIntSrcState(uart->config->rxto_int_src))) { -#if defined (BSP_UART1_RX_USING_DMA) || defined (BSP_UART2_RX_USING_DMA) || defined (BSP_UART3_RX_USING_DMA) || \ - defined (BSP_UART4_RX_USING_DMA) || defined (BSP_UART5_RX_USING_DMA) +#if defined(BSP_UART1_RX_USING_DMA) || defined(BSP_UART2_RX_USING_DMA) || defined(BSP_UART3_RX_USING_DMA) || \ + defined(BSP_UART4_RX_USING_DMA) || defined(BSP_UART5_RX_USING_DMA) hc32_uart_rxto_irq_handler(uart); #endif } #endif - if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_FULL)) && \ - (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && \ - (ENABLE == INTC_GetIntSrcState(uart->config->rx_int_src))) + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_RX_FULL)) && + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && + (ENABLE == INTC_GetIntSrcState(uart->config->rx_int_src))) { hc32_uart_rx_irq_handler(uart); } - if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY)) && \ - (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_TX_EMPTY)) && \ - (ENABLE == INTC_GetIntSrcState(uart->config->tx_int_src))) + if ((SET == USART_GetStatus(uart->config->Instance, USART_FLAG_TX_EMPTY)) && + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_TX_EMPTY)) && + (ENABLE == INTC_GetIntSrcState(uart->config->tx_int_src))) { hc32_uart_tx_irq_handler(uart); } - if ((SET == USART_GetStatus(uart->config->Instance, (USART_FLAG_OVERRUN | \ - USART_FLAG_FRAME_ERR | USART_FLAG_PARITY_ERR))) && \ - (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && \ - (ENABLE == INTC_GetIntSrcState(uart->config->rxerr_int_src))) + if ((SET == USART_GetStatus(uart->config->Instance, (USART_FLAG_OVERRUN | + USART_FLAG_FRAME_ERR | USART_FLAG_PARITY_ERR))) && + (ENABLE == USART_GetFuncState(uart->config->Instance, USART_INT_RX)) && + (ENABLE == INTC_GetIntSrcState(uart->config->rxerr_int_src))) { hc32_uart_rxerr_irq_handler(uart); } } #endif -#if defined (BSP_USING_UART1) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART1) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart1_rx_irq_handler(void) { /* enter interrupt */ @@ -925,9 +930,9 @@ static void hc32_uart1_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART1_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART1_RX_USING_DMA) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart1_rxto_irq_handler(void) { /* enter interrupt */ @@ -953,7 +958,7 @@ static void hc32_uart1_dma_rx_irq_handler(void) #endif /* BSP_UART1_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART1_Handler(void) { /* enter interrupt */ @@ -978,8 +983,8 @@ void USART1_TxComplete_Handler(void) #endif #endif /* BSP_USING_UART1 */ -#if defined (BSP_USING_UART2) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART2) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart2_rx_irq_handler(void) { /* enter interrupt */ @@ -1025,9 +1030,9 @@ static void hc32_uart2_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART2_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART2_RX_USING_DMA) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart2_rxto_irq_handler(void) { /* enter interrupt */ @@ -1053,7 +1058,7 @@ static void hc32_uart2_dma_rx_irq_handler(void) #endif /* BSP_UART2_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART2_Handler(void) { /* enter interrupt */ @@ -1078,8 +1083,8 @@ void USART2_TxComplete_Handler(void) #endif #endif /* BSP_USING_UART2 */ -#if defined (BSP_USING_UART3) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART3) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart3_rx_irq_handler(void) { /* enter interrupt */ @@ -1125,9 +1130,9 @@ static void hc32_uart3_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART3_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART3_RX_USING_DMA) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart3_rxto_irq_handler(void) { /* enter interrupt */ @@ -1148,13 +1153,12 @@ static void hc32_uart3_dma_rx_irq_handler(void) /* leave interrupt */ rt_interrupt_leave(); - } #endif #endif /* BSP_UART3_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART3_Handler(void) { /* enter interrupt */ @@ -1179,8 +1183,8 @@ void USART3_TxComplete_Handler(void) #endif #endif /* BSP_USING_UART3 */ -#if defined (BSP_USING_UART4) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART4) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart4_rx_irq_handler(void) { /* enter interrupt */ @@ -1226,9 +1230,9 @@ static void hc32_uart4_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART4_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A8) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART4_RX_USING_DMA) +#if defined(HC32F460) || defined(HC32F4A8) static void hc32_uart4_rxto_irq_handler(void) { /* enter interrupt */ @@ -1254,7 +1258,7 @@ static void hc32_uart4_dma_rx_irq_handler(void) #endif /* BSP_UART4_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#if defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#if defined(HC32F448) || defined(HC32F472) || defined(HC32F334) void USART4_Handler(void) { /* enter interrupt */ @@ -1279,9 +1283,9 @@ void USART4_TxComplete_Handler(void) #endif #endif /* BSP_USING_UART4 */ -#if defined (BSP_USING_UART5) -#if defined (HC32F4A0) || defined (HC32F4A8) -#if defined (HC32F4A8) +#if defined(BSP_USING_UART5) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) +#if defined(HC32F4A8) static void hc32_uart5_rxto_irq_handler(void) { /* enter interrupt */ @@ -1339,9 +1343,9 @@ static void hc32_uart5_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (HC32F448) || defined (HC32F472) -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART5_RX_USING_DMA) +#if defined(HC32F448) || defined(HC32F472) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART5_RX_USING_DMA) static void hc32_uart5_dma_rx_irq_handler(void) { /* enter interrupt */ @@ -1379,8 +1383,8 @@ void USART5_TxComplete_Handler(void) #endif #endif /* BSP_USING_UART5 */ -#if defined (BSP_USING_UART6) -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(BSP_USING_UART6) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) static void hc32_uart6_rx_irq_handler(void) { /* enter interrupt */ @@ -1426,9 +1430,9 @@ static void hc32_uart6_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART6_RX_USING_DMA) -#if defined (HC32F460) || defined (HC32F4A0) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART6_RX_USING_DMA) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) static void hc32_uart6_rxto_irq_handler(void) { /* enter interrupt */ @@ -1454,7 +1458,7 @@ static void hc32_uart6_dma_rx_irq_handler(void) #endif /* BSP_UART6_RX_USING_DMA */ #endif /* RT_SERIAL_USING_DMA */ -#if defined (HC32F448) || defined (HC32F472) +#if defined(HC32F448) || defined(HC32F472) void USART6_Handler(void) { /* enter interrupt */ @@ -1479,7 +1483,7 @@ void USART6_TxComplete_Handler(void) #endif #endif /* BSP_USING_UART6 */ -#if defined (BSP_USING_UART7) +#if defined(BSP_USING_UART7) static void hc32_uart7_rx_irq_handler(void) { /* enter interrupt */ @@ -1524,8 +1528,8 @@ static void hc32_uart7_tc_irq_handler(void) rt_interrupt_leave(); } -#if defined (RT_SERIAL_USING_DMA) -#if defined (BSP_UART7_RX_USING_DMA) +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART7_RX_USING_DMA) static void hc32_uart7_rxto_irq_handler(void) { /* enter interrupt */ @@ -1551,7 +1555,7 @@ static void hc32_uart7_dma_rx_irq_handler(void) #endif /* RT_SERIAL_USING_DMA */ #endif /* BSP_USING_UART7 */ -#if defined (BSP_USING_UART8) +#if defined(BSP_USING_UART8) static void hc32_uart8_rx_irq_handler(void) { /* enter interrupt */ @@ -1597,7 +1601,7 @@ static void hc32_uart8_tc_irq_handler(void) } #endif /* BSP_USING_UART8 */ -#if defined (BSP_USING_UART9) +#if defined(BSP_USING_UART9) static void hc32_uart9_rx_irq_handler(void) { /* enter interrupt */ @@ -1643,7 +1647,7 @@ static void hc32_uart9_tc_irq_handler(void) } #endif /* BSP_USING_UART9 */ -#if defined (BSP_USING_UART10) +#if defined(BSP_USING_UART10) static void hc32_uart10_rx_irq_handler(void) { /* enter interrupt */ @@ -1710,7 +1714,7 @@ static void hc32_uart_get_info(void) static struct dma_config uart1_dma_rx = UART1_DMA_RX_CONFIG; static struct hc32_uart_rxto uart1_rx_timeout = UART1_RXTO_CONFIG; uart1_dma_rx.irq_callback = hc32_uart1_dma_rx_irq_handler; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) uart1_rx_timeout.irq_callback = hc32_uart1_rxto_irq_handler; #endif uart_config[UART1_INDEX].rx_timeout = &uart1_rx_timeout; @@ -1734,7 +1738,7 @@ static void hc32_uart_get_info(void) static struct dma_config uart2_dma_rx = UART2_DMA_RX_CONFIG; static struct hc32_uart_rxto uart2_rx_timeout = UART2_RXTO_CONFIG; uart2_dma_rx.irq_callback = hc32_uart2_dma_rx_irq_handler; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) uart2_rx_timeout.irq_callback = hc32_uart2_rxto_irq_handler; #endif uart_config[UART2_INDEX].rx_timeout = &uart2_rx_timeout; @@ -1780,7 +1784,7 @@ static void hc32_uart_get_info(void) static struct dma_config uart4_dma_rx = UART4_DMA_RX_CONFIG; static struct hc32_uart_rxto uart4_rx_timeout = UART4_RXTO_CONFIG; uart4_dma_rx.irq_callback = hc32_uart4_dma_rx_irq_handler; -#if defined (HC32F460) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A8) uart4_rx_timeout.irq_callback = hc32_uart4_rxto_irq_handler; #endif uart_config[UART4_INDEX].rx_timeout = &uart4_rx_timeout; @@ -1804,7 +1808,7 @@ static void hc32_uart_get_info(void) static struct dma_config uart5_dma_rx = UART5_DMA_RX_CONFIG; static struct hc32_uart_rxto uart5_rx_timeout = UART5_RXTO_CONFIG; uart5_dma_rx.irq_callback = hc32_uart5_dma_rx_irq_handler; -#if defined (HC32F4A8) +#if defined(HC32F4A8) uart5_rx_timeout.irq_callback = hc32_uart5_rxto_irq_handler; #endif uart_config[UART5_INDEX].rx_timeout = &uart5_rx_timeout; @@ -1883,7 +1887,7 @@ static void hc32_uart_get_info(void) #endif } -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) /** * @brief This function gets uart irq handle. * @param None @@ -1972,7 +1976,7 @@ static void hc32_get_uart_callback(void) uart_config[UART10_INDEX].tc_irq.irq_callback = hc32_uart10_tc_irq_handler; #endif } -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) /** * @brief This function gets uart irq handle. * @param None @@ -2013,8 +2017,7 @@ static void hc32_get_uart_callback(void) } #endif /* HC32F448, HC32F472 */ -static const struct rt_uart_ops hc32_uart_ops = -{ +static const struct rt_uart_ops hc32_uart_ops = { .configure = hc32_configure, .control = hc32_control, .putc = hc32_putc, @@ -2033,9 +2036,9 @@ int rt_hw_usart_init(void) for (int i = 0; i < obj_num; i++) { /* init UART object */ - uart_obj[i].serial.ops = &hc32_uart_ops; - uart_obj[i].config = &uart_config[i]; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) + uart_obj[i].serial.ops = &hc32_uart_ops; + uart_obj[i].config = &uart_config[i]; +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) /* register the handle */ hc32_install_irq_handler(&uart_config[i].rxerr_irq.irq_config, uart_config[i].rxerr_irq.irq_callback, RT_FALSE); #endif @@ -2043,7 +2046,7 @@ int rt_hw_usart_init(void) if (uart_obj[i].uart_dma_flag & RT_DEVICE_FLAG_DMA_RX) { hc32_install_irq_handler(&uart_config[i].dma_rx->irq_config, uart_config[i].dma_rx->irq_callback, RT_FALSE); -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) hc32_install_irq_handler(&uart_config[i].rx_timeout->irq_config, uart_config[i].rx_timeout->irq_callback, RT_FALSE); #endif } @@ -2055,7 +2058,7 @@ int rt_hw_usart_init(void) /* register UART device */ result = rt_hw_serial_register(&uart_obj[i].serial, uart_obj[i].config->name, - (RT_DEVICE_FLAG_RDWR | + (RT_DEVICE_FLAG_RDWR | uart_obj[i].uart_dma_flag), &uart_obj[i]); RT_ASSERT(result == RT_EOK); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h index c513062391a..3caa1d4d7ec 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_usart_v2.h @@ -21,8 +21,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -31,48 +30,48 @@ extern "C" struct hc32_uart_irq_config { struct hc32_irq_config irq_config; - func_ptr_t irq_callback; + func_ptr_t irq_callback; }; /* HC32 config Rx timeout */ struct hc32_uart_rxto { - CM_TMR0_TypeDef *TMR0_Instance; - rt_uint32_t channel; - rt_uint32_t clock; - rt_size_t timeout_bits; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) - struct hc32_irq_config irq_config; - func_ptr_t irq_callback; + CM_TMR0_TypeDef *TMR0_Instance; + rt_uint32_t channel; + rt_uint32_t clock; + rt_size_t timeout_bits; +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; #endif }; /* HC32 config uart class */ struct hc32_uart_config { - const char *name; - CM_USART_TypeDef *Instance; - rt_uint32_t clock; -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F4A8) + const char *name; + CM_USART_TypeDef *Instance; + rt_uint32_t clock; +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) struct hc32_uart_irq_config rxerr_irq; struct hc32_uart_irq_config rx_irq; struct hc32_uart_irq_config tx_irq; -#elif defined (HC32F448) || defined (HC32F472) || defined (HC32F334) - IRQn_Type irq_num; - en_int_src_t rxerr_int_src; - en_int_src_t tx_int_src; - en_int_src_t rx_int_src; +#elif defined(HC32F448) || defined(HC32F472) || defined(HC32F334) + IRQn_Type irq_num; + en_int_src_t rxerr_int_src; + en_int_src_t tx_int_src; + en_int_src_t rx_int_src; #ifdef RT_SERIAL_USING_DMA - en_int_src_t rxto_int_src; + en_int_src_t rxto_int_src; #endif #endif struct hc32_uart_irq_config tc_irq; #ifdef RT_SERIAL_USING_DMA - struct hc32_uart_rxto *rx_timeout; - stc_dma_llp_descriptor_t llp_desc[2U]; - struct dma_config *dma_rx; - struct dma_config *dma_tx; + struct hc32_uart_rxto *rx_timeout; + stc_dma_llp_descriptor_t llp_desc[2U]; + struct dma_config *dma_rx; + struct dma_config *dma_tx; #endif }; @@ -81,9 +80,9 @@ struct hc32_uart { struct hc32_uart_config *config; #ifdef RT_SERIAL_USING_DMA - rt_size_t dma_rx_remaining_cnt; + rt_size_t dma_rx_remaining_cnt; #endif - rt_uint16_t uart_dma_flag; + rt_uint16_t uart_dma_flag; struct rt_serial_device serial; }; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usbd.c b/bsp/hc32/libraries/hc32_drivers/drv_usbd.c index b1324771683..45a4f3c5353 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usbd.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usbd.c @@ -7,6 +7,8 @@ * Date Author Notes * 2023-02-14 CDT first version * 2025-07-25 CDT support HC32F4A8 + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ /******************************************************************************* @@ -18,7 +20,7 @@ #if defined(BSP_USING_USBD) //#define DRV_DEBUG -#define LOG_TAG "drv.usbd" +#define LOG_TAG "drv.usbd" #include #include "board_config.h" @@ -26,13 +28,13 @@ #include "drv_usbd.h" #if defined(HC32F472) - #define USBFS_VBUS_INT_PIN (rt_base_t)(((rt_uint16_t)USBF_VBUS_PORT * 16) + __CLZ(__RBIT(USBF_VBUS_PIN))) +#define USBFS_VBUS_INT_PIN (rt_base_t)(((rt_uint16_t)USBF_VBUS_PORT * 16) + __CLZ(__RBIT(USBF_VBUS_PIN))) #endif #if !defined(BSP_USING_USBD_HS) - extern rt_err_t rt_hw_usbfs_board_init(void); +extern rt_err_t rt_hw_usbfs_board_init(void); #else - extern rt_err_t rt_hw_usbhs_board_init(void); +extern rt_err_t rt_hw_usbhs_board_init(void); #endif extern void rt_hw_us_delay(rt_uint32_t us); @@ -40,42 +42,41 @@ static usb_core_instance _hc32_usbd; static struct udcd _hc32_udc; -static struct ep_id _ep_pool[] = -{ - {0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, - {0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x2, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x2, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x4, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x5, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x5, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED}, -#if defined (HC32F4A0) || defined(HC32F4A8) - {0x6, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x6, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x8, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x8, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0x9, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0x9, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0xA, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0xA, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0xB, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0xB, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0xC, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0xC, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0xD, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0xD, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0xE, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0xE, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED}, - {0xF, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED}, - {0xF, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED}, +static struct ep_id _ep_pool[] = { + { 0x0, USB_EP_ATTR_CONTROL, USB_DIR_INOUT, 64, ID_ASSIGNED }, + { 0x1, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0x1, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0x2, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0x2, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0x3, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0x3, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0x4, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0x4, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0x5, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0x5, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED }, +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) + { 0x6, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0x6, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0x7, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0x7, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0x8, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0x8, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0x9, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0x9, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0xA, USB_EP_ATTR_BULK, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0xA, USB_EP_ATTR_BULK, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0xB, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0xB, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0xC, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0xC, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0xD, USB_EP_ATTR_INT, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0xD, USB_EP_ATTR_INT, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0xE, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0xE, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED }, + { 0xF, USB_EP_ATTR_ISOC, USB_DIR_IN, 64, ID_UNASSIGNED }, + { 0xF, USB_EP_ATTR_ISOC, USB_DIR_OUT, 64, ID_UNASSIGNED }, #endif - {0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, + { 0xFF, USB_EP_ATTR_TYPE_MASK, USB_DIR_MASK, 0, ID_ASSIGNED }, }; __WEAK void usb_udelay(const uint32_t usec) @@ -104,7 +105,7 @@ static void usb_opendevep(usb_core_instance *pdev, uint8_t ep_addr, uint16_t ep_ ep = &pdev->dev.out_ep[tmp_2]; } - ep->epidx = tmp_2; + ep->epidx = tmp_2; ep->ep_dir = tmp_1; ep->maxpacket = ep_mps; @@ -122,7 +123,7 @@ static void usb_opendevep(usb_core_instance *pdev, uint8_t ep_addr, uint16_t ep_ usb_epactive(&pdev->regs, ep); } -static void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr) +static void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr) { USB_DEV_EP *ep; __IO uint8_t tmp_1, tmp_2; @@ -137,11 +138,26 @@ static void usb_shutdevep(usb_core_instance *pdev, uint8_t ep_addr) { ep = &pdev->dev.out_ep[tmp_2]; } - ep->epidx = tmp_2; + ep->epidx = tmp_2; ep->ep_dir = tmp_1; usb_epdeactive(&pdev->regs, ep); } +static void usb_flsdevep(usb_core_instance *pdev, uint8_t epnum) +{ + __IO uint8_t tmp_1; + + tmp_1 = epnum >> 7; /* EP type, it is IN(=1) or OUT(=0) */ + if (tmp_1 != 0U) + { + usb_txfifoflush(&pdev->regs, (uint32_t)epnum & (uint32_t)0x7F); + } + else + { + usb_rxfifoflush(&pdev->regs); + } +} + static void usb_readytorx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, uint16_t buf_len) { USB_DEV_EP *ep; @@ -185,7 +201,7 @@ static void usb_deveptx(usb_core_instance *pdev, uint8_t ep_addr, uint8_t *pbuf, ep->xfer_buff = pbuf; ep->dma_addr = (uint32_t)pbuf; ep->xfer_count = 0UL; - ep->xfer_len = buf_len; + ep->xfer_len = buf_len; if (tmp_1 == 0U) { @@ -215,7 +231,7 @@ static void usb_stalldevep(usb_core_instance *pdev, uint8_t epnum) } ep->ep_stall = 1U; - ep->epidx = tmp_2; + ep->epidx = tmp_2; if (tmp_1 != 0U) { ep->ep_dir = 1U; @@ -245,7 +261,7 @@ static void usb_clrstall(usb_core_instance *pdev, uint8_t epnum) } ep->ep_stall = 0U; - ep->epidx = tmp_2; + ep->epidx = tmp_2; if (tmp_1 != 0U) { ep->ep_dir = 1U; @@ -310,7 +326,7 @@ static void usb_dataout_process(usb_core_instance *pdev, uint8_t epnum) } else { - rt_usbd_ep0_out_handler(&_hc32_udc, pdev->dev.out_ep[0].xfer_count); + rt_usbd_ep0_out_handler(&_hc32_udc, pdev->dev.out_ep[0].xfer_count); } } @@ -336,8 +352,7 @@ static void usb_isooutincomplt_process(usb_core_instance *pdev) /* reserved */ } -static usb_dev_int_cbk_typedef dev_int_cbk = -{ +static usb_dev_int_cbk_typedef dev_int_cbk = { &usb_dev_rst, &usb_ctrlconn, &usb_dev_susp, @@ -350,7 +365,7 @@ static usb_dev_int_cbk_typedef dev_int_cbk = &usb_isooutincomplt_process }; -static usb_dev_int_cbk_typedef *dev_int_cbkpr = &dev_int_cbk; +static usb_dev_int_cbk_typedef *dev_int_cbkpr = &dev_int_cbk; static uint32_t usb_rddevinep(usb_core_instance *pdev, uint8_t epnum) { @@ -370,7 +385,7 @@ static void usb_wrblanktxfifo(usb_core_instance *pdev, uint32_t epnum) uint16_t u16spclen; uint32_t u32diepempmsk; - ep = &pdev->dev.in_ep[epnum]; + ep = &pdev->dev.in_ep[epnum]; u32Len = ep->xfer_len - ep->xfer_count; if (u32Len > ep->maxpacket) { @@ -388,7 +403,7 @@ static void usb_wrblanktxfifo(usb_core_instance *pdev, uint32_t epnum) } u32Len32b = (u32Len + 3UL) >> 2; usb_wrpkt(&pdev->regs, ep->xfer_buff, (uint8_t)epnum, (uint16_t)u32Len, pdev->basic_cfgs.dmaen); - ep->xfer_buff += u32Len; + ep->xfer_buff += u32Len; ep->xfer_count += u32Len; u16spclen = usb_rdineptxfspcavail(pdev, epnum); } @@ -400,7 +415,8 @@ static void usb_wrblanktxfifo(usb_core_instance *pdev, uint32_t epnum) } } -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F4A8) || \ + defined(HC32F467) #ifdef VBUS_SENSING_ENABLED static void usb_sessionrequest_isr(usb_core_instance *pdev) { @@ -532,8 +548,8 @@ static void usb_outep_isr(usb_core_instance *pdev) { if ((pdev->dev.device_state == USB_EP0_STATUS_OUT) && (u8epnum == 0U)) { - pdev->dev.out_ep[0].xfer_len = 64U; - pdev->dev.out_ep[0].rem_data_len = 64U; + pdev->dev.out_ep[0].xfer_len = 64U; + pdev->dev.out_ep[0].rem_data_len = 64U; pdev->dev.out_ep[0].total_data_len = 64U; usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf); pdev->dev.device_state = USB_EP0_IDLE; @@ -575,7 +591,7 @@ static void usb_rxstsqlvl_isr(usb_core_instance *pdev) CLR_REG32_BIT(pdev->regs.GREGS->GINTMSK, USBFS_GINTMSK_RXFNEM); - u32grxsts = READ_REG32(pdev->regs.GREGS->GRXSTSP); + u32grxsts = READ_REG32(pdev->regs.GREGS->GRXSTSP); u8epnum = (uint8_t)(u32grxsts & USBFS_GRXSTSP_CHNUM_EPNUM); u8PktStatus = (uint8_t)((u32grxsts & USBFS_GRXSTSP_PKTSTS) >> USBFS_GRXSTSP_PKTSTS_POS); u16ByteCnt = (uint16_t)((u32grxsts & USBFS_GRXSTSP_BCNT) >> USBFS_GRXSTSP_BCNT_POS); @@ -616,7 +632,7 @@ static void usb_reset_isr(usb_core_instance *pdev) CLR_REG32_BIT(pdev->regs.DREGS->DCTL, USBFS_DCTL_RWUSIG); usb_txfifoflush(&pdev->regs, 0UL); - for (i = 0UL; i < pdev->basic_cfgs.dev_epnum ; i++) + for (i = 0UL; i < pdev->basic_cfgs.dev_epnum; i++) { WRITE_REG32(pdev->regs.INEP_REGS[i]->DIEPINT, 0xFFUL); WRITE_REG32(pdev->regs.OUTEP_REGS[i]->DOEPINT, 0xFFUL); @@ -635,8 +651,8 @@ static void usb_reset_isr(usb_core_instance *pdev) #endif CLR_REG32_BIT(pdev->regs.DREGS->DCFG, USBFS_DCFG_DAD); - pdev->dev.out_ep[0].xfer_len = 64U; - pdev->dev.out_ep[0].rem_data_len = 64U; + pdev->dev.out_ep[0].xfer_len = 64U; + pdev->dev.out_ep[0].rem_data_len = 64U; pdev->dev.out_ep[0].total_data_len = 64U; usb_ep0revcfg(&pdev->regs, pdev->basic_cfgs.dmaen, pdev->dev.setup_pkt_buf); WRITE_REG32(pdev->regs.GREGS->GINTSTS, USBFS_GINTSTS_USBRST); @@ -718,7 +734,8 @@ static void usb_isr_handler(usb_core_instance *pdev) { usb_isooutincomplt_isr(pdev); } -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F4A8) || \ + defined(HC32F467) #ifdef VBUS_SENSING_ENABLED if ((u32gintsts & VBUSV_INT) != 0UL) { @@ -786,6 +803,7 @@ static rt_err_t _usbd_ep_enable(uep_t ep) RT_ASSERT(ep->ep_desc != RT_NULL); usb_opendevep(&_hc32_usbd, ep->ep_desc->bEndpointAddress, ep->ep_desc->wMaxPacketSize, ep->ep_desc->bmAttributes); + usb_flsdevep(&_hc32_usbd, ep->ep_desc->bEndpointAddress); return RT_EOK; } @@ -793,6 +811,7 @@ static rt_err_t _usbd_ep_disable(uep_t ep) { RT_ASSERT(ep != RT_NULL); RT_ASSERT(ep->ep_desc != RT_NULL); + usb_flsdevep(&_hc32_usbd, ep->ep_desc->bEndpointAddress); usb_shutdevep(&_hc32_usbd, ep->ep_desc->bEndpointAddress); return RT_EOK; } @@ -852,7 +871,7 @@ static rt_err_t _usbd_init(rt_device_t device) #else stcPortIdentify.u8CoreID = USBHS_CORE_ID; #endif -#if defined (HC32F4A0) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) #if !defined(BSP_USING_USBHS_PHY_EXTERN) stcPortIdentify.u8PhyType = USBHS_PHY_EMBED; #else @@ -896,8 +915,7 @@ static rt_err_t _usbd_init(rt_device_t device) return RT_EOK; } -const static struct udcd_ops _udc_ops = -{ +const static struct udcd_ops _udc_ops = { _usbd_set_address, _usbd_set_config, _usbd_ep_set_stall, @@ -913,8 +931,7 @@ const static struct udcd_ops _udc_ops = }; #ifdef RT_USING_DEVICE_OPS -const static struct rt_device_ops _ops = -{ +const static struct rt_device_ops _ops = { _usbd_init, RT_NULL, RT_NULL, diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usbd.h b/bsp/hc32/libraries/hc32_drivers/drv_usbd.h index f99bad4f283..ea8d915ac0f 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usbd.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_usbd.h @@ -20,8 +20,7 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* @@ -29,43 +28,43 @@ extern "C" ******************************************************************************/ /* The bit of the diepint/doepint */ -#define XFER_COMPL (1UL) -#define EPDISABLED (1UL<<1) -#define TIME_OUT (1UL<<3) -#define SETUP_BIT (1UL<<3) -#define INTKNTXFEMP (1UL<<4) -#define INEPNAKEFF (1UL<<6) -#define TXFEMP (1UL<<7) +#define XFER_COMPL (1UL) +#define EPDISABLED (1UL << 1) +#define TIME_OUT (1UL << 3) +#define SETUP_BIT (1UL << 3) +#define INTKNTXFEMP (1UL << 4) +#define INEPNAKEFF (1UL << 6) +#define TXFEMP (1UL << 7) /* The bit of the GINTSTS */ -#define MODEMIS_INT (1UL<<1) -#define SOF_INT (1UL<<3) -#define RXFLVL_INT (1UL<<4) -#define USBSUSP_INT (1UL<<11) -#define USBRST_INT (1UL<<12) -#define ENUMDONE_INT (1UL<<13) -#define INEP_INT (1UL<<18) -#define OUTEP_INT (1UL<<19) -#define INCOMPLSOIN (1UL<<20) -#define INCOMPLSOOUT (1UL<<21) -#define VBUSV_INT (1UL<<30) -#define WAKEUP_INT (1UL<<31) +#define MODEMIS_INT (1UL << 1) +#define SOF_INT (1UL << 3) +#define RXFLVL_INT (1UL << 4) +#define USBSUSP_INT (1UL << 11) +#define USBRST_INT (1UL << 12) +#define ENUMDONE_INT (1UL << 13) +#define INEP_INT (1UL << 18) +#define OUTEP_INT (1UL << 19) +#define INCOMPLSOIN (1UL << 20) +#define INCOMPLSOOUT (1UL << 21) +#define VBUSV_INT (1UL << 30) +#define WAKEUP_INT (1UL << 31) /* Data packet status for device mode */ -#define STS_GOUT_NAK (1U) -#define STS_DATA_UPDT (2U) -#define STS_XFER_COMP (3U) -#define STS_SETUP_COMP (4U) -#define STS_SETUP_UPDT (6U) +#define STS_GOUT_NAK (1U) +#define STS_DATA_UPDT (2U) +#define STS_XFER_COMP (3U) +#define STS_SETUP_COMP (4U) +#define STS_SETUP_UPDT (6U) /* USB EP0 state */ -#define USB_EP0_IDLE (0U) -#define USB_EP0_SETUP (1U) -#define USB_EP0_DATA_IN (2U) -#define USB_EP0_DATA_OUT (3U) -#define USB_EP0_STATUS_IN (4U) -#define USB_EP0_STATUS_OUT (5U) -#define USB_EP0_STALL (6U) +#define USB_EP0_IDLE (0U) +#define USB_EP0_SETUP (1U) +#define USB_EP0_DATA_IN (2U) +#define USB_EP0_DATA_OUT (3U) +#define USB_EP0_STATUS_IN (4U) +#define USB_EP0_STATUS_OUT (5U) +#define USB_EP0_STALL (6U) /******************************************************************************* * Global type definitions ('typedef') @@ -86,22 +85,22 @@ typedef enum typedef struct { - uint8_t bmRequest; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; } USB_SETUP_REQ; typedef struct { - uint8_t *(*get_dev_desc)(uint16_t *length); - uint8_t *(*get_dev_langiddesc)(uint16_t *length); - uint8_t *(*get_dev_manufacturerstr)(uint16_t *length); - uint8_t *(*get_dev_productstr)(uint16_t *length); - uint8_t *(*get_dev_serialstr)(uint16_t *length); - uint8_t *(*get_dev_configstr)(uint16_t *length); - uint8_t *(*get_dev_interfacestr)(uint16_t *length); + uint8_t *(*get_dev_desc)(uint16_t *length); + uint8_t *(*get_dev_langiddesc)(uint16_t *length); + uint8_t *(*get_dev_manufacturerstr)(uint16_t *length); + uint8_t *(*get_dev_productstr)(uint16_t *length); + uint8_t *(*get_dev_serialstr)(uint16_t *length); + uint8_t *(*get_dev_configstr)(uint16_t *length); + uint8_t *(*get_dev_interfacestr)(uint16_t *length); } usb_dev_desc_func; typedef struct @@ -111,7 +110,7 @@ typedef struct uint8_t (*ep0_setup)(void *pdev, USB_SETUP_REQ *req); void (*ep0_datain)(void *pdev); void (*ep0_dataout)(void *pdev); - uint8_t *(*class_getconfigdesc)(uint16_t *length); + uint8_t *(*class_getconfigdesc)(uint16_t *length); uint8_t (*class_sof)(void *pdev); void (*class_datain)(void *pdev, uint8_t epnum); void (*class_dataout)(void *pdev, uint8_t epnum); @@ -132,43 +131,43 @@ typedef struct typedef struct { - __IO uint8_t device_config; - __IO uint8_t device_address; - __IO uint8_t device_state; - __IO uint8_t device_old_status; - __IO uint8_t device_cur_status; - __IO uint8_t connection_status; - __IO uint8_t device_remote_wakeup; - __IO uint8_t test_mode; - USB_DEV_EP in_ep[USB_MAX_TX_FIFOS]; - USB_DEV_EP out_ep[USB_MAX_TX_FIFOS]; - uint8_t setup_pkt_buf[24]; - usb_dev_class_func *class_callback; - usb_dev_user_func *user_callback; - usb_dev_desc_func *desc_callback; + __IO uint8_t device_config; + __IO uint8_t device_address; + __IO uint8_t device_state; + __IO uint8_t device_old_status; + __IO uint8_t device_cur_status; + __IO uint8_t connection_status; + __IO uint8_t device_remote_wakeup; + __IO uint8_t test_mode; + USB_DEV_EP in_ep[USB_MAX_TX_FIFOS]; + USB_DEV_EP out_ep[USB_MAX_TX_FIFOS]; + uint8_t setup_pkt_buf[24]; + usb_dev_class_func *class_callback; + usb_dev_user_func *user_callback; + usb_dev_desc_func *desc_callback; } USB_DEV_PARAM; typedef struct { - USB_CORE_BASIC_CFGS basic_cfgs; - LL_USB_TypeDef regs; + USB_CORE_BASIC_CFGS basic_cfgs; + LL_USB_TypeDef regs; #ifdef USE_DEVICE_MODE - USB_DEV_PARAM dev; + USB_DEV_PARAM dev; #endif } usb_core_instance; typedef struct { - void (* Reset)(usb_core_instance *pdev); - void (* devctrlconnect)(usb_core_instance *pdev, uint8_t conn); - void (* Suspend)(usb_core_instance *pdev); - void (* Resume)(usb_core_instance *pdev); - void (* SOF)(usb_core_instance *pdev); - void (* SetupStage)(usb_core_instance *pdev); - void (* DataOutStage)(usb_core_instance *pdev, uint8_t epnum); - void (* DataInStage)(usb_core_instance *pdev, uint8_t epnum); - void (* IsoINIncomplete)(usb_core_instance *pdev); - void (* IsoOUTIncomplete)(usb_core_instance *pdev); + void (*Reset)(usb_core_instance *pdev); + void (*devctrlconnect)(usb_core_instance *pdev, uint8_t conn); + void (*Suspend)(usb_core_instance *pdev); + void (*Resume)(usb_core_instance *pdev); + void (*SOF)(usb_core_instance *pdev); + void (*SetupStage)(usb_core_instance *pdev); + void (*DataOutStage)(usb_core_instance *pdev, uint8_t epnum); + void (*DataInStage)(usb_core_instance *pdev, uint8_t epnum); + void (*IsoINIncomplete)(usb_core_instance *pdev); + void (*IsoOUTIncomplete)(usb_core_instance *pdev); } usb_dev_int_cbk_typedef; diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usbh.c b/bsp/hc32/libraries/hc32_drivers/drv_usbh.c index 8c0b11c6d85..a49c1502a0a 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usbh.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_usbh.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2023-05-25 CDT first version + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ /******************************************************************************* @@ -17,7 +19,7 @@ #if defined(BSP_USING_USBH) //#define DRV_DEBUG -#define LOG_TAG "drv.usbh" +#define LOG_TAG "drv.usbh" #include #include "board_config.h" @@ -25,13 +27,13 @@ #include "drv_usbh.h" #if defined(HC32F472) - #define USBFS_DRVVBUS_PIN (rt_base_t)(((rt_uint16_t)USBF_DRVVBUS_PORT * 16) + __CLZ(__RBIT(USBF_DRVVBUS_PIN))) +#define USBFS_DRVVBUS_PIN (rt_base_t)(((rt_uint16_t)USBF_DRVVBUS_PORT * 16) + __CLZ(__RBIT(USBF_DRVVBUS_PIN))) #endif #if !defined(BSP_USING_USBH_HS) - extern rt_err_t rt_hw_usbfs_board_init(void); +extern rt_err_t rt_hw_usbfs_board_init(void); #else - extern rt_err_t rt_hw_usbhs_board_init(void); +extern rt_err_t rt_hw_usbhs_board_init(void); #endif extern void rt_hw_us_delay(rt_uint32_t us); @@ -112,7 +114,8 @@ static void usb_host_chx_out_isr(usb_core_instance *pdev, uint8_t chnum) { usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK); } -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F467) else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) { usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR); @@ -152,7 +155,7 @@ static void usb_host_chx_out_isr(usb_core_instance *pdev, uint8_t chnum) { usb_host_int_unmskchhltd(pdev, chnum); usb_hchstop(&pdev->regs, chnum); - pdev->host.ErrCnt[chnum] ++; + pdev->host.ErrCnt[chnum]++; pdev->host.HC_Status[chnum] = HOST_CH_XACTERR; usb_host_clrint(pdev, chnum, USBFS_HCINT_TXERR); } @@ -236,7 +239,8 @@ static void usb_host_chx_in_isr(usb_core_instance *pdev, uint8_t chnum) { usb_host_clrint(pdev, chnum, USBFS_HCINT_ACK); } -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F467) else if (0UL != (u32hcint & USBFS_HCINT_AHBERR)) { usb_host_clrint(pdev, chnum, USBFS_HCINT_AHBERR); @@ -277,11 +281,11 @@ static void usb_host_chx_in_isr(usb_core_instance *pdev, uint8_t chnum) if (pdev->basic_cfgs.dmaen == 1U) { u32hctsiz = READ_REG32(pdev->regs.HC_REGS[chnum]->HCTSIZ); - pdev->host.XferCnt[chnum] = pdev->host.hc[chnum].xfer_len - (u32hctsiz & USBFS_HCTSIZ_XFRSIZ); + pdev->host.XferCnt[chnum] = pdev->host.hc[chnum].xfer_len - (u32hctsiz & USBFS_HCTSIZ_XFRSIZ); pdev->host.hc[chnum].xfer_count += pdev->host.XferCnt[chnum]; } pdev->host.HC_Status[chnum] = HOST_CH_XFERCOMPL; - pdev->host.ErrCnt [chnum] = 0U; + pdev->host.ErrCnt[chnum] = 0U; usb_host_clrint(pdev, chnum, USBFS_HCINT_XFRC); switch (u32eptypetmp) { @@ -332,7 +336,7 @@ static void usb_host_chx_in_isr(usb_core_instance *pdev, uint8_t chnum) } else if (pdev->host.HC_Status[chnum] == HOST_CH_BBLERR) { - pdev->host.ErrCnt[chnum] ++; + pdev->host.ErrCnt[chnum]++; pdev->host.URB_State[chnum] = HOST_CH_XFER_ERROR; } else if (u32eptypetmp == EP_TYPE_INTR) @@ -349,7 +353,7 @@ static void usb_host_chx_in_isr(usb_core_instance *pdev, uint8_t chnum) else if (0UL != (u32hcint & USBFS_HCINT_TXERR)) { usb_host_int_unmskchhltd(pdev, chnum); - pdev->host.ErrCnt[chnum] ++; + pdev->host.ErrCnt[chnum]++; pdev->host.HC_Status[chnum] = HOST_CH_XACTERR; usb_hchstop(&pdev->regs, chnum); usb_host_clrint(pdev, chnum, USBFS_HCINT_TXERR); @@ -426,8 +430,8 @@ static void usb_host_disconn_isr(usb_core_instance *pdev) usb_device_disconnect_callback(pdev); } -#define USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM_POS (27U) -#define USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM (0x78000000UL) +#define USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM_POS (27U) +#define USBFS_HNPTXSTS_NPTXQTOP_CHEPNUM (0x78000000UL) static void usb_host_nptxfifoempty_isr(usb_core_instance *pdev) { @@ -457,8 +461,8 @@ static void usb_host_nptxfifoempty_isr(usb_core_instance *pdev) } } -#define USBFS_HPTXSTS_PTXQTOP_CHNUM_POS (27U) -#define USBFS_HPTXSTS_PTXQTOP_CHNUM (0x78000000UL) +#define USBFS_HPTXSTS_PTXQTOP_CHNUM_POS (27U) +#define USBFS_HPTXSTS_PTXQTOP_CHNUM (0x78000000UL) static void usb_host_ptxfifoempty_isr(usb_core_instance *pdev) { @@ -585,7 +589,7 @@ static void usb_host_rxflvl_isr(usb_core_instance *pdev) { usb_rdpkt(&pdev->regs, pdev->host.hc[u8chnum].xfer_buff, u16bcnt); pdev->host.hc[u8chnum].xfer_buff += u16bcnt; - pdev->host.hc[u8chnum].xfer_count += u16bcnt; + pdev->host.hc[u8chnum].xfer_count += u16bcnt; pdev->host.XferCnt[u8chnum] = pdev->host.hc[u8chnum].xfer_count; u32hctsiz = READ_REG32(pdev->regs.HC_REGS[u8chnum]->HCTSIZ); @@ -690,41 +694,41 @@ void USBFS_Handler(void) #endif static void usb_host_chopen(usb_core_instance *pdev, - uint8_t hc_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, + uint8_t hc_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, uint16_t mps) { pdev->host.channel[hc_num] = epnum; /* assign channel here */ - pdev->host.hc[hc_num].ep_idx = (uint8_t) pdev->host.channel[hc_num] & 0x7FU; - pdev->host.hc[hc_num].is_epin = (uint8_t)((pdev->host.channel[hc_num] & 0x80U) == 0x80U); - pdev->host.hc[hc_num].dev_addr = dev_address; - pdev->host.hc[hc_num].ep_type = ep_type; + pdev->host.hc[hc_num].ep_idx = (uint8_t)pdev->host.channel[hc_num] & 0x7FU; + pdev->host.hc[hc_num].is_epin = (uint8_t)((pdev->host.channel[hc_num] & 0x80U) == 0x80U); + pdev->host.hc[hc_num].dev_addr = dev_address; + pdev->host.hc[hc_num].ep_type = ep_type; pdev->host.hc[hc_num].max_packet = mps; - pdev->host.hc[hc_num].ch_speed = speed; - pdev->host.hc[hc_num].in_toggle = 0U; + pdev->host.hc[hc_num].ch_speed = speed; + pdev->host.hc[hc_num].in_toggle = 0U; pdev->host.hc[hc_num].out_toggle = 0U; (void)usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen); } static void usb_host_ch_init(usb_core_instance *pdev, - uint8_t hc_num, - uint8_t epnum, - uint8_t dev_address, - uint8_t speed, - uint8_t ep_type, + uint8_t hc_num, + uint8_t epnum, + uint8_t dev_address, + uint8_t speed, + uint8_t ep_type, uint16_t mps) { pdev->host.channel[hc_num] = epnum; /* assign channel here */ - pdev->host.hc[hc_num].ep_idx = (uint8_t) pdev->host.channel[hc_num] & 0x7FU; - pdev->host.hc[hc_num].is_epin = (uint8_t)((pdev->host.channel[hc_num] & 0x80U) == 0x80U); - pdev->host.hc[hc_num].dev_addr = dev_address; - pdev->host.hc[hc_num].ep_type = ep_type; + pdev->host.hc[hc_num].ep_idx = (uint8_t)pdev->host.channel[hc_num] & 0x7FU; + pdev->host.hc[hc_num].is_epin = (uint8_t)((pdev->host.channel[hc_num] & 0x80U) == 0x80U); + pdev->host.hc[hc_num].dev_addr = dev_address; + pdev->host.hc[hc_num].ep_type = ep_type; pdev->host.hc[hc_num].max_packet = mps; - pdev->host.hc[hc_num].ch_speed = speed; + pdev->host.hc[hc_num].ch_speed = speed; (void)usb_inithch(&pdev->regs, hc_num, &pdev->host.hc[hc_num], pdev->basic_cfgs.dmaen); } @@ -739,7 +743,7 @@ static uint32_t usb_host_submitrequest(usb_core_instance *pdev, uint8_t do_ping) { pdev->host.hc[ch_num].is_epin = direction; - pdev->host.hc[ch_num].ep_type = ep_type; + pdev->host.hc[ch_num].ep_type = ep_type; if (token == 0U) { @@ -837,7 +841,7 @@ static uint32_t usb_host_submitrequest(usb_core_instance *pdev, } pdev->host.hc[ch_num].xfer_buff = pbuff; - pdev->host.hc[ch_num].xfer_len = length; + pdev->host.hc[ch_num].xfer_len = length; pdev->host.hc[ch_num].xfer_count = 0U; pdev->host.HC_Status[ch_num] = HOST_CH_IDLE; /* state */ pdev->host.URB_State[ch_num] = HOST_CH_XFER_IDLE; /* urb state */ @@ -870,7 +874,7 @@ static rt_err_t _usbh_reset_port(rt_uint8_t port) static int _usbh_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nbytes, int timeouts) { int timeout = timeouts; - uint8_t devspeed; + uint8_t devspeed; uint32_t u32NakCnt = 0; if (pipe->pipe_index >= USB_MAX_CH_NUM) @@ -908,8 +912,8 @@ static int _usbh_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nby if (usb_hsot_get_ch_state(&_hc32_usbh, pipe->pipe_index) == HOST_CH_NAK) { LOG_D("nak"); -#define MAX_NAK_CNT (5U) - u32NakCnt ++; +#define MAX_NAK_CNT (5U) + u32NakCnt++; if (u32NakCnt > MAX_NAK_CNT) { #if defined(RT_USBH_MSTORAGE) || defined(RT_USBH_HID) @@ -981,9 +985,8 @@ static int _usbh_pipe_xfer(upipe_t pipe, rt_uint8_t token, void *buffer, int nby } - static rt_uint16_t pipe_index = 0; -static rt_uint8_t _usbh_get_free_pipe_index(void) +static rt_uint8_t _usbh_get_free_pipe_index(void) { rt_uint8_t idx; for (idx = 0; idx < USB_MAX_CH_NUM; idx++) @@ -1005,7 +1008,7 @@ static void _usbh_free_pipe_index(rt_uint8_t index) static rt_err_t _usbh_open_pipe(upipe_t pipe) { - uint8_t devspeed; + uint8_t devspeed; pipe->pipe_index = _usbh_get_free_pipe_index(); if (pipe->pipe_index >= USB_MAX_CH_NUM) @@ -1049,8 +1052,7 @@ static rt_err_t _usbh_close_pipe(upipe_t pipe) } -static struct uhcd_ops _uhcd_ops = -{ +static struct uhcd_ops _uhcd_ops = { _usbh_reset_port, _usbh_pipe_xfer, _usbh_open_pipe, @@ -1106,7 +1108,7 @@ static rt_err_t _usbh_init(rt_device_t device) #else stcPortIdentify.u8CoreID = USBHS_CORE_ID; #endif -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) #if !defined(BSP_USING_USBHS_PHY_EXTERN) stcPortIdentify.u8PhyType = USBHS_PHY_EMBED; #else @@ -1175,5 +1177,4 @@ int rt_hw_usbh_init(void) INIT_DEVICE_EXPORT(rt_hw_usbh_init); - #endif /* BSP_USING_USBH */ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_usbh.h b/bsp/hc32/libraries/hc32_drivers/drv_usbh.h index 1c0f0a3a576..f7190e88f0e 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_usbh.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_usbh.h @@ -20,24 +20,23 @@ /* C binding of definitions if building with C++ compiler */ #ifdef __cplusplus -extern "C" -{ +extern "C" { #endif /******************************************************************************* * Global pre-processor symbols/macros ('#define') ******************************************************************************/ -#define USB_FS_PORT (1U) +#define USB_FS_PORT (1U) -#define MAX_DATA_LENGTH (0x200U) +#define MAX_DATA_LENGTH (0x200U) -#define HCINT_NYET (1UL << 6) +#define HCINT_NYET (1UL << 6) /* Macro definations for host mode */ -#define PID_DATA0 (0U) -#define PID_DATA2 (1U) -#define PID_DATA1 (2U) -#define PID_SETUP (3U) +#define PID_DATA0 (0U) +#define PID_DATA2 (1U) +#define PID_DATA1 (2U) +#define PID_SETUP (3U) /******************************************************************************* * Global type definitions ('typedef') ******************************************************************************/ @@ -85,11 +84,11 @@ typedef enum typedef struct { - uint8_t bmRequest; - uint8_t bRequest; - uint16_t wValue; - uint16_t wIndex; - uint16_t wLength; + uint8_t bmRequest; + uint8_t bRequest; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; } USB_SETUP_REQ; typedef struct @@ -105,29 +104,28 @@ typedef struct typedef struct { - uint16_t channel[USB_MAX_TX_FIFOS]; - USB_HOST_CH hc[USB_MAX_TX_FIFOS]; - __IO uint32_t is_dev_connect; - uint8_t Rx_Buffer[MAX_DATA_LENGTH]; - __IO uint32_t ErrCnt[USB_MAX_TX_FIFOS]; - __IO uint32_t XferCnt[USB_MAX_TX_FIFOS]; - __IO HOST_CH_STATUS HC_Status[USB_MAX_TX_FIFOS]; - __IO HOST_CH_XFER_STATE URB_State[USB_MAX_TX_FIFOS]; - __IO uint8_t devspeed; + uint16_t channel[USB_MAX_TX_FIFOS]; + USB_HOST_CH hc[USB_MAX_TX_FIFOS]; + __IO uint32_t is_dev_connect; + uint8_t Rx_Buffer[MAX_DATA_LENGTH]; + __IO uint32_t ErrCnt[USB_MAX_TX_FIFOS]; + __IO uint32_t XferCnt[USB_MAX_TX_FIFOS]; + __IO HOST_CH_STATUS HC_Status[USB_MAX_TX_FIFOS]; + __IO HOST_CH_XFER_STATE URB_State[USB_MAX_TX_FIFOS]; + __IO uint8_t devspeed; } USB_HOST_PARAM; typedef struct { - USB_CORE_BASIC_CFGS basic_cfgs; - LL_USB_TypeDef regs; + USB_CORE_BASIC_CFGS basic_cfgs; + LL_USB_TypeDef regs; #ifdef USE_HOST_MODE - USB_HOST_PARAM host; - void *pData; + USB_HOST_PARAM host; + void *pData; #endif } usb_core_instance; - /******************************************************************************* Global function prototypes (definition in C source) ******************************************************************************/ diff --git a/bsp/hc32/libraries/hc32_drivers/drv_wdt.c b/bsp/hc32/libraries/hc32_drivers/drv_wdt.c index cb7221bce46..bd4156e72d7 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_wdt.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_wdt.c @@ -16,7 +16,7 @@ #include // #define DRV_DEBUG -#define LOG_TAG "drv_wdt" +#define LOG_TAG "drv_wdt" #include enum @@ -47,8 +47,8 @@ struct time_match float timeout_s; }; -static uint32_t const Div[] = {4U, 64U, 128U, 256U, 512U, 1024U, 2048U, 8192U}; -static uint32_t const Peri[] = {256U, 4096U, 16384U, 65536U}; +static uint32_t const Div[] = { 4U, 64U, 128U, 256U, 512U, 1024U, 2048U, 8192U }; +static uint32_t const Peri[] = { 256U, 4096U, 16384U, 65536U }; static struct time_match wdt_match[(sizeof(Div) / sizeof(Div[0])) * (sizeof(Peri) / sizeof(Peri[0]))]; static void wdt_match_init(uint32_t clock) @@ -160,11 +160,11 @@ static rt_err_t _wdt_init(rt_watchdog_t *wdt) } wdt_match_init(hc32_wdt.pclk3); wdt_match_sort(); - hc32_wdt.stcwdg.u32RefreshRange = WDT_RANGE_0TO100PCT; + hc32_wdt.stcwdg.u32RefreshRange = WDT_RANGE_0TO100PCT; #ifdef BSP_WDT_CONTINUE_COUNT - hc32_wdt.stcwdg.u32LPMCount = WDT_LPM_CNT_CONT; + hc32_wdt.stcwdg.u32LPMCount = WDT_LPM_CNT_CONT; #else - hc32_wdt.stcwdg.u32LPMCount = WDT_LPM_CNT_STOP; + hc32_wdt.stcwdg.u32LPMCount = WDT_LPM_CNT_STOP; #endif hc32_wdt.stcwdg.u32ExceptionType = WDT_EXP_TYPE_RST; hc32_wdt.sta = WDT_INIT_ING; @@ -188,8 +188,8 @@ static rt_err_t _wdt_control(rt_watchdog_t *wdt, int cmd, void *arg) /* set watchdog timeout */ case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: hc32_wdt.index = wdt_match_find_index((*((rt_uint32_t *)arg))); - hc32_wdt.stcwdg.u32CountPeriod = wdt_match_find_period(wdt_match[hc32_wdt.index].u32CountPeriod); - hc32_wdt.stcwdg.u32ClockDiv = ((uint32_t)log2(wdt_match[hc32_wdt.index].u32ClockDiv) << WDT_CR_CKS_POS); + hc32_wdt.stcwdg.u32CountPeriod = wdt_match_find_period(wdt_match[hc32_wdt.index].u32CountPeriod); + hc32_wdt.stcwdg.u32ClockDiv = ((uint32_t)log2(wdt_match[hc32_wdt.index].u32ClockDiv) << WDT_CR_CKS_POS); if (WDT_Init(&hc32_wdt.stcwdg) != LL_OK) { LOG_E("wdg set timeout failed."); @@ -258,8 +258,8 @@ struct time_match float timeout_s; }; -static uint32_t const Div[] = {1U, 16U, 32U, 64U, 128U, 256U, 2048U}; -static uint32_t const Peri[] = {256U, 4096U, 16384U, 65536U}; +static uint32_t const Div[] = { 1U, 16U, 32U, 64U, 128U, 256U, 2048U }; +static uint32_t const Peri[] = { 256U, 4096U, 16384U, 65536U }; static struct time_match swdt_match[(sizeof(Div) / sizeof(Div[0])) * (sizeof(Peri) / sizeof(Peri[0]))]; static void swdt_match_init(uint32_t clock) @@ -365,11 +365,11 @@ static rt_err_t swdt_init(rt_watchdog_t *swdt) hc32_swdt.swdtclk = 10000U; swdt_match_init(hc32_swdt.swdtclk); swdt_match_sort(); - hc32_swdt.stcwdg.u32RefreshRange = SWDT_RANGE_0TO100PCT; + hc32_swdt.stcwdg.u32RefreshRange = SWDT_RANGE_0TO100PCT; #ifdef BSP_WDT_CONTINUE_COUNT - hc32_swdt.stcwdg.u32LPMCount = SWDT_LPM_CNT_CONT; + hc32_swdt.stcwdg.u32LPMCount = SWDT_LPM_CNT_CONT; #else - hc32_swdt.stcwdg.u32LPMCount = SWDT_LPM_CNT_STOP; + hc32_swdt.stcwdg.u32LPMCount = SWDT_LPM_CNT_STOP; #endif hc32_swdt.stcwdg.u32ExceptionType = SWDT_EXP_TYPE_RST; hc32_swdt.sta = WDT_INIT_ING; @@ -393,8 +393,8 @@ static rt_err_t swdt_control(rt_watchdog_t *swdt, int cmd, void *arg) /* set watchdog timeout */ case RT_DEVICE_CTRL_WDT_SET_TIMEOUT: hc32_swdt.index = swdt_match_find_index((*((rt_uint32_t *)arg))); - hc32_swdt.stcwdg.u32CountPeriod = swdt_match_find_period(swdt_match[hc32_swdt.index].u32CountPeriod); - hc32_swdt.stcwdg.u32ClockDiv = ((uint32_t)log2(swdt_match[hc32_swdt.index].u32ClockDiv) << SWDT_CR_CKS_POS); + hc32_swdt.stcwdg.u32CountPeriod = swdt_match_find_period(swdt_match[hc32_swdt.index].u32CountPeriod); + hc32_swdt.stcwdg.u32ClockDiv = ((uint32_t)log2(swdt_match[hc32_swdt.index].u32ClockDiv) << SWDT_CR_CKS_POS); if (SWDT_Init(&hc32_swdt.stcwdg) != LL_OK) { LOG_E("swdg set timeout failed."); diff --git a/bsp/hc32/libraries/hc32_drivers/drv_wktm.c b/bsp/hc32/libraries/hc32_drivers/drv_wktm.c index 8b8b9ed3e59..e690474d4a3 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_wktm.c +++ b/bsp/hc32/libraries/hc32_drivers/drv_wktm.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2023-02-09 CDT first version + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-03 CDT support HC32F467 */ #include @@ -16,24 +18,24 @@ #if defined(BSP_USING_PM) // #define DRV_DEBUG -#define LOG_TAG "drv_wktm" +#define LOG_TAG "drv_wktm" #include -#define CMPVAL_MAX (0xFFFUL) +#define CMPVAL_MAX (0xFFFUL) #if defined(BSP_USING_WKTM_XTAL32) - #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_XTAL32) - #define PWC_WKT_COUNT_FRQ (32768UL) +#define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_XTAL32) +#define PWC_WKT_COUNT_FRQ (32768UL) #elif defined(BSP_USING_WKTM_64HZ) - #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_64HZ) - #define PWC_WKT_COUNT_FRQ (64U) +#define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_64HZ) +#define PWC_WKT_COUNT_FRQ (64U) #else - #if defined(HC32F4A0) || defined(HC32F4A8) - #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_RTCLRC) - #elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) || defined(HC32F334) - #define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_LRC) - #endif - #define PWC_WKT_COUNT_FRQ (32768UL) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) +#define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_RTCLRC) +#elif defined(HC32F460) || defined(HC32F448) || defined(HC32F472) || defined(HC32F334) +#define PWC_WKT_CLK_SRC (PWC_WKT_CLK_SRC_LRC) +#endif +#define PWC_WKT_COUNT_FRQ (32768UL) #endif /** @@ -119,8 +121,8 @@ int rt_hw_wktm_init(void) /* WKTM init */ PWC_WKT_Config(PWC_WKT_CLK_SRC, CMPVAL_MAX); -#if defined(HC32F4A0) || defined(HC32F4A8) - /* F4A0 if select RTCLRC clock need open the LRCEN by RTC->CR3 register */ +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) + /* F4A0/F4A2 if select RTCLRC clock need open the LRCEN by RTC->CR3 register */ #if (PWC_WKT_CLK_SRC == PWC_WKT_CLK_SRC_RTCLRC) MODIFY_REG8(CM_RTC->CR3, RTC_CR3_LRCEN, 0x01U << RTC_CR3_LRCEN_POS); #endif diff --git a/bsp/hc32/libraries/hc32_drivers/drv_wktm.h b/bsp/hc32/libraries/hc32_drivers/drv_wktm.h index 47e3c6ce3e3..29b93807881 100644 --- a/bsp/hc32/libraries/hc32_drivers/drv_wktm.h +++ b/bsp/hc32/libraries/hc32_drivers/drv_wktm.h @@ -8,8 +8,8 @@ * 2023-02-09 CDT first version */ -#ifndef __DRV_WKTM_H__ -#define __DRV_WKTM_H__ +#ifndef __DRV_WKTM_H__ +#define __DRV_WKTM_H__ #include diff --git a/bsp/hc32/platform/cherryusb/cherryusb_port.c b/bsp/hc32/platform/cherryusb/cherryusb_port.c index a5adc74b06d..1455b21e3eb 100644 --- a/bsp/hc32/platform/cherryusb/cherryusb_port.c +++ b/bsp/hc32/platform/cherryusb/cherryusb_port.c @@ -16,13 +16,12 @@ #include "board_config.h" #if defined(RT_CHERRYUSB_HOST) && defined(RT_CHERRYUSB_DEVICE) - #if defined(HC32F460) || defined(HC32F472) - #error "Only one USB role can be selected!" - #endif +#if defined(HC32F460) || defined(HC32F472) +#error "Only one USB role can be selected!" +#endif #endif -const struct dwc2_user_params param_fs_core = -{ +const struct dwc2_user_params param_fs_core = { .phy_type = DWC2_PHY_TYPE_PARAM_FS, #ifdef CONFIG_USB_DWC2_DMA_ENABLE .device_dma_enable = true, @@ -32,17 +31,17 @@ const struct dwc2_user_params param_fs_core = .device_dma_desc_enable = false, .device_rx_fifo_size = CONFIG_USB_FS_CORE_DEVICE_RX_FIFO_SIZE, .device_tx_fifo_size = { - [0] = CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE, - [1] = CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE, - [2] = CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE, - [3] = CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE, - [4] = CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE, - [5] = CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE, + [0] = CONFIG_USB_FS_CORE_DEVICE_TX0_FIFO_SIZE, + [1] = CONFIG_USB_FS_CORE_DEVICE_TX1_FIFO_SIZE, + [2] = CONFIG_USB_FS_CORE_DEVICE_TX2_FIFO_SIZE, + [3] = CONFIG_USB_FS_CORE_DEVICE_TX3_FIFO_SIZE, + [4] = CONFIG_USB_FS_CORE_DEVICE_TX4_FIFO_SIZE, + [5] = CONFIG_USB_FS_CORE_DEVICE_TX5_FIFO_SIZE, #if defined(HC32F4A0) || defined(HC32F4A8) - [6] = CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE, - [7] = CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE, - [8] = CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE, - [9] = CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE, + [6] = CONFIG_USB_FS_CORE_DEVICE_TX6_FIFO_SIZE, + [7] = CONFIG_USB_FS_CORE_DEVICE_TX7_FIFO_SIZE, + [8] = CONFIG_USB_FS_CORE_DEVICE_TX8_FIFO_SIZE, + [9] = CONFIG_USB_FS_CORE_DEVICE_TX9_FIFO_SIZE, [10] = CONFIG_USB_FS_CORE_DEVICE_TX10_FIFO_SIZE, [11] = CONFIG_USB_FS_CORE_DEVICE_TX11_FIFO_SIZE, [12] = CONFIG_USB_FS_CORE_DEVICE_TX12_FIFO_SIZE, @@ -50,10 +49,10 @@ const struct dwc2_user_params param_fs_core = [14] = CONFIG_USB_FS_CORE_DEVICE_TX14_FIFO_SIZE, [15] = CONFIG_USB_FS_CORE_DEVICE_TX15_FIFO_SIZE #elif defined(HC32F460) || defined(HC32F472) - [6] = 0, - [7] = 0, - [8] = 0, - [9] = 0, + [6] = 0, + [7] = 0, + [8] = 0, + [9] = 0, [10] = 0, [11] = 0, [12] = 0, @@ -78,8 +77,7 @@ const struct dwc2_user_params param_fs_core = }; #if defined(HC32F4A0) || defined(HC32F4A8) -const struct dwc2_user_params param_hs_core = -{ +const struct dwc2_user_params param_hs_core = { #ifdef CONFIG_USB_HS .phy_type = DWC2_PHY_TYPE_PARAM_UTMI, #else @@ -93,23 +91,22 @@ const struct dwc2_user_params param_hs_core = .device_dma_desc_enable = false, .device_rx_fifo_size = CONFIG_USB_HS_CORE_DEVICE_RX_FIFO_SIZE, .device_tx_fifo_size = { - [0] = CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE, - [1] = CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE, - [2] = CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE, - [3] = CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE, - [4] = CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE, - [5] = CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE, - [6] = CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE, - [7] = CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE, - [8] = CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE, - [9] = CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE, + [0] = CONFIG_USB_HS_CORE_DEVICE_TX0_FIFO_SIZE, + [1] = CONFIG_USB_HS_CORE_DEVICE_TX1_FIFO_SIZE, + [2] = CONFIG_USB_HS_CORE_DEVICE_TX2_FIFO_SIZE, + [3] = CONFIG_USB_HS_CORE_DEVICE_TX3_FIFO_SIZE, + [4] = CONFIG_USB_HS_CORE_DEVICE_TX4_FIFO_SIZE, + [5] = CONFIG_USB_HS_CORE_DEVICE_TX5_FIFO_SIZE, + [6] = CONFIG_USB_HS_CORE_DEVICE_TX6_FIFO_SIZE, + [7] = CONFIG_USB_HS_CORE_DEVICE_TX7_FIFO_SIZE, + [8] = CONFIG_USB_HS_CORE_DEVICE_TX8_FIFO_SIZE, + [9] = CONFIG_USB_HS_CORE_DEVICE_TX9_FIFO_SIZE, [10] = CONFIG_USB_HS_CORE_DEVICE_TX10_FIFO_SIZE, [11] = CONFIG_USB_HS_CORE_DEVICE_TX11_FIFO_SIZE, [12] = CONFIG_USB_HS_CORE_DEVICE_TX12_FIFO_SIZE, [13] = CONFIG_USB_HS_CORE_DEVICE_TX13_FIFO_SIZE, [14] = CONFIG_USB_HS_CORE_DEVICE_TX14_FIFO_SIZE, - [15] = CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE - }, + [15] = CONFIG_USB_HS_CORE_DEVICE_TX15_FIFO_SIZE }, .total_fifo_size = CONFIG_USB_HS_CORE_TOTAL_FIFO_SIZE, .host_dma_desc_enable = false, @@ -149,13 +146,13 @@ void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params) } #endif -#define BOARD_INIT_USB_HOST_MODE (0U) -#define BOARD_INIT_USB_DEVICE_MODE (1U) +#define BOARD_INIT_USB_HOST_MODE (0U) +#define BOARD_INIT_USB_DEVICE_MODE (1U) extern rt_err_t rt_hw_usbfs_board_init(uint8_t devmode); static uint8_t g_usb_fs_busid = 0U; #if defined(HC32F4A0) || defined(HC32F4A8) - extern rt_err_t rt_hw_usbhs_board_init(uint8_t devmode); - static uint8_t g_usb_hs_busid = 0U; +extern rt_err_t rt_hw_usbhs_board_init(uint8_t devmode); +static uint8_t g_usb_hs_busid = 0U; #endif #if defined(RT_CHERRYUSB_HOST) @@ -218,7 +215,6 @@ void usb_hc_low_level_init(struct usbh_bus *bus) usbh_fs_irq_handler, RT_TRUE); } - } #endif diff --git a/bsp/hc32/platform/fal/fal_flash_sfud_nor.c b/bsp/hc32/platform/fal/fal_flash_sfud_nor.c index d1f9be24ee9..dd41523bb7a 100644 --- a/bsp/hc32/platform/fal/fal_flash_sfud_nor.c +++ b/bsp/hc32/platform/fal/fal_flash_sfud_nor.c @@ -11,17 +11,17 @@ #include #include #ifdef RT_USING_SFUD - #include +#include #endif #ifndef FAL_USING_NOR_FLASH_DEV_NAME - #define FAL_USING_NOR_FLASH_DEV_NAME "w25q64" +#define FAL_USING_NOR_FLASH_DEV_NAME "w25q64" #endif -#define EXT_NOR_FLASH_START_ADDR 0 -#define EXT_NOR_FLASH_CHIP_SIZE 8 * 1024 * 1024 -#define EXT_NOR_FLASH_BLOCK_SIZE 4096 -#define EXT_NOR_FLASH_WR_MIN_GRAN 1 +#define EXT_NOR_FLASH_START_ADDR 0 +#define EXT_NOR_FLASH_CHIP_SIZE 8 * 1024 * 1024 +#define EXT_NOR_FLASH_BLOCK_SIZE 4096 +#define EXT_NOR_FLASH_WR_MIN_GRAN 1 static int init(void); @@ -31,13 +31,12 @@ static int erase(long offset, rt_size_t size); static sfud_flash_t sfud_dev = NULL; -struct fal_flash_dev ext_nor_flash0 = -{ - .name = FAL_USING_NOR_FLASH_DEV_NAME, - .addr = EXT_NOR_FLASH_START_ADDR, - .len = EXT_NOR_FLASH_CHIP_SIZE, - .blk_size = EXT_NOR_FLASH_BLOCK_SIZE, - .ops = {init, read, write, erase}, +struct fal_flash_dev ext_nor_flash0 = { + .name = FAL_USING_NOR_FLASH_DEV_NAME, + .addr = EXT_NOR_FLASH_START_ADDR, + .len = EXT_NOR_FLASH_CHIP_SIZE, + .blk_size = EXT_NOR_FLASH_BLOCK_SIZE, + .ops = { init, read, write, erase }, .write_gran = EXT_NOR_FLASH_WR_MIN_GRAN, }; @@ -52,7 +51,7 @@ static int init(void) } /* update the flash chip information */ ext_nor_flash0.blk_size = sfud_dev->chip.erase_gran; - ext_nor_flash0.len = sfud_dev->chip.capacity; + ext_nor_flash0.len = sfud_dev->chip.capacity; return 0; } diff --git a/bsp/hc32/platform/sfud/drv_spi_flash.c b/bsp/hc32/platform/sfud/drv_spi_flash.c index 70ccd18f715..67b4c849994 100644 --- a/bsp/hc32/platform/sfud/drv_spi_flash.c +++ b/bsp/hc32/platform/sfud/drv_spi_flash.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2022-04-28 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-04 CDT Support HC32F467 */ #include @@ -20,35 +22,35 @@ #include "dev_spi_flash.h" #ifdef RT_USING_SFUD - #include "dev_spi_flash_sfud.h" +#include "dev_spi_flash_sfud.h" #endif -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) - #define SPI_BUS_NAME "spi1" - #define SPI_FLASH_DEVICE_NAME "spi10" - #define SPI_FLASH_CHIP "w25q64" - #define SPI_FLASH_SS_PIN GET_PIN(C, 7) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F467) +#define SPI_BUS_NAME "spi1" +#define SPI_FLASH_DEVICE_NAME "spi10" +#define SPI_FLASH_CHIP "w25q64" +#define SPI_FLASH_SS_PIN GET_PIN(C, 7) #elif defined(HC32F460) - #define SPI_BUS_NAME "spi3" - #define SPI_FLASH_DEVICE_NAME "spi30" - #define SPI_FLASH_CHIP "w25q64" - #define SPI_FLASH_SS_PIN GET_PIN(C, 7) +#define SPI_BUS_NAME "spi3" +#define SPI_FLASH_DEVICE_NAME "spi30" +#define SPI_FLASH_CHIP "w25q64" +#define SPI_FLASH_SS_PIN GET_PIN(C, 7) #elif defined(HC32F472) - #define SPI_BUS_NAME "spi1" - #define SPI_FLASH_DEVICE_NAME "spi10" - #define SPI_FLASH_CHIP "w25q64" - #define SPI_FLASH_SS_PIN GET_PIN(B,12) +#define SPI_BUS_NAME "spi1" +#define SPI_FLASH_DEVICE_NAME "spi10" +#define SPI_FLASH_CHIP "w25q64" +#define SPI_FLASH_SS_PIN GET_PIN(B, 12) #elif defined(HC32F334) - #define SPI_BUS_NAME "spi1" - #define SPI_FLASH_DEVICE_NAME "spi10" - #define SPI_FLASH_CHIP "w25q64" - #define SPI_FLASH_SS_PIN GET_PIN(C,1) +#define SPI_BUS_NAME "spi1" +#define SPI_FLASH_DEVICE_NAME "spi10" +#define SPI_FLASH_CHIP "w25q64" +#define SPI_FLASH_SS_PIN GET_PIN(C, 1) #endif -#define SPI_FLASH_CMD_ENABLE_RESET 0x66 -#define SPI_FLASH_CMD_RESET_DEVICE 0x99 +#define SPI_FLASH_CMD_ENABLE_RESET 0x66 +#define SPI_FLASH_CMD_RESET_DEVICE 0x99 /* Partition Name */ -#define FS_PARTITION_NAME "filesystem" +#define FS_PARTITION_NAME "filesystem" #ifdef RT_USING_SFUD diff --git a/bsp/hc32/platform/tca9539/tca9539.c b/bsp/hc32/platform/tca9539/tca9539.c index 7ee4c84281b..b08dd71ae25 100644 --- a/bsp/hc32/platform/tca9539/tca9539.c +++ b/bsp/hc32/platform/tca9539/tca9539.c @@ -1,11 +1,12 @@ /* - * Copyright (c) 2022-2024, Xiaohua Semiconductor Co., Ltd. + * Copyright (c) 2022-2026, Xiaohua Semiconductor Co., Ltd. * * SPDX-License-Identifier: Apache-2.0 * * Change Logs: * Date Author Notes * 2024-02-20 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ #include @@ -24,15 +25,17 @@ * Local pre-processor symbols/macros ('#define') ******************************************************************************/ /* Define for TCA9539 */ -#define BSP_TCA9539_I2C_BUS_NAME "i2c1" -#define BSP_TCA9539_DEV_ADDR (0x74U) +#define BSP_TCA9539_I2C_BUS_NAME "i2c1" +#define BSP_TCA9539_DEV_ADDR (0x74U) -#if defined(HC32F4A0) || defined(HC32F4A8) - #define TCA9539_RST_PIN (45) /* PC13 */ +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) +#define TCA9539_RST_PIN (45) /* PC13 */ #elif defined(HC32F448) - #define TCA9539_RST_PIN (31) /* PB15 */ +#define TCA9539_RST_PIN (31) /* PB15 */ #elif defined(HC32F472) - #define TCA9539_RST_PIN (44) /* PC12 */ +#define TCA9539_RST_PIN (44) /* PC12 */ +#elif defined(HC32F467) +#define TCA9539_RST_PIN (141) /* PI13 */ #endif /******************************************************************************* @@ -78,10 +81,10 @@ static rt_err_t BSP_TCA9539_I2C_Write(struct rt_i2c_bus_device *bus, rt_uint8_t return -RT_ERROR; } } - msgs.addr = BSP_TCA9539_DEV_ADDR; - msgs.flags = RT_I2C_WR; - msgs.buf = buf; - msgs.len = len + 1; + msgs.addr = BSP_TCA9539_DEV_ADDR; + msgs.flags = RT_I2C_WR; + msgs.buf = buf; + msgs.len = len + 1; if (rt_i2c_transfer(bus, &msgs, 1) == 1) { return RT_EOK; @@ -110,10 +113,10 @@ static rt_err_t BSP_TCA9539_I2C_Read(struct rt_i2c_bus_device *bus, rt_uint8_t r { return -RT_ERROR; } - msgs.addr = BSP_TCA9539_DEV_ADDR; - msgs.flags = RT_I2C_RD; - msgs.buf = data; - msgs.len = len; + msgs.addr = BSP_TCA9539_DEV_ADDR; + msgs.flags = RT_I2C_RD; + msgs.buf = data; + msgs.len = len; if (rt_i2c_transfer(bus, &msgs, 1) == 1) { return RT_EOK; @@ -137,6 +140,10 @@ static void TCA9539_Reset(void) rt_pin_write(TCA9539_RST_PIN, PIN_LOW); rt_thread_mdelay(3U); rt_pin_write(TCA9539_RST_PIN, PIN_HIGH); +#if defined(HC32F467) + rt_thread_mdelay(3U); + rt_pin_write(TCA9539_RST_PIN, PIN_LOW); // reused MD pin, logic low level to reset +#endif } /** diff --git a/bsp/hc32/platform/tca9539/tca9539.h b/bsp/hc32/platform/tca9539/tca9539.h index 76ed6ed3d4f..6d8531276fc 100644 --- a/bsp/hc32/platform/tca9539/tca9539.h +++ b/bsp/hc32/platform/tca9539/tca9539.h @@ -17,14 +17,14 @@ * @defgroup TCA9539_REGISTER_Definition TCA9539 Register Definition * @{ */ -#define TCA9539_REG_INPUT_PORT0 (0x00U) -#define TCA9539_REG_INPUT_PORT1 (0x01U) -#define TCA9539_REG_OUTPUT_PORT0 (0x02U) -#define TCA9539_REG_OUTPUT_PORT1 (0x03U) -#define TCA9539_REG_INVERT_PORT0 (0x04U) -#define TCA9539_REG_INVERT_PORT1 (0x05U) -#define TCA9539_REG_CONFIG_PORT0 (0x06U) -#define TCA9539_REG_CONFIG_PORT1 (0x07U) +#define TCA9539_REG_INPUT_PORT0 (0x00U) +#define TCA9539_REG_INPUT_PORT1 (0x01U) +#define TCA9539_REG_OUTPUT_PORT0 (0x02U) +#define TCA9539_REG_OUTPUT_PORT1 (0x03U) +#define TCA9539_REG_INVERT_PORT0 (0x04U) +#define TCA9539_REG_INVERT_PORT1 (0x05U) +#define TCA9539_REG_CONFIG_PORT0 (0x06U) +#define TCA9539_REG_CONFIG_PORT1 (0x07U) /** * @} */ @@ -33,8 +33,8 @@ * @defgroup TCA9539_Port_Definition TCA9539 Port Definition * @{ */ -#define TCA9539_IO_PORT0 (0x00U) -#define TCA9539_IO_PORT1 (0x01U) +#define TCA9539_IO_PORT0 (0x00U) +#define TCA9539_IO_PORT1 (0x01U) /** * @} */ @@ -43,15 +43,15 @@ * @defgroup TCA9539_Pin_Definition TCA9539 Pin Definition * @{ */ -#define TCA9539_IO_PIN0 (0x01U) -#define TCA9539_IO_PIN1 (0x02U) -#define TCA9539_IO_PIN2 (0x04U) -#define TCA9539_IO_PIN3 (0x08U) -#define TCA9539_IO_PIN4 (0x10U) -#define TCA9539_IO_PIN5 (0x20U) -#define TCA9539_IO_PIN6 (0x40U) -#define TCA9539_IO_PIN7 (0x80U) -#define TCA9539_IO_PIN_ALL (0xFFU) +#define TCA9539_IO_PIN0 (0x01U) +#define TCA9539_IO_PIN1 (0x02U) +#define TCA9539_IO_PIN2 (0x04U) +#define TCA9539_IO_PIN3 (0x08U) +#define TCA9539_IO_PIN4 (0x10U) +#define TCA9539_IO_PIN5 (0x20U) +#define TCA9539_IO_PIN6 (0x40U) +#define TCA9539_IO_PIN7 (0x80U) +#define TCA9539_IO_PIN_ALL (0xFFU) /** * @} */ @@ -60,8 +60,8 @@ * @defgroup TCA9539_Direction_Definition TCA9539 Direction Definition * @{ */ -#define TCA9539_DIR_OUT (0x00U) -#define TCA9539_DIR_IN (0x01U) +#define TCA9539_DIR_OUT (0x00U) +#define TCA9539_DIR_IN (0x01U) /** * @} */ @@ -70,8 +70,8 @@ * @defgroup TCA9539_Pin_State_Definition TCA9539 Pin State Definition * @{ */ -#define TCA9539_PIN_RESET (0x00U) -#define TCA9539_PIN_SET (0x01U) +#define TCA9539_PIN_RESET (0x00U) +#define TCA9539_PIN_SET (0x01U) /** * @} */ diff --git a/bsp/hc32/tests/SConscript b/bsp/hc32/tests/SConscript index 3733761301b..74d279fda2a 100644 --- a/bsp/hc32/tests/SConscript +++ b/bsp/hc32/tests/SConscript @@ -15,7 +15,9 @@ if GetDepend(['RT_USING_SERIAL']): src += ['test_uart_v1.c'] if GetDepend(['BSP_USING_SPI']): - src += ['test_spi.c'] + # don't add test file when use RT_USB_DEVICE_MSTORAGE + if not (GetDepend(['BSP_USING_USBD']) and GetDepend(['RT_USB_DEVICE_MSTORAGE'])): + src += ['test_spi.c'] if GetDepend(['BSP_USING_QSPI']): src += ['test_qspi.c'] @@ -66,6 +68,7 @@ if GetDepend(['BSP_USING_INPUT_CAPTURE']): if GetDepend(['BSP_USING_PM']): src += ['test_pm.c'] + src += ['test_wktm.c'] if GetDepend('BSP_USING_HWCRYPTO'): src += ['test_crypto.c'] diff --git a/bsp/hc32/tests/test_adc.c b/bsp/hc32/tests/test_adc.c index abe95b0c9da..5eb8ad3b57b 100644 --- a/bsp/hc32/tests/test_adc.c +++ b/bsp/hc32/tests/test_adc.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ /* @@ -22,29 +23,33 @@ #ifdef BSP_USING_ADC -#define REFER_VOLTAGE 3300 /* 参考电压 3.3V,单位mv */ -#define CONVERT_BITS (1 << 12) /* 转换位数为12位 */ +#define REFER_VOLTAGE 3300 /* 参考电压 3.3V,单位mv */ +#define CONVERT_BITS (1 << 12) /* 转换位数为12位 */ /* ADC Channel Max */ -#if defined (HC32F460) - #define ADC1_CH_MAX (16U) - #define ADC2_CH_MAX (8U) -#elif defined (HC32F472) - #define ADC1_CH_MAX (21U) - #define ADC2_CH_MAX (21U) - #define ADC3_CH_MAX (22U) -#elif defined (HC32F4A0) || defined (HC32F4A8) - #define ADC1_CH_MAX (16U) - #define ADC2_CH_MAX (16U) - #define ADC3_CH_MAX (20U) -#elif defined (HC32F448) - #define ADC1_CH_MAX (16U) - #define ADC2_CH_MAX (8U) - #define ADC3_CH_MAX (12U) -#elif defined (HC32F334) - #define ADC1_CH_MAX (16U) - #define ADC2_CH_MAX (12U) - #define ADC3_CH_MAX (10U) +#if defined(HC32F460) +#define ADC1_CH_MAX (16U) +#define ADC2_CH_MAX (8U) +#elif defined(HC32F472) +#define ADC1_CH_MAX (21U) +#define ADC2_CH_MAX (21U) +#define ADC3_CH_MAX (22U) +#elif defined(HC32F467) +#define ADC1_CH_MAX (16U) +#define ADC2_CH_MAX (16U) +#define ADC3_CH_MAX (16U) +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) +#define ADC1_CH_MAX (16U) +#define ADC2_CH_MAX (16U) +#define ADC3_CH_MAX (20U) +#elif defined(HC32F448) +#define ADC1_CH_MAX (16U) +#define ADC2_CH_MAX (8U) +#define ADC3_CH_MAX (12U) +#elif defined(HC32F334) +#define ADC1_CH_MAX (16U) +#define ADC2_CH_MAX (12U) +#define ADC3_CH_MAX (10U) #endif @@ -59,7 +64,7 @@ rt_err_t adc_dma_trig_config(void) { stc_tmr0_init_t stcTmr0Init; -#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || defined (HC32F334) +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) || defined(HC32F467) FCG_Fcg2PeriphClockCmd(FCG2_PERIPH_TMR0_1, ENABLE); #endif (void)TMR0_StructInit(&stcTmr0Init); @@ -105,7 +110,7 @@ static int adc_vol_sample(int argc, char **argv) rt_strcpy(adc_device, "adc2"); adc_max_channel = ADC2_CH_MAX; } -#if defined (HC32F472) || defined (HC32F4A0) || defined (HC32F448) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) || defined(HC32F467) else if (0 == rt_strcmp(argv[1], "adc3")) { rt_strcpy(adc_device, "adc3"); @@ -131,8 +136,8 @@ static int adc_vol_sample(int argc, char **argv) /* DMA配置 */ adc_priv.flag = ADC_USING_EOCA_DMA_FLAG; priv_ops.dma_trig_config = &adc_dma_trig_config; - priv_ops.dma_trig_start = &adc_dma_trig_start; - priv_ops.dma_trig_stop = &adc_dma_trig_stop; + priv_ops.dma_trig_start = &adc_dma_trig_start; + priv_ops.dma_trig_stop = &adc_dma_trig_stop; adc_priv.ops = &priv_ops; adc_dev->parent.user_data = &adc_priv; #endif @@ -148,7 +153,7 @@ static int adc_vol_sample(int argc, char **argv) /* 转换为对应电压值 */ vol = value * REFER_VOLTAGE / CONVERT_BITS; rt_kprintf("Simulate voltage is :%d mv\r\n", vol); - vol = rt_adc_voltage(adc_dev, adc_channel); + vol = rt_adc_voltage(adc_dev, adc_channel); rt_kprintf("Read voltage is :%d mv\r\n", vol); rt_kprintf("*********************\r\n"); } @@ -157,5 +162,5 @@ static int adc_vol_sample(int argc, char **argv) } /* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(adc_vol_sample, adc convert sample: select < adc1 | adc2 | adc3 >); +MSH_CMD_EXPORT(adc_vol_sample, adc convert sample : select); #endif diff --git a/bsp/hc32/tests/test_can.c b/bsp/hc32/tests/test_can.c index b96471eacae..3eeccfc2554 100644 --- a/bsp/hc32/tests/test_can.c +++ b/bsp/hc32/tests/test_can.c @@ -10,16 +10,23 @@ /* * 功能 -* 展示 CAN1、CAN2、CAN3 接收消息和回发消息。 -* 代码使用方法 -* 在终端执行：can_sample 参数选择：can1 | can2 | can3 以启动CAN收发测试 +* 测试 can 和 mcan 接收消息和回发消息 +* 注：mcan 仅部分系列MCU支持(参考宏定义MCAN_DEV_CNT) +* +* 测试方法 +* 连接 can 测试设备与MCU can(mcan）： +* 注：MCU can(mcan）通信引脚的配置位于 board_config.h， +* 若测试单元的通信引脚未配置，需测试人员自行添加，并于board_config.c中做初始化 +* 初始化测试: 在终端按需执行：can_sample canx 或 can_sample mcany +* 其中x和y是单元号， x = 1 ~ CAN_DEV_CNT, y = 1 ~ MCAN_DEV_CNT +* 测试：can 测试设备发送满足过滤条件的消息（见后文：接收和发送消息） +* 终端打印接收到的ID和消息，并将消息原样发回给测试设备。 * * 默认波特率 * 仲裁段:波特率500K,采样率80% * 数据段:波特率为4M,采样率80% (仅支持CAN FD的单元) * * 接收和发送消息 -* CAN1: * 仅接收满足以下过滤条件的消息，并发送接收到的消息 * 1）标准帧：match ID:0x100~0x1ff * 2）扩展帧：match ID:0x12345100~0x123451ff @@ -57,13 +64,29 @@ #include "rtdevice.h" #include "drv_can.h" -#define MSH_USAGE_CAN_SAMPLE "can_sample - open can device and test\n" -#define MSH_USAGE_CAN_SET_BAUD "can set_baud - set can baud\n" -#define MSH_USAGE_CAN_SET_BAUDFD "can set_baudfd - set can baudfd\n" -#define MSH_USAGE_CAN_SET_BITTIMING "can set_bittiming - set can bit timing,\n" -#define MSH_USAGE_CAN_SEND_MSG "can send_msg \n" +#if defined(HC32F452) || defined(HC32F460) +#define CAN_DEV_CNT (1) +#elif defined(HC32F472) +#define CAN_DEV_CNT (3) +#elif defined(HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) +#define CAN_DEV_CNT (2) +#endif + +#if defined(HC32F334) || defined(HC32F336) || defined(HC32F448) || defined(HC32F4A8) +#define MCAN_DEV_CNT (2) +#elif defined(HC32K118) +#define MCAN_DEV_CNT (1) +#elif defined(HC32F558) +#define MCAN_DEV_CNT (3) +#endif + +#define MSH_USAGE_CAN_SAMPLE "can_sample - open can device and test\n" +#define MSH_USAGE_CAN_SET_BAUD "can set_baud - set can baud\n" +#define MSH_USAGE_CAN_SET_BAUDFD "can set_baudfd - set can baudfd\n" +#define MSH_USAGE_CAN_SET_BITTIMING "can set_bittiming - set can bit timing,\n" +#define MSH_USAGE_CAN_SEND_MSG "can send_msg \n" -#define MSH_RESULT_STR(result) ((result == RT_EOK) ? "success" : "failure") +#define MSH_RESULT_STR(result) ((result == RT_EOK) ? "success" : "failure") static rt_device_t can_dev = RT_NULL; static struct rt_semaphore can_rx_sem; @@ -71,15 +94,18 @@ static rt_mutex_t can_mutex = RT_NULL; static rt_thread_t rx_thread; #ifdef RT_CAN_USING_CANFD -static const uint8_t mcan_data_size[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64}; +static const uint8_t mcan_data_size[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 12, 16, 20, 24, 32, 48, 64 }; #endif -#define CAN_IF_INIT() do { \ - if (can_dev == RT_NULL || can_mutex == RT_NULL) { \ - rt_kprintf("failed! please first execute can_sample cmd!\n"); \ - return; \ - } \ - } while (0) +#define CAN_IF_INIT() \ + do \ + { \ + if (can_dev == RT_NULL || can_mutex == RT_NULL) \ + { \ + rt_kprintf("failed! please first execute can_sample cmd!\n"); \ + return; \ + } \ + } while (0) static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size) { @@ -90,13 +116,12 @@ static rt_err_t can_rx_call(rt_device_t dev, rt_size_t size) static void _set_default_filter(void) { #ifdef RT_CAN_USING_HDR - struct rt_can_filter_item can_items[3] = - { + struct rt_can_filter_item can_items[3] = { RT_CAN_FILTER_ITEM_INIT(0x100, RT_CAN_STDID, RT_CAN_DTR, 1, 0x700, RT_NULL, RT_NULL), /* std,match ID:0x100~0x1ff，过滤表模式为1(0表示标识符列表模式，1表示标识符屏蔽位模式)，hdr = -1(表示不指定过滤表号)，设置默认过滤表，过滤表回调函数和参数均为NULL */ RT_CAN_FILTER_ITEM_INIT(0x12345100, RT_CAN_EXTID, RT_CAN_DTR, 1, 0xFFFFFF00, RT_NULL, RT_NULL), /* ext,match ID:0x12345100~0x123451ff，hdr = -1 */ - {0x555, RT_CAN_STDID, RT_CAN_DTR, 1, 0x7ff, 7} /* std,match ID:0x555，hdr= 7，指定设置7号过滤表 */ + { 0x555, RT_CAN_STDID, RT_CAN_DTR, 1, 0x7ff, 7 } /* std,match ID:0x555，hdr= 7，指定设置7号过滤表 */ }; - struct rt_can_filter_config cfg = {3, 1, can_items}; /* 一共有3个过滤表，1表示初始化过滤表控制块 */ + struct rt_can_filter_config cfg = { 3, 1, can_items }; /* 一共有3个过滤表，1表示初始化过滤表控制块 */ rt_err_t res; res = rt_device_control(can_dev, RT_CAN_CMD_SET_FILTER, &cfg); RT_ASSERT(res == RT_EOK); @@ -121,8 +146,8 @@ static uint8_t _get_can_data_bytes_len(uint32_t dlc) static void can_rx_thread(void *parameter) { - struct rt_can_msg rxmsg = {0}; - rt_size_t size; + struct rt_can_msg rxmsg = { 0 }; + rt_size_t size; uint8_t data_len; while (1) @@ -173,7 +198,7 @@ static void _msh_cmd_set_baud(int argc, char **argv) } #ifdef RT_CAN_USING_CANFD -void _msh_cmd_set_timing(int argc, char **argv) +static void _msh_cmd_set_timing(int argc, char **argv) { rt_err_t result; @@ -190,17 +215,17 @@ void _msh_cmd_set_timing(int argc, char **argv) struct rt_can_bit_timing_config cfg; uint32_t pos = 3; items[0].prescaler = atoi(argv[pos++]); - items[0].num_seg1 = atoi(argv[pos++]); - items[0].num_seg2 = atoi(argv[pos++]); - items[0].num_sjw = atoi(argv[pos++]); + items[0].num_seg1 = atoi(argv[pos++]); + items[0].num_seg2 = atoi(argv[pos++]); + items[0].num_sjw = atoi(argv[pos++]); items[0].num_sspoff = atoi(argv[pos++]); if (count > 1) { - items[1].prescaler = atoi(argv[pos++]); - items[1].num_seg1 = atoi(argv[pos++]); - items[1].num_seg2 = atoi(argv[pos++]); - items[1].num_sjw = atoi(argv[pos++]); - items[1].num_sspoff = atoi(argv[pos]); + items[1].prescaler = atoi(argv[pos++]); + items[1].num_seg1 = atoi(argv[pos++]); + items[1].num_seg2 = atoi(argv[pos++]); + items[1].num_sjw = atoi(argv[pos++]); + items[1].num_sspoff = atoi(argv[pos]); } cfg.count = count; cfg.items = items; @@ -218,7 +243,7 @@ void _msh_cmd_set_timing(int argc, char **argv) } } -void _msh_cmd_set_baudfd(int argc, char **argv) +static void _msh_cmd_set_baudfd(int argc, char **argv) { rt_err_t result; @@ -239,10 +264,10 @@ void _msh_cmd_set_baudfd(int argc, char **argv) } #endif -void _msh_cmd_send_msg(int argc, char **argv) +static void _msh_cmd_send_msg(int argc, char **argv) { - rt_size_t size; - struct rt_can_msg msg = {0}; + rt_size_t size; + struct rt_can_msg msg = { 0 }; uint8_t u8Tick; if (argc == 2) @@ -250,7 +275,7 @@ void _msh_cmd_send_msg(int argc, char **argv) CAN_IF_INIT(); rt_mutex_take(can_mutex, RT_WAITING_FOREVER); #ifdef RT_CAN_USING_CANFD - msg.id = 0x300; + msg.id = 0x300; msg.ide = RT_CAN_STDID; msg.rtr = RT_CAN_DTR; msg.len = 0xFU; @@ -261,7 +286,7 @@ void _msh_cmd_send_msg(int argc, char **argv) msg.data[u8Tick] = u8Tick + 1 + 0xA0; } #else - msg.id = 0x300; + msg.id = 0x300; msg.ide = RT_CAN_STDID; msg.rtr = RT_CAN_DTR; #ifdef BSP_USING_MCAN @@ -291,7 +316,7 @@ void _msh_cmd_send_msg(int argc, char **argv) } } -void _show_usage(void) +static void _show_usage(void) { rt_kprintf("Usage: \n"); rt_kprintf(MSH_USAGE_CAN_SET_BAUD); @@ -405,4 +430,4 @@ int can_sample(int argc, char **argv) return -RT_ERROR; } } -MSH_CMD_EXPORT(can_sample, can sample: select < can1 | can2 | mcan1 | mcan2 >); +MSH_CMD_EXPORT(can_sample, can sample : select); diff --git a/bsp/hc32/tests/test_cherryusb.c b/bsp/hc32/tests/test_cherryusb.c index d8223826e70..568b0697b53 100644 --- a/bsp/hc32/tests/test_cherryusb.c +++ b/bsp/hc32/tests/test_cherryusb.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2025-08-08 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include #include @@ -15,18 +17,18 @@ */ #if defined(RT_CHERRYUSB_HOST) && defined(RT_CHERRYUSB_DEVICE) - #if defined(HC32F4A0) || defined(HC32F4A8) - #define TEST_USBH_CORE_BASE (CM_USBFS_BASE) - #define TEST_USBD_CORE_BASE (CM_USBHS_BASE) - #else - #error "Only one USB role can be selected" - #endif +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) +#define TEST_USBH_CORE_BASE (CM_USBFS_BASE) +#define TEST_USBD_CORE_BASE (CM_USBHS_BASE) #else - #if defined(RT_CHERRYUSB_HOST) - #define TEST_USBH_CORE_BASE (CM_USBFS_BASE) - #elif defined(RT_CHERRYUSB_DEVICE) - #define TEST_USBD_CORE_BASE (CM_USBFS_BASE) - #endif +#error "Only one USB role can be selected" +#endif +#else +#if defined(RT_CHERRYUSB_HOST) +#define TEST_USBH_CORE_BASE (CM_USBFS_BASE) +#elif defined(RT_CHERRYUSB_DEVICE) +#define TEST_USBD_CORE_BASE (CM_USBFS_BASE) +#endif #endif #if defined(RT_CHERRYUSB_HOST) @@ -34,8 +36,7 @@ #if defined(RT_CHERRYUSB_HOST_CDC_ECM) || defined(RT_CHERRYUSB_HOST_CDC_RNDIS) || defined(RT_CHERRYUSB_HOST_MSC) /* 使用USB Host 时，应确保主机对设备供电充足 - menuconfig: ECM 关键配置 - + ************************* menuconfig: ECM 关键配置 ************************* RT-Thread Kernel --->[*] Enable soft timer with a timer thread (4096) The stack size of timer thread @@ -55,25 +56,11 @@ ... [*] Enable ping features - 备注:CherryUSB Host枚举设备时，默认选择Configuration 1，若指定设备(如CH397A模组CDC-ECM模式)需要选择Configuration 2，需在 - components/drivers/usb/cherryusb/core/usbh_core.c文件中usbh_enumerate()函数内添加如下代码： - int usbh_enumerate(struct usbh_hubport *hport) - { - ... - config_index = 0; - // Add code start - if((0x1A86 == ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->idVendor) && \ - (0x5397 == ((struct usb_device_descriptor *)ep0_request_buffer[hport->bus->busid])->idProduct)) { - config_index = 1; // For CH397, we need to select configuration 2 - } - // Add code end - USB_LOG_DBG("The device selects config %d\r\n", config_index); - ... - } - - - menuconfig: MSC 关键配置 + 备注:CherryUSB Host枚举设备时，默认选择Configuration 1，若指定设备(如CH397A模组CDC-ECM模式)需要选择Configuration 2，重新定义 + uint8_t usbh_get_hport_active_config_index(struct usbh_hubport *hport)。 + + ************************* menuconfig: MSC 关键配置 ************************* RT-Thread Kernel --->[*] Enable soft timer with a timer thread (4096) The stack size of timer thread @@ -84,7 +71,6 @@ [*] Enable usb msc driver ... (/)usb host dfs mount point - */ @@ -107,7 +93,7 @@ msh />ping www.baidu.com */ static int cherryusb_host_init(void) { - usbh_initialize(0, TEST_USBH_CORE_BASE); + usbh_initialize(0, TEST_USBH_CORE_BASE, RT_NULL); return 0; } INIT_APP_EXPORT(cherryusb_host_init); @@ -119,6 +105,18 @@ void ipconfig(void) list_if(); } MSH_CMD_EXPORT(ipconfig, list network interface information); + +uint8_t usbh_get_hport_active_config_index(struct usbh_hubport *hport) +{ + uint8_t config_index = 0U; /* Default to configuration index 0 */ + + if ((0x1A86U == hport->device_desc.idVendor) && (0x5397U == hport->device_desc.idProduct)) + { + config_index = 1U; /* For CH397, we need to select configuration 2 */ + } + + return config_index; +} #endif #endif @@ -127,18 +125,17 @@ MSH_CMD_EXPORT(ipconfig, list network interface information); #if defined(RT_CHERRYUSB_DEVICE) #if defined(RT_CHERRYUSB_DEVICE_TEMPLATE_CDC_ACM) /* - menuconfig:关键配置 - + ************************* menuconfig: ACM 关键配置 ************************* RT-Thread Components--->Devicee Drivers--->[*] Using USB with CherryUSB [*] Enable usb device mode - Selectot usb host ip.... ---> + Selectot usb device ip.... ---> [*]dwc2_hc [*] Enable usb cdc acm device Select usb device template...---> [*] cdc acm */ -static int cherryusb_device_cdc_acm_init(void) +static int cherryusb_device_cdc_acm_init(void) { extern void cdc_acm_init(uint8_t busid, uint32_t reg_base); cdc_acm_init(0, TEST_USBD_CORE_BASE); diff --git a/bsp/hc32/tests/test_clock_timer.c b/bsp/hc32/tests/test_clock_timer.c index b5536b9bed7..649bf35a4fb 100644 --- a/bsp/hc32/tests/test_clock_timer.c +++ b/bsp/hc32/tests/test_clock_timer.c @@ -151,7 +151,8 @@ static int clock_timer_sample(int argc, char *argv[]) } /* 确保oneshot模式cb函数执行一次后才关闭定时器 */ - while (cb_run == RT_FALSE); + while (cb_run == RT_FALSE) + ; cb_run = RT_FALSE; /* close */ @@ -160,5 +161,5 @@ static int clock_timer_sample(int argc, char *argv[]) return ret; } /* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample: devname [oneshot | period] timeout); +MSH_CMD_EXPORT(clock_timer_sample, clock_timer sample : devname[oneshot | period] timeout); #endif diff --git a/bsp/hc32/tests/test_crypto.c b/bsp/hc32/tests/test_crypto.c index 439433723af..9eff8fa527a 100644 --- a/bsp/hc32/tests/test_crypto.c +++ b/bsp/hc32/tests/test_crypto.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include @@ -15,15 +17,17 @@ #if defined(BSP_USING_HWCRYPTO) -#define ARR_SIZE(arr) (sizeof(arr)/sizeof(*arr)) -#define PRINT_DIGIT_ARR(arr) do { \ - rt_kprintf("%s: ", #arr); \ - for(int i = 0; i < ARR_SIZE(arr); i++) \ - rt_kprintf("%d ", arr[i]); \ - rt_kprintf("\n"); \ - } while(0) +#define ARR_SIZE(arr) (sizeof(arr) / sizeof(*arr)) +#define PRINT_DIGIT_ARR(arr) \ + do \ + { \ + rt_kprintf("%s: ", #arr); \ + for (int i = 0; i < ARR_SIZE(arr); i++) \ + rt_kprintf("%d ", arr[i]); \ + rt_kprintf("\n"); \ + } while (0) -#define WDT_DEVICE_NAME "crypto" +#define WDT_DEVICE_NAME "crypto" static void _crypto_cmd_print_usage(void) { @@ -44,7 +48,8 @@ static void _crypto_cmd_print_usage(void) rt_kprintf(" aes: test aes module. \n"); #if defined(HC32F460) rt_kprintf(" e.g. msh >crypto_sample aes 128 \n"); -#elif defined (HC32F4A0) || defined (HC32F448) || defined (HC32F472) || defined (HC32F4A8) +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F472) || defined(HC32F4A8) || \ + defined(HC32F467) rt_kprintf(" e.g. msh >crypto_sample aes 128/192/256 \n"); #endif #endif @@ -58,23 +63,22 @@ static void _crypto_cmd_print_usage(void) #if defined(BSP_USING_CRC) /* menuconfig: - Hardware Drivers Config--->On-Chip Peripheral Driver--->Using Hardware Crypto ---> - [*]Enable Hardeware CRC + Hardware Drivers Config--->On-Chip Peripheral Driver--->Using Hardware Crypto Drivers ---> + [*]Using Hardeware CRC * CRC16命令调用：crypto_sample crc 16 * CRC32命令调用：crypto_sample crc 32 * 程序功能：打印CRC输入数据和计数结果，使用第三方软件计算数据，再做比较 */ -#define CRC16_WIDTH 16U -#define CRC32_WIDTH 32U +#define CRC16_WIDTH 16U +#define CRC32_WIDTH 32U static void crc_test(rt_uint32_t width) { - rt_uint8_t temp_in[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9}; + rt_uint8_t temp_in[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 }; struct rt_hwcrypto_ctx *ctx; rt_uint32_t result = 0; /* CRC16_X25 */ - struct hwcrypto_crc_cfg cfg = - { + struct hwcrypto_crc_cfg cfg = { .last_val = 0xFFFFU, .poly = 0x1021U, .width = CRC16_WIDTH, @@ -110,19 +114,27 @@ static void crc_test(rt_uint32_t width) } rt_kprintf("\n"); result = rt_hwcrypto_crc_update(ctx, temp_in, sizeof(temp_in) / 2U); - rt_kprintf("crc%d result: 0x%x \n", width, result); + rt_kprintf("crc%d expect_result: 0x%X \n", width, (width == 16) ? 0x0A38 : 0x515Ad3CC); + rt_kprintf(" calc_result: 0x%X \n\n", result); /* Accumulate test */ PRINT_DIGIT_ARR(temp_in); result = rt_hwcrypto_crc_update(ctx, &temp_in[sizeof(temp_in) / 2U], sizeof(temp_in) / 2U); - rt_kprintf("crc%d result: 0x%x \n", width, result); + rt_kprintf("crc%d expect_result: 0x%X \n", width, (width == 16) ? 0x2FE2 : 0x456CD746); + rt_kprintf(" calc_result: 0x%X \n\n", result); rt_hwcrypto_crc_destroy(ctx); } #endif #if defined(BSP_USING_AES) -#define AES_DATA_LEN 32U /* data of length must be a multiple of 16(128 Bit) */ +/* menuconfig: + Hardware Drivers Config--->On-Chip Peripheral Driver--->Using Hardware Crypto Drivers ---> + [*]Using Hardeware AES + * AES命令调用：crypto_sample aes 128/192/256 + * 程序功能：打印明文、密文、密文解密后的数据 + */ +#define AES_DATA_LEN 32U /* data of length must be a multiple of 16(128 Bit) */ static void aes_test(rt_uint16_t key_bitlen) { rt_uint32_t result = RT_EOK; @@ -135,23 +147,21 @@ static void aes_test(rt_uint16_t key_bitlen) const char *key256 = "1234567890abcdefghijklmnopqrstuv"; const char *key; rt_uint8_t type_max = 1U; - hwcrypto_type types[] = - { + hwcrypto_type types[] = { HWCRYPTO_TYPE_AES_ECB, HWCRYPTO_TYPE_AES_CBC, HWCRYPTO_TYPE_AES_CTR, HWCRYPTO_TYPE_AES_CFB, HWCRYPTO_TYPE_AES_OFB, }; - const char *type_str[] = - { + const char *type_str[] = { "aes_ecb", "aes_cbc", "aes_ctr", "aes_cfb", "aes_ofb", }; -#if defined (HC32F4A8) +#if defined(HC32F4A8) type_max = 5U; #endif for (int i = 0; i < type_max; i++) @@ -178,7 +188,7 @@ static void aes_test(rt_uint16_t key_bitlen) break; } result = rt_hwcrypto_symmetric_setkey(ctx, (rt_uint8_t *)key, key_bitlen); -#if defined (HC32F4A8) +#if defined(HC32F4A8) const char *iv = "1234567812345678"; result = rt_hwcrypto_symmetric_setiv(ctx, (const rt_uint8_t *)iv, strlen(iv)); #endif @@ -214,9 +224,9 @@ static void aes_test(rt_uint16_t key_bitlen) { rt_kprintf("%c", dec_out[i]); } - rt_kprintf("\n"); + rt_kprintf("\n\n"); -_exit: + _exit: rt_hwcrypto_symmetric_destroy(ctx); } } @@ -224,11 +234,21 @@ static void aes_test(rt_uint16_t key_bitlen) #endif #if defined(BSP_USING_HASH) -#define HASH_SHA256_MSG_DIGEST_SIZE (32U) +/* menuconfig: + Hardware Drivers Config--->On-Chip Peripheral Driver--->Using Hardware Crypto Drivers ---> + [*]Using Hardeware Hash + * Hash命令调用：crypto_sample hash test + * 程序功能：打印hash原始消息、期望的SHA256结果和计算的SHA256结果 + */ +#define HASH_SHA256_MSG_DIGEST_SIZE (32U) static void hash_sha256_test(void) { const char *in = "0123456789abcdefghijklmnopqrstuvwxyz"; - uint8_t out[HASH_SHA256_MSG_DIGEST_SIZE]; + uint8_t calc_out[HASH_SHA256_MSG_DIGEST_SIZE]; + const uint8_t expect_out[HASH_SHA256_MSG_DIGEST_SIZE] = { 0x74, 0xE7, 0xE5, 0xBB, 0x9D, 0x22, 0xD6, 0xDB, 0x26, 0xBF, + 0x76, 0x94, 0x6D, 0x40, 0xFF, 0xF3, 0xEA, 0x9F, 0x03, 0x46, + 0xB8, 0x84, 0xFD, 0x06, 0x94, 0x92, 0x0F, 0xCC, 0xFA, 0xD1, + 0x5E, 0x33 }; struct rt_hwcrypto_ctx *ctx; ctx = rt_hwcrypto_hash_create(rt_hwcrypto_dev_default(), HWCRYPTO_TYPE_SHA256); @@ -242,13 +262,20 @@ static void hash_sha256_test(void) } rt_kprintf("\n"); - rt_hwcrypto_hash_finish(ctx, out, HASH_SHA256_MSG_DIGEST_SIZE); - rt_kprintf("hash out data:"); + rt_hwcrypto_hash_finish(ctx, calc_out, HASH_SHA256_MSG_DIGEST_SIZE); + rt_kprintf("hash out expect_data:"); for (int i = 0; i < HASH_SHA256_MSG_DIGEST_SIZE; i++) { - rt_kprintf("%x ", out[i]); + rt_kprintf("%x ", expect_out[i]); } rt_kprintf("\n"); + + rt_kprintf("hash out calc_data:"); + for (int i = 0; i < HASH_SHA256_MSG_DIGEST_SIZE; i++) + { + rt_kprintf("%x ", calc_out[i]); + } + rt_kprintf("\n\n"); rt_hwcrypto_hash_destroy(ctx); } } @@ -269,7 +296,7 @@ static int crypto_sample(int argc, char *argv[]) if (!rt_strcmp("get", argv[2])) { rt_uint32_t result = rt_hwcrypto_rng_update(); - rt_kprintf("random number = %x \n", result); + rt_kprintf("random number = %x \n\n", result); } else { @@ -330,6 +357,6 @@ static int crypto_sample(int argc, char *argv[]) return -RT_ERROR; } -MSH_CMD_EXPORT(crypto_sample, crypto [option]); +MSH_CMD_EXPORT(crypto_sample, crypto[option]); #endif diff --git a/bsp/hc32/tests/test_dac.c b/bsp/hc32/tests/test_dac.c index 9821993bfa6..02f218edc5c 100644 --- a/bsp/hc32/tests/test_dac.c +++ b/bsp/hc32/tests/test_dac.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT support HC32F4A2 + * 2026-06-05 CDT support HC32F467 */ /* @@ -21,11 +23,11 @@ #ifdef BSP_USING_DAC -#define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ -#define DAC_MAX_OUTPUT_VALUE 4095 +#define REFER_VOLTAGE 330 /* 参考电压 3.3V,数据精度乘以100保留2位小数*/ +#define DAC_MAX_OUTPUT_VALUE 4095 -#if (defined (HC32F4A8) || defined (HC32F4A0)) && defined (BSP_USING_DAC2) - extern void EthPhyDisable(void); +#if (defined(HC32F4A8) || defined(HC32F4A0) || defined(HC32F4A2)) && defined(BSP_USING_DAC2) +extern void EthPhyDisable(void); #endif /* HC32F4A8 && BSP_USING_DAC2 */ static int dac_vol_sample(int argc, char *argv[]) @@ -47,18 +49,18 @@ static int dac_vol_sample(int argc, char *argv[]) rt_strcpy(dac_device_name, "dac1"); max_channel = 2; } -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) || defined (HC32F334) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) || defined(HC32F472) || defined(HC32F4A8) || defined(HC32F334) else if (0 == rt_strcmp(argv[1], "dac2")) { rt_strcpy(dac_device_name, "dac2"); -#if defined (HC32F4A0) || defined (HC32F472) || defined (HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467) || defined(HC32F472) || defined(HC32F4A8) max_channel = 2; -#elif defined (HC32F334) +#elif defined(HC32F334) max_channel = 1; #endif } #endif -#if defined (HC32F472) +#if defined(HC32F472) else if (0 == rt_strcmp(argv[1], "dac3")) { rt_strcpy(dac_device_name, "dac3"); @@ -76,7 +78,7 @@ static int dac_vol_sample(int argc, char *argv[]) return -RT_ERROR; } } -#if (defined (HC32F4A8) || defined (HC32F4A0)) && defined (BSP_USING_DAC2) +#if (defined(HC32F4A8) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467)) && defined(BSP_USING_DAC2) EthPhyDisable(); #endif /* 查找设备 */ @@ -117,5 +119,5 @@ static int dac_vol_sample(int argc, char *argv[]) return ret; } /* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(dac_vol_sample, dac voltage convert sample < dac1 | dac2 value >); +MSH_CMD_EXPORT(dac_vol_sample, dac voltage convert sample); #endif diff --git a/bsp/hc32/tests/test_eth.c b/bsp/hc32/tests/test_eth.c index ac726651928..2fa3bde119a 100644 --- a/bsp/hc32/tests/test_eth.c +++ b/bsp/hc32/tests/test_eth.c @@ -29,7 +29,7 @@ * ETH Communication USING MII * 3）拨码开关J33拨到MII端，编译下载、运行代码 * 4）等待msh> - * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.120 icmp_seq=0 ttl=128 time=1 ms） + * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.10 icmp_seq=0 ttl=128 time=1 ms） * 6）msh>窗口输入命令：eth_webserver * 7）PC打开浏览器，输入IP地址：192.168.1.30再按回车键，显示lwip的简介网页（lwIP - A Lightweight TCP/IP Stack）， * 表示成功访问目标板的HTTP服务器。 @@ -41,7 +41,7 @@ * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable ETH PHY interrupt mode: (16) ETH PHY Interrupt pin number * 3）拨码开关J33拨到MII端，编译下载、运行代码 * 4）等待msh> - * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.120 icmp_seq=0 ttl=128 time=1 ms） + * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.10 icmp_seq=0 ttl=128 time=1 ms） * 6）msh>窗口输入命令：eth_webserver * 7）PC打开浏览器，输入IP地址：192.168.1.30再按回车键，显示lwip的简介网页（lwIP - A Lightweight TCP/IP Stack）， * 表示成功访问目标板的HTTP服务器。 @@ -52,10 +52,12 @@ * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable Ethernet: ETH Communication USING RMII * 3）拨码开关J33拨到RMII端，编译下载、运行代码 * 4）等待msh> - * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.120 icmp_seq=0 ttl=128 time=1 ms） + * 5）msh>窗口输入命令：ping 192.168.1.10，显示连接正常（60 bytes from 192.168.1.10 icmp_seq=0 ttl=128 time=1 ms） * 6）msh>窗口输入命令：eth_webserver * 7）PC打开浏览器，输入IP地址：192.168.1.30再按回车键，显示lwip的简介网页（lwIP - A Lightweight TCP/IP Stack）， * 表示成功访问目标板的HTTP服务器。 + * + * 注意：HC32F467仅支持case 3，且步骤3不需要拨码。 */ #include @@ -69,6 +71,6 @@ void eth_webserver(void) rt_kprintf("Initialize the httpd...... \r\n"); httpd_init(); } -MSH_CMD_EXPORT(eth_webserver, eth: start web server); +MSH_CMD_EXPORT(eth_webserver, eth : start web server); #endif diff --git a/bsp/hc32/tests/test_fal.c b/bsp/hc32/tests/test_fal.c index 6acb246a4ad..b06e7bdc8cf 100644 --- a/bsp/hc32/tests/test_fal.c +++ b/bsp/hc32/tests/test_fal.c @@ -16,7 +16,8 @@ * menuconfig: * RT-Thread Components ---> FAL: flash abstraction layer * ---> Device Drivers ---> Using SPI Bus/Device device drivers ---> Using Serial Flash Universal Driver - * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable on-chip FLASH + * Hardware Drivers Config ---> Onboard On-chip Peripheral Drivers ----> Enable on-chip FLASH + * NOTE: 忽略‘[E/SFUD] ERROR: Flash device w25q64 not found!’错误，不影响测试 */ #include #include @@ -26,15 +27,15 @@ #include "board.h" #include -#define FAL_PART_NAME "app" -#define TEST_BUF_SIZE 1024UL -#define TEST_RW_CNT 32UL +#define FAL_PART_NAME "app" +#define TEST_BUF_SIZE 1024UL +#define TEST_RW_CNT 32UL -#define TEST_RW_START_ADDR HC32_FLASH_END_ADDRESS - (TEST_BUF_SIZE * TEST_RW_CNT) +#define TEST_RW_START_ADDR HC32_FLASH_END_ADDRESS - (TEST_BUF_SIZE * TEST_RW_CNT) -static uint8_t write_buffer[TEST_BUF_SIZE] = {0}; -static uint8_t read_buffer[TEST_BUF_SIZE] = {0}; +static uint8_t write_buffer[TEST_BUF_SIZE] = { 0 }; +static uint8_t read_buffer[TEST_BUF_SIZE] = { 0 }; static int fal_sample(int argc, char **argv) @@ -108,8 +109,7 @@ static int fal_sample(int argc, char **argv) for (int i = 0; i < TEST_BUF_SIZE; i++) { #if defined(HC32F460) - if ((j == (TEST_RW_CNT - 1)) && (i >= (TEST_BUF_SIZE - 32)) ? - (read_buffer[i] != 0xFF) : (read_buffer[i] != write_buffer[i])) + if ((j == (TEST_RW_CNT - 1)) && (i >= (TEST_BUF_SIZE - 32)) ? (read_buffer[i] != 0xFF) : (read_buffer[i] != write_buffer[i])) #else if (read_buffer[i] != write_buffer[i]) #endif diff --git a/bsp/hc32/tests/test_gpio.c b/bsp/hc32/tests/test_gpio.c index 9107abe83ff..af6d7a59c63 100644 --- a/bsp/hc32/tests/test_gpio.c +++ b/bsp/hc32/tests/test_gpio.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ /* @@ -27,20 +28,24 @@ * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable TCA9539 */ #if defined(HC32F460) - #define LED1_PIN_NUM GET_PIN(D, 3) /* LED0 */ - #define KEY1_PIN_NUM GET_PIN(B, 1) /* K10 */ -#elif defined(HC32F4A0) || defined(HC32F4A8) - #define LED1_PIN_NUM GET_PIN(B, 11) /* LED10 */ - #define KEY1_PIN_NUM GET_PIN(A, 0) /* K10 */ +#define LED_PIN_NUM GET_PIN(D, 3) /* LED0 */ +#define KEY_PIN_NUM GET_PIN(B, 1) /* K10 */ +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) +#define LED_PIN_NUM GET_PIN(B, 11) /* LED10 */ +#define KEY_PIN_NUM GET_PIN(A, 0) /* K10 */ #elif defined(HC32F448) - #define LED1_PIN_NUM GET_PIN(A, 2) /* LED3 */ - #define KEY1_PIN_NUM GET_PIN(B, 6) /* K5 */ +#define LED_PIN_NUM GET_PIN(A, 2) /* LED3 */ +#define KEY_PIN_NUM GET_PIN(B, 6) /* K5 */ #elif defined(HC32F472) - #define LED1_PIN_NUM GET_PIN(C, 9) /* LED5 */ - #define KEY1_PIN_NUM GET_PIN(B, 5) /* K10 */ +#define LED_PIN_NUM GET_PIN(C, 9) /* LED5 */ +#define KEY_PIN_NUM GET_PIN(B, 5) /* K10 */ #elif defined(HC32F334) - #define LED1_PIN_NUM GET_PIN(C, 13) /* LED1 */ - #define KEY1_PIN_NUM GET_PIN(C, 3) /* K1 */ +#define LED_PIN_NUM GET_PIN(C, 13) /* LED1 */ +#define KEY_PIN_NUM GET_PIN(C, 3) /* K1 */ +#elif defined(HC32F467) + /* NOTE: NEED short J13 to use LED11. */ +#define LED_PIN_NUM GET_PIN(C, 9) /* LED11 */ +#define KEY_PIN_NUM GET_PIN(A, 0) /* K5 */ #endif static uint8_t u8LedState = 1; @@ -50,29 +55,29 @@ void led_control(void *args) u8LedState = !u8LedState; if (0 == u8LedState) { - rt_pin_write(LED1_PIN_NUM, PIN_LOW); + rt_pin_write(LED_PIN_NUM, PIN_LOW); } else { - rt_pin_write(LED1_PIN_NUM, PIN_HIGH); + rt_pin_write(LED_PIN_NUM, PIN_HIGH); } } static void pin_sample(void) { /* LED引脚为输出模式 */ - rt_pin_mode(LED1_PIN_NUM, PIN_MODE_OUTPUT); + rt_pin_mode(LED_PIN_NUM, PIN_MODE_OUTPUT); /* 默认高电平 */ - rt_pin_write(LED1_PIN_NUM, PIN_HIGH); + rt_pin_write(LED_PIN_NUM, PIN_HIGH); /* 按键1引脚为输入模式 */ - rt_pin_mode(KEY1_PIN_NUM, PIN_MODE_INPUT_PULLUP); + rt_pin_mode(KEY_PIN_NUM, PIN_MODE_INPUT_PULLUP); /* 绑定中断，下降沿模式，回调函数名为led_control */ - // rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_RISING, led_control, RT_NULL); - // rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_FALLING, led_control, RT_NULL); - rt_pin_attach_irq(KEY1_PIN_NUM, PIN_IRQ_MODE_RISING_FALLING, led_control, RT_NULL); + // rt_pin_attach_irq(KEY_PIN_NUM, PIN_IRQ_MODE_RISING, led_control, RT_NULL); + // rt_pin_attach_irq(KEY_PIN_NUM, PIN_IRQ_MODE_FALLING, led_control, RT_NULL); + rt_pin_attach_irq(KEY_PIN_NUM, PIN_IRQ_MODE_RISING_FALLING, led_control, RT_NULL); /* 使能中断 */ - rt_pin_irq_enable(KEY1_PIN_NUM, PIN_IRQ_ENABLE); + rt_pin_irq_enable(KEY_PIN_NUM, PIN_IRQ_ENABLE); } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(pin_sample, pin sample); diff --git a/bsp/hc32/tests/test_i2c.c b/bsp/hc32/tests/test_i2c.c index ecfea2f1004..c7d572f324d 100644 --- a/bsp/hc32/tests/test_i2c.c +++ b/bsp/hc32/tests/test_i2c.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ /* @@ -30,47 +31,49 @@ #define USING_RT_I2C_TRANSFER /* defined EEPROM */ -#if defined(HC32F472) || defined(HC32F460) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) || \ - defined(HC32F334) - #define EE_DEV_ADDR 0x50 - #define EE_TEST_PAGE_CNT 8 // Test 8 pages +#if defined(HC32F472) || defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || \ + defined(HC32F4A8) || defined(HC32F334) || defined(HC32F467) +#define EE_DEV_ADDR 0x50 +#define EE_TEST_PAGE_CNT 8 // Test 8 pages #endif /* define EEPROM hardware */ -#if defined(HC32F472) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) - #define EE24C256 -#elif defined(HC32F4A0) - #define EE24C02 +#if defined(HC32F472) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) || \ + defined(HC32F334) || defined(HC32F467) +#define EE24C256 +#elif defined(HC32F4A0) || defined(HC32F4A2) +#define EE24C02 #endif -#if defined (EE24C1024) - #define EE_PAGE_SIZE 256 // 24C1024 - #define EE_WORD_ADR_SIZE 2 // 2 word addr -#elif defined (EE24C256) - #define EE_PAGE_SIZE 64 // 24C256 - #define EE_WORD_ADR_SIZE 2 // 2 word addr -#elif defined (EE24C02) - #define EE_PAGE_SIZE 8 // 24C02 - #define EE_WORD_ADR_SIZE 1 // 1 word addr +#if defined(EE24C1024) +#define EE_PAGE_SIZE 256 // 24C1024 +#define EE_WORD_ADR_SIZE 2 // 2 word addr +#elif defined(EE24C256) +#define EE_PAGE_SIZE 64 // 24C256 +#define EE_WORD_ADR_SIZE 2 // 2 word addr +#elif defined(EE24C02) +#define EE_PAGE_SIZE 8 // 24C02 +#define EE_WORD_ADR_SIZE 1 // 1 word addr #endif /* device information */ -#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F334) - #define HW_I2C_DEV "i2c1" - #define SW_I2C_DEV "i2c1_sw" +#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || \ + defined(HC32F4A8) || defined(HC32F334) || defined(HC32F467) +#define HW_I2C_DEV "i2c1" +#define SW_I2C_DEV "i2c1_sw" #elif defined(HC32F460) - #define HW_I2C_DEV "i2c3" - #define SW_I2C_DEV "i2c1_sw" +#define HW_I2C_DEV "i2c3" +#define SW_I2C_DEV "i2c1_sw" #endif /* this API is for eeprom size is smaller than 256Bytes */ static void eeprom_page_write(uint32_t page, uint8_t *pBuf) { struct rt_i2c_bus_device *hc32_i2c = RT_NULL; - uint8_t TxBuf[EE_PAGE_SIZE + EE_WORD_ADR_SIZE] = {0}; + uint8_t TxBuf[EE_PAGE_SIZE + EE_WORD_ADR_SIZE] = { 0 }; struct rt_i2c_msg msg[1]; -#if defined (BSP_USING_I2C_HW) +#if defined(BSP_USING_I2C_HW) hc32_i2c = rt_i2c_bus_device_find(HW_I2C_DEV); //hw i2c #else hc32_i2c = rt_i2c_bus_device_find(SW_I2C_DEV); //sw i2c @@ -90,10 +93,10 @@ static void eeprom_page_write(uint32_t page, uint8_t *pBuf) { TxBuf[i + EE_WORD_ADR_SIZE] = *pBuf++; } - msg[0].addr = EE_DEV_ADDR; + msg[0].addr = EE_DEV_ADDR; msg[0].flags = RT_I2C_WR; - msg[0].len = EE_PAGE_SIZE + EE_WORD_ADR_SIZE; - msg[0].buf = TxBuf; + msg[0].len = EE_PAGE_SIZE + EE_WORD_ADR_SIZE; + msg[0].buf = TxBuf; #if defined(USING_RT_I2C_TRANSFER) rt_i2c_transfer(hc32_i2c, &msg[0], 1); @@ -113,32 +116,29 @@ static void eeprom_page_read(uint32_t page, uint8_t *pBuf) struct rt_i2c_msg msg[2]; #endif -#if defined (BSP_USING_I2C_HW) +#if defined(BSP_USING_I2C_HW) hc32_i2c = rt_i2c_bus_device_find(HW_I2C_DEV); //hw i2c #else hc32_i2c = rt_i2c_bus_device_find(SW_I2C_DEV); //sw i2c #endif - if (EE_WORD_ADR_SIZE == 2) - { - readAddr[0] = (page * EE_PAGE_SIZE) / 256; // addrH - readAddr[1] = page * EE_PAGE_SIZE; // addrL - } - else - { - readAddr[0] = page * EE_PAGE_SIZE; - } +#if (EE_WORD_ADR_SIZE == 2) + readAddr[0] = (page * EE_PAGE_SIZE) / 256; // addrH + readAddr[1] = page * EE_PAGE_SIZE; // addrL +#else + readAddr[0] = page * EE_PAGE_SIZE; +#endif #if defined(USING_RT_I2C_TRANSFER) - msg[0].addr = EE_DEV_ADDR; + msg[0].addr = EE_DEV_ADDR; msg[0].flags = RT_I2C_WR; - msg[0].len = EE_WORD_ADR_SIZE; - msg[0].buf = readAddr; + msg[0].len = EE_WORD_ADR_SIZE; + msg[0].buf = readAddr; - msg[1].addr = EE_DEV_ADDR; + msg[1].addr = EE_DEV_ADDR; msg[1].flags = RT_I2C_RD; - msg[1].len = EE_PAGE_SIZE; - msg[1].buf = pBuf; + msg[1].len = EE_PAGE_SIZE; + msg[1].buf = pBuf; rt_i2c_transfer(hc32_i2c, &msg[0], 2); #else rt_i2c_master_send(hc32_i2c, EE_DEV_ADDR, RT_I2C_NO_STOP, readAddr, EE_WORD_ADR_SIZE); @@ -191,19 +191,20 @@ void eeprom_test(void) } /* TCA9539 device */ -#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || \ + defined(HC32F4A8) || defined(HC32F467) /* TCA9539 define */ -#define TCA9539_DEV_ADDR (0x74) // TCA9539 chip address on I2C bus +#define TCA9539_DEV_ADDR (0x74) // TCA9539 chip address on I2C bus -#define TCA9539_REG_INPUT_PORT0 (0x00U) -#define TCA9539_REG_INPUT_PORT1 (0x01U) -#define TCA9539_REG_OUTPUT_PORT0 (0x02U) -#define TCA9539_REG_OUTPUT_PORT1 (0x03U) -#define TCA9539_REG_INVERT_PORT0 (0x04U) -#define TCA9539_REG_INVERT_PORT1 (0x05U) -#define TCA9539_REG_CONFIG_PORT0 (0x06U) -#define TCA9539_REG_CONFIG_PORT1 (0x07U) +#define TCA9539_REG_INPUT_PORT0 (0x00U) +#define TCA9539_REG_INPUT_PORT1 (0x01U) +#define TCA9539_REG_OUTPUT_PORT0 (0x02U) +#define TCA9539_REG_OUTPUT_PORT1 (0x03U) +#define TCA9539_REG_INVERT_PORT0 (0x04U) +#define TCA9539_REG_INVERT_PORT1 (0x05U) +#define TCA9539_REG_CONFIG_PORT0 (0x06U) +#define TCA9539_REG_CONFIG_PORT1 (0x07U) void tca9539_test(void) { @@ -212,7 +213,7 @@ void tca9539_test(void) static rt_uint8_t send_buf1[0x10], recv_buf1[0x10]; struct rt_i2c_msg msg[2]; -#if defined (BSP_USING_I2C_HW) +#if defined(BSP_USING_I2C_HW) hc32_i2c = rt_i2c_bus_device_find(HW_I2C_DEV); //hw i2c #else hc32_i2c = rt_i2c_bus_device_find(SW_I2C_DEV); //sw i2c @@ -221,31 +222,31 @@ void tca9539_test(void) send_buf0[0] = TCA9539_REG_CONFIG_PORT1; send_buf0[1] = 0xFF; - msg[0].addr = TCA9539_DEV_ADDR; + msg[0].addr = TCA9539_DEV_ADDR; msg[0].flags = RT_I2C_WR; - msg[0].len = 2; - msg[0].buf = send_buf0; + msg[0].len = 2; + msg[0].buf = send_buf0; rt_i2c_transfer(hc32_i2c, &msg[0], 1); send_buf0[0] = TCA9539_REG_OUTPUT_PORT1; send_buf0[1] = 0xAC; - msg[1].addr = TCA9539_DEV_ADDR; + msg[1].addr = TCA9539_DEV_ADDR; msg[1].flags = RT_I2C_WR; - msg[1].len = 2; - msg[1].buf = send_buf0; + msg[1].len = 2; + msg[1].buf = send_buf0; rt_i2c_transfer(hc32_i2c, &msg[1], 1); /* read */ send_buf1[0] = TCA9539_REG_OUTPUT_PORT1; - msg[0].addr = TCA9539_DEV_ADDR; + msg[0].addr = TCA9539_DEV_ADDR; msg[0].flags = RT_I2C_WR; - msg[0].len = 1; - msg[0].buf = send_buf1; + msg[0].len = 1; + msg[0].buf = send_buf1; - msg[1].addr = TCA9539_DEV_ADDR; + msg[1].addr = TCA9539_DEV_ADDR; msg[1].flags = RT_I2C_RD; - msg[1].len = 1; - msg[1].buf = recv_buf1; + msg[1].len = 1; + msg[1].buf = recv_buf1; rt_i2c_transfer(hc32_i2c, &msg[0], 2); if (recv_buf1[0] == 0xAC) @@ -262,7 +263,8 @@ void tca9539_test(void) static void i2c_sample(int argc, char *argv[]) { eeprom_test(); -#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F472) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F4A8) || \ + defined(HC32F467) tca9539_test(); #endif } diff --git a/bsp/hc32/tests/test_nand.c b/bsp/hc32/tests/test_nand.c index 5958ba93384..9b2790818c4 100644 --- a/bsp/hc32/tests/test_nand.c +++ b/bsp/hc32/tests/test_nand.c @@ -14,7 +14,7 @@ * 程序功能：对整个Nand存储空间进行擦除、写和读操作，比较数据是否一致 * * 注意: - * F4A0: 修改函数SystemClock_Config，调用函数CLK_SetClockDiv参数，CLK_EXCLK_DIV2改为CLK_EXCLK_DIV4; + * F4A0/F4A2: 修改函数SystemClock_Config，调用函数CLK_SetClockDiv参数，CLK_EXCLK_DIV2改为CLK_EXCLK_DIV4; * * menuconfig: * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable EXMC ----> Using SDRAM or NAND ----> Using NAND @@ -28,7 +28,7 @@ #if defined(BSP_USING_EXMC) && defined(BSP_USING_NAND) #include "nand_port.h" -#define NAND_DEVICE_NAME "nand" +#define NAND_DEVICE_NAME "nand" static rt_err_t nand_read_id(struct rt_mtd_nand_device *mtd_nand) { diff --git a/bsp/hc32/tests/test_pm.c b/bsp/hc32/tests/test_pm.c index cb334e2b55d..b76e125e9e2 100644 --- a/bsp/hc32/tests/test_pm.c +++ b/bsp/hc32/tests/test_pm.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-04 CDT Support HC32F467 */ /* @@ -41,106 +43,106 @@ #if defined(BSP_USING_PM) -#if defined (HC32F4A0) || defined (HC32F4A8) - #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) - #define BSP_KEY_PORT (GPIO_PORT_A) - #define BSP_KEY_PIN (GPIO_PIN_00) - #define BSP_KEY_EXTINT (EXTINT_CH00) - #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ0) - #define BSP_KEY_IRQn (INT001_IRQn) - #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH0) - #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ0) - #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP0) - #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP00) - - #define LED_GREEN_PORT (GPIO_PORT_C) - #define LED_GREEN_PIN (GPIO_PIN_09) - - #define MCO_PORT (GPIO_PORT_A) - #define MCO_PIN (GPIO_PIN_08) - #define MCO_GPIO_FUNC (GPIO_FUNC_1) - -#elif defined (HC32F460) - #define PLL_SRC ((CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC) >> CMU_PLLCFGR_PLLSRC_POS) - #define BSP_KEY_PORT (GPIO_PORT_B) /* Key10 */ - #define BSP_KEY_PIN (GPIO_PIN_01) - #define BSP_KEY_EXTINT (EXTINT_CH01) - #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ1) - #define BSP_KEY_IRQn (INT001_IRQn) - #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH1) - #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ1) - #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) - #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP01) - - #define LED_GREEN_PORT (GPIO_PORT_D) - #define LED_GREEN_PIN (GPIO_PIN_04) - - #define MCO_PORT (GPIO_PORT_A) - #define MCO_PIN (GPIO_PIN_08) - #define MCO_GPIO_FUNC (GPIO_FUNC_1) - -#elif defined (HC32F448) - #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) - #define BSP_KEY_PORT (GPIO_PORT_B) /* Key5 */ - #define BSP_KEY_PIN (GPIO_PIN_06) - #define BSP_KEY_EXTINT (EXTINT_CH06) - #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ6) - #define BSP_KEY_IRQn (INT001_IRQn) - #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH6) - #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ6) - #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) - #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP12) - - #define LED_GREEN_PORT (GPIO_PORT_A) - #define LED_GREEN_PIN (GPIO_PIN_02) - - #define MCO_PORT (GPIO_PORT_A) - #define MCO_PIN (GPIO_PIN_08) - #define MCO_GPIO_FUNC (GPIO_FUNC_1) - -#elif defined (HC32F472) - #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) - #define BSP_KEY_PORT (GPIO_PORT_B) /* Key5 */ - #define BSP_KEY_PIN (GPIO_PIN_05) - #define BSP_KEY_EXTINT (EXTINT_CH05) - #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ5) - #define BSP_KEY_IRQn (INT001_IRQn) - #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH5) - #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ5) - #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) - #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP11) - - #define LED_GREEN_PORT (GPIO_PORT_C) - #define LED_GREEN_PIN (GPIO_PIN_09) - -#elif defined (HC32F334) - #define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) - #define BSP_KEY_PORT (GPIO_PORT_B) /* Key5 */ - #define BSP_KEY_PIN (GPIO_PIN_09) - #define BSP_KEY_EXTINT (EXTINT_CH09) - #define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ9) - #define BSP_KEY_IRQn (INT001_IRQn) - #define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH9) - #define BSP_KEY_EVT (EVT_SRC_PORT_EIRQ9) - #define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP2) - #define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP21) - - #define LED_GREEN_PORT (GPIO_PORT_C) - #define LED_GREEN_PIN (GPIO_PIN_13) +#if defined(HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) +#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) +#define BSP_KEY_PORT (GPIO_PORT_A) +#define BSP_KEY_PIN (GPIO_PIN_00) +#define BSP_KEY_EXTINT (EXTINT_CH00) +#define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ0) +#define BSP_KEY_IRQn (INT001_IRQn) +#define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH0) +#define BSP_KEY_EVT (INTC_EVT1) +#define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP0) +#define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP00) + +#define LED_GREEN_PORT (GPIO_PORT_C) +#define LED_GREEN_PIN (GPIO_PIN_09) + +#define MCO_PORT (GPIO_PORT_A) +#define MCO_PIN (GPIO_PIN_08) +#define MCO_GPIO_FUNC (GPIO_FUNC_1) + +#elif defined(HC32F460) +#define PLL_SRC ((CM_CMU->PLLCFGR & CMU_PLLCFGR_PLLSRC) >> CMU_PLLCFGR_PLLSRC_POS) +#define BSP_KEY_PORT (GPIO_PORT_B) /* Key10 */ +#define BSP_KEY_PIN (GPIO_PIN_01) +#define BSP_KEY_EXTINT (EXTINT_CH01) +#define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ1) +#define BSP_KEY_IRQn (INT001_IRQn) +#define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH1) +#define BSP_KEY_EVT (INTC_EVT1) +#define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) +#define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP01) + +#define LED_GREEN_PORT (GPIO_PORT_D) +#define LED_GREEN_PIN (GPIO_PIN_04) + +#define MCO_PORT (GPIO_PORT_A) +#define MCO_PIN (GPIO_PIN_08) +#define MCO_GPIO_FUNC (GPIO_FUNC_1) + +#elif defined(HC32F448) +#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) +#define BSP_KEY_PORT (GPIO_PORT_B) /* Key5 */ +#define BSP_KEY_PIN (GPIO_PIN_06) +#define BSP_KEY_EXTINT (EXTINT_CH06) +#define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ6) +#define BSP_KEY_IRQn (INT001_IRQn) +#define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH6) +#define BSP_KEY_EVT (INTC_EVT1) +#define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) +#define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP12) + +#define LED_GREEN_PORT (GPIO_PORT_A) +#define LED_GREEN_PIN (GPIO_PIN_02) + +#define MCO_PORT (GPIO_PORT_A) +#define MCO_PIN (GPIO_PIN_08) +#define MCO_GPIO_FUNC (GPIO_FUNC_1) + +#elif defined(HC32F472) +#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) +#define BSP_KEY_PORT (GPIO_PORT_B) /* Key5 */ +#define BSP_KEY_PIN (GPIO_PIN_05) +#define BSP_KEY_EXTINT (EXTINT_CH05) +#define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ5) +#define BSP_KEY_IRQn (INT001_IRQn) +#define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH5) +#define BSP_KEY_EVT (INTC_EVT1) +#define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP1) +#define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP11) + +#define LED_GREEN_PORT (GPIO_PORT_C) +#define LED_GREEN_PIN (GPIO_PIN_09) + +#elif defined(HC32F334) +#define PLL_SRC ((CM_CMU->PLLHCFGR & CMU_PLLHCFGR_PLLSRC) >> CMU_PLLHCFGR_PLLSRC_POS) +#define BSP_KEY_PORT (GPIO_PORT_B) /* Key5 */ +#define BSP_KEY_PIN (GPIO_PIN_09) +#define BSP_KEY_EXTINT (EXTINT_CH09) +#define BSP_KEY_INT_SRC (INT_SRC_PORT_EIRQ9) +#define BSP_KEY_IRQn (INT001_IRQn) +#define BSP_KEY_INTC_STOP_WKUP_EXTINT (INTC_STOP_WKUP_EXTINT_CH9) +#define BSP_KEY_EVT (INTC_EVT1) +#define BSP_KEY_PWC_PD_WKUP_TRIG_WKUP (PWC_PD_WKUP_TRIG_WKUP2) +#define BSP_KEY_PWC_PD_WKUP_WKUP (PWC_PD_WKUP_WKUP21) + +#define LED_GREEN_PORT (GPIO_PORT_C) +#define LED_GREEN_PIN (GPIO_PIN_13) #endif -#define KEYCNT_BACKUP_ADDR (uint32_t *)(0x200F0010) -#define KEYCNT_CMD_SLEEP_NONE (0) -#define KEYCNT_CMD_SLEEP_IDLE (1) -#define KEYCNT_CMD_SLEEP_DEEP (3) -#define KEYCNT_CMD_SLEEP_STANDBY (5) -#define KEYCNT_CMD_SLEEP_SHUTDOWN (7) +#define KEYCNT_BACKUP_ADDR (uint32_t *)(0x200F0010) +#define KEYCNT_CMD_SLEEP_NONE (0) +#define KEYCNT_CMD_SLEEP_IDLE (1) +#define KEYCNT_CMD_SLEEP_DEEP (3) +#define KEYCNT_CMD_SLEEP_STANDBY (5) +#define KEYCNT_CMD_SLEEP_SHUTDOWN (7) #define PM_DBG #if defined PM_DBG - #define pm_dbg rt_kprintf +#define pm_dbg rt_kprintf #else - #define pm_dbg +#define pm_dbg #endif static volatile uint32_t g_keycnt_cmd; @@ -188,7 +190,7 @@ static void _key_int_init(void) /* IRQ sign-in */ stcIrqSignConfig.enIntSrc = BSP_KEY_INT_SRC; - stcIrqSignConfig.enIRQn = BSP_KEY_IRQn; + stcIrqSignConfig.enIRQn = BSP_KEY_IRQn; stcIrqSignConfig.pfnCallback = KEY_IrqHandler; (void)INTC_IrqSignIn(&stcIrqSignConfig); @@ -198,10 +200,10 @@ static void _key_int_init(void) NVIC_EnableIRQ(stcIrqSignConfig.enIRQn); } - static void _wkup_cfg_sleep_deep() { INTC_WakeupSrcCmd(BSP_KEY_INTC_STOP_WKUP_EXTINT, ENABLE); + INTC_EventCmd(BSP_KEY_EVT, ENABLE); } static void _wkup_cfg_sleep_standby(void) @@ -232,7 +234,7 @@ static void _sleep_enter_event_deep(void) static void _sleep_enter_event_standby(void) { _wkup_cfg_sleep_standby(); -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) PWC_BKR_Write(0, g_keycnt_cmd & 0xFF); #endif *KEYCNT_BACKUP_ADDR = g_keycnt_cmd; @@ -257,7 +259,7 @@ static void _sleep_exit_event_idle(void) static void _sleep_exit_event_deep(void) { -#if defined (HC32F460) +#if defined(HC32F460) PWC_STOP_ClockRecover(); #endif rt_pm_release(PM_SLEEP_MODE_DEEP); @@ -266,8 +268,7 @@ static void _sleep_exit_event_deep(void) } typedef void (*notify)(void); -static notify sleep_enter_func[PM_SLEEP_MODE_MAX] = -{ +static notify sleep_enter_func[PM_SLEEP_MODE_MAX] = { RT_NULL, _sleep_enter_event_idle, RT_NULL, @@ -276,8 +277,7 @@ static notify sleep_enter_func[PM_SLEEP_MODE_MAX] = _sleep_enter_event_shutdown, }; -static notify sleep_exit_func[PM_SLEEP_MODE_MAX] = -{ +static notify sleep_exit_func[PM_SLEEP_MODE_MAX] = { RT_NULL, _sleep_exit_event_idle, RT_NULL, @@ -286,16 +286,18 @@ static notify sleep_exit_func[PM_SLEEP_MODE_MAX] = RT_NULL, }; -static void _notify_func(uint8_t event, uint8_t mode, void *data) +static void _notify_func(uint8_t event, uint8_t mode, void *data) { if (event == RT_PM_ENTER_SLEEP) { - SysTick_Suspend(); if (sleep_enter_func[mode] == RT_NULL) { return; } - GPIO_ResetPins(LED_GREEN_PORT, LED_GREEN_PIN); + /* shutdown LED before enter sleep mode to decrease power consumption */ + rt_pin_write(LED_GREEN_PIN, PIN_LOW); + + SysTick_Suspend(); sleep_enter_func[mode](); } else @@ -319,8 +321,8 @@ static void pm_cmd_handler(void *parameter) while (1) { - if ((KEYCNT_CMD_SLEEP_IDLE == g_keycnt_cmd) || (KEYCNT_CMD_SLEEP_DEEP == g_keycnt_cmd) || \ - (KEYCNT_CMD_SLEEP_STANDBY == g_keycnt_cmd) || (KEYCNT_CMD_SLEEP_SHUTDOWN == g_keycnt_cmd)) + if ((KEYCNT_CMD_SLEEP_IDLE == g_keycnt_cmd) || (KEYCNT_CMD_SLEEP_DEEP == g_keycnt_cmd) || + (KEYCNT_CMD_SLEEP_STANDBY == g_keycnt_cmd) || (KEYCNT_CMD_SLEEP_SHUTDOWN == g_keycnt_cmd)) { switch (g_keycnt_cmd) { @@ -350,12 +352,12 @@ static void pm_cmd_handler(void *parameter) } } -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) static void pm_run_main(void *parameter) { static rt_uint8_t run_index = 0; - char *speed[] = {"low", "high"}; - const rt_uint8_t run_mode[] = {PM_RUN_MODE_LOW_SPEED, PM_RUN_MODE_HIGH_SPEED}; + char *speed[] = { "low", "high" }; + const rt_uint8_t run_mode[] = { PM_RUN_MODE_LOW_SPEED, PM_RUN_MODE_HIGH_SPEED }; GPIO_SetFunc(MCO_PORT, MCO_PIN, MCO_GPIO_FUNC); /* Configure clock output system clock */ @@ -383,7 +385,7 @@ static void pm_run_main(void *parameter) static void _keycnt_cmd_init_after_power_on(void) { en_flag_status_t wkup_from_ptwk = PWC_PD_GetWakeupStatus(PWC_PD_WKUP_FLAG_WKUP0); -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) en_flag_status_t bakram_pd = PWC_BKR_GetStatus(PWC_BACKUP_RAM_FLAG_RAMPDF); uint8_t bkr0 = PWC_BKR_Read(0); @@ -421,7 +423,7 @@ static void _keycnt_cmd_init_after_power_on(void) pm_dbg("KEYCNT_BACKUP_ADDR addr =0x%p,value = %d\n", KEYCNT_BACKUP_ADDR, *KEYCNT_BACKUP_ADDR); pm_dbg("wkup_from_ptwk = %d\n", wkup_from_ptwk); -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) pm_dbg("bakram_pd = %d\n", bakram_pd); pm_dbg("bkr0 = %d\n", bkr0); #endif @@ -429,17 +431,17 @@ static void _keycnt_cmd_init_after_power_on(void) static void _vbat_init(void) { -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) while (PWC_BKR_GetStatus(PWC_BACKUP_RAM_FLAG_RAMVALID) == RESET) { rt_thread_delay(10); } FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMB, ENABLE); -#elif defined (HC32F448) || defined (HC32F334) +#elif defined(HC32F448) || defined(HC32F334) FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMB, ENABLE); -#elif defined (HC32F460) +#elif defined(HC32F460) FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMRET, ENABLE); -#elif defined (HC32F472) +#elif defined(HC32F472) FCG_Fcg0PeriphClockCmd(FCG0_PERIPH_SRAMRET, ENABLE); #endif pm_dbg("vbat init success\n"); @@ -455,7 +457,7 @@ int pm_sample_init(void) rt_pm_notify_set(_notify_func, NULL); - rt_thread_t thread = rt_thread_create("pm_cmd_handler", pm_cmd_handler, RT_NULL, 1024, 25, 10); + rt_thread_t thread = rt_thread_create("pm_cmd_handler", pm_cmd_handler, RT_NULL, 1024, 25, 10); if (thread != RT_NULL) { rt_thread_startup(thread); @@ -465,7 +467,7 @@ int pm_sample_init(void) rt_kprintf("create pm sample thread failed!\n"); } -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) +#if defined(HC32F467) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) thread = rt_thread_create("pm_run_main", pm_run_main, RT_NULL, 1024, 25, 10); if (thread != RT_NULL) { diff --git a/bsp/hc32/tests/test_pulse_encoder.c b/bsp/hc32/tests/test_pulse_encoder.c index 641e45d00f0..16197f6847b 100644 --- a/bsp/hc32/tests/test_pulse_encoder.c +++ b/bsp/hc32/tests/test_pulse_encoder.c @@ -6,11 +6,16 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-09 CDT Support HC32F467 */ /* - * 程序清单： Pulse encoder 设备使用例程, 请在图形化配置界面打开pulse encoder device， - * 并使能tmra_1和tmr6_1. + * 程序清单： Pulse encoder 设备使用例程 + * + * menuconfig: + * Hardware Drivers Config ---> On-Chip Peripheral Drivers ----> [*] Enable Pulse Encoder ----> [*] Use TIMERA As The Pulse Encoder ---> [*] Use TIMERA_1 As The Pulse Encoder + * [*] Use TIMER6 As The Pulse Encoder ---> [*] Use TIMER6_1 As The Pulse Encoder * 例程导出了 encoder_sample 命令到控制终端, 通过串口可查看当前的count数值 * 命令调用格式：pulse_encoder_sample devname [option1] [option2] * devname: [pulse_a1/pulse_61] 编码器单元名称 @@ -19,7 +24,6 @@ * eg:encoder_sample pulse_a1 2000 1000 * 编码器的分辨率是1000 * 硬件IO查看对应board/board_config.h中相关端口定义，并且需要正确连接到对应模拟脉冲生成的端口 - * 程序功能： */ #include @@ -30,19 +34,19 @@ #ifdef BSP_USING_PULSE_ENCODER -#if defined (HC32F4A0) || defined (HC32F4A8) - #define TEST_IO_A_PIN GET_PIN(A, 5) - #define TEST_IO_B_PIN GET_PIN(A, 6) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) +#define TEST_IO_A_PIN GET_PIN(A, 5) +#define TEST_IO_B_PIN GET_PIN(A, 6) #else - #define TEST_IO_A_PIN GET_PIN(B, 0) - #define TEST_IO_B_PIN GET_PIN(B, 1) +#define TEST_IO_A_PIN GET_PIN(B, 0) +#define TEST_IO_B_PIN GET_PIN(B, 1) #endif static rt_device_t pulse_encoder_dev = RT_NULL; static void printf_connect(void) { -#if defined (HC32F4A0) || defined (HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) rt_kprintf(" [tmra]*connect PA5-->PA8 PA6-->PA9\n"); #endif @@ -50,7 +54,7 @@ static void printf_connect(void) rt_kprintf(" [tmr6]*connect PA5-->PB9 PA6-->PB8\n"); #endif #endif -#if defined (HC32F460) +#if defined(HC32F460) #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) rt_kprintf(" [tmra]*connect PB0-->PA8 PB1-->PA9\n"); #endif @@ -58,7 +62,7 @@ static void printf_connect(void) rt_kprintf(" [tmr6]*connect PB0-->PE9 PB1-->PE8\n"); #endif #endif -#if defined (HC32F448) +#if defined(HC32F448) #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) rt_kprintf(" [tmra]*connect PB0-->PA8 PB1-->PA9\n"); #endif @@ -66,7 +70,7 @@ static void printf_connect(void) rt_kprintf(" [tmr6]*connect PB0-->PB5 PB1-->PB13\n"); #endif #endif -#if defined (HC32F472) +#if defined(HC32F472) #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) rt_kprintf(" [tmra]*connect PB0-->PA0 PB1-->PA1\n"); #endif @@ -74,7 +78,7 @@ static void printf_connect(void) rt_kprintf(" [tmr6]*connect PB0-->PA3 PB1-->PA7\n"); #endif #endif -#if defined (HC32F334) +#if defined(HC32F334) #if defined(BSP_USING_PULSE_ENCODER_TMRA_1) rt_kprintf(" [tmra]*connect PB0-->PA0 PB1-->PA1\n"); #endif @@ -98,8 +102,8 @@ static void GenClkUp(const uint16_t cnt) { uint32_t i, j; rt_int32_t count; - const uint8_t bAin[4U] = {1U, 1U, 0U, 0U}; - const uint8_t bBin[4U] = {0U, 1U, 1U, 0U}; + const uint8_t bAin[4U] = { 1U, 1U, 0U, 0U }; + const uint8_t bBin[4U] = { 0U, 1U, 1U, 0U }; for (j = 0UL; j < cnt; j++) { for (i = 0UL; i < 4UL; i++) @@ -131,8 +135,8 @@ static void GenClkDown(const uint16_t cnt) { uint32_t i, j; rt_int32_t count; - const uint8_t bAin[4U] = {0U, 1U, 1U, 0U}; - const uint8_t bBin[4U] = {1U, 1U, 0U, 0U}; + const uint8_t bAin[4U] = { 0U, 1U, 1U, 0U }; + const uint8_t bBin[4U] = { 1U, 1U, 0U, 0U }; for (j = 0UL; j < cnt; j++) { for (i = 0UL; i < 4UL; i++) @@ -222,5 +226,5 @@ static int encoder_sample(int argc, char **argv) } /* 导出到 msh 命令列表中 */ -MSH_CMD_EXPORT(encoder_sample, encoder sample devname [option1] [option2]); +MSH_CMD_EXPORT(encoder_sample, encoder sample devname[option1][option2]); #endif diff --git a/bsp/hc32/tests/test_pwm.c b/bsp/hc32/tests/test_pwm.c index d675dd89737..3004338b6ca 100644 --- a/bsp/hc32/tests/test_pwm.c +++ b/bsp/hc32/tests/test_pwm.c @@ -21,7 +21,7 @@ #ifdef BSP_USING_PWM -#define PWM_DEV_CHANNEL 1 +#define PWM_DEV_CHANNEL 1 struct rt_device_pwm *pwm_dev; @@ -61,7 +61,7 @@ static rt_int32_t pwm_sample(int argc, char *argv[]) } } } -MSH_CMD_EXPORT(pwm_sample, pwm_sample [opt]) +MSH_CMD_EXPORT(pwm_sample, pwm_sample[opt]) #endif /* EOF diff --git a/bsp/hc32/tests/test_qspi.c b/bsp/hc32/tests/test_qspi.c index 66bd0106d77..24b50b70e86 100644 --- a/bsp/hc32/tests/test_qspi.c +++ b/bsp/hc32/tests/test_qspi.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-10 CDT Support HC32F467 */ /* @@ -24,73 +26,73 @@ #if defined(BSP_USING_QSPI) #include "drv_qspi.h" -#define W25Q_QSPI_DEVICE_NAME "qspi10" - -#define W25Q_FLAG_BUSY (0x01) -#define W25Q_WR_ENABLE (0x06) -#define W25Q_SECTOR_ERASE (0x20) -#define W25Q_RD_STATUS_REG1 (0x05) -#define W25Q_PAGE_PROGRAM (0x02) -#define W25Q64_QUAD_INPUT_PAGE_PROGRAM (0x32) - -#define W25Q_STD_RD (0x03) -#define W25Q_FAST_RD (0x0B) -#define W25Q_FAST_RD_DUAL_OUTPUT (0x3B) -#define W25Q_FAST_RD_DUAL_IO (0xBB) -#define W25Q_FAST_RD_QUAD_OUTPUT (0x6B) -#define W25Q_FAST_RD_QUAD_IO (0xEB) - -#define W25Q64_RD_STATUS_REG1 (0x05) -#define W25Q64_WR_STATUS_REG1 (0x01) -#define W25Q64_RD_STATUS_REG2 (0x35) -#define W25Q64_WR_STATUS_REG2 (0x31) -#define W25Q64_RD_STATUS_REG3 (0x15) -#define W25Q64_WR_STATUS_REG3 (0x11) - -#define W25Q_PAGE_SIZE (256UL) -#define W25Q_SECTOR_SIZE (1024UL * 4UL) -#define W25Q_PAGE_PER_SECTOR (W25Q_SECTOR_SIZE / W25Q_PAGE_SIZE) -#define W25Q_MAX_ADDR (0x800000UL) - -#define W25Q_QSPI_DATA_LINE_WIDTH 1 -#define W25Q_QSPI_RD_MD (W25Q_FAST_RD_QUAD_IO) - -#define W25Q_QSPI_WR_RD_ADDR 0x4000 -#define W25Q_QSPI_DATA_BUF_LEN 0x2000 -#define W25Q_QSPI_WR_CMD W25Q64_QUAD_INPUT_PAGE_PROGRAM - -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) - #ifndef BSP_QSPI_USING_SOFT_CS - #if (W25Q_QSPI_WR_CMD == W25Q64_QUAD_INPUT_PAGE_PROGRAM) - #error "QUAD PAGE PROGRAM must use soft CS pin!!" - #endif - #endif +#define W25Q_QSPI_DEVICE_NAME "qspi10" + +#define W25Q_FLAG_BUSY (0x01) +#define W25Q_WR_ENABLE (0x06) +#define W25Q_SECTOR_ERASE (0x20) +#define W25Q_RD_STATUS_REG1 (0x05) +#define W25Q_PAGE_PROGRAM (0x02) +#define W25Q64_QUAD_INPUT_PAGE_PROGRAM (0x32) + +#define W25Q_STD_RD (0x03) +#define W25Q_FAST_RD (0x0B) +#define W25Q_FAST_RD_DUAL_OUTPUT (0x3B) +#define W25Q_FAST_RD_DUAL_IO (0xBB) +#define W25Q_FAST_RD_QUAD_OUTPUT (0x6B) +#define W25Q_FAST_RD_QUAD_IO (0xEB) + +#define W25Q64_RD_STATUS_REG1 (0x05) +#define W25Q64_WR_STATUS_REG1 (0x01) +#define W25Q64_RD_STATUS_REG2 (0x35) +#define W25Q64_WR_STATUS_REG2 (0x31) +#define W25Q64_RD_STATUS_REG3 (0x15) +#define W25Q64_WR_STATUS_REG3 (0x11) + +#define W25Q_PAGE_SIZE (256UL) +#define W25Q_SECTOR_SIZE (1024UL * 4UL) +#define W25Q_PAGE_PER_SECTOR (W25Q_SECTOR_SIZE / W25Q_PAGE_SIZE) +#define W25Q_MAX_ADDR (0x800000UL) + +#define W25Q_QSPI_DATA_LINE_WIDTH 1 +#define W25Q_QSPI_RD_MD (W25Q_FAST_RD_QUAD_IO) + +#define W25Q_QSPI_WR_RD_ADDR 0x4000 +#define W25Q_QSPI_DATA_BUF_LEN 0x2000 +#define W25Q_QSPI_WR_CMD W25Q64_QUAD_INPUT_PAGE_PROGRAM + +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F467) +#ifndef BSP_QSPI_USING_SOFT_CS +#if (W25Q_QSPI_WR_CMD == W25Q64_QUAD_INPUT_PAGE_PROGRAM) +#error "QUAD PAGE PROGRAM must use soft CS pin!!" +#endif +#endif #endif #if W25Q_QSPI_RD_MD == W25Q_STD_RD - #define W25Q_QSPI_RD_DUMMY_CYCLE 0 +#define W25Q_QSPI_RD_DUMMY_CYCLE 0 #elif W25Q_QSPI_RD_MD == W25Q_FAST_RD_DUAL_IO - #define W25Q_QSPI_RD_DUMMY_CYCLE 4 +#define W25Q_QSPI_RD_DUMMY_CYCLE 4 #elif W25Q_QSPI_RD_MD == W25Q_FAST_RD_QUAD_IO - #define W25Q_QSPI_RD_DUMMY_CYCLE 6 +#define W25Q_QSPI_RD_DUMMY_CYCLE 6 #else - #define W25Q_QSPI_RD_DUMMY_CYCLE 8 +#define W25Q_QSPI_RD_DUMMY_CYCLE 8 #endif #if (W25Q_QSPI_RD_MD == W25Q_FAST_RD_QUAD_IO) - #define W25Q_QSPI_ADDR_LINE 4 +#define W25Q_QSPI_ADDR_LINE 4 #elif (W25Q_QSPI_RD_MD == W25Q_FAST_RD_DUAL_IO) - #define W25Q_QSPI_ADDR_LINE 2 +#define W25Q_QSPI_ADDR_LINE 2 #else - #define W25Q_QSPI_ADDR_LINE 1 +#define W25Q_QSPI_ADDR_LINE 1 #endif #if (W25Q_QSPI_RD_MD == W25Q_STD_RD) || (W25Q_QSPI_RD_MD == W25Q_FAST_RD) - #define W25Q_QSPI_DATA_LINE 1 +#define W25Q_QSPI_DATA_LINE 1 #elif (W25Q_QSPI_RD_MD == W25Q_FAST_RD_DUAL_OUTPUT) || (W25Q_QSPI_RD_MD == W25Q_FAST_RD_DUAL_IO) - #define W25Q_QSPI_DATA_LINE 2 +#define W25Q_QSPI_DATA_LINE 2 #else - #define W25Q_QSPI_DATA_LINE 4 +#define W25Q_QSPI_DATA_LINE 4 #endif @@ -105,9 +107,9 @@ static int rt_hw_qspi_flash_init(void) #ifndef BSP_QSPI_USING_SOFT_CS if (RT_EOK != rt_hw_qspi_bus_attach_device("qspi1", "qspi10", RT_NULL, W25Q_QSPI_DATA_LINE_WIDTH, RT_NULL, RT_NULL)) #else -#if defined (HC32F472) +#if defined(HC32F472) if (RT_EOK != rt_hw_qspi_bus_attach_device("qspi1", "qspi10", GET_PIN(B, 12), W25Q_QSPI_DATA_LINE_WIDTH, RT_NULL, RT_NULL)) -#elif defined (HC32F4A0) || defined (HC32F460) || defined (HC32F448) || defined (HC32F4A8) +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F467) if (RT_EOK != rt_hw_qspi_bus_attach_device("qspi1", "qspi10", GET_PIN(C, 7), W25Q_QSPI_DATA_LINE_WIDTH, RT_NULL, RT_NULL)) #endif #endif @@ -125,8 +127,8 @@ INIT_COMPONENT_EXPORT(rt_hw_qspi_flash_init); void w25q_read_uid(struct rt_qspi_device *device) { rt_uint8_t w25x_read_uid = 0x4B; /* 命令 */ - rt_uint8_t u8UID[8] = {0}; - rt_uint8_t txBuf[5] = {0}; + rt_uint8_t u8UID[8] = { 0 }; + rt_uint8_t txBuf[5] = { 0 }; rt_memset(txBuf, 0xFF, 5); txBuf[0] = w25x_read_uid; @@ -147,8 +149,8 @@ int32_t w25q_check_process_done(struct rt_qspi_device *device, uint32_t u32Timeo { __IO uint32_t u32Count = 0U; int32_t i32Ret = LL_ERR_TIMEOUT; - rt_uint8_t rxBuf[5] = {0}; - rt_uint8_t txBuf[5] = {0}; + rt_uint8_t rxBuf[5] = { 0 }; + rt_uint8_t txBuf[5] = { 0 }; txBuf[0] = W25Q_RD_STATUS_REG1; while (u32Count < u32Timeout) @@ -206,7 +208,7 @@ rt_err_t bsp_qspi_send_then_recv(struct rt_qspi_device *device, const void *send else { /* no address stage */ - message.address.content = 0 ; + message.address.content = 0; message.address.qspi_lines = 0; message.address.size = 0; } @@ -247,7 +249,7 @@ rt_err_t bsp_qspi_send(struct rt_qspi_device *device, const void *send_buf, rt_s struct rt_qspi_message message; unsigned char *ptr = (unsigned char *)send_buf; - rt_size_t count = 0; + rt_size_t count = 0; rt_err_t result = 0; message.instruction.content = ptr[0]; @@ -276,16 +278,15 @@ rt_err_t bsp_qspi_send(struct rt_qspi_device *device, const void *send_buf, rt_s else { /* no address stage */ - message.address.content = 0 ; + message.address.content = 0; message.address.qspi_lines = 0; message.address.size = 0; } - } else { /* no address stage */ - message.address.content = 0 ; + message.address.content = 0; message.address.qspi_lines = 0; message.address.size = 0; } @@ -327,10 +328,9 @@ rt_err_t bsp_qspi_send(struct rt_qspi_device *device, const void *send_buf, rt_s } - void w25q_write_sr(struct rt_qspi_device *device, uint8_t reg, uint8_t value) { - rt_uint8_t txBuf[5] = {0}; + rt_uint8_t txBuf[5] = { 0 }; txBuf[0] = W25Q_WR_ENABLE; if (1 != rt_qspi_send(device, txBuf, 1)) @@ -353,7 +353,7 @@ void w25q_write_sr(struct rt_qspi_device *device, uint8_t reg, uint8_t value) int32_t w25q_read_data(struct rt_qspi_device *device, uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32Size) { int32_t i32Ret = LL_OK; - rt_uint8_t txBuf[5] = {0}; + rt_uint8_t txBuf[5] = { 0 }; txBuf[0] = W25Q_QSPI_RD_MD; txBuf[1] = (u32Addr >> 16) & 0xFFU; @@ -419,9 +419,9 @@ int32_t w25q_write_data(struct rt_qspi_device *device, uint32_t u32Addr, uint8_t break; } - u32Addr += u32TempSize; + u32Addr += u32TempSize; u32AddrOffset += u32TempSize; - u32Size -= u32TempSize; + u32Size -= u32TempSize; } return i32Ret; @@ -481,11 +481,11 @@ void w25q_write_read_data(struct rt_qspi_device *device, uint32_t u32Addr) { rt_kprintf("qspi erase sector failed!\n"); } - if (LL_OK != w25q_write_data(device, u32Addr, u8WrBuf, W25Q_QSPI_DATA_BUF_LEN)) + if (LL_OK != w25q_write_data(device, u32Addr, u8WrBuf, W25Q_QSPI_DATA_BUF_LEN)) { rt_kprintf("qspi write data failed!\n"); } - if (LL_OK != w25q_read_data(device, u32Addr, u8RdBuf, W25Q_QSPI_DATA_BUF_LEN)) + if (LL_OK != w25q_read_data(device, u32Addr, u8RdBuf, W25Q_QSPI_DATA_BUF_LEN)) { rt_kprintf("qspi read data failed!\n"); } @@ -502,14 +502,14 @@ void w25q_write_read_data(struct rt_qspi_device *device, uint32_t u32Addr) static void qspi_thread_entry(void *parameter) { rt_err_t ret; - struct rt_qspi_configuration qcfg = {0}; + struct rt_qspi_configuration qcfg = { 0 }; uint32_t u32Addr = W25Q_QSPI_WR_RD_ADDR; - qcfg.medium_size = W25Q_MAX_ADDR; - qcfg.qspi_dl_width = W25Q_QSPI_DATA_LINE_WIDTH; - qcfg.parent.mode = RT_SPI_MODE_0; - qcfg.parent.data_width = 8; - qcfg.parent.max_hz = 10000000UL; + qcfg.medium_size = W25Q_MAX_ADDR; + qcfg.qspi_dl_width = W25Q_QSPI_DATA_LINE_WIDTH; + qcfg.parent.mode = RT_SPI_MODE_0; + qcfg.parent.data_width = 8; + qcfg.parent.max_hz = 10000000UL; ret = rt_qspi_configure(qspi_dev_w25q, &qcfg); if ((RT_EOK != ret) && (-RT_EBUSY != ret)) { diff --git a/bsp/hc32/tests/test_rtc.c b/bsp/hc32/tests/test_rtc.c index 8aa0bde8d87..6b5dc17508b 100644 --- a/bsp/hc32/tests/test_rtc.c +++ b/bsp/hc32/tests/test_rtc.c @@ -11,9 +11,15 @@ /* * 程序清单：这是 RTC 设备使用例程和 Alarm 使用示例。 * 例程导出了 rtc_sample 命令到控制终端。 + * menuconfig: + * 1.Hardware Drivers Config--->On-Chip Peripheral Driver--->Enable RTC---> Select clock source(RTC USING XTAL32) + * 2.RT-Thread Components---> Device Drivers ---> [-*-] Using RTC device drivers ---> [*] Using RTC alarm + * (1024) stack size for alarm thread + * [*] Using local time for the alarm calculation * 命令调用格式：rtc_sample x * 命令解释：命令第二个参数是要使用的功能对应的编号， * RTC 基本功能对应的编号为 0~3，Alarm 功能对应的编号为 4~9 + * NOTE: 注意时间和日期格式，请严格按照提示位数输入！ */ #include @@ -26,24 +32,23 @@ #if defined(BSP_USING_RTC) /* macros define */ -#define SAMPLE_RTC_NAME "rtc" +#define SAMPLE_RTC_NAME "rtc" /* variables define */ static rt_device_t rtc_dev; #if defined(RT_USING_ALARM) - extern void rt_alarm_dump(void); +extern void rt_alarm_dump(void); - static rt_uint16_t callback_counter, alarm_idx = 0; - static struct rt_alarm *ptr_alarm = RT_NULL; - static struct rt_alarm_setup alarm_setup; +static struct rt_alarm *ptr_alarm = RT_NULL; +static struct rt_alarm_setup alarm_setup; #endif /* RT_USING_ALARM */ /* command type */ enum RTC_CMD { - CMD_OPEN_RTC = 0x00, - CMD_SET_TIME = 0x01, - CMD_SET_DATE = 0x02, + CMD_OPEN_RTC = 0x00, + CMD_SET_TIME = 0x01, + CMD_SET_DATE = 0x02, CMD_GET_DATE_TIME, #if defined(RT_USING_ALARM) CMD_SET_ALARM, @@ -56,18 +61,7 @@ enum RTC_CMD void alarm_callback_fun(rt_alarm_t alarm, time_t timestamp) { - rt_kprintf("\nuser alarm %d callback function.\n", alarm_idx); - if ((0 == (--callback_counter)) && (alarm_idx)) - { - rt_kprintf("stop alarm %d \n", alarm_idx); - if (RT_EOK != rt_alarm_stop(alarm)) - { - rt_kprintf("failed to stop alarm\n"); - } - /* enter callback 2 times */ - callback_counter = 2; - --alarm_idx; - } + rt_kprintf("User alarm callback function.\nNow time is: %s", ctime(×tamp)); } #else }; @@ -85,18 +79,20 @@ static int rtc_sample(int argc, char *argv[]) if (argc < 2) { rt_kprintf("unkown rtc command, rtc [usage] as the following: \n"); - rt_kprintf("\'0\': find and open rtc \n"); - rt_kprintf("\'1 xx:xx:xx\': set time with \n"); - rt_kprintf("\'2 xxxx-xx-xx\': set date with \n"); - rt_kprintf("\'3\': get time and date \n"); + rt_kprintf("\'rtc_sample 0\': find and open rtc \n"); + rt_kprintf("\'rtc_sample 1 HH:MM:SS\': set time with \n"); + rt_kprintf("\'rtc_sample 2 yyyy-mm-dd\': set date with \n"); + rt_kprintf("\'rtc_sample 3\': get time and date \n"); #if defined(RT_USING_ALARM) - rt_kprintf("\'4\': set current time + 10s as alarm \n"); - rt_kprintf("\'5\': start alarm \n"); - rt_kprintf("\'6\': stop alarm \n"); + rt_kprintf("\'rtc_sample 4\': set current time + 1 Min as alarm \n"); + rt_kprintf("\'rtc_sample 5\': start alarm \n"); + rt_kprintf("\'rtc_sample 6\': stop alarm \n"); rt_kprintf("cmd-7 based on cmd-4\n"); - rt_kprintf("\'7\' o: oneshot,\n\'7\' s: second,\n\'7\' m: minute \n"); - rt_kprintf("\'8\': dump all alarm \n"); - rt_kprintf("\'9\': delete all alarm \n"); + rt_kprintf("\'rtc_sample 7 o\': oneshot \n"); + rt_kprintf("\'rtc_sample 7 s\': second \n"); + rt_kprintf("\'rtc_sample 7 m\': minute \n"); + rt_kprintf("\'rtc_sample 8\': dump all alarm \n"); + rt_kprintf("\'rtc_sample 9\': delete all alarm \n"); #endif /* RT_USING_ALARM */ return -RT_ERROR; } @@ -120,17 +116,17 @@ static int rtc_sample(int argc, char *argv[]) rt_kprintf("rtc opened\n"); break; case CMD_SET_TIME: - /* set time with xx:xx:xx format characters */ + /* set time with hh:mm:ss format characters */ if (argc < 3) { rt_kprintf("unsurpported command\n"); return -RT_ERROR; } - temp1 = ((argv[2][0] - '0') * 10) + \ + temp1 = ((argv[2][0] - '0') * 10) + (argv[2][1] - '0'); - temp2 = ((argv[2][3] - '0') * 10) + \ + temp2 = ((argv[2][3] - '0') * 10) + (argv[2][4] - '0'); - temp3 = ((argv[2][6] - '0') * 10) + \ + temp3 = ((argv[2][6] - '0') * 10) + (argv[2][7] - '0'); if (RT_EOK != set_time(temp1, temp2, temp3)) { @@ -140,21 +136,21 @@ static int rtc_sample(int argc, char *argv[]) rt_kprintf("\nset RTC time as %2d:%2d:%2d\n", temp1, temp2, temp3); break; case CMD_SET_DATE: - /* set data xxxx-xx-xx format characters */ - temp1 = ((argv[2][0] - '0') * 1000) + \ - ((argv[2][1] - '0') * 100) + \ - ((argv[2][2] - '0') * 10) + \ + /* set data yyyy-mm-dd format characters */ + temp1 = ((argv[2][0] - '0') * 1000) + + ((argv[2][1] - '0') * 100) + + ((argv[2][2] - '0') * 10) + (argv[2][3] - '0'); - temp2 = ((argv[2][5] - '0') * 10) + \ + temp2 = ((argv[2][5] - '0') * 10) + (argv[2][6] - '0'); - temp3 = ((argv[2][8] - '0') * 10) + \ + temp3 = ((argv[2][8] - '0') * 10) + (argv[2][9] - '0'); if (RT_EOK != set_date(temp1, temp2, temp3)) { rt_kprintf("failed to set date for %s\n", SAMPLE_RTC_NAME); return -RT_ERROR; } - rt_kprintf("\nset RTC date as %4d-%2d-%2d\n", temp1, temp2, temp3); + rt_kprintf("\nset RTC date as %4d-%02d-%02d\n", temp1, temp2, temp3); break; case CMD_GET_DATE_TIME: /* get current time and print it */ @@ -166,9 +162,12 @@ static int rtc_sample(int argc, char *argv[]) /* get current time (uint: second) from 1970-01-01 */ now = time(NULL); rt_kprintf("GMT time is: \n%s\n", ctime(&now)); - now += 60; + /* converts the local time into the calendar time. */ +#ifdef RT_ALARM_USING_LOCAL_TIME + localtime_r(&now, &p_tm); +#else gmtime_r(&now, &p_tm); - // localtime_r(&now, &p_tm); +#endif alarm_setup.flag = RT_ALARM_MINUTE; alarm_setup.wktime.tm_year = p_tm.tm_year; alarm_setup.wktime.tm_mon = p_tm.tm_mon; @@ -177,23 +176,31 @@ static int rtc_sample(int argc, char *argv[]) alarm_setup.wktime.tm_wday = p_tm.tm_wday; alarm_setup.wktime.tm_hour = p_tm.tm_hour; alarm_setup.wktime.tm_min = p_tm.tm_min; - alarm_setup.wktime.tm_sec = p_tm.tm_sec; + alarm_setup.wktime.tm_sec = 0; //p_tm.tm_sec; alarm_setup.wktime.tm_isdst = -1; + alarm_setup.wktime.tm_min += 1; + if (alarm_setup.wktime.tm_min > 59) + { + alarm_setup.wktime.tm_min = 0; + alarm_setup.wktime.tm_hour += 1; + if (alarm_setup.wktime.tm_hour > 23) + { + alarm_setup.wktime.tm_hour = 0; + } + } rt_kprintf("UTC alarm Time: \n%d-%02d-%02d %02d:%02d:%02d\n\n", - p_tm.tm_year + 1900, - p_tm.tm_mon + 1, - p_tm.tm_mday, - p_tm.tm_hour, - p_tm.tm_min, - p_tm.tm_sec); + alarm_setup.wktime.tm_year + 1900, + alarm_setup.wktime.tm_mon + 1, + alarm_setup.wktime.tm_mday, + alarm_setup.wktime.tm_hour, + alarm_setup.wktime.tm_min, + alarm_setup.wktime.tm_sec); ptr_alarm = rt_alarm_create(alarm_callback_fun, &alarm_setup); if (RT_NULL == ptr_alarm) { rt_kprintf("failed to create rtc alarm\n"); return -RT_ERROR; } - callback_counter = 2; - ++alarm_idx; rt_alarm_dump(); break; case CMD_SET_START_ALARM: @@ -245,7 +252,6 @@ static int rtc_sample(int argc, char *argv[]) { rt_kprintf("failed to delete alarm\n"); } - alarm_idx = 0; rt_kprintf("alarm deleted\n"); break; #endif /* RT_USING_ALARM */ diff --git a/bsp/hc32/tests/test_sdmmc.c b/bsp/hc32/tests/test_sdmmc.c index 9cebb78e161..cf461d1b712 100644 --- a/bsp/hc32/tests/test_sdmmc.c +++ b/bsp/hc32/tests/test_sdmmc.c @@ -18,6 +18,11 @@ * stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL; * 改为 * stcPLLHInit.PLLCFGR_f.PLLN = 100UL - 1UL; + * + * menuconfig: + * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable SDIO ----> Enable SDIOx（x：测试板硬件决定） + * + * RT-Thread Components ---> Device Drivers ---> Using SD/MMC device drivers ---> (1024) The stack size for mmcsd thread */ #include @@ -27,14 +32,14 @@ #if defined(BSP_USING_SDIO) -#define SDMMC_DEVICE_NAME "sd" -#define SDMMC_SECTOR_SIZE 512UL +#define SDMMC_DEVICE_NAME "sd" +#define SDMMC_SECTOR_SIZE 512UL -#define SDMMC_TEST_SECTORS_PER_TIME 100UL -#define SDMMC_TEST_TIME 10UL +#define SDMMC_TEST_SECTORS_PER_TIME 100UL +#define SDMMC_TEST_TIME 10UL -#define SDMMC_TEST_SECTORS (SDMMC_TEST_TIME * SDMMC_TEST_SECTORS_PER_TIME) -#define SDMMC_TEST_BUF_SIZE (SDMMC_SECTOR_SIZE * SDMMC_TEST_SECTORS_PER_TIME) +#define SDMMC_TEST_SECTORS (SDMMC_TEST_TIME * SDMMC_TEST_SECTORS_PER_TIME) +#define SDMMC_TEST_BUF_SIZE (SDMMC_SECTOR_SIZE * SDMMC_TEST_SECTORS_PER_TIME) static void sdmmc_thread_entry(void *parameter) { @@ -42,7 +47,8 @@ static void sdmmc_thread_entry(void *parameter) rt_uint32_t err_count = 0; rt_device_t sd_device; rt_uint32_t sector_start; - rt_uint32_t sector_end;; + rt_uint32_t sector_end; + ; rt_uint32_t sector_cur_start; rt_uint32_t sector_cur_end; rt_uint8_t *sector_rbuf; @@ -138,7 +144,6 @@ static void sdmmc_thread_entry(void *parameter) if (err_count == 0) { rt_kprintf("sector=[%d, %d]: ...... test ok...... !\r\n\r\n", sector_start, sector_end); - } else { diff --git a/bsp/hc32/tests/test_sdram.c b/bsp/hc32/tests/test_sdram.c index c02c78f0d38..ef37650e98f 100644 --- a/bsp/hc32/tests/test_sdram.c +++ b/bsp/hc32/tests/test_sdram.c @@ -14,7 +14,7 @@ * 程序功能：以8/16/32bit方式分别对整个SDRAM存储空间进行写和读操作，比较数据是否一致 * * 注意: - * F4A0: 修改函数SystemClock_Config，调用函数CLK_SetClockDiv参数，CLK_EXCLK_DIV2改为CLK_EXCLK_DIV8(EXCLK: 30MHz); + * F4A0/F4A2/F467: 修改函数SystemClock_Config，调用函数CLK_SetClockDiv参数，CLK_EXCLK_DIV2改为CLK_EXCLK_DIV8(EXCLK: 30MHz); * * menuconfig: * Hardware Drivers Config ---> Onboard Peripheral Drivers ----> Enable EXMC ----> Using SDRAM or NAND ----> Using SDRAM diff --git a/bsp/hc32/tests/test_soft_i2c.c b/bsp/hc32/tests/test_soft_i2c.c index 4cce95dabde..fd2b3b8127c 100644 --- a/bsp/hc32/tests/test_soft_i2c.c +++ b/bsp/hc32/tests/test_soft_i2c.c @@ -28,26 +28,26 @@ #if defined(BSP_USING_I2C1_SW) /* using i2c1 control oled12864 */ -#define SW_I2C_NAME "i2c1_sw" -#define SSD1306_ADDR (0x78U >> 1) -#define SSD1306_MD_CMD (0x00U) -#define SSD1306_MD_DATA (0x40U) +#define SW_I2C_NAME "i2c1_sw" +#define SSD1306_ADDR (0x78U >> 1) +#define SSD1306_MD_CMD (0x00U) +#define SSD1306_MD_DATA (0x40U) /* symbol parameters: width pixles, lenght pixels */ -#define SYM_W_PIX (8U) -#define SYM_H_PIX (8U) +#define SYM_W_PIX (8U) +#define SYM_H_PIX (8U) /* ssd ohysical parameters */ -#define SSD_PAGE_SIZE (8U) -#define SSD_COL_SIZE (128U) +#define SSD_PAGE_SIZE (8U) +#define SSD_COL_SIZE (128U) /* each page 8 pix */ -#define PAGE_PIX_SIZE (8U) +#define PAGE_PIX_SIZE (8U) /* each byte set horizontal 1 pix */ -#define SYM_W_BYTE (SYM_W_PIX / 1) +#define SYM_W_BYTE (SYM_W_PIX / 1) /* each byte set vertical 8 pix */ -#define SYM_H_BYTE (SYM_H_PIX / 8) +#define SYM_H_BYTE (SYM_H_PIX / 8) /* each character occupis */ -#define SYM_BYTE_SIZE (SYM_W_BYTE * SYM_H_BYTE) +#define SYM_BYTE_SIZE (SYM_W_BYTE * SYM_H_BYTE) /* soft i2c command defines */ enum SW_I2C_CMD @@ -175,8 +175,7 @@ static int sw_i2c_sample(int argc, char *argv[]) /* ssd1306 de-init and turn off */ static void ssd1306_deinit(struct rt_i2c_bus_device *i2c_dev) { - rt_uint8_t ssd_deinit_array[] = - { + rt_uint8_t ssd_deinit_array[] = { 0X8D, /* set charge pump */ 0X10, /* turn off charge pump */ 0XAE, /* OLED sleep */ @@ -259,8 +258,7 @@ static void ssd1306_roll_display(struct rt_i2c_bus_device *i2c_dev) u16WriteTimes++; } -rt_uint8_t ssd_init_array[] = -{ +rt_uint8_t ssd_init_array[] = { 0xAE, /* display off */ 0x20, /* Set Memory Addressing Mode */ 0x10, /* Set addressing orient */ @@ -293,13 +291,47 @@ rt_uint8_t ssd_init_array[] = }; -rt_uint8_t logo_array[][SYM_BYTE_SIZE] = -{ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x44, 0x44, 0x6C, 0x74, 0x54, 0x6C, 0x44, 0x44, /*"X"*/ - 0x44, 0x7C, 0x54, 0x10, 0x10, 0x54, 0x7C, 0x44, /*"H"*/ - 0x00, 0x68, 0x54, 0x54, 0x54, 0x54, 0x24, 0x00, /*"S"*/ - 0x38, 0x6C, 0x44, 0x44, 0x44, 0x44, 0x24, 0x00, /*"C"*/ +rt_uint8_t logo_array[][SYM_BYTE_SIZE] = { + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x00, + 0x44, + 0x44, + 0x6C, + 0x74, + 0x54, + 0x6C, + 0x44, + 0x44, /*"X"*/ + 0x44, + 0x7C, + 0x54, + 0x10, + 0x10, + 0x54, + 0x7C, + 0x44, /*"H"*/ + 0x00, + 0x68, + 0x54, + 0x54, + 0x54, + 0x54, + 0x24, + 0x00, /*"S"*/ + 0x38, + 0x6C, + 0x44, + 0x44, + 0x44, + 0x44, + 0x24, + 0x00, /*"C"*/ }; MSH_CMD_EXPORT(sw_i2c_sample, soft i2c sample); diff --git a/bsp/hc32/tests/test_spi.c b/bsp/hc32/tests/test_spi.c index 171c70da8d4..4381e6f28f8 100644 --- a/bsp/hc32/tests/test_spi.c +++ b/bsp/hc32/tests/test_spi.c @@ -6,6 +6,9 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-04 CDT Support HC32F467 + * 2026-07-10 CDT Modify SPI maxium clock to 30MHz */ /* @@ -24,54 +27,54 @@ #if defined(BSP_USING_SPI) #include "drv_spi.h" -#define W25Q_FLAG_BUSY (0x01) -#define W25Q_WR_ENABLE (0x06) -#define W25Q_SECTOR_ERASE (0x20) -#define W25Q_RD_STATUS_REG1 (0x05) -#define W25Q_PAGE_PROGRAM (0x02) -#define W25Q_STD_RD (0x03) - -#define W25Q_PAGE_SIZE (256UL) -#define W25Q_SECTOR_SIZE (1024UL * 4UL) -#define W25Q_PAGE_PER_SECTOR (W25Q_SECTOR_SIZE / W25Q_PAGE_SIZE) -#define W25Q_MAX_ADDR (0x800000UL) - -#define W25Q_SPI_WR_RD_ADDR 0x4000 -#if defined (HC32F460) || defined (HC32F4A0) || defined (HC32F472) || defined (HC32F448) || defined (HC32F4A8) - #define W25Q_SPI_DATA_BUF_LEN 0x2000 -#elif defined (HC32F334) - #define W25Q_SPI_DATA_BUF_LEN 0x1000 +#define W25Q_FLAG_BUSY (0x01) +#define W25Q_WR_ENABLE (0x06) +#define W25Q_SECTOR_ERASE (0x20) +#define W25Q_RD_STATUS_REG1 (0x05) +#define W25Q_PAGE_PROGRAM (0x02) +#define W25Q_STD_RD (0x03) + +#define W25Q_PAGE_SIZE (256UL) +#define W25Q_SECTOR_SIZE (1024UL * 4UL) +#define W25Q_PAGE_PER_SECTOR (W25Q_SECTOR_SIZE / W25Q_PAGE_SIZE) +#define W25Q_MAX_ADDR (0x800000UL) + +#define W25Q_SPI_WR_RD_ADDR 0x4000 +#if defined(HC32F460) || defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F472) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F467) +#define W25Q_SPI_DATA_BUF_LEN 0x2000 +#elif defined(HC32F334) +#define W25Q_SPI_DATA_BUF_LEN 0x1000 #endif -#if defined(HC32F4A0) || defined(HC32F448) || defined(HC32F4A8) - #define SPI_CS_PORT SPI1_CS_PORT - #define SPI_CS_PIN SPI1_CS_PIN - #define SPI_CS_PORT_PIN GET_PIN(C, 7) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F448) || defined(HC32F4A8) || defined(HC32F467) +#define SPI_CS_PORT SPI1_CS_PORT +#define SPI_CS_PIN SPI1_CS_PIN +#define SPI_CS_PORT_PIN GET_PIN(C, 7) - #define W25Q_SPI_BUS_NAME "spi1" - #define W25Q_SPI_DEVICE_NAME "spi10" +#define W25Q_SPI_BUS_NAME "spi1" +#define W25Q_SPI_DEVICE_NAME "spi10" #elif defined(HC32F472) - #define SPI_CS_PORT SPI1_CS_PORT - #define SPI_CS_PIN SPI1_CS_PIN - #define SPI_CS_PORT_PIN GET_PIN(B, 12) +#define SPI_CS_PORT SPI1_CS_PORT +#define SPI_CS_PIN SPI1_CS_PIN +#define SPI_CS_PORT_PIN GET_PIN(B, 12) - #define W25Q_SPI_BUS_NAME "spi1" - #define W25Q_SPI_DEVICE_NAME "spi10" +#define W25Q_SPI_BUS_NAME "spi1" +#define W25Q_SPI_DEVICE_NAME "spi10" #elif defined(HC32F460) - #define SPI_CS_PORT SPI3_CS_PORT - #define SPI_CS_PIN SPI3_CS_PIN - #define SPI_CS_PORT_PIN GET_PIN(C, 7) +#define SPI_CS_PORT SPI3_CS_PORT +#define SPI_CS_PIN SPI3_CS_PIN +#define SPI_CS_PORT_PIN GET_PIN(C, 7) - #define W25Q_SPI_BUS_NAME "spi3" - #define W25Q_SPI_DEVICE_NAME "spi30" +#define W25Q_SPI_BUS_NAME "spi3" +#define W25Q_SPI_DEVICE_NAME "spi30" #elif defined(HC32F334) - #define SPI_CS_PORT SPI1_CS_PORT - #define SPI_CS_PIN SPI1_CS_PIN - #define SPI_CS_PORT_PIN GET_PIN(C, 1) +#define SPI_CS_PORT SPI1_CS_PORT +#define SPI_CS_PIN SPI1_CS_PIN +#define SPI_CS_PORT_PIN GET_PIN(C, 1) - #define W25Q_SPI_BUS_NAME "spi1" - #define W25Q_SPI_DEVICE_NAME "spi10" +#define W25Q_SPI_BUS_NAME "spi1" +#define W25Q_SPI_DEVICE_NAME "spi10" #endif @@ -96,8 +99,8 @@ INIT_COMPONENT_EXPORT(rt_hw_spi_flash_init); void w25q_read_uid(struct rt_spi_device *device) { rt_uint8_t w25x_read_uid = 0x4B; /* 命令 */ - rt_uint8_t u8UID[8] = {0}; - rt_uint8_t txBuf[5] = {0}; + rt_uint8_t u8UID[8] = { 0 }; + rt_uint8_t txBuf[5] = { 0 }; memset(txBuf, 0xFF, 5); txBuf[0] = w25x_read_uid; @@ -115,19 +118,19 @@ void w25q_read_uid(struct rt_spi_device *device) /* 方式2：使用 rt_spi_transfer_message()发送命令读取ID */ struct rt_spi_message msg1, msg2; - msg1.send_buf = txBuf; - msg1.recv_buf = RT_NULL; - msg1.length = 5; - msg1.cs_take = 1; + msg1.send_buf = txBuf; + msg1.recv_buf = RT_NULL; + msg1.length = 5; + msg1.cs_take = 1; msg1.cs_release = 0; - msg1.next = &msg2; + msg1.next = &msg2; - msg2.send_buf = RT_NULL; - msg2.recv_buf = u8UID; - msg2.length = 8; - msg2.cs_take = 0; + msg2.send_buf = RT_NULL; + msg2.recv_buf = u8UID; + msg2.length = 8; + msg2.cs_take = 0; msg2.cs_release = 1; - msg2.next = RT_NULL; + msg2.next = RT_NULL; rt_spi_transfer_message(device, &msg1); rt_kprintf("use rt_spi_transfer_message() read w25q ID is: UID is: %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\r\n", @@ -138,8 +141,8 @@ int32_t w25q_check_process_done(struct rt_spi_device *device, uint32_t u32Timeou { __IO uint32_t u32Count = 0U; int32_t i32Ret = LL_ERR_TIMEOUT; - rt_uint8_t rxBuf[5] = {0}; - rt_uint8_t txBuf[5] = {0}; + rt_uint8_t rxBuf[5] = { 0 }; + rt_uint8_t txBuf[5] = { 0 }; txBuf[0] = W25Q_RD_STATUS_REG1; while (u32Count < u32Timeout) @@ -166,7 +169,7 @@ int32_t w25q_check_process_done(struct rt_spi_device *device, uint32_t u32Timeou int32_t w25q_read_data(struct rt_spi_device *device, uint32_t u32Addr, uint8_t *pu8ReadBuf, uint32_t u32Size) { int32_t i32Ret = LL_OK; - rt_uint8_t txBuf[5] = {0}; + rt_uint8_t txBuf[5] = { 0 }; txBuf[0] = W25Q_STD_RD; txBuf[1] = (u32Addr >> 16) & 0xFFU; @@ -221,9 +224,9 @@ int32_t w25q_write_data(struct rt_spi_device *device, uint32_t u32Addr, uint8_t break; } - u32Addr += u32TempSize; + u32Addr += u32TempSize; u32AddrOffset += u32TempSize; - u32Size -= u32TempSize; + u32Size -= u32TempSize; } return i32Ret; @@ -283,11 +286,11 @@ void w25q_write_read_data(struct rt_spi_device *device, uint32_t u32Addr) { rt_kprintf("spi erase sector failed!\n"); } - if (LL_OK != w25q_write_data(device, u32Addr, u8WrBuf, W25Q_SPI_DATA_BUF_LEN)) + if (LL_OK != w25q_write_data(device, u32Addr, u8WrBuf, W25Q_SPI_DATA_BUF_LEN)) { rt_kprintf("spi write data failed!\n"); } - if (LL_OK != w25q_read_data(device, u32Addr, u8RdBuf, W25Q_SPI_DATA_BUF_LEN)) + if (LL_OK != w25q_read_data(device, u32Addr, u8RdBuf, W25Q_SPI_DATA_BUF_LEN)) { rt_kprintf("spi read data failed!\n"); } @@ -308,7 +311,7 @@ static void spi_thread_entry(void *parameter) cfg.data_width = 8; cfg.mode = RT_SPI_MASTER | RT_SPI_MODE_0 | RT_SPI_MSB; - cfg.max_hz = 80 * 1000 * 1000; /* 80M */ + cfg.max_hz = 30 * 1000 * 1000; /* 30M */ rt_spi_configure(spi_dev_w25q, &cfg); /* 读取UID */ w25q_read_uid(spi_dev_w25q); diff --git a/bsp/hc32/tests/test_tmr_capture.c b/bsp/hc32/tests/test_tmr_capture.c index 2a94e5aee78..4f723bf966b 100644 --- a/bsp/hc32/tests/test_tmr_capture.c +++ b/bsp/hc32/tests/test_tmr_capture.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2025-01-10 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ /* @@ -16,7 +17,8 @@ * 默认配置 * input pin： * icx: INPUT_CAPTURE_TMR6_x_PORT, INPUT_CAPTURE_TMR6_x_PIN (x=1~IC_DEV_CNT) - 注：该引脚配置位于 board_config.h，若测试单元的input pin未配置，需测试人员自行添加 + 注：该引脚配置位于 board_config.h，若测试单元的input pin未配置，需测试人员自行添加,并于 + board_config.c中做初始化 * watermark： * 默认值为 5 * @@ -53,23 +55,23 @@ #include #include -#define MSH_USAGE_IC_OPEN " ic open - e.g., open ic3: ic open 3 \n" -#define MSH_USAGE_IC_CLOSE " ic close - e.g., close ic3: ic close 3\n" -#define MSH_USAGE_IC_SET_WM " ic wm - e.g., set warter mark of ic3 to 11: ic wm 3 11\n" -#define MSH_USAGE_IC_CLR " ic clr - e.g., clear data buffer of ic3: ic clr 3 \n" - -#if defined (HC32F4A0) || defined (HC32F4A8) - #define IC_DEV_CNT (8) -#elif defined (HC32F460) - #define IC_DEV_CNT (3) -#elif defined (HC32F334) - #define IC_DEV_CNT (4) -#elif defined (HC32F448) - #define IC_DEV_CNT (2) -#elif defined (HC32F472) - #define IC_DEV_CNT (10) +#define MSH_USAGE_IC_OPEN " ic open - e.g., open ic3: ic open 3 \n" +#define MSH_USAGE_IC_CLOSE " ic close - e.g., close ic3: ic close 3\n" +#define MSH_USAGE_IC_SET_WM " ic wm - e.g., set warter mark of ic3 to 11: ic wm 3 11\n" +#define MSH_USAGE_IC_CLR " ic clr - e.g., clear data buffer of ic3: ic clr 3 \n" + +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) +#define IC_DEV_CNT (8) +#elif defined(HC32F460) || defined(HC32F467) +#define IC_DEV_CNT (3) +#elif defined(HC32F334) +#define IC_DEV_CNT (4) +#elif defined(HC32F448) +#define IC_DEV_CNT (2) +#elif defined(HC32F472) +#define IC_DEV_CNT (10) #endif -#define DEFAULT_WATER_MARK (5) +#define DEFAULT_WATER_MARK (5) #ifdef BSP_USING_INPUT_CAPTURE @@ -82,7 +84,7 @@ typedef struct rt_thread_t thread; } test_ic_t; -static test_ic_t g_arr_test_ic[IC_DEV_CNT] = {0}; +static test_ic_t g_arr_test_ic[IC_DEV_CNT] = { 0 }; static int32_t _get_test_id(rt_device_t ic_dev) { @@ -109,7 +111,7 @@ static rt_err_t ic_rx_all(rt_device_t dev, rt_size_t size) static void ic_rx_thread(void *parameter) { - rt_size_t size; + rt_size_t size; rt_device_t ic_dev; test_ic_t *p_test_ic = parameter; ic_dev = p_test_ic->ic_dev; @@ -223,7 +225,7 @@ static rt_err_t _msh_cmd_parse_unit(char *n, uint32_t *u_out) return RT_EOK; } -void _show_usage(void) +static void _show_usage(void) { rt_kprintf("Usage: \n"); rt_kprintf(MSH_USAGE_IC_OPEN); @@ -297,7 +299,7 @@ static rt_int32_t ic(int argc, char *argv[]) } -MSH_CMD_EXPORT(ic, ic [opt]) +MSH_CMD_EXPORT(ic, ic[opt]) #endif /* EOF diff --git a/bsp/hc32/tests/test_uart_v1.c b/bsp/hc32/tests/test_uart_v1.c index 9d5958c0939..5799e8029d6 100644 --- a/bsp/hc32/tests/test_uart_v1.c +++ b/bsp/hc32/tests/test_uart_v1.c @@ -6,6 +6,7 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 */ /* @@ -39,17 +40,19 @@ #include #if defined(HC32F460) && defined(BSP_USING_UART2) - #define SAMPLE_DEFAULT_UART_NAME "uart2" -#elif defined(HC32F4A0) && defined (BSP_USING_UART6) - #define SAMPLE_DEFAULT_UART_NAME "uart6" -#elif defined(HC32F448) && defined (BSP_USING_UART1) - #define SAMPLE_DEFAULT_UART_NAME "uart1" -#elif defined(HC32F472) && defined (BSP_USING_UART1) - #define SAMPLE_DEFAULT_UART_NAME "uart1" -#elif defined(HC32F4A8) && defined (BSP_USING_UART6) - #define SAMPLE_DEFAULT_UART_NAME "uart6" -#elif defined(HC32F334) && defined (BSP_USING_UART1) - #define SAMPLE_DEFAULT_UART_NAME "uart1" +#define SAMPLE_DEFAULT_UART_NAME "uart2" +#elif (defined(HC32F4A0) || defined(HC32F4A2)) && defined(BSP_USING_UART6) +#define SAMPLE_DEFAULT_UART_NAME "uart6" /* TX:PE6, RX:PH6 */ +#elif defined(HC32F448) && defined(BSP_USING_UART1) +#define SAMPLE_DEFAULT_UART_NAME "uart1" +#elif defined(HC32F472) && defined(BSP_USING_UART1) +#define SAMPLE_DEFAULT_UART_NAME "uart1" +#elif defined(HC32F4A8) && defined(BSP_USING_UART6) +#define SAMPLE_DEFAULT_UART_NAME "uart6" +#elif defined(HC32F334) && defined(BSP_USING_UART1) +#define SAMPLE_DEFAULT_UART_NAME "uart1" +#elif defined(HC32F467) && defined(BSP_USING_UART6) +#define SAMPLE_DEFAULT_UART_NAME "uart6" #endif #if defined(SAMPLE_DEFAULT_UART_NAME) @@ -207,7 +210,7 @@ int uart_sample_v1(int argc, char *argv[]) config.baud_rate = BAUD_RATE_115200; //baudrate 115200 config.data_bits = DATA_BITS_8; //data bit 8 config.stop_bits = STOP_BITS_1; //stop bit 1 - config.parity = PARITY_NONE; + config.parity = PARITY_NONE; rt_device_control(serial, RT_DEVICE_CTRL_CONFIG, &config); if (0 == rt_strncmp(comm_mode, comm_mode_dma, 3)) diff --git a/bsp/hc32/tests/test_uart_v2.c b/bsp/hc32/tests/test_uart_v2.c index 11ab6c466de..48325d59958 100644 --- a/bsp/hc32/tests/test_uart_v2.c +++ b/bsp/hc32/tests/test_uart_v2.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ /* @@ -14,7 +16,7 @@ * * 命令解释：命令第二个参数是要使用的串口设备名称，为空则使用默认的串口设备(uart1) * 程序功能：通过串口输出字符串: - * drv_usart: drv_usart_v1 + * drv_usart: drv_usart_v2 * commnucation：using DMA/interrupt, * uart_ch: uartx (x对应测试通道) * 输出输入的字符 @@ -67,17 +69,19 @@ #include #if defined(HC32F460) && defined(BSP_USING_UART2) - #define SAMPLE_DEFAULT_UART_NAME "uart2" -#elif defined(HC32F4A0) && defined (BSP_USING_UART6) - #define SAMPLE_DEFAULT_UART_NAME "uart6" -#elif defined(HC32F448) && defined (BSP_USING_UART1) - #define SAMPLE_DEFAULT_UART_NAME "uart1" -#elif defined(HC32F472) && defined (BSP_USING_UART1) - #define SAMPLE_DEFAULT_UART_NAME "uart1" -#elif defined(HC32F4A8) && defined (BSP_USING_UART6) - #define SAMPLE_DEFAULT_UART_NAME "uart6" -#elif defined(HC32F334) && defined (BSP_USING_UART1) - #define SAMPLE_DEFAULT_UART_NAME "uart1" +#define SAMPLE_DEFAULT_UART_NAME "uart2" +#elif (defined(HC32F4A0) || defined(HC32F4A2)) && defined(BSP_USING_UART6) +#define SAMPLE_DEFAULT_UART_NAME "uart6" /* TX:PE6, RX:PH6 */ +#elif defined(HC32F448) && defined(BSP_USING_UART1) +#define SAMPLE_DEFAULT_UART_NAME "uart1" +#elif defined(HC32F472) && defined(BSP_USING_UART1) +#define SAMPLE_DEFAULT_UART_NAME "uart1" +#elif defined(HC32F4A8) && defined(BSP_USING_UART6) +#define SAMPLE_DEFAULT_UART_NAME "uart6" +#elif defined(HC32F334) && defined(BSP_USING_UART1) +#define SAMPLE_DEFAULT_UART_NAME "uart1" +#elif defined(HC32F467) && defined(BSP_USING_UART6) +#define SAMPLE_DEFAULT_UART_NAME "uart6" #endif #if defined(SAMPLE_DEFAULT_UART_NAME) @@ -234,7 +238,7 @@ int uart_sample_v2(int argc, char *argv[]) config.baud_rate = BAUD_RATE_115200; //baudrate 115200 config.data_bits = DATA_BITS_8; //data bit 8 config.stop_bits = STOP_BITS_1; //stop bit 1 - config.parity = PARITY_NONE; + config.parity = PARITY_NONE; rt_device_control(serial, RT_DEVICE_CTRL_CONFIG, &config); if (0 == rt_strncmp(comm_mode, comm_mode_dma, 3)) diff --git a/bsp/hc32/tests/test_usbd.c b/bsp/hc32/tests/test_usbd.c index 5a4a19027bd..be867a3bfe7 100644 --- a/bsp/hc32/tests/test_usbd.c +++ b/bsp/hc32/tests/test_usbd.c @@ -6,6 +6,8 @@ * Change Logs: * Date Author Notes * 2024-12-30 CDT first version + * 2026-05-27 CDT Support HC32F4A2 + * 2026-06-03 CDT Support HC32F467 */ #include @@ -31,14 +33,19 @@ * 发送内容可在Finsh串口显示。 */ -#define USBD_DEV_NAME "vcom" /* 名称 */ -rt_uint8_t str_read[255]; +#define USBD_DEV_NAME "vcom" /* 名称 */ +static rt_uint8_t cdc_str_read[256]; static rt_err_t cdc_rx_handle(rt_device_t dev, rt_size_t size) { + if (size >= sizeof(cdc_str_read)) + { + size = sizeof(cdc_str_read) - 1; + } /* 读取虚拟串口接收内容 */ - rt_device_read(dev, 0, str_read, size); - rt_kprintf("Read message: %s\n", str_read); + rt_device_read(dev, 0, cdc_str_read, size); + cdc_str_read[size] = '\0'; + rt_kprintf("Read message: %s\n", cdc_str_read); return RT_EOK; } @@ -90,9 +97,9 @@ MSH_CMD_EXPORT(cdc_sample, usbd cdc sample); #if defined(RT_USB_DEVICE_MSTORAGE) -/* F4A0 only FS can used with spi flash */ -#if ((defined(HC32F4A0) || defined(HC32F4A8)) && defined(BSP_USING_USBFS)) || \ - defined(HC32F460) || defined(HC32F472) +/* F4A0/F4A2/HC32F467 only FS can used with spi flash */ +#if ((defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F467)) && defined(BSP_USING_USBFS)) || \ + defined(HC32F460) || defined(HC32F472) /* Enable spibus1, SFUD, usb msc */ /* menuconfig: @@ -108,30 +115,30 @@ MSH_CMD_EXPORT(cdc_sample, usbd cdc sample); (50000000)Default spi maximum speed(HZ) 4. RT-Thread Components--->Using USB legacy version [*]Using USB device---> - Device type--->...Mass Storage device - (spiflash)msc class disk name + [*]Device type---> Enable to use device as Mass Storage device + (spiflash)msc class disk name */ #include "drv_gpio.h" #include "drv_spi.h" #include "dev_spi_flash_sfud.h" -#define SPI_FLASH_CHIP RT_USB_MSTORAGE_DISK_NAME /* msc class disk name */ -#if defined(HC32F4A0) || defined(HC32F4A8) - #define SPI_FLASH_SS_PORT GPIO_PORT_C - #define SPI_FLASH_SS_PIN GPIO_PIN_07 - #define SPI_BUS_NAME "spi1" - #define SPI_FLASH_DEVICE_NAME "spi10" +#define SPI_FLASH_CHIP RT_USB_MSTORAGE_DISK_NAME /* msc class disk name */ +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) +#define SPI_FLASH_SS_PORT GPIO_PORT_C +#define SPI_FLASH_SS_PIN GPIO_PIN_07 +#define SPI_BUS_NAME "spi1" +#define SPI_FLASH_DEVICE_NAME "spi10" #elif defined(HC32F460) - #define SPI_FLASH_SS_PORT GPIO_PORT_C - #define SPI_FLASH_SS_PIN GPIO_PIN_07 - #define SPI_BUS_NAME "spi3" - #define SPI_FLASH_DEVICE_NAME "spi30" +#define SPI_FLASH_SS_PORT GPIO_PORT_C +#define SPI_FLASH_SS_PIN GPIO_PIN_07 +#define SPI_BUS_NAME "spi3" +#define SPI_FLASH_DEVICE_NAME "spi30" #elif defined(HC32F472) - #define SPI_FLASH_SS_PORT GPIO_PORT_B - #define SPI_FLASH_SS_PIN GPIO_PIN_12 - #define SPI_BUS_NAME "spi1" - #define SPI_FLASH_DEVICE_NAME "spi10" +#define SPI_FLASH_SS_PORT GPIO_PORT_B +#define SPI_FLASH_SS_PIN GPIO_PIN_12 +#define SPI_BUS_NAME "spi1" +#define SPI_FLASH_DEVICE_NAME "spi10" #endif static void rt_hw_spi_flash_reset(char *spi_dev_name) @@ -157,7 +164,8 @@ static void rt_hw_spi_flash_reset(char *spi_dev_name) static int rt_hw_spi_flash_with_sfud_init(void) { -#if defined(HC32F4A0) || defined(HC32F460) || defined(HC32F4A8) +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F460) || defined(HC32F4A8) || \ + defined(HC32F467) rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, GET_PIN(C, 7)); #elif defined(HC32F472) rt_hw_spi_device_attach(SPI_BUS_NAME, SPI_FLASH_DEVICE_NAME, GET_PIN(B, 12)); @@ -200,20 +208,20 @@ INIT_COMPONENT_EXPORT(rt_hw_spi_flash_with_sfud_init); * 发送内容可在Finsh串口显示。 */ -#define USBD_DEV_NAME "hidd" /* 名称 */ -#if defined(HC32F4A0) || defined(HC32F4A8) - #define KEY_PIN_NUM GET_PIN(A,0) /* PA0 */ +#define USBD_DEV_NAME "hidd" /* 名称 */ +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) +#define KEY_PIN_NUM GET_PIN(A, 0) /* PA0 */ #elif defined(HC32F460) - #define KEY_PIN_NUM GET_PIN(B,1) /* PB1 */ +#define KEY_PIN_NUM GET_PIN(B, 1) /* PB1 */ #elif defined(HC32F472) - #define KEY_PIN_NUM GET_PIN(B,5) /* PB5 */ +#define KEY_PIN_NUM GET_PIN(B, 5) /* PB5 */ #endif static int hid_sample(void) { rt_err_t ret = RT_EOK; rt_device_t hid_dev = RT_NULL; /* usb device设备句柄 */ - char str_write[2][5] = {"test", "Key0"}; + char str_write[2][5] = { "test", "Key0" }; /* 查找设备 */ @@ -246,7 +254,8 @@ static int hid_sample(void) } } - //return ret; + /* unreachable, but keeps static analyzers happy */ + return ret; } /* 导出到 msh 命令列表中 */ MSH_CMD_EXPORT(hid_sample, usbd hid sample); @@ -274,25 +283,29 @@ MSH_CMD_EXPORT(hid_sample, usbd hid sample); * 通过llcom.exe可发送bulk数据（100字符以内）到设备，设备收到后会回发给主机(llcom.exe)，同时通过MSH终端显示收到的HEX数据。 * 注意：1、llcom.exe中的GUID与驱动程序中设定保持一致(通过设备管理器选择RTT Win USB设备的属性来查看)； * 2、win_usb_read()函数中的UIO_REQUEST_READ_FULL改为UIO_REQUEST_READ_BEST，实现数据即读即取; - * 否则需要接满传入的size数量，才会回调接收函数。 + * 否则需要接满传入的sizeof(winusb_str_read)数量的数据，才会回调接收函数。 * */ -#define WINUSB_DEV_NAME "winusb" /* 名称 */ -uint8_t str_read[100]; +#define WINUSB_DEV_NAME "winusb" /* 名称 */ +static rt_uint8_t winusb_str_read[100]; static rt_err_t winusb_rx_handle(rt_device_t dev, rt_size_t size) { uint8_t i; + if (size > sizeof(winusb_str_read)) + { + size = sizeof(winusb_str_read); + } /* 读取定时器当前值 */ rt_kprintf("Rx:"); for (i = 0; i < size; i++) { - rt_kprintf("%x", str_read[i]); + rt_kprintf("%x", winusb_str_read[i]); } rt_kprintf("\r\n"); - rt_device_write(dev, 0, str_read, size); + rt_device_write(dev, 0, winusb_str_read, size); /* prepare read config */ - rt_device_read(dev, 0, str_read, sizeof(str_read)); + rt_device_read(dev, 0, winusb_str_read, sizeof(winusb_str_read)); return RT_EOK; } @@ -322,7 +335,7 @@ static int winusb_sample(void) if (ret == RT_EOK) { /* prepare read config,set once,read once, */ - rt_device_read(winusb_dev, 0, str_read, sizeof(str_read)); + rt_device_read(winusb_dev, 0, winusb_str_read, sizeof(winusb_str_read)); } return ret; } diff --git a/bsp/hc32/tests/test_usbh.c b/bsp/hc32/tests/test_usbh.c index e5cddafc61d..243acb5a0ed 100644 --- a/bsp/hc32/tests/test_usbh.c +++ b/bsp/hc32/tests/test_usbh.c @@ -38,7 +38,7 @@ */ #include #include -#define TEST_FN "/test_usbh.c" +#define TEST_FN "/test_usbh.c" static char test_data[120], buffer[120]; void usbh_readwrite(const char *filename) @@ -53,7 +53,7 @@ void usbh_readwrite(const char *filename) return; } - for (index = 0; index < sizeof(test_data); index ++) + for (index = 0; index < sizeof(test_data); index++) { test_data[index] = index + 27; } @@ -83,7 +83,7 @@ void usbh_readwrite(const char *filename) return; } - for (index = 0; index < sizeof(test_data); index ++) + for (index = 0; index < sizeof(test_data); index++) { if (test_data[index] != buffer[index]) { diff --git a/bsp/hc32/tests/test_wdt.c b/bsp/hc32/tests/test_wdt.c index c3c17151427..476a5a4305a 100644 --- a/bsp/hc32/tests/test_wdt.c +++ b/bsp/hc32/tests/test_wdt.c @@ -23,9 +23,9 @@ #ifdef BSP_USING_WDT_TMR #if defined(BSP_USING_WDT) - #define WDT_DEVICE_NAME "wdt" +#define WDT_DEVICE_NAME "wdt" #elif defined(BSP_USING_SWDT) - #define WDT_DEVICE_NAME "swdt" +#define WDT_DEVICE_NAME "swdt" #endif static rt_device_t wdg_dev; @@ -120,6 +120,6 @@ static int wdt_sample(int argc, char *argv[]) return ret; } -MSH_CMD_EXPORT(wdt_sample, wdt_sample [option]); +MSH_CMD_EXPORT(wdt_sample, wdt_sample[option]); #endif diff --git a/bsp/hc32/tests/test_wktm.c b/bsp/hc32/tests/test_wktm.c new file mode 100644 index 00000000000..6633b448631 --- /dev/null +++ b/bsp/hc32/tests/test_wktm.c @@ -0,0 +1,115 @@ +/* + * Copyright (c) 2022-2026, Xiaohua Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2026-06-24 CDT first version + */ + +/** + * menuconfig: + * Hardware Drivers Config ---> On-Chip Peripheral Driver---> [*] Enable PM + * RT-Thread Kernel ---> (1024) The stack size of idle thread + */ + +#include +#include "board.h" +#include "drv_wktm.h" + +#if defined(BSP_USING_PM) + +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) +#define WKTM_IRQn (INT131_IRQn) +#elif defined(HC32F460) +#define WKTM_IRQn (INT130_IRQn) +#endif + +static volatile rt_uint32_t last_tick; + +#if defined(HC32F334) || defined(HC32F448) || defined(HC32F472) +void PWC_WKTM_Handler(void) +#elif defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) || defined(HC32F460) +void PWC_WakeupTimer_IrqHandler(void) +#endif +{ + static rt_uint32_t delta_tick; + + rt_interrupt_enter(); + + delta_tick = rt_tick_get() - last_tick; + last_tick = rt_tick_get(); + + /* 打印出的tick值由于printf原因可能有误差 */ + rt_kprintf("Wakeup-timer irq interval ticks: approximate %d.\r\n", delta_tick); + + rt_interrupt_leave(); + +#if defined(HC32F334) || defined(HC32F448) || defined(HC32F472) + __DSB(); /* Arm Errata 838869: Cortex-M4, Cortex-M4F */ +#endif +} + +void wktm_sample(int argc, char **argv) +{ + rt_base_t level; + rt_uint32_t cmp_value; + rt_uint32_t cmp_max = hc32_wktm_get_tick_max(); + + if (argc >= 2) + { + cmp_value = atol(argv[1]); + if (0UL == cmp_value) + { + /*********************** Stop wakeup-timer ************************/ + hc32_wktm_stop(); + + NVIC_DisableIRQ(WKTM_IRQn); + NVIC_ClearPendingIRQ(WKTM_IRQn); + + rt_kprintf("Stop Wakeup-timer\n\n"); + } + else if (cmp_value > cmp_max) + { + /*********************** Hold the wakeup timer configuration ******/ + rt_kprintf("compare value %d is out of %d(max), so hold the wakeup timer configuration \n\n", cmp_value, cmp_max); + } + else if (cmp_value < (cmp_max / 2)) + { + /*********************** Hold the wakeup timer configuration ******/ + rt_kprintf("compare value %d is less of %d(max/2), so hold the wakeup timer configuration: ", cmp_value, cmp_max / 2); + rt_kprintf("to avoid frequent interruptions: too much printed information affcets console commands \n\n"); + } + else + { + /*********************** Start wakeup-timer ***********************/ + /* Wakeup timer NVIC config */ +#if defined(HC32F4A0) || defined(HC32F4A2) || defined(HC32F4A8) || defined(HC32F467) || defined(HC32F460) + (void)INTC_ShareIrqCmd(INT_SRC_WKTM_PRD, ENABLE); +#endif + NVIC_ClearPendingIRQ(WKTM_IRQn); + NVIC_SetPriority(WKTM_IRQn, DDL_IRQ_PRIO_DEFAULT); + NVIC_EnableIRQ(WKTM_IRQn); + + if (RT_EOK == hc32_wktm_start(cmp_value)) + { + level = rt_hw_interrupt_disable(); + last_tick = rt_tick_get(); + rt_hw_interrupt_enable(level); + rt_kprintf("Update wakeup-timer compare value = %d, and start timer \n\n", cmp_value); + } + else + { + rt_kprintf("Fail to set wakeup-timer compare value \n\n", cmp_value); + } + } + } + else + { + rt_kprintf("wktm_sample 0: stop wakeup-timer \n"); + rt_kprintf("wktm_sample %d~%d: set wakeup-timer compare value and start timer \n\n", cmp_max / 2, cmp_max); + } +} +MSH_CMD_EXPORT(wktm_sample, wktm_sample compare_value); +#endif