diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index 9ac03f6b7ab..b044ad4604e 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -189,8 +189,10 @@ jobs: - "lpc176x" - "xplorer4330/M4" #- "lpc43xx/M4" - - "renesas/ra6m3-ek" + - "renesas/ebf_qi_min_6m5" - "renesas/ra6m4-cpk" + - "renesas/ra6m4-iot" + - "renesas/ra6m3-ek" - "renesas/ra6m3-hmi-board" - "renesas/ra4m2-eco" - "renesas/ra2l1-cpk" diff --git a/bsp/renesas/README.md b/bsp/renesas/README.md index e97034442d5..15a603eef90 100644 --- a/bsp/renesas/README.md +++ b/bsp/renesas/README.md @@ -3,15 +3,18 @@ RA 系列 BSP 目前支持情况如下表所示： -| **BSP 文件夹名称** | **开发板名称** | -|:------------------------- |:-------------------------- | -| **RA6 系列** | | -| [ra6m4-cpk](ra6m4-cpk) | Renesas 官方 CPK-RA6M4 开发板 | -| [ra6m4-iot](ra6m4-iot) | Renesas 官方 IOT-RA6M4 开发板 | -| [ra6m3-ek](ra6m3-ek) | Renesas 官方 RA6M3-EK 开发板 | +| **BSP 文件夹名称** | **开发板名称** | +| :--------------------------------- | :-------------------------------------------- | +| **RA6 系列** | | +| [ebf_qi_min_6m5](ebf_qi_min_6m5) | 野火 启明6 开发板 | +| [ra6m4-cpk](ra6m4-cpk) | Renesas 官方 CPK-RA6M4 开发板 | +| [ra6m4-iot](ra6m4-iot) | Renesas 官方 IOT-RA6M4 开发板 | +| [ra6m3-ek](ra6m3-ek) | Renesas 官方 RA6M3-EK 开发板 | | [ra6m3-hmi-board](ra6m3-hmi-board) | Renesas 联合 RT-Thread RA6M3-HMI-Board 开发板 | +| **RA4 系列** | | +| [ra4m2-eco](ra4m2-eco) | Renesas 官方 RA-Eco-RA4M2 开发板 | | **RA2 系列** | | -| [ra2l1-cpk](ra2l1-cpk) | Renesas 官方 CPK-RA2L1 开发板 | +| [ra2l1-cpk](ra2l1-cpk) | Renesas 官方 CPK-RA2L1 开发板 | 可以通过阅读相应 BSP 下的 README 来快速上手，如果想要使用 BSP 更多功能可参考 docs 文件夹下提供的说明文档，如下表所示： @@ -20,6 +23,8 @@ RA 系列 BSP 目前支持情况如下表所示： | [外设驱动使用教程](docs/RA系列BSP外设驱动使用教程.md) | 讲解 BSP 上更多外设驱动的使用方法 | | [外设驱动介绍与应用](docs/RA系列驱动介绍.md) | 讲解 RA 系列 BSP 驱动的支持情况，以及如何利用驱动框架开发应用程序 | | [使用 FSP 配置外设驱动](docs/RA系列使用FSP配置外设驱动.md) | 介绍如何使用 FSP 工具添加和配置外设 | +| [瑞萨RA2L1开发实践指南](https://docs.qq.com/doc/DQktJWmpBZkNiTnh6) | 介绍基于 RA2L1 如何添加和配置外设 | +| [瑞萨RA6m3开发实践指南](https://docs.qq.com/doc/DQmVYUEN1dHVyd0hi) | 介绍基于 RA6M3 如何添加和配置外设 | | **BSP 制作与提交** | **简介** | | [BSP 制作教程](docs/RA系列BSP制作教程.md) | 讲解 RA 系列 BSP 的制作方法，以及在制作 BSP 和提交 BSP 时应当遵守的规范 | | [外设驱动添加指南](docs/RA系列外设驱动添加指南.md) | 讲解 BSP 添加更多设备驱动的方法 | diff --git a/bsp/renesas/ebf_qi_min_6m5/.config b/bsp/renesas/ebf_qi_min_6m5/.config index d81bb2408af..0b5a67ff2c0 100644 --- a/bsp/renesas/ebf_qi_min_6m5/.config +++ b/bsp/renesas/ebf_qi_min_6m5/.config @@ -9,6 +9,7 @@ CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=8 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -33,18 +34,10 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set # CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y # # Inter-Thread communication @@ -54,12 +47,12 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 # CONFIG_RT_USING_MEMPOOL is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set @@ -83,7 +76,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" -CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set # CONFIG_RT_USING_CACHE is not set CONFIG_RT_USING_HW_ATOMIC=y @@ -117,6 +110,10 @@ CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# # CONFIG_RT_USING_DFS is not set # CONFIG_RT_USING_FAL is not set @@ -210,9 +207,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set # # RT-Thread Utestcases @@ -237,7 +236,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set @@ -508,6 +506,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set # CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set # # peripheral libraries and drivers @@ -592,6 +591,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_FT5426 is not set # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -604,7 +604,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set # # Kendryte SDK @@ -662,14 +661,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # # AI packages @@ -688,7 +690,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # Signal Processing and Control Algorithm Packages # # CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set # # miscellaneous packages @@ -735,7 +740,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set @@ -760,8 +764,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set @@ -908,14 +913,19 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set # # Timing # # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # # Data Processing @@ -995,6 +1005,9 @@ CONFIG_BSP_USING_UART4=y # CONFIG_BSP_UART4_TX_USING_DMA is not set CONFIG_BSP_UART4_RX_BUFSIZE=256 CONFIG_BSP_UART4_TX_BUFSIZE=0 +# CONFIG_BSP_USING_I2C is not set +# CONFIG_BSP_USING_SCI_SPI is not set +# CONFIG_BSP_USING_SPI is not set # # Board extended module Drivers diff --git a/bsp/renesas/ebf_qi_min_6m5/SConstruct b/bsp/renesas/ebf_qi_min_6m5/SConstruct index d00d0dbeaac..67511e3048a 100644 --- a/bsp/renesas/ebf_qi_min_6m5/SConstruct +++ b/bsp/renesas/ebf_qi_min_6m5/SConstruct @@ -21,6 +21,7 @@ DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/bsp/renesas/ebf_qi_min_6m5/project.uvoptx b/bsp/renesas/ebf_qi_min_6m5/project.uvoptx index 8a461588377..f9621db9c45 100644 --- a/bsp/renesas/ebf_qi_min_6m5/project.uvoptx +++ b/bsp/renesas/ebf_qi_min_6m5/project.uvoptx @@ -1,180 +1,745 @@ - + - 1.0 -
### uVision Project, (C) Keil Software
- - *.c - *.s*; *.src; *.a* - *.obj; *.o - *.lib - *.txt; *.h; *.inc - *.plm - *.cpp - 0 - - - 0 - 0 - - - Target 1 - 0x4 - ARM-ADS - - 12000000 - - 1 - 1 - 0 - 1 - 1 - - - 1 - 65535 - 0 - 0 - 0 - - - 79 - 66 - 8 - .\Listings\ - - - 1 - 1 - 1 - 0 - 1 - 1 - 0 - 1 - 0 - 0 - 0 - 0 - - - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 0 - - - 1 - 0 - 1 - - 255 - - 0 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 0 - 1 - 1 - 1 - 1 - 0 - 0 - 1 - 0 - 0 - 4 - - - - - - - - - - - Segger\JL2CM3.dll - - - - 0 - JL2CM3 - -U-O78 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C-1 -JU1 -JI127.0.0.1 -JP0 -RST0 -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD0 -FC800 -FN0 - - - - - 0 - - - 0 - 1 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - 0 - - - - 0 - 0 - 0 - - - - - - - - - - - - Source Group 1 - 0 + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc; *.md + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + Target 1 + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 1 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\Listings\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 1 0 - 0 - 0 - - - ::Flex Software - 0 - 0 - 0 - 1 - + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 4 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC2000 -FN3 -FF0RA6M5_2M -FS00 -FL0200000 -FF1RA6M5_DATA_C2M -FS18000000 -FL12000 -FF2RA6M5_CONF -FS2100A000 -FL2300 -FP0($$Device:R7FA6M5BH$Flash\RA6M5_2M.FLM) -FP1($$Device:R7FA6M5BH$Flash\RA6M5_DATA_C2M.FLM) -FP2($$Device:R7FA6M5BH$Flash\RA6M5_CONF.FLM)) + + + 0 + JL2CM3 + -U20730543 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST0 -N00("ARM CoreSight SW-DP") -D00(6BA02477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD20000000 -FC8000 -FN3 -FF0RA6M5_2M -FS00 -FL0200000 -FP0($$Device:R7FA6M5BH$Flash\RA6M5_2M.FLM) -FF1RA6M5_CONF -FS1100A100 -FL1300 -FP1($$Device:R7FA6M5BH$Flash\RA6M5_CONF.FLM) -FF2RA6M5_DATA_C2M -FS28000000 -FL22000 -FP2($$Device:R7FA6M5BH$Flash\RA6M5_DATA_C2M.FLM) + + + + + 0 + + + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + 0 + 0 + + + + + + + + + + + + + Compiler + 0 + 0 + 0 + 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdio.c + cstdio.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\atomic_arm.c + atomic_arm.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 12 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\core\device.c + device.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion.c + completion.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial_v2.c + serial_v2.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 24 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_common.c + drv_common.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_usart_v2.c + drv_usart_v2.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 5 + 27 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 28 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler_up.c + scheduler_up.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + :Renesas RA Smart Configurator:Common Sources + 0 + 0 + 0 + 0 + + 7 + 42 + 1 + 0 + 0 + 0 + .\src\hal_entry.c + hal_entry.c + 0 + 0 + + + + + ::Flex Software + 0 + 0 + 0 + 1 + + diff --git a/bsp/renesas/ebf_qi_min_6m5/project.uvprojx b/bsp/renesas/ebf_qi_min_6m5/project.uvprojx index 7a9bcfa946b..0a12cd08aaf 100644 --- a/bsp/renesas/ebf_qi_min_6m5/project.uvprojx +++ b/bsp/renesas/ebf_qi_min_6m5/project.uvprojx @@ -1,42 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ Target 1 0x4 ARM-ADS + 6190000::V6.19::ARMCLANG 1 R7FA6M5BH Renesas - Renesas.RA_DFP.3.5.0 - + Renesas.RA_DFP.4.4.0 + https://www2.renesas.eu/Keil_MDK_Packs/ CPUTYPE("Cortex-M33") FPU2 CLOCK(12000000) ELITTLE - - - + + + 0 - - - - - - - - - - - + + + + + + + + + + + $$Device:R7FA6M5BH$SVD\R7FA6M5BH.svd 0 0 - - - - - + + + + + 0 0 @@ -58,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -68,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -79,14 +83,14 @@ 1 0 cmd /c "start "Renesas" /w cmd /c ""$Slauncher\rasc_launcher.bat" "3.5.0" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2> "%%TEMP%%\rasc_stderr.out""" - + 0 0 2 0 0 - + 0 @@ -100,8 +104,8 @@ 0 0 3 - - + + 1 @@ -125,20 +129,20 @@ - 0 + 1 0 0 - 0 + 1 1 -1 1 - + "" () - - - - + + + + 0 @@ -171,7 +175,7 @@ 0 0 "Cortex-M33" - + 0 0 0 @@ -182,6 +186,7 @@ 2 0 0 + 0 0 0 0 @@ -305,7 +310,7 @@ 0x0 - + 1 @@ -318,7 +323,7 @@ 0 0 0 - 0 + 3 0 0 0 @@ -333,9 +338,9 @@ 0 -Wno-license-management -Wunused -Wuninitialized -Wall -Wextra -Wmissing-declarations -Wconversion -Wpointer-arith -Wshadow -Waggregate-return -Wfloat-equal - RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - - ..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\include;board\ports;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers;board;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;. + __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC + + board;..\..\..\components\finsh;board\ports;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;..\libraries\HAL_Drivers\config;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m4;.;..\..\..\components\libc\posix\io\stdio;..\..\..\include @@ -350,10 +355,10 @@ 0 4 - - - - + + + + @@ -363,14 +368,14 @@ 0 0 0 - - - + + + .\script\fsp.scat - - - - + + + + 6319,6314 @@ -384,50 +389,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdio.c 1 ..\..\..\components\libc\compilers\common\cstdio.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cwchar.c 1 @@ -443,29 +434,21 @@ 1 ..\..\..\libcpu\arm\common\atomic_arm.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - - cpuport.c 1 @@ -476,62 +459,51 @@ DeviceDrivers + + device.c + 1 + ..\..\..\components\drivers\core\device.c + completion.c 1 ..\..\..\components\drivers\ipc\completion.c - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c - - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - serial_v2.c 1 @@ -547,51 +519,164 @@ 1 ..\libraries\HAL_Drivers\drv_common.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 -std=c99 - + - - drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 -std=c99 - + - - drv_usart_v2.c 1 ..\libraries\HAL_Drivers\drv_usart_v2.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 -std=c99 - + @@ -603,30 +688,24 @@ Finsh - shell.c + cmd.c 1 - ..\..\..\components\finsh\shell.c + ..\..\..\components\finsh\cmd.c - - - msh.c + shell.c 1 - ..\..\..\components\finsh\msh.c + ..\..\..\components\finsh\shell.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - - cmd.c + msh.c 1 - ..\..\..\components\finsh\cmd.c + ..\..\..\components\finsh\msh.c @@ -638,78 +717,51 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - object.c 1 ..\..\..\src\object.c - - scheduler_up.c 1 ..\..\..\src\scheduler_up.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -717,26 +769,41 @@ + + :Renesas RA Smart Configurator:Common Sources + + + hal_entry.c + 1 + .\src\hal_entry.c + + + + + ::Flex Software + + - + - + - + - + - + + diff --git a/bsp/renesas/ebf_qi_min_6m5/rtconfig.h b/bsp/renesas/ebf_qi_min_6m5/rtconfig.h index 47fc8c0192b..00801a18997 100644 --- a/bsp/renesas/ebf_qi_min_6m5/rtconfig.h +++ b/bsp/renesas/ebf_qi_min_6m5/rtconfig.h @@ -23,8 +23,10 @@ /* kservice optimization */ -#define RT_DEBUG -#define RT_DEBUG_COLOR +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ @@ -36,7 +38,6 @@ /* Memory Management */ -#define RT_PAGE_MAX_ORDER 11 #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP @@ -47,7 +48,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart4" -#define RT_VER_NUM 0x50000 +#define RT_VER_NUM 0x50001 #define RT_USING_HW_ATOMIC #define RT_USING_CPU_FFS #define ARCH_ARM @@ -74,6 +75,9 @@ #define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 +/* DFS: device virtual file system */ + + /* Device Drivers */ #define RT_USING_DEVICE_IPC @@ -190,7 +194,7 @@ /* Arduino libraries */ -/* Projects */ +/* Projects and Demos */ /* Sensors */ diff --git a/bsp/renesas/ebf_qi_min_6m5/rtconfig.py b/bsp/renesas/ebf_qi_min_6m5/rtconfig.py index fecaf84af2e..92a08e434d8 100644 --- a/bsp/renesas/ebf_qi_min_6m5/rtconfig.py +++ b/bsp/renesas/ebf_qi_min_6m5/rtconfig.py @@ -56,6 +56,7 @@ AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -Os' + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/renesas/ra2l1-cpk/.config b/bsp/renesas/ra2l1-cpk/.config index 58814a1f3b0..f39474c3404 100644 --- a/bsp/renesas/ra2l1-cpk/.config +++ b/bsp/renesas/ra2l1-cpk/.config @@ -34,18 +34,10 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set # CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT is not set -# CONFIG_RT_DEBUG_THREAD is not set -# CONFIG_RT_DEBUG_SCHEDULER is not set -# CONFIG_RT_DEBUG_IPC is not set -# CONFIG_RT_DEBUG_TIMER is not set -# CONFIG_RT_DEBUG_IRQ is not set -# CONFIG_RT_DEBUG_MEM is not set -# CONFIG_RT_DEBUG_SLAB is not set -# CONFIG_RT_DEBUG_MEMHEAP is not set -# CONFIG_RT_DEBUG_MODULE is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y # # Inter-Thread communication @@ -134,6 +126,7 @@ CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set # CONFIG_RT_USING_FAL is not set # @@ -226,10 +219,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set -# CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RESOURCE_ID is not set +# CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set # # RT-Thread Utestcases diff --git a/bsp/renesas/ra2l1-cpk/SConstruct b/bsp/renesas/ra2l1-cpk/SConstruct index d00d0dbeaac..67511e3048a 100644 --- a/bsp/renesas/ra2l1-cpk/SConstruct +++ b/bsp/renesas/ra2l1-cpk/SConstruct @@ -21,6 +21,7 @@ DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/bsp/renesas/ra2l1-cpk/project.uvoptx b/bsp/renesas/ra2l1-cpk/project.uvoptx index 2a3804a8cb6..a966455febc 100644 --- a/bsp/renesas/ra2l1-cpk/project.uvoptx +++ b/bsp/renesas/ra2l1-cpk/project.uvoptx @@ -135,7 +135,7 @@ 0 DLGUARM - d + 0 @@ -149,7 +149,7 @@ 0 43 1 -
9320
+
2612
0 0 0 @@ -323,18 +323,6 @@ 0 0 0 - ..\..\..\libcpu\arm\common\backtrace.c - backtrace.c - 0 - 0 - - - 2 - 10 - 1 - 0 - 0 - 0 ..\..\..\libcpu\arm\common\div0.c div0.c 0 @@ -342,7 +330,7 @@ 2 - 11 + 10 1 0 0 @@ -354,7 +342,7 @@ 2 - 12 + 11 2 0 0 @@ -366,7 +354,7 @@ 2 - 13 + 12 1 0 0 @@ -384,6 +372,18 @@ 0 0 0 + + 3 + 13 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\core\device.c + device.c + 0 + 0 + 3 14 @@ -487,30 +487,6 @@ 0 0 0 - ..\..\..\components\drivers\pm\lptimer.c - lptimer.c - 0 - 0 - - - 3 - 23 - 1 - 0 - 0 - 0 - ..\..\..\components\drivers\pm\pm.c - pm.c - 0 - 0 - - - 3 - 24 - 1 - 0 - 0 - 0 ..\..\..\components\drivers\serial\serial_v2.c serial_v2.c 0 @@ -520,13 +496,13 @@ Drivers - 1 + 0 0 0 0 4 - 25 + 23 1 0 0 @@ -538,7 +514,7 @@ 4 - 26 + 24 1 0 0 @@ -550,7 +526,7 @@ 4 - 27 + 25 1 0 0 @@ -563,67 +539,91 @@ - Finsh + Filesystem 0 0 0 0 5 - 28 + 26 1 0 0 0 - ..\..\..\components\finsh\shell.c - shell.c + ..\..\..\components\dfs\dfs_v1\src\dfs_posix.c + dfs_posix.c 0 0 5 - 29 + 27 1 0 0 0 - ..\..\..\components\finsh\msh.c - msh.c + ..\..\..\components\dfs\dfs_v1\src\dfs_fs.c + dfs_fs.c 0 0 5 - 30 + 28 1 0 0 0 - ..\..\..\components\finsh\msh_parse.c - msh_parse.c + ..\..\..\components\dfs\dfs_v1\src\dfs.c + dfs.c 0 0 5 - 31 + 29 1 0 0 0 - ..\..\..\components\finsh\cmd.c - cmd.c + ..\..\..\components\dfs\dfs_v1\src\dfs_file.c + dfs_file.c 0 0 - Kernel + Finsh 0 0 0 0 + + 6 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + 6 32 @@ -631,8 +631,8 @@ 0 0 0 - ..\..\..\src\clock.c - clock.c + ..\..\..\components\finsh\msh.c + msh.c 0 0 @@ -643,8 +643,8 @@ 0 0 0 - ..\..\..\src\components.c - components.c + ..\..\..\components\finsh\msh_file.c + msh_file.c 0 0 @@ -655,26 +655,58 @@ 0 0 0 - ..\..\..\src\device.c - device.c + ..\..\..\components\finsh\msh_parse.c + msh_parse.c 0 0 + + + + Kernel + 0 + 0 + 0 + 0 - 6 + 7 35 1 0 0 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 7 + 36 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 7 + 37 + 1 + 0 + 0 + 0 ..\..\..\src\idle.c idle.c 0 0 - 6 - 36 + 7 + 38 1 0 0 @@ -685,8 +717,8 @@ 0 - 6 - 37 + 7 + 39 1 0 0 @@ -697,8 +729,8 @@ 0 - 6 - 38 + 7 + 40 1 0 0 @@ -709,8 +741,8 @@ 0 - 6 - 39 + 7 + 41 1 0 0 @@ -721,8 +753,20 @@ 0 - 6 - 40 + 7 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\mempool.c + mempool.c + 0 + 0 + + + 7 + 43 1 0 0 @@ -733,20 +777,20 @@ 0 - 6 - 41 + 7 + 44 1 0 0 0 - ..\..\..\src\scheduler.c - scheduler.c + ..\..\..\src\scheduler_up.c + scheduler_up.c 0 0 - 6 - 42 + 7 + 45 1 0 0 @@ -757,8 +801,8 @@ 0 - 6 - 43 + 7 + 46 1 0 0 @@ -777,8 +821,8 @@ 0 0 - 7 - 44 + 8 + 47 1 0 0 diff --git a/bsp/renesas/ra2l1-cpk/project.uvprojx b/bsp/renesas/ra2l1-cpk/project.uvprojx index 0b1399110d8..56c05798a3e 100644 --- a/bsp/renesas/ra2l1-cpk/project.uvprojx +++ b/bsp/renesas/ra2l1-cpk/project.uvprojx @@ -10,13 +10,13 @@ Target 1 0x4 ARM-ADS - 6160000::V6.16::ARMCLANG + 6190000::V6.19::ARMCLANG 1 R7FA2L1AB2DFM Renesas - Renesas.RA_DFP.3.1.0 + Renesas.RA_DFP.3.6.0 https://www2.renesas.eu/Keil_MDK_Packs/ CPUTYPE("Cortex-M23") CLOCK(12000000) ELITTLE @@ -186,6 +186,7 @@ 0 0 0 + 0 0 0 0 @@ -337,9 +338,9 @@ 0 -Wno-license-management -Wunused -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal - RT_USING_LIBC, __RTTHREAD__, __STDC_LIMIT_MACROS, RT_USING_ARM_LIBC, __CLK_TCK=RT_TICK_PER_SECOND + RT_USING_LIBC, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC, __RTTHREAD__ - ..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m23;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board;board\ports;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\finsh;.;..\..\..\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\ipc;ra_cfg\fsp_cfg;ra_cfg\fsp_cfg\bsp + ..\..\..\components\libc\posix\io\stdio;..\..\..\components\dfs\dfs_v1\include;ra_cfg\fsp_cfg;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include;..\..\..\components\finsh;..\libraries\HAL_Drivers\config;..\..\..\components\libc\posix\ipc;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;.;board\ports;ra_cfg\fsp_cfg\bsp;..\libraries\HAL_Drivers;..\..\..\libcpu\arm\cortex-m23;board;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\include;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal @@ -428,11 +429,6 @@ CPU - - backtrace.c - 1 - ..\..\..\libcpu\arm\common\backtrace.c - div0.c 1 @@ -458,6 +454,11 @@ DeviceDrivers + + device.c + 1 + ..\..\..\components\drivers\core\device.c + completion.c 1 @@ -498,16 +499,6 @@ 1 ..\..\..\components\drivers\misc\pin.c - - lptimer.c - 1 - ..\..\..\components\drivers\pm\lptimer.c - - - pm.c - 1 - ..\..\..\components\drivers\pm\pm.c - serial_v2.c 1 @@ -688,6 +679,31 @@ + + Filesystem + + + dfs_posix.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs_posix.c + + + dfs_fs.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs_fs.c + + + dfs.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs.c + + + dfs_file.c + 1 + ..\..\..\components\dfs\dfs_v1\src\dfs_file.c + + + Finsh @@ -696,20 +712,25 @@ 1 ..\..\..\components\finsh\shell.c + + cmd.c + 1 + ..\..\..\components\finsh\cmd.c + msh.c 1 ..\..\..\components\finsh\msh.c - msh_parse.c + msh_file.c 1 - ..\..\..\components\finsh\msh_parse.c + ..\..\..\components\finsh\msh_file.c - cmd.c + msh_parse.c 1 - ..\..\..\components\finsh\cmd.c + ..\..\..\components\finsh\msh_parse.c @@ -726,11 +747,6 @@ 1 ..\..\..\src\components.c - - device.c - 1 - ..\..\..\src\device.c - idle.c 1 @@ -756,15 +772,20 @@ 1 ..\..\..\src\mem.c + + mempool.c + 1 + ..\..\..\src\mempool.c + object.c 1 ..\..\..\src\object.c - scheduler.c + scheduler_up.c 1 - ..\..\..\src\scheduler.c + ..\..\..\src\scheduler_up.c thread.c @@ -806,7 +827,7 @@ - + diff --git a/bsp/renesas/ra2l1-cpk/rtconfig.h b/bsp/renesas/ra2l1-cpk/rtconfig.h index 0e69af83964..52015dbf7a0 100644 --- a/bsp/renesas/ra2l1-cpk/rtconfig.h +++ b/bsp/renesas/ra2l1-cpk/rtconfig.h @@ -24,7 +24,10 @@ /* kservice optimization */ #define RT_KSERVICE_USING_STDLIB -#define RT_DEBUG +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ diff --git a/bsp/renesas/ra2l1-cpk/rtconfig.py b/bsp/renesas/ra2l1-cpk/rtconfig.py index 3ce1475bc36..95209a27068 100644 --- a/bsp/renesas/ra2l1-cpk/rtconfig.py +++ b/bsp/renesas/ra2l1-cpk/rtconfig.py @@ -56,6 +56,7 @@ AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -Os' + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/renesas/ra4m2-eco/.config b/bsp/renesas/ra4m2-eco/.config index fbed3c5fd2f..370ab41f50b 100644 --- a/bsp/renesas/ra4m2-eco/.config +++ b/bsp/renesas/ra4m2-eco/.config @@ -9,6 +9,7 @@ CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=8 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -33,18 +34,10 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set # CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y # # Inter-Thread communication @@ -54,12 +47,12 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 # CONFIG_RT_USING_MEMPOOL is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set @@ -83,7 +76,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart4" -CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set # CONFIG_RT_USING_CACHE is not set CONFIG_RT_USING_HW_ATOMIC=y @@ -117,19 +110,26 @@ CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# CONFIG_RT_USING_DFS=y CONFIG_DFS_USING_POSIX=y CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set CONFIG_DFS_FILESYSTEMS_MAX=4 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -CONFIG_DFS_FD_MAX=16 -# CONFIG_RT_USING_DFS_MNTTABLE is not set # CONFIG_RT_USING_DFS_ELMFAT is not set CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set # CONFIG_RT_USING_DFS_RAMFS is not set # CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set # CONFIG_RT_USING_FAL is not set # @@ -228,9 +228,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set # # RT-Thread Utestcases @@ -255,7 +257,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set @@ -456,6 +457,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_HASH_MATCH is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set # # system packages @@ -527,6 +529,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set # CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set # # peripheral libraries and drivers @@ -611,6 +614,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_FT5426 is not set # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -623,7 +627,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set # # Kendryte SDK @@ -681,14 +684,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # # AI packages @@ -707,7 +713,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # Signal Processing and Control Algorithm Packages # # CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set # # miscellaneous packages @@ -754,7 +763,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set @@ -779,8 +787,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set @@ -927,14 +936,19 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set # # Timing # # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # # Data Processing @@ -1023,10 +1037,14 @@ CONFIG_BSP_USING_UART4=y CONFIG_BSP_UART4_RX_BUFSIZE=256 CONFIG_BSP_UART4_TX_BUFSIZE=0 # CONFIG_BSP_USING_UART9 is not set -CONFIG_BSP_USING_SPI=y -# CONFIG_BSP_USING_SPI0 is not set -# CONFIG_BSP_USING_SPI1 is not set -# CONFIG_BSP_USING_SCI_SPI is not set +# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_SCI_SPI=y +# CONFIG_BSP_USING_SCI_SPI0 is not set +# CONFIG_BSP_USING_SCI_SPI1 is not set +# CONFIG_BSP_USING_SCI_SPI2 is not set +# CONFIG_BSP_USING_SCI_SPI3 is not set +# CONFIG_BSP_USING_SCI_SPI4 is not set +CONFIG_BSP_USING_SCI_SPI9=y # # Board extended module Drivers diff --git a/bsp/renesas/ra4m2-eco/SConscript b/bsp/renesas/ra4m2-eco/SConscript index aee8a3bb36d..0f2e5f740a5 100644 --- a/bsp/renesas/ra4m2-eco/SConscript +++ b/bsp/renesas/ra4m2-eco/SConscript @@ -16,6 +16,7 @@ elif rtconfig.PLATFORM in ['gcc', 'armclang']: if GetOption('target') != 'mdk5': CPPPATH = [cwd] src = Glob('./src/*.c') + src += Glob('./src/*.cpp') group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) diff --git a/bsp/renesas/ra4m2-eco/SConstruct b/bsp/renesas/ra4m2-eco/SConstruct index d00d0dbeaac..67511e3048a 100644 --- a/bsp/renesas/ra4m2-eco/SConstruct +++ b/bsp/renesas/ra4m2-eco/SConstruct @@ -21,6 +21,7 @@ DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/bsp/renesas/ra4m2-eco/project.uvoptx b/bsp/renesas/ra4m2-eco/project.uvoptx index 73b0827c8e4..da1969e7742 100644 --- a/bsp/renesas/ra4m2-eco/project.uvoptx +++ b/bsp/renesas/ra4m2-eco/project.uvoptx @@ -77,7 +77,7 @@ 0 1 - 0 + 255 0 1 @@ -170,28 +170,688 @@ - Source Group 1 + Compiler 0 0 0 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdio.c + cstdio.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + - :Renesas RA Smart Configurator:Common Sources - 1 + CPU + 0 0 0 0 2 - 1 + 9 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\atomic_arm.c + atomic_arm.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 12 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\core\device.c + device.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion.c + completion.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial_v2.c + serial_v2.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_core.c + spi_core.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_dev.c + spi_dev.c + 0 + 0 + + + 3 + 26 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_msd.c + spi_msd.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 27 1 0 0 0 - .\src\hal_entry.c - hal_entry.c + ..\libraries\HAL_Drivers\drv_common.c + drv_common.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 29 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_sci_spi.c + drv_sci_spi.c + 0 + 0 + + + 4 + 30 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_usart_v2.c + drv_usart_v2.c + 0 + 0 + + + + + Filesystem + 0 + 0 + 0 + 0 + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c + devfs.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\src\dfs.c + dfs.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\src\dfs_file.c + dfs_file.c + 0 + 0 + + + 5 + 34 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\src\dfs_fs.c + dfs_fs.c + 0 + 0 + + + 5 + 35 + 1 + 0 + 0 + 0 + ..\..\..\components\dfs\dfs_v1\src\dfs_posix.c + dfs_posix.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_file.c + msh_file.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 7 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 7 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 7 + 43 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 7 + 44 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 7 + 45 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 7 + 46 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 7 + 47 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 7 + 48 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 7 + 49 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler_up.c + scheduler_up.c + 0 + 0 + + + 7 + 50 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 7 + 51 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + :Renesas RA Smart Configurator:Common Sources + 0 + 0 + 0 + 0 + + 8 + 52 + 8 + 0 + 0 + 0 + .\src\hal_entry.cpp + hal_entry.cpp 0 0 diff --git a/bsp/renesas/ra4m2-eco/project.uvprojx b/bsp/renesas/ra4m2-eco/project.uvprojx index dc9a2b49a0b..206d6ab32c5 100644 --- a/bsp/renesas/ra4m2-eco/project.uvprojx +++ b/bsp/renesas/ra4m2-eco/project.uvprojx @@ -1,42 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ Target 1 0x4 ARM-ADS + 6190000::V6.19::ARMCLANG 1 R7FA4M2AD Renesas - Renesas.RA_DFP.4.1.0 + Renesas.RA_DFP.4.4.0 https://www2.renesas.eu/Keil_MDK_Packs/ IRAM(0x20000000,0x020000) IROM(0x00000000,0x080000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE - - + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC2000 -FN3 -FF0RA4M2_512K -FS00 -FL080000 -FF1RA4M2_DATA_C512K -FS18000000 -FL12000 -FF2RA4M2_CONF -FS2100A000 -FL2300 -FP0($$Device:R7FA4M2AD$Flash\RA4M2_512K.FLM) -FP1($$Device:R7FA4M2AD$Flash\RA4M2_DATA_C512K.FLM) -FP2($$Device:R7FA4M2AD$Flash\RA4M2_CONF.FLM)) 0 - - - - - - - - - - + + + + + + + + + + $$Device:R7FA4M2AD$SVD\R7FA4M2AD.svd 0 0 - - - - - + + + + + 0 0 @@ -58,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -68,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -79,14 +83,14 @@ 0 0 cmd /c "start "Renesas" /w cmd /c ""$Slauncher\rasc_launcher.bat" "3.5.0" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2> "%%TEMP%%\rasc_stderr.out""" - + 0 0 2 0 0 - + 0 @@ -100,15 +104,15 @@ 0 0 3 - - + + 1 - - - - + + + + SARMV8M.DLL -MPU TCM.DLL @@ -134,11 +138,11 @@ 1 BIN\UL2V8M.DLL - - - - - + + + + + 0 @@ -171,7 +175,7 @@ 0 0 "Cortex-M33" - + 0 0 0 @@ -306,7 +310,7 @@ 0x0 - + 1 @@ -334,9 +338,9 @@ 0 -Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal - RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - - ..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\include;board\ports;..\..\..\components\drivers\include;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\dfs\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\spi;.;..\..\..\components\libc\posix\io\stdio + RT_USING_LIBC, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC + + ..\..\..\components\drivers\spi;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\posix\io\stdio;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\include;..\..\..\components\libc\compilers\common\extension;..\..\..\libcpu\arm\common;..\libraries\HAL_Drivers;board\ports;..\..\..\components\finsh;..\libraries\HAL_Drivers\config;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;board;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\dfs\dfs_v1\filesystems\devfs;..\..\..\components\dfs\dfs_v1\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;. @@ -351,10 +355,10 @@ 0 4 - - - - + + + + @@ -364,14 +368,14 @@ 0 0 0 - - - + + + .\script\fsp.scat - - - - + + + + 6319,6314 @@ -385,50 +389,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdio.c 1 ..\..\..\components\libc\compilers\common\cstdio.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cwchar.c 1 @@ -444,29 +434,21 @@ 1 ..\..\..\libcpu\arm\common\atomic_arm.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - - cpuport.c 1 @@ -477,83 +459,66 @@ DeviceDrivers + + device.c + 1 + ..\..\..\components\drivers\core\device.c + completion.c 1 ..\..\..\components\drivers\ipc\completion.c - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c - - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - serial_v2.c 1 ..\..\..\components\drivers\serial\serial_v2.c - - spi_core.c 1 ..\..\..\components\drivers\spi\spi_core.c - - spi_dev.c 1 ..\..\..\components\drivers\spi\spi_dev.c - - spi_msd.c 1 @@ -569,70 +534,220 @@ 1 ..\libraries\HAL_Drivers\drv_common.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 -std=c99 - + - - drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 -std=c99 - + - - - drv_spi.c + drv_sci_spi.c 1 - ..\libraries\HAL_Drivers\drv_spi.c + ..\libraries\HAL_Drivers\drv_sci_spi.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 -std=c99 - + - - drv_usart_v2.c 1 ..\libraries\HAL_Drivers\drv_usart_v2.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 -std=c99 - + @@ -646,35 +761,27 @@ devfs.c 1 - ..\..\..\components\dfs\filesystems\devfs\devfs.c + ..\..\..\components\dfs\dfs_v1\filesystems\devfs\devfs.c - - dfs.c 1 - ..\..\..\components\dfs\src\dfs.c + ..\..\..\components\dfs\dfs_v1\src\dfs.c - - dfs_file.c 1 - ..\..\..\components\dfs\src\dfs_file.c + ..\..\..\components\dfs\dfs_v1\src\dfs_file.c - - dfs_fs.c 1 - ..\..\..\components\dfs\src\dfs_fs.c + ..\..\..\components\dfs\dfs_v1\src\dfs_fs.c - - dfs_posix.c 1 - ..\..\..\components\dfs\src\dfs_posix.c + ..\..\..\components\dfs\dfs_v1\src\dfs_posix.c @@ -686,35 +793,27 @@ 1 ..\..\..\components\finsh\shell.c - - + + msh_file.c + 1 + ..\..\..\components\finsh\msh_file.c + msh.c 1 ..\..\..\components\finsh\msh.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - cmd.c 1 ..\..\..\components\finsh\cmd.c - - - msh_file.c - 1 - ..\..\..\components\finsh\msh_file.c - - Kernel @@ -724,78 +823,51 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - object.c 1 ..\..\..\src\object.c - - scheduler_up.c 1 ..\..\..\src\scheduler_up.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -803,26 +875,41 @@ + + :Renesas RA Smart Configurator:Common Sources + + + hal_entry.cpp + 8 + .\src\hal_entry.cpp + + + + + ::Flex Software + + - + - + - + - + - + + diff --git a/bsp/renesas/ra4m2-eco/rtconfig.h b/bsp/renesas/ra4m2-eco/rtconfig.h index cff3ec5b2fa..01e3b6c383b 100644 --- a/bsp/renesas/ra4m2-eco/rtconfig.h +++ b/bsp/renesas/ra4m2-eco/rtconfig.h @@ -23,8 +23,10 @@ /* kservice optimization */ -#define RT_DEBUG -#define RT_DEBUG_COLOR +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ @@ -36,7 +38,6 @@ /* Memory Management */ -#define RT_PAGE_MAX_ORDER 11 #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP @@ -47,7 +48,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart4" -#define RT_VER_NUM 0x50000 +#define RT_VER_NUM 0x50001 #define RT_USING_HW_ATOMIC #define RT_USING_CPU_FFS #define ARCH_ARM @@ -73,12 +74,16 @@ #define MSH_USING_BUILT_IN_COMMANDS #define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + #define RT_USING_DFS #define DFS_USING_POSIX #define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 #define DFS_FILESYSTEMS_MAX 4 #define DFS_FILESYSTEM_TYPES_MAX 4 -#define DFS_FD_MAX 16 #define RT_USING_DFS_DEVFS /* Device Drivers */ @@ -199,7 +204,7 @@ /* Arduino libraries */ -/* Projects */ +/* Projects and Demos */ /* Sensors */ @@ -249,7 +254,8 @@ #define BSP_USING_UART4 #define BSP_UART4_RX_BUFSIZE 256 #define BSP_UART4_TX_BUFSIZE 0 -#define BSP_USING_SPI +#define BSP_USING_SCI_SPI +#define BSP_USING_SCI_SPI9 /* Board extended module Drivers */ diff --git a/bsp/renesas/ra4m2-eco/rtconfig.py b/bsp/renesas/ra4m2-eco/rtconfig.py index f03ce7604dd..f1952b0d522 100644 --- a/bsp/renesas/ra4m2-eco/rtconfig.py +++ b/bsp/renesas/ra4m2-eco/rtconfig.py @@ -57,6 +57,8 @@ else: CFLAGS += ' -Os' + CXXFLAGS = CFLAGS + POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/renesas/ra4m2-eco/src/hal_entry.c b/bsp/renesas/ra4m2-eco/src/hal_entry.cpp similarity index 100% rename from bsp/renesas/ra4m2-eco/src/hal_entry.c rename to bsp/renesas/ra4m2-eco/src/hal_entry.cpp diff --git a/bsp/renesas/ra6m3-ek/.config b/bsp/renesas/ra6m3-ek/.config index cab83169375..5621a829c22 100644 --- a/bsp/renesas/ra6m3-ek/.config +++ b/bsp/renesas/ra6m3-ek/.config @@ -34,9 +34,10 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set # CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y # # Inter-Thread communication @@ -210,6 +211,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set # # RT-Thread Utestcases diff --git a/bsp/renesas/ra6m3-ek/SConstruct b/bsp/renesas/ra6m3-ek/SConstruct index d00d0dbeaac..67511e3048a 100644 --- a/bsp/renesas/ra6m3-ek/SConstruct +++ b/bsp/renesas/ra6m3-ek/SConstruct @@ -21,6 +21,7 @@ DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/bsp/renesas/ra6m3-ek/project.uvoptx b/bsp/renesas/ra6m3-ek/project.uvoptx index e748ab817ac..9a085ce0b06 100644 --- a/bsp/renesas/ra6m3-ek/project.uvoptx +++ b/bsp/renesas/ra6m3-ek/project.uvoptx @@ -531,8 +531,8 @@ 0 0 0 - ..\..\..\components\finsh\shell.c - shell.c + ..\..\..\components\finsh\msh_parse.c + msh_parse.c 0 0 @@ -555,8 +555,8 @@ 0 0 0 - ..\..\..\components\finsh\msh_parse.c - msh_parse.c + ..\..\..\components\finsh\cmd.c + cmd.c 0 0 @@ -567,8 +567,8 @@ 0 0 0 - ..\..\..\components\finsh\cmd.c - cmd.c + ..\..\..\components\finsh\shell.c + shell.c 0 0 diff --git a/bsp/renesas/ra6m3-ek/project.uvprojx b/bsp/renesas/ra6m3-ek/project.uvprojx index 0cec09bcb45..4b3e657100a 100644 --- a/bsp/renesas/ra6m3-ek/project.uvprojx +++ b/bsp/renesas/ra6m3-ek/project.uvprojx @@ -10,13 +10,13 @@ Target 1 0x4 ARM-ADS - 6160000::V6.16::ARMCLANG + 6190000::V6.19::ARMCLANG 1 R7FA6M3AH Renesas - Renesas.RA_DFP.4.2.0 + Renesas.RA_DFP.4.4.0 https://www2.renesas.eu/Keil_MDK_Packs/ IRAM(0x1FFE0000,0x020000) IRAM2(0x20000000,0x080000) IROM(0x00000000,0x200000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE @@ -186,6 +186,7 @@ 2 0 0 + 0 1 0 8 @@ -337,9 +338,9 @@ 0 -Wno-license-management -Wunused -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal - RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + __RTTHREAD__, RT_USING_LIBC, __STDC_LIMIT_MACROS, RT_USING_ARMLIBC, __CLK_TCK=RT_TICK_PER_SECOND - ..\..\..\include;board;.;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\stdio;..\..\..\components\finsh;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\..\..\components\libc\posix\ipc;..\libraries\HAL_Drivers;board\ports;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m4;packages\ili9341-latest;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\include + ..\libraries\HAL_Drivers;..\..\..\components\drivers\include;board;..\..\..\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;..\libraries\HAL_Drivers\config;..\..\..\components\drivers\include;..\..\..\components\finsh;board\ports;.;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\poll @@ -534,9 +535,9 @@ Finsh - shell.c + msh_parse.c 1 - ..\..\..\components\finsh\shell.c + ..\..\..\components\finsh\msh_parse.c msh.c @@ -544,14 +545,14 @@ ..\..\..\components\finsh\msh.c - msh_parse.c + cmd.c 1 - ..\..\..\components\finsh\msh_parse.c + ..\..\..\components\finsh\cmd.c - cmd.c + shell.c 1 - ..\..\..\components\finsh\cmd.c + ..\..\..\components\finsh\shell.c @@ -643,7 +644,7 @@ - + diff --git a/bsp/renesas/ra6m3-ek/rtconfig.h b/bsp/renesas/ra6m3-ek/rtconfig.h index fe1ef2f7cd2..274016b31c4 100644 --- a/bsp/renesas/ra6m3-ek/rtconfig.h +++ b/bsp/renesas/ra6m3-ek/rtconfig.h @@ -23,8 +23,10 @@ /* kservice optimization */ -#define RT_DEBUG -#define RT_DEBUG_COLOR +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ diff --git a/bsp/renesas/ra6m3-ek/rtconfig.py b/bsp/renesas/ra6m3-ek/rtconfig.py index f7024ac808f..b30bf918ac3 100644 --- a/bsp/renesas/ra6m3-ek/rtconfig.py +++ b/bsp/renesas/ra6m3-ek/rtconfig.py @@ -4,7 +4,7 @@ # toolchains options ARCH='arm' CPU='cortex-m4' -CROSS_TOOL='keil' +CROSS_TOOL='gcc' if os.getenv('RTT_CC'): CROSS_TOOL = os.getenv('RTT_CC') @@ -56,6 +56,7 @@ AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -Os' + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/renesas/ra6m3-hmi-board/.config b/bsp/renesas/ra6m3-hmi-board/.config index c69cf35b0f4..d41898ccbb4 100644 --- a/bsp/renesas/ra6m3-hmi-board/.config +++ b/bsp/renesas/ra6m3-hmi-board/.config @@ -34,9 +34,10 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set # CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y # # Inter-Thread communication @@ -210,6 +211,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set # # RT-Thread Utestcases diff --git a/bsp/renesas/ra6m3-hmi-board/SConstruct b/bsp/renesas/ra6m3-hmi-board/SConstruct index d00d0dbeaac..67511e3048a 100644 --- a/bsp/renesas/ra6m3-hmi-board/SConstruct +++ b/bsp/renesas/ra6m3-hmi-board/SConstruct @@ -21,6 +21,7 @@ DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/bsp/renesas/ra6m3-hmi-board/project.uvoptx b/bsp/renesas/ra6m3-hmi-board/project.uvoptx index fb1ba3e861a..0c1e60e73fd 100644 --- a/bsp/renesas/ra6m3-hmi-board/project.uvoptx +++ b/bsp/renesas/ra6m3-hmi-board/project.uvoptx @@ -548,8 +548,8 @@ 0 0 0 - ..\..\..\components\finsh\shell.c - shell.c + ..\..\..\components\finsh\msh.c + msh.c 0 0 @@ -560,8 +560,8 @@ 0 0 0 - ..\..\..\components\finsh\msh.c - msh.c + ..\..\..\components\finsh\cmd.c + cmd.c 0 0 @@ -584,8 +584,8 @@ 0 0 0 - ..\..\..\components\finsh\cmd.c - cmd.c + ..\..\..\components\finsh\shell.c + shell.c 0 0 diff --git a/bsp/renesas/ra6m3-hmi-board/project.uvprojx b/bsp/renesas/ra6m3-hmi-board/project.uvprojx index 939ba09b32b..9c0f8779407 100644 --- a/bsp/renesas/ra6m3-hmi-board/project.uvprojx +++ b/bsp/renesas/ra6m3-hmi-board/project.uvprojx @@ -10,13 +10,13 @@ Target 1 0x4 ARM-ADS - 6160000::V6.16::ARMCLANG + 6190000::V6.19::ARMCLANG 1 R7FA6M3AH Renesas - Renesas.RA_DFP.4.2.0 + Renesas.RA_DFP.4.4.0 https://www2.renesas.eu/Keil_MDK_Packs/ IRAM(0x1FFE0000,0x020000) IRAM2(0x20000000,0x080000) IROM(0x00000000,0x200000) CPUTYPE("Cortex-M4") FPU2 DSP CLOCK(12000000) ELITTLE @@ -186,6 +186,7 @@ 2 0 0 + 0 1 0 8 @@ -337,9 +338,9 @@ 0 -Wno-license-management -Wunused -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal - RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND + __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, RT_USING_LIBC, __RTTHREAD__ - ..\..\..\include;..\..\..\components\finsh;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\posix\io\stdio;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\libcpu\arm\common;.;board\ports;board;..\libraries\HAL_Drivers;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\include;board\ports\wifi;..\..\..\components\drivers\include + ..\..\..\components\drivers\include;board\ports\wifi;..\..\..\libcpu\arm\common;..\..\..\include;..\..\..\components\libc\posix\io\poll;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\stdio;..\..\..\components\drivers\include;..\..\..\libcpu\arm\cortex-m4;..\..\..\components\finsh;..\..\..\components\libc\posix\ipc;..\libraries\HAL_Drivers;board;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers\config;.;board\ports;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\libc\compilers\common\extension @@ -743,14 +744,14 @@ Finsh - shell.c + msh.c 1 - ..\..\..\components\finsh\shell.c + ..\..\..\components\finsh\msh.c - msh.c + cmd.c 1 - ..\..\..\components\finsh\msh.c + ..\..\..\components\finsh\cmd.c msh_parse.c @@ -758,9 +759,9 @@ ..\..\..\components\finsh\msh_parse.c - cmd.c + shell.c 1 - ..\..\..\components\finsh\cmd.c + ..\..\..\components\finsh\shell.c @@ -852,7 +853,7 @@ - + @@ -861,13 +862,4 @@ - - - - project - 1 - - - - diff --git a/bsp/renesas/ra6m3-hmi-board/rtconfig.h b/bsp/renesas/ra6m3-hmi-board/rtconfig.h index b275391261b..570d8afddfd 100644 --- a/bsp/renesas/ra6m3-hmi-board/rtconfig.h +++ b/bsp/renesas/ra6m3-hmi-board/rtconfig.h @@ -23,8 +23,10 @@ /* kservice optimization */ -#define RT_DEBUG -#define RT_DEBUG_COLOR +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ diff --git a/bsp/renesas/ra6m3-hmi-board/rtconfig.py b/bsp/renesas/ra6m3-hmi-board/rtconfig.py index 9d944a9b20d..97abe4c4b9c 100644 --- a/bsp/renesas/ra6m3-hmi-board/rtconfig.py +++ b/bsp/renesas/ra6m3-hmi-board/rtconfig.py @@ -59,6 +59,7 @@ AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -Os' + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/renesas/ra6m4-cpk/.config b/bsp/renesas/ra6m4-cpk/.config index dd491e5dcca..19bd0c2a801 100644 --- a/bsp/renesas/ra6m4-cpk/.config +++ b/bsp/renesas/ra6m4-cpk/.config @@ -9,6 +9,7 @@ CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=8 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -33,18 +34,10 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set # CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y # # Inter-Thread communication @@ -54,12 +47,12 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 # CONFIG_RT_USING_MEMPOOL is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set @@ -83,7 +76,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart7" -CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set # CONFIG_RT_USING_CACHE is not set CONFIG_RT_USING_HW_ATOMIC=y @@ -117,6 +110,10 @@ CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# # CONFIG_RT_USING_DFS is not set # CONFIG_RT_USING_FAL is not set @@ -148,7 +145,13 @@ CONFIG_RT_USING_PIN=y # CONFIG_RT_USING_FDT is not set # CONFIG_RT_USING_RTC is not set # CONFIG_RT_USING_SDIO is not set -# CONFIG_RT_USING_SPI is not set +CONFIG_RT_USING_SPI=y +# CONFIG_RT_USING_SPI_BITOPS is not set +# CONFIG_RT_USING_QSPI is not set +# CONFIG_RT_USING_SPI_MSD is not set +# CONFIG_RT_USING_SFUD is not set +# CONFIG_RT_USING_ENC28J60 is not set +# CONFIG_RT_USING_SPI_WIFI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_SENSOR is not set @@ -210,9 +213,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set # # RT-Thread Utestcases @@ -237,7 +242,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set @@ -438,6 +442,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_HASH_MATCH is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set # # system packages @@ -509,6 +514,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set # CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set # # peripheral libraries and drivers @@ -593,6 +599,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_FT5426 is not set # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -605,7 +612,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set # # Kendryte SDK @@ -663,14 +669,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # # AI packages @@ -689,7 +698,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # Signal Processing and Control Algorithm Packages # # CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set # # miscellaneous packages @@ -736,7 +748,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set @@ -761,8 +772,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set @@ -909,14 +921,19 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set # # Timing # # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # # Data Processing @@ -1008,7 +1025,9 @@ CONFIG_BSP_UART7_TX_BUFSIZE=0 # CONFIG_BSP_USING_UART9 is not set # CONFIG_BSP_USING_I2C is not set # CONFIG_BSP_USING_SCI_SPI is not set -# CONFIG_BSP_USING_SPI is not set +CONFIG_BSP_USING_SPI=y +CONFIG_BSP_USING_SPI0=y +# CONFIG_BSP_USING_SPI1 is not set # CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_DAC is not set # CONFIG_BSP_USING_PWM is not set diff --git a/bsp/renesas/ra6m4-cpk/.settings/standalone.prefs b/bsp/renesas/ra6m4-cpk/.settings/standalone.prefs index c1826f515d8..7b5785859e1 100644 --- a/bsp/renesas/ra6m4-cpk/.settings/standalone.prefs +++ b/bsp/renesas/ra6m4-cpk/.settings/standalone.prefs @@ -1,20 +1,24 @@ -#Fri Jul 22 16:07:30 CST 2022 +#Mon Jul 24 15:57:07 CST 2023 com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_spi\#\#\#\#3.5.0/all=1610456547,ra/fsp/inc/api/r_transfer_api.h|2044432844,ra/fsp/inc/instances/r_spi.h|1108533607,ra/fsp/inc/api/r_spi_api.h|1854500045,ra/fsp/src/r_spi/r_spi.c +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|2425160085,ra/fsp/inc/api/bsp_api.h|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|2208590403,ra/fsp/inc/instances/r_ioport.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|3297195641,ra/fsp/inc/fsp_version.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|1728953905,ra/fsp/inc/fsp_features.h|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|546480625,ra/fsp/inc/fsp_common_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h +com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.201575186=false +com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/all=1906465970,ra/fsp/inc/api/r_external_irq_api.h|2545672180,ra/fsp/inc/instances/r_icu.h|3018483678,ra/fsp/src/r_icu/r_icu.c com.renesas.cdt.ddsc.content/com.renesas.cdt.ddsc.content.defaultlinkerscript=script/fsp.scat -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#Common\#\#all\#\#fsp_common\#\#\#\#3.5.0/all=3983299396,ra/fsp/src/bsp/mcu/all/bsp_delay.h|4222527282,ra/fsp/src/bsp/mcu/all/bsp_module_stop.h|1499520276,ra/fsp/src/bsp/mcu/all/bsp_group_irq.c|3984836408,ra/fsp/src/bsp/mcu/all/bsp_group_irq.h|546480625,ra/fsp/inc/fsp_common_api.h|3297195641,ra/fsp/inc/fsp_version.h|1615019982,ra/fsp/src/bsp/mcu/all/bsp_sbrk.c|3549961311,ra/fsp/src/bsp/mcu/all/bsp_tfu.h|2386285210,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/renesas.h|521902797,ra/fsp/src/bsp/mcu/all/bsp_security.h|1904866635,ra/fsp/src/bsp/mcu/all/bsp_clocks.h|1728953905,ra/fsp/inc/fsp_features.h|470601830,ra/fsp/src/bsp/mcu/all/bsp_clocks.c|2977689308,ra/fsp/src/bsp/mcu/all/bsp_mcu_api.h|3606266210,ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c|1353647784,ra/fsp/src/bsp/mcu/all/bsp_delay.c|568600546,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.c|400573940,ra/fsp/src/bsp/mcu/all/bsp_register_protection.h|3492513568,ra/fsp/src/bsp/mcu/all/bsp_register_protection.c|460577388,ra/fsp/src/bsp/mcu/all/bsp_io.h|1236602439,ra/fsp/src/bsp/mcu/all/bsp_io.c|2847966430,ra/fsp/src/bsp/mcu/all/bsp_security.c|1992062042,ra/fsp/src/bsp/mcu/all/bsp_compiler_support.h|2425160085,ra/fsp/inc/api/bsp_api.h|1939984091,ra/fsp/inc/api/r_ioport_api.h|2920829723,ra/fsp/src/bsp/mcu/all/bsp_guard.c|3753300083,ra/fsp/src/bsp/mcu/all/bsp_arm_exceptions.h|1552630912,ra/fsp/src/bsp/mcu/all/bsp_guard.h|3998046333,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/base_addresses.h|1630997354,ra/fsp/src/bsp/mcu/all/bsp_irq.c|2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h|2906400,ra/fsp/src/bsp/mcu/all/bsp_common.c|731782070,ra/fsp/src/bsp/mcu/all/bsp_irq.h|2208590403,ra/fsp/inc/instances/r_ioport.h|3255765648,ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.c|4051445857,ra/fsp/src/bsp/mcu/all/bsp_common.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.5.0/all=2308894280,ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/system.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#device\#\#\#\#3.5.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/libraries= com.renesas.cdt.ddsc.settingseditor/com.renesas.cdt.ddsc.settingseditor.active_page=SWPConfigurator -com.renesas.cdt.ddsc.threads.configurator/collapse/module.driver.uart_on_sci_uart.201575186=false -com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/all=1044777225,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armcc.h|1577199483,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_iccarm.h|1372010515,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm23.h|3007265674,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mbl.h|2701379970,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv8.h|1494441116,ra/arm/CMSIS_5/CMSIS/Core/Include/mpu_armv7.h|1441545198,ra/arm/CMSIS_5/LICENSE.txt|3898569239,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang.h|3911746910,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_armclang_ltm.h|2635219934,ra/arm/CMSIS_5/CMSIS/Core/Include/tz_context.h|3552689244,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv81mml.h|2333906976,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_version.h|2381390623,ra/arm/CMSIS_5/CMSIS/Core/Include/core_armv8mml.h|3163610011,ra/arm/CMSIS_5/CMSIS/Core/Include/pmu_armv8.h|2327633156,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc000.h|4290386133,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0plus.h|2718020009,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm33.h|1168186370,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm55.h|1564341101,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm7.h|304461792,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm3.h|3358993753,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm4.h|302860276,ra/arm/CMSIS_5/CMSIS/Core/Include/cachel1_armv7.h|1745843273,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm0.h|2851112248,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm1.h|965562395,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_gcc.h|364344841,ra/arm/CMSIS_5/CMSIS/Core/Include/core_sc300.h|3127123217,ra/arm/CMSIS_5/CMSIS/Core/Include/core_cm35p.h|1017116116,ra/arm/CMSIS_5/CMSIS/Core/Include/cmsis_compiler.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.5.0/libraries= -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.5.0/all=3938710240,ra/board/ra6m4_cpk/board_leds.c|2967196421,ra/board/ra6m4_cpk/board_init.h|3343992478,ra/board/ra6m4_cpk/board.h|3559227370,ra/board/ra6m4_cpk/board_init.c|2525887392,ra/board/ra6m4_cpk/board_ethernet_phy.h|1768800601,ra/board/ra6m4_cpk/board_leds.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#3.5.0/all=3271601603,ra/fsp/inc/instances/r_dtc.h|356298762,ra/fsp/src/r_dtc/r_dtc.c|1610456547,ra/fsp/inc/api/r_transfer_api.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.5.0/all=ra/board/ra6m4_cpk/board_leds.c|ra/board/ra6m4_cpk/board_init.h|ra/board/ra6m4_cpk/board.h|ra/board/ra6m4_cpk/board_init.c|ra/board/ra6m4_cpk/board_ethernet_phy.h|ra/board/ra6m4_cpk/board_leds.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/libraries= -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.5.0/all=2347061782,ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h|3301568719,ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h|1009023542,ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c|2208590403,ra/fsp/inc/instances/r_ioport.h -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_icu\#\#\#\#3.5.0/all=1906465970,ra/fsp/inc/api/r_external_irq_api.h|2545672180,ra/fsp/inc/instances/r_icu.h|3018483678,ra/fsp/src/r_icu/r_icu.c -com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|1610456547,ra/fsp/inc/api/r_transfer_api.h|3916852077,ra/fsp/inc/api/r_uart_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_dtc\#\#\#\#3.5.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_spi\#\#\#\#3.5.0/libraries= +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#ra6m4\#\#fsp\#\#\#\#3.5.0/all=3301568719,ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h|2347061782,ra/fsp/src/bsp/mcu/ra6m4/bsp_mcu_info.h|1009023542,ra/fsp/src/bsp/mcu/ra6m4/bsp_elc.h +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/all=1939984091,ra/fsp/inc/api/r_ioport_api.h|2208590403,ra/fsp/inc/instances/r_ioport.h|3254285722,ra/fsp/src/r_ioport/r_ioport.c +com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_sci_uart\#\#\#\#3.5.0/all=3916852077,ra/fsp/inc/api/r_uart_api.h|3094200246,ra/fsp/src/r_sci_uart/r_sci_uart.c|1610456547,ra/fsp/inc/api/r_transfer_api.h|1889256766,ra/fsp/inc/instances/r_sci_uart.h com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#BSP\#\#Board\#\#ra6m4_cpk\#\#\#\#3.5.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Arm\#\#CMSIS\#\#CMSIS5\#\#CoreM\#\#\#\#5.8.0+renesas.0.fsp.3.5.0/libraries= com.renesas.cdt.ddsc.packs.componentfiles/Renesas\#\#HAL\ Drivers\#\#all\#\#r_ioport\#\#\#\#3.5.0/libraries= diff --git a/bsp/renesas/ra6m4-cpk/SConstruct b/bsp/renesas/ra6m4-cpk/SConstruct index d00d0dbeaac..67511e3048a 100644 --- a/bsp/renesas/ra6m4-cpk/SConstruct +++ b/bsp/renesas/ra6m4-cpk/SConstruct @@ -21,6 +21,7 @@ DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/bsp/renesas/ra6m4-cpk/buildinfo.gpdsc b/bsp/renesas/ra6m4-cpk/buildinfo.gpdsc index ed18fa25062..55635206a0a 100644 --- a/bsp/renesas/ra6m4-cpk/buildinfo.gpdsc +++ b/bsp/renesas/ra6m4-cpk/buildinfo.gpdsc @@ -74,55 +74,39 @@ - - - - - - - - - - - - - - - - diff --git a/bsp/renesas/ra6m4-cpk/project.uvoptx b/bsp/renesas/ra6m4-cpk/project.uvoptx index 853ddaf7327..b388c48d70e 100644 --- a/bsp/renesas/ra6m4-cpk/project.uvoptx +++ b/bsp/renesas/ra6m4-cpk/project.uvoptx @@ -89,7 +89,7 @@ 1 1 1 - 0 + 1 1 1 1 @@ -117,6 +117,11 @@ Segger\JL2CM3.dll + + 0 + UL2V8M + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC2000 -FN3 -FF0RA6M4_1M -FS00 -FL0100000 -FF1RA6M4_DATA_C1M -FS18000000 -FL12000 -FF2RA6M4_CONF -FS2100A000 -FL2300 -FP0($$Device:R7FA6M4AF$Flash\RA6M4_1M.FLM) -FP1($$Device:R7FA6M4AF$Flash\RA6M4_DATA_C1M.FLM) -FP2($$Device:R7FA6M4AF$Flash\RA6M4_CONF.FLM)) + 0 JL2CM3 @@ -170,7 +175,7 @@ - :Renesas RA Smart Configurator:Common Sources + Compiler 0 0 0 @@ -182,6 +187,582 @@ 0 0 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdio.c + cstdio.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + + + + + CPU + 0 + 0 + 0 + 0 + + 2 + 9 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\atomic_arm.c + atomic_arm.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 12 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\core\device.c + device.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion.c + completion.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial_v2.c + serial_v2.c + 0 + 0 + + + 3 + 24 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_core.c + spi_core.c + 0 + 0 + + + 3 + 25 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\spi\spi_dev.c + spi_dev.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 26 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_common.c + drv_common.c + 0 + 0 + + + 4 + 27 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 28 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_spi.c + drv_spi.c + 0 + 0 + + + 4 + 29 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_usart_v2.c + drv_usart_v2.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + 5 + 31 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 32 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 33 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 42 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler_up.c + scheduler_up.c + 0 + 0 + + + 6 + 43 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 44 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + :Renesas RA Smart Configurator:Common Sources + 0 + 0 + 0 + 0 + + 7 + 45 + 1 + 0 + 0 + 0 .\src\hal_entry.c hal_entry.c 0 diff --git a/bsp/renesas/ra6m4-cpk/project.uvprojx b/bsp/renesas/ra6m4-cpk/project.uvprojx index be1273af623..f41a7173cc9 100644 --- a/bsp/renesas/ra6m4-cpk/project.uvprojx +++ b/bsp/renesas/ra6m4-cpk/project.uvprojx @@ -1,43 +1,46 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ Target 1 0x4 ARM-ADS - 6160000::V6.16::ARMCLANG + 6190000::V6.19::ARMCLANG 1 - R7FA6M4AF3CFB + R7FA6M4AF Renesas - Renesas.RA_DFP.3.1.0 + Renesas.RA_DFP.4.4.0 https://www2.renesas.eu/Keil_MDK_Packs/ - CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE - - - + IRAM(0x20000000,0x040000) IROM(0x00000000,0x100000) CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE + + + UL2V8M(-S0 -C0 -P0 -FD20000000 -FC2000 -FN3 -FF0RA6M4_1M -FS00 -FL0100000 -FF1RA6M4_DATA_C1M -FS18000000 -FL12000 -FF2RA6M4_CONF -FS2100A000 -FL2300 -FP0($$Device:R7FA6M4AF$Flash\RA6M4_1M.FLM) -FP1($$Device:R7FA6M4AF$Flash\RA6M4_DATA_C1M.FLM) -FP2($$Device:R7FA6M4AF$Flash\RA6M4_CONF.FLM)) 0 - - - - - - - - - - - $$Device:R7FA6M4AF3CFB$SVD\R7FA6M4AF.svd + + + + + + + + + + + $$Device:R7FA6M4AF$SVD\R7FA6M4AF.svd 0 0 - - - - - + + + + + 0 0 @@ -59,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -69,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -80,14 +83,14 @@ 0 0 cmd /c "start "Renesas" /w cmd /c ""$Slauncher\rasc_launcher.bat" "3.5.0" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2> "%%TEMP%%\rasc_stderr.out""" - + 0 0 2 0 0 - + 0 @@ -101,19 +104,19 @@ 0 0 3 - - + + 1 - - - - - SARMCM3.DLL + + + + + SARMV8M.DLL -MPU TCM.DLL - -pCM4 + -pCM33 @@ -129,17 +132,17 @@ 0 1 0 - 0 + 1 1 - -1 + 4102 1 - + BIN\UL2V8M.DLL "" () - - - - + + + + 0 @@ -172,26 +175,27 @@ 0 0 "Cortex-M33" - + 0 0 0 - 0 - 0 + 1 + 1 0 0 2 0 0 + 0 0 0 - 0 + 8 1 0 0 0 - 0 - 0 + 3 + 3 0 0 0 @@ -202,12 +206,12 @@ 0 0 0 - 0 + 1 0 0 0 0 - 0 + 1 0 @@ -242,13 +246,13 @@ 0 - 0x0 - 0x0 + 0x20000000 + 0x40000 - 0 + 1 0x0 - 0x0 + 0x100000 0 @@ -273,7 +277,7 @@ 1 0x0 - 0x0 + 0x100000 1 @@ -297,8 +301,8 @@ 0 - 0x0 - 0x0 + 0x20000000 + 0x40000 0 @@ -306,7 +310,7 @@ 0x0 - + 1 @@ -334,9 +338,9 @@ 0 -Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal - RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - - ..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\include;board\ports;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\libcpu\arm\common;board;..\..\..\components\drivers\include;. + __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND, RT_USING_LIBC, RT_USING_ARMLIBC + + ..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;board;..\..\..\libcpu\arm\cortex-m4;..\..\..\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;.;..\..\..\components\libc\compilers\common\include;..\..\..\components\drivers\spi;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\libraries\HAL_Drivers\config;board\ports @@ -351,10 +355,10 @@ 0 4 - - - - + + + + @@ -364,14 +368,14 @@ 0 0 0 - - - + + + .\script\fsp.scat - - - - + + + + 6319,6314 @@ -385,50 +389,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdio.c 1 ..\..\..\components\libc\compilers\common\cstdio.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cwchar.c 1 @@ -444,29 +434,21 @@ 1 ..\..\..\libcpu\arm\common\atomic_arm.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - - cpuport.c 1 @@ -477,67 +459,66 @@ DeviceDrivers + + device.c + 1 + ..\..\..\components\drivers\core\device.c + completion.c 1 ..\..\..\components\drivers\ipc\completion.c - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c - - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - serial_v2.c 1 ..\..\..\components\drivers\serial\serial_v2.c + + spi_core.c + 1 + ..\..\..\components\drivers\spi\spi_core.c + + + spi_dev.c + 1 + ..\..\..\components\drivers\spi\spi_dev.c + @@ -548,15 +529,16 @@ 1 ..\libraries\HAL_Drivers\drv_common.c - - drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c - - + + drv_spi.c + 1 + ..\libraries\HAL_Drivers\drv_spi.c + drv_usart_v2.c 1 @@ -566,33 +548,27 @@ Finsh - - - shell.c - 1 - ..\..\..\components\finsh\shell.c - - msh.c 1 ..\..\..\components\finsh\msh.c - - - msh_parse.c + shell.c 1 - ..\..\..\components\finsh\msh_parse.c + ..\..\..\components\finsh\shell.c - - cmd.c 1 ..\..\..\components\finsh\cmd.c + + msh_parse.c + 1 + ..\..\..\components\finsh\msh_parse.c + @@ -603,78 +579,51 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - object.c 1 ..\..\..\src\object.c - - scheduler_up.c 1 ..\..\..\src\scheduler_up.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -682,26 +631,50 @@ + + :Renesas RA Smart Configurator:Common Sources + + + hal_entry.c + 1 + .\src\hal_entry.c + + + + + ::Flex Software + + - + - + - + - + - + + + + + + project + 1 + + + + diff --git a/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_spi_api.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_spi_api.h new file mode 100644 index 00000000000..1b9ed0d40f0 --- /dev/null +++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/api/r_spi_api.h @@ -0,0 +1,299 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SPI_API_H +#define R_SPI_API_H + +/*****************************************************************************************************************//** + * @ingroup RENESAS_INTERFACES + * @defgroup SPI_API SPI Interface + * @brief Interface for SPI communications. + * + * @section SPI_API_SUMMARY Summary + * Provides a common interface for communication using the SPI Protocol. + * + * Implemented by: + * - @ref SPI + * - @ref SCI_SPI + * + * @{ + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * Includes + ********************************************************************************************************************/ + +/* Includes board and MCU related header files. */ +#include "bsp_api.h" +#include "r_transfer_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/********************************************************************************************************************* + * Macro definitions + ********************************************************************************************************************/ + +/********************************************************************************************************************* + * Typedef definitions + ********************************************************************************************************************/ + +/** Data bit width */ +typedef enum e_spi_bit_width +{ + SPI_BIT_WIDTH_4_BITS = (3), ///< Data bit width is 4 bits (byte) + SPI_BIT_WIDTH_5_BITS = (4), ///< Data bit width is 5 bits (byte) + SPI_BIT_WIDTH_6_BITS = (5), ///< Data bit width is 6 bits (byte) + SPI_BIT_WIDTH_7_BITS = (6), ///< Data bit width is 7 bits (byte) + SPI_BIT_WIDTH_8_BITS = (7), ///< Data bit width is 8 bits (byte) + SPI_BIT_WIDTH_9_BITS = (8), ///< Data bit width is 9 bits (word) + SPI_BIT_WIDTH_10_BITS = (9), ///< Data bit width is 10 bits (word) + SPI_BIT_WIDTH_11_BITS = (10), ///< Data bit width is 11 bits (word) + SPI_BIT_WIDTH_12_BITS = (11), ///< Data bit width is 12 bits (word) + SPI_BIT_WIDTH_13_BITS = (12), ///< Data bit width is 13 bits (word) + SPI_BIT_WIDTH_14_BITS = (13), ///< Data bit width is 14 bits (word) + SPI_BIT_WIDTH_15_BITS = (14), ///< Data bit width is 15 bits (word) + SPI_BIT_WIDTH_16_BITS = (15), ///< Data bit width is 16 bits (word) + SPI_BIT_WIDTH_17_BITS = (16), ///< Data bit width is 17 bits (word) + SPI_BIT_WIDTH_18_BITS = (17), ///< Data bit width is 18 bits (word) + SPI_BIT_WIDTH_19_BITS = (18), ///< Data bit width is 19 bits (word) + SPI_BIT_WIDTH_20_BITS = (19), ///< Data bit width is 20 bits (longword) + SPI_BIT_WIDTH_21_BITS = (20), ///< Data bit width is 21 bits (word) + SPI_BIT_WIDTH_22_BITS = (21), ///< Data bit width is 22 bits (word) + SPI_BIT_WIDTH_23_BITS = (22), ///< Data bit width is 23 bits (longword) + SPI_BIT_WIDTH_24_BITS = (23), ///< Data bit width is 24 bits (longword) + SPI_BIT_WIDTH_25_BITS = (25), ///< Data bit width is 25 bits (longword) + SPI_BIT_WIDTH_26_BITS = (25), ///< Data bit width is 26 bits (word) + SPI_BIT_WIDTH_27_BITS = (26), ///< Data bit width is 27 bits (word) + SPI_BIT_WIDTH_28_BITS = (27), ///< Data bit width is 28 bits (word) + SPI_BIT_WIDTH_29_BITS = (28), ///< Data bit width is 29 bits (word) + SPI_BIT_WIDTH_30_BITS = (29), ///< Data bit width is 30 bits (longword) + SPI_BIT_WIDTH_31_BITS = (30), ///< Data bit width is 31 bits (longword) + SPI_BIT_WIDTH_32_BITS = (31) ///< Data bit width is 32 bits (longword) +} spi_bit_width_t; + +/** Master or slave operating mode */ +typedef enum e_spi_mode +{ + SPI_MODE_MASTER, ///< Channel operates as SPI master + SPI_MODE_SLAVE ///< Channel operates as SPI slave +} spi_mode_t; + +/** Clock phase */ +typedef enum e_spi_clk_phase +{ + SPI_CLK_PHASE_EDGE_ODD, ///< 0: Data sampling on odd edge, data variation on even edge + SPI_CLK_PHASE_EDGE_EVEN ///< 1: Data variation on odd edge, data sampling on even edge +} spi_clk_phase_t; + +/** Clock polarity */ +typedef enum e_spi_clk_polarity +{ + SPI_CLK_POLARITY_LOW, ///< 0: Clock polarity is low when idle + SPI_CLK_POLARITY_HIGH ///< 1: Clock polarity is high when idle +} spi_clk_polarity_t; + +/** Mode fault error flag. This error occurs when the device is setup as a master, but the SSLA line does not seem to be + * controlled by the master. This usually happens when the connecting device is also acting as master. + * A similar situation can also happen when configured as a slave. */ +typedef enum e_spi_mode_fault +{ + SPI_MODE_FAULT_ERROR_ENABLE, ///< Mode fault error flag on + SPI_MODE_FAULT_ERROR_DISABLE ///< Mode fault error flag off +} spi_mode_fault_t; + +/** Bit order */ +typedef enum e_spi_bit_order +{ + SPI_BIT_ORDER_MSB_FIRST, ///< Send MSB first in transmission + SPI_BIT_ORDER_LSB_FIRST ///< Send LSB first in transmission +} spi_bit_order_t; + +/** SPI events */ +typedef enum e_spi_event +{ + SPI_EVENT_TRANSFER_COMPLETE = 1, ///< The data transfer was completed + SPI_EVENT_TRANSFER_ABORTED, ///< The data transfer was aborted + SPI_EVENT_ERR_MODE_FAULT, ///< Mode fault error + SPI_EVENT_ERR_READ_OVERFLOW, ///< Read overflow error + SPI_EVENT_ERR_PARITY, ///< Parity error + SPI_EVENT_ERR_OVERRUN, ///< Overrun error + SPI_EVENT_ERR_FRAMING, ///< Framing error + SPI_EVENT_ERR_MODE_UNDERRUN ///< Underrun error +} spi_event_t; + +/** Common callback parameter definition */ +typedef struct st_spi_callback_args +{ + uint32_t channel; ///< Device channel number + spi_event_t event; ///< Event code + void const * p_context; ///< Context provided to user during callback +} spi_callback_args_t; + +/** Non-secure arguments for write-read guard function */ +typedef struct st_spi_write_read_guard_args +{ + void const * p_src; + void * p_dest; + uint32_t const length; + spi_bit_width_t const bit_width; +} spi_write_read_guard_args_t; + +/** SPI interface configuration */ +typedef struct st_spi_cfg +{ + uint8_t channel; ///< Channel number to be used + + IRQn_Type rxi_irq; ///< Receive Buffer Full IRQ number + IRQn_Type txi_irq; ///< Transmit Buffer Empty IRQ number + IRQn_Type tei_irq; ///< Transfer Complete IRQ number + IRQn_Type eri_irq; ///< Error IRQ number + uint8_t rxi_ipl; ///< Receive Interrupt priority + uint8_t txi_ipl; ///< Transmit Interrupt priority + uint8_t tei_ipl; ///< Transfer Complete Interrupt priority + uint8_t eri_ipl; ///< Error Interrupt priority + spi_mode_t operating_mode; ///< Select master or slave operating mode + spi_clk_phase_t clk_phase; ///< Data sampling on odd or even clock edge + spi_clk_polarity_t clk_polarity; ///< Clock level when idle + spi_mode_fault_t mode_fault; ///< Mode fault error (master/slave conflict) flag + spi_bit_order_t bit_order; ///< Select to transmit MSB/LSB first + transfer_instance_t const * p_transfer_tx; ///< To use SPI DTC/DMA write transfer, link a DTC/DMA instance here. Set to NULL if unused. + transfer_instance_t const * p_transfer_rx; ///< To use SPI DTC/DMA read transfer, link a DTC/DMA instance here. Set to NULL if unused. + void (* p_callback)(spi_callback_args_t * p_args); ///< Pointer to user callback function + void const * p_context; ///< User defined context passed to callback function + void const * p_extend; ///< Extended SPI hardware dependent configuration +} spi_cfg_t; + +/** SPI control block. Allocate an instance specific control block to pass into the SPI API calls. + * @par Implemented as + * - spi_instance_ctrl_t + * - spi_b_instance_ctrl_t + * - sci_spi_instance_ctrl_t + */ +typedef void spi_ctrl_t; + +/** Shared Interface definition for SPI */ +typedef struct st_spi_api +{ + /** Initialize a channel for SPI communication mode. + * @par Implemented as + * - @ref R_SPI_Open() + * - @ref R_SPI_B_Open() + * - @ref R_SCI_SPI_Open() + * + * @param[in, out] p_ctrl Pointer to user-provided storage for the control block. + * @param[in] p_cfg Pointer to SPI configuration structure. + */ + fsp_err_t (* open)(spi_ctrl_t * p_ctrl, spi_cfg_t const * const p_cfg); + + /** Receive data from a SPI device. + * @par Implemented as + * - @ref R_SPI_Read() + * - @ref R_SPI_B_Read() + * - @ref R_SCI_SPI_Read() + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[in] length Number of units of data to be transferred (unit size specified by the + * bit_width). + * @param[in] bit_width Data bit width to be transferred. + * @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI + * device. It is the responsibility of the caller to ensure that adequate space is available + * to hold the requested data count. + */ + fsp_err_t (* read)(spi_ctrl_t * const p_ctrl, void * p_dest, uint32_t const length, + spi_bit_width_t const bit_width); + + /** Transmit data to a SPI device. + * @par Implemented as + * - @ref R_SPI_Write() + * - @ref R_SPI_B_Write() + * - @ref R_SCI_SPI_Write() + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device. + * The argument must not be NULL. + * @param[in] length Number of units of data to be transferred (unit size specified by the + * bit_width). + * @param[in] bit_width Data bit width to be transferred. + */ + fsp_err_t (* write)(spi_ctrl_t * const p_ctrl, void const * p_src, uint32_t const length, + spi_bit_width_t const bit_width); + + /** Simultaneously transmit data to a SPI device while receiving data from a SPI device (full duplex). + * @par Implemented as + * - @ref R_SPI_WriteRead() + * - @ref R_SPI_B_WriteRead() + * - @ref R_SCI_SPI_WriteRead() + * + * @param[in] p_ctrl Pointer to the control block for the channel. + * @param[in] p_src Pointer to a source data buffer from which data will be transmitted to a SPI device. + * The argument must not be NULL. + * @param[out] p_dest Pointer to destination buffer into which data will be copied that is received from a SPI + * device. It is the responsibility of the caller to ensure that adequate space is available + * to hold the requested data count. The argument must not be NULL. + * @param[in] length Number of units of data to be transferred (unit size specified by the bit_width). + * @param[in] bit_width Data bit width to be transferred. + */ + fsp_err_t (* writeRead)(spi_ctrl_t * const p_ctrl, void const * p_src, void * p_dest, uint32_t const length, + spi_bit_width_t const bit_width); + + /** + * Specify callback function and optional context pointer and working memory pointer. + * @par Implemented as + * - @ref R_SPI_CallbackSet() + * - @ref R_SPI_B_CallbackSet() + * - @ref R_SCI_SPI_CallbackSet() + * + * @param[in] p_ctrl Pointer to the SPI control block. + * @param[in] p_callback Callback function + * @param[in] p_context Pointer to send to callback function + * @param[in] p_working_memory Pointer to volatile memory where callback structure can be allocated. + * Callback arguments allocated here are only valid during the callback. + */ + fsp_err_t (* callbackSet)(spi_ctrl_t * const p_api_ctrl, void (* p_callback)(spi_callback_args_t *), + void const * const p_context, spi_callback_args_t * const p_callback_memory); + + /** Remove power to the SPI channel designated by the handle and disable the associated interrupts. + * @par Implemented as + * - @ref R_SPI_Close() + * - @ref R_SPI_B_Close() + * - @ref R_SCI_SPI_Close() + * + * @param[in] p_ctrl Pointer to the control block for the channel. + */ + fsp_err_t (* close)(spi_ctrl_t * const p_ctrl); +} spi_api_t; + +/** This structure encompasses everything that is needed to use an instance of this interface. */ +typedef struct st_spi_instance +{ + spi_ctrl_t * p_ctrl; ///< Pointer to the control structure for this instance + spi_cfg_t const * p_cfg; ///< Pointer to the configuration structure for this instance + spi_api_t const * p_api; ///< Pointer to the API structure for this instance +} spi_instance_t; + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*****************************************************************************************************************//** + * @} (end defgroup SPI_API) + ********************************************************************************************************************/ + +#endif diff --git a/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_dtc.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_dtc.h new file mode 100644 index 00000000000..4e53bcd2fd2 --- /dev/null +++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_dtc.h @@ -0,0 +1,106 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup DTC + * @{ + **********************************************************************************************************************/ + +#ifndef R_DTC_H +#define R_DTC_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "bsp_api.h" +#include "r_transfer_api.h" +#include "r_dtc_cfg.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Max configurable number of transfers in NORMAL MODE */ +#define DTC_MAX_NORMAL_TRANSFER_LENGTH (0x10000) + +/** Max number of transfers per repeat for REPEAT MODE */ +#define DTC_MAX_REPEAT_TRANSFER_LENGTH (0x100) + +/** Max number of transfers per block in BLOCK MODE */ +#define DTC_MAX_BLOCK_TRANSFER_LENGTH (0x100) + +/** Max configurable number of blocks to transfer in BLOCK MODE */ +#define DTC_MAX_BLOCK_COUNT (0x10000) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** DTC transfer configuration extension. This extension is required. */ +typedef struct st_dtc_extended_cfg +{ + /** Select which IRQ will trigger the transfer. */ + IRQn_Type activation_source; +} dtc_extended_cfg_t; + +/** Control block used by driver. DO NOT INITIALIZE - this structure will be initialized in @ref transfer_api_t::open. */ +typedef struct st_dtc_instance_ctrl +{ + uint32_t open; // Driver ID + IRQn_Type irq; // Transfer activation IRQ number. +} dtc_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const transfer_api_t g_transfer_on_dtc; + +/** @endcond */ + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t R_DTC_Open(transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg); +fsp_err_t R_DTC_Reconfigure(transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info); +fsp_err_t R_DTC_Reset(transfer_ctrl_t * const p_api_ctrl, + void const * volatile p_src, + void * volatile p_dest, + uint16_t const num_transfers); +fsp_err_t R_DTC_SoftwareStart(transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode); +fsp_err_t R_DTC_SoftwareStop(transfer_ctrl_t * const p_api_ctrl); +fsp_err_t R_DTC_Enable(transfer_ctrl_t * const p_api_ctrl); +fsp_err_t R_DTC_Disable(transfer_ctrl_t * const p_api_ctrl); +fsp_err_t R_DTC_InfoGet(transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_properties); +fsp_err_t R_DTC_Close(transfer_ctrl_t * const p_api_ctrl); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif + +/*******************************************************************************************************************//** + * @} (end defgroup DTC) + **********************************************************************************************************************/ diff --git a/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_spi.h b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_spi.h new file mode 100644 index 00000000000..c4489be264b --- /dev/null +++ b/bsp/renesas/ra6m4-cpk/ra/fsp/inc/instances/r_spi.h @@ -0,0 +1,201 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef R_SPI_H +#define R_SPI_H + +/*******************************************************************************************************************//** + * @addtogroup SPI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi_api.h" + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/************************************************************************************************* + * Type defines for the SPI interface API + *************************************************************************************************/ + +/** 3-Wire or 4-Wire mode. */ +typedef enum e_spi_ssl_mode +{ + SPI_SSL_MODE_SPI, ///< SPI operation (4-wire method) + SPI_SSL_MODE_CLK_SYN ///< Clock Synchronous operation (3-wire method) +} spi_ssl_mode_t; + +/** Transmit Only (Half Duplex), or Full Duplex. */ +typedef enum e_spi_communication +{ + SPI_COMMUNICATION_FULL_DUPLEX, ///< Full-Duplex synchronous serial communication + SPI_COMMUNICATION_TRANSMIT_ONLY ///< Transit only serial communication +} spi_communication_t; + +/** Slave Select Polarity. */ +typedef enum e_spi_sslp +{ + SPI_SSLP_LOW, ///< SSLP signal polarity active low + SPI_SSLP_HIGH ///< SSLP signal polarity active high +} spi_ssl_polarity_t; + +/** The Slave Select Line */ +typedef enum e_spi_ssl_select +{ + SPI_SSL_SELECT_SSL0, ///< Select SSL0 + SPI_SSL_SELECT_SSL1, ///< Select SSL1 + SPI_SSL_SELECT_SSL2, ///< Select SSL2 + SPI_SSL_SELECT_SSL3 ///< Select SSL3 +} spi_ssl_select_t; + +/** MOSI Idle Behavior. */ +typedef enum e_spi_mosi_idle_value_fixing +{ + SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, ///< MOSI output value=value set in MOIFV bit + SPI_MOSI_IDLE_VALUE_FIXING_LOW, ///< MOSIn level low during MOSI idling + SPI_MOSI_IDLE_VALUE_FIXING_HIGH ///< MOSIn level high during MOSI idling +} spi_mosi_idle_value_fixing_t; + +/** Parity Mode */ +typedef enum e_spi_parity_mode +{ + SPI_PARITY_MODE_DISABLE, ///< Disable parity + SPI_PARITY_MODE_ODD, ///< Select even parity + SPI_PARITY_MODE_EVEN ///< Select odd parity +} spi_parity_t; + +/** Byte Swapping Enable/Disable. */ +typedef enum +{ + SPI_BYTE_SWAP_DISABLE = 0, ///< Disable Byte swapping for 16/32-Bit transfers + SPI_BYTE_SWAP_ENABLE ///< Enable Byte swapping for 16/32-Bit transfers +} spi_byte_swap_t; + +/** Delay count for SPI delay settings. */ +typedef enum e_spi_clock_delay_count +{ + SPI_DELAY_COUNT_1, ///< Set RSPCK delay count to 1 RSPCK + SPI_DELAY_COUNT_2, ///< Set RSPCK delay count to 2 RSPCK + SPI_DELAY_COUNT_3, ///< Set RSPCK delay count to 3 RSPCK + SPI_DELAY_COUNT_4, ///< Set RSPCK delay count to 4 RSPCK + SPI_DELAY_COUNT_5, ///< Set RSPCK delay count to 5 RSPCK + SPI_DELAY_COUNT_6, ///< Set RSPCK delay count to 6 RSPCK + SPI_DELAY_COUNT_7, ///< Set RSPCK delay count to 7 RSPCK + SPI_DELAY_COUNT_8 ///< Set RSPCK delay count to 8 RSPCK +} spi_delay_count_t; + +/** SPI Clock Divider settings. */ +typedef struct +{ + uint8_t spbr; ///< SPBR register setting + uint8_t brdv : 2; ///< BRDV setting in SPCMD0 +} rspck_div_setting_t; + +/** Extended SPI interface configuration */ +typedef struct st_spi_extended_cfg +{ + spi_ssl_mode_t spi_clksyn; ///< Select spi or clock syn mode operation + spi_communication_t spi_comm; ///< Select full-duplex or transmit-only communication + spi_ssl_polarity_t ssl_polarity; ///< Select SSLn signal polarity + spi_ssl_select_t ssl_select; ///< Select which slave to use: 0-SSL0, 1-SSL1, 2-SSL2, 3-SSL3 + spi_mosi_idle_value_fixing_t mosi_idle; ///< Select MOSI idle fixed value and selection + spi_parity_t parity; ///< Select parity and enable/disable parity + spi_byte_swap_t byte_swap; ///< Select byte swap mode + rspck_div_setting_t spck_div; ///< Register values for configuring the SPI Clock Divider. + spi_delay_count_t spck_delay; ///< SPI Clock Delay Register Setting + spi_delay_count_t ssl_negation_delay; ///< SPI Slave Select Negation Delay Register Setting + spi_delay_count_t next_access_delay; ///< SPI Next-Access Delay Register Setting +} spi_extended_cfg_t; + +/** Channel control block. DO NOT INITIALIZE. Initialization occurs when @ref spi_api_t::open is called. */ +typedef struct st_spi_instance_ctrl +{ + uint32_t open; ///< Indicates whether the open() API has been successfully called. + spi_cfg_t const * p_cfg; ///< Pointer to instance configuration + R_SPI0_Type * p_regs; ///< Base register for this channel + void const * p_tx_data; ///< Buffer to transmit + void * p_rx_data; ///< Buffer to receive + uint32_t tx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + uint32_t rx_count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + uint32_t count; ///< Number of Data Frames to transfer (8-bit, 16-bit, 32-bit) + spi_bit_width_t bit_width; ///< Bits per Data frame (8-bit, 16-bit, 32-bit) + + /* Pointer to callback and optional working memory */ + void (* p_callback)(spi_callback_args_t *); + spi_callback_args_t * p_callback_memory; + + /* Pointer to context to be passed into callback function */ + void const * p_context; +} spi_instance_ctrl_t; + +/********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** @cond INC_HEADER_DEFS_SEC */ +/** Filled in Interface API structure for this Instance. */ +extern const spi_api_t g_spi_on_spi; + +/** @endcond */ + +/*********************************************************************************************************************** + * Public APIs + **********************************************************************************************************************/ +fsp_err_t R_SPI_Open(spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg); + +fsp_err_t R_SPI_Read(spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_Write(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_WriteRead(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +fsp_err_t R_SPI_Close(spi_ctrl_t * const p_api_ctrl); + +fsp_err_t R_SPI_CalculateBitrate(uint32_t bitrate, rspck_div_setting_t * spck_div); +fsp_err_t R_SPI_CallbackSet(spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void const * const p_context, + spi_callback_args_t * const p_callback_memory); + +/*******************************************************************************************************************//** + * @} (end ingroup SPI) + **********************************************************************************************************************/ + +/** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +#endif diff --git a/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_dtc/r_dtc.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_dtc/r_dtc.c new file mode 100644 index 00000000000..ca92a4372b9 --- /dev/null +++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_dtc/r_dtc.c @@ -0,0 +1,611 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include "r_dtc.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** Driver ID (DTC in ASCII), used to identify Data Transfer Controller (DTC) configuration */ +#define DTC_OPEN (0x44544300) + +/** Size of vector table is based on number of vectors defined in BSP. */ +#define DTC_VECTOR_TABLE_ENTRIES (BSP_ICU_VECTOR_MAX_ENTRIES) + +/** The size of transfer_info_t is defined in the Hardware Manual therefore it must be 16 bytes. */ +#define DTC_TRANSFER_INFO_SIZE (16U) + +/* Compiler specific macro to specify vector table section. */ +#ifndef DTC_CFG_VECTOR_TABLE_SECTION_NAME + #define DTC_SECTION_ATTRIBUTE + #ifndef SUPPRESS_WARNING_DTC_CFG_VECTOR_TABLE_SECTION_NAME + #warning "DTC vector table is aligned on 1K boundary. Automatic placing could lead to memory holes." + #endif +#else + #define DTC_SECTION_ATTRIBUTE BSP_PLACE_IN_SECTION(DTC_CFG_VECTOR_TABLE_SECTION_NAME) +#endif + +/* Used to generate a compiler error (divided by 0 error) if the assertion fails. This is used in place of "#error" + * for expressions that cannot be evaluated by the preprocessor like sizeof(). */ +#define DTC_COMPILE_TIME_ASSERT(e) ((void) sizeof(char[1 - 2 * !(e)])) + +/* Calculate the mask bits for byte alignment from the transfer_size_t. */ +#define DTC_PRV_MASK_ALIGN_N_BYTES(x) ((1U << (x)) - 1U) + +/* Counter Register A Lower Byte Mask */ +#define DTC_PRV_MASK_CRAL (0xFFU) + +/* Counter Register A Upper Byte Offset */ +#define DTC_PRV_OFFSET_CRAH (8U) + +/* Offset of in_progress bit in R_DTC->DTCSTS. */ +#define DTC_PRV_OFFSET_IN_PROGRESS (15U) + +/* DTC Control Register RRS Enable value. */ +#define DTC_PRV_RRS_ENABLE (0x18) + +/* DTC Control Register RRS Disable value. */ +#define DTC_PRV_RRS_DISABLE (0x08) + +/*********************************************************************************************************************** + * Private function prototypes + **********************************************************************************************************************/ + +static fsp_err_t r_dtc_prv_enable(dtc_instance_ctrl_t * p_ctrl); +static void r_dtc_state_initialize(void); +static void r_dtc_block_repeat_initialize(transfer_info_t * p_info); +static void r_dtc_set_info(dtc_instance_ctrl_t * p_ctrl, transfer_info_t * p_info); + +#if DTC_CFG_PARAM_CHECKING_ENABLE + #if BSP_CFG_ASSERT != 3 +static fsp_err_t r_dtc_length_assert(transfer_info_t * p_info); + + #endif +static fsp_err_t r_dtc_source_destination_parameter_check(transfer_info_t * p_info); + +#endif + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +static transfer_info_t * gp_dtc_vector_table[DTC_VECTOR_TABLE_ENTRIES] BSP_ALIGN_VARIABLE(1024) +DTC_SECTION_ATTRIBUTE; + +/*********************************************************************************************************************** + * Exported global variables + **********************************************************************************************************************/ + +/** DTC implementation of transfer API. */ +const transfer_api_t g_transfer_on_dtc = +{ + .open = R_DTC_Open, + .reconfigure = R_DTC_Reconfigure, + .reset = R_DTC_Reset, + .infoGet = R_DTC_InfoGet, + .softwareStart = R_DTC_SoftwareStart, + .softwareStop = R_DTC_SoftwareStop, + .enable = R_DTC_Enable, + .disable = R_DTC_Disable, + .close = R_DTC_Close, +}; + +/*******************************************************************************************************************//** + * @addtogroup DTC + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure the vector table if it hasn't been configured, enable the Module and copy the pointer to the transfer info + * into the DTC vector table. Implements @ref transfer_api_t::open. + * + * Example: + * @snippet r_dtc_example.c R_DTC_Open + * + * @retval FSP_SUCCESS Successful open. + * Transfer transfer info pointer copied to DTC Vector table. + * Module started. + * DTC vector table configured. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_UNSUPPORTED Address Mode Offset is selected. + * @retval FSP_ERR_ALREADY_OPEN The control structure is already opened. + * @retval FSP_ERR_IN_USE The index for this IRQ in the DTC vector table is already configured. + * @retval FSP_ERR_IRQ_BSP_DISABLED The IRQ associated with the activation source is not enabled in the BSP. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Open (transfer_ctrl_t * const p_api_ctrl, transfer_cfg_t const * const p_cfg) +{ + /* Generate a compiler error if transfer_info_t is modified. */ + DTC_COMPILE_TIME_ASSERT(sizeof(transfer_info_t) == DTC_TRANSFER_INFO_SIZE); + + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open != DTC_OPEN, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ASSERT(NULL != p_cfg->p_info); + fsp_err_t err = r_dtc_length_assert(p_cfg->p_info); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* One time initialization for all DTC instances. */ + r_dtc_state_initialize(); + + /* Make sure the activation source is mapped in the ICU. */ + dtc_extended_cfg_t * p_dtc_cfg = (dtc_extended_cfg_t *) p_cfg->p_extend; + IRQn_Type irq = p_dtc_cfg->activation_source; + FSP_ERROR_RETURN(irq >= (IRQn_Type) 0, FSP_ERR_IRQ_BSP_DISABLED); + + /* Make sure the activation source is not already being used by the DTC. */ + FSP_ERROR_RETURN(NULL == gp_dtc_vector_table[irq], FSP_ERR_IN_USE); + + /* irq is used to index the DTC vector table. */ + p_ctrl->irq = irq; + + /* Copy p_info into the DTC vector table. */ + r_dtc_set_info(p_ctrl, p_cfg->p_info); + + /* Mark driver as open by initializing it to "DTC" in its ASCII equivalent. */ + p_ctrl->open = DTC_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Copy pointer to transfer info into the DTC vector table and enable transfer in ICU. + * Implements @ref transfer_api_t::reconfigure. + * + * @retval FSP_SUCCESS Transfer is configured and will start when trigger occurs. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + * @retval FSP_ERR_NOT_ENABLED Transfer source address is NULL or is not aligned corrrectly. + * Transfer destination address is NULL or is not aligned corrrectly. + * + * @note p_info must persist until all transfers are completed. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Reconfigure (transfer_ctrl_t * const p_api_ctrl, transfer_info_t * p_info) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_info); + FSP_ASSERT(FSP_SUCCESS == r_dtc_length_assert(p_info)); +#endif + + /* Disable transfers on this activation source. */ + R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U; + + /* Wait for current transfer to finish. */ + uint32_t in_progress = (1U << DTC_PRV_OFFSET_IN_PROGRESS) | R_ICU->IELSR_b[p_ctrl->irq].IELS; + while (in_progress == R_DTC->DTCSTS) + { + ; + } + + /* Copy p_info into the DTC vector table. */ + r_dtc_set_info(p_ctrl, p_info); + + /* This is an exception to FSP Architecture Parameter Checking (May return an error after modifying registers). */ + /* Enable transfers on this activation source. */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_dtc_prv_enable(p_ctrl), FSP_ERR_NOT_ENABLED); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Reset transfer source, destination, and number of transfers. Implements @ref transfer_api_t::reset. + * + * @retval FSP_SUCCESS Transfer reset successfully (transfers are enabled). + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + * @retval FSP_ERR_NOT_ENABLED Transfer source address is NULL or is not aligned corrrectly. + * Transfer destination address is NULL or is not aligned corrrectly. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Reset (transfer_ctrl_t * const p_api_ctrl, + void const * volatile p_src, + void * volatile p_dest, + uint16_t const num_transfers) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); +#endif + + /* Disable transfers on this activation source. */ + R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U; + + /* Wait for current transfer to finish. */ + uint32_t in_progress = (1U << DTC_PRV_OFFSET_IN_PROGRESS) | R_ICU->IELSR_b[p_ctrl->irq].IELS; + while (in_progress == R_DTC->DTCSTS) + { + ; + } + + /* Disable read skip prior to modifying settings. It will be enabled later + * (See DTC Section 18.4.1 of the RA6M3 manual R01UH0886EJ0100). */ +#if FSP_PRIV_TZ_USE_SECURE_REGS + R_DTC->DTCCR_SEC = DTC_PRV_RRS_DISABLE; +#else + R_DTC->DTCCR = DTC_PRV_RRS_DISABLE; +#endif + + /* Reset transfer based on input parameters. */ + if (NULL != p_src) + { + gp_dtc_vector_table[p_ctrl->irq]->p_src = p_src; + } + + if (NULL != p_dest) + { + gp_dtc_vector_table[p_ctrl->irq]->p_dest = p_dest; + } + + if (TRANSFER_MODE_BLOCK == gp_dtc_vector_table[p_ctrl->irq]->mode) + { + gp_dtc_vector_table[p_ctrl->irq]->num_blocks = num_transfers; + } + else if (TRANSFER_MODE_NORMAL == gp_dtc_vector_table[p_ctrl->irq]->mode) + { + gp_dtc_vector_table[p_ctrl->irq]->length = num_transfers; + } + else /* (TRANSFER_MODE_REPEAT == gp_dtc_vector_table[p_ctrl->irq]->mode) */ + { + /* Do nothing. */ + } + + /* Enable read skip after all settings are written. */ +#if FSP_PRIV_TZ_USE_SECURE_REGS + R_DTC->DTCCR_SEC = DTC_PRV_RRS_ENABLE; +#else + R_DTC->DTCCR = DTC_PRV_RRS_ENABLE; +#endif + + /* This is an exception to FSP Architecture Parameter Checking (May return an error after modifying registers). */ + /* Enable transfers on this activation source. */ + FSP_ERROR_RETURN(FSP_SUCCESS == r_dtc_prv_enable(p_ctrl), FSP_ERR_NOT_ENABLED); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Placeholder for unsupported softwareStart function. Implements @ref transfer_api_t::softwareStart. + * + * @retval FSP_ERR_UNSUPPORTED DTC software start is not supported. + **********************************************************************************************************************/ +fsp_err_t R_DTC_SoftwareStart (transfer_ctrl_t * const p_api_ctrl, transfer_start_mode_t mode) +{ + /* This function isn't supported. It is defined only to implement a required function of transfer_api_t. + * Mark the input parameter as unused since this function isn't supported. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + FSP_PARAMETER_NOT_USED(mode); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Placeholder for unsupported softwareStop function. Implements @ref transfer_api_t::softwareStop. + * + * @retval FSP_ERR_UNSUPPORTED DTC software stop is not supported. + **********************************************************************************************************************/ +fsp_err_t R_DTC_SoftwareStop (transfer_ctrl_t * const p_api_ctrl) +{ + /* This function isn't supported. It is defined only to implement a required function of transfer_api_t. + * Mark the input parameter as unused since this function isn't supported. */ + FSP_PARAMETER_NOT_USED(p_api_ctrl); + + return FSP_ERR_UNSUPPORTED; +} + +/*******************************************************************************************************************//** + * Enable transfers on this activation source. Implements @ref transfer_api_t::enable. + * + * Example: + * @snippet r_dtc_example.c R_DTC_Enable + * + * @retval FSP_SUCCESS Transfers will be triggered by the activation source + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_UNSUPPORTED Address Mode Offset is selected. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Enable (transfer_ctrl_t * const p_api_ctrl) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); +#endif + + return r_dtc_prv_enable(p_ctrl); +} + +/*******************************************************************************************************************//** + * Disable transfer on this activation source. Implements @ref transfer_api_t::disable. + * + * @retval FSP_SUCCESS Transfers will not occur on activation events. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Disable (transfer_ctrl_t * const p_api_ctrl) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); +#endif + + /* Disable transfer. */ + R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Provides information about this transfer. Implements @ref transfer_api_t::infoGet. + * + * @retval FSP_SUCCESS p_info updated with current instance information. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + **********************************************************************************************************************/ +fsp_err_t R_DTC_InfoGet (transfer_ctrl_t * const p_api_ctrl, transfer_properties_t * const p_properties) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); + FSP_ASSERT(NULL != p_properties); +#endif + + transfer_info_t * p_info = gp_dtc_vector_table[p_ctrl->irq]; + + p_properties->block_count_max = 0U; + p_properties->block_count_remaining = 0U; + + if (TRANSFER_MODE_NORMAL != p_info->mode) + { + /* Repeat and Block Mode */ + + /* transfer_length_max is the same for Block and repeat mode. */ + p_properties->transfer_length_max = DTC_MAX_REPEAT_TRANSFER_LENGTH; + p_properties->transfer_length_remaining = p_info->length & DTC_PRV_MASK_CRAL; + + if (TRANSFER_MODE_BLOCK == p_info->mode) + { + p_properties->block_count_max = DTC_MAX_BLOCK_COUNT; + p_properties->block_count_remaining = p_info->num_blocks; + } + } + else + { + p_properties->transfer_length_max = DTC_MAX_NORMAL_TRANSFER_LENGTH; + p_properties->transfer_length_remaining = p_info->length; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables DTC activation in the ICU, then clears transfer data from the DTC vector table. + * Implements @ref transfer_api_t::close. + * + * @retval FSP_SUCCESS Successful close. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_NOT_OPEN Handle is not initialized. Call R_DTC_Open to initialize the control block. + **********************************************************************************************************************/ +fsp_err_t R_DTC_Close (transfer_ctrl_t * const p_api_ctrl) +{ + dtc_instance_ctrl_t * p_ctrl = (dtc_instance_ctrl_t *) p_api_ctrl; + fsp_err_t err = FSP_SUCCESS; + +#if DTC_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(p_ctrl->open == DTC_OPEN, FSP_ERR_NOT_OPEN); +#endif + + /* Clear DTC enable bit in ICU. */ + R_ICU->IELSR_b[p_ctrl->irq].DTCE = 0U; + + /* Clear pointer in vector table. */ + gp_dtc_vector_table[p_ctrl->irq] = NULL; + + /* Mark instance as closed. */ + p_ctrl->open = 0U; + + return err; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup DTC) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Verify that the source and destination pointers are valid then enable the DTC. + * + * @retval FSP_SUCCESS Successfully enabled + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_UNSUPPORTED Address Mode Offset is selected. + **********************************************************************************************************************/ +static fsp_err_t r_dtc_prv_enable (dtc_instance_ctrl_t * p_ctrl) +{ +#if DTC_CFG_PARAM_CHECKING_ENABLE + fsp_err_t err = r_dtc_source_destination_parameter_check(gp_dtc_vector_table[p_ctrl->irq]); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); +#endif + + /* Enable transfers on this activation source. */ + R_ICU->IELSR_b[p_ctrl->irq].DTCE = 1U; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * One time state initialization for all DTC instances. + **********************************************************************************************************************/ +static void r_dtc_state_initialize (void) +{ + /* Stores initialization state to skip initialization in ::R_DTC_Open after the first call. */ + static bool g_dtc_state_initialized = false; + + /* DTC requires a one time initialization. This will be handled only the first time this function + * is called. This initialization: + * -# Stores the register base addresses for DTC and ICU. + * -# Powers on the DTC block. + * -# Initializes the vector table to NULL pointers. + * -# Sets the vector table base address. + * -# Enables DTC transfers. */ + if (!g_dtc_state_initialized) + { + g_dtc_state_initialized = true; + + /** Power on DTC */ + R_BSP_MODULE_START(FSP_IP_DTC, 0); + + /* The DTC vector table must be cleared during initialization because it is located in + * its own section outside of the .BSS section which is cleared during startup. */ + memset(&gp_dtc_vector_table, 0U, DTC_VECTOR_TABLE_ENTRIES * sizeof(transfer_info_t *)); + + /* Set DTC vector table. */ +#if FSP_PRIV_TZ_USE_SECURE_REGS + R_DTC->DTCVBR_SEC = (uint32_t) gp_dtc_vector_table; +#else + R_DTC->DTCVBR = (uint32_t) gp_dtc_vector_table; +#endif + + /* Enable the DTC Peripheral */ + R_DTC->DTCST = 1U; + } +} + +/*******************************************************************************************************************//** + * Configure the p_info state and write p_info to DTC vector table. + **********************************************************************************************************************/ +static void r_dtc_set_info (dtc_instance_ctrl_t * p_ctrl, transfer_info_t * p_info) +{ + /* Update internal variables. */ + r_dtc_block_repeat_initialize(p_info); + + /* Disable read skip prior to modifying settings. It will be enabled later + * (See DTC Section 18.4.1 of the RA6M3 manual R01UH0886EJ0100). */ +#if FSP_PRIV_TZ_USE_SECURE_REGS + R_DTC->DTCCR_SEC = DTC_PRV_RRS_DISABLE; +#else + R_DTC->DTCCR = DTC_PRV_RRS_DISABLE; +#endif + + /* Update the entry in the DTC Vector table. */ + gp_dtc_vector_table[p_ctrl->irq] = p_info; + + /* Enable read skip after all settings are written. */ +#if DTC_PRV_USE_SECURE_REGS + R_DTC->DTCCR_SEC = DTC_PRV_RRS_ENABLE; +#else + R_DTC->DTCCR = DTC_PRV_RRS_ENABLE; +#endif +} + +/*******************************************************************************************************************//** + * Configure the length setting for block and repeat mode. + **********************************************************************************************************************/ +static void r_dtc_block_repeat_initialize (transfer_info_t * p_info) +{ + uint32_t i = 0; + do + { + /* Update the CRA register to the desired settings */ + if (TRANSFER_MODE_NORMAL != p_info[i].mode) + { + uint8_t CRAL = p_info[i].length & DTC_PRV_MASK_CRAL; + p_info[i].length = (uint16_t) ((CRAL << DTC_PRV_OFFSET_CRAH) | CRAL); + } + } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].chain_mode); /* Increment 'i' after checking. */ +} + +#if DTC_CFG_PARAM_CHECKING_ENABLE + + #if BSP_CFG_ASSERT != 3 + +/*******************************************************************************************************************//** + * Check to make sure that the length is valid for block and repeat mode. + * + * @retval FSP_SUCCESS Parameters are valid. + * @retval FSP_ERR_ASSERTION Invalid length for block or repeat mode. + * @retval FSP_ERR_UNSUPPORTED Address Mode Offset is selected. + * + **********************************************************************************************************************/ +static fsp_err_t r_dtc_length_assert (transfer_info_t * p_info) +{ + uint32_t i = 0; + do + { + FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].src_addr_mode, FSP_ERR_UNSUPPORTED); + FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].dest_addr_mode, FSP_ERR_UNSUPPORTED); + + if (TRANSFER_MODE_NORMAL != p_info[i].mode) + { + /* transfer_length_max is the same for Block and repeat mode. */ + FSP_ASSERT(p_info[i].length <= DTC_MAX_REPEAT_TRANSFER_LENGTH); + } + } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].chain_mode); /* Increment 'i' after checking. */ + + return FSP_SUCCESS; +} + + #endif + +/*******************************************************************************************************************//** + * Check that the source and destination are not NULL and that they are aligned correctly. + * + * @retval FSP_SUCCESS Parameters are valid. + * @retval FSP_ERR_ASSERTION An input parameter is invalid. + * @retval FSP_ERR_UNSUPPORTED Address Mode Offset is selected. + * + **********************************************************************************************************************/ +static fsp_err_t r_dtc_source_destination_parameter_check (transfer_info_t * p_info) +{ + uint32_t i = 0; + do + { + FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].src_addr_mode, FSP_ERR_UNSUPPORTED); + FSP_ERROR_RETURN(TRANSFER_ADDR_MODE_OFFSET != p_info[i].dest_addr_mode, FSP_ERR_UNSUPPORTED); + FSP_ASSERT(NULL != p_info[i].p_src); + FSP_ASSERT(NULL != p_info[i].p_dest); + FSP_ASSERT(0U == ((uint32_t) p_info[i].p_dest & DTC_PRV_MASK_ALIGN_N_BYTES(p_info[i].size))); + FSP_ASSERT(0U == ((uint32_t) p_info[i].p_src & DTC_PRV_MASK_ALIGN_N_BYTES(p_info[i].size))); + } while (TRANSFER_CHAIN_MODE_DISABLED != p_info[i++].chain_mode); /* Increment 'i' after checking. */ + + return FSP_SUCCESS; +} + +#endif diff --git a/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_spi/r_spi.c b/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_spi/r_spi.c new file mode 100644 index 00000000000..5c92ab7cd61 --- /dev/null +++ b/bsp/renesas/ra6m4-cpk/ra/fsp/src/r_spi/r_spi.c @@ -0,0 +1,1208 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "r_spi.h" +#include "r_spi_cfg.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/** "SPI" in ASCII, used to determine if channel is open. */ +#define SPI_OPEN (0x52535049ULL) + +/** SPI base register access macro. */ +#define SPI_REG(channel) ((R_SPI0_Type *) ((uint32_t) R_SPI0 + \ + ((uint32_t) R_SPI1 - (uint32_t) R_SPI0) * \ + (channel))) + +#define SPI_DTC_MAX_TRANSFER (0x10000) + +#define SPI_DTC_RX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SPI_DTC_TX_TRANSFER_SETTINGS ((TRANSFER_MODE_NORMAL << TRANSFER_SETTINGS_MODE_BITS) | \ + (TRANSFER_SIZE_1_BYTE << TRANSFER_SETTINGS_SIZE_BITS) | \ + (TRANSFER_ADDR_MODE_INCREMENTED << TRANSFER_SETTINGS_SRC_ADDR_BITS) | \ + (TRANSFER_IRQ_END << TRANSFER_SETTINGS_IRQ_BITS) | \ + (TRANSFER_ADDR_MODE_FIXED << TRANSFER_SETTINGS_DEST_ADDR_BITS)) + +#define SPI_CLK_N_DIV_MULTIPLIER (512U) ///< Maximum divider for N=0 +#define SPI_CLK_MAX_DIV (4096U) ///< Maximum SPI CLK divider +#define SPI_CLK_MIN_DIV (2U) ///< Minimum SPI CLK divider + +/* SPCMD0 Bit Field Definitions */ +#define R_SPI0_SPCMD0_CPHA_Pos (0U) ///< Clock Phase setting offset +#define R_SPI0_SPCMD0_CPHA_Msk (1U << R_SPI0_SPCMD0_CPHA_Pos) ///< Clock Phase setting mask +#define R_SPI0_SPCMD0_CPOL_Pos (1U) ///< Clock Polarity setting offset +#define R_SPI0_SPCMD0_CPOL_Msk (1U << R_SPI0_SPCMD0_CPOL_Pos) ///< Clock Polarity setting mask +#define R_SPI0_SPCMD0_BRDV_Pos (2U) ///< Bitrate division setting offset +#define R_SPI0_SPCMD0_BRDV_Msk (0x0003U << R_SPI0_SPCMD0_BRDV_Pos) ///< Bitrate division setting mask +#define R_SPI0_SPCMD0_SSLA_Pos (4U) ///< SSL Signal selection setting offset +#define R_SPI0_SPCMD0_SSLA_Msk (0x0007U << R_SPI0_SPCMD0_SSLA_Pos) ///< SSL Signal selection setting mask +#define R_SPI0_SPCMD0_SSLKP_Pos (7U) ///< SSL Level Keep setting offset +#define R_SPI0_SPCMD0_SSLKP_Msk (1U << R_SPI0_SPCMD0_SSLKP_Pos) ///< SSL Level Keep setting mask +#define R_SPI0_SPCMD0_SPB_Pos (8U) ///< Bit Width setting offset +#define R_SPI0_SPCMD0_SPB_Msk (0x000FU << R_SPI0_SPCMD0_SPB_Pos) ///< Bit Width setting mask +#define R_SPI0_SPCMD0_LSBF_Pos (12U) ///< LSB/MSB setting offset +#define R_SPI0_SPCMD0_LSBF_Msk (1U << R_SPI0_SPCMD0_LSBF_Pos) ///< LSB/MSB setting mask +#define R_SPI0_SPCMD0_SPNDEN_Pos (13) ///< SPI Next-Access Delay Enable setting offset +#define R_SPI0_SPCMD0_SPNDEN_Msk (1U << R_SPI0_SPCMD0_SPNDEN_Pos) ///< SPI Next-Access Delay Enable setting mask +#define R_SPI0_SPCMD0_SLNDEN_Pos (14) ///< SSL Negation Delay Setting Enable setting offset +#define R_SPI0_SPCMD0_SLNDEN_Msk (1U << R_SPI0_SPCMD0_SLNDEN_Pos) ///< SSL Negation Delay Setting Enable setting mask +#define R_SPI0_SPCMD0_SCKDEN_Pos (15) ///< RSPCK Delay Setting Enable setting offset +#define R_SPI0_SPCMD0_SCKDEN_Msk (1U << R_SPI0_SPCMD0_SCKDEN_Pos) ///< RSPCK Delay Setting Enable setting mask + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ +#if defined(__ARMCC_VERSION) || defined(__ICCARM__) +typedef void (BSP_CMSE_NONSECURE_CALL * spi_prv_ns_callback)(spi_callback_args_t * p_args); +#elif defined(__GNUC__) +typedef BSP_CMSE_NONSECURE_CALL void (*volatile spi_prv_ns_callback)(spi_callback_args_t * p_args); +#endif + +/*********************************************************************************************************************** + * Private function declarations + **********************************************************************************************************************/ +static fsp_err_t r_spi_transfer_config(spi_cfg_t const * const p_cfg); +static void r_spi_hw_config(spi_instance_ctrl_t * p_ctrl); +static void r_spi_nvic_config(spi_instance_ctrl_t * p_ctrl); + +static void r_spi_bit_width_config(spi_instance_ctrl_t * p_ctrl); +static void r_spi_start_transfer(spi_instance_ctrl_t * p_ctrl); +static fsp_err_t r_spi_write_read_common(spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width); + +static void r_spi_receive(spi_instance_ctrl_t * p_ctrl); +static void r_spi_transmit(spi_instance_ctrl_t * p_ctrl); +static void r_spi_call_callback(spi_instance_ctrl_t * p_ctrl, spi_event_t event); + +/*********************************************************************************************************************** + * ISR prototypes + **********************************************************************************************************************/ +void spi_rxi_isr(void); +void spi_txi_isr(void); +void spi_tei_isr(void); +void spi_eri_isr(void); + +/*********************************************************************************************************************** + * Private global variables + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Global variables + **********************************************************************************************************************/ + +/* SPI implementation of SPI interface. */ +const spi_api_t g_spi_on_spi = +{ + .open = R_SPI_Open, + .read = R_SPI_Read, + .write = R_SPI_Write, + .writeRead = R_SPI_WriteRead, + .close = R_SPI_Close, + .callbackSet = R_SPI_CallbackSet +}; + +/*******************************************************************************************************************//** + * @addtogroup SPI + * @{ + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * This functions initializes a channel for SPI communication mode. Implements @ref spi_api_t::open. + * + * This function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Configures the pperipheral registers acording to the configuration. + * - Initialize the control structure for use in other @ref SPI_API functions. + * + * @retval FSP_SUCCESS Channel initialized successfully. + * @retval FSP_ERR_ALREADY_OPEN Instance was already initialized. + * @retval FSP_ERR_ASSERTION An invalid argument was given in the configuration structure. + * @retval FSP_ERR_UNSUPPORTED A requested setting is not possible on this device with the current build + * configuration. + * @retval FSP_ERR_IP_CHANNEL_NOT_PRESENT The channel number is invalid. + * @return See @ref RENESAS_ERROR_CODES or functions called by this function for other possible return codes. This + * function calls: @ref transfer_api_t::open + * @note This function is reentrant. + **********************************************************************************************************************/ +fsp_err_t R_SPI_Open (spi_ctrl_t * p_api_ctrl, spi_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl; + +#if SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); + FSP_ASSERT(NULL != p_cfg); + FSP_ASSERT(NULL != p_cfg->p_callback); + FSP_ASSERT(NULL != p_cfg->p_extend); + FSP_ERROR_RETURN(BSP_FEATURE_SPI_MAX_CHANNEL > p_cfg->channel, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ASSERT(p_cfg->rxi_irq >= 0); + FSP_ASSERT(p_cfg->txi_irq >= 0); + FSP_ASSERT(p_cfg->tei_irq >= 0); + FSP_ASSERT(p_cfg->eri_irq >= 0); + + /* CPHA=0 is not supported in slave mode because of hardware limitations. Reference section 38.3.10.2(3) "Slave + * mode operation" in the RA6M3 manual R01UH0886EJ0100. */ + if (SPI_MODE_SLAVE == p_cfg->operating_mode) + { + FSP_ERROR_RETURN(SPI_CLK_PHASE_EDGE_EVEN == p_cfg->clk_phase, FSP_ERR_UNSUPPORTED); + } + + #if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 0 || SPI_TRANSMIT_FROM_RXI_ISR == 1 + spi_extended_cfg_t * p_extend = (spi_extended_cfg_t *) p_cfg->p_extend; + #endif + #if SPI_TRANSMIT_FROM_RXI_ISR == 1 + + /* Half Duplex - Transmit Only mode is not supported when transmit interrupt is handled in the RXI ISR. */ + FSP_ERROR_RETURN(p_extend->spi_comm != SPI_COMMUNICATION_TRANSMIT_ONLY, FSP_ERR_UNSUPPORTED); + + /* When the TXI Interrupt is handled in the RXI ISR, a TX DTC instance must be present if there is a + * RX DTC instance present otherwise the TXI Interrupts will not be processed. */ + if (p_cfg->p_transfer_rx) + { + FSP_ERROR_RETURN(0 != p_cfg->p_transfer_tx, FSP_ERR_UNSUPPORTED); + } + #endif + + #if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 0 + if ((SPI_MODE_MASTER == p_cfg->operating_mode)) + { + /* 4-Wire Mode is not supported in master mode on devices without SSL_LEVEL_KEEP */ + FSP_ERROR_RETURN(SPI_SSL_MODE_SPI != p_extend->spi_clksyn, FSP_ERR_UNSUPPORTED); + } + #endif +#endif + + /* Configure transfers if they are provided in p_cfg. */ + err = r_spi_transfer_config(p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + /* Get the register address of the channel. */ + p_ctrl->p_cfg = p_cfg; + p_ctrl->p_callback = p_cfg->p_callback; + p_ctrl->p_context = p_cfg->p_context; + p_ctrl->p_callback_memory = NULL; + + p_ctrl->p_regs = SPI_REG(p_ctrl->p_cfg->channel); + + /* Configure hardware registers according to the r_spi_api configuration structure. */ + r_spi_hw_config(p_ctrl); + + /* Enable interrupts in NVIC. */ + r_spi_nvic_config(p_ctrl); + + p_ctrl->open = SPI_OPEN; + + return err; +} + +/*******************************************************************************************************************//** + * This function receives data from a SPI device. Implements @ref spi_api_t::read. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI read operation. + * + * @retval FSP_SUCCESS Read operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control or destination parameters or transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + **********************************************************************************************************************/ +fsp_err_t R_SPI_Read (spi_ctrl_t * const p_api_ctrl, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + return r_spi_write_read_common(p_api_ctrl, NULL, p_dest, length, bit_width); +} + +/*******************************************************************************************************************//** + * This function transmits data to a SPI device using the TX Only Communications Operation Mode. + * Implements @ref spi_api_t::write. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI write operation. + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control or source parameters or transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + **********************************************************************************************************************/ +fsp_err_t R_SPI_Write (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + return r_spi_write_read_common(p_api_ctrl, p_src, NULL, length, bit_width); +} + +/*******************************************************************************************************************//** + * This function simultaneously transmits and receive data. Implements @ref spi_api_t::writeRead. + * + * The function performs the following tasks: + * - Performs parameter checking and processes error conditions. + * - Sets up the instance to complete a SPI writeRead operation. + * + * @retval FSP_SUCCESS Write operation successfully completed. + * @retval FSP_ERR_ASSERTION NULL pointer to control, source or destination parameters or + * transfer length is zero. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + *********************************************************************************************************************/ +fsp_err_t R_SPI_WriteRead (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ +#if SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(p_src != NULL); + FSP_ASSERT(p_dest != NULL); +#endif + + return r_spi_write_read_common(p_api_ctrl, p_src, p_dest, length, bit_width); +} + +/*******************************************************************************************************************//** + * Updates the user callback and has option of providing memory for callback structure. + * Implements spi_api_t::callbackSet + * + * @retval FSP_SUCCESS Callback updated successfully. + * @retval FSP_ERR_ASSERTION A required pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The control block has not been opened. + * @retval FSP_ERR_NO_CALLBACK_MEMORY p_callback is non-secure and p_callback_memory is either secure or NULL. + **********************************************************************************************************************/ +fsp_err_t R_SPI_CallbackSet (spi_ctrl_t * const p_api_ctrl, + void ( * p_callback)(spi_callback_args_t *), + void const * const p_context, + spi_callback_args_t * const p_callback_memory) +{ + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl; + +#if (SPI_CFG_PARAM_CHECKING_ENABLE) + FSP_ASSERT(p_ctrl); + FSP_ASSERT(p_callback); + FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + +#if BSP_TZ_SECURE_BUILD + + /* Get security state of p_callback */ + bool callback_is_secure = + (NULL == cmse_check_address_range((void *) p_callback, sizeof(void *), CMSE_AU_NONSECURE)); + + #if SPI_CFG_PARAM_CHECKING_ENABLE + + /* In secure projects, p_callback_memory must be provided in non-secure space if p_callback is non-secure */ + spi_callback_args_t * const p_callback_memory_checked = cmse_check_pointed_object(p_callback_memory, + CMSE_AU_NONSECURE); + FSP_ERROR_RETURN(callback_is_secure || (NULL != p_callback_memory_checked), FSP_ERR_NO_CALLBACK_MEMORY); + #endif +#endif + + /* Store callback and context */ +#if BSP_TZ_SECURE_BUILD + p_ctrl->p_callback = callback_is_secure ? p_callback : + (void (*)(spi_callback_args_t *))cmse_nsfptr_create(p_callback); +#else + p_ctrl->p_callback = p_callback; +#endif + p_ctrl->p_context = p_context; + p_ctrl->p_callback_memory = p_callback_memory; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * This function manages the closing of a channel by the following task. Implements @ref spi_api_t::close. + * + * Disables SPI operations by disabling the SPI bus. + * - Disables the SPI peripheral. + * - Disables all the associated interrupts. + * - Update control structure so it will not work with @ref SPI_API functions. + * + * @retval FSP_SUCCESS Channel successfully closed. + * @retval FSP_ERR_ASSERTION A required pointer argument is NULL. + * @retval FSP_ERR_NOT_OPEN The channel has not been opened. Open the channel first. + **********************************************************************************************************************/ +fsp_err_t R_SPI_Close (spi_ctrl_t * const p_api_ctrl) +{ + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl; + +#if SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + p_ctrl->open = 0; + +#if SPI_DTC_SUPPORT_ENABLE == 1 + if (NULL != p_ctrl->p_cfg->p_transfer_rx) + { + p_ctrl->p_cfg->p_transfer_rx->p_api->close(p_ctrl->p_cfg->p_transfer_rx->p_ctrl); + } + + if (NULL != p_ctrl->p_cfg->p_transfer_tx) + { + p_ctrl->p_cfg->p_transfer_tx->p_api->close(p_ctrl->p_cfg->p_transfer_tx->p_ctrl); + } +#endif + + /* Disable interrupts in NVIC. */ + R_BSP_IrqDisable(p_ctrl->p_cfg->txi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->rxi_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->tei_irq); + R_BSP_IrqDisable(p_ctrl->p_cfg->eri_irq); + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0U; + + /* Clear the status register. */ + + /* The status register must be read before cleared. Reference section 38.2.4 SPI Status Register (SPSR) in the + * RA6M3 manual R01UH0886EJ0100. */ + p_ctrl->p_regs->SPSR; + p_ctrl->p_regs->SPSR = 0; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Calculates the SPBR register value and the BRDV bits for a desired bitrate. + * If the desired bitrate is faster than the maximum bitrate, than the bitrate is set to the + * maximum bitrate. If the desired bitrate is slower than the minimum bitrate, than an error is returned. + * + * @param[in] bitrate Desired bitrate + * @param[out] spck_div Memory location to store bitrate register settings. + * + * @retval FSP_SUCCESS Valid spbr and brdv values were calculated + * @retval FSP_ERR_UNSUPPORTED Bitrate is not achievable + **********************************************************************************************************************/ +fsp_err_t R_SPI_CalculateBitrate (uint32_t bitrate, rspck_div_setting_t * spck_div) +{ + /* desired_divider = Smallest integer greater than or equal to SPI_CLK / bitrate. */ + uint32_t desired_divider = (R_FSP_SystemClockHzGet(BSP_FEATURE_SPI_CLK) + bitrate - 1) / bitrate; + + /* Can't achieve bitrate slower than desired. */ + if (desired_divider > SPI_CLK_MAX_DIV) + { + return FSP_ERR_UNSUPPORTED; + } + + if (desired_divider < SPI_CLK_MIN_DIV) + { + /* Configure max bitrate (SPI_CLK / 2) */ + spck_div->brdv = 0; + spck_div->spbr = 0; + + return FSP_SUCCESS; + } + + /* + * Possible SPI_CLK dividers for values of N: + * N = 0; div = [2,4,6,..,512] + * N = 1; div = [4,8,12,..,1024] + * N = 2; div = [8,16,32,..,2048] + * N = 3; div = [16,32,64,..,4096] + */ + uint8_t i; + for (i = 0; i < 4; i++) + { + /* Select smallest value for N possible. */ + + /* div <= 512; N = 0 + * 512 < div <= 1024; N=1 + * ... + */ + if (desired_divider <= (SPI_CLK_N_DIV_MULTIPLIER << i)) + { + break; + } + } + + spck_div->brdv = i & 0x03U; + + /* + * desired_divider = 2 * (spbr + 1) * 2^i. + * + * With desired_divider and i known, solve for spbr. + * + * spbr = SPI_CLK_DIV / (2 * 2^i) - 1 + */ + uint32_t spbr_divisor = (2U * (1U << i)); + + /* spbr = (Smallest integer greater than or equal to SPI_CLK_DIV / (2 * 2^i)) - 1. */ + spck_div->spbr = (uint8_t) (((desired_divider + spbr_divisor - 1U) / spbr_divisor) - 1U) & UINT8_MAX; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup SPI) + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Private Functions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Configure the given transfer instances for receiving and transmitting data without CPU intervention. + * + * @param p_cfg Configuration structure with references to receive and transmit transfer instances. + * + * @retval FSP_SUCCESS The given transfer instances were configured successfully. + * @return See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally + * calls @ref transfer_api_t::open. + **********************************************************************************************************************/ +static fsp_err_t r_spi_transfer_config (spi_cfg_t const * const p_cfg) +{ + fsp_err_t err = FSP_SUCCESS; + +#if SPI_DTC_SUPPORT_ENABLE == 1 + const transfer_instance_t * p_transfer_tx = p_cfg->p_transfer_tx; + void * p_spdr = (void *) &(SPI_REG(p_cfg->channel)->SPDR); + if (p_transfer_tx) + { + p_transfer_tx->p_cfg->p_info->transfer_settings_word = SPI_DTC_TX_TRANSFER_SETTINGS; + p_transfer_tx->p_cfg->p_info->p_dest = p_spdr; + + err = p_transfer_tx->p_api->open(p_transfer_tx->p_ctrl, p_transfer_tx->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + const transfer_instance_t * p_transfer_rx = p_cfg->p_transfer_rx; + if (p_transfer_rx) + { + p_transfer_rx->p_cfg->p_info->transfer_settings_word = SPI_DTC_RX_TRANSFER_SETTINGS; + p_transfer_rx->p_cfg->p_info->p_src = p_spdr; + + err = p_transfer_rx->p_api->open(p_transfer_rx->p_ctrl, p_transfer_rx->p_cfg); + + if ((FSP_SUCCESS != err) && p_transfer_tx) + { + p_transfer_tx->p_api->close(p_transfer_tx->p_ctrl); + } + } + +#else + FSP_PARAMETER_NOT_USED(p_cfg); +#endif + + return err; +} + +/*******************************************************************************************************************//** + * Hardware configuration for settings given by the configuration structure. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_hw_config (spi_instance_ctrl_t * p_ctrl) +{ + uint32_t spcr = 0; + uint32_t sslp = 0; + uint32_t sppcr = 0; + uint32_t spcr2 = 0; + uint32_t spckd = 0; + uint32_t sslnd = 0; + uint32_t spnd = 0; + uint32_t spcmd0 = 0; + uint32_t spdcr2 = 0; + + /* Enable Receive Buffer Full interrupt. */ + spcr |= R_SPI0_SPCR_SPRIE_Msk; + + /* The TXI interrupt is not needed when TRANSMIT_FROM_RXI_ISR optimization is enabled. */ +#if SPI_TRANSMIT_FROM_RXI_ISR == 0 + + /* Enable Transmit Buffer Empty interrupt. */ + spcr |= R_SPI0_SPCR_SPTIE_Msk; +#endif + + /* Enable Error interrupt. */ + spcr |= R_SPI0_SPCR_SPEIE_Msk; + + /* Configure Master Mode setting. */ + spcr |= (uint32_t) (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) << R_SPI0_SPCR_MSTR_Pos; + + /* Enable SCK Auto Stop setting in order to prevent RX Overflow in Master Mode */ + spcr2 |= (uint32_t) (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) << R_SPI0_SPCR2_SCKASE_Pos; + + /* Configure CPHA setting. */ + spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_phase << R_SPI0_SPCMD0_CPHA_Pos; + + /* Configure CPOL setting. */ + spcmd0 |= (uint32_t) p_ctrl->p_cfg->clk_polarity << R_SPI0_SPCMD0_CPOL_Pos; + + /* Configure Bit Order (MSB,LSB) */ + spcmd0 |= (uint32_t) p_ctrl->p_cfg->bit_order << R_SPI0_SPCMD0_LSBF_Pos; + + if (p_ctrl->p_cfg->p_transfer_tx) + { + /* Transmit Buffer Empty IRQ must be enabled for DTC even if TRANSMIT_FROM_RXI is enabled. */ + spcr |= R_SPI0_SPCR_SPTIE_Msk; + } + + spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + + if (SPI_SSL_MODE_SPI == p_extend->spi_clksyn) + { +#if BSP_FEATURE_SPI_HAS_SSL_LEVEL_KEEP == 1 + + /* Configure SSL Level Keep Setting. */ + spcmd0 |= R_SPI0_SPCMD0_SSLKP_Msk; +#endif + + /* Configure 4-Wire Mode Setting. */ + spcr &= ~R_SPI0_SPCR_SPMS_Msk; + } + else + { + /* Configure 3-Wire Mode Setting. */ + spcr |= R_SPI0_SPCR_SPMS_Msk; + } + + /* Configure Full Duplex or TX Only Setting. */ + spcr &= (uint32_t) ~(p_extend->spi_comm << R_SPI0_SPCR_SPRIE_Pos), + spcr |= + (uint32_t) ((p_extend->spi_comm << R_SPI0_SPCR_TXMD_Pos) | + (p_extend->spi_comm << R_SPI0_SPCR_SPTIE_Pos)); + + /* Configure SSLn polarity setting. */ + sslp &= ~0x0FU; + sslp |= (uint32_t) p_extend->ssl_polarity << p_extend->ssl_select; + + /* Configure SSLn setting. (SSL0, SSL1, SSL2, SSL3)*/ + spcmd0 &= ~R_SPI0_SPCMD0_SSLA_Msk; + spcmd0 |= (uint32_t) p_extend->ssl_select << R_SPI0_SPCMD0_SSLA_Pos; + + if (SPI_MOSI_IDLE_VALUE_FIXING_DISABLE != p_extend->mosi_idle) + { + /* Enable mosi value fixing */ + sppcr |= R_SPI0_SPPCR_MOIFE_Msk; + + if (SPI_MOSI_IDLE_VALUE_FIXING_HIGH == p_extend->mosi_idle) + { + sppcr |= R_SPI0_SPPCR_MOIFV_Msk; + } + } + + if (SPI_PARITY_MODE_DISABLE != p_extend->parity) + { + /* Enable Parity Mode. */ + spcr2 |= R_SPI0_SPCR2_SPPE_Msk; + + if (SPI_PARITY_MODE_ODD == p_extend->parity) + { + /* Configure ODD Parity Setting. */ + spcr2 |= R_SPI0_SPCR2_SPOE_Msk; + } + } + + /* Configure byte swapping for 16/32-Bit mode. */ + spdcr2 |= p_extend->byte_swap; + + /* Configure the Bit Rate Division Setting */ + spcmd0 |= (uint32_t) p_extend->spck_div.brdv << R_SPI0_SPCMD0_BRDV_Pos; + + /* Enable all delay settings. */ + if (SPI_MODE_MASTER == p_ctrl->p_cfg->operating_mode) + { + /* Note that disabling delay settings is same as setting delay to 1. */ + spcmd0 |= (uint32_t) R_SPI0_SPCMD0_SPNDEN_Msk | R_SPI0_SPCMD0_SLNDEN_Msk | R_SPI0_SPCMD0_SCKDEN_Msk; + + spckd = p_extend->spck_delay; + sslnd = p_extend->ssl_negation_delay; + spnd = p_extend->next_access_delay; + } + + /* Power up the SPI module. */ + R_BSP_MODULE_START(FSP_IP_SPI, p_ctrl->p_cfg->channel); + + /* Clear the status register. */ + + /* The status register must be read before cleared. Reference section 38.2.4 SPI Status Register (SPSR) in the + * RA6M3 manual R01UH0886EJ0100. */ + p_ctrl->p_regs->SPSR; + p_ctrl->p_regs->SPSR = 0; + + /* Write registers */ + p_ctrl->p_regs->SPCR = (uint8_t) spcr; + p_ctrl->p_regs->SSLP = (uint8_t) sslp; + p_ctrl->p_regs->SPPCR = (uint8_t) sppcr; + p_ctrl->p_regs->SPBR = p_extend->spck_div.spbr; + p_ctrl->p_regs->SPCKD = (uint8_t) spckd; + p_ctrl->p_regs->SSLND = (uint8_t) sslnd; + p_ctrl->p_regs->SPND = (uint8_t) spnd; + p_ctrl->p_regs->SPCR2 = (uint8_t) spcr2; + p_ctrl->p_regs->SPCMD[0] = (uint16_t) spcmd0; + p_ctrl->p_regs->SPDCR2 = (uint8_t) spdcr2; + +#if BSP_FEATURE_SPI_HAS_SPCR3 == 1 + p_ctrl->p_regs->SPCR3 = R_SPI0_SPCR3_CENDIE_Msk; +#endif +} + +/*******************************************************************************************************************//** + * Enable Receive Buffer Full, Transmit Buffer Empty, and Error Interrupts in the NVIC. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_nvic_config (spi_instance_ctrl_t * p_ctrl) +{ + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->txi_irq, p_ctrl->p_cfg->txi_ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->rxi_irq, p_ctrl->p_cfg->rxi_ipl, p_ctrl); + R_BSP_IrqCfgEnable(p_ctrl->p_cfg->eri_irq, p_ctrl->p_cfg->eri_ipl, p_ctrl); + + R_BSP_IrqCfg(p_ctrl->p_cfg->tei_irq, p_ctrl->p_cfg->tei_ipl, p_ctrl); + + /* Note tei_irq is not enabled until the last data frame is transfered. */ +} + +/*******************************************************************************************************************//** + * Setup the bit width configuration for a transfer. + * + * @param[in] p_ctrl pointer to control structure. + * + * Note: For 8-Bit wide data frames, the devices require the SPBYT bit to enable byte level access to the + * data register. Although this register is not documented in some MCU hardware manuals, it does seem to be available + * on all of them. + **********************************************************************************************************************/ +static void r_spi_bit_width_config (spi_instance_ctrl_t * p_ctrl) +{ + uint32_t spdcr = p_ctrl->p_regs->SPDCR; + uint32_t spcmd0 = p_ctrl->p_regs->SPCMD[0]; + + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths of 20, 24 or 32 bits */ + { + /* Configure Word access to data register. */ + spdcr &= ~R_SPI0_SPDCR_SPBYT_Msk; + spdcr |= R_SPI0_SPDCR_SPLW_Msk; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width of 8 bits*/ + { + /* Set SPBYT so 8bit transfer works with the DTC/DMAC. */ + spdcr |= R_SPI0_SPDCR_SPBYT_Msk; + } + else /* Bit Widths of 9, 10, 11, 12, 13, 14, 15 or 16 bits */ + { + /* Configure Half-Word access to data register. */ + spdcr &= ~(R_SPI0_SPDCR_SPBYT_Msk | R_SPI0_SPDCR_SPLW_Msk); + } + + /* Configure data length based on the selected bit width . */ + uint32_t bit_width = p_ctrl->bit_width; + if (bit_width > SPI_BIT_WIDTH_16_BITS) + { + bit_width = ((bit_width + 1) >> 2) - 5; + } + + spcmd0 &= ~R_SPI0_SPCMD0_SPB_Msk; + spcmd0 |= bit_width << R_SPI0_SPCMD0_SPB_Pos; + + p_ctrl->p_regs->SPDCR = (uint8_t) spdcr; + p_ctrl->p_regs->SPCMD[0] = (uint16_t) spcmd0; +} + +/*******************************************************************************************************************//** + * Initiates a SPI transfer by setting the SPE bit in SPCR. + * + * @param[in] p_ctrl pointer to control structure. + * + * Note: When not using the DTC to transmit, this function pre-loads the SPI shift-register and shift-register-buffer + * instead of waiting for the transmit buffer empty interrupt. This is required when transmitting from the + * Receive Buffer Full interrupt, but it does not interfere with transmitting when using the transmit buffer empty + * interrupt. + **********************************************************************************************************************/ +static void r_spi_start_transfer (spi_instance_ctrl_t * p_ctrl) +{ +#if SPI_TRANSMIT_FROM_RXI_ISR == 1 + if (!p_ctrl->p_cfg->p_transfer_tx) + { + /* Handle the first two transmit empty events here because transmit interrupt may not be enabled. */ + + /* Critical section required so that the txi interrupt can be handled here instead of in the ISR. */ + FSP_CRITICAL_SECTION_DEFINE; + FSP_CRITICAL_SECTION_ENTER; + + /* Enable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 1; + + /* Must call transmit to kick off transfer when transmitting from rxi ISR. */ + r_spi_transmit(p_ctrl); ///< First data immediately copied into the SPI shift register. + + /* Second transmit significantly improves slave mode performance. */ + r_spi_transmit(p_ctrl); ///< Second data copied into the SPI transmit buffer. + + /* Must clear the txi IRQ status (The interrupt was handled here). */ + R_BSP_IrqEnable(p_ctrl->p_cfg->txi_irq); + + FSP_CRITICAL_SECTION_EXIT; + } + else + { + /* Enable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 1; + } + +#else + + /* Enable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 1; +#endif +} + +/*******************************************************************************************************************//** + * Configures the driver state and initiates a SPI transfer for all modes of operation. + * + * @param[in] p_api_ctrl pointer to control structure. + * @param p_src Buffer to transmit data from. + * @param p_dest Buffer to store received data in. + * @param[in] length Number of transfers + * @param[in] bit_width Data frame size (8-Bit, 16-Bit, 32-Bit) + * + * @retval FSP_SUCCESS Transfer was started successfully. + * @retval FSP_ERR_ASSERTION An argument is invalid. + * @retval FSP_ERR_NOT_OPEN The instance has not been initialized. + * @retval FSP_ERR_IN_USE A transfer is already in progress. + * @return See @ref RENESAS_ERROR_CODES for other possible return codes. This function internally + * calls @ref transfer_api_t::reconfigure. + **********************************************************************************************************************/ +static fsp_err_t r_spi_write_read_common (spi_ctrl_t * const p_api_ctrl, + void const * p_src, + void * p_dest, + uint32_t const length, + spi_bit_width_t const bit_width) +{ + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) p_api_ctrl; + +#if SPI_CFG_PARAM_CHECKING_ENABLE + FSP_ASSERT(NULL != p_ctrl); + FSP_ERROR_RETURN(SPI_OPEN == p_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(p_src || p_dest); + FSP_ASSERT(0 != length); + if (p_ctrl->p_cfg->p_transfer_tx || p_ctrl->p_cfg->p_transfer_rx) + { + FSP_ASSERT(length <= SPI_DTC_MAX_TRANSFER); + } + + /* Reject bit width settings not compatible with R_SPI */ + FSP_ASSERT(!((bit_width < SPI_BIT_WIDTH_8_BITS) || + ((bit_width > SPI_BIT_WIDTH_16_BITS) && ((bit_width + 1) & 0x3)) || + (bit_width == SPI_BIT_WIDTH_28_BITS))); +#endif + + FSP_ERROR_RETURN(0 == (p_ctrl->p_regs->SPCR & R_SPI0_SPCR_SPE_Msk), FSP_ERR_IN_USE); + + p_ctrl->p_tx_data = p_src; + p_ctrl->p_rx_data = p_dest; + p_ctrl->tx_count = 0; + p_ctrl->rx_count = 0; + p_ctrl->count = length; + p_ctrl->bit_width = bit_width; + +#if SPI_DTC_SUPPORT_ENABLE == 1 + if (p_ctrl->p_cfg->p_transfer_rx) + { + /* When the rxi interrupt is called, all transfers will be finished. */ + p_ctrl->rx_count = length; + + /* Configure the receive DMA instance. */ + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->size = TRANSFER_SIZE_4_BYTE; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->size = TRANSFER_SIZE_1_BYTE; + } + else + { + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->size = TRANSFER_SIZE_2_BYTE; + } + + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->length = (uint16_t) length; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = p_dest; + + if (NULL == p_dest) + { + static uint32_t dummy_rx; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->dest_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info->p_dest = &dummy_rx; + } + + fsp_err_t err = p_ctrl->p_cfg->p_transfer_rx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_rx->p_ctrl, + p_ctrl->p_cfg->p_transfer_rx->p_cfg->p_info); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } + + if (p_ctrl->p_cfg->p_transfer_tx) + { + /* When the txi interrupt is called, all transfers will be finished. */ + p_ctrl->tx_count = length; + + /* Configure the transmit DMA instance. */ + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->size = TRANSFER_SIZE_4_BYTE; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->size = TRANSFER_SIZE_1_BYTE; + } + else + { + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->size = TRANSFER_SIZE_2_BYTE; + } + + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->length = (uint16_t) length; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = p_src; + + if (NULL == p_src) + { + static uint32_t dummy_tx = 0; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->src_addr_mode = TRANSFER_ADDR_MODE_FIXED; + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info->p_src = &dummy_tx; + } + + fsp_err_t err = p_ctrl->p_cfg->p_transfer_tx->p_api->reconfigure(p_ctrl->p_cfg->p_transfer_tx->p_ctrl, + p_ctrl->p_cfg->p_transfer_tx->p_cfg->p_info); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + } +#endif + + r_spi_bit_width_config(p_ctrl); + r_spi_start_transfer(p_ctrl); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Copy configured bit width from the SPI data register to the current rx data location. + * If the receive buffer is NULL, just read the SPI data register. + * If the total transfer length has already been received than do nothing. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_receive (spi_instance_ctrl_t * p_ctrl) +{ + uint32_t rx_count = p_ctrl->rx_count; + if (rx_count == p_ctrl->count) + { + return; + } + + if (0 == p_ctrl->p_rx_data) + { + /* Read the received data but do nothing with it. */ + p_ctrl->p_regs->SPDR; + } + else + { + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths of 20, 24 or 32 bits */ + { + ((uint32_t *) (p_ctrl->p_rx_data))[rx_count] = p_ctrl->p_regs->SPDR; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width of 8 bits*/ + { + ((uint8_t *) (p_ctrl->p_rx_data))[rx_count] = p_ctrl->p_regs->SPDR_BY; + } + else /* Bit Widths of 9, 10, 11, 12, 13, 14, 15 or 16 bits */ + { + ((uint16_t *) (p_ctrl->p_rx_data))[rx_count] = p_ctrl->p_regs->SPDR_HA; + } + } + + p_ctrl->rx_count = rx_count + 1; +} + +/*******************************************************************************************************************//** + * Copy configured bit width from the current tx data location into the SPI data register. + * If the transmit buffer is NULL, than write zero to the SPI data register. + * If the total transfer length has already been transmitted than do nothing. + * + * @param[in] p_ctrl pointer to control structure. + **********************************************************************************************************************/ +static void r_spi_transmit (spi_instance_ctrl_t * p_ctrl) +{ + uint32_t tx_count = p_ctrl->tx_count; + if (tx_count == p_ctrl->count) + { + return; + } + + if (0 == p_ctrl->p_tx_data) + { + /* Transmit zero if no tx buffer present. */ + p_ctrl->p_regs->SPDR = 0; + } + else + { + if (SPI_BIT_WIDTH_16_BITS < p_ctrl->bit_width) /* Bit Widths of 20, 24 or 32 bits */ + { + p_ctrl->p_regs->SPDR = ((uint32_t *) p_ctrl->p_tx_data)[tx_count]; + } + else if (SPI_BIT_WIDTH_8_BITS >= p_ctrl->bit_width) /* Bit Width of 8 bits*/ + { + p_ctrl->p_regs->SPDR_BY = ((uint8_t *) p_ctrl->p_tx_data)[tx_count]; + } + else /* Bit Widths of 9, 10, 11, 12, 13, 14, 15 or 16 bits */ + { + p_ctrl->p_regs->SPDR_HA = ((uint16_t *) p_ctrl->p_tx_data)[tx_count]; + } + } + + p_ctrl->tx_count = tx_count + 1; +} + +/*******************************************************************************************************************//** + * Calls user callback. + * + * @param[in] p_ctrl Pointer to SPI instance control block + * @param[in] event Event code + **********************************************************************************************************************/ +static void r_spi_call_callback (spi_instance_ctrl_t * p_ctrl, spi_event_t event) +{ + spi_callback_args_t args; + + /* Store callback arguments in memory provided by user if available. This allows callback arguments to be + * stored in non-secure memory so they can be accessed by a non-secure callback function. */ + spi_callback_args_t * p_args = p_ctrl->p_callback_memory; + if (NULL == p_args) + { + /* Store on stack */ + p_args = &args; + } + else + { + /* Save current arguments on the stack in case this is a nested interrupt. */ + args = *p_args; + } + + p_args->channel = p_ctrl->p_cfg->channel; + p_args->event = event; + p_args->p_context = p_ctrl->p_context; + +#if BSP_TZ_SECURE_BUILD + + /* p_callback can point to a secure function or a non-secure function. */ + if (!cmse_is_nsfptr(p_ctrl->p_callback)) + { + /* If p_callback is secure, then the project does not need to change security state. */ + p_ctrl->p_callback(p_args); + } + else + { + /* If p_callback is Non-secure, then the project must change to Non-secure state in order to call the callback. */ + spi_prv_ns_callback p_callback = (spi_prv_ns_callback) (p_ctrl->p_callback); + p_callback(p_args); + } + +#else + + /* If the project is not Trustzone Secure, then it will never need to change security state in order to call the callback. */ + p_ctrl->p_callback(p_args); +#endif + if (NULL != p_ctrl->p_callback_memory) + { + /* Restore callback memory in case this is a nested interrupt. */ + *p_ctrl->p_callback_memory = args; + } +} + +/*******************************************************************************************************************//** + * ISR called when data is loaded into SPI data register from the shift register. + **********************************************************************************************************************/ +void spi_rxi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + r_spi_receive(p_ctrl); + +#if SPI_TRANSMIT_FROM_RXI_ISR == 1 + + /* It is a little faster to handle the transmit buffer empty event in the receive buffer full ISR. + * Note that this is only possible when the instance is not using a transfer instance to receive data. */ + r_spi_transmit(p_ctrl); +#endif + + if (p_ctrl->rx_count == p_ctrl->count) + { + /* If the transmit and receive ISRs are too slow to keep up at high bitrates, + * the hardware will generate an interrupt before all of the transfers are completed. + * By enabling the transfer end ISR here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * ISR called when data is copied from the SPI data register into the SPI shift register. + **********************************************************************************************************************/ +void spi_txi_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + +#if SPI_TRANSMIT_FROM_RXI_ISR == 0 + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + spi_extended_cfg_t * p_extend = ((spi_extended_cfg_t *) p_ctrl->p_cfg->p_extend); + if (p_extend && (SPI_COMMUNICATION_TRANSMIT_ONLY == p_extend->spi_comm)) + { + /* Only enable the transfer end ISR if there are no receive buffer full interrupts expected to be handled + * after this interrupt. */ + if (p_ctrl->tx_count == p_ctrl->count - 1) + { + /* If the transmit and receive ISRs are too slow to keep up at high bitrates, + * the hardware will generate an interrupt before all of the transfers are completed. + * By enabling the transfer end ISR here, all of the transfers are guaranteed to be completed. */ + R_BSP_IrqEnable(p_ctrl->p_cfg->tei_irq); + } + else if (p_ctrl->p_cfg->p_transfer_tx) + { + /* If DMA is used to transmit data, enable the interrupt after all the data has been transfered, but do not + * clear the IRQ Pending Bit. */ + R_BSP_IrqEnableNoClear(p_ctrl->p_cfg->tei_irq); + } + else + { + } + } + + /* Transmit happens after checking if the last transfer has been written to the transmit buffer in order + * to ensure that the end interrupt is not enabled while there is data still in the transmit buffer. */ + r_spi_transmit(p_ctrl); +#endif + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * ISR called when the SPI peripheral transitions from the transferring state to the IDLE state. + **********************************************************************************************************************/ +void spi_tei_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + if ((0 == p_ctrl->p_regs->SPSR_b.IDLNF) || (SPI_MODE_SLAVE == p_ctrl->p_cfg->operating_mode)) + { + R_BSP_IrqDisable(irq); + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0; + + /* Signal that a transfer has completed. */ + r_spi_call_callback(p_ctrl, SPI_EVENT_TRANSFER_COMPLETE); + } + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/*******************************************************************************************************************//** + * ISR called in the event that an error occurs (Ex: RX_OVERFLOW). + **********************************************************************************************************************/ +void spi_eri_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE; + + IRQn_Type irq = R_FSP_CurrentIrqGet(); + spi_instance_ctrl_t * p_ctrl = (spi_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + /* Disable the SPI Transfer. */ + p_ctrl->p_regs->SPCR_b.SPE = 0; + + /* Read the status register. */ + uint8_t status = p_ctrl->p_regs->SPSR; + + /* Clear the status register. */ + p_ctrl->p_regs->SPSR = 0; + + /* Check if the error is a Parity Error. */ + if (R_SPI0_SPSR_PERF_Msk & status) + { + r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_PARITY); + } + + /* Check if the error is a Receive Buffer Overflow Error. */ + if (R_SPI0_SPSR_OVRF_Msk & status) + { + r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_READ_OVERFLOW); + } + + /* Check if the error is a Mode Fault Error. */ + if (R_SPI0_SPSR_MODF_Msk & status) + { + /* Check if the error is a Transmit Buffer Underflow Error. */ + if (R_SPI0_SPSR_UDRF_Msk & status) + { + r_spi_call_callback(p_ctrl, SPI_EVENT_ERR_MODE_UNDERRUN); + } + } + + R_BSP_IrqStatusClear(irq); + + /* Restore context if RTOS is used */ + FSP_CONTEXT_RESTORE; +} + +/* End of file R_SPI. */ diff --git a/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h index 8943340af53..650b0db9f56 100644 --- a/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h +++ b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -76,7 +76,7 @@ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 9) /* IIC0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 11) /* USBFS */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 18) /* SPI1 */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ + (((1 > 0) ? 0U : 1U) << 19) /* SPI0 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 22) /* SCI9 */ | \ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 23) /* SCI8 */ | \ (((1 > 0) ? 0U : 1U) << 24) /* SCI7 */ | \ @@ -138,7 +138,7 @@ #ifndef BSP_TZ_CFG_MSSAR #define BSP_TZ_CFG_MSSAR (\ (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 0) /* ELC */ | \ - (((RA_NOT_DEFINED > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ + (((2 > 0) ? 0U : 1U) << 1) /* DTC_DMAC */ | \ 0xfffffffc) /* Unused */ #endif @@ -244,7 +244,7 @@ #endif /* Set DTCSTSAR if the Secure program uses the DTC. */ -#if RA_NOT_DEFINED == RA_NOT_DEFINED +#if 2 == RA_NOT_DEFINED #define BSP_TZ_CFG_DTC_USED (0U) #else #define BSP_TZ_CFG_DTC_USED (1U) diff --git a/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_dtc_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_dtc_cfg.h new file mode 100644 index 00000000000..21405f96741 --- /dev/null +++ b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_dtc_cfg.h @@ -0,0 +1,6 @@ +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" +#endif /* R_DTC_CFG_H_ */ diff --git a/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_spi_cfg.h b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_spi_cfg.h new file mode 100644 index 00000000000..792e1846680 --- /dev/null +++ b/bsp/renesas/ra6m4-cpk/ra_cfg/fsp_cfg/r_spi_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SPI_CFG_H_ +#define R_SPI_CFG_H_ +#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) + #define SPI_DTC_SUPPORT_ENABLE (1) + #define SPI_TRANSMIT_FROM_RXI_ISR (0) +#endif /* R_SPI_CFG_H_ */ diff --git a/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.c b/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.c index 08248591ea4..cea21b7eb33 100644 --- a/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.c +++ b/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.c @@ -1,5 +1,144 @@ /* generated HAL source file - do not edit */ #include "hal_data.h" +dtc_instance_ctrl_t g_transfer1_ctrl; + +transfer_info_t g_transfer1_info = +{ + .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *) NULL, + .p_src = (void const *) NULL, + .num_blocks = 0, + .length = 0, +}; +const dtc_extended_cfg_t g_transfer1_cfg_extend = +{ + .activation_source = VECTOR_NUMBER_SPI0_RXI, +}; +const transfer_cfg_t g_transfer1_cfg = +{ + .p_info = &g_transfer1_info, + .p_extend = &g_transfer1_cfg_extend, +}; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer1 = +{ + .p_ctrl = &g_transfer1_ctrl, + .p_cfg = &g_transfer1_cfg, + .p_api = &g_transfer_on_dtc +}; +dtc_instance_ctrl_t g_transfer0_ctrl; + +transfer_info_t g_transfer0_info = +{ + .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *) NULL, + .p_src = (void const *) NULL, + .num_blocks = 0, + .length = 0, +}; +const dtc_extended_cfg_t g_transfer0_cfg_extend = +{ + .activation_source = VECTOR_NUMBER_SPI0_TXI, +}; +const transfer_cfg_t g_transfer0_cfg = +{ + .p_info = &g_transfer0_info, + .p_extend = &g_transfer0_cfg_extend, +}; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = +{ + .p_ctrl = &g_transfer0_ctrl, + .p_cfg = &g_transfer0_cfg, + .p_api = &g_transfer_on_dtc +}; +spi_instance_ctrl_t g_spi0_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi0_ext_cfg = +{ + .spi_clksyn = SPI_SSL_MODE_CLK_SYN, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = { + /* Actual calculated bitrate: 12500000. */ .spbr = 3, .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1 + }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi0_cfg = +{ + .channel = 0, + +#if defined(VECTOR_NUMBER_SPI0_RXI) + .rxi_irq = VECTOR_NUMBER_SPI0_RXI, +#else + .rxi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_TXI) + .txi_irq = VECTOR_NUMBER_SPI0_TXI, +#else + .txi_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_TEI) + .tei_irq = VECTOR_NUMBER_SPI0_TEI, +#else + .tei_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_SPI0_ERI) + .eri_irq = VECTOR_NUMBER_SPI0_ERI, +#else + .eri_irq = FSP_INVALID_VECTOR, +#endif + + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi0_P_TRANSFER_TX, + .p_transfer_rx = g_spi0_P_TRANSFER_RX, + .p_callback = spi0_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi0_ext_cfg, +}; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi0 = +{ + .p_ctrl = &g_spi0_ctrl, + .p_cfg = &g_spi0_cfg, + .p_api = &g_spi_on_spi +}; icu_instance_ctrl_t g_external_irq0_ctrl; const external_irq_cfg_t g_external_irq0_cfg = { diff --git a/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.h b/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.h index cf149a31a61..ef3650f45b2 100644 --- a/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.h +++ b/bsp/renesas/ra6m4-cpk/ra_gen/hal_data.h @@ -4,11 +4,51 @@ #include #include "bsp_api.h" #include "common_data.h" +#include "r_dtc.h" +#include "r_transfer_api.h" +#include "r_spi.h" #include "r_icu.h" #include "r_external_irq_api.h" #include "r_sci_uart.h" #include "r_uart_api.h" FSP_HEADER +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi0_callback +void spi0_callback(spi_callback_args_t * p_args); +#endif + + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) + #define g_spi0_P_TRANSFER_TX (NULL) +#else + #define g_spi0_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == g_transfer1) + #define g_spi0_P_TRANSFER_RX (NULL) +#else + #define g_spi0_P_TRANSFER_RX (&g_transfer1) +#endif +#undef RA_NOT_DEFINED /** External IRQ on ICU Instance. */ extern const external_irq_instance_t g_external_irq0; diff --git a/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.c b/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.c index 5bbc4946182..bb38bcfadd7 100644 --- a/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.c +++ b/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.c @@ -9,6 +9,10 @@ [2] = sci_uart_tei_isr, /* SCI7 TEI (Transmit end) */ [3] = sci_uart_eri_isr, /* SCI7 ERI (Receive error) */ [4] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [5] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [6] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [7] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [8] = spi_eri_isr, /* SPI0 ERI (Error) */ }; const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = { @@ -17,5 +21,9 @@ [2] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TEI), /* SCI7 TEI (Transmit end) */ [3] = BSP_PRV_IELS_ENUM(EVENT_SCI7_ERI), /* SCI7 ERI (Receive error) */ [4] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ + [5] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [6] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [7] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [8] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ }; #endif \ No newline at end of file diff --git a/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.h b/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.h index 0da697c477c..7e5be61ea4c 100644 --- a/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.h +++ b/bsp/renesas/ra6m4-cpk/ra_gen/vector_data.h @@ -3,7 +3,7 @@ #define VECTOR_DATA_H /* Number of interrupts allocated */ #ifndef VECTOR_DATA_IRQ_COUNT - #define VECTOR_DATA_IRQ_COUNT (5) + #define VECTOR_DATA_IRQ_COUNT (9) #endif /* ISR prototypes */ void sci_uart_rxi_isr(void); @@ -11,6 +11,10 @@ void sci_uart_tei_isr(void); void sci_uart_eri_isr(void); void r_icu_isr(void); + void spi_rxi_isr(void); + void spi_txi_isr(void); + void spi_tei_isr(void); + void spi_eri_isr(void); /* Vector table allocations */ #define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type) 0) /* SCI7 RXI (Received data full) */ @@ -23,4 +27,12 @@ #define SCI7_ERI_IRQn ((IRQn_Type) 3) /* SCI7 ERI (Receive error) */ #define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type) 4) /* ICU IRQ0 (External pin interrupt 0) */ #define ICU_IRQ0_IRQn ((IRQn_Type) 4) /* ICU IRQ0 (External pin interrupt 0) */ + #define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type) 5) /* SPI0 RXI (Receive buffer full) */ + #define SPI0_RXI_IRQn ((IRQn_Type) 5) /* SPI0 RXI (Receive buffer full) */ + #define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type) 6) /* SPI0 TXI (Transmit buffer empty) */ + #define SPI0_TXI_IRQn ((IRQn_Type) 6) /* SPI0 TXI (Transmit buffer empty) */ + #define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type) 7) /* SPI0 TEI (Transmission complete event) */ + #define SPI0_TEI_IRQn ((IRQn_Type) 7) /* SPI0 TEI (Transmission complete event) */ + #define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type) 8) /* SPI0 ERI (Error) */ + #define SPI0_ERI_IRQn ((IRQn_Type) 8) /* SPI0 ERI (Error) */ #endif /* VECTOR_DATA_H */ \ No newline at end of file diff --git a/bsp/renesas/ra6m4-cpk/rtconfig.h b/bsp/renesas/ra6m4-cpk/rtconfig.h index 80ca686b1c0..269f47875ab 100644 --- a/bsp/renesas/ra6m4-cpk/rtconfig.h +++ b/bsp/renesas/ra6m4-cpk/rtconfig.h @@ -23,8 +23,10 @@ /* kservice optimization */ -#define RT_DEBUG -#define RT_DEBUG_COLOR +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ @@ -36,7 +38,6 @@ /* Memory Management */ -#define RT_PAGE_MAX_ORDER 11 #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP @@ -47,7 +48,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart7" -#define RT_VER_NUM 0x50000 +#define RT_VER_NUM 0x50001 #define RT_USING_HW_ATOMIC #define RT_USING_CPU_FFS #define ARCH_ARM @@ -74,6 +75,9 @@ #define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 +/* DFS: device virtual file system */ + + /* Device Drivers */ #define RT_USING_DEVICE_IPC @@ -82,6 +86,7 @@ #define RT_USING_SERIAL_V2 #define RT_SERIAL_USING_DMA #define RT_USING_PIN +#define RT_USING_SPI /* Using USB */ @@ -190,7 +195,7 @@ /* Arduino libraries */ -/* Projects */ +/* Projects and Demos */ /* Sensors */ @@ -238,6 +243,8 @@ #define BSP_USING_UART7 #define BSP_UART7_RX_BUFSIZE 256 #define BSP_UART7_TX_BUFSIZE 0 +#define BSP_USING_SPI +#define BSP_USING_SPI0 /* Board extended module Drivers */ diff --git a/bsp/renesas/ra6m4-cpk/rtconfig.py b/bsp/renesas/ra6m4-cpk/rtconfig.py index 9565e9fad49..b0cb2c8ab7a 100644 --- a/bsp/renesas/ra6m4-cpk/rtconfig.py +++ b/bsp/renesas/ra6m4-cpk/rtconfig.py @@ -56,6 +56,7 @@ AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -Os' + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' diff --git a/bsp/renesas/ra6m4-iot/.config b/bsp/renesas/ra6m4-iot/.config index 17adf2e9c63..88a440ef128 100644 --- a/bsp/renesas/ra6m4-iot/.config +++ b/bsp/renesas/ra6m4-iot/.config @@ -9,6 +9,7 @@ CONFIG_RT_NAME_MAX=8 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set # CONFIG_RT_USING_SMP is not set CONFIG_RT_ALIGN_SIZE=8 # CONFIG_RT_THREAD_PRIORITY_8 is not set @@ -33,18 +34,10 @@ CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set # CONFIG_RT_KPRINTF_USING_LONGLONG is not set -CONFIG_RT_DEBUG=y -CONFIG_RT_DEBUG_COLOR=y -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y # # Inter-Thread communication @@ -54,12 +47,12 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 # CONFIG_RT_USING_MEMPOOL is not set CONFIG_RT_USING_SMALL_MEM=y # CONFIG_RT_USING_SLAB is not set @@ -83,7 +76,7 @@ CONFIG_RT_USING_DEVICE=y CONFIG_RT_USING_CONSOLE=y CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart6" -CONFIG_RT_VER_NUM=0x50000 +CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set # CONFIG_RT_USING_CACHE is not set CONFIG_RT_USING_HW_ATOMIC=y @@ -117,6 +110,10 @@ CONFIG_FINSH_USING_DESCRIPTION=y # CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set # CONFIG_FINSH_USING_AUTH is not set CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# # CONFIG_RT_USING_DFS is not set # CONFIG_RT_USING_FAL is not set @@ -210,9 +207,11 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set +# CONFIG_RT_USING_RESOURCE_ID is not set # CONFIG_RT_USING_ADT is not set # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +# CONFIG_RT_USING_KTIME is not set # # RT-Thread Utestcases @@ -237,7 +236,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set @@ -438,6 +436,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_HASH_MATCH is not set # CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set # CONFIG_PKG_USING_VOFA_PLUS is not set +# CONFIG_PKG_USING_RT_TRACE is not set # # system packages @@ -509,6 +508,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set # CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set # # peripheral libraries and drivers @@ -593,6 +593,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_FT5426 is not set # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -605,7 +606,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_LKDGUI is not set # CONFIG_PKG_USING_NRF5X_SDK is not set # CONFIG_PKG_USING_NRFX is not set -# CONFIG_PKG_USING_WM_LIBRARIES is not set # # Kendryte SDK @@ -663,14 +663,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_MISAKA_AT24CXX is not set # CONFIG_PKG_USING_MISAKA_RGB_BLING is not set # CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set -# CONFIG_PKG_USING_BL_MCU_SDK is not set # CONFIG_PKG_USING_SOFT_SERIAL is not set # CONFIG_PKG_USING_MB85RS16 is not set # CONFIG_PKG_USING_RFM300 is not set # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # # AI packages @@ -689,7 +692,10 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # Signal Processing and Control Algorithm Packages # # CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set # # miscellaneous packages @@ -736,7 +742,6 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set @@ -761,8 +766,9 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set @@ -909,14 +915,19 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set # # Timing # # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # # Data Processing diff --git a/bsp/renesas/ra6m4-iot/SConstruct b/bsp/renesas/ra6m4-iot/SConstruct index d00d0dbeaac..67511e3048a 100644 --- a/bsp/renesas/ra6m4-iot/SConstruct +++ b/bsp/renesas/ra6m4-iot/SConstruct @@ -21,6 +21,7 @@ DefaultEnvironment(tools=[]) env = Environment(tools = ['mingw'], AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS, + CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS, AR = rtconfig.AR, ARFLAGS = '-rc', LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) env.PrependENVPath('PATH', rtconfig.EXEC_PATH) diff --git a/bsp/renesas/ra6m4-iot/project.uvoptx b/bsp/renesas/ra6m4-iot/project.uvoptx index 56802c399c7..b664c0928e2 100644 --- a/bsp/renesas/ra6m4-iot/project.uvoptx +++ b/bsp/renesas/ra6m4-iot/project.uvoptx @@ -170,22 +170,554 @@ - Source Group 1 + Compiler 0 0 0 0 + + 1 + 1 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscall_mem.c + syscall_mem.c + 0 + 0 + + + 1 + 2 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\armlibc\syscalls.c + syscalls.c + 0 + 0 + + + 1 + 3 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cctype.c + cctype.c + 0 + 0 + + + 1 + 4 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdio.c + cstdio.c + 0 + 0 + + + 1 + 5 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstdlib.c + cstdlib.c + 0 + 0 + + + 1 + 6 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cstring.c + cstring.c + 0 + 0 + + + 1 + 7 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\ctime.c + ctime.c + 0 + 0 + + + 1 + 8 + 1 + 0 + 0 + 0 + ..\..\..\components\libc\compilers\common\cwchar.c + cwchar.c + 0 + 0 + - :Renesas RA Smart Configurator:Common Sources + CPU 0 0 0 0 2 - 1 + 9 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\atomic_arm.c + atomic_arm.c + 0 + 0 + + + 2 + 10 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\div0.c + div0.c + 0 + 0 + + + 2 + 11 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\common\showmem.c + showmem.c + 0 + 0 + + + 2 + 12 + 2 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\context_rvds.S + context_rvds.S + 0 + 0 + + + 2 + 13 + 1 + 0 + 0 + 0 + ..\..\..\libcpu\arm\cortex-m4\cpuport.c + cpuport.c + 0 + 0 + + + + + DeviceDrivers + 0 + 0 + 0 + 0 + + 3 + 14 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\core\device.c + device.c + 0 + 0 + + + 3 + 15 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\completion.c + completion.c + 0 + 0 + + + 3 + 16 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\dataqueue.c + dataqueue.c + 0 + 0 + + + 3 + 17 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\pipe.c + pipe.c + 0 + 0 + + + 3 + 18 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringblk_buf.c + ringblk_buf.c + 0 + 0 + + + 3 + 19 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\ringbuffer.c + ringbuffer.c + 0 + 0 + + + 3 + 20 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\waitqueue.c + waitqueue.c + 0 + 0 + + + 3 + 21 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\ipc\workqueue.c + workqueue.c + 0 + 0 + + + 3 + 22 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\misc\pin.c + pin.c + 0 + 0 + + + 3 + 23 + 1 + 0 + 0 + 0 + ..\..\..\components\drivers\serial\serial_v2.c + serial_v2.c + 0 + 0 + + + + + Drivers + 0 + 0 + 0 + 0 + + 4 + 24 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_common.c + drv_common.c + 0 + 0 + + + 4 + 25 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_gpio.c + drv_gpio.c + 0 + 0 + + + 4 + 26 + 1 + 0 + 0 + 0 + ..\libraries\HAL_Drivers\drv_usart_v2.c + drv_usart_v2.c + 0 + 0 + + + + + Finsh + 0 + 0 + 0 + 0 + + 5 + 27 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\cmd.c + cmd.c + 0 + 0 + + + 5 + 28 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\shell.c + shell.c + 0 + 0 + + + 5 + 29 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh_parse.c + msh_parse.c + 0 + 0 + + + 5 + 30 + 1 + 0 + 0 + 0 + ..\..\..\components\finsh\msh.c + msh.c + 0 + 0 + + + + + Kernel + 0 + 0 + 0 + 0 + + 6 + 31 + 1 + 0 + 0 + 0 + ..\..\..\src\clock.c + clock.c + 0 + 0 + + + 6 + 32 + 1 + 0 + 0 + 0 + ..\..\..\src\components.c + components.c + 0 + 0 + + + 6 + 33 + 1 + 0 + 0 + 0 + ..\..\..\src\idle.c + idle.c + 0 + 0 + + + 6 + 34 + 1 + 0 + 0 + 0 + ..\..\..\src\ipc.c + ipc.c + 0 + 0 + + + 6 + 35 + 1 + 0 + 0 + 0 + ..\..\..\src\irq.c + irq.c + 0 + 0 + + + 6 + 36 + 1 + 0 + 0 + 0 + ..\..\..\src\kservice.c + kservice.c + 0 + 0 + + + 6 + 37 + 1 + 0 + 0 + 0 + ..\..\..\src\mem.c + mem.c + 0 + 0 + + + 6 + 38 + 1 + 0 + 0 + 0 + ..\..\..\src\object.c + object.c + 0 + 0 + + + 6 + 39 + 1 + 0 + 0 + 0 + ..\..\..\src\scheduler_up.c + scheduler_up.c + 0 + 0 + + + 6 + 40 + 1 + 0 + 0 + 0 + ..\..\..\src\thread.c + thread.c + 0 + 0 + + + 6 + 41 + 1 + 0 + 0 + 0 + ..\..\..\src\timer.c + timer.c + 0 + 0 + + + + + :Renesas RA Smart Configurator:Common Sources + 0 + 0 + 0 + 0 + + 7 + 42 1 0 0 diff --git a/bsp/renesas/ra6m4-iot/project.uvprojx b/bsp/renesas/ra6m4-iot/project.uvprojx index e74d4a4f6b2..74998c8648e 100644 --- a/bsp/renesas/ra6m4-iot/project.uvprojx +++ b/bsp/renesas/ra6m4-iot/project.uvprojx @@ -1,12 +1,16 @@ + 2.1 +
### uVision Project, (C) Keil Software
+ Target 1 0x4 ARM-ADS + 6190000::V6.19::ARMCLANG 1 @@ -15,28 +19,28 @@ Renesas.RA_DFP.3.1.0 https://www2.renesas.eu/Keil_MDK_Packs/ CPUTYPE("Cortex-M33") FPU3(SFPU) DSP TZ CLOCK(12000000) ELITTLE - - - + + + 0 - - - - - - - - - - + + + + + + + + + + $$Device:R7FA6M4AF3CFP$SVD\R7FA6M4AF.svd 0 0 - - - - - + + + + + 0 0 @@ -58,8 +62,8 @@ 0 0 - - + + 0 0 0 @@ -68,8 +72,8 @@ 0 0 - - + + 0 0 0 @@ -79,14 +83,14 @@ 0 0 cmd /c "start "Renesas" /w cmd /c ""$Slauncher\rasc_launcher.bat" "3.5.0" --gensecurebundle --compiler ARMv6 "$Pconfiguration.xml" "$L%L" 2> "%%TEMP%%\rasc_stderr.out""" - + 0 0 2 0 0 - + 0 @@ -100,8 +104,8 @@ 0 0 3 - - + + 1 @@ -133,12 +137,12 @@ -1 1 - + "" () - - - - + + + + 0 @@ -171,7 +175,7 @@ 0 0 "Cortex-M33" - + 0 0 0 @@ -182,6 +186,7 @@ 2 0 0 + 0 0 0 0 @@ -305,7 +310,7 @@ 0x0 - + 1 @@ -333,9 +338,9 @@ 0 -Wno-license-management -Wuninitialized -Wall -Wmissing-declarations -Wpointer-arith -Waggregate-return -Wfloat-equal - RT_USING_LIBC, RT_USING_ARMLIBC, __STDC_LIMIT_MACROS, __RTTHREAD__, __CLK_TCK=RT_TICK_PER_SECOND - - ..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\include;..\..\..\components\libc\posix\io\stdio;..\..\..\components\libc\compilers\common\extension;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\poll;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers\config;..\..\..\components\libc\compilers\common\include;..\libraries\HAL_Drivers;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\finsh;..\..\..\libcpu\arm\common;.;board\ports;..\..\..\components\drivers\include;board + RT_USING_LIBC, __STDC_LIMIT_MACROS, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, RT_USING_ARMLIBC + + .;..\..\..\include;..\..\..\components\libc\compilers\common\include;..\..\..\components\libc\compilers\common\extension;..\..\..\components\libc\posix\io\poll;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\components\drivers\include;..\..\..\components\libc\posix\io\stdio;board\ports;..\..\..\components\finsh;..\..\..\libcpu\arm\cortex-m4;..\libraries\HAL_Drivers;..\libraries\HAL_Drivers\config;..\..\..\components\drivers\include;..\..\..\components\libc\posix\ipc;..\..\..\components\drivers\include;board;..\..\..\libcpu\arm\common;..\..\..\components\drivers\include @@ -350,10 +355,10 @@ 0 4 - - - - + + + + @@ -363,14 +368,14 @@ 0 0 0 - - - + + + .\script\fsp.scat - - - - + + + + 6319,6314 @@ -384,50 +389,36 @@ 1 ..\..\..\components\libc\compilers\armlibc\syscall_mem.c - - syscalls.c 1 ..\..\..\components\libc\compilers\armlibc\syscalls.c - - cctype.c 1 ..\..\..\components\libc\compilers\common\cctype.c - - cstdio.c 1 ..\..\..\components\libc\compilers\common\cstdio.c - - cstdlib.c 1 ..\..\..\components\libc\compilers\common\cstdlib.c - - cstring.c 1 ..\..\..\components\libc\compilers\common\cstring.c - - ctime.c 1 ..\..\..\components\libc\compilers\common\ctime.c - - cwchar.c 1 @@ -443,29 +434,21 @@ 1 ..\..\..\libcpu\arm\common\atomic_arm.c - - div0.c 1 ..\..\..\libcpu\arm\common\div0.c - - showmem.c 1 ..\..\..\libcpu\arm\common\showmem.c - - context_rvds.S 2 ..\..\..\libcpu\arm\cortex-m4\context_rvds.S - - cpuport.c 1 @@ -476,62 +459,51 @@ DeviceDrivers + + device.c + 1 + ..\..\..\components\drivers\core\device.c + completion.c 1 ..\..\..\components\drivers\ipc\completion.c - - dataqueue.c 1 ..\..\..\components\drivers\ipc\dataqueue.c - - pipe.c 1 ..\..\..\components\drivers\ipc\pipe.c - - ringblk_buf.c 1 ..\..\..\components\drivers\ipc\ringblk_buf.c - - ringbuffer.c 1 ..\..\..\components\drivers\ipc\ringbuffer.c - - waitqueue.c 1 ..\..\..\components\drivers\ipc\waitqueue.c - - workqueue.c 1 ..\..\..\components\drivers\ipc\workqueue.c - - pin.c 1 ..\..\..\components\drivers\misc\pin.c - - serial_v2.c 1 @@ -547,51 +519,164 @@ 1 ..\libraries\HAL_Drivers\drv_common.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 -std=c99 - + - - drv_gpio.c 1 ..\libraries\HAL_Drivers\drv_gpio.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 -std=c99 - + - - drv_usart_v2.c 1 ..\libraries\HAL_Drivers\drv_usart_v2.c + + 2 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 2 + 0 + 2 + 2 + 2 + 2 + 2 + 0 + 0 + 2 + 2 + 2 + 2 + 2 -std=c99 - + @@ -603,30 +688,24 @@ Finsh - shell.c + cmd.c 1 - ..\..\..\components\finsh\shell.c + ..\..\..\components\finsh\cmd.c - - - msh.c + shell.c 1 - ..\..\..\components\finsh\msh.c + ..\..\..\components\finsh\shell.c - - msh_parse.c 1 ..\..\..\components\finsh\msh_parse.c - - - cmd.c + msh.c 1 - ..\..\..\components\finsh\cmd.c + ..\..\..\components\finsh\msh.c @@ -638,78 +717,51 @@ 1 ..\..\..\src\clock.c - - components.c 1 ..\..\..\src\components.c - - - - device.c - 1 - ..\..\..\src\device.c - - - idle.c 1 ..\..\..\src\idle.c - - ipc.c 1 ..\..\..\src\ipc.c - - irq.c 1 ..\..\..\src\irq.c - - kservice.c 1 ..\..\..\src\kservice.c - - mem.c 1 ..\..\..\src\mem.c - - object.c 1 ..\..\..\src\object.c - - scheduler_up.c 1 ..\..\..\src\scheduler_up.c - - thread.c 1 ..\..\..\src\thread.c - - timer.c 1 @@ -717,26 +769,41 @@ + + :Renesas RA Smart Configurator:Common Sources + + + hal_entry.c + 1 + .\src\hal_entry.c + + + + + ::Flex Software + + - + - + - + - + - + + diff --git a/bsp/renesas/ra6m4-iot/rtconfig.h b/bsp/renesas/ra6m4-iot/rtconfig.h index cd1629e765c..3bffc274e19 100644 --- a/bsp/renesas/ra6m4-iot/rtconfig.h +++ b/bsp/renesas/ra6m4-iot/rtconfig.h @@ -23,8 +23,10 @@ /* kservice optimization */ -#define RT_DEBUG -#define RT_DEBUG_COLOR +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ @@ -36,7 +38,6 @@ /* Memory Management */ -#define RT_PAGE_MAX_ORDER 11 #define RT_USING_SMALL_MEM #define RT_USING_SMALL_MEM_AS_HEAP #define RT_USING_HEAP @@ -47,7 +48,7 @@ #define RT_USING_CONSOLE #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart6" -#define RT_VER_NUM 0x50000 +#define RT_VER_NUM 0x50001 #define RT_USING_HW_ATOMIC #define RT_USING_CPU_FFS #define ARCH_ARM @@ -74,6 +75,9 @@ #define FINSH_USING_DESCRIPTION #define FINSH_ARG_MAX 10 +/* DFS: device virtual file system */ + + /* Device Drivers */ #define RT_USING_DEVICE_IPC @@ -190,7 +194,7 @@ /* Arduino libraries */ -/* Projects */ +/* Projects and Demos */ /* Sensors */ diff --git a/bsp/renesas/ra6m4-iot/rtconfig.py b/bsp/renesas/ra6m4-iot/rtconfig.py index f03ce7604dd..6bfbb5a71b2 100644 --- a/bsp/renesas/ra6m4-iot/rtconfig.py +++ b/bsp/renesas/ra6m4-iot/rtconfig.py @@ -56,6 +56,7 @@ AFLAGS += ' -gdwarf-2' else: CFLAGS += ' -Os' + CXXFLAGS = CFLAGS POST_ACTION = OBJCPY + ' -O ihex $TARGET rtthread.hex\n' + SIZE + ' $TARGET \n' # POST_ACTION += OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'