diff --git a/.github/workflows/action.yml b/.github/workflows/action.yml index 9069c35bb49..e7e992d7e25 100644 --- a/.github/workflows/action.yml +++ b/.github/workflows/action.yml @@ -285,6 +285,7 @@ jobs: - "raspberry-pi/raspi3-64" - "raspberry-pi/raspi4-64" - "rockchip/rk3568" + - "phytium/aarch64" - RTT_BSP: "riscv-none" RTT_TOOL_CHAIN: "sourcery-riscv-none-embed" SUB_RTT_BSP: diff --git a/.github/workflows/manual_trigger_scons_except_STM32_all.yml b/.github/workflows/manual_trigger_scons_except_STM32_all.yml index 53183312948..c68deef13b9 100644 --- a/.github/workflows/manual_trigger_scons_except_STM32_all.yml +++ b/.github/workflows/manual_trigger_scons_except_STM32_all.yml @@ -210,8 +210,8 @@ jobs: - {RTT_BSP_NAME: "nuclei_gd32vf103_rvstar", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuclei/gd32vf103_rvstar"} #- {RTT_BSP_NAME: "nuclei_nuclei_fpga_eval", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nuclei/nuclei_fpga_eval"} #riscv-nuclei-elf-gcc toolchain不支持 #- {RTT_BSP_NAME: "nv32f100x", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "nv32f100x"} #编译错误 - #- {RTT_BSP_NAME: "phytium_aarch32", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "phytium/aarch32"} #编译错误 - # - {RTT_BSP_NAME: "phytium_aarch64", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "phytium/aarch64"} #编译错误 + # - {RTT_BSP_NAME: "phytium_aarch32", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "phytium/aarch32"} + - {RTT_BSP_NAME: "phytium_aarch64", RTT_TOOL_CHAIN: "sourcery-aarch64", RTT_BSP: "phytium/aarch64"} #- {RTT_BSP_NAME: "pic32ethernet", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "pic32ethernet"} #编译错误 - {RTT_BSP_NAME: "qemu-vexpress-a9", RTT_TOOL_CHAIN: "sourcery-arm", RTT_BSP: "qemu-vexpress-a9"} - {RTT_BSP_NAME: "qemu-virt64-aarch64", RTT_TOOL_CHAIN: "sourcery-aarch64", RTT_BSP: "qemu-virt64-aarch64"} diff --git a/bsp/phytium/.gitignore b/bsp/phytium/.gitignore index a93827b5720..43c09682e74 100644 --- a/bsp/phytium/.gitignore +++ b/bsp/phytium/.gitignore @@ -4,8 +4,11 @@ /aarch32/tools/ci.py /aarch32/tools/get_toolchain.py /aarch32/smart-env.sh +/aarch32/smart-env.bat /aarch64/tools/gnu_gcc/* /aarch64/tools/ci.py /aarch64/tools/get_toolchain.py /aarch64/smart-env.sh -**/**/makefile \ No newline at end of file +/aarch64/smart-env.bat +**/**/makefile +/libraries/tests/* \ No newline at end of file diff --git a/bsp/phytium/aarch32/.config b/bsp/phytium/aarch32/.config index 62d8bff4b03..260fcdcd87f 100644 --- a/bsp/phytium/aarch32/.config +++ b/bsp/phytium/aarch32/.config @@ -9,6 +9,7 @@ CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_AMP is not set CONFIG_RT_USING_SMP=y CONFIG_RT_CPUS_NR=2 CONFIG_RT_ALIGN_SIZE=4 @@ -36,19 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set CONFIG_RT_KPRINTF_USING_LONGLONG=y -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_PAGE_LEAK is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set # # Inter-Thread communication @@ -58,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY=y # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_MEMHEAP_FAST_MODE=y # CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP_ISR=y CONFIG_RT_USING_HEAP=y # @@ -91,6 +85,10 @@ CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set + +# +# RT-Thread Architecture +# CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_HW_ATOMIC=y # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set @@ -144,12 +142,36 @@ CONFIG_RT_USING_DFS_V1=y # CONFIG_RT_USING_DFS_V2 is not set CONFIG_DFS_FILESYSTEMS_MAX=4 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_TMPFS is not set +CONFIG_RT_USING_DFS_MQUEUE=y +# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set CONFIG_RT_USING_LWP=y CONFIG_RT_LWP_MAX_NR=30 @@ -195,7 +217,13 @@ CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set @@ -205,7 +233,7 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set @@ -229,6 +257,7 @@ CONFIG_RT_USING_POSIX_DEVIO=y CONFIG_RT_USING_POSIX_STDIO=y CONFIG_RT_USING_POSIX_POLL=y CONFIG_RT_USING_POSIX_SELECT=y +# CONFIG_RT_USING_POSIX_EVENTFD is not set # CONFIG_RT_USING_POSIX_SOCKET is not set CONFIG_RT_USING_POSIX_TERMIOS=y CONFIG_RT_USING_POSIX_AIO=y @@ -255,9 +284,82 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -271,10 +373,15 @@ CONFIG_RT_USING_UTEST=y CONFIG_UTEST_THR_STACK_SIZE=4096 CONFIG_UTEST_THR_PRIORITY=20 # CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_RESOURCE_ID=y CONFIG_RT_USING_ADT=y CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +CONFIG_RT_USING_KTIME=y # # RT-Thread Utestcases @@ -299,7 +406,6 @@ CONFIG_RT_USING_ADT_AVL=y # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set @@ -571,6 +677,7 @@ CONFIG_RT_USING_ADT_AVL=y # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set # CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set # # peripheral libraries and drivers @@ -635,6 +742,7 @@ CONFIG_RT_USING_ADT_AVL=y # CONFIG_PKG_USING_BALANCE is not set # CONFIG_PKG_USING_SHT2X is not set # CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_SHT4X is not set # CONFIG_PKG_USING_AD7746 is not set # CONFIG_PKG_USING_ADT74XX is not set # CONFIG_PKG_USING_MAX17048 is not set @@ -655,6 +763,7 @@ CONFIG_RT_USING_ADT_AVL=y # CONFIG_PKG_USING_FT5426 is not set # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -730,7 +839,12 @@ CONFIG_RT_USING_ADT_AVL=y # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_ST7789 is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # # AI packages @@ -749,7 +863,10 @@ CONFIG_RT_USING_ADT_AVL=y # Signal Processing and Control Algorithm Packages # # CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set # # miscellaneous packages @@ -796,7 +913,6 @@ CONFIG_RT_USING_ADT_AVL=y # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set @@ -821,8 +937,9 @@ CONFIG_RT_USING_ADT_AVL=y # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set @@ -969,14 +1086,20 @@ CONFIG_RT_USING_ADT_AVL=y # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set # # Timing # +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # # Data Processing @@ -1010,7 +1133,6 @@ CONFIG_RT_USING_ADT_AVL=y # # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set -# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set # # Signal IO @@ -1040,7 +1162,15 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART0 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set # # Board extended module Drivers @@ -1073,6 +1203,8 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_USE_QSPI is not set CONFIG_USE_GIC=y CONFIG_ENABLE_GICV3=y +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y CONFIG_USE_SERIAL=y # @@ -1080,7 +1212,15 @@ CONFIG_USE_SERIAL=y # CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_GPIO is not set -# CONFIG_USE_ETH is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set # CONFIG_USE_CAN is not set # CONFIG_USE_I2C is not set # CONFIG_USE_TIMER is not set @@ -1098,15 +1238,19 @@ CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_IPC is not set # CONFIG_USE_MEDIA is not set # CONFIG_USE_SCMI_MHU is not set + +# +# Sdk common configuration +# # CONFIG_LOG_VERBOS is not set # CONFIG_LOG_DEBUG is not set # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y # CONFIG_LOG_NONE is not set -CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y -CONFIG_INTERRUPT_ROLE_MASTER=y -# CONFIG_INTERRUPT_ROLE_SLAVE is not set # CONFIG_LOG_EXTRA_INFO is not set # CONFIG_LOG_DISPALY_CORE_NUM is not set # CONFIG_BOOTUP_DEBUG_PRINTS is not set +CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y +CONFIG_INTERRUPT_ROLE_MASTER=y +# CONFIG_INTERRUPT_ROLE_SLAVE is not set diff --git a/bsp/phytium/aarch32/Kconfig b/bsp/phytium/aarch32/Kconfig index cc9a3fe042a..3f92dee45b2 100644 --- a/bsp/phytium/aarch32/Kconfig +++ b/bsp/phytium/aarch32/Kconfig @@ -49,6 +49,4 @@ menu "Standalone Setting" source "$STANDALONE_DIR/board/Kconfig" source "$STANDALONE_DIR/drivers/Kconfig" source "$STANDALONE_DIR/common/Kconfig" - endmenu - diff --git a/bsp/phytium/aarch32/README.md b/bsp/phytium/aarch32/README.md index 4c2e5944bd1..dcec0d0049e 100644 --- a/bsp/phytium/aarch32/README.md +++ b/bsp/phytium/aarch32/README.md @@ -113,6 +113,12 @@ rtthread_a32.map - 可以用串口通过 XMODEM 协议将 bin/elf 文件上传到开发板，然后启动， +- 如果使用 SD-1 控制器 + +``` +mw.l 0x32b31178 0x1f +``` + - 首先在 Phytium 开发板上输入，上传 bin 文件 ``` diff --git a/bsp/phytium/aarch32/applications/mnt.c b/bsp/phytium/aarch32/applications/mnt.c index 447f518f78d..9c62ae49195 100644 --- a/bsp/phytium/aarch32/applications/mnt.c +++ b/bsp/phytium/aarch32/applications/mnt.c @@ -8,56 +8,89 @@ * Change Logs: * Date Author Notes * 2023-04-27 huanghe first version + * 2023-07-14 liqiaozhong add SD file sys mount func * */ - #include -#ifdef RT_USING_DFS_RAMFS +#if defined(RT_USING_DFS) +#include + #include +#include -extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); +#define DBG_TAG "app.filesystem" +#define DBG_LVL DBG_INFO -int mnt_init(void) +#ifdef BSP_USING_SDCARD_FATFS +#define SD_DEIVCE_NAME "sd" +static int filesystem_mount(void) { + while (rt_device_find(SD_DEIVCE_NAME) == RT_NULL) + { + rt_thread_mdelay(1); + } + + if (dfs_mount(SD_DEIVCE_NAME, "/", "elm", 0, 0) == 0) + { + LOG_I("file system initialization done!\n"); + } + else + { + LOG_W("[sd] File System on SD initialization failed!"); + LOG_W("[sd] Try to format and re-mount..."); + if (dfs_mkfs("elm", SD_DEIVCE_NAME) == 0) + { + if (dfs_mount(SD_DEIVCE_NAME, "/", "elm", 0, 0) == 0) + { + LOG_I("[sd] File System on SD initialized!"); + } + } + LOG_E("[sd] File System on SD initialization failed!"); + return -1; + } + + mkdir("/ram", 0x777); + +#ifdef RT_USING_DFS_RAMFS + extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); + rt_uint8_t *pool = RT_NULL; - rt_size_t size = 8*1024*1024; + rt_size_t size = 8 * 1024 * 1024; pool = rt_malloc(size); if (pool == RT_NULL) - return 0; + LOG_E("Malloc fail!"); - if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) - rt_kprintf("RAM file system initializated!\n"); + if (dfs_mount(RT_NULL, "/ram", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) + LOG_I("RAM file system initializated!"); else - rt_kprintf("RAM file system initializate failed!\n"); - - return 0; -} -INIT_ENV_EXPORT(mnt_init); + LOG_E("RAM file system initializate failed!"); #endif + return RT_EOK; +} +INIT_ENV_EXPORT(filesystem_mount); -#ifdef BSP_USING_SDCARD_FATFS -#include -#include -#define DBG_TAG "app.filesystem" -#define DBG_LVL DBG_INFO -#include +#else static int filesystem_mount(void) { - while(rt_device_find("sd0") == RT_NULL) - { - rt_thread_mdelay(1); - } +#ifdef RT_USING_DFS_RAMFS + extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); - int ret = dfs_mount("sd0", "/", "elm", 0, 0); - if (ret != 0) - { - rt_kprintf("ret: %d\n",ret); - LOG_E("sd0 mount to '/' failed!"); - return ret; - } + rt_uint8_t *pool = RT_NULL; + rt_size_t size = 8 * 1024 * 1024; + + pool = rt_malloc(size); + if (pool == RT_NULL) + LOG_E("Malloc fail!"); + + if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) + LOG_I("RAM file system initializated!"); + else + LOG_E("RAM file system initializate failed!"); +#endif return RT_EOK; } INIT_ENV_EXPORT(filesystem_mount); -#endif +#endif // #ifdef BSP_USING_SDCARD_FATFS +#endif // #if defined(RT_USING_DFS) \ No newline at end of file diff --git a/bsp/phytium/aarch32/boot/aarch32_boot.S b/bsp/phytium/aarch32/boot/aarch32_boot.S index c1e3bdf4493..8ab99da5833 100644 --- a/bsp/phytium/aarch32/boot/aarch32_boot.S +++ b/bsp/phytium/aarch32/boot/aarch32_boot.S @@ -7,7 +7,8 @@ * * Change Logs: * Date Author Notes - * 2022-10-26 huanghe first commit + * 2022-10-26 huanghe first commit + * 2023-07-27 zhugengyu flush cache in aarch64-el2 * */ @@ -18,8 +19,75 @@ .section .boot,"ax" -/* switch from aarch64-el2 to aarch32-el1 */ _boot: + /* hard code aarch64 instruction to flush dcache, refer to rt-thread __asm_flush_dcache_all */ + .long 0xd2800000 /* mov x0, #0x0 // clean and invaildate d-cache */ + .long 0x1400001a /* b */ + +InvalidateFlushDcacheLevel: + .long 0xd37ff80c /* lsl x12, x0, #1 */ + .long 0xd51a000c /* msr csselr_el1, x12 */ + .long 0xd5033fdf /* isb */ + .long 0xd5390006 /* mrs x6, ccsidr_el1 */ + .long 0x924008c2 /* and x2, x6, #0x7 */ + .long 0x91001042 /* add x2, x2, #0x4 */ + .long 0xd2807fe3 /* mov x3, #0x3ff */ + .long 0x8a460c63 /* and x3, x3, x6, lsr #3 */ + .long 0x5ac01065 /* clz w5, w3 */ + .long 0xd28fffe4 /* mov x4, #0x7fff */ + .long 0x8a463484 /* and x4, x4, x6, lsr #13 */ + +InvalidateFlushCacheSet: + .long 0xaa0303e6 /* mov x6, x3 */ + +InvalidateFlushCacheWay: + .long 0x9ac520c7 /* lsl x7, x6, x5 */ + .long 0xaa070189 /* orr x9, x12, x7 */ + .long 0x9ac22087 /* lsl x7, x4, x2 */ + .long 0xaa070129 /* orr x9, x9, x7 */ + .long 0x36000061 /* tbz w1, #0, */ + .long 0xd5087649 /* dc isw, x9 */ + .long 0x14000002 /* b */ + .long 0xd5087e49 /* dc cisw, x9 */ + .long 0xf10004c6 /* subs x6, x6, #0x1 */ + .long 0x54fffeea /* b.ge */ + .long 0xf1000484 /* subs x4, x4, #0x1 */ + .long 0x54fffe8a /* b.ge */ + .long 0xd65f03c0 /* ret */ + +InvalidateFlushDcaches: + .long 0xaa0003e1 /* mov x1, x0 */ + .long 0xd5033f9f /* dsb sy */ + .long 0xd539002a /* mrs x10, clidr_el1 */ + .long 0xd358fd4b /* lsr x11, x10, #24 */ + .long 0x9240096b /* and x11, x11, #0x7 */ + .long 0xb400024b /* cbz x11, */ + .long 0xaa1e03ef /* mov x15, x30 */ + .long 0xd2800000 /* mov x0, #0x0 */ + +InvalidateFlushCachesLoopLevel: + .long 0xd37ff80c /* lsl x12, x0, #1 */ + .long 0x8b00018c /* add x12, x12, x0 */ + .long 0x9acc254c /* lsr x12, x10, x12 */ + .long 0x9240098c /* and x12, x12, #0x7 */ + .long 0xf100099f /* cmp x12, #0x2 */ + .long 0x5400004b /* b.lt */ + .long 0x97ffffd9 /* bl */ + +InvalidateFlushCachesSkipLevel: + .long 0x91000400 /* add x0, x0, #0x1 */ + .long 0xeb00017f /* cmp x11, x0 */ + .long 0x54fffeec /* b.gt */ + .long 0xd2800000 /* mov x0, #0x0 */ + .long 0xd51a0000 /* msr csselr_el1, x0 */ + .long 0xd5033f9f /* dsb sy */ + .long 0xd5033fdf /* isb */ + .long 0xaa0f03fe /* mov x30, x15 */ + +InvalidateFlushDcacheEnd: +/***************************************************************/ + +/* switch from aarch64-el2 to aarch32-el1 */ Startup_Aarch32: .long 0xd5384240 /* mrs x0, currentel */ .long 0xd342fc00 /* lsr x0, x0, #2 */ diff --git a/bsp/phytium/aarch32/configs/e2000d_rtsmart b/bsp/phytium/aarch32/configs/e2000d_rtsmart index e78d576898c..9fb864a5b6d 100644 --- a/bsp/phytium/aarch32/configs/e2000d_rtsmart +++ b/bsp/phytium/aarch32/configs/e2000d_rtsmart @@ -9,6 +9,7 @@ CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_AMP is not set CONFIG_RT_USING_SMP=y CONFIG_RT_CPUS_NR=2 CONFIG_RT_ALIGN_SIZE=4 @@ -36,19 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set CONFIG_RT_KPRINTF_USING_LONGLONG=y -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_PAGE_LEAK is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set # # Inter-Thread communication @@ -58,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY=y # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_MEMHEAP_FAST_MODE=y # CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP_ISR=y CONFIG_RT_USING_HEAP=y # @@ -91,6 +85,10 @@ CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set + +# +# RT-Thread Architecture +# CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_HW_ATOMIC=y # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set @@ -144,12 +142,36 @@ CONFIG_RT_USING_DFS_V1=y # CONFIG_RT_USING_DFS_V2 is not set CONFIG_DFS_FILESYSTEMS_MAX=4 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_TMPFS is not set +CONFIG_RT_USING_DFS_MQUEUE=y +# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set CONFIG_RT_USING_LWP=y CONFIG_RT_LWP_MAX_NR=30 @@ -195,7 +217,13 @@ CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set @@ -205,7 +233,7 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set @@ -255,9 +283,82 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -271,9 +372,15 @@ CONFIG_RT_USING_UTEST=y CONFIG_UTEST_THR_STACK_SIZE=4096 CONFIG_UTEST_THR_PRIORITY=20 # CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_RESOURCE_ID=y CONFIG_RT_USING_ADT=y +CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +CONFIG_RT_USING_KTIME=y # # RT-Thread Utestcases @@ -1039,7 +1146,15 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART0 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set # # Board extended module Drivers @@ -1072,6 +1187,8 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_USE_QSPI is not set CONFIG_USE_GIC=y CONFIG_ENABLE_GICV3=y +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y CONFIG_USE_SERIAL=y # @@ -1079,7 +1196,15 @@ CONFIG_USE_SERIAL=y # CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_GPIO is not set -# CONFIG_USE_ETH is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set # CONFIG_USE_CAN is not set # CONFIG_USE_I2C is not set # CONFIG_USE_TIMER is not set @@ -1097,15 +1222,19 @@ CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_IPC is not set # CONFIG_USE_MEDIA is not set # CONFIG_USE_SCMI_MHU is not set + +# +# Sdk common configuration +# # CONFIG_LOG_VERBOS is not set # CONFIG_LOG_DEBUG is not set # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y # CONFIG_LOG_NONE is not set -CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y -CONFIG_INTERRUPT_ROLE_MASTER=y -# CONFIG_INTERRUPT_ROLE_SLAVE is not set # CONFIG_LOG_EXTRA_INFO is not set # CONFIG_LOG_DISPALY_CORE_NUM is not set # CONFIG_BOOTUP_DEBUG_PRINTS is not set +CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y +CONFIG_INTERRUPT_ROLE_MASTER=y +# CONFIG_INTERRUPT_ROLE_SLAVE is not set diff --git a/bsp/phytium/aarch32/configs/e2000d_rtsmart.h b/bsp/phytium/aarch32/configs/e2000d_rtsmart.h index 7aae38b854e..997fc8457b9 100644 --- a/bsp/phytium/aarch32/configs/e2000d_rtsmart.h +++ b/bsp/phytium/aarch32/configs/e2000d_rtsmart.h @@ -30,6 +30,9 @@ #define RT_KSERVICE_USING_STDLIB #define RT_KPRINTF_USING_LONGLONG #define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ @@ -38,15 +41,16 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +#define RT_USING_MESSAGEQUEUE_PRIORITY /* Memory Management */ #define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_USING_SLAB #define RT_USING_MEMHEAP #define RT_MEMHEAP_FAST_MODE -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR #define RT_USING_HEAP /* Kernel Device Object */ @@ -56,6 +60,9 @@ #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x50001 + +/* RT-Thread Architecture */ + #define RT_USING_CACHE #define RT_USING_HW_ATOMIC #define RT_USING_CPU_FFS @@ -95,8 +102,24 @@ #define RT_USING_DFS_V1 #define DFS_FILESYSTEMS_MAX 4 #define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS #define RT_USING_DFS_RAMFS +#define RT_USING_DFS_MQUEUE #define RT_USING_LWP #define RT_LWP_MAX_NR 30 #define LWP_TASK_STACK_SIZE 16384 @@ -122,6 +145,13 @@ #define RT_USING_ZERO #define RT_USING_RANDOM #define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 4096 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_DEV_BUS /* Using USB */ @@ -155,6 +185,59 @@ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING /* Utilities */ @@ -163,7 +246,13 @@ #define RT_USING_UTEST #define UTEST_THR_STACK_SIZE 4096 #define UTEST_THR_PRIORITY 20 +#define RT_USING_RESOURCE_ID #define RT_USING_ADT +#define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF +#define RT_USING_KTIME /* RT-Thread Utestcases */ @@ -287,6 +376,11 @@ #define BSP_USING_UART #define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 /* Board extended module Drivers */ @@ -307,11 +401,22 @@ #define USE_GIC #define ENABLE_GICV3 +#define USE_IOPAD +#define ENABLE_IOPAD #define USE_SERIAL /* Usart Configuration */ #define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON + +/* Sdk common configuration */ + #define LOG_ERROR #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER diff --git a/bsp/phytium/aarch32/configs/e2000d_rtthread b/bsp/phytium/aarch32/configs/e2000d_rtthread index 9ccf9ae3b7c..dde45595a4b 100644 --- a/bsp/phytium/aarch32/configs/e2000d_rtthread +++ b/bsp/phytium/aarch32/configs/e2000d_rtthread @@ -9,6 +9,7 @@ CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set CONFIG_RT_USING_SMP=y CONFIG_RT_CPUS_NR=2 CONFIG_RT_ALIGN_SIZE=4 @@ -36,19 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set CONFIG_RT_KPRINTF_USING_LONGLONG=y -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_PAGE_LEAK is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set # # Inter-Thread communication @@ -58,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY=y # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_MEMHEAP_FAST_MODE=y # CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP_ISR=y CONFIG_RT_USING_HEAP=y # @@ -91,6 +85,10 @@ CONFIG_RT_CONSOLEBUF_SIZE=256 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set + +# +# RT-Thread Architecture +# CONFIG_RT_USING_CACHE=y CONFIG_RT_USING_HW_ATOMIC=y # CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set @@ -142,12 +140,36 @@ CONFIG_RT_USING_DFS_V1=y # CONFIG_RT_USING_DFS_V2 is not set CONFIG_DFS_FILESYSTEMS_MAX=4 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_TMPFS is not set +CONFIG_RT_USING_DFS_MQUEUE=y +# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set # @@ -182,7 +204,13 @@ CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set @@ -192,7 +220,7 @@ CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_HWCRYPTO is not set # CONFIG_RT_USING_PULSE_ENCODER is not set # CONFIG_RT_USING_INPUT_CAPTURE is not set -# CONFIG_RT_USING_DEV_BUS is not set +CONFIG_RT_USING_DEV_BUS=y # CONFIG_RT_USING_WIFI is not set # CONFIG_RT_USING_VIRTIO is not set @@ -242,9 +270,82 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -258,9 +359,15 @@ CONFIG_RT_USING_UTEST=y CONFIG_UTEST_THR_STACK_SIZE=4096 CONFIG_UTEST_THR_PRIORITY=20 # CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_RESOURCE_ID=y CONFIG_RT_USING_ADT=y +CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +CONFIG_RT_USING_KTIME=y # # RT-Thread Utestcases @@ -1026,7 +1133,15 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART0 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set # # Board extended module Drivers @@ -1059,6 +1174,8 @@ CONFIG_DEFAULT_DEBUG_PRINT_UART1=y # CONFIG_USE_QSPI is not set CONFIG_USE_GIC=y CONFIG_ENABLE_GICV3=y +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y CONFIG_USE_SERIAL=y # @@ -1066,7 +1183,15 @@ CONFIG_USE_SERIAL=y # CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_GPIO is not set -# CONFIG_USE_ETH is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set # CONFIG_USE_CAN is not set # CONFIG_USE_I2C is not set # CONFIG_USE_TIMER is not set @@ -1084,15 +1209,19 @@ CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_IPC is not set # CONFIG_USE_MEDIA is not set # CONFIG_USE_SCMI_MHU is not set + +# +# Sdk common configuration +# # CONFIG_LOG_VERBOS is not set # CONFIG_LOG_DEBUG is not set # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y # CONFIG_LOG_NONE is not set -CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y -CONFIG_INTERRUPT_ROLE_MASTER=y -# CONFIG_INTERRUPT_ROLE_SLAVE is not set # CONFIG_LOG_EXTRA_INFO is not set # CONFIG_LOG_DISPALY_CORE_NUM is not set # CONFIG_BOOTUP_DEBUG_PRINTS is not set +CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y +CONFIG_INTERRUPT_ROLE_MASTER=y +# CONFIG_INTERRUPT_ROLE_SLAVE is not set diff --git a/bsp/phytium/aarch32/configs/e2000d_rtthread.h b/bsp/phytium/aarch32/configs/e2000d_rtthread.h index cadee425a4d..b4cc3b82dd5 100644 --- a/bsp/phytium/aarch32/configs/e2000d_rtthread.h +++ b/bsp/phytium/aarch32/configs/e2000d_rtthread.h @@ -29,6 +29,9 @@ #define RT_KSERVICE_USING_STDLIB #define RT_KPRINTF_USING_LONGLONG #define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ @@ -37,15 +40,16 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +#define RT_USING_MESSAGEQUEUE_PRIORITY /* Memory Management */ #define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_USING_SLAB #define RT_USING_MEMHEAP #define RT_MEMHEAP_FAST_MODE -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR #define RT_USING_HEAP /* Kernel Device Object */ @@ -55,6 +59,9 @@ #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x50001 + +/* RT-Thread Architecture */ + #define RT_USING_CACHE #define RT_USING_HW_ATOMIC #define RT_USING_CPU_FFS @@ -93,8 +100,24 @@ #define RT_USING_DFS_V1 #define DFS_FILESYSTEMS_MAX 4 #define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS #define RT_USING_DFS_RAMFS +#define RT_USING_DFS_MQUEUE /* Device Drivers */ @@ -111,6 +134,13 @@ #define RT_USING_ZERO #define RT_USING_RANDOM #define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 4096 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_DEV_BUS /* Using USB */ @@ -144,6 +174,59 @@ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING /* Utilities */ @@ -152,7 +235,13 @@ #define RT_USING_UTEST #define UTEST_THR_STACK_SIZE 4096 #define UTEST_THR_PRIORITY 20 +#define RT_USING_RESOURCE_ID #define RT_USING_ADT +#define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF +#define RT_USING_KTIME /* RT-Thread Utestcases */ @@ -276,6 +365,11 @@ #define BSP_USING_UART #define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 /* Board extended module Drivers */ @@ -296,11 +390,22 @@ #define USE_GIC #define ENABLE_GICV3 +#define USE_IOPAD +#define ENABLE_IOPAD #define USE_SERIAL /* Usart Configuration */ #define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON + +/* Sdk common configuration */ + #define LOG_ERROR #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER diff --git a/bsp/phytium/aarch32/configs/e2000d_rtthread_test b/bsp/phytium/aarch32/configs/e2000d_rtthread_test new file mode 100644 index 00000000000..9dadd0b38ef --- /dev/null +++ b/bsp/phytium/aarch32/configs/e2000d_rtthread_test @@ -0,0 +1,1344 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +CONFIG_RT_USING_SMP=y +CONFIG_RT_CPUS_NR=2 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=4096 +CONFIG_SYSTEM_THREAD_STACK_SIZE=4096 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +CONFIG_RT_KPRINTF_USING_LONGLONG=y +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_PAGE_LEAK is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_PAGE_MAX_ORDER=11 +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP_ISR=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=256 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_RT_USING_CACHE=y +CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_ARCH_ARM_CORTEX_A=y +# CONFIG_RT_SMP_AUTO_BOOT is not set +# CONFIG_RT_USING_GIC_V2 is not set +CONFIG_RT_USING_GIC_V3=y +# CONFIG_ARCH_ARM_SECURE_MODE is not set +# CONFIG_RT_BACKTRACE_FUNCTION_NAME is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +CONFIG_RT_USING_DFS_RAMFS=y +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_NFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=4096 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=1024 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +CONFIG_RT_USING_POSIX_DEVIO=y +CONFIG_RT_USING_POSIX_STDIO=y +CONFIG_RT_USING_POSIX_POLL=y +CONFIG_RT_USING_POSIX_SELECT=y +# CONFIG_RT_USING_POSIX_SOCKET is not set +CONFIG_RT_USING_POSIX_TERMIOS=y +CONFIG_RT_USING_POSIX_AIO=y +# CONFIG_RT_USING_POSIX_MMAN is not set +CONFIG_RT_USING_POSIX_DELAY=y +CONFIG_RT_USING_POSIX_CLOCK=y +CONFIG_RT_USING_POSIX_TIMER=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +CONFIG_RT_USING_POSIX_PIPE=y +CONFIG_RT_USING_POSIX_PIPE_SIZE=512 +CONFIG_RT_USING_POSIX_MESSAGE_QUEUE=y +CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_DEBUG is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +CONFIG_RT_USING_RYM=y +# CONFIG_YMODEM_USING_CRC_TABLE is not set +CONFIG_YMODEM_USING_FILE_TRANSFER=y +# CONFIG_RT_USING_ULOG is not set +CONFIG_RT_USING_UTEST=y +CONFIG_UTEST_THR_STACK_SIZE=4096 +CONFIG_UTEST_THR_PRIORITY=20 +# CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_ADT=y +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +CONFIG_RT_USING_UTESTCASES=y + +# +# Utest Self Testcase +# +CONFIG_UTEST_SELF_PASS_TC=y + +# +# Kernel Testcase +# +CONFIG_UTEST_MEMHEAP_TC=y +CONFIG_UTEST_SLAB_TC=y +CONFIG_UTEST_IRQ_TC=y +CONFIG_UTEST_SEMAPHORE_TC=y +CONFIG_UTEST_EVENT_TC=y +CONFIG_UTEST_TIMER_TC=y +# CONFIG_UTEST_MESSAGEQUEUE_TC is not set +# CONFIG_UTEST_SIGNAL_TC is not set +CONFIG_UTEST_MUTEX_TC=y +CONFIG_UTEST_MAILBOX_TC=y +CONFIG_UTEST_THREAD_TC=y +CONFIG_UTEST_ATOMIC_TC=y + +# +# CPP11 Testcase +# +# CONFIG_UTEST_CPP11_THREAD_TC is not set + +# +# Utest Serial Testcase +# +# CONFIG_UTEST_SERIAL_TC is not set + +# +# RTT Posix Testcase +# +CONFIG_RTT_POSIX_TESTCASE=y +# CONFIG_RTT_POSIX_TESTCASE_DIRENT_H is not set +# CONFIG_RTT_POSIX_TESTCASE_PTHREAD_H is not set +CONFIG_RTT_POSIX_TESTCASE_STDIO_H=y +# CONFIG_STDIO_H_CLEARERR is not set +# CONFIG_STDIO_H_FCLOSE is not set +# CONFIG_STDIO_H_FDOPEN is not set +# CONFIG_STDIO_H_FEOF is not set +# CONFIG_STDIO_H_FERROR is not set +# CONFIG_STDIO_H_FFLUSH is not set +# CONFIG_STDIO_H_FGETC is not set +# CONFIG_STDIO_H_FGETS is not set +# CONFIG_STDIO_H_FILENO is not set +# CONFIG_STDIO_H_FOPEN is not set +# CONFIG_STDIO_H_FPRINTF is not set +# CONFIG_STDIO_H_FPUTC is not set +# CONFIG_STDIO_H_FPUTS is not set +# CONFIG_STDIO_H_FREAD is not set +# CONFIG_STDIO_H_FSCANF is not set +# CONFIG_STDIO_H_FSEEK is not set +# CONFIG_STDIO_H_FTELL is not set +# CONFIG_STDIO_H_FWRITE is not set +# CONFIG_STDIO_H_PERROR is not set +# CONFIG_STDIO_H_PRINTF is not set +# CONFIG_STDIO_H_PUTC is not set +# CONFIG_STDIO_H_PUTCHAR is not set +# CONFIG_STDIO_H_PUTS is not set +# CONFIG_STDIO_H_REMOVE is not set +# CONFIG_STDIO_H_RENAME is not set +# CONFIG_STDIO_H_REWIND is not set +# CONFIG_STDIO_H_SETBUF is not set +# CONFIG_STDIO_H_SETVBUF is not set +# CONFIG_STDIO_H_SNPRINTF is not set +# CONFIG_STDIO_H_SPRINTF is not set +# CONFIG_STDIO_H_SSCANF is not set +# CONFIG_STDIO_H_VFPRINTF is not set +# CONFIG_STDIO_H_VPRINTF is not set +# CONFIG_STDIO_H_VSNPRINTF is not set +# CONFIG_STDIO_H_VSPRINTF is not set +CONFIG_RTT_POSIX_TESTCASE_STDLIB_H=y +# CONFIG_STDLIB_H_ATOI is not set +# CONFIG_STDLIB_H_ATOL is not set +# CONFIG_STDLIB_H_QSORT is not set +# CONFIG_STDLIB_H_STRTOL is not set +CONFIG_RTT_POSIX_TESTCASE_UNISTD_H=y +# CONFIG_UNISTD_H_ACCESS is not set +# CONFIG_UNISTD_H_CHDIR is not set +# CONFIG_UNISTD_H_FTRUNCATE is not set +# CONFIG_UNISTD_H_ISATTY is not set +# CONFIG_UNISTD_H_FSYNC is not set +# CONFIG_UNISTD_H_RMDIR is not set + +# +# Memory Management Subsytem Testcase +# +# CONFIG_UTEST_MM_API_TC is not set +# CONFIG_UTEST_MM_LWP_TC is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_FINGERPRINT is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_RT_USING_UART1=y +# CONFIG_RT_USING_UART0 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set + +# +# Board extended module Drivers +# +CONFIG_PHYTIUM_ARCH_AARCH32=y + +# +# Standalone Setting +# +CONFIG_TARGET_ARMV8_AARCH32=y +CONFIG_USE_AARCH64_L1_TO_AARCH32=y + +# +# Board Configuration +# +# CONFIG_TARGET_F2000_4 is not set +# CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_E2000Q is not set +CONFIG_TARGET_E2000D=y +# CONFIG_TARGET_E2000S is not set +CONFIG_TARGET_E2000=y +CONFIG_DEFAULT_DEBUG_PRINT_UART1=y +# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set +# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set + +# +# Components Configuration +# +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_GIC=y +CONFIG_ENABLE_GICV3=y +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y +CONFIG_USE_SERIAL=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# CONFIG_USE_GPIO is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set +# CONFIG_USE_CAN is not set +# CONFIG_USE_I2C is not set +# CONFIG_USE_TIMER is not set +# CONFIG_USE_MIO is not set +# CONFIG_USE_SDMMC is not set +# CONFIG_USE_PCIE is not set +# CONFIG_USE_WDT is not set +# CONFIG_USE_DMA is not set +# CONFIG_USE_NAND is not set +# CONFIG_USE_RTC is not set +# CONFIG_USE_SATA is not set +# CONFIG_USE_USB is not set +# CONFIG_USE_ADC is not set +# CONFIG_USE_PWM is not set +# CONFIG_USE_IPC is not set +# CONFIG_USE_MEDIA is not set +# CONFIG_USE_SCMI_MHU is not set + +# +# Sdk common configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# CONFIG_LOG_EXTRA_INFO is not set +# CONFIG_LOG_DISPALY_CORE_NUM is not set +# CONFIG_BOOTUP_DEBUG_PRINTS is not set +CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y +CONFIG_INTERRUPT_ROLE_MASTER=y +# CONFIG_INTERRUPT_ROLE_SLAVE is not set +CONFIG_PHYTIUM_RTT_TEST=y +CONFIG_ENABLE_RTT_UTEST=y + +# +# RT-Thread Utestcases +# + +# +# Kernel Testcase +# + +# +# CPP11 Testcase +# + +# +# Utest Serial Testcase +# + +# +# RTT Posix Testcase +# + +# +# Memory Management Subsytem Testcase +# +# CONFIG_ENABLE_KERNEL_TEST is not set +# CONFIG_ENABLE_KERNEL_SAMPLE is not set +# CONFIG_ENABLE_COREMARK is not set +# CONFIG_ENABLE_DHRYSTONE is not set diff --git a/bsp/phytium/aarch32/configs/e2000d_rtthread_test.h b/bsp/phytium/aarch32/configs/e2000d_rtthread_test.h new file mode 100644 index 00000000000..ca41af627ed --- /dev/null +++ b/bsp/phytium/aarch32/configs/e2000d_rtthread_test.h @@ -0,0 +1,447 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 16 +#define RT_USING_SMP +#define RT_CPUS_NR 2 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 4096 +#define SYSTEM_THREAD_STACK_SIZE 4096 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 4096 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_KPRINTF_USING_LONGLONG +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_PAGE_MAX_ORDER 11 +#define RT_USING_SLAB +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 256 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50001 +#define RT_USING_CACHE +#define RT_USING_HW_ATOMIC +#define RT_USING_CPU_FFS +#define ARCH_MM_MMU +#define ARCH_ARM +#define ARCH_ARM_MMU +#define ARCH_ARM_CORTEX_A +#define RT_USING_GIC_V3 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_RAMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 4096 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 1024 +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 4096 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + +#define RT_USING_POSIX_FS +#define RT_USING_POSIX_DEVIO +#define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_POLL +#define RT_USING_POSIX_SELECT +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_AIO +#define RT_USING_POSIX_DELAY +#define RT_USING_POSIX_CLOCK +#define RT_USING_POSIX_TIMER + +/* Interprocess Communication (IPC) */ + +#define RT_USING_POSIX_PIPE +#define RT_USING_POSIX_PIPE_SIZE 512 +#define RT_USING_POSIX_MESSAGE_QUEUE +#define RT_USING_POSIX_MESSAGE_SEMAPHORE + +/* Socket is in the 'Network' category */ + + +/* Network */ + +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING + +/* Utilities */ + +#define RT_USING_RYM +#define YMODEM_USING_FILE_TRANSFER +#define RT_USING_UTEST +#define UTEST_THR_STACK_SIZE 4096 +#define UTEST_THR_PRIORITY 20 +#define RT_USING_ADT + +/* RT-Thread Utestcases */ + +#define RT_USING_UTESTCASES + +/* Utest Self Testcase */ + +#define UTEST_SELF_PASS_TC + +/* Kernel Testcase */ + +#define UTEST_MEMHEAP_TC +#define UTEST_SLAB_TC +#define UTEST_IRQ_TC +#define UTEST_SEMAPHORE_TC +#define UTEST_EVENT_TC +#define UTEST_TIMER_TC +#define UTEST_MUTEX_TC +#define UTEST_MAILBOX_TC +#define UTEST_THREAD_TC +#define UTEST_ATOMIC_TC + +/* CPP11 Testcase */ + + +/* Utest Serial Testcase */ + + +/* RTT Posix Testcase */ + +#define RTT_POSIX_TESTCASE +#define RTT_POSIX_TESTCASE_STDIO_H +#define RTT_POSIX_TESTCASE_STDLIB_H +#define RTT_POSIX_TESTCASE_UNISTD_H + +/* Memory Management Subsytem Testcase */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 + +/* Board extended module Drivers */ + +#define PHYTIUM_ARCH_AARCH32 + +/* Standalone Setting */ + +#define TARGET_ARMV8_AARCH32 +#define USE_AARCH64_L1_TO_AARCH32 + +/* Board Configuration */ + +#define TARGET_E2000D +#define TARGET_E2000 +#define DEFAULT_DEBUG_PRINT_UART1 + +/* Components Configuration */ + +#define USE_GIC +#define ENABLE_GICV3 +#define USE_IOPAD +#define ENABLE_IOPAD +#define USE_SERIAL + +/* Usart Configuration */ + +#define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON + +/* Sdk common configuration */ + +#define LOG_ERROR +#define USE_DEFAULT_INTERRUPT_CONFIG +#define INTERRUPT_ROLE_MASTER +#define PHYTIUM_RTT_TEST +#define ENABLE_RTT_UTEST + +/* RT-Thread Utestcases */ + +/* Kernel Testcase */ + +/* CPP11 Testcase */ + +/* Utest Serial Testcase */ + +/* RTT Posix Testcase */ + +/* Memory Management Subsytem Testcase */ + + +#endif diff --git a/bsp/phytium/aarch32/configs/e2000q_rtsmart b/bsp/phytium/aarch32/configs/e2000q_rtsmart index e844590ed2a..5271c16f007 100644 --- a/bsp/phytium/aarch32/configs/e2000q_rtsmart +++ b/bsp/phytium/aarch32/configs/e2000q_rtsmart @@ -64,19 +64,19 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # Memory Management # CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_MEMHEAP_FAST_MODE=y # CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP_ISR=y CONFIG_RT_USING_HEAP=y # @@ -150,6 +150,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set CONFIG_RT_USING_LWP=y CONFIG_RT_LWP_MAX_NR=30 @@ -255,9 +256,82 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -298,7 +372,6 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set @@ -570,6 +643,7 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set # CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set # # peripheral libraries and drivers @@ -654,6 +728,7 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_FT5426 is not set # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -729,7 +804,11 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # # AI packages @@ -748,7 +827,10 @@ CONFIG_RT_USING_ADT=y # Signal Processing and Control Algorithm Packages # # CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set # # miscellaneous packages @@ -795,7 +877,6 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set @@ -820,8 +901,9 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set @@ -968,14 +1050,19 @@ CONFIG_RT_USING_ADT=y # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set # # Timing # # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # # Data Processing @@ -1040,6 +1127,8 @@ CONFIG_RT_USING_UART1=y # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 # # Board extended module Drivers @@ -1079,7 +1168,15 @@ CONFIG_USE_SERIAL=y # CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_GPIO is not set -# CONFIG_USE_ETH is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set # CONFIG_USE_CAN is not set # CONFIG_USE_I2C is not set # CONFIG_USE_TIMER is not set diff --git a/bsp/phytium/aarch32/configs/e2000q_rtsmart.h b/bsp/phytium/aarch32/configs/e2000q_rtsmart.h index 4a866173bc9..df5914ff60c 100644 --- a/bsp/phytium/aarch32/configs/e2000q_rtsmart.h +++ b/bsp/phytium/aarch32/configs/e2000q_rtsmart.h @@ -29,7 +29,7 @@ #define RT_KSERVICE_USING_STDLIB #define RT_KPRINTF_USING_LONGLONG -#define RT_USING_DEBUG +#define RT_DEBUG /* Inter-Thread communication */ @@ -42,11 +42,11 @@ /* Memory Management */ #define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_USING_SLAB #define RT_USING_MEMHEAP #define RT_MEMHEAP_FAST_MODE -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR #define RT_USING_HEAP /* Kernel Device Object */ @@ -155,6 +155,59 @@ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING /* Utilities */ @@ -250,7 +303,7 @@ /* Arduino libraries */ -/* Projects */ +/* Projects and Demos */ /* Sensors */ @@ -287,6 +340,8 @@ #define BSP_USING_UART #define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 /* Board extended module Drivers */ @@ -312,6 +367,12 @@ /* Usart Configuration */ #define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON #define LOG_ERROR #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER diff --git a/bsp/phytium/aarch32/configs/e2000q_rtthread b/bsp/phytium/aarch32/configs/e2000q_rtthread index 1ecf99a540b..138851310dd 100644 --- a/bsp/phytium/aarch32/configs/e2000q_rtthread +++ b/bsp/phytium/aarch32/configs/e2000q_rtthread @@ -64,19 +64,19 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # Memory Management # CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_MEMHEAP_FAST_MODE=y # CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP_ISR=y CONFIG_RT_USING_HEAP=y # @@ -148,6 +148,7 @@ CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set # @@ -242,9 +243,82 @@ CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE=y # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +# CONFIG_RT_LWIP_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -285,7 +359,6 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_KAWAII_MQTT is not set # CONFIG_PKG_USING_BC28_MQTT is not set # CONFIG_PKG_USING_WEBTERMINAL is not set -# CONFIG_PKG_USING_LIBMODBUS is not set # CONFIG_PKG_USING_FREEMODBUS is not set # CONFIG_PKG_USING_NANOPB is not set @@ -557,6 +630,7 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_QPC is not set # CONFIG_PKG_USING_AGILE_UPGRADE is not set # CONFIG_PKG_USING_FLASH_BLOB is not set +# CONFIG_PKG_USING_MLIBC is not set # # peripheral libraries and drivers @@ -641,6 +715,7 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_FT5426 is not set # CONFIG_PKG_USING_FT6236 is not set # CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_CST816X is not set # CONFIG_PKG_USING_REALTEK_AMEBA is not set # CONFIG_PKG_USING_STM32_SDIO is not set # CONFIG_PKG_USING_ESP_IDF is not set @@ -716,7 +791,11 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_IO_INPUT_FILTER is not set # CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set # CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_AIP650 is not set # CONFIG_PKG_USING_FINGERPRINT is not set +# CONFIG_PKG_USING_BT_ECB02C is not set +# CONFIG_PKG_USING_UAT is not set +# CONFIG_PKG_USING_SPI_TOOLS is not set # # AI packages @@ -735,7 +814,10 @@ CONFIG_RT_USING_ADT=y # Signal Processing and Control Algorithm Packages # # CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_QPID is not set # CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_KISSFFT is not set # # miscellaneous packages @@ -782,7 +864,6 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_DSTR is not set # CONFIG_PKG_USING_TINYFRAME is not set # CONFIG_PKG_USING_KENDRYTE_DEMO is not set -# CONFIG_PKG_USING_DIGITALCTRL is not set # CONFIG_PKG_USING_UPACKER is not set # CONFIG_PKG_USING_UPARAM is not set # CONFIG_PKG_USING_HELLO is not set @@ -807,8 +888,9 @@ CONFIG_RT_USING_ADT=y # CONFIG_PKG_USING_RTDUINO is not set # -# Projects +# Projects and Demos # +# CONFIG_PKG_USING_ARDUINO_MSGQ_C_CPP_DEMO is not set # CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set # CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set # CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set @@ -955,14 +1037,19 @@ CONFIG_RT_USING_ADT=y # # Display # +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_GFX_LIBRARY is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set -# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ST7735 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SSD1306 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ILI9341 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set # # Timing # # CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set +# CONFIG_PKG_USING_ARDUINO_TICKER is not set +# CONFIG_PKG_USING_ARDUINO_TASKSCHEDULER is not set # # Data Processing @@ -1027,6 +1114,8 @@ CONFIG_RT_USING_UART1=y # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set # CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 # # Board extended module Drivers @@ -1066,7 +1155,15 @@ CONFIG_USE_SERIAL=y # CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_GPIO is not set -# CONFIG_USE_ETH is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set # CONFIG_USE_CAN is not set # CONFIG_USE_I2C is not set # CONFIG_USE_TIMER is not set diff --git a/bsp/phytium/aarch32/configs/e2000q_rtthread.h b/bsp/phytium/aarch32/configs/e2000q_rtthread.h index 7de715186fa..07749b2cf87 100644 --- a/bsp/phytium/aarch32/configs/e2000q_rtthread.h +++ b/bsp/phytium/aarch32/configs/e2000q_rtthread.h @@ -28,7 +28,7 @@ #define RT_KSERVICE_USING_STDLIB #define RT_KPRINTF_USING_LONGLONG -#define RT_USING_DEBUG +#define RT_DEBUG /* Inter-Thread communication */ @@ -41,11 +41,11 @@ /* Memory Management */ #define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_USING_SLAB #define RT_USING_MEMHEAP #define RT_MEMHEAP_FAST_MODE -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR #define RT_USING_HEAP /* Kernel Device Object */ @@ -144,6 +144,59 @@ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING /* Utilities */ @@ -239,7 +292,7 @@ /* Arduino libraries */ -/* Projects */ +/* Projects and Demos */ /* Sensors */ @@ -276,6 +329,8 @@ #define BSP_USING_UART #define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 /* Board extended module Drivers */ @@ -301,6 +356,12 @@ /* Usart Configuration */ #define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON #define LOG_ERROR #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER diff --git a/bsp/phytium/aarch32/makefile b/bsp/phytium/aarch32/makefile index 13f412d6dfb..f095b76c1ec 100644 --- a/bsp/phytium/aarch32/makefile +++ b/bsp/phytium/aarch32/makefile @@ -27,6 +27,10 @@ else RTCONFIG := $(RTCONFIG)_rtthread endif +ifdef CONFIG_PHYTIUM_RTT_TEST +RTCONFIG := $(RTCONFIG)_test +endif + boot: make all cp rtthread_a32.elf /mnt/d/tftboot @@ -59,20 +63,44 @@ load_e2000q_rtsmart: @cp ./configs/e2000q_rtsmart.h ./rtconfig.h -f @scons -c +load_e2000q_rtsmart_test: + @echo "Load configs from ./configs/e2000q_rtsmart_test" + @cp ./configs/e2000q_rtsmart_test ./.config -f + @cp ./configs/e2000q_rtsmart_test.h ./rtconfig.h -f + @scons -c + load_e2000q_rtthread: @echo "Load configs from ./configs/e2000q_rtthread" @cp ./configs/e2000q_rtthread ./.config -f @cp ./configs/e2000q_rtthread.h ./rtconfig.h -f @scons -c +load_e2000q_rtthread_test: + @echo "Load configs from ./configs/e2000q_rtthread_test" + @cp ./configs/e2000q_rtthread_test ./.config -f + @cp ./configs/e2000q_rtthread_test.h ./rtconfig.h -f + @scons -c + load_e2000d_rtsmart: @echo "Load configs from ./configs/e2000d_rtsmart" @cp ./configs/e2000d_rtsmart ./.config -f @cp ./configs/e2000d_rtsmart.h ./rtconfig.h -f @scons -c +load_e2000d_rtsmart_test: + @echo "Load configs from ./configs/e2000d_rtsmart_test" + @cp ./configs/e2000d_rtsmart_test ./.config -f + @cp ./configs/e2000d_rtsmart_test.h ./rtconfig.h -f + @scons -c + load_e2000d_rtthread: @echo "Load configs from ./configs/e2000d_rtthread" @cp ./configs/e2000d_rtthread ./.config -f @cp ./configs/e2000d_rtthread.h ./rtconfig.h -f + scons -c + +load_e2000d_rtthread_test: + @echo "Load configs from ./configs/e2000d_rtthread_test" + @cp ./configs/e2000d_rtthread_test ./.config -f + @cp ./configs/e2000d_rtthread_test.h ./rtconfig.h -f scons -c \ No newline at end of file diff --git a/bsp/phytium/aarch32/rtconfig.h b/bsp/phytium/aarch32/rtconfig.h index 4146488599e..d3f21544885 100644 --- a/bsp/phytium/aarch32/rtconfig.h +++ b/bsp/phytium/aarch32/rtconfig.h @@ -29,7 +29,10 @@ #define RT_KSERVICE_USING_STDLIB #define RT_KPRINTF_USING_LONGLONG -#define RT_DEBUG +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ @@ -38,15 +41,16 @@ #define RT_USING_EVENT #define RT_USING_MAILBOX #define RT_USING_MESSAGEQUEUE +#define RT_USING_MESSAGEQUEUE_PRIORITY /* Memory Management */ #define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_USING_SLAB #define RT_USING_MEMHEAP #define RT_MEMHEAP_FAST_MODE -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR #define RT_USING_HEAP /* Kernel Device Object */ @@ -56,6 +60,9 @@ #define RT_CONSOLEBUF_SIZE 256 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x50001 + +/* RT-Thread Architecture */ + #define RT_USING_CACHE #define RT_USING_HW_ATOMIC #define RT_USING_CPU_FFS @@ -95,8 +102,24 @@ #define RT_USING_DFS_V1 #define DFS_FILESYSTEMS_MAX 4 #define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS #define RT_USING_DFS_RAMFS +#define RT_USING_DFS_MQUEUE #define RT_USING_LWP #define RT_LWP_MAX_NR 30 #define LWP_TASK_STACK_SIZE 16384 @@ -122,6 +145,13 @@ #define RT_USING_ZERO #define RT_USING_RANDOM #define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 4096 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 +#define RT_USING_DEV_BUS /* Using USB */ @@ -155,6 +185,59 @@ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING /* Utilities */ @@ -163,8 +246,13 @@ #define RT_USING_UTEST #define UTEST_THR_STACK_SIZE 4096 #define UTEST_THR_PRIORITY 20 +#define RT_USING_RESOURCE_ID #define RT_USING_ADT #define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF +#define RT_USING_KTIME /* RT-Thread Utestcases */ @@ -251,7 +339,7 @@ /* Arduino libraries */ -/* Projects */ +/* Projects and Demos */ /* Sensors */ @@ -288,6 +376,11 @@ #define BSP_USING_UART #define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 /* Board extended module Drivers */ @@ -308,11 +401,22 @@ #define USE_GIC #define ENABLE_GICV3 +#define USE_IOPAD +#define ENABLE_IOPAD #define USE_SERIAL /* Usart Configuration */ #define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON + +/* Sdk common configuration */ + #define LOG_ERROR #define USE_DEFAULT_INTERRUPT_CONFIG #define INTERRUPT_ROLE_MASTER diff --git a/bsp/phytium/aarch32/rtconfig.py b/bsp/phytium/aarch32/rtconfig.py index 507716031f8..6bc9bb4437c 100644 --- a/bsp/phytium/aarch32/rtconfig.py +++ b/bsp/phytium/aarch32/rtconfig.py @@ -16,6 +16,7 @@ PREFIX = os.getenv('RTT_CC_PREFIX') or 'arm-none-eabi-' CC = PREFIX + 'gcc' CXX = PREFIX + 'g++' + CPP = PREFIX + 'cpp' AS = PREFIX + 'gcc' AR = PREFIX + 'ar' LINK = PREFIX + 'gcc' @@ -28,6 +29,7 @@ AFPFLAGS = ' -mfloat-abi=softfp -mfpu=neon' DEVICE = ' -march=armv8-a -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' + CPPFLAGS= ' -E -P -x assembler-with-cpp' CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always' CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -D_POSIX_SOURCE -fdiagnostics-color=always' AFLAGS = DEVICE + ' -c' + AFPFLAGS + ' -x assembler-with-cpp' diff --git a/bsp/phytium/aarch64/.config b/bsp/phytium/aarch64/.config index 24e339bf7c9..72b8700b982 100644 --- a/bsp/phytium/aarch64/.config +++ b/bsp/phytium/aarch64/.config @@ -9,6 +9,7 @@ CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set CONFIG_RT_USING_SMP=y CONFIG_RT_CPUS_NR=2 CONFIG_RT_ALIGN_SIZE=4 @@ -22,11 +23,11 @@ CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=40960 -CONFIG_SYSTEM_THREAD_STACK_SIZE=40960 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 +CONFIG_SYSTEM_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 # # kservice optimization @@ -36,19 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set CONFIG_RT_KPRINTF_USING_LONGLONG=y -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_PAGE_LEAK is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set # # Inter-Thread communication @@ -58,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_PAGE_MAX_ORDER=16 +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_MEMHEAP_FAST_MODE=y # CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP_ISR=y CONFIG_RT_USING_HEAP=y # @@ -91,9 +85,13 @@ CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set + +# +# RT-Thread Architecture +# CONFIG_ARCH_CPU_64BIT=y CONFIG_RT_USING_CACHE=y -CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_RT_USING_HW_ATOMIC is not set CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # CONFIG_RT_USING_CPU_FFS is not set @@ -101,6 +99,10 @@ CONFIG_ARCH_MM_MMU=y CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_MMU=y CONFIG_ARCH_ARMV8=y +CONFIG_ARCH_TEXT_OFFSET=0x80000 +CONFIG_ARCH_RAM_OFFSET=0x80000000 +CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 +CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y # # RT-Thread Components @@ -138,12 +140,36 @@ CONFIG_RT_USING_DFS_V1=y # CONFIG_RT_USING_DFS_V2 is not set CONFIG_DFS_FILESYSTEMS_MAX=4 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set # @@ -178,7 +204,13 @@ CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set @@ -237,9 +269,110 @@ CONFIG_RT_USING_POSIX_TIMER=y # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +CONFIG_RT_LWIP_DEBUG=y +# CONFIG_RT_LWIP_SYS_DEBUG is not set +# CONFIG_RT_LWIP_ETHARP_DEBUG is not set +# CONFIG_RT_LWIP_PPP_DEBUG is not set +# CONFIG_RT_LWIP_MEM_DEBUG is not set +# CONFIG_RT_LWIP_MEMP_DEBUG is not set +# CONFIG_RT_LWIP_PBUF_DEBUG is not set +# CONFIG_RT_LWIP_API_LIB_DEBUG is not set +# CONFIG_RT_LWIP_API_MSG_DEBUG is not set +# CONFIG_RT_LWIP_TCPIP_DEBUG is not set +CONFIG_RT_LWIP_NETIF_DEBUG=y +# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set +# CONFIG_RT_LWIP_DNS_DEBUG is not set +# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set +# CONFIG_RT_LWIP_DHCP_DEBUG is not set +# CONFIG_RT_LWIP_IP_DEBUG is not set +# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set +# CONFIG_RT_LWIP_ICMP_DEBUG is not set +# CONFIG_RT_LWIP_IGMP_DEBUG is not set +# CONFIG_RT_LWIP_UDP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set +# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set +# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -251,10 +384,15 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_RESOURCE_ID=y CONFIG_RT_USING_ADT=y CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +CONFIG_RT_USING_KTIME=y # # RT-Thread Utestcases @@ -1043,7 +1181,15 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART0 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set # # Board extended module Drivers @@ -1083,6 +1229,8 @@ CONFIG_USE_QSPI=y # CONFIG_USE_FQSPI=y # CONFIG_USE_GIC is not set +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y CONFIG_USE_SERIAL=y # @@ -1090,7 +1238,15 @@ CONFIG_USE_SERIAL=y # CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_GPIO is not set -# CONFIG_USE_ETH is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set # CONFIG_USE_CAN is not set # CONFIG_USE_I2C is not set # CONFIG_USE_TIMER is not set @@ -1108,13 +1264,17 @@ CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_IPC is not set # CONFIG_USE_MEDIA is not set # CONFIG_USE_SCMI_MHU is not set + +# +# Sdk common configuration +# # CONFIG_LOG_VERBOS is not set # CONFIG_LOG_DEBUG is not set # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y # CONFIG_LOG_NONE is not set -# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set # CONFIG_LOG_EXTRA_INFO is not set # CONFIG_LOG_DISPALY_CORE_NUM is not set # CONFIG_BOOTUP_DEBUG_PRINTS is not set +# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set diff --git a/bsp/phytium/aarch64/Kconfig b/bsp/phytium/aarch64/Kconfig index 25f6b180c35..ad91af90866 100644 --- a/bsp/phytium/aarch64/Kconfig +++ b/bsp/phytium/aarch64/Kconfig @@ -65,5 +65,3 @@ menu "Standalone Setting" endmenu - - diff --git a/bsp/phytium/aarch64/README.md b/bsp/phytium/aarch64/README.md index 94dace980d2..af1b3a7d666 100644 --- a/bsp/phytium/aarch64/README.md +++ b/bsp/phytium/aarch64/README.md @@ -114,6 +114,12 @@ rtthread_a64.map - 可以用串口通过 XMODEM 协议将 bin/elf 文件上传到开发板，然后启动， +- 如果使用 SD-1 控制器 + +``` +mw.l 0x32b31178 0x1f +``` + - 首先在 Phytium 开发板上输入，上传 bin 文件 ``` diff --git a/bsp/phytium/aarch64/SConstruct b/bsp/phytium/aarch64/SConstruct index 8132cd8deff..ae659dfb217 100644 --- a/bsp/phytium/aarch64/SConstruct +++ b/bsp/phytium/aarch64/SConstruct @@ -53,10 +53,6 @@ if not IS_EXPORTED: # if project is not exported, libraries and board need to ma # include board objs.extend(SConscript(os.path.join(BSP_ROOT + '/board', 'SConscript'))) -if GetDepend('RT_USING_SMART'): - # use smart link.lds - env['LINKFLAGS'] = env['LINKFLAGS'].replace('link.lds', 'link_smart.lds') - # make a building DoBuilding(TARGET, objs) diff --git a/bsp/phytium/aarch64/applications/mnt.c b/bsp/phytium/aarch64/applications/mnt.c index 447f518f78d..cd631ce5066 100644 --- a/bsp/phytium/aarch64/applications/mnt.c +++ b/bsp/phytium/aarch64/applications/mnt.c @@ -8,56 +8,88 @@ * Change Logs: * Date Author Notes * 2023-04-27 huanghe first version + * 2023-07-14 liqiaozhong add SD file sys mount func * */ - #include -#ifdef RT_USING_DFS_RAMFS -#include - -extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); - -int mnt_init(void) -{ - rt_uint8_t *pool = RT_NULL; - rt_size_t size = 8*1024*1024; - - pool = rt_malloc(size); - if (pool == RT_NULL) - return 0; - - if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) - rt_kprintf("RAM file system initializated!\n"); - else - rt_kprintf("RAM file system initializate failed!\n"); - - return 0; -} -INIT_ENV_EXPORT(mnt_init); -#endif +#if defined(RT_USING_DFS) +#include -#ifdef BSP_USING_SDCARD_FATFS #include #include + #define DBG_TAG "app.filesystem" #define DBG_LVL DBG_INFO -#include + +#ifdef BSP_USING_SDCARD_FATFS +#define SD_DEIVCE_NAME "sd" static int filesystem_mount(void) { - while(rt_device_find("sd0") == RT_NULL) + while (rt_device_find(SD_DEIVCE_NAME) == RT_NULL) { rt_thread_mdelay(1); } - int ret = dfs_mount("sd0", "/", "elm", 0, 0); - if (ret != 0) + if (dfs_mount(SD_DEIVCE_NAME, "/", "elm", 0, 0) == 0) + { + LOG_I("file system initialization done!\n"); + } + else { - rt_kprintf("ret: %d\n",ret); - LOG_E("sd0 mount to '/' failed!"); - return ret; + LOG_W("[sd] File System on SD initialization failed!"); + LOG_W("[sd] Try to format and re-mount..."); + if (dfs_mkfs("elm", SD_DEIVCE_NAME) == 0) + { + if (dfs_mount(SD_DEIVCE_NAME, "/", "elm", 0, 0) == 0) + { + LOG_I("[sd] File System on SD initialized!"); + } + } + LOG_E("[sd] File System on SD initialization failed!"); + return -1; } + mkdir("/ram", 0x777); + +#ifdef RT_USING_DFS_RAMFS + extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); + + rt_uint8_t *pool = RT_NULL; + rt_size_t size = 8 * 1024 * 1024; + + pool = rt_malloc(size); + if (pool == RT_NULL) + LOG_E("Malloc fail!"); + + if (dfs_mount(RT_NULL, "/ram", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) + LOG_I("RAM file system initializated!"); + else + LOG_E("RAM file system initializate failed!"); +#endif return RT_EOK; } INIT_ENV_EXPORT(filesystem_mount); +#else +static int filesystem_mount(void) +{ +#ifdef RT_USING_DFS_RAMFS + extern struct dfs_ramfs *dfs_ramfs_create(rt_uint8_t *pool, rt_size_t size); + + rt_uint8_t *pool = RT_NULL; + rt_size_t size = 8 * 1024 * 1024; + + pool = rt_malloc(size); + if (pool == RT_NULL) + LOG_E("Malloc fail!"); + + if (dfs_mount(RT_NULL, "/", "ram", 0, (const void *)dfs_ramfs_create(pool, size)) == 0) + LOG_I("RAM file system initializated!"); + else + LOG_E("RAM file system initializate failed!"); #endif + + return RT_EOK; +} +INIT_ENV_EXPORT(filesystem_mount); +#endif // #ifdef BSP_USING_SDCARD_FATFS +#endif // #if defined(RT_USING_DFS) \ No newline at end of file diff --git a/bsp/phytium/aarch64/configs/e2000d_rtsmart b/bsp/phytium/aarch64/configs/e2000d_rtsmart index d938d301eab..1c34ffbbc08 100644 --- a/bsp/phytium/aarch64/configs/e2000d_rtsmart +++ b/bsp/phytium/aarch64/configs/e2000d_rtsmart @@ -9,6 +9,7 @@ CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set CONFIG_RT_USING_SMART=y +# CONFIG_RT_USING_AMP is not set CONFIG_RT_USING_SMP=y CONFIG_RT_CPUS_NR=2 CONFIG_RT_ALIGN_SIZE=4 @@ -22,11 +23,11 @@ CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=40960 -CONFIG_SYSTEM_THREAD_STACK_SIZE=40960 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 +CONFIG_SYSTEM_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 # # kservice optimization @@ -36,18 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set CONFIG_RT_KPRINTF_USING_LONGLONG=y -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set # # Inter-Thread communication @@ -57,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_PAGE_MAX_ORDER=16 +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_MEMHEAP_FAST_MODE=y # CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP_ISR=y CONFIG_RT_USING_HEAP=y # @@ -90,9 +85,13 @@ CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set + +# +# RT-Thread Architecture +# CONFIG_ARCH_CPU_64BIT=y CONFIG_RT_USING_CACHE=y -CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_RT_USING_HW_ATOMIC is not set CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # CONFIG_RT_USING_CPU_FFS is not set @@ -101,6 +100,10 @@ CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_MMU=y CONFIG_KERNEL_VADDR_START=0xffff000000000000 CONFIG_ARCH_ARMV8=y +CONFIG_ARCH_TEXT_OFFSET=0x80000 +CONFIG_ARCH_RAM_OFFSET=0x80000000 +CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 +CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y # # RT-Thread Components @@ -138,12 +141,36 @@ CONFIG_RT_USING_DFS_V1=y # CONFIG_RT_USING_DFS_V2 is not set CONFIG_DFS_FILESYSTEMS_MAX=4 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set CONFIG_RT_USING_LWP=y CONFIG_RT_LWP_MAX_NR=30 @@ -188,7 +215,13 @@ CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set @@ -247,9 +280,110 @@ CONFIG_RT_USING_POSIX_TIMER=y # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +CONFIG_RT_LWIP_DEBUG=y +# CONFIG_RT_LWIP_SYS_DEBUG is not set +# CONFIG_RT_LWIP_ETHARP_DEBUG is not set +# CONFIG_RT_LWIP_PPP_DEBUG is not set +# CONFIG_RT_LWIP_MEM_DEBUG is not set +# CONFIG_RT_LWIP_MEMP_DEBUG is not set +# CONFIG_RT_LWIP_PBUF_DEBUG is not set +# CONFIG_RT_LWIP_API_LIB_DEBUG is not set +# CONFIG_RT_LWIP_API_MSG_DEBUG is not set +# CONFIG_RT_LWIP_TCPIP_DEBUG is not set +CONFIG_RT_LWIP_NETIF_DEBUG=y +# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set +# CONFIG_RT_LWIP_DNS_DEBUG is not set +# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set +# CONFIG_RT_LWIP_DHCP_DEBUG is not set +# CONFIG_RT_LWIP_IP_DEBUG is not set +# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set +# CONFIG_RT_LWIP_ICMP_DEBUG is not set +# CONFIG_RT_LWIP_IGMP_DEBUG is not set +# CONFIG_RT_LWIP_UDP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set +# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set +# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -261,9 +395,15 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_RESOURCE_ID=y CONFIG_RT_USING_ADT=y +CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +CONFIG_RT_USING_KTIME=y # # RT-Thread Utestcases @@ -1052,7 +1192,15 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART0 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set # # Board extended module Drivers @@ -1092,6 +1240,8 @@ CONFIG_USE_QSPI=y # CONFIG_USE_FQSPI=y # CONFIG_USE_GIC is not set +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y CONFIG_USE_SERIAL=y # @@ -1099,7 +1249,15 @@ CONFIG_USE_SERIAL=y # CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_GPIO is not set -# CONFIG_USE_ETH is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set # CONFIG_USE_CAN is not set # CONFIG_USE_I2C is not set # CONFIG_USE_TIMER is not set @@ -1117,13 +1275,17 @@ CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_IPC is not set # CONFIG_USE_MEDIA is not set # CONFIG_USE_SCMI_MHU is not set + +# +# Sdk common configuration +# # CONFIG_LOG_VERBOS is not set # CONFIG_LOG_DEBUG is not set # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y # CONFIG_LOG_NONE is not set -# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set # CONFIG_LOG_EXTRA_INFO is not set # CONFIG_LOG_DISPALY_CORE_NUM is not set # CONFIG_BOOTUP_DEBUG_PRINTS is not set +# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set diff --git a/bsp/phytium/aarch64/configs/e2000d_rtsmart.h b/bsp/phytium/aarch64/configs/e2000d_rtsmart.h index 4b8c32c9aab..0398272f394 100644 --- a/bsp/phytium/aarch64/configs/e2000d_rtsmart.h +++ b/bsp/phytium/aarch64/configs/e2000d_rtsmart.h @@ -19,17 +19,20 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 40960 -#define SYSTEM_THREAD_STACK_SIZE 40960 +#define IDLE_THREAD_STACK_SIZE 8192 +#define SYSTEM_THREAD_STACK_SIZE 8192 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 4096 +#define RT_TIMER_THREAD_STACK_SIZE 8192 /* kservice optimization */ #define RT_KSERVICE_USING_STDLIB #define RT_KPRINTF_USING_LONGLONG #define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ @@ -41,12 +44,12 @@ /* Memory Management */ -#define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_PAGE_MAX_ORDER 16 +#define RT_USING_SLAB #define RT_USING_MEMHEAP #define RT_MEMHEAP_FAST_MODE -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR #define RT_USING_HEAP /* Kernel Device Object */ @@ -56,15 +59,21 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x50001 + +/* RT-Thread Architecture */ + #define ARCH_CPU_64BIT #define RT_USING_CACHE -#define RT_USING_HW_ATOMIC #define ARCH_ARM_BOOTWITH_FLUSH_CACHE #define ARCH_MM_MMU #define ARCH_ARM #define ARCH_ARM_MMU #define KERNEL_VADDR_START 0xffff000000000000 #define ARCH_ARMV8 +#define ARCH_TEXT_OFFSET 0x80000 +#define ARCH_RAM_OFFSET 0x80000000 +#define ARCH_SECONDARY_CPU_STACK_SIZE 4096 +#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS /* RT-Thread Components */ @@ -95,6 +104,21 @@ #define RT_USING_DFS_V1 #define DFS_FILESYSTEMS_MAX 4 #define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS #define RT_USING_DFS_RAMFS #define RT_USING_LWP @@ -121,6 +145,12 @@ #define RT_USING_ZERO #define RT_USING_RANDOM #define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 4096 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 /* Using USB */ @@ -147,12 +177,73 @@ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +#define RT_LWIP_DEBUG +#define RT_LWIP_NETIF_DEBUG /* Utilities */ #define RT_USING_RYM #define YMODEM_USING_FILE_TRANSFER +#define RT_USING_RESOURCE_ID #define RT_USING_ADT +#define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF +#define RT_USING_KTIME /* RT-Thread Utestcases */ @@ -279,6 +370,11 @@ #define BSP_USING_UART #define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 /* Board extended module Drivers */ @@ -306,11 +402,22 @@ /* Qspi Configuration */ #define USE_FQSPI +#define USE_IOPAD +#define ENABLE_IOPAD #define USE_SERIAL /* Usart Configuration */ #define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON + +/* Sdk common configuration */ + #define LOG_ERROR #endif diff --git a/bsp/phytium/aarch64/configs/e2000d_rtsmart_test b/bsp/phytium/aarch64/configs/e2000d_rtsmart_test new file mode 100644 index 00000000000..63c61429c80 --- /dev/null +++ b/bsp/phytium/aarch64/configs/e2000d_rtsmart_test @@ -0,0 +1,1284 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +CONFIG_RT_USING_SMP=y +CONFIG_RT_CPUS_NR=2 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=40960 +CONFIG_SYSTEM_THREAD_STACK_SIZE=40960 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +CONFIG_RT_KPRINTF_USING_LONGLONG=y +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_PAGE_LEAK is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_PAGE_MAX_ORDER=16 +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP_ISR=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_HW_ATOMIC is not set +CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_KERNEL_VADDR_START=0xffff000000000000 +CONFIG_ARCH_ARMV8=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +CONFIG_RT_USING_DFS_RAMFS=y +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_NFS is not set +# CONFIG_RT_USING_FAL is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +CONFIG_RT_USING_TTY=y +# CONFIG_RT_TTY_DEBUG is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +CONFIG_RT_USING_POSIX_DEVIO=y +CONFIG_RT_USING_POSIX_STDIO=y +# CONFIG_RT_USING_POSIX_POLL is not set +# CONFIG_RT_USING_POSIX_SELECT is not set +# CONFIG_RT_USING_POSIX_SOCKET is not set +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set +CONFIG_RT_USING_POSIX_DELAY=y +CONFIG_RT_USING_POSIX_CLOCK=y +CONFIG_RT_USING_POSIX_TIMER=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +CONFIG_RT_LWIP_DEBUG=y +# CONFIG_RT_LWIP_SYS_DEBUG is not set +# CONFIG_RT_LWIP_ETHARP_DEBUG is not set +# CONFIG_RT_LWIP_PPP_DEBUG is not set +# CONFIG_RT_LWIP_MEM_DEBUG is not set +# CONFIG_RT_LWIP_MEMP_DEBUG is not set +# CONFIG_RT_LWIP_PBUF_DEBUG is not set +# CONFIG_RT_LWIP_API_LIB_DEBUG is not set +# CONFIG_RT_LWIP_API_MSG_DEBUG is not set +# CONFIG_RT_LWIP_TCPIP_DEBUG is not set +CONFIG_RT_LWIP_NETIF_DEBUG=y +# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set +# CONFIG_RT_LWIP_DNS_DEBUG is not set +# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set +# CONFIG_RT_LWIP_DHCP_DEBUG is not set +# CONFIG_RT_LWIP_IP_DEBUG is not set +# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set +# CONFIG_RT_LWIP_ICMP_DEBUG is not set +# CONFIG_RT_LWIP_IGMP_DEBUG is not set +# CONFIG_RT_LWIP_UDP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set +# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set +# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +CONFIG_RT_USING_RYM=y +# CONFIG_YMODEM_USING_CRC_TABLE is not set +CONFIG_YMODEM_USING_FILE_TRANSFER=y +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_ADT=y +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_FINGERPRINT is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +CONFIG_PKG_USING_KERNEL_SAMPLES=y +CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples" +# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set +# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set +CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y +CONFIG_PKG_KERNEL_SAMPLES_VER="latest" +CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y +# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set +# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set +# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set +# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set +# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set +# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set +# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set +# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set +# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set +# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set +# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set +# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set +# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set +# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set +# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set +# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set +# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set +# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_RT_USING_UART1=y +# CONFIG_RT_USING_UART0 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set + +# +# Board extended module Drivers +# +CONFIG_BSP_USING_GIC=y +CONFIG_BSP_USING_GICV3=y +CONFIG_PHYTIUM_ARCH_AARCH64=y +CONFIG_ARM_SPI_BIND_CPU_ID=0 + +# +# Standalone Setting +# +CONFIG_TARGET_ARMV8_AARCH64=y + +# +# Board Configuration +# +# CONFIG_TARGET_F2000_4 is not set +# CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_E2000Q is not set +CONFIG_TARGET_E2000D=y +# CONFIG_TARGET_E2000S is not set +CONFIG_TARGET_E2000=y +CONFIG_DEFAULT_DEBUG_PRINT_UART1=y +# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set +# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set + +# +# Components Configuration +# +CONFIG_USE_SPI=y +CONFIG_USE_FSPIM=y +CONFIG_USE_QSPI=y + +# +# Qspi Configuration +# +CONFIG_USE_FQSPI=y +# CONFIG_USE_GIC is not set +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y +CONFIG_USE_SERIAL=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# CONFIG_USE_GPIO is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set +# CONFIG_USE_CAN is not set +# CONFIG_USE_I2C is not set +# CONFIG_USE_TIMER is not set +# CONFIG_USE_MIO is not set +# CONFIG_USE_SDMMC is not set +# CONFIG_USE_PCIE is not set +# CONFIG_USE_WDT is not set +# CONFIG_USE_DMA is not set +# CONFIG_USE_NAND is not set +# CONFIG_USE_RTC is not set +# CONFIG_USE_SATA is not set +# CONFIG_USE_USB is not set +# CONFIG_USE_ADC is not set +# CONFIG_USE_PWM is not set +# CONFIG_USE_IPC is not set +# CONFIG_USE_MEDIA is not set +# CONFIG_USE_SCMI_MHU is not set +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set +# CONFIG_LOG_EXTRA_INFO is not set +# CONFIG_LOG_DISPALY_CORE_NUM is not set +# CONFIG_BOOTUP_DEBUG_PRINTS is not set +CONFIG_PHYTIUM_RTT_TEST=y +# CONFIG_ENABLE_RTT_UTEST is not set +# CONFIG_ENABLE_KERNEL_TEST is not set +# CONFIG_ENABLE_KERNEL_SAMPLE is not set +# CONFIG_ENABLE_COREMARK is not set +# CONFIG_ENABLE_DHRYSTONE is not set diff --git a/bsp/phytium/aarch64/configs/e2000d_rtsmart_test.h b/bsp/phytium/aarch64/configs/e2000d_rtsmart_test.h new file mode 100644 index 00000000000..03c1c48df90 --- /dev/null +++ b/bsp/phytium/aarch64/configs/e2000d_rtsmart_test.h @@ -0,0 +1,405 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 16 +#define RT_USING_SMART +#define RT_USING_SMP +#define RT_CPUS_NR 2 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 40960 +#define SYSTEM_THREAD_STACK_SIZE 40960 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 4096 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_KPRINTF_USING_LONGLONG +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_PAGE_MAX_ORDER 16 +#define RT_USING_SLAB +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50001 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_ARM_BOOTWITH_FLUSH_CACHE +#define ARCH_MM_MMU +#define ARCH_ARM +#define ARCH_ARM_MMU +#define KERNEL_VADDR_START 0xffff000000000000 +#define ARCH_ARMV8 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_RAMFS +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_TTY +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 4096 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + +#define RT_USING_POSIX_FS +#define RT_USING_POSIX_DEVIO +#define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_DELAY +#define RT_USING_POSIX_CLOCK +#define RT_USING_POSIX_TIMER + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +#define RT_LWIP_DEBUG +#define RT_LWIP_NETIF_DEBUG + +/* Utilities */ + +#define RT_USING_RYM +#define YMODEM_USING_FILE_TRANSFER +#define RT_USING_ADT + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + +#define PKG_USING_KERNEL_SAMPLES +#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION +#define PKG_USING_KERNEL_SAMPLES_EN + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 + +/* Board extended module Drivers */ + +#define BSP_USING_GIC +#define BSP_USING_GICV3 +#define PHYTIUM_ARCH_AARCH64 +#define ARM_SPI_BIND_CPU_ID 0 + +/* Standalone Setting */ + +#define TARGET_ARMV8_AARCH64 + +/* Board Configuration */ + +#define TARGET_E2000D +#define TARGET_E2000 +#define DEFAULT_DEBUG_PRINT_UART1 + +/* Components Configuration */ + +#define USE_SPI +#define USE_FSPIM +#define USE_QSPI + +/* Qspi Configuration */ + +#define USE_FQSPI +#define USE_IOPAD +#define ENABLE_IOPAD +#define USE_SERIAL + +/* Usart Configuration */ + +#define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON +#define LOG_ERROR +#define PHYTIUM_RTT_TEST + +#endif diff --git a/bsp/phytium/aarch64/configs/e2000d_rtthread b/bsp/phytium/aarch64/configs/e2000d_rtthread index b228d85dfcf..72b8700b982 100644 --- a/bsp/phytium/aarch64/configs/e2000d_rtthread +++ b/bsp/phytium/aarch64/configs/e2000d_rtthread @@ -9,6 +9,7 @@ CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMART is not set +# CONFIG_RT_USING_AMP is not set CONFIG_RT_USING_SMP=y CONFIG_RT_CPUS_NR=2 CONFIG_RT_ALIGN_SIZE=4 @@ -22,11 +23,11 @@ CONFIG_RT_USING_HOOK=y CONFIG_RT_HOOK_USING_FUNC_PTR=y CONFIG_RT_USING_IDLE_HOOK=y CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 -CONFIG_IDLE_THREAD_STACK_SIZE=40960 -CONFIG_SYSTEM_THREAD_STACK_SIZE=40960 +CONFIG_IDLE_THREAD_STACK_SIZE=8192 +CONFIG_SYSTEM_THREAD_STACK_SIZE=8192 CONFIG_RT_USING_TIMER_SOFT=y CONFIG_RT_TIMER_THREAD_PRIO=4 -CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=8192 # # kservice optimization @@ -36,18 +37,11 @@ CONFIG_RT_KSERVICE_USING_STDLIB=y # CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set # CONFIG_RT_USING_TINY_FFS is not set CONFIG_RT_KPRINTF_USING_LONGLONG=y -CONFIG_RT_DEBUG=y -# CONFIG_RT_DEBUG_COLOR is not set -# CONFIG_RT_DEBUG_INIT_CONFIG is not set -# CONFIG_RT_DEBUG_THREAD_CONFIG is not set -# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set -# CONFIG_RT_DEBUG_IPC_CONFIG is not set -# CONFIG_RT_DEBUG_TIMER_CONFIG is not set -# CONFIG_RT_DEBUG_IRQ_CONFIG is not set -# CONFIG_RT_DEBUG_MEM_CONFIG is not set -# CONFIG_RT_DEBUG_SLAB_CONFIG is not set -# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set -# CONFIG_RT_DEBUG_MODULE_CONFIG is not set +CONFIG_RT_USING_DEBUG=y +CONFIG_RT_DEBUGING_COLOR=y +CONFIG_RT_DEBUGING_CONTEXT=y +CONFIG_RT_DEBUGING_INIT=y +# CONFIG_RT_DEBUGING_PAGE_LEAK is not set # # Inter-Thread communication @@ -57,25 +51,26 @@ CONFIG_RT_USING_MUTEX=y CONFIG_RT_USING_EVENT=y CONFIG_RT_USING_MAILBOX=y CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_MESSAGEQUEUE_PRIORITY is not set # CONFIG_RT_USING_SIGNALS is not set # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_PAGE_MAX_ORDER=16 +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_MEMHEAP_FAST_MODE=y # CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP_ISR=y CONFIG_RT_USING_HEAP=y # @@ -90,9 +85,13 @@ CONFIG_RT_CONSOLEBUF_SIZE=128 CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set + +# +# RT-Thread Architecture +# CONFIG_ARCH_CPU_64BIT=y CONFIG_RT_USING_CACHE=y -CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_RT_USING_HW_ATOMIC is not set CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # CONFIG_RT_USING_CPU_FFS is not set @@ -100,6 +99,10 @@ CONFIG_ARCH_MM_MMU=y CONFIG_ARCH_ARM=y CONFIG_ARCH_ARM_MMU=y CONFIG_ARCH_ARMV8=y +CONFIG_ARCH_TEXT_OFFSET=0x80000 +CONFIG_ARCH_RAM_OFFSET=0x80000000 +CONFIG_ARCH_SECONDARY_CPU_STACK_SIZE=4096 +CONFIG_ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS=y # # RT-Thread Components @@ -137,12 +140,36 @@ CONFIG_RT_USING_DFS_V1=y # CONFIG_RT_USING_DFS_V2 is not set CONFIG_DFS_FILESYSTEMS_MAX=4 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_MQUEUE is not set +# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set # @@ -177,7 +204,13 @@ CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set @@ -236,9 +269,110 @@ CONFIG_RT_USING_POSIX_TIMER=y # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +CONFIG_RT_LWIP_DEBUG=y +# CONFIG_RT_LWIP_SYS_DEBUG is not set +# CONFIG_RT_LWIP_ETHARP_DEBUG is not set +# CONFIG_RT_LWIP_PPP_DEBUG is not set +# CONFIG_RT_LWIP_MEM_DEBUG is not set +# CONFIG_RT_LWIP_MEMP_DEBUG is not set +# CONFIG_RT_LWIP_PBUF_DEBUG is not set +# CONFIG_RT_LWIP_API_LIB_DEBUG is not set +# CONFIG_RT_LWIP_API_MSG_DEBUG is not set +# CONFIG_RT_LWIP_TCPIP_DEBUG is not set +CONFIG_RT_LWIP_NETIF_DEBUG=y +# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set +# CONFIG_RT_LWIP_DNS_DEBUG is not set +# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set +# CONFIG_RT_LWIP_DHCP_DEBUG is not set +# CONFIG_RT_LWIP_IP_DEBUG is not set +# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set +# CONFIG_RT_LWIP_ICMP_DEBUG is not set +# CONFIG_RT_LWIP_IGMP_DEBUG is not set +# CONFIG_RT_LWIP_UDP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set +# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set +# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -250,9 +384,15 @@ CONFIG_YMODEM_USING_FILE_TRANSFER=y # CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_RESOURCE_ID=y CONFIG_RT_USING_ADT=y +CONFIG_RT_USING_ADT_AVL=y +CONFIG_RT_USING_ADT_BITMAP=y +CONFIG_RT_USING_ADT_HASHMAP=y +CONFIG_RT_USING_ADT_REF=y # CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_VBUS is not set +CONFIG_RT_USING_KTIME=y # # RT-Thread Utestcases @@ -1041,7 +1181,15 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART0 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set # # Board extended module Drivers @@ -1081,6 +1229,8 @@ CONFIG_USE_QSPI=y # CONFIG_USE_FQSPI=y # CONFIG_USE_GIC is not set +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y CONFIG_USE_SERIAL=y # @@ -1088,7 +1238,15 @@ CONFIG_USE_SERIAL=y # CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_GPIO is not set -# CONFIG_USE_ETH is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set # CONFIG_USE_CAN is not set # CONFIG_USE_I2C is not set # CONFIG_USE_TIMER is not set @@ -1106,13 +1264,17 @@ CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_IPC is not set # CONFIG_USE_MEDIA is not set # CONFIG_USE_SCMI_MHU is not set + +# +# Sdk common configuration +# # CONFIG_LOG_VERBOS is not set # CONFIG_LOG_DEBUG is not set # CONFIG_LOG_INFO is not set # CONFIG_LOG_WARN is not set CONFIG_LOG_ERROR=y # CONFIG_LOG_NONE is not set -# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set # CONFIG_LOG_EXTRA_INFO is not set # CONFIG_LOG_DISPALY_CORE_NUM is not set # CONFIG_BOOTUP_DEBUG_PRINTS is not set +# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set diff --git a/bsp/phytium/aarch64/configs/e2000d_rtthread.h b/bsp/phytium/aarch64/configs/e2000d_rtthread.h index 052dfdbd554..2aaee109e05 100644 --- a/bsp/phytium/aarch64/configs/e2000d_rtthread.h +++ b/bsp/phytium/aarch64/configs/e2000d_rtthread.h @@ -18,17 +18,20 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 40960 -#define SYSTEM_THREAD_STACK_SIZE 40960 +#define IDLE_THREAD_STACK_SIZE 8192 +#define SYSTEM_THREAD_STACK_SIZE 8192 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 4096 +#define RT_TIMER_THREAD_STACK_SIZE 8192 /* kservice optimization */ #define RT_KSERVICE_USING_STDLIB #define RT_KPRINTF_USING_LONGLONG #define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ @@ -40,12 +43,12 @@ /* Memory Management */ -#define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_PAGE_MAX_ORDER 16 +#define RT_USING_SLAB #define RT_USING_MEMHEAP #define RT_MEMHEAP_FAST_MODE -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR #define RT_USING_HEAP /* Kernel Device Object */ @@ -55,14 +58,20 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x50001 + +/* RT-Thread Architecture */ + #define ARCH_CPU_64BIT #define RT_USING_CACHE -#define RT_USING_HW_ATOMIC #define ARCH_ARM_BOOTWITH_FLUSH_CACHE #define ARCH_MM_MMU #define ARCH_ARM #define ARCH_ARM_MMU #define ARCH_ARMV8 +#define ARCH_TEXT_OFFSET 0x80000 +#define ARCH_RAM_OFFSET 0x80000000 +#define ARCH_SECONDARY_CPU_STACK_SIZE 4096 +#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS /* RT-Thread Components */ @@ -93,6 +102,21 @@ #define RT_USING_DFS_V1 #define DFS_FILESYSTEMS_MAX 4 #define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS #define RT_USING_DFS_RAMFS @@ -111,6 +135,12 @@ #define RT_USING_ZERO #define RT_USING_RANDOM #define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 4096 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 /* Using USB */ @@ -137,12 +167,73 @@ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +#define RT_LWIP_DEBUG +#define RT_LWIP_NETIF_DEBUG /* Utilities */ #define RT_USING_RYM #define YMODEM_USING_FILE_TRANSFER +#define RT_USING_RESOURCE_ID #define RT_USING_ADT +#define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF +#define RT_USING_KTIME /* RT-Thread Utestcases */ @@ -269,6 +360,11 @@ #define BSP_USING_UART #define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 /* Board extended module Drivers */ @@ -296,11 +392,22 @@ /* Qspi Configuration */ #define USE_FQSPI +#define USE_IOPAD +#define ENABLE_IOPAD #define USE_SERIAL /* Usart Configuration */ #define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON + +/* Sdk common configuration */ + #define LOG_ERROR #endif diff --git a/bsp/phytium/aarch64/configs/e2000d_rtthread_test b/bsp/phytium/aarch64/configs/e2000d_rtthread_test new file mode 100644 index 00000000000..0fdea70111a --- /dev/null +++ b/bsp/phytium/aarch64/configs/e2000d_rtthread_test @@ -0,0 +1,1273 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +CONFIG_RT_USING_SMP=y +CONFIG_RT_CPUS_NR=2 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=40960 +CONFIG_SYSTEM_THREAD_STACK_SIZE=40960 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +CONFIG_RT_KPRINTF_USING_LONGLONG=y +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_PAGE_LEAK is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_PAGE_MAX_ORDER=16 +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP_ISR=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_HW_ATOMIC is not set +CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_ARCH_ARMV8=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +CONFIG_RT_USING_DFS_RAMFS=y +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_NFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=4096 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=4096 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +CONFIG_RT_USING_POSIX_DEVIO=y +CONFIG_RT_USING_POSIX_STDIO=y +# CONFIG_RT_USING_POSIX_POLL is not set +# CONFIG_RT_USING_POSIX_SELECT is not set +# CONFIG_RT_USING_POSIX_SOCKET is not set +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set +CONFIG_RT_USING_POSIX_DELAY=y +CONFIG_RT_USING_POSIX_CLOCK=y +CONFIG_RT_USING_POSIX_TIMER=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +CONFIG_RT_LWIP_DEBUG=y +# CONFIG_RT_LWIP_SYS_DEBUG is not set +# CONFIG_RT_LWIP_ETHARP_DEBUG is not set +# CONFIG_RT_LWIP_PPP_DEBUG is not set +# CONFIG_RT_LWIP_MEM_DEBUG is not set +# CONFIG_RT_LWIP_MEMP_DEBUG is not set +# CONFIG_RT_LWIP_PBUF_DEBUG is not set +# CONFIG_RT_LWIP_API_LIB_DEBUG is not set +# CONFIG_RT_LWIP_API_MSG_DEBUG is not set +# CONFIG_RT_LWIP_TCPIP_DEBUG is not set +CONFIG_RT_LWIP_NETIF_DEBUG=y +# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set +# CONFIG_RT_LWIP_DNS_DEBUG is not set +# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set +# CONFIG_RT_LWIP_DHCP_DEBUG is not set +# CONFIG_RT_LWIP_IP_DEBUG is not set +# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set +# CONFIG_RT_LWIP_ICMP_DEBUG is not set +# CONFIG_RT_LWIP_IGMP_DEBUG is not set +# CONFIG_RT_LWIP_UDP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set +# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set +# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +CONFIG_RT_USING_RYM=y +# CONFIG_YMODEM_USING_CRC_TABLE is not set +CONFIG_YMODEM_USING_FILE_TRANSFER=y +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_ADT=y +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_FINGERPRINT is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +CONFIG_PKG_USING_KERNEL_SAMPLES=y +CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples" +# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set +# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set +CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y +CONFIG_PKG_KERNEL_SAMPLES_VER="latest" +CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y +# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set +# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set +# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set +# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set +# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set +# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set +# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set +# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set +# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set +# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set +# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set +# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set +# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set +# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set +# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set +# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set +# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set +# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_RT_USING_UART1=y +# CONFIG_RT_USING_UART0 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set + +# +# Board extended module Drivers +# +CONFIG_BSP_USING_GIC=y +CONFIG_BSP_USING_GICV3=y +CONFIG_PHYTIUM_ARCH_AARCH64=y +CONFIG_ARM_SPI_BIND_CPU_ID=0 + +# +# Standalone Setting +# +CONFIG_TARGET_ARMV8_AARCH64=y + +# +# Board Configuration +# +# CONFIG_TARGET_F2000_4 is not set +# CONFIG_TARGET_D2000 is not set +# CONFIG_TARGET_E2000Q is not set +CONFIG_TARGET_E2000D=y +# CONFIG_TARGET_E2000S is not set +CONFIG_TARGET_E2000=y +CONFIG_DEFAULT_DEBUG_PRINT_UART1=y +# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set +# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set + +# +# Components Configuration +# +CONFIG_USE_SPI=y +CONFIG_USE_FSPIM=y +CONFIG_USE_QSPI=y + +# +# Qspi Configuration +# +CONFIG_USE_FQSPI=y +# CONFIG_USE_GIC is not set +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y +CONFIG_USE_SERIAL=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# CONFIG_USE_GPIO is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set +# CONFIG_USE_CAN is not set +# CONFIG_USE_I2C is not set +# CONFIG_USE_TIMER is not set +# CONFIG_USE_MIO is not set +# CONFIG_USE_SDMMC is not set +# CONFIG_USE_PCIE is not set +# CONFIG_USE_WDT is not set +# CONFIG_USE_DMA is not set +# CONFIG_USE_NAND is not set +# CONFIG_USE_RTC is not set +# CONFIG_USE_SATA is not set +# CONFIG_USE_USB is not set +# CONFIG_USE_ADC is not set +# CONFIG_USE_PWM is not set +# CONFIG_USE_IPC is not set +# CONFIG_USE_MEDIA is not set +# CONFIG_USE_SCMI_MHU is not set +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set +# CONFIG_LOG_EXTRA_INFO is not set +# CONFIG_LOG_DISPALY_CORE_NUM is not set +# CONFIG_BOOTUP_DEBUG_PRINTS is not set +CONFIG_PHYTIUM_RTT_TEST=y +# CONFIG_ENABLE_RTT_UTEST is not set +# CONFIG_ENABLE_KERNEL_TEST is not set +# CONFIG_ENABLE_KERNEL_SAMPLE is not set +# CONFIG_ENABLE_COREMARK is not set +# CONFIG_ENABLE_DHRYSTONE is not set diff --git a/bsp/phytium/aarch64/configs/e2000d_rtthread_test.h b/bsp/phytium/aarch64/configs/e2000d_rtthread_test.h new file mode 100644 index 00000000000..e7d8209481d --- /dev/null +++ b/bsp/phytium/aarch64/configs/e2000d_rtthread_test.h @@ -0,0 +1,395 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 16 +#define RT_USING_SMP +#define RT_CPUS_NR 2 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 40960 +#define SYSTEM_THREAD_STACK_SIZE 40960 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 4096 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_KPRINTF_USING_LONGLONG +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_PAGE_MAX_ORDER 16 +#define RT_USING_SLAB +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50001 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_ARM_BOOTWITH_FLUSH_CACHE +#define ARCH_MM_MMU +#define ARCH_ARM +#define ARCH_ARM_MMU +#define ARCH_ARMV8 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_RAMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 4096 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + +#define RT_USING_POSIX_FS +#define RT_USING_POSIX_DEVIO +#define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_DELAY +#define RT_USING_POSIX_CLOCK +#define RT_USING_POSIX_TIMER + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +#define RT_LWIP_DEBUG +#define RT_LWIP_NETIF_DEBUG + +/* Utilities */ + +#define RT_USING_RYM +#define YMODEM_USING_FILE_TRANSFER +#define RT_USING_ADT + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + +#define PKG_USING_KERNEL_SAMPLES +#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION +#define PKG_USING_KERNEL_SAMPLES_EN + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 + +/* Board extended module Drivers */ + +#define BSP_USING_GIC +#define BSP_USING_GICV3 +#define PHYTIUM_ARCH_AARCH64 +#define ARM_SPI_BIND_CPU_ID 0 + +/* Standalone Setting */ + +#define TARGET_ARMV8_AARCH64 + +/* Board Configuration */ + +#define TARGET_E2000D +#define TARGET_E2000 +#define DEFAULT_DEBUG_PRINT_UART1 + +/* Components Configuration */ + +#define USE_SPI +#define USE_FSPIM +#define USE_QSPI + +/* Qspi Configuration */ + +#define USE_FQSPI +#define USE_IOPAD +#define ENABLE_IOPAD +#define USE_SERIAL + +/* Usart Configuration */ + +#define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON +#define LOG_ERROR +#define PHYTIUM_RTT_TEST + +#endif diff --git a/bsp/phytium/aarch64/configs/e2000q_rtsmart b/bsp/phytium/aarch64/configs/e2000q_rtsmart index de04313cc94..7cd8e6f232e 100644 --- a/bsp/phytium/aarch64/configs/e2000q_rtsmart +++ b/bsp/phytium/aarch64/configs/e2000q_rtsmart @@ -47,6 +47,7 @@ CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_MEM_CONFIG is not set # CONFIG_RT_DEBUG_SLAB_CONFIG is not set # CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_PAGE_LEAK is not set # CONFIG_RT_DEBUG_MODULE_CONFIG is not set # @@ -62,20 +63,20 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_PAGE_MAX_ORDER=16 +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_MEMHEAP_FAST_MODE=y # CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP_ISR=y CONFIG_RT_USING_HEAP=y # @@ -92,7 +93,7 @@ CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_ARCH_CPU_64BIT=y CONFIG_RT_USING_CACHE=y -CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_RT_USING_HW_ATOMIC is not set CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # CONFIG_RT_USING_CPU_FFS is not set @@ -138,12 +139,35 @@ CONFIG_RT_USING_DFS_V1=y # CONFIG_RT_USING_DFS_V2 is not set CONFIG_DFS_FILESYSTEMS_MAX=4 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set CONFIG_RT_USING_LWP=y CONFIG_RT_LWP_MAX_NR=30 @@ -188,7 +212,13 @@ CONFIG_RT_USING_RANDOM=y CONFIG_RT_USING_RTC=y # CONFIG_RT_USING_ALARM is not set # CONFIG_RT_USING_SOFT_RTC is not set -# CONFIG_RT_USING_SDIO is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_USING_SPI is not set # CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_AUDIO is not set @@ -247,9 +277,110 @@ CONFIG_RT_USING_POSIX_TIMER=y # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +CONFIG_RT_LWIP_DEBUG=y +# CONFIG_RT_LWIP_SYS_DEBUG is not set +# CONFIG_RT_LWIP_ETHARP_DEBUG is not set +# CONFIG_RT_LWIP_PPP_DEBUG is not set +# CONFIG_RT_LWIP_MEM_DEBUG is not set +# CONFIG_RT_LWIP_MEMP_DEBUG is not set +# CONFIG_RT_LWIP_PBUF_DEBUG is not set +# CONFIG_RT_LWIP_API_LIB_DEBUG is not set +# CONFIG_RT_LWIP_API_MSG_DEBUG is not set +# CONFIG_RT_LWIP_TCPIP_DEBUG is not set +CONFIG_RT_LWIP_NETIF_DEBUG=y +# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set +# CONFIG_RT_LWIP_DNS_DEBUG is not set +# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set +# CONFIG_RT_LWIP_DHCP_DEBUG is not set +# CONFIG_RT_LWIP_IP_DEBUG is not set +# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set +# CONFIG_RT_LWIP_ICMP_DEBUG is not set +# CONFIG_RT_LWIP_IGMP_DEBUG is not set +# CONFIG_RT_LWIP_UDP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set +# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set +# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -1052,7 +1183,15 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART0 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set # # Board extended module Drivers @@ -1092,6 +1231,8 @@ CONFIG_USE_QSPI=y # CONFIG_USE_FQSPI=y # CONFIG_USE_GIC is not set +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y CONFIG_USE_SERIAL=y # @@ -1099,7 +1240,15 @@ CONFIG_USE_SERIAL=y # CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_GPIO is not set -# CONFIG_USE_ETH is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set # CONFIG_USE_CAN is not set # CONFIG_USE_I2C is not set # CONFIG_USE_TIMER is not set @@ -1127,3 +1276,4 @@ CONFIG_LOG_ERROR=y # CONFIG_LOG_EXTRA_INFO is not set # CONFIG_LOG_DISPALY_CORE_NUM is not set # CONFIG_BOOTUP_DEBUG_PRINTS is not set +# CONFIG_PHYTIUM_RTT_TEST is not set diff --git a/bsp/phytium/aarch64/configs/e2000q_rtsmart.h b/bsp/phytium/aarch64/configs/e2000q_rtsmart.h index 06660b7a349..83c352b1458 100644 --- a/bsp/phytium/aarch64/configs/e2000q_rtsmart.h +++ b/bsp/phytium/aarch64/configs/e2000q_rtsmart.h @@ -29,7 +29,7 @@ #define RT_KSERVICE_USING_STDLIB #define RT_KPRINTF_USING_LONGLONG -#define RT_USING_DEBUG +#define RT_DEBUG /* Inter-Thread communication */ @@ -41,12 +41,12 @@ /* Memory Management */ -#define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_PAGE_MAX_ORDER 16 +#define RT_USING_SLAB #define RT_USING_MEMHEAP #define RT_MEMHEAP_FAST_MODE -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR #define RT_USING_HEAP /* Kernel Device Object */ @@ -58,7 +58,6 @@ #define RT_VER_NUM 0x50001 #define ARCH_CPU_64BIT #define RT_USING_CACHE -#define RT_USING_HW_ATOMIC #define ARCH_ARM_BOOTWITH_FLUSH_CACHE #define ARCH_MM_MMU #define ARCH_ARM @@ -95,6 +94,21 @@ #define RT_USING_DFS_V1 #define DFS_FILESYSTEMS_MAX 4 #define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS #define RT_USING_DFS_RAMFS #define RT_USING_LWP @@ -121,6 +135,12 @@ #define RT_USING_ZERO #define RT_USING_RANDOM #define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 /* Using USB */ @@ -147,6 +167,61 @@ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +#define RT_LWIP_DEBUG +#define RT_LWIP_NETIF_DEBUG /* Utilities */ @@ -279,6 +354,11 @@ #define BSP_USING_UART #define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 /* Board extended module Drivers */ @@ -306,11 +386,19 @@ /* Qspi Configuration */ #define USE_FQSPI +#define USE_IOPAD +#define ENABLE_IOPAD #define USE_SERIAL /* Usart Configuration */ #define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON #define LOG_ERROR #endif diff --git a/bsp/phytium/aarch64/configs/e2000q_rtsmart_test b/bsp/phytium/aarch64/configs/e2000q_rtsmart_test new file mode 100644 index 00000000000..225d3e5e067 --- /dev/null +++ b/bsp/phytium/aarch64/configs/e2000q_rtsmart_test @@ -0,0 +1,1284 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +CONFIG_RT_USING_SMART=y +CONFIG_RT_USING_SMP=y +CONFIG_RT_CPUS_NR=4 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=40960 +CONFIG_SYSTEM_THREAD_STACK_SIZE=40960 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +CONFIG_RT_KPRINTF_USING_LONGLONG=y +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_PAGE_LEAK is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_PAGE_MAX_ORDER=16 +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP_ISR=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_HW_ATOMIC is not set +CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_KERNEL_VADDR_START=0xffff000000000000 +CONFIG_ARCH_ARMV8=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +CONFIG_RT_USING_DFS_RAMFS=y +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_NFS is not set +# CONFIG_RT_USING_FAL is not set +CONFIG_RT_USING_LWP=y +CONFIG_RT_LWP_MAX_NR=30 +CONFIG_LWP_TASK_STACK_SIZE=16384 +CONFIG_RT_CH_MSG_MAX_NR=1024 +CONFIG_LWP_CONSOLE_INPUT_BUFFER_SIZE=1024 +CONFIG_LWP_TID_MAX_NR=64 +CONFIG_RT_LWP_SHM_MAX_NR=64 +# CONFIG_LWP_UNIX98_PTY is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +CONFIG_RT_USING_TTY=y +# CONFIG_RT_TTY_DEBUG is not set +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +CONFIG_RT_USING_SDIO=y +CONFIG_RT_SDIO_STACK_SIZE=512 +CONFIG_RT_SDIO_THREAD_PRIORITY=15 +CONFIG_RT_MMCSD_STACK_SIZE=1024 +CONFIG_RT_MMCSD_THREAD_PREORITY=22 +CONFIG_RT_MMCSD_MAX_PARTITION=16 +# CONFIG_RT_SDIO_DEBUG is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +CONFIG_RT_USING_POSIX_DEVIO=y +CONFIG_RT_USING_POSIX_STDIO=y +# CONFIG_RT_USING_POSIX_POLL is not set +# CONFIG_RT_USING_POSIX_SELECT is not set +# CONFIG_RT_USING_POSIX_SOCKET is not set +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set +CONFIG_RT_USING_POSIX_DELAY=y +CONFIG_RT_USING_POSIX_CLOCK=y +CONFIG_RT_USING_POSIX_TIMER=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +CONFIG_RT_LWIP_DEBUG=y +# CONFIG_RT_LWIP_SYS_DEBUG is not set +# CONFIG_RT_LWIP_ETHARP_DEBUG is not set +# CONFIG_RT_LWIP_PPP_DEBUG is not set +# CONFIG_RT_LWIP_MEM_DEBUG is not set +# CONFIG_RT_LWIP_MEMP_DEBUG is not set +# CONFIG_RT_LWIP_PBUF_DEBUG is not set +# CONFIG_RT_LWIP_API_LIB_DEBUG is not set +# CONFIG_RT_LWIP_API_MSG_DEBUG is not set +# CONFIG_RT_LWIP_TCPIP_DEBUG is not set +CONFIG_RT_LWIP_NETIF_DEBUG=y +# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set +# CONFIG_RT_LWIP_DNS_DEBUG is not set +# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set +# CONFIG_RT_LWIP_DHCP_DEBUG is not set +# CONFIG_RT_LWIP_IP_DEBUG is not set +# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set +# CONFIG_RT_LWIP_ICMP_DEBUG is not set +# CONFIG_RT_LWIP_IGMP_DEBUG is not set +# CONFIG_RT_LWIP_UDP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set +# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set +# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +CONFIG_RT_USING_RYM=y +# CONFIG_YMODEM_USING_CRC_TABLE is not set +CONFIG_YMODEM_USING_FILE_TRANSFER=y +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_ADT=y +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_FINGERPRINT is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +CONFIG_PKG_USING_KERNEL_SAMPLES=y +CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples" +# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set +# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set +CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y +CONFIG_PKG_KERNEL_SAMPLES_VER="latest" +CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y +# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set +# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set +# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set +# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set +# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set +# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set +# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set +# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set +# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set +# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set +# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set +# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set +# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set +# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set +# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set +# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set +# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set +# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_RT_USING_UART1=y +# CONFIG_RT_USING_UART0 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +CONFIG_BSP_USING_SDIO=y +CONFIG_BSP_USING_SDCARD_FATFS=y +# CONFIG_USING_SDIO0 is not set +CONFIG_USING_SDIO1=y +# CONFIG_USING_EMMC is not set + +# +# Board extended module Drivers +# +CONFIG_BSP_USING_GIC=y +CONFIG_BSP_USING_GICV3=y +CONFIG_PHYTIUM_ARCH_AARCH64=y +CONFIG_ARM_SPI_BIND_CPU_ID=2 + +# +# Standalone Setting +# +CONFIG_TARGET_ARMV8_AARCH64=y + +# +# Board Configuration +# +# CONFIG_TARGET_F2000_4 is not set +# CONFIG_TARGET_D2000 is not set +CONFIG_TARGET_E2000Q=y +# CONFIG_TARGET_E2000D is not set +# CONFIG_TARGET_E2000S is not set +CONFIG_TARGET_E2000=y +CONFIG_DEFAULT_DEBUG_PRINT_UART1=y +# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set +# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set + +# +# Components Configuration +# +CONFIG_USE_SPI=y +CONFIG_USE_FSPIM=y +CONFIG_USE_QSPI=y + +# +# Qspi Configuration +# +CONFIG_USE_FQSPI=y +# CONFIG_USE_GIC is not set +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y +CONFIG_USE_SERIAL=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# CONFIG_USE_GPIO is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set +# CONFIG_USE_CAN is not set +# CONFIG_USE_I2C is not set +# CONFIG_USE_TIMER is not set +# CONFIG_USE_MIO is not set +# CONFIG_USE_SDMMC is not set +# CONFIG_USE_PCIE is not set +# CONFIG_USE_WDT is not set +# CONFIG_USE_DMA is not set +# CONFIG_USE_NAND is not set +# CONFIG_USE_RTC is not set +# CONFIG_USE_SATA is not set +# CONFIG_USE_USB is not set +# CONFIG_USE_ADC is not set +# CONFIG_USE_PWM is not set +# CONFIG_USE_IPC is not set +# CONFIG_USE_MEDIA is not set +# CONFIG_USE_SCMI_MHU is not set +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set +# CONFIG_LOG_EXTRA_INFO is not set +# CONFIG_LOG_DISPALY_CORE_NUM is not set +# CONFIG_BOOTUP_DEBUG_PRINTS is not set +CONFIG_PHYTIUM_RTT_TEST=y +# CONFIG_ENABLE_RTT_UTEST is not set +# CONFIG_ENABLE_KERNEL_TEST is not set +# CONFIG_ENABLE_KERNEL_SAMPLE is not set +# CONFIG_ENABLE_COREMARK is not set +# CONFIG_ENABLE_DHRYSTONE is not set diff --git a/bsp/phytium/aarch64/configs/e2000q_rtsmart_test.h b/bsp/phytium/aarch64/configs/e2000q_rtsmart_test.h new file mode 100644 index 00000000000..59885eb3972 --- /dev/null +++ b/bsp/phytium/aarch64/configs/e2000q_rtsmart_test.h @@ -0,0 +1,405 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 16 +#define RT_USING_SMART +#define RT_USING_SMP +#define RT_CPUS_NR 4 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 40960 +#define SYSTEM_THREAD_STACK_SIZE 40960 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 4096 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_KPRINTF_USING_LONGLONG +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_PAGE_MAX_ORDER 16 +#define RT_USING_SLAB +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50001 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_ARM_BOOTWITH_FLUSH_CACHE +#define ARCH_MM_MMU +#define ARCH_ARM +#define ARCH_ARM_MMU +#define KERNEL_VADDR_START 0xffff000000000000 +#define ARCH_ARMV8 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_RAMFS +#define RT_USING_LWP +#define RT_LWP_MAX_NR 30 +#define LWP_TASK_STACK_SIZE 16384 +#define RT_CH_MSG_MAX_NR 1024 +#define LWP_CONSOLE_INPUT_BUFFER_SIZE 1024 +#define LWP_TID_MAX_NR 64 +#define RT_LWP_SHM_MAX_NR 64 + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_TTY +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 512 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 1024 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + +#define RT_USING_POSIX_FS +#define RT_USING_POSIX_DEVIO +#define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_DELAY +#define RT_USING_POSIX_CLOCK +#define RT_USING_POSIX_TIMER + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +#define RT_LWIP_DEBUG +#define RT_LWIP_NETIF_DEBUG + +/* Utilities */ + +#define RT_USING_RYM +#define YMODEM_USING_FILE_TRANSFER +#define RT_USING_ADT + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + +#define PKG_USING_KERNEL_SAMPLES +#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION +#define PKG_USING_KERNEL_SAMPLES_EN + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 + +/* Board extended module Drivers */ + +#define BSP_USING_GIC +#define BSP_USING_GICV3 +#define PHYTIUM_ARCH_AARCH64 +#define ARM_SPI_BIND_CPU_ID 2 + +/* Standalone Setting */ + +#define TARGET_ARMV8_AARCH64 + +/* Board Configuration */ + +#define TARGET_E2000Q +#define TARGET_E2000 +#define DEFAULT_DEBUG_PRINT_UART1 + +/* Components Configuration */ + +#define USE_SPI +#define USE_FSPIM +#define USE_QSPI + +/* Qspi Configuration */ + +#define USE_FQSPI +#define USE_IOPAD +#define ENABLE_IOPAD +#define USE_SERIAL + +/* Usart Configuration */ + +#define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON +#define LOG_ERROR +#define PHYTIUM_RTT_TEST + +#endif diff --git a/bsp/phytium/aarch64/configs/e2000q_rtthread b/bsp/phytium/aarch64/configs/e2000q_rtthread index 8edc0d37f33..7c929903474 100644 --- a/bsp/phytium/aarch64/configs/e2000q_rtthread +++ b/bsp/phytium/aarch64/configs/e2000q_rtthread @@ -10,7 +10,7 @@ CONFIG_RT_NAME_MAX=16 # CONFIG_RT_USING_ARCH_DATA_TYPE is not set # CONFIG_RT_USING_SMART is not set CONFIG_RT_USING_SMP=y -CONFIG_RT_CPUS_NR=4 +CONFIG_RT_CPUS_NR=2 CONFIG_RT_ALIGN_SIZE=4 # CONFIG_RT_THREAD_PRIORITY_8 is not set CONFIG_RT_THREAD_PRIORITY_32=y @@ -47,6 +47,7 @@ CONFIG_RT_DEBUG=y # CONFIG_RT_DEBUG_MEM_CONFIG is not set # CONFIG_RT_DEBUG_SLAB_CONFIG is not set # CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_PAGE_LEAK is not set # CONFIG_RT_DEBUG_MODULE_CONFIG is not set # @@ -62,20 +63,20 @@ CONFIG_RT_USING_MESSAGEQUEUE=y # # Memory Management # -CONFIG_RT_PAGE_MAX_ORDER=11 -CONFIG_RT_USING_MEMPOOL=y -CONFIG_RT_USING_SMALL_MEM=y -# CONFIG_RT_USING_SLAB is not set +CONFIG_RT_PAGE_MAX_ORDER=16 +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y CONFIG_RT_USING_MEMHEAP=y CONFIG_RT_MEMHEAP_FAST_MODE=y # CONFIG_RT_MEMHEAP_BEST_MODE is not set -CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set # CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set -# CONFIG_RT_USING_SLAB_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y # CONFIG_RT_USING_USERHEAP is not set # CONFIG_RT_USING_NOHEAP is not set # CONFIG_RT_USING_MEMTRACE is not set -# CONFIG_RT_USING_HEAP_ISR is not set +CONFIG_RT_USING_HEAP_ISR=y CONFIG_RT_USING_HEAP=y # @@ -92,7 +93,7 @@ CONFIG_RT_VER_NUM=0x50001 # CONFIG_RT_USING_STDC_ATOMIC is not set CONFIG_ARCH_CPU_64BIT=y CONFIG_RT_USING_CACHE=y -CONFIG_RT_USING_HW_ATOMIC=y +# CONFIG_RT_USING_HW_ATOMIC is not set CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y # CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set # CONFIG_RT_USING_CPU_FFS is not set @@ -137,12 +138,35 @@ CONFIG_RT_USING_DFS_V1=y # CONFIG_RT_USING_DFS_V2 is not set CONFIG_DFS_FILESYSTEMS_MAX=4 CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 -# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 CONFIG_RT_USING_DFS_DEVFS=y # CONFIG_RT_USING_DFS_ROMFS is not set # CONFIG_RT_USING_DFS_CROMFS is not set CONFIG_RT_USING_DFS_RAMFS=y # CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_NFS is not set # CONFIG_RT_USING_FAL is not set # @@ -236,9 +260,110 @@ CONFIG_RT_USING_POSIX_TIMER=y # # Network # -# CONFIG_RT_USING_SAL is not set -# CONFIG_RT_USING_NETDEV is not set -# CONFIG_RT_USING_LWIP is not set +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +CONFIG_RT_LWIP_DEBUG=y +# CONFIG_RT_LWIP_SYS_DEBUG is not set +# CONFIG_RT_LWIP_ETHARP_DEBUG is not set +# CONFIG_RT_LWIP_PPP_DEBUG is not set +# CONFIG_RT_LWIP_MEM_DEBUG is not set +# CONFIG_RT_LWIP_MEMP_DEBUG is not set +# CONFIG_RT_LWIP_PBUF_DEBUG is not set +# CONFIG_RT_LWIP_API_LIB_DEBUG is not set +# CONFIG_RT_LWIP_API_MSG_DEBUG is not set +# CONFIG_RT_LWIP_TCPIP_DEBUG is not set +CONFIG_RT_LWIP_NETIF_DEBUG=y +# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set +# CONFIG_RT_LWIP_DNS_DEBUG is not set +# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set +# CONFIG_RT_LWIP_DHCP_DEBUG is not set +# CONFIG_RT_LWIP_IP_DEBUG is not set +# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set +# CONFIG_RT_LWIP_ICMP_DEBUG is not set +# CONFIG_RT_LWIP_IGMP_DEBUG is not set +# CONFIG_RT_LWIP_UDP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set +# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set +# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set # CONFIG_RT_USING_AT is not set # @@ -1041,7 +1166,11 @@ CONFIG_RT_USING_UART1=y # CONFIG_RT_USING_UART0 is not set # CONFIG_BSP_USING_SPI is not set # CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set # CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +# CONFIG_BSP_USING_SDIO is not set # # Board extended module Drivers @@ -1081,6 +1210,8 @@ CONFIG_USE_QSPI=y # CONFIG_USE_FQSPI=y # CONFIG_USE_GIC is not set +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y CONFIG_USE_SERIAL=y # @@ -1088,7 +1219,15 @@ CONFIG_USE_SERIAL=y # CONFIG_ENABLE_Pl011_UART=y # CONFIG_USE_GPIO is not set -# CONFIG_USE_ETH is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set # CONFIG_USE_CAN is not set # CONFIG_USE_I2C is not set # CONFIG_USE_TIMER is not set diff --git a/bsp/phytium/aarch64/configs/e2000q_rtthread.h b/bsp/phytium/aarch64/configs/e2000q_rtthread.h index 4dd6b1f99d4..6244beb00cc 100644 --- a/bsp/phytium/aarch64/configs/e2000q_rtthread.h +++ b/bsp/phytium/aarch64/configs/e2000q_rtthread.h @@ -8,7 +8,7 @@ #define RT_NAME_MAX 16 #define RT_USING_SMP -#define RT_CPUS_NR 4 +#define RT_CPUS_NR 2 #define RT_ALIGN_SIZE 4 #define RT_THREAD_PRIORITY_32 #define RT_THREAD_PRIORITY_MAX 32 @@ -28,7 +28,7 @@ #define RT_KSERVICE_USING_STDLIB #define RT_KPRINTF_USING_LONGLONG -#define RT_USING_DEBUG +#define RT_DEBUG /* Inter-Thread communication */ @@ -40,12 +40,12 @@ /* Memory Management */ -#define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_PAGE_MAX_ORDER 16 +#define RT_USING_SLAB #define RT_USING_MEMHEAP #define RT_MEMHEAP_FAST_MODE -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR #define RT_USING_HEAP /* Kernel Device Object */ @@ -57,7 +57,6 @@ #define RT_VER_NUM 0x50001 #define ARCH_CPU_64BIT #define RT_USING_CACHE -#define RT_USING_HW_ATOMIC #define ARCH_ARM_BOOTWITH_FLUSH_CACHE #define ARCH_MM_MMU #define ARCH_ARM @@ -93,6 +92,21 @@ #define RT_USING_DFS_V1 #define DFS_FILESYSTEMS_MAX 4 #define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS #define RT_USING_DFS_RAMFS @@ -137,6 +151,61 @@ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +#define RT_LWIP_DEBUG +#define RT_LWIP_NETIF_DEBUG /* Utilities */ @@ -269,6 +338,8 @@ #define BSP_USING_UART #define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 /* Board extended module Drivers */ @@ -296,11 +367,19 @@ /* Qspi Configuration */ #define USE_FQSPI +#define USE_IOPAD +#define ENABLE_IOPAD #define USE_SERIAL /* Usart Configuration */ #define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON #define LOG_ERROR #endif diff --git a/bsp/phytium/aarch64/configs/e2000q_rtthread_test b/bsp/phytium/aarch64/configs/e2000q_rtthread_test new file mode 100644 index 00000000000..cdcbb579239 --- /dev/null +++ b/bsp/phytium/aarch64/configs/e2000q_rtthread_test @@ -0,0 +1,1263 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=16 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMART is not set +CONFIG_RT_USING_SMP=y +CONFIG_RT_CPUS_NR=2 +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_HOOK_USING_FUNC_PTR=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=40960 +CONFIG_SYSTEM_THREAD_STACK_SIZE=40960 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=4096 + +# +# kservice optimization +# +CONFIG_RT_KSERVICE_USING_STDLIB=y +# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set +# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set +# CONFIG_RT_USING_TINY_FFS is not set +CONFIG_RT_KPRINTF_USING_LONGLONG=y +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_PAGE_LEAK is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_PAGE_MAX_ORDER=16 +# CONFIG_RT_USING_MEMPOOL is not set +# CONFIG_RT_USING_SMALL_MEM is not set +CONFIG_RT_USING_SLAB=y +CONFIG_RT_USING_MEMHEAP=y +CONFIG_RT_MEMHEAP_FAST_MODE=y +# CONFIG_RT_MEMHEAP_BEST_MODE is not set +# CONFIG_RT_USING_SMALL_MEM_AS_HEAP is not set +# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set +CONFIG_RT_USING_SLAB_AS_HEAP=y +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP_ISR=y +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_DM is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x50001 +# CONFIG_RT_USING_STDC_ATOMIC is not set +CONFIG_ARCH_CPU_64BIT=y +CONFIG_RT_USING_CACHE=y +# CONFIG_RT_USING_HW_ATOMIC is not set +CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set +# CONFIG_RT_USING_CPU_FFS is not set +CONFIG_ARCH_MM_MMU=y +CONFIG_ARCH_ARM=y +CONFIG_ARCH_ARM_MMU=y +CONFIG_ARCH_ARMV8=y + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=8192 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 +# CONFIG_RT_USING_LEGACY is not set +CONFIG_RT_USING_MSH=y +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_CMD_SIZE=80 +CONFIG_MSH_USING_BUILT_IN_COMMANDS=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# DFS: device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_POSIX=y +CONFIG_DFS_USING_WORKDIR=y +# CONFIG_RT_USING_DFS_MNTTABLE is not set +CONFIG_DFS_FD_MAX=16 +CONFIG_RT_USING_DFS_V1=y +# CONFIG_RT_USING_DFS_V2 is not set +CONFIG_DFS_FILESYSTEMS_MAX=4 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=4 +CONFIG_RT_USING_DFS_ELMFAT=y + +# +# elm-chan's FatFs, Generic FAT Filesystem Module +# +CONFIG_RT_DFS_ELM_CODE_PAGE=437 +CONFIG_RT_DFS_ELM_WORD_ACCESS=y +# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set +# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set +CONFIG_RT_DFS_ELM_USE_LFN_3=y +CONFIG_RT_DFS_ELM_USE_LFN=3 +CONFIG_RT_DFS_ELM_LFN_UNICODE_0=y +# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set +# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set +CONFIG_RT_DFS_ELM_LFN_UNICODE=0 +CONFIG_RT_DFS_ELM_MAX_LFN=255 +CONFIG_RT_DFS_ELM_DRIVES=2 +CONFIG_RT_DFS_ELM_MAX_SECTOR_SIZE=512 +# CONFIG_RT_DFS_ELM_USE_ERASE is not set +CONFIG_RT_DFS_ELM_REENTRANT=y +CONFIG_RT_DFS_ELM_MUTEX_TIMEOUT=3000 +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_CROMFS is not set +CONFIG_RT_USING_DFS_RAMFS=y +# CONFIG_RT_USING_DFS_TMPFS is not set +# CONFIG_RT_USING_DFS_NFS is not set +# CONFIG_RT_USING_FAL is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_UNAMED_PIPE_NUMBER=64 +CONFIG_RT_USING_SYSTEM_WORKQUEUE=y +CONFIG_RT_SYSTEM_WORKQUEUE_STACKSIZE=8192 +CONFIG_RT_SYSTEM_WORKQUEUE_PRIORITY=23 +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_USING_SERIAL_V1=y +# CONFIG_RT_USING_SERIAL_V2 is not set +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +# CONFIG_RT_USING_PIN is not set +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +CONFIG_RT_USING_NULL=y +CONFIG_RT_USING_ZERO=y +CONFIG_RT_USING_RANDOM=y +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_FDT is not set +CONFIG_RT_USING_RTC=y +# CONFIG_RT_USING_ALARM is not set +# CONFIG_RT_USING_SOFT_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_LCD is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_DEV_BUS is not set +# CONFIG_RT_USING_WIFI is not set +# CONFIG_RT_USING_VIRTIO is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB is not set +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# C/C++ and POSIX layer +# +CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 + +# +# POSIX (Portable Operating System Interface) layer +# +CONFIG_RT_USING_POSIX_FS=y +CONFIG_RT_USING_POSIX_DEVIO=y +CONFIG_RT_USING_POSIX_STDIO=y +# CONFIG_RT_USING_POSIX_POLL is not set +# CONFIG_RT_USING_POSIX_SELECT is not set +# CONFIG_RT_USING_POSIX_SOCKET is not set +CONFIG_RT_USING_POSIX_TERMIOS=y +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_POSIX_MMAN is not set +CONFIG_RT_USING_POSIX_DELAY=y +CONFIG_RT_USING_POSIX_CLOCK=y +CONFIG_RT_USING_POSIX_TIMER=y +# CONFIG_RT_USING_PTHREADS is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Interprocess Communication (IPC) +# +# CONFIG_RT_USING_POSIX_PIPE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set +# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set + +# +# Socket is in the 'Network' category +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Network +# +CONFIG_RT_USING_SAL=y +CONFIG_SAL_INTERNET_CHECK=y + +# +# Docking with protocol stacks +# +CONFIG_SAL_USING_LWIP=y +# CONFIG_SAL_USING_AT is not set +# CONFIG_SAL_USING_TLS is not set +CONFIG_SAL_USING_POSIX=y +# CONFIG_SAL_USING_AF_UNIX is not set +CONFIG_RT_USING_NETDEV=y +CONFIG_NETDEV_USING_IFCONFIG=y +CONFIG_NETDEV_USING_PING=y +CONFIG_NETDEV_USING_NETSTAT=y +CONFIG_NETDEV_USING_AUTO_DEFAULT=y +# CONFIG_NETDEV_USING_IPV6 is not set +CONFIG_NETDEV_IPV4=1 +CONFIG_NETDEV_IPV6=0 +# CONFIG_NETDEV_IPV6_SCOPES is not set +CONFIG_RT_USING_LWIP=y +# CONFIG_RT_USING_LWIP_LOCAL_VERSION is not set +# CONFIG_RT_USING_LWIP141 is not set +# CONFIG_RT_USING_LWIP203 is not set +CONFIG_RT_USING_LWIP212=y +# CONFIG_RT_USING_LWIP_LATEST is not set +CONFIG_RT_USING_LWIP_VER_NUM=0x20102 +# CONFIG_RT_USING_LWIP_IPV6 is not set +CONFIG_RT_LWIP_MEM_ALIGNMENT=64 +CONFIG_RT_LWIP_IGMP=y +CONFIG_RT_LWIP_ICMP=y +# CONFIG_RT_LWIP_SNMP is not set +CONFIG_RT_LWIP_DNS=y +# CONFIG_RT_LWIP_DHCP is not set + +# +# Static IPv4 Address +# +CONFIG_RT_LWIP_IPADDR="192.168.4.10" +CONFIG_RT_LWIP_GWADDR="192.168.4.1" +CONFIG_RT_LWIP_MSKADDR="255.255.255.0" +CONFIG_RT_LWIP_UDP=y +CONFIG_RT_LWIP_TCP=y +CONFIG_RT_LWIP_RAW=y +# CONFIG_RT_LWIP_PPP is not set +CONFIG_RT_MEMP_NUM_NETCONN=8 +CONFIG_RT_LWIP_PBUF_NUM=512 +CONFIG_RT_LWIP_RAW_PCB_NUM=4 +CONFIG_RT_LWIP_UDP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_PCB_NUM=4 +CONFIG_RT_LWIP_TCP_SEG_NUM=40 +CONFIG_RT_LWIP_TCP_SND_BUF=8196 +CONFIG_RT_LWIP_TCP_WND=8196 +CONFIG_RT_LWIP_TCPTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_TCPTHREAD_MBOX_SIZE=8 +CONFIG_RT_LWIP_TCPTHREAD_STACKSIZE=16184 +# CONFIG_LWIP_NO_RX_THREAD is not set +# CONFIG_LWIP_NO_TX_THREAD is not set +CONFIG_RT_LWIP_ETHTHREAD_PRIORITY=12 +CONFIG_RT_LWIP_ETHTHREAD_STACKSIZE=2048 +CONFIG_RT_LWIP_ETHTHREAD_MBOX_SIZE=8 +# CONFIG_RT_LWIP_REASSEMBLY_FRAG is not set +CONFIG_LWIP_NETIF_STATUS_CALLBACK=1 +CONFIG_LWIP_NETIF_LINK_CALLBACK=1 +CONFIG_SO_REUSE=1 +CONFIG_LWIP_SO_RCVTIMEO=1 +CONFIG_LWIP_SO_SNDTIMEO=1 +CONFIG_LWIP_SO_RCVBUF=1 +CONFIG_LWIP_SO_LINGER=0 +# CONFIG_RT_LWIP_NETIF_LOOPBACK is not set +CONFIG_LWIP_NETIF_LOOPBACK=0 +# CONFIG_RT_LWIP_STATS is not set +# CONFIG_RT_LWIP_USING_HW_CHECKSUM is not set +CONFIG_RT_LWIP_USING_PING=y +# CONFIG_LWIP_USING_DHCPD is not set +CONFIG_RT_LWIP_DEBUG=y +# CONFIG_RT_LWIP_SYS_DEBUG is not set +# CONFIG_RT_LWIP_ETHARP_DEBUG is not set +# CONFIG_RT_LWIP_PPP_DEBUG is not set +# CONFIG_RT_LWIP_MEM_DEBUG is not set +# CONFIG_RT_LWIP_MEMP_DEBUG is not set +# CONFIG_RT_LWIP_PBUF_DEBUG is not set +# CONFIG_RT_LWIP_API_LIB_DEBUG is not set +# CONFIG_RT_LWIP_API_MSG_DEBUG is not set +# CONFIG_RT_LWIP_TCPIP_DEBUG is not set +CONFIG_RT_LWIP_NETIF_DEBUG=y +# CONFIG_RT_LWIP_SOCKETS_DEBUG is not set +# CONFIG_RT_LWIP_DNS_DEBUG is not set +# CONFIG_RT_LWIP_AUTOIP_DEBUG is not set +# CONFIG_RT_LWIP_DHCP_DEBUG is not set +# CONFIG_RT_LWIP_IP_DEBUG is not set +# CONFIG_RT_LWIP_IP_REASS_DEBUG is not set +# CONFIG_RT_LWIP_ICMP_DEBUG is not set +# CONFIG_RT_LWIP_IGMP_DEBUG is not set +# CONFIG_RT_LWIP_UDP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_DEBUG is not set +# CONFIG_RT_LWIP_TCP_INPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_OUTPUT_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RTO_DEBUG is not set +# CONFIG_RT_LWIP_TCP_CWND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_WND_DEBUG is not set +# CONFIG_RT_LWIP_TCP_FR_DEBUG is not set +# CONFIG_RT_LWIP_TCP_QLEN_DEBUG is not set +# CONFIG_RT_LWIP_TCP_RST_DEBUG is not set +# CONFIG_RT_USING_AT is not set + +# +# Utilities +# +CONFIG_RT_USING_RYM=y +# CONFIG_YMODEM_USING_CRC_TABLE is not set +CONFIG_YMODEM_USING_FILE_TRANSFER=y +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_VAR_EXPORT is not set +CONFIG_RT_USING_ADT=y +# CONFIG_RT_USING_RT_LINK is not set +# CONFIG_RT_USING_VBUS is not set + +# +# RT-Thread Utestcases +# +# CONFIG_RT_USING_UTESTCASES is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LWIP is not set +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set +# CONFIG_PKG_USING_ZB_COORDINATOR is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_EZ_IOT_OS is not set +# CONFIG_PKG_USING_IOTSHARP_SDK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set +# CONFIG_PKG_USING_MAVLINK is not set +# CONFIG_PKG_USING_BSAL is not set +# CONFIG_PKG_USING_AGILE_MODBUS is not set +# CONFIG_PKG_USING_AGILE_FTP is not set +# CONFIG_PKG_USING_EMBEDDEDPROTO is not set +# CONFIG_PKG_USING_RT_LINK_HW is not set +# CONFIG_PKG_USING_RYANMQTT is not set +# CONFIG_PKG_USING_RYANW5500 is not set +# CONFIG_PKG_USING_LORA_PKT_FWD is not set +# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set +# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set +# CONFIG_PKG_USING_HM is not set +# CONFIG_PKG_USING_SMALL_MODBUS is not set +# CONFIG_PKG_USING_NET_SERVER is not set +# CONFIG_PKG_USING_ZFTP is not set +# CONFIG_PKG_USING_WOL is not set +# CONFIG_PKG_USING_ZEPHYR_POLLING is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_LIBSODIUM is not set +# CONFIG_PKG_USING_LIBHYDROGEN is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# + +# +# JSON: JavaScript Object Notation, a lightweight data-interchange format +# +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_RAPIDJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PARSON is not set + +# +# XML: Extensible Markup Language +# +# CONFIG_PKG_USING_SIMPLE_XML is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_LUATOS_SOC is not set +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set +# CONFIG_PKG_USING_PIKASCRIPT is not set +# CONFIG_PKG_USING_RTT_RUST is not set + +# +# multimedia packages +# + +# +# LVGL: powerful and easy-to-use embedded GUI library +# +# CONFIG_PKG_USING_LVGL is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set +# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set + +# +# u8g2: a monochrome graphic library +# +# CONFIG_PKG_USING_U8G2_OFFICIAL is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_PDFGEN is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set +# CONFIG_PKG_USING_NUEMWIN is not set +# CONFIG_PKG_USING_MP3PLAYER is not set +# CONFIG_PKG_USING_TINYJPEG is not set +# CONFIG_PKG_USING_UGUI is not set +# CONFIG_PKG_USING_MCURSES is not set +# CONFIG_PKG_USING_TERMBOX is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_3GPP_AMRNB is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_SEGGER_RTT is not set +# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_LOGMGR is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set +# CONFIG_PKG_USING_KDB is not set +# CONFIG_PKG_USING_WAMR is not set +# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set +# CONFIG_PKG_USING_LWLOG is not set +# CONFIG_PKG_USING_ANV_TRACE is not set +# CONFIG_PKG_USING_ANV_MEMLEAK is not set +# CONFIG_PKG_USING_ANV_TESTSUIT is not set +# CONFIG_PKG_USING_ANV_BENCH is not set +# CONFIG_PKG_USING_DEVMEM is not set +# CONFIG_PKG_USING_REGEX is not set +# CONFIG_PKG_USING_MEM_SANDBOX is not set +# CONFIG_PKG_USING_SOLAR_TERMS is not set +# CONFIG_PKG_USING_GAN_ZHI is not set +# CONFIG_PKG_USING_FDT is not set +# CONFIG_PKG_USING_CBOX is not set +# CONFIG_PKG_USING_SNOWFLAKE is not set +# CONFIG_PKG_USING_HASH_MATCH is not set +# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set +# CONFIG_PKG_USING_VOFA_PLUS is not set + +# +# system packages +# + +# +# enhanced kernel services +# +# CONFIG_PKG_USING_RT_MEMCPY_CM is not set +# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set +# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set + +# +# acceleration: Assembly language or algorithmic acceleration packages +# +# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set +# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set +# CONFIG_PKG_USING_QFPLIB_M3 is not set + +# +# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard +# +# CONFIG_PKG_USING_CMSIS_5 is not set +# CONFIG_PKG_USING_CMSIS_RTOS1 is not set +# CONFIG_PKG_USING_CMSIS_RTOS2 is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_PERF_COUNTER is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_DFS_JFFS2 is not set +# CONFIG_PKG_USING_DFS_UFFS is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set +# CONFIG_PKG_USING_PPOOL is not set +# CONFIG_PKG_USING_OPENAMP is not set +# CONFIG_PKG_USING_LPM is not set +# CONFIG_PKG_USING_TLSF is not set +# CONFIG_PKG_USING_EVENT_RECORDER is not set +# CONFIG_PKG_USING_ARM_2D is not set +# CONFIG_PKG_USING_MCUBOOT is not set +# CONFIG_PKG_USING_TINYUSB is not set +# CONFIG_PKG_USING_CHERRYUSB is not set +# CONFIG_PKG_USING_KMULTI_RTIMER is not set +# CONFIG_PKG_USING_TFDB is not set +# CONFIG_PKG_USING_QPC is not set +# CONFIG_PKG_USING_AGILE_UPGRADE is not set +# CONFIG_PKG_USING_FLASH_BLOB is not set + +# +# peripheral libraries and drivers +# + +# +# sensors drivers +# +# CONFIG_PKG_USING_LSM6DSM is not set +# CONFIG_PKG_USING_LSM6DSL is not set +# CONFIG_PKG_USING_LPS22HB is not set +# CONFIG_PKG_USING_HTS221 is not set +# CONFIG_PKG_USING_LSM303AGR is not set +# CONFIG_PKG_USING_BME280 is not set +# CONFIG_PKG_USING_BME680 is not set +# CONFIG_PKG_USING_BMA400 is not set +# CONFIG_PKG_USING_BMI160_BMX160 is not set +# CONFIG_PKG_USING_SPL0601 is not set +# CONFIG_PKG_USING_MS5805 is not set +# CONFIG_PKG_USING_DA270 is not set +# CONFIG_PKG_USING_DF220 is not set +# CONFIG_PKG_USING_HSHCAL001 is not set +# CONFIG_PKG_USING_BH1750 is not set +# CONFIG_PKG_USING_MPU6XXX is not set +# CONFIG_PKG_USING_AHT10 is not set +# CONFIG_PKG_USING_AP3216C is not set +# CONFIG_PKG_USING_TSL4531 is not set +# CONFIG_PKG_USING_DS18B20 is not set +# CONFIG_PKG_USING_DHT11 is not set +# CONFIG_PKG_USING_DHTXX is not set +# CONFIG_PKG_USING_GY271 is not set +# CONFIG_PKG_USING_GP2Y10 is not set +# CONFIG_PKG_USING_SGP30 is not set +# CONFIG_PKG_USING_HDC1000 is not set +# CONFIG_PKG_USING_BMP180 is not set +# CONFIG_PKG_USING_BMP280 is not set +# CONFIG_PKG_USING_SHTC1 is not set +# CONFIG_PKG_USING_BMI088 is not set +# CONFIG_PKG_USING_HMC5883 is not set +# CONFIG_PKG_USING_MAX6675 is not set +# CONFIG_PKG_USING_TMP1075 is not set +# CONFIG_PKG_USING_SR04 is not set +# CONFIG_PKG_USING_CCS811 is not set +# CONFIG_PKG_USING_PMSXX is not set +# CONFIG_PKG_USING_RT3020 is not set +# CONFIG_PKG_USING_MLX90632 is not set +# CONFIG_PKG_USING_MLX90393 is not set +# CONFIG_PKG_USING_MLX90392 is not set +# CONFIG_PKG_USING_MLX90397 is not set +# CONFIG_PKG_USING_MS5611 is not set +# CONFIG_PKG_USING_MAX31865 is not set +# CONFIG_PKG_USING_VL53L0X is not set +# CONFIG_PKG_USING_INA260 is not set +# CONFIG_PKG_USING_MAX30102 is not set +# CONFIG_PKG_USING_INA226 is not set +# CONFIG_PKG_USING_LIS2DH12 is not set +# CONFIG_PKG_USING_HS300X is not set +# CONFIG_PKG_USING_ZMOD4410 is not set +# CONFIG_PKG_USING_ISL29035 is not set +# CONFIG_PKG_USING_MMC3680KJ is not set +# CONFIG_PKG_USING_QMP6989 is not set +# CONFIG_PKG_USING_BALANCE is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_ADT74XX is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_AS7341 is not set +# CONFIG_PKG_USING_CW2015 is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_STHS34PF80 is not set + +# +# touch drivers +# +# CONFIG_PKG_USING_GT9147 is not set +# CONFIG_PKG_USING_GT1151 is not set +# CONFIG_PKG_USING_GT917S is not set +# CONFIG_PKG_USING_GT911 is not set +# CONFIG_PKG_USING_FT6206 is not set +# CONFIG_PKG_USING_FT5426 is not set +# CONFIG_PKG_USING_FT6236 is not set +# CONFIG_PKG_USING_XPT2046_TOUCH is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ESP_IDF is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set + +# +# Kendryte SDK +# +# CONFIG_PKG_USING_K210_SDK is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_MULTI_INFRARED is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_ILI9341 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_RS232 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set +# CONFIG_PKG_USING_SGM706 is not set +# CONFIG_PKG_USING_STM32WB55_SDK is not set +# CONFIG_PKG_USING_RDA58XX is not set +# CONFIG_PKG_USING_LIBNFC is not set +# CONFIG_PKG_USING_MFOC is not set +# CONFIG_PKG_USING_TMC51XX is not set +# CONFIG_PKG_USING_TCA9534 is not set +# CONFIG_PKG_USING_KOBUKI is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_MICRO_ROS is not set +# CONFIG_PKG_USING_MCP23008 is not set +# CONFIG_PKG_USING_BLUETRUM_SDK is not set +# CONFIG_PKG_USING_MISAKA_AT24CXX is not set +# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set +# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set +# CONFIG_PKG_USING_SOFT_SERIAL is not set +# CONFIG_PKG_USING_MB85RS16 is not set +# CONFIG_PKG_USING_RFM300 is not set +# CONFIG_PKG_USING_IO_INPUT_FILTER is not set +# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set +# CONFIG_PKG_USING_LRF_NV7LIDAR is not set +# CONFIG_PKG_USING_FINGERPRINT is not set + +# +# AI packages +# +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_QUEST is not set +# CONFIG_PKG_USING_NAXOS is not set + +# +# Signal Processing and Control Algorithm Packages +# +# CONFIG_PKG_USING_FIRE_PID_CURVE is not set +# CONFIG_PKG_USING_UKAL is not set + +# +# miscellaneous packages +# + +# +# project laboratory +# + +# +# samples: kernel and components samples +# +CONFIG_PKG_USING_KERNEL_SAMPLES=y +CONFIG_PKG_KERNEL_SAMPLES_PATH="/packages/misc/samples/kernel_samples" +# CONFIG_PKG_USING_KERNEL_SAMPLES_V030 is not set +# CONFIG_PKG_USING_KERNEL_SAMPLES_V040 is not set +CONFIG_PKG_USING_KERNEL_SAMPLES_LATEST_VERSION=y +CONFIG_PKG_KERNEL_SAMPLES_VER="latest" +CONFIG_PKG_USING_KERNEL_SAMPLES_EN=y +# CONFIG_PKG_USING_KERNEL_SAMPLES_ZH is not set +# CONFIG_KERNEL_SAMPLES_USING_THREAD is not set +# CONFIG_KERNEL_SAMPLES_USING_SEMAPHORE is not set +# CONFIG_KERNEL_SAMPLES_USING_MUTEX is not set +# CONFIG_KERNEL_SAMPLES_USING_MAILBOX is not set +# CONFIG_KERNEL_SAMPLES_USING_EVENT is not set +# CONFIG_KERNEL_SAMPLES_USING_MESSAGEQUEUE is not set +# CONFIG_KERNEL_SAMPLES_USING_TIMER is not set +# CONFIG_KERNEL_SAMPLES_USING_HEAP is not set +# CONFIG_KERNEL_SAMPLES_USING_MEMHEAP is not set +# CONFIG_KERNEL_SAMPLES_USING_MEMPOOL is not set +# CONFIG_KERNEL_SAMPLES_USING_IDLEHOOK is not set +# CONFIG_KERNEL_SAMPLES_USING_SIGNAL is not set +# CONFIG_KERNEL_SAMPLES_USING_INTERRUPT is not set +# CONFIG_KERNEL_SAMPLES_USING_PRI_INVERSION is not set +# CONFIG_KERNEL_SAMPLES_USING_TIME_SLICE is not set +# CONFIG_KERNEL_SAMPLES_USING_SCHEDULER_HOOK is not set +# CONFIG_KERNEL_SAMPLES_USING_PRODUCER_CONSUMER is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set + +# +# entertainment: terminal games and other interesting software packages +# +# CONFIG_PKG_USING_CMATRIX is not set +# CONFIG_PKG_USING_SL is not set +# CONFIG_PKG_USING_CAL is not set +# CONFIG_PKG_USING_ACLOCK is not set +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_DONUT is not set +# CONFIG_PKG_USING_COWSAY is not set +# CONFIG_PKG_USING_MORSE is not set +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_MINIZIP is not set +# CONFIG_PKG_USING_HEATSHRINK is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_CRCLIB is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_STATE_MACHINE is not set +# CONFIG_PKG_USING_DESIGN_PATTERN is not set +# CONFIG_PKG_USING_CONTROLLER is not set +# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set +# CONFIG_PKG_USING_MFBD is not set +# CONFIG_PKG_USING_SLCAN2RTT is not set +# CONFIG_PKG_USING_SOEM is not set +# CONFIG_PKG_USING_QPARAM is not set +# CONFIG_PKG_USING_CorevMCU_CLI is not set + +# +# Arduino libraries +# +# CONFIG_PKG_USING_RTDUINO is not set + +# +# Projects +# +# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set +# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set +# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set + +# +# Sensors +# +# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set +# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set +# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set +# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set +# CONFIG_PKG_USING_SEEED_ITG3200 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set +# CONFIG_PKG_USING_SEEED_MP503 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set + +# +# Display +# +# CONFIG_PKG_USING_ARDUINO_U8G2 is not set +# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set +# CONFIG_PKG_USING_SEEED_TM1637 is not set + +# +# Timing +# +# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set + +# +# Data Processing +# +# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set +# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set + +# +# Data Storage +# + +# +# Communication +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set + +# +# Device Control +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set +# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set + +# +# Other +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set +# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set + +# +# Signal IO +# +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set +# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set + +# +# Uncategorized +# + +# +# Hardware Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_UART=y +CONFIG_RT_USING_UART1=y +# CONFIG_RT_USING_UART0 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_CAN is not set +# CONFIG_BSP_USING_GPIO is not set +# CONFIG_BSP_USING_QSPI is not set +CONFIG_BSP_USING_ETH=y +CONFIG_RT_LWIP_PBUF_POOL_BUFSIZE=1700 +# CONFIG_BSP_USING_SDIO is not set + +# +# Board extended module Drivers +# +CONFIG_BSP_USING_GIC=y +CONFIG_BSP_USING_GICV3=y +CONFIG_PHYTIUM_ARCH_AARCH64=y +CONFIG_ARM_SPI_BIND_CPU_ID=2 + +# +# Standalone Setting +# +CONFIG_TARGET_ARMV8_AARCH64=y + +# +# Board Configuration +# +# CONFIG_TARGET_F2000_4 is not set +# CONFIG_TARGET_D2000 is not set +CONFIG_TARGET_E2000Q=y +# CONFIG_TARGET_E2000D is not set +# CONFIG_TARGET_E2000S is not set +CONFIG_TARGET_E2000=y +CONFIG_DEFAULT_DEBUG_PRINT_UART1=y +# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set +# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set + +# +# Components Configuration +# +CONFIG_USE_SPI=y +CONFIG_USE_FSPIM=y +CONFIG_USE_QSPI=y + +# +# Qspi Configuration +# +CONFIG_USE_FQSPI=y +# CONFIG_USE_GIC is not set +CONFIG_USE_IOPAD=y +CONFIG_ENABLE_IOPAD=y +CONFIG_USE_SERIAL=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# CONFIG_USE_GPIO is not set +CONFIG_USE_ETH=y + +# +# Eth Configuration +# +CONFIG_ENABLE_FXMAC=y +# CONFIG_ENABLE_FGMAC is not set +CONFIG_FXMAC_PHY_COMMON=y +# CONFIG_FXMAC_PHY_YT is not set +# CONFIG_USE_CAN is not set +# CONFIG_USE_I2C is not set +# CONFIG_USE_TIMER is not set +# CONFIG_USE_MIO is not set +# CONFIG_USE_SDMMC is not set +# CONFIG_USE_PCIE is not set +# CONFIG_USE_WDT is not set +# CONFIG_USE_DMA is not set +# CONFIG_USE_NAND is not set +# CONFIG_USE_RTC is not set +# CONFIG_USE_SATA is not set +# CONFIG_USE_USB is not set +# CONFIG_USE_ADC is not set +# CONFIG_USE_PWM is not set +# CONFIG_USE_IPC is not set +# CONFIG_USE_MEDIA is not set +# CONFIG_USE_SCMI_MHU is not set +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +# CONFIG_USE_DEFAULT_INTERRUPT_CONFIG is not set +# CONFIG_LOG_EXTRA_INFO is not set +# CONFIG_LOG_DISPALY_CORE_NUM is not set +# CONFIG_BOOTUP_DEBUG_PRINTS is not set +CONFIG_PHYTIUM_RTT_TEST=y +# CONFIG_ENABLE_RTT_UTEST is not set +# CONFIG_ENABLE_KERNEL_TEST is not set +# CONFIG_ENABLE_KERNEL_SAMPLE is not set +# CONFIG_ENABLE_COREMARK is not set +# CONFIG_ENABLE_DHRYSTONE is not set diff --git a/bsp/phytium/aarch64/configs/e2000q_rtthread_test.h b/bsp/phytium/aarch64/configs/e2000q_rtthread_test.h new file mode 100644 index 00000000000..e50c791aea6 --- /dev/null +++ b/bsp/phytium/aarch64/configs/e2000q_rtthread_test.h @@ -0,0 +1,386 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 16 +#define RT_USING_SMP +#define RT_CPUS_NR 2 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_HOOK_USING_FUNC_PTR +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 40960 +#define SYSTEM_THREAD_STACK_SIZE 40960 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 4096 + +/* kservice optimization */ + +#define RT_KSERVICE_USING_STDLIB +#define RT_KPRINTF_USING_LONGLONG +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_PAGE_MAX_ORDER 16 +#define RT_USING_SLAB +#define RT_USING_MEMHEAP +#define RT_MEMHEAP_FAST_MODE +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x50001 +#define ARCH_CPU_64BIT +#define RT_USING_CACHE +#define ARCH_ARM_BOOTWITH_FLUSH_CACHE +#define ARCH_MM_MMU +#define ARCH_ARM +#define ARCH_ARM_MMU +#define ARCH_ARMV8 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 8192 +#define RT_MAIN_THREAD_PRIORITY 10 +#define RT_USING_MSH +#define RT_USING_FINSH +#define FINSH_USING_MSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_CMD_SIZE 80 +#define MSH_USING_BUILT_IN_COMMANDS +#define FINSH_USING_DESCRIPTION +#define FINSH_ARG_MAX 10 + +/* DFS: device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_POSIX +#define DFS_USING_WORKDIR +#define DFS_FD_MAX 16 +#define RT_USING_DFS_V1 +#define DFS_FILESYSTEMS_MAX 4 +#define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 +#define RT_USING_DFS_DEVFS +#define RT_USING_DFS_RAMFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_UNAMED_PIPE_NUMBER 64 +#define RT_USING_SYSTEM_WORKQUEUE +#define RT_SYSTEM_WORKQUEUE_STACKSIZE 8192 +#define RT_SYSTEM_WORKQUEUE_PRIORITY 23 +#define RT_USING_SERIAL +#define RT_USING_SERIAL_V1 +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_NULL +#define RT_USING_ZERO +#define RT_USING_RANDOM +#define RT_USING_RTC + +/* Using USB */ + + +/* C/C++ and POSIX layer */ + +#define RT_LIBC_DEFAULT_TIMEZONE 8 + +/* POSIX (Portable Operating System Interface) layer */ + +#define RT_USING_POSIX_FS +#define RT_USING_POSIX_DEVIO +#define RT_USING_POSIX_STDIO +#define RT_USING_POSIX_TERMIOS +#define RT_USING_POSIX_DELAY +#define RT_USING_POSIX_CLOCK +#define RT_USING_POSIX_TIMER + +/* Interprocess Communication (IPC) */ + + +/* Socket is in the 'Network' category */ + + +/* Network */ + +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +#define RT_LWIP_DEBUG +#define RT_LWIP_NETIF_DEBUG + +/* Utilities */ + +#define RT_USING_RYM +#define YMODEM_USING_FILE_TRANSFER +#define RT_USING_ADT + +/* RT-Thread Utestcases */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + +/* JSON: JavaScript Object Notation, a lightweight data-interchange format */ + + +/* XML: Extensible Markup Language */ + + +/* multimedia packages */ + +/* LVGL: powerful and easy-to-use embedded GUI library */ + + +/* u8g2: a monochrome graphic library */ + + +/* tools packages */ + + +/* system packages */ + +/* enhanced kernel services */ + + +/* acceleration: Assembly language or algorithmic acceleration packages */ + + +/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + +/* sensors drivers */ + + +/* touch drivers */ + + +/* Kendryte SDK */ + + +/* AI packages */ + + +/* Signal Processing and Control Algorithm Packages */ + + +/* miscellaneous packages */ + +/* project laboratory */ + +/* samples: kernel and components samples */ + +#define PKG_USING_KERNEL_SAMPLES +#define PKG_USING_KERNEL_SAMPLES_LATEST_VERSION +#define PKG_USING_KERNEL_SAMPLES_EN + +/* entertainment: terminal games and other interesting software packages */ + + +/* Arduino libraries */ + + +/* Projects */ + + +/* Sensors */ + + +/* Display */ + + +/* Timing */ + + +/* Data Processing */ + + +/* Data Storage */ + +/* Communication */ + + +/* Device Control */ + + +/* Other */ + + +/* Signal IO */ + + +/* Uncategorized */ + +/* Hardware Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_UART +#define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 + +/* Board extended module Drivers */ + +#define BSP_USING_GIC +#define BSP_USING_GICV3 +#define PHYTIUM_ARCH_AARCH64 +#define ARM_SPI_BIND_CPU_ID 2 + +/* Standalone Setting */ + +#define TARGET_ARMV8_AARCH64 + +/* Board Configuration */ + +#define TARGET_E2000Q +#define TARGET_E2000 +#define DEFAULT_DEBUG_PRINT_UART1 + +/* Components Configuration */ + +#define USE_SPI +#define USE_FSPIM +#define USE_QSPI + +/* Qspi Configuration */ + +#define USE_FQSPI +#define USE_IOPAD +#define ENABLE_IOPAD +#define USE_SERIAL + +/* Usart Configuration */ + +#define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON +#define LOG_ERROR +#define PHYTIUM_RTT_TEST + +#endif diff --git a/bsp/phytium/aarch64/link.lds b/bsp/phytium/aarch64/link.lds deleted file mode 100644 index 2fbf19407bf..00000000000 --- a/bsp/phytium/aarch64/link.lds +++ /dev/null @@ -1,148 +0,0 @@ -/* - * Copyright (c) 2006-2021, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * 2017-5-30 bernard first version - */ - -/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */ - -SECTIONS -{ - . = 0x80080000 ; - . = ALIGN(4096); - .text : - { - KEEP(*(.text.entrypoint)) /* The entry point */ - *(.vectors) - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - *(COMMON) - - /* section information for utest */ - . = ALIGN(8); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - __rt_utest_tc_tab_end = .; - - /* section information for finsh shell */ - . = ALIGN(16); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - . = ALIGN(16); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - . = ALIGN(16); - - /* section information for initial. */ - . = ALIGN(16); - __rt_init_start = .; - KEEP(*(SORT(.rti_fn*))) - __rt_init_end = .; - . = ALIGN(16); - - . = ALIGN(16); - _etext = .; - } - . = ALIGN(4); - .eh_frame_hdr : - { - *(.eh_frame_hdr) - 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} -} - -__bss_size = SIZEOF(.bss); \ No newline at end of file diff --git a/bsp/phytium/aarch64/link_smart.lds b/bsp/phytium/aarch64/link_smart.lds deleted file mode 100644 index f9aa24b24a6..00000000000 --- a/bsp/phytium/aarch64/link_smart.lds +++ /dev/null @@ -1,149 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * 2017-5-30 bernard first version - */ - -/* _EL1_STACK_SIZE = DEFINED(_EL1_STACK_SIZE) ? _EL1_STACK_SIZE : 0x20000; */ - -SECTIONS -{ - /* . = 0x80080000 ; */ - . = 0xffff000000080000 ; - . = ALIGN(4096); - .text : - { - KEEP(*(.text.entrypoint)) /* The entry point */ - *(.vectors) - *(.text) /* remaining code */ - *(.text.*) /* remaining code */ - - *(.rodata) /* read-only data (constants) */ - *(.rodata*) - *(.glue_7) - *(.glue_7t) - *(.gnu.linkonce.t*) - - *(COMMON) - - /* section information for utest */ - . = ALIGN(8); - __rt_utest_tc_tab_start = .; - KEEP(*(UtestTcTab)) - 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.); - KEEP(*(SORT(.dtors.*))) - KEEP(*(.dtors)) - PROVIDE(__dtors_end__ = .); - } - - . = ALIGN(16); - .bss : - { - PROVIDE(__bss_start = .); - *(.bss) - *(.bss.*) - *(.dynbss) - . = ALIGN(32); - PROVIDE(__bss_end = .); - } - - _end = .; - - /* Stabs debugging sections. */ - .stab 0 : { *(.stab) } - .stabstr 0 : { *(.stabstr) } - .stab.excl 0 : { *(.stab.excl) } - .stab.exclstr 0 : { *(.stab.exclstr) } - .stab.index 0 : { *(.stab.index) } - .stab.indexstr 0 : { *(.stab.indexstr) } - .comment 0 : { *(.comment) } - /* DWARF debug sections. - * Symbols in the DWARF debugging sections are relative to the beginning - * of the section so we begin them at 0. */ - /* DWARF 1 */ - .debug 0 : { *(.debug) } - .line 0 : { *(.line) } - /* GNU DWARF 1 extensions */ - .debug_srcinfo 0 : { *(.debug_srcinfo) } - .debug_sfnames 0 : { *(.debug_sfnames) } - /* DWARF 1.1 and DWARF 2 */ - .debug_aranges 0 : { *(.debug_aranges) } - .debug_pubnames 0 : { *(.debug_pubnames) } - /* DWARF 2 */ - .debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) } - .debug_abbrev 0 : { *(.debug_abbrev) } - .debug_line 0 : { *(.debug_line) } - .debug_frame 0 : { *(.debug_frame) } - .debug_str 0 : { *(.debug_str) } - .debug_loc 0 : { *(.debug_loc) } - .debug_macinfo 0 : { *(.debug_macinfo) } - /* SGI/MIPS DWARF 2 extensions */ - .debug_weaknames 0 : { *(.debug_weaknames) } - .debug_funcnames 0 : { *(.debug_funcnames) } - .debug_typenames 0 : { *(.debug_typenames) } - .debug_varnames 0 : { *(.debug_varnames) } -} - -__bss_size = SIZEOF(.bss); \ No newline at end of file diff --git a/bsp/phytium/aarch64/makefile b/bsp/phytium/aarch64/makefile index d97df767343..1bef4b2c3a2 100644 --- a/bsp/phytium/aarch64/makefile +++ b/bsp/phytium/aarch64/makefile @@ -28,6 +28,10 @@ else RTCONFIG := $(RTCONFIG)_rtthread endif +ifdef CONFIG_PHYTIUM_RTT_TEST +RTCONFIG := $(RTCONFIG)_test +endif + boot: make all cp rtthread_a64.elf /mnt/d/tftboot @@ -60,20 +64,44 @@ load_e2000q_rtsmart: @cp ./configs/e2000q_rtsmart.h ./rtconfig.h -f @scons -c +load_e2000q_rtsmart_test: + @echo "Load configs from ./configs/e2000q_rtsmart" + @cp ./configs/e2000q_rtsmart_test ./.config -f + @cp ./configs/e2000q_rtsmart_test.h ./rtconfig.h -f + @scons -c + load_e2000q_rtthread: @echo "Load configs from ./configs/e2000q_rtthread" @cp ./configs/e2000q_rtthread ./.config -f @cp ./configs/e2000q_rtthread.h ./rtconfig.h -f @scons -c +load_e2000q_rtthread_test: + @echo "Load configs from ./configs/e2000q_rtthread" + @cp ./configs/e2000q_rtthread_test ./.config -f + @cp ./configs/e2000q_rtthread_test.h ./rtconfig.h -f + @scons -c + load_e2000d_rtsmart: @echo "Load configs from ./configs/e2000d_rtsmart" @cp ./configs/e2000d_rtsmart ./.config -f @cp ./configs/e2000d_rtsmart.h ./rtconfig.h -f @scons -c +load_e2000d_rtsmart_test: + @echo "Load configs from ./configs/e2000d_rtsmart" + @cp ./configs/e2000d_rtsmart_test ./.config -f + @cp ./configs/e2000d_rtsmart_test.h ./rtconfig.h -f + @scons -c + load_e2000d_rtthread: @echo "Load configs from ./configs/e2000d_rtthread" @cp ./configs/e2000d_rtthread ./.config -f @cp ./configs/e2000d_rtthread.h ./rtconfig.h -f @scons -c + +load_e2000d_rtthread_test: + @echo "Load configs from ./configs/e2000d_rtthread" + @cp ./configs/e2000d_rtthread_test ./.config -f + @cp ./configs/e2000d_rtthread_test.h ./rtconfig.h -f + @scons -c \ No newline at end of file diff --git a/bsp/phytium/aarch64/rtconfig.h b/bsp/phytium/aarch64/rtconfig.h index 29e11f836e3..2aaee109e05 100644 --- a/bsp/phytium/aarch64/rtconfig.h +++ b/bsp/phytium/aarch64/rtconfig.h @@ -18,17 +18,20 @@ #define RT_HOOK_USING_FUNC_PTR #define RT_USING_IDLE_HOOK #define RT_IDLE_HOOK_LIST_SIZE 4 -#define IDLE_THREAD_STACK_SIZE 40960 -#define SYSTEM_THREAD_STACK_SIZE 40960 +#define IDLE_THREAD_STACK_SIZE 8192 +#define SYSTEM_THREAD_STACK_SIZE 8192 #define RT_USING_TIMER_SOFT #define RT_TIMER_THREAD_PRIO 4 -#define RT_TIMER_THREAD_STACK_SIZE 4096 +#define RT_TIMER_THREAD_STACK_SIZE 8192 /* kservice optimization */ #define RT_KSERVICE_USING_STDLIB #define RT_KPRINTF_USING_LONGLONG -#define RT_DEBUG +#define RT_USING_DEBUG +#define RT_DEBUGING_COLOR +#define RT_DEBUGING_CONTEXT +#define RT_DEBUGING_INIT /* Inter-Thread communication */ @@ -40,12 +43,12 @@ /* Memory Management */ -#define RT_PAGE_MAX_ORDER 11 -#define RT_USING_MEMPOOL -#define RT_USING_SMALL_MEM +#define RT_PAGE_MAX_ORDER 16 +#define RT_USING_SLAB #define RT_USING_MEMHEAP #define RT_MEMHEAP_FAST_MODE -#define RT_USING_SMALL_MEM_AS_HEAP +#define RT_USING_SLAB_AS_HEAP +#define RT_USING_HEAP_ISR #define RT_USING_HEAP /* Kernel Device Object */ @@ -55,14 +58,20 @@ #define RT_CONSOLEBUF_SIZE 128 #define RT_CONSOLE_DEVICE_NAME "uart1" #define RT_VER_NUM 0x50001 + +/* RT-Thread Architecture */ + #define ARCH_CPU_64BIT #define RT_USING_CACHE -#define RT_USING_HW_ATOMIC #define ARCH_ARM_BOOTWITH_FLUSH_CACHE #define ARCH_MM_MMU #define ARCH_ARM #define ARCH_ARM_MMU #define ARCH_ARMV8 +#define ARCH_TEXT_OFFSET 0x80000 +#define ARCH_RAM_OFFSET 0x80000000 +#define ARCH_SECONDARY_CPU_STACK_SIZE 4096 +#define ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS /* RT-Thread Components */ @@ -93,6 +102,21 @@ #define RT_USING_DFS_V1 #define DFS_FILESYSTEMS_MAX 4 #define DFS_FILESYSTEM_TYPES_MAX 4 +#define RT_USING_DFS_ELMFAT + +/* elm-chan's FatFs, Generic FAT Filesystem Module */ + +#define RT_DFS_ELM_CODE_PAGE 437 +#define RT_DFS_ELM_WORD_ACCESS +#define RT_DFS_ELM_USE_LFN_3 +#define RT_DFS_ELM_USE_LFN 3 +#define RT_DFS_ELM_LFN_UNICODE_0 +#define RT_DFS_ELM_LFN_UNICODE 0 +#define RT_DFS_ELM_MAX_LFN 255 +#define RT_DFS_ELM_DRIVES 2 +#define RT_DFS_ELM_MAX_SECTOR_SIZE 512 +#define RT_DFS_ELM_REENTRANT +#define RT_DFS_ELM_MUTEX_TIMEOUT 3000 #define RT_USING_DFS_DEVFS #define RT_USING_DFS_RAMFS @@ -111,6 +135,12 @@ #define RT_USING_ZERO #define RT_USING_RANDOM #define RT_USING_RTC +#define RT_USING_SDIO +#define RT_SDIO_STACK_SIZE 4096 +#define RT_SDIO_THREAD_PRIORITY 15 +#define RT_MMCSD_STACK_SIZE 4096 +#define RT_MMCSD_THREAD_PREORITY 22 +#define RT_MMCSD_MAX_PARTITION 16 /* Using USB */ @@ -137,13 +167,73 @@ /* Network */ +#define RT_USING_SAL +#define SAL_INTERNET_CHECK + +/* Docking with protocol stacks */ + +#define SAL_USING_LWIP +#define SAL_USING_POSIX +#define RT_USING_NETDEV +#define NETDEV_USING_IFCONFIG +#define NETDEV_USING_PING +#define NETDEV_USING_NETSTAT +#define NETDEV_USING_AUTO_DEFAULT +#define NETDEV_IPV4 1 +#define NETDEV_IPV6 0 +#define RT_USING_LWIP +#define RT_USING_LWIP212 +#define RT_USING_LWIP_VER_NUM 0x20102 +#define RT_LWIP_MEM_ALIGNMENT 64 +#define RT_LWIP_IGMP +#define RT_LWIP_ICMP +#define RT_LWIP_DNS + +/* Static IPv4 Address */ + +#define RT_LWIP_IPADDR "192.168.4.10" +#define RT_LWIP_GWADDR "192.168.4.1" +#define RT_LWIP_MSKADDR "255.255.255.0" +#define RT_LWIP_UDP +#define RT_LWIP_TCP +#define RT_LWIP_RAW +#define RT_MEMP_NUM_NETCONN 8 +#define RT_LWIP_PBUF_NUM 512 +#define RT_LWIP_RAW_PCB_NUM 4 +#define RT_LWIP_UDP_PCB_NUM 4 +#define RT_LWIP_TCP_PCB_NUM 4 +#define RT_LWIP_TCP_SEG_NUM 40 +#define RT_LWIP_TCP_SND_BUF 8196 +#define RT_LWIP_TCP_WND 8196 +#define RT_LWIP_TCPTHREAD_PRIORITY 12 +#define RT_LWIP_TCPTHREAD_MBOX_SIZE 8 +#define RT_LWIP_TCPTHREAD_STACKSIZE 16184 +#define RT_LWIP_ETHTHREAD_PRIORITY 12 +#define RT_LWIP_ETHTHREAD_STACKSIZE 2048 +#define RT_LWIP_ETHTHREAD_MBOX_SIZE 8 +#define LWIP_NETIF_STATUS_CALLBACK 1 +#define LWIP_NETIF_LINK_CALLBACK 1 +#define SO_REUSE 1 +#define LWIP_SO_RCVTIMEO 1 +#define LWIP_SO_SNDTIMEO 1 +#define LWIP_SO_RCVBUF 1 +#define LWIP_SO_LINGER 0 +#define LWIP_NETIF_LOOPBACK 0 +#define RT_LWIP_USING_PING +#define RT_LWIP_DEBUG +#define RT_LWIP_NETIF_DEBUG /* Utilities */ #define RT_USING_RYM #define YMODEM_USING_FILE_TRANSFER +#define RT_USING_RESOURCE_ID #define RT_USING_ADT #define RT_USING_ADT_AVL +#define RT_USING_ADT_BITMAP +#define RT_USING_ADT_HASHMAP +#define RT_USING_ADT_REF +#define RT_USING_KTIME /* RT-Thread Utestcases */ @@ -270,6 +360,11 @@ #define BSP_USING_UART #define RT_USING_UART1 +#define BSP_USING_ETH +#define RT_LWIP_PBUF_POOL_BUFSIZE 1700 +#define BSP_USING_SDIO +#define BSP_USING_SDCARD_FATFS +#define USING_SDIO1 /* Board extended module Drivers */ @@ -297,11 +392,22 @@ /* Qspi Configuration */ #define USE_FQSPI +#define USE_IOPAD +#define ENABLE_IOPAD #define USE_SERIAL /* Usart Configuration */ #define ENABLE_Pl011_UART +#define USE_ETH + +/* Eth Configuration */ + +#define ENABLE_FXMAC +#define FXMAC_PHY_COMMON + +/* Sdk common configuration */ + #define LOG_ERROR #endif diff --git a/bsp/phytium/aarch64/rtconfig.py b/bsp/phytium/aarch64/rtconfig.py index 26c597293de..170052b9fad 100644 --- a/bsp/phytium/aarch64/rtconfig.py +++ b/bsp/phytium/aarch64/rtconfig.py @@ -13,6 +13,7 @@ PREFIX = os.getenv('RTT_CC_PREFIX') or 'aarch64-none-elf-' CC = PREFIX + 'gcc' CXX = PREFIX + 'g++' + CPP = PREFIX + 'cpp' AS = PREFIX + 'gcc' AR = PREFIX + 'ar' LINK = PREFIX + 'gcc' @@ -25,10 +26,11 @@ AFPFLAGS = ' ' DEVICE = ' -march=armv8-a -ftree-vectorize -ffast-math -funwind-tables -fno-strict-aliasing' - CXXFLAGS= DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always' + CPPFLAGS = ' -E -P -x assembler-with-cpp' + CXXFLAGS = DEVICE + CFPFLAGS + ' -Wall -fdiagnostics-color=always' CFLAGS = DEVICE + CFPFLAGS + ' -Wall -Wno-cpp -std=gnu99 -fdiagnostics-color=always' AFLAGS = ' -c' + AFPFLAGS + ' -x assembler-with-cpp' - LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread_a64.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static' + LFLAGS = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread_a64.map,-cref,-u,system_vectors -T link.lds' + ' -lsupc++ -lgcc -static' CPATH = '' LPATH = '' diff --git a/bsp/phytium/board/board.c b/bsp/phytium/board/board.c index fe9aba293bd..4485a1e5fbd 100644 --- a/bsp/phytium/board/board.c +++ b/bsp/phytium/board/board.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2006-2023, RT-Thread Development Team + * Copyright (c) 2006-2021, RT-Thread Development Team * * SPDX-License-Identifier: Apache-2.0 * @@ -10,6 +10,7 @@ * 2022-10-26 huanghe first commit * 2022-10-26 zhugengyu support aarch64 * 2023-04-13 zhugengyu support RT-Smart + * 2023-07-27 zhugengyu update aarch32 gtimer usage * */ @@ -22,8 +23,8 @@ #include #ifdef RT_USING_SMART -#include -#include + #include + #include #endif #include @@ -41,6 +42,11 @@ #include "fprintk.h" #include "fearly_uart.h" #include "fcpu_info.h" +#include "fiopad.h" + +#ifdef RT_USING_SMP + #include "fpsci.h" +#endif #define LOG_DEBUG_TAG "BOARD" #define BSP_LOG_ERROR(format, ...) FT_DEBUG_PRINT_E(LOG_DEBUG_TAG, format, ##__VA_ARGS__) @@ -48,6 +54,7 @@ #define BSP_LOG_INFO(format, ...) FT_DEBUG_PRINT_I(LOG_DEBUG_TAG, format, ##__VA_ARGS__) #define BSP_LOG_DEBUG(format, ...) FT_DEBUG_PRINT_D(LOG_DEBUG_TAG, format, ##__VA_ARGS__) +FIOPadCtrl iopad_ctrl; /* mmu config */ extern struct mem_desc platform_mem_desc[]; extern const rt_uint32_t platform_mem_desc_size; @@ -62,7 +69,8 @@ void idle_wfi(void) */ extern size_t MMUTable[]; -rt_region_t init_page_region = { +rt_region_t init_page_region = +{ PAGE_START, PAGE_END }; @@ -78,7 +86,7 @@ static rt_uint32_t timer_step; void rt_hw_timer_isr(int vector, void *parameter) { - GenericTimerCompare(timer_step); + GenericTimerSetTimerCompareValue(GENERIC_TIMER_ID0, timer_step); rt_tick_increase(); } @@ -89,9 +97,9 @@ int rt_hw_timer_init(void) timer_step = GenericTimerFrequecy(); timer_step /= RT_TICK_PER_SECOND; - GenericTimerCompare(timer_step); - GenericTimerInterruptEnable(); - GenericTimerStart(); + GenericTimerSetTimerCompareValue(GENERIC_TIMER_ID0, timer_step); + GenericTimerInterruptEnable(GENERIC_TIMER_ID0); + GenericTimerStart(GENERIC_TIMER_ID0); return 0; } INIT_BOARD_EXPORT(rt_hw_timer_init); @@ -106,17 +114,17 @@ INIT_BOARD_EXPORT(rt_hw_timer_init); void rt_hw_board_aarch64_init(void) { /* AARCH64 */ - #if defined(RT_USING_SMART) - /* 1. init rt_kernel_space table (aspace.start = KERNEL_VADDR_START , aspace.size = ), 2. init io map range (rt_ioremap_start \ rt_ioremap_size) 3. */ - rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET); - #else - rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0); - #endif +#if defined(RT_USING_SMART) + /* 1. init rt_kernel_space table (aspace.start = KERNEL_VADDR_START , aspace.size = ), 2. init io map range (rt_ioremap_start \ rt_ioremap_size) 3. */ + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xfffffffff0000000, 0x10000000, MMUTable, PV_OFFSET); +#else + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0x80000000, 0x10000000, MMUTable, 0); +#endif rt_page_init(init_page_region); rt_hw_mmu_setup(&rt_kernel_space, platform_mem_desc, platform_mem_desc_size); - /* init memory pool */ + /* init memory pool */ #ifdef RT_USING_HEAP rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif @@ -125,7 +133,13 @@ void rt_hw_board_aarch64_init(void) rt_hw_gtimer_init(); + FEarlyUartProbe(); + FIOPadCfgInitialize(&iopad_ctrl, FIOPadLookupConfig(FIOPAD0_ID)); + +#ifdef RT_USING_SMART + iopad_ctrl.config.base_address = (uintptr)rt_ioremap((void *)iopad_ctrl.config.base_address, 0x2000); +#endif /* compoent init */ #ifdef RT_USING_COMPONENTS_INIT @@ -141,12 +155,15 @@ void rt_hw_board_aarch64_init(void) rt_thread_idle_sethook(idle_wfi); #ifdef RT_USING_SMP + FPsciInit(); /* install IPI handle */ rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16); rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler); rt_hw_interrupt_umask(RT_SCHEDULE_IPI); #endif + + } #else @@ -156,25 +173,25 @@ void rt_hw_board_aarch32_init(void) #if defined(RT_USING_SMART) /* set io map range is 0xf0000000 ~ 0x10000000 , Memory Protection start address is 0xf0000000 - rt_mpr_size */ - rt_hw_mmu_map_init(&rt_kernel_space, (void*)0xf0000000, 0x10000000, MMUTable, PV_OFFSET); + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0xf0000000, 0x10000000, MMUTable, PV_OFFSET); rt_page_init(init_page_region); /* rt_kernel_space 在start_gcc.S 中被初始化，此函数将iomap 空间放置在kernel space 上 */ - rt_hw_mmu_ioremap_init(&rt_kernel_space, (void*)0xf0000000, 0x10000000); + rt_hw_mmu_ioremap_init(&rt_kernel_space, (void *)0xf0000000, 0x10000000); /* */ - arch_kuser_init(&rt_kernel_space, (void*)0xffff0000); + arch_kuser_init(&rt_kernel_space, (void *)0xffff0000); #else /* map kernel space memory (totally 1GB = 0x10000000), pv_offset = 0 if not RT_SMART: 0x80000000 ~ 0x80100000: kernel stack 0x80100000 ~ __bss_end: kernel code and data */ - rt_hw_mmu_map_init(&rt_kernel_space, (void*)0x80000000, 0x10000000, MMUTable, 0); - rt_hw_mmu_ioremap_init(&rt_kernel_space, (void*)0x80000000, 0x10000000); + rt_hw_mmu_map_init(&rt_kernel_space, (void *)0x80000000, 0x10000000, MMUTable, 0); + rt_hw_mmu_ioremap_init(&rt_kernel_space, (void *)0x80000000, 0x10000000); #endif - /* init memory pool */ + /* init memory pool */ #ifdef RT_USING_HEAP rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); #endif @@ -189,8 +206,13 @@ void rt_hw_board_aarch32_init(void) #endif rt_uint32_t redist_addr = 0; + FEarlyUartProbe(); + + FIOPadCfgInitialize(&iopad_ctrl, FIOPadLookupConfig(FIOPAD0_ID)); + #if defined(RT_USING_SMART) - redist_addr = (uint32_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * 128*1024); + redist_addr = (uint32_t)rt_ioremap(GICV3_RD_BASE_ADDR, 4 * 128 * 1024); + iopad_ctrl.config.base_address = (uintptr)rt_ioremap((void *)iopad_ctrl.config.base_address, 0x2000); #else redist_addr = GICV3_RD_BASE_ADDR; #endif @@ -242,6 +264,7 @@ void rt_hw_board_aarch32_init(void) rt_thread_idle_sethook(idle_wfi); #ifdef RT_USING_SMP + FPsciInit(); /* install IPI handle */ rt_hw_interrupt_set_priority(RT_SCHEDULE_IPI, 16); rt_hw_ipi_handler_install(RT_SCHEDULE_IPI, rt_scheduler_ipi_handler); diff --git a/bsp/phytium/board/board.h b/bsp/phytium/board/board.h index 35ada57347c..8b8646365c6 100644 --- a/bsp/phytium/board/board.h +++ b/bsp/phytium/board/board.h @@ -9,6 +9,7 @@ * Date Author Notes * 2022-10-26 huanghe first commit * 2022-04-13 zhugengyu support RT-Smart + * 2023-07-27 liqiaozhong add gpio pin definition * */ @@ -17,6 +18,7 @@ #include "fparameters.h" #include "phytium_cpu.h" +#include "fkernel.h" #include "mmu.h" #ifdef RT_USING_SMART @@ -44,6 +46,16 @@ #define PAGE_END (PAGE_START +PAGE_POOL_SIZE) #endif +#ifdef RT_USING_PIN +/* gpio pin_index handle */ +#define FGPIO_OPS_PIN_INDEX(ctrl, port, pin) SET_REG32_BITS(ctrl, 19, 12) | \ + SET_REG32_BITS(port, 11, 8) | \ + SET_REG32_BITS(pin, 7, 0) +#define FGPIO_OPS_PIN_CTRL_ID(pin_idx) GET_REG32_BITS(pin_idx, 19, 12) +#define FGPIO_OPS_PIN_PORT_ID(pin_idx) GET_REG32_BITS(pin_idx, 11, 8) +#define FGPIO_OPS_PIN_ID(pin_idx) GET_REG32_BITS(pin_idx, 7, 0) +#endif + void rt_hw_board_init(void); #endif diff --git a/bsp/phytium/board/e2000/memory_map.c b/bsp/phytium/board/e2000/memory_map.c index 4222a4855aa..fdea92c5bc4 100644 --- a/bsp/phytium/board/e2000/memory_map.c +++ b/bsp/phytium/board/e2000/memory_map.c @@ -8,6 +8,7 @@ * Change Logs: * Date Author Notes * 2023-04-27 huanghe first version + * 2023-07-27 zhangyan add qspi io space * */ @@ -48,6 +49,12 @@ struct mem_desc platform_mem_desc[] = { 0x28000000U, DEVICE_MEM }, + { + 0x00001000U, + 0x0FFFFFFFU, + 0x00001000U, + DEVICE_MEM + }, }; #else struct mem_desc platform_mem_desc[] = diff --git a/bsp/phytium/board/phytium_cpu_id.S b/bsp/phytium/board/phytium_cpu_id.S index b25da4421f4..a62ad272274 100644 --- a/bsp/phytium/board/phytium_cpu_id.S +++ b/bsp/phytium/board/phytium_cpu_id.S @@ -1,3 +1,16 @@ +/* + * Copyright (c) 2006-2021, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Email: opensource_embedded@phytium.com.cn + * + * Change Logs: + * Date Author Notes + * 2023-07-26 huanghe first commit + * + */ + #include "fparameters.h" #include "sdkconfig.h" diff --git a/bsp/phytium/board/secondary_cpu.c b/bsp/phytium/board/secondary_cpu.c index feffab4b50c..bba1bfaa0a5 100644 --- a/bsp/phytium/board/secondary_cpu.c +++ b/bsp/phytium/board/secondary_cpu.c @@ -9,6 +9,7 @@ * Date Author Notes * 2022-10-26 huanghe first commit * 2022-10-26 zhugengyu support aarch64 + * 2023-07-26 huanghe update psci uage * */ @@ -82,13 +83,14 @@ void rt_hw_secondary_cpu_up(void) #if defined(TARGET_ARMV8_AARCH64) /* code */ + rt_kprintf("cpu_mask = 0x%x \n", cpu_mask); char *entry = (char *)_secondary_cpu_entry; entry += PV_OFFSET; - PsciCpuOn(cpu_mask, (uintptr)entry); + FPsciCpuMaskOn(cpu_mask, (uintptr)entry); __DSB(); #else /* code */ - PsciCpuOn(cpu_mask, (uintptr)rt_secondary_cpu_entry); + FPsciCpuMaskOn(cpu_mask, (uintptr)rt_secondary_cpu_entry); __asm__ volatile("dsb" ::: "memory"); #endif diff --git a/bsp/phytium/libraries/SConscript b/bsp/phytium/libraries/SConscript index e7184b93779..ebe52c87ae7 100644 --- a/bsp/phytium/libraries/SConscript +++ b/bsp/phytium/libraries/SConscript @@ -19,7 +19,10 @@ if GetDepend(['TARGET_ARMV8_AARCH32']): path += [STANDALONE_DIR + '/port/arch/armv8/aarch32'] elif GetDepend(['TARGET_ARMV8_AARCH64']): src += Glob(STANDALONE_DIR+'/port/arch/armv8/aarch64/*.c') + Glob(STANDALONE_DIR+'/port/arch/armv8/aarch64/*.S') - path += [STANDALONE_DIR + '/port/arch/armv8/aarch64'] + path += [STANDALONE_DIR + '/port/arch/armv8/aarch64'] + + src += Glob(STANDALONE_DIR+'/port/*.c') + path += [STANDALONE_DIR + '/port/*.h'] # board src += Glob(STANDALONE_DIR+'/board/common/*.c') + Glob(STANDALONE_DIR+'/board/common/*.S') @@ -70,6 +73,26 @@ if GetDepend(['BSP_USING_QSPI']): src += Glob(STANDALONE_DIR+'/drivers/qspi/fqspi/*.c') + Glob(STANDALONE_DIR+'/drivers/qspi/fqspi/*.S') path += [STANDALONE_DIR + '/drivers/qspi/fqspi/'] +## eth +if GetDepend(['BSP_USING_ETH']): + src += Glob(STANDALONE_DIR+'/drivers/eth/fxmac/*.c') + Glob(STANDALONE_DIR+'/drivers/eth/fxmac/*.S') + path += [STANDALONE_DIR + '/drivers/eth/fxmac/'] + [STANDALONE_DIR + '/drivers/eth/fxmac/phy/'] + +## sdio +if GetDepend(['BSP_USING_SDIO']): + src += Glob(STANDALONE_DIR+'/drivers/mmc/fsdio/*.c') + Glob(STANDALONE_DIR+'/drivers/mmc/fsdio/*.S') + path += [STANDALONE_DIR + '/drivers/mmc/fsdio/'] + +## gpio +if GetDepend(['BSP_USING_GPIO']): + src += Glob(STANDALONE_DIR+'/drivers/pin/fgpio/*.c') + Glob(STANDALONE_DIR+'/drivers/pin/fgpio/*.S') + path += [STANDALONE_DIR + '/drivers/pin/fgpio/'] + +## iopad +if GetDepend(['ENABLE_IOPAD']): + src += Glob(STANDALONE_DIR+'/drivers/iopad/fiopad/*.c') + Glob(STANDALONE_DIR+'/drivers/iopad/fiopad/*.S') + path += [STANDALONE_DIR + '/drivers/iopad/fiopad/'] + # phytium ports rt-thread drivers PORT_DRV_DIR = cwd + '/drivers' diff --git a/bsp/phytium/libraries/drivers/Kconfig b/bsp/phytium/libraries/drivers/Kconfig index ddbbb9b5ffd..e1e7482b0fc 100644 --- a/bsp/phytium/libraries/drivers/Kconfig +++ b/bsp/phytium/libraries/drivers/Kconfig @@ -19,7 +19,7 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_SPI bool "Enable Spi" - default y + default n select USE_SPI # sdk spi component select RT_USING_SPI if BSP_USING_SPI @@ -42,17 +42,69 @@ menu "On-chip Peripheral Drivers" menuconfig BSP_USING_CAN bool "Enable CAN" - default y + default n select RT_USING_CAN select RT_CAN_USING_HDR select RT_CAN_USING_CANFD + menuconfig BSP_USING_GPIO + bool "Enable GPIO" + default n + select RT_USING_PIN + menuconfig BSP_USING_QSPI bool "Enable QSPI" - default y + default n select RT_USING_QSPI select RT_USING_SPI + if BSP_USING_QSPI + config USING_QSPI_CHANNEL0 + bool "using qspi channel_0" + default n + config USING_QSPI_CHANNEL1 + bool "using qspi channel_1" + default n + endif + menuconfig BSP_USING_ETH + bool "Enable ETH" + default y + select USE_ETH + if BSP_USING_ETH + config RT_LWIP_PBUF_POOL_BUFSIZE + int "The size of each pbuf in the pbuf pool" + range 1500 2000 + default 1700 + endif + + + + + menuconfig BSP_USING_SDIO + bool "Enable SDIO" + default y + select RT_USING_SDIO + + if BSP_USING_SDIO + config BSP_USING_SDCARD_FATFS + bool "Enable SDCARD (FATFS)" + select RT_USING_DFS_ELMFAT + default y + + choice + prompt "Choose a card to mount" + default USING_SDIO1 + + config USING_SDIO0 + bool "Use SDIO0" + + config USING_SDIO1 + bool "Use SDIO1" + + config USING_EMMC + bool "Use EMMC" + endchoice + endif endmenu menu "Board extended module Drivers" diff --git a/bsp/phytium/libraries/drivers/drv_gpio.c b/bsp/phytium/libraries/drivers/drv_gpio.c new file mode 100644 index 00000000000..3632ff1d798 --- /dev/null +++ b/bsp/phytium/libraries/drivers/drv_gpio.c @@ -0,0 +1,394 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Email: opensource_embedded@phytium.com.cn + * + * Change Logs: + * Date Author Notes + * 2023/7/24 liqiaozhong first add, support intr + * + */ + +#include +#include +#include "interrupt.h" +#include "rtdbg.h" +#ifdef RT_USING_SMART + #include "ioremap.h" +#endif + +#include + +#if defined(TARGET_E2000) + #include "fparameters.h" +#endif +#include "fkernel.h" +#include "fpinctrl.h" +#include "fcpu_info.h" +#include "ftypes.h" +#include "board.h" + +#ifdef RT_USING_PIN +#include "fiopad.h" +#include "fgpio.h" +#include "drv_gpio.h" +/**************************** Type Definitions *******************************/ +typedef void (*FGpioOpsIrqHandler)(s32 vector, void *param); +typedef struct +{ + FGpioDirection direction; + boolean en_irq; + FGpioIrqType irq_type; + FGpioOpsIrqHandler irq_handler; + void *irq_args; +} FGpioOpsPinConfig; + +typedef struct +{ + FGpio ctrl; + FGpioPin pins[FGPIO_PORT_NUM][FGPIO_PIN_NUM]; + FGpioOpsPinConfig pin_config[FGPIO_PORT_NUM][FGPIO_PIN_NUM]; + boolean init_ok; +} FGpioOps; +/***************** Macros (Inline Functions) Definitions *********************/ +#if defined(TARGET_E2000) + #define FGPIO_VERSION_2 +#endif +/************************** Variable Definitions *****************************/ +static FGpioOps gpio[FGPIO_NUM]; +extern FIOPadCtrl iopad_ctrl; +/*******************************Api Functions*********************************/ +static void FGpioOpsSetupCtrlIRQ(FGpio *ctrl) +{ + u32 cpu_id; + u32 irq_num = ctrl->config.irq_num[0]; + + GetCpuId(&cpu_id); + LOG_D("In FGpioOpsSetupCtrlIRQ() -> cpu_id %d, irq_num %d\r\n", cpu_id, irq_num); + rt_hw_interrupt_set_target_cpus(irq_num, cpu_id); + rt_hw_interrupt_set_priority(irq_num, ctrl->config.irq_priority); /* setup interrupt */ + rt_hw_interrupt_install(irq_num, FGpioInterruptHandler, ctrl, NULL); /* register intr handler */ + rt_hw_interrupt_umask(irq_num); + return; +} + +/* setup gpio pin interrupt */ +static void FGpioOpsSetupPinIRQ(FGpio *ctrl, FGpioPin *const pin, FGpioOpsPinConfig *config) +{ + u32 cpu_id; + u32 irq_num = ctrl->config.irq_num[pin->index.pin]; + + GetCpuId(&cpu_id); + LOG_D("in FGpioOpsSetupPinIRQ() -> cpu_id %d, irq_num %d", cpu_id, irq_num); + rt_hw_interrupt_set_target_cpus(irq_num, cpu_id); + rt_hw_interrupt_set_priority(irq_num, ctrl->config.irq_priority); /* setup interrupt */ + rt_hw_interrupt_install(irq_num, FGpioInterruptHandler, config->irq_args, NULL); /* register intr handler */ + rt_hw_interrupt_umask(irq_num); + return; +} + +void FIOPadSetGpioMux(u32 ctrl_id_p, u32 pin_id_p) +{ +#if defined(TARGET_E2000D) + if (ctrl_id_p == FGPIO4_ID) + { + switch (pin_id_p) + { + case 11: /* gpio 4-a-11 */ + FIOPadSetFunc(&iopad_ctrl, FIOPAD_AC45_REG0_OFFSET, FIOPAD_FUNC6); + break; + case 12: /* gpio 4-a-12 */ + FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE43_REG0_OFFSET, FIOPAD_FUNC6); + break; + default: + LOG_E("Unsupported ctrl pin."); + RT_ASSERT(0); + break; + } + } + else + { + LOG_E("Unsupported ctrl."); + RT_ASSERT(0); + } +#endif + +#if defined(TARGET_E2000Q) + if (ctrl_id_p == FGPIO4_ID) + { + switch (pin_id_p) + { + case 11: /* gpio 4-a-11 */ + FIOPadSetFunc(&iopad_ctrl, FIOPAD_AC49_REG0_OFFSET, FIOPAD_FUNC6); + break; + case 12: /* gpio 4-a-12 */ + FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE47_REG0_OFFSET, FIOPAD_FUNC6); + break; + default: + LOG_E("Unsupported ctrl pin."); + RT_ASSERT(0); + break; + } + } + else + { + LOG_E("Unsupported ctrl."); + RT_ASSERT(0); + } +#endif +} + +/* on E2000, if u want use GPIO-4-11, set pin = FGPIO_OPS_PIN_INDEX(4, 0, 11) */ +static void drv_pin_mode(struct rt_device *device, rt_base_t pin, rt_uint8_t mode) +{ + u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin); + u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin); + u32 pin_id = FGPIO_OPS_PIN_ID(pin); + FGpioPinId gpio_pin_id; + FError err = FGPIO_SUCCESS; + FGpio *instance = &gpio[ctrl_id].ctrl; + FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id]; + FGpioOpsPinConfig *pin_config = &gpio[ctrl_id].pin_config[port_id][pin_id]; + + if (ctrl_id >= FGPIO_NUM) + { + LOG_E("ctrl_id too large!!!"); + return; + } + + if (FALSE == gpio[ctrl_id].init_ok) /* init ctrl if needed */ + { + FGpioConfig input_cfg = *FGpioLookupConfig(ctrl_id); + memset(instance, 0, sizeof(*instance)); +#ifdef RT_USING_SMART + input_cfg.base_addr = (uintptr)rt_ioremap((void *)input_cfg.base_addr, 0x1000); +#endif + err = FGpioCfgInitialize(instance, &input_cfg); + if (FGPIO_SUCCESS != err) + { + LOG_E("Ctrl: %d init fail!!!\n", ctrl_id); + return; + } + gpio[ctrl_id].init_ok = TRUE; + } + + FIOPadSetGpioMux(ctrl_id, pin_id); + + if (FT_COMPONENT_IS_READY == pin_instance->is_ready) + { + FGpioPinDeInitialize(pin_instance); + } + + gpio_pin_id.ctrl = ctrl_id; + gpio_pin_id.port = port_id; + gpio_pin_id.pin = pin_id; + err = FGpioPinInitialize(instance, pin_instance, gpio_pin_id); + + if (FGPIO_SUCCESS != err) + { + LOG_E("Pin %d-%c-%d init fail!!!\n", + ctrl_id, + port_id == 0 ? 'a' : 'b', + pin_id); + return; + } + + switch (mode) + { + case PIN_MODE_OUTPUT: + pin_config->direction = FGPIO_DIR_OUTPUT; + pin_config->en_irq = FALSE; + break; + case PIN_MODE_INPUT: + pin_config->direction = FGPIO_DIR_INPUT; + pin_config->en_irq = TRUE; + pin_config->irq_type = FGPIO_IRQ_TYPE_EDGE_RISING; + break; + default: + rt_kprintf("Not support mode %d!!!\n", mode); + break; + } + + FGpioSetDirection(pin_instance, pin_config->direction); + rt_kprintf("Init GPIO-%d-%c-%d as an %sput pin\r\n", + ctrl_id, + port_id, + pin_id, pin_config->direction == FGPIO_DIR_OUTPUT ? "out" : "in"); +} + +void drv_pin_write(struct rt_device *device, rt_base_t pin, rt_uint8_t value) +{ + u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin); + u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin); + u32 pin_id = FGPIO_OPS_PIN_ID(pin); + FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id]; + + if (pin_instance == RT_NULL) + { + rt_kprintf("Pin %d-%c-%d not set mode\n", + ctrl_id, + port_id == 0 ? 'a' : 'b', + pin_id); + return; + } + FGpioSetOutputValue(pin_instance, (value == PIN_HIGH) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW); +} + +rt_int8_t drv_pin_read(struct rt_device *device, rt_base_t pin) +{ + u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin); + u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin); + u32 pin_id = FGPIO_OPS_PIN_ID(pin); + FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id]; + + if (pin_instance == RT_NULL) + { + rt_kprintf("Pin %d-%c-%d not set mode\n", + ctrl_id, + port_id == 0 ? 'a' : 'b', + pin_id); + return RT_ERROR; + } + return FGpioGetInputValue(pin_instance) == FGPIO_PIN_HIGH ? PIN_HIGH : PIN_LOW; +} + +rt_err_t drv_pin_attach_irq(struct rt_device *device, rt_base_t pin, + rt_uint8_t mode, void (*hdr)(void *args), void *args) +{ + u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin); + u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin); + u32 pin_id = FGPIO_OPS_PIN_ID(pin); + rt_base_t level; + FGpio *instance = &gpio[ctrl_id].ctrl; + FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id]; + FGpioOpsPinConfig *pin_config = &gpio[ctrl_id].pin_config[port_id][pin_id]; + + level = rt_hw_interrupt_disable(); + + pin_config->irq_handler = (FGpioOpsIrqHandler)hdr; + pin_config->irq_args = args; + + if (pin_instance == RT_NULL) + { + LOG_E("GPIO%d-%c-%d not init yet.\n", ctrl_id, port_id == 0 ? 'a' : 'b', pin_id); + return RT_ERROR; + } + + if (pin_config->en_irq) + { + FGpioSetInterruptMask(pin_instance, FALSE); + FGpioPinId pin_of_ctrl = + { + .ctrl = ctrl_id, + .port = FGPIO_PORT_A, + .pin = FGPIO_PIN_0 + }; + + if (FGPIO_IRQ_BY_CONTROLLER == FGpioGetPinIrqSourceType(pin_of_ctrl)) /* setup for ctrl report interrupt */ + { + FGpioOpsSetupCtrlIRQ(instance); + LOG_I("GPIO-%d report irq by controller", ctrl_id); + } + else if (FGPIO_IRQ_BY_PIN == FGpioGetPinIrqSourceType(pin_of_ctrl)) + { + FGpioOpsSetupPinIRQ(instance, pin_instance, pin_config); + LOG_I("GPIO-%d report irq by pin", ctrl_id); + } + + switch (mode) + { + case PIN_IRQ_MODE_RISING: + pin_config->irq_type = FGPIO_IRQ_TYPE_EDGE_RISING; + break; + case PIN_IRQ_MODE_FALLING: + pin_config->irq_type = FGPIO_IRQ_TYPE_EDGE_FALLING; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + pin_config->irq_type = FGPIO_IRQ_TYPE_LEVEL_LOW; + break; + case PIN_IRQ_MODE_HIGH_LEVEL: + pin_config->irq_type = FGPIO_IRQ_TYPE_LEVEL_HIGH; + break; + default: + LOG_E("Do not spport irq_mode: %d\n", mode); + break; + } + FGpioSetInterruptType(pin_instance, pin_config->irq_type); + FGpioRegisterInterruptCB(pin_instance, pin_config->irq_handler, + pin_config->irq_args, TRUE); /* register intr callback */ + } + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t drv_pin_detach_irq(struct rt_device *device, rt_base_t pin) +{ + u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin); + u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin); + u32 pin_id = FGPIO_OPS_PIN_ID(pin); + rt_base_t level; + FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id]; + FGpioOpsPinConfig *pin_config = &gpio[ctrl_id].pin_config[port_id][pin_id]; + + if (pin_instance == RT_NULL) + { + rt_kprintf("pin %d-%c-%d not set mode\n", + ctrl_id, + port_id == 0 ? 'a' : 'b', + pin_id); + return RT_ERROR; + } + + level = rt_hw_interrupt_disable(); + pin_config->irq_handler = RT_NULL; + pin_config->irq_args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +rt_err_t drv_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled) +{ + u32 ctrl_id = FGPIO_OPS_PIN_CTRL_ID(pin); + u32 port_id = FGPIO_OPS_PIN_PORT_ID(pin); + u32 pin_id = FGPIO_OPS_PIN_ID(pin); + FGpioPin *pin_instance = &gpio[ctrl_id].pins[port_id][pin_id]; + + if (pin_instance == RT_NULL) + { + rt_kprintf("Pin %d-%c-%d not set mode\n", + ctrl_id, + port_id == 0 ? 'a' : 'b', + pin_id); + return RT_ERROR; + } + + FGpioSetInterruptMask(pin_instance, enabled); + + return RT_EOK; +} + +const struct rt_pin_ops drv_pin_ops = +{ + .pin_mode = drv_pin_mode, + .pin_write = drv_pin_write, + .pin_read = drv_pin_read, + + .pin_attach_irq = drv_pin_attach_irq, + .pin_detach_irq = drv_pin_detach_irq, + .pin_irq_enable = drv_pin_irq_enable, + .pin_get = RT_NULL +}; + +int ft_pin_init(void) +{ + rt_err_t ret = RT_EOK; + ret = rt_device_pin_register("pin", &drv_pin_ops, RT_NULL); + rt_kprintf("Register pin with return: %d\n", ret); + return ret; +} +INIT_DEVICE_EXPORT(ft_pin_init); +#endif /* RT_USING_PIN */ \ No newline at end of file diff --git a/bsp/phytium/libraries/drivers/drv_gpio.h b/bsp/phytium/libraries/drivers/drv_gpio.h new file mode 100644 index 00000000000..769a689af02 --- /dev/null +++ b/bsp/phytium/libraries/drivers/drv_gpio.h @@ -0,0 +1,20 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Email: opensource_embedded@phytium.com.cn + * + * Change Logs: + * Date Author Notes + * 2023/7/24 liqiaozhong first add, support intr + * + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +/**************************** Type Definitions *******************************/ + +/************************** Function Prototypes ******************************/ +#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/drivers/drv_qspi.c b/bsp/phytium/libraries/drivers/drv_qspi.c index bdd76a2eb1c..a4af85a51a5 100644 --- a/bsp/phytium/libraries/drivers/drv_qspi.c +++ b/bsp/phytium/libraries/drivers/drv_qspi.c @@ -10,72 +10,72 @@ * 2023-03-20 zhangyan first version * */ - -#include "drv_qspi.h" -#include "sdkconfig.h" +#include "rtconfig.h" #ifdef RT_USING_QSPI #include #include "rtdevice.h" +#include "drv_qspi.h" #include "fqspi_flash.h" -#include "fdebug.h" -#include "fpinctrl.h" - -#define FQSPI_DEBUG_TAG "FQSPI" -#define FQSPI_ERROR(format, ...) FT_DEBUG_PRINT_E(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__) -#define FQSPI_WARN(format, ...) FT_DEBUG_PRINT_W(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__) -#define FQSPI_INFO(format, ...) FT_DEBUG_PRINT_I(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__) -#define FQSPI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FQSPI_DEBUG_TAG, format, ##__VA_ARGS__) +#include "rtdbg.h" +#include "fiopad.h" #define DAT_LENGTH 128 -struct phytium_qspi_bus + +static phytium_qspi_bus phytium_qspi = { - char *name; - rt_uint32_t init; /* 0 is init already */ - FQspiCtrl fqspi; - struct rt_spi_bus qspi_bus; + .fqspi_id = FQSPI0_ID, }; -static struct phytium_qspi_bus phytium_qspi; /* phytium qspi bus handle */ static struct rt_qspi_device *qspi_device; /* phytium device bus handle */ static char qspi_bus_name[RT_NAME_MAX] = "QSPIBUS"; static char qspi_dev_name[RT_NAME_MAX] = "QSPIDEV"; +extern FIOPadCtrl iopad_ctrl; -rt_err_t FQspiInit(FQspiCtrl *fqspi) +rt_err_t FQspiInit(phytium_qspi_bus *phytium_qspi_bus) { - u32 qspi_id = FQSPI0_ID; FError ret = FT_SUCCESS; + rt_uint32_t qspi_id = phytium_qspi_bus->fqspi_id; + +#ifdef USING_QSPI_CHANNEL0 + FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR51_REG0_OFFSET, FIOPAD_FUNC0); + FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR45_REG0_OFFSET, FIOPAD_FUNC0); +#endif -#if defined(CONFIG_TARGET_E2000) - FIOPadSetQspiMux(qspi_id, FQSPI_CS_0); - FIOPadSetQspiMux(qspi_id, FQSPI_CS_1); +#ifdef USING_QSPI_CHANNEL1 + FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR55_REG0_OFFSET, FIOPAD_FUNC0); + FIOPadSetFunc(&iopad_ctrl, FIOPAD_AR49_REG0_OFFSET, FIOPAD_FUNC0); #endif - FQspiDeInitialize(fqspi); + FQspiDeInitialize(&(phytium_qspi_bus->fqspi)); FQspiConfig pconfig = *FQspiLookupConfig(qspi_id); +#ifdef RT_USING_SMART + pconfig.base_addr = (uintptr)rt_ioremap((void *)pconfig.base_addr, 0x1000); +#endif + /* Norflash init, include reset and read flash_size */ - ret = FQspiCfgInitialize(fqspi, &pconfig); + ret = FQspiCfgInitialize(&(phytium_qspi_bus->fqspi), &pconfig); if (FT_SUCCESS != ret) { - FQSPI_DEBUG("Qspi init failed.\n"); + LOG_E("Qspi init failed.\n"); return RT_ERROR; } else { - FQSPI_DEBUG("Qspi init successfully.\n"); + rt_kprintf("Qspi init successfully.\n"); } /* Detect connected flash infomation */ - ret = FQspiFlashDetect(fqspi); + ret = FQspiFlashDetect(&(phytium_qspi_bus->fqspi)); if (FT_SUCCESS != ret) { - FQSPI_DEBUG("Qspi flash detect failed.\n"); + LOG_E("Qspi flash detect failed.\n"); return RT_ERROR; } else { - FQSPI_DEBUG("Qspi flash detect successfully.\n"); + rt_kprintf("Qspi flash detect successfully.\n"); } return RT_EOK; @@ -85,15 +85,15 @@ static rt_err_t phytium_qspi_configure(struct rt_spi_device *device, struct rt_s { RT_ASSERT(device != RT_NULL); RT_ASSERT(configuration != RT_NULL); - struct phytium_qspi_bus *qspi_bus; + phytium_qspi_bus *qspi_bus; qspi_bus = (struct phytium_qspi_bus *) device->bus->parent.user_data; rt_err_t ret = RT_EOK; - ret = FQspiInit(&(qspi_bus->fqspi)); + ret = FQspiInit(qspi_bus); if (RT_EOK != ret) { qspi_bus->init = RT_FALSE; - FQSPI_DEBUG("Qspi init failed!!!\n"); + rt_kprintf("Qspi init failed!!!\n"); return RT_ERROR; } qspi_bus->init = RT_EOK; @@ -105,38 +105,47 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi { RT_ASSERT(device != RT_NULL); RT_ASSERT(message != RT_NULL); - struct phytium_qspi_bus *qspi_bus; + phytium_qspi_bus *qspi_bus; struct rt_qspi_message *qspi_message = (struct rt_qspi_message *)message; rt_uint32_t cmd = qspi_message->instruction.content; rt_uint32_t flash_addr = qspi_message->address.content; + rt_uint8_t *rcvb = message->recv_buf; rt_uint8_t *sndb = message->send_buf; FError ret = FT_SUCCESS; qspi_bus = (struct phytium_qspi_bus *) device->bus->parent.user_data; +#ifdef USING_QSPI_CHANNEL0 + qspi_bus->fqspi.config.channel = 0; +#endif +#ifdef USING_QSPI_CHANNEL1 + qspi_bus->fqspi.config.channel = 1; +#endif + uintptr addr = qspi_bus->fqspi.config.mem_start + qspi_bus->fqspi.config.channel * qspi_bus->fqspi.flash_size + flash_addr; + +#ifdef RT_USING_SMART + addr = (uintptr)rt_ioremap((void *)addr, 0x2000); +#endif /*Distinguish the write mode according to different commands*/ - if (cmd == FQSPI_FLASH_CMD_PP||cmd == FQSPI_FLASH_CMD_QPP||cmd ==FQSPI_FLASH_CMD_4PP||cmd ==FQSPI_FLASH_CMD_4QPP ) + if (cmd == FQSPI_FLASH_CMD_PP || cmd == FQSPI_FLASH_CMD_QPP || cmd == FQSPI_FLASH_CMD_4PP || cmd == FQSPI_FLASH_CMD_4QPP) { - char *strs = (char *)message->send_buf; - rt_uint8_t len = strlen(strs) + 1; rt_uint8_t *wr_buf = NULL; wr_buf = (rt_uint8_t *)rt_malloc(DAT_LENGTH * sizeof(rt_uint8_t)); - - rt_memcpy(wr_buf, strs, len); - message->length = len; + rt_uint8_t len = message->length; + rt_memcpy(wr_buf, (char *)message->send_buf, len); ret = FQspiFlashErase(&(qspi_bus->fqspi), FQSPI_FLASH_CMD_SE, flash_addr); if (FT_SUCCESS != ret) { - FQSPI_DEBUG("Failed to erase mem, test result 0x%x.\r\n", ret); + LOG_E("Failed to erase mem, test result 0x%x.\r\n", ret); return RT_ERROR; } /* write norflash data */ - ret = FQspiFlashWriteData(&(qspi_bus->fqspi), cmd, flash_addr, wr_buf, len); + ret = FQspiFlashWriteData(&(qspi_bus->fqspi), cmd, addr, wr_buf, len); if (FT_SUCCESS != ret) { - FQSPI_DEBUG("Failed to write mem, test result 0x%x.\r\n", ret); + LOG_E("Failed to write mem, test result 0x%x.\r\n", ret); return RT_ERROR; } else @@ -149,8 +158,8 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi } /*Distinguish the read mode according to different commands*/ - if (cmd == FQSPI_FLASH_CMD_READ||cmd == FQSPI_FLASH_CMD_4READ||cmd == FQSPI_FLASH_CMD_FAST_READ||cmd == FQSPI_FLASH_CMD_4FAST_READ|| - cmd == FQSPI_FLASH_CMD_DUAL_READ||cmd == FQSPI_FLASH_CMD_QIOR||cmd == FQSPI_FLASH_CMD_4QIOR) + if (cmd == FQSPI_FLASH_CMD_READ || cmd == FQSPI_FLASH_CMD_4READ || cmd == FQSPI_FLASH_CMD_FAST_READ || cmd == FQSPI_FLASH_CMD_4FAST_READ || + cmd == FQSPI_FLASH_CMD_DUAL_READ || cmd == FQSPI_FLASH_CMD_QIOR || cmd == FQSPI_FLASH_CMD_4QIOR) { rt_uint8_t *rd_buf = NULL; rd_buf = (rt_uint8_t *)rt_malloc(DAT_LENGTH * sizeof(rt_uint8_t)); @@ -159,15 +168,15 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi if (FT_SUCCESS != ret) { - FQSPI_DEBUG("Failed to config read, test result 0x%x.\r\n", ret); + rt_kprintf("Failed to config read, test result 0x%x.\r\n", ret); return RT_ERROR; } /* read norflash data */ - size_t read_len = FQspiFlashReadData(&(qspi_bus->fqspi), flash_addr, rd_buf, DAT_LENGTH); + size_t read_len = FQspiFlashReadData(&(qspi_bus->fqspi), addr, rd_buf, DAT_LENGTH); message->length = read_len; if (read_len != DAT_LENGTH) { - FQSPI_DEBUG("Failed to read mem, read len = %d.\r\n", read_len); + rt_kprintf("Failed to read mem, read len = %d.\r\n", read_len); return RT_ERROR; } else @@ -176,19 +185,19 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi message->recv_buf = rd_buf; rt_free(rd_buf); } - FtDumpHexByte(message->recv_buf, DAT_LENGTH); + FtDumpHexByte(message->recv_buf, read_len); - return RT_EOK; + return RT_EOK; } if (rcvb) { - if (cmd == FQSPI_FLASH_CMD_RDID||cmd == FQSPI_FLASH_CMD_RDSR1||cmd == FQSPI_FLASH_CMD_RDSR2 ||cmd == FQSPI_FLASH_CMD_RDSR3) + if (cmd == FQSPI_FLASH_CMD_RDID || cmd == FQSPI_FLASH_CMD_RDSR1 || cmd == FQSPI_FLASH_CMD_RDSR2 || cmd == FQSPI_FLASH_CMD_RDSR3) { ret |= FQspiFlashSpecialInstruction(&(qspi_bus->fqspi), cmd, rcvb, sizeof(rcvb)); if (FT_SUCCESS != ret) { - FQSPI_DEBUG("Failed to read flash information.\n"); + LOG_E("Failed to read flash information.\n"); return RT_ERROR; } } @@ -201,14 +210,14 @@ static rt_uint32_t phytium_qspi_xfer(struct rt_spi_device *device, struct rt_spi ret |= FQspiFlashEnableWrite(&(qspi_bus->fqspi)); if (FT_SUCCESS != ret) { - FQSPI_DEBUG("Failed to enable flash reg write.\n"); + LOG_E("Failed to enable flash reg write.\n"); return RT_ERROR; } ret |= FQspiFlashWriteReg(&(qspi_bus->fqspi), cmd, sndb, 1); if (FT_SUCCESS != ret) { - FQSPI_DEBUG("Failed to write flash reg.\n"); + LOG_E("Failed to write flash reg.\n"); return RT_ERROR; } @@ -232,7 +241,7 @@ rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device qspi_device = (struct rt_qspi_device *)rt_malloc(sizeof(struct rt_qspi_device)); if (qspi_device == RT_NULL) { - FQSPI_DEBUG("Qspi bus attach device failed."); + LOG_E("Qspi bus attach device failed."); result = RT_ENOMEM; goto __exit; } @@ -247,23 +256,23 @@ rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device } - return result; -} + return result; + } } int rt_hw_qspi_init(void) { - int i = 0; int result = RT_EOK; + phytium_qspi.qspi_bus.parent.user_data = &phytium_qspi; - if(rt_qspi_bus_register(&phytium_qspi.qspi_bus, qspi_bus_name , &phytium_qspi_ops) == RT_EOK) + if (rt_qspi_bus_register(&phytium_qspi.qspi_bus, qspi_bus_name, &phytium_qspi_ops) == RT_EOK) { rt_kprintf("Qspi bus register successfully!!!\n"); } else { - FQSPI_DEBUG("Qspi bus register Failed!!!\n"); + LOG_E("Qspi bus register Failed!!!\n"); result = -RT_ERROR; } @@ -288,16 +297,17 @@ rt_err_t qspi_init() /*read cmd example message improvement*/ void ReadCmd(struct rt_spi_message *spi_message) { - struct rt_qspi_message *message = (struct rt_qspi_message*) spi_message; + struct rt_qspi_message *message = (struct rt_qspi_message *) spi_message; message->address.content = 0x360000 ;/*Flash address*/ message->instruction.content = 0x03 ;/*read cmd*/ + rt_qspi_transfer_message(qspi_device, message); } /*write cmd example message improvement*/ void WriteCmd(struct rt_spi_message *spi_message) { - struct rt_qspi_message *message = (struct rt_qspi_message*) spi_message; + struct rt_qspi_message *message = (struct rt_qspi_message *) spi_message; message->address.content = 0x360000 ;/*Flash address*/ message->instruction.content = 0x02 ;/*write cmd*/ rt_qspi_transfer_message(qspi_device, message); @@ -310,24 +320,27 @@ void qspi_thread(void *parameter) qspi_init(); /*Read and write flash chip fixed area repeatedly*/ - write_message.send_buf = "111111111111111111111111"; + write_message.send_buf = "phytium"; + write_message.length = strlen((char *)write_message.send_buf) + 1; WriteCmd(&write_message); ReadCmd(&read_message); - write_message.send_buf = "222222222222222222222222"; + write_message.send_buf = "phytium hello world!"; + write_message.length = strlen((char *)write_message.send_buf) + 1; WriteCmd(&write_message); ReadCmd(&read_message); - write_message.send_buf = "333333333333333333333333"; + write_message.send_buf = "Welcome to phytium chip"; + write_message.length = strlen((char *)write_message.send_buf) + 1; WriteCmd(&write_message); ReadCmd(&read_message); rt_uint8_t recv; rt_uint8_t cmd = 0x9F;/*read the flash status reg2*/ res = rt_qspi_send_then_recv(qspi_device, &cmd, sizeof(cmd), &recv, sizeof(recv)); - RT_ASSERT(res!=RT_EOK); + RT_ASSERT(res != RT_EOK); - rt_kprintf("The status reg = %x \n" ,recv); + rt_kprintf("The status reg = %x \n", recv); return 0; } @@ -336,13 +349,13 @@ rt_err_t qspi_sample(int argc, char *argv[]) { rt_thread_t thread; rt_err_t res; - thread = rt_thread_create("qspi_thread", qspi_thread, RT_NULL, 1024, 25, 10); + thread = rt_thread_create("qspi_thread", qspi_thread, RT_NULL, 2048, 25, 10); res = rt_thread_startup(thread); - RT_ASSERT(res==RT_EOK); + RT_ASSERT(res == RT_EOK); return res; - } /* Enter qspi_sample command for testing */ MSH_CMD_EXPORT(qspi_sample, qspi sample); #endif + diff --git a/bsp/phytium/libraries/drivers/drv_qspi.h b/bsp/phytium/libraries/drivers/drv_qspi.h index 32af7f34bb5..c92b884b7f1 100644 --- a/bsp/phytium/libraries/drivers/drv_qspi.h +++ b/bsp/phytium/libraries/drivers/drv_qspi.h @@ -14,8 +14,12 @@ #ifndef __DRT_QSPI_H__ #define __DRT_QSPI_H__ -#include +#include "rtconfig.h" + #ifdef RT_USING_QSPI +#include +#include "rtdevice.h" +#include "fqspi_flash.h" #define PHYTIUM_QSPI_NAME "qspi" #ifdef __cplusplus @@ -23,6 +27,14 @@ extern "C" { #endif +typedef struct +{ + rt_uint32_t fqspi_id; + rt_uint32_t init; /* 0 is init already */ + FQspiCtrl fqspi; + struct rt_spi_bus qspi_bus; +} phytium_qspi_bus; + rt_err_t phytium_qspi_bus_attach_device(const char *bus_name, const char *device_name); #ifdef __cplusplus diff --git a/bsp/phytium/libraries/drivers/drv_sdio.c b/bsp/phytium/libraries/drivers/drv_sdio.c new file mode 100644 index 00000000000..95318c2a340 --- /dev/null +++ b/bsp/phytium/libraries/drivers/drv_sdio.c @@ -0,0 +1,393 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Email: opensource_embedded@phytium.com.cn + * + * Change Logs: + * Date Author Notes + * 2023/7/11 liqiaozhong init SD card and mount file system + */ + +/***************************** Include Files *********************************/ +#include +#include + +#ifdef BSP_USING_SDIO +#include +#include +#include + +#ifdef RT_USING_SMART + #include "ioremap.h" +#endif +#include "mm_aspace.h" + +#include "ftypes.h" +#if defined(TARGET_E2000) + #include "fparameters.h" +#endif +#include "fparameters_comm.h" + +#include "fsdio.h" +#include "fsdio_hw.h" + +#include "drv_sdio.h" +/************************** Constant Definitions *****************************/ +#ifdef USING_SDIO0 + #define SDIO_CONTROLLER_ID FSDIO0_ID +#elif defined (USING_SDIO1) + #define SDIO_CONTROLLER_ID FSDIO1_ID +#elif defined (USING_EMMC) + #define SDIO_CONTROLLER_ID FSDIO0_ID +#endif +#define SDIO_TF_CARD_HOST_ID 0x1 +#define SDIO_MALLOC_CAP_DESC 256U +#define SDIO_DMA_ALIGN 512U +#define SDIO_DMA_BLK_SZ 512U +#define SDIO_VALID_OCR 0x00FFFF80 /* supported voltage range is 1.65v-3.6v (VDD_165_195-VDD_35_36) */ +#define SDIO_MAX_BLK_TRANS 20U +/**************************** Type Definitions *******************************/ +typedef struct +{ + FSdio *mmcsd_instance; + FSdioIDmaDesc *rw_desc; + rt_err_t (*transfer)(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req, FSdioCmdData *cmd_data_p); +} mmcsd_info_t; +/************************** Variable Definitions *****************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*******************************Api Functions*********************************/ +static void fsdio_host_relax(void) +{ + rt_thread_mdelay(1); +} + +static rt_err_t fsdio_ctrl_init(struct rt_mmcsd_host *host) +{ + mmcsd_info_t *private_data_t = (mmcsd_info_t *)host->private_data; + FSdio *mmcsd_instance = RT_NULL; + const FSdioConfig *default_mmcsd_config = RT_NULL; + FSdioConfig mmcsd_config; + FSdioIDmaDesc *rw_desc = RT_NULL; + + mmcsd_instance = rt_malloc(sizeof(FSdio)); + if (!mmcsd_instance) + { + LOG_E("Malloc mmcsd_instance failed"); + return RT_ERROR; + } + + rw_desc = rt_malloc_align(SDIO_MAX_BLK_TRANS * sizeof(FSdioIDmaDesc), SDIO_MALLOC_CAP_DESC); + if (!rw_desc) + { + LOG_E("Malloc rw_desc failed"); + return RT_ERROR; + } + + rt_memset(mmcsd_instance, 0, sizeof(FSdio)); + rt_memset(rw_desc, 0, SDIO_MAX_BLK_TRANS * sizeof(FSdioIDmaDesc)); + + /* SDIO controller init */ + RT_ASSERT((default_mmcsd_config = FSdioLookupConfig(SDIO_CONTROLLER_ID)) != RT_NULL); + mmcsd_config = *default_mmcsd_config; /* load default config */ +#ifdef RT_USING_SMART + mmcsd_config.base_addr = (uintptr)rt_ioremap((void *)mmcsd_config.base_addr, 0x1000); +#endif + mmcsd_config.trans_mode = FSDIO_IDMA_TRANS_MODE; +#ifdef USING_EMMC + mmcsd_config.non_removable = TRUE; /* eMMC is unremovable on board */ +#else + mmcsd_config.non_removable = FALSE; /* TF card is removable on board */ +#endif + + + if (FSDIO_SUCCESS != FSdioCfgInitialize(mmcsd_instance, &mmcsd_config)) + { + LOG_E("SDIO controller init failed."); + return RT_ERROR; + } + + if (FSDIO_SUCCESS != FSdioSetIDMAList(mmcsd_instance, rw_desc, SDIO_MAX_BLK_TRANS)) + { + LOG_E("SDIO controller setup DMA failed."); + return RT_ERROR; + } + mmcsd_instance->desc_list.first_desc_p = (uintptr)rw_desc + PV_OFFSET; + + FSdioRegisterRelaxHandler(mmcsd_instance, fsdio_host_relax); /* SDIO delay for a while */ + + private_data_t->mmcsd_instance = mmcsd_instance; + private_data_t->rw_desc = rw_desc; + + rt_kprintf("SDIO controller init success!\r\n"); + return RT_EOK; +} + +rt_inline rt_err_t sdio_dma_transfer(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req, FSdioCmdData *req_cmd) +{ + FError ret = FT_SUCCESS; + mmcsd_info_t *private_data_t = (mmcsd_info_t *)host->private_data; + FSdio *mmcsd_instance = private_data_t->mmcsd_instance; + + ret = FSdioDMATransfer(mmcsd_instance, req_cmd); + if (ret != FT_SUCCESS) + { + LOG_E("FSdioDMATransfer() fail."); + return -RT_ERROR; + } + + ret = FSdioPollWaitDMAEnd(mmcsd_instance, req_cmd); + if (ret != FT_SUCCESS) + { + LOG_E("FSdioPollWaitDMAEnd() fail."); + return -RT_ERROR; + } + + if (resp_type(req->cmd) & RESP_MASK) + { + if (resp_type(req->cmd) == RESP_R2) + { + req->cmd->resp[3] = req_cmd->response[0]; + req->cmd->resp[2] = req_cmd->response[1]; + req->cmd->resp[1] = req_cmd->response[2]; + req->cmd->resp[0] = req_cmd->response[3]; + } + else + { + req->cmd->resp[0] = req_cmd->response[0]; + } + } + + return RT_EOK; +} + +static void mmc_request_send(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req) +{ + /* ignore some SDIO-ONIY cmd */ + if ((req->cmd->cmd_code == SD_IO_SEND_OP_COND) || (req->cmd->cmd_code == SD_IO_RW_DIRECT)) + { + req->cmd->err = -1; + goto skip_cmd; + } + + mmcsd_info_t *private_data_t = (mmcsd_info_t *)host->private_data; + FSdioCmdData req_cmd; + FSdioCmdData req_stop; + FSdioData req_data; + rt_uint32_t *data_buf_aligned = RT_NULL; + rt_uint32_t cmd_flag = resp_type(req->cmd); + + rt_memset(&req_cmd, 0, sizeof(FSdioCmdData)); + rt_memset(&req_stop, 0, sizeof(FSdioCmdData)); + rt_memset(&req_data, 0, sizeof(FSdioData)); + + /* convert req into ft driver type */ + if (req->cmd->cmd_code == GO_IDLE_STATE) + { + req_cmd.flag |= FSDIO_CMD_FLAG_NEED_INIT; + } + + if (req->cmd->cmd_code == GO_INACTIVE_STATE) + { + req_cmd.flag |= FSDIO_CMD_FLAG_NEED_AUTO_STOP; + } + + if ((cmd_flag != RESP_R3) && (cmd_flag != RESP_R4) && (cmd_flag != RESP_NONE)) + { + req_cmd.flag |= FSDIO_CMD_FLAG_NEED_RESP_CRC; + } + + if (cmd_flag & RESP_MASK) + { + req_cmd.flag |= FSDIO_CMD_FLAG_EXP_RESP; + + if (cmd_flag == RESP_R2) + { + req_cmd.flag |= FSDIO_CMD_FLAG_EXP_LONG_RESP; + } + } + + if (req->data) /* transfer command with data */ + { + data_buf_aligned = rt_malloc_align(SDIO_DMA_BLK_SZ * req->data->blks, SDIO_DMA_ALIGN); + if (!data_buf_aligned) + { + LOG_E("Malloc data_buf_aligned failed"); + return; + } + rt_memset(data_buf_aligned, 0, SDIO_DMA_BLK_SZ * req->data->blks); + + req_cmd.flag |= FSDIO_CMD_FLAG_EXP_DATA; + + req_data.blksz = req->data->blksize; + req_data.blkcnt = req->data->blks; + req_data.datalen = req->data->blksize * req->data->blks; + if ((uintptr)req->data->buf % SDIO_DMA_ALIGN) /* data buffer should be 512-aligned */ + { + if (req->data->flags & DATA_DIR_WRITE) + { + rt_memcpy((void *)data_buf_aligned, (void *)req->data->buf, req_data.datalen); + } + req_data.buf = (rt_uint8_t *)data_buf_aligned; + req_data.buf_p = (uintptr)data_buf_aligned + PV_OFFSET; + } + else + { + req_data.buf = (rt_uint8_t *)req->data->buf; + req_data.buf_p = (uintptr)req->data->buf + PV_OFFSET; + } + req_cmd.data_p = &req_data; + + if (req->data->flags & DATA_DIR_READ) + { + req_cmd.flag |= FSDIO_CMD_FLAG_READ_DATA; + } + else if (req->data->flags & DATA_DIR_WRITE) + { + req_cmd.flag |= FSDIO_CMD_FLAG_WRITE_DATA; + } + } + + req_cmd.cmdidx = req->cmd->cmd_code; + req_cmd.cmdarg = req->cmd->arg; + + /* do cmd and data transfer */ + req->cmd->err = (private_data_t->transfer)(host, req, &req_cmd); + if (req->cmd->err != RT_EOK) + { + LOG_E("transfer failed in %s", __func__); + } + + if (req->data && (req->data->flags & DATA_DIR_READ)) + { + if ((uintptr)req->data->buf % SDIO_DMA_ALIGN) /* data buffer should be 512-aligned */ + { + rt_memcpy((void *)req->data->buf, (void *)data_buf_aligned, req_data.datalen); + } + } + + /* stop cmd */ + if (req->stop) + { + req_stop.cmdidx = req->stop->cmd_code; + req_stop.cmdarg = req->stop->arg; + if (req->stop->flags & RESP_MASK) + { + req_stop.flag |= FSDIO_CMD_FLAG_READ_DATA; + if (resp_type(req->stop) == RESP_R2) + req_stop.flag |= FSDIO_CMD_FLAG_EXP_LONG_RESP; + } + req->stop->err = (private_data_t->transfer)(host, req, &req_stop); + } + + if (data_buf_aligned) + rt_free_align(data_buf_aligned); + +skip_cmd: + mmcsd_req_complete(host); +} + +static void mmc_set_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg) +{ + FError ret = FT_SUCCESS; + mmcsd_info_t *private_data_t = (mmcsd_info_t *)host->private_data; + FSdio *mmcsd_instance = private_data_t->mmcsd_instance; + uintptr base_addr = mmcsd_instance->config.base_addr; + + if (0 != io_cfg->clock) + { + ret = FSdioSetClkFreq(mmcsd_instance, io_cfg->clock); + if (ret != FT_SUCCESS) + { + LOG_E("FSdioSetClkFreq fail."); + } + } + + switch (io_cfg->bus_width) + { + case MMCSD_BUS_WIDTH_1: + FSdioSetBusWidth(base_addr, 1U); + break; + case MMCSD_BUS_WIDTH_4: + FSdioSetBusWidth(base_addr, 4U); + break; + case MMCSD_BUS_WIDTH_8: + FSdioSetBusWidth(base_addr, 8U); + break; + default: + LOG_E("Invalid bus width %d", io_cfg->bus_width); + break; + } +} + +static const struct rt_mmcsd_host_ops ops = +{ + mmc_request_send, + mmc_set_iocfg, + RT_NULL, + RT_NULL, + RT_NULL, +}; + +int ft_mmcsd_init(void) +{ + /* variables init */ + struct rt_mmcsd_host *host = RT_NULL; + mmcsd_info_t *private_data = RT_NULL; + + host = mmcsd_alloc_host(); + if (!host) + { + LOG_E("Alloc host failed"); + goto err_free; + } + + private_data = rt_malloc(sizeof(mmcsd_info_t)); + if (!private_data) + { + LOG_E("Malloc private_data failed"); + goto err_free; + } + + rt_memset(private_data, 0, sizeof(mmcsd_info_t)); + private_data->transfer = sdio_dma_transfer; + + /* host data init */ + host->ops = &ops; + host->freq_min = 400000; + host->freq_max = 50000000; + host->valid_ocr = SDIO_VALID_OCR; /* the voltage range supported is 1.65v-3.6v */ + host->flags = MMCSD_MUTBLKWRITE | MMCSD_BUSWIDTH_4; + host->max_seg_size = SDIO_DMA_BLK_SZ; /* used in block_dev.c */ + host->max_dma_segs = SDIO_MAX_BLK_TRANS; /* physical segment number */ + host->max_blk_size = SDIO_DMA_BLK_SZ; /* all the 4 para limits size of one blk tran */ + host->max_blk_count = SDIO_MAX_BLK_TRANS; + host->private_data = private_data; + + if (RT_EOK != fsdio_ctrl_init(host)) + { + LOG_E("fsdio_ctrl_init() failed"); + goto err_free; + } + + mmcsd_change(host); + + return RT_EOK; + +err_free: + if (host) + rt_free(host); + if (private_data->mmcsd_instance) + rt_free(private_data->mmcsd_instance); + if (private_data->rw_desc) + rt_free_align(private_data->rw_desc); + if (private_data) + rt_free(private_data); + + return -RT_EOK; +} +INIT_DEVICE_EXPORT(ft_mmcsd_init); +#endif // #ifdef RT_USING_SDIO \ No newline at end of file diff --git a/bsp/phytium/libraries/drivers/drv_sdio.h b/bsp/phytium/libraries/drivers/drv_sdio.h new file mode 100644 index 00000000000..c1fbf333836 --- /dev/null +++ b/bsp/phytium/libraries/drivers/drv_sdio.h @@ -0,0 +1,28 @@ +/* + * Copyright (c) 2006-2023, RT-Thread Development Team + * + * SPDX-License-Identifier: Apache-2.0 + * + * Email: opensource_embedded@phytium.com.cn + * + * Change Logs: + * Date Author Notes + * 2023/7/11 liqiaozhong init SD card and mount file system + * + */ + +#ifndef __DRV_SDIO_H__ +#define __DRV_SDIO_H__ +/***************************** Include Files *********************************/ +#include +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/************************** Variable Definitions *****************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/*******************************Api Functions*********************************/ + +#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/drivers/drv_spi.c b/bsp/phytium/libraries/drivers/drv_spi.c index f7d537256d0..2b1d2130b83 100644 --- a/bsp/phytium/libraries/drivers/drv_spi.c +++ b/bsp/phytium/libraries/drivers/drv_spi.c @@ -116,6 +116,9 @@ static rt_err_t spim_configure(struct rt_spi_device *device, RT_ASSERT(configuration != RT_NULL); struct drv_spi *user_data_cfg = device->parent.user_data; FSpimConfig input_cfg = *FSpimLookupConfig(user_data_cfg->spi_id); +#ifdef RT_USING_SMART + input_cfg.base_addr = (uintptr)rt_ioremap((void*)input_cfg.base_addr, 0x1000); +#endif FSpimConfig *set_input_cfg = &input_cfg; /* set fspim device according to configuration */ diff --git a/bsp/phytium/libraries/drivers/drv_xmac.c b/bsp/phytium/libraries/drivers/drv_xmac.c index 61f5dbfb400..f8207ee7301 100644 --- a/bsp/phytium/libraries/drivers/drv_xmac.c +++ b/bsp/phytium/libraries/drivers/drv_xmac.c @@ -1,22 +1,1651 @@ /* - * @Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. + * Copyright (c) 2006-2023, RT-Thread Development Team * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. + * SPDX-License-Identifier: Apache-2.0 * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. + * Email: opensource_embedded@phytium.com.cn * - * - * @FilePath: drv_xmac.c - * @Date: 2023-04-19 15:19:29 - * @LastEditTime: 2023-04-19 15:19:29 - * @Description: This file is for - * - * @Modify History: - * Ver Who Date Changes - * ----- ------ -------- -------------------------------------- + * Change Logs: + * Date Author Notes + * 2022-07-07 liuzhihong first commit + * 2023-07-14 liuzhihong support RT-Smart + */ + +#include "board.h" + +#ifdef BSP_USING_ETH + +#include "mm_aspace.h" +#ifdef RT_USING_SMART + #include "ioremap.h" +#endif + +#ifdef __aarch64__ + #include "faarch64.h" +#else + #include "faarch32.h" +#endif + +#include "drv_xmac.h" + + +#define FXMAC_OS_XMAC_DEBUG_TAG "FXMAC_OS_XMAC" +#define FXMAC_OS_XMAC_PRINT_E(format, ...) FT_DEBUG_PRINT_E(FXMAC_OS_XMAC_DEBUG_TAG, format, ##__VA_ARGS__) +#define FXMAC_OS_XMAC_PRINT_I(format, ...) FT_DEBUG_PRINT_I(FXMAC_OS_XMAC_DEBUG_TAG, format, ##__VA_ARGS__) +#define FXMAC_OS_XMAC_PRINT_D(format, ...) FT_DEBUG_PRINT_D(FXMAC_OS_XMAC_DEBUG_TAG, format, ##__VA_ARGS__) +#define FXMAC_OS_XMAC_PRINT_W(format, ...) FT_DEBUG_PRINT_W(FXMAC_OS_XMAC_DEBUG_TAG, format, ##__VA_ARGS__) + +#define LOG_E(format, ...) FT_DEBUG_PRINT_E(FXMAC_OS_XMAC_DEBUG_TAG, format, ##__VA_ARGS__) +#define LOG_I(format, ...) FT_DEBUG_PRINT_I(FXMAC_OS_XMAC_DEBUG_TAG, format, ##__VA_ARGS__) +#define LOG_D(format, ...) FT_DEBUG_PRINT_D(FXMAC_OS_XMAC_DEBUG_TAG, format, ##__VA_ARGS__) + +#define FXMAC_BD_TO_INDEX(ringptr, bdptr) \ + (((uintptr)bdptr - (uintptr)(ringptr)->base_bd_addr) / (ringptr)->separation) + + +static char *os_drv_xmac0_name = "e0"; + +static void FXmacInitOnError(FXmacOs *instance_p); +static void FXmacSetupIsr(FXmacOs *instance_p); + +static FXmacOs fxmac_os_instace[FXMAC_NUM] = +{ + [FXMAC0_ID] = {.config = (0)}, + [FXMAC1_ID] = {.config = (0)}, + [FXMAC2_ID] = {.config = (0)}, + [FXMAC3_ID] = {.config = (0)}, +}; + +int isr_calling_flg = 0; + +/* queue */ + +void FXmacQueueInit(PqQueue *q) +{ + FASSERT(q != NULL); + q->head = q->tail = q->len = 0; +} + +int FXmacPqEnqueue(PqQueue *q, void *p) +{ + if (q->len == PQ_QUEUE_SIZE) + { + return -1; + } + + q->data[q->head] = (uintptr)p; + q->head = (q->head + 1) % PQ_QUEUE_SIZE; + q->len++; + + return 0; +} + +void *FXmacPqDequeue(PqQueue *q) +{ + int ptail; + + if (q->len == 0) + { + return NULL; + } + + ptail = q->tail; + q->tail = (q->tail + 1) % PQ_QUEUE_SIZE; + q->len--; + + return (void *)q->data[ptail]; +} + +int FXmacPqQlength(PqQueue *q) +{ + return q->len; +} + +/* dma */ + +/** + * @name: IsTxSpaceAvailable + * @msg: Get the number of free BDs in the Bdrings + * @param {ethernetif} *ethernetif_p + * @return {*} + */ +static u32 IsTxSpaceAvailable(FXmacOs *instance_p) +{ + FXmacBdRing *txring; + u32 freecnt; + FASSERT(instance_p != NULL); + + txring = &(FXMAC_GET_TXRING(instance_p->instance)); + + /* tx space is available as long as there are valid BD's */ + freecnt = FXMAC_BD_RING_GET_FREE_CNT(txring); + return freecnt; +} + +/** + * @name: FXmacProcessSentBds + * @msg: Free up memory space of pbuf on the send queue + * @return {*} + * @param {ethernetif} *ethernetif_p + * @param {FXmacBdRing} *txring + */ +void FXmacProcessSentBds(FXmacOs *instance_p, FXmacBdRing *txring) +{ + FXmacBd *txbdset; + FXmacBd *curbdpntr; + u32 n_bds; + FError status; + u32 n_pbufs_freed; + u32 bdindex; + struct pbuf *p; + u32 *temp; + + while (1) + { + /* obtain processed BD's */ + n_bds = FXmacBdRingFromHwTx(txring, FXMAX_TX_PBUFS_LENGTH, &txbdset); + if (n_bds == 0) + { + return; + } + /* free the processed BD's */ + n_pbufs_freed = n_bds; + curbdpntr = txbdset; + while (n_pbufs_freed > 0) + { + bdindex = FXMAC_BD_TO_INDEX(txring, curbdpntr); + temp = (u32 *)curbdpntr; + *temp = 0; /* Word 0 */ + temp++; + if (bdindex == (FXMAX_TX_PBUFS_LENGTH - 1)) + { + *temp = 0xC0000000; /* Word 1 ,used/Wrap – marks last descriptor in transmit buffer descriptor list.*/ + } + else + { + *temp = 0x80000000; /* Word 1 , Used – must be zero for GEM to read data to the transmit buffer.*/ + } + + + p = (struct pbuf *)instance_p->buffer.tx_pbufs_storage[bdindex]; + + if (p != NULL) + { + pbuf_free(p); + } + instance_p->buffer.tx_pbufs_storage[bdindex] = (uintptr)NULL; + curbdpntr = FXMAC_BD_RING_NEXT(txring, curbdpntr); + n_pbufs_freed--; + + } + + status = FXmacBdRingFree(txring, n_bds, txbdset); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_I("Failure while freeing in Tx Done ISR."); + } + } + return; +} + +void FXmacSendHandler(void *arg) +{ + FXmacOs *instance_p; + FXmacBdRing *txringptr; + u32 regval; + + instance_p = (FXmacOs *)arg; + txringptr = &(FXMAC_GET_TXRING(instance_p->instance)); + regval = FXMAC_READREG32(instance_p->instance.config.base_address, FXMAC_TXSR_OFFSET); + FXMAC_WRITEREG32(instance_p->instance.config.base_address, FXMAC_TXSR_OFFSET, regval); /* 清除中断状态位来停止中断 */ + + /* If Transmit done interrupt is asserted, process completed BD's */ + FXmacProcessSentBds(instance_p, txringptr); +} + +FError FXmacSgsend(FXmacOs *instance_p, struct pbuf *p) +{ + struct pbuf *q; + u32 n_pbufs; + FXmacBd *txbdset, *txbd, *last_txbd = NULL; + FXmacBd *temp_txbd; + FError status; + FXmacBdRing *txring; + u32 bdindex; + uintptr tx_payload ; + u32 max_fr_size; + + + txring = &(FXMAC_GET_TXRING(instance_p->instance)); + + /* first count the number of pbufs */ + for (q = p, n_pbufs = 0; q != NULL; q = q->next) + { + n_pbufs++; + } + + /* obtain as many BD's */ + status = FXmacBdRingAlloc(txring, n_pbufs, &txbdset); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_I("sgsend: Error allocating TxBD."); + return ERR_GENERAL; + } + + for (q = p, txbd = txbdset; q != NULL; q = q->next) + { + bdindex = FXMAC_BD_TO_INDEX(txring, txbd); + + if (instance_p->buffer.tx_pbufs_storage[bdindex]) + { + FXMAC_OS_XMAC_PRINT_I("txbd %p, txring->base_bd_addr %p", txbd, txring->base_bd_addr); + FXMAC_OS_XMAC_PRINT_I("PBUFS not available bdindex is %d ", bdindex); + FXMAC_OS_XMAC_PRINT_I("instance_p->buffer.tx_pbufs_storage[bdindex] %p ", instance_p->buffer.tx_pbufs_storage[bdindex]); + return ERR_GENERAL; + } + + /* Send the data from the pbuf to the interface, one pbuf at a + time. The size of the data in each pbuf is kept in the ->len + variable. */ + tx_payload = (uintptr)p->payload; +#ifdef RT_USING_SMART + tx_payload += PV_OFFSET; +#endif + FXMAC_BD_SET_ADDRESS_TX(txbd, (uintptr)tx_payload); + if (instance_p->config & FXMAC_OS_CONFIG_JUMBO) + { + max_fr_size = FXMAC_MAX_FRAME_SIZE_JUMBO; + } + else + { + max_fr_size = FXMAC_MAX_FRAME_SIZE; + } + + if (q->len > max_fr_size) + { + FXMAC_BD_SET_LENGTH(txbd, max_fr_size & 0x3FFF); + } + else + { + FXMAC_BD_SET_LENGTH(txbd, q->len & 0x3FFF); + } + + instance_p->buffer.tx_pbufs_storage[bdindex] = (uintptr)q; + + pbuf_ref(q); + last_txbd = txbd; + FXMAC_BD_CLEAR_LAST(txbd); + txbd = FXMAC_BD_RING_NEXT(txring, txbd); + } + FXMAC_BD_SET_LAST(last_txbd); + /* For fragmented packets, remember the 1st BD allocated for the 1st + packet fragment. The used bit for this BD should be cleared at the end + after clearing out used bits for other fragments. For packets without + just remember the allocated BD. */ + temp_txbd = txbdset; + txbd = txbdset; + txbd = FXMAC_BD_RING_NEXT(txring, txbd); + q = p->next; + for (; q != NULL; q = q->next) + { + FXMAC_BD_CLEAR_TX_USED(txbd); + + txbd = FXMAC_BD_RING_NEXT(txring, txbd); + } + FXMAC_BD_CLEAR_TX_USED(temp_txbd); + + + status = FXmacBdRingToHw(txring, n_pbufs, txbdset); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_I("sgsend: Error submitting TxBD."); + return ERR_GENERAL; + } + /* Start transmit */ + FXMAC_WRITEREG32((instance_p->instance).config.base_address, + FXMAC_NWCTRL_OFFSET, + (FXMAC_READREG32(instance_p->instance.config.base_address, + FXMAC_NWCTRL_OFFSET) | + FXMAC_NWCTRL_STARTTX_MASK)); + + return status; +} + +void SetupRxBds(FXmacOs *instance_p, FXmacBdRing *rxring) +{ + FXmacBd *rxbd; + FError status; + struct pbuf *p; + u32 freebds; + u32 bdindex; + u32 *temp; + uintptr_t pl_paddr; + freebds = FXMAC_BD_RING_GET_FREE_CNT(rxring); + while (freebds > 0) + { + freebds--; + + if (instance_p->config & FXMAC_OS_CONFIG_JUMBO) + { + p = pbuf_alloc(PBUF_RAW, FXMAC_MAX_FRAME_SIZE_JUMBO, PBUF_POOL); + } + else + { + p = pbuf_alloc(PBUF_RAW, FXMAC_MAX_FRAME_SIZE, PBUF_POOL); + } + + if (!p) + { +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + FXMAC_OS_XMAC_PRINT_I("Unable to alloc pbuf in recv_handler."); + return; + } + status = FXmacBdRingAlloc(rxring, 1, &rxbd); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_I("SetupRxBds: Error allocating RxBD."); + pbuf_free(p); + return; + } + status = FXmacBdRingToHw(rxring, 1, rxbd); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_I("Error committing RxBD to hardware: "); + if (status == FXMAC_ERR_SG_LIST) + { + FXMAC_OS_XMAC_PRINT_I("XST_DMA_SG_LIST_ERROR: this function was called out of sequence with FXmacBdRingAlloc()."); + } + else + { + FXMAC_OS_XMAC_PRINT_I("Set of BDs was rejected because the first BD did not have its start-of-packet bit set, or the last BD did not have its end-of-packet bit set, or any one of the BD set has 0 as length value."); + } + + pbuf_free(p); + FXmacBdRingUnAlloc(rxring, 1, rxbd); + return; + } + + bdindex = FXMAC_BD_TO_INDEX(rxring, rxbd); + temp = (u32 *)rxbd; + if (bdindex == (FXMAX_RX_PBUFS_LENGTH - 1)) + { + *temp = 0x00000002; + } + else + { + *temp = 0; + } + temp++; + *temp = 0; + pl_paddr = (uintptr)p->payload; +#ifdef RT_USING_SMART + pl_paddr += PV_OFFSET; +#endif + FXMAC_BD_SET_ADDRESS_RX(rxbd, (uintptr)pl_paddr); + instance_p->buffer.rx_pbufs_storage[bdindex] = (uintptr)p; + } +} +void FXmacRecvSemaphoreHandler(void *arg) +{ + FXmacOs *instance_p; + rt_err_t result; + + if (RT_NULL == arg) + { + LOG_E("Args is NULL"); + return; + } + + instance_p = (FXmacOs *)arg; + + result = eth_device_ready(&(instance_p->parent)); + if (result != RT_EOK) + { + LOG_I("RxCpltCallback err = %d", result); + } + +} +void FXmacRecvHandler(void *arg) +{ + struct pbuf *p; + FXmacBd *rxbdset, *curbdptr; + FXmacBdRing *rxring; + volatile u32 bd_processed; + u32 rx_bytes, k; + u32 bdindex; + u32 regval; + FXmacOs *instance_p; + FASSERT(arg != NULL); + + instance_p = (FXmacOs *)arg; + rxring = &FXMAC_GET_RXRING(instance_p->instance); + + /* If Reception done interrupt is asserted, call RX call back function + to handle the processed BDs and then raise the according flag.*/ + regval = FXMAC_READREG32(instance_p->instance.config.base_address, FXMAC_RXSR_OFFSET); + FXMAC_WRITEREG32(instance_p->instance.config.base_address, FXMAC_RXSR_OFFSET, regval); + + while (1) + { + bd_processed = FXmacBdRingFromHwRx(rxring, FXMAX_RX_PBUFS_LENGTH, &rxbdset); + if (bd_processed <= 0) + { + break; + } + + for (k = 0, curbdptr = rxbdset; k < bd_processed; k++) + { + + bdindex = FXMAC_BD_TO_INDEX(rxring, curbdptr); + p = (struct pbuf *)instance_p->buffer.rx_pbufs_storage[bdindex]; + /* + * Adjust the buffer size to the actual number of bytes received. + */ + if (instance_p->config & FXMAC_OS_CONFIG_JUMBO) + { + rx_bytes = FXMAC_GET_RX_FRAME_SIZE(curbdptr); + } + else + { + rx_bytes = FXMAC_BD_GET_LENGTH(curbdptr); + } + + pbuf_realloc(p, rx_bytes); + + /* Invalidate RX frame before queuing to handle + * L1 cache prefetch conditions on any architecture. + */ + // FCacheDCacheInvalidateRange((uintptr)p->payload, rx_bytes); + + /* store it in the receive queue, + * where it'll be processed by a different handler + */ + if (FXmacPqEnqueue(&instance_p->recv_q, (void *)p) < 0) + { +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + pbuf_free(p); + } + instance_p->buffer.rx_pbufs_storage[bdindex] = (uintptr)NULL; + curbdptr = FXMAC_BD_RING_NEXT(rxring, curbdptr); + } + + /* free up the BD's */ + FXmacBdRingFree(rxring, bd_processed, rxbdset); + SetupRxBds(instance_p, rxring); + + } + + return; +} + + +void CleanDmaTxdescs(FXmacOs *instance_p) +{ + FXmacBd bdtemplate; + FXmacBdRing *txringptr; + + txringptr = &FXMAC_GET_TXRING((instance_p->instance)); + FXMAC_BD_CLEAR(&bdtemplate); + FXMAC_BD_SET_STATUS(&bdtemplate, FXMAC_TXBUF_USED_MASK); + + FXmacBdRingCreate(txringptr, (uintptr)instance_p->buffer.tx_bdspace, + (uintptr)instance_p->buffer.tx_bdspace, BD_ALIGNMENT, + sizeof(instance_p->buffer.tx_bdspace)); + + FXmacBdRingClone(txringptr, &bdtemplate, FXMAC_SEND); +} + +FError FXmacInitDma(FXmacOs *instance_p) +{ + FXmacBd bdtemplate; + FXmacBdRing *rxringptr, *txringptr; + FXmacBd *rxbd; + struct pbuf *p; + FError status; + int i; + u32 bdindex; + u32 *temp; + uintptr rx_paddr; + uintptr tx_paddr; + uintptr pl_paddr; + + /* + * The BDs need to be allocated in uncached memory. Hence the 1 MB + * address range allocated for Bd_Space is made uncached + * by setting appropriate attributes in the translation table. + * The Bd_Space is aligned to 1MB and has a size of 1 MB. This ensures + * a reserved uncached area used only for BDs. + */ + + rxringptr = &FXMAC_GET_RXRING(instance_p->instance); + txringptr = &FXMAC_GET_TXRING(instance_p->instance); + FXMAC_OS_XMAC_PRINT_I("rxringptr: 0x%08x", rxringptr); + FXMAC_OS_XMAC_PRINT_I("txringptr: 0x%08x", txringptr); + + FXMAC_OS_XMAC_PRINT_I("rx_bdspace: %p ", instance_p->buffer.rx_bdspace); + FXMAC_OS_XMAC_PRINT_I("tx_bdspace: %p ", instance_p->buffer.tx_bdspace); + + /* Setup RxBD space. */ + FXMAC_BD_CLEAR(&bdtemplate); + rx_paddr = (uintptr)instance_p->buffer.rx_bdspace; +#ifdef RT_USING_SMART + rx_paddr += PV_OFFSET; +#endif + + /* Create the RxBD ring */ + status = FXmacBdRingCreate(rxringptr, (uintptr)rx_paddr, + (uintptr)instance_p->buffer.rx_bdspace, BD_ALIGNMENT, + FXMAX_RX_PBUFS_LENGTH); + + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_I("Error setting up RxBD space."); + return ERR_IF; + } + + status = FXmacBdRingClone(rxringptr, &bdtemplate, FXMAC_RECV); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_I("Error initializing RxBD space."); + return ERR_IF; + } + + FXMAC_BD_CLEAR(&bdtemplate); + FXMAC_BD_SET_STATUS(&bdtemplate, FXMAC_TXBUF_USED_MASK); + + tx_paddr = (uintptr)instance_p->buffer.tx_bdspace; +#ifdef RT_USING_SMART + tx_paddr += PV_OFFSET; +#endif + /* Create the TxBD ring */ + status = FXmacBdRingCreate(txringptr, (uintptr)tx_paddr, + (uintptr)instance_p->buffer.tx_bdspace, BD_ALIGNMENT, + FXMAX_TX_PBUFS_LENGTH); + + if (status != FT_SUCCESS) + { + return ERR_IF; + } + + /* We reuse the bd template, as the same one will work for both rx and tx. */ + status = FXmacBdRingClone(txringptr, &bdtemplate, FXMAC_SEND); + if (status != FT_SUCCESS) + { + return ERR_IF; + } + + /* + * Allocate RX descriptors, 1 RxBD at a time. + */ + for (i = 0; i < FXMAX_RX_PBUFS_LENGTH; i++) + { + if (instance_p->config & FXMAC_OS_CONFIG_JUMBO) + { + p = pbuf_alloc(PBUF_RAW, FXMAC_MAX_FRAME_SIZE_JUMBO, PBUF_POOL); + } + else + { + p = pbuf_alloc(PBUF_RAW, FXMAC_MAX_FRAME_SIZE, PBUF_POOL); + } + + if (!p) + { +#if LINK_STATS + lwip_stats.link.memerr++; + lwip_stats.link.drop++; +#endif + FXMAC_OS_XMAC_PRINT_E("Unable to alloc pbuf in InitDma."); + return ERR_IF; + } + status = FXmacBdRingAlloc(rxringptr, 1, &rxbd); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_E("InitDma: Error allocating RxBD."); + pbuf_free(p); + return ERR_IF; + } + /* Enqueue to HW */ + status = FXmacBdRingToHw(rxringptr, 1, rxbd); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_E("Error: committing RxBD to HW."); + pbuf_free(p); + FXmacBdRingUnAlloc(rxringptr, 1, rxbd); + return ERR_IF; + } + + bdindex = FXMAC_BD_TO_INDEX(rxringptr, rxbd); + temp = (u32 *)rxbd; + *temp = 0; + if (bdindex == (FXMAX_RX_PBUFS_LENGTH - 1)) + { + *temp = 0x00000002; + } + temp++; + *temp = 0; + + pl_paddr = (uintptr)p->payload; +#ifdef RT_USING_SMART + pl_paddr += PV_OFFSET; +#endif + FXMAC_BD_SET_ADDRESS_RX(rxbd, (uintptr)pl_paddr); + + instance_p->buffer.rx_pbufs_storage[bdindex] = (uintptr)p; + } + + FXmacSetQueuePtr(&(instance_p->instance), instance_p->instance.tx_bd_queue.bdring.phys_base_addr, 0, (u16)FXMAC_SEND); + FXmacSetQueuePtr(&(instance_p->instance), instance_p->instance.rx_bd_queue.bdring.phys_base_addr, 0, (u16)FXMAC_RECV); + + return 0; +} + +static void FreeOnlyTxPbufs(FXmacOs *instance_p) +{ + u32 index; + struct pbuf *p; + + for (index = 0; index < (FXMAX_TX_PBUFS_LENGTH); index++) + { + if (instance_p->buffer.tx_pbufs_storage[index] != 0) + { + p = (struct pbuf *)instance_p->buffer.tx_pbufs_storage[index]; + pbuf_free(p); + instance_p->buffer.tx_pbufs_storage[index] = (uintptr)NULL; + } + instance_p->buffer.tx_pbufs_storage[index] = (uintptr)0; + } +} + + +static void FreeOnlyRxPbufs(FXmacOs *instance_p) +{ + u32 index; + struct pbuf *p; + + for (index = 0; index < (FXMAX_RX_PBUFS_LENGTH); index++) + { + if (instance_p->buffer.rx_pbufs_storage[index] != 0) + { + p = (struct pbuf *)instance_p->buffer.rx_pbufs_storage[index]; + pbuf_free(p); + instance_p->buffer.rx_pbufs_storage[index] = (uintptr)0; + } + } +} + + +static void FreeTxRxPbufs(FXmacOs *instance_p) +{ + u32 rx_queue_len; + struct pbuf *p; + /* first :free PqQueue data */ + rx_queue_len = FXmacPqQlength(&instance_p->recv_q); + + while (rx_queue_len) + { + /* return one packet from receive q */ + p = (struct pbuf *)FXmacPqDequeue(&instance_p->recv_q); + pbuf_free(p); + FXMAC_OS_XMAC_PRINT_E("Delete queue %p", p); + rx_queue_len--; + } + FreeOnlyTxPbufs(instance_p); + FreeOnlyRxPbufs(instance_p); + +} + +/* interrupt */ +static void FXmacHandleDmaTxError(FXmacOs *instance_p) +{ + s32_t status = FT_SUCCESS; + u32 dmacrreg; + + FreeTxRxPbufs(instance_p); + status = FXmacCfgInitialize(&instance_p->instance, &instance_p->instance.config); + + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_E("In %s:EmacPs Configuration Failed....", __func__); + } + + /* initialize the mac */ + FXmacInitOnError(instance_p); /* need to set mac filter address */ + dmacrreg = FXMAC_READREG32(instance_p->instance.config.base_address, FXMAC_DMACR_OFFSET); + dmacrreg = dmacrreg | (FXMAC_DMACR_ORCE_DISCARD_ON_ERR_MASK); /* force_discard_on_err */ + FXMAC_WRITEREG32(instance_p->instance.config.base_address, FXMAC_DMACR_OFFSET, dmacrreg); + FXmacSetupIsr(instance_p); + FXmacInitDma(instance_p); + + FXmacStart(&instance_p->instance); + +} + +void FXmacHandleTxErrors(FXmacOs *instance_p) +{ + u32 netctrlreg; + + netctrlreg = FXMAC_READREG32(instance_p->instance.config.base_address, + FXMAC_NWCTRL_OFFSET); + netctrlreg = netctrlreg & (~FXMAC_NWCTRL_TXEN_MASK); + FXMAC_WRITEREG32(instance_p->instance.config.base_address, + FXMAC_NWCTRL_OFFSET, netctrlreg); + FreeOnlyTxPbufs(instance_p); + + CleanDmaTxdescs(instance_p); + netctrlreg = FXMAC_READREG32(instance_p->instance.config.base_address, FXMAC_NWCTRL_OFFSET); + netctrlreg = netctrlreg | (FXMAC_NWCTRL_TXEN_MASK); + FXMAC_WRITEREG32(instance_p->instance.config.base_address, FXMAC_NWCTRL_OFFSET, netctrlreg); +} + +void FXmacErrorHandler(void *arg, u8 direction, u32 error_word) +{ + FXmacBdRing *rxring; + FXmacBdRing *txring; + FXmacOs *instance_p; + + instance_p = (FXmacOs *)arg; + rxring = &FXMAC_GET_RXRING(instance_p->instance); + txring = &FXMAC_GET_TXRING(instance_p->instance); + + if (error_word != 0) + { + switch (direction) + { + case FXMAC_RECV: + if (error_word & FXMAC_RXSR_HRESPNOK_MASK) + { + FXMAC_OS_XMAC_PRINT_I("Receive DMA error."); + FXmacHandleDmaTxError(instance_p); + } + if (error_word & FXMAC_RXSR_RXOVR_MASK) + { + FXMAC_OS_XMAC_PRINT_I("Receive over run."); + FXmacRecvHandler(instance_p); + SetupRxBds(instance_p, rxring); + } + if (error_word & FXMAC_RXSR_BUFFNA_MASK) + { + FXMAC_OS_XMAC_PRINT_I("Receive buffer not available."); + FXmacRecvHandler(arg); + SetupRxBds(instance_p, rxring); + } + break; + case FXMAC_SEND: + if (error_word & FXMAC_TXSR_HRESPNOK_MASK) + { + FXMAC_OS_XMAC_PRINT_I("Transmit DMA error."); + FXmacHandleDmaTxError(instance_p); + } + if (error_word & FXMAC_TXSR_URUN_MASK) + { + FXMAC_OS_XMAC_PRINT_I("Transmit under run."); + FXmacHandleTxErrors(instance_p); + } + if (error_word & FXMAC_TXSR_BUFEXH_MASK) + { + FXMAC_OS_XMAC_PRINT_I("Transmit buffer exhausted."); + FXmacHandleTxErrors(instance_p); + } + if (error_word & FXMAC_TXSR_RXOVR_MASK) + { + FXMAC_OS_XMAC_PRINT_I("Transmit retry excessed limits."); + FXmacHandleTxErrors(instance_p); + } + if (error_word & FXMAC_TXSR_FRAMERX_MASK) + { + FXMAC_OS_XMAC_PRINT_I("Transmit collision."); + FXmacProcessSentBds(instance_p, txring); + } + break; + } + } +} + +void FXmacLinkChange(void *arg) +{ + u32 ctrl; + u32 link, link_status; + u32 speed; + u32 speed_bit; + u32 duplex; + FXmac *xmac_p; + FXmacOs *instance_p; + + instance_p = (FXmacOs *)arg; + xmac_p = &instance_p->instance; + + if (xmac_p->config.interface == FXMAC_PHY_INTERFACE_MODE_SGMII) + { + FXMAC_OS_XMAC_PRINT_I("xmac_p->config.base_address is %p", xmac_p->config.base_address); + ctrl = FXMAC_READREG32(xmac_p->config.base_address, FXMAC_PCS_AN_LP_OFFSET); + link = (ctrl & FXMAC_PCS_LINK_PARTNER_NEXT_PAGE_STATUS) >> 15; + FXMAC_OS_XMAC_PRINT_I("Link status is 0x%x", link); + + switch (link) + { + case 0: + link_status = FXMAC_LINKDOWN; + break; + case 1: + link_status = FXMAC_LINKUP; + break; + default: + FXMAC_OS_XMAC_PRINT_E("Link status is error 0x%x ", link); + return; + } + + if (xmac_p->config.auto_neg == 0) + { + if (link_status == FXMAC_LINKUP) + { + FXMAC_OS_XMAC_PRINT_I("No neg link up (%d/%s)", xmac_p->config.speed, xmac_p->config.duplex == 1 ? "FULL" : "Half"); + xmac_p->link_status = FXMAC_NEGOTIATING; + } + else + { + FXMAC_OS_XMAC_PRINT_I("No neg link down."); + xmac_p->link_status = FXMAC_LINKDOWN; + } + } + + /* read sgmii reg to get status */ + ctrl = FXMAC_READREG32(xmac_p->config.base_address, FXMAC_PCS_AN_LP_OFFSET); + speed_bit = (ctrl & FXMAC_PCS_AN_LP_SPEED) >> FXMAC_PCS_AN_LP_SPEED_OFFSET; + duplex = (ctrl & FXMAC_PCS_AN_LP_DUPLEX) >> FXMAC_PCS_AN_LP_DUPLEX_OFFSET; + + if (speed_bit == 2) + { + speed = FXMAC_SPEED_1000; + } + else if (speed_bit == 1) + { + speed = FXMAC_SPEED_100; + } + else + { + speed = FXMAC_SPEED_10; + } + + if (link_status != xmac_p->link_status) + { + FXMAC_OS_XMAC_PRINT_I("Sgmii link_status has changed."); + } + + /* add erase NCFGR config */ + if ((speed != xmac_p->config.speed) || (duplex != xmac_p->config.duplex)) + { + FXMAC_OS_XMAC_PRINT_I("Sgmii link_status has changed."); + FXMAC_OS_XMAC_PRINT_I("New speed is %d, duplex is %d", speed, duplex); + } + + if (link_status == FXMAC_LINKUP) + { + if (link_status != xmac_p->link_status) + { + xmac_p->link_status = FXMAC_NEGOTIATING; + FXMAC_OS_XMAC_PRINT_I("Need NEGOTIATING."); + } + } + else + { + xmac_p->link_status = link_status; + FXMAC_OS_XMAC_PRINT_I("Change status is 0x%x", link_status); + } + } +} + +/* phy */ + +/** + * @name: FXmacPhyLinkDetect + * @msg: Get current link status + * @note: + * @param {FXmac} *fxmac_p + * @param {u32} phy_addr + * @return {*} 1 is link up , 0 is link down + */ +static u32 FXmacPhyLinkDetect(FXmac *xmac_p, u32 phy_addr) +{ + u16 status; + + /* Read Phy Status register twice to get the confirmation of the current + * link status. + */ + + FXmacPhyRead(xmac_p, phy_addr, PHY_STATUS_REG_OFFSET, &status); + + if (status & PHY_STAT_LINK_STATUS) + { + return 1; + } + return 0; +} + +static u32 FXmacPhyAutonegStatus(FXmac *xmac_p, u32 phy_addr) +{ + u16 status; + + /* Read Phy Status register twice to get the confirmation of the current + * link status. + */ + FXmacPhyRead(xmac_p, phy_addr, PHY_STATUS_REG_OFFSET, &status); + + if (status & PHY_STATUS_AUTONEGOTIATE_COMPLETE) + { + return 1; + } + return 0; +} + +enum lwip_port_link_status FXmacLwipPortLinkDetect(FXmacOs *instance_p) +{ + u32 phy_link_status; + FXmac *xmac_p = &instance_p->instance; + + if (xmac_p->is_ready != (u32)FT_COMPONENT_IS_READY) + { + return ETH_LINK_UNDEFINED; + } + + phy_link_status = FXmacPhyLinkDetect(xmac_p, xmac_p->phy_address); + + if ((xmac_p->link_status == FXMAC_LINKUP) && (!phy_link_status)) + { + xmac_p->link_status = FXMAC_LINKDOWN; + } + + switch (xmac_p->link_status) + { + case FXMAC_LINKUP: + return ETH_LINK_UP; + case FXMAC_LINKDOWN: + xmac_p->link_status = FXMAC_NEGOTIATING; + FXMAC_OS_XMAC_PRINT_D("Ethernet Link down."); + return ETH_LINK_DOWN; + case FXMAC_NEGOTIATING: + if ((phy_link_status == FXMAC_LINKUP) && FXmacPhyAutonegStatus(xmac_p, xmac_p->phy_address)) + { + err_t phy_ret; + phy_ret = FXmacPhyInit(xmac_p, xmac_p->config.speed, xmac_p->config.duplex, xmac_p->config.auto_neg); + + if (phy_ret != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_E("FXmacPhyInit is error."); + return ETH_LINK_DOWN; + } + FXmacSelectClk(xmac_p); + FXmacInitInterface(xmac_p); + + /* Initiate Phy setup to get link speed */ + xmac_p->link_status = FXMAC_LINKUP; + FXMAC_OS_XMAC_PRINT_D("Ethernet Link up."); + return ETH_LINK_UP; + } + return ETH_LINK_DOWN; + default: + return ETH_LINK_DOWN; + } +} + +enum lwip_port_link_status FXmacPhyReconnect(FXmacOs *instance_p) +{ + FXmac *xmac_p; + + xmac_p = &instance_p->instance; + + if (xmac_p->config.interface == FXMAC_PHY_INTERFACE_MODE_SGMII) + { + rt_hw_interrupt_mask(xmac_p->config.queue_irq_num[0]); + if (xmac_p->link_status == FXMAC_NEGOTIATING) + { + /* auto negotiation again*/ + err_t phy_ret; + phy_ret = FXmacPhyInit(xmac_p, xmac_p->config.speed, xmac_p->config.duplex, xmac_p->config.auto_neg); + if (phy_ret != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_I("FXmacPhyInit is error."); + rt_hw_interrupt_umask(xmac_p->config.queue_irq_num[0]); + return ETH_LINK_DOWN; + } + FXmacSelectClk(xmac_p); + FXmacInitInterface(xmac_p); + xmac_p->link_status = FXMAC_LINKUP; + } + + rt_hw_interrupt_umask(xmac_p->config.queue_irq_num[0]); + + switch (xmac_p->link_status) + { + case FXMAC_LINKDOWN: + return ETH_LINK_DOWN; + case FXMAC_LINKUP: + return ETH_LINK_UP; + default: + return ETH_LINK_DOWN; + } + } + else if ((xmac_p->config.interface == FXMAC_PHY_INTERFACE_MODE_RMII) || (xmac_p->config.interface == FXMAC_PHY_INTERFACE_MODE_RGMII)) + { + return FXmacLwipPortLinkDetect(instance_p); + } + else + { + switch (xmac_p->link_status) + { + case FXMAC_LINKDOWN: + return ETH_LINK_DOWN; + case FXMAC_LINKUP: + return ETH_LINK_UP; + default: + return ETH_LINK_DOWN; + } + } +} + +static void FxmacOsIntrHandler(s32 vector, void *args) +{ + isr_calling_flg++; + FXmacIntrHandler(vector, args); + isr_calling_flg--; +} + +static void FXmacSetupIsr(FXmacOs *instance_p) +{ + u32 cpu_id; + GetCpuId(&cpu_id); + + /* Setup callbacks */ + FXmacSetHandler(&instance_p->instance, FXMAC_HANDLER_DMASEND, FXmacSendHandler, instance_p); + FXmacSetHandler(&instance_p->instance, FXMAC_HANDLER_DMARECV, FXmacRecvSemaphoreHandler, instance_p); + FXmacSetHandler(&instance_p->instance, FXMAC_HANDLER_ERROR, FXmacErrorHandler, instance_p); + FXmacSetHandler(&instance_p->instance, FXMAC_HANDLER_LINKCHANGE, FXmacLinkChange, instance_p); + + rt_hw_interrupt_install(instance_p->instance.config.queue_irq_num[0], FxmacOsIntrHandler, &instance_p->instance, "fxmac"); + rt_hw_interrupt_umask(instance_p->instance.config.queue_irq_num[0]); +} + +/* init fxmac instance */ + +static void FXmacInitOnError(FXmacOs *instance_p) +{ + FXmac *xmac_p; + u32 status = FT_SUCCESS; + xmac_p = &instance_p->instance; + + /* set mac address */ + status = FXmacSetMacAddress(xmac_p, (void *)(instance_p->hwaddr), 1); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_E("In %s:Emac Mac Address set failed...", __func__); + } +} + +/* step 1: initialize instance */ +/* step 2: depend on config set some options : JUMBO / IGMP */ +/* step 3: FXmacSelectClk */ +/* step 4: FXmacInitInterface */ +/* step 5: initialize phy */ +/* step 6: initialize dma */ +/* step 7: initialize interrupt */ +/* step 8: start mac */ + +FError FXmacOsInit(FXmacOs *instance_p) +{ + FXmacConfig mac_config; + FXmacConfig *mac_config_p; + FXmacPhyInterface interface = FXMAC_PHY_INTERFACE_MODE_SGMII; + FXmac *xmac_p; + u32 dmacrreg; + FError status; + FASSERT(instance_p != NULL); + FASSERT(instance_p->mac_config.instance_id < FXMAC_NUM); + + xmac_p = &instance_p->instance; + FXMAC_OS_XMAC_PRINT_I("instance_id IS %d", instance_p->mac_config.instance_id); + mac_config_p = FXmacLookupConfig(instance_p->mac_config.instance_id); + if (mac_config_p == NULL) + { + FXMAC_OS_XMAC_PRINT_E("FXmacLookupConfig is error , instance_id is %d", instance_p->mac_config.instance_id); + return FREERTOS_XMAC_INIT_ERROR; + } +#ifdef RT_USING_SMART + mac_config_p->base_address = (uintptr)rt_ioremap((void *)mac_config_p->base_address, 0x2000); +#endif + mac_config = *mac_config_p; + switch (instance_p->mac_config.interface) + { + case FXMAC_OS_INTERFACE_SGMII: + interface = FXMAC_PHY_INTERFACE_MODE_SGMII; + FXMAC_OS_XMAC_PRINT_I("SGMII select."); + break; + case FXMAC_OS_INTERFACE_RMII: + interface = FXMAC_PHY_INTERFACE_MODE_RMII; + FXMAC_OS_XMAC_PRINT_I("RMII select."); + break; + case FXMAC_OS_INTERFACE_RGMII: + FXMAC_OS_XMAC_PRINT_I("RGMII select."); + interface = FXMAC_PHY_INTERFACE_MODE_RGMII; + break; + default: + FXMAC_OS_XMAC_PRINT_E("Update interface is error , interface is %d", instance_p->mac_config.instance_id); + return FREERTOS_XMAC_INIT_ERROR; + } + mac_config.interface = interface; + + if (instance_p->mac_config.autonegotiation) + { + mac_config.auto_neg = 1; + } + else + { + mac_config.auto_neg = 0; + } + + switch (instance_p->mac_config.phy_speed) + { + case FXMAC_PHY_SPEED_10M: + mac_config.speed = FXMAC_SPEED_10; + break; + case FXMAC_PHY_SPEED_100M: + mac_config.speed = FXMAC_SPEED_100; + break; + case FXMAC_PHY_SPEED_1000M: + mac_config.speed = FXMAC_SPEED_1000; + break; + default: + FXMAC_OS_XMAC_PRINT_E("Setting speed is not valid , speed is %d", instance_p->mac_config.phy_speed); + return FREERTOS_XMAC_INIT_ERROR; + } + + switch (instance_p->mac_config.phy_duplex) + { + case FXMAC_PHY_HALF_DUPLEX: + mac_config.duplex = 0; + break; + case FXMAC_PHY_FULL_DUPLEX: + mac_config.duplex = 1; + break; + } + + status = FXmacCfgInitialize(xmac_p, &mac_config); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_E("In %s:EmacPs Configuration Failed....", __func__); + } + + if (instance_p->config & FXMAC_OS_CONFIG_JUMBO) + { + FXmacSetOptions(xmac_p, FXMAC_JUMBO_ENABLE_OPTION, 0); + } + + if (instance_p->config & FXMAC_OS_CONFIG_MULTICAST_ADDRESS_FILITER) + { + FXmacSetOptions(xmac_p, FXMAC_MULTICAST_OPTION, 0); + } + + /* enable copy all frames */ + if (instance_p->config & FXMAC_OS_CONFIG_COPY_ALL_FRAMES) + { + FXmacSetOptions(xmac_p, FXMAC_PROMISC_OPTION, 0); + } + + status = FXmacSetMacAddress(xmac_p, (void *)(instance_p->hwaddr), 0); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_E("In %s:Emac Mac Address set failed...", __func__); + } + + /* close fcs check */ + if (instance_p->config & FXMAC_OS_CONFIG_CLOSE_FCS_CHECK) + { + FXmacSetOptions(xmac_p, FXMAC_FCS_STRIP_OPTION, 0); + } + + /* initialize phy */ + status = FXmacPhyInit(xmac_p, xmac_p->config.speed, xmac_p->config.duplex, xmac_p->config.auto_neg); + if (status != FT_SUCCESS) + { + FXMAC_OS_XMAC_PRINT_W("FXmacPhyInit is error."); + } + + FXmacSelectClk(xmac_p); + FXmacInitInterface(xmac_p); + + /* initialize dma */ + dmacrreg = FXMAC_READREG32(xmac_p->config.base_address, FXMAC_DMACR_OFFSET); + dmacrreg &= (~(FXMAC_DMACR_BLENGTH_MASK)); + dmacrreg |= (FXMAC_DMACR_INCR16_AHB_AXI_BURST); /* Attempt to use bursts of up to 16. */ + FXMAC_WRITEREG32(xmac_p->config.base_address, FXMAC_DMACR_OFFSET, dmacrreg); + FXmacInitDma(instance_p); + + + /* initialize interrupt */ + FXmacSetupIsr(instance_p); + + return FT_SUCCESS; +} + + + + +/** + * @name: FXmacOsRx + * @msg: struct pbuf *FXmacOsRx(FXmacOs *instance_p) + * @return {*} + * @note: + * @param {FXmacOs} *instance_p */ +struct pbuf *FXmacOsRx(FXmacOs *instance_p) +{ + FASSERT(instance_p != NULL); + struct pbuf *p; + + /* see if there is data to process */ + if (FXmacPqQlength(&instance_p->recv_q) == 0) + { + return NULL; + } + /* return one packet from receive q */ + p = (struct pbuf *)FXmacPqDequeue(&instance_p->recv_q); + + return p; +} + +static FError FXmacOsOutput(FXmacOs *instance_p, struct pbuf *p) +{ + FError status; + + status = FXmacSgsend(instance_p, p); + if (status != FT_SUCCESS) + { +#if LINK_STATS + lwip_stats.link.drop++; +#endif + } + +#if LINK_STATS + lwip_stats.link.xmit++; +#endif /* LINK_STATS */ + + return status; +} + +FError FXmacOsTx(FXmacOs *instance_p, void *tx_buf) +{ + u32 freecnt; + FXmacBdRing *txring; + FError ret; + struct pbuf *p; + FASSERT(instance_p != NULL); + if (tx_buf == NULL) + { + FXMAC_OS_XMAC_PRINT_E("tx_buf is null."); + return FREERTOS_XMAC_PARAM_ERROR; + } + + p = tx_buf; + + /* check if space is available to send */ + freecnt = IsTxSpaceAvailable(instance_p); + + if (freecnt <= 5) + { + txring = &(FXMAC_GET_TXRING(instance_p->instance)); + FXmacProcessSentBds(instance_p, txring); + } + + if (IsTxSpaceAvailable(instance_p)) + { + FXmacOsOutput(instance_p, p); + ret = FT_SUCCESS; + } + else + { +#if LINK_STATS + lwip_stats.link.drop++; +#endif + FXMAC_OS_XMAC_PRINT_E("Pack dropped, no space."); + ret = FREERTOS_XMAC_NO_VALID_SPACE; + } + + return ret; +} + +FXmacOs *FXmacOsGetInstancePointer(FXmacOsControl *config_p) +{ + FXmacOs *instance_p; + FASSERT(config_p != NULL); + FASSERT(config_p->instance_id < FXMAC_NUM); + FASSERT_MSG(config_p->interface < FXMAC_OS_INTERFACE_LENGTH, "config_p->interface %d is over %d", config_p->interface, FXMAC_OS_INTERFACE_LENGTH); + FASSERT_MSG(config_p->autonegotiation <= 1, "config_p->autonegotiation %d is over 1", config_p->autonegotiation); + FASSERT_MSG(config_p->phy_speed <= FXMAC_PHY_SPEED_1000M, "config_p->phy_speed %d is over 1000", config_p->phy_speed); + FASSERT_MSG(config_p->phy_duplex <= FXMAC_PHY_FULL_DUPLEX, "config_p->phy_duplex %d is over FXMAC_PHY_FULL_DUPLEX", config_p->phy_duplex); + + instance_p = &fxmac_os_instace[config_p->instance_id]; + memcpy(&instance_p->mac_config, config_p, sizeof(FXmacOsControl)); + return instance_p; +} + +void FXmacOsStart(FXmacOs *instance_p) +{ + FASSERT(instance_p != NULL); + + /* start mac */ + FXmacStart(&instance_p->instance); +} + +static rt_err_t rt_xmac_init(rt_device_t dev) +{ + + struct eth_device *pXmacParent; + FXmacOs *pOsMac; + + FError ret; + + pXmacParent = rt_container_of(dev, struct eth_device, parent); + if (NULL == pXmacParent) + { + return -RT_ENOMEM; + } + + pOsMac = rt_container_of(pXmacParent, FXmacOs, parent); + if (NULL == pOsMac) + { + return -RT_ENOMEM; + } + + + ret = FXmacOsInit(pOsMac); + + if (ret != FT_SUCCESS) + { + LOG_E("FXmacOsInit is error\r\n"); + return -RT_ERROR; + } + rt_kprintf("FXMAC OS Init Success!\n"); + + + return RT_EOK; +} + +static rt_err_t rt_xmac_open(rt_device_t dev, rt_uint16_t oflag) +{ + LOG_D("xmac open"); + return RT_EOK; +} + +static rt_err_t rt_xmac_close(rt_device_t dev) +{ + LOG_D("xmac close"); + return RT_EOK; +} + +static rt_ssize_t rt_xmac_read(rt_device_t dev, rt_off_t pos, void *buffer, rt_size_t size) +{ + LOG_D("xmac read"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_ssize_t rt_xmac_write(rt_device_t dev, rt_off_t pos, const void *buffer, rt_size_t size) +{ + LOG_D("xmac write"); + rt_set_errno(-RT_ENOSYS); + return 0; +} + +static rt_err_t rt_xmac_control(rt_device_t dev, int cmd, void *args) +{ + + FXmacOs *pOsMac; + struct eth_device *pXmacParent; + + + pXmacParent = rt_container_of(dev, struct eth_device, parent); + + if (NULL == pXmacParent) + { + return -RT_ENOMEM; + } + + pOsMac = rt_container_of(pXmacParent, FXmacOs, parent); + if (NULL == pOsMac) + { + return -RT_ENOMEM; + } + switch (cmd) + { + case NIOCTL_GADDR: + /* get mac address */ + if (args) + { + rt_memcpy(args, pOsMac->hwaddr, 6); + } + + else + return -RT_ERROR; + break; + + default: + break; + } + + return RT_EOK; +} + +rt_err_t rt_xmac_tx(rt_device_t dev, struct pbuf *p) +{ + FXmacOs *pOsMac; + struct eth_device *pXmacParent; + rt_base_t level; + FError ret; + + pXmacParent = rt_container_of(dev, struct eth_device, parent); + if (NULL == pXmacParent) + { + return -RT_ENOMEM; + } + + pOsMac = rt_container_of(pXmacParent, FXmacOs, parent); + if (NULL == pOsMac) + { + return -RT_ENOMEM; + } + + + level = rt_hw_interrupt_disable(); +#if RT_LWIP_ETH_PAD_SIZE + pbuf_header(p, -RT_LWIP_ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + ret = FXmacOsTx(pOsMac, p); +#if RT_LWIP_ETH_PAD_SIZE + pbuf_header(p, ETH_PAD_SIZE); /* reclaim the padding word */ +#endif + rt_hw_interrupt_enable(level); + + if (ret != FT_SUCCESS) + { + return ERR_MEM; + } + + return RT_EOK; + +} + +struct pbuf *rt_xmac_rx(rt_device_t dev) +{ + FXmacOs *pOsMac; + struct eth_device *pXmacParent; + struct pbuf *p; + rt_base_t level; + + pXmacParent = rt_container_of(dev, struct eth_device, parent); + if (NULL == pXmacParent) + { + return RT_NULL; + } + + pOsMac = rt_container_of(pXmacParent, FXmacOs, parent); + if (NULL == pOsMac) + { + return RT_NULL; + } + + level = rt_hw_interrupt_disable(); + FXmacRecvHandler(pOsMac); + p = FXmacOsRx(pOsMac); + rt_hw_interrupt_enable(level); + return p; +} + + +enum lwip_port_link_status eth_link_detect(FXmacOs *instance_p) +{ + if (instance_p->instance.is_ready != FT_COMPONENT_IS_READY) + { + return ETH_LINK_UNDEFINED; + } + + return FXmacPhyReconnect(instance_p); +} + + +static void ethernet_link_thread(void *Args) +{ + FXmacOs *pOsMac; + static int is_link_up = 0; + if (RT_NULL == Args) + { + return; + } + + pOsMac = (FXmacOs *)Args; + + while (1) + { + /* Call eth_link_detect() every 10ms to detect Ethernet link + * change. + */ + + switch (eth_link_detect(pOsMac)) + { + case ETH_LINK_UP: + if (is_link_up == 0) + { + rt_kprintf("link up\n"); + is_link_up = 1; + eth_device_linkchange(&pOsMac->parent, RT_TRUE); + } + break; + case ETH_LINK_DOWN: + default: + if (is_link_up == 1) + { + rt_kprintf("link down\n"); + is_link_up = 0; + eth_device_linkchange(&pOsMac->parent, RT_FALSE); + } + break; + } + rt_thread_mdelay(10); + } +} + + + + +static int rt_hw_xmac_init(FXmacOs *pOsMac, const char *name) +{ + rt_err_t state = RT_EOK; + + pOsMac->parent.parent.init = rt_xmac_init; + pOsMac->parent.parent.open = rt_xmac_open; + pOsMac->parent.parent.close = rt_xmac_close; + pOsMac->parent.parent.read = rt_xmac_read; + pOsMac->parent.parent.write = rt_xmac_write; + pOsMac->parent.parent.control = rt_xmac_control; + pOsMac->parent.parent.user_data = RT_NULL; + + pOsMac->parent.eth_rx = rt_xmac_rx; + pOsMac->parent.eth_tx = rt_xmac_tx; + + pOsMac->hwaddr[0] = 0x98; + pOsMac->hwaddr[1] = 0x0e; + pOsMac->hwaddr[2] = 0x24; + pOsMac->hwaddr[3] = 0x00; + pOsMac->hwaddr[4] = 0x11; + pOsMac->hwaddr[5] = 0; + + /* register eth device */ + state = eth_device_init(&(pOsMac->parent), name); + if (RT_EOK != state) + { + LOG_E("xmac device init faild: %d", state); + return -RT_ERROR; + } + rt_kprintf("Xmac0 Initiailized!\n"); + + + state = rt_thread_init(&pOsMac->_link_thread, + "e0_link_detect", + ethernet_link_thread, + pOsMac, + &pOsMac->_link_thread_stack[0], + sizeof(pOsMac->_link_thread_stack), + 10, 2); + if (RT_EOK == state) + { + rt_thread_startup(&pOsMac->_link_thread); + } + else + { + LOG_E("rt_thread_init is error"); + return -RT_ERROR; + } + + FXmacOsStart(pOsMac); + + return RT_EOK; +} +static int rt_hw_xmac_eth_init(void) +{ + rt_err_t state = RT_EOK; + FXmacOsControl os_config; + FXmacOs *pOsMac; + + + /* os_config initialize，need to be set manually here */ + os_config.instance_id = 0; + os_config.interface = FXMAC_OS_INTERFACE_SGMII; + os_config.autonegotiation = 1; /* 1 is autonegotiation ,0 is manually set */ + os_config.phy_speed = FXMAC_PHY_SPEED_1000M; /* FXMAC_PHY_SPEED_XXX */ + os_config.phy_duplex = FXMAC_PHY_FULL_DUPLEX; /* FXMAC_PHY_XXX_DUPLEX */ + + pOsMac = FXmacOsGetInstancePointer(&os_config); + if (pOsMac == NULL) + { + LOG_E("FXmacOsGetInstancePointer is error\r\n"); + return -RT_ERROR; + } + + state = rt_hw_xmac_init(pOsMac, os_drv_xmac0_name); + if (RT_EOK != state) + { + goto __exit; + } + + +__exit: + return state; +} +INIT_DEVICE_EXPORT(rt_hw_xmac_eth_init); + +#endif + + diff --git a/bsp/phytium/libraries/drivers/drv_xmac.h b/bsp/phytium/libraries/drivers/drv_xmac.h index c935747e241..b54675ba5d5 100644 --- a/bsp/phytium/libraries/drivers/drv_xmac.h +++ b/bsp/phytium/libraries/drivers/drv_xmac.h @@ -1,22 +1,142 @@ /* - * @Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. + * Copyright (c) 2006-2023, RT-Thread Development Team * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. + * SPDX-License-Identifier: Apache-2.0 * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. + * Email: opensource_embedded@phytium.com.cn * - * - * @FilePath: drv_xmac.h - * @Date: 2023-04-19 15:19:39 - * @LastEditTime: 2023-04-19 15:19:40 - * @Description: This file is for - * - * @Modify History: - * Ver Who Date Changes - * ----- ------ -------- -------------------------------------- + * Change Logs: + * Date Author Notes + * 2022-07-07 liuzhihong first commit + * 2023-07-14 liuzhihong support RT-Smart */ +#ifndef __DRV_XMAC_H__ +#define __DRV_XMAC_H__ +#include +#include + +#include + +#include "fxmac.h" +#include "fkernel.h" +#include "ferror_code.h" +#include "fassert.h" +#include "fcache.h" +#include "fxmac_bdring.h" +#include "eth_ieee_reg.h" +#include "fcpu_info.h" +#include "fdebug.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#define FREERTOS_XMAC_INIT_ERROR FT_CODE_ERR(ErrModPort, 0, 0x1) +#define FREERTOS_XMAC_PARAM_ERROR FT_CODE_ERR(ErrModPort, 0, 0x2) +#define FREERTOS_XMAC_NO_VALID_SPACE FT_CODE_ERR(ErrModPort, 0, 0x3) + +#define FXMAX_RX_BDSPACE_LENGTH 0x20000 /* default set 128KB*/ +#define FXMAX_TX_BDSPACE_LENGTH 0x20000 /* default set 128KB*/ + +#define FXMAX_RX_PBUFS_LENGTH 16 +#define FXMAX_TX_PBUFS_LENGTH 16 + +#define FXMAX_MAX_HARDWARE_ADDRESS_LENGTH 6 + +/* configuration */ +#define FXMAC_OS_CONFIG_JUMBO BIT(0) +#define FXMAC_OS_CONFIG_MULTICAST_ADDRESS_FILITER BIT(1) /* Allow multicast address filtering */ +#define FXMAC_OS_CONFIG_COPY_ALL_FRAMES BIT(2) /* enable copy all frames */ +#define FXMAC_OS_CONFIG_CLOSE_FCS_CHECK BIT(3) /* close fcs check */ +#define FXMAC_OS_CONFIG_RX_POLL_RECV BIT(4) /* select poll mode */ +/* Phy */ +#define FXMAC_PHY_SPEED_10M 10 +#define FXMAC_PHY_SPEED_100M 100 +#define FXMAC_PHY_SPEED_1000M 1000 + +#define FXMAC_PHY_HALF_DUPLEX 0 +#define FXMAC_PHY_FULL_DUPLEX 1 + +#define MAX_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE) + +/* Byte alignment of BDs */ +#define BD_ALIGNMENT (FXMAC_DMABD_MINIMUM_ALIGNMENT*2) + +/* frame queue */ +#define PQ_QUEUE_SIZE 4096 + +#define LINK_THREAD_STACK_LENGTH 0x20400 + + +typedef struct +{ + uintptr data[PQ_QUEUE_SIZE]; + int head, tail, len; +} PqQueue; + +typedef enum +{ + FXMAC_OS_INTERFACE_SGMII = 0, + FXMAC_OS_INTERFACE_RMII, + FXMAC_OS_INTERFACE_RGMII, + FXMAC_OS_INTERFACE_LENGTH +} FXmacRtThreadInterface; + + +typedef struct +{ + u8 rx_bdspace[FXMAX_RX_BDSPACE_LENGTH] __attribute__((aligned(128))); /* 接收bd 缓冲区 */ + u8 tx_bdspace[FXMAX_RX_BDSPACE_LENGTH] __attribute__((aligned(128))); /* 发送bd 缓冲区 */ + + uintptr rx_pbufs_storage[FXMAX_RX_PBUFS_LENGTH]; + uintptr tx_pbufs_storage[FXMAX_TX_PBUFS_LENGTH]; + +} FXmacNetifBuffer; + +typedef struct +{ + u32 instance_id; + FXmacRtThreadInterface interface; + u32 autonegotiation; /* 1 is autonegotiation ,0 is manually set */ + u32 phy_speed; /* FXMAC_PHY_SPEED_XXX */ + u32 phy_duplex; /* FXMAC_PHY_XXX_DUPLEX */ +} FXmacOsControl; + + +typedef struct +{ + struct eth_device parent; /* inherit from ethernet device */ + + FXmac instance; /* Xmac controller */ + FXmacOsControl mac_config; + + FXmacNetifBuffer buffer; /* DMA buffer */ + + /* queue to store overflow packets */ + PqQueue recv_q; + PqQueue send_q; + + /* configuration */ + u32 config; + + rt_uint8_t hwaddr[FXMAX_MAX_HARDWARE_ADDRESS_LENGTH]; /* MAC address */ + + struct rt_thread _link_thread; /* link detect thread */ + rt_uint8_t _link_thread_stack[LINK_THREAD_STACK_LENGTH];/* link detect thread stack*/ +} FXmacOs; + +enum lwip_port_link_status +{ + ETH_LINK_UNDEFINED = 0, + ETH_LINK_UP, + ETH_LINK_DOWN, + ETH_LINK_NEGOTIATING +}; + + + +#ifdef __cplusplus +} +#endif + +#endif // ! diff --git a/bsp/phytium/libraries/examples/spi_sfud_sample.c b/bsp/phytium/libraries/examples/spi_sfud_sample.c deleted file mode 100644 index ed9d0423ac3..00000000000 --- a/bsp/phytium/libraries/examples/spi_sfud_sample.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Email: opensource_embedded@phytium.com.cn - * - * Change Logs: - * Date Author Notes - * 2022-11-20 liqiaozhong first commit - * 2022-03-08 liqiaozhong add format function and mount table - */ -#include -#include - -#if defined (RT_USING_SFUD) && defined(RT_USING_DFS) - -#include -#include -#include -#include -#include -#include -#include "spi_flash.h" -#include "spi_flash_sfud.h" - -#include "fdebug.h" -#include "fparameters_comm.h" - -#include "fspim.h" -/************************** Variable Definitions *****************************/ -sfud_flash_t spim_flash = RT_NULL; -const struct dfs_mount_tbl mount_table[] = -{ - { "flash2", "/", "elm", 0, RT_NULL }, - {0}, -}; -/***************** Macros (Inline Fungoctions) Definitions *********************/ -#define FSPIM_DEBUG_TAG "SPIM" -#define FSPIM_ERROR(format, ...) FT_DEBUG_PRINT_E(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__) -#define FSPIM_WARN(format, ...) FT_DEBUG_PRINT_W(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__) -#define FSPIM_INFO(format, ...) FT_DEBUG_PRINT_I(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__) -#define FSPIM_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSPIM_DEBUG_TAG, format, ##__VA_ARGS__) - -/*******************************Api Functions*********************************/ -static int spi_flash_sfud_init(void) -{ - if (RT_NULL == rt_sfud_flash_probe("flash2", "spi02")) - { - rt_kprintf("rt_sfud_flash_probe failed\n"); - return RT_ERROR; - } - spim_flash = rt_sfud_flash_find_by_dev_name("flash2"); - if (RT_NULL == spim_flash) - { - rt_kprintf("Flash init failed -> can't find flash2 device!\n"); - return RT_ERROR; - } - rt_kprintf("Spi flash device flash2 init\n"); - rt_kprintf("Flash device: flash2 info\nmf_id: 0x%x\ntype_id: 0x%x\ncapacity_id: 0x%x\nerase granularity: %lu\n", - spim_flash->chip.mf_id, - spim_flash->chip.type_id, - spim_flash->chip.capacity_id, - spim_flash->chip.erase_gran); - - return RT_EOK; -} -INIT_DEVICE_EXPORT(spi_flash_sfud_init); - -/* format the flash with elm environment */ -static int flash_format_operation(void) -{ - int result = RT_EOK; - result = dfs_mkfs("elm", "flash2"); - return result; -} -INIT_ENV_EXPORT(flash_format_operation); - -#endif /* RT_USING_SFUD || RT_USING_DFS */ diff --git a/bsp/phytium/libraries/standalone/README.md b/bsp/phytium/libraries/standalone/README.md index 8011132ab35..b05bd14a685 100644 --- a/bsp/phytium/libraries/standalone/README.md +++ b/bsp/phytium/libraries/standalone/README.md @@ -1,6 +1,6 @@ # Phytium-Standalone-SDK -**v1.0.0** [ReleaseNote](./doc/ChangeLog.md) +**v1.1.1** [ReleaseNote](./doc/ChangeLog.md) ## 1. 项目概要 @@ -16,20 +16,15 @@ release 分支：发布分支，包含核心启动代码、芯片外设驱动、 ![LetterShell](./doc/fig/letter_shell.png) - ### 1.3 系统架构 - 本项目的整体设计如下所示，自下而上可以分为平台层、组件层、框架层和应用层。 ![Framework](./doc/design/system_2.png) - 平台层（Platform）在整个软件框架中位于最底层，提供了基本数据结构类型定义、驱动参数标定、硬件平台耦合的寄存器自检、板级启动、CPU 内存虚拟等功能 - - 组件层（Component）在整个软件框架中位于中间位置，向下依赖于平台层提供的参数配置与内存方案，向上提供应用开发与模块测试的支持 - - 框架层（Framework）为开发主机提供了开发环境，支持SDK安装，应用工程配置和二进制文件构建及烧录等工具。 - - 应用层（Application）提供了应用开发模板和例程，帮助开发者迅速熟悉SDK的使用，进行不同类型的应用程序开发 ### 1.4 源代码结构 @@ -39,15 +34,15 @@ release 分支：发布分支，包含核心启动代码、芯片外设驱动、 ├── Kconfig --> 配置定义 ├── LICENSE --> 版权声明 ├── README.md --> 使用说明 -├── arch +├── arch │   └── armv8 --> 架构相关 ├── baremetal │   └── example --> 裸机例程 -├── board +├── board │   ├── d2000 │   ├── e2000 │   └── ft2004 --> 平台相关 -├── common +├── common │   ├── fprintf.c │   ├── fprintf.h │   ├── fsleep.c @@ -63,7 +58,7 @@ release 分支：发布分支，包含核心启动代码、芯片外设驱动、 │   ├── dma │   └── watchdog --> 外设驱动 ├── install.py --> 安装脚本 -├── lib +├── lib │   ├── Kconfiglib │   ├── lib.mk │   ├── libc @@ -77,7 +72,7 @@ release 分支：发布分支，包含核心启动代码、芯片外设驱动、 ├── scripts ├── standalone.mk ├── third-party -│   └── letter-shell-3.1 --> 第三方库 +│   └── letter-shell-3.1 --> 第三方库 ├── tools ``` @@ -89,12 +84,10 @@ release 分支：发布分支，包含核心启动代码、芯片外设驱动、 ![windows](./doc/fig/windows.png)![linux](./doc/fig/linux.png)![输入图片说明](./doc/fig/kylin.png) - - 参考[Windows10 快速入门](./doc/reference/usr/install_windows.md), [Linux x86_64 快速入门](./doc/reference/usr/install_linux_x86_64.md) - - 参考[使用说明](./doc/reference/usr/usage.md), 新建Phytium Standalone SDK的应用工程，与开发板建立连接 - - 参考[例程](./baremetal/example)，开始使用SDK +- 参考[系统测试](./example)，开始使用重构后的系统测试用例(v1.1.0版本开始，测试用例将逐步进行重构) --- @@ -134,7 +127,6 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个 ### 3.3 E2000Q - E2000Q 集成2个FTC664核和2个FTC310核。主要技术特征如下： - - 兼容ARM v8 64 位指令系统，兼容32 位指令 - 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA - 支持单精度、双精度浮点运算指令 @@ -150,7 +142,6 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个 ### 3.4 E2000D - E2000D 集成 2 个 FTC310 核。主要技术特征如下： - - 兼容ARM v8 64 位指令系统，兼容32 位指令 - 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA - 支持单精度、双精度浮点运算指令 @@ -166,7 +157,6 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个 ### 3.5 E2000S - E2000S 集成 1 个 FTC310 核，单核结构。主要技术特征如下： - - 兼容ARM v8 64 位指令系统，兼容32 位指令 - 集成 1 路 16 通道 General DMA 和 1 路 8 通道 Device DMA - 支持单精度、双精度浮点运算指令 @@ -178,50 +168,48 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个 - 2路 DisplayPort1.4 接口 - 集成常用低速接口：WDT、DMAC、PWM、QSPI、SD/SDIO/eMMC、SPI Master、UART、I2C、MIO、I3C、PMBUS、GPIO、SGPIO、One-Wire、Timer、One-Wire - ## 4 外设驱动支持情况 -| Hardware Interface | Platform Supported | Platform Developing | Component | -| ------------------------------ | -------------------------- | --------------------------- | ------------------------- | -| Generic Intrrupt Controller v3 | FT2000/4
E2000
D2000 | | gic/fgic | -| Generic Timer | FT2000/4
E2000
D2000 | | generic_timer | -| UART (PrimeCell PL011) | FT2000/4
E2000
D2000 | | usart/pl011_uart | -| 10/100/1000MB-ETHERNET | FT2000/4
E2000
D2000 | | eth/fgmac
eth/fxmac | -| ADC | E2000 | | adc/fadc | -| CAN | FT2000/4
E2000
D2000 | | can/fcan | -| DDMA | | E2000 | dma/fddma | -| GDMA | E2000 | | dma/gdma | -| GPIO | FT2000/4
E2000
D2000 | | gpio/fgpio | -| I2C | FT2000/4
E2000
D2000 | | i2c/fi2c | -| QSPI (Nor Flash) | FT2000/4
E2000
D2000 | | qspi/fqspi | -| SPI | FT2000/4
E2000
D2000 | | spi/fspim | -| TIMER & TACHO | E2000 | | timer/ftimer_tacho | -| MIO | E2000 | | mio/fmio | -| SDMMC | | FT2000/4
D2000 | mmc/fsdmmc | -| SDIO | E2000 | | mmc/fsdio | -| PCIE | FT2000/4
D2000
E2000 | | pcie/fpcie | -| NAND | E2000 | | nand/fnand | -| RTC | FT2000/4
D2000 | | rtc/frtc | -| SATA | FT2000/4
D2000
E2000 | | sata/fsata | -| USB-PCI | | FT2000/4
E2000
D2000 | usb/fxhci | -| PWM | E2000 | | pwm/fpwm | -| WDT | FT2000/4
D2000
E2000 | | watchdog/fwdt | - - -| Third-Party | Platform Supported | Platform Developing | Component | -| ------------------------------ | -------------------------- | --------------------------- | ------------------------- | -| LWIP 2.1.2 | FT2000/4
D2000
E2000 | | lwip-2.1.2 | -| Letter shell 3.1 | FT2000/4
D2000
E2000 | | letter-shell-3.1 | -| Sdmmc | FT2000/4
D2000 | | sdmmc | -| Sfud 1.1.0 | FT2000/4
D2000
E2000 | | sfud-1.1.0 | -| Backtrace | FT2000/4
D2000
E2000 | | backtrace | -| Tlsf | FT2000/4
D2000
E2000 | | tlsf-3.1.0 | -| Fatfs (RAM/Sd/SATA) | FT2000/4
D2000
E2000 | | fatfs-0.1.3 | -| Ymodem | FT2000/4
D2000
E2000 | | | -| OpenAMP | FT2000/4
D2000
E2000 | | openamp | -| LittleFS-2.4.2 | | FT2000/4
E2000
D2000 | littlefs-2.4.2 | -| SPIFFS-0.3.7 | FT2000/4
D2000
E2000 | | spiffs-0.3.7 | -| freemodbus-v1.6 | E2000 | | protocols/fmodbus_test | +| Hardware Interface | Platform Supported | Platform Developing | Component | +| ------------------------------ | ---------------------------------- | ---------------------------------- | -------------------------- | +| Generic Intrrupt Controller v3 | FT2000/4`
`E2000`
`D2000 | | gic/fgic | +| Generic Timer | FT2000/4`
`E2000`
`D2000 | | generic_timer | +| UART (PrimeCell PL011) | FT2000/4`
`E2000`
`D2000 | | usart/pl011_uart | +| 10/100/1000MB-ETHERNET | FT2000/4`
`E2000`
`D2000 | | eth/fgmac`
`eth/fxmac | +| ADC | E2000 | | adc/fadc | +| CAN | FT2000/4`
`E2000`
`D2000 | | can/fcan | +| DDMA | | E2000 | dma/fddma | +| GDMA | E2000 | | dma/gdma | +| GPIO | FT2000/4`
`E2000`
`D2000 | | gpio/fgpio | +| I2C | FT2000/4`
`E2000`
`D2000 | | i2c/fi2c | +| QSPI (Nor Flash) | FT2000/4`
`E2000`
`D2000 | | qspi/fqspi | +| SPI | FT2000/4`
`E2000`
`D2000 | | spi/fspim | +| TIMER & TACHO | E2000 | | timer/ftimer_tacho | +| MIO | E2000 | | mio/fmio | +| SDMMC | | FT2000/4`
`D2000 | mmc/fsdmmc | +| SDIO | E2000 | | mmc/fsdio | +| PCIE | FT2000/4`
`D2000`
`E2000 | | pcie/fpcie | +| NAND | E2000 | | nand/fnand | +| RTC | FT2000/4`
`D2000 | | rtc/frtc | +| SATA | FT2000/4`
`D2000`
`E2000 | | sata/fsata | +| USB-PCI | | FT2000/4`
`E2000`
`D2000 | usb/fxhci | +| PWM | E2000 | | pwm/fpwm | +| WDT | FT2000/4`
`D2000`
`E2000 | | watchdog/fwdt | + +| Third-Party | Platform Supported | Platform Developing | Component | +| ------------------- | ---------------------------------- | ---------------------------------- | ---------------------- | +| LWIP 2.1.2 | FT2000/4`
`D2000`
`E2000 | | lwip-2.1.2 | +| Letter shell 3.1 | FT2000/4`
`D2000`
`E2000 | | letter-shell-3.1 | +| Sdmmc | FT2000/4`
`D2000 | | sdmmc | +| Sfud 1.1.0 | FT2000/4`
`D2000`
`E2000 | | sfud-1.1.0 | +| Backtrace | FT2000/4`
`D2000`
`E2000 | | backtrace | +| Tlsf | FT2000/4`
`D2000`
`E2000 | | tlsf-3.1.0 | +| Fatfs (RAM/Sd/SATA) | FT2000/4`
`D2000`
`E2000 | | fatfs-0.1.3 | +| Ymodem | FT2000/4`
`D2000`
`E2000 | | | +| OpenAMP | FT2000/4`
`D2000`
`E2000 | | openamp | +| LittleFS-2.4.2 | | FT2000/4`
`E2000`
`D2000 | littlefs-2.4.2 | +| SPIFFS-0.3.7 | FT2000/4`
`D2000`
`E2000 | | spiffs-0.3.7 | +| freemodbus-v1.6 | E2000 | | protocols/fmodbus_test | --- @@ -266,15 +254,18 @@ D2000 是一款面向桌面应用的高性能通用 8 核处理器。每 2 个 #### 5.1.18 [FMEDIA](doc/reference/driver/fmedia.md) ### 5.2 MEMORY + #### 5.2.1 [FMEMORY_POOL](./doc/reference/sdk/fmemory_pool.md) ### 5.3 CPU -#### 5.3.1 [MMU](./doc/reference/processor/mmu.md) +#### 5.3.1 [MMU](./doc/reference/cpu/mmu.md) #### 5.3.2 [FPINCTRL](./doc/reference/sdk/fpinctrl.md) -#### 5.3.2 [INTERRUPT](./doc/reference/processor/interrupt.md) +#### 5.3.2 [FINTERRUPT](./doc/reference/cpu/finterrupt.md) + +#### 5.3.3 [FPSCI](./doc/reference/cpu/psci.md) --- @@ -302,7 +293,6 @@ zhangyan1491@phytium.com.cn ## 6. 相关资源 - - ARM Architecture Reference Manual - ARM Cortex-A Series Programmer’s Guide - Programmer Guide for ARMv8-A diff --git a/bsp/phytium/libraries/standalone/board/Kconfig b/bsp/phytium/libraries/standalone/board/Kconfig index 5169f3e1e23..c0216c2dbe0 100644 --- a/bsp/phytium/libraries/standalone/board/Kconfig +++ b/bsp/phytium/libraries/standalone/board/Kconfig @@ -8,21 +8,31 @@ menu "Board Configuration" config TARGET_F2000_4 bool "FT2000-4" + select USE_SERIAL + select ENABLE_Pl011_UART config TARGET_D2000 bool "D2000" + select USE_SERIAL + select ENABLE_Pl011_UART config TARGET_E2000Q bool "E2000Q" select TARGET_E2000 + select USE_SERIAL + select ENABLE_Pl011_UART config TARGET_E2000D bool "E2000D" select TARGET_E2000 + select USE_SERIAL + select ENABLE_Pl011_UART config TARGET_E2000S bool "E2000S" select TARGET_E2000 + select USE_SERIAL + select ENABLE_Pl011_UART # config TARGET_TARDIGRADE # bool "TARDIGRADE" diff --git a/bsp/phytium/libraries/standalone/board/common/fsmp.c b/bsp/phytium/libraries/standalone/board/common/fsmp.c new file mode 100644 index 00000000000..806e33d2ef6 --- /dev/null +++ b/bsp/phytium/libraries/standalone/board/common/fsmp.c @@ -0,0 +1,68 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fsmp.c + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-02-17 17:58:14 + * Description:  This files is for a way to provide spinlocks for multicore operations + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * v1.1 carl 2022-12-30 add init function + * v1.2 cark 2023-02-28 Use GCC built-in functions to implement spinlock + */ + +#if 0 + +#include "fsmp.h" +#include "sdkconfig.h" +#include "ftypes.h" +#include "fatomic.h" + + +typedef struct +{ + int v; +}FCpuLock; + + +#ifdef CONFIG_SPIN_MEM + FCpuLock *_lock = (FCpuLock *)CONFIG_SPIN_MEM; +#else + FCpuLock _static_lock ; + FCpuLock *_lock = &_static_lock ; +#endif + + +void SpinUnlock(void) +{ + FATOMIC_UNLOCK(_lock->v); +} + +void SpinLock(void) +{ + + while(FATOMIC_LOCK(_lock->v,1)) + { + + } + +} + +void SpinInit(void) +{ + FATOMIC_UNLOCK(_lock->v); +} + +#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.h b/bsp/phytium/libraries/standalone/board/common/fsmp.h similarity index 69% rename from bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.h rename to bsp/phytium/libraries/standalone/board/common/fsmp.h index 195a787ffd7..e16f69a6163 100644 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.h +++ b/bsp/phytium/libraries/standalone/board/common/fsmp.h @@ -11,34 +11,36 @@ * See the Phytium Public License for more details. * * - * FilePath: fpsci.h - * Date: 2022-02-10 14:53:41 - * LastEditTime: 2022-02-17 17:30:40 - * Description:  This file is for cpu energy management + * FilePath: fsmp.h + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-02-17 17:58:18 + * Description:  This file is for spinlock function * * Modify History: * Ver   Who        Date         Changes * ----- ------     --------    -------------------------------------- - * 1.0 huanghe 2021/7/3 first release + * 1.0 carl 2023-02-28 Use GCC built-in functions to implement spinlock */ -#ifndef ARCH_ARMV8_AARCH32_PSCI_H -#define ARCH_ARMV8_AARCH32_PSCI_H +#ifndef BSP_BOARD_COMMON_SMP_H +#define BSP_BOARD_COMMON_SMP_H + +#include "ftypes.h" + #ifdef __cplusplus extern "C" { #endif -#include "ftypes.h" -#include "ferror_code.h" - -FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr); -void PsciCpuReset(void); +void SpinInit(void); +void SpinLock(void); +void SpinUnlock(void); #ifdef __cplusplus } #endif -#endif // ! + +#endif // DEBUG \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/d2000/fioctrl.c b/bsp/phytium/libraries/standalone/board/d2000/fioctrl.c deleted file mode 100644 index ae1ff0d3a2a..00000000000 --- a/bsp/phytium/libraries/standalone/board/d2000/fioctrl.c +++ /dev/null @@ -1,406 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fioctrl.c - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-18 08:25:29 - * Description:  This files is for io-ctrl function implementation (io-mux/io-config/io-delay) - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 zhugengyu 2022/2/22 init commit - */ - - -/***************************** Include Files *********************************/ -#include "fparameters.h" -#include "fio.h" -#include "fkernel.h" -#include "fassert.h" -#include "fdebug.h" - -#include "fioctrl.h" -#include "fpinctrl.h" - -/************************** Constant Definitions *****************************/ -/* Bit[0] : 输入延迟功能使能 */ -#define FIOCTRL_DELAY_EN(delay_beg) BIT(delay_beg) -#define FIOCTRL_INPUT_DELAY_OFF 0 - -/* Bit[3:1] : 输入延迟精调档位选择 */ -#define FIOCTRL_DELICATE_DELAY_MASK(delay_beg) GENMASK((delay_beg + 3), (delay_beg + 1)) -#define FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1)) -#define FIOCTRL_DELICATE_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1)) - -/* Bit[6:4] : 输入延迟粗调档位选择 */ -#define FIOCTRL_ROUGH_DELAY_MASK(delay_beg) GENMASK((delay_beg + 6), (delay_beg + 4)) -#define FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4)) -#define FIOCTRL_ROUGH_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4)) - -/* Bit[7] : 保留 */ -/* Bit[8] : 输出延迟功能使能 */ - -/* Bit[11:9] : 输出延迟精调档位选择 */ -/* Bit [14:12] : 输出延迟粗调档位选择 */ -/* Bit [15] : 保留 */ - -#define FIOCTRL_FUNC_BEG_OFF(reg_bit) ((reg_bit) + 0) -#define FIOCTRL_FUNC_END_OFF(reg_bit) ((reg_bit) + 1) /* bit[1:0] 复用功能占2个位 */ -#define FIOCTRL_PULL_BEG_OFF(reg_bit) ((reg_bit) + 2) -#define FIOCTRL_PULL_END_OFF(reg_bit) ((reg_bit) + 3) /* bit[3:2] 上下拉功能占2个位 */ - -#define FIOCTRL_DELAY_IN_BEG_OFF(reg_bit) ((reg_bit) + 0) -#define FIOCTRL_DELAY_IN_END_OFF(reg_bit) ((reg_bit) + 7) /* bit[8:1] 输入延时占7个位 */ -#define FIOCTRL_DELAY_OUT_BEG_OFF(reg_bit) ((reg_bit) + 8) -#define FIOCTRL_DELAY_OUT_END_OFF(reg_bit) ((reg_bit) + 15) /* bit[15:9] 输出延时占7个位 */ - -/* 芯片引脚控制寄存器的起止位置 */ -#define FIOCTRL_REG_OFFSET_MIN 0x200 -#define FIOCTRL_REG_OFFSET_MAX 0x22c - -/* 芯片引脚延时寄存器的起止位置 */ -#define FIOCTRL_DELAY_REG_OFFSET_MIN 0x400 -#define FIOCTRL_DELAY_REG_OFFSET_MAX 0x404 - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -#define FIOCTRL_DEBUG_TAG "FIOCTRL" -#define FIOCTRL_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOCTRL_WARN(format, ...) FT_DEBUG_PRINT_W(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOCTRL_INFO(format, ...) FT_DEBUG_PRINT_I(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOCTRL_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__) - -#define FIOCTRL_ASSERT_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_REG_OFFSET_MAX)), "invalid pin register off @%d", (pin.reg_off)) -#define FIOCTRL_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d", (func)) -#define FIOCTRL_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d", (pull)) - -#define FIOCTRL_ASSERT_DELAY_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_DELAY_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_DELAY_REG_OFFSET_MAX)), "invalid delay pin register off @%d", (pin.reg_off)) -#define FIOCTRL_ASSERT_DELAY(delay) FASSERT_MSG(((delay) < FPIN_NUM_OF_DELAY), "invalid delay as %d", (delay)); -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/*****************************************************************************/ - -/** - * @name: FPinGetFunc - * @msg: 获取IO引脚当前的复用功能 - * @return {FPinFunc} 当前的复用功能 - * @param {FPinIndex} pin IO引脚索引 - * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值 - */ -FPinFunc FPinGetFunc(const FPinIndex pin) -{ - FIOCTRL_ASSERT_REG_OFF(pin); - - u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit); - u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 func = GET_REG32_BITS(reg_val, func_end, func_beg); - FIOCTRL_ASSERT_FUNC(func); - - return (FPinFunc)GET_REG32_BITS(reg_val, func_end, func_beg); -} - -/** - * @name: FPinSetFunc - * @msg: 设置IO引脚复用功能 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @param {FPinFunc} func IO复用功能 - * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值 - */ -void FPinSetFunc(const FPinIndex pin, FPinFunc func) -{ - FIOCTRL_ASSERT_REG_OFF(pin); - FIOCTRL_ASSERT_FUNC(func); - - u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit); - u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - - reg_val &= ~GENMASK(func_end, func_beg); - reg_val |= SET_REG32_BITS(func, func_end, func_beg); - - FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val); - return; -} - -/** - * @name: FPinGetPull - * @msg: 获取IO引脚当前的上下拉设置 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值 - */ -FPinPull FPinGetPull(const FPinIndex pin) -{ - FIOCTRL_ASSERT_REG_OFF(pin); - - u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit); - u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 pull = GET_REG32_BITS(reg_val, pull_end, pull_beg); - - FIOCTRL_ASSERT_PULL(pull); - return (FPinPull)pull; -} - -/** - * @name: FPinSetPull - * @msg: 设置IO引脚当前的上下拉 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @param {FPinPull} pull 上下拉设置 - */ -void FPinSetPull(const FPinIndex pin, FPinPull pull) -{ - FIOCTRL_ASSERT_REG_OFF(pin); - FIOCTRL_ASSERT_PULL(pull); - - u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit); - u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - - reg_val &= ~GENMASK(pull_end, pull_beg); - reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg); - - FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val); - return; -} - -/** - * @name: FPinGetConfig - * @msg: 获取IO引脚的复用、上下拉和驱动能力设置 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @param {FPinFunc} *func IO复用功能 - * @param {FPinPull} *pull pull 上下拉设置 - */ -void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull) -{ - FIOCTRL_ASSERT_REG_OFF(pin); - - u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit); - u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit); - u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit); - u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - - if (func) - { - *func = GET_REG32_BITS(reg_val, func_end, func_beg); - } - - if (pull) - { - *pull = GET_REG32_BITS(reg_val, pull_end, pull_beg); - } - - return; -} - -/** - * @name: FPinSetConfig - * @msg: 设置IO引脚的复用、上下拉和驱动能力 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @param {FPinFunc} func IO复用功能 - * @param {FPinPull} pull pull 上下拉设置 - */ -void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull) -{ - FIOCTRL_ASSERT_REG_OFF(pin); - u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit); - u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit); - u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit); - u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - - reg_val &= ~GENMASK(func_end, func_beg); - reg_val |= SET_REG32_BITS(func, func_end, func_beg); - - reg_val &= ~GENMASK(pull_end, pull_beg); - reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg); - - FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val); - return; -} - -/** - * @name: FPinGetDelay - * @msg: 获取IO引脚当前的延时设置 - * @return {FPinDelay} 当前的延时设置 - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - * @param {FPinDelayType} type 精调/粗调延时 - */ -FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type) -{ - FIOCTRL_ASSERT_DELAY_REG_OFF(pin); - u8 delay = 0; - const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 delay_beg = 0, delay_end = 0; - - if (FPIN_OUTPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off); - } - else if (FPIN_INPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off); - } - else - { - FASSERT(0); - } - - if (FPIN_DELAY_FINE_TUNING == type) - { - delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg); - } - else if (FPIN_DELAY_COARSE_TUNING == type) - { - delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg); - } - else - { - FASSERT(0); - } - - FIOCTRL_ASSERT_DELAY(delay); - return (FPinDelay)delay; -} - - -/** - * @name: FPinGetDelayEn - * @msg: 获取IO引脚当前的延时使能标志位 - * @return {*} - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - */ -boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir) -{ - FIOCTRL_ASSERT_DELAY_REG_OFF(pin); - boolean enabled = FALSE; - const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 delay_beg = 0, delay_end = 0; - - if (FPIN_OUTPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off); - } - else if (FPIN_INPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off); - } - else - { - FASSERT(0); - } - - if (FIOCTRL_DELAY_EN(delay_beg) & reg_val) - { - enabled = TRUE; - } - - return enabled; -} - -/** - * @name: FPinSetDelay - * @msg: 设置IO引脚延时 - * @return {*} - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - * @param {FPinDelayType} type 精调/粗调延时 - * @param {FPinDelay} delay 延时档位设置 0 ~ 8 档可用 - */ -void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay) -{ - FIOCTRL_ASSERT_DELAY_REG_OFF(pin); - FIOCTRL_ASSERT_DELAY(delay); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 delay_beg = 0, delay_end = 0; - - if (FPIN_OUTPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off); - } - else if (FPIN_INPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off); - } - else - { - FASSERT(0); - } - - if (FPIN_DELAY_FINE_TUNING == type) - { - reg_val &= ~FIOCTRL_DELICATE_DELAY_MASK(delay_beg); - delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg); - } - else if (FPIN_DELAY_COARSE_TUNING == type) - { - reg_val &= ~FIOCTRL_ROUGH_DELAY_MASK(delay_beg); - delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg); - } - else - { - FASSERT(0); - } - - FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val); - return; -} - -/** - * @name: FPinSetDelayEn - * @msg: 使能/去使能IO引脚延时 - * @return {*} - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - * @param {boolean} enable TRUE: 使能, FALSE: 去使能 - */ -void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable) -{ - FIOCTRL_ASSERT_DELAY_REG_OFF(pin); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 delay_beg = 0, delay_end = 0; - - if (FPIN_OUTPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off); - } - else if (FPIN_INPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off); - } - else - { - FASSERT(0); - } - - reg_val &= ~FIOCTRL_DELAY_EN(delay_beg); - if (enable) - { - reg_val |= FIOCTRL_DELAY_EN(delay_beg); - } - - FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val); - return; -} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/d2000/fioctrl.h b/bsp/phytium/libraries/standalone/board/d2000/fioctrl.h deleted file mode 100644 index 9012e7d2abc..00000000000 --- a/bsp/phytium/libraries/standalone/board/d2000/fioctrl.h +++ /dev/null @@ -1,83 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fioctrl.h - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-18 08:25:35 - * Description:  This files is for io-ctrl function definition (io-mux/io-config/io-delay) - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 zhugengyu 2022/2/22 init commit - */ - - -#ifndef BOARD_D2000_FIOCTRL_H -#define BOARD_D2000_FIOCTRL_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/***************************** Include Files *********************************/ -#include "ftypes.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -#define FIOCTRL_INDEX(offset, func_beg) \ - { \ - /* reg_off */ (offset), \ - /* reg_bit */ (func_beg) \ - } - -/************************** Variable Definitions *****************************/ -#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24) -#define FIOCTRL_SPI0_CSN0_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 16) -#define FIOCTRL_SPI0_SCK_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 12) -#define FIOCTRL_SPI0_SO_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 8) -#define FIOCTRL_SPI0_SI_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 4) - -#define FIOCTRL_TJTAG_TDI_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 24) /* can0-tx: func 1 */ -#define FIOCTRL_SWDITMS_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 12) /* can0-rx: func 1 */ - -#define FIOCTRL_NTRST_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 20) /* can1-tx: func 1 */ -#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* can1-rx: func 1 */ - -#define FIOCTRL_I2C0_SCL_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 24) /* i2c0-scl: func 0 */ -#define FIOCTRL_I2C0_SDA_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 20) /* i2c0-sda: func 0 */ -#define FIOCTRL_ALL_PLL_LOCK_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 28) /* i2c1-scl: func 2 */ -#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24) /* i2c1-sda: func 2 */ -#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* i2c2-scl: func 2 */ -#define FIOCTRL_TDO_SWJ_IN_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 4) /* i2c2-sda: func 2 */ -#define FIOCTRL_HDT_MB_DONE_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 0) /* i2c3-scl: func 2 */ -#define FIOCTRL_HDT_MB_FAIL_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */ - -#define FIOCTRL_UART_2_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x210, 0) /* spi1_csn0: func 1 */ -#define FIOCTRL_UART_2_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */ -#define FIOCTRL_UART_3_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */ -#define FIOCTRL_UART_3_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 20) /* spi1_si: func 1 */ -#define FIOCTRL_QSPI_CSN2_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 8) /* spi1_csn1: func 1 */ -#define FIOCTRL_QSPI_CSN3_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 4) /* spi1_csn2: func 1 */ - - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/phytium/libraries/standalone/board/d2000/fparameters.h b/bsp/phytium/libraries/standalone/board/d2000/fparameters.h deleted file mode 100644 index e848dfa90d7..00000000000 --- a/bsp/phytium/libraries/standalone/board/d2000/fparameters.h +++ /dev/null @@ -1,347 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fparameters.h - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-17 17:58:51 - * Description:  This file is for - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_BOARD_D2000_PARAMETERS_H -#define BSP_BOARD_D2000_PARAMETERS_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#if !defined(__ASSEMBLER__) -#include "ftypes.h" -#endif - -#define CORE0_AFF 0x0 -#define CORE1_AFF 0x1 -#define CORE2_AFF 0x100 -#define CORE3_AFF 0x101 -#define CORE4_AFF 0x200 -#define CORE5_AFF 0x201 -#define CORE6_AFF 0x300 -#define CORE7_AFF 0x301 - -/* cache */ -#define CACHE_LINE_ADDR_MASK 0x3F -#define CACHE_LINE 64U - -/* Device register address */ -#define FDEV_BASE_ADDR 0x28000000 -#define FDEV_END_ADDR 0x2FFFFFFF - -/* Generic Timer */ -#define GENERIC_TIMER_NS_IRQ_NUM 30 - -/* PCI */ - -#define FPCIE_NUM 1 -#define FPCIE0_ID 0 -#define FPCIE0_MISC_IRQ_NUM 59 - -#define FPCIE_CFG_MAX_NUM_OF_BUS 256 -#define FPCIE_CFG_MAX_NUM_OF_DEV 32 -#define FPCIE_CFG_MAX_NUM_OF_FUN 8 - -#define FPCI_CONFIG_BASE_ADDR 0x40000000 -#define FPCI_CONFIG_REG_LENGTH 0x10000000 - -#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000 -#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000 - -#define FPCI_MEM32_BASE_ADDR 0x58000000 -#define FPCI_MEM32_REG_LENGTH 0x27ffffff - -#define FPCI_MEM64_BASE_ADDR 0x1000000000 -#define FPCI_MEM64_REG_LENGTH 0x1000000000 - -#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29900000 -#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29910000 -#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29920000 -#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29930000 -#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29940000 -#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29950000 - -#define FPCI_EU0_CONFIG_BASE_ADDR 0x29900000 -#define FPCI_EU1_CONFIG_BASE_ADDR 0x299A0000 - - -#define FPCI_INTA_IRQ_NUM 60 -#define FPCI_INTB_IRQ_NUM 61 -#define FPCI_INTC_IRQ_NUM 62 -#define FPCI_INTD_IRQ_NUM 63 - -#define FPCI_NEED_SKIP 0 - -#define FPCI_INTX_EOI -#define FPCI_INTX_PEU0_STAT 0x29100000 -#define FPCI_INTX_PEU1_STAT 0x29101000 - -#define FPCI_INTX_EU0_C0_CONTROL 0x29000184 -#define FPCI_INTX_EU0_C1_CONTROL 0x29010184 -#define FPCI_INTX_EU0_C2_CONTROL 0x29020184 -#define FPCI_INTX_EU1_C0_CONTROL 0x29030184 -#define FPCI_INTX_EU1_C1_CONTROL 0x29040184 -#define FPCI_INTX_EU1_C2_CONTROL 0x29050184 - -#define FPCI_INTX_CONTROL_NUM 6 /* Total number of controllers */ -#define FPCI_INTX_SATA_NUM 2 /* Total number of controllers */ - -/* platform ahci host */ -#define PLAT_AHCI_HOST_MAX_COUNT 5 -#define AHCI_BASE_0 0 -#define AHCI_BASE_1 0 -#define AHCI_BASE_2 0 -#define AHCI_BASE_3 0 -#define AHCI_BASE_4 0 - -#define AHCI_IRQ_0 0 -#define AHCI_IRQ_1 0 -#define AHCI_IRQ_2 0 -#define AHCI_IRQ_3 0 -#define AHCI_IRQ_4 0 - -/* UART */ -#if !defined(__ASSEMBLER__) -enum -{ - FUART0_ID = 0, - FUART1_ID, - FUART2_ID, - FUART3_ID, - - FUART_NUM -}; -#endif - -#define FUART0_IRQ_NUM 38 -#define FUART0_BASE_ADDR 0x28000000 -#define FUART0_CLK_FREQ_HZ 48000000 - -#define FUART1_IRQ_NUM 39 -#define FUART1_BASE_ADDR 0x28001000 -#define FUART1_CLK_FREQ_HZ 48000000 - -#define FUART2_IRQ_NUM 40 -#define FUART2_BASE_ADDR 0x28002000 -#define FUART2_CLK_FREQ_HZ 48000000 - -#define FUART3_IRQ_NUM 41 -#define FUART3_BASE_ADDR 0x28003000 -#define FUART3_CLK_FREQ_HZ 48000000 - -#define FT_STDOUT_BASE_ADDR FUART1_BASE_ADDR -#define FT_STDIN_BASE_ADDR FUART1_BASE_ADDR - -/* QSPI */ -#if !defined(__ASSEMBLER__) -enum -{ - FQSPI0_ID = 0, - - FQSPI_NUM -}; - -/* FQSPI cs 0_3, chip number */ -enum -{ - FQSPI_CS_0 = 0, - FQSPI_CS_1 = 1, - FQSPI_CS_2 = 2, - FQSPI_CS_3 = 3, - FQSPI_CS_NUM -}; -#endif - -#define FQSPI_BASE_ADDR 0x28014000 -#define FQSPI_MEM_START_ADDR 0x0 -#define FQSPI_MEM_END_ADDR 0x1FFFFFFF - -/* GIC v3 */ -#define ARM_GIC_NR_IRQS 1024 -#define ARM_GIC_IRQ_START 0 -#define FGIC_NUM 1 - - -#define GICV3_BASE_ADDR 0x29a00000U -#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0) -#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x100000U) -#define GICV3_RD_OFFSET (2U << 16) -#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM - -/* - * The maximum priority value that can be used in the GIC. - */ -#define GICV3_MAX_INTR_PRIO_VAL 240U -#define GICV3_INTR_PRIO_MASK 0x000000f0U - -#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ -#define SGI_INT_MAX 16 -#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ -#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ -#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ - -/* GPIO */ -#define FGPIO0_BASE_ADDR (0x28004000) -#define FGPIO1_BASE_ADDR (0x28005000) - -#define FGPIO0_ID 0 -#define FGPIO1_ID 1 -#define FGPIO_NUM 2 - -#define FGPIO0_IRQ_NUM (42) /* gpio0 irq number */ -#define FGPIO1_IRQ_NUM (43) /* gpio1 irq number */ - -/* IOMUX */ -#define FIOCTRL_REG_BASE_ADDR 0x28180000 - -/* SPI */ -#define FSPI0_BASE_ADDR 0x2800c000 -#define FSPI1_BASE_ADDR 0x28013000 -#define FSPI0_ID 0 -#define FSPI1_ID 1 -#define FSPI_CLK_FREQ_HZ 48000000 -#define FSPI_NUM 2 -#define FSPI0_IRQ_NUM 50 -#define FSPI1_IRQ_NUM 51 - -/* I2C */ -#if !defined(__ASSEMBLER__) -enum -{ - FI2C0_ID = 0, - FI2C1_ID = 1, - FI2C2_ID, - FI2C3_ID, - - FI2C_NUM -}; -#endif - -#define FI2C0_BASE_ADDR 0x28006000 -#define FI2C1_BASE_ADDR 0x28007000 -#define FI2C2_BASE_ADDR 0x28008000 -#define FI2C3_BASE_ADDR 0x28009000 - -#define FI2C0_IRQ_NUM 44 -#define FI2C1_IRQ_NUM 45 -#define FI2C2_IRQ_NUM 46 -#define FI2C3_IRQ_NUM 47 - -#define FI2C_CLK_FREQ_HZ 48000000 /* 48MHz */ - -/* WDT */ -#if !defined(__ASSEMBLER__) -enum -{ - FWDT0_ID = 0, - FWDT1_ID = 1, - - FWDT_NUM -}; -#endif - -#define FWDT0_REFRESH_BASE_ADDR 0x2800a000 -#define FWDT1_REFRESH_BASE_ADDR 0x28016000 - -#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000) - -#define FWDT0_IRQ_NUM 48 -#define FWDT1_IRQ_NUM 49 - -#define FWDT_CLK_FREQ_HZ 48000000 /* 48MHz */ - -/* SDCI */ -#if !defined(__ASSEMBLER__) -enum -{ - FSDMMC0_ID = 0, - - FSDMMC_NUM -}; -#endif - -#define FSDMMC0_BASE_ADDR 0x28207C00 - -#define FSDMMC0_DMA_IRQ_NUM 52 -#define FSDMMC0_CMD_IRQ_NUM 53 -#define FSDMMC0_ERR_IRQ_NUM 54 - -#define FSDMMC_CLK_FREQ_HZ 600000000 /* 600 MHz */ - -/* GMAC */ -#define FGMAC_PUB_REG_BASE_ADDR 0x2820B000 /* 公共寄存器基地址 */ - -#if !defined(__ASSEMBLER__) -enum -{ - FGMAC0_ID = 0, - FGMAC1_ID, - - FGMAC_NUM -}; -#endif - -#define FGMAC0_BASE_ADDR 0x2820C000 -#define FGMAC1_BASE_ADDR 0x28210000 - -#define FGMAC0_IRQ_NUM 81 -#define FGMAC1_IRQ_NUM 82 - -#define FGMAC_DMA_MIN_ALIGN 128 -#define FGMAC_MAX_PACKET_SIZE 1600 - -/* rtc base address */ -#define RTC_CONTROL_BASE 0x2800D000 - -#define FT_CPUS_NR CORE_NUM - - - -/* can */ -#define FCAN_CLK_FREQ_HZ 600000000 - -#define FCAN_REG_LENGTH 0x1000 -#define FCAN0_BASE_ADDR 0x28207000 -#define FCAN1_BASE_ADDR 0x28207400 -#define FCAN2_BASE_ADDR 0x28207800 -#define FCAN0_IRQ_NUM 119 -#define FCAN1_IRQ_NUM 123 -#define FCAN2_IRQNUM 124 - -#if !defined(__ASSEMBLER__) -enum -{ - FCAN0_ID = 0, - FCAN1_ID = 1, - FCAN2_ID = 2, - - FCAN_NUM -}; -#endif - -#ifdef __cplusplus -} -#endif - -#endif // ! \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/e2000/d/fiopad.h b/bsp/phytium/libraries/standalone/board/e2000/d/fiopad.h deleted file mode 100644 index 41af7df2ed8..00000000000 --- a/bsp/phytium/libraries/standalone/board/e2000/d/fiopad.h +++ /dev/null @@ -1,269 +0,0 @@ - -#ifndef BOARD_E2000D_FIOPAD_H -#define BOARD_E2000D_FIOPAD_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/***************************** Include Files *********************************/ -#include "fiopad_comm.h" - -/************************** Constant Definitions *****************************/ -/* register offset of iopad function / pull / driver strength */ -#define FIOPAD_AN55 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET) -#define FIOPAD_AW43 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET) -#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET) -#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET) -#define FIOPAD_AL51 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET) -#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET) -#define FIOPAD_AN47 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET) -#define FIOPAD_AR47 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET) -#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET) -#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET) -#define FIOPAD_AW53 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET) -#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET) -#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET) -#define FIOPAD_AN53 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET) -#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET) -#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET) -#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET) -#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET) -#define FIOPAD_AG53 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET) -#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET) -#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET) -#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET) -#define FIOPAD_AR45 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET) -#define FIOPAD_BA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET) -#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET) -#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET) -#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET) -#define FIOPAD_AR53 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET) -#define FIOPAD_BA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET) -#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET) -#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET) -#define FIOPAD_R53 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET) -#define FIOPAD_R55 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET) -#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET) -#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET) -#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET) -#define FIOPAD_AA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET) -#define FIOPAD_AA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET) -#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET) -#define FIOPAD_AU47 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET) -#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET) -#define FIOPAD_C35 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET) -#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET) -#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET) -#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET) -#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET) -#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET) -#define FIOPAD_C41 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET) -#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET) -#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET) -#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET) -#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET) -#define FIOPAD_A29 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET) -#define FIOPAD_C29 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET) -#define FIOPAD_C27 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET) -#define FIOPAD_A27 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET) -#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET) -#define FIOPAD_AL45 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET) -#define FIOPAD_AL43 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET) -#define FIOPAD_AN45 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET) -#define FIOPAD_AG47 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET) -#define FIOPAD_AJ47 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET) -#define FIOPAD_AG45 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET) -#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET) -#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET) -#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET) -#define FIOPAD_AJ45 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET) -#define FIOPAD_AC51 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET) -#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET) -#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET) -#define FIOPAD_W47 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET) -#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET) -#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET) -#define FIOPAD_U51 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET) -#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET) -#define FIOPAD_AE45 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET) -#define FIOPAD_AC45 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET) -#define FIOPAD_AE43 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET) -#define FIOPAD_AA43 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET) -#define FIOPAD_AA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET) -#define FIOPAD_W45 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET) -#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET) -#define FIOPAD_U45 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET) -#define FIOPAD_G55 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET) -#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET) -#define FIOPAD_L53 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET) -#define FIOPAD_C55 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET) -#define FIOPAD_E55 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET) -#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET) -#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET) -#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET) -#define FIOPAD_C53 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET) -#define FIOPAD_E53 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET) -#define FIOPAD_E27 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET) -#define FIOPAD_G27 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET) -#define FIOPAD_N37 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET) -#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET) -#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET) -#define FIOPAD_N29 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET) -#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET) -#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET) -#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET) -#define FIOPAD_L27 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET) -#define FIOPAD_J27 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET) -#define FIOPAD_J25 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET) -#define FIOPAD_E25 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET) -#define FIOPAD_G25 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET) -#define FIOPAD_N23 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET) -#define FIOPAD_L25 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET) -#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET) -#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET) -#define FIOPAD_G37 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET) -#define FIOPAD_E39 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET) -#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET) -#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET) -#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET) -#define FIOPAD_L41 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET) -#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET) -#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET) -#define FIOPAD_L35 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET) -#define FIOPAD_E33 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET) -#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET) -#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET) -#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET) -#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET) -#define FIOPAD_N31 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET) -#define FIOPAD_R47 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET) -#define FIOPAD_R45 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET) -#define FIOPAD_N47 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET) -#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET) -#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET) -#define FIOPAD_J51 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET) -#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET) -#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET) -#define FIOPAD_G43 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET) -#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET) -#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET) -#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET) -#define FIOPAD_L47 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET) -#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET) -#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET) -#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET) - -/* register offset of iopad delay */ -#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET) -#define FIOPAD_AL51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET) -#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET) -#define FIOPAD_AN47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET) -#define FIOPAD_AR47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET) -#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET) -#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET) -#define FIOPAD_AG53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET) -#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET) -#define FIOPAD_BA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET) -#define FIOPAD_BA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET) -#define FIOPAD_AR55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET) -#define FIOPAD_AU55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET) -#define FIOPAD_A41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET) -#define FIOPAD_C41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET) -#define FIOPAD_A43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET) -#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET) -#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET) -#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET) -#define FIOPAD_A29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET) -#define FIOPAD_C29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET) -#define FIOPAD_C27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET) -#define FIOPAD_A27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET) -#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET) -#define FIOPAD_AL45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET) -#define FIOPAD_AL43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET) -#define FIOPAD_AN45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET) -#define FIOPAD_AG47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET) -#define FIOPAD_AJ47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET) -#define FIOPAD_AG45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET) -#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET) -#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET) -#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET) -#define FIOPAD_AJ45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET) -#define FIOPAD_AC51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET) -#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET) -#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET) -#define FIOPAD_W47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET) -#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET) -#define FIOPAD_U51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET) -#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET) -#define FIOPAD_AE45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET) -#define FIOPAD_AC45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET) -#define FIOPAD_AE43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET) -#define FIOPAD_AA43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET) -#define FIOPAD_AA45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET) -#define FIOPAD_W45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET) -#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET) -#define FIOPAD_U45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET) -#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET) -#define FIOPAD_L53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET) -#define FIOPAD_C55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET) -#define FIOPAD_E55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET) -#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET) -#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET) -#define FIOPAD_N55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET) -#define FIOPAD_E27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET) -#define FIOPAD_G27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET) -#define FIOPAD_N37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET) -#define FIOPAD_N35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET) -#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET) -#define FIOPAD_N29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET) -#define FIOPAD_L29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET) -#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET) -#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET) -#define FIOPAD_L27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET) -#define FIOPAD_J27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET) -#define FIOPAD_J25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET) -#define FIOPAD_E25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET) -#define FIOPAD_G25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET) -#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET) -#define FIOPAD_J35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET) -#define FIOPAD_G37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET) -#define FIOPAD_E39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET) -#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET) -#define FIOPAD_C39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET) -#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET) -#define FIOPAD_L41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET) -#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET) -#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET) -#define FIOPAD_L35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET) -#define FIOPAD_E33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET) -#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET) -#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET) -#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET) -#define FIOPAD_J51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET) -#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET) -#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET) -#define FIOPAD_G43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET) -#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET) -#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET) -#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET) -#define FIOPAD_L47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET) -#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET) -#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET) -#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET) - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ - - - -#ifdef __cplusplus -} - -#endif - -#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/e2000/d/fiopad_config.c b/bsp/phytium/libraries/standalone/board/e2000/d/fiopad_config.c deleted file mode 100644 index 2453c866e40..00000000000 --- a/bsp/phytium/libraries/standalone/board/e2000/d/fiopad_config.c +++ /dev/null @@ -1,555 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fiopad_config.c - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-18 08:25:29 - * Description:  This file is for io-pad function definition - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 huanghe 2021/11/5 init commit - * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec. - */ - -/***************************** Include Files *********************************/ -#include "fiopad.h" -#include "fparameters.h" -#include "fdebug.h" -#include "fpinctrl.h" -#include "fassert.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -#define FIOPAD_DEBUG_TAG "FIOPAD-CFG" -#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** - * @name: FIOPadSetSpimMux - * @msg: set iopad mux for spim - * @return {*} - * @param {u32} spim_id, instance id of spi - */ -void FIOPadSetSpimMux(u32 spim_id) -{ - if (FSPI2_ID == spim_id) - { - FPinSetFunc(FIOPAD_A29, FPIN_FUNC0); /* sclk */ - FPinSetFunc(FIOPAD_C29, FPIN_FUNC0); /* txd */ - FPinSetFunc(FIOPAD_C27, FPIN_FUNC0); /* rxd */ - FPinSetFunc(FIOPAD_A27, FPIN_FUNC0); /* csn0 */ - } -} - -/** - * @name: FIOPadSetGpioMux - * @msg: set iopad mux for gpio - * @return {*} - * @param {u32} gpio_id, instance id of gpio - * @param {u32} pin_id, index of pin - */ -void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) -{ - if (FGPIO3_ID == gpio_id) - { - switch (pin_id) - { - case 3: /* gpio 3-a-3 */ - FPinSetFunc(FIOPAD_A29, FPIN_FUNC6); - break; - case 4: /* gpio 3-a-4 */ - FPinSetFunc(FIOPAD_C29, FPIN_FUNC6); - break; - case 5: /* gpio 3-a-5 */ - FPinSetFunc(FIOPAD_C27, FPIN_FUNC6); - break; - case 6: /* gpio 3-a-6 */ - FPinSetFunc(FIOPAD_A27, FPIN_FUNC6); - break; - case 7: /* gpio 3-a-7 */ /*cannot use this pin*/ - FPinSetFunc(FIOPAD_AJ49, FPIN_FUNC6); - break; - case 8: /* gpio 3-a-8 */ - FPinSetFunc(FIOPAD_AL45, FPIN_FUNC6); - break; - case 9: /* gpio 3-a-9 */ - FPinSetFunc(FIOPAD_AL43, FPIN_FUNC6); - break; - default: - break; - } - } - else if (FGPIO4_ID == gpio_id) - { - switch (pin_id) - { - case 5: /* gpio 4-a-5 */ - FPinSetFunc(FIOPAD_W47, FPIN_FUNC6); - break; - case 9: /* gpio 4-a-9 */ - FPinSetFunc(FIOPAD_U49, FPIN_FUNC6); - break; - case 10: /* gpio 4-a-10 */ - FPinSetFunc(FIOPAD_AE45, FPIN_FUNC6); - break; - case 11: /* gpio 4-a-11 */ - FPinSetFunc(FIOPAD_AC45, FPIN_FUNC6); - break; - case 12: /* gpio 4-a-12 */ - FPinSetFunc(FIOPAD_AE43, FPIN_FUNC6); - break; - case 13: /* gpio 4-a-13 */ - FPinSetFunc(FIOPAD_AA43, FPIN_FUNC6); - break; - default: - break; - } - } -} - -/** - * @name: FIOPadSetCanMux - * @msg: set iopad mux for can - * @return {*} - * @param {u32} can_id, instance id of can - */ -void FIOPadSetCanMux(u32 can_id) -{ - if (can_id == FCAN0_ID) - { - /* can0 */ - FPinSetFunc(FIOPAD_A37, FPIN_FUNC0); /* can0-tx: func 0 */ - FPinSetFunc(FIOPAD_A39, FPIN_FUNC0); /* can0-rx: func 0 */ - } - else if (can_id == FCAN1_ID) - { - /* can1 */ - FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can1-tx: func 0 */ - FPinSetFunc(FIOPAD_C41, FPIN_FUNC0); /* can1-rx: func 0 */ - } - else - { - FIOPAD_ERROR("can id is error.\r\n"); - } -} - -/** - * @name: FIOPadSetQspiMux - * @msg: set iopad mux for qspi - * @return {*} - * @param {u32} qspi_id, id of qspi instance - * @param {u32} cs_id, id of qspi cs - */ -void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id) -{ - - if (qspi_id == FQSPI0_ID) - { - /* add sck, io0-io3 iopad multiplex */ - } - - if (cs_id == FQSPI_CS_0) - { - FPinSetFunc(FIOPAD_AR51, FPIN_FUNC0); - } - else if (cs_id == FQSPI_CS_1) - { - FPinSetFunc(FIOPAD_AR45, FPIN_FUNC0); - } - else if (cs_id == FQSPI_CS_2) - { - FPinSetFunc(FIOPAD_C33, FPIN_FUNC5); - } - else if (cs_id == FQSPI_CS_3) - { - FPinSetFunc(FIOPAD_A33, FPIN_FUNC5); - } - else - { - FIOPAD_ERROR("can id is error.\r\n"); - } -} - - -/** - * @name: FIOPadSetPwmMux - * @msg: set iopad mux for pwm - * @return {*} - * @param {u32} pwm_id, id of pwm instance - * @param {u32} pwm_channel, channel of pwm instance - */ -void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel) -{ - FASSERT(pwm_id < FPWM_NUM); - FASSERT(pwm_channel < FPWM_CHANNEL_NUM); - - switch (pwm_id) - { - case FPWM0_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_AL55, FPIN_FUNC1); /* PWM0_OUT: func 1 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_AJ53, FPIN_FUNC1); /* PWM1_OUT: func 1 */ - } - break; - - case FPWM1_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_AG53, FPIN_FUNC1); /* PWM2_OUT: func 1 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_AC55, FPIN_FUNC1); /* PWM3_OUT: func 1 */ - } - break; - - case FPWM2_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_BA51, FPIN_FUNC1); /* PWM4_OUT: func 1 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_C35, FPIN_FUNC2); /* PWM5_OUT: func 2 */ - } - break; - - case FPWM3_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_A33, FPIN_FUNC2); /* PWM6_OUT: func 2 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_A39, FPIN_FUNC2); /* PWM7_OUT: func 2 */ - } - break; - - case FPWM4_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_C41, FPIN_FUNC2); /* PWM8_OUT: func 2 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_A45, FPIN_FUNC2); /* PWM9_OUT: func 2 */ - } - break; - - case FPWM5_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_A47, FPIN_FUNC2); /* PWM10_OUT: func 2 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_C29, FPIN_FUNC2); /* PWM11_OUT: func 2 */ - } - break; - - case FPWM6_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_A27, FPIN_FUNC2); /* PWM12_OUT: func 2 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_J35, FPIN_FUNC3); /* PWM13_OUT: func 3 */ - } - break; - - case FPWM7_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_E39, FPIN_FUNC3); /* PWM14_OUT: func 3 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_C39, FPIN_FUNC3); /* PWM15_OUT: func 3 */ - } - break; - - default: - FIOPAD_ERROR("pwm id is error.\r\n"); - break; - } -} - - -/** - * @name: FIOPadSetAdcMux - * @msg: set iopad mux for adc - * @return {*} - * @param {u32} adc_id, id of adc instance - * @param {u32} adc_channel, id of adc channel - */ -void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel) -{ - - if (adc_id == FADC0_ID) - { - switch (adc_channel) - { - case FADC_CHANNEL_0: - FPinSetFunc(FIOPAD_R47, FPIN_FUNC7); /* adc0-0: func 7 */ - break; - case FADC_CHANNEL_1: - FPinSetFunc(FIOPAD_R45, FPIN_FUNC7); /* adc0-1: func 7 */ - break; - case FADC_CHANNEL_2: - FPinSetFunc(FIOPAD_N47, FPIN_FUNC7); /* adc0-2: func 7 */ - break; - case FADC_CHANNEL_3: - FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-3: func 7 */ - break; - case FADC_CHANNEL_4: - FPinSetFunc(FIOPAD_L51, FPIN_FUNC7); /* adc0-4: func 7 */ - break; - case FADC_CHANNEL_5: - FPinSetFunc(FIOPAD_J51, FPIN_FUNC7); /* adc0-5: func 7 */ - break; - case FADC_CHANNEL_6: - FPinSetFunc(FIOPAD_J41, FPIN_FUNC7); /* adc0-6: func 7 */ - break; - case FADC_CHANNEL_7: - FPinSetFunc(FIOPAD_E43, FPIN_FUNC7); /* adc0-7: func 7 */ - break; - default: - FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel); - break; - } - } - else - { - FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel); - } -} - -/** - * @name: FIOPadSetMioMux - * @msg: set iopad mux for mio - * @return {*} - * @param {u32} mio_id, instance id of i2c - */ -void FIOPadSetMioMux(u32 mio_id) -{ - switch (mio_id) - { - case FMIO0_ID: - { - FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */ - } - break; - case FMIO1_ID: - { - FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */ - } - break; - case FMIO2_ID: - { - FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */ - } - break; - case FMIO3_ID: - { - FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */ - } - break; - case FMIO4_ID: - { - FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */ - } - break; - case FMIO5_ID: - { - FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */ - } - break; - case FMIO6_ID: - { - FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */ - } - break; - case FMIO7_ID: - { - FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */ - } - break; - case FMIO8_ID: - { - FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */ - } - break; - case FMIO9_ID: - { - FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */ - } - break; - case FMIO10_ID: - { - FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */ - } - break; - case FMIO11_ID: - { - FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */ - FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */ - } - break; - case FMIO12_ID: - { - FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */ - FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */ - } - break; - case FMIO13_ID: - { - FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */ - FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */ - } - break; - case FMIO14_ID: - { - FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */ - FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */ - } - break; - case FMIO15_ID: - { - FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */ - FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */ - } - break; - default: - break; - } -} - -/** - * @name: FIOPadSetTachoMux - * @msg: set iopad mux for pwm_in - * @return {*} - * @param {u32} pwm_in_id, instance id of tacho - */ -void FIOPadSetTachoMux(u32 pwm_in_id) -{ - switch (pwm_in_id) - { - case FTACHO0_ID: - FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1); - break; - case FTACHO1_ID: - FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1); - break; - case FTACHO2_ID: - FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1); - break; - case FTACHO3_ID: - FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1); - break; - case FTACHO4_ID: - FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1); - break; - case FTACHO5_ID: - FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1); - break; - case FTACHO6_ID: - FPinSetFunc(FIOPAD_C33, FPIN_FUNC2); - break; - case FTACHO7_ID: - FPinSetFunc(FIOPAD_A37, FPIN_FUNC2); - break; - case FTACHO8_ID: - FPinSetFunc(FIOPAD_A41, FPIN_FUNC2); - break; - case FTACHO9_ID: - FPinSetFunc(FIOPAD_A43, FPIN_FUNC2); - break; - case FTACHO10_ID: - FPinSetFunc(FIOPAD_C45, FPIN_FUNC2); - break; - case FTACHO11_ID: - FPinSetFunc(FIOPAD_A29, FPIN_FUNC2); - break; - case FTACHO12_ID: - FPinSetFunc(FIOPAD_C27, FPIN_FUNC2); - break; - case FTACHO13_ID: - FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2); - break; - case FTACHO14_ID: - FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2); - break; - case FTACHO15_ID: - FPinSetFunc(FIOPAD_G55, FPIN_FUNC2); - break; - default: - break; - } -} - -/** - * @name: FIOPadSetUartMux - * @msg: set iopad mux for uart - * @return {*} - * @param {u32} uart_id, instance id of uart - */ -void FIOPadSetUartMux(u32 uart_id) -{ - switch (uart_id) - { - case FUART0_ID: - FPinSetFunc(FIOPAD_J33, FPIN_FUNC4); - FPinSetFunc(FIOPAD_J35, FPIN_FUNC4); - break; - case FUART1_ID: - FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0); - FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0); - break; - case FUART2_ID: - FPinSetFunc(FIOPAD_A43, FPIN_FUNC0); - FPinSetFunc(FIOPAD_A45, FPIN_FUNC0); - break; - case FUART3_ID: - FPinSetFunc(FIOPAD_L33, FPIN_FUNC2); - FPinSetFunc(FIOPAD_N31, FPIN_FUNC2); - break; - default: - break; - } -} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/e2000/d/fparameters.h b/bsp/phytium/libraries/standalone/board/e2000/d/fparameters.h index 7857ed48ce6..d97c0e590c7 100644 --- a/bsp/phytium/libraries/standalone/board/e2000/d/fparameters.h +++ b/bsp/phytium/libraries/standalone/board/e2000/d/fparameters.h @@ -35,17 +35,260 @@ extern "C" /************************** Constant Definitions *****************************/ #define CORE0_AFF 0x200U #define CORE1_AFF 0x201U +#define FCORE_NUM 2 #define FT_CPUS_NR 2U /* GIC offset */ - #define FT_GIC_REDISTRUBUTIOR_OFFSET 2 -/*****************************************************************************/ +/* register offset of iopad function / pull / driver strength */ +#define FIOPAD_AN55_REG0_OFFSET 0x0000U +#define FIOPAD_AW43_REG0_OFFSET 0x0004U +#define FIOPAD_AR51_REG0_OFFSET 0x0020U +#define FIOPAD_AJ51_REG0_OFFSET 0x0024U +#define FIOPAD_AL51_REG0_OFFSET 0x0028U +#define FIOPAD_AL49_REG0_OFFSET 0x002CU +#define FIOPAD_AN47_REG0_OFFSET 0x0030U +#define FIOPAD_AR47_REG0_OFFSET 0x0034U +#define FIOPAD_BA53_REG0_OFFSET 0x0038U +#define FIOPAD_BA55_REG0_OFFSET 0x003CU +#define FIOPAD_AW53_REG0_OFFSET 0x0040U +#define FIOPAD_AW55_REG0_OFFSET 0x0044U +#define FIOPAD_AU51_REG0_OFFSET 0x0048U +#define FIOPAD_AN53_REG0_OFFSET 0x004CU +#define FIOPAD_AL55_REG0_OFFSET 0x0050U +#define FIOPAD_AJ55_REG0_OFFSET 0x0054U +#define FIOPAD_AJ53_REG0_OFFSET 0x0058U +#define FIOPAD_AG55_REG0_OFFSET 0x005CU +#define FIOPAD_AG53_REG0_OFFSET 0x0060U +#define FIOPAD_AE55_REG0_OFFSET 0x0064U +#define FIOPAD_AC55_REG0_OFFSET 0x0068U +#define FIOPAD_AC53_REG0_OFFSET 0x006CU +#define FIOPAD_AR45_REG0_OFFSET 0x0070U +#define FIOPAD_BA51_REG0_OFFSET 0x0074U +#define FIOPAD_BA49_REG0_OFFSET 0x0078U +#define FIOPAD_AR55_REG0_OFFSET 0x007CU +#define FIOPAD_AU55_REG0_OFFSET 0x0080U +#define FIOPAD_AR53_REG0_OFFSET 0x0084U +#define FIOPAD_BA45_REG0_OFFSET 0x0088U +#define FIOPAD_AW51_REG0_OFFSET 0x008CU +#define FIOPAD_A31_REG0_OFFSET 0x0090U +#define FIOPAD_R53_REG0_OFFSET 0x0094U +#define FIOPAD_R55_REG0_OFFSET 0x0098U +#define FIOPAD_U55_REG0_OFFSET 0x009CU +#define FIOPAD_W55_REG0_OFFSET 0x00A0U +#define FIOPAD_U53_REG0_OFFSET 0x00A4U +#define FIOPAD_AA53_REG0_OFFSET 0x00A8U +#define FIOPAD_AA55_REG0_OFFSET 0x00ACU +#define FIOPAD_AW47_REG0_OFFSET 0x00B0U +#define FIOPAD_AU47_REG0_OFFSET 0x00B4U +#define FIOPAD_A35_REG0_OFFSET 0x00B8U +#define FIOPAD_C35_REG0_OFFSET 0x00BCU +#define FIOPAD_C33_REG0_OFFSET 0x00C0U +#define FIOPAD_A33_REG0_OFFSET 0x00C4U +#define FIOPAD_A37_REG0_OFFSET 0x00C8U +#define FIOPAD_A39_REG0_OFFSET 0x00CCU +#define FIOPAD_A41_REG0_OFFSET 0x00D0U +#define FIOPAD_C41_REG0_OFFSET 0x00D4U +#define FIOPAD_A43_REG0_OFFSET 0x00D8U +#define FIOPAD_A45_REG0_OFFSET 0x00DCU +#define FIOPAD_C45_REG0_OFFSET 0x00E0U +#define FIOPAD_A47_REG0_OFFSET 0x00E4U +#define FIOPAD_A29_REG0_OFFSET 0x00E8U +#define FIOPAD_C29_REG0_OFFSET 0x00ECU +#define FIOPAD_C27_REG0_OFFSET 0x00F0U +#define FIOPAD_A27_REG0_OFFSET 0x00F4U +#define FIOPAD_AJ49_REG0_OFFSET 0x00F8U +#define FIOPAD_AL45_REG0_OFFSET 0x00FCU +#define FIOPAD_AL43_REG0_OFFSET 0x0100U +#define FIOPAD_AN45_REG0_OFFSET 0x0104U +#define FIOPAD_AG47_REG0_OFFSET 0x0108U +#define FIOPAD_AJ47_REG0_OFFSET 0x010CU +#define FIOPAD_AG45_REG0_OFFSET 0x0110U +#define FIOPAD_AE51_REG0_OFFSET 0x0114U +#define FIOPAD_AE49_REG0_OFFSET 0x0118U +#define FIOPAD_AG51_REG0_OFFSET 0x011CU +#define FIOPAD_AJ45_REG0_OFFSET 0x0120U +#define FIOPAD_AC51_REG0_OFFSET 0x0124U +#define FIOPAD_AC49_REG0_OFFSET 0x0128U +#define FIOPAD_AE47_REG0_OFFSET 0x012CU +#define FIOPAD_W47_REG0_OFFSET 0x0130U +#define FIOPAD_W51_REG0_OFFSET 0x0134U +#define FIOPAD_W49_REG0_OFFSET 0x0138U +#define FIOPAD_U51_REG0_OFFSET 0x013CU +#define FIOPAD_U49_REG0_OFFSET 0x0140U +#define FIOPAD_AE45_REG0_OFFSET 0x0144U +#define FIOPAD_AC45_REG0_OFFSET 0x0148U +#define FIOPAD_AE43_REG0_OFFSET 0x014CU +#define FIOPAD_AA43_REG0_OFFSET 0x0150U +#define FIOPAD_AA45_REG0_OFFSET 0x0154U +#define FIOPAD_W45_REG0_OFFSET 0x0158U +#define FIOPAD_AA47_REG0_OFFSET 0x015CU +#define FIOPAD_U45_REG0_OFFSET 0x0160U +#define FIOPAD_G55_REG0_OFFSET 0x0164U +#define FIOPAD_J55_REG0_OFFSET 0x0168U +#define FIOPAD_L53_REG0_OFFSET 0x016CU +#define FIOPAD_C55_REG0_OFFSET 0x0170U +#define FIOPAD_E55_REG0_OFFSET 0x0174U +#define FIOPAD_J53_REG0_OFFSET 0x0178U +#define FIOPAD_L55_REG0_OFFSET 0x017CU +#define FIOPAD_N55_REG0_OFFSET 0x0180U +#define FIOPAD_C53_REG0_OFFSET 0x0184U +#define FIOPAD_E53_REG0_OFFSET 0x0188U +#define FIOPAD_E27_REG0_OFFSET 0x018CU +#define FIOPAD_G27_REG0_OFFSET 0x0190U +#define FIOPAD_N37_REG0_OFFSET 0x0194U +#define FIOPAD_N35_REG0_OFFSET 0x0198U +#define FIOPAD_J29_REG0_OFFSET 0x019CU +#define FIOPAD_N29_REG0_OFFSET 0x01A0U +#define FIOPAD_L29_REG0_OFFSET 0x01A4U +#define FIOPAD_N41_REG0_OFFSET 0x01A8U +#define FIOPAD_N39_REG0_OFFSET 0x01ACU +#define FIOPAD_L27_REG0_OFFSET 0x01B0U +#define FIOPAD_J27_REG0_OFFSET 0x01B4U +#define FIOPAD_J25_REG0_OFFSET 0x01B8U +#define FIOPAD_E25_REG0_OFFSET 0x01BCU +#define FIOPAD_G25_REG0_OFFSET 0x01C0U +#define FIOPAD_N23_REG0_OFFSET 0x01C4U +#define FIOPAD_L25_REG0_OFFSET 0x01C8U +#define FIOPAD_J33_REG0_OFFSET 0x01CCU +#define FIOPAD_J35_REG0_OFFSET 0x01D0U +#define FIOPAD_G37_REG0_OFFSET 0x01D4U +#define FIOPAD_E39_REG0_OFFSET 0x01D8U +#define FIOPAD_L39_REG0_OFFSET 0x01DCU +#define FIOPAD_C39_REG0_OFFSET 0x01E0U +#define FIOPAD_E37_REG0_OFFSET 0x01E4U +#define FIOPAD_L41_REG0_OFFSET 0x01E8U +#define FIOPAD_J39_REG0_OFFSET 0x01ECU +#define FIOPAD_J37_REG0_OFFSET 0x01F0U +#define FIOPAD_L35_REG0_OFFSET 0x01F4U +#define FIOPAD_E33_REG0_OFFSET 0x01F8U +#define FIOPAD_E31_REG0_OFFSET 0x01FCU +#define FIOPAD_G31_REG0_OFFSET 0x0200U +#define FIOPAD_J31_REG0_OFFSET 0x0204U +#define FIOPAD_L33_REG0_OFFSET 0x0208U +#define FIOPAD_N31_REG0_OFFSET 0x020CU +#define FIOPAD_R47_REG0_OFFSET 0x0210U +#define FIOPAD_R45_REG0_OFFSET 0x0214U +#define FIOPAD_N47_REG0_OFFSET 0x0218U +#define FIOPAD_N51_REG0_OFFSET 0x021CU +#define FIOPAD_L51_REG0_OFFSET 0x0220U +#define FIOPAD_J51_REG0_OFFSET 0x0224U +#define FIOPAD_J41_REG0_OFFSET 0x0228U +#define FIOPAD_E43_REG0_OFFSET 0x022CU +#define FIOPAD_G43_REG0_OFFSET 0x0230U +#define FIOPAD_J43_REG0_OFFSET 0x0234U +#define FIOPAD_J45_REG0_OFFSET 0x0238U +#define FIOPAD_N45_REG0_OFFSET 0x023CU +#define FIOPAD_L47_REG0_OFFSET 0x0240U +#define FIOPAD_L45_REG0_OFFSET 0x0244U +#define FIOPAD_N49_REG0_OFFSET 0x0248U +#define FIOPAD_J49_REG0_OFFSET 0x024CU +#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN55_REG0_OFFSET +#define FIOPAD_REG0_END_OFFSET FIOPAD_J49_REG0_OFFSET +/* register offset of iopad delay */ +#define FIOPAD_AJ51_REG1_OFFSET 0x1024U +#define FIOPAD_AL51_REG1_OFFSET 0x1028U +#define FIOPAD_AL49_REG1_OFFSET 0x102CU +#define FIOPAD_AN47_REG1_OFFSET 0x1030U +#define FIOPAD_AR47_REG1_OFFSET 0x1034U +#define FIOPAD_AJ53_REG1_OFFSET 0x1058U +#define FIOPAD_AG55_REG1_OFFSET 0x105CU +#define FIOPAD_AG53_REG1_OFFSET 0x1060U +#define FIOPAD_AE55_REG1_OFFSET 0x1064U +#define FIOPAD_BA51_REG1_OFFSET 0x1074U +#define FIOPAD_BA49_REG1_OFFSET 0x1078U +#define FIOPAD_AR55_REG1_OFFSET 0x107CU +#define FIOPAD_AU55_REG1_OFFSET 0x1080U +#define FIOPAD_A41_REG1_OFFSET 0x10D0U +#define FIOPAD_C41_REG1_OFFSET 0x10D4U +#define FIOPAD_A43_REG1_OFFSET 0x10D8U +#define FIOPAD_A45_REG1_OFFSET 0x10DCU +#define FIOPAD_C45_REG1_OFFSET 0x10E0U +#define FIOPAD_A47_REG1_OFFSET 0x10E4U +#define FIOPAD_A29_REG1_OFFSET 0x10E8U +#define FIOPAD_C29_REG1_OFFSET 0x10ECU +#define FIOPAD_C27_REG1_OFFSET 0x10F0U +#define FIOPAD_A27_REG1_OFFSET 0x10F4U +#define FIOPAD_AJ49_REG1_OFFSET 0x10F8U +#define FIOPAD_AL45_REG1_OFFSET 0x10FCU +#define FIOPAD_AL43_REG1_OFFSET 0x1100U +#define FIOPAD_AN45_REG1_OFFSET 0x1104U +#define FIOPAD_AG47_REG1_OFFSET 0x1108U +#define FIOPAD_AJ47_REG1_OFFSET 0x110CU +#define FIOPAD_AG45_REG1_OFFSET 0x1110U +#define FIOPAD_AE51_REG1_OFFSET 0x1114U +#define FIOPAD_AE49_REG1_OFFSET 0x1118U +#define FIOPAD_AG51_REG1_OFFSET 0x111CU +#define FIOPAD_AJ45_REG1_OFFSET 0x1120U +#define FIOPAD_AC51_REG1_OFFSET 0x1124U +#define FIOPAD_AC49_REG1_OFFSET 0x1128U +#define FIOPAD_AE47_REG1_OFFSET 0x112CU +#define FIOPAD_W47_REG1_OFFSET 0x1130U +#define FIOPAD_W49_REG1_OFFSET 0x1138U +#define FIOPAD_U51_REG1_OFFSET 0x113CU +#define FIOPAD_U49_REG1_OFFSET 0x1140U +#define FIOPAD_AE45_REG1_OFFSET 0x1144U +#define FIOPAD_AC45_REG1_OFFSET 0x1148U +#define FIOPAD_AE43_REG1_OFFSET 0x114CU +#define FIOPAD_AA43_REG1_OFFSET 0x1150U +#define FIOPAD_AA45_REG1_OFFSET 0x1154U +#define FIOPAD_W45_REG1_OFFSET 0x1158U +#define FIOPAD_AA47_REG1_OFFSET 0x115CU +#define FIOPAD_U45_REG1_OFFSET 0x1160U +#define FIOPAD_J55_REG1_OFFSET 0x1168U +#define FIOPAD_L53_REG1_OFFSET 0x116CU +#define FIOPAD_C55_REG1_OFFSET 0x1170U +#define FIOPAD_E55_REG1_OFFSET 0x1174U +#define FIOPAD_J53_REG1_OFFSET 0x1178U +#define FIOPAD_L55_REG1_OFFSET 0x117CU +#define FIOPAD_N55_REG1_OFFSET 0x1180U +#define FIOPAD_E27_REG1_OFFSET 0x118CU +#define FIOPAD_G27_REG1_OFFSET 0x1190U +#define FIOPAD_N37_REG1_OFFSET 0x1194U +#define FIOPAD_N35_REG1_OFFSET 0x1198U +#define FIOPAD_J29_REG1_OFFSET 0x119CU +#define FIOPAD_N29_REG1_OFFSET 0x11A0U +#define FIOPAD_L29_REG1_OFFSET 0x11A4U +#define FIOPAD_N41_REG1_OFFSET 0x11A8U +#define FIOPAD_N39_REG1_OFFSET 0x11ACU +#define FIOPAD_L27_REG1_OFFSET 0x11B0U +#define FIOPAD_J27_REG1_OFFSET 0x11B4U +#define FIOPAD_J25_REG1_OFFSET 0x11B8U +#define FIOPAD_E25_REG1_OFFSET 0x11BCU +#define FIOPAD_G25_REG1_OFFSET 0x11C0U +#define FIOPAD_J33_REG1_OFFSET 0x11CCU +#define FIOPAD_J35_REG1_OFFSET 0x11D0U +#define FIOPAD_G37_REG1_OFFSET 0x11D4U +#define FIOPAD_E39_REG1_OFFSET 0x11D8U +#define FIOPAD_L39_REG1_OFFSET 0x11DCU +#define FIOPAD_C39_REG1_OFFSET 0x11E0U +#define FIOPAD_E37_REG1_OFFSET 0x11E4U +#define FIOPAD_L41_REG1_OFFSET 0x11E8U +#define FIOPAD_J39_REG1_OFFSET 0x11ECU +#define FIOPAD_J37_REG1_OFFSET 0x11F0U +#define FIOPAD_L35_REG1_OFFSET 0x11F4U +#define FIOPAD_E33_REG1_OFFSET 0x11F8U +#define FIOPAD_E31_REG1_OFFSET 0x11FCU +#define FIOPAD_G31_REG1_OFFSET 0x1200U +#define FIOPAD_L51_REG1_OFFSET 0x1220U +#define FIOPAD_J51_REG1_OFFSET 0x1224U +#define FIOPAD_J41_REG1_OFFSET 0x1228U +#define FIOPAD_E43_REG1_OFFSET 0x122CU +#define FIOPAD_G43_REG1_OFFSET 0x1230U +#define FIOPAD_J43_REG1_OFFSET 0x1234U +#define FIOPAD_J45_REG1_OFFSET 0x1238U +#define FIOPAD_N45_REG1_OFFSET 0x123CU +#define FIOPAD_L47_REG1_OFFSET 0x1240U +#define FIOPAD_L45_REG1_OFFSET 0x1244U +#define FIOPAD_N49_REG1_OFFSET 0x1248U +#define FIOPAD_J49_REG1_OFFSET 0x124CU +#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ51_REG1_OFFSET +#define FIOPAD_REG1_END_OFFSET FIOPAD_J49_REG1_OFFSET #ifdef __cplusplus } diff --git a/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.c b/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.c deleted file mode 100644 index 3be376cce18..00000000000 --- a/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.c +++ /dev/null @@ -1,588 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fiopad_comm.c - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-18 08:25:29 - * Description:  This file is for io-pad function definition - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 huanghe 2021/11/5 init commit - * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec. - */ - - -/***************************** Include Files *********************************/ -#include "fparameters.h" -#include "fio.h" -#include "fkernel.h" -#include "fassert.h" -#include "fdebug.h" -#include "stdio.h" -#include "fpinctrl.h" - -/************************** Constant Definitions *****************************/ -/** @name IO PAD Control Register - */ -#define FIOPAD_X_REG0_BEG_OFFSET 0x0 /* 上下拉/驱动能力/复用功能配置 */ -#define FIOPAD_X_REG0_END_OFFSET 0x24c - -#define FIOPAD_X_REG1_BEG_OFFSET 0x1024 /* 输入/输出延时配置 */ -#define FIOPAD_X_REG1_END_OFFSET 0x124c - -/** @name X_reg0 Register - */ -#define FIOPAD_X_REG0_PULL_MASK GENMASK(9, 8) /* 上下拉配置 */ -#define FIOPAD_X_REG0_PULL_GET(x) GET_REG32_BITS((x), 9, 8) -#define FIOPAD_X_REG0_PULL_SET(x) SET_REG32_BITS((x), 9, 8) - -#define FIOPAD_X_REG0_DRIVE_MASK GENMASK(7, 4) /* 驱动能力配置 */ -#define FIOPAD_X_REG0_DRIVE_GET(x) GET_REG32_BITS((x), 7, 4) -#define FIOPAD_X_REG0_DRIVE_SET(x) SET_REG32_BITS((x), 7, 4) - -#define FIOPAD_X_REG0_FUNC_MASK GENMASK(2, 0) /* 引脚复用配置 */ -#define FIOPAD_X_REG0_FUNC_GET(x) GET_REG32_BITS((x), 2, 0) -#define FIOPAD_X_REG0_FUNC_SET(x) SET_REG32_BITS((x), 2, 0) - -/** @name X_reg1 Register - */ -#define FIOPAD_X_REG1_OUT_DELAY_EN BIT(8) -#define FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK GENMASK(11, 9) -#define FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(x) GET_REG32_BITS((x), 11, 9) /* 延时精调 */ -#define FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(x) SET_REG32_BITS((x), 11, 9) -#define FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK GENMASK(14, 12) -#define FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(x) GET_REG32_BITS((x), 14, 12) /* 延时粗调 */ -#define FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(x) SET_REG32_BITS((x), 14, 12) - -#define FIOPAD_X_REG1_IN_DELAY_EN BIT(0) -#define FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK GENMASK(3, 1) -#define FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(x) GET_REG32_BITS((x), 3, 1) /* 延时精调 */ -#define FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(x) SET_REG32_BITS((x), 3, 1) -#define FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK GENMASK(6, 4) -#define FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(x) GET_REG32_BITS((x), 6, 4) /* 延时粗调 */ -#define FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(x) SET_REG32_BITS((x), 6, 4) - -#define FIOPAD_DELAY_MAX 15 - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -static inline u32 FIOPadRead(FPinIndex pin) -{ - return FtIn32(FIOPAD_BASE_ADDR + pin.reg_off); -} - -static inline void FIOPadWrite(FPinIndex pin, u32 reg_val) -{ - FtOut32(FIOPAD_BASE_ADDR + pin.reg_off, reg_val); - return; -} - -#define FIOPAD_ASSERT_REG0_OFF(pin) FASSERT_MSG((FIOPAD_X_REG0_END_OFFSET >= pin.reg_off), "invalid reg0 offset @0x%x\r\n", (pin.reg_off)) -#define FIOPAD_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d\r\n", (func)) -#define FIOPAD_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d\r\n", (pull)) -#define FIOPAD_ASSERT_DRIVE(drive) FASSERT_MSG((drive < FPIN_NUM_OF_DRIVE), "invalid pull as %d\r\n", (drive)) - -#define FIOPAD_ASSERT_REG1_OFF(pin) FASSERT_MSG(((FIOPAD_X_REG1_BEG_OFFSET <= pin.reg_off) && (FIOPAD_X_REG1_END_OFFSET >= pin.reg_off)), "invalid reg1 offset @0x%x\r\n", (pin.reg_off)) -#define FIOPAD_ASSERT_DELAY(delay) FASSERT_MSG((delay < FPIN_NUM_OF_DELAY), "invalid delay as %d\r\n", (delay)) - -#define FIOPAD_DEBUG_TAG "FIOPAD" -#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) - -/************************** Function Prototypes ******************************/ -/** - * @name: FPinGetFunc - * @msg: 获取IO引脚当前的复用功能 - * @return {FPinFunc} 当前的复用功能 - * @param {FPinIndex} pin IO引脚索引 - * @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值 - */ -FPinFunc FPinGetFunc(const FPinIndex pin) -{ - FIOPAD_ASSERT_REG0_OFF(pin); - u32 func = FIOPAD_X_REG0_FUNC_GET(FIOPadRead(pin)); - FIOPAD_ASSERT_FUNC(func); - return (FPinFunc)func; -} - -/** - * @name: FPinSetFunc - * @msg: 设置IO引脚复用功能 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @param {FPinFunc} func IO复用功能 - * @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值 - */ -void FPinSetFunc(const FPinIndex pin, FPinFunc func) -{ - FIOPAD_ASSERT_REG0_OFF(pin); - FIOPAD_ASSERT_FUNC(func); - u32 reg_val = FIOPadRead(pin); - u32 test_val = 0; - - reg_val &= ~FIOPAD_X_REG0_FUNC_MASK; - reg_val |= FIOPAD_X_REG0_FUNC_SET(func); - - FIOPadWrite(pin, reg_val); - - test_val = FIOPadRead(pin); - - if (reg_val != test_val) - { - FIOPAD_ERROR("ERROR: FIOPad write is failed ,pin is %x\n, 0x%x != 0x%x", - pin.reg_off, reg_val, test_val); - } - - return; -} - -/** - * @name: FPinGetDrive - * @msg: 获取IO引脚的驱动能力 - * @return {FPinDrive} 引脚的当前的驱动能力 - * @param {FPinIndex} pin IO引脚索引 - */ -FPinDrive FPinGetDrive(const FPinIndex pin) -{ - FIOPAD_ASSERT_REG0_OFF(pin); - u32 drive = FIOPAD_X_REG0_DRIVE_GET(FIOPadRead(pin)); - FIOPAD_ASSERT_DRIVE(drive); - return (FPinDrive)drive; -} - -/** - * @name: FPinSetDrive - * @msg: 设置IO引脚的驱动能力 - * @return {*} - * @param {FPinIndex} pin, IO引脚索引 - * @param {FPinDrive} drive, 引脚驱动能力设置 - */ -void FPinSetDrive(const FPinIndex pin, FPinDrive drive) -{ - FIOPAD_ASSERT_REG0_OFF(pin); - FIOPAD_ASSERT_DRIVE(drive); - u32 reg_val = FIOPadRead(pin); - - reg_val &= ~FIOPAD_X_REG0_DRIVE_MASK; - reg_val |= FIOPAD_X_REG0_DRIVE_SET(drive); - - FIOPadWrite(pin, reg_val); - return; -} - -void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull, FPinDrive *drive) -{ - FIOPAD_ASSERT_REG0_OFF(pin); - u32 reg_val = FIOPadRead(pin); - - if (func) - { - *func = FIOPAD_X_REG0_FUNC_GET(reg_val); - } - - if (pull) - { - *pull = FIOPAD_X_REG0_PULL_GET(reg_val); - } - - if (drive) - { - *drive = FIOPAD_X_REG0_DRIVE_GET(reg_val); - } - - return; -} - -void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull, FPinDrive drive) -{ - FIOPAD_ASSERT_REG0_OFF(pin); - u32 reg_val = FIOPadRead(pin); - - reg_val &= ~FIOPAD_X_REG0_FUNC_MASK; - reg_val |= FIOPAD_X_REG0_FUNC_SET(func); - - reg_val &= ~FIOPAD_X_REG0_PULL_MASK; - reg_val |= FIOPAD_X_REG0_PULL_SET(pull); - - reg_val &= ~FIOPAD_X_REG0_DRIVE_MASK; - reg_val |= FIOPAD_X_REG0_DRIVE_SET(drive); - - FIOPadWrite(pin, reg_val); - return; -} - -/** - * @name: FPinGetPull - * @msg: 获取IO引脚当前的上下拉设置 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @note 参考编程手册，使用 FIOPAD_INDEX 宏定义index的值 - */ -FPinPull FPinGetPull(const FPinIndex pin) -{ - FIOPAD_ASSERT_REG0_OFF(pin); - u32 pull = FIOPAD_X_REG0_PULL_GET(FIOPadRead(pin)); - FIOPAD_ASSERT_PULL(pull); - return (FPinPull)pull; -} - -/** - * @name: FPinSetPull - * @msg: 设置IO引脚当前的上下拉 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @param {FPinPull} pull 上下拉设置 - */ -void FPinSetPull(const FPinIndex pin, FPinPull pull) -{ - FIOPAD_ASSERT_REG0_OFF(pin); - FIOPAD_ASSERT_PULL(pull); - - u32 reg_val = FIOPadRead(pin); - - reg_val &= ~FIOPAD_X_REG0_PULL_MASK; - reg_val |= FIOPAD_X_REG0_PULL_SET(pull); - - FIOPadWrite(pin, reg_val); - return; -} - -/** - * @name: FPinGetDelay - * @msg: 获取IO引脚当前的延时设置 - * @return {FPinDelay} 当前的延时设置 - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - * @param {FPinDelayType} type 精调/粗调延时 - */ -FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type) -{ - FIOPAD_ASSERT_REG1_OFF(pin); - const u32 reg_val = FIOPadRead(pin); - u8 delay = 0; - - if (FPIN_OUTPUT_DELAY == dir) - { - if (FPIN_DELAY_FINE_TUNING == type) - { - delay = FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(reg_val); - } - else if (FPIN_DELAY_COARSE_TUNING == type) - { - delay = FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(reg_val); - } - else - { - FASSERT(0); - } - } - else if (FPIN_INPUT_DELAY == dir) - { - if (FPIN_DELAY_FINE_TUNING == type) - { - delay = FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(reg_val); - } - else if (FPIN_DELAY_COARSE_TUNING == type) - { - delay = FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(reg_val); - } - else - { - FASSERT(0); - } - } - else - { - FASSERT(0); - } - - FIOPAD_ASSERT_DELAY(delay); - return (FPinDelay)delay; -} - -/** - * @name: FPinGetDelayEn - * @msg: 获取IO引脚当前的延时使能标志位 - * @return {*} - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - */ -boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir) -{ - FIOPAD_ASSERT_REG1_OFF(pin); - const u32 reg_val = FIOPadRead(pin); - boolean enabled = FALSE; - - if (FPIN_OUTPUT_DELAY == dir) - { - if (FIOPAD_X_REG1_OUT_DELAY_EN & reg_val) - { - enabled = TRUE; - } - else - { - enabled = FALSE; - } - } - else if (FPIN_INPUT_DELAY == dir) - { - if (FIOPAD_X_REG1_IN_DELAY_EN & reg_val) - { - enabled = TRUE; - } - else - { - enabled = FALSE; - } - } - else - { - FASSERT(0); - } - - return enabled; -} - -/** - * @name: FPinSetDelay - * @msg: 设置IO引脚延时 - * @return {*} - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - * @param {FPinDelayType} type 精调/粗调延时 - * @param {FPinDelay} delay 延时设置 - */ -void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay) -{ - FIOPAD_ASSERT_REG1_OFF(pin); - FIOPAD_ASSERT_DELAY(delay); - u32 reg_val = FIOPadRead(pin); - - if (FPIN_OUTPUT_DELAY == dir) - { - if (FPIN_DELAY_FINE_TUNING == type) - { - reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK; - reg_val |= FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(delay); - } - else if (FPIN_DELAY_COARSE_TUNING == type) - { - reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK; - reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(delay); - } - else - { - FASSERT(0); - } - } - else if (FPIN_INPUT_DELAY == dir) - { - if (FPIN_DELAY_FINE_TUNING == type) - { - reg_val &= ~FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK; - reg_val |= FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(delay); - } - else if (FPIN_DELAY_COARSE_TUNING == type) - { - reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK; - reg_val |= FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(delay); - } - else - { - FASSERT(0); - } - } - else - { - FASSERT(0); - } - - FIOPadWrite(pin, reg_val); - return; -} - -/** - * @name: FPinSetDelayEn - * @msg: 使能/去使能IO引脚延时 - * @return {*} - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - * @param {boolean} enable TRUE: 使能, FALSE: 去使能 - */ -void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable) -{ - FIOPAD_ASSERT_REG1_OFF(pin); - u32 reg_val = FIOPadRead(pin); - - if (FPIN_OUTPUT_DELAY == dir) - { - if (enable) - { - reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN; - } - else - { - reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN; - } - } - else if (FPIN_INPUT_DELAY == dir) - { - if (enable) - { - reg_val |= FIOPAD_X_REG1_IN_DELAY_EN; - } - else - { - reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN; - } - } - else - { - FASSERT(0); - } - - FIOPadWrite(pin, reg_val); - return; -} - - -/** - * @name: FPinSetDelayConfig - * @msg: Update and enable common IO pin delay config - * @return {NONE} - * @param {FPinIndex} pin, IO pin index - * @param {FPinDelayIOType} in_out_type, Select the input and output types ， - * @param {FPinDelay} roungh_delay, delay rough setting - * @param {FPinDelay} delicate_delay, delay delicate setting - * @param {boolean} enable, enable delay - */ -void FPinSetDelayConfig(const FPinIndex pin, FPinDelayIOType in_out_type, FPinDelay roungh_delay, FPinDelay delicate_delay, boolean enable) -{ - FIOPAD_ASSERT_REG1_OFF(pin); - u32 reg_val = FIOPadRead(pin); - - if (in_out_type == FPIN_DELAY_IN_TYPE) - { - reg_val = FIOPadRead(pin); - - /* update delicate input delay */ - reg_val &= ~FIOPAD_X_REG1_IN_DELAY_DELICATE_MASK; - reg_val |= FIOPAD_X_REG1_IN_DELAY_DELICATE_SET(delicate_delay); - - /* update rough input delay */ - reg_val &= ~FIOPAD_X_REG1_IN_DELAY_ROUGH_MASK; - reg_val |= FIOPAD_X_REG1_IN_DELAY_ROUGH_SET(roungh_delay); - - /* enable input delay */ - if (enable) - { - reg_val |= FIOPAD_X_REG1_IN_DELAY_EN; - } - else - { - reg_val &= ~FIOPAD_X_REG1_IN_DELAY_EN; - } - } - else - { - /* update delicate output delay */ - reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_DELICATE_MASK; - reg_val |= FIOPAD_X_REG1_OUT_DELAY_DELICATE_SET(delicate_delay); - - /* update rough output delay */ - reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_ROUGH_MASK; - reg_val |= FIOPAD_X_REG1_OUT_DELAY_ROUGH_SET(roungh_delay); - - /* enable output delay */ - if (enable) - { - reg_val |= FIOPAD_X_REG1_OUT_DELAY_EN; - } - else - { - reg_val &= ~FIOPAD_X_REG1_OUT_DELAY_EN; - } - } - - FIOPadWrite(pin, reg_val); - return; -} - -/** - * @name: FPinGetDelayConfig - * @msg: Get current common IO pin delay config - * @return {NONE} - * @param {FPinIndex} pin, IO pin index - * @param {FPinDelay} *in_roungh_delay, input delay rough setting (输入粗调) - * @param {FPinDelay} *in_delicate_delay, input delay delicate setting (输入精调) - * @param {FPinDelay} *out_roungh_delay, output delay rough setting (输出粗调) - * @param {FPinDelay} *out_delicate_delay, output delay delicate setting (输出精调) - */ -void FPinGetDelayConfig(const FPinIndex pin, FPinDelay *in_roungh_delay, FPinDelay *in_delicate_delay, - FPinDelay *out_roungh_delay, FPinDelay *out_delicate_delay) -{ - FIOPAD_ASSERT_REG1_OFF(pin); - u32 reg_val = FIOPadRead(pin); - - if (out_delicate_delay) - { - *out_delicate_delay = FIOPAD_X_REG1_OUT_DELAY_DELICATE_GET(reg_val); - } - - if (out_roungh_delay) - { - *out_roungh_delay = FIOPAD_X_REG1_OUT_DELAY_ROUGH_GET(reg_val); - } - - if (in_delicate_delay) - { - *in_delicate_delay = FIOPAD_X_REG1_IN_DELAY_DELICATE_GET(reg_val); - } - - if (in_roungh_delay) - { - *in_roungh_delay = FIOPAD_X_REG1_IN_DELAY_ROUGH_GET(reg_val); - } - - return; -} - -/** - * @name: FIOPadDumpPadFunc - * @msg: print information of all iopad - * @return {*} - */ -void FIOPadDumpPadFunc(void) -{ - uintptr beg_off = FIOPAD_0_FUNC_OFFSET; - uintptr end_off = FIOPAD_147_FUNC_OFFSET; - uintptr off; - FPinIndex pin; - const char *pull_state[FPIN_NUM_OF_PULL] = {"none", "down", "up"}; - - FIOPAD_DEBUG("Pad Func Info..."); - for (off = beg_off; off <= end_off; off += 4U) - { - pin.reg_off = off; - FIOPAD_DEBUG(" [0x%x] func: %d, ds: %d, pull: %s ", - pin.reg_off, - FPinGetFunc(pin), - FPinGetDrive(pin), - pull_state[FPinGetPull(pin)]); - } -} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.h b/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.h deleted file mode 100644 index 8251caee75e..00000000000 --- a/bsp/phytium/libraries/standalone/board/e2000/fiopad_comm.h +++ /dev/null @@ -1,310 +0,0 @@ -#ifndef BOARD_E2000_FIOPAD_COMMON_H -#define BOARD_E2000_FIOPAD_COMMON_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/***************************** Include Files *********************************/ -#include "ftypes.h" - -/**************************** Type Definitions *******************************/ - -/************************** Constant Definitions *****************************/ - -/************************** Variable Definitions *****************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -#define FIOPAD_INDEX(offset) \ - { \ - /* reg_off */ (offset), \ - /* reg_bit */ (0) \ - } - -/*****************************************************************************/ -/* register offset of iopad function / pull / driver strength */ -#define FIOPAD_0_FUNC_OFFSET 0x0000U -#define FIOPAD_2_FUNC_OFFSET 0x0004U -#define FIOPAD_3_FUNC_OFFSET 0x0008U -#define FIOPAD_4_FUNC_OFFSET 0x000CU -#define FIOPAD_5_FUNC_OFFSET 0x0010U -#define FIOPAD_6_FUNC_OFFSET 0x0014U -#define FIOPAD_7_FUNC_OFFSET 0x0018U -#define FIOPAD_8_FUNC_OFFSET 0x001CU -#define FIOPAD_9_FUNC_OFFSET 0x0020U -#define FIOPAD_10_FUNC_OFFSET 0x0024U -#define FIOPAD_11_FUNC_OFFSET 0x0028U -#define FIOPAD_12_FUNC_OFFSET 0x002CU -#define FIOPAD_13_FUNC_OFFSET 0x0030U -#define FIOPAD_14_FUNC_OFFSET 0x0034U -#define FIOPAD_15_FUNC_OFFSET 0x0038U -#define FIOPAD_16_FUNC_OFFSET 0x003CU -#define FIOPAD_17_FUNC_OFFSET 0x0040U -#define FIOPAD_18_FUNC_OFFSET 0x0044U -#define FIOPAD_19_FUNC_OFFSET 0x0048U -#define FIOPAD_20_FUNC_OFFSET 0x004CU -#define FIOPAD_21_FUNC_OFFSET 0x0050U -#define FIOPAD_22_FUNC_OFFSET 0x0054U -#define FIOPAD_23_FUNC_OFFSET 0x0058U -#define FIOPAD_24_FUNC_OFFSET 0x005CU -#define FIOPAD_25_FUNC_OFFSET 0x0060U -#define FIOPAD_26_FUNC_OFFSET 0x0064U -#define FIOPAD_27_FUNC_OFFSET 0x0068U -#define FIOPAD_28_FUNC_OFFSET 0x006CU -#define FIOPAD_31_FUNC_OFFSET 0x0070U -#define FIOPAD_32_FUNC_OFFSET 0x0074U -#define FIOPAD_33_FUNC_OFFSET 0x0078U -#define FIOPAD_34_FUNC_OFFSET 0x007CU -#define FIOPAD_35_FUNC_OFFSET 0x0080U -#define FIOPAD_36_FUNC_OFFSET 0x0084U -#define FIOPAD_37_FUNC_OFFSET 0x0088U -#define FIOPAD_38_FUNC_OFFSET 0x008CU -#define FIOPAD_39_FUNC_OFFSET 0x0090U -#define FIOPAD_40_FUNC_OFFSET 0x0094U -#define FIOPAD_41_FUNC_OFFSET 0x0098U -#define FIOPAD_42_FUNC_OFFSET 0x009CU -#define FIOPAD_43_FUNC_OFFSET 0x00A0U -#define FIOPAD_44_FUNC_OFFSET 0x00A4U -#define FIOPAD_45_FUNC_OFFSET 0x00A8U -#define FIOPAD_46_FUNC_OFFSET 0x00ACU -#define FIOPAD_47_FUNC_OFFSET 0x00B0U -#define FIOPAD_48_FUNC_OFFSET 0x00B4U -#define FIOPAD_49_FUNC_OFFSET 0x00B8U -#define FIOPAD_50_FUNC_OFFSET 0x00BCU -#define FIOPAD_51_FUNC_OFFSET 0x00C0U -#define FIOPAD_52_FUNC_OFFSET 0x00C4U -#define FIOPAD_53_FUNC_OFFSET 0x00C8U -#define FIOPAD_54_FUNC_OFFSET 0x00CCU -#define FIOPAD_55_FUNC_OFFSET 0x00D0U -#define FIOPAD_56_FUNC_OFFSET 0x00D4U -#define FIOPAD_57_FUNC_OFFSET 0x00D8U -#define FIOPAD_58_FUNC_OFFSET 0x00DCU -#define FIOPAD_59_FUNC_OFFSET 0x00E0U -#define FIOPAD_60_FUNC_OFFSET 0x00E4U -#define FIOPAD_61_FUNC_OFFSET 0x00E8U -#define FIOPAD_62_FUNC_OFFSET 0x00ECU -#define FIOPAD_63_FUNC_OFFSET 0x00F0U -#define FIOPAD_64_FUNC_OFFSET 0x00F4U -#define FIOPAD_65_FUNC_OFFSET 0x00F8U -#define FIOPAD_66_FUNC_OFFSET 0x00FCU -#define FIOPAD_67_FUNC_OFFSET 0x0100U -#define FIOPAD_68_FUNC_OFFSET 0x0104U -#define FIOPAD_148_FUNC_OFFSET 0x0108U -#define FIOPAD_69_FUNC_OFFSET 0x010CU -#define FIOPAD_70_FUNC_OFFSET 0x0110U -#define FIOPAD_71_FUNC_OFFSET 0x0114U -#define FIOPAD_72_FUNC_OFFSET 0x0118U -#define FIOPAD_73_FUNC_OFFSET 0x011CU -#define FIOPAD_74_FUNC_OFFSET 0x0120U -#define FIOPAD_75_FUNC_OFFSET 0x0124U -#define FIOPAD_76_FUNC_OFFSET 0x0128U -#define FIOPAD_77_FUNC_OFFSET 0x012CU -#define FIOPAD_78_FUNC_OFFSET 0x0130U -#define FIOPAD_79_FUNC_OFFSET 0x0134U -#define FIOPAD_80_FUNC_OFFSET 0x0138U -#define FIOPAD_81_FUNC_OFFSET 0x013CU -#define FIOPAD_82_FUNC_OFFSET 0x0140U -#define FIOPAD_83_FUNC_OFFSET 0x0144U -#define FIOPAD_84_FUNC_OFFSET 0x0148U -#define FIOPAD_85_FUNC_OFFSET 0x014CU -#define FIOPAD_86_FUNC_OFFSET 0x0150U -#define FIOPAD_87_FUNC_OFFSET 0x0154U -#define FIOPAD_88_FUNC_OFFSET 0x0158U -#define FIOPAD_89_FUNC_OFFSET 0x015CU -#define FIOPAD_90_FUNC_OFFSET 0x0160U -#define FIOPAD_91_FUNC_OFFSET 0x0164U -#define FIOPAD_92_FUNC_OFFSET 0x0168U -#define FIOPAD_93_FUNC_OFFSET 0x016CU -#define FIOPAD_94_FUNC_OFFSET 0x0170U -#define FIOPAD_95_FUNC_OFFSET 0x0174U -#define FIOPAD_96_FUNC_OFFSET 0x0178U -#define FIOPAD_97_FUNC_OFFSET 0x017CU -#define FIOPAD_98_FUNC_OFFSET 0x0180U -#define FIOPAD_29_FUNC_OFFSET 0x0184U -#define FIOPAD_30_FUNC_OFFSET 0x0188U -#define FIOPAD_99_FUNC_OFFSET 0x018CU -#define FIOPAD_100_FUNC_OFFSET 0x0190U -#define FIOPAD_101_FUNC_OFFSET 0x0194U -#define FIOPAD_102_FUNC_OFFSET 0x0198U -#define FIOPAD_103_FUNC_OFFSET 0x019CU -#define FIOPAD_104_FUNC_OFFSET 0x01A0U -#define FIOPAD_105_FUNC_OFFSET 0x01A4U -#define FIOPAD_106_FUNC_OFFSET 0x01A8U -#define FIOPAD_107_FUNC_OFFSET 0x01ACU -#define FIOPAD_108_FUNC_OFFSET 0x01B0U -#define FIOPAD_109_FUNC_OFFSET 0x01B4U -#define FIOPAD_110_FUNC_OFFSET 0x01B8U -#define FIOPAD_111_FUNC_OFFSET 0x01BCU -#define FIOPAD_112_FUNC_OFFSET 0x01C0U -#define FIOPAD_113_FUNC_OFFSET 0x01C4U -#define FIOPAD_114_FUNC_OFFSET 0x01C8U -#define FIOPAD_115_FUNC_OFFSET 0x01CCU -#define FIOPAD_116_FUNC_OFFSET 0x01D0U -#define FIOPAD_117_FUNC_OFFSET 0x01D4U -#define FIOPAD_118_FUNC_OFFSET 0x01D8U -#define FIOPAD_119_FUNC_OFFSET 0x01DCU -#define FIOPAD_120_FUNC_OFFSET 0x01E0U -#define FIOPAD_121_FUNC_OFFSET 0x01E4U -#define FIOPAD_122_FUNC_OFFSET 0x01E8U -#define FIOPAD_123_FUNC_OFFSET 0x01ECU -#define FIOPAD_124_FUNC_OFFSET 0x01F0U -#define FIOPAD_125_FUNC_OFFSET 0x01F4U -#define FIOPAD_126_FUNC_OFFSET 0x01F8U -#define FIOPAD_127_FUNC_OFFSET 0x01FCU -#define FIOPAD_128_FUNC_OFFSET 0x0200U -#define FIOPAD_129_FUNC_OFFSET 0x0204U -#define FIOPAD_130_FUNC_OFFSET 0x0208U -#define FIOPAD_131_FUNC_OFFSET 0x020CU -#define FIOPAD_132_FUNC_OFFSET 0x0210U -#define FIOPAD_133_FUNC_OFFSET 0x0214U -#define FIOPAD_134_FUNC_OFFSET 0x0218U -#define FIOPAD_135_FUNC_OFFSET 0x021CU -#define FIOPAD_136_FUNC_OFFSET 0x0220U -#define FIOPAD_137_FUNC_OFFSET 0x0224U -#define FIOPAD_138_FUNC_OFFSET 0x0228U -#define FIOPAD_139_FUNC_OFFSET 0x022CU -#define FIOPAD_140_FUNC_OFFSET 0x0230U -#define FIOPAD_141_FUNC_OFFSET 0x0234U -#define FIOPAD_142_FUNC_OFFSET 0x0238U -#define FIOPAD_143_FUNC_OFFSET 0x023CU -#define FIOPAD_144_FUNC_OFFSET 0x0240U -#define FIOPAD_145_FUNC_OFFSET 0x0244U -#define FIOPAD_146_FUNC_OFFSET 0x0248U -#define FIOPAD_147_FUNC_OFFSET 0x024CU - -/* register offset of iopad delay */ -#define FIOPAD_10_DELAY_OFFSET 0x1024U -#define FIOPAD_11_DELAY_OFFSET 0x1028U -#define FIOPAD_12_DELAY_OFFSET 0x102CU -#define FIOPAD_13_DELAY_OFFSET 0x1030U -#define FIOPAD_14_DELAY_OFFSET 0x1034U -#define FIOPAD_23_DELAY_OFFSET 0x1058U -#define FIOPAD_24_DELAY_OFFSET 0x105CU -#define FIOPAD_25_DELAY_OFFSET 0x1060U -#define FIOPAD_26_DELAY_OFFSET 0x1064U -#define FIOPAD_32_DELAY_OFFSET 0x1074U -#define FIOPAD_33_DELAY_OFFSET 0x1078U -#define FIOPAD_34_DELAY_OFFSET 0x107CU -#define FIOPAD_35_DELAY_OFFSET 0x1080U -#define FIOPAD_55_DELAY_OFFSET 0x10D0U -#define FIOPAD_56_DELAY_OFFSET 0x10D4U -#define FIOPAD_57_DELAY_OFFSET 0x10D8U -#define FIOPAD_58_DELAY_OFFSET 0x10DCU -#define FIOPAD_59_DELAY_OFFSET 0x10E0U -#define FIOPAD_60_DELAY_OFFSET 0x10E4U -#define FIOPAD_61_DELAY_OFFSET 0x10E8U -#define FIOPAD_62_DELAY_OFFSET 0x10ECU -#define FIOPAD_63_DELAY_OFFSET 0x10F0U -#define FIOPAD_64_DELAY_OFFSET 0x10F4U -#define FIOPAD_65_DELAY_OFFSET 0x10F8U -#define FIOPAD_66_DELAY_OFFSET 0x10FCU -#define FIOPAD_67_DELAY_OFFSET 0x1100U -#define FIOPAD_68_DELAY_OFFSET 0x1104U -#define FIOPAD_148_DELAY_OFFSET 0x1108U -#define FIOPAD_69_DELAY_OFFSET 0x110CU -#define FIOPAD_70_DELAY_OFFSET 0x1110U -#define FIOPAD_71_DELAY_OFFSET 0x1114U -#define FIOPAD_72_DELAY_OFFSET 0x1118U -#define FIOPAD_73_DELAY_OFFSET 0x111CU -#define FIOPAD_74_DELAY_OFFSET 0x1120U -#define FIOPAD_75_DELAY_OFFSET 0x1124U -#define FIOPAD_76_DELAY_OFFSET 0x1128U -#define FIOPAD_77_DELAY_OFFSET 0x112CU -#define FIOPAD_78_DELAY_OFFSET 0x1130U -#define FIOPAD_80_DELAY_OFFSET 0x1138U -#define FIOPAD_81_DELAY_OFFSET 0x113CU -#define FIOPAD_82_DELAY_OFFSET 0x1140U -#define FIOPAD_83_DELAY_OFFSET 0x1144U -#define FIOPAD_84_DELAY_OFFSET 0x1148U -#define FIOPAD_85_DELAY_OFFSET 0x114CU -#define FIOPAD_86_DELAY_OFFSET 0x1150U -#define FIOPAD_87_DELAY_OFFSET 0x1154U -#define FIOPAD_88_DELAY_OFFSET 0x1158U -#define FIOPAD_89_DELAY_OFFSET 0x115CU -#define FIOPAD_90_DELAY_OFFSET 0x1160U -#define FIOPAD_92_DELAY_OFFSET 0x1168U -#define FIOPAD_93_DELAY_OFFSET 0x116CU -#define FIOPAD_94_DELAY_OFFSET 0x1170U -#define FIOPAD_95_DELAY_OFFSET 0x1174U -#define FIOPAD_96_DELAY_OFFSET 0x1178U -#define FIOPAD_97_DELAY_OFFSET 0x117CU -#define FIOPAD_98_DELAY_OFFSET 0x1180U -#define FIOPAD_99_DELAY_OFFSET 0x118CU -#define FIOPAD_100_DELAY_OFFSET 0x1190U -#define FIOPAD_101_DELAY_OFFSET 0x1194U -#define FIOPAD_102_DELAY_OFFSET 0x1198U -#define FIOPAD_103_DELAY_OFFSET 0x119CU -#define FIOPAD_104_DELAY_OFFSET 0x11A0U -#define FIOPAD_105_DELAY_OFFSET 0x11A4U -#define FIOPAD_106_DELAY_OFFSET 0x11A8U -#define FIOPAD_107_DELAY_OFFSET 0x11ACU -#define FIOPAD_108_DELAY_OFFSET 0x11B0U -#define FIOPAD_109_DELAY_OFFSET 0x11B4U -#define FIOPAD_110_DELAY_OFFSET 0x11B8U -#define FIOPAD_111_DELAY_OFFSET 0x11BCU -#define FIOPAD_112_DELAY_OFFSET 0x11C0U -#define FIOPAD_115_DELAY_OFFSET 0x11CCU -#define FIOPAD_116_DELAY_OFFSET 0x11D0U -#define FIOPAD_117_DELAY_OFFSET 0x11D4U -#define FIOPAD_118_DELAY_OFFSET 0x11D8U -#define FIOPAD_119_DELAY_OFFSET 0x11DCU -#define FIOPAD_120_DELAY_OFFSET 0x11E0U -#define FIOPAD_121_DELAY_OFFSET 0x11E4U -#define FIOPAD_122_DELAY_OFFSET 0x11E8U -#define FIOPAD_123_DELAY_OFFSET 0x11ECU -#define FIOPAD_124_DELAY_OFFSET 0x11F0U -#define FIOPAD_125_DELAY_OFFSET 0x11F4U -#define FIOPAD_126_DELAY_OFFSET 0x11F8U -#define FIOPAD_127_DELAY_OFFSET 0x11FCU -#define FIOPAD_128_DELAY_OFFSET 0x1200U -#define FIOPAD_136_DELAY_OFFSET 0x1220U -#define FIOPAD_137_DELAY_OFFSET 0x1224U -#define FIOPAD_138_DELAY_OFFSET 0x1228U -#define FIOPAD_139_DELAY_OFFSET 0x122CU -#define FIOPAD_140_DELAY_OFFSET 0x1230U -#define FIOPAD_141_DELAY_OFFSET 0x1234U -#define FIOPAD_142_DELAY_OFFSET 0x1238U -#define FIOPAD_143_DELAY_OFFSET 0x123CU -#define FIOPAD_144_DELAY_OFFSET 0x1240U -#define FIOPAD_145_DELAY_OFFSET 0x1244U -#define FIOPAD_146_DELAY_OFFSET 0x1248U -#define FIOPAD_147_DELAY_OFFSET 0x124CU - -/************************** Function Prototypes ******************************/ -/* set iopad mux for spim */ -void FIOPadSetSpimMux(u32 spim_id); - -/* set iopad mux for gpio */ -void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id); - -/* set iopad mux for mio */ -void FIOPadSetMioMux(u32 mio_id); - -/* print information of all iopad */ -void FIOPadDumpPadFunc(void); - -/* set iopad mux for can */ -void FIOPadSetCanMux(u32 can_id); - -/* set iopad mux for qspi */ -void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id); - -/* set iopad mux for pwm */ -void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel); - -/* set iopad mux for adc */ -void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel); - -/* set iopad mux for tacho*/ -void FIOPadSetTachoMux(u32 pwm_in_id); - -/* set iopad mux for uart*/ -void FIOPadSetUartMux(u32 uart_id); - -#ifdef __cplusplus -} - -#endif - -#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/e2000/fparameters_comm.h b/bsp/phytium/libraries/standalone/board/e2000/fparameters_comm.h index 77076546548..eeecdf778e5 100644 --- a/bsp/phytium/libraries/standalone/board/e2000/fparameters_comm.h +++ b/bsp/phytium/libraries/standalone/board/e2000/fparameters_comm.h @@ -36,7 +36,7 @@ extern "C" /************************** Constant Definitions *****************************/ /* CACHE */ -#define CACHE_LINE_ADDR_MASK 0x3FU +#define CACHE_LINE_ADDR_MASK 0x3FUL #define CACHE_LINE 64U /* DEVICE Register Address */ @@ -141,12 +141,6 @@ enum #define FSCMI_MAX_PERF_DOMAINS 3 #define FSCMI_MAX_OPPS 4 -/* Generic Timer */ -#define GENERIC_TIMER_CLK_FREQ_MHZ 48U -#define GENERIC_TIMER_NS_IRQ_NUM 30U -#define GENERIC_TIMER_NS_CLK_FREQ 2000000U -#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ - /* UART */ #define FUART_NUM 4U #define FUART_REG_LENGTH 0x18000U @@ -312,6 +306,18 @@ enum #define FXMAC_PHY_MAX_NUM 32U +#define FXMAC_CLK_TYPE_0 + +#if !defined(__ASSEMBLER__) +/* IOPAD */ +enum +{ + FIOPAD0_ID = 0, + + FIOPAD_NUM +}; +#endif + /* QSPI */ #if !defined(__ASSEMBLER__) enum @@ -342,7 +348,7 @@ enum /* TIMER and TACHO */ #define FTIMER_NUM 38U -#define FTIMER_CLK_FREQ_HZ 50000000U /* 50MHz */ +#define FTIMER_CLK_FREQ_HZ 50000000ULL /* 50MHz */ #define FTIMER_TICK_PERIOD_NS 20U /* 20ns */ #define FTIMER_TACHO_IRQ_NUM(n) (226U + (n)) #define FTIMER_TACHO_BASE_ADDR(n) (0x28054000U + 0x1000U * (n)) @@ -533,6 +539,41 @@ enum #define FDDMA0_SPIM2_RX_SLAVE_ID 21U /* spi2 rx slave-id */ #define FDDMA0_SPIM3_RX_SLAVE_ID 22U /* spi3 rx slave-id */ +/* FDDMA1_ID */ +#define FDDMA1_MIO0_TX_SLAVE_ID 0U /* mio0 rx slave-id */ +#define FDDMA1_MIO1_TX_SLAVE_ID 1U /* mio1 rx slave-id */ +#define FDDMA1_MIO2_TX_SLAVE_ID 2U /* mio2 rx slave-id */ +#define FDDMA1_MIO3_TX_SLAVE_ID 3U /* mio3 rx slave-id */ +#define FDDMA1_MIO4_TX_SLAVE_ID 4U /* mio4 rx slave-id */ +#define FDDMA1_MIO5_TX_SLAVE_ID 5U /* mio5 rx slave-id */ +#define FDDMA1_MIO6_TX_SLAVE_ID 6U /* mio6 rx slave-id */ +#define FDDMA1_MIO7_TX_SLAVE_ID 7U /* mio7 rx slave-id */ +#define FDDMA1_MIO8_TX_SLAVE_ID 8U /* mio8 rx slave-id */ +#define FDDMA1_MIO9_TX_SLAVE_ID 9U /* mio9 rx slave-id */ +#define FDDMA1_MIO10_TX_SLAVE_ID 10U /* mio10 rx slave-id */ +#define FDDMA1_MIO11_TX_SLAVE_ID 11U /* mio11 rx slave-id */ +#define FDDMA1_MIO12_TX_SLAVE_ID 12U /* mio12 rx slave-id */ +#define FDDMA1_MIO13_TX_SLAVE_ID 13U /* mio13 rx slave-id */ +#define FDDMA1_MIO14_TX_SLAVE_ID 14U /* mio14 rx slave-id */ +#define FDDMA1_MIO15_TX_SLAVE_ID 15U /* mio15 rx slave-id */ + +#define FDDMA1_MIO0_RX_SLAVE_ID 16U /* mio0 tx slave-id */ +#define FDDMA1_MIO1_RX_SLAVE_ID 17U /* mio1 tx slave-id */ +#define FDDMA1_MIO2_RX_SLAVE_ID 18U /* mio2 tx slave-id */ +#define FDDMA1_MIO3_RX_SLAVE_ID 19U /* mio3 tx slave-id */ +#define FDDMA1_MIO4_RX_SLAVE_ID 20U /* mio4 tx slave-id */ +#define FDDMA1_MIO5_RX_SLAVE_ID 21U /* mio5 tx slave-id */ +#define FDDMA1_MIO6_RX_SLAVE_ID 22U /* mio6 tx slave-id */ +#define FDDMA1_MIO7_RX_SLAVE_ID 23U /* mio7 tx slave-id */ +#define FDDMA1_MIO8_RX_SLAVE_ID 24U /* mio8 tx slave-id */ +#define FDDMA1_MIO9_RX_SLAVE_ID 25U /* mio9 tx slave-id */ +#define FDDMA1_MIO10_RX_SLAVE_ID 26U /* mio10 tx slave-id */ +#define FDDMA1_MIO11_RX_SLAVE_ID 27U /* mio11 tx slave-id */ +#define FDDMA1_MIO12_RX_SLAVE_ID 28U /* mio12 tx slave-id */ +#define FDDMA1_MIO13_RX_SLAVE_ID 29U /* mio13 tx slave-id */ +#define FDDMA1_MIO14_RX_SLAVE_ID 30U /* mio14 tx slave-id */ +#define FDDMA1_MIO15_RX_SLAVE_ID 31U /* mio15 tx slave-id */ + #define FDDMA_MIN_SLAVE_ID 0U #define FDDMA_MAX_SLAVE_ID 31U @@ -657,6 +698,23 @@ typedef enum #define FDCDP_IRQ_NUM 76 +/* generic timer */ +/* non-secure physical timer int id */ +#define GENERIC_TIMER_NS_IRQ_NUM 30U + +/* virtual timer int id */ +#define GENERIC_VTIMER_IRQ_NUM 27U + +#if !defined(__ASSEMBLER__) +enum +{ + GENERIC_TIMER_ID0 = 0, /* non-secure physical timer */ + GENERIC_TIMER_ID1 = 1, /* virtual timer */ + + GENERIC_TIMER_NUM +}; +#endif + /*****************************************************************************/ #ifdef __cplusplus diff --git a/bsp/phytium/libraries/standalone/board/e2000/q/fiopad.h b/bsp/phytium/libraries/standalone/board/e2000/q/fiopad.h deleted file mode 100644 index 74eb5aa77e3..00000000000 --- a/bsp/phytium/libraries/standalone/board/e2000/q/fiopad.h +++ /dev/null @@ -1,266 +0,0 @@ - -#ifndef BOARD_E2000Q_FIOPAD_H -#define BOARD_E2000Q_FIOPAD_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/***************************** Include Files *********************************/ -#include "fiopad_comm.h" - -/************************** Constant Definitions *****************************/ -/* register offset of iopad function / pull / driver strength */ -#define FIOPAD_AN59 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET) -#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET) -#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET) -#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET) -#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET) -#define FIOPAD_AL53 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET) -#define FIOPAD_AN51 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET) -#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET) -#define FIOPAD_BA57 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET) -#define FIOPAD_BA59 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET) -#define FIOPAD_AW57 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET) -#define FIOPAD_AW59 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET) -#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET) -#define FIOPAD_AN57 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET) -#define FIOPAD_AL59 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET) -#define FIOPAD_AJ59 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET) -#define FIOPAD_AJ57 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET) -#define FIOPAD_AG59 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET) -#define FIOPAD_AG57 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET) -#define FIOPAD_AE59 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET) -#define FIOPAD_AC59 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET) -#define FIOPAD_AC57 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET) -#define FIOPAD_AR49 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET) -#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET) -#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET) -#define FIOPAD_AR59 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET) -#define FIOPAD_AU59 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET) -#define FIOPAD_AR57 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET) -#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET) -#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET) -#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET) -#define FIOPAD_R57 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET) -#define FIOPAD_R59 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET) -#define FIOPAD_U59 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET) -#define FIOPAD_W59 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET) -#define FIOPAD_U57 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET) -#define FIOPAD_AA57 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET) -#define FIOPAD_AA59 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET) -#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET) -#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET) -#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET) -#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET) -#define FIOPAD_C37 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET) -#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET) -#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET) -#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET) -#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET) -#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET) -#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET) -#define FIOPAD_A49 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET) -#define FIOPAD_C49 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET) -#define FIOPAD_A51 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET) -#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET) -#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET) -#define FIOPAD_C31 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET) -#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET) -#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET) -#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET) -#define FIOPAD_AL47 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET) -#define FIOPAD_AN49 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET) -#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET) -#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET) -#define FIOPAD_AG49 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET) -#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET) -#define FIOPAD_AE53 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET) -#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET) -#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET) -#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET) -#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET) -#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET) -#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET) -#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET) -#define FIOPAD_W53 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET) -#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET) -#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET) -#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET) -#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET) -#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET) -#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET) -#define FIOPAD_AA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET) -#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET) -#define FIOPAD_AA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET) -#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET) -#define FIOPAD_G59 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET) -#define FIOPAD_J59 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET) -#define FIOPAD_L57 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET) -#define FIOPAD_C59 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET) -#define FIOPAD_E59 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET) -#define FIOPAD_J57 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET) -#define FIOPAD_L59 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET) -#define FIOPAD_N59 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET) -#define FIOPAD_C57 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET) -#define FIOPAD_E57 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET) -#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET) -#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET) -#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET) -#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET) -#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET) -#define FIOPAD_N33 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET) -#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET) -#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET) -#define FIOPAD_N43 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET) -#define FIOPAD_L31 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET) -#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET) -#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET) -#define FIOPAD_E29 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET) -#define FIOPAD_G29 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET) -#define FIOPAD_N27 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET) -#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET) -#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET) -#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET) -#define FIOPAD_G41 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET) -#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET) -#define FIOPAD_L43 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET) -#define FIOPAD_C43 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET) -#define FIOPAD_E41 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET) -#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET) -#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET) -#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET) -#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET) -#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET) -#define FIOPAD_E35 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET) -#define FIOPAD_G35 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET) -#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET) -#define FIOPAD_L37 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET) -#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET) -#define FIOPAD_R51 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET) -#define FIOPAD_R49 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET) -#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET) -#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET) -#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET) -#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET) -#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET) -#define FIOPAD_E47 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET) -#define FIOPAD_G47 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET) -#define FIOPAD_J47 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET) -#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET) -#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET) -#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET) -#define FIOPAD_L49 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET) -#define FIOPAD_N53 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET) -#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET) - -/* register offset of iopad delay */ -#define FIOPAD_AJ55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET) -#define FIOPAD_AL55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET) -#define FIOPAD_AL53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET) -#define FIOPAD_AN51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET) -#define FIOPAD_AR51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET) -#define FIOPAD_AJ57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET) -#define FIOPAD_AG59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET) -#define FIOPAD_AG57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET) -#define FIOPAD_AE59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET) -#define FIOPAD_BA55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET) -#define FIOPAD_BA53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET) -#define FIOPAD_AR59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET) -#define FIOPAD_AU59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET) -#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET) -#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET) -#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET) -#define FIOPAD_A49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET) -#define FIOPAD_C49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET) -#define FIOPAD_A51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET) -#define FIOPAD_A33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET) -#define FIOPAD_C33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET) -#define FIOPAD_C31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET) -#define FIOPAD_A31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET) -#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET) -#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET) -#define FIOPAD_AL47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET) -#define FIOPAD_AN49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET) -#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET) -#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET) -#define FIOPAD_AG49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET) -#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET) -#define FIOPAD_AE53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET) -#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET) -#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET) -#define FIOPAD_AC55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET) -#define FIOPAD_AC53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET) -#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET) -#define FIOPAD_W51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET) -#define FIOPAD_W53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET) -#define FIOPAD_U55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET) -#define FIOPAD_U53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET) -#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET) -#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET) -#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET) -#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET) -#define FIOPAD_AA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET) -#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET) -#define FIOPAD_AA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET) -#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET) -#define FIOPAD_J59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET) -#define FIOPAD_L57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET) -#define FIOPAD_C59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET) -#define FIOPAD_E59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET) -#define FIOPAD_J57_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET) -#define FIOPAD_L59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET) -#define FIOPAD_N59_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET) -#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET) -#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET) -#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET) -#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET) -#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET) -#define FIOPAD_N33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET) -#define FIOPAD_L33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET) -#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET) -#define FIOPAD_N43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET) -#define FIOPAD_L31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET) -#define FIOPAD_J31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET) -#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET) -#define FIOPAD_E29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET) -#define FIOPAD_G29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET) -#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET) -#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET) -#define FIOPAD_G41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET) -#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET) -#define FIOPAD_L43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET) -#define FIOPAD_C43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET) -#define FIOPAD_E41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET) -#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET) -#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET) -#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET) -#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET) -#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET) -#define FIOPAD_E35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET) -#define FIOPAD_G35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET) -#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET) -#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET) -#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET) -#define FIOPAD_E47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET) -#define FIOPAD_G47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET) -#define FIOPAD_J47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET) -#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET) -#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET) -#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET) -#define FIOPAD_L49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET) -#define FIOPAD_N53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET) -#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET) - -/***************** Macros (Inline Functions) Definitions *********************/ - -/*****************************************************************************/ - - -#ifdef __cplusplus -} - -#endif - -#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/e2000/q/fiopad_config.c b/bsp/phytium/libraries/standalone/board/e2000/q/fiopad_config.c deleted file mode 100644 index c60770ce712..00000000000 --- a/bsp/phytium/libraries/standalone/board/e2000/q/fiopad_config.c +++ /dev/null @@ -1,609 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fiopad_config.c - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-18 08:25:29 - * Description:  This file is for io-pad function definition - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 huanghe 2021/11/5 init commit - * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec. - */ - -/***************************** Include Files *********************************/ -#include "fiopad.h" -#include "fparameters.h" -#include "fdebug.h" -#include "fpinctrl.h" -#include "fassert.h" -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -#define FIOPAD_DEBUG_TAG "FIOPAD-CFG" -#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** - * @name: FIOPadSetSpimMux - * @msg: set iopad mux for spim - * @return {*} - * @param {u32} spim_id, instance id of spi - */ -void FIOPadSetSpimMux(u32 spim_id) -{ - if (FSPI0_ID == spim_id) - { - FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_W55), - FPinGetFunc(FIOPAD_W53), FPinGetFunc(FIOPAD_U55), - FPinGetFunc(FIOPAD_U53)); - FPinSetFunc(FIOPAD_W55, FPIN_FUNC2); /* sclk */ - FPinSetFunc(FIOPAD_W53, FPIN_FUNC2); /* txd */ - FPinSetFunc(FIOPAD_U55, FPIN_FUNC2); /* rxd */ - FPinSetFunc(FIOPAD_U53, FPIN_FUNC2); /* csn0 */ - FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_W55), - FPinGetFunc(FIOPAD_W53), FPinGetFunc(FIOPAD_U55), - FPinGetFunc(FIOPAD_U53)); - } - else if (FSPI1_ID == spim_id) - { - FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_N43), - FPinGetFunc(FIOPAD_L31), FPinGetFunc(FIOPAD_J31), - FPinGetFunc(FIOPAD_J29)); - FPinSetFunc(FIOPAD_N43, FPIN_FUNC4); /* sclk */ - FPinSetFunc(FIOPAD_L31, FPIN_FUNC4); /* txd */ - FPinSetFunc(FIOPAD_J31, FPIN_FUNC4); /* rxd */ - FPinSetFunc(FIOPAD_J29, FPIN_FUNC4); /* csn0 */ - FIOPAD_INFO("%d-%d-%d-%d", FPinGetFunc(FIOPAD_N43), - FPinGetFunc(FIOPAD_L31), FPinGetFunc(FIOPAD_J31), - FPinGetFunc(FIOPAD_J29)); - } - else if (FSPI2_ID == spim_id) - { - FPinSetFunc(FIOPAD_A33, FPIN_FUNC0); /* sclk */ - FPinSetFunc(FIOPAD_C33, FPIN_FUNC0); /* txd */ - FPinSetFunc(FIOPAD_C31, FPIN_FUNC0); /* rxd */ - FPinSetFunc(FIOPAD_A31, FPIN_FUNC0); /* csn0 */ - } - else if (FSPI3_ID == spim_id) - { - FPinSetFunc(FIOPAD_AC55, FPIN_FUNC2); /* sclk */ - FPinSetFunc(FIOPAD_AC53, FPIN_FUNC2); /* txd */ - FPinSetFunc(FIOPAD_AE51, FPIN_FUNC2); /* rxd */ - FPinSetFunc(FIOPAD_W51, FPIN_FUNC2); /* csn0 */ - } -} - -static void FIOPadDumpGpioPin(FPinIndex pin, u32 gpio_id, u32 pin_id) -{ - FPinFunc func = FPIN_FUNC0; - FPinPull pull = FPIN_PULL_NONE; - FPinDrive drive = FPIN_DRV0; - - FPinGetConfig(pin, &func, &pull, &drive); - FIOPAD_DEBUG("GPIO-%d-%d: func: %d, pull: %d, drive: %d", - gpio_id, pin_id, func, pull, drive); -} - -/** - * @name: FIOPadSetGpioMux - * @msg: set iopad mux for gpio - * @return {*} - * @param {u32} gpio_id, instance id of gpio - * @param {u32} pin_id, index of pin - */ -void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) -{ - if (FGPIO2_ID == gpio_id) - { - switch (pin_id) - { - case 11: /* gpio 2-a-11 */ - FPinSetFunc(FIOPAD_N49, FPIN_FUNC0); - break; - case 12: /* gpio 2-a-12 */ - FPinSetFunc(FIOPAD_L51, FPIN_FUNC0); - break; - case 13: /* gpio 2-a-13 */ - FPinSetFunc(FIOPAD_L49, FPIN_FUNC0); - break; - case 14: /* gpio 2-a-14 */ - FPinSetFunc(FIOPAD_N53, FPIN_FUNC0); - break; - case 15: /* gpio 2-a-15 */ - FPinSetFunc(FIOPAD_J53, FPIN_FUNC0); - break; - } - } - else if (FGPIO3_ID == gpio_id) - { - switch (pin_id) - { - case 3: /* gpio 3-a-3 */ - FPinSetFunc(FIOPAD_A33, FPIN_FUNC6); - break; - case 4: /* gpio 3-a-4 */ - FPinSetFunc(FIOPAD_C33, FPIN_FUNC6); - break; - case 5: /* gpio 3-a-5 */ - FPinSetFunc(FIOPAD_C31, FPIN_FUNC6); - break; - case 6: /* gpio 3-a-6 */ - FPinSetFunc(FIOPAD_A31, FPIN_FUNC6); - break; - default: - break; - } - } - else if (FGPIO4_ID == gpio_id) - { - switch (pin_id) - { - case 5: /* gpio 4-a-5 */ - FPinSetFunc(FIOPAD_W51, FPIN_FUNC6); - break; - case 9: /* gpio 4-a-9 */ - FPinSetFunc(FIOPAD_U53, FPIN_FUNC6); - break; - case 10: /* gpio 4-a-10 */ - FPinSetFunc(FIOPAD_AE49, FPIN_FUNC6); - break; - case 11: /* gpio 4-a-11 */ - FPinSetFunc(FIOPAD_AC49, FPIN_FUNC6); - break; - case 12: /* gpio 4-a-12 */ - FPinSetFunc(FIOPAD_AE47, FPIN_FUNC6); - break; - case 13: /* gpio 4-a-13 */ - FPinSetFunc(FIOPAD_AA47, FPIN_FUNC6); - break; - default: - break; - } - } -} - - -/** - * @name: FIOPadSetCanMux - * @msg: set iopad mux for can - * @return {*} - * @param {u32} can_id, instance id of can - */ -void FIOPadSetCanMux(u32 can_id) -{ - if (can_id == FCAN0_ID) - { - /* can0 */ - FPinSetFunc(FIOPAD_A41, FPIN_FUNC0); /* can0-tx: func 0 */ - FPinSetFunc(FIOPAD_A43, FPIN_FUNC0); /* can0-rx: func 0 */ - } - else if (can_id == FCAN1_ID) - { - /* can1 */ - FPinSetFunc(FIOPAD_A45, FPIN_FUNC0); /* can1-tx: func 0 */ - FPinSetFunc(FIOPAD_C45, FPIN_FUNC0); /* can1-rx: func 0 */ - } - else - { - FIOPAD_ERROR("can id is error.\r\n"); - } -} - -/** - * @name: FIOPadSetQspiMux - * @msg: set iopad mux for qspi - * @return {*} - * @param {u32} qspi_id, id of qspi instance - * @param {u32} cs_id, id of qspi cs - */ -void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id) -{ - - if (qspi_id == FQSPI0_ID) - { - /* add sck, io0-io3 iopad multiplex */ - } - - if (cs_id == FQSPI_CS_0) - { - FPinSetFunc(FIOPAD_AR55, FPIN_FUNC0); - } - else if (cs_id == FQSPI_CS_1) - { - FPinSetFunc(FIOPAD_AR49, FPIN_FUNC0); - } - else if (cs_id == FQSPI_CS_2) - { - FPinSetFunc(FIOPAD_C37, FPIN_FUNC5); - } - else if (cs_id == FQSPI_CS_3) - { - FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); - } - else - { - FIOPAD_ERROR("can id is error.\r\n"); - } -} - -/** - * @name: FIOPadSetPwmMux - * @msg: set iopad mux for pwm - * @return {*} - * @param {u32} pwm_id, id of pwm instance - * @param {u32} pwm_channel, channel of pwm instance - */ -void FIOPadSetPwmMux(u32 pwm_id, u32 pwm_channel) -{ - FASSERT(pwm_id < FPWM_NUM); - FASSERT(pwm_channel < FPWM_CHANNEL_NUM); - - switch (pwm_id) - { - case FPWM0_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_AL59, FPIN_FUNC1); /* PWM0_OUT: func 1 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_AJ57, FPIN_FUNC1); /* PWM1_OUT: func 1 */ - } - break; - - case FPWM1_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_AG57, FPIN_FUNC1); /* PWM2_OUT: func 1 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_AC59, FPIN_FUNC1); /* PWM3_OUT: func 1 */ - } - break; - - case FPWM2_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_BA55, FPIN_FUNC1); /* PWM4_OUT: func 1 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_C39, FPIN_FUNC2); /* PWM5_OUT: func 2 */ - } - break; - - case FPWM3_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_A37, FPIN_FUNC2); /* PWM6_OUT: func 2 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_A43, FPIN_FUNC2); /* PWM7_OUT: func 2 */ - } - break; - - case FPWM4_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_C45, FPIN_FUNC2); /* PWM8_OUT: func 2 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_A49, FPIN_FUNC2); /* PWM9_OUT: func 2 */ - } - break; - - case FPWM5_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_A51, FPIN_FUNC2); /* PWM10_OUT: func 2 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_C33, FPIN_FUNC2); /* PWM11_OUT: func 2 */ - } - break; - - case FPWM6_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_A31, FPIN_FUNC2); /* PWM12_OUT: func 2 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_J39, FPIN_FUNC3); /* PWM13_OUT: func 3 */ - } - break; - - case FPWM7_ID: - if (pwm_channel == 0) - { - FPinSetFunc(FIOPAD_E43, FPIN_FUNC3); /* PWM14_OUT: func 3 */ - } - if (pwm_channel == 1) - { - FPinSetFunc(FIOPAD_C43, FPIN_FUNC3); /* PWM15_OUT: func 3 */ - } - break; - - default: - FIOPAD_ERROR("pwm id is error.\r\n"); - break; - } -} - - -/** - * @name: FIOPadSetAdcMux - * @msg: set iopad mux for adc - * @return {*} - * @param {u32} adc_id, id of adc instance - * @param {u32} adc_channel, id of adc channel - */ -void FIOPadSetAdcMux(u32 adc_id, u32 adc_channel) -{ - if (adc_id == FADC0_ID) - { - switch (adc_channel) - { - case FADC_CHANNEL_0: - FPinSetFunc(FIOPAD_R51, FPIN_FUNC7); /* adc0-0: func 7 */ - break; - case FADC_CHANNEL_1: - FPinSetFunc(FIOPAD_R49, FPIN_FUNC7); /* adc0-1: func 7 */ - break; - case FADC_CHANNEL_2: - FPinSetFunc(FIOPAD_N51, FPIN_FUNC7); /* adc0-2: func 7 */ - break; - case FADC_CHANNEL_3: - FPinSetFunc(FIOPAD_N55, FPIN_FUNC7); /* adc0-3: func 7 */ - break; - case FADC_CHANNEL_4: - FPinSetFunc(FIOPAD_L55, FPIN_FUNC7); /* adc0-4: func 7 */ - break; - case FADC_CHANNEL_5: - FPinSetFunc(FIOPAD_J55, FPIN_FUNC7); /* adc0-5: func 7 */ - break; - case FADC_CHANNEL_6: - FPinSetFunc(FIOPAD_J45, FPIN_FUNC7); /* adc0-6: func 7 */ - break; - case FADC_CHANNEL_7: - FPinSetFunc(FIOPAD_E47, FPIN_FUNC7); /* adc0-7: func 7 */ - break; - default: - FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel); - break; - } - } - else - { - FIOPAD_ERROR("adc %d channel %d is error.\r\n", adc_id, adc_channel); - } -} - -/** - * @name: FIOPadSetMioMux - * @msg: set iopad mux for mio - * @return {*} - * @param {u32} mio_id, instance id of i2c - */ -void FIOPadSetMioMux(u32 mio_id) -{ - switch (mio_id) - { - case FMIO0_ID: - { - FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* sda */ - } - break; - case FMIO1_ID: - { - FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* sda */ - } - break; - case FMIO2_ID: - { - FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_A49, FPIN_FUNC5); /* sda */ - } - break; - case FMIO3_ID: - { - FPinSetFunc(FIOPAD_BA55, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_BA53, FPIN_FUNC4); /* sda */ - } - break; - case FMIO4_ID: - { - FPinSetFunc(FIOPAD_R59, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_U59, FPIN_FUNC4); /* sda */ - } - break; - case FMIO5_ID: - { - FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_U57, FPIN_FUNC4); /* sda */ - } - break; - case FMIO6_ID: - { - FPinSetFunc(FIOPAD_AA57, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_AA59, FPIN_FUNC4); /* sda */ - } - break; - case FMIO7_ID: - { - FPinSetFunc(FIOPAD_A39, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_C39, FPIN_FUNC4); /* sda */ - } - break; - case FMIO8_ID: - { - FPinSetFunc(FIOPAD_AA49, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_W49, FPIN_FUNC4); /* sda */ - } - break; - case FMIO9_ID: - { - FPinSetFunc(FIOPAD_AA51, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_U49, FPIN_FUNC4); /* sda */ - } - break; - case FMIO10_ID: - { - FPinSetFunc(FIOPAD_C49, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_A51, FPIN_FUNC5); /* sda */ - } - break; - case FMIO11_ID: - { - FPinSetFunc(FIOPAD_N27, FPIN_FUNC3); /* scl */ - FPinSetFunc(FIOPAD_L29, FPIN_FUNC3); /* sda */ - } - break; - case FMIO12_ID: - { - FPinSetFunc(FIOPAD_E41, FPIN_FUNC3); /* scl */ - FPinSetFunc(FIOPAD_L45, FPIN_FUNC3); /* sda */ - } - break; - case FMIO13_ID: - { - FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* scl */ - FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* sda */ - } - break; - case FMIO14_ID: - { - FPinSetFunc(FIOPAD_L51, FPIN_FUNC6); /* scl */ - FPinSetFunc(FIOPAD_L49, FPIN_FUNC6); /* sda */ - } - break; - case FMIO15_ID: - { - FPinSetFunc(FIOPAD_N53, FPIN_FUNC6); /* scl */ - FPinSetFunc(FIOPAD_J53, FPIN_FUNC6); /* sda */ - } - break; - default: - break; - } -} - -/** - * @name: FIOPadSetTachoMux - * @msg: set iopad mux for pwm_in - * @return {*} - * @param {u32} pwm_in_id, instance id of tacho - */ -void FIOPadSetTachoMux(u32 pwm_in_id) -{ - switch (pwm_in_id) - { - case FTACHO0_ID: - FPinSetFunc(FIOPAD_AN57, FPIN_FUNC1); - break; - case FTACHO1_ID: - FPinSetFunc(FIOPAD_AJ59, FPIN_FUNC1); - break; - case FTACHO2_ID: - FPinSetFunc(FIOPAD_AG59, FPIN_FUNC1); - break; - case FTACHO3_ID: - FPinSetFunc(FIOPAD_AE59, FPIN_FUNC1); - break; - case FTACHO4_ID: - FPinSetFunc(FIOPAD_AC57, FPIN_FUNC1); - break; - case FTACHO5_ID: - FPinSetFunc(FIOPAD_BA53, FPIN_FUNC1); - break; - case FTACHO6_ID: - FPinSetFunc(FIOPAD_C37, FPIN_FUNC2); - break; - case FTACHO7_ID: - FPinSetFunc(FIOPAD_A41, FPIN_FUNC2); - break; - case FTACHO8_ID: - FPinSetFunc(FIOPAD_A45, FPIN_FUNC2); - break; - case FTACHO9_ID: - FPinSetFunc(FIOPAD_A47, FPIN_FUNC2); - break; - case FTACHO10_ID: - FPinSetFunc(FIOPAD_C49, FPIN_FUNC2); - break; - case FTACHO11_ID: - FPinSetFunc(FIOPAD_A33, FPIN_FUNC2); - break; - case FTACHO12_ID: - FPinSetFunc(FIOPAD_C31, FPIN_FUNC2); - break; - case FTACHO13_ID: - FPinSetFunc(FIOPAD_AA49, FPIN_FUNC2); - break; - case FTACHO14_ID: - FPinSetFunc(FIOPAD_AA51, FPIN_FUNC2); - break; - case FTACHO15_ID: - FPinSetFunc(FIOPAD_G59, FPIN_FUNC2); - break; - default: - break; - } -} - -/** - * @name: FIOPadSetUartMux - * @msg: set iopad mux for uart - * @return {*} - * @param {u32} uart_id, instance id of uart - */ -void FIOPadSetUartMux(u32 uart_id) -{ - switch (uart_id) - { - case FUART0_ID: - FPinSetFunc(FIOPAD_J37, FPIN_FUNC4); - FPinSetFunc(FIOPAD_J39, FPIN_FUNC4); - break; - case FUART1_ID: - FPinSetFunc(FIOPAD_AW51, FPIN_FUNC0); - FPinSetFunc(FIOPAD_AU51, FPIN_FUNC0); - break; - case FUART2_ID: - FPinSetFunc(FIOPAD_A47, FPIN_FUNC0); - FPinSetFunc(FIOPAD_A49, FPIN_FUNC0); - break; - case FUART3_ID: - FPinSetFunc(FIOPAD_L37, FPIN_FUNC2); - FPinSetFunc(FIOPAD_N35, FPIN_FUNC2); - break; - default: - break; - } -} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h b/bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h index 680ba76b2d1..033074ab7ed 100644 --- a/bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h +++ b/bsp/phytium/libraries/standalone/board/e2000/q/fparameters.h @@ -37,10 +37,257 @@ extern "C" #define CORE1_AFF 0x100U #define CORE2_AFF 0x200U #define CORE3_AFF 0x201U +#define FCORE_NUM 4 #define FT_CPUS_NR 4U /*****************************************************************************/ +/* register offset of iopad function / pull / driver strength */ +#define FIOPAD_AN59_REG0_OFFSET 0x0000U +#define FIOPAD_AW47_REG0_OFFSET 0x0004U +#define FIOPAD_AR55_REG0_OFFSET 0x0020U +#define FIOPAD_AJ55_REG0_OFFSET 0x0024U +#define FIOPAD_AL55_REG0_OFFSET 0x0028U +#define FIOPAD_AL53_REG0_OFFSET 0x002CU +#define FIOPAD_AN51_REG0_OFFSET 0x0030U +#define FIOPAD_AR51_REG0_OFFSET 0x0034U +#define FIOPAD_BA57_REG0_OFFSET 0x0038U +#define FIOPAD_BA59_REG0_OFFSET 0x003CU +#define FIOPAD_AW57_REG0_OFFSET 0x0040U +#define FIOPAD_AW59_REG0_OFFSET 0x0044U +#define FIOPAD_AU55_REG0_OFFSET 0x0048U +#define FIOPAD_AN57_REG0_OFFSET 0x004CU +#define FIOPAD_AL59_REG0_OFFSET 0x0050U +#define FIOPAD_AJ59_REG0_OFFSET 0x0054U +#define FIOPAD_AJ57_REG0_OFFSET 0x0058U +#define FIOPAD_AG59_REG0_OFFSET 0x005CU +#define FIOPAD_AG57_REG0_OFFSET 0x0060U +#define FIOPAD_AE59_REG0_OFFSET 0x0064U +#define FIOPAD_AC59_REG0_OFFSET 0x0068U +#define FIOPAD_AC57_REG0_OFFSET 0x006CU +#define FIOPAD_AR49_REG0_OFFSET 0x0070U +#define FIOPAD_BA55_REG0_OFFSET 0x0074U +#define FIOPAD_BA53_REG0_OFFSET 0x0078U +#define FIOPAD_AR59_REG0_OFFSET 0x007CU +#define FIOPAD_AU59_REG0_OFFSET 0x0080U +#define FIOPAD_AR57_REG0_OFFSET 0x0084U +#define FIOPAD_BA49_REG0_OFFSET 0x0088U +#define FIOPAD_AW55_REG0_OFFSET 0x008CU +#define FIOPAD_A35_REG0_OFFSET 0x0090U +#define FIOPAD_R57_REG0_OFFSET 0x0094U +#define FIOPAD_R59_REG0_OFFSET 0x0098U +#define FIOPAD_U59_REG0_OFFSET 0x009CU +#define FIOPAD_W59_REG0_OFFSET 0x00A0U +#define FIOPAD_U57_REG0_OFFSET 0x00A4U +#define FIOPAD_AA57_REG0_OFFSET 0x00A8U +#define FIOPAD_AA59_REG0_OFFSET 0x00ACU +#define FIOPAD_AW51_REG0_OFFSET 0x00B0U +#define FIOPAD_AU51_REG0_OFFSET 0x00B4U +#define FIOPAD_A39_REG0_OFFSET 0x00B8U +#define FIOPAD_C39_REG0_OFFSET 0x00BCU +#define FIOPAD_C37_REG0_OFFSET 0x00C0U +#define FIOPAD_A37_REG0_OFFSET 0x00C4U +#define FIOPAD_A41_REG0_OFFSET 0x00C8U +#define FIOPAD_A43_REG0_OFFSET 0x00CCU +#define FIOPAD_A45_REG0_OFFSET 0x00D0U +#define FIOPAD_C45_REG0_OFFSET 0x00D4U +#define FIOPAD_A47_REG0_OFFSET 0x00D8U +#define FIOPAD_A49_REG0_OFFSET 0x00DCU +#define FIOPAD_C49_REG0_OFFSET 0x00E0U +#define FIOPAD_A51_REG0_OFFSET 0x00E4U +#define FIOPAD_A33_REG0_OFFSET 0x00E8U +#define FIOPAD_C33_REG0_OFFSET 0x00ECU +#define FIOPAD_C31_REG0_OFFSET 0x00F0U +#define FIOPAD_A31_REG0_OFFSET 0x00F4U +#define FIOPAD_AJ53_REG0_OFFSET 0x00F8U +#define FIOPAD_AL49_REG0_OFFSET 0x00FCU +#define FIOPAD_AL47_REG0_OFFSET 0x0100U +#define FIOPAD_AN49_REG0_OFFSET 0x0104U +#define FIOPAD_AG51_REG0_OFFSET 0x0108U +#define FIOPAD_AJ51_REG0_OFFSET 0x010CU +#define FIOPAD_AG49_REG0_OFFSET 0x0110U +#define FIOPAD_AE55_REG0_OFFSET 0x0114U +#define FIOPAD_AE53_REG0_OFFSET 0x0118U +#define FIOPAD_AG55_REG0_OFFSET 0x011CU +#define FIOPAD_AJ49_REG0_OFFSET 0x0120U +#define FIOPAD_AC55_REG0_OFFSET 0x0124U +#define FIOPAD_AC53_REG0_OFFSET 0x0128U +#define FIOPAD_AE51_REG0_OFFSET 0x012CU +#define FIOPAD_W51_REG0_OFFSET 0x0130U +#define FIOPAD_W55_REG0_OFFSET 0x0134U +#define FIOPAD_W53_REG0_OFFSET 0x0138U +#define FIOPAD_U55_REG0_OFFSET 0x013CU +#define FIOPAD_U53_REG0_OFFSET 0x0140U +#define FIOPAD_AE49_REG0_OFFSET 0x0144U +#define FIOPAD_AC49_REG0_OFFSET 0x0148U +#define FIOPAD_AE47_REG0_OFFSET 0x014CU +#define FIOPAD_AA47_REG0_OFFSET 0x0150U +#define FIOPAD_AA49_REG0_OFFSET 0x0154U +#define FIOPAD_W49_REG0_OFFSET 0x0158U +#define FIOPAD_AA51_REG0_OFFSET 0x015CU +#define FIOPAD_U49_REG0_OFFSET 0x0160U +#define FIOPAD_G59_REG0_OFFSET 0x0164U +#define FIOPAD_J59_REG0_OFFSET 0x0168U +#define FIOPAD_L57_REG0_OFFSET 0x016CU +#define FIOPAD_C59_REG0_OFFSET 0x0170U +#define FIOPAD_E59_REG0_OFFSET 0x0174U +#define FIOPAD_J57_REG0_OFFSET 0x0178U +#define FIOPAD_L59_REG0_OFFSET 0x017CU +#define FIOPAD_N59_REG0_OFFSET 0x0180U +#define FIOPAD_C57_REG0_OFFSET 0x0184U +#define FIOPAD_E57_REG0_OFFSET 0x0188U +#define FIOPAD_E31_REG0_OFFSET 0x018CU +#define FIOPAD_G31_REG0_OFFSET 0x0190U +#define FIOPAD_N41_REG0_OFFSET 0x0194U +#define FIOPAD_N39_REG0_OFFSET 0x0198U +#define FIOPAD_J33_REG0_OFFSET 0x019CU +#define FIOPAD_N33_REG0_OFFSET 0x01A0U +#define FIOPAD_L33_REG0_OFFSET 0x01A4U +#define FIOPAD_N45_REG0_OFFSET 0x01A8U +#define FIOPAD_N43_REG0_OFFSET 0x01ACU +#define FIOPAD_L31_REG0_OFFSET 0x01B0U +#define FIOPAD_J31_REG0_OFFSET 0x01B4U +#define FIOPAD_J29_REG0_OFFSET 0x01B8U +#define FIOPAD_E29_REG0_OFFSET 0x01BCU +#define FIOPAD_G29_REG0_OFFSET 0x01C0U +#define FIOPAD_N27_REG0_OFFSET 0x01C4U +#define FIOPAD_L29_REG0_OFFSET 0x01C8U +#define FIOPAD_J37_REG0_OFFSET 0x01CCU +#define FIOPAD_J39_REG0_OFFSET 0x01D0U +#define FIOPAD_G41_REG0_OFFSET 0x01D4U +#define FIOPAD_E43_REG0_OFFSET 0x01D8U +#define FIOPAD_L43_REG0_OFFSET 0x01DCU +#define FIOPAD_C43_REG0_OFFSET 0x01E0U +#define FIOPAD_E41_REG0_OFFSET 0x01E4U +#define FIOPAD_L45_REG0_OFFSET 0x01E8U +#define FIOPAD_J43_REG0_OFFSET 0x01ECU +#define FIOPAD_J41_REG0_OFFSET 0x01F0U +#define FIOPAD_L39_REG0_OFFSET 0x01F4U +#define FIOPAD_E37_REG0_OFFSET 0x01F8U +#define FIOPAD_E35_REG0_OFFSET 0x01FCU +#define FIOPAD_G35_REG0_OFFSET 0x0200U +#define FIOPAD_J35_REG0_OFFSET 0x0204U +#define FIOPAD_L37_REG0_OFFSET 0x0208U +#define FIOPAD_N35_REG0_OFFSET 0x020CU +#define FIOPAD_R51_REG0_OFFSET 0x0210U +#define FIOPAD_R49_REG0_OFFSET 0x0214U +#define FIOPAD_N51_REG0_OFFSET 0x0218U +#define FIOPAD_N55_REG0_OFFSET 0x021CU +#define FIOPAD_L55_REG0_OFFSET 0x0220U +#define FIOPAD_J55_REG0_OFFSET 0x0224U +#define FIOPAD_J45_REG0_OFFSET 0x0228U +#define FIOPAD_E47_REG0_OFFSET 0x022CU +#define FIOPAD_G47_REG0_OFFSET 0x0230U +#define FIOPAD_J47_REG0_OFFSET 0x0234U +#define FIOPAD_J49_REG0_OFFSET 0x0238U +#define FIOPAD_N49_REG0_OFFSET 0x023CU +#define FIOPAD_L51_REG0_OFFSET 0x0240U +#define FIOPAD_L49_REG0_OFFSET 0x0244U +#define FIOPAD_N53_REG0_OFFSET 0x0248U +#define FIOPAD_J53_REG0_OFFSET 0x024CU +#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN59_REG0_OFFSET +#define FIOPAD_REG0_END_OFFSET FIOPAD_J53_REG0_OFFSET + +/* register offset of iopad delay */ +#define FIOPAD_AJ55_REG1_OFFSET 0x1024U +#define FIOPAD_AL55_REG1_OFFSET 0x1028U +#define FIOPAD_AL53_REG1_OFFSET 0x102CU +#define FIOPAD_AN51_REG1_OFFSET 0x1030U +#define FIOPAD_AR51_REG1_OFFSET 0x1034U +#define FIOPAD_AJ57_REG1_OFFSET 0x1058U +#define FIOPAD_AG59_REG1_OFFSET 0x105CU +#define FIOPAD_AG57_REG1_OFFSET 0x1060U +#define FIOPAD_AE59_REG1_OFFSET 0x1064U +#define FIOPAD_BA55_REG1_OFFSET 0x1074U +#define FIOPAD_BA53_REG1_OFFSET 0x1078U +#define FIOPAD_AR59_REG1_OFFSET 0x107CU +#define FIOPAD_AU59_REG1_OFFSET 0x1080U +#define FIOPAD_A45_REG1_OFFSET 0x10D0U +#define FIOPAD_C45_REG1_OFFSET 0x10D4U +#define FIOPAD_A47_REG1_OFFSET 0x10D8U +#define FIOPAD_A49_REG1_OFFSET 0x10DCU +#define FIOPAD_C49_REG1_OFFSET 0x10E0U +#define FIOPAD_A51_REG1_OFFSET 0x10E4U +#define FIOPAD_A33_REG1_OFFSET 0x10E8U +#define FIOPAD_C33_REG1_OFFSET 0x10ECU +#define FIOPAD_C31_REG1_OFFSET 0x10F0U +#define FIOPAD_A31_REG1_OFFSET 0x10F4U +#define FIOPAD_AJ53_REG1_OFFSET 0x10F8U +#define FIOPAD_AL49_REG1_OFFSET 0x10FCU +#define FIOPAD_AL47_REG1_OFFSET 0x1100U +#define FIOPAD_AN49_REG1_OFFSET 0x1104U +#define FIOPAD_AG51_REG1_OFFSET 0x1108U +#define FIOPAD_AJ51_REG1_OFFSET 0x110CU +#define FIOPAD_AG49_REG1_OFFSET 0x1110U +#define FIOPAD_AE55_REG1_OFFSET 0x1114U +#define FIOPAD_AE53_REG1_OFFSET 0x1118U +#define FIOPAD_AG55_REG1_OFFSET 0x111CU +#define FIOPAD_AJ49_REG1_OFFSET 0x1120U +#define FIOPAD_AC55_REG1_OFFSET 0x1124U +#define FIOPAD_AC53_REG1_OFFSET 0x1128U +#define FIOPAD_AE51_REG1_OFFSET 0x112CU +#define FIOPAD_W51_REG1_OFFSET 0x1130U +#define FIOPAD_W53_REG1_OFFSET 0x1138U +#define FIOPAD_U55_REG1_OFFSET 0x113CU +#define FIOPAD_U53_REG1_OFFSET 0x1140U +#define FIOPAD_AE49_REG1_OFFSET 0x1144U +#define FIOPAD_AC49_REG1_OFFSET 0x1148U +#define FIOPAD_AE47_REG1_OFFSET 0x114CU +#define FIOPAD_AA47_REG1_OFFSET 0x1150U +#define FIOPAD_AA49_REG1_OFFSET 0x1154U +#define FIOPAD_W49_REG1_OFFSET 0x1158U +#define FIOPAD_AA51_REG1_OFFSET 0x115CU +#define FIOPAD_U49_REG1_OFFSET 0x1160U +#define FIOPAD_J59_REG1_OFFSET 0x1168U +#define FIOPAD_L57_REG1_OFFSET 0x116CU +#define FIOPAD_C59_REG1_OFFSET 0x1170U +#define FIOPAD_E59_REG1_OFFSET 0x1174U +#define FIOPAD_J57_REG1_OFFSET 0x1178U +#define FIOPAD_L59_REG1_OFFSET 0x117CU +#define FIOPAD_N59_REG1_OFFSET 0x1180U +#define FIOPAD_E31_REG1_OFFSET 0x118CU +#define FIOPAD_G31_REG1_OFFSET 0x1190U +#define FIOPAD_N41_REG1_OFFSET 0x1194U +#define FIOPAD_N39_REG1_OFFSET 0x1198U +#define FIOPAD_J33_REG1_OFFSET 0x119CU +#define FIOPAD_N33_REG1_OFFSET 0x11A0U +#define FIOPAD_L33_REG1_OFFSET 0x11A4U +#define FIOPAD_N45_REG1_OFFSET 0x11A8U +#define FIOPAD_N43_REG1_OFFSET 0x11ACU +#define FIOPAD_L31_REG1_OFFSET 0x11B0U +#define FIOPAD_J31_REG1_OFFSET 0x11B4U +#define FIOPAD_J29_REG1_OFFSET 0x11B8U +#define FIOPAD_E29_REG1_OFFSET 0x11BCU +#define FIOPAD_G29_REG1_OFFSET 0x11C0U +#define FIOPAD_J37_REG1_OFFSET 0x11CCU +#define FIOPAD_J39_REG1_OFFSET 0x11D0U +#define FIOPAD_G41_REG1_OFFSET 0x11D4U +#define FIOPAD_E43_REG1_OFFSET 0x11D8U +#define FIOPAD_L43_REG1_OFFSET 0x11DCU +#define FIOPAD_C43_REG1_OFFSET 0x11E0U +#define FIOPAD_E41_REG1_OFFSET 0x11E4U +#define FIOPAD_L45_REG1_OFFSET 0x11E8U +#define FIOPAD_J43_REG1_OFFSET 0x11ECU +#define FIOPAD_J41_REG1_OFFSET 0x11F0U +#define FIOPAD_L39_REG1_OFFSET 0x11F4U +#define FIOPAD_E37_REG1_OFFSET 0x11F8U +#define FIOPAD_E35_REG1_OFFSET 0x11FCU +#define FIOPAD_G35_REG1_OFFSET 0x1200U +#define FIOPAD_L55_REG1_OFFSET 0x1220U +#define FIOPAD_J55_REG1_OFFSET 0x1224U +#define FIOPAD_J45_REG1_OFFSET 0x1228U +#define FIOPAD_E47_REG1_OFFSET 0x122CU +#define FIOPAD_G47_REG1_OFFSET 0x1230U +#define FIOPAD_J47_REG1_OFFSET 0x1234U +#define FIOPAD_J49_REG1_OFFSET 0x1238U +#define FIOPAD_N49_REG1_OFFSET 0x123CU +#define FIOPAD_L51_REG1_OFFSET 0x1240U +#define FIOPAD_L49_REG1_OFFSET 0x1244U +#define FIOPAD_N53_REG1_OFFSET 0x1248U +#define FIOPAD_J53_REG1_OFFSET 0x124CU + +#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ55_REG1_OFFSET +#define FIOPAD_REG1_END_OFFSET FIOPAD_J53_REG1_OFFSET #ifdef __cplusplus } diff --git a/bsp/phytium/libraries/standalone/board/e2000/s/fiopad.h b/bsp/phytium/libraries/standalone/board/e2000/s/fiopad.h deleted file mode 100644 index d6588ad99e5..00000000000 --- a/bsp/phytium/libraries/standalone/board/e2000/s/fiopad.h +++ /dev/null @@ -1,270 +0,0 @@ - -#ifndef BOARD_E2000Q_FIOPAD_H -#define BOARD_E2000Q_FIOPAD_H - -#ifdef __cplusplus -extern "C" -{ -#endif - - -/***************************** Include Files *********************************/ -#include "fiopad_comm.h" - -/************************** Constant Definitions *****************************/ -/* register offset of iopad function / pull / driver strength */ -#define FIOPAD_AN55 (FPinIndex)FIOPAD_INDEX(FIOPAD_0_FUNC_OFFSET) -#define FIOPAD_AW43 (FPinIndex)FIOPAD_INDEX(FIOPAD_2_FUNC_OFFSET) -#define FIOPAD_AR51 (FPinIndex)FIOPAD_INDEX(FIOPAD_9_FUNC_OFFSET) -#define FIOPAD_AJ51 (FPinIndex)FIOPAD_INDEX(FIOPAD_10_FUNC_OFFSET) -#define FIOPAD_AL51 (FPinIndex)FIOPAD_INDEX(FIOPAD_11_FUNC_OFFSET) -#define FIOPAD_AL49 (FPinIndex)FIOPAD_INDEX(FIOPAD_12_FUNC_OFFSET) -#define FIOPAD_AN47 (FPinIndex)FIOPAD_INDEX(FIOPAD_13_FUNC_OFFSET) -#define FIOPAD_AR47 (FPinIndex)FIOPAD_INDEX(FIOPAD_14_FUNC_OFFSET) -#define FIOPAD_BA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_15_FUNC_OFFSET) -#define FIOPAD_BA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_16_FUNC_OFFSET) -#define FIOPAD_AW53 (FPinIndex)FIOPAD_INDEX(FIOPAD_17_FUNC_OFFSET) -#define FIOPAD_AW55 (FPinIndex)FIOPAD_INDEX(FIOPAD_18_FUNC_OFFSET) -#define FIOPAD_AU51 (FPinIndex)FIOPAD_INDEX(FIOPAD_19_FUNC_OFFSET) -#define FIOPAD_AN53 (FPinIndex)FIOPAD_INDEX(FIOPAD_20_FUNC_OFFSET) -#define FIOPAD_AL55 (FPinIndex)FIOPAD_INDEX(FIOPAD_21_FUNC_OFFSET) -#define FIOPAD_AJ55 (FPinIndex)FIOPAD_INDEX(FIOPAD_22_FUNC_OFFSET) -#define FIOPAD_AJ53 (FPinIndex)FIOPAD_INDEX(FIOPAD_23_FUNC_OFFSET) -#define FIOPAD_AG55 (FPinIndex)FIOPAD_INDEX(FIOPAD_24_FUNC_OFFSET) -#define FIOPAD_AG53 (FPinIndex)FIOPAD_INDEX(FIOPAD_25_FUNC_OFFSET) -#define FIOPAD_AE55 (FPinIndex)FIOPAD_INDEX(FIOPAD_26_FUNC_OFFSET) -#define FIOPAD_AC55 (FPinIndex)FIOPAD_INDEX(FIOPAD_27_FUNC_OFFSET) -#define FIOPAD_AC53 (FPinIndex)FIOPAD_INDEX(FIOPAD_28_FUNC_OFFSET) -#define FIOPAD_AR45 (FPinIndex)FIOPAD_INDEX(FIOPAD_31_FUNC_OFFSET) -#define FIOPAD_BA51 (FPinIndex)FIOPAD_INDEX(FIOPAD_32_FUNC_OFFSET) -#define FIOPAD_BA49 (FPinIndex)FIOPAD_INDEX(FIOPAD_33_FUNC_OFFSET) -#define FIOPAD_AR55 (FPinIndex)FIOPAD_INDEX(FIOPAD_34_FUNC_OFFSET) -#define FIOPAD_AU55 (FPinIndex)FIOPAD_INDEX(FIOPAD_35_FUNC_OFFSET) -#define FIOPAD_AR53 (FPinIndex)FIOPAD_INDEX(FIOPAD_36_FUNC_OFFSET) -#define FIOPAD_BA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_37_FUNC_OFFSET) -#define FIOPAD_AW51 (FPinIndex)FIOPAD_INDEX(FIOPAD_38_FUNC_OFFSET) -#define FIOPAD_A31 (FPinIndex)FIOPAD_INDEX(FIOPAD_39_FUNC_OFFSET) -#define FIOPAD_R53 (FPinIndex)FIOPAD_INDEX(FIOPAD_40_FUNC_OFFSET) -#define FIOPAD_R55 (FPinIndex)FIOPAD_INDEX(FIOPAD_41_FUNC_OFFSET) -#define FIOPAD_U55 (FPinIndex)FIOPAD_INDEX(FIOPAD_42_FUNC_OFFSET) -#define FIOPAD_W55 (FPinIndex)FIOPAD_INDEX(FIOPAD_43_FUNC_OFFSET) -#define FIOPAD_U53 (FPinIndex)FIOPAD_INDEX(FIOPAD_44_FUNC_OFFSET) -#define FIOPAD_AA53 (FPinIndex)FIOPAD_INDEX(FIOPAD_45_FUNC_OFFSET) -#define FIOPAD_AA55 (FPinIndex)FIOPAD_INDEX(FIOPAD_46_FUNC_OFFSET) -#define FIOPAD_AW47 (FPinIndex)FIOPAD_INDEX(FIOPAD_47_FUNC_OFFSET) -#define FIOPAD_AU47 (FPinIndex)FIOPAD_INDEX(FIOPAD_48_FUNC_OFFSET) -#define FIOPAD_A35 (FPinIndex)FIOPAD_INDEX(FIOPAD_49_FUNC_OFFSET) -#define FIOPAD_C35 (FPinIndex)FIOPAD_INDEX(FIOPAD_50_FUNC_OFFSET) -#define FIOPAD_C33 (FPinIndex)FIOPAD_INDEX(FIOPAD_51_FUNC_OFFSET) -#define FIOPAD_A33 (FPinIndex)FIOPAD_INDEX(FIOPAD_52_FUNC_OFFSET) -#define FIOPAD_A37 (FPinIndex)FIOPAD_INDEX(FIOPAD_53_FUNC_OFFSET) -#define FIOPAD_A39 (FPinIndex)FIOPAD_INDEX(FIOPAD_54_FUNC_OFFSET) -#define FIOPAD_A41 (FPinIndex)FIOPAD_INDEX(FIOPAD_55_FUNC_OFFSET) -#define FIOPAD_C41 (FPinIndex)FIOPAD_INDEX(FIOPAD_56_FUNC_OFFSET) -#define FIOPAD_A43 (FPinIndex)FIOPAD_INDEX(FIOPAD_57_FUNC_OFFSET) -#define FIOPAD_A45 (FPinIndex)FIOPAD_INDEX(FIOPAD_58_FUNC_OFFSET) -#define FIOPAD_C45 (FPinIndex)FIOPAD_INDEX(FIOPAD_59_FUNC_OFFSET) -#define FIOPAD_A47 (FPinIndex)FIOPAD_INDEX(FIOPAD_60_FUNC_OFFSET) -#define FIOPAD_A29 (FPinIndex)FIOPAD_INDEX(FIOPAD_61_FUNC_OFFSET) -#define FIOPAD_C29 (FPinIndex)FIOPAD_INDEX(FIOPAD_62_FUNC_OFFSET) -#define FIOPAD_C27 (FPinIndex)FIOPAD_INDEX(FIOPAD_63_FUNC_OFFSET) -#define FIOPAD_A27 (FPinIndex)FIOPAD_INDEX(FIOPAD_64_FUNC_OFFSET) -#define FIOPAD_AJ49 (FPinIndex)FIOPAD_INDEX(FIOPAD_65_FUNC_OFFSET) -#define FIOPAD_AL45 (FPinIndex)FIOPAD_INDEX(FIOPAD_66_FUNC_OFFSET) -#define FIOPAD_AL43 (FPinIndex)FIOPAD_INDEX(FIOPAD_67_FUNC_OFFSET) -#define FIOPAD_AN45 (FPinIndex)FIOPAD_INDEX(FIOPAD_68_FUNC_OFFSET) -#define FIOPAD_AG47 (FPinIndex)FIOPAD_INDEX(FIOPAD_148_FUNC_OFFSET) -#define FIOPAD_AJ47 (FPinIndex)FIOPAD_INDEX(FIOPAD_69_FUNC_OFFSET) -#define FIOPAD_AG45 (FPinIndex)FIOPAD_INDEX(FIOPAD_70_FUNC_OFFSET) -#define FIOPAD_AE51 (FPinIndex)FIOPAD_INDEX(FIOPAD_71_FUNC_OFFSET) -#define FIOPAD_AE49 (FPinIndex)FIOPAD_INDEX(FIOPAD_72_FUNC_OFFSET) -#define FIOPAD_AG51 (FPinIndex)FIOPAD_INDEX(FIOPAD_73_FUNC_OFFSET) -#define FIOPAD_AJ45 (FPinIndex)FIOPAD_INDEX(FIOPAD_74_FUNC_OFFSET) -#define FIOPAD_AC51 (FPinIndex)FIOPAD_INDEX(FIOPAD_75_FUNC_OFFSET) -#define FIOPAD_AC49 (FPinIndex)FIOPAD_INDEX(FIOPAD_76_FUNC_OFFSET) -#define FIOPAD_AE47 (FPinIndex)FIOPAD_INDEX(FIOPAD_77_FUNC_OFFSET) -#define FIOPAD_W47 (FPinIndex)FIOPAD_INDEX(FIOPAD_78_FUNC_OFFSET) -#define FIOPAD_W51 (FPinIndex)FIOPAD_INDEX(FIOPAD_79_FUNC_OFFSET) -#define FIOPAD_W49 (FPinIndex)FIOPAD_INDEX(FIOPAD_80_FUNC_OFFSET) -#define FIOPAD_U51 (FPinIndex)FIOPAD_INDEX(FIOPAD_81_FUNC_OFFSET) -#define FIOPAD_U49 (FPinIndex)FIOPAD_INDEX(FIOPAD_82_FUNC_OFFSET) -#define FIOPAD_AE45 (FPinIndex)FIOPAD_INDEX(FIOPAD_83_FUNC_OFFSET) -#define FIOPAD_AC45 (FPinIndex)FIOPAD_INDEX(FIOPAD_84_FUNC_OFFSET) -#define FIOPAD_AE43 (FPinIndex)FIOPAD_INDEX(FIOPAD_85_FUNC_OFFSET) -#define FIOPAD_AA43 (FPinIndex)FIOPAD_INDEX(FIOPAD_86_FUNC_OFFSET) -#define FIOPAD_AA45 (FPinIndex)FIOPAD_INDEX(FIOPAD_87_FUNC_OFFSET) -#define FIOPAD_W45 (FPinIndex)FIOPAD_INDEX(FIOPAD_88_FUNC_OFFSET) -#define FIOPAD_AA47 (FPinIndex)FIOPAD_INDEX(FIOPAD_89_FUNC_OFFSET) -#define FIOPAD_U45 (FPinIndex)FIOPAD_INDEX(FIOPAD_90_FUNC_OFFSET) -#define FIOPAD_G55 (FPinIndex)FIOPAD_INDEX(FIOPAD_91_FUNC_OFFSET) -#define FIOPAD_J55 (FPinIndex)FIOPAD_INDEX(FIOPAD_92_FUNC_OFFSET) -#define FIOPAD_L53 (FPinIndex)FIOPAD_INDEX(FIOPAD_93_FUNC_OFFSET) -#define FIOPAD_C55 (FPinIndex)FIOPAD_INDEX(FIOPAD_94_FUNC_OFFSET) -#define FIOPAD_E55 (FPinIndex)FIOPAD_INDEX(FIOPAD_95_FUNC_OFFSET) -#define FIOPAD_J53 (FPinIndex)FIOPAD_INDEX(FIOPAD_96_FUNC_OFFSET) -#define FIOPAD_L55 (FPinIndex)FIOPAD_INDEX(FIOPAD_97_FUNC_OFFSET) -#define FIOPAD_N55 (FPinIndex)FIOPAD_INDEX(FIOPAD_98_FUNC_OFFSET) -#define FIOPAD_C53 (FPinIndex)FIOPAD_INDEX(FIOPAD_29_FUNC_OFFSET) -#define FIOPAD_E53 (FPinIndex)FIOPAD_INDEX(FIOPAD_30_FUNC_OFFSET) -#define FIOPAD_E27 (FPinIndex)FIOPAD_INDEX(FIOPAD_99_FUNC_OFFSET) -#define FIOPAD_G27 (FPinIndex)FIOPAD_INDEX(FIOPAD_100_FUNC_OFFSET) -#define FIOPAD_N37 (FPinIndex)FIOPAD_INDEX(FIOPAD_101_FUNC_OFFSET) -#define FIOPAD_N35 (FPinIndex)FIOPAD_INDEX(FIOPAD_102_FUNC_OFFSET) -#define FIOPAD_J29 (FPinIndex)FIOPAD_INDEX(FIOPAD_103_FUNC_OFFSET) -#define FIOPAD_N29 (FPinIndex)FIOPAD_INDEX(FIOPAD_104_FUNC_OFFSET) -#define FIOPAD_L29 (FPinIndex)FIOPAD_INDEX(FIOPAD_105_FUNC_OFFSET) -#define FIOPAD_N41 (FPinIndex)FIOPAD_INDEX(FIOPAD_106_FUNC_OFFSET) -#define FIOPAD_N39 (FPinIndex)FIOPAD_INDEX(FIOPAD_107_FUNC_OFFSET) -#define FIOPAD_L27 (FPinIndex)FIOPAD_INDEX(FIOPAD_108_FUNC_OFFSET) -#define FIOPAD_J27 (FPinIndex)FIOPAD_INDEX(FIOPAD_109_FUNC_OFFSET) -#define FIOPAD_J25 (FPinIndex)FIOPAD_INDEX(FIOPAD_110_FUNC_OFFSET) -#define FIOPAD_E25 (FPinIndex)FIOPAD_INDEX(FIOPAD_111_FUNC_OFFSET) -#define FIOPAD_G25 (FPinIndex)FIOPAD_INDEX(FIOPAD_112_FUNC_OFFSET) -#define FIOPAD_N23 (FPinIndex)FIOPAD_INDEX(FIOPAD_113_FUNC_OFFSET) -#define FIOPAD_L25 (FPinIndex)FIOPAD_INDEX(FIOPAD_114_FUNC_OFFSET) -#define FIOPAD_J33 (FPinIndex)FIOPAD_INDEX(FIOPAD_115_FUNC_OFFSET) -#define FIOPAD_J35 (FPinIndex)FIOPAD_INDEX(FIOPAD_116_FUNC_OFFSET) -#define FIOPAD_G37 (FPinIndex)FIOPAD_INDEX(FIOPAD_117_FUNC_OFFSET) -#define FIOPAD_E39 (FPinIndex)FIOPAD_INDEX(FIOPAD_118_FUNC_OFFSET) -#define FIOPAD_L39 (FPinIndex)FIOPAD_INDEX(FIOPAD_119_FUNC_OFFSET) -#define FIOPAD_C39 (FPinIndex)FIOPAD_INDEX(FIOPAD_120_FUNC_OFFSET) -#define FIOPAD_E37 (FPinIndex)FIOPAD_INDEX(FIOPAD_121_FUNC_OFFSET) -#define FIOPAD_L41 (FPinIndex)FIOPAD_INDEX(FIOPAD_122_FUNC_OFFSET) -#define FIOPAD_J39 (FPinIndex)FIOPAD_INDEX(FIOPAD_123_FUNC_OFFSET) -#define FIOPAD_J37 (FPinIndex)FIOPAD_INDEX(FIOPAD_124_FUNC_OFFSET) -#define FIOPAD_L35 (FPinIndex)FIOPAD_INDEX(FIOPAD_125_FUNC_OFFSET) -#define FIOPAD_E33 (FPinIndex)FIOPAD_INDEX(FIOPAD_126_FUNC_OFFSET) -#define FIOPAD_E31 (FPinIndex)FIOPAD_INDEX(FIOPAD_127_FUNC_OFFSET) -#define FIOPAD_G31 (FPinIndex)FIOPAD_INDEX(FIOPAD_128_FUNC_OFFSET) -#define FIOPAD_J31 (FPinIndex)FIOPAD_INDEX(FIOPAD_129_FUNC_OFFSET) -#define FIOPAD_L33 (FPinIndex)FIOPAD_INDEX(FIOPAD_130_FUNC_OFFSET) -#define FIOPAD_N31 (FPinIndex)FIOPAD_INDEX(FIOPAD_131_FUNC_OFFSET) -#define FIOPAD_R47 (FPinIndex)FIOPAD_INDEX(FIOPAD_132_FUNC_OFFSET) -#define FIOPAD_R45 (FPinIndex)FIOPAD_INDEX(FIOPAD_133_FUNC_OFFSET) -#define FIOPAD_N47 (FPinIndex)FIOPAD_INDEX(FIOPAD_134_FUNC_OFFSET) -#define FIOPAD_N51 (FPinIndex)FIOPAD_INDEX(FIOPAD_135_FUNC_OFFSET) -#define FIOPAD_L51 (FPinIndex)FIOPAD_INDEX(FIOPAD_136_FUNC_OFFSET) -#define FIOPAD_J51 (FPinIndex)FIOPAD_INDEX(FIOPAD_137_FUNC_OFFSET) -#define FIOPAD_J41 (FPinIndex)FIOPAD_INDEX(FIOPAD_138_FUNC_OFFSET) -#define FIOPAD_E43 (FPinIndex)FIOPAD_INDEX(FIOPAD_139_FUNC_OFFSET) -#define FIOPAD_G43 (FPinIndex)FIOPAD_INDEX(FIOPAD_140_FUNC_OFFSET) -#define FIOPAD_J43 (FPinIndex)FIOPAD_INDEX(FIOPAD_141_FUNC_OFFSET) -#define FIOPAD_J45 (FPinIndex)FIOPAD_INDEX(FIOPAD_142_FUNC_OFFSET) -#define FIOPAD_N45 (FPinIndex)FIOPAD_INDEX(FIOPAD_143_FUNC_OFFSET) -#define FIOPAD_L47 (FPinIndex)FIOPAD_INDEX(FIOPAD_144_FUNC_OFFSET) -#define FIOPAD_L45 (FPinIndex)FIOPAD_INDEX(FIOPAD_145_FUNC_OFFSET) -#define FIOPAD_N49 (FPinIndex)FIOPAD_INDEX(FIOPAD_146_FUNC_OFFSET) -#define FIOPAD_J49 (FPinIndex)FIOPAD_INDEX(FIOPAD_147_FUNC_OFFSET) - -/* register offset of iopad delay */ -#define FIOPAD_AJ51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_10_DELAY_OFFSET) -#define FIOPAD_AL51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_11_DELAY_OFFSET) -#define FIOPAD_AL49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_12_DELAY_OFFSET) -#define FIOPAD_AN47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_13_DELAY_OFFSET) -#define FIOPAD_AR47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_14_DELAY_OFFSET) -#define FIOPAD_AJ53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_23_DELAY_OFFSET) -#define FIOPAD_AG55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_24_DELAY_OFFSET) -#define FIOPAD_AG53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_25_DELAY_OFFSET) -#define FIOPAD_AE55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_26_DELAY_OFFSET) -#define FIOPAD_BA51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_32_DELAY_OFFSET) -#define FIOPAD_BA49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_33_DELAY_OFFSET) -#define FIOPAD_AR55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_34_DELAY_OFFSET) -#define FIOPAD_AU55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_35_DELAY_OFFSET) -#define FIOPAD_A41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_55_DELAY_OFFSET) -#define FIOPAD_C41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_56_DELAY_OFFSET) -#define FIOPAD_A43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_57_DELAY_OFFSET) -#define FIOPAD_A45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_58_DELAY_OFFSET) -#define FIOPAD_C45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_59_DELAY_OFFSET) -#define FIOPAD_A47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_60_DELAY_OFFSET) -#define FIOPAD_A29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_61_DELAY_OFFSET) -#define FIOPAD_C29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_62_DELAY_OFFSET) -#define FIOPAD_C27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_63_DELAY_OFFSET) -#define FIOPAD_A27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_64_DELAY_OFFSET) -#define FIOPAD_AJ49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_65_DELAY_OFFSET) -#define FIOPAD_AL45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_66_DELAY_OFFSET) -#define FIOPAD_AL43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_67_DELAY_OFFSET) -#define FIOPAD_AN45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_68_DELAY_OFFSET) -#define FIOPAD_AG47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_148_DELAY_OFFSET) -#define FIOPAD_AJ47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_69_DELAY_OFFSET) -#define FIOPAD_AG45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_70_DELAY_OFFSET) -#define FIOPAD_AE51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_71_DELAY_OFFSET) -#define FIOPAD_AE49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_72_DELAY_OFFSET) -#define FIOPAD_AG51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_73_DELAY_OFFSET) -#define FIOPAD_AJ45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_74_DELAY_OFFSET) -#define FIOPAD_AC51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_75_DELAY_OFFSET) -#define FIOPAD_AC49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_76_DELAY_OFFSET) -#define FIOPAD_AE47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_77_DELAY_OFFSET) -#define FIOPAD_W47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_78_DELAY_OFFSET) -#define FIOPAD_W49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_80_DELAY_OFFSET) -#define FIOPAD_U51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_81_DELAY_OFFSET) -#define FIOPAD_U49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_82_DELAY_OFFSET) -#define FIOPAD_AE45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_83_DELAY_OFFSET) -#define FIOPAD_AC45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_84_DELAY_OFFSET) -#define FIOPAD_AE43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_85_DELAY_OFFSET) -#define FIOPAD_AA43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_86_DELAY_OFFSET) -#define FIOPAD_AA45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_87_DELAY_OFFSET) -#define FIOPAD_W45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_88_DELAY_OFFSET) -#define FIOPAD_AA47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_89_DELAY_OFFSET) -#define FIOPAD_U45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_90_DELAY_OFFSET) -#define FIOPAD_J55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_92_DELAY_OFFSET) -#define FIOPAD_L53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_93_DELAY_OFFSET) -#define FIOPAD_C55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_94_DELAY_OFFSET) -#define FIOPAD_E55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_95_DELAY_OFFSET) -#define FIOPAD_J53_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_96_DELAY_OFFSET) -#define FIOPAD_L55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_97_DELAY_OFFSET) -#define FIOPAD_N55_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_98_DELAY_OFFSET) -#define FIOPAD_E27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_99_DELAY_OFFSET) -#define FIOPAD_G27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_100_DELAY_OFFSET) -#define FIOPAD_N37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_101_DELAY_OFFSET) -#define FIOPAD_N35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_102_DELAY_OFFSET) -#define FIOPAD_J29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_103_DELAY_OFFSET) -#define FIOPAD_N29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_104_DELAY_OFFSET) -#define FIOPAD_L29_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_105_DELAY_OFFSET) -#define FIOPAD_N41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_106_DELAY_OFFSET) -#define FIOPAD_N39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_107_DELAY_OFFSET) -#define FIOPAD_L27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_108_DELAY_OFFSET) -#define FIOPAD_J27_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_109_DELAY_OFFSET) -#define FIOPAD_J25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_110_DELAY_OFFSET) -#define FIOPAD_E25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_111_DELAY_OFFSET) -#define FIOPAD_G25_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_112_DELAY_OFFSET) -#define FIOPAD_J33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_115_DELAY_OFFSET) -#define FIOPAD_J35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_116_DELAY_OFFSET) -#define FIOPAD_G37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_117_DELAY_OFFSET) -#define FIOPAD_E39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_118_DELAY_OFFSET) -#define FIOPAD_L39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_119_DELAY_OFFSET) -#define FIOPAD_C39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_120_DELAY_OFFSET) -#define FIOPAD_E37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_121_DELAY_OFFSET) -#define FIOPAD_L41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_122_DELAY_OFFSET) -#define FIOPAD_J39_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_123_DELAY_OFFSET) -#define FIOPAD_J37_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_124_DELAY_OFFSET) -#define FIOPAD_L35_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_125_DELAY_OFFSET) -#define FIOPAD_E33_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_126_DELAY_OFFSET) -#define FIOPAD_E31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_127_DELAY_OFFSET) -#define FIOPAD_G31_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_128_DELAY_OFFSET) -#define FIOPAD_L51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_136_DELAY_OFFSET) -#define FIOPAD_J51_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_137_DELAY_OFFSET) -#define FIOPAD_J41_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_138_DELAY_OFFSET) -#define FIOPAD_E43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_139_DELAY_OFFSET) -#define FIOPAD_G43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_140_DELAY_OFFSET) -#define FIOPAD_J43_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_141_DELAY_OFFSET) -#define FIOPAD_J45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_142_DELAY_OFFSET) -#define FIOPAD_N45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_143_DELAY_OFFSET) -#define FIOPAD_L47_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_144_DELAY_OFFSET) -#define FIOPAD_L45_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_145_DELAY_OFFSET) -#define FIOPAD_N49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_146_DELAY_OFFSET) -#define FIOPAD_J49_DELAY (FPinIndex)FIOPAD_INDEX(FIOPAD_147_DELAY_OFFSET) - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ - - - -#ifdef __cplusplus -} - -#endif - -#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/e2000/s/fiopad_config.c b/bsp/phytium/libraries/standalone/board/e2000/s/fiopad_config.c deleted file mode 100644 index ac4fb903af2..00000000000 --- a/bsp/phytium/libraries/standalone/board/e2000/s/fiopad_config.c +++ /dev/null @@ -1,317 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fiopad_config.c - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-18 08:25:29 - * Description:  This file is for io-pad function definition - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 huanghe 2021/11/5 init commit - * 1.1 zhugengyu 2022/3/21 adopt to lastest tech spec. - */ - -/***************************** Include Files *********************************/ -#include "fiopad.h" -#include "fparameters.h" -#include "fpinctrl.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/*****************************************************************************/ -/** - * @name: FIOPadSetSpimMux - * @msg: set iopad mux for spim - * @return {*} - * @param {u32} spim_id, instance id of spi - */ -void FIOPadSetSpimMux(u32 spim_id) -{ - if (FSPI2_ID == spim_id) - { - FPinSetFunc(FIOPAD_A29, FPIN_FUNC0); /* sclk */ - FPinSetFunc(FIOPAD_C29, FPIN_FUNC0); /* txd */ - FPinSetFunc(FIOPAD_C27, FPIN_FUNC0); /* rxd */ - FPinSetFunc(FIOPAD_A27, FPIN_FUNC0); /* csn0 */ - } -} - -/** - * @name: FIOPadSetGpioMux - * @msg: set iopad mux for gpio - * @return {*} - * @param {u32} gpio_id, instance id of gpio - * @param {u32} pin_id, index of pin - */ -void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) -{ - if (FGPIO3_ID == gpio_id) - { - switch (pin_id) - { - case 3: /* gpio 3-a-3 */ - FPinSetFunc(FIOPAD_A29, FPIN_FUNC6); - break; - case 4: /* gpio 3-a-4 */ - FPinSetFunc(FIOPAD_C29, FPIN_FUNC6); - break; - case 5: /* gpio 3-a-5 */ - FPinSetFunc(FIOPAD_C27, FPIN_FUNC6); - break; - case 6: /* gpio 3-a-6 */ - FPinSetFunc(FIOPAD_A27, FPIN_FUNC6); - break; - default: - break; - } - } - else if (FGPIO4_ID == gpio_id) - { - switch (pin_id) - { - case 5: /* gpio 4-a-5 */ - FPinSetFunc(FIOPAD_W47, FPIN_FUNC6); - break; - case 9: /* gpio 4-a-9 */ - FPinSetFunc(FIOPAD_U49, FPIN_FUNC6); - break; - case 10: /* gpio 4-a-10 */ - FPinSetFunc(FIOPAD_AE45, FPIN_FUNC6); - break; - case 11: /* gpio 4-a-11 */ - FPinSetFunc(FIOPAD_AC45, FPIN_FUNC6); - break; - case 12: /* gpio 4-a-12 */ - FPinSetFunc(FIOPAD_AE43, FPIN_FUNC6); - break; - case 13: /* gpio 4-a-13 */ - FPinSetFunc(FIOPAD_AA43, FPIN_FUNC6); - break; - default: - break; - } - } -} - -/** - * @name: FIOPadSetMioMux - * @msg: set iopad mux for mio - * @return {*} - * @param {u32} mio_id, instance id of i2c - */ -void FIOPadSetMioMux(u32 mio_id) -{ - switch (mio_id) - { - case FMIO0_ID: - { - FPinSetFunc(FIOPAD_A37, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_A39, FPIN_FUNC5); /* sda */ - } - break; - case FMIO1_ID: - { - FPinSetFunc(FIOPAD_A41, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_C41, FPIN_FUNC5); /* sda */ - } - break; - case FMIO2_ID: - { - FPinSetFunc(FIOPAD_A43, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_A45, FPIN_FUNC5); /* sda */ - } - break; - case FMIO3_ID: - { - FPinSetFunc(FIOPAD_BA51, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_BA49, FPIN_FUNC4); /* sda */ - } - break; - case FMIO4_ID: - { - FPinSetFunc(FIOPAD_R55, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_U55, FPIN_FUNC4); /* sda */ - } - break; - case FMIO5_ID: - { - FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_U53, FPIN_FUNC4); /* sda */ - } - break; - case FMIO6_ID: - { - FPinSetFunc(FIOPAD_AA53, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_AA55, FPIN_FUNC4); /* sda */ - } - break; - case FMIO7_ID: - { - FPinSetFunc(FIOPAD_A35, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_C35, FPIN_FUNC4); /* sda */ - } - break; - case FMIO8_ID: - { - FPinSetFunc(FIOPAD_AA45, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_W45, FPIN_FUNC4); /* sda */ - } - break; - case FMIO9_ID: - { - FPinSetFunc(FIOPAD_AA47, FPIN_FUNC4); /* scl */ - FPinSetFunc(FIOPAD_U45, FPIN_FUNC4); /* sda */ - } - break; - case FMIO10_ID: - { - FPinSetFunc(FIOPAD_C45, FPIN_FUNC5); /* scl */ - FPinSetFunc(FIOPAD_A47, FPIN_FUNC5); /* sda */ - } - break; - case FMIO11_ID: - { - FPinSetFunc(FIOPAD_N23, FPIN_FUNC3); /* scl */ - FPinSetFunc(FIOPAD_L25, FPIN_FUNC3); /* sda */ - } - break; - case FMIO12_ID: - { - FPinSetFunc(FIOPAD_E37, FPIN_FUNC3); /* scl */ - FPinSetFunc(FIOPAD_L41, FPIN_FUNC3); /* sda */ - } - break; - case FMIO13_ID: - { - FPinSetFunc(FIOPAD_J45, FPIN_FUNC6); /* scl */ - FPinSetFunc(FIOPAD_N45, FPIN_FUNC6); /* sda */ - } - break; - case FMIO14_ID: - { - FPinSetFunc(FIOPAD_L47, FPIN_FUNC6); /* scl */ - FPinSetFunc(FIOPAD_L45, FPIN_FUNC6); /* sda */ - } - break; - case FMIO15_ID: - { - FPinSetFunc(FIOPAD_N49, FPIN_FUNC6); /* scl */ - FPinSetFunc(FIOPAD_J49, FPIN_FUNC6); /* sda */ - } - break; - default: - break; - } -} - -/** - * @name: FIOPadSetTachoMux - * @msg: set iopad mux for pwm_in - * @return {*} - * @param {u32} pwm_in_id, instance id of tacho - */ -void FIOPadSetTachoMux(u32 pwm_in_id) -{ - switch (pwm_in_id) - { - case FTACHO0_ID: - FPinSetFunc(FIOPAD_AN53, FPIN_FUNC1); - break; - case FTACHO1_ID: - FPinSetFunc(FIOPAD_AJ55, FPIN_FUNC1); - break; - case FTACHO2_ID: - FPinSetFunc(FIOPAD_AG55, FPIN_FUNC1); - break; - case FTACHO3_ID: - FPinSetFunc(FIOPAD_AE55, FPIN_FUNC1); - break; - case FTACHO4_ID: - FPinSetFunc(FIOPAD_AC53, FPIN_FUNC1); - break; - case FTACHO5_ID: - FPinSetFunc(FIOPAD_BA49, FPIN_FUNC1); - break; - case FTACHO6_ID: - FPinSetFunc(FIOPAD_C33, FPIN_FUNC2); - break; - case FTACHO7_ID: - FPinSetFunc(FIOPAD_A37, FPIN_FUNC2); - break; - case FTACHO8_ID: - FPinSetFunc(FIOPAD_A41, FPIN_FUNC2); - break; - case FTACHO9_ID: - FPinSetFunc(FIOPAD_A43, FPIN_FUNC2); - break; - case FTACHO10_ID: - FPinSetFunc(FIOPAD_C45, FPIN_FUNC2); - break; - case FTACHO11_ID: - FPinSetFunc(FIOPAD_A29, FPIN_FUNC2); - break; - case FTACHO12_ID: - FPinSetFunc(FIOPAD_C27, FPIN_FUNC2); - break; - case FTACHO13_ID: - FPinSetFunc(FIOPAD_AA45, FPIN_FUNC2); - break; - case FTACHO14_ID: - FPinSetFunc(FIOPAD_AA47, FPIN_FUNC2); - break; - case FTACHO15_ID: - FPinSetFunc(FIOPAD_G55, FPIN_FUNC2); - break; - default: - break; - } -} - -/** - * @name: FIOPadSetUartMux - * @msg: set iopad mux for uart - * @return {*} - * @param {u32} uart_id, instance id of uart - */ -void FIOPadSetUartMux(u32 uart_id) -{ - switch (uart_id) - { - case FUART0_ID: - FPinSetFunc(FIOPAD_J33, FPIN_FUNC4); - FPinSetFunc(FIOPAD_J35, FPIN_FUNC4); - break; - case FUART1_ID: - FPinSetFunc(FIOPAD_AW47, FPIN_FUNC0); - FPinSetFunc(FIOPAD_AU47, FPIN_FUNC0); - break; - case FUART2_ID: - FPinSetFunc(FIOPAD_A43, FPIN_FUNC0); - FPinSetFunc(FIOPAD_A45, FPIN_FUNC0); - break; - case FUART3_ID: - FPinSetFunc(FIOPAD_L33, FPIN_FUNC2); - FPinSetFunc(FIOPAD_N31, FPIN_FUNC2); - break; - default: - break; - } -} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h b/bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h index 4948188f85e..1d02f993b05 100644 --- a/bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h +++ b/bsp/phytium/libraries/standalone/board/e2000/s/fparameters.h @@ -28,20 +28,266 @@ extern "C" { #endif - /***************************** Include Files *********************************/ #include "fparameters_comm.h" /************************** Constant Definitions *****************************/ #define CORE0_AFF 0x200U +#define FCORE_NUM 1 #define FT_CPUS_NR 1U - /* GIC offset */ - #define FT_GIC_REDISTRUBUTIOR_OFFSET 2 +/* register offset of iopad function / pull / driver strength */ +#define FIOPAD_AN55_REG0_OFFSET 0x0000U +#define FIOPAD_AW43_REG0_OFFSET 0x0004U +#define FIOPAD_AR51_REG0_OFFSET 0x0020U +#define FIOPAD_AJ51_REG0_OFFSET 0x0024U +#define FIOPAD_AL51_REG0_OFFSET 0x0028U +#define FIOPAD_AL49_REG0_OFFSET 0x002CU +#define FIOPAD_AN47_REG0_OFFSET 0x0030U +#define FIOPAD_AR47_REG0_OFFSET 0x0034U +#define FIOPAD_BA53_REG0_OFFSET 0x0038U +#define FIOPAD_BA55_REG0_OFFSET 0x003CU +#define FIOPAD_AW53_REG0_OFFSET 0x0040U +#define FIOPAD_AW55_REG0_OFFSET 0x0044U +#define FIOPAD_AU51_REG0_OFFSET 0x0048U +#define FIOPAD_AN53_REG0_OFFSET 0x004CU +#define FIOPAD_AL55_REG0_OFFSET 0x0050U +#define FIOPAD_AJ55_REG0_OFFSET 0x0054U +#define FIOPAD_AJ53_REG0_OFFSET 0x0058U +#define FIOPAD_AG55_REG0_OFFSET 0x005CU +#define FIOPAD_AG53_REG0_OFFSET 0x0060U +#define FIOPAD_AE55_REG0_OFFSET 0x0064U +#define FIOPAD_AC55_REG0_OFFSET 0x0068U +#define FIOPAD_AC53_REG0_OFFSET 0x006CU +#define FIOPAD_AR45_REG0_OFFSET 0x0070U +#define FIOPAD_BA51_REG0_OFFSET 0x0074U +#define FIOPAD_BA49_REG0_OFFSET 0x0078U +#define FIOPAD_AR55_REG0_OFFSET 0x007CU +#define FIOPAD_AU55_REG0_OFFSET 0x0080U +#define FIOPAD_AR53_REG0_OFFSET 0x0084U +#define FIOPAD_BA45_REG0_OFFSET 0x0088U +#define FIOPAD_AW51_REG0_OFFSET 0x008CU +#define FIOPAD_A31_REG0_OFFSET 0x0090U +#define FIOPAD_R53_REG0_OFFSET 0x0094U +#define FIOPAD_R55_REG0_OFFSET 0x0098U +#define FIOPAD_U55_REG0_OFFSET 0x009CU +#define FIOPAD_W55_REG0_OFFSET 0x00A0U +#define FIOPAD_U53_REG0_OFFSET 0x00A4U +#define FIOPAD_AA53_REG0_OFFSET 0x00A8U +#define FIOPAD_AA55_REG0_OFFSET 0x00ACU +#define FIOPAD_AW47_REG0_OFFSET 0x00B0U +#define FIOPAD_AU47_REG0_OFFSET 0x00B4U +#define FIOPAD_A35_REG0_OFFSET 0x00B8U +#define FIOPAD_C35_REG0_OFFSET 0x00BCU +#define FIOPAD_C33_REG0_OFFSET 0x00C0U +#define FIOPAD_A33_REG0_OFFSET 0x00C4U +#define FIOPAD_A37_REG0_OFFSET 0x00C8U +#define FIOPAD_A39_REG0_OFFSET 0x00CCU +#define FIOPAD_A41_REG0_OFFSET 0x00D0U +#define FIOPAD_C41_REG0_OFFSET 0x00D4U +#define FIOPAD_A43_REG0_OFFSET 0x00D8U +#define FIOPAD_A45_REG0_OFFSET 0x00DCU +#define FIOPAD_C45_REG0_OFFSET 0x00E0U +#define FIOPAD_A47_REG0_OFFSET 0x00E4U +#define FIOPAD_A29_REG0_OFFSET 0x00E8U +#define FIOPAD_C29_REG0_OFFSET 0x00ECU +#define FIOPAD_C27_REG0_OFFSET 0x00F0U +#define FIOPAD_A27_REG0_OFFSET 0x00F4U +#define FIOPAD_AJ49_REG0_OFFSET 0x00F8U +#define FIOPAD_AL45_REG0_OFFSET 0x00FCU +#define FIOPAD_AL43_REG0_OFFSET 0x0100U +#define FIOPAD_AN45_REG0_OFFSET 0x0104U +#define FIOPAD_AG47_REG0_OFFSET 0x0108U +#define FIOPAD_AJ47_REG0_OFFSET 0x010CU +#define FIOPAD_AG45_REG0_OFFSET 0x0110U +#define FIOPAD_AE51_REG0_OFFSET 0x0114U +#define FIOPAD_AE49_REG0_OFFSET 0x0118U +#define FIOPAD_AG51_REG0_OFFSET 0x011CU +#define FIOPAD_AJ45_REG0_OFFSET 0x0120U +#define FIOPAD_AC51_REG0_OFFSET 0x0124U +#define FIOPAD_AC49_REG0_OFFSET 0x0128U +#define FIOPAD_AE47_REG0_OFFSET 0x012CU +#define FIOPAD_W47_REG0_OFFSET 0x0130U +#define FIOPAD_W51_REG0_OFFSET 0x0134U +#define FIOPAD_W49_REG0_OFFSET 0x0138U +#define FIOPAD_U51_REG0_OFFSET 0x013CU +#define FIOPAD_U49_REG0_OFFSET 0x0140U +#define FIOPAD_AE45_REG0_OFFSET 0x0144U +#define FIOPAD_AC45_REG0_OFFSET 0x0148U +#define FIOPAD_AE43_REG0_OFFSET 0x014CU +#define FIOPAD_AA43_REG0_OFFSET 0x0150U +#define FIOPAD_AA45_REG0_OFFSET 0x0154U +#define FIOPAD_W45_REG0_OFFSET 0x0158U +#define FIOPAD_AA47_REG0_OFFSET 0x015CU +#define FIOPAD_U45_REG0_OFFSET 0x0160U +#define FIOPAD_G55_REG0_OFFSET 0x0164U +#define FIOPAD_J55_REG0_OFFSET 0x0168U +#define FIOPAD_L53_REG0_OFFSET 0x016CU +#define FIOPAD_C55_REG0_OFFSET 0x0170U +#define FIOPAD_E55_REG0_OFFSET 0x0174U +#define FIOPAD_J53_REG0_OFFSET 0x0178U +#define FIOPAD_L55_REG0_OFFSET 0x017CU +#define FIOPAD_N55_REG0_OFFSET 0x0180U +#define FIOPAD_C53_REG0_OFFSET 0x0184U +#define FIOPAD_E53_REG0_OFFSET 0x0188U +#define FIOPAD_E27_REG0_OFFSET 0x018CU +#define FIOPAD_G27_REG0_OFFSET 0x0190U +#define FIOPAD_N37_REG0_OFFSET 0x0194U +#define FIOPAD_N35_REG0_OFFSET 0x0198U +#define FIOPAD_J29_REG0_OFFSET 0x019CU +#define FIOPAD_N29_REG0_OFFSET 0x01A0U +#define FIOPAD_L29_REG0_OFFSET 0x01A4U +#define FIOPAD_N41_REG0_OFFSET 0x01A8U +#define FIOPAD_N39_REG0_OFFSET 0x01ACU +#define FIOPAD_L27_REG0_OFFSET 0x01B0U +#define FIOPAD_J27_REG0_OFFSET 0x01B4U +#define FIOPAD_J25_REG0_OFFSET 0x01B8U +#define FIOPAD_E25_REG0_OFFSET 0x01BCU +#define FIOPAD_G25_REG0_OFFSET 0x01C0U +#define FIOPAD_N23_REG0_OFFSET 0x01C4U +#define FIOPAD_L25_REG0_OFFSET 0x01C8U +#define FIOPAD_J33_REG0_OFFSET 0x01CCU +#define FIOPAD_J35_REG0_OFFSET 0x01D0U +#define FIOPAD_G37_REG0_OFFSET 0x01D4U +#define FIOPAD_E39_REG0_OFFSET 0x01D8U +#define FIOPAD_L39_REG0_OFFSET 0x01DCU +#define FIOPAD_C39_REG0_OFFSET 0x01E0U +#define FIOPAD_E37_REG0_OFFSET 0x01E4U +#define FIOPAD_L41_REG0_OFFSET 0x01E8U +#define FIOPAD_J39_REG0_OFFSET 0x01ECU +#define FIOPAD_J37_REG0_OFFSET 0x01F0U +#define FIOPAD_L35_REG0_OFFSET 0x01F4U +#define FIOPAD_E33_REG0_OFFSET 0x01F8U +#define FIOPAD_E31_REG0_OFFSET 0x01FCU +#define FIOPAD_G31_REG0_OFFSET 0x0200U +#define FIOPAD_J31_REG0_OFFSET 0x0204U +#define FIOPAD_L33_REG0_OFFSET 0x0208U +#define FIOPAD_N31_REG0_OFFSET 0x020CU +#define FIOPAD_R47_REG0_OFFSET 0x0210U +#define FIOPAD_R45_REG0_OFFSET 0x0214U +#define FIOPAD_N47_REG0_OFFSET 0x0218U +#define FIOPAD_N51_REG0_OFFSET 0x021CU +#define FIOPAD_L51_REG0_OFFSET 0x0220U +#define FIOPAD_J51_REG0_OFFSET 0x0224U +#define FIOPAD_J41_REG0_OFFSET 0x0228U +#define FIOPAD_E43_REG0_OFFSET 0x022CU +#define FIOPAD_G43_REG0_OFFSET 0x0230U +#define FIOPAD_J43_REG0_OFFSET 0x0234U +#define FIOPAD_J45_REG0_OFFSET 0x0238U +#define FIOPAD_N45_REG0_OFFSET 0x023CU +#define FIOPAD_L47_REG0_OFFSET 0x0240U +#define FIOPAD_L45_REG0_OFFSET 0x0244U +#define FIOPAD_N49_REG0_OFFSET 0x0248U +#define FIOPAD_J49_REG0_OFFSET 0x024CU + +#define FIOPAD_REG0_BEG_OFFSET FIOPAD_AN55_REG0_OFFSET +#define FIOPAD_REG0_END_OFFSET FIOPAD_J49_REG0_OFFSET + +/* register offset of iopad delay */ +#define FIOPAD_AJ51_REG1_OFFSET 0x1024U +#define FIOPAD_AL51_REG1_OFFSET 0x1028U +#define FIOPAD_AL49_REG1_OFFSET 0x102CU +#define FIOPAD_AN47_REG1_OFFSET 0x1030U +#define FIOPAD_AR47_REG1_OFFSET 0x1034U +#define FIOPAD_AJ53_REG1_OFFSET 0x1058U +#define FIOPAD_AG55_REG1_OFFSET 0x105CU +#define FIOPAD_AG53_REG1_OFFSET 0x1060U +#define FIOPAD_AE55_REG1_OFFSET 0x1064U +#define FIOPAD_BA51_REG1_OFFSET 0x1074U +#define FIOPAD_BA49_REG1_OFFSET 0x1078U +#define FIOPAD_AR55_REG1_OFFSET 0x107CU +#define FIOPAD_AU55_REG1_OFFSET 0x1080U +#define FIOPAD_A41_REG1_OFFSET 0x10D0U +#define FIOPAD_C41_REG1_OFFSET 0x10D4U +#define FIOPAD_A43_REG1_OFFSET 0x10D8U +#define FIOPAD_A45_REG1_OFFSET 0x10DCU +#define FIOPAD_C45_REG1_OFFSET 0x10E0U +#define FIOPAD_A47_REG1_OFFSET 0x10E4U +#define FIOPAD_A29_REG1_OFFSET 0x10E8U +#define FIOPAD_C29_REG1_OFFSET 0x10ECU +#define FIOPAD_C27_REG1_OFFSET 0x10F0U +#define FIOPAD_A27_REG1_OFFSET 0x10F4U +#define FIOPAD_AJ49_REG1_OFFSET 0x10F8U +#define FIOPAD_AL45_REG1_OFFSET 0x10FCU +#define FIOPAD_AL43_REG1_OFFSET 0x1100U +#define FIOPAD_AN45_REG1_OFFSET 0x1104U +#define FIOPAD_AG47_REG1_OFFSET 0x1108U +#define FIOPAD_AJ47_REG1_OFFSET 0x110CU +#define FIOPAD_AG45_REG1_OFFSET 0x1110U +#define FIOPAD_AE51_REG1_OFFSET 0x1114U +#define FIOPAD_AE49_REG1_OFFSET 0x1118U +#define FIOPAD_AG51_REG1_OFFSET 0x111CU +#define FIOPAD_AJ45_REG1_OFFSET 0x1120U +#define FIOPAD_AC51_REG1_OFFSET 0x1124U +#define FIOPAD_AC49_REG1_OFFSET 0x1128U +#define FIOPAD_AE47_REG1_OFFSET 0x112CU +#define FIOPAD_W47_REG1_OFFSET 0x1130U +#define FIOPAD_W49_REG1_OFFSET 0x1138U +#define FIOPAD_U51_REG1_OFFSET 0x113CU +#define FIOPAD_U49_REG1_OFFSET 0x1140U +#define FIOPAD_AE45_REG1_OFFSET 0x1144U +#define FIOPAD_AC45_REG1_OFFSET 0x1148U +#define FIOPAD_AE43_REG1_OFFSET 0x114CU +#define FIOPAD_AA43_REG1_OFFSET 0x1150U +#define FIOPAD_AA45_REG1_OFFSET 0x1154U +#define FIOPAD_W45_REG1_OFFSET 0x1158U +#define FIOPAD_AA47_REG1_OFFSET 0x115CU +#define FIOPAD_U45_REG1_OFFSET 0x1160U +#define FIOPAD_J55_REG1_OFFSET 0x1168U +#define FIOPAD_L53_REG1_OFFSET 0x116CU +#define FIOPAD_C55_REG1_OFFSET 0x1170U +#define FIOPAD_E55_REG1_OFFSET 0x1174U +#define FIOPAD_J53_REG1_OFFSET 0x1178U +#define FIOPAD_L55_REG1_OFFSET 0x117CU +#define FIOPAD_N55_REG1_OFFSET 0x1180U +#define FIOPAD_E27_REG1_OFFSET 0x118CU +#define FIOPAD_G27_REG1_OFFSET 0x1190U +#define FIOPAD_N37_REG1_OFFSET 0x1194U +#define FIOPAD_N35_REG1_OFFSET 0x1198U +#define FIOPAD_J29_REG1_OFFSET 0x119CU +#define FIOPAD_N29_REG1_OFFSET 0x11A0U +#define FIOPAD_L29_REG1_OFFSET 0x11A4U +#define FIOPAD_N41_REG1_OFFSET 0x11A8U +#define FIOPAD_N39_REG1_OFFSET 0x11ACU +#define FIOPAD_L27_REG1_OFFSET 0x11B0U +#define FIOPAD_J27_REG1_OFFSET 0x11B4U +#define FIOPAD_J25_REG1_OFFSET 0x11B8U +#define FIOPAD_E25_REG1_OFFSET 0x11BCU +#define FIOPAD_G25_REG1_OFFSET 0x11C0U +#define FIOPAD_J33_REG1_OFFSET 0x11CCU +#define FIOPAD_J35_REG1_OFFSET 0x11D0U +#define FIOPAD_G37_REG1_OFFSET 0x11D4U +#define FIOPAD_E39_REG1_OFFSET 0x11D8U +#define FIOPAD_L39_REG1_OFFSET 0x11DCU +#define FIOPAD_C39_REG1_OFFSET 0x11E0U +#define FIOPAD_E37_REG1_OFFSET 0x11E4U +#define FIOPAD_L41_REG1_OFFSET 0x11E8U +#define FIOPAD_J39_REG1_OFFSET 0x11ECU +#define FIOPAD_J37_REG1_OFFSET 0x11F0U +#define FIOPAD_L35_REG1_OFFSET 0x11F4U +#define FIOPAD_E33_REG1_OFFSET 0x11F8U +#define FIOPAD_E31_REG1_OFFSET 0x11FCU +#define FIOPAD_G31_REG1_OFFSET 0x1200U +#define FIOPAD_L51_REG1_OFFSET 0x1220U +#define FIOPAD_J51_REG1_OFFSET 0x1224U +#define FIOPAD_J41_REG1_OFFSET 0x1228U +#define FIOPAD_E43_REG1_OFFSET 0x122CU +#define FIOPAD_G43_REG1_OFFSET 0x1230U +#define FIOPAD_J43_REG1_OFFSET 0x1234U +#define FIOPAD_J45_REG1_OFFSET 0x1238U +#define FIOPAD_N45_REG1_OFFSET 0x123CU +#define FIOPAD_L47_REG1_OFFSET 0x1240U +#define FIOPAD_L45_REG1_OFFSET 0x1244U +#define FIOPAD_N49_REG1_OFFSET 0x1248U +#define FIOPAD_J49_REG1_OFFSET 0x124CU + +#define FIOPAD_REG1_BEG_OFFSET FIOPAD_AJ51_REG1_OFFSET +#define FIOPAD_REG1_END_OFFSET FIOPAD_J49_REG1_OFFSET + /*****************************************************************************/ @@ -50,4 +296,4 @@ extern "C" #endif -#endif \ No newline at end of file +#endif diff --git a/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.c b/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.c deleted file mode 100644 index 7591b19fade..00000000000 --- a/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fioctrl.c - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-18 08:25:29 - * Description:  This files is for io-ctrl function implementation (io-mux/io-config/io-delay) - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 zhugengyu 2022/2/22 init commit - */ - - -/***************************** Include Files *********************************/ -#include "fparameters.h" -#include "fio.h" -#include "fkernel.h" -#include "fassert.h" -#include "fdebug.h" - -#include "fioctrl.h" -#include "fpinctrl.h" - -/************************** Constant Definitions *****************************/ -/* Bit[0] : 输入延迟功能使能 */ -#define FIOCTRL_DELAY_EN(delay_beg) BIT(delay_beg) -#define FIOCTRL_INPUT_DELAY_OFF 0 - -/* Bit[3:1] : 输入延迟精调档位选择 */ -#define FIOCTRL_DELICATE_DELAY_MASK(delay_beg) GENMASK((delay_beg + 3), (delay_beg + 1)) -#define FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 3), (delay_beg + 1)) -#define FIOCTRL_DELICATE_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 3), (delay_beg + 1)) - -/* Bit[6:4] : 输入延迟粗调档位选择 */ -#define FIOCTRL_ROUGH_DELAY_MASK(delay_beg) GENMASK((delay_beg + 6), (delay_beg + 4)) -#define FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg) GET_REG32_BITS((reg_val), (delay_beg + 6), (delay_beg + 4)) -#define FIOCTRL_ROUGH_DELAY_SET(val, delay_beg) SET_REG32_BITS((val), (delay_beg + 6), (delay_beg + 4)) - -/* Bit[7] : 保留 */ -/* Bit[8] : 输出延迟功能使能 */ - -/* Bit[11:9] : 输出延迟精调档位选择 */ -/* Bit [14:12] : 输出延迟粗调档位选择 */ -/* Bit [15] : 保留 */ - -#define FIOCTRL_FUNC_BEG_OFF(reg_bit) ((reg_bit) + 0) -#define FIOCTRL_FUNC_END_OFF(reg_bit) ((reg_bit) + 1) /* bit[1:0] 复用功能占2个位 */ -#define FIOCTRL_PULL_BEG_OFF(reg_bit) ((reg_bit) + 2) -#define FIOCTRL_PULL_END_OFF(reg_bit) ((reg_bit) + 3) /* bit[3:2] 上下拉功能占2个位 */ - -#define FIOCTRL_DELAY_IN_BEG_OFF(reg_bit) ((reg_bit) + 0) -#define FIOCTRL_DELAY_IN_END_OFF(reg_bit) ((reg_bit) + 7) /* bit[8:1] 输入延时占7个位 */ -#define FIOCTRL_DELAY_OUT_BEG_OFF(reg_bit) ((reg_bit) + 8) -#define FIOCTRL_DELAY_OUT_END_OFF(reg_bit) ((reg_bit) + 15) /* bit[15:9] 输出延时占7个位 */ - -/* 芯片引脚控制寄存器的起止位置 */ -#define FIOCTRL_REG_OFFSET_MIN 0x200 -#define FIOCTRL_REG_OFFSET_MAX 0x22c - -/* 芯片引脚延时寄存器的起止位置 */ -#define FIOCTRL_DELAY_REG_OFFSET_MIN 0x400 -#define FIOCTRL_DELAY_REG_OFFSET_MAX 0x404 - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -#define FIOCTRL_DEBUG_TAG "FIOCTRL" -#define FIOCTRL_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOCTRL_WARN(format, ...) FT_DEBUG_PRINT_W(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOCTRL_INFO(format, ...) FT_DEBUG_PRINT_I(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__) -#define FIOCTRL_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOCTRL_DEBUG_TAG, format, ##__VA_ARGS__) - -#define FIOCTRL_ASSERT_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_REG_OFFSET_MAX)), "invalid pin register off @%d", (pin.reg_off)) -#define FIOCTRL_ASSERT_FUNC(func) FASSERT_MSG((func < FPIN_NUM_OF_FUNC), "invalid func as %d", (func)) -#define FIOCTRL_ASSERT_PULL(pull) FASSERT_MSG((pull < FPIN_NUM_OF_PULL), "invalid pull as %d", (pull)) - -#define FIOCTRL_ASSERT_DELAY_REG_OFF(pin) FASSERT_MSG(((pin.reg_off >= FIOCTRL_DELAY_REG_OFFSET_MIN) && (pin.reg_off <= FIOCTRL_DELAY_REG_OFFSET_MAX)), "invalid delay pin register off @%d", (pin.reg_off)) -#define FIOCTRL_ASSERT_DELAY(delay) FASSERT_MSG(((delay) < FPIN_NUM_OF_DELAY), "invalid delay as %d", (delay)); -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/*****************************************************************************/ - -/** - * @name: FPinGetFunc - * @msg: 获取IO引脚当前的复用功能 - * @return {FPinFunc} 当前的复用功能 - * @param {FPinIndex} pin IO引脚索引 - * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值 - */ -FPinFunc FPinGetFunc(const FPinIndex pin) -{ - FIOCTRL_ASSERT_REG_OFF(pin); - - u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit); - u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 func = GET_REG32_BITS(reg_val, func_end, func_beg); - FIOCTRL_ASSERT_FUNC(func); - - return (FPinFunc)GET_REG32_BITS(reg_val, func_end, func_beg); -} - -/** - * @name: FPinSetFunc - * @msg: 设置IO引脚复用功能 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @param {FPinFunc} func IO复用功能 - * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值 - */ -void FPinSetFunc(const FPinIndex pin, FPinFunc func) -{ - FIOCTRL_ASSERT_REG_OFF(pin); - FIOCTRL_ASSERT_FUNC(func); - - u32 func_beg = FIOCTRL_FUNC_BEG_OFF(pin.reg_bit); - u32 func_end = FIOCTRL_FUNC_END_OFF(pin.reg_bit); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - - reg_val &= ~GENMASK(func_end, func_beg); - reg_val |= SET_REG32_BITS(func, func_end, func_beg); - - FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val); - return; -} - -/** - * @name: FPinGetPull - * @msg: 获取IO引脚当前的上下拉设置 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @note 参考编程手册，使用 FIOCTRL_INDEX 宏定义index的值 - */ -FPinPull FPinGetPull(const FPinIndex pin) -{ - FIOCTRL_ASSERT_REG_OFF(pin); - - u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit); - u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 pull = GET_REG32_BITS(reg_val, pull_end, pull_beg); - - FIOCTRL_ASSERT_PULL(pull); - return (FPinPull)pull; -} - -/** - * @name: FPinSetPull - * @msg: 设置IO引脚当前的上下拉 - * @return {*} - * @param {FPinIndex} pin IO引脚索引 - * @param {FPinPull} pull 上下拉设置 - */ -void FPinSetPull(const FPinIndex pin, FPinPull pull) -{ - FIOCTRL_ASSERT_REG_OFF(pin); - FIOCTRL_ASSERT_PULL(pull); - - u32 pull_beg = FIOCTRL_PULL_BEG_OFF(pin.reg_bit); - u32 pull_end = FIOCTRL_PULL_END_OFF(pin.reg_bit); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - - reg_val &= ~GENMASK(pull_end, pull_beg); - reg_val |= SET_REG32_BITS(pull, pull_end, pull_beg); - - FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val); - return; -} - -/** - * @name: FPinGetDelay - * @msg: 获取IO引脚当前的延时设置 - * @return {FPinDelay} 当前的延时设置 - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - * @param {FPinDelayType} type 精调/粗调延时 - */ -FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type) -{ - FIOCTRL_ASSERT_DELAY_REG_OFF(pin); - u8 delay = 0; - const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 delay_beg = 0, delay_end = 0; - - if (FPIN_OUTPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off); - } - else if (FPIN_INPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off); - } - else - { - FASSERT(0); - } - - if (FPIN_DELAY_FINE_TUNING == type) - { - delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg); /* bit[3:1] delicate delay tune */ - } - else if (FPIN_DELAY_COARSE_TUNING == type) - { - delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg); /* bit[6:4] rough delay adjust */ - } - else - { - FASSERT(0); - } - - FIOCTRL_ASSERT_DELAY(delay); - return (FPinDelay)delay; -} - - -/** - * @name: FPinGetDelayEn - * @msg: 获取IO引脚当前的延时使能标志位 - * @return {*} - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - */ -boolean FPinGetDelayEn(const FPinIndex pin, FPinDelayDir dir) -{ - FIOCTRL_ASSERT_DELAY_REG_OFF(pin); - boolean enabled = FALSE; - const u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 delay_beg = 0, delay_end = 0; - - if (FPIN_OUTPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off); - } - else if (FPIN_INPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off); - } - else - { - FASSERT(0); - } - - if (FIOCTRL_DELAY_EN(delay_beg) & reg_val) - { - enabled = TRUE; - } - - return enabled; -} - -/** - * @name: FPinSetDelay - * @msg: 设置IO引脚延时 - * @return {*} - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - * @param {FPinDelayType} type 精调/粗调延时 - * @param {FPinDelay} delay 延时档位设置 0 ~ 8 档可用 - */ -void FPinSetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type, FPinDelay delay) -{ - FIOCTRL_ASSERT_DELAY_REG_OFF(pin); - FIOCTRL_ASSERT_DELAY(delay); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 delay_beg = 0, delay_end = 0; - - if (FPIN_OUTPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off); - } - else if (FPIN_INPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off); - } - else - { - FASSERT(0); - } - - if (FPIN_DELAY_FINE_TUNING == type) - { - reg_val &= ~FIOCTRL_DELICATE_DELAY_MASK(delay_beg); - delay = FIOCTRL_DELICATE_DELAY_GET(reg_val, delay_beg); - } - else if (FPIN_DELAY_COARSE_TUNING == type) - { - reg_val &= ~FIOCTRL_ROUGH_DELAY_MASK(delay_beg); - delay = FIOCTRL_ROUGH_DELAY_GET(reg_val, delay_beg); - } - else - { - FASSERT(0); - } - - FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val); - return; -} - -/** - * @name: FPinSetDelayEn - * @msg: 使能/去使能IO引脚延时 - * @return {*} - * @param {FPinIndex} pin IO引脚延时设置索引 - * @param {FPinDelayDir} dir 输入/输出延时 - * @param {boolean} enable TRUE: 使能, FALSE: 去使能 - */ -void FPinSetDelayEn(const FPinIndex pin, FPinDelayDir dir, boolean enable) -{ - FIOCTRL_ASSERT_DELAY_REG_OFF(pin); - u32 reg_val = FtIn32(FIOCTRL_REG_BASE_ADDR + pin.reg_off); - u32 delay_beg = 0, delay_end = 0; - - if (FPIN_OUTPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_OUT_BEG_OFF(pin.reg_off); - } - else if (FPIN_INPUT_DELAY == dir) - { - delay_beg = FIOCTRL_DELAY_IN_BEG_OFF(pin.reg_off); - } - else - { - FASSERT(0); - } - - reg_val &= ~FIOCTRL_DELAY_EN(delay_beg); - if (enable) - { - reg_val |= FIOCTRL_DELAY_EN(delay_beg); - } - - FtOut32(FIOCTRL_REG_BASE_ADDR + pin.reg_off, reg_val); - return; -} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.h b/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.h deleted file mode 100644 index 5d0caac525d..00000000000 --- a/bsp/phytium/libraries/standalone/board/ft2004/fioctrl.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fioctrl.h - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-18 08:25:35 - * Description:  This files is for io-ctrl function definition (io-mux/io-config/io-delay) - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 zhugengyu 2022/2/22 init commit - */ - - -#ifndef BOARD_D2000_FIOCTRL_H -#define BOARD_D2000_FIOCTRL_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -/***************************** Include Files *********************************/ -#include "ftypes.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -#define FIOCTRL_INDEX(offset, func_beg) \ - { \ - /* reg_off */ (offset), \ - /* reg_bit */ (func_beg) \ - } - -/************************** Variable Definitions *****************************/ -#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24) -#define FIOCTRL_SPI0_CSN0_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 16) -#define FIOCTRL_SPI0_SCK_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 12) -#define FIOCTRL_SPI0_SO_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 8) -#define FIOCTRL_SPI0_SI_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 4) - -#define FIOCTRL_TJTAG_TDI_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 24) /* can0-tx: func 1 */ -#define FIOCTRL_SWDITMS_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 12) /* can0-rx: func 1 */ - -#define FIOCTRL_NTRST_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 20) /* can1-tx: func 1 */ -#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* can1-rx: func 1 */ - -#define FIOCTRL_I2C0_SCL_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 24) /* i2c0-scl: func 0 */ -#define FIOCTRL_I2C0_SDA_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 20) /* i2c0-sda: func 0 */ -#define FIOCTRL_ALL_PLL_LOCK_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 28) /* i2c1-scl: func 2 */ -#define FIOCTRL_CRU_CLK_OBV_PAD (FPinIndex)FIOCTRL_INDEX(0x200, 24) /* i2c1-sda: func 2 */ -#define FIOCTRL_SWDO_SWJ_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 8) /* i2c2-scl: func 2 */ -#define FIOCTRL_TDO_SWJ_IN_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 4) /* i2c2-sda: func 2 */ -#define FIOCTRL_HDT_MB_DONE_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x204, 0) /* i2c3-scl: func 2 */ -#define FIOCTRL_HDT_MB_FAIL_STATE_PAD (FPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */ - -#define FIOCTRL_UART_2_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x210, 0) /* spi1_csn0: func 1 */ -#define FIOCTRL_UART_2_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */ -#define FIOCTRL_UART_3_RXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */ -#define FIOCTRL_UART_3_TXD_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 20) /* spi1_si: func 1 */ -#define FIOCTRL_QSPI_CSN2_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 8) /* spi1_csn1: func 1 */ -#define FIOCTRL_QSPI_CSN3_PAD (FPinIndex)FIOCTRL_INDEX(0x214, 4) /* spi1_csn2: func 1 */ - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/phytium/libraries/standalone/board/ft2004/fparameters.h b/bsp/phytium/libraries/standalone/board/ft2004/fparameters.h deleted file mode 100644 index 61a1943a5b4..00000000000 --- a/bsp/phytium/libraries/standalone/board/ft2004/fparameters.h +++ /dev/null @@ -1,327 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fparameters.h - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-17 18:01:11 - * Description:  This file is for - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - */ - -#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H -#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H - -#ifdef __cplusplus -extern "C" -{ -#endif - -#if !defined(__ASSEMBLER__) -#include "ftypes.h" -#endif - -#define CORE0_AFF 0x0 -#define CORE1_AFF 0x1 -#define CORE2_AFF 0x100 -#define CORE3_AFF 0x101 - - -/* cache */ -#define CACHE_LINE_ADDR_MASK 0x3F -#define CACHE_LINE 64U - - -/* Device register address */ -#define FDEV_BASE_ADDR 0x28000000 -#define FDEV_END_ADDR 0x2FFFFFFF - -/* PCI */ - -#define FPCIE_NUM 1 -#define FPCIE0_ID 0 -#define FPCIE0_MISC_IRQ_NUM 59 - -#define FPCIE_CFG_MAX_NUM_OF_BUS 256 -#define FPCIE_CFG_MAX_NUM_OF_DEV 32 -#define FPCIE_CFG_MAX_NUM_OF_FUN 8 - -#define FPCI_CONFIG_BASE_ADDR 0x40000000 -#define FPCI_CONFIG_REG_LENGTH 0x10000000 - -#define FPCI_IO_CONFIG_BASE_ADDR 0x50000000 -#define FPCI_IO_CONFIG_REG_LENGTH 0x08000000 - -#define FPCI_MEM32_BASE_ADDR 0x58000000 -#define FPCI_MEM32_REG_LENGTH 0x27ffffff - -#define FPCI_MEM64_BASE_ADDR 0x1000000000 -#define FPCI_MEM64_REG_LENGTH 0x1000000000 - -#define FPCI_EU0_C0_CONTROL_BASE_ADDR 0x29000000 -#define FPCI_EU0_C1_CONTROL_BASE_ADDR 0x29010000 -#define FPCI_EU0_C2_CONTROL_BASE_ADDR 0x29020000 -#define FPCI_EU1_C0_CONTROL_BASE_ADDR 0x29030000 -#define FPCI_EU1_C1_CONTROL_BASE_ADDR 0x29040000 -#define FPCI_EU1_C2_CONTROL_BASE_ADDR 0x29050000 - -#define FPCI_EU0_CONFIG_BASE_ADDR 0x29100000 -#define FPCI_EU1_CONFIG_BASE_ADDR 0x29101000 - -#define FPCI_INTA_IRQ_NUM 60 -#define FPCI_INTB_IRQ_NUM 61 -#define FPCI_INTC_IRQ_NUM 62 -#define FPCI_INTD_IRQ_NUM 63 - -#define FPCI_NEED_SKIP 1 - -/* platform ahci host */ -#define PLAT_AHCI_HOST_MAX_COUNT 5 -#define AHCI_BASE_0 0 -#define AHCI_BASE_1 0 -#define AHCI_BASE_2 0 -#define AHCI_BASE_3 0 -#define AHCI_BASE_4 0 - -#define AHCI_IRQ_0 0 -#define AHCI_IRQ_1 0 -#define AHCI_IRQ_2 0 -#define AHCI_IRQ_3 0 -#define AHCI_IRQ_4 0 - -// timer -#define GENERIC_TIMER_NS_IRQ_NUM 30 -#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ - -// UART - -#define FUART_NUM 4 -#define FUART_REG_LENGTH 0x18000 - -#define FUART0_ID 0 -#define FUART0_IRQ_NUM 38 -#define FUART0_BASE_ADDR 0x28000000 -#define FUART0_CLK_FREQ_HZ 48000000 - -#define FUART1_ID 1 -#define FUART1_IRQ_NUM 39 -#define FUART1_BASE_ADDR 0x28001000 -#define FUART1_CLK_FREQ_HZ 48000000 - -#define FUART2_ID 2 -#define FUART2_IRQ_NUM 40 -#define FUART2_BASE_ADDR 0x28002000 -#define FUART2_CLK_FREQ_HZ 48000000 - -#define FUART3_BASE_ADDR 0x28003000 -#define FUART3_ID 3 -#define FUART3_IRQ_NUM 41 -#define FUART3_CLK_FREQ_HZ 48000000 - -#define FT_STDOUT_BASE_ADDRESS FUART1_BASE_ADDR -#define FT_STDIN_BASE_ADDRESS FUART1_BASE_ADDR - -/****** GIC v3 *****/ -#define FT_GICV3_INSTANCES_NUM 1U -#define GICV3_REG_LENGTH 0x00009000 - -/* - * The maximum priority value that can be used in the GIC. - */ -#define GICV3_MAX_INTR_PRIO_VAL 240U -#define GICV3_INTR_PRIO_MASK 0x000000f0U -#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ -#define SGI_INT_MAX 16 -#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ -#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ -#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ -#define GICV3_BASE_ADDR 0x29900000U -#define GICV3_DISTRIBUTOR_BASE_ADDR (GICV3_BASE_ADDR + 0) -#define GICV3_RD_BASE_ADDR (GICV3_BASE_ADDR + 0x80000U) -#define GICV3_RD_OFFSET (2U << 16) -#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM - -/* GPIO */ -#define FGPIO0_BASE_ADDR 0x28004000 -#define FGPIO1_BASE_ADDR 0x28005000 - -#define FGPIO0_ID 0 -#define FGPIO1_ID 1 -#define FGPIO_NUM 2 - -#define FGPIO0_IRQ_NUM 42 /* gpio0 irq number */ -#define FGPIO1_IRQ_NUM 43 /* gpio1 irq number */ - -/* SPI */ -#define FSPI0_BASE_ADDR 0x2800c000 -#define FSPI1_BASE_ADDR 0x28013000 -#define FSPI0_ID 0 -#define FSPI1_ID 1 -#define FSPI_CLK_FREQ_HZ 48000000 -#define FSPI_NUM 2 -#define FSPI0_IRQ_NUM 50 -#define FSPI1_IRQ_NUM 51 - -/* QSPI */ -/* QSPI */ -#if !defined(__ASSEMBLER__) -typedef enum -{ - FQSPI0_ID = 0, - - FQSPI_NUM -} FQspiInstance; - -/* FQSPI cs 0_3, chip number */ -enum -{ - FQSPI_CS_0 = 0, - FQSPI_CS_1 = 1, - FQSPI_CS_2 = 2, - FQSPI_CS_3 = 3, - FQSPI_CS_NUM -}; -#endif - -#define FQSPI_BASE_ADDR 0x28014000 -#define FQSPI_MEM_START_ADDR 0x0 -#define FQSPI_MEM_END_ADDR 0x1FFFFFFF - -/* IOCTRL */ -#define FIOCTRL_REG_BASE_ADDR 0x28180000 - -// Gic -#define ARM_GIC_NR_IRQS 1024 -#define ARM_GIC_IRQ_START 0 -#define FGIC_NUM 1 - -/* can */ -#if !defined(__ASSEMBLER__) -enum -{ - FCAN0_ID = 0, - FCAN1_ID = 1, - FCAN2_ID = 2, - - FCAN_NUM -}; -#endif - -#define FCAN_CLK_FREQ_HZ 600000000 - -#define FCAN0_BASE_ADDR 0x28207000 -#define FCAN1_BASE_ADDR 0x28207400 -#define FCAN2_BASE_ADDR 0x28207800 -#define FCAN0_IRQ_NUM 119 -#define FCAN1_IRQ_NUM 123 -#define FCAN2_IRQNUM 124 - -/* I2C */ -#if !defined(__ASSEMBLER__) -enum -{ - FI2C0_ID = 0, - FI2C1_ID = 1, - FI2C2_ID, - FI2C3_ID, - - FI2C_NUM -}; -#endif - -#define FI2C0_BASE_ADDR 0x28006000 -#define FI2C1_BASE_ADDR 0x28007000 -#define FI2C2_BASE_ADDR 0x28008000 -#define FI2C3_BASE_ADDR 0x28009000 - -#define FI2C0_IRQ_NUM 44 -#define FI2C1_IRQ_NUM 45 -#define FI2C2_IRQ_NUM 46 -#define FI2C3_IRQ_NUM 47 - -#define FI2C_CLK_FREQ_HZ 48000000 /* 48MHz */ - -/* WDT */ -#if !defined(__ASSEMBLER__) -enum -{ - FWDT0_ID = 0, - FWDT1_ID = 1, - - FWDT_NUM -} ; -#endif - -#define FWDT0_REFRESH_BASE_ADDR 0x2800a000 -#define FWDT1_REFRESH_BASE_ADDR 0x28016000 - -#define FWDT_CONTROL_BASE_ADDR(x) ((x)+0x1000) - -#define FWDT0_IRQ_NUM 48 -#define FWDT1_IRQ_NUM 49 - -#define FWDT_CLK_FREQ_HZ 48000000 /* 48MHz */ - -/* SDCI */ -#if !defined(__ASSEMBLER__) -enum -{ - FSDMMC0_ID = 0, - FSDMMC_NUM -}; -#endif - -#define FSDMMC0_BASE_ADDR 0x28207C00 - -#define FSDMMC0_DMA_IRQ_NUM 52 -#define FSDMMC0_CMD_IRQ_NUM 53 -#define FSDMMC0_ERR_IRQ_NUM 54 - -#define FSDMMC_CLK_FREQ_HZ 600000000 /* 600 MHz */ -#define SDCI_SEN_DEBNCE 10000000 /* 10 MHz */ -#define SDCI_CMD_TIMEOUT 10000000 /* 1s */ -#define SDCI_DATA_TIMEOUT 40000000 /* 4S */ - -/* GMAC */ -#if !defined(__ASSEMBLER__) -enum -{ - FGMAC0_ID = 0, - FGMAC1_ID, - - FGMAC_NUM -}; -#endif -#define FGMAC_PUB_REG_BASE_ADDR 0x2820B000 /* 公共寄存器基地址 */ - -#define FGMAC0_BASE_ADDR 0x2820C000 -#define FGMAC1_BASE_ADDR 0x28210000 - -#define FGMAC0_IRQ_NUM 81 -#define FGMAC1_IRQ_NUM 82 - -#define FGMAC_DMA_MIN_ALIGN 128 -#define FGMAC_MAX_PACKET_SIZE 1600 - -/*RTC*/ -#define RTC_CONTROL_BASE 0x2800D000 - -#define FT_CPUS_NR CORE_NUM - -#ifdef __cplusplus -} -#endif - -#endif // ! \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/common/Kconfig b/bsp/phytium/libraries/standalone/common/Kconfig index 221bbbaca2f..50288894b95 100644 --- a/bsp/phytium/libraries/standalone/common/Kconfig +++ b/bsp/phytium/libraries/standalone/common/Kconfig @@ -1,7 +1,6 @@ - - +menu "Sdk common configuration" choice DEBUG_LOG_LEVEL - prompt "Debug Log Level" + prompt "Debug log level" default LOG_ERROR help VERBOS: Print bigger chunks of debugging information @@ -11,20 +10,40 @@ choice DEBUG_LOG_LEVEL ERROR: Print critical errors, software module can not recover on its own config LOG_VERBOS - bool "VERBOS" + bool "Verbos" config LOG_DEBUG - bool "DEBUG" + bool "Debug" config LOG_INFO - bool "INFO" + bool "Info" config LOG_WARN - bool "WARN" + bool "Warn" config LOG_ERROR - bool "ERROR" + bool "Error" config LOG_NONE - bool "NONE" + bool "None" endchoice # DEBUG_LOG_LEVEL +config LOG_EXTRA_INFO + bool "Debug log with extra info" + default n + help + Print debug information with source file name and source code line num. + +config LOG_DISPALY_CORE_NUM + bool "Debug display with core" + default n + help + To display CPU core information during debugging + +config BOOTUP_DEBUG_PRINTS + bool + prompt "Bootup debug" + default n + help + Enable Bootup debug printing + + config USE_DEFAULT_INTERRUPT_CONFIG bool @@ -40,30 +59,12 @@ config USE_DEFAULT_INTERRUPT_CONFIG "Select Interrupt role" config INTERRUPT_ROLE_MASTER - bool "use master role" + bool "Use master role" config INTERRUPT_ROLE_SLAVE - bool "use slave role" + bool "Use slave role" endchoice # INTERRUPT_ROLE_SELECT endif -config LOG_EXTRA_INFO - bool "Debug Log with Extra Info" - default n - help - Print debug information with source file name and source code line num. - -config LOG_DISPALY_CORE_NUM - bool "Debug Display with Core" - default n - help - To display CPU core information during debugging - -config BOOTUP_DEBUG_PRINTS - bool - prompt "Bootup debug" - default n - help - Enable Bootup debug printing - +endmenu diff --git a/bsp/phytium/libraries/standalone/common/fdebug.h b/bsp/phytium/libraries/standalone/common/fdebug.h index 63d8a218fc7..6ac4f83a009 100644 --- a/bsp/phytium/libraries/standalone/common/fdebug.h +++ b/bsp/phytium/libraries/standalone/common/fdebug.h @@ -33,9 +33,7 @@ #include "fsmp.h" #endif -#if defined(CONFIG_USE_AMP) #include "fcpu_info.h" -#endif #ifdef __cplusplus @@ -133,7 +131,7 @@ typedef enum { \ if (LOG_LOCAL_LEVEL < log_level) \ break; \ - DISPALY_CORE_NUM() \ + DISPALY_CORE_NUM(); \ PORT_KPRINTF(LOG_FORMAT(log_tag_letter, format" @%s:%d"), tag, ##__VA_ARGS__, __FILENAME__, __LINE__); \ } while (0) #endif diff --git a/bsp/phytium/libraries/standalone/common/felf.c b/bsp/phytium/libraries/standalone/common/felf.c index 93b423c4258..310166a67e7 100644 --- a/bsp/phytium/libraries/standalone/common/felf.c +++ b/bsp/phytium/libraries/standalone/common/felf.c @@ -1,25 +1,26 @@ /* - * Copyright : (C) 2022 Phytium Information Technology, Inc. + * @Copyright : (C) 2022 Phytium Information Technology, Inc. * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: felf.c - * Date: 2021-08-31 11:16:59 - * LastEditTime: 2022-02-17 18:05:16 + * See the Phytium Public License for more details. + * + * + * @FilePath: felf.c + * @Date: 2023-05-25 19:27:49 + * @LastEditTime: 2023-06-05 14:11:48 * Description:  This file is for providing elf functions. * * Modify History: * Ver   Who        Date         Changes * ----- ------     --------    -------------------------------------- * 1.0 zhugengyu 2022/10/27 rename file name + * 1.1 huanghe 2023/06/05 add get section information */ #include @@ -731,6 +732,7 @@ static unsigned long ElfLoadElf64ImagePhdr(unsigned long addr) { Elf64_Ehdr *ehdr; /* Elf header structure pointer */ Elf64_Phdr *phdr; /* Program header structure pointer */ + int i; ehdr = (Elf64_Ehdr *)addr; @@ -742,7 +744,7 @@ static unsigned long ElfLoadElf64ImagePhdr(unsigned long addr) void *dst = (void *)(unsigned long)phdr->p_paddr; void *src = (void *)addr + phdr->p_offset; - f_printk("Loading phdr %i to 0x%p (%lu bytes)", + f_printk("Loading phdr %i to %p (%lu bytes) \r\n", i, dst, (unsigned long)phdr->p_filesz); if (phdr->p_filesz) { @@ -774,6 +776,8 @@ static unsigned long ElfLoadElf64ImagePhdr(unsigned long addr) return ehdr->e_entry; } + + static unsigned long ElfLoadElf64ImageShdr(unsigned long addr) { Elf64_Ehdr *ehdr; /* Elf header structure pointer */ @@ -807,7 +811,7 @@ static unsigned long ElfLoadElf64ImageShdr(unsigned long addr) if (strtab) { - f_printk("%sing %s @ 0x%08lx (%ld bytes)", + f_printk("%sing %s @ 0x%08lx (%ld bytes) \r\n", (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load", &strtab[shdr->sh_name], (unsigned long)shdr->sh_addr, @@ -864,7 +868,7 @@ unsigned long ElfLoadElfImagePhdr(unsigned long addr) void *dst = (void *)(uintptr)phdr->p_paddr; void *src = (void *)addr + phdr->p_offset; - f_printk("Loading phdr %i to 0x%p (%i bytes)", + f_printk("Loading phdr %i to %p (%i bytes)", i, dst, phdr->p_filesz); if (phdr->p_filesz) { @@ -958,13 +962,11 @@ int ElfIsImageValid(unsigned long addr) if (!IS_ELF(*ehdr)) { - f_printk("## No elf image at address 0x%08lx.", addr); return 0; } if (ehdr->e_type != ET_EXEC) { - f_printk("## Not a 32-bit elf image at address 0x%08lx.", addr); return 0; } @@ -984,4 +986,201 @@ unsigned long ElfExecBootElf(unsigned long (*entry)(int, char *const[]), ret = entry(argc, argv); return ret; -} \ No newline at end of file +} + + + + +/** + * @name: Elf64GetTargetSection + * @msg: 从ELF文件中获取指定名称的section的数据 + * @return: FError，表示函数执行结果的错误码 + * @note: + * @param {Elf64_Ehdr} *ehdr，指向ELF文件头的指针 + * @param {char} *section_name，指定的section名称 + * @param {u8} *data_get，用于存储获取到的section数据的缓冲区指针 + * @param {u32} *length_p，用于存储获取到的section数据长度的指针 + */ +static FError Elf64GetTargetSection(unsigned long addr,char *section_name ,u8 *data_get,u32 *length_p) +{ + Elf64_Ehdr *ehdr; /* Elf header structure pointer */ + Elf64_Shdr *shdr; /* Section header structure pointer */ + unsigned char *strtab = 0; /* String table pointer */ + unsigned char *image; /* Binary image pointer */ + int i; /* Loop counter */ + + ehdr = (Elf64_Ehdr *)addr; + /* Find the section header string table for output info */ + shdr = (Elf64_Shdr *)(addr + (unsigned long)ehdr->e_shoff + + (ehdr->e_shstrndx * sizeof(Elf64_Shdr))); + + if (shdr->sh_type == SHT_STRTAB) + { + strtab = (unsigned char *)(addr + (unsigned long)shdr->sh_offset); + } + else + { + f_printk("There is no string table \r\n"); + return FELF_SECTION_NO_STRTAB; + } + + /* Load each appropriate section */ + for (i = 0; i < ehdr->e_shnum; ++i) + { + shdr = (Elf64_Shdr *)(addr + (unsigned long)ehdr->e_shoff + + (i * sizeof(Elf64_Shdr))); + + if (!(shdr->sh_flags & SHF_ALLOC) || + shdr->sh_addr == 0 || shdr->sh_size == 0) + { + continue; + } + + if(strcmp(section_name, &strtab[shdr->sh_name]) == 0) + { + f_printk("%sing %s @ 0x%08lx (%ld bytes) \r\n", + (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load", + &strtab[shdr->sh_name], + (unsigned long)shdr->sh_addr, + (long)shdr->sh_size); + + if(shdr->sh_type == SHT_NOBITS) + { + f_printk("There is no space section \r\n"); + return FELF_SECTION_NO_SPACE; + } + printf("*length_p is %d \r\n",*length_p); + if (shdr->sh_size < *length_p) + { + *length_p = shdr->sh_size; + } + + image = (unsigned char *)addr + (unsigned long)shdr->sh_offset; + memcpy((void *)(uintptr)data_get, + (const void *)image, *length_p); + + return FELF_SUCCESS; + } + + } + + f_printk("%s: No %s section exists in this elf file \r\n",__func__,section_name); + return FELF_SECTION_NOT_FIT; +} + + + +/** + * @name: + * @msg: + * @return {*} + * @note: + * @param {Elf32_Shdr} *ehdr + * @param {char} *section_name + * @param {u8} *data_get + * @param {u32} *length_p + */ +static FError Elf32GetTargetSection(unsigned long addr,char *section_name ,u8 *data_get,u32 *length_p) +{ + + Elf32_Ehdr *ehdr; /* Elf header structure pointer */ + Elf32_Shdr *shdr; /* Section header structure pointer */ + unsigned char *strtab = 0; /* String table pointer */ + unsigned char *image; /* Binary image pointer */ + int i; /* Loop counter */ + + ehdr = (Elf32_Ehdr *)addr; + /* Find the section header string table for output info */ + shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + + (ehdr->e_shstrndx * sizeof(Elf32_Shdr))); + + if (shdr->sh_type == SHT_STRTAB) + { + strtab = (unsigned char *)(addr + shdr->sh_offset); + } + else + { + f_printk("There is no string table \r\n"); + return FELF_SECTION_NO_STRTAB; + } + + /* Load each appropriate section */ + for (i = 0; i < ehdr->e_shnum; ++i) + { + shdr = (Elf32_Shdr *)(addr + ehdr->e_shoff + + (i * sizeof(Elf32_Shdr))); + + if (!(shdr->sh_flags & SHF_ALLOC) || + shdr->sh_addr == 0 || shdr->sh_size == 0) + { + continue; + } + + if (strcmp(section_name, &strtab[shdr->sh_name]) == 0) + { + printf("%sing %s @ 0x%08lx (%ld bytes)", + (shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load", + &strtab[shdr->sh_name], + (unsigned long)shdr->sh_addr, + (long)shdr->sh_size); + + printf("copy num is \r\n"); + printf("*length_p is %d \r\n",*length_p); + if(shdr->sh_size < *length_p) + { + *length_p = shdr->sh_size; + } + + + image = (unsigned char *)addr + (unsigned long)shdr->sh_offset; + memcpy((void *)(uintptr)data_get, + (const void *)image, *length_p); + + return FELF_SUCCESS; + + } + } + + f_printk("%s: No %s section exists in this elf file \r\n",__func__,section_name); + return FELF_SECTION_NOT_FIT; +} + + + + +/** + * @name: ElfGetSection + * @msg: 获取 ELF 文件中指定节的内容 + * @return {FError} 返回错误码，表示获取节内容的结果 + * @note: 函数将根据 ELF 文件的类型（32位或64位）调用相应的函数来获取指定节的内容。 + * @param {unsigned long} addr ELF 文件的基地址 + * @param {char*} section_name 节的名称 + * @param {u8*} data_get 用于存储节内容的缓冲区 + * @param {u32*} length_p 存储获取到的节内容的长度 + */ +FError ElfGetSection(unsigned long addr, char *section_name, u8 *data_get, u32 *length_p) +{ + Elf32_Ehdr *ehdr; /* ELF 文件头指针 */ + Elf32_Shdr *shdr; /* 节头指针 */ + unsigned char *strtab = 0; /* 字符串表指针 */ + unsigned char *image; /* 二进制映像指针 */ + int i; /* 循环计数器 */ + + /* 检查 ELF 文件的类型 */ + ehdr = (Elf32_Ehdr *)addr; + if (ehdr->e_ident[EI_CLASS] == ELFCLASS64) + { + /* 如果是64位 ELF，则调用 Elf64GetTargetSection 函数获取指定节的内容 */ + return Elf64GetTargetSection(addr, section_name, data_get, length_p); + } + + /* 如果是32位 ELF，则调用 Elf32GetTargetSection 函数获取指定节的内容 */ + if (ehdr->e_ident[EI_CLASS] == ELFCLASS32) + { + return Elf32GetTargetSection(addr, section_name, data_get, length_p); + } + + /* 若未匹配到有效的 ELF 类型，则返回 FELF_SECTION_GET_ERROR 错误码 */ + return FELF_SECTION_GET_ERROR; +} + diff --git a/bsp/phytium/libraries/standalone/common/felf.h b/bsp/phytium/libraries/standalone/common/felf.h index bc485787430..9fd51befeb9 100644 --- a/bsp/phytium/libraries/standalone/common/felf.h +++ b/bsp/phytium/libraries/standalone/common/felf.h @@ -26,18 +26,27 @@ #define FELF_H #include "ftypes.h" +#include "ferror_code.h" #ifdef __cplusplus extern "C" { #endif +#define FELF_SUCCESS FT_SUCCESS /* SUCCESS */ +#define FELF_SECTION_NO_STRTAB FT_MAKE_ERRCODE(ErrorModGeneral, ErrElf, 1) /* There is no string table */ +#define FELF_SECTION_NO_SPACE FT_MAKE_ERRCODE(ErrorModGeneral, ErrElf, 2) /* There is no space section */ +#define FELF_SECTION_NOT_FIT FT_MAKE_ERRCODE(ErrorModGeneral, ErrElf, 3) /* No corresponding section was matched */ +#define FELF_SECTION_GET_ERROR FT_MAKE_ERRCODE(ErrorModGeneral, ErrElf, 3) + unsigned long ElfLoadElfImagePhdr(unsigned long addr); unsigned long ElfLoadElfImageShdr(unsigned long addr); int ElfIsImageValid(unsigned long addr); unsigned long ElfExecBootElf(unsigned long (*entry)(int, char *const[]), int argc, char *const argv[]); +FError ElfGetSection(unsigned long addr, char *section_name, u8 *data_get, u32 *length_p); + #ifdef __cplusplus } #endif diff --git a/bsp/phytium/libraries/standalone/common/ferror_code.h b/bsp/phytium/libraries/standalone/common/ferror_code.h index 98ca6ea870c..be2012fc03e 100644 --- a/bsp/phytium/libraries/standalone/common/ferror_code.h +++ b/bsp/phytium/libraries/standalone/common/ferror_code.h @@ -52,6 +52,7 @@ typedef enum ErrCommGeneral = 0, ErrCommMemp, ErrInterrupt, + ErrElf, } FtErrCodeCommMask; /* BSP模块的错误子模块定义 */ @@ -86,6 +87,7 @@ typedef enum ErrSema, ErrBspMEDIA, ErrBspMhu, + ErrBspIOPad, ErrBspModMaxMask = 255 } FtErrCodeBspMask; diff --git a/bsp/phytium/libraries/standalone/common/fpinctrl.h b/bsp/phytium/libraries/standalone/common/fpinctrl.h index 113a4db7231..be817061a5c 100644 --- a/bsp/phytium/libraries/standalone/common/fpinctrl.h +++ b/bsp/phytium/libraries/standalone/common/fpinctrl.h @@ -34,24 +34,7 @@ extern "C" #include "sdkconfig.h" #if defined(CONFIG_TARGET_F2000_4) || defined(CONFIG_TARGET_D2000) -#ifndef FPIN_IO_CTRL -#define FPIN_IO_CTRL -#endif -#endif - -#if defined(CONFIG_TARGET_E2000) || defined(CONFIG_TARGET_TARDIGRADE) -#ifndef FPIN_IO_PAD -#define FPIN_IO_PAD -#endif -#endif - -#if defined(FPIN_IO_CTRL) #include "fioctrl.h" -#endif - -#if defined(FPIN_IO_PAD) -#include "fiopad.h" -#endif /**************************** Type Definitions *******************************/ @@ -61,39 +44,10 @@ typedef enum FPIN_FUNC1, FPIN_FUNC2, FPIN_FUNC3 = 0b011, -#if defined(FPIN_IO_PAD) /* E2000 support more pin func */ - FPIN_FUNC4, - FPIN_FUNC5, - FPIN_FUNC6, - FPIN_FUNC7 = 0b111, -#endif + FPIN_NUM_OF_FUNC } FPinFunc; /* 引脚复用功能配置, func0为默认功能 */ -#if defined(FPIN_IO_PAD) /* Only support driver strength config in E2000 */ -typedef enum -{ - FPIN_DRV0 = 0b0000, - FPIN_DRV1, - FPIN_DRV2, - FPIN_DRV3, - FPIN_DRV4, - FPIN_DRV5, - FPIN_DRV6, - FPIN_DRV7, - FPIN_DRV8, - FPIN_DRV9, - FPIN_DRV10, - FPIN_DRV11, - FPIN_DRV12, - FPIN_DRV13, - FPIN_DRV14, - FPIN_DRV15 = 0b1111, - - FPIN_NUM_OF_DRIVE -} FPinDrive; /* 引脚驱动能力配置 */ -#endif - typedef enum { FPIN_PULL_NONE = 0b00, @@ -162,29 +116,12 @@ FPinPull FPinGetPull(const FPinIndex pin); /* 设置IO引脚的上下拉 */ void FPinSetPull(const FPinIndex pin, FPinPull pull); -#if defined(FPIN_IO_PAD) -/* 获取IO引脚的驱动能力 */ -FPinDrive FPinGetDrive(const FPinIndex pin); - -/* 设置IO引脚的驱动能力 */ -void FPinSetDrive(const FPinIndex pin, FPinDrive drive); - -/* 获取IO引脚的复用、上下拉和驱动能力设置 */ -void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull, FPinDrive *drive); - -/* 设置IO引脚的复用、上下拉和驱动能力 */ -void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull, FPinDrive drive); - -#else - /* 获取IO引脚的复用、上下拉和驱动能力设置 */ void FPinGetConfig(const FPinIndex pin, FPinFunc *func, FPinPull *pull); /* 设置IO引脚的复用、上下拉和驱动能力 */ void FPinSetConfig(const FPinIndex pin, FPinFunc func, FPinPull pull); -#endif - /* 获取IO引脚当前的单项延时设置 */ FPinDelay FPinGetDelay(const FPinIndex pin, FPinDelayDir dir, FPinDelayType type); @@ -208,4 +145,5 @@ void FPinGetDelayConfig(const FPinIndex pin, FPinDelay *in_roungh_delay, FPinDel } #endif +#endif #endif \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/common/fprintk.c b/bsp/phytium/libraries/standalone/common/fprintk.c index eb83ae74e8c..0852d52a72e 100644 --- a/bsp/phytium/libraries/standalone/common/fprintk.c +++ b/bsp/phytium/libraries/standalone/common/fprintk.c @@ -404,7 +404,7 @@ int cbvprintf(cbprintf_cb out, void *ctx, const char *fmt, va_list ap) } } -static void f_vprintf(const char *restrict format, va_list vargs) +static int f_vprintf(const char *restrict format, va_list vargs) { struct str_context ctx = {0}; cbvprintf(char_out, &ctx, format, vargs); diff --git a/bsp/phytium/libraries/standalone/common/fpsci.c b/bsp/phytium/libraries/standalone/common/fpsci.c new file mode 100644 index 00000000000..2842a929db2 --- /dev/null +++ b/bsp/phytium/libraries/standalone/common/fpsci.c @@ -0,0 +1,344 @@ +/* + * Copyright : (C) 2023 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fpsci.c + * Created Date: 2023-06-21 10:36:53 + * Last Modified: 2023-06-30 13:32:06 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + * 1.0 huanghe 2023-06-21 first release + */ + + +#include +#include "fsmcc.h" /* 根据你的平台和编译环境来确定这个路径 */ +#include "fpsci.h" +#include "fassert.h" +#include "fcompiler.h" +#include "fdebug.h" +#include "fcpu_info.h" + +#define FPSCI_DEBUG_TAG "FPSCI" +#define FPSCI_DEBUG(format, ...) FT_DEBUG_PRINT_D(FPSCI_DEBUG_TAG, format, ##__VA_ARGS__) +#define FPSCI_INFO(format, ...) FT_DEBUG_PRINT_I(FPSCI_DEBUG_TAG, format, ##__VA_ARGS__) +#define FPSCI_WARN(format, ...) FT_DEBUG_PRINT_W(FPSCI_DEBUG_TAG, format, ##__VA_ARGS__) +#define FPSCI_ERROR(format, ...) FT_DEBUG_PRINT_E(FPSCI_DEBUG_TAG, format, ##__VA_ARGS__) + +/* 定义PSCI 函数值 */ +#define FPSCI_0_2_FN32_BASE 0x84000000 +#define FPSCI_0_2_FN64_BASE 0xC4000000 +#define FPSCI_VERSION (FPSCI_0_2_FN32_BASE + 0x000) +#define FPSCI_FEATURES (FPSCI_0_2_FN32_BASE + 0x00a) +#define FPSCI_CPU_SUSPEND_AARCH32 (FPSCI_0_2_FN32_BASE + 0x001) +#define FPSCI_CPU_SUSPEND_AARCH64 (FPSCI_0_2_FN64_BASE + 0x001) +#define FPSCI_CPU_OFF (FPSCI_0_2_FN32_BASE + 0x002) +#define FPSCI_CPU_ON_AARCH32 (FPSCI_0_2_FN32_BASE + 0x003) +#define FPSCI_CPU_ON_AARCH64 (FPSCI_0_2_FN64_BASE + 0x003) +#define FPSCI_FAFFINITY_INFO_AARCH32 (FPSCI_0_2_FN32_BASE + 0x004) +#define FPSCI_FAFFINITY_INFO_AARCH64 (FPSCI_0_2_FN64_BASE + 0x004) +#define FPSCI_SYSTEM_OFF (FPSCI_0_2_FN32_BASE + 0x008) +#define FPSCI_SYSTEM_RESET (FPSCI_0_2_FN32_BASE + 0x009) +#define FPSCI_SYSTEM_SUSPEND (FPSCI_0_2_FN32_BASE + 0x00E) + +/* 定义每个PSCI函数ID的位标记 */ +#define FPSCI_PSCI_VERSION_BIT (1 << 0) +#define FPSCI_PSCI_FEATURES_BIT (1 << 1) +#define FPSCI_CPU_SUSPEND_AARCH32_BIT (1 << 2) +#define FPSCI_CPU_SUSPEND_AARCH64_BIT (1 << 3) +#define FPSCI_CPU_OFF_BIT (1 << 4) +#define FPSCI_CPU_ON_AARCH32_BIT (1 << 5) +#define FPSCI_CPU_ON_AARCH64_BIT (1 << 6) +#define FPSCI_AFFINITY_INFO_AARCH32_BIT (1 << 7) +#define FPSCI_AFFINITY_INFO_AARCH64_BIT (1 << 8) +#define FPSCI_SYSTEM_OFF_BIT (1 << 9) +#define FPSCI_SYSTEM_RESET_BIT (1 << 10) + + +static int fpsci_ringt_bit_flg = 0; + +/* 定义函数指针 */ +typedef void (*FPsciInvokeFun)(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct FSmcccRes *res); + +/* 为函数指针初始化为默认的函数 */ +FPsciInvokeFun f_psci_invoke = FSmcccSmcCall; + + +/** + * @name: FPsciVersion + * @msg: Get the version of the PSCI implementation. + * @return {int}: The version information of the PSCI implementation. + * @note: This function returns the version information obtained from the PSCI VERSION function. + */ +int FPsciVersion(void) { + struct FSmcccRes res; + FASSERT((*f_psci_invoke)); + (*f_psci_invoke)(FPSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +/** + * @name: FPsciFeatures + * @msg: Check whether a PSCI function is supported. + * @param {u32} psci_fid: The function ID of the PSCI function to be checked. + * @return {int}: 1 if the function is supported; 0 otherwise. + * @note: This function returns whether the PSCI function represented by psci_fid is supported or not. + */ +int FPsciFeatures(u32 psci_fid) { + struct FSmcccRes res; + FASSERT((*f_psci_invoke)); + (*f_psci_invoke)(FPSCI_FEATURES, psci_fid, 0, 0, 0, 0, 0, 0, &res); + return res.a0 == FPSCI_SUCCESS ? 1 : 0; +} + +/** + * @name: FPsciCpuSuspend + * @msg: Suspend execution on a particular CPU. + * @param {u32} power_state: The power state to be entered. + * @param {unsigned long} entry_point_address: The address to be executed upon waking up. + * @param {unsigned long} context_id: The context-specific identifier. + * @return {int}: The status code of the operation, as defined by the PSCI specification. + * @note: This function suspends the execution on a particular CPU and returns a status code indicating whether the operation was successful or not. + */ +int FPsciCpuSuspend(u32 power_state, unsigned long entry_point_address, unsigned long context_id) { + struct FSmcccRes res; + FASSERT((fpsci_ringt_bit_flg & FPSCI_CPU_SUSPEND_AARCH32_BIT) != 0); + FASSERT((*f_psci_invoke)); + (*f_psci_invoke)(FPSCI_CPU_SUSPEND_AARCH32, power_state, entry_point_address, context_id, 0, 0, 0, 0, &res); + return res.a0; +} + + +/** + * @name: FPsciCpuOn + * @msg: Power on a particular CPU. + * @param {unsigned long} target_cpu: The target CPU to be powered on. + * @param {unsigned long} entry_point_address: The address to be executed upon waking up. + * @param {unsigned long} context_id: The context-specific identifier. + * @return {int}: The status code of the operation, as defined by the PSCI specification. + * @note: This function powers on a particular CPU and returns a status code indicating whether the operation was successful or not. + */ +int FPsciCpuOn(unsigned long target_cpu, unsigned long entry_point_address, unsigned long context_id) { + struct FSmcccRes res; + unsigned long cpu_on_id ; + + #if defined(FAARCH64_USE) + cpu_on_id = FPSCI_CPU_ON_AARCH64 ; + #else + cpu_on_id = FPSCI_CPU_ON_AARCH32; + #endif + + FASSERT((fpsci_ringt_bit_flg & (FPSCI_CPU_ON_AARCH32_BIT|FPSCI_CPU_ON_AARCH64_BIT)) != 0); + FASSERT((*f_psci_invoke)); + (*f_psci_invoke)(cpu_on_id, target_cpu, entry_point_address, context_id, 0, 0, 0, 0, &res); + return res.a0; +} + +/** + * @name: FPsciCpuOff + * @msg: This is a wrapper for the PSCI CPU Off interface, intended to turn off the current CPU. + * @return: Returns the 'a0' field of the 'FSmcccRes' structure, indicating the result of the call. A return value of 0 (PSCI_SUCCESS) indicates success, any other value indicates an error occurred. + * @note: A core that is powered down by CPU_OFF can only be powered up again in response to a CPU_ON. + */ +int FPsciCpuOff(void) { + struct FSmcccRes res; + FASSERT((fpsci_ringt_bit_flg & FPSCI_CPU_OFF_BIT) != 0); + FASSERT((*f_psci_invoke)); + (*f_psci_invoke)(FPSCI_CPU_OFF, 0, 0, 0, 0, 0, 0, 0, &res); + return res.a0; +} + + + +/** + * @name: FPsciAffinityInfo + * @msg: Get the power state of a particular affinity level. + * @param {unsigned long} target_affinity: The target affinity level. + * @param {u32} lowest_affinity_level: The lowest affinity level. + * @return {int}: The power state of the specified affinity level, as defined by the PSCI specification. + * @note: This function returns the power state of a particular affinity level. + */ +int FPsciAffinityInfo(unsigned long target_affinity, u32 lowest_affinity_level) { + struct FSmcccRes res; + FASSERT((fpsci_ringt_bit_flg & (FPSCI_AFFINITY_INFO_AARCH32_BIT|FPSCI_AFFINITY_INFO_AARCH64_BIT)) != 0); + FASSERT((*f_psci_invoke)); + unsigned long cpu_on_id ; + + #if defined(FAARCH64_USE) + cpu_on_id = FPSCI_CPU_ON_AARCH64 ; + #else + cpu_on_id = FPSCI_CPU_ON_AARCH32; + #endif + + (*f_psci_invoke)(FPSCI_FAFFINITY_INFO_AARCH32, target_affinity, lowest_affinity_level, 0, 0, 0, 0, 0, &res); + return res.a0; +} + +/** + * @name: FPsciSystemReset + * @msg: Reset the system. + * @param {u32} reset_type: The type of the system reset (cold/warm). + * @note: This function resets the system. The reset type is specified by the parameter reset_type. + */ +void FPsciSystemReset(u32 reset_type) { + struct FSmcccRes res; + FASSERT((fpsci_ringt_bit_flg & FPSCI_SYSTEM_RESET_BIT) != 0); + FASSERT((*f_psci_invoke)); + (*f_psci_invoke)(FPSCI_SYSTEM_RESET, reset_type, 0, 0, 0, 0, 0, 0, &res); +} + + +/** + * @name: FPsciCheckFeatures + * @msg: This function checks for the availability of various PSCI features and sets the corresponding bits in the 'fpsci_ringt_bit_flg' global flag accordingly. + * @return: This function does not return a value. + */ +static void FPsciCheckFeatures(void) +{ + FPSCI_INFO("Checking PSCI features...\r\n"); + fpsci_ringt_bit_flg = 0 ; + if (FPsciFeatures(FPSCI_CPU_SUSPEND_AARCH32)) + { + fpsci_ringt_bit_flg |= FPSCI_CPU_SUSPEND_AARCH32_BIT; + FPSCI_INFO("CPU_SUSPEND_AARCH32 supported.\r\n"); + } + else + { + FPSCI_ERROR("CPU_SUSPEND_AARCH32 not supported.\r\n"); + } + + if (FPsciFeatures(FPSCI_CPU_OFF)) + { + fpsci_ringt_bit_flg |= FPSCI_CPU_OFF_BIT; + FPSCI_INFO("CPU_OFF supported.\r\n"); + } + else + { + FPSCI_ERROR("CPU_OFF not supported.\r\n"); + } + +#if defined(FAARCH64_USE) + if (FPsciFeatures(FPSCI_CPU_ON_AARCH64)) + { + fpsci_ringt_bit_flg |= FPSCI_CPU_ON_AARCH64_BIT; + FPSCI_INFO("CPU_ON_AARCH64 supported.\r\n"); + } + else + { + FPSCI_ERROR("CPU_ON_AARCH64 not supported.\r\n"); + } +#else + if (FPsciFeatures(FPSCI_CPU_ON_AARCH32)) + { + fpsci_ringt_bit_flg |= FPSCI_CPU_ON_AARCH32_BIT; + FPSCI_INFO("CPU_ON_AARCH32 supported.\r\n"); + } + else + { + FPSCI_ERROR("CPU_ON_AARCH32 not supported.\r\n"); + } +#endif + + +#if defined(FAARCH64_USE) + if (FPsciFeatures(FPSCI_FAFFINITY_INFO_AARCH64)) + { + fpsci_ringt_bit_flg |= FPSCI_AFFINITY_INFO_AARCH64_BIT; + FPSCI_INFO("AFFINITY_INFO_AARCH64 supported.\r\n"); + } + else + { + FPSCI_ERROR("AFFINITY_INFO_AARCH64 not supported.\r\n"); + } + +#else + if (FPsciFeatures(FPSCI_FAFFINITY_INFO_AARCH32)) + { + fpsci_ringt_bit_flg |= FPSCI_AFFINITY_INFO_AARCH32_BIT; + FPSCI_INFO("FPSCI_AFFINITY_INFO_AARCH32 supported.\r\n"); + } + else + { + FPSCI_ERROR("AFFINITY_INFO_AARCH32 not supported.\r\n"); + } +#endif + + if (FPsciFeatures(FPSCI_SYSTEM_OFF)) + { + fpsci_ringt_bit_flg |= FPSCI_SYSTEM_OFF_BIT; + FPSCI_INFO("SYSTEM_OFF supported.\r\n"); + } + else + { + FPSCI_ERROR("SYSTEM_OFF not supported.\r\n"); + } + + if (FPsciFeatures(FPSCI_SYSTEM_RESET)) + { + fpsci_ringt_bit_flg |= FPSCI_SYSTEM_RESET_BIT; + FPSCI_INFO("SYSTEM_RESET supported.\r\n"); + } + else + { + FPSCI_ERROR("SYSTEM_RESET not supported.\r\n"); + } +} + + +/** + * @name: FPsci_CpuOn + * @msg: Power up a core + * @in param cpu_id_mask: cpu id mask + * @in param bootaddr: a 32-bit entry point physical address (or IPA). + * @return int + */ +int FPsciCpuMaskOn(s32 cpu_id_mask, uintptr bootaddr) +{ + FError ret ; + u64 cluster = 0; + ret = GetCpuAffinityByMask(cpu_id_mask, &cluster); + if (ret != ERR_SUCCESS) + { + return FPSCI_INVALID_PARAMS; + } + return FPsciCpuOn(cluster,(unsigned long)bootaddr,0) ; +} + + +static void FSmccInit(int method) { + if (method == 1) { + f_psci_invoke = FSmcccHvcCall; + } + else + { + f_psci_invoke = FSmcccSmcCall; + } +} + +int FPsciInit(void) { + int psci_version = 0; + FSmccInit(0); + psci_version = FPsciVersion() ; + FPSCI_INFO("major is 0x%x,minor is 0x%x \r\n", FPSCI_MAJOR_VERSION(psci_version),FPSCI_MINOR_VERSION(psci_version)) ; + FPsciCheckFeatures(); + return 0; +} + + + diff --git a/bsp/phytium/libraries/standalone/common/fpsci.h b/bsp/phytium/libraries/standalone/common/fpsci.h new file mode 100644 index 00000000000..9261eff4ae3 --- /dev/null +++ b/bsp/phytium/libraries/standalone/common/fpsci.h @@ -0,0 +1,89 @@ +/* + * Copyright : (C) 2023 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fpsci.h + * Created Date: 2023-06-21 16:13:14 + * Last Modified: 2023-06-27 15:33:23 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + * 1.0 huanghe 2023-06-21 first release + */ + +#ifndef FPSCI_H +#define FPSCI_H + +#ifdef __cplusplus +extern "C" +{ +#endif +#include "ftypes.h" + +/* 版本掩码 */ + +#define FPSCI_VERSION_MASK 0x0000FFFF +#define FPSCI_MAJOR_VERSION(x) ((x) >> 16) +#define FPSCI_MINOR_VERSION(x) ((x) & 0xFFFF) + +/* Power State 参数 */ + +#define FPSCI_POWER_STATE_ID_MASK 0xFFFF +#define FPSCI_POWER_STATE_ID_SHIFT 0 +#define FPSCI_POWER_STATE_TYPE_SHIFT 16 +#define FPSCI_POWER_STATE_AFFL_SHIFT 24 + +/* stateid encoding */ +#define FPSCI_STATEID_CORE_RETENTION 0x2 +#define FPSCI_STATEID_CORE_POWERDOWN 0x8 + + +/* 版本掩码 */ + +#define FPSCI_VERSION_MASK 0x0000FFFF + + +/* 定义复位模式 */ + +#define FPSCI_SYSTEM_RESET_TYPE_COLD 0 +#define FPSCI_SYSTEM_RESET_TYPE_WARM 1 + +/* 定义PSCI 错误码 */ + +#define FPSCI_SUCCESS 0 +#define FPSCI_NOT_SUPPORTED -1 +#define FPSCI_INVALID_PARAMS -2 +#define FPSCI_DENIED -3 +#define FPSCI_ALREADY_ON -4 +#define FPSCI_ON_PENDING -5 +#define FPSCI_INTERNAL_FAILURE -6 +#define FPSCI_NOT_PRESENT -7 +#define FPSCI_DISABLED -8 +#define FPSCI_INVALID_ADDRESS -9 + +int FPsciInit(void) ; +int FPsciVersion(void) ; +int FPsciCpuSuspend(u32 power_state, unsigned long entry_point_address, unsigned long context_id) ; +int FPsciCpuOn(unsigned long target_cpu, unsigned long entry_point_address, unsigned long context_id) ; +int FPsciAffinityInfo(unsigned long target_affinity, u32 lowest_affinity_level) ; +void FPsciSystemReset(u32 reset_type) ; +int FPsciFeatures(u32 psci_fid) ; +int FPsciCpuOff(void) ; +int FPsciCpuMaskOn(s32 cpu_id_mask, uintptr bootaddr) ; +#ifdef __cplusplus +} +#endif + +#endif /* __ASM_ARM_MACRO_H__ */ + diff --git a/bsp/phytium/libraries/standalone/common/ftypes.h b/bsp/phytium/libraries/standalone/common/ftypes.h index 1ec12c05a3d..dd27b1936d4 100644 --- a/bsp/phytium/libraries/standalone/common/ftypes.h +++ b/bsp/phytium/libraries/standalone/common/ftypes.h @@ -84,6 +84,7 @@ typedef unsigned long ULONG; #endif #define _INLINE inline +#define _ALWAYS_INLINE inline __attribute__((always_inline)) #define _WEAK __attribute__((weak)) typedef void (*FIrqHandler)(void *InstancePtr); diff --git a/bsp/phytium/libraries/standalone/doc/ChangeLog.md b/bsp/phytium/libraries/standalone/doc/ChangeLog.md index 4e4f95863fc..c488fd977bb 100644 --- a/bsp/phytium/libraries/standalone/doc/ChangeLog.md +++ b/bsp/phytium/libraries/standalone/doc/ChangeLog.md @@ -1,3 +1,586 @@ +# Phytium Standalone SDK 2023-7-18 ChangeLog + +Change Log since 2023-07-11 + +## drivers + +- add iopad driver +# Phytium Standalone SDK 2023-7-14 ChangeLog + +Change Log since 2023-07-11 + +## tools + +- modify scripts to adapt freertos + +# Phytium Standalone SDK 2023-7-11 ChangeLog + +Change Log since 2023-07-11 + +## board + +- modify fearly uart + +# Phytium Standalone SDK 2023-7-06 ChangeLog + +Change Log since 2023-07-03 + +## tools + +- Resolved an issue where the header file could not be recognized after modification + +* Fixed a bug where C++ logic could not generate binary + +# Phytium Standalone SDK 2023-7-03 ChangeLog + +Change Log since 2023-06-30 + +## arch + +- added new features such as smcc and psci +- Remove the old smcc and psci methods + +## exampe + +- add psci example + +# Phytium Standalone SDK 2023-6-30 ChangeLog + +Change Log since 2023-06-28 + +## driver + +- change the struct of FDcDisplayTimmingConfig + +# Phytium Standalone SDK 2023-6-28 ChangeLog + +Change Log since 2023-06-26 + +## example + +- Add serial new examples + +## driver + +- Add new state clear function in fpl011_intr.c + +# Phytium Standalone SDK 2023-6-26 ChangeLog + +Change Log since 2023-06-21 + +## arch + +- Add fpen choice in fboot.S to compatible with rtos startup + +## driver + +- Modify the method of reading and writing gic 64-bit registers in aarch32 mode + +# Phytium Standalone SDK 2023-6-20 ChangeLog + +Change Log since 2023-06-12 + +## board + +- Added mio slave id + +## example + +- Added mio ddma example + +# Phytium Standalone SDK 2023-06-19 ChangeLog + +Change Log since 2023-06-19 + +## third-party + +- add callback function eth_poll in LwipPortInputThread: to enable the NIC to send and receive packets steadily in FreeRTOS. + +# Phytium Standalone SDK 2023-06-19 ChangeLog + +Change Log since 2023-06-08 + +## arch + +- restruct aarch32 system register access interface +- delete fcp15 file + +## driver + +- add windbond qspi flash support + +# Phytium Standalone SDK 2023-6-16 ChangeLog + +Change Log since 2023-06-15 + +## tools + +Added some memory check tools + +## doc + +Added user document + +## example + +Added libmetal example + +# Phytium Standalone SDK 2023-6-15 ChangeLog + +Change Log since 2023-6-12 + +## driver + +- Modify the framebuffer generate method and the driver lib + +## driver + +- adjust the lvgl and the driver relation + +## example + +- adapt the driver change + +# Phytium Standalone SDK 2023-6-15 ChangeLog + +Change Log since 2023-6-12 + +## sdmmc + +- Modify the variable name in sdmmc.mk to resolve the issue of variable name overloading. + +# Phytium Standalone SDK 2023-6-12 ChangeLog + +Change Log since 2023-6-12 + +## example + +- modify uart ddma example +- remove FDDMA_MAX_TRANSFER_LEN + +## drivers + +- remove FDDMA_MAX_TRANSFER_LEN + +# Phytium Standalone SDK 2023-6-12 ChangeLog + +Change Log since 2023-6-8 + +## drivers + +- modify annotation and variable name in gdma driver. +- solve customer issue in gdma. + +## example + +- modify gdma example. + +# Phytium Standalone SDK 2023-6-8 ChangeLog + +Change Log since 2023-6-8 + +## example + +- modify gic example Kconfig. +- gic example debug. + +# Phytium Standalone SDK 2023-6-8 ChangeLog + +Change Log since 2023-6-6 + +## arch + +- add gcc atomic api + +## example + +- add atomic test example. + +# Phytium Standalone SDK 2023-6-8 ChangeLog + +Change Log since 2023-06-7 + +## example + +- add cxx example +- add crypto++ example + +## arch + +- support c++ + +## lib + +- add some stub functions for std c++ library + +## third-party + +- add crypto++ + +# Phytium Standalone SDK 2023-6-7 ChangeLog + +Change Log since 2023-6-6 + +## example + +- network/raw_api/tcp_client example debug: Memory double free problem solved. +- network/raw_api/tcp_client example modified: The new code is more robust and secure. + +# Phytium Standalone SDK 2023-6-7 ChangeLog + +Change Log since 2023-6-2 + +## example + +- add wdt example. + +# Phytium Standalone SDK 2023-6-6 ChangeLog + +Change Log since 2023-6-6 + +## arch + +- modify generic timer api + +# Phytium Standalone SDK 2023-6-05 ChangeLog + +Change Log since 2023-05-31 + +## example + +- add timer example. + +# Phytium Standalone SDK 2023-6-05 ChangeLog + +Change Log since 2023-05-31 + +## baremetal + +- modified license of libmetal demo +- add loadelf function for openamp example + +## third-party + +- add image store file +- complete remote processor operation ports + +# Phytium Standalone SDK 2023-6-2 ChangeLog + +Change Log since 2023-6-1 + +## scrips + +- update settings.json (fileheader extentions update) + +# Phytium Standalone SDK 2023-5-31 ChangeLog + +Change Log since 2023-05-29 + +## tools + +Added a new compilation framework + +## baremetal + +Added a new test code + +## SDK + +Add a series of makefile scripts + +# Phytium Standalone SDK 2023-5-29 ChangeLog + +Change Log since 2023-05-25 + +## example + +- add ipc semaphore refactoring example. + +# Phytium Standalone SDK 2023-5-29 ChangeLog + +Change Log since 2023-05-23 + +## arch + +- modify generic timer api, add virtual timer's use +- delete USE_SYS_TICK kconfig + +## example + +- add generic_timer example to test physical and virtual timers + +# Phytium Standalone SDK 2023-05-24 v1.1.1 ChangeLog + +Change Log since 2023-05-23 + +## README + +- add developer infomation. +- install.py update including version infomation modified. + +## common + +- according to user issue, add a ; in fdebug.h + +# Phytium Standalone SDK 2023-5-23 ChangeLog + +Change Log since 2023-05-16 + +## example + +- add LwipEthProcessLoop call in LwipTestLoop. +- add new macro definition: CONFIG_LWIP_RX_POLL to control LwipEthProcessLoop calls. + +## drivers + +- add new member variable: mask in struct Fxmac,which can be used to manage TX and RX interrupts. +- add new macro definition: FXMAC_INTR_MASK,which can be used to enable TX and RX interrupts. + +## third-party + +- delete LWIP_DEBUG_ESP_LOG in /lwip-2.1.2/Kconfig +- add new function LwipEthProcessLoop. +- add new callback function ethernetif_poll,which can poll network packets. +- add new macro definitions: FXMAC_LWIP_PORT_CONFIG_RX_POLL_RECV,which controls whether Frame received interrupts are enabled or not. + +# Phytium Standalone SDK 2023-5-16 ChangeLog + +Change Log since 2023-05-12 + +## example + +- add new openamp demo,support manager core and remote core communicate always. +- Change openamp for linux demo folder name “openamp old”. + +## third-party + +- modified some const variable +- add some defines of service + +# Phytium Standalone SDK 2023-5-12 ChangeLog + +Change Log since 2023-05-10 + +## example + +- add pcie refactoring example. + +## driver + +-little change to pcie driver + +# Phytium Standalone SDK 2023-5-10 ChangeLog + +Change Log since 2023-05-09 + +## board + +- Modify the description in the MMUs table in the aarch64. + +## aarch64 + +* Modify the execution mode in fmmu.c + +# Phytium Standalone SDK 2023-5-09 ChangeLog + +Change Log since 2023-04-28 + +## board + +- Change the suffix of CACHE_LINE_ADDR_MASK, resolve the problem that cache flush addresses are truncated . + +# Phytium Standalone SDK 2023-4-28 ChangeLog + +Change Log since 2023-04-24 + +## example + +- add gic refactoring example. + +# Phytium Standalone SDK 2023-04-24 v1.1.0 ChangeLog + +Change Log since 2023-04-20 + +## README + +- add developer infomation. +- install.py update including version infomation modified. + +## example + +- add new refactoring examples. + +# Phytium Standalone SDK 2023-4-21 ChangeLog + +Change Log since 2023-04-12 + +## example + +- add serial refactoring example. + +# Phytium Standalone SDK 2023-4-20 ChangeLog + +Change Log since 2023-04-15 + +## example + +- add new spim test refactoring example. + +# Phytium Standalone SDK 2023-4-18 ChangeLog + +Change Log since 2023-04-13 + +## common + +- finterrupt: modify priority icc_pmr set and icc_rpr get, according to different configurations. + +# Phytium Standalone SDK 2023-4-18 ChangeLog + +Change Log since 2023-04-10 + +## example + +- add new sata test refactoring example. + +# Phytium Standalone SDK 2023-4-11 ChangeLog + +Change Log since 2023-04-11 + +## driver + +- resolve the driver clock configuration in xmac cannot perform network auto-negotiation bug. + +# Phytium Standalone SDK 2023-4-11 ChangeLog + +Change Log since 2023-03-30 + +## example + +- update lwip_start_up README.md : add new description about jumbo mode enable and related operating instructions. + +## driver + +- modify macro definitions about jumbo registers and delete useless code. + +## third-party + +- add new instructions which can change netif mtu manually according to the actual transmission. +- modify pbuf alloc type and delete redundant code. + +# Phytium Standalone SDK 2023-3-30 ChangeLog + +Change Log since 2023-03-29 + +## example + +- lwip instructions has been updated by which we can choose driver type manually. +- update README.md : add new description about lwip probe instructions. + +# Phytium Standalone SDK 2023-3-29 ChangeLog + +Change Log since 2023-03-27 + +## example + +- add new gdma test refactoring example: gdma_direct_transfer_example, gdma_bdl_transfer_example, gdma_performance_test_example. +- little change in old gdma example. + +## driver + +- add wait mode feature in gdma driver. + +# Phytium Standalone SDK 2023-3-27 ChangeLog + +Change Log since 2023-03-24 + +## example + +- remove lib_core0 lib_core1 folder,add apu_running and rpu_running,support more example. +- modified README.md and update picture. +- fix atomic operation bug. + +## doc + +- add libmetal.md to introduce how to use it + +## third-party + +- remove extra code + +# Phytium Standalone SDK 2023-3-24 ChangeLog + +Change Log since 2023-03-20 + +## third-party + +- add apps lwiperf by which we can test mac bandwidth +- modify kconfig to add a new feature : LWIP_WND_SCALE,which can boost window maximum + +# Phytium Standalone SDK 2023-3-23 ChangeLog + +Change Log since 2023-03-20 + +## example + +- modify the lvgl example +- change the cmd, and interface , add the test fig and modify the readme + +## driver + +- modify the format +- add a dump function +- change some function and interface +- generate a new lib driver of dcdp + +## third-party + +- delete the unused part of port +- modify the format + +# Phytium Standalone SDK 2023-3-20 ChangeLog + +Change Log since 2023-03-17 + +## aarch + +- Adapt exception frame sequence + +## example + +- Add some exception test example + +# Phytium Standalone SDK 2023-3-17 ChangeLog + +Change Log since 2023-03-17 + +- add pwm example + +# Phytium Standalone SDK 2023-3-13 ChangeLog + +Change Log since 2023-03-3 + +## third-party + +- delete redundant code about NO_SYS macro definition +- modify kconfig ：delete config_LWIP_PORT_DEBUG_EN and add config_LWIP_USE_MEM__HEAP_DEBUG, which can manage parameters in memory debug mode +- modify LwipPortStop function : add dhcp_cleanup api and free emac after sys_thread_delete + +# Phytium Standalone SDK 2023-3-3 ChangeLog + +Change Log since 2023-03-3 + +# third-party + +- delete redundant code about NO_SYS macro definition +- modify kconfig ：delete config_LWIP_PORT_DEBUG_EN and add config_LWIP_USE_MEM__HEAP_DEBUG, which can manage parameters in memory debug mode +- modify LwipPortStop function : add dhcp_cleanup api and free emac after sys_thread_delete + +# Phytium Standalone SDK 2023-3-3 ChangeLog + +Change Log since 2023-03-1 + +- add qspi example + # Phytium Standalone SDK 2023-3-2 ChangeLog Change Log since 2023-03-01 @@ -15,7 +598,7 @@ Change Log since 2023-03-01 - add drviver.mk, board.mk, arch.mk and lib.mk, to seprate src and inc to groups - remove un-used packsource.mk - support compiling with makefile depends -- support compiling drviver only without arch support +- support compiling drviver only without arch support ## drivers @@ -33,7 +616,7 @@ Change Log since 2023-03-01 ## baremetal -- add multi-display test example +- add multi-display test example ## driver @@ -43,6 +626,18 @@ Change Log since 2023-03-01 - change the lvgl/port config and adapt to the multi-display config +# Phytium Standalone SDK 2023-03-01 ChangeLog + +Change Log since 2023-03-01 + +## example + +- add can example, modify adc example + +## driver + +- modify can driver + # Phytium Standalone SDK 2023-3-1 ChangeLog Change Log since 2023-02-20 diff --git a/bsp/phytium/libraries/standalone/doc/fig/flush_cache.png b/bsp/phytium/libraries/standalone/doc/fig/flush_cache.png new file mode 100644 index 00000000000..ca79e63a077 Binary files /dev/null and b/bsp/phytium/libraries/standalone/doc/fig/flush_cache.png differ diff --git a/bsp/phytium/libraries/standalone/doc/reference/cpu/interrupt.md b/bsp/phytium/libraries/standalone/doc/reference/cpu/finterrupt.md similarity index 95% rename from bsp/phytium/libraries/standalone/doc/reference/cpu/interrupt.md rename to bsp/phytium/libraries/standalone/doc/reference/cpu/finterrupt.md index cb5360de7fd..98d497e8dd6 100644 --- a/bsp/phytium/libraries/standalone/doc/reference/cpu/interrupt.md +++ b/bsp/phytium/libraries/standalone/doc/reference/cpu/finterrupt.md @@ -21,7 +21,7 @@ * ----- ------     --------    -------------------------------------- --> -# interrupt +# finterrupt ## 1概述 @@ -65,7 +65,6 @@ struct IrqDesc }; ``` - ``` #define INTERRUPT_CPU_ALL_SELECT 0xffffffffffffffffULL /* 当进行核间，发送给所有核心时需要用到的参数 */ #define INTERRUPT_CPU_TARGET_ALL_SET 0xffffffffUL /* 设置SPI 中断亲和度时，此值默认SPI 中断发送给所有人 */ @@ -137,15 +136,14 @@ IRQ_PRIORITY_MASK_* 中断优先级掩码一共支持以上这16个挡位，当 #define FINT_SET_TARGET_ERR /* 涉及到CPU id 的配置时，CPU 不具有此ID 信息 */ #define FINT_INT_NUM_NOT_FIT /* 使用中断号不符合当前实际情况 */ - ## 5应用示例 -/baremetal/example/peripheral/gic/fgic_test gic与interrupt 特性例程 +/baremetal/example/peripheral/gic/fgic_test gic与interrupt 特性例程 ## 6API使用步骤 1. 初始化中断模块,根据当前使用此核心角色的定位（主核、从核），进行初始化 - + ``` InterruptInit(&interrupt_instance,INTERRUPT_DRV_INTS_ID,INTERRUPT_ROLE_MASTER); ``` @@ -202,20 +200,22 @@ InterruptMask(INT_NUM) ### 1. InterruptInit - ``` void InterruptInit(InterruptDrvType * int_driver_p,u32 instance_id,INTERRUPT_ROLE_SELECT role_select) ``` #### 介绍 + 初始化中断模块的接口函数 #### 参数 + - InterruptDrvType * int_driver_p ： 指向中断驱动实例的指针 - u32 instance_id: 驱动实例的标号 - INTERRUPT_ROLE_SELECT role_select ：初始化中断接口时的角色选择。INTERRUPT_ROLE_MASTER 作为主核角色，INTERRUPT_ROLE_SLAVE 作为从核角色。具体特点参照数据结构中的描述 #### 返回 + 无 ### 2. InterruptMask @@ -225,12 +225,15 @@ void InterruptMask(int int_id) ``` #### 介绍 + 基于中断ID关闭对应的中断 #### 参数 + - int int_id ：中断的id 编号 #### 返回 + 无 ### 3. InterruptUmask @@ -240,12 +243,15 @@ void InterruptUmask(int int_id) ``` #### 介绍 + 基于中断ID开启对应的中断 #### 参数 + - int int_id ：中断的id 编号 #### 返回 + 无 ### 4. InterruptSetTargetCpus @@ -255,13 +261,16 @@ FError InterruptSetTargetCpus(int int_id,u32 cpu_id) ``` #### 介绍 + 将中断路由给特定的CPU,或者路由给所有的CPU #### 参数 + - int int_id ：中断的id 编号 ，中断优先级范围为 32-1019 - u32 cpu_id : 需要路由给CPU的编号，如果值为INTERRUPT_CPU_TARGET_ALL_SET 则路由给芯片中所有可以接收此中断的CPU #### 返回 + FError FINT_SUCCESS：设置成功，FINT_INT_NUM_NOT_FIT：使用中断号不符合当前实际情况 ，FINT_SET_TARGET_ERR： 涉及到CPU id 的配置时，CPU 不具有此ID 信息 ### 5. InterruptGetTargetCpus @@ -271,13 +280,16 @@ FError InterruptGetTargetCpus(int int_id,u32 *cpu_p) ``` #### 介绍 + 基于中断ID 获取中断的路由信息 #### 参数 + - int int_id ：中断的id 编号 - u32 *cpu_p : 它的值为：需要路由给CPU的编号，如果值为INTERRUPT_CPU_TARGET_ALL_SET 则路由给芯片中所有可以接收此中断的CPU #### 返回 + FError FINT_SUCCESS：设置成功，FINT_INT_NUM_NOT_FIT：使用中断号不符合当前实际情况 ，FINT_SET_TARGET_ERR： 涉及到CPU id 的配置时，CPU 不具有此ID 信息 ### 6. InterruptSetTrigerMode @@ -287,14 +299,17 @@ void InterruptSetTrigerMode(int int_id, unsigned int mode) ``` #### 介绍 + 基于中断ID 设置中断的触发方式 #### 参数 + - int int_id ：中断的id 编号 - unsigned int mode : IRQ_MODE_TRIG_LEVEL ：(0x00) /* Trigger: level triggered interrupt */ - IRQ_MODE_TRIG_EDGE ：(0x01) /* Trigger: edge triggered interrupt */ #### 返回 + 无 ### 7. InterruptGetTrigerMode @@ -304,12 +319,15 @@ unsigned int InterruptGetTrigerMode(int int_id) ``` #### 介绍 + 基于中断ID 获取中断的触发方式 #### 参数 + - int int_id ：中断的id 编号 #### 返回 + - unsigned int mode : IRQ_MODE_TRIG_LEVEL ：(0x00) /* Trigger: level triggered interrupt */ - IRQ_MODE_TRIG_EDGE ：(0x01) /* Trigger: edge triggered interrupt */ @@ -320,13 +338,16 @@ void InterruptSetPriority(int int_id, unsigned int priority) ``` #### 介绍 + 基于中断ID 设置中断的触发方式 #### 参数 + - int int_id ：中断的id 编号 - unsigned int priority ：中断优先级的值 ，采用IRQ_PRIORITY_VALUE_*的值作为输入 #### 返回 + 无 ### 9. InterruptGetPriority @@ -336,13 +357,16 @@ void InterruptSetPriority(int int_id, unsigned int priority) ``` #### 介绍 + 基于中断ID获取中断的触发方式 #### 参数 + - int int_id ：中断的id 编号 - unsigned int priority ：中断优先级的值 #### 返回 + 无 ### 10. InterruptSetPriorityMask @@ -352,12 +376,15 @@ void InterruptSetPriorityMask(unsigned int priority) ``` #### 介绍 + 设置中断优先级掩码 #### 参数 + - unsigned int priority ：中断掩码值，当设置此掩码之后，各个中断优先级的值必须小于此值，才能被CPU 承认，并且转为激活态 。采用IRQ_PRIORITY_MASK_* 参数作为输入 #### 返回 + 无 ### 11. InterruptGetPriorityMask @@ -367,11 +394,13 @@ void InterruptGetPriorityMask(void) ``` #### 介绍 + 获取中断优先级掩码 #### 参数 #### 返回 + - unsigned int priority ：中断掩码值，当设置此掩码之后，各个中断优先级的值必须小于此值，才能被CPU 承认，并且转为激活态 ### 12. InterruptSetPriorityGroupBits @@ -381,15 +410,19 @@ void InterruptSetPriorityGroupBits(unsigned int bits) ``` #### 介绍 + 设置中断优先级分组位 #### 参数 + - unsigned int bits ：该字段的值控制如何将8位中断优先级字段拆分为组优先级字段与子优先级字段，采用IRQ_GROUP_PRIORITY_*参数作为输入。 分组关系如下： - * |bits 取值 ----------------0-------1--------2------3-------4------5-------6-------7 - * |组 优先级有效值取值------[---]----[7:1]---[7:2]--[7:3]---[7:4]--[7:5]--[7:6]---[7] - * |子 优先级有效值取值------[---]-----[0]----[1:0]--[2:0]---[3:0]---[4:0]--[5:0]--[6:0] - + +* |bits 取值 ----------------0-------1--------2------3-------4------5-------6-------7 +* |组 优先级有效值取值------[---]----[7:1]---[7:2]--[7:3]---[7:4]--[7:5]--[7:6]---[7] +* |子 优先级有效值取值------[---]-----[0]----[1:0]--[2:0]---[3:0]---[4:0]--[5:0]--[6:0] + #### 返回 + 无 ### 13. InterruptInstall @@ -399,15 +432,18 @@ IrqHandler InterruptInstall(int int_id, IrqHandler handler,void *param, const ch ``` #### 介绍 + 本函数将自定义的中断回调函数与回调参数注册至对应中断id数据结构中 #### 参数 + - int int_id：中断的id 编号 - IrqHandler handler：中断回调函数 - void *param：中断回调参数 - const char *name：中断函数的命名 - + #### 返回 + 无 ### 14. InterruptCoreInterSend @@ -417,13 +453,16 @@ void InterruptCoreInterSend(int ipi_vector, u64 cpu_mask) ``` #### 介绍 + 核心间中断触发函数 #### 参数 + - int int_id：中断的id 编号 ,中断范围 0~15 -- u64 cpu_mask：cpu_mask表示每一位代表所选CPU，例如，0x3代表core0和CORE1。 +- u64 cpu_mask：cpu_mask表示每一位代表所选CPU，例如，0x3代表core0和CORE1。 #### 返回 + 无 ### 15. InterruptEarlyInit @@ -433,10 +472,31 @@ void InterruptEarlyInit(void) ``` #### 介绍 + 中断提前初始化函数，此函数一般在汇编代码时被调用，当用户设置默认初始化模式时，本函数将会使用CORE0为主核心并且初始化中断驱动中所有组件，其他CORE为从属核心将初始化中断驱动中必备的组件。 #### 参数 + 无 #### 返回 -无 \ No newline at end of file + +无 + +### 16. InterruptGetPriorityConfig + +``` +u8 InterruptGetPriorityConfig(void) +``` + +#### 介绍 + +根据uboot差异，返回是否需要对ICC_PMR和ICC_RPR的值进行转换。 + +#### 参数 + +无 + +#### 返回 + +u8 需要转换返回1，不需要转换返回0 \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal.dio b/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal.dio new file mode 100644 index 00000000000..2bbbf535829 --- /dev/null +++ b/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal.dio @@ -0,0 +1,540 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal.md b/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal.md new file mode 100644 index 00000000000..bec5af72ff6 --- /dev/null +++ b/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal.md @@ -0,0 +1,75 @@ +# libmetal + +## 1. 概述 + +- libmetal 是一个用于处理嵌入式系统中硬件访问和共享资源的库，其提供了一套简单易用的 API 接口，可以用于开发各种类型的嵌入式系统应用程序。 + +- 在本例程中，采用的APU与RPU的简称来模拟。 + +## 2. 功能 + +ARM 处理器可以分为两种类型：Application Processing Unit（APU）和 Real-time Processing Unit（RPU）。 + +APU 是系统中的主要处理器，它运行 Linux 或其他操作系统，用于执行应用程序和高层次的系统功能。APU 具有更高的性能和功能，可以支持多任务、多线程、虚拟化等复杂的应用场景。 + +RPU 是系统中的实时处理器，它专门用于处理实时任务和低延迟的操作，例如实时控制、数据采集和处理等。RPU 具有更低的延迟和更可靠的性能，可以保证实时任务的及时响应和稳定性。 + +## 3. 配置方法 + +在使用 libmetal 库时，可以针对不同的处理器核心和应用场景选择合适的 API 接口和驱动程序。例如，在 APU 上运行 Linux 操作系统时，可以使用 libmetal 提供的 Linux 驱动程序和 API 接口，以实现对硬件资源的访问和管理；而在 RPU 上运行裸机程序时，可以使用 libmetal 提供的裸机驱动程序和 API 接口，以实现对硬件资源的低延迟访问和控制。 + +但是本例程APU也采用裸机程序去运行。 + +## 4. 应用示例 + +"baremetal/example/system/amp/libmetal_test" + +## 5. API参考设计 + +- 流程图解 + +![流程图解](./libmetal.svg) + +### 5.1 用户定义 + +- 主要使用的结构体 + +![主要使用的结构体](./libmetal_struct.svg) + +在common文件夹的sys_init.c文件中，我们定义了三种metal_device，并对其进行了实例化，特别是shm的内存分配，需要根据实际需要进行配置。 + +- TTC（Time-Triggered Communication）是一种基于时间触发的通信机制，用于实时系统和分布式系统中的通信和同步。在 Libmetal 库中，TTC API 提供了时间触发机制和通信机制，用于周期性地触发事件和实现处理器之间的数据共享、通信和同步等操作。 + +- SHM（Shared Memory）是一种共享内存机制，用于在不同的处理器之间共享数据。在 Libmetal 库中，SHM API 提供了共享内存管理功能，包括创建共享内存区域、映射共享内存区域等。 + +- IPI（Inter-Processor Interrupt）是一种处理器之间的中断机制，用于实现处理器之间的通信和同步。在 Libmetal 库中，IPI API 提供了处理器之间的中断管理功能，包括注册中断处理函数、发送中断等。 + +其中结构体成员 '.regions' 可以根据自己的实际需求进行定义。如果您有多个物理地址空间需要描述，可以更改sys.h文件中的METAL_MAX_DEVICE_REGIONS来扩展多个地址空间，物理地址区域可以用于地址映射和访问设备的寄存器和内存空间。 + +结构体成员 ' metal_bus ' 在libmetal/metal/device.c中进行实例化 struct metal_bus metal_weak metal_generic_bus，采用弱符合定义的方式，也可根据自己的需求进行修改，决定后续的设备打开参数传递，后续初始化会进行说明。 + +### 5.2 初始化 + +#### 5.2.1 libmetal环境初始化 + +在shell下运行libmetalapu 后执行 FLibmetalSysInit() 函数： + +- FLibmetalSysInit -> ' metal_init(&metal_param); ' 初始化libmetal环境，首先进行log日志的打印初始化，然后执行metal_sys_init()，进行总线的注册，注意上述两个文件虽然都采用init.c的命名方式，但是其结构作用是单向依赖的关系，我们将上述metal_generic_bus的实例注册到链表中，方便后续查找打开设备。 + +- ' FRegisterMetalDevice() ' 进行设备的注册，将实例化的设备参数进行注册，将bus实例的指针指向初始化设备中的bus成员（其中static struct metal_device metal_dev_table[]与后面在实际例程中关系紧密，成员.regions是主要的操作对象）。 + +- ' FOpenMetalDevice() ' 根据bus的名字以及设备名称查找对应的内存空间以及操作，bus->ops.dev_open 可以在 metal_generic_bus实例中找到对应操作metal_generic_dev_open，直到找到并设置内存属性。 + +初始化完成后，我们就可以进行实例的演示。 + +#### 5.2.2 构建例程（以ipi_latency_demo.c、ipi_latency_demod.c为例） + +- 首先申明metal_device、metal_io_region的结构体指针，用于临时储存通过bus_name和设备名字查询到得设备.（环境初始化注册的metal_dev_table[]） +- 然后打开三种设备SHM、TTC、IPI，也可以根据需要使用部分设备，获取到已经注册的设备结构体地址. +- 进行中断绑定、原子标志位初始化（用于休眠等待，中断服务函数中结束休眠）和使能操作， 因为本项目并未使用ipi来绑定中断控制器得地址，所以采用软中断的操作来控制中断触发和绑定。 +- 运行measure_ipi_latency示例 +- 中断失能，关闭打开的设备 + +#### 5.2.3 关闭libmetal环境 + +- 如果不再使用libmetal环境可以使用 FLibmetalSysCleanup()关闭. \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal.svg b/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal.svg new file mode 100644 index 00000000000..8b8f9754741 --- /dev/null +++ b/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal.svg @@ -0,0 +1,4 @@ +
metal_device
metal_device
IPI metal device
IPI metal device
TTC metal device
TTC metal device
SHM metal device
SHM metal device

（处理器间中断）是一个处理器中断另一个处理器的机制。 这通常用于多处理器系统中的处理器间通信和同步。 Libmetal 提供了一个 IPI API，允许软件在不同的处理器之间发送和接收中断，而不管它们的架构如何。

（处理器间中断）是一个处理器中断另一个处理器的机制。 这通常用于多处理器系统中的处理器间通信和同步。 Libmetal 提供了一个 IPI API，允许软件在不同的处理器之间发送和接收中断，而不管它们的架构如何。 +

（时间触发通信）是一种基于公共时钟同步两个或多个处理器的机制。 这对于实现实时系统非常有用，其中精确计时至关重要。 Libmetal 提供了一个 TTC API，允许软件配置和管理 TTC 硬件，以及基于 TTC 时钟发送和接收消息。

（时间触发通信）是一种基于公共时钟同步两个或多个处理器的机制。 这对于实现实时系统非常有用，其中精确计时至关重要。 Libmetal 提供了一个 TTC API，允许软件配置和管理 TTC 硬件，以及基于 TTC 时钟发送和接收消息。 +

(共享内存) 是一种让两个或多个处理器共享公共内存区域的机制。 这对于实现处理器间通信和同步以及在不同处理器之间共享数据很有用。 Libmetal 提供了一个 SHM API，允许软件分配和释放共享内存区域，以及读取和写入这些区域的数据。

(共享内存) 是一种让两个或多个处理器共享公共内存区域的机制。 这对于实现处理器间通信和同步以及在不同处理器之间共享数据很有用。 Libmetal 提供了一个 SHM API，允许软件分配和释放共享内存区域，以及读取和写入这些区域的数据。 +
int ipi_latency_demod()
int ipi_latency_demod()
struct channel_s
struct channel_s
struct metal_io_region *ipi_io; /* IPI metal i/o region */
struct metal_io_region *ipi_io; /* IPI meta...
struct metal_io_region *shm_io; /* Shared memory metal i/o region */
struct metal_io_region *shm_io; /* Shared m...
struct metal_io_region *ttc_io; /* TTC metal i/o region */
struct metal_io_region *ttc_io; /* TTC meta...
uint32_t ipi_mask;             /* RPU IPI mask */
uint32_t ipi_mask;             /* RPU IPI m...
atomic_int remote_nkicked;     /* 0 - kicked from remote */
atomic_int remote_nkicked;     /* 0 - kicke...
ch
ch
int sys_init()
int sys_init()
enable_caches();
enable_caches();
struct metal_init_params metal_param
struct metal_init_params metal_param
metal_log_handler      log_handler;
metal_log_handler      log_handler;
enum metal_log_level       log_level;
enum metal_log_level       log_level;
init_uart();
init_uart();
init_irq()
init_irq()
port
port
port
port
port
port
/* Initialize libmetal environment */
  metal_init(&metal_param);
/* Initialize libmetal environment */...
/* Initialize metal Xilinx IRQ controller */
    ret = metal_xlnx_irq_init();
/* Initialize metal Xilinx IRQ controller */...
port
port
/* Register libmetal devices */
platform_register_metal_device();
/* Register libmetal devices */...
/* Open libmetal devices which have been registered */
open_metal_devices();
/* Open libmetal devices which have been registered */...
int open_metal_devices(void)
int open_metal_devices(void)
/* Open TTC device */
    ret = metal_device_open(BUS_NAME, TTC_DEV_NAME,&ttc_dev);
/* Open TTC device */...
/* Open shared memory device */
    ret = metal_device_open(BUS_NAME, SHM_DEV_NAME,&shm_dev);
/* Open shared memory device */...
/* Open IPI device */
    ret = metal_device_open(BUS_NAME, IPI_DEV_NAME,&ipi_dev);
/* Open IPI device */...
application
applica...
void close_metal_devices(void)
void close_metal_devices(void)
/* Close IPI device */
metal_device_close(ipi_dev);
/* Close IPI device */...
/* Close TTC device */
metal_device_close(ttc_dev);
/* Close TTC device */...
/* Close shared memory device */
metal_device_close(shm_dev);
/* Close shared memory device */...
void sys_cleanup()
void sys_cleanup()
/* Close libmetal devices which have been opened */
close_metal_devices();
/* Close libmetal devices which have been...
/* Finish libmetal environment */
    metal_finish();
/* Finish libmetal environment */...
disable_caches();
disable_caches();
static struct metal_device metal_dev_table[] = 
{
/* IPI device */
        .name = IPI_DEV_NAME,
        .bus = NULL,
        .num_regions = 1,
        .regions = {
            {
                .virt = (void *)IPI_BASE_ADDR,
                .physmap = &metal_phys[0],
                .size = 0x1000,
                .page_shift = DEFAULT_PAGE_SHIFT,
                .page_mask = DEFAULT_PAGE_MASK,
                .mem_flags = DEVICE_NONSHARED | PRIV_RW_USER_RW,
                .ops = {NULL},
            }},
        .node = {NULL},
        .irq_num = 1,
        .irq_info = (void *)IPI_IRQ_VECT_ID,
}
static struct metal_device metal_dev_table[] =...
const metal_phys_addr_t metal_phys[]
const metal_phys_addr_t metal...
IPI_BASE_ADDR
IPI_BASE_ADDR
SHM_BASE_ADDR
SHM_BASE_ADDR
TTC0_BASE_ADDR
TTC0_BASE_ADDR
struct metal_device
struct metal_device
*ipi_dev
*ipi_dev
*shm_dev
*shm_dev
*ttc_dev
*ttc_dev
sys_init.c
sys_init.c
实例化设备
实例化设备
main（）
main（）
libmetal_amp_demod.c
libmetal_amp_demod.c
Setup libmetal resources
sys_init();
Setup libmetal resources...
Run the shared memory throughput demo
shmem_throughput_demod();
Run the shared memory throughput demo...
Run the shared memory latency demo
shmem_latency_demod();
Run the shared memory latency demo...
Run the ipi latency demo
ipi_latency_demod();
Run the ipi latency demo...
Run the IPI with shared memory demo
ipi_shmem_demod();
Run the IPI with shared memory demo...
Run the atomic across shared memory demo
atomic_shmem_demod();
Run the atomic across shared memory demo...
Run the shared memory demo
shmem_demod();
Run the shared memory demo...
Cleanup libmetal resources
sys_cleanup();
Cleanup libmetal resources...
shmem_echod() - Show use of shared memory with libmetal.
Wait for message from APU. Once received, read and echo it back.
shmem_echod() - Show use of shared memory wit...
reset_timer() - function to reset TTC counter
Set the RST bit in the Count Control Reg.
stop_timer() - function to stop TTC counter
Set the disable bit in the Count Control Reg.
reset_timer() - function to reset TTC counter...
ipi_irq_handler() - IPI interrupt handler
measure_ipi_latencyd() - measure IPI latency with libmetal Loop until APU tells RPU to stop via shared memory.
ipi_irq_handler() - IPI interrupt handler...
shm
shm
ttc
ttc
ipi
ipi
shmem_demo.c(主机 APU)
shmem_demo.c(主机 APU)
1.Open the shared memory device.
1.Open the shared memory device.
2.Clear the demo control TX/RX available values in shared memory.
2.Clear the demo control TX/RX available value...
3.APU set demo control in shared memory to notify RPU demo has started
3.APU set demo control in shared memory to not...
4.APU will write message to the shared memory.
4.APU will write message to the shared memory.
5.APU will increase TX avail values in the shared memory to notify RPU there is a message ready to read.
5.APU will increase TX avail values in the sha...
6.APU will poll the RX avail value in th shared memory to see if RPU has echoed back the message into the shared memory.
6.APU will poll the RX avail value in th share...
7.When APU knows there is new RX message available, it will read the RX message from the shared memory.
7.When APU knows there is new RX message avail...
8.APU will verify the message to see if it matches the one it has sent.
8.APU will verify the message to see if it mat...
9.Close the shared memory device.
9.Close the shared memory device.
shmem_demo.c(从机 RPU)
shmem_demo.c(从机 RPU)
1.Get the shared memory device I/O region.
1.Get the shared memory device I/O region.
2.Clear the demo control value in shared memory.
2.Clear the demo control value in shared memor...
3.Check the demo control value in the shared memory to wait for APU to start the demo.
3.Check the demo control value in the shared m...
4.Once the demo control value indicates the demo starts, it polls on RX available value to see if there is new RX message available.
4.Once the demo control value indicates the de...
5.If there is a new RX message available, it reads the message from the shared memory.
5.If there is a new RX message available, it r...
6.It echos back the message to the shared memory.
6.It echos back the message to the shared memo...
7.AIt increases the TX available value in the shared memory to notify the other end there is a message available to read.
7.AIt increases the TX available value in the...
8.Check if the demo control value and the RX available values to see if demo finishes and if there is new RX data available.
8.Check if the demo control value and the RX a...
主从机通信交互
主从机通信交互Table
偏移
偏移
大小
大小
说明
说明
0
0
4Bytes
4Bytes
DEMO control status shows if demo starts or not
DEMO control status shows if demo starts or not
0x04
0x04
4Bytes
4Bytes
number of APU to RPU buffers available to RPU
number of APU to RPU buffers available to RPU
0x08
0x08
4Bytes
4Bytes
number of APU to RPU buffers consumed by RPU
number of APU to RPU buffers consumed by RPU
0x0c
0x0c
4Bytes
4Bytes
number of RPU to APU buffers available to APU
number of RPU to APU buffers available to APU
0x10
0x10
4Bytes
4Bytes
number of RPU to APU buffers consumed by APU
number of RPU to APU buffers consumed by APU
0x14
0x14
1KBytes
1KBytes
APU to RPU buffer
APU to RPU buffer
0x800
0x800
1KBytes
1KBytes
RPU to APU buffer
RPU to APU bufferText is not SVG - cannot display \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal_struct.dio b/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal_struct.dio new file mode 100644 index 00000000000..0dfa9622530 --- /dev/null +++ b/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal_struct.dio @@ -0,0 +1,94 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal_struct.svg b/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal_struct.svg new file mode 100644 index 00000000000..0299cca6e2e --- /dev/null +++ b/bsp/phytium/libraries/standalone/doc/reference/cpu/libmetal_struct.svg @@ -0,0 +1 @@ +
metal_device
metal_device
const char             *name;       /**< Device name */
const char             *name;       /**< Device name */
struct metal_bus
struct metal_bus
const char     *name;
const char     *name;
/** Bus operations. */


struct metal_bus_ops {
void        (*bus_close)(struct metal_bus *bus);
int     (*dev_open)(struct metal_bus *bus,
                    const char *dev_name,
                    struct metal_device **device);
void        (*dev_close)(struct metal_bus *bus,
                     struct metal_device *device);
void        (*dev_irq_ack)(struct metal_bus *bus,
                       struct metal_device *device,
                       int irq);
int     (*dev_dma_map)(struct metal_bus *bus,
                       struct metal_device *device,
                       uint32_t dir,
                       struct metal_sg *sg_in,
                       int nents_in,
                       struct metal_sg *sg_out);
 void        (*dev_dma_unmap)(struct metal_bus *bus,
                     struct metal_device *device,
                     uint32_t dir,
                     struct metal_sg *sg,
                     int nents);
};
/** Bus operations. */...
struct metal_list  devices;
struct metal_list  devices;
struct metal_list  node;
struct metal_list  node;
unsigned int           num_regions; /**< Number of I/O regions indevice */
unsigned int           num_regions; /**< Number of I/O regions indevice */

struct metal_io_region regions[METAL_MAX_DEVICE_REGIONS]; /**< Array of I/O regions in device*/

struct metal_io_region regions[METAL_MAX_DEVICE_REGIONS]; /**< Array of I/O regions in device*/...
void                   *irq_info;  /**< IRQ ID */
void                   *irq_info;  /**< IRQ ID */
int                    irq_num;    /**< Number of IRQs per device */
int                    irq_num;    /**< Number of IRQs per device */
struct metal_list      node;       /**< Node on bus' list of devices */
struct metal_list      node;       /**< Node on bus' list of devices */
struct metal_io_region
struct metal_io_region
struct metal_bus       *bus;        /**< Bus that contains device */
struct metal_bus       *bus;        /**< Bus that contains device */
struct metal_bus_ops   ops;
struct metal_bus_ops   ops;
void           *virt;      /**< base virtual address */
void           *virt;      /**< base virtual address...
const metal_phys_addr_t    *physmap;   /**< table of base physical address
 of each of the pages in the I/O region*/
const metal_phys_addr_t    *physmap;   /**< table of...
size_t         size;/**< size of the I/O region */
size_t         size;/**< size of the I/O region */
unsigned long      page_shift; /**< page shift of I/O region */
unsigned long      page_shift; /**< page shift of I/...
metal_phys_addr_t  page_mask;  /**< page mask of I/O region */
metal_phys_addr_t  page_mask;  /**< page mask of I/O...
unsigned int       mem_flags;  /**< memory attribute of the I/O region */
unsigned int       mem_flags;  /**< memory attribute...
struct metal_io_ops    ops;        /**< I/O region operations */
struct metal_io_ops    ops;        /**< I/O region o...Text is not SVG - cannot display \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/doc/reference/cpu/psci.md b/bsp/phytium/libraries/standalone/doc/reference/cpu/psci.md new file mode 100644 index 00000000000..62d704f6442 --- /dev/null +++ b/bsp/phytium/libraries/standalone/doc/reference/cpu/psci.md @@ -0,0 +1,334 @@ +# fpsci + +## 1概述 + +PSCI 规范关注的是安全世界和正常世界之间进行电源管理的接口。 +PSCI具有以下预期用途： + +- 提供一个通用接口，监管软件可以使用该接口在以下情况下管理电源： + - 核心空闲管理。（core idle management） + - 动态添加和移除系统中的核心，通常称为热插拔。 （hotplug） + - 辅助核心引导。（Secibdary core boot） + - 在不同核心之间移动可信操作系统上下文。 (trusted) + - 系统关机和重启。(system shutdown and reset) +- 提供一个接口，监管软件可以与固件表（FDT和ACPI）描述一起使用，以支持电源管理代码的通用化。 + +## 2驱动功能 + +组成由以下所示 +. +├── fpsci.c +└── fpsci.h + +本驱动为开发者提供了特性： + +1. PSCI接口初始化以及function id 检查 +2. 查看PSCI 版本信息功能 +3. CPU_SUSPEND接口支持 +4. CPU hotplug 接口支持 +5. CPU Affinity power state 查看接口支持 +6. 冷启动接口支持 + +## 3数据结构 + +## 4错误码定义 + +```c +#define FPSCI_SUCCESS 0 +#define FPSCI_NOT_SUPPORTED -1 +#define FPSCI_INVALID_PARAMS -2 +#define FPSCI_DENIED -3 +#define FPSCI_ALREADY_ON -4 +#define FPSCI_ON_PENDING -5 +#define FPSCI_INTERNAL_FAILURE -6 +#define FPSCI_NOT_PRESENT -7 +#define FPSCI_DISABLED -8 +#define FPSCI_INVALID_ADDRESS -9 +``` + +## 5应用示例 + +/example/arch/armv8/fpsci --- 展示接口特性以及cpu hotplug 特性 + +## 6API使用步骤 + +1. 初始化PSCI模块，并且确定当前soc下支持哪些psci的functions + + ```c + FPsciInit() ; + ``` +2. 初始化之后以下接口可以被正常使用： + + ```c + FPsciVersion + FPsciCpuSuspend + FPsciCpuOn + FPsciAffinityInfo + FPsciSystemReset + FPsciFeatureCheck + FPsciCpuOff + ``` +3. hotplug 功能示例 + + ```c + /* 需要power down 的核心,假设次核心ID为1，主动调用以下接口实现CPU_OFF */ + FPsciCpuOff() ; + /* Never get here */ + ``` + + ```c + /* 准备唤醒核心ID为1的CPU */ + unsigned long cpu_affinity ; + GetCpuAffinity(1,&cpu_affinity) ; + /* 其中0x80100000为核心1需要执行的地址 */ + FPsciCpuOn(cpu_affinity,0x80100000,0) ; + ``` + +## 7API介绍 + +### 1. FPsciInit + +```c +int FPsciInit(void) +``` + +#### 介绍 + +初始化 PSCI 驱动的接口函数。 + +#### 参数 + +无 + +#### 返回 + +- int: 返回值表示初始化结果，0 表示初始化成功，其他值表示初始化失败。 + +#### 功能描述 + +- 调用 FSmccInit 函数对 SMCC 接口进行初始化。 +- 调用 FPsciVersion 函数获取 PSCI 的版本信息，并打印主版本号和次版本号。 +- 调用 FPsciCheckFeatures 函数检查 PSCI 支持的接口是否可用。 + +### 2. FPsciSystemReset + +```c +void FPsciSystemReset(u32 reset_type) +``` + +#### 介绍 + +重置系统的接口函数。 + +#### 参数 + +- u32 reset_type: 系统重置的类型（冷启动/热启动）。使用FPSCI_SYSTEM_RESET_TYPE_COLD 、FPSCI_SYSTEM_RESET_TYPE_WARM + +#### 返回 + +无 + +#### 功能描述 + +- 该函数用于重置系统。通过 reset_type 参数指定重置的类型。 +- 在调用此函数之前，请确保 PSCI 驱动已经初始化。 +- 函数内部通过调用 f_psci_invoke 函数实现 PSCI 接口的调用，并传递相应的参数。 +- 使用 FASSERT 宏来检查相关条件是否满足，例如检查 fpsci_ringt_bit_flg 和 f_psci_invoke 是否已经初始化。 + +注意： + +- 调用该函数将会重置整个系统，请谨慎使用。该接口是否有效也与固件有关 + +### 3. FPsciVersion + +```c +int FPsciVersion(void) +``` + +#### 介绍 + +获取 PSCI 实现的版本信息的接口函数。 + +#### 返回 + +- int: PSCI 实现的版本信息。配合FPSCI_MAJOR_VERSION与 FPSCI_MINOR_VERSION 可以解析出版本号 + +#### 功能描述 + +- 该函数用于获取 PSCI 实现的版本信息，该信息从 PSCI VERSION 接口中获取。 +- 在调用此函数之前，请确保 PSCI 驱动已经初始化。 +- 函数内部通过调用 f_psci_invoke 函数实现 PSCI 接口的调用，并传递相应的参数。 +- 使用 FASSERT 宏来检查相关条件是否满足，例如检查 f_psci_invoke 是否已经初始化。 +- 函数返回 PSCI 实现的版本信息，该信息存储在 f_psci_invoke 的返回值 res.a0 中。 + +### 4. FPsciCpuSuspend + +```c +int FPsciCpuSuspend(u32 power_state, unsigned long entry_point_address, unsigned long context_id) +``` + +#### 介绍 + +暂停特定 CPU 的执行的接口函数。 + +#### 参数 + +- u32 power_state: 要进入的电源状态。 +- unsigned long entry_point_address: 在唤醒时要执行的地址。 +- unsigned long context_id: 上下文特定的标识符。 + +#### 返回 + +- int: 操作的状态代码，根据 PSCI 规范定义。 + +#### 功能描述 + +- 该函数用于暂停特定 CPU 的执行，并返回指示操作是否成功的状态代码。 +- 函数参数 power_state 指定要进入的电源状态，entry_point_address 指定唤醒时要执行的地址，context_id 为上下文特定的标识符。 +- 在调用此函数之前，请确保 PSCI 驱动已经初始化。 +- 函数内部通过调用 f_psci_invoke 函数实现 PSCI 接口的调用，并传递相应的参数。 +- 使用 FASSERT 宏来检查相关条件是否满足，例如检查 f_psci_invoke 是否已经初始化。 +- 函数返回操作的状态代码，该代码存储在 f_psci_invoke 的返回值 res.a0 中，状态代码的含义由 PSCI 规范定义。 + +### 5. FPsciCpuOn + +```c +int FPsciCpuOn(unsigned long target_cpu, unsigned long entry_point_address, unsigned long context_id) +``` + +#### 介绍 + +启动特定 CPU 的接口函数。 + +#### 参数 + +- unsigned long target_cpu: 要启动的目标 CPU。 +- unsigned long entry_point_address: 在唤醒时要执行的地址。 +- unsigned long context_id: 上下文特定的标识符。 + +#### 返回 + +- int: 操作的状态代码，根据 PSCI 规范定义。 + +#### 功能描述 + +- 该函数用于启动特定 CPU，并返回指示操作是否成功的状态代码。 +- 函数参数 target_cpu 指定要启动的目标 CPU，entry_point_address 指定唤醒时要执行的地址，context_id 为上下文特定的标识符。 +- 根据目标 CPU 的位宽，选择相应的 PSCI_CPU_ON 接口 ID。 +- 在调用此函数之前，请确保 PSCI 驱动已经初始化。 +- 函数内部通过调用 f_psci_invoke 函数实现 PSCI 接口的调用，并传递相应的参数。 +- 使用 FASSERT 宏来检查相关条件是否满足，例如检查 f_psci_invoke 是否已经初始化。 +- 函数返回操作的状态代码，该代码存储在 f_psci_invoke 的返回值 res.a0 中，状态代码的含义由 PSCI 规范定义。 + +### 6. FPsciAffinityInfo + +```c +int FPsciAffinityInfo(unsigned long target_affinity, u32 lowest_affinity_level) +``` + +#### 介绍 + +获取特定关联级别的电源状态的接口函数。 + +#### 参数 + +- unsigned long target_affinity: 目标关联级别。 +- u32 lowest_affinity_level: 最低关联级别。 + +#### 返回 + +- int: 指定关联级别的电源状态，根据 PSCI 规范定义。 + +#### 功能描述 + +- 该函数用于获取特定关联级别的电源状态，并返回该电源状态的代码。 +- 函数参数 target_affinity 指定要获取电源状态的关联级别，lowest_affinity_level 指定最低关联级别。 +- 根据目标关联级别的位宽，选择相应的 PSCI_AFFINITY_INFO 接口 ID。 +- 在调用此函数之前，请确保 PSCI 驱动已经初始化。 +- 函数内部通过调用 f_psci_invoke 函数实现 PSCI 接口的调用，并传递相应的参数。 +- 使用 FASSERT 宏来检查相关条件是否满足，例如检查 f_psci_invoke 是否已经初始化。 +- 函数返回指定关联级别的电源状态代码，该代码存储在 f_psci_invoke 的返回值 res.a0 中，电源状态的含义由 PSCI 规范定义。 + +### 7. FPsciFeatures + +```c +int FPsciFeatures(u32 psci_fid) +``` + +#### 介绍 + +检查是否支持某个 PSCI 功能的接口函数。 + +#### 参数 + +- u32 psci_fid: 要检查的 PSCI 功能的功能 ID。 + +#### 返回 + +- int: 如果支持该功能，则返回1；否则返回0。 + +#### 功能描述 + +- 该函数用于检查是否支持指定的 PSCI 功能。 +- 在调用此函数之前，请确保 PSCI 驱动已经初始化。 +- 使用 FASSERT 宏来检查 f_psci_invoke 是否已经初始化。 +- 函数内部通过调用 f_psci_invoke 函数实现 PSCI 接口的调用，并传递相应的参数。 +- 函数返回值为1表示支持指定的 PSCI 功能，返回值为0表示不支持。 + +### 8. FPsciCpuOff + +```c +int FPsciCpuOff(void) +``` + +#### 介绍 + +这是 PSCI CPU_Off 接口的包装函数，用于关闭当前 CPU。 + +#### 返回 + +- int: 返回 'FSmcccRes' 结构体的 'a0' 字段，表示调用的结果。返回值为 0 (PSCI_SUCCESS) 表示成功，其他任何值表示发生了错误。 + +#### 功能描述 + +- 该函数用于关闭当前 CPU，即将当前 CPU 关机。 +- 在调用此函数之前，请确保 PSCI 驱动已经初始化。 +- 使用 FASSERT 宏来检查 f_psci_invoke 是否已经初始化。 +- 函数内部通过调用 f_psci_invoke 函数实现 PSCI 接口的调用，并传递相应的参数。 +- 函数返回值为 'a0' 字段，表示 PSCI 调用的结果。返回值为 0 表示成功，其他任何值表示发生了错误。 + +注意事项： + +- 被 CPU_OFF 关闭的核心只能通过 CPU_ON 命令重新启动。 + + +### 10. FPsciCpuMaskOn + +```c +int FPsciCpuMaskOn(s32 cpu_id_mask, uintptr bootaddr) +``` + +#### 介绍 + +此函数用于根据 CPU ID 掩码将指定的 CPU 打开并进入指定的入口地址。 + +#### 参数 + +- s32 cpu_id_mask: CPU ID 掩码，用于指定要打开的 CPU。 +- uintptr bootaddr: 要执行的入口地址。 + +#### 返回 + +- int: 函数执行的结果代码。返回值为 FPSCI_SUCCESS 表示成功，其他值表示错误。 + +#### 功能描述 + +- 通过调用 `GetCpuAffinityByMask` 函数获取与 CPU ID 掩码对应的 CPU 所属的集群。 +- 如果获取集群失败，则返回 `FPSCI_INVALID_PARAMS` 错误。 +- 否则，调用 `FPsciCpuOn` 函数将指定的集群打开，并进入指定的入口地址。 +- 函数返回 `FPsciCpuOn` 函数的执行结果。 + +注意事项： + +- 在调用此函数之前，请确保 PSCI 驱动已经初始化。 +- 请确保 `GetCpuAffinityByMask` 函数已经正确实现，并能根据 CPU ID 掩码获取正确的 CPU 所属的集群信息。 diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fddma.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fddma.md index 0663e4b9801..e45c959d863 100644 --- a/bsp/phytium/libraries/standalone/doc/reference/driver/fddma.md +++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fddma.md @@ -64,7 +64,6 @@ typedef struct uintptr ddr_addr; /* DMA channel DDR address, could be source or destination */ u32 dev_addr; /* DMA channel Perpherial, could be source or destination */ u32 trans_len; /* DMA channel transfer length */ -#define FDDMA_MAX_TRANSFER_LEN 64 /* max bytes in transfer */ #define FDDMA_MIN_TRANSFER_LEN 4 /* min bytes in transfer */ u32 timeout; /* timeout = 0 means no use DMA timeout */ } FDdmaChanConfig; /* DDMA channel instance */ diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fgdma.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fgdma.md index 7cac74a8201..0fa20eb345d 100644 --- a/bsp/phytium/libraries/standalone/doc/reference/driver/fgdma.md +++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fgdma.md @@ -66,8 +66,8 @@ typedef struct FGdmaOperPriority wr_qos; /* DMA通道写Qos配置 */ FGdmaOperMode trans_mode; /* DMA通道的操作模式，直接模式或者BDL模式 */ /* Direct模式有效 */ - FGdmaBurstSize rd_align; /* DMA读请求的Burst对齐方式 */ - FGdmaBurstSize wr_align; /* DMA写请求的Burst对齐方式 */ + FGdmaBurstSize rd_size; /* DMA读请求的burst size */ + FGdmaBurstSize wr_size; /* DMA写请求的burst size */ /* BDL模式有效 */ boolean roll_back; /* 循环模式，TRUE: 当前BDL列表完成后，从第一个BDL项从新开始传输 */ FGdmaBdlDesc *descs; diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fiopad.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fiopad.md new file mode 100644 index 00000000000..a9a095ed4f4 --- /dev/null +++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fiopad.md @@ -0,0 +1,470 @@ +# FIOPAD 驱动程序 + +## 1. 概述 +IOPad，是输入/输出（Input/Output）引脚。嵌入式系统通常由处理器、内存、外设和输入/输出接口组成。输入/输出引脚是用于连接外部设备和嵌入式系统的接口。它们用于数据和控制信号的输入和输出，可以连接各种传感器、执行器、存储设备等外围设备。IOPad通常由特定的计算机芯片或微控制器提供，并通过编程方式进行配置和控制 + +## 2. 功能 + +iopad控制器驱动提供了iopad的控制访问方法， +- 初始化iopad控制器 +- 配置引脚复用，引脚输入输出延迟等 + +驱动相关的源文件包括 +``` +. +├── fiopad_g.c +├── fiopad_hw.c +├── fiopad_hw.h +├── fiopad_intr.c +├── fiopad_sinit.c +├── fiopad.c +└── fiopad.h +``` + +## 3. 配置方法 + +以下部分将指导您完成 fiopad 驱动的软件配置: + +- 初始化iopad控制器 +- 设置引脚功能复用，设置引脚延时 + +## 4 应用示例 + + +## 5. API参考 + +### 5.1. 用户数据结构 + +- fiopad控制数据 + +```c +typedef struct +{ + FIOPadConfig config;/* iopad config */ + u32 is_ready;/* iopad init ready flag */ + +} FIOPadCtrl; +``` + +- fiopad配置数据，FIOPadConfig主要是iopad控制器id、基地址，FIOPadMulConfig主要包括用户可配置的复用参数，包括复用功能，上下拉，驱动能力等，FIOPadDelayConfig主要用户可配置的延时参数，输入输出方向，粗调延时，精调延时等 + +```c +typedef struct +{ + u32 instance_id; /* Device instance id */ + uintptr base_address; /* iopad control register base address */ + +} FIOPadConfig; +``` + +- fiopad复用功能，E2000最多支持8种功能 +```c +typedef enum +{ + FIOPAD_FUNC0 = 0b000, + FIOPAD_FUNC1, + FIOPAD_FUNC2, + FIOPAD_FUNC3 = 0b011, + FIOPAD_FUNC4, + FIOPAD_FUNC5, + FIOPAD_FUNC6, + FIOPAD_FUNC7 = 0b111, + + FIOPAD_NUM_OF_FUNC +} FIOPadFunc; /* Pin multiplexing function configuration, func0 is the default function */ +``` + +- fiopad驱动能力 +```c +typedef enum +{ + FIOPAD_DRV0 = 0b0000, + FIOPAD_DRV1, + FIOPAD_DRV2, + FIOPAD_DRV3, + FIOPAD_DRV4, + FIOPAD_DRV5, + FIOPAD_DRV6, + FIOPAD_DRV7, + FIOPAD_DRV8, + FIOPAD_DRV9, + FIOPAD_DRV10, + FIOPAD_DRV11, + FIOPAD_DRV12, + FIOPAD_DRV13, + FIOPAD_DRV14, + FIOPAD_DRV15 = 0b1111, + + FIOPAD_NUM_OF_DRIVE +} FIOPadDrive; /* Pin drive capability configuration ，divided into 16 levels*/ +``` + +- fiopad上下拉配置 +```c +typedef enum +{ + FIOPAD_PULL_NONE = 0b00, + FIOPAD_PULL_DOWN = 0b01, + FIOPAD_PULL_UP = 0b10, + + FIOPAD_NUM_OF_PULL +} FIOPadPull; /* Pin up pull-down configuration */ + +``` + +- fiopad延迟输入输出方向配置 +```c +typedef enum +{ + FIOPAD_OUTPUT_DELAY = 0, /* Delay setting direction to output */ + FIOPAD_INPUT_DELAY, /* Delay setting direction to input */ + + FIOPAD_NUM_OF_DELAY_DIR +} FIOPadDelayDir; /* Pin delay configuration direction */ + +``` + +- fiopad粗调，精调类型配置 +```c +typedef enum +{ + FIOPAD_DELAY_COARSE_TUNING = 0, /*delay coarse tuning */ + FIOPAD_DELAY_FINE_TUNING, /*delay fine tuning */ + + FIOPAD_NUM_OF_DELAY_TYPE +} FIOPadDelayType; /* Pin delay configuration type */ + +``` + +- fiopad粗调，精调类型配置，粗调每级延时均值约360ps，精调每级延时均值约100ps +```c +typedef enum +{ + FIOPAD_DELAY_NONE = 0, + FIOPAD_DELAY_1, + FIOPAD_DELAY_2, + FIOPAD_DELAY_3, + FIOPAD_DELAY_4, + FIOPAD_DELAY_5, + FIOPAD_DELAY_6, + FIOPAD_DELAY_7, + + FIOPAD_NUM_OF_DELAY +} FIOPadDelay;/* Pin delay level configuration */ + +``` + +### 5.2 错误码定义 +- FIOPAD_SUCCESS 执行成功 +- FIOPAD_INVAL_PARAM 参数无效 +- FIOPAD_NOT_READY 驱动未初始化 +- FIOPAD_NOT_SUPPORT 驱动不支持 + +### 5.3. 用户API接口 + +#### FIOPadLookupConfig + +- 获取fiopad控制器默认配置 + +```c +const FIOPadConfig *FIOPadLookupConfig(u32 instance_id); +``` + +Note: + +- 获取默认配置参数，包括基地址等 + +Input: + +- {u32} instance_id，iopad控制器id号 + +Return: + +- {const FIOPadConfig *} iopad默认配置，返回NULL如果找不到默认配置 + +#### FIOPadCfgInitialize + +- 初始化fiopad控制器, 使之可以使用 + +```c +FError FIOPadCfgInitialize(FIOPadCtrl *instance_p, const FIOPadConfig *input_config_p); +``` + +Note: + +- 输入配置通过FIOPadLookupConfig获取，用户按照需要修改后传入此函数 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {FIOPadConfig} *input_config_p，iopad用户输入配置 + +Return: + +- {FError} 驱动初始化的错误码信息，FIOPAD_SUCCESS 表示初始化成功，其它返回值表示初始化失败 + +#### FIOPadGetFunc + +- 获取iopad pin当前复用功能 + +```c +FIOPadFunc FIOPadGetFunc(FIOPadCtrl *instance_p, const u32 pin_reg_off); +``` + +Note: + +- 获取iopad pin当前复用功能 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 + +Return: + +- {FIOPadFunc} iopad pin当前复用功能 + +#### FIOPadSetFunc + +- 设置iopad pin复用功能 + +```c +FError FIOPadSetFunc(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadFunc func); +``` + +Note: + +- 设置iopad pin复用功能 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 +- {FIOPadFunc} func, 具体复用功能 + +Return: + +- {FError} 驱动初始化的错误码信息，FIOPAD_SUCCESS 表示初始化成功，其它返回值表示初始化失败 + +#### FIOPadGetPull + +- 获取iopad pin当前上下拉配置 + +```c +FIOPadPull FIOPadGetPull(FIOPadCtrl *instance_p, const u32 pin_reg_off); +``` + +Note: + +- 获取iopad pin当前上下拉配置 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 + +Return: + +- {FIOPadFunc} iopad pin当前上下拉配置 + +#### FIOPadSetPull + +- 设置iopad pin上下拉 + +```c +FError FIOPadSetPull(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadPull pull); +``` + +Note: + +- 设置iopad pin上下拉 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 +- {FIOPadPull} pull, 具体上下拉配置 + +Return: + +- {FError} 驱动初始化的错误码信息，FIOPAD_SUCCESS 表示初始化成功，其它返回值表示初始化失败 + +#### FIOPadGetDriver + +- 获取iopad pin当前驱动能力 + +```c +FIOPadDrive FIOPadGetDriver(FIOPadCtrl *instance_p, const u32 pin_reg_off); +``` + +Note: + +- 获取iopad pin当前驱动能力 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 + +Return: + +- {FIOPadDrive} iopad pin当前驱动能力 + +#### FIOPadSetDriver + +- 设置iopad pin驱动能力 + +```c +FError FIOPadSetDriver(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDrive drive); +``` + +Note: + +- 设置iopad pin驱动能力 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 +- {FIOPadDrive} Driver, 具体驱动能力参数 + +Return: + +- {FError} 驱动初始化的错误码信息，FIOPAD_SUCCESS 表示初始化成功，其它返回值表示初始化失败 + +#### FIOPadSetConfig + +- 设置iopad pin复用功能，上下拉配置，驱动能力 + +```c +FError FIOPadSetConfig(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadFunc func, FIOPadPull pull, FIOPadDrive drive); +``` + +Note: + +- 设置iopad pin复用功能，上下拉配置，驱动能力，此接口一次性设置三种配置 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 +- {FIOPadFunc} func, 具体复用功能 +- {FIOPadPull} pull, 具体上下拉配置 +- {FIOPadDrive} Driver, 具体驱动能力参数 + +Return: + +- {FError} 驱动初始化的错误码信息，FIOPAD_SUCCESS 表示初始化成功，其它返回值表示初始化失败 + +#### FIOPadGetConfig + +- 获取iopad pin复用功能，上下拉配置，驱动能力 + +```c +FError FIOPadGetConfig(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadFunc *func, FIOPadPull *pull, FIOPadDrive *drive) +``` + +Note: + +- 胡去哦去iopad pin复用功能，上下拉配置，驱动能力，此接口一次性获取三种配置 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 +- {FIOPadFunc} *func, 具体复用功能 +- {FIOPadPull} *pull, 具体上下拉配置 +- {FIOPadDrive} *Driver, 具体驱动能力参数 + +Return: + +- {FError} 驱动初始化的错误码信息，FIOPAD_SUCCESS 表示初始化成功，其它返回值表示初始化失败 + +#### FIOPadGetDelay + +- 获取iopad pin当前延迟相关配置 + +```c +FIOPadDelay FIOPadGetDelay(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDelayDir dir, FIOPadDelayType type); +``` + +Note: + +- 获取iopad pin当前延迟相关配置 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 +- {FIOPadDelayDir} dir，延迟配置方向 +- {FIOPadDelayType} type，延迟配置类型 + +Return: + +- {FIOPadDelay} iopad pin在具体方向和类型下延迟的具体挡位 + +#### FIOPadSetDelay + +- 设置iopad pin延迟挡位 + +```c +FError FIOPadSetDelay(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDelayDir dir, FIOPadDelayType type, FIOPadDelay delay); +``` + +Note: + +- 设置iopad pin延迟在具体方向和类型下的挡位 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 +- {FIOPadDelayDir} dir，延迟配置方向 +- {FIOPadDelayType} type，延迟配置类型 +- {FIOPadDelay} delay，要设置的延迟具体值 + +Return: + +- {FError} 驱动初始化的错误码信息，FIOPAD_SUCCESS 表示初始化成功，其它返回值表示初始化失败 + +#### FIOPadSetDelayEn + +- 设置iopad pin延迟使能 + +```c +FError FIOPadSetDelayEn(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDelayDir dir, boolean enable); +``` + +Note: + +- 设置iopad pin在具体方向和类型下的延迟使能 + +Input: + +- {FIOPadCtrl} *instance_p，iopad驱动控制数据 +- {u32} pin_reg_off，对应pin地址偏移量 +- {FIOPadDelayDir} dir，延迟配置方向 +- {FIOPadDelayType} type，延迟配置类型 +- {boolean}enable，ture 使能;false 去使能 + +Return: + +- {FError} 驱动初始化的错误码信息，FIOPAD_SUCCESS 表示初始化成功，其它返回值表示初始化失败 + +#### FIOPadDeInitialize + +```c +FError FIOPadDeInitialize(FIOPadCtrl *instance_p) +``` + +Note: + +- 去初始化FIOPAD控制器实例 + +Input: + +- {FIOPadCtrl}instance_p, FIOPAD控制器实例 + +Return: + +- {FError} 驱动初始化的错误码信息，FIOPAD_SUCCESS 表示初始化成功，其它返回值表示初始化失败 \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fmedia.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fmedia.md index 20c8943ecf0..ac4777e7881 100644 --- a/bsp/phytium/libraries/standalone/doc/reference/driver/fmedia.md +++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fmedia.md @@ -52,20 +52,19 @@ ├── fdc_hw.h ├── fdc_g.c ├── fdc_common_hw.c -├── fdc_common_hw.c +├── fdc_common_hw.h ├── fdp.c ├── fdp.h ├── fdp_static.c ├── fdp_phy.c ├── fdp_phy.h -├── fdp_hq.c +├── fdp_hw.c ├── fdp_hw.h ├── fdp_g.c ├── fdp_aux.c ├── fdp_aux.h ├── fdcdp.c ├── fdcdp.h -├── fdcdp_param.c ├── fdcdp_intr.c ├── fdcdp_multi_display.c ├── fdcdp_multi_display.h @@ -86,19 +85,14 @@ typedef struct FDcCtrl dc_instance_p[FDCDP_INSTANCE_NUM]; /* fdp instace object */ FDpCtrl dp_instance_p[FDCDP_INSTANCE_NUM]; - /* user config */ - /* resolution */ - /* color depth */ - FDcDpDisplaySetting display_setting[FDCDP_DISPLAY_ID_MAX_NUM]; - /* gamma parameter */ - /* .... */ - /* uintptr fb_p[FDCDP_INSTANCE_NUM];*/ - u32 is_ready; /* Device is ininitialized and ready*/ + /* uintptr fb_config[FDCDP_INSTANCE_NUM];*/ + uintptr fb_config[FDCDP_INSTANCE_NUM]; + /*the intr config of dcdp*/ FMediaIntrConfig intr_event[FDCDP_INTR_MAX_NUM]; - - void *args; + /*connect status ,1 :connected,0:disconnected*/ u32 connect_flg[FDCDP_INSTANCE_NUM]; - u32 connect_changed_flg[FDCDP_INSTANCE_NUM]; + /* Device is ininitialized and ready*/ + u32 is_ready; } FDcDp; 其中FdcPrivateParams结构体为dc模块相关变量，包含有时序，frambuffer，pannel,gamma,dither,cursor等等；FdpPrivateParams结构体为dp模块相关变量，包括有时序，传输参数，phy等等。 @@ -106,15 +100,16 @@ typedef struct dc 相关结构体定义 typedef struct { - FDcDtdTable dtd_table; - FDcDisplayVHTimmingConfig timming_config; - FDcDisplayFramebuffer framebuffer; - FDcDisplayPanel panel; - FDcDisplayGamma gamma; - FDcDisplayDither dither; - FDcDisplayDpMode dp_mode; - FDcDisplayVideoMode video_mode; - FDcDisplayCursor cursor; + FDcDtdTable dtd_table; /*the table of dtd params*/ + FDcSyncParameter sync_parameter[FDC_GOP_MAX_MODENUM]; + FDcDisplayFramebuffer framebuffer; + FDcDisplayPanel panel; + FDcDisplayGamma gamma; + FDcDisplayDither dither; + FDcDisplayDpMode dp_mode; + FDcDisplayVideoMode video_mode; /*the params of video*/ + FDcDisplayCursor cursor; + FDcDisplaySetting display_setting[FDC_DISPLAY_ID_MAX_NUM]; } FDcCurrentConfig; typedef struct @@ -123,14 +118,13 @@ typedef struct uintptr dcch_baseaddr; /* DC channel register address*/ uintptr dcctrl_baseaddr; /* DC control register address */ u32 irq_num; /* Device intrrupt id */ - } FDcConfig; typedef struct { FDcCurrentConfig fdc_currentconfig; FDcConfig config; - u32 multimode; /* The display mode of the device , including clone, horizontal and vertical display*/ + u32 multi_mode; /* The display mode of the device , including clone, horizontal and vertical display*/ } FDcCtrl; @@ -147,9 +141,9 @@ typedef struct FDpStatus status; u8 down_spread_enable; -#define dtd_list_max 4 +#define DTD_MAX 4 /* edid 缓冲数据 */ - FDpDtdTable dtd_table[dtd_list_max]; /* the max dtd num is 4 */ + FDpDtdTable dtd_table[DTD_MAX]; /* the max dtd num is 4 */ } FDpCurrentConfig; @@ -254,7 +248,7 @@ FDpConfig * :dp静态默认配置 ### 2. FDcDpSetBasicParam ``` -FError FDcDpSetBasicParam(FDcDp *instance_p, u32 channel_num, u32 mode_id); +FError FDcDpSetBasicParam(FDcDp *instance_p, u32 mode_id, u32 color_depth, u32 refresh_rate); ``` #### 介绍 - 根据传入配置，初始化MEDIA驱动实例，设置基本参数 @@ -263,6 +257,8 @@ FError FDcDpSetBasicParam(FDcDp *instance_p, u32 channel_num, u32 mode_id); - FDcDp *instance_p FDcDp 控制器实例的指针 - u32 channel_num DP通道号 - u32 mode_id sync时序模式 +- u32 color_depth 色深 +-u32 refresh_rate 刷新率 #### 返回 - FError :FMEDIA_DP_SUCCESS 为初始成功 @@ -288,8 +284,7 @@ FError FDcDpInitial(FDcDp *instance_p, u32 channel_num, u32 mode_id, u32 multi_m ### 4. FDcDpRegisterHandler ``` -void FDcDpRegisterHandler(FDcDp *instance_p, FMediaIntrConfig *intr_event_p) - +void FDcDpRegisterHandler(FDcDp *instance_p, FDcDpIntrEventType type,FMediaIntrHandler handler,void *param) ``` #### 介绍 @@ -297,7 +292,9 @@ void FDcDpRegisterHandler(FDcDp *instance_p, FMediaIntrConfig *intr_event_p) #### 参数 - FDcDp *instance_p FDcDp 控制器实例的指针 -- FMediaIntrConfig event_p 中断事件参数 +- FDcDpIntrEventType type 中断事件 +- FMediaIntrHandler 中断事件响应函数 +- void *param 回调函数参数 ### 5. FDcDpInterruptHandler @@ -319,7 +316,7 @@ void *irq_args 回调结构体指针 ### 6. FDcDpIrqEnable ``` -void FDcDpIrqEnable(FDcDp *instance_p, FMediaIntrConfigintr_event_p); +void FDcDpIrqEnable(FDcDp *instance_p,u32 index, FDcDpIntrEventType intr_event_p); ``` #### 介绍 @@ -328,6 +325,7 @@ void FDcDpIrqEnable(FDcDp *instance_p, FMediaIntrConfigintr_event_p); #### 参数 ``` FDcDp *instance_p dcdp驱动实例 +u32 index 通道序号 FMediaIntrConfig intr_event_p 中断类型 ``` #### 返回 @@ -335,8 +333,8 @@ FMediaIntrConfig intr_event_p 中断类型 ### 7. FDcDpMultiDisplayFrameBufferSet -``` -FError FDcDpMultiDisplayFrameBufferSet(FDcDp *instance_p, u32 channel_num, u32 multi_mode); +disp_parm *FDcDpMultiDisplayFrameBufferSet(u32 channel, u32 width,u32 height,u32 color_depth,u32 multi_mode); + ``` #### 介绍 @@ -344,26 +342,13 @@ FError FDcDpMultiDisplayFrameBufferSet(FDcDp *instance_p, u32 channel_num, u32 m #### 参数 ``` -FDcDp *instance_p dcdp驱动实例 -u32 channel_num 通道号 -u32 multi_mode 单屏/多屏 +u32 channel 通道号 +u32 width 宽度 +u32 height 高度 +u32 color_depth 色深 +u32 multi_mode 多频模式 ``` #### 返回 -- FMEDIA_DP_SUCCESS - -### 8. FDcDpGetFramebuffer - -``` -FDcDpFrameBuffer *FDcDpGetFramebuffer(FDcDp *instance_p); -``` +- &disp_parm -#### 介绍 --提供framebuffer信息对外接口 -#### 参数 -``` -FDcDp *instance_p dcdp驱动实例 -``` -#### 返回 -- &framebuffer_config -frambuffer信息 diff --git a/bsp/phytium/libraries/standalone/doc/reference/driver/fxmac.md b/bsp/phytium/libraries/standalone/doc/reference/driver/fxmac.md index 4ce27297f61..1c626dc5a48 100644 --- a/bsp/phytium/libraries/standalone/doc/reference/driver/fxmac.md +++ b/bsp/phytium/libraries/standalone/doc/reference/driver/fxmac.md @@ -20,6 +20,7 @@ * Ver Who Date Changes * ----- ------ -------- -------------------------------------- --> + # FXMAC 驱动程序 ## 1. 概述 @@ -27,6 +28,7 @@ 以太网控制器（XMAC）的主要功能是在兼容 IEEE802.3 standard 标准的以太网中发送和接收数据，当前支持 SGMII/RGMII 的 PHY 接口 XMAC 接口特点包括 + - 支持速率 1000Mbps/100Mbps/10Mbps - 支持 Reduced Gigabit Media Independent Interface (RGMII) - 支持 SGMII Serial Gigabit Media-Independent Interface （SGMII） @@ -60,6 +62,7 @@ XMAC 驱动程序的源文件包括， ``` - 其中fxmac.h/fxmac.c 为开发者提供以下功能： + 1. mac 控制器实例初始化 2. 设置每个控制器实例中4个mac地址的接口 3. 设置每个控制器实例中4个mac匹配地址的接口 @@ -67,12 +70,11 @@ XMAC 驱动程序的源文件包括， 5. 中断相关接口 - 其中fxmac_bdring.h/fxmac_bdring.c 为开发者提供了以下功能： -1. 创建dma 环形队列 -2. 环形队列数据拷贝 -3. 环形队列描述符分配 -4. 环形队列描述符释放 - +1. 创建dma 环形队列 +2. 环形队列数据拷贝 +3. 环形队列描述符分配 +4. 环形队列描述符释放 ## 4 应用示例 @@ -89,6 +91,7 @@ XMAC 驱动程序的源文件包括， ### 5.1. 用户数据结构 - FXMAC 驱动配置数据 + ```c typedef struct { @@ -112,6 +115,7 @@ XMAC 驱动程序的源文件包括， ``` - FGMAC 驱动控制数据 + ```c typedef struct { @@ -180,6 +184,7 @@ XMAC 驱动程序的源文件包括， ``` - FGMAC DMA描述符表(链式)相关数据 + ```c typedef struct { @@ -190,6 +195,8 @@ typedef struct } FGmacRingDescData; ``` +- NOTE: + E2000 系列CPU 需要在参数表中增加 FXMAC_CLK_TYPE_0 ### 5.2 错误码定义 @@ -204,7 +211,6 @@ typedef struct - FXMAC_PHY_AUTO_AUTONEGOTIATION_FAILED : PHY autonegotiation is error - FXMAC_ERR_MAC_IS_PROCESSING : MAC controllers are enabled together. As a result, some operations cannot be mirrored - ### 5.3 初始化流程 1. FXmacLookupConfig 获取默认配置 @@ -215,7 +221,6 @@ typedef struct 6. 初始化dma 模块 7. 根据mac 默认配置启动mac 功能 - ### 5.4. 用户API接口 #### FXmacLookupConfig @@ -238,6 +243,7 @@ Input: Return: - {const FXmacConfig *}, 驱动默认配置 + #### FXmacCfgInitialize - 完成FGMAC驱动实例的初始化，使之可以使用 @@ -253,7 +259,6 @@ Note: Input: - {FXmac} *instance_p MAC 控制器实例指针 - - {FXmacConfig} *cofig_p 控制器驱动配置数据 Return: @@ -269,9 +274,11 @@ void FXmacInitInterface(FXmac *instance_p) ``` Note: + - 此函数一般用于 PHY 芯片协商完成之后被调用，与PHY配置进行适配 Input: + - {FXmac} *instance_p MAC 控制器实例指针 #### FXmacGetMacAddress @@ -288,8 +295,8 @@ Input : - {u8} index MAC(0-3)地址的索引 Output : -- {u8} *address_ptr 是指向缓冲区的指针当前MAC地址将被复制。 +- {u8} *address_ptr 是指向缓冲区的指针当前MAC地址将被复制。 #### FXmacSetMacAddress @@ -318,14 +325,17 @@ FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num) ``` Note: + - 必须在mac 控制器关闭的情况被调用 Input: + - {FGmac} *instance_p MAC 控制器实例指针 -- {u32} options 是要设置的选项。 选项参数位于 fxmac.h 中的 FXMAC_****_OPTION +- {u32} options 是要设置的选项。 选项参数位于 fxmac.h 中的 FXMAC_****_OPTION - {u32} queue_num mac控制器中队列的选项，仅在 FXMAC_JUMBO_ENABLE_OPTION 配置时被使用 Return: + - {FError} FT_SUCCESS 设置成功 #### FXmacClearOptions @@ -337,14 +347,17 @@ FError FXmacClearOptions(FXmac *instance_p, u32 options, u32 queue_num) ``` Note: + - 必须在mac 控制器关闭的情况被调用 Input: + - {FGmac} *instance_p MAC 控制器实例指针 -- {u32} options 是要设置的选项。 选项参数位于 fxmac.h 中的 FXMAC_****_OPTION +- {u32} options 是要设置的选项。 选项参数位于 fxmac.h 中的 FXMAC_****_OPTION - {u32} queue_num mac控制器中队列的选项，仅在 FXMAC_JUMBO_ENABLE_OPTION 配置时被使用 Return: + - {FError} FT_SUCCESS 清除成功 #### FXmacStart @@ -357,14 +370,13 @@ void FXmacStart(FXmac *instance_p) note: -- 根据 network_default_config 中的 FXMAC_TRANSMIT_ENABLE_OPTION 与 -FXMAC_RECEIVER_ENABLE_OPTION ，决定是否开启控制器的接收与发送功能。并且默认开启接收与发送相关中断 +- 根据 network_default_config 中的 FXMAC_TRANSMIT_ENABLE_OPTION 与 + FXMAC_RECEIVER_ENABLE_OPTION ，决定是否开启控制器的接收与发送功能。并且默认开启接收与发送相关中断 Input: - {FGmac} *instance_p MAC 控制器实例指针 - #### FXmacStop - 关闭以太网控制器 @@ -374,13 +386,13 @@ void FXmacStop(FXmac *instance_p) ``` note: + - 关闭所有中断，关闭接收与发送功能 Input: - {FGmac} *instance_p MAC 控制器实例指针 - #### FXmacSetQueuePtr - 设置mac 控制器中接收/发送缓冲区 的描述符环形队列的首地址 @@ -391,6 +403,7 @@ void FXmacSetQueuePtr(FXmac *instance_p, uintptr queue_p, u8 queue_num, ``` Note: + - 描述符环形队列的首地址按照128bit 对其 Input: @@ -400,7 +413,6 @@ Input: - {u8} queue_num 缓冲队列索引 - {u32} direction 当为 FXMAC_SEND 表示方向为发送，当为 FXMAC_RECV 表示方向为接收 - #### FXmacPhyWrite - 将数据写入指定的PHY寄存器。 @@ -410,20 +422,21 @@ FError FXmacPhyWrite(FXmac *instance_p, u32 phy_address, u32 register_num, u16 phy_data) ``` -Note: -- 这个函数不是线程安全的。 用户必须提供互斥的如果有多个线程可以调用该函数，则访问该函数。 +Note: + +- 这个函数不是线程安全的。 用户必须提供互斥的如果有多个线程可以调用该函数，则访问该函数。 Input: + - {FXmac} *instance_p MAC 控制器实例指针 - {u32} phy_address 要写入的PHY的地址 -- {u32} register_num 要写入的PHY的地址，特定PHY寄存器的寄存器号0-31 +- {u32} register_num 要写入的PHY的地址，特定PHY寄存器的寄存器号0-31 - {u16} phy_data 需要写入对应PHY 芯片中 对应register_num 的参数 Return: - {FError} FT_SUCCESS PHY 写入成功 - #### FXmacPhyRead - 指定PHY 芯片中对应的寄存器号，读出其中对应的参数 @@ -435,21 +448,22 @@ FError FXmacPhyRead(FXmac *instance_p, u32 phy_address, Note: -- 这个函数不是线程安全的。 用户必须提供互斥的如果有多个线程可以调用该函数，则访问该函数。 +- 这个函数不是线程安全的。 用户必须提供互斥的如果有多个线程可以调用该函数，则访问该函数。 Input: + - {FXmac} *instance_p MAC 控制器实例指针 - {u32} phy_address 要写入的PHY的地址 -- {u32} register_num 要写入的PHY的地址，特定PHY寄存器的寄存器号0-31 +- {u32} register_num 要写入的PHY的地址，特定PHY寄存器的寄存器号0-31 Output: + - {u16} *phydat_aptr 需要读出对应PHY 芯片中 对应register_num中值的指针 - + Return: - {FError} FT_SUCCESS PHY 读入成功 - #### FXmacPhyInit - 初始化PHY 芯片 ，首先检查出当前已连接的PHY 芯片地址，然后根据协商方式，确定 @@ -459,14 +473,15 @@ FError FXmacPhyInit(FXmac *instance_p, u32 speed,u32 duplex_mode, u32 autonegoti ``` Input: + - {FXmac} *instance_p MAC 控制器实例指针 - {u32} speed 需要设置的速度 - {u32} duplex_mode 双工模式配置，1为全双工，0 为半双工 - {u32} autonegotiation_en 为1 时，PHY 会进行自协商操作。为0时 ，将根据配置项进行协商 Return: -- FError FT_SUCCESS 初始化成功 +- FError FT_SUCCESS 初始化成功 #### FXmacSelectClk @@ -477,8 +492,8 @@ void FXmacSelectClk(FXmac *instance_p ) ``` Input: -- {FXmac} *instance_p MAC 控制器实例指针 +- {FXmac} *instance_p MAC 控制器实例指针 #### FXmacSetHandler @@ -489,8 +504,8 @@ FError FXmacSetHandler(FXmac *instance_p, u32 handler_type, void *func_pointer, ``` Input: + - {FXmac} *instance_p MAC 控制器实例指针 -- {u32} handler_type 指示中断处理程序类型 ,具体参数参考 FXMAC_HANDLER_*** -- {void } *func_pointer 回调函数接口 +- {u32} handler_type 指示中断处理程序类型 ,具体参数参考 FXMAC_HANDLER_*** +- {void } *func_pointer 回调函数接口 - {void } *call_back_ref 回调函数的传入参数 - diff --git a/bsp/phytium/libraries/standalone/doc/reference/sdk/flwip_port.md b/bsp/phytium/libraries/standalone/doc/reference/sdk/flwip_port.md index 0c109e62c19..c358fc95c50 100644 --- a/bsp/phytium/libraries/standalone/doc/reference/sdk/flwip_port.md +++ b/bsp/phytium/libraries/standalone/doc/reference/sdk/flwip_port.md @@ -15,6 +15,8 @@ Lwip Port为开发者提供了一系列接口，驱动开发者在完成GMAC/XMA 6. 管理mac 控制器的状态（phy link status） 7. 管理lwip 中link up/down 状态 8. 提供多网卡检索功能 +9. 提供巨帧模式使能 +10.提供轮询模式接收数据包使能 相关源文件为： ``` @@ -57,6 +59,7 @@ typedef struct enum lwip_port_link_status (*eth_detect)(struct netif *netif); void (*eth_deinit)(struct netif *netif); void (*eth_start)(struct netif *netif); + void (*eth_poll)(struct netif *netif); } LwipPortOps; /* lwip port 网卡注册函数*/ struct LwipPort { @@ -180,3 +183,23 @@ Return: - 无 + +#### LwipEthProcessLoop + +- 网卡接收数据包底层处理 + +```c +void LwipEthProcessLoop(struct netif *netif); +``` + +Note: + +- 在main函数中循环调用，轮询处理到来的网络数据包 + +Input: + +- {struct netif} *netif 网卡对象 + +Return: + +- 无 \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/doc/reference/usr/how_to_use.md b/bsp/phytium/libraries/standalone/doc/reference/usr/how_to_use.md new file mode 100644 index 00000000000..95ee5caee77 --- /dev/null +++ b/bsp/phytium/libraries/standalone/doc/reference/usr/how_to_use.md @@ -0,0 +1,199 @@ +# 工程编译构建软件使用文档 + +## 一、概述 + +本节例程主要向开发者介绍如何利用SDK 自带脚本与构建工具一步一步完成工程的搭建 + +## 二、单核工程构建 + +### 1. 编写makefile文件 + +在工程目录下创建一个新的 `makefile`文件，并按照下列步骤进行编辑： + +- 设置 `PROJECT_DIR`变量，该变量应指向当前工程的路径,需要使用绝对路径。 +- 设置 `SDK_DIR`变量，该变量用于指定使用的sdk的路径，如需更换sdk，只需修改此变量，需要使用绝对路径。 +- 设置 `USER_CSRC`变量，该变量应包含开发者需要添加并且参与编译的C语言源代码的名称，应使用相对于 `PROJECT_DIR`的相对路径名。 +- 设置 `USER_CXXSRC`变量，该变量应包含开发者需要添加并且参与编译的C++语言源代码的名称，应使用相对于 `PROJECT_DIR`的相对路径名。 +- 设置 `USER_ASRC`变量，该变量应包含开发者需要添加并且参与编译的汇编语言源代码的名称，应使用相对于 `PROJECT_DIR`的相对路径名。 +- 设置 `EXTEND_CSRC`变量，该变量应包含开发者需要添加并且参与编译的C语言源代码的名称，该变量为外部扩展的源代码，请使用绝对地址。 +- 设置 `EXTEND_CXXSRC`变量，该变量应包含开发者需要添加并且参与编译的C++语言源代码的名称，该变量为外部扩展的源代码，请使用绝对地址。 +- 设置 `EXTEND_ASRC`变量，该变量应包含开发者需要添加并且参与编译的汇编语言源代码的名称，该变量为外部扩展的源代码，请使用绝对地址。 +- 设置 `USER_INCLUDE`变量，该变量应包含开发者需要引用的自定义头文件的绝对路径。 +- 引用 `include $(SDK_DIR)/tools/build/makeall.mk`。 + +```makefile +PROJECT_DIR = $(CURDIR) +SDK_DIR = $(CURDIR)/../../../.. + + +USER_CSRC := main.c +USER_CSRC += $(wildcard src/*.c) +USER_CSRC += $(wildcard ../common/*.c) + +USER_ASRC := +USER_CXXSRC := + +USER_INCLUDE := $(PROJECT_DIR) \ + $(PROJECT_DIR)/inc \ + $(PROJECT_DIR)/../common + + +include $(SDK_DIR)/tools/build/makeall.mk +``` + +### 2. 编写kconfig文件 + +在工程目录下创建一个新的 `kconfig`文件，并按照下列步骤进行编辑： + +- 添加一个顶级菜单 `mainmenu`。 +- 添加一个kconfig配置项的依赖 `source "$(SDK_DIR)/standalone.kconfig"`。 + +```c +mainmenu "Phytium Baremetal Configuration" + +source "$(SDK_DIR)/standalone.kconfig" +``` + +### 3. 添加sdkconfig文件 + +在工程目录下添加一个新的、空白的 `sdkconfig`文件。 + +![1686017484866](image/how_to_use/1686017484866.png) + + 图1. 添加 sdkconfig + +### 4. 配置工程 + +运行 `make menuconfig`命令，按照下列步骤进行配置： + +- 在 `Arch Configuration`中选择目标架构，例如 `armv8`。 +- 在 `Arm architecture configuration`中选择对应的执行状态。 +- 在 `Soc configuration`中选择对应soc，并选择调试uart。 +- 在 `Sdk common configuration`中选择 `Debug log level`，确定调试打印的等级。 +- 在 `Drivers configuration`中选择需要参与编译的外设。 +- 在 `Third-party configuration`中选择第三方仓库的配置。 +- 在 `User configuration`设置board和project的命名，这两个命名将会影响kconfig备份以及镜像输出的命名。 +- 在 `Build setup`中的 `Linker Options`中选择”Use sdk default linker script“，并根据实际情况配置。 + +![1686017538445](image/how_to_use/1686017538445.png) + + 图2. make menuconfig 效果图 + +![1686019401543](image/how_to_use/1686019401543.png) + + 图3. 链接脚本配置效果图 + +### 5. 编译和调试 + +完成基础配置后，可以使用以下命令对代码进行编译和调试： + +- 使用 `make + 'table'`按键可以查看支持哪些目标。 +- 使用 `make backup_kconfig`备份已经完成的配置项。 +- 使用 `make list_kconfig`查看当前工程支持哪些已经备份好的配置项，kconfig配置项的命名方式为 `soc名称_执行状态_板子命名_项目命名`。 +- 使用 `make load_kconfig l=`加载已经备份好的配置项。 +- 使用 `make xxx.a`，单独编译某个特定的模块，例如 `libarch.a`。 +- 使用 `make`指令，完整编译一个工程。 + +![1686017723541](image/how_to_use/1686017723541.png) + + 图4. make +'table' 效果图 + +![1686017806288](image/how_to_use/1686017806288.png) + + 图5. make`backup_kconfig` 备份现有配置效果图 + +### 6. 编译调试 + +当编译过程出现问题时，可以使用以下方式进行调试： + +- 使用 `make `libuser_debug，对用户模块进行预编译。 +- 使用 `make xxx_info`，对模块编译条件进行打印。 + +![1686018164493](image/how_to_use/1686018164493.png) + +![1686018209933](image/how_to_use/1686018209933.png) + + 图6. make `libuser_debug` 对用户的代码进行预编译 + +## 三、多核工程构建 + +若需要构建一个多核工程，可以按照以下的步骤进行： + +### 1. 编写makefile文件 + +在一个独立的目录下创建一个新的 `makefile`文件，并进行如下配置： + +- 设置 `PROJECT_DIR`变量，该变量应指向当前工程的路径,需要使用绝对路径。 +- 设置 `SDK_DIR`变量，该变量用于指定当前引导程序会使用的sdk的路径，如需更换sdk，只需修改此变量，需要使用绝对路径。 +- 设置 `AMP_PATH`变量，该变量表示需要参与多核构建的工程路径 +- 引用 `include $(SDK_DIR)/tools/build/amp_makeall.mk`。 + +```makefile +PROJECT_DIR = $(CURDIR) + +SDK_DIR = $(CURDIR)/../../.. + + +AMP_PATH += $(PROJECT_DIR)/apu_running +AMP_PATH += $(PROJECT_DIR)/rpu_running + +include $(SDK_DIR)/tools/build/amp_makeall.mk + +USR_BOOT_DIR ?= /mnt/d/tftboot +``` + +如图5 所示，如果需要建立多核异构工程，可以按照图中的结构构建 + +![1686018381398](image/how_to_use/1686018381398.png) + +图5. 多核异构程序文件结构 + +### 2. 配置工程 + +多核工程会引入一个boot 程序会根据每个多核工程中配置信息自动将工程加载至指定的核心之上,多核工程的配置需要按照以下几个步骤进行： + + 1. 在每个参与构建的工程中，使用make menuconfig ，配置当前工程工作的核心位置，以及当前工程特定的链接加载地址 + +![1686019565525](image/how_to_use/1686019565525.png) + +图6. 镜像工作核心配置 + + 2. 在每个参与构建的工程中，使用make menuconfig ,将所有参与构建的工程的soc 内容进行统一 + +![1686019757548](image/how_to_use/1686019757548.png) + +图7. 镜像soc配置 + +3. 在每个参与构建的工程中，使用make menuconfig ,将所有参与构建的工程的cpu 架构 内容进行统一 + +![1686019830855](image/how_to_use/1686019830855.png) + +图8. 执行架构配置 + + 4. 在多核工程的根目录下通过,make menuconfig 配置boot 程序,要求与其他参与构建的工程在soc 与 cpu架构方面保持一致 + +### 3. 编译调试过程 + + 多核构建工具具备工程镜像检查功能,会对soc\cpu架构 和 链接加载地址方面的问题进行检查,本节将会从一些具体的问题现象上指导开发者,如何调整自己多核异构的方案 + +Q : 当出现下图问题时 + +![1686020115768](image/how_to_use/1686020115768.png) + +A: 此问题为soc 对应的执行状态不一致导致,其中rpu_runing 工程的执行状态为aarch32 ,需要将其与其他工程进行统一 + +Q: 当出现下图问题时 + +![1686020270939](image/how_to_use/1686020270939.png) + +A: 此问题的原因是 apu_runing 与 rpu_runing 的工程中加载地址存在重叠的情况,请调整两个工程,以达到合适的区间 + +Q: 当出现下图问题时 + +![1686020499979](image/how_to_use/1686020499979.png) + +A: 此问题的原因是,boot 的加载地址与其他工程的地址存在冲突,此时在多核的根目录下通过make menuconfig 指令重新调整boot 程序的链接地址，以保证链接地址能够在上图的范围之内。 + +# 四、结语 + +完成以上步骤后，即可成功构建单核或多核工程。如果在使用过程中遇到问题，可以查阅相关文档或者与我们的技术团队联系。 diff --git a/bsp/phytium/libraries/standalone/doc/reference/usr/image/how_to_use/1686017484866.png b/bsp/phytium/libraries/standalone/doc/reference/usr/image/how_to_use/1686017484866.png new file mode 100644 index 00000000000..9045d33c4a0 Binary files /dev/null and b/bsp/phytium/libraries/standalone/doc/reference/usr/image/how_to_use/1686017484866.png differ diff --git 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a/bsp/phytium/libraries/standalone/doc/reference/usr/usage.md +++ b/bsp/phytium/libraries/standalone/doc/reference/usr/usage.md @@ -243,6 +243,10 @@ fatload mmc 1:1 0x80100000 baremetal.bin dcache flush go 0x80100000 ``` +- 如果固件中没有 ```dcache flush```指令，可以在编译镜像时，将刷新cache的配置选择 + +![](../../fig/flush_cache.png) + - 输入下列命令，可以下电、上电启动，自动从 SD 卡介质中引导系统 > 使用 saveenv 前，需要找 FAE 确认 u-boot 版本是否支持 diff --git a/bsp/phytium/libraries/standalone/drivers/Kconfig b/bsp/phytium/libraries/standalone/drivers/Kconfig index d1b05305006..32a49bb7151 100644 --- a/bsp/phytium/libraries/standalone/drivers/Kconfig +++ b/bsp/phytium/libraries/standalone/drivers/Kconfig @@ -32,6 +32,17 @@ config USE_GIC source "$STANDALONE_DIR/drivers/gic/Kconfig" endif +config USE_IOPAD + bool + prompt "Use Iopad" + depends on TARGET_E2000 + help + Include Iopad + + if USE_IOPAD + source "$STANDALONE_DIR/drivers/iopad/Kconfig" + endif + config USE_SERIAL bool prompt "Use SERIAL" diff --git a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_intr.c b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_intr.c index 2f5c40c5464..cb14b494717 100644 --- a/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_intr.c +++ b/bsp/phytium/libraries/standalone/drivers/can/fcan/fcan_intr.c @@ -105,14 +105,14 @@ void FCanIntrHandler(s32 vector, void *args) if (irq_status & FCAN_INTR_RFIS_MASK) { FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_FIFOFULL); - FCAN_ERROR("rx_fifo is full!!!"); + FCAN_DEBUG("rx_fifo is full!!!"); /* disable rx fifo full interrupt */ FCAN_CLEARBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_RFIE_MASK); } if (irq_status & FCAN_INTR_TFIS_MASK) { FCAN_CALL_INTR_EVENT_HANDLDER(instance_p, FCAN_INTR_EVENT_FIFOEMPTY); - FCAN_ERROR("tx_fifo is empty!!!"); + FCAN_DEBUG("tx_fifo is empty!!!"); /* disable tx fifo empty interrupt */ FCAN_CLEARBIT(config_p->base_address, FCAN_INTR_OFFSET, FCAN_INTR_TFIE_MASK); } diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.c b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.c index 31fc660b65f..dbb79935c62 100644 --- a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.c +++ b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.c @@ -191,8 +191,7 @@ FError FDdmaAllocateChan(FDdma *const instance, FDdmaChan *const dma_chan, const return FDDMA_ERR_INVALID_DDR_ADDR; } - if ((FDDMA_MAX_TRANSFER_LEN < dma_chan_config->trans_len) || - (FDDMA_MIN_TRANSFER_LEN > dma_chan_config->trans_len) || + if ((FDDMA_MIN_TRANSFER_LEN > dma_chan_config->trans_len) || (0 != dma_chan_config->trans_len % FDDMA_MIN_TRANSFER_LEN)) { FDDMA_ERROR("Invalid transfer size %d bytes !!!", dma_chan_config->trans_len); diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.h b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.h index 5529a0c1e12..8b2ff53b5dc 100644 --- a/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.h +++ b/bsp/phytium/libraries/standalone/drivers/dma/fddma/fddma.h @@ -94,7 +94,6 @@ typedef struct uintptr ddr_addr; /* DMA channel DDR address, could be source or destination */ u32 dev_addr; /* DMA channel Perpherial, could be source or destination */ u32 trans_len; /* DMA channel transfer length */ -#define FDDMA_MAX_TRANSFER_LEN 64 /* max bytes in transfer */ #define FDDMA_MIN_TRANSFER_LEN 4 /* min bytes in transfer */ u32 timeout; /* timeout = 0 means no use DMA timeout */ } FDdmaChanConfig; /* DDMA channel instance */ diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.c b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.c index e5d256db219..e008cf083d7 100644 --- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.c +++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.c @@ -225,12 +225,12 @@ FError FGdmaAllocateChan(FGdma *const instance_p, FGdmaChan *const dma_chan, /* set xfer config */ reg_val = 0; - reg_val |= FGDMA_CHX_XFER_CFG_AR_LEN_SET(FGDMA_MAX_BURST_LEN) | /* burst length configed as max 8, which adapted when trans bytes less than 8 */ - FGDMA_CHX_XFER_CFG_AR_SIZE_SET((u32)dma_chan->config.rd_align) | + reg_val |= FGDMA_CHX_XFER_CFG_AR_LEN_SET(FGDMA_BURST_LEN) | /* burst length configed as max 8, which adapted when trans bytes less than 8 */ + FGDMA_CHX_XFER_CFG_AR_SIZE_SET((u32)dma_chan->config.rd_size) | FGDMA_CHX_XFER_CFG_AR_BRUST_SET(FGDMA_INCR); /* mem to mem trans work in incr mode */ - reg_val |= FGDMA_CHX_XFER_CFG_AW_LEN_SET(FGDMA_MAX_BURST_LEN) | - FGDMA_CHX_XFER_CFG_AW_SIZE_SET((u32)dma_chan->config.wr_align) | + reg_val |= FGDMA_CHX_XFER_CFG_AW_LEN_SET(FGDMA_BURST_LEN) | + FGDMA_CHX_XFER_CFG_AW_SIZE_SET((u32)dma_chan->config.wr_size) | FGDMA_CHX_XFER_CFG_AW_BRUST_SET(FGDMA_INCR); /* mem to mem trans work in incr mode */ FGDMA_WRITEREG(base_addr, FGDMA_CHX_XFER_CFG_OFFSET(chan_idx), reg_val); FGDMA_INFO("xfer cfg: 0x%x", FGDMA_READREG(base_addr, FGDMA_CHX_XFER_CFG_OFFSET(chan_idx))); @@ -238,6 +238,12 @@ FError FGdmaAllocateChan(FGdma *const instance_p, FGdmaChan *const dma_chan, instance_p->chans[chan_idx] = dma_chan; dma_chan->gdma = instance_p; + if (dma_chan->config.wait_mode == FGDMA_WAIT_INTR) + { + /* enable channel interrupt */ + FGdmaChanIrqEnable(base_addr, chan_idx, FGDMA_CHX_INT_CTRL_TRANS_END_ENABLE); + } + return ret; } @@ -305,18 +311,18 @@ FError FGdmaDirectTransfer(FGdmaChan *const chan_p, uintptr src_addr, uintptr ds return FGDMA_ERR_NOT_INIT; } - if ((src_addr % FGDMA_GET_BURST_SIZE(chan_p->config.rd_align)) || - (dst_addr % FGDMA_GET_BURST_SIZE(chan_p->config.wr_align))) + if ((src_addr % FGDMA_GET_BURST_BYTE(chan_p->config.rd_size)) || + (dst_addr % FGDMA_GET_BURST_BYTE(chan_p->config.wr_size))) /* 报文传输的首地址需要与burst size所代表的单次burst传输的最大数据字节数对齐 */ { - FGDMA_ERROR("src addr 0x%x or dst addr 0x%x not aligned with %d bytes", - src_addr, dst_addr, FGDMA_ADDR_ALIGMENT); + FGDMA_ERROR("src addr 0x%x or dst addr 0x%x not aligned with burst size !!!", + src_addr, dst_addr); return FGDMA_ERR_INVALID_ADDR; } - if (0 != (data_len % chan_p->config.wr_align)) + if (0 != (data_len % FGDMA_GET_BURST_BYTE(chan_p->config.wr_size))) /* 报文传输的总数据量必须是burst size所代表的单次burst传输的最大数据字节数的整数倍 */ { - FGDMA_ERROR("data length %d must be N times of burst size %d !!!", - data_len, chan_p->config.wr_align); + FGDMA_ERROR("data length %d must be N times of burst size: %d bytes!!!", + data_len, FGDMA_GET_BURST_BYTE(chan_p->config.wr_size)); return FGDMA_ERR_INVALID_SIZE; } @@ -354,9 +360,6 @@ FError FGdmaDirectTransfer(FGdmaChan *const chan_p, uintptr src_addr, uintptr ds FGDMA_INFO("ts: 0x%x", FGDMA_READREG(base_addr, FGDMA_CHX_TS_OFFSET(chan_idx))); - /* enable channel interrupt */ - FGdmaChanIrqEnable(base_addr, chan_idx, FGDMA_CHX_INT_CTRL_TRANS_END_ENABLE); - /* enable channel and start transfer */ FGdmaChanEnable(base_addr, chan_idx); @@ -385,18 +388,18 @@ FError FGdmaAppendBDLEntry(FGdmaChan *const chan_p, uintptr src_addr, uintptr ds return FGDMA_ERR_BDL_NOT_ENOUGH; } - if ((0U != (dst_addr % FGDMA_GET_BURST_SIZE(chan_p->config.wr_align))) || - (0U != (src_addr % FGDMA_GET_BURST_SIZE(chan_p->config.rd_align)))) + if ((0U != (dst_addr % FGDMA_GET_BURST_BYTE(chan_p->config.wr_size))) || + (0U != (src_addr % FGDMA_GET_BURST_BYTE(chan_p->config.rd_size)))) /* 报文传输的首地址需要与burst size所代表的单次burst传输的最大数据字节数对齐 */ { FGDMA_ERROR("SRC addr 0x%x or DST addr 0x%x are not aligned with the %d transfer size", - src_addr, dst_addr, FGDMA_GET_BURST_SIZE(chan_p->config.wr_align)); + src_addr, dst_addr, FGDMA_GET_BURST_BYTE(chan_p->config.wr_size)); return FGDMA_ERR_INVALID_ADDR; } - if (0U != (data_len % chan_p->config.wr_align)) + if (0U != (data_len % FGDMA_GET_BURST_BYTE(chan_p->config.wr_size))) /* 报文传输的总数据量必须是burst size所代表的单次burst传输的最大数据字节数的整数倍 */ { FGDMA_ERROR("The data length %d must be N times the burst size %d !!!", - data_len, chan_p->config.wr_align); + data_len, FGDMA_GET_BURST_BYTE(chan_p->config.wr_size)); return FGDMA_ERR_INVALID_SIZE; } @@ -414,13 +417,13 @@ FError FGdmaAppendBDLEntry(FGdmaChan *const chan_p, uintptr src_addr, uintptr ds /* rd = src */ desc_entry->src_tc = FGDMA_SRC_TC_BDL_BURST_SET(FGDMA_INCR) | - FGDMA_SRC_TC_BDL_SIZE_SET((u32)chan_p->config.rd_align) | - FGDMA_SRC_TC_BDL_LEN_SET(FGDMA_MAX_BURST_LEN); + FGDMA_SRC_TC_BDL_SIZE_SET((u32)chan_p->config.rd_size) | + FGDMA_SRC_TC_BDL_LEN_SET(FGDMA_BURST_LEN); /* wr = dst */ desc_entry->dst_tc = FGDMA_DST_TC_BDL_BURST_SET(FGDMA_INCR) | - FGDMA_DST_TC_BDL_SIZE_SET((u32)chan_p->config.wr_align) | - FGDMA_DST_TC_BDL_LEN_SET(FGDMA_MAX_BURST_LEN); + FGDMA_DST_TC_BDL_SIZE_SET((u32)chan_p->config.wr_size) | + FGDMA_DST_TC_BDL_LEN_SET(FGDMA_BURST_LEN); desc_entry->total_bytes = data_len; desc_entry->ioc = 0U; @@ -488,9 +491,6 @@ FError FGdmaBDLTransfer(FGdmaChan *const chan_p) /* num of BDL entry */ FGDMA_WRITEREG(base_addr, FGDMA_CHX_LVI_OFFSET(chan_idx), FGDMA_CHX_LVI_SET(chan_p->config.valid_desc_num)); - /* enable channel interrupt */ - FGdmaChanIrqEnable(base_addr, chan_idx, FGDMA_CHX_INT_CTRL_TRANS_END_ENABLE); - /* enable channel and start transfer */ FGdmaChanEnable(base_addr, chan_idx); @@ -526,10 +526,8 @@ FError FGdmaStart(FGdma *const instance_p) reg_val |= FGDMA_CTL_OT_SET(FGDMA_OUTSTANDING); /* 设置传输outstanding数 */ reg_val |= FGDMA_CTL_ENABLE; /* 使能DMA传输 */ FGDMA_WRITEREG(base_addr, FGDMA_CTL_OFFSET, reg_val); - - - return FGDMA_SUCCESS; // 放到初始化 + return FGDMA_SUCCESS; //放到初始化 } /** diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.h b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.h index 8474ba88823..8f6c9655b3b 100644 --- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.h +++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma.h @@ -75,6 +75,12 @@ typedef enum FGDMA_OPER_BDL /* BDL操作模式 */ } FGdmaOperMode; /* 支持的操作模式 */ +typedef enum +{ + FGDMA_WAIT_INTR = 0, /* 中断模式 */ + FGDMA_WAIT_POLL /* 轮询模式 */ +} FGdmaWaitEnd; /* 支持的等待传输完成的模式 */ + typedef enum { FGDMA_BURST_SIZE_1_BYTE = 0, @@ -82,9 +88,10 @@ typedef enum FGDMA_BURST_SIZE_4_BYTE = 2, FGDMA_BURST_SIZE_8_BYTE = 3, FGDMA_BURST_SIZE_16_BYTE = 4 -} FGdmaBurstSize; /* 支持的读写请求size大小 */ +} FGdmaBurstSize; /* 所支持的读写请求burst size范围，其值本身是一个二次幂指数 + * 即，单次burst传输的最大数据字节数 = 2^burst size */ -#define FGDMA_GET_BURST_SIZE(brust_align) (1U << brust_align) +#define FGDMA_GET_BURST_BYTE(burst_size) (1U << burst_size) /* 获取burst size所代表的单次burst传输的最大数据字节数 */ typedef enum { @@ -105,7 +112,7 @@ typedef enum #define FGDMA_ERR_INVALID_SIZE FT_MAKE_ERRCODE(ErrModBsp, ErrGdma, 4) #define FGDMA_ERR_BDL_NOT_ENOUGH FT_MAKE_ERRCODE(ErrModBsp, ErrGdma, 5) -#define FGDMA_ADDR_ALIGMENT 128U /* 直接模式和BDL模式的地址需要按128位对齐 */ +#define FGDMA_ADDR_ALIGMENT 128U /* BDL链表的地址需要按128字节对齐 */ /**************************** Type Definitions *******************************/ typedef struct _FGdma FGdma; @@ -113,12 +120,12 @@ typedef struct _FGdmaChan FGdmaChan; typedef struct { - u32 instance_id; /* GDMA控制器ID */ - u32 irq_num[FGDMA_NUM_OF_CHAN]; /* GDMA控制器中断号 */ - u32 irq_prority; /* GDMA控制器中断优先级 */ - volatile uintptr_t base_addr; /* GDMA控制器基地址 */ - FGdmaOperPriority rd_qos; /* 读操作优先级 */ - FGdmaOperPriority wr_qos; /* 写操作优先级 */ + u32 instance_id; /* GDMA控制器ID */ + u32 irq_num[FGDMA_NUM_OF_CHAN]; /* GDMA控制器中断号 */ + u32 irq_prority; /* GDMA控制器中断优先级 */ + volatile uintptr_t base_addr; /* GDMA控制器基地址 */ + FGdmaOperPriority rd_qos; /* 读操作优先级 */ + FGdmaOperPriority wr_qos; /* 写操作优先级 */ u32 caps; /* driver capacity */ } FGdmaConfig; /* GDMA控制器配置 */ @@ -150,9 +157,10 @@ typedef struct FGdmaOperPriority rd_qos; /* DMA通道读Qos配置 */ FGdmaOperPriority wr_qos; /* DMA通道写Qos配置 */ FGdmaOperMode trans_mode; /* DMA通道的操作模式，直接模式或者BDL模式 */ + FGdmaWaitEnd wait_mode; /* 等待传输完成信号的模式，中断模式或轮询模式 */ /* Direct模式有效 */ - FGdmaBurstSize rd_align; /* DMA读请求的Burst对齐方式 */ - FGdmaBurstSize wr_align; /* DMA写请求的Burst对齐方式 */ + FGdmaBurstSize rd_size; /* DMA读请求的burst size */ + FGdmaBurstSize wr_size; /* DMA写请求的burst size */ /* BDL模式有效 */ boolean roll_back; /* 循环模式，TRUE: 当前BDL列表完成后，从第一个BDL项从新开始传输 */ FGdmaBdlDesc *descs; @@ -185,22 +193,24 @@ typedef struct _FGdma #define FGDMA_DEFAULT_DIRECT_CHAN_CONFIG(_chan_id)\ (FGdmaChanConfig){ \ .chan_id = (_chan_id),\ - .rd_align = FGDMA_BURST_SIZE_4_BYTE,\ - .wr_align = FGDMA_BURST_SIZE_4_BYTE,\ + .rd_size = FGDMA_BURST_SIZE_4_BYTE,\ + .wr_size = FGDMA_BURST_SIZE_4_BYTE,\ .rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\ .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\ .trans_mode = FGDMA_OPER_DIRECT,\ + .wait_mode = FGDMA_WAIT_INTR,\ .roll_back = FALSE\ } #define FGDMA_DEFAULT_BDL_CHAN_CONFIG(_chan_id, _bdl_descs, _bdl_desc_num)\ (FGdmaChanConfig){ \ .chan_id = (_chan_id),\ - .rd_align = FGDMA_BURST_SIZE_4_BYTE,\ - .wr_align = FGDMA_BURST_SIZE_4_BYTE,\ + .rd_size = FGDMA_BURST_SIZE_4_BYTE,\ + .wr_size = FGDMA_BURST_SIZE_4_BYTE,\ .rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\ .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL,\ .trans_mode = FGDMA_OPER_BDL,\ + .wait_mode = FGDMA_WAIT_INTR,\ .roll_back = FALSE,\ .descs = _bdl_descs,\ .total_desc_num = _bdl_desc_num,\ diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_g.c b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_g.c index fcd0dbc7f13..e8dca34d504 100644 --- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_g.c +++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_g.c @@ -71,7 +71,7 @@ const FGdmaConfig fgdma_cfg_tbl[FGDMA_INSTANCE_NUM] = .irq_prority = 0, .rd_qos = FGDMA_OPER_NONE_PRIORITY_POLL, .wr_qos = FGDMA_OPER_NONE_PRIORITY_POLL, - .caps = FGDMA0_CAPACITY + .caps = FGDMA0_CAPACITY | FGDMA_TRANS_NEED_RESET_MASK } }; diff --git a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_hw.h b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_hw.h index 6ab2ffc9faf..521294f48b7 100644 --- a/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_hw.h +++ b/bsp/phytium/libraries/standalone/drivers/dma/fgdma/fgdma_hw.h @@ -164,21 +164,21 @@ extern "C" /** @name FGDMA_CHX_XFER_CFG_OFFSET Register */ -#define FGDMA_CHX_XFER_CFG_AR_LEN_SET(len) SET_REG32_BITS((len), 31, 24) /* CHX 读请求Burst length 大小 */ -#define FGDMA_CHX_XFER_CFG_AR_SIZE_SET(size) SET_REG32_BITS((size), 22, 20) /* CHX 读请求Size 大小 ， 支持 1、2、8、16 Byte */ -#define FGDMA_CHX_XFER_CFG_AR_BRUST_SET(type) SET_REG32_BITS((type), 17, 16) /* CHX 读请求Brust 类型： 0：fix ，1：incr */ -#define FGDMA_CHX_XFER_CFG_AW_LEN_SET(len) SET_REG32_BITS((len), 15, 8) /* CHX 写请求Burst length 大小 */ -#define FGDMA_CHX_XFER_CFG_AW_SIZE_SET(size) SET_REG32_BITS((size), 6, 4) /* CHX 写请求Size 大小 ， 支持 1、2、8、16 Byte */ -#define FGDMA_CHX_XFER_CFG_AW_BRUST_SET(type) SET_REG32_BITS((type), 1, 0) /* CHX 写请求Brust 类型： 0：fix ，1：incr */ +#define FGDMA_CHX_XFER_CFG_AR_LEN_SET(len) SET_REG32_BITS((len), 31, 24) /* CHX 读请求 Burst length 大小 */ +#define FGDMA_CHX_XFER_CFG_AR_SIZE_SET(size) SET_REG32_BITS((size), 22, 20) /* CHX 读请求 Burst size 大小， 支持 1、2、8、16 Byte */ +#define FGDMA_CHX_XFER_CFG_AR_BRUST_SET(type) SET_REG32_BITS((type), 17, 16) /* CHX 读请求 Brust 类型： 0：fix ，1：incr */ +#define FGDMA_CHX_XFER_CFG_AW_LEN_SET(len) SET_REG32_BITS((len), 15, 8) /* CHX 写请求 Burst length 大小 */ +#define FGDMA_CHX_XFER_CFG_AW_SIZE_SET(size) SET_REG32_BITS((size), 6, 4) /* CHX 写请求 Burst size 大小， 支持 1、2、8、16 Byte */ +#define FGDMA_CHX_XFER_CFG_AW_BRUST_SET(type) SET_REG32_BITS((type), 1, 0) /* CHX 写请求 Brust 类型： 0：fix ，1：incr */ #define FGDMA_INCR 1U #define FGDMA_FIX 0U -#define FGDMA_MAX_BURST_LEN 8U +#define FGDMA_BURST_LEN 7U /* burst lenth = FGDMA_BURST_LEN + 1，写入寄存器的最大合法值为7，burst length最大值为8 */ /** @name FGDMA_CHX_LCP_OFFSET Register */ -#define FGDMA_CHX_LCP_GET(reg_val) GET_REG32_BITS((reg_val), 31, 0) /* 当前操作了多少个 BDL 列表 */ +#define FGDMA_CHX_LCP_GET(reg_val) GET_REG32_BITS((reg_val), 31, 0) /* 当前操作的BDL列表数 */ /** @name FGDMA_CHX_SECCTL_OFFSET Register */ diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.c index 4b03f2782dd..363937f44f1 100644 --- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.c +++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.c @@ -78,6 +78,8 @@ static void FXmacHighSpeedConfiguration(FXmac *instance_p,u32 speed) FXMAC_PRINT_I("FXMAC_GEM_HSMAC is %x \r\n ", reg_value); } +#if defined(FXMAC_CLK_TYPE_0) + /** * @name: FXmacSelectClk * @msg: Determine the driver clock configuration based on the media independent interface @@ -85,7 +87,7 @@ static void FXmacHighSpeedConfiguration(FXmac *instance_p,u32 speed) * @param {u32} speed interface speed * @return {*} */ -void FXmacSelectClkOld(FXmac *instance_p) +void FXmacSelectClk(FXmac *instance_p) { u32 reg_value; @@ -244,7 +246,7 @@ void FXmacSelectClkOld(FXmac *instance_p) FXmacHighSpeedConfiguration(instance_p,speed); } - +#else void FXmacSelectClk(FXmac *instance_p) { u32 reg_value; @@ -273,7 +275,7 @@ void FXmacSelectClk(FXmac *instance_p) FXmacHighSpeedConfiguration(instance_p,speed); } } - +#endif /** * Start the Ethernet controller as follows: @@ -310,26 +312,6 @@ void FXmacStart(FXmac *instance_p) FASSERT(instance_p != NULL); FASSERT(instance_p->is_ready == (u32)FT_COMPONENT_IS_READY); - /* Start DMA */ - /* When starting the DMA channels, both transmit and receive sides - * need an initialized BD list. - */ - - FASSERT(instance_p->rx_bd_queue.bdring.base_bd_addr != 0); - - reg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_RXQBASE_OFFSET); - reg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_TXQBASE_OFFSET); - - FXMAC_WRITEREG32(instance_p->config.base_address, - FXMAC_RXQBASE_OFFSET, - instance_p->rx_bd_queue.bdring.base_bd_addr); - - FXMAC_WRITEREG32(instance_p->config.base_address, - FXMAC_TXQBASE_OFFSET, - instance_p->tx_bd_queue.bdring.base_bd_addr); - - reg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_RXQBASE_OFFSET); - reg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_TXQBASE_OFFSET); /* clear any existed int status */ FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_ISR_OFFSET, @@ -366,7 +348,8 @@ void FXmacStart(FXmac *instance_p) FXMAC_NWCTRL_OFFSET)); /* Enable TX and RX interrupt */ - FXMAC_INT_ENABLE(instance_p, FXMAC_IXR_LINKCHANGE_MASK | FXMAC_IXR_TX_ERR_MASK | FXMAC_IXR_RX_ERR_MASK | FXMAC_IXR_RXCOMPL_MASK | FXMAC_IXR_TXCOMPL_MASK); + FXMAC_INT_ENABLE(instance_p, instance_p->mask); + /* Mark as started */ instance_p->is_started = FT_COMPONENT_IS_STARTED; @@ -623,11 +606,11 @@ static void FXmacReset(FXmac *instance_p) instance_p->moudle_id = (FXMAC_READREG32(instance_p->config.base_address, FXMAC_REVISION_REG_OFFSET) & FXMAC_IDENTIFICATION_MASK) >> 16; FXMAC_PRINT_I("instance_p->moudle_id is %d \r\n", instance_p->moudle_id); instance_p->max_mtu_size = FXMAC_MTU; - instance_p->max_frame_size = FXMAC_MTU + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE; + instance_p->max_frame_size = FXMAC_MAX_FRAME_SIZE; FXMAC_WRITEREG32(instance_p->config.base_address, FXMAC_NWCTRL_OFFSET, - ((FXMAC_NWCTRL_STATCLR_MASK) & (u32)(~FXMAC_NWCTRL_LOOPEN_MASK)) | FXMAC_NWCTRL_MDEN_MASK); + ((FXMAC_NWCTRL_STATCLR_MASK) & (u32)(~FXMAC_NWCTRL_LOOPBACK_LOCAL_MASK)) | FXMAC_NWCTRL_MDEN_MASK); FXmacConfigureCaps(instance_p); write_reg = FXmacClkDivGet(instance_p); /* mdio clock division */ write_reg |= FXmacDmaWidth(instance_p); /* DMA位宽 */ @@ -810,7 +793,7 @@ void FXmacInitInterface(FXmac *instance_p) config = FXMAC_READREG32(config_p->base_address, FXMAC_NWCFG_OFFSET); config |= FXMAC_NWCFG_PCSSEL_MASK | FXMAC_NWCFG_SGMII_MODE_ENABLE_MASK; - config &= ~(FXMAC_NWCFG_100_MASK | FXMAC_NWCFG_FDEN_MASK|FXMAC_NWCFG_LENGTH_FIELD_ERROR_FRAME_DISCARD); + config &= ~(FXMAC_NWCFG_100_MASK | FXMAC_NWCFG_FDEN_MASK|FXMAC_NWCFG_LENGTH_FIELD_ERROR_FRAME_DISCARD_MASK); if (instance_p->moudle_id >= 2) { @@ -931,6 +914,7 @@ FError FXmacCfgInitialize(FXmac *instance_p, const FXmacConfig *config_p) instance_p->restart_handler = (FXmacIrqHandler)FXmacIrqStubHandler; instance_p->restart_args = NULL; + instance_p->mask = FXMAC_INTR_MASK; return FT_SUCCESS; } diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.h b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.h index a0182db38c3..f0a61d3aadb 100644 --- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.h +++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac.h @@ -137,7 +137,7 @@ extern "C" (u32)FXMAC_RECEIVER_ENABLE_OPTION | \ (u32)FXMAC_RX_CHKSUM_ENABLE_OPTION | \ (u32)FXMAC_TX_CHKSUM_ENABLE_OPTION) - + typedef enum { FXMAC_LINKDOWN = 0, @@ -151,18 +151,20 @@ typedef enum #define FXMAC_MAC_ADDR_SIZE 6U /* size of Ethernet header */ #define FXMAC_MTU 1500U /* max MTU size of Ethernet frame */ -#define FXMAC_MTU_JUMBO 10240U /* max MTU size of jumbo frame */ +#define FXMAC_MTU_JUMBO 10240U /* max MTU size of jumbo frame including Ip header + IP payload */ #define FXMAC_HDR_SIZE 14U /* size of Ethernet header , DA + SA + TYPE*/ #define FXMAC_HDR_VLAN_SIZE 18U /* size of Ethernet header with VLAN */ #define FXMAC_TRL_SIZE 4U /* size of Ethernet trailer (FCS) */ -#define FXMAC_MAX_FRAME_SIZE (FXMAC_MTU + FXMAC_HDR_SIZE + \ - FXMAC_TRL_SIZE) + +#define FXMAC_MAX_FRAME_SIZE (FXMAC_MTU + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE) +#define FXMAC_MAX_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE) + #define FXMAC_MAX_VLAN_FRAME_SIZE (FXMAC_MTU + FXMAC_HDR_SIZE + \ FXMAC_HDR_VLAN_SIZE + FXMAC_TRL_SIZE) #define FXMAC_MAX_VLAN_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + \ - FXMAC_HDR_VLAN_SIZE + FXMAC_TRL_SIZE) + FXMAC_HDR_VLAN_SIZE + FXMAC_TRL_SIZE) + -#define FXMAC_MAX_FRAME_SIZE_JUMBO (FXMAC_MTU_JUMBO + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE) /** @name Callback identifiers * @@ -268,8 +270,9 @@ typedef struct u32 is_ready; /* Device is ininitialized and ready*/ u32 is_started; u32 link_status; /* indicates link status ,FXMAC_LINKUP is link up ,FXMAC_LINKDOWN is link down,FXMAC_NEGOTIATING is need to negotiating*/ - u32 options; - u32 caps; /* Capability mask bits */ + u32 options; + u32 mask; /*indicate intr mask */ + u32 caps; /* Capability mask bits */ FXmacQueue tx_bd_queue; /* Transmit Queue */ FXmacQueue rx_bd_queue; /* Receive Queue */ diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bd.h b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bd.h index 203e39e1b56..0441ad30270 100644 --- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bd.h +++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_bd.h @@ -184,7 +184,6 @@ extern "C" * @name: FXMAC_GET_RX_FRAME_SIZE * @msg: The returned value is the size of the received packet. * This API supports jumbo frame sizes if enabled. - * @param instance_p is the pointer to xmac instance * @param bd_ptr is the BD pointer to operate on * * @return Length field processed by hardware or set by @@ -193,7 +192,7 @@ extern "C" #define FXMAC_BD_JUMBO_LENGTH_MASK -#define FXMAC_GET_RX_FRAME_SIZE(instance_p, bd_ptr) \ +#define FXMAC_GET_RX_FRAME_SIZE(bd_ptr) \ (FXMAC_BD_READ((bd_ptr), FXMAC_BD_STAT_OFFSET) & \ 0x00003FFFU) diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_hw.h b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_hw.h index 0df7a81f6b9..f354228a009 100644 --- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_hw.h +++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_hw.h @@ -20,6 +20,7 @@ * Ver   Who        Date         Changes * ----- ------     --------    -------------------------------------- * 1.0 huanghe 2022/06/16 first release + * 1.1 liuzhihong 2023/4/11 jumbo support */ #ifndef FXMAC_HW_H @@ -35,9 +36,6 @@ extern "C" { #endif -#define FXMAC_RX_BUF_SIZE 1536U /* Specify the receive buffer size in bytes, 64, 128, ... 10240 */ -#define FXMAC_RX_BUF_SIZE_JUMBO 10240U - #define FXMAC_RX_BUF_UNIT 64U /* Number of receive buffer bytes as a unit, this is HW setup */ #define FXMAC_MAX_RXBD 128U /* Size of RX buffer descriptor queues */ @@ -186,6 +184,7 @@ extern "C" #define FXMAC_MSBBUF_TXQBASE_OFFSET 0x000004C8U /* MSB Buffer TX Q Base reg */ #define FXMAC_MSBBUF_RXQBASE_OFFSET 0x000004D4U /* MSB Buffer RX Q Base reg */ +#define FXMAC_TXQSEGALLOC_QLOWER_OFFSET 0x000005A0U /* Transmit SRAM segment distribution */ #define FXMAC_INTQ1_IER_OFFSET 0x00000600U /* Interrupt Q1 Enable reg */ #define FXMAC_INTQX_IER_SIZE_OFFSET(x) (FXMAC_INTQ1_IER_OFFSET + (x << 2)) @@ -255,7 +254,7 @@ extern "C" #define FXMAC_IXR_RXUSED_MASK BIT(2) /* Rx buffer used bit read */ #define FXMAC_IXR_RXCOMPL_MASK BIT(1) /* Frame received ok */ #define FXMAC_IXR_MGMNT_MASK BIT(0) /* PHY management complete */ -#define FXMAC_IXR_ALL_MASK GENMASK(14, 0) /* Everything! */ +#define FXMAC_IXR_ALL_MASK GENMASK(31, 0) /* Everything! */ #define FXMAC_IXR_TX_ERR_MASK ((u32)FXMAC_IXR_TXEXH_MASK | \ (u32)FXMAC_IXR_RETRY_MASK | \ @@ -265,6 +264,13 @@ extern "C" (u32)FXMAC_IXR_RXUSED_MASK | \ (u32)FXMAC_IXR_RXOVR_MASK) +#define FXMAC_INTR_MASK \ + ((u32)FXMAC_IXR_LINKCHANGE_MASK | \ + (u32)FXMAC_IXR_TX_ERR_MASK | \ + (u32)FXMAC_IXR_RX_ERR_MASK | \ + (u32)FXMAC_IXR_RXCOMPL_MASK | \ + (u32)FXMAC_IXR_TXCOMPL_MASK) + /** @name network control register bit definitions * @{ */ @@ -284,12 +290,22 @@ extern "C" #define FXMAC_NWCTRL_MDEN_MASK BIT(4) /* Enable MDIO port */ #define FXMAC_NWCTRL_TXEN_MASK BIT(3) /* Enable transmit */ #define FXMAC_NWCTRL_RXEN_MASK BIT(2) /* Enable receive */ -#define FXMAC_NWCTRL_LOOPEN_MASK BIT(1) /* local loopback */ +#define FXMAC_NWCTRL_LOOPBACK_LOCAL_MASK BIT(1) /* Loopback local */ + -/* External address match enable */ +/** @name network configuration register bit definitions + * @{ + */ +#define FXMAC_NWCFG_BADPREAMBEN_MASK BIT(29) /* disable rejection of non-standard preamble */ +#define FXMAC_NWCFG_IPDSTRETCH_MASK BIT(28) /* enable transmit IPG */ #define FXMAC_NWCFG_SGMII_MODE_ENABLE_MASK BIT(27) /* SGMII mode enable */ +#define FXMAC_NWCFG_FCSIGNORE_MASK BIT(26) /* disable rejection of FCS error */ +#define FXMAC_NWCFG_HDRXEN_MASK BIT(25) /* RX half duplex */ +#define FXMAC_NWCFG_RXCHKSUMEN_MASK BIT(24) /* enable RX checksum offload */ +#define FXMAC_NWCFG_PAUSECOPYDI_MASK BIT(23) /* Do not copy pause Frames to memory */ +#define FXMAC_NWCFG_DWIDTH_64_MASK BIT(21) /* 64 bit Data bus width */ #define FXMAC_NWCFG_BUS_WIDTH_32_MASK (0U << 21) #define FXMAC_NWCFG_BUS_WIDTH_64_MASK (1U << 21) #define FXMAC_NWCFG_BUS_WIDTH_128_MASK (2U << 21) @@ -302,12 +318,18 @@ extern "C" #define FXMAC_NWCFG_CLOCK_DIV32_MASK (2U << 18) #define FXMAC_NWCFG_CLOCK_DIV16_MASK (1U << 18) #define FXMAC_NWCFG_CLOCK_DIV8_MASK (0U << 18) +#define FXMAC_NWCFG_RESET_MASK BIT(19) /* reset value of mdc_clock_division*/ +#define FXMAC_NWCFG_MDC_SHIFT_MASK 18U /* shift bits for MDC */ +#define FXMAC_NWCFG_MDCCLKDIV_MASK GENMASK(20, 18) /* MDC Mask PCLK divisor */ -#define FXMAC_NWCFG_FCS_REMOVE BIT(17) /* FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). */ -#define FXMAC_NWCFG_LENGTH_FIELD_ERROR_FRAME_DISCARD BIT(16) -#define FXMAC_NWCFG_PAUSE_ENABLE BIT(13) /* Pause enable - when set, transmission will pause if a non-zero 802.3 classic pause frame is received and PFC has not been negotiated. */ +#define FXMAC_NWCFG_FCS_REMOVE_MASK BIT(17) /* FCS remove - setting this bit will cause received frames to be written to memory without their frame check sequence (last 4 bytes). */ +#define FXMAC_NWCFG_LENGTH_FIELD_ERROR_FRAME_DISCARD_MASK BIT(16) /* RX length error discard */ +#define FXMAC_NWCFG_RXOFFS_MASK GENMASK(15) /* RX buffer offset */ +#define FXMAC_NWCFG_PAUSE_ENABLE_MASK BIT(13) /* Pause enable - when set, transmission will pause if a non-zero 802.3 classic pause frame is received and PFC has not been negotiated. */ +#define FXMAC_NWCFG_RETRYTESTEN_MASK BIT(12) /* Retry test */ #define FXMAC_NWCFG_PCSSEL_MASK BIT(11) /* PCS Select */ #define FXMAC_NWCFG_1000_MASK BIT(10) /* Gigabit mode enable */ +#define FXMAC_NWCFG_XTADDMACHEN_MASK BIT(9) /* External address match enable */ #define FXMAC_NWCFG_1536RXEN_MASK BIT(8) /* Enable 1536 byte frames reception */ #define FXMAC_NWCFG_UCASTHASHEN_MASK BIT(7) /* Receive unicast hash frames */ #define FXMAC_NWCFG_MCASTHASHEN_MASK BIT(6) /* Receive multicast hash frames */ @@ -317,7 +339,7 @@ extern "C" #define FXMAC_NWCFG_NVLANDISC_MASK BIT(2) /* Receive only VLAN frames */ #define FXMAC_NWCFG_FDEN_MASK BIT(1) /* full duplex */ #define FXMAC_NWCFG_100_MASK BIT(0) /* 100 Mbps */ -#define FXMAC_NWCFG_RESET_MASK BIT(19) /* reset value */ + /* Receive buffer descriptor status words bit positions. * Receive buffer descriptor consists of two 32-bit registers, @@ -378,28 +400,6 @@ matched */ * @} */ -/** @name network configuration register bit definitions - * @{ - */ -#define FXMAC_NWCFG_BADPREAMBEN_MASK BIT(29) /* disable rejection of non-standard preamble */ -#define FXMAC_NWCFG_IPDSTRETCH_MASK BIT(28) /* enable transmit IPG */ -#define FXMAC_NWCFG_SGMIIEN_MASK BIT(27) /* SGMII Enable */ -#define FXMAC_NWCFG_FCSIGNORE_MASK BIT(26) /* disable rejection of FCS error */ -#define FXMAC_NWCFG_HDRXEN_MASK BIT(25) /* RX half duplex */ -#define FXMAC_NWCFG_RXCHKSUMEN_MASK BIT(24) /* enable RX checksum offload */ -#define FXMAC_NWCFG_PAUSECOPYDI_MASK BIT(23) /* Do not copy pause Frames to memory */ -#define FXMAC_NWCFG_DWIDTH_64_MASK BIT(21) /* 64 bit Data bus width */ -#define FXMAC_NWCFG_MDC_SHIFT_MASK 18U /* shift bits for MDC */ -#define FXMAC_NWCFG_MDCCLKDIV_MASK GENMASK(20, 18) /* MDC Mask PCLK divisor */ -#define FXMAC_NWCFG_FCSREM_MASK BIT(17) /* Discard FCS from received frames */ -#define FXMAC_NWCFG_LENERRDSCRD_MASK BIT(16) /* RX length error discard */ -#define FXMAC_NWCFG_RXOFFS_MASK GENMASK(15) /* RX buffer offset */ -#define FXMAC_NWCFG_PAUSEEN_MASK BIT(13) /* Enable pause RX */ -#define FXMAC_NWCFG_RETRYTESTEN_MASK BIT(12) /* Retry test */ -#define FXMAC_NWCFG_XTADDMACHEN_MASK BIT(9) -#define FXMAC_NWCFG_LOOPBACK_LOCAL_MASK BIT(1) /* Loopback local */ - -/* External address match enable */ /** * @name receive status register bit definitions @@ -479,7 +479,11 @@ matched */ (u32)FXMAC_TXSR_RXOVR_MASK | \ (u32)FXMAC_TXSR_FRAMERX_MASK | \ (u32)FXMAC_TXSR_USEDREAD_MASK) - +/** @name transmit SRAM segment allocation by queue 0 to 7 register bit definitions + * @{ + */ +#define FXMAC_TXQSEGALLOC_QLOWER_MASK BIT(2) /* 16 segments are distributed to queue 0*/ +#define FXMAC_TXQSEGALLOC_QLOWER_CLEAN_MASK 0x0U /** * @name Interrupt Q1 status register bit definitions * @{ diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_intr.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_intr.c index 63d0f66cbe1..e7d0b3c8783 100644 --- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_intr.c +++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_intr.c @@ -181,7 +181,7 @@ void FXmacIntrHandler(s32 vector, void *args) } } - /* link chaged */ + /* link changed */ if ((reg_isr & FXMAC_IXR_LINKCHANGE_MASK) != 0x00000000U) { if (instance_p->link_change_handler) diff --git a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_options.c b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_options.c index 1d05fef0979..b82ed635088 100644 --- a/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_options.c +++ b/bsp/phytium/libraries/standalone/drivers/eth/fxmac/fxmac_options.c @@ -20,6 +20,7 @@ * Ver   Who        Date         Changes * ----- ------     --------    -------------------------------------- * 1.0 huanghe 2022/06/16 first release + * 1.1 liuzhihong 2023/4/11 jumbo support */ #include "fxmac_hw.h" @@ -218,19 +219,19 @@ FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num) /* Turn on FCS stripping on receive packets */ if ((options & FXMAC_FCS_STRIP_OPTION) != 0x00000000U) { - reg_new_netcfg |= FXMAC_NWCFG_FCSREM_MASK; + reg_new_netcfg |= FXMAC_NWCFG_FCS_REMOVE_MASK; } /* Turn on length/type field checking on receive packets */ if ((options & FXMAC_LENTYPE_ERR_OPTION) != 0x00000000U) { - reg_new_netcfg |= FXMAC_NWCFG_LENERRDSCRD_MASK; + reg_new_netcfg |= FXMAC_NWCFG_LENGTH_FIELD_ERROR_FRAME_DISCARD_MASK; } /* Turn on flow control */ if ((options & FXMAC_FLOW_CONTROL_OPTION) != 0x00000000U) { - reg_new_netcfg |= FXMAC_NWCFG_PAUSEEN_MASK; + reg_new_netcfg |= FXMAC_NWCFG_PAUSE_ENABLE_MASK; } /* Turn on promiscuous frame filtering (all frames are received) */ @@ -261,13 +262,13 @@ FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num) if ((options & FXMAC_JUMBO_ENABLE_OPTION) != 0x00000000U) { instance_p->max_mtu_size = FXMAC_MTU_JUMBO; - instance_p->max_frame_size = FXMAC_MTU_JUMBO + - FXMAC_HDR_SIZE + FXMAC_TRL_SIZE; + instance_p->max_frame_size = FXMAC_MAX_FRAME_SIZE_JUMBO; reg_new_netcfg |= FXMAC_NWCFG_JUMBO_MASK; FXMAC_WRITEREG32(config_p->base_address, - FXMAC_JUMBOMAXLEN_OFFSET, FXMAC_MTU_JUMBO); - + FXMAC_JUMBOMAXLEN_OFFSET, FXMAC_MAX_FRAME_SIZE_JUMBO); + FXMAC_WRITEREG32(config_p->base_address, + FXMAC_TXQSEGALLOC_QLOWER_OFFSET,FXMAC_TXQSEGALLOC_QLOWER_MASK); if (queue_num == 0) { u32 rx_buf_size = 0; @@ -275,8 +276,8 @@ FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num) FXMAC_DMACR_OFFSET); reg &= ~FXMAC_DMACR_RXBUF_MASK; - rx_buf_size = ((u32)instance_p->max_mtu_size / (u32)FXMAC_RX_BUF_UNIT); - rx_buf_size += (((u32)instance_p->max_mtu_size % (u32)FXMAC_RX_BUF_UNIT) != (u32)0) ? 1U : 0U; + rx_buf_size = ((u32)instance_p->max_frame_size / (u32)FXMAC_RX_BUF_UNIT); + rx_buf_size += (((u32)instance_p->max_frame_size % (u32)FXMAC_RX_BUF_UNIT) != (u32)0) ? 1U : 0U; reg |= ((rx_buf_size << (u32)(FXMAC_DMACR_RXBUF_SHIFT)) & (u32)(FXMAC_DMACR_RXBUF_MASK)); @@ -286,8 +287,8 @@ FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num) else if (queue_num < instance_p->config.max_queue_num) { u32 rx_buf_size = 0; - rx_buf_size = ((u32)instance_p->max_mtu_size / (u32)FXMAC_RX_BUF_UNIT); - rx_buf_size += (((u32)instance_p->max_mtu_size % (u32)FXMAC_RX_BUF_UNIT) != (u32)0) ? 1U : 0U; + rx_buf_size = ((u32)instance_p->max_frame_size / (u32)FXMAC_RX_BUF_UNIT); + rx_buf_size += (((u32)instance_p->max_frame_size % (u32)FXMAC_RX_BUF_UNIT) != (u32)0) ? 1U : 0U; FXMAC_WRITEREG32(config_p->base_address, FXMAC_RXBUFQX_SIZE_OFFSET(queue_num), rx_buf_size & FXMAC_RXBUFQX_SIZE_MASK); } @@ -295,14 +296,14 @@ FError FXmacSetOptions(FXmac *instance_p, u32 options, u32 queue_num) if (((options & FXMAC_SGMII_ENABLE_OPTION) != 0x00000000U)) { - reg_new_netcfg |= (FXMAC_NWCFG_SGMIIEN_MASK | + reg_new_netcfg |= (FXMAC_NWCFG_SGMII_MODE_ENABLE_MASK | FXMAC_NWCFG_PCSSEL_MASK); } if ((options & FXMAC_LOOPBACK_NO_MII_OPTION) != 0x00000000U) { reg = FXMAC_READREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET); - reg |= FXMAC_NWCFG_LOOPBACK_LOCAL_MASK; + reg |= FXMAC_NWCTRL_LOOPBACK_LOCAL_MASK; FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET, reg); } @@ -421,19 +422,19 @@ FError FXmacClearOptions(FXmac *instance_p, u32 options, u32 queue_num) /* Turn off FCS stripping on receive packets */ if ((options & FXMAC_FCS_STRIP_OPTION) != 0x00000000U) { - reg_new_net_cfg &= (u32)(~FXMAC_NWCFG_FCSREM_MASK); + reg_new_net_cfg &= (u32)(~FXMAC_NWCFG_FCS_REMOVE_MASK); } /* Turn off length/type field checking on receive packets */ if ((options & FXMAC_LENTYPE_ERR_OPTION) != 0x00000000U) { - reg_new_net_cfg &= (u32)(~FXMAC_NWCFG_LENERRDSCRD_MASK); + reg_new_net_cfg &= (u32)(~FXMAC_NWCFG_LENGTH_FIELD_ERROR_FRAME_DISCARD_MASK); } /* Turn off flow control */ if ((options & FXMAC_FLOW_CONTROL_OPTION) != 0x00000000U) { - reg_new_net_cfg &= (u32)(~FXMAC_NWCFG_PAUSEEN_MASK); + reg_new_net_cfg &= (u32)(~FXMAC_NWCFG_PAUSE_ENABLE_MASK); } /* Turn off promiscuous frame filtering (all frames are received) */ @@ -465,12 +466,14 @@ FError FXmacClearOptions(FXmac *instance_p, u32 options, u32 queue_num) { instance_p->max_mtu_size = FXMAC_MTU; - instance_p->max_frame_size = FXMAC_MTU + FXMAC_HDR_SIZE + FXMAC_TRL_SIZE; + instance_p->max_frame_size = FXMAC_MAX_FRAME_SIZE; reg_new_net_cfg &= (u32)(~FXMAC_NWCFG_JUMBO_MASK); reg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_DMACR_OFFSET); reg &= ~FXMAC_DMACR_RXBUF_MASK; + FXMAC_WRITEREG32(config_p->base_address, + FXMAC_TXQSEGALLOC_QLOWER_OFFSET,FXMAC_TXQSEGALLOC_QLOWER_CLEAN_MASK); if (queue_num == 0) { @@ -479,8 +482,8 @@ FError FXmacClearOptions(FXmac *instance_p, u32 options, u32 queue_num) reg = FXMAC_READREG32(instance_p->config.base_address, FXMAC_DMACR_OFFSET); reg &= ~FXMAC_DMACR_RXBUF_MASK; - rx_buf_size = ((u32)instance_p->max_mtu_size / (u32)FXMAC_RX_BUF_UNIT); - rx_buf_size += ((u32)instance_p->max_mtu_size % ((u32)FXMAC_RX_BUF_UNIT) != (u32)0) ? 1U : 0U; + rx_buf_size = ((u32)instance_p->max_frame_size / (u32)FXMAC_RX_BUF_UNIT); + rx_buf_size += ((u32)instance_p->max_frame_size % ((u32)FXMAC_RX_BUF_UNIT) != (u32)0) ? 1U : 0U; reg |= ((rx_buf_size << (u32)(FXMAC_DMACR_RXBUF_SHIFT)) & (u32)(FXMAC_DMACR_RXBUF_MASK)); @@ -489,8 +492,8 @@ FError FXmacClearOptions(FXmac *instance_p, u32 options, u32 queue_num) else if (queue_num < instance_p->config.max_queue_num) { u32 rx_buf_size = 0; - rx_buf_size = ((u32)instance_p->max_mtu_size / (u32)FXMAC_RX_BUF_UNIT); - rx_buf_size += (((u32)instance_p->max_mtu_size % (u32)FXMAC_RX_BUF_UNIT) != (u32)0) ? 1U : 0U; + rx_buf_size = ((u32)instance_p->max_frame_size / (u32)FXMAC_RX_BUF_UNIT); + rx_buf_size += (((u32)instance_p->max_frame_size % (u32)FXMAC_RX_BUF_UNIT) != (u32)0) ? 1U : 0U; FXMAC_WRITEREG32(config_p->base_address, FXMAC_RXBUFQX_SIZE_OFFSET(queue_num), rx_buf_size & FXMAC_RXBUFQX_SIZE_MASK); } @@ -498,14 +501,14 @@ FError FXmacClearOptions(FXmac *instance_p, u32 options, u32 queue_num) if (((options & FXMAC_SGMII_ENABLE_OPTION) != 0x00000000U)) { - reg_new_net_cfg &= (u32)(~(FXMAC_NWCFG_SGMIIEN_MASK | + reg_new_net_cfg &= (u32)(~(FXMAC_NWCFG_SGMII_MODE_ENABLE_MASK | FXMAC_NWCFG_PCSSEL_MASK)); } if ((options & FXMAC_LOOPBACK_NO_MII_OPTION) != 0x00000000U) { reg = FXMAC_READREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET); - reg &= (u32)(~FXMAC_NWCFG_LOOPBACK_LOCAL_MASK); + reg &= (u32)(~FXMAC_NWCTRL_LOOPBACK_LOCAL_MASK); FXMAC_WRITEREG32(config_p->base_address, FXMAC_NWCTRL_OFFSET, reg); } diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.c b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.c index a1c96c46ce4..4431c8fc6e4 100644 --- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.c +++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic.c @@ -49,7 +49,7 @@ #define FGIC_GICD_4_PER_REG 4 #define FGIC_INT_DEFAULT_PRI_X4 0xa0a0a0a0 /* 考虑到当前一般程序工作于EL1，对于NS 或 S 安全状态 ，0x80 - 0xff 的优先级都有存在的可能性 */ -#define FGIC_CPU_INTERFACE_DEFAULT_FLITER 0xFF +#define FGIC_CPU_INTERFACE_DEFAULT_FILTER 0xFF typedef enum { @@ -236,7 +236,7 @@ void FGicCpuInterfaceInit(void) FASSERT(reg & GICC_SRE_SRE); } - FGicSetICC_PMR(FGIC_CPU_INTERFACE_DEFAULT_FLITER); + FGicSetICC_PMR(FGIC_CPU_INTERFACE_DEFAULT_FILTER); FGicEnableGroup1_EL1(); diff --git a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_hw.h b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_hw.h index aafc131c27d..0c74cb4fab1 100644 --- a/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_hw.h +++ b/bsp/phytium/libraries/standalone/drivers/gic/fgic/fgic_hw.h @@ -146,9 +146,29 @@ extern "C" #define FGIC_READREG32(addr, reg_offset) FtIn32(addr + (u32)reg_offset) #define FGIC_WRITEREG32(addr, reg_offset, reg_value) FtOut32(addr + (u32)reg_offset, (u32)reg_value) +#ifdef __aarch64__ + #define FGIC_READREG64(addr, reg_offset) FtIn64(addr + (u64)reg_offset) #define FGIC_WRITEREG64(addr, reg_offset, reg_value) FtOut64(addr +(u64)reg_offset, (u64)reg_value) +#else + +#define FGIC_READREG64(addr, reg_offset) \ +({ \ + u64 reg_val; \ + reg_val = FtIn32(addr + (u32)reg_offset + 4); \ + reg_val = (reg_val << 32) | FtIn32(addr + (u32)reg_offset); \ + reg_val; \ +}) + +#define FGIC_WRITEREG64(addr, reg_offset, reg_value) \ +({ \ + FtOut32(addr + (u32)reg_offset, (u32)reg_value); \ + FtOut32(addr + (u32)reg_offset + 4, (u32)(((u64)reg_value) >> 32)); \ +}) + +#endif + #define FGIC_SETBIT(base_addr, reg_offset, data) \ FtSetBit32((base_addr) + (u32)(reg_offset), (u32)(data)) diff --git a/bsp/phytium/libraries/standalone/drivers/iopad/Kconfig b/bsp/phytium/libraries/standalone/drivers/iopad/Kconfig new file mode 100644 index 00000000000..972a37025f9 --- /dev/null +++ b/bsp/phytium/libraries/standalone/drivers/iopad/Kconfig @@ -0,0 +1,4 @@ + config ENABLE_IOPAD + bool + prompt "Enable iopad" + default y if TARGET_E2000 \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad.c b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad.c new file mode 100644 index 00000000000..d5aedbd9b06 --- /dev/null +++ b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad.c @@ -0,0 +1,478 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fiopad.c + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-02-18 08:25:29 + * Description:  This file is for iopad function + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhangyan 2023/7/4 init commit + */ + +/***************************** Include Files *********************************/ +#include "fparameters.h" +#include +#include "fio.h" +#include "fkernel.h" +#include "fassert.h" +#include "fdebug.h" +#include "stdio.h" +#include "fpinctrl.h" +#include "fiopad_hw.h" +#include "fiopad.h" + +/************************** Constant Definitions *****************************/ + +/**************************** Type Definitions *******************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +#define FIOPAD_DEBUG_TAG "FIOPAD" +#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) +#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) +#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) +#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) + +/************************** Function Prototypes ******************************/ + +/** + * @name: FIOPadCfgInitialize + * @msg: Initializes a specific instance such that it is ready to be used + * @param {FIOPadCtrl} *pctrl, instance of FIOPAD controller + * @param {FIOPadConfig} input_config_p, Configuration parameters of IOPAD + * @return err code information, FPWM_SUCCESS indicates success，others indicates failed + */ +FError FIOPadCfgInitialize(FIOPadCtrl *instance_p, const FIOPadConfig *input_config_p) +{ + FASSERT(instance_p != NULL); + FASSERT(input_config_p != NULL); + + FError ret = FIOPAD_SUCCESS; + /* + * If the device is started, disallow the initialize and return a Status + * indicating it is started. This allows the user to de-initialize the device + * and reinitialize, but prevents a user from inadvertently + * initializing. + */ + if (FT_COMPONENT_IS_READY == instance_p->is_ready) + { + FIOPAD_WARN("Device is already initialized."); + } + + /*Set default values and configuration data */ + FIOPadDeInitialize(instance_p); + + instance_p->config = *input_config_p; + + instance_p->is_ready = FT_COMPONENT_IS_READY; + + return ret; +} + +/** + * @name: FPinGetFunc + * @msg: get the current multiplexing function of IO pins + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @return {FIOPadFunc} current multiplexing function + */ +FIOPadFunc FIOPadGetFunc(FIOPadCtrl *instance_p, const u32 pin_reg_off) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG0_OFF(pin_reg_off); + uintptr base_addr = instance_p->config.base_address; + u32 func = FIOPAD_REG0_FUNC_GET(FIOPAD_READ_REG32(base_addr, pin_reg_off)); + FIOPAD_ASSERT_FUNC(func); + + return (FIOPadFunc)func; +} + +/** + * @name: FPinSetFunc + * @msg: set the multiplexing function of IO pins + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @param {FIOPadFunc} func, specific multiplexing function + * @return err code information, FIOPAD_SUCCESS indicates success，others indicates failed + */ +FError FIOPadSetFunc(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadFunc func) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG0_OFF(pin_reg_off); + FIOPAD_ASSERT_FUNC(func); + u32 ret = FIOPAD_SUCCESS; + uintptr base_addr = instance_p->config.base_address; + u32 reg_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + u32 test_val = 0; + + reg_val &= ~FIOPAD_REG0_FUNC_MASK; + reg_val |= FIOPAD_REG0_FUNC_SET(func); + + FIOPAD_WRITE_REG32(base_addr, pin_reg_off, reg_val); + + test_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + + if (reg_val != test_val) + { + FIOPAD_ERROR("ERROR: FIOPad write is failed ,pin is %x\n, 0x%x != 0x%x", + pin_reg_off, reg_val, test_val); + } + + return ret; +} + +/** + * @name: FIOPadGetPull + * @msg: get the current up_down_pull configuration of IO pins + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @return {FIOPadPull} current up_down_pull configuration + */ +FIOPadPull FIOPadGetPull(FIOPadCtrl *instance_p, const u32 pin_reg_off) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG0_OFF(pin_reg_off); + uintptr base_addr = instance_p->config.base_address; + u32 pull = FIOPAD_REG0_PULL_GET(FIOPAD_READ_REG32(base_addr, pin_reg_off)); + FIOPAD_ASSERT_PULL(pull); + + return (FIOPadPull)pull; +} + +/** + * @name: FIOPadSetPull + * @msg: set the up_down_pull configuration of IO pins + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @param {FIOPadPull} func, up_down_pull configuration + * @return err code information, FIOPAD_SUCCESS indicates success，others indicates failed + */ +FError FIOPadSetPull(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadPull pull) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG0_OFF(pin_reg_off); + FIOPAD_ASSERT_PULL(pull); + u32 ret = FIOPAD_SUCCESS; + uintptr base_addr = instance_p->config.base_address; + u32 reg_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + + reg_val &= ~FIOPAD_REG0_PULL_MASK; + reg_val |= FIOPAD_REG0_PULL_SET(pull); + + FIOPAD_WRITE_REG32(base_addr, pin_reg_off, reg_val); + + return ret; +} + +/** + * @name: FIOPadGetDriver + * @msg: get the current driver strength of IO pins + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @return {FIOPadDrive} current driver strength + */ +FIOPadDrive FIOPadGetDriver(FIOPadCtrl *instance_p, const u32 pin_reg_off) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG0_OFF(pin_reg_off); + uintptr base_addr = instance_p->config.base_address; + u32 drive = FIOPAD_REG0_DRIVE_GET(FIOPAD_READ_REG32(base_addr, pin_reg_off)); + FIOPAD_ASSERT_DRIVE(drive); + + return (FIOPadDrive)drive; +} + +/** + * @name: FIOPadSetDriver + * @msg: set the driver strength of IO pins + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @param {FIOPadDrive} func, driver strength + * @return err code information, FIOPAD_SUCCESS indicates success，others indicates failed + */ +FError FIOPadSetDriver(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDrive drive) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG0_OFF(pin_reg_off); + FIOPAD_ASSERT_DRIVE(drive); + u32 ret = FIOPAD_SUCCESS; + uintptr base_addr = instance_p->config.base_address; + u32 reg_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + + reg_val &= ~FIOPAD_REG0_DRIVE_MASK; + reg_val |= FIOPAD_REG0_DRIVE_SET(drive); + + FIOPAD_WRITE_REG32(base_addr, pin_reg_off, reg_val); + + return ret; +} + +/** + * @name: FIOPadSetConfig + * @msg: set the func, up_down_pull, driver strength of IO pins + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @param {FIOPadFunc} func, specific multiplexing function + * @param {FIOPadPull} pull, up_down_pull configurations + * @param {FIOPadDrive} driver, driver strength + * @return err code information, FIOPAD_SUCCESS indicates success，others indicates failed + */ +FError FIOPadSetConfig(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadFunc func, FIOPadPull pull, FIOPadDrive drive) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG0_OFF(pin_reg_off); + FIOPAD_ASSERT_FUNC(func); + FIOPAD_ASSERT_PULL(pull); + FIOPAD_ASSERT_DRIVE(drive); + u32 ret = FIOPAD_SUCCESS; + uintptr base_addr = instance_p->config.base_address; + u32 reg_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + + reg_val &= ~FIOPAD_REG0_FUNC_MASK; + reg_val |= FIOPAD_REG0_FUNC_SET(func); + + reg_val &= ~FIOPAD_REG0_PULL_MASK; + reg_val |= FIOPAD_REG0_PULL_SET(pull); + + reg_val &= ~FIOPAD_REG0_DRIVE_MASK; + reg_val |= FIOPAD_REG0_DRIVE_SET(drive); + + FIOPAD_WRITE_REG32(base_addr, pin_reg_off, reg_val); + reg_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + + return ret; +} + +/** + * @name: FIOPadGetConfig + * @msg: set the func, up_down_pull, driver strength of IO pins + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @param {FIOPadFunc} *func, multiplexing function + * @param {FIOPadPull} *pull, up_down_pull configurations + * @param {FIOPadDrive} *driver, driver strength + * @return err code information, FIOPAD_SUCCESS indicates success，others indicates failed + */ +FError FIOPadGetConfig(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadFunc *func, FIOPadPull *pull, FIOPadDrive *drive) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG0_OFF(pin_reg_off); + u32 ret = FIOPAD_SUCCESS; + uintptr base_addr = instance_p->config.base_address; + u32 reg_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + + *func = FIOPAD_REG0_FUNC_GET(reg_val); + *pull = FIOPAD_REG0_PULL_GET(reg_val); + *drive = FIOPAD_REG0_DRIVE_GET(reg_val); + + return ret; +} + +/** + * @name: FIOPadGetDelay + * @msg: get the current delay configuration of IO pins + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @param {FIOPadDelayDir} dir, the delay direction + * @param {FIOPadDelayType} type, the delay type + * @return {FIOPadDelay} current delay value + */ +FIOPadDelay FIOPadGetDelay(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDelayDir dir, FIOPadDelayType type) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG1_OFF(pin_reg_off); + uintptr base_addr = instance_p->config.base_address; + const u32 reg_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + u8 delay = 0; + + if (FIOPAD_OUTPUT_DELAY == dir) + { + if (FIOPAD_DELAY_FINE_TUNING == type) + { + delay = FIOPAD_REG1_OUT_DELAY_DELICATE_GET(reg_val); + } + else if (FIOPAD_DELAY_COARSE_TUNING == type) + { + delay = FIOPAD_REG1_OUT_DELAY_ROUGH_GET(reg_val); + } + else + { + FASSERT(0); + } + } + else if (FIOPAD_INPUT_DELAY == dir) + { + if (FIOPAD_DELAY_FINE_TUNING == type) + { + delay = FIOPAD_REG1_IN_DELAY_DELICATE_GET(reg_val); + } + else if (FIOPAD_DELAY_COARSE_TUNING == type) + { + delay = FIOPAD_REG1_IN_DELAY_ROUGH_GET(reg_val); + } + else + { + FASSERT(0); + } + } + else + { + FASSERT(0); + } + + FIOPAD_ASSERT_DELAY(delay); + + return (FIOPadDelay)delay; +} + +/** + * @name: FIOPadSetDelay + * @msg: set the current delay configuration of IO pins + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @param {FIOPadDelayDir} dir, the delay direction + * @param {FIOPadDelayType} type, the delay type + * @param {FIOPadDelay} delay, delay value + * @return err code information, FIOPAD_SUCCESS indicates success，others indicates failed + */ +FError FIOPadSetDelay(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDelayDir dir, FIOPadDelayType type, FIOPadDelay delay) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG1_OFF(pin_reg_off); + FIOPAD_ASSERT_DELAY(delay); + u32 ret = FIOPAD_SUCCESS; + uintptr base_addr = instance_p->config.base_address; + u32 reg_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + + if (FIOPAD_OUTPUT_DELAY == dir) + { + if (FIOPAD_DELAY_FINE_TUNING == type) + { + reg_val &= ~FIOPAD_REG1_OUT_DELAY_DELICATE_MASK; + reg_val |= FIOPAD_REG1_OUT_DELAY_DELICATE_SET(delay); + } + else if (FIOPAD_DELAY_COARSE_TUNING == type) + { + reg_val &= ~FIOPAD_REG1_OUT_DELAY_ROUGH_MASK; + reg_val |= FIOPAD_REG1_OUT_DELAY_ROUGH_SET(delay); + } + else + { + FASSERT(0); + } + } + else if (FIOPAD_INPUT_DELAY == dir) + { + if (FIOPAD_DELAY_FINE_TUNING == type) + { + reg_val &= ~FIOPAD_REG1_IN_DELAY_DELICATE_MASK; + reg_val |= FIOPAD_REG1_IN_DELAY_DELICATE_SET(delay); + } + else if (FIOPAD_DELAY_COARSE_TUNING == type) + { + reg_val &= ~FIOPAD_REG1_IN_DELAY_ROUGH_MASK; + reg_val |= FIOPAD_REG1_IN_DELAY_ROUGH_SET(delay); + } + else + { + FASSERT(0); + } + } + else + { + FASSERT(0); + } + + FIOPAD_WRITE_REG32(base_addr, pin_reg_off, reg_val); + + return ret; +} + +/** + * @name: FPinSetDelayEn + * @msg: Enable/disable IO pin delay + * @param {FIOPadCtrl} *instance_p, instance of FIOPAD controller + * @param {u32} pin_reg_off, pin reg offset + * @param {FIOPadDelayDir} dir, the delay direction + * @param {boolean} enable TRUE: enable, FALSE: disable + * @return err code information, FIOPAD_SUCCESS indicates success，others indicates failed + */ +FError FIOPadSetDelayEn(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDelayDir dir, boolean enable) +{ + FASSERT(instance_p); + FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY); + FIOPAD_ASSERT_REG1_OFF(pin_reg_off); + u32 ret = FIOPAD_SUCCESS; + uintptr base_addr = instance_p->config.base_address; + u32 reg_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + + if (FIOPAD_OUTPUT_DELAY == dir) + { + if (enable) + { + reg_val |= FIOPAD_REG1_OUT_DELAY_EN; + } + else + { + reg_val &= ~FIOPAD_REG1_OUT_DELAY_EN; + } + } + else if (FIOPAD_INPUT_DELAY == dir) + { + if (enable) + { + reg_val |= FIOPAD_REG1_IN_DELAY_EN; + } + else + { + reg_val &= ~FIOPAD_REG1_IN_DELAY_EN; + } + } + else + { + FASSERT(0); + } + + FIOPAD_WRITE_REG32(base_addr, pin_reg_off, reg_val); + + return ret; +} + +/** + * @name: FIOPadDeInitialize + * @msg: DeInitialization function for the device instance + * @param {FIOPadCtrl} *pctrl, instance of FIOPAD controller + * @return {*} + */ +FError FIOPadDeInitialize(FIOPadCtrl *instance_p) +{ + FASSERT(instance_p); + FError ret = FIOPAD_SUCCESS; + instance_p->is_ready = 0; + memset(instance_p, 0, sizeof(*instance_p)); + + return ret; +} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad.h b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad.h new file mode 100644 index 00000000000..280ea510a49 --- /dev/null +++ b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad.h @@ -0,0 +1,190 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fiopad.h + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-04-15 11:45:05 + * Description: This file is for detailed description of the device configuration and driver. + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhangyan 2023/7/4 init commit + */ + +#ifndef FIOPAD_H +#define FIOPAD_H + +/***************************** Include Files *********************************/ +#include "ftypes.h" +#include "fparameters.h" +#include "fio.h" +#include "fkernel.h" +#include "fassert.h" +#include "fdebug.h" +#include "stdio.h" +#include "fpinctrl.h" +#include "fiopad_hw.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/**************************** Type Definitions *******************************/ +#define FIOPAD_SUCCESS FT_SUCCESS +#define FIOPAD_INVAL_PARAM FT_MAKE_ERRCODE(ErrModBsp, ErrBspIOPad, 1) +#define FIOPAD_NOT_READY FT_MAKE_ERRCODE(ErrModBsp, ErrBspIOPad, 2) +#define FIOPAD_NOT_SUPPORT FT_MAKE_ERRCODE(ErrModBsp, ErrBspIOPad, 3) + +typedef enum +{ + FIOPAD_FUNC0 = 0b000, + FIOPAD_FUNC1, + FIOPAD_FUNC2, + FIOPAD_FUNC3 = 0b011, + FIOPAD_FUNC4, + FIOPAD_FUNC5, + FIOPAD_FUNC6, + FIOPAD_FUNC7 = 0b111, + + FIOPAD_NUM_OF_FUNC +} FIOPadFunc; /* Pin multiplexing function configuration, func0 is the default function */ + +typedef enum +{ + FIOPAD_DRV0 = 0b0000, + FIOPAD_DRV1, + FIOPAD_DRV2, + FIOPAD_DRV3, + FIOPAD_DRV4, + FIOPAD_DRV5, + FIOPAD_DRV6, + FIOPAD_DRV7, + FIOPAD_DRV8, + FIOPAD_DRV9, + FIOPAD_DRV10, + FIOPAD_DRV11, + FIOPAD_DRV12, + FIOPAD_DRV13, + FIOPAD_DRV14, + FIOPAD_DRV15 = 0b1111, + + FIOPAD_NUM_OF_DRIVE +} FIOPadDrive; /* Pin drive capability configuration */ + +typedef enum +{ + FIOPAD_PULL_NONE = 0b00, + FIOPAD_PULL_DOWN = 0b01, + FIOPAD_PULL_UP = 0b10, + + FIOPAD_NUM_OF_PULL +} FIOPadPull; /* Pin up pull-down configuration */ + +typedef enum +{ + FIOPAD_OUTPUT_DELAY = 0, /* Delay setting direction to output */ + FIOPAD_INPUT_DELAY, /* Delay setting direction to input */ + + FIOPAD_NUM_OF_DELAY_DIR +} FIOPadDelayDir; /* Pin delay configuration direction */ + +typedef enum +{ + FIOPAD_DELAY_COARSE_TUNING = 0, /*delay coarse tuning */ + FIOPAD_DELAY_FINE_TUNING, /*delay fine tuning */ + + FIOPAD_NUM_OF_DELAY_TYPE +} FIOPadDelayType; /* Pin delay configuration type */ + +typedef enum +{ + FIOPAD_DELAY_NONE = 0, + FIOPAD_DELAY_1, + FIOPAD_DELAY_2, + FIOPAD_DELAY_3, + FIOPAD_DELAY_4, + FIOPAD_DELAY_5, + FIOPAD_DELAY_6, + FIOPAD_DELAY_7, + + FIOPAD_NUM_OF_DELAY +} FIOPadDelay; + +typedef struct +{ + u32 instance_id; /* Device instance id */ + uintptr base_address; + +} FIOPadConfig; + +typedef struct +{ + FIOPadConfig config; + u32 is_ready; + +} FIOPadCtrl; +/************************** Variable Definitions *****************************/ + +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/* get iopad configs by id */ +const FIOPadConfig *FIOPadLookupConfig(u32 instance_id); + +/*Initializes a specific instance such that it is ready to be used*/ +FError FIOPadCfgInitialize(FIOPadCtrl *instance_p, const FIOPadConfig *input_config_p); + +/*get the current multiplexing function of IO pins*/ +FIOPadFunc FIOPadGetFunc(FIOPadCtrl *instance_p, const u32 pin_reg_off); + +/*set the multiplexing function of IO pins*/ +FError FIOPadSetFunc(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadFunc func); + +/*get the current up_down_pull configuration of IO pins*/ +FIOPadPull FIOPadGetPull(FIOPadCtrl *instance_p, const u32 pin_reg_off); + +/*set the up_down_pull configuration of IO pins*/ +FError FIOPadSetPull(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadPull pull); + +/*get the current driver strength of IO pins*/ +FIOPadDrive FIOPadGetDriver(FIOPadCtrl *instance_p, const u32 pin_reg_off); + +/*get the driver strength of IO pins*/ +FError FIOPadSetDriver(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDrive drive); + +/*set the func, pull, driver strength */ +FError FIOPadGetConfig(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadFunc *func, FIOPadPull *pull, FIOPadDrive *drive); + +/*set the func, pull, driver strength */ +FError FIOPadSetConfig(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadFunc func, FIOPadPull pull, FIOPadDrive drive); + +/*get the current delay configuration of IO pins*/ +FIOPadDelay FIOPadGetDelay(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDelayDir dir, FIOPadDelayType type); + +/*set the current delay configuration of IO pins*/ +FError FIOPadSetDelay(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDelayDir dir, FIOPadDelayType type, FIOPadDelay delay); + +/*Enable/disable IO pin delay*/ +FError FIOPadSetDelayEn(FIOPadCtrl *instance_p, const u32 pin_reg_off, FIOPadDelayDir dir, boolean enable); + +/* DeInitialization function for the device instance */ +FError FIOPadDeInitialize(FIOPadCtrl *instance_p); + +#ifdef __cplusplus +} + +#endif +#endif diff --git a/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_g.c b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_g.c new file mode 100644 index 00000000000..bf75f302859 --- /dev/null +++ b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_g.c @@ -0,0 +1,34 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fiopad_g.c + * Date: 2021-04-29 10:21:53 + * LastEditTime: 2022-02-18 08:29:20 + * Description:  This files is for the iopad register related functions + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhangyan 2023/7/3 first release + */ +#include "fparameters.h" +#include "fiopad_hw.h" +#include "fiopad.h" + +FIOPadConfig FIOPadConfigTbl[FIOPAD_NUM] = +{ + { + .instance_id = FIOPAD0_ID, + .base_address = FIOPAD_BASE_ADDR, + } +}; \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_hw.c b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_hw.c new file mode 100644 index 00000000000..da22a38338c --- /dev/null +++ b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_hw.c @@ -0,0 +1,69 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fiopad_hw.c + * Date: 2021-04-29 10:21:53 + * LastEditTime: 2022-02-18 08:29:20 + * Description:  This files is for the iopad register related functions + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhangyan 2023/7/3 first release + */ + +/***************************** Include Files *********************************/ +#include "fparameters.h" +#include "fiopad_hw.h" +#include "fdebug.h" + +#define FIOPAD_DEBUG_TAG "FIOPAD_HW" +#define FIOPAD_ERROR(format, ...) FT_DEBUG_PRINT_E(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) +#define FIOPAD_WARN(format, ...) FT_DEBUG_PRINT_W(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) +#define FIOPAD_INFO(format, ...) FT_DEBUG_PRINT_I(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) +#define FIOPAD_DEBUG(format, ...) FT_DEBUG_PRINT_D(FIOPAD_DEBUG_TAG, format, ##__VA_ARGS__) + +/** + * @name: FIOPadDump + * @msg: print information of all iopad + * @return {*} + */ +void FIOPadDump(uintptr base_addr) +{ + uintptr beg_off = 0x0000U; + uintptr end_off = 0x024CU; + uintptr off; + FIOPadFunc pin_func; + FIOPadDrive pin_drv; + FIOPadPull pin_pull; + u32 pin_reg_off; + const char *pull_state[FIOPAD_NUM_OF_PULL] = {"none", "down", "up"}; + + FIOPAD_DEBUG("Pad Func Info..."); + for (off = beg_off; off <= end_off; off += 4U) + { + pin_reg_off = off; + u32 reg_val = FIOPAD_READ_REG32(base_addr, pin_reg_off); + pin_func = FIOPAD_REG0_FUNC_GET(reg_val); + pin_pull = FIOPAD_REG0_PULL_GET(reg_val); + pin_drv = FIOPAD_REG0_DRIVE_GET(reg_val); + + FIOPAD_DEBUG(" [0x%x] func: %d, ds: %d, pull: %s ", + pin_reg_off, + pin_func, + pin_drv, + pull_state[pin_pull]); + } + + return; +} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_hw.h b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_hw.h new file mode 100644 index 00000000000..5d5fa9f7b5f --- /dev/null +++ b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_hw.h @@ -0,0 +1,92 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fiopad_hw.h + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-02-18 08:29:05 + * Description:  This files is for the iopad register related definition + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhangyan 2023/7/3 first release + */ + +#ifndef FIOPAD_HW_H +#define FIOPAD_HW_H + +#include "fparameters.h" +#include "fkernel.h" +#include "fiopad.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + +/** @name X_reg0 Register + */ +#define FIOPAD_REG0_PULL_MASK GENMASK(9, 8) /* 上下拉配置 */ +#define FIOPAD_REG0_PULL_GET(x) GET_REG32_BITS((x), 9, 8) +#define FIOPAD_REG0_PULL_SET(x) SET_REG32_BITS((x), 9, 8) + +#define FIOPAD_REG0_DRIVE_MASK GENMASK(7, 4) /* 驱动能力配置 */ +#define FIOPAD_REG0_DRIVE_GET(x) GET_REG32_BITS((x), 7, 4) +#define FIOPAD_REG0_DRIVE_SET(x) SET_REG32_BITS((x), 7, 4) + +#define FIOPAD_REG0_FUNC_MASK GENMASK(2, 0) /* 引脚复用配置 */ +#define FIOPAD_REG0_FUNC_GET(x) GET_REG32_BITS((x), 2, 0) +#define FIOPAD_REG0_FUNC_SET(x) SET_REG32_BITS((x), 2, 0) + +/** @name X_reg1 Register + */ +#define FIOPAD_REG1_OUT_DELAY_EN BIT(8) +#define FIOPAD_REG1_OUT_DELAY_DELICATE_MASK GENMASK(11, 9) +#define FIOPAD_REG1_OUT_DELAY_DELICATE_GET(x) GET_REG32_BITS((x), 11, 9) /* 延时精调 */ +#define FIOPAD_REG1_OUT_DELAY_DELICATE_SET(x) SET_REG32_BITS((x), 11, 9) +#define FIOPAD_REG1_OUT_DELAY_ROUGH_MASK GENMASK(14, 12) +#define FIOPAD_REG1_OUT_DELAY_ROUGH_GET(x) GET_REG32_BITS((x), 14, 12) /* 延时粗调 */ +#define FIOPAD_REG1_OUT_DELAY_ROUGH_SET(x) SET_REG32_BITS((x), 14, 12) + +#define FIOPAD_REG1_IN_DELAY_EN BIT(0) +#define FIOPAD_REG1_IN_DELAY_DELICATE_MASK GENMASK(3, 1) +#define FIOPAD_REG1_IN_DELAY_DELICATE_GET(x) GET_REG32_BITS((x), 3, 1) /* 延时精调 */ +#define FIOPAD_REG1_IN_DELAY_DELICATE_SET(x) SET_REG32_BITS((x), 3, 1) +#define FIOPAD_REG1_IN_DELAY_ROUGH_MASK GENMASK(6, 4) +#define FIOPAD_REG1_IN_DELAY_ROUGH_GET(x) GET_REG32_BITS((x), 6, 4) /* 延时粗调 */ +#define FIOPAD_REG1_IN_DELAY_ROUGH_SET(x) SET_REG32_BITS((x), 6, 4) + +#define FIOPAD_ASSERT_REG0_OFF(pin) FASSERT_MSG((FIOPAD_REG0_END_OFFSET >= pin), "invalid reg0 offset @0x%x\r\n", (pin)) +#define FIOPAD_ASSERT_FUNC(func) FASSERT_MSG((func < FIOPAD_NUM_OF_FUNC), "invalid func as %d\r\n", (func)) +#define FIOPAD_ASSERT_PULL(pull) FASSERT_MSG((pull < FIOPAD_NUM_OF_PULL), "invalid pull as %d\r\n", (pull)) +#define FIOPAD_ASSERT_DRIVE(drive) FASSERT_MSG((drive < FIOPAD_NUM_OF_DRIVE), "invalid pull as %d\r\n", (drive)) + +#define FIOPAD_ASSERT_REG1_OFF(pin) FASSERT_MSG(((FIOPAD_REG1_BEG_OFFSET <= pin) && (FIOPAD_REG1_END_OFFSET >= pin)), "invalid reg1 offset @0x%x\r\n", (pin)) +#define FIOPAD_ASSERT_DELAY(delay) FASSERT_MSG((delay < FIOPAD_NUM_OF_DELAY), "invalid delay as %d\r\n", (delay)) + +#define FIOPAD_DELAY_MAX 15 + +/* 读FPWM寄存器 */ +#define FIOPAD_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)reg_offset) + +/* 写FPWM寄存器 */ +#define FIOPAD_WRITE_REG32(addr, reg_offset, reg_value) FtOut32((addr) + (u32)reg_offset, (u32)reg_value) + +/* print information of all iopad */ +void FIOPadDump(uintptr base_addr); + +#ifdef __cplusplus +} + +#endif +#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_sinit.c b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_sinit.c new file mode 100644 index 00000000000..65a8638bb64 --- /dev/null +++ b/bsp/phytium/libraries/standalone/drivers/iopad/fiopad/fiopad_sinit.c @@ -0,0 +1,53 @@ +/* + * Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fiopad_sinit.c + * Date: 2022-02-10 14:53:42 + * LastEditTime: 2022-02-18 09:01:10 + * Description:  This files is for getting default configuration of specific IOPad instance_id + * + * Modify History: + * Ver   Who         Date        Changes + * -----  ------      --------    -------------------------------------- + * 1.0 zhangyan 2023/7/3 first release + */ + +#include "fparameters.h" +#include "fassert.h" +#include "fiopad.h" + +extern FIOPadConfig FIOPadConfigTbl[FIOPAD_NUM]; + +/** + * @name: FIOPadLookupConfig + * @msg: get iopad configs by id + * @return {*} + * @param {u32} instanceId, id of iopad ctrl + */ +const FIOPadConfig *FIOPadLookupConfig(u32 instance_id) +{ + FASSERT(instance_id < FIOPAD_NUM); + const FIOPadConfig *pconfig = NULL; + u32 index; + + for (index = 0; index < (u32)FIOPAD_NUM; index++) + { + if (FIOPadConfigTbl[index].instance_id == instance_id) + { + pconfig = &FIOPadConfigTbl[index]; + break; + } + } + + return (const FIOPadConfig *)pconfig; +} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/drivers/ipc/Kconfig b/bsp/phytium/libraries/standalone/drivers/ipc/Kconfig index 2012b165d23..0f2f05ca01f 100644 --- a/bsp/phytium/libraries/standalone/drivers/ipc/Kconfig +++ b/bsp/phytium/libraries/standalone/drivers/ipc/Kconfig @@ -2,7 +2,7 @@ config ENABLE_FSEMAPHORE bool prompt "Use FSemaphore" default n - depends on TARGET_E2000S || TARGET_E2000D || TARGET_E2000Q + depends on TARGET_E2000S || TARGET_E2000D || TARGET_E2000Q || TARGET_T2000Q help Select FSemaphore driver component diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc.h index 80452f23490..56d59f533ba 100644 --- a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc.h +++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc.h @@ -27,22 +27,25 @@ /***************************** Include Files *********************************/ #include "ftypes.h" - -#include "fdcdp_param.h" +#include "fparameters.h" +#include "ferror_code.h" +#ifdef __cplusplus +extern "C" +{ +#endif /************************** Constant Definitions *****************************/ #define FMEDIA_DC_SUCCESS FT_SUCCESS -/************************** Constant Definitions *****************************/ - #define FDC_FALSE 0 #define FDC_TRUE 1 -#define FDCDP_PATH_NUM 2 + #define FDC_GOP_MAX_MODENUM 11 #define FDC_PCCON_BUFFER_SIZE (1 * 1024 * 1024) +/**************************** Type Definitions *******************************/ typedef enum { FDC_MULTI_MODE_CLONE = 0, @@ -121,8 +124,6 @@ typedef enum FDC_OUTPUT_RGB1010, } FDcOutputColor; -/**************************** Type Definitions *******************************/ - typedef struct { u32 instance_id; /* dc id */ @@ -133,8 +134,8 @@ typedef struct typedef struct { - u32 visble_line; /* Visible Number of lines */ u32 total_line; /* Total Number of lines. */ + u32 visble_line; /* Visible Number of lines */ u32 sync_start; /* Start of sync pulse. */ u32 sync_end; /* End of sync pulse. */ boolean sync_polarity; /* Polarity of the sync pulse.1 - positive , 0 - negative. */ @@ -150,7 +151,7 @@ typedef struct typedef struct { u32 color_format; /* color format. */ - uintptr framebuffer_p; /* Starting address of the frame buffer. */ + uintptr framebuffer_p; /* Starting address of the frame buffer. */ u32 tiling_mode; /* tile mode */ u32 yuv_type; /* unused , reserved */ u32 stride; /* memory image line span , --- FDcWidthToStride */ @@ -208,7 +209,7 @@ typedef struct typedef struct { boolean enable; - u64 phys_addr; /* Address of the cursor shape. */ + uintptr phys_addr; /* Address of the cursor shape. */ u32 type; /* Cursor type , 0 - disable , 1 - mask mode , 2 - argb mode. */ u32 x; /* X location of cursor's hotspot. */ u32 y; /* Y location of cursor's hotspot. */ @@ -221,9 +222,9 @@ typedef struct typedef struct { - u32 y_address; - u32 u_address; - u32 v_address; + uintptr y_address; + uintptr u_address; + uintptr v_address; u32 u_stride; u32 v_stride; u32 rot_angle; @@ -263,6 +264,32 @@ typedef struct FDcSyncParameter FDcSyncParameter; } FDcDtdTable; +typedef enum +{ + FDC_DISPLAY_ID_640_480 = 0, + FDC_DISPLAY_ID_800_600, + FDC_DISPLAY_ID_1024_768, + FDC_DISPLAY_ID_1280_720, + FDC_DISPLAY_ID_1366_768, + FDC_DISPLAY_ID_1920_1080, + FDC_DISPLAY_ID_1600_1200, + FDC_DISPLAY_ID_1280_800, + FDC_DISPLAY_ID_800_480, + FDC_DISPLAY_ID_1280_768, + FDC_DISPLAY_ID_1280_1024, + FDC_DISPLAY_ID_MAX_NUM + +} FDcDisplayId; + +typedef struct +{ + u32 width; + u32 height; + u32 color_depth; /* value follow the DISPLAY_REFRESH_RATE_XX */ + u32 refresh_rate; /* value follow the DISPLAY_COLOR_DEPTH_XX */ + FDcDisplayId id; +} FDcDisplaySetting; + typedef struct { FDcDtdTable dtd_table; /*the table of dtd params*/ @@ -274,22 +301,20 @@ typedef struct FDcDisplayDpMode dp_mode; FDcDisplayVideoMode video_mode; /*the params of video*/ FDcDisplayCursor cursor; + FDcDisplaySetting display_setting[FDC_DISPLAY_ID_MAX_NUM]; } FDcCurrentConfig; typedef struct { FDcCurrentConfig fdc_current_config; FDcConfig config; - u32 multimode; /* The display mode of the device , including clone, horizontal and vertical display*/ - + u32 multi_mode; /* The display mode of the device , including clone, horizontal and vertical display*/ } FDcCtrl; /************************** Function Prototypes ******************************/ /*Initialization of dc configuration parameter */ -FError FDcConfigInit(FDcCtrl *instance_p, FDcDpDisplaySetting *gop_mode, u32 mode_id); - -/* config to ddr */ +FError FDcConfigInit(FDcCtrl *instance_p, FDcDisplaySetting *gop_mode, u32 mode_id); /*config the panel data of core data */ void FDcPanelSetConfig(FDcCtrl *instance_p, boolean data_enable_polarity, boolean data_polarity, boolean clock_Polarity); @@ -299,6 +324,7 @@ void FDcDisplaySetHorizontal(FDcCtrl *instance_p, u32 mode_id, u32 total_pixels, /* set the vertical timing parameter */ void FDcDisplaySetVertical(FDcCtrl *instance_p, u32 mode_id, u32 line_pixels, u32 total_pixels, u32 vsync_start, u32 vsync_end, boolean vsync_polarity); + /* select core data about dc output mode , DP mode or DPI mode */ void FDcOutputSelect(FDcCtrl *instance_p, FDcPhyOutPutType output_type); @@ -314,8 +340,6 @@ void FDcFramebufferSetFramebuffer(FDcCtrl *instance_p, FDcDisplayVideoMode *fdc_ /* config core data about dither enable */ void FDcDitherEnable(FDcCtrl *instance_p, boolean enable); -/* update config */ - /* enable core data about gamma */ void FDcGammaEnable(FDcCtrl *instance_p, boolean enable); @@ -323,8 +347,6 @@ void FDcGammaEnable(FDcCtrl *instance_p, boolean enable); the main function interface to set the dc parameters*/ FError FDcCoreCommit(FDcCtrl *instance_p, u32 mode_id); -/* direct update config */ - /* commit display configuration about timing parameter*/ void FDcDisplayCommit(FDcCtrl *instance_p, u32 mode_id); @@ -337,8 +359,6 @@ void FDcPanelCommit(FDcCtrl *instance_p); /* config register about cursor parameter */ void FDcCursorCommit(FDcCtrl *instance_p); -/* cursor setting */ - /* enable the cursor */ void FDcCursorEnable(FDcCtrl *instance_p, boolean enable); @@ -351,9 +371,12 @@ void FDcCursorSetPos(FDcCtrl *instance_p, uintptr x, uintptr y); /* Config register about vedio parameter and framebuffer */ void FDcFramebufferCommit(FDcCtrl *instance_p); -/* common setting */ - /* according to the width, calculate the stride */ -FError FDcWidthToStride(u32 width, u32 color_depth, u32 multimode); +FError FDcWidthToStride(u32 width, u32 color_depth, u32 multi_mode); +#ifdef __cplusplus +} #endif + +#endif + diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_common_hw.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_common_hw.h index ca387a920bd..b931e8b5e3a 100644 --- a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_common_hw.h +++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_common_hw.h @@ -31,6 +31,13 @@ #include "ferror_code.h" #include "fdc.h" +#ifdef __cplusplus +extern "C" +{ +#endif + +/************************** Function Prototypes ******************************/ + /*set pixel clock in kilohertz unit by configurating register */ FError FDcReqChangePixel(FDcCtrl *instance_p, u32 pixel_clk); @@ -39,4 +46,10 @@ void FDcHwFramebufferReset(FDcCtrl *instance_p, u32 num, FDcRestType type); /* Get mode number by width and height */ FError FDcResToModeNum(u32 width, u32 height); + +#ifdef __cplusplus +} #endif + +#endif + diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_hw.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_hw.h index dfae755c13e..8584239d909 100644 --- a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_hw.h +++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdc_hw.h @@ -31,14 +31,16 @@ #include "ferror_code.h" #include "fkernel.h" -/**************************** Type Definitions *******************************/ +#ifdef __cplusplus +extern "C" +{ +#endif +/************************** Constant Definitions *****************************/ #define FDC_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)(reg_offset)) #define FDC_WRITE_REG32(addr, reg_value) FtOut32(addr, (u32)(reg_value)) #define FDC_PHY_ALIGN(data, Offset) ((data + Offset - 1) & ~(Offset - 1)) -/************************** Constant Definitions *****************************/ - /* AHB Byte Address DC Ctrl Register*/ @@ -102,6 +104,19 @@ DC Ctrl Register*/ #define FDC_GCREG_READ_OT 0xCC8 #define FDC_GCREG_DPCONFIG0 0xCD0 + +/*FDC_AQ_HI_CLOCK_CONTROL*/ + +#define FDC_AQ_HI_CLOCK_CORE_SOFT_RESET_DC1 BIT(18) +#define FDC_AQ_HI_CLOCK_CORE_SOFT_RESET_DC0 BIT(17) +#define FDC_AQ_HI_CLOCK_AXI_SOFT_RESET BIT(16) +#define FDC_AQ_HI_CLOCK_AHB_SOFT_RESET BIT(12) + +/*FDC_CTRL_CH1_PIXEL_CLOCK*/ +#define FDC_CTRL_PIXEL_CLOCK_CLEAR_MASK GENMASK(31,30) +#define FDC_CTRL_PIXEL_CLOCK_VALID BIT(31) +#define FDC_CTRL_PIXEL_CLOCK_ENABLE BIT(30) + /* FDC_GCREG_FRAMEBUFFER_SIZE0 */ #define FDC_GCREG_FRAMEBUFFER_SIZE0_HEIGHT_SET(x) SET_REG32_BITS((x), 29, 15) /* the height of window size of the framebuffer in memory - in pixels*/ #define FDC_GCREG_FRAMEBUFFER_SIZE0_WIDTH_SET(x) SET_REG32_BITS((x), 14, 0) /* the width of window size of the framebuffer in memory -in pixels*/ @@ -183,7 +198,7 @@ DC Ctrl Register*/ #define FDC_GCREG_DISPLAY_INTR_ENABLE_DC0_UNDERFLOW BIT(1) /* dc0 underflow interrupt enable */ #define FDC_GCREG_DISPLAY_INTR_ENABLE_DC0_INTR BIT(0) /* dc0 frame complete interrupt enable */ -/**************************************************************************************/ +/************************** Function Prototypes ******************************/ /* write the data to the channel of DcDp */ void FDcChannelRegWrite(uintptr addr, uintptr offset, u32 data); @@ -197,4 +212,11 @@ void FDcCtrlRegWrite(uintptr addr, uintptr offset, u32 data); /* read Dc control register */ FError FDcCtrlRegRead(uintptr addr, uintptr offset); +/*dump the dc info*/ +void FDcDump(uintptr address); + +#ifdef __cplusplus +} +#endif + #endif \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp.h index 0afce2cf4ac..9824536a55e 100644 --- a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp.h +++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp.h @@ -25,11 +25,22 @@ #ifndef FDCDP_H #define FDCDP_H -#include "fdc.h" -#include "fdp.h" #include "ftypes.h" #include "fparameters.h" -#include "fdcdp_param.h" +#include "fdc.h" +#include "fdp.h" + +/************************** Constant Definitions *****************************/ +#define FMEDIA_DEFAULT_PARAM_ERR FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 1) +#define FMEDIA_ERR_PIXEL FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 3) +#define FMEDIA_ERR_EDID FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 4) +#define FMEDIA_ERR_HPD_DISCONNECTED FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 5) +#define FMEDIA_AUX_CONNECT_FAILED FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 7) +#define FMEDIA_TRAIN_TIME_ERR FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 8) +#define FMEDIA_REACH_MAX_VOLTAGE FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 9) + +/************************** Constant Definitions *****************************/ +#define FMEDIA_DCDP_SUCCESS FT_SUCCESS #define FDP_DISPLAY_REFRESH_RATE_60 60 #define FDP_DISPLAY_REFRESH_RATE_59 59 @@ -47,28 +58,42 @@ #define FDP_CMD_STATE_OFFSET 28 #define FDP_LIGHT_VALUE_OFFSET 21 -#define FDP_ALL_CHANNEL 0xffffffff - #define FDP_MRAM_SIZE (3840 * 2160 * 4) +#ifdef __cplusplus +extern "C" +{ +#endif + + +/**************************** Type Definitions *******************************/ + + +/**************************** Type Definitions *******************************/ typedef enum { - FDCDP_HPD_IRQ_CONNECTED = 0, /* hpd 中断 */ - FDCDP_HPD_IRQ_DISCONNECTED, - FDCDP_AUX_REPLY_TIMEOUT, - FDCDP_AUX_REPLY_ERROR, + FDCDP_HPD_IRQ_CONNECTED = 0, /* dp disconnected */ + FDCDP_HPD_IRQ_DISCONNECTED, /*the dp disconnected*/ + FDCDP_AUX_REPLY_TIMEOUT, /*receive aux reply timeout*/ + FDCDP_AUX_REPLY_ERROR, /*the aux reply is invalid*/ FDCDP_INTR_MAX_NUM } FDcDpIntrEventType; +typedef enum +{ + FDCDP_CONNECT_TO_DISCONNCET = 0, + FDCDP_DISCONNCET_TO_CONNECT +} FDcDpConnectStatus; + typedef void (*FMediaIntrHandler)(void *param, u32 index); -typedef struct +typedef struct { - FDcDpIntrEventType type; /* data */ - FMediaIntrHandler handler; - void *param; + FDcDpIntrEventType type; /* the intr type */ + FMediaIntrHandler handler; + void *param; } FMediaIntrConfig; typedef struct @@ -77,39 +102,52 @@ typedef struct FDcCtrl dc_instance_p[FDCDP_INSTANCE_NUM]; /* fdp instace object */ FDpCtrl dp_instance_p[FDCDP_INSTANCE_NUM]; - /* user config */ - /* resolution */ - /* color depth */ - FDcDpDisplaySetting display_setting[FDCDP_DISPLAY_ID_MAX_NUM]; - /* gamma parameter */ - /* .... */ - /* uintptr fb_p[FDCDP_INSTANCE_NUM];*/ - u32 is_ready; /* Device is ininitialized and ready*/ + /* u8 *fb_config[FDCDP_INSTANCE_NUM];*/ + u8 *fb_config[FDCDP_INSTANCE_NUM]; + /*the intr config of dcdp*/ FMediaIntrConfig intr_event[FDCDP_INTR_MAX_NUM]; - - void *args; + /*connect status ,1 :connected,0:disconnected*/ u32 connect_flg[FDCDP_INSTANCE_NUM]; - u32 connect_changed_flg[FDCDP_INSTANCE_NUM]; + /* Device is ininitialized and ready*/ + u32 is_ready; } FDcDp; +/************************** Function Prototypes ******************************/ +/*set the dp static params*/ const FDpConfig *FDpLookupConfig(u32 instance_id); + +/*set the dc static params*/ const FDcConfig *FDcLookupConfig(u32 instance_id); + +/*init the dcdp*/ +FError FDcDpCfgInitialize(FDcDp *instance_p); + /*get the default config*/ -FError FDcDpGetDefaultConfig(FDcDp *instance_p, u32 channel_num); +FError FDcDpGetDefaultConfig(FDcDp *instance_p); + +/*the basic params init*/ +FError FDcDpSetBasicParam(FDcDp *instance_p, u32 width, u32 height,u32 color_depth, u32 refresh_rate); + +/* init the DcDp */ + +FError FDcDpInitial(FDcDp *instance_p, u32 channel, u32 width, u32 height, u32 color_depth, u32 multi_mode); +/* deinit the DcDp */ +FError FDcDpDeInitialize(FDcDp *instance_p, u32 id); /*register the interrupt*/ -void FDcDpRegisterHandler(FDcDp *instance_p, FMediaIntrConfig *intr_event_p); +void FDcDpRegisterHandler(FDcDp *instance_p, FDcDpIntrEventType type,FMediaIntrHandler handler,void *param); /*the interrupt handler*/ void FDcDpInterruptHandler(s32 vector, void *args); /*enable the interrupt*/ -void FDcDpIrqEnable(FDcDp *instance_p, FDcDpIntrEventType intr_event_p); +void FDcDpIrqEnable(FDcDp *instance_p,u32 index, FDcDpIntrEventType intr_event_p); -/* init the DcDp */ -FError FDcDpInitial(FDcDp *instance_p, u32 channel_num, u32 mode_id,u32 multi_mode); +/*the hotplug information*/ +void FDcDpHotPlug(FDcDp *instance_p, u32 index, FDcDpConnectStatus connect_status); -/*the basic params init*/ -FError FDcDpSetBasicParam(FDcDp *instance_p, u32 channel_num, u32 mode_id); +#ifdef __cplusplus +} +#endif #endif diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_multi_display.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_multi_display.h index 95893b121d0..1f1fc23dcfe 100644 --- a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_multi_display.h +++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_multi_display.h @@ -28,17 +28,29 @@ #include "ftypes.h" #include "fparameters.h" +#ifdef __cplusplus +extern "C" +{ +#endif +/**************************** Type Definitions *******************************/ typedef struct { - uintptr dp0_framebuffer;/* data */ - uintptr dp1_framebuffer; - u32 multi_mode; -} FDcDpFrameBuffer; + u32 channel; + u32 color_depth; + u32 width; + u32 height; + u32 multi_mode; + u8 *fb_config[FDCDP_INSTANCE_NUM]; + u32 connect[FDCDP_INSTANCE_NUM]; +} disp_parm; + +/************************** Function Prototypes ******************************/ +/*set the frambbufferconfig*/ -/*set the frambbuffer of multidisplay*/ -FError FDcDpMultiDisplayFrameBufferSet(FDcDp *instance_p, u32 channel_num, u32 multi_mode); +disp_parm *FDcDpMultiDisplayFrameBufferSet(u32 channel, u32 width,u32 height,u32 color_depth,u32 multi_mode); -/*return the framebuffer*/ -FDcDpFrameBuffer *FDcDpGetFramebuffer(FDcDp *instance_p); +#ifdef __cplusplus +} +#endif -#endif \ No newline at end of file +#endif diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_param.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_param.h deleted file mode 100644 index 0a11d981839..00000000000 --- a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdcdp_param.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fdcdp_param.h - * Date: 2022-09-05 17:31:47 - * LastEditTime: 2022-09-05 17:31:47 - * Description: This file is for providing some general config and params of dc and dp - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------ -------- -------------------------------------- - * 1.0 Wangzq 2022/12/20 Modify the format and establish the version - */ - -#ifndef FDCDP_PARAM_H -#define FDCDP_PARAM_H - -#include "ftypes.h" -#include "fparameters.h" -#include "ferror_code.h" - -#define FMEDIA_DEFAULT_PARAM_ERR FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 1) -#define FMEDIA_ERR_PIXEL FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 3) -#define FMEDIA_ERR_EDID FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 4) -#define FMEDIA_ERR_HPD_DISCONNECTED FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 5) -#define FMEDIA_AUX_CONNECT_FAILED FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 7) -#define FMEDIA_TRAIN_TIME_ERR FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 8) -#define FMEDIA_REACH_MAX_VOLTAGE FT_MAKE_ERRCODE(ErrModBsp, ErrBspMEDIA, 9) - -typedef enum -{ - FDCDP_DISPLAY_ID_640_480 = 0, - FDCDP_DISPLAY_ID_800_600, - FDCDP_DISPLAY_ID_1024_768, - FDCDP_DISPLAY_ID_1280_720, - FDCDP_DISPLAY_ID_1366_768, - FDCDP_DISPLAY_ID_1920_1080, - FDCDP_DISPLAY_ID_1600_1200, - FDCDP_DISPLAY_ID_1280_800, - FDCDP_DISPLAY_ID_800_480, - FDCDP_DISPLAY_ID_1280_768, - FDCDP_DISPLAY_ID_1280_1024, - FDCDP_DISPLAY_ID_MAX_NUM - -} FDcDpDisplayId; -typedef struct -{ - u32 width; - u32 height; - u32 color_depth; /* value follow the DISPLAY_REFRESH_RATE_XX */ - u32 refresh_rate; /* value follow the DISPLAY_COLOR_DEPTH_XX */ - FDcDpDisplayId id; -} FDcDpDisplaySetting; - - -#endif \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp.h index e6f6c215614..b6795e9a317 100644 --- a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp.h +++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp.h @@ -29,13 +29,15 @@ #include "ftypes.h" #include "fparameters_comm.h" -#include "fdcdp_param.h" #include "fdc.h" - +#include "ferror_code.h" +#ifdef __cplusplus +extern "C" +{ +#endif /************************** Constant Definitions *****************************/ #define FMEDIA_DP_SUCCESS FT_SUCCESS - -/************************** Constant Definitions *****************************/ +#define FMEDIA_DP_FAILED 1 #define FDP_HAS_TRAINED 1 #define FDP_NOT_TRAINED 0 @@ -46,8 +48,12 @@ #define FDP_DIS_CONNECTED 1 #define FDP_IS_CONNECTED 0 +#define FDP_TRAIN_SUCCESS 0 +#define FDP_TRAIN_FAILED 1 + #define DP_GOP_MAX_MODENUM 11 +/**************************** Type Definitions *******************************/ typedef enum { FDP_TRAINING_OFF = 0, @@ -74,16 +80,16 @@ typedef enum typedef struct { - u16 h_total; - u16 v_total; + u16 h_total; /* Horizontal total lines. */ + u16 v_total; /* Vertical total lines. */ boolean h_polarity; /*0 - active high , 1 - active low */ boolean v_polarity; /*0 - active high , 1 - active low */ u16 hs_width; /* Horizontal Sync Pulse Width in pixels. */ u16 vs_width; /* Vertical Sync Pulse Width in lines. */ u16 h_res; /* Horizontal Addressable video in lines. */ u16 v_res; /* Vertical Addressable video in lines. */ - u16 h_start; /* Horizontal Blanking in pixels minus Horizontal Front Proch in pixels. */ - u16 v_start; /* Vertical Blanking in pixels minus Vertical Front Proch in pixels. */ + u16 h_start; /* Horizontal Blanking in pixels minus */ + u16 v_start; /* Vertical Blanking in pixels minus */ boolean h_user_polarity; /* Horizontal Sync Polarity. */ boolean v_user_polarity; /* Vertical Sync Polarity. */ } FDpSyncParameter; @@ -126,9 +132,9 @@ typedef struct FDpStatus status; u8 down_spread_enable; -#define dtd_list_max 4 +#define DTD_MAX 4 /* edid 缓冲数据 */ - FDpDtdTable dtd_table[dtd_list_max]; /* the max dtd num is 4 */ + FDpDtdTable dtd_table[DTD_MAX]; /* the max dtd num is 4 */ } FDpCurrentConfig; @@ -146,11 +152,13 @@ typedef struct FDpConfig config; } FDpCtrl; +/************************** Function Prototypes ******************************/ + /* dp init */ -FError FDpInit(FDcCtrl *dc_config, FDpCtrl *instance_p, FDcDpDisplaySetting *gop_mode, u32 mode_id); +FError FDpInit(FDcCtrl *dc_config, FDpCtrl *dp_config, FDcDisplaySetting *gop_mode, u32 mode_id); /* Initialization of dp configuration parameter */ -void FDpConfigInit(FDpCtrl *instance_p, FDcDpDisplaySetting *gop_mode); +void FDpConfigInit(FDpCtrl *instance_p, FDcDisplaySetting *gop_mode); /* Dp connect to sink */ FError FDpConnect(FDpCtrl *instance_p); @@ -168,8 +176,6 @@ FError FDpConfigTraingPattern(FDpCtrl *instance_p); stream attributes configuration*/ void FDpConfigMainStreamAttr(FDpCtrl *instance_p, FDpTransmissionConfig *fdp_trans_config, FDpSyncParameter *fdp_sync_config); -/*Dp link training*/ - /*Set sink device to D0(normal operation mode).*/ FError FDpWakeUpSink(FDpCtrl *instance_p); @@ -187,4 +193,9 @@ FError FDpCheckTrainingStatus(FDpCtrl *instance_p, u8 lane_count, u8 tpsn, u8 *v /*Check the HPD status*/ FError FDpCheckHpdStatus(FDpCtrl *instance_p); +#ifdef __cplusplus +} #endif + +#endif + diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_aux.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_aux.h index 276b0dafb4e..6b85ce047ba 100644 --- a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_aux.h +++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_aux.h @@ -27,26 +27,35 @@ /***************************** Include Files *********************************/ #include "ftypes.h" - +#include "fdp.h" +#ifdef __cplusplus +extern "C" +{ +#endif +/************************** Constant Definitions *****************************/ #define AUX_TIMEOUT 1 #define AUX_CONNECT 0 -#define dtd_list_max 4 +#define DTD_MAX 4 +/**************************** Type Definitions *******************************/ typedef struct { - u32 pixel_clock; - u32 hor_pixel; - u32 ver_pixel; - u32 hor_blanking; - u32 ver_blanking; - u32 hor_sync_front; - u32 ver_sync_front; - u32 hor_sync_width; - u32 ver_sync_width; - u8 hor_polarity; - u8 ver_polarity; + u32 pixel_clock; /* pixel clock frequence in megahertz unit */ + u32 hor_pixel; /* Horizontal total lines. */ + u32 ver_pixel; /* Vertical total lines. */ + u32 hor_blanking; /* Horizontal Blanking in pixels minus*/ + u32 ver_blanking; /* Vertical Blanking in pixels minus*/ + u32 hor_sync_front; /*Horizontal Front Proch in pixels. */ + u32 ver_sync_front; /*vertical Front Proch in pixels. */ + u32 hor_sync_width; /* Horizontal Sync Pulse Width in pixels. */ + u32 ver_sync_width; /* Vertical Sync Pulse Width in lines. */ + u8 hor_polarity; /*0 - active high , 1 - active low */ + u8 ver_polarity; /*0 - active high , 1 - active low */ } Auxtable; + +/************************** Function Prototypes ******************************/ + /*Initialize AUX channel include aux clock Initialization, dp timer Initialization and interrupt mask. */ FError FDpInitAux(FDpCtrl *instance_p); @@ -55,16 +64,16 @@ FError FDpInitAux(FDpCtrl *instance_p); FError FDpWaitAuxReply(FDpCtrl *instance_p); /*translate the dp information the dpsync*/ -FError FDpTimingToDpSync(Auxtable *instance_p, FDpSyncParameter *sync); +FError FDpTimingToDpSync(Auxtable *list, FDpSyncParameter *sync); /*translate the dc information the dcsync*/ -FError FDpTimingToDcSync(Auxtable *instance_p, FDcSyncParameter *sync); +FError FDpTimingToDcSync(Auxtable *list, FDcSyncParameter *sync); /* write phy register through aux channel.*/ -FError FDpSinkDpcdWrite(FDpCtrl *instance_p, u32 addr, u8 data); +FError FDpSinkDpcdWrite(FDpCtrl *instance_p, uintptr addr, u8 data); /* Read phy register through aux channel. */ -FError FDpSinkDpcdRead(FDpCtrl *instance_p, u32 addr, u8 *data); +FError FDpSinkDpcdRead(FDpCtrl *instance_p, uintptr addr, u8 *data); /* Get edid information form sink*/ FError FDpGetEdid(FDpCtrl *instance_p, u8 *buffer); @@ -72,4 +81,8 @@ FError FDpGetEdid(FDpCtrl *instance_p, u8 *buffer); /*translate the edid information to the struct*/ FError FDpParseDpEdidDtdList(u8 *buffer, Auxtable *list); +#ifdef __cplusplus +} +#endif + #endif diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_hw.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_hw.h index 89fb78e6a7b..98787e42e4d 100644 --- a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_hw.h +++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_hw.h @@ -31,7 +31,11 @@ #include "fio.h" #include "fkernel.h" -/****************************************************************************/ +#ifdef __cplusplus +extern "C" +{ +#endif +/************************** Constant Definitions *****************************/ /** * This macro writes the given register. * @param base_addr is the base address of the device. @@ -97,6 +101,11 @@ #define FDP_TX_AUX_TRANSACTION_STATUS 0x014C #define FDP_TX_TIMER 0x0158 +/*FDPTX_MAIN_LINK_MISC0*/ +#define FDPTX_MAIN_LINK_MISC0_CLOCK_MODE BIT(0) +#define FDPTX_MAIN_LINK_MISC0_COLOR_FORMAT GENMASK(2,1) +#define FDPTX_MAIN_LINK_MISC0_BIT_DEPTH GENMASK(7,5) + /* Main Link registers */ @@ -127,11 +136,11 @@ #define FDP_TX_HPD_INTR_MASK BIT(1) //hpd irq 中断 #define FDP_TX_HPD_EVENT_MASK BIT(0)//HPD 连接或断开事件 中断 -#define FDP_TX_STATUS_AUX_ERROR BIT(6) -#define FDP_TX_STATUS_GP_TIME BIT(4) +#define FDP_TX_STATUS_AUX_ERROR BIT(6) +#define FDP_TX_STATUS_GP_TIME BIT(4) #define FDP_TX_STATUS_AUX_TIMEOUT BIT(3) -#define FDP_TX_STATUS_AUX_RECEIVED BIT(2) -#define FDP_TX_STATUS_HPD_INTR BIT(1) +#define FDP_TX_STATUS_AUX_RECEIVED BIT(2) +#define FDP_TX_STATUS_HPD_INTR BIT(1) #define FDP_TX_STATUS_HPD_EVENT BIT(0) /* @@ -142,6 +151,9 @@ #define FDPTX_EDP_CRC_GREEN 0x01D8 #define FDPTX_EDP_CRC_BLUE 0x01DC + +/************************** Function Prototypes ******************************/ + /* write the data to the channel of dp */ void FDpChannelRegWrite(uintptr addr, uintptr offset, u32 data); @@ -149,9 +161,16 @@ void FDpChannelRegWrite(uintptr addr, uintptr offset, u32 data); FError FDpChannelRegRead(uintptr addr, uintptr offset); /* write FdpPhy control register */ -void FDpPhyRegWrite(uintptr addr,uintptr offset, u32 data); +void FDpPhyRegWrite(uintptr addr, uintptr offset, u32 data); /* read FdpPhy control register */ FError FDpPhyRegRead(uintptr addr, uintptr offset); -#endif \ No newline at end of file +/*dump the dp info*/ +void FDpDump(uintptr address); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_phy.h b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_phy.h index c8316b89427..56f99efe383 100644 --- a/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_phy.h +++ b/bsp/phytium/libraries/standalone/drivers/media/fdcdp_lib/inc/fdp_phy.h @@ -25,6 +25,12 @@ #define FDP_PHY_H #include "fdp.h" + +#ifdef __cplusplus +extern "C" +{ +#endif +/************************** Constant Definitions *****************************/ /* ** DPCD Address */ @@ -310,6 +316,8 @@ #define PHY_PMA_CMN_CTRL2 0x38004 #define PHY_PMA_PLL_RAW_CTRL 0x3800c +/************************** Function Prototypes ******************************/ + FError FDptxPhyGetLaneCount(FDpCtrl *instance_p, u8 *lanecount); FError FDpTxPhyGetLinkRate(FDpCtrl *instance_p, u32 *linkrate); @@ -318,25 +326,25 @@ FError FDpTxPhyGetLinkRate(FDpCtrl *instance_p, u32 *linkrate); void FDpLinkPhyChangeRate(FDpCtrl *instance_p, u32 link_rate); /* Get sink ENHANCED_FRAME_CAP */ -FError FDpTxPhyGetEnhancedFrameCap(FDpCtrl *instance_p); +u8 FDpTxPhyGetEnhancedFrameCap(FDpCtrl *instance_p); /* configure the PHY for the specified link rate */ FError FDpTxPhyUpdateLinkRate(FDpCtrl *instance_p, u32 link_rate); /* set the lane count in the PHY */ -void FDpTxPhySetLaneCount(FDpCtrl *instance_p, u32 lane_count); +void FDpTxPhySetLaneCount(FDpCtrl *instance_p, u8 lane_count); /*Get voltage swing of a specified lane.Voltage swing has three levels*/ -FError FDpTxSourceVswingForValue(FDpCtrl *instance_p, u8 lane_num); +u8 FDpTxSourceVswingForValue(FDpCtrl *instance_p, u8 lane_num); /* Get pre-emphasis level of a specified lane*/ -FError FDpTxSourcePreemphasisForValue(FDpCtrl *instance_p, u8 lane_num); +u8 FDpTxSourcePreemphasisForValue(FDpCtrl *instance_p, u8 lane_num); /* Get sink TPS4 support.*/ -FError FDpTxPhyTps4Supported(FDpCtrl *instance_p); +u8 FDpTxPhyTps4Supported(FDpCtrl *instance_p); /* Get sink TPS3 support.*/ -FError FDpTxPhyTps3Supported(FDpCtrl *instance_p); +u8 FDpTxPhyTps3Supported(FDpCtrl *instance_p); /* Get Swing and pre-emphasis level form sink*/ FError FDpTxPhyGetAdjustRequest(FDpCtrl *instance_p, u8 *swing, u8 *pre_emphasis); @@ -346,4 +354,9 @@ void FDpLinkPhyInit(FDpCtrl *instance_p, u32 link_rate); /* Voltage swing and pre-emphasis training.*/ void FDpLinkPhyChangeVsWing(FDpCtrl *instance_p, u32 vswing, u32 pre_emphasis); + +#ifdef __cplusplus +} +#endif + #endif diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.c index 51e20c0a5c1..6878e6af5d6 100644 --- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.c +++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.c @@ -122,7 +122,6 @@ FError FSdioSetClkFreq(FSdio *const instance_p, u32 input_clk_hz) { FASSERT(instance_p); uintptr base_addr = instance_p->config.base_addr; - u32 reg_val; u32 div = 0xff, drv = 0, sample = 0; u32 first_uhs_div, tmp_ext_reg, div_reg; FError ret = FSDIO_SUCCESS; @@ -222,34 +221,6 @@ u32 FSdioGetClkFreq(FSdio *const instance_p) return real_clk_hz; } -/** - * @name: FSdioWaitClkReady - * @msg: Wait clock ready after modify clock setting - * @return {FError} FSDIO_SUCCESS if wait success, FSDIO_ERR_TIMEOUT if wait timeout - * @param {uintptr} base_addr, base address of SDIO controller - * @param {int} retries, retry times in waiting - */ -static FError FSdioWaitClkReady(uintptr base_addr, int retries) -{ - FASSERT(retries > 1); - u32 reg_val = 0; - - do - { - reg_val = FSDIO_READ_REG(base_addr, FSDIO_GPIO_OFFSET); - } - while (!(reg_val & FSDIO_CLK_READY) && (retries-- > 0)); - - if (!(reg_val & FSDIO_CLK_READY) && (retries <= 0)) - { - FSDIO_ERROR("Wait clk ready timeout !!! status: 0x%x", - reg_val); - return FSDIO_ERR_TIMEOUT; - } - - return FSDIO_SUCCESS; -} - /** * @name: FSdioUpdateExternalClk * @msg: update uhs clock value and wait clock ready @@ -443,11 +414,6 @@ static FError FSdioReset(FSdio *const instance_p) u32 reg_val; FError ret = FSDIO_SUCCESS; - /* set creg_nand_mmcsd DMA path */ - FSDIO_INFO("Prev LSD CFG: 0x%x", FtIn32(FLSD_CONFIG_BASE + FLSD_NAND_MMCSD_HADDR)); - FtOut32(FLSD_CONFIG_BASE + FLSD_NAND_MMCSD_HADDR, 0x0U); - FSDIO_INFO("Curr LSD CFG: 0x%x", FtIn32(FLSD_CONFIG_BASE + FLSD_NAND_MMCSD_HADDR)); - /* set fifo */ reg_val = FSDIO_FIFOTH(FSDIO_FIFOTH_DMA_TRANS_8, FSDIO_RX_WMARK, FSDIO_TX_WMARK); FSDIO_WRITE_REG(base_addr, FSDIO_FIFOTH_OFFSET, reg_val); @@ -550,7 +516,6 @@ FError FSdioRestart(FSdio *const instance_p) { FASSERT(instance_p); uintptr base_addr = instance_p->config.base_addr; - u32 reg_val; FError ret = FSDIO_SUCCESS; if (FT_COMPONENT_IS_READY != instance_p->is_ready) diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.h b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.h index a2e2fed38fd..3560a65c791 100644 --- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.h +++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio.h @@ -116,12 +116,14 @@ typedef struct typedef struct { volatile FSdioIDmaDesc *first_desc; /* first descriptor in the list */ + volatile uintptr first_desc_p; u32 desc_num; /* num of descriptors in the list */ } FSdioIDmaDescList; /* SDIO DMA descriptors list */ typedef struct { u8 *buf; /* trans buffer */ + uintptr buf_p; u32 blksz; /* card block size */ u32 blkcnt; /* num of block in trans */ u32 datalen; /* bytes in trans */ diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_cmd.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_cmd.c index 8c163b40f0a..32f253d6d02 100644 --- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_cmd.c +++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_cmd.c @@ -194,7 +194,6 @@ FError FSdioGetCmdResponse(FSdio *const instance_p, FSdioCmdData *const cmd_data FASSERT(instance_p); FASSERT(cmd_data_p); FError ret = FSDIO_SUCCESS; - u32 reg_val; const boolean read = cmd_data_p->flag & FSDIO_CMD_FLAG_READ_DATA; uintptr base_addr = instance_p->config.base_addr; diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_dma.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_dma.c index 549f48652ab..ea9d8719d74 100644 --- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_dma.c +++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_dma.c @@ -29,7 +29,6 @@ #include "fassert.h" #include "ftypes.h" - #include "fsdio_hw.h" #include "fsdio.h" @@ -126,10 +125,10 @@ static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p cur_desc->len = FSDIO_IDMAC_DES2_BUF1_SIZE(data_p->blksz) | FSDIO_IDMAC_DES2_BUF2_SIZE(0U); /* set data buffer for transfer */ - buff_addr = (uintptr)data_p->buf + (uintptr)(loop * data_p->blksz); + buff_addr = data_p->buf_p + (uintptr)(loop * data_p->blksz); if (buff_addr % data_p->blksz) /* make sure buffer aligned and not cross page boundary */ { - FSDIO_ERROR("Data buffer 0x%x do not align.", buff_addr); + FSDIO_ERROR("Data buffer 0x%x do not align to %d.", buff_addr, data_p->blksz); return FSDIO_ERR_DMA_BUF_UNALIGN; } @@ -142,7 +141,7 @@ static FError FSdioSetupDMADescriptor(FSdio *const instance_p, FSdioData *data_p #endif /* set address of next descriptor entry, NULL for last entry */ - desc_addr = is_last ? 0U : (uintptr)&instance_p->desc_list.first_desc[loop + 1]; + desc_addr = is_last ? 0U : (instance_p->desc_list.first_desc_p + (uintptr)((loop + 1) * sizeof(FSdioIDmaDesc))); if (desc_addr % sizeof(FSdioIDmaDesc)) /* make sure dma descriptor aligned and not cross page boundary */ { FSDIO_ERROR("dma descriptor 0x%x do not align.", desc_addr); @@ -197,7 +196,7 @@ static FError FSdioDMATransferData(FSdio *const instance_p, FSdioData *data_p) data_p->blksz); /* set transfer info to register */ - FSdioSetDescriptor(base_addr, (uintptr)(instance_p->desc_list.first_desc)); + FSdioSetDescriptor(base_addr, instance_p->desc_list.first_desc_p); FSdioSetTransBytes(base_addr, data_p->datalen); FSdioSetBlockSize(base_addr, data_p->blksz); @@ -377,6 +376,7 @@ FError FSdioSetIDMAList(FSdio *const instance_p, volatile FSdioIDmaDesc *desc, u } instance_p->desc_list.first_desc = desc; + instance_p->desc_list.first_desc_p = (uintptr)desc; /* physical address equals with virtual address */ instance_p->desc_list.desc_num = desc_num; return ret; } \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_hw.h b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_hw.h index 33a7edf1937..80832d0fa3f 100644 --- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_hw.h +++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_hw.h @@ -37,7 +37,7 @@ #ifdef __aarch64__ #include "faarch64.h" #else -#include "fcp15.h" +#include "faarch32.h" #endif #ifdef __cplusplus diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_intr.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_intr.c index 4cd69976343..eff362f66bf 100644 --- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_intr.c +++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_intr.c @@ -168,7 +168,7 @@ void FSdioInterruptHandler(s32 vector, void *param) FSDIO_WRITE_REG(base_addr, FSDIO_DMAC_STATUS_OFFSET, dmac_events); if (((events & event_mask) == 0) && - ((dmac_events & dmac_evt_mask == 0))) + (((dmac_events & dmac_evt_mask) == 0))) { return; /* no need to handle interrupt */ } diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_pio.c b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_pio.c index 488f10be0c2..37aaebc4de2 100644 --- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_pio.c +++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdio/fsdio_pio.c @@ -202,7 +202,6 @@ FError FSdioPollWaitPIOEnd(FSdio *const instance_p, FSdioCmdData *const cmd_data FASSERT(instance_p); FASSERT(cmd_data_p); FError ret = FSDIO_SUCCESS; - u32 loop; u32 reg_val; int delay; const boolean read = cmd_data_p->flag & FSDIO_CMD_FLAG_READ_DATA; diff --git a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.h b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.h index 82220a99fcf..3572d88859b 100644 --- a/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.h +++ b/bsp/phytium/libraries/standalone/drivers/mmc/fsdmmc/fsdmmc_hw.h @@ -34,7 +34,7 @@ #ifdef __aarch64__ #include "faarch64.h" #else -#include "fcp15.h" +#include "faarch32.h" #endif #ifdef __cplusplus diff --git a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.c b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.c index 93f3aa6c92d..bd256f5cb60 100644 --- a/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.c +++ b/bsp/phytium/libraries/standalone/drivers/pcie/fpcie/fpcie.c @@ -319,6 +319,7 @@ int FPcieAutoRegionAllocate(struct FPcieRegion *res, pci_size_t size, +/* This function uses BAR to request IO or MMIO space and configure the expansion ROM address */ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num, struct FPcieRegion *mem, struct FPcieRegion *prefetch, struct FPcieRegion *io, @@ -335,6 +336,7 @@ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num, int found_mem64 = 0; u16 class; + /* Command register: enable or disable the access to I/O and memory */ FPcieEcamReadConfig16bit(instance_p->config.ecam, bdf, FPCIE_COMMAND_REG, &cmdstat); cmdstat = (cmdstat & ~(FPCIE_COMMAND_IO | FPCIE_COMMAND_MEMORY)) | FPCIE_COMMAND_MASTER; @@ -361,6 +363,7 @@ void FPcieAutoSetupDevice(FPcie *instance_p, u32 bdf, int bars_num, /* Check the BAR type and set our address mask */ if (bar_response & FPCIE_BASE_ADDRESS_SPACE) { + /* formula to get addr space of BAR */ bar_size = ((~(bar_response & FPCIE_BASE_ADDRESS_IO_MASK)) & 0xffff) + 1; if (!enum_only) @@ -779,10 +782,10 @@ FError FPcieBindBusDevices(FPcie *instance_p, u32 bus_num, u32 parent_bdf, struc sprintf(buf_bdf_print, "pci_%x:%x:%x", FPCIE_BUS(parent_bdf), FPCIE_DEV(parent_bdf), FPCIE_FUNC(parent_bdf)); } - printf(" %02x:%02x.%02x - %04lx:%04lx %s", + printf("\t%02x:%02x.%02x\t\t%04lx:%04lx\t\t%s", FPCIE_BUS(bdf), FPCIE_DEV(bdf), FPCIE_FUNC(bdf), vendor, device, buf_bdf_print); - printf(" 0x%.2x (%s)\n", (int)class_show, FPcieClassStr(class_show)); + printf("\t\t\t0x%.2x (%s)\n", (int)class_show, FPcieClassStr(class_show)); /* ARI function handle */ /* step 1: detect if PCI Express Device */ @@ -849,5 +852,7 @@ FError FPcieScanBus(FPcie *instance_p, u32 bus_num, u32 parent_bdf) } } instance_p->is_scaned = 1; //表示已经扫描完成 + + return FT_SUCCESS; } diff --git a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.c b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.c index 5bb2edbdcae..a48064cd40e 100644 --- a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.c +++ b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.c @@ -393,7 +393,7 @@ FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output) FASSERT_MSG(instance->is_ready == FT_COMPONENT_IS_READY, "gpio instance is not yet inited !!!"); FGpioPinId index = pin->index; - u32 base_addr = instance->config.base_addr; + uintptr base_addr = instance->config.base_addr; u32 reg_val; if (FGPIO_DIR_OUTPUT != FGpioGetDirection(pin)) diff --git a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.h b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.h index 8d190b70085..3aeee3f91fb 100644 --- a/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.h +++ b/bsp/phytium/libraries/standalone/drivers/pin/fgpio/fgpio.h @@ -104,8 +104,8 @@ typedef enum typedef enum { - FGPIO_IRQ_TYPE_EDGE_FALLING = 0, /* 上升沿中断，引脚检测到电平从低变高时触发 */ - FGPIO_IRQ_TYPE_EDGE_RISING, /* 下降沿中断，引脚检测到电平从高变低时触发 */ + FGPIO_IRQ_TYPE_EDGE_FALLING = 0, /* 下降沿中断，引脚检测到电平从高变低时触发 */ + FGPIO_IRQ_TYPE_EDGE_RISING, /* 上升沿中断，引脚检测到电平从低变高时触发 */ FGPIO_IRQ_TYPE_LEVEL_LOW, /* 低电平中断，引脚电平为低时触发 */ FGPIO_IRQ_TYPE_LEVEL_HIGH /* 高电平中断，引脚电平为高时触发 */ } FGpioIrqType; /* GPIO引脚中断类型 */ diff --git a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.h b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.h index 7050ba4a647..0c28cf086e2 100644 --- a/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.h +++ b/bsp/phytium/libraries/standalone/drivers/pwm/fpwm/fpwm_hw.h @@ -50,6 +50,7 @@ extern "C" /* DB register */ #define FPWM_DB_CTRL_OFFSET 0x00 #define FPWM_DB_DLY_OFFSET 0x04 + #define FPWM_OFFSET 0x400 #define FPWM_TIM_CNT_OFFSET 0x00 #define FPWM_TIM_CTRL_OFFSET 0x04 diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.c b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.c index 5e7e5d876c2..78b32a4cc3c 100644 --- a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.c +++ b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.c @@ -76,7 +76,7 @@ FError FQspiFlashDetect(FQspiCtrl *pctrl) ret = FQspiFlashSpecialInstruction(pctrl, FQSPI_FLASH_CMD_RDID, flash_id, sizeof(flash_id)); if (FQSPI_SUCCESS != ret) { - FQSPI_ERROR("Read flash id failed, ret 0x%x\r\n", ret); + FQSPI_INFO("Read flash id failed, ret 0x%x\r\n", ret); return ret; } @@ -86,7 +86,7 @@ FError FQspiFlashDetect(FQspiCtrl *pctrl) } else { - FQSPI_ERROR("The Detected CSN%d flash is not matched", index); + FQSPI_INFO("The Detected CSN%d flash is not matched", index); } for (i = 0; i < sizeof(flash_info_table) / sizeof(FQspiFlashInfo); i++) @@ -108,7 +108,7 @@ FError FQspiFlashDetect(FQspiCtrl *pctrl) if (i == sizeof(flash_info_table) / sizeof(FQspiFlashInfo) && flash_id[0] != 0xff) { - FQSPI_ERROR("The Detected CSN%d flash not detected, id = 0x%x, 0x%x, 0x%x\r\n", index, flash_id[0], flash_id[1], flash_id[2]); + FQSPI_INFO("The Detected CSN%d flash not detected, id = 0x%x, 0x%x, 0x%x\r\n", index, flash_id[0], flash_id[1], flash_id[2]); } } @@ -478,7 +478,7 @@ FError FQspiFlashReadDataConfig(FQspiCtrl *pctrl, u8 command) pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3; pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_2_2; pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE; - + pctrl->rd_cfg.dummy = 4; if (pctrl->mf_id == FQSPI_FLASH_MF_ID_CYPRESS) { pctrl->rd_cfg.mode_byte = 0x1; @@ -502,6 +502,8 @@ FError FQspiFlashReadDataConfig(FQspiCtrl *pctrl, u8 command) pctrl->rd_cfg.rd_addr_sel = FQSPI_ADDR_SEL_3; pctrl->rd_cfg.rd_transfer = FQSPI_TRANSFER_1_4_4; pctrl->rd_cfg.rd_latency = FQSPI_CMD_LATENCY_ENABLE; + + pctrl->rd_cfg.dummy = 6; if (pctrl->mf_id == FQSPI_FLASH_MF_ID_CYPRESS) { @@ -615,8 +617,11 @@ FError FQspiFlashWriteData(FQspiCtrl *pctrl, u8 command, u32 chip_addr, const u8 switch (command) { case FQSPI_FLASH_CMD_PP: + pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_3; + break; case FQSPI_FLASH_CMD_QPP: pctrl->wr_cfg.wr_addr_sel = FQSPI_ADDR_SEL_3; + pctrl->wr_cfg.wr_transfer = FQSPI_TRANSFER_1_1_4; break; case FQSPI_FLASH_CMD_4PP: case FQSPI_FLASH_CMD_4QPP: diff --git a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.h b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.h index 0c74afa5c01..5eae7a10281 100644 --- a/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.h +++ b/bsp/phytium/libraries/standalone/drivers/qspi/fqspi/fqspi_flash.h @@ -47,6 +47,7 @@ extern "C" #define FQSPI_FLASH_MF_ID_CYPRESS 0x01 #define FQSPI_FLASH_MF_ID_GIGADEVICE 0xC8 #define FQSPI_FLASH_MF_ID_BOYA 0x68 +#define FQSPI_FLASH_MF_ID_WINBOND 0xEF /* qspi flash supported information table */ #define FQSPI_FLASH_INFO_TABLE \ @@ -60,7 +61,8 @@ extern "C" {"GD25QL256D", FQSPI_FLASH_MF_ID_GIGADEVICE, 0x60, 0x19, FQSPI_FLASH_CAP_32MB}, \ {"BY25Q64BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x17, FQSPI_FLASH_CAP_8MB}, \ {"BY25Q128BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x18, FQSPI_FLASH_CAP_16MB}, \ - {"BY25Q32BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x16, FQSPI_FLASH_CAP_4MB} \ + {"BY25Q32BS", FQSPI_FLASH_MF_ID_BOYA, 0x40, 0x16, FQSPI_FLASH_CAP_4MB}, \ + {"W25Q128", FQSPI_FLASH_MF_ID_WINBOND, 0x40, 0x18, FQSPI_FLASH_CAP_16MB} \ } #define FQSPI_FLASH_CMD_WRR 0x01 /* Write status register */ @@ -107,8 +109,8 @@ extern "C" #define FQSPI_BUSY_TIMEOUT_US 1000000 #define FQSPI_NOR_FLASH_STATE_BUSY BIT(0) -#define FQSPI_FLASH_WP_ENABLE 0x7c /* Write status register 2 */ -#define FQSPI_FLASH_WP_DISABLE 0x00 /* Write status register 2 */ +#define FQSPI_FLASH_WP_ENABLE 0x7c +#define FQSPI_FLASH_WP_DISABLE 0x00 /* Read some flash information */ FError FQspiFlashSpecialInstruction(FQspiCtrl *pctrl, u8 cmd, u8 *buf, size_t len); diff --git a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.c b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.c index 381eba09c98..54cb0bd5da6 100644 --- a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.c +++ b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.c @@ -554,7 +554,7 @@ FError FSataAhciInit(FSataCtrl *instance_p) ret = FSataAhciLinkUp(instance_p, i); if (ret) { - FSATA_DEBUG("sata host %d, port %d link timeout.", instance_p->config.instance_id, i); + FSATA_DEBUG("sata host %d, port %d link timeout.", instance_p->config.instance_id, i); continue; } else @@ -602,6 +602,11 @@ FError FSataAhciInit(FSataCtrl *instance_p) instance_p->link_port_map |= BIT(i); } } + if (instance_p->link_port_map == 0) + { + FSATA_ERROR("Sata ports link failed.\n"); + return FSATA_UNKNOWN_DEVICE; + } /* host interrupt enable */ reg_val = FSATA_READ_REG32(base_addr, FSATA_HOST_CTL); @@ -770,7 +775,7 @@ static FError FSataAhciDataIO(FSataCtrl *instance_p, u8 port, u8 *fis, if (port >= instance_p->n_ports) { FSATA_DEBUG("Invalid port number %d.", port); - return FSATA_ERR_INVAILD_PARAMETER; + return FSATA_ERR_INVALID_PARAMETER; } u32 reg_val = FSATA_READ_REG32(port_base_addr, FSATA_PORT_SCR_STAT); @@ -788,7 +793,7 @@ static FError FSataAhciDataIO(FSataCtrl *instance_p, u8 port, u8 *fis, if (prdt_length == -1) { FSATA_ERROR("FSataAhciFillCmdTablePrdt failed, buf_len = %d.\n", buf_len); - return FSATA_ERR_INVAILD_PARAMETER; + return FSATA_ERR_INVALID_PARAMETER; } /* command list DW0: PRDTL(buf len) + W/R + CFL(fis len, 4 Byte(Dword) aligned) */ diff --git a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.h b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.h index 74f67ac0111..67a225ee233 100644 --- a/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.h +++ b/bsp/phytium/libraries/standalone/drivers/sata/fsata/fsata.h @@ -37,7 +37,7 @@ extern "C" #endif #define FSATA_SUCCESS FT_SUCCESS -#define FSATA_ERR_INVAILD_PARAMETER FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 1) +#define FSATA_ERR_INVALID_PARAMETER FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 1) #define FSATA_ERR_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 2) #define FSATA_ERR_OPERATION FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 3) #define FSATA_UNKNOWN_DEVICE FT_MAKE_ERRCODE(ErrModBsp, ErrBspSata, 4) diff --git a/bsp/phytium/libraries/standalone/drivers/serial/Kconfig b/bsp/phytium/libraries/standalone/drivers/serial/Kconfig index e84c41301c1..95192bccbea 100644 --- a/bsp/phytium/libraries/standalone/drivers/serial/Kconfig +++ b/bsp/phytium/libraries/standalone/drivers/serial/Kconfig @@ -3,7 +3,7 @@ menu "Usart Configuration" config ENABLE_Pl011_UART bool prompt "Use Pl011 uart" - default n + default y endmenu diff --git a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.h b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.h index 354743d4606..0e2aac6025f 100644 --- a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.h +++ b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011.h @@ -173,6 +173,7 @@ u32 FPl011GetInterruptMask(FPl011 *uart_p) ; void FPl011InterruptHandler(s32 vector, void *param); void FPl011SetHandler(FPl011 *uart_p, FPl011EventHandler fun_p, void *args); void FPl011SetInterruptMask(FPl011 *uart_p, u32 mask); +void FPl011InterruptClearAll(FPl011 *uart_p); diff --git a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_intr.c b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_intr.c index 6a263dd6566..9b75b63a049 100644 --- a/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_intr.c +++ b/bsp/phytium/libraries/standalone/drivers/serial/fpl011/fpl011_intr.c @@ -25,7 +25,6 @@ /***************************** Include Files *********************************/ - #include "fpl011.h" /************************** Constant Definitions *****************************/ @@ -83,6 +82,21 @@ void FPl011SetInterruptMask(FPl011 *uart_p, u32 mask) FUART_WRITEREG32(uart_p->config.base_address, FPL011IMSC_OFFSET, temp_mask); } +/** + * @name: FPl011InterruptClear + * @msg: This function clears all interrupt state. + * @param uart_p is a pointer to the uart instance + */ +void FPl011InterruptClearAll(FPl011 *uart_p) +{ + FASSERT(uart_p != NULL); + + if (FUART_READREG32(uart_p->config.base_address, FPL011RIS_OFFSET)) + { + FUART_WRITEREG32(uart_p->config.base_address, FPL011ICR_OFFSET, 0xFFFFFFFF); + } +} + /** * @name: FPl011SetHandler * @msg: This function sets the handler that will be called when an event (interrupt) diff --git a/bsp/phytium/libraries/standalone/drivers/spi/Kconfig b/bsp/phytium/libraries/standalone/drivers/spi/Kconfig index 1d17ec511ca..9cfe5f79a3b 100644 --- a/bsp/phytium/libraries/standalone/drivers/spi/Kconfig +++ b/bsp/phytium/libraries/standalone/drivers/spi/Kconfig @@ -6,5 +6,4 @@ config USE_FSPIM depends on USE_SPI help Select FSPIM driver component - - + diff --git a/bsp/phytium/libraries/standalone/drivers/timer/Kconfig b/bsp/phytium/libraries/standalone/drivers/timer/Kconfig index 2ba3ac26d86..ff5c83ebaac 100644 --- a/bsp/phytium/libraries/standalone/drivers/timer/Kconfig +++ b/bsp/phytium/libraries/standalone/drivers/timer/Kconfig @@ -2,7 +2,7 @@ menu "Hardware Timer Configuration" config ENABLE_TIMER_TACHO bool prompt "Use Timer Tacho" - depends on TARGET_E2000S || TARGET_E2000D || TARGET_E2000Q + depends on TARGET_E2000S || TARGET_E2000D || TARGET_E2000Q || TARGET_T2000Q default n endmenu diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.c b/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.c index f48d945eb59..237db1db642 100644 --- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.c +++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_msc.c @@ -23,6 +23,7 @@ */ #include +#include "fparameters.h" #include "fswap.h" #include "fsleep.h" #include "fassert.h" @@ -41,18 +42,18 @@ static inline tick_t FUsbMscGetTick(void) { - return GenericTimerRead(); + return GenericTimerRead(GENERIC_TIMER_ID0); } static inline tick_t FUsbMscStartTick(void) { - GenericTimerStart(); + GenericTimerStart(GENERIC_TIMER_ID0); return FUsbMscGetTick(); } static inline void FUsbMscStopTick(void) { - GenericTimerStop(); + GenericTimerStop(GENERIC_TIMER_ID0); } static inline boolean FUsbMscTimeout(tick_t start_tick, tick_t timeout_tick) diff --git a/bsp/phytium/libraries/standalone/drivers/usb/fusb_private.h b/bsp/phytium/libraries/standalone/drivers/usb/fusb_private.h index 859db19a090..9ad5e4c3e39 100644 --- a/bsp/phytium/libraries/standalone/drivers/usb/fusb_private.h +++ b/bsp/phytium/libraries/standalone/drivers/usb/fusb_private.h @@ -29,7 +29,7 @@ #ifdef __aarch64__ #include "faarch64.h" #else - #include "fcp15.h" + #include "faarch32.h" #endif #include "fkernel.h" diff --git a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.c b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.c index 0fc9c907fd9..34ec0c23afa 100644 --- a/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.c +++ b/bsp/phytium/libraries/standalone/drivers/watchdog/fwdt/fwdt.c @@ -164,7 +164,7 @@ u32 FWdtGetTimeleft(FWdtCtrl *pctrl) u32 wcvl = (u32)FWdtReadWCVL(base_addr); u64 wcv = (((u64)wcvh << 32) | wcvl); - timeleft += (wcv - GenericTimerRead()); + timeleft += (wcv - GenericTimerRead(GENERIC_TIMER_ID0)); FWDT_DEBUG("wcvh=%llx, wcvl=%llx, wcv=%llx, timeleft=%llx\n", wcvh, wcvl, wcv, timeleft); diff --git a/bsp/phytium/libraries/standalone/gitinfo b/bsp/phytium/libraries/standalone/gitinfo index e6334ebcefe..4a54f59d730 100644 --- a/bsp/phytium/libraries/standalone/gitinfo +++ b/bsp/phytium/libraries/standalone/gitinfo @@ -1,3 +1,3 @@ -[commit-id]: 41da10704f28d248120e389ae889e92f43f49a98 -[branch]: pin_example_reconsitution -[date]: 2023-03-09 14:58:04 +[commit-id]: 9404e64c23d012173cfe3caf9281475bd27a149b +[branch]: iopad +[date]: 2023-07-17 18:51:36 diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/faarch32.c similarity index 98% rename from bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.c rename to bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/faarch32.c index e2945ede4b6..5fc72f95f62 100644 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.c +++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/faarch32.c @@ -24,7 +24,7 @@ /***************************** Include Files *********************************/ #include "fassert.h" -#include "fcp15.h" +#include "faarch32.h" /************************** Constant Definitions *****************************/ diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/faarch32.h similarity index 100% rename from bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fcp15.h rename to bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/faarch32.h diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fgeneric_timer.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fgeneric_timer.c index 8512d868565..39eee00f4f4 100644 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fgeneric_timer.c +++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fgeneric_timer.c @@ -43,12 +43,12 @@ /************************** Function Prototypes ******************************/ /************************** Function *****************************************/ -u64 GenericTimerRead(void) +u64 GenericTimerRead(u32 id) { return (u64)gtimer_get_current_value(); } -void GenericTimerStart(void) +void GenericTimerStart(u32 id) { u32 ctrl = gtimer_get_control(); /* get CNTP_CTL */ @@ -59,7 +59,7 @@ void GenericTimerStart(void) } } -void GenericTimerStop(void) +void GenericTimerStop(u32 id) { u32 ctrl = gtimer_get_control(); /* get CNTP_CTL */ if ((ctrl & CNTP_CTL_ENABLE)) @@ -76,13 +76,13 @@ u32 GenericTimerFrequecy(void) return rate; } -void GenericTimerCompare(u32 interval) +void GenericTimerSetTimerCompareValue(u32 id, u32 interval) { /* set CNTP_CVAL, set compare value for physical timer */ gtimer_set_load_value((rt_uint64_t)interval); } -void GenericTimerInterruptEnable(void) +void GenericTimerInterruptEnable(u32 id) { u64 ctrl = gtimer_get_control(); if (ctrl & CNTP_CTL_IMASK) diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.c deleted file mode 100644 index 19dc830d38a..00000000000 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fpsci.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fpsci.c - * Date: 2022-02-10 14:53:41 - * LastEditTime: 2022-02-17 17:30:35 - * Description:  This file is for cpu energy management - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 huanghe 2021/7/3 first release - */ - - -#include "fpsci.h" -#include "fsmc.h" -#include "fcpu_info.h" -#include "ferror_code.h" -#include "fparameters.h" -#include "ftypes.h" - -#define PSCI_CPUON_NUM 0x84000003 -#define PSCI_RESET_NUM 0x84000009 - -/** - * @name: FPsci_CpuOn - * @msg: Power up a core - * @in param cpu_id_mask: cpu id mask - * @in param bootaddr: a 32-bit entry point physical address (or IPA). - * @return FError - */ -FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr) -{ - FError ret ; - u64 cluster = 0; - FSmc_Data_t input = {0}; - FSmc_Data_t output = {0}; - input.function_identifier = PSCI_CPUON_NUM; - ret = GetCpuAffinityByMask(cpu_id_mask, &cluster); - if (ret != ERR_SUCCESS) - { - return ret; - } - - input.a1 = cluster; - - input.a2 = (u32)(bootaddr & 0xFFFFFFFF); - FSmcCall(&input, &output); - __asm__ volatile("NOP"); - return ERR_SUCCESS; -} - -void PsciCpuReset(void) -{ - - FSmc_Data_t input = {0}; - FSmc_Data_t output = {0}; - - input.function_identifier = PSCI_RESET_NUM; - FSmcCall(&input, &output); - - __asm__ volatile("NOP"); - while (1) - ; -} diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsleep.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsleep.c index 165b599c52f..4fbdd2d9a30 100644 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsleep.c +++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsleep.c @@ -23,8 +23,11 @@ */ /***************************** Include Files *********************************/ +#include "fparameters.h" #include "fassert.h" +#include "fgeneric_timer.h" #include "fsleep.h" +#include "fkernel.h" /************************** Constant Definitions *****************************/ @@ -37,17 +40,34 @@ /************************** Function Prototypes ******************************/ /************************** Function *****************************************/ +static u32 fsleep_general(u32 ticks, u32 div) +{ + u64 end_time; + u64 cur_time; + GenericTimerStart(GENERIC_TIMER_ID0); + cur_time = GenericTimerRead(GENERIC_TIMER_ID0); + end_time = cur_time + ((u64)ticks * GenericTimerFrequecy() / div); + + do + { + cur_time = GenericTimerRead(GENERIC_TIMER_ID0); + } + while (cur_time < end_time); + + return 0; +} + u32 fsleep_seconds(u32 seconds) { - FASSERT_MSG(0, "%s not implment !!!", __func__); + return fsleep_general(seconds, 1); } u32 fsleep_millisec(u32 mseconds) { - FASSERT_MSG(0, "%s not implment !!!", __func__); + return fsleep_general(mseconds, NANO_TO_MICRO); } -u32 fsleep_microsec(u32 useconds) +u32 fsleep_microsec(u32 mseconds) { - FASSERT_MSG(0, "%s not implment !!!", __func__); + return fsleep_general(mseconds, NANO_TO_KILO); } diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmc.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmc.h deleted file mode 100644 index 445ba4813c0..00000000000 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmc.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * @Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * @FilePath: fsmc.h - * @Date: 2023-04-19 10:14:11 - * @LastEditTime: 2023-04-19 10:14:12 - * @Description: This file is for - * - * @Modify History: - * Ver Who Date Changes - * ----- ------ -------- -------------------------------------- - */ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fsmc.h - * Date: 2022-02-10 14:53:41 - * LastEditTime: 2022-02-17 17:30:49 - * Description:  This file is for Non-secure SMC Call - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 huanghe 2021/7/3 first release - */ - - -#ifndef ARCH_ARMV8_AARCH32_SMC_H -#define ARCH_ARMV8_AARCH32_SMC_H - -#ifdef __cplusplus -extern "C" -{ -#endif -#include "ftypes.h" - -typedef struct -{ - /* data */ - u32 function_identifier; - u32 a1; - u32 a2; - u32 a3; - u32 a4; - u32 a5; - u32 a6; - -} FSmc_Data_t; - -void FSmcCall(FSmc_Data_t *Input, FSmc_Data_t *Output); - -#ifdef __cplusplus -} -#endif - -#endif // !FT_SMC_H diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmcc.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmcc.c new file mode 100644 index 00000000000..8d1944669c0 --- /dev/null +++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmcc.c @@ -0,0 +1,114 @@ +/* + * Copyright : (C) 2023 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fsmcc.c + * Created Date: 2023-06-16 11:30:41 + * Last Modified: 2023-06-30 13:19:25 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + * 1.0 huanghe 2023-06-16 first init + */ + + +#include "fsmcc.h" +#include "ftypes.h" + + +/** +@name: FSmcccHvcCall +@msg: 执行HVC（虚拟化监管CALL）指令。 +@param {unsigned long} arg0: 第一个参数传递给HVC调用。 +@param {unsigned long} arg1: 第二个参数传递给HVC调用。 +@param {unsigned long} arg2: 第三个参数传递给HVC调用。 +@param {unsigned long} arg3: 第四个参数传递给HVC调用。 +@param {unsigned long} arg4: 第五个参数传递给HVC调用。 +@param {unsigned long} arg5: 第六个参数传递给HVC调用。 +@param {unsigned long} arg6: 第七个参数传递给HVC调用。 +@param {unsigned long} arg7: 第八个参数传递给HVC调用。 +@param {struct FSmcccRes*} res: 结构体指针，用于保存HVC调用的结果。 +@note: 此函数执行SMC（虚拟化监管CALL）指令，并将结果保存在提供的结构体指针中。 +*/ +void FSmcccHvcCall(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct FSmcccRes *res) +{ + register unsigned long r0 asm("r0") = arg0; + register unsigned long r1 asm("r1") = arg1; + register unsigned long r2 asm("r2") = arg2; + register unsigned long r3 asm("r3") = arg3; + register unsigned long r4 asm("r4") = arg4; + register unsigned long r5 asm("r5") = arg5; + register unsigned long r6 asm("r6") = arg6; + register unsigned long r7 asm("r7") = arg7; + + asm volatile( + "hvc #0\n" + : "+r"(r0), "+r"(r1), "+r"(r2), "+r"(r3), + "+r"(r4), "+r"(r5), "+r"(r6), "+r"(r7) + : + : "memory"); + + res->a0 = r0; + res->a1 = r1; + res->a2 = r2; + res->a3 = r3; +} + + +/** +@name: FSmcccSmcCall +@msg: 执行SMC（Secure Monitor Call）指令。 +@param {unsigned long} arg0: 第一个参数传递给SMC调用。 +@param {unsigned long} arg1: 第二个参数传递给SMC调用。 +@param {unsigned long} arg2: 第三个参数传递给SMC调用。 +@param {unsigned long} arg3: 第四个参数传递给SMC调用。 +@param {unsigned long} arg4: 第五个参数传递给SMC调用。 +@param {unsigned long} arg5: 第六个参数传递给SMC调用。 +@param {unsigned long} arg6: 第七个参数传递给SMC调用。 +@param {unsigned long} arg7: 第八个参数传递给SMC调用。 +@param {struct FSmcccRes*} res: 结构体指针，用于保存SMC调用的结果。 +@note: 此函数执行SMC（Secure Monitor Call）指令，并将结果保存在提供的结构体指针中。 +*/ +void FSmcccSmcCall(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct FSmcccRes *res) +{ + register unsigned long r0 asm("r0") = arg0; + register unsigned long r1 asm("r1") = arg1; + register unsigned long r2 asm("r2") = arg2; + register unsigned long r3 asm("r3") = arg3; + register unsigned long r4 asm("r4") = arg4; + register unsigned long r5 asm("r5") = arg5; + register unsigned long r6 asm("r6") = arg6; + register unsigned long r7 asm("r7") = arg7; + + asm volatile( + "smc #0\n" + : "+r"(r0), "+r"(r1), "+r"(r2), "+r"(r3), + "+r"(r4), "+r"(r5), "+r"(r6), "+r"(r7) + : + : "memory"); + + res->a0 = r0; + res->a1 = r1; + res->a2 = r2; + res->a3 = r3; +} + diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmcc.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmcc.h new file mode 100644 index 00000000000..53bb22f1dda --- /dev/null +++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmcc.h @@ -0,0 +1,63 @@ +/* + * Copyright : (C) 2023 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fsmcc.h + * Created Date: 2023-06-16 11:30:49 + * Last Modified: 2023-06-16 15:47:29 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + * 1.0 huanghe 2023-06-16 first init + */ +#ifndef ARCH_ARMV8_AARCH32_SMCC_H +#define ARCH_ARMV8_AARCH32_SMCC_H + + + +#ifdef __cplusplus +extern "C" +{ +#endif +#include "ftypes.h" + +struct FSmcccRes { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + + +void FSmcccHvcCall(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct FSmcccRes *res) ; + + + +void FSmcccSmcCall(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct FSmcccRes *res) ; + +void FSmcccSmcGetSocIdCall(struct FSmcccRes *res) ; + +#ifdef __cplusplus +} +#endif + +#endif // !FT_SMC_H diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmccc_call.S b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmccc_call.S deleted file mode 100644 index 7845646194c..00000000000 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/fsmccc_call.S +++ /dev/null @@ -1,59 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: smccc-call.S - * Date: 2022-02-10 14:53:41 - * LastEditTime: 2022-02-17 17:28:10 - * Description:  This file is for initiating SMC call - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 huanghe 2021/7/3 first release - */ - - -/******************************************************************************* -* -* FSmcCall - initiate SMC call -* -* This routine initiates SMC call which traps the processor into Monitor Mode. -* The ARM SMC Call Convetion defines that up to eight registers can be exchanged -* during an SMC call. The input parameter contains eight INT32 valeus which are -* to be passed in the SMC call; similarily the output parameter also contains -* eight INT32 values which are returned from the SMC call. -* -* \NOMANUAL -* -* RETURNS: OK -* -* void FSmcCall -* ( -* FSmc_Data_t * input, /@ r0 - input register values @/ -* FSmc_Data_t * output /@ r1 - output register values @/ -* ) -*/ - -.arm -.align 4 -.globl FSmcCall -FSmcCall: - STMDB sp!, {r0-r7} /* save clobbered registers to stack */ - ldr r12, [sp, #(4 * 0)] /* get 1st argument (ptr to input struct) */ - ldmia r12, {r0-r7} /* save input argument to r0-r7 */ - smc #0 - ldr r12, [sp, #(4 * 1)] /* get 2th argument (ptr to output result) */ - stmia r12, {r0-r7} /* get output argument from r0-r7 */ - ldmfd sp!, {r0-r7} /* restore clobbered registers from stack */ - bx lr -.size FSmcCall, .- FSmcCall diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/sdkopts.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/sdkopts.h deleted file mode 100644 index 3379577aa6b..00000000000 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch32/sdkopts.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: sdkopts.h - * Date: 2022-09-16 13:54:28 - * LastEditTime: 2022-09-16 13:54:28 - * Description: This file is for configure sdkconfig in non-Kconfig way - * - * Modify History: - * Ver Who Date Changes - * ----- ------ -------- -------------------------------------- - * 1.0 liuzhihong 2022/10/20 first release - */ - -#ifndef SDK_OPTS_H -#define SDK_OPTS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*******************Control Options*******************/ -/* cpu aarch 32/64 */ -#define CPU_AARCH 32 -#define TARGET_NAME "e2000d_baremetal_a32" - -/* e2000d e2000q e2000s d2000 ft2004 */ -#define CPU_TYPE_E2000D 0 -#define CPU_TYPE_E2000Q 1 -#define CPU_TYPE_E2000S 2 -#define CPU_TYPE_D2000 3 -#define CPU_TYPE_FT2004 4 -#define CPU_TYPE CPU_TYPE_E2000D - -/* log type */ -#define LOG_TYPE_VERBOS 0 -#define LOG_TYPE_DEBUG 1 -#define LOG_TYPE_INFO 2 -#define LOG_TYPE_WARN 3 -#define LOG_TYPE_ERROR 4 -#define LOG_TYPE_NONE 5 -#define LOG_TYPE LOG_TYPE_ERROR - -/*******************SDK Configures*******************/ -#include "sdkopts.h" - -#ifdef __cplusplus -} -#endif - -#endif /* SDK_OPTS_H */ \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/faarch64.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/faarch64.c index 88906b1e2df..c1a9fbf6181 100644 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/faarch64.c +++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/faarch64.c @@ -25,7 +25,8 @@ /***************************** Include Files *********************************/ #include "fassert.h" #include "faarch64.h" - +#include "rtdef.h" +#include "cpuport.h" /************************** Constant Definitions *****************************/ /**************************** Type Definitions *******************************/ @@ -37,3 +38,7 @@ /************************** Function Prototypes ******************************/ /************************** Function *****************************************/ +void WMB(void) +{ + rt_hw_dsb(); +} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fgeneric_timer.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fgeneric_timer.c index ead65027be6..a4b56a101b6 100644 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fgeneric_timer.c +++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fgeneric_timer.c @@ -22,45 +22,6 @@ * 1.0 zhugengyu 2023/2/28 first release */ -/***************************** Include Files *********************************/ -#include "fassert.h" -#include "fgeneric_timer.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/************************** Variable Definitions *****************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Function *****************************************/ -/* - * Copyright : (C) 2023 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fgeneric_timer.c - * Date: 2022-02-10 14:53:41 - * LastEditTime: 2022-02-17 17:36:17 - * Description:  This file is for generic timer function port for driver - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 zhugengyu 2023/2/28 first release - */ - /***************************** Include Files *********************************/ #include @@ -78,35 +39,7 @@ /************************** Function Prototypes ******************************/ /************************** Function *****************************************/ -u64 GenericTimerRead(void) +u64 GenericTimerRead(u32 id) { return (u64)rt_hw_get_gtimer_val(); -} - -void GenericTimerStart(void) -{ - /* shall not be called in rtt */ - FASSERT_MSG(0, "%s not implment !!!", __func__); -} - -void GenericTimerStop(void) -{ - /* shall not be called in rtt */ - FASSERT_MSG(0, "%s not implment !!!", __func__); -} - -u32 GenericTimerFrequecy(void) -{ - FASSERT_MSG(0, "%s not implment !!!", __func__); - return 0U; -} - -void GenericTimerCompare(u32 interval) -{ - FASSERT_MSG(0, "%s not implment !!!", __func__); -} - -void GenericTimerInterruptEnable(void) -{ - FASSERT_MSG(0, "%s not implment !!!", __func__); } \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.c deleted file mode 100644 index 36b373683bc..00000000000 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fpsci.c - * Date: 2022-02-10 14:53:41 - * LastEditTime: 2022-02-17 17:33:51 - * Description:  This file is for cpu energy management - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 huanghe 2021/7/3 first release - */ - -#include "fpsci.h" -#include "farm_smccc.h" -#include "ftypes.h" -#include "fcpu_info.h" -#include "ferror_code.h" -#include "fprintk.h" - -FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr) -{ - FError ret ; - u64 cluster = 0; - struct arm_smccc_res res; - struct arm_smccc_quirk quirk; - ret = GetCpuAffinityByMask(cpu_id_mask, &cluster); - if (ret != ERR_SUCCESS) - { - f_printk("GetCpuAffinity is failed \r\n") ; - return ret ; - } - __arm_smccc_smc(0xc4000003, cluster, bootaddr, 0, 0, 0, 0, 0,&res, &quirk); - return ERR_SUCCESS ; -} -void PsciCpuReset(void) -{ - struct arm_smccc_res res; - __arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res,NULL); -} \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.h deleted file mode 100644 index c672a45bbd8..00000000000 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fpsci.h +++ /dev/null @@ -1,66 +0,0 @@ -/* - * @Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * @FilePath: fpsci.h - * @Date: 2023-04-21 15:39:57 - * @LastEditTime: 2023-04-21 15:39:57 - * @Description: This file is for - * - * @Modify History: - * Ver Who Date Changes - * ----- ------ -------- -------------------------------------- - */ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fpsci.h - * Date: 2022-02-10 14:53:41 - * LastEditTime: 2022-02-17 17:34:06 - * Description:  This file is for cpu energy management - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 huanghe 2021/7/3 first release - */ - - -#ifndef FPSCI_H -#define FPSCI_H - -#include "ftypes.h" -#include "ferror_code.h" - -#ifdef __cplusplus -extern "C" -{ -#endif - -void PsciCpuReset(void); -FError PsciCpuOn(s32 cpu_id_mask, uintptr bootaddr); - -#ifdef __cplusplus -} -#endif - -#endif // FPSCI_H \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsmcc.c b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsmcc.c new file mode 100644 index 00000000000..4865c0840b8 --- /dev/null +++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsmcc.c @@ -0,0 +1,112 @@ +/* + * Copyright : (C) 2023 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fsmcc.c + * Created Date: 2023-06-19 11:12:23 + * Last Modified: 2023-06-30 13:17:16 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + */ + +#include "fsmcc.h" +#include "ftypes.h" + + + +/** +@name: FSmcccSmcCall +@msg: 执行SMC（Secure Monitor Call）指令。 +@param {unsigned long} arg0: 第一个参数传递给SMC调用。 +@param {unsigned long} arg1: 第二个参数传递给SMC调用。 +@param {unsigned long} arg2: 第三个参数传递给SMC调用。 +@param {unsigned long} arg3: 第四个参数传递给SMC调用。 +@param {unsigned long} arg4: 第五个参数传递给SMC调用。 +@param {unsigned long} arg5: 第六个参数传递给SMC调用。 +@param {unsigned long} arg6: 第七个参数传递给SMC调用。 +@param {unsigned long} arg7: 第八个参数传递给SMC调用。 +@param {struct FSmcccRes*} res: 结构体指针，用于保存SMC调用的结果。 +@note: 此函数执行SMC（Secure Monitor Call）指令，并将结果保存在提供的结构体指针中。 +*/ +void FSmcccSmcCall(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct FSmcccRes *res) +{ + register unsigned long x0 asm("x0") = arg0; + register unsigned long x1 asm("x1") = arg1; + register unsigned long x2 asm("x2") = arg2; + register unsigned long x3 asm("x3") = arg3; + register unsigned long x4 asm("x4") = arg4; + register unsigned long x5 asm("x5") = arg5; + register unsigned long x6 asm("x6") = arg6; + register unsigned long x7 asm("x7") = arg7; + + asm volatile( + "smc #0\n" + : "+r"(x0), "+r"(x1), "+r"(x2), "+r"(x3), + "+r"(x4), "+r"(x5), "+r"(x6), "+r"(x7) + : + : "memory"); + + res->a0 = x0; + res->a1 = x1; + res->a2 = x2; + res->a3 = x3; +} + +/** +@name: FSmcccHvcCall +@msg: 执行HVC（虚拟化监管CALL）指令。 +@param {unsigned long} arg0: 第一个参数传递给HVC调用。 +@param {unsigned long} arg1: 第二个参数传递给HVC调用。 +@param {unsigned long} arg2: 第三个参数传递给HVC调用。 +@param {unsigned long} arg3: 第四个参数传递给HVC调用。 +@param {unsigned long} arg4: 第五个参数传递给HVC调用。 +@param {unsigned long} arg5: 第六个参数传递给HVC调用。 +@param {unsigned long} arg6: 第七个参数传递给HVC调用。 +@param {unsigned long} arg7: 第八个参数传递给HVC调用。 +@param {struct FSmcccRes*} res: 结构体指针，用于保存HVC调用的结果。 +@note: 此函数执行SMC（虚拟化监管CALL）指令，并将结果保存在提供的结构体指针中。 +*/ +void FSmcccHvcCall(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct FSmcccRes *res) +{ + register unsigned long x0 asm("x0") = arg0; + register unsigned long x1 asm("x1") = arg1; + register unsigned long x2 asm("x2") = arg2; + register unsigned long x3 asm("x3") = arg3; + register unsigned long x4 asm("x4") = arg4; + register unsigned long x5 asm("x5") = arg5; + register unsigned long x6 asm("x6") = arg6; + register unsigned long x7 asm("x7") = arg7; + + asm volatile( + "hvc #0\n" + : "+r"(x0), "+r"(x1), "+r"(x2), "+r"(x3), + "+r"(x4), "+r"(x5), "+r"(x6), "+r"(x7) + : + : "memory"); + + res->a0 = x0; + res->a1 = x1; + res->a2 = x2; + res->a3 = x3; +} + diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsmcc.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsmcc.h new file mode 100644 index 00000000000..1cb1cda92fe --- /dev/null +++ b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/fsmcc.h @@ -0,0 +1,65 @@ +/* + * Copyright : (C) 2023 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fsmcc.h + * Created Date: 2023-06-19 11:12:31 + * Last Modified: 2023-06-21 16:11:36 + * Description: This file is for + * + * Modify History: + * Ver Who Date Changes + * ----- ---------- -------- --------------------------------- + * 1.0 huanghe 2023-06-16 first release + */ + + +#ifndef ARCH_ARMV8_AARCH64_SMCC_H +#define ARCH_ARMV8_AARCH64_SMCC_H + + + +#ifdef __cplusplus +extern "C" +{ +#endif +#include "ftypes.h" + +struct FSmcccRes { + unsigned long a0; + unsigned long a1; + unsigned long a2; + unsigned long a3; +}; + + +void FSmcccHvcCall(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct FSmcccRes *res) ; + + + +void FSmcccSmcCall(unsigned long arg0, unsigned long arg1, + unsigned long arg2, unsigned long arg3, + unsigned long arg4, unsigned long arg5, + unsigned long arg6, unsigned long arg7, + struct FSmcccRes *res) ; + +void FSmcccSmcGetSocIdCall(struct FSmcccRes *res) ; + +#ifdef __cplusplus +} +#endif + +#endif // !ARCH_ARMV8_AARCH64_SMCC_H diff --git a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/sdkopts.h b/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/sdkopts.h deleted file mode 100644 index e86224eb82a..00000000000 --- a/bsp/phytium/libraries/standalone/port/arch/armv8/aarch64/sdkopts.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: sdkopts.h - * Date: 2022-09-16 13:54:28 - * LastEditTime: 2022-09-16 13:54:28 - * Description: This file is for configure sdkconfig in non-Kconfig way - * - * Modify History: - * Ver Who Date Changes - * ----- ------ -------- -------------------------------------- - * 1.0 zhugengyu 2023/03/03 first release - */ - -#ifndef SDK_OPTS_H -#define SDK_OPTS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/*******************Control Options*******************/ -/* cpu aarch 32/64 */ -#define CPU_AARCH 64 -#define TARGET_NAME "e2000d_baremetal_a64" - -/* e2000d e2000q e2000s d2000 ft2004 */ -#define CPU_TYPE_E2000D 0 -#define CPU_TYPE_E2000Q 1 -#define CPU_TYPE_E2000S 2 -#define CPU_TYPE_D2000 3 -#define CPU_TYPE_FT2004 4 -#define CPU_TYPE CPU_TYPE_E2000D - -/* log type */ -#define LOG_TYPE_VERBOS 0 -#define LOG_TYPE_DEBUG 1 -#define LOG_TYPE_INFO 2 -#define LOG_TYPE_WARN 3 -#define LOG_TYPE_ERROR 4 -#define LOG_TYPE_NONE 5 -#define LOG_TYPE LOG_TYPE_ERROR - -/*******************SDK Configures*******************/ -#include "sdkopts.h" - -#ifdef __cplusplus -} -#endif - -#endif /* SDK_OPTS_H */ \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/port/arch/fgeneric_timer.h b/bsp/phytium/libraries/standalone/port/arch/fgeneric_timer.h index 19e6edefae5..f1ae3e33f14 100644 --- a/bsp/phytium/libraries/standalone/port/arch/fgeneric_timer.h +++ b/bsp/phytium/libraries/standalone/port/arch/fgeneric_timer.h @@ -44,12 +44,29 @@ extern "C" /************************** Function Prototypes ******************************/ /************************** Function *****************************************/ -u64 GenericTimerRead(void); -void GenericTimerStart(void); -void GenericTimerStop(void); +/* Set generic timer CompareValue */ +void GenericTimerSetTimerCompareValue(u32 id, u32 interval); + +/* Set generic timer TimerValue */ +void GenericTimerSetTimerValue(u32 id, u32 timeout); + +/* Unmask generic timer interrupt */ +void GenericTimerInterruptEnable(u32 id); + +/* Mask generic timer interrupt */ +void GenericTimerInterruptDisable(u32 id); + +/* Enable generic timer */ +void GenericTimerStart(u32 id); + +/* Get generic timer physical count value */ +u64 GenericTimerRead(u32 id); + +/* Get generic timer frequency of the system counter */ u32 GenericTimerFrequecy(void); -void GenericTimerCompare(u32 interval); -void GenericTimerInterruptEnable(void); + +/* Disable generic timer */ +void GenericTimerStop(u32 id); #ifdef __cplusplus } diff --git a/bsp/phytium/libraries/standalone/port/fcompiler.h b/bsp/phytium/libraries/standalone/port/fcompiler.h new file mode 100644 index 00000000000..48ffd423119 --- /dev/null +++ b/bsp/phytium/libraries/standalone/port/fcompiler.h @@ -0,0 +1,44 @@ +/* + * @Copyright : (C) 2022 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * @FilePath: fcompiler.h + * @Date: 2023-05-26 11:11:30 + * @LastEditTime: 2023-05-26 11:11:31 + * @Description: This file is for gcc compiler compilation + * + * @Modify History: + * Ver Who Date Changes + * ----- ------ -------- -------------------------------------- + * 1.0 huanghe 2023-05-26 init + */ + + +#ifndef FCOMPILER_H +#define FCOMPILER_H + +#ifdef __cplusplus +extern "C" +{ +#endif + +#define FCOMPILER_SECTION(section_name) __attribute__ ((section (section_name))) +#if defined(__aarch64__) +#define FAARCH64_USE __aarch64__ +#endif + +#ifdef __cplusplus +} +#endif + +#endif // ! + diff --git a/bsp/phytium/libraries/standalone/board/common/fearly_uart.c b/bsp/phytium/libraries/standalone/port/fearly_uart.c similarity index 72% rename from bsp/phytium/libraries/standalone/board/common/fearly_uart.c rename to bsp/phytium/libraries/standalone/port/fearly_uart.c index 7d114ceac91..b7b268dbb05 100644 --- a/bsp/phytium/libraries/standalone/board/common/fearly_uart.c +++ b/bsp/phytium/libraries/standalone/port/fearly_uart.c @@ -19,16 +19,35 @@ * Modify History: * Ver   Who        Date         Changes * ----- ------     --------    -------------------------------------- + * 1.0 rtos 2022/6/25 init commit + * 1.1 zhangyan 2023/7/11 modify */ /***************************** Include Files *********************************/ +#include "rtconfig.h" +#ifdef RT_USING_SMART +#include +#endif + #include "fkernel.h" #include "fio.h" #include "fparameters.h" #include "fearly_uart.h" +#include "fpl011.h" /**************************** Type Definitions *******************************/ +static FPl011 early_uart; +void FEarlyUartProbe(void) +{ + FPl011Config config; + config = *FPl011LookupConfig(EARLY_UART_CTRL_ID); +#ifdef RT_USING_SMART + config.base_address = (uintptr)rt_ioremap((void*)config.base_address, 0x2000); +#endif + FPl011CfgInitialize(&early_uart, &config); + return; +} /************************** Constant Definitions *****************************/ /************************** Variable Definitions *****************************/ @@ -38,22 +57,10 @@ /*****************************************************************************/ void OutByte(s8 byte) { - /* wait until tx fifo is not full */ - while ((FtIn32(EARLY_UART_UARTFR) & EARLY_UART_TXFF) == EARLY_UART_TXFF) - { - - } - - FtOut32(EARLY_UART_UARTDR, (((u32)byte) & EARLY_UART_DATA_MASK)); + FPl011BlockSend(&early_uart, (u8 *)&byte, 1); } char GetByte(void) { - /* wait until rx fifo is not empty */ - while ((FtIn32(EARLY_UART_UARTFR) & EARLY_UART_RXFE) == EARLY_UART_RXFE) - { - - } - - return (char)(EARLY_UART_DATA_MASK & FtIn32(EARLY_UART_UARTDR)); + return (char)(FPl011BlockReceive(&early_uart)); } \ No newline at end of file diff --git a/bsp/phytium/libraries/standalone/board/common/fearly_uart.h b/bsp/phytium/libraries/standalone/port/fearly_uart.h similarity index 61% rename from bsp/phytium/libraries/standalone/board/common/fearly_uart.h rename to bsp/phytium/libraries/standalone/port/fearly_uart.h index d1568048671..7518e677fba 100644 --- a/bsp/phytium/libraries/standalone/board/common/fearly_uart.h +++ b/bsp/phytium/libraries/standalone/port/fearly_uart.h @@ -20,6 +20,7 @@ * Ver   Who        Date         Changes * ----- ------     --------    -------------------------------------- * 1.0 rtos 2022/6/25 init commit + * 1.1 zhangyan 2023/7/11 reconstruct */ #ifndef BOARD_COMMON_EARLY_UART_H #define BOARD_COMMON_EARLY_UART_H @@ -39,40 +40,20 @@ extern "C" /************************** Constant Definitions *****************************/ #if defined(CONFIG_DEFAULT_DEBUG_PRINT_UART2) -#define EARLY_UART_BASE FUART2_BASE_ADDR -#define EARLY_UART_IRQ_NUM FUART2_IRQ_NUM +#define EARLY_UART_CTRL_ID FUART2_ID #elif defined(CONFIG_DEFAULT_DEBUG_PRINT_UART0) -#define EARLY_UART_BASE FUART0_BASE_ADDR -#define EARLY_UART_IRQ_NUM FUART0_IRQ_NUM +#define EARLY_UART_CTRL_ID FUART0_ID #else -#define EARLY_UART_BASE FUART1_BASE_ADDR -#define EARLY_UART_IRQ_NUM FUART1_IRQ_NUM +#define EARLY_UART_CTRL_ID FUART1_ID #endif -#define EARLY_UART_UARTDR (EARLY_UART_BASE + 0x0) /* UART 数据寄存器地址 */ -#define EARLY_UART_UARTFR (EARLY_UART_BASE + 0x18) /* UART 状态寄存器地址 */ -#define EARLY_UART_UARTCR (EARLY_UART_BASE + 0x30) -#define EARLY_UART_UARTCR_UARTEN BIT(0) -#define EARLY_UART_UARTCR_TXE BIT(8) -#define EARLY_UART_UARTCR_RXE BIT(9) -#define EARLY_UART_UARTCR_INIT (EARLY_UART_UARTCR_UARTEN | EARLY_UART_UARTCR_TXE | \ - EARLY_UART_UARTCR_RXE) -#define EARLY_UART_UARTIMSC (EARLY_UART_BASE + 0x38) -#define EARLY_UART_UARTIMSC_RXIM BIT(4) -#define EARLY_UART_UARTIMSC_RTIM BIT(6) -#define EARLY_UART_UARTMIS (EARLY_UART_BASE + 0x40) -#define EARLY_UART_UARTICR (EARLY_UART_BASE + 0x44) -#define EARLY_UART_TXFF BIT(5) /* 发送 FIFO 已满标志位 */ -#define EARLY_UART_RXFE BIT(4) /* 接收 FIFO 为空标志位 */ -#define EARLY_UART_DATA_MASK GENMASK(7, 0) -#define EARLY_UART_RXI_MASK BIT(4) - #define STDOUT_BASEADDRESS /************************** Variable Definitions *****************************/ /***************** Macros (Inline Functions) Definitions *********************/ /*****************************************************************************/ +void FEarlyUartProbe(void); void OutByte(s8 byte); char GetByte(void); diff --git a/bsp/phytium/libraries/standalone/port/sdkconfig.h b/bsp/phytium/libraries/standalone/port/sdkconfig.h index 6be880137e0..aaa9cd50125 100644 --- a/bsp/phytium/libraries/standalone/port/sdkconfig.h +++ b/bsp/phytium/libraries/standalone/port/sdkconfig.h @@ -82,6 +82,9 @@ extern "C" { #define CONFIG_USE_FQSPI #endif +#if defined(BSP_USING_ETH) +#define CONFIG_USE_ETH +#endif #ifdef __cplusplus } diff --git a/bsp/phytium/tools/lite_tools.md b/bsp/phytium/tools/lite_tools.md deleted file mode 100644 index 0f807e2d28a..00000000000 --- a/bsp/phytium/tools/lite_tools.md +++ /dev/null @@ -1,44 +0,0 @@ -# 背景 - -- RT-Thread 中有大量代码平常是不需要使用的，这里使用脚本将不使用的代码临时删除，后面又提供了一种方法在需要时恢复 - -# 精简 RT-Thread 代码 - -- 首先运行 reduce_rtt_code.py 脚本，用 -i 指定 RT-Thread 完整版代码路径，用 -o 指定输出 - -``` -./reduce_rtt_code.py -i=/mnt/d/proj/rt-thread/rt-thread-base -o=/mnt/d/proj/rt-thread/rt-thread-lite -``` - -![](./figures/reduce_rtt.png) - -- 进入 rt-thread-lite 目录，然后提交删除动作，记录删除动作前一个 commit 号 - -``` -git add . -git commit -m 'reduce rtt code tree' -``` - -![](./figures/commit_reduce.png) - -![](./figures/commit_id.png) - -# 恢复 RT-Thread 代码 - -- 需要同步 RT-Thread 基线仓库时，可能需要完整版的代码 -- 用 git rebase 撤销删除动作，在交互界面里将 pick 修改为 d，表示删除指定 commit, 然后保存修改 - -``` -git rebase -i -``` - -![](./figures/rebase_commit.png) - -- 等待一段时间可以看到原来删除的文件都恢复了 - -![](./figures/rebase_done.png) - - -# 删除 tools 文件夹 - -- lite 工具所在的文件夹在上传社区的时候可能不需要，要收到删除本文件夹 \ No newline at end of file diff --git a/bsp/phytium/tools/reduce_rtt_code.py b/bsp/phytium/tools/reduce_rtt_code.py deleted file mode 100644 index e2c1ec5d62e..00000000000 --- a/bsp/phytium/tools/reduce_rtt_code.py +++ /dev/null @@ -1,130 +0,0 @@ -#!/usr/bin/env python3 -# Copyright : (C) 2022 Phytium Information Technology, Inc. -# All Rights Reserved. - -# This program is OPEN SOURCE software: you can redistribute it and/or modify it -# under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, -# either version 1.0 of the License, or (at your option) any later version. - -# This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; -# without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. -# See the Phytium Public License for more details. - -# FilePath: reduce_rtt_cde.py -# Date: 2021-10-14 08:19:30 -# LastEditTime: 2022-02-18 09:26:24 -# Description:  This files is for install phytiunm standalone sdk - -# Modify History: -# Ver   Who        Date         Changes -# ----- ------     --------    -------------------------------------- -# 1.0 zhugengyu 2023/1/12 init commit - -# -# ./reduce_rtt_code.py -i=/mnt/d/proj/rt-thread/rt-thread-base -o=/mnt/d/proj/rt-thread/rt-thread-lite -# - - -import sys -import os -import argparse -import shutil - -src_path = [] -dst_path = [] - -dry_run = False #True - -def append_path(path): - src_path.append(os.path.abspath(path)) - -parser = argparse.ArgumentParser() -parser.description='please enter two parameters and ...' -parser.add_argument("-i", "--input", help="input PATH of RTT", type=str, default="./rt-thread") -parser.add_argument("-o", "--output", help="export PATH for RTT", type=str, default="./rt-thread-lite") -args = parser.parse_args() - -rtt_src_dir = os.path.abspath(args.input) -rtt_dst_dir = os.path.abspath(args.output) - -os.chdir(rtt_src_dir) # change to rt-thread folder - -# append path and files need to reserve - -## root -append_path(r'./.git') -append_path(r'./.gitee') -append_path(r'./.github') -append_path(r'./.gitattributes') -append_path(r'./.gitignore') -append_path(r'./ChangeLog.md') -append_path(r'./Kconfig') -append_path(r'./LICENSE') -append_path(r'./README.md') -append_path(r'./README_de.md') -append_path(r'./README_es.md') -append_path(r'./README_zh.md') - -## bsp -append_path(r'./bsp/phytium') - -## components -append_path(r'./components') - -## examples -append_path(r'./examples') - -## include -append_path(r'./include') - -## libcpu -append_path(r'./libcpu/Kconfig') -append_path(r'./libcpu/SConscript') -append_path(r'./libcpu/aarch64') -append_path(r'./libcpu/arm') - -## src -append_path(r'./src') - -## tools -append_path(r'./tools') - -print('Source path ======') -for path in src_path: - print(path) -print('====================') - -for path in src_path: - dst_path.append(path.replace(rtt_src_dir, rtt_dst_dir)) - -print('Destination path ======') -for path in dst_path: - print(path) -print('====================') - -print('Total {} items'.format(len(src_path))) -print('Current dir: {}'.format(os.getcwd())) - -if dry_run: - for i in range(len(src_path)): - print('copy {} to {}'.format(src_path[i], dst_path[i])) -else: - root_dir = r'.' + rtt_dst_dir - if os.path.exists(root_dir): - shutil.rmtree(root_dir) - - for i in range(len(src_path)): - if os.path.exists(dst_path[i]): - continue - - # do real copy !!!! - if os.path.isdir(src_path[i]): - shutil.copytree(src_path[i], dst_path[i]) - else: - file_dir = os.path.dirname(dst_path[i]) - if not os.path.exists(file_dir): - os.mkdir(file_dir) - shutil.copyfile(src_path[i], dst_path[i]) - - - os.chdir(rtt_dst_dir) # change to rt-thread folder