This project simulates the designed 4 bit ring counter. A ring counter is a digital sequential circuit that recirculates the same data throughout the circuit. It is one of the applications of shift registers.
In this digital world, counters are the most important sequential logic circuits which are used widely in many day-to-day life applications such as microwave ovens, washing machines, digital clocks, timers and in many electronic devices such as frequency dividers, analog to digital converters, triangular waveform generators, etc. Any digital circuit which is used to count the number of occurrences of the input is called counter. The purpose of counters is not only for counting but also for measuring frequency and time. Basically, counters are of 2 types: synchronous and asynchronous counters. If the change in transition occurs based on the clock input of the counter, then it is called synchronous counter. If not, then, it is called asynchronous counter. There are many other types of counters, such as decade counter, mod counter, binary counter, ring counter,etc. This paper mainly focuses on the ring counter only.
Ring counters can be used in many applications such as:
- Frequency counter
- ADC
- Digital clocks
- Measure timers and rate, etc.
A ring counter is a synchronous counter which transfers the same data throughout it. It is a typical application of shift register and can be designed using either D or JK flip-flops (FFs). Here, a 4-bit ring counter is designed by a series of 4 D-FFs connected together in feedback manner. That means the output of the last FF is connected to the input of the first FF. The clock signal is applied to all the FFs simultaneously.
Initially all the FFs are at RESET state. When the PRESET is applied, the input of the ring counter becomes 1. Now the output of the first FF (Q3) is 1 and other FF outputs (Q2, Q1 and Q0) will be low. Then for the next clock signal, Q2 becomes 1 and others outputs will be low. In this way, as the clock input changes, the outputs change and the data sequence rotates in the ring counter.
State diagram is used to describe the behaviour of the digital sequential circuits. It shows the transitions of states from one state to the next as well as the output for a given input.
Icarus Verilog is a simulator tool to check the design with the help of test bench. The design is nothing but the Verilog hardware description language code which specifies the functionality. The testbench is the setup to apply stimulus to test the functionality of the design. This simulator looks for the changes to the input. Upon changes to the input, the output is evaluated.
GTKWave is a fully featured GTK+ v1. 2 based wave viewer for Unix and Win32 which reads Ver Structural Verilog Compiler generated AET files as well as standard Verilog VCD/EVCD files and allows their viewing.
Yosys is a framework for Verilog RTL synthesis. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Open your terminal and type the following to install iverilog and GTKWave
$ sudo apt-get update
$ sudo apt-get install iverilog gtkwave
Follow the steps from the below git repository to install yosys on Ubuntu. https://github.com/YosysHQ/yosys/blob/master/README.md#installation
$ git clone https://github.com/YosysHQ/yosys.git
$ cd yosys-master
$ sudo apt install make (If make is not installed please install it)
$ sudo apt-get install build-essential clang bison flex \
libreadline-dev gawk tcl-dev libffi-dev git \
graphviz xdot pkg-config python3 libboost-system-dev \
libboost-python-dev libboost-filesystem-dev zlib1g-dev
$ make
$ sudo make install
To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal.
$ sudo apt install -y git
$ git clone https://github.com/RamyaIIIT/iiitb_4bitrc
$ cd iiitb_4bitrc
$ iverilog iiitb_4bit_ring_counter.v iiitb_4bit_ring_counter_tb.v
$ ./a.out
$ gtkwave dump.vcd
Synthesis transforms the simple RTL design into a gate-level netlist with all the constraints as specified by the designer. In simple language, Synthesis is a process that converts the abstract form of design to a properly implemented chip in terms of logic gates.
Synthesis takes place in multiple steps:
- Converting RTL into simple logic gates.
- Mapping those gates to actual technology-dependent logic gates available in the technology libraries.
- Optimizing the mapped netlist keeping the constraints set by the designer intact.
Invoke ''yosys' and execute the below commands to perform the synthesis of the above circuit.
$ read_liberty -lib ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
$ read_verilog iiitb_4bit_ring_counter.v
$ synth -top -top ring_counter
$ dfflibmap -liberty ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
$ abc -liberty -lib ./lib/sky130_fd_sc_hd__tt_025C_1v80.lib
$ show
$ stat
GLS implies running the testbench with netlist as the design under test. It is used to verify the logical correctness of the design after synthesis. It also ensures that the timing constraints are met.
Execute below commands in the project directory to perform GLS.
$ iverilog -DFUNCTIONAL -DUNIT_DELAY=#0 ./verilog_model/primitives.v ./verilog_model/sky130_fd_sc_hd.v
$ ./a.out
$ gtkwave dump.vcd
$ sudo apt install -y build-essential python3 python3-venv python3-pip
$ sudo apt-get remove docker docker-engine docker.io containerd runc (to remove the older version of docker if already installed)
$ sudo apt-get update
$ sudo apt-get install \
ca-certificates \
curl \
gnupg \
lsb-release
$ sudo mkdir -p /etc/apt/keyrings
$ curl -fsSL https://download.docker.com/linux/ubuntu/gpg | sudo gpg --dearmor -o /etc/apt/keyrings/docker.gpg
$ echo \
"deb [arch=$(dpkg --print-architecture) signed-by=/etc/apt/keyrings/docker.gpg] https://download.docker.com/linux/ubuntu \
$(lsb_release -cs) stable" | sudo tee /etc/apt/sources.list.d/docker.list > /dev/null
$ sudo apt-get update
$ sudo apt-get install docker-ce docker-ce-cli containerd.io docker-compose-plugin
$ apt-cache madison docker-ce (copy the version string you want to install)
$ sudo apt-get install docker-ce=<VERSION_STRING> docker-ce-cli=<VERSION_STRING> containerd.io docker-compose-plugin (paste the version string copies in place of <VERSION_STRING>)
$ sudo docker run hello-world (If the docker is successfully installed u will get a success message here)
$ git clone https://github.com/The-OpenROAD-Project/OpenLane.git
$ cd OpenLane/
$ make
$ make test
Before installing Magic, the following softwares have to be installed first:
$ sudo apt-get install csh (to install csh)
$ sudo apt-get install x11 (to install x11/xorg)
$ sudo apt-get install xorg
$ sudo apt-get install xorg openbox
$ sudo apt-get install gcc (to install gcc)
$ sudo apt-get install build-essential (to install build-essential)
$ sudo apt-get install freeglut3-dev (to install OpenGL)
$ sudo apt-get install tcl-dev tk-dev (to install tcl/tk)
$ git clone https://github.com/RTimothyEdwards/magic (to install magic)
$ cd magic
$ ./configure
$ make
$ make install
$ sudo apt-get install klayout (to install klayout)
$ sudo apt-get install ngspice (to install ngspice)
$ git clone https://github.com/nickson-jose/vsdstdcelldesign.git
$ cd vsdstdcelldesign
$ cp ./libs/sky130A.tech sky130A.tech
$ magic -T sky130A.tech sky130_inv.mag &
% extract all
% ext2spice cthresh 0 rthresh 0
% ext2spice
The layout is generated using OpenLane. To run the custom design on OpenLane, open the OpenLane folder in Terminal and run the following commands:
$ cd designs
$ mkdir iiitb_4bitrc
$ cd iiitb_4bitrc
$ mkdir src
$ touch config.json
$ cd src
$ touch iiitb_4bitrc.v
Copy sky130_fd_sc_hd__fast.lib, sky130_fd_sc_hd__slow.lib, sky130_fd_sc_hd__typical.lib and sky130_vsdinv.lef files to src folder in your design.
$ make mount (if this command doesnot go through prefix it with sudo)
$ ./flow.tcl -interactive
% package require openlane 0.9
% prep -design iiitb_4bitrc
set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
add_lefs -src $lefs
% run_synthesis
Run the floorplan and view the floorplan using the below commands:
% run_floorplan
$ magic -T /home/Ramya/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.min.lef def read iiitb_4bitrc.def &
Run the placement and view the placement using the below commands:
% run_placement
$ magic -T /home/Ramya/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_4bitrc.def &
Refer below image for zoomed view of layout after placement:
The zoomed in view of one of the sky130_inv cell is as below:
Run the cts with the below command:
% run_cts
Run routing and view the layout using the following commands:
% run_routing
$ magic -T /home/Ramya/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../tmp/merged.nom.lef def read iiitb_4bitrc.def &
Refer below image for zoomed view of after routing
- Ramya S
- Kunal Ghosh
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
- Ramya S, Ph.D Student, International Institute of Information Technology, Bangalore. ramya.suriyarani@gmail.com
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com