Instances of parametrized VHDL Posit Arithmetic units generated with the FloPoCo tool (http://flopoco.gforge.inria.fr/). These operators support the posit standard including round to nearest-even method.
FloPoCo allows to generate VHDL code for Posit⟨n,es⟩ arithmetic units with any configuration of bitwidth (n) and exponent-size (es). This repository contains concrete generated instances to facilitate its use and dissemination.
- Posit Adder
- Posit Multiplier
- Posit Fused Multiply-accumulate (MAC) with quire support
- Posit Logarithm-Approximate Multiplier
This work is the result from the following articles. Please refer to them for more detailed description of the posit cores.
If you find this code useful in your research, please consider citing:
R. Murillo, A. A. Del Barrio and G. Botella, "Customized Posit Adders and Multipliers using the FloPoCo Core Generator," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.9180771.
@inproceedings{murillo2020customized,
title={Customized posit adders and multipliers using the FloPoCo core generator},
author={Murillo, Raul and Del Barrio, Alberto Antonio and Botella, Guillermo},
booktitle={2020 IEEE International Symposium on Circuits and Systems (ISCAS)},
pages={1--5},
year={2020},
doi={10.1109/ISCAS45731.2020.9180771},
url={https://ieeexplore.ieee.org/document/9180771},
organization={IEEE}
}
R. Murillo, A. A. Del Barrio Garcia, G. Botella, M. S. Kim, H. Kim and N. Bagherzadeh, "PLAM: a Posit Logarithm-Approximate Multiplier," in IEEE Transactions on Emerging Topics in Computing (2021), doi: 10.1109/TETC.2021.3109127.
@article{murillo2021plam,
title={PLAM: a Posit Logarithm-Approximate Multiplier},
author={Murillo, Raul and Del Barrio, Alberto Antonio and Botella, Guillermo and Kim, Min Soo and Kim, Hyunjin and Bagherzadeh, Nader},
journal={IEEE Transactions on Emerging Topics in Computing},
year={2021},
volume={},
number={},
pages={1-1},
doi={10.1109/TETC.2021.3109127}},
url={https://ieeexplore.ieee.org/document/9530365},
publisher={IEEE}
}
R. Murillo, D. Mallasén, A. A. Del Barrio Garcia and G. Botella, "Energy-Efficient MAC Units for Fused Posit Arithmetic." 2021 IEEE 39th International Conference on Computer Design (ICCD). IEEE, 2021, doi: 10.1109/ICCD53106.2021.00032.
@inproceedings{murillo2021energy,
title={Energy-Efficient MAC Units for Fused Posit Arithmetic},
author={Murillo, Raul and Mallas{\'e}n, David and Del Barrio, Alberto A. and Botella, Guillermo},
booktitle={2021 IEEE 39th International Conference on Computer Design (ICCD)},
pages={138--145},
year={2021},
doi={10.1109/ICCD53106.2021.00032},
url={https://ieeexplore.ieee.org/document/9643752},
organization={IEEE}
}
R. Murillo, D. Mallasén, A. A. Del Barrio Garcia and G. Botella, "Comparing different decodings for posit arithmetic." Conference on Next Generation Arithmetic. Springer, Cham, 2022, doi: 10.1007/978-3-031-09779-9_6.
@inproceedings{murillo2022comparing,
title={Comparing different decodings for posit arithmetic},
author={Murillo, Raul and Mallas{\'e}n, David and Del Barrio, Alberto A. and Botella, Guillermo},
booktitle={Conference on Next Generation Arithmetic},
pages={84--99},
year={2022},
doi={10.1007/978-3-031-09779-9_6},
url={https://link.springer.com/chapter/10.1007/978-3-031-09779-9_6},
organization={Springer}
}
This work was supported by a 2020 Leonardo Grant for Researchers and Cultural Creators, from BBVA Foundation, whose id is PR2003 20/01, by the EU(FEDER) and the Spanish MINECO under grant RTI2018-093684-B-I00, and by the CM under grant S2018/TCS-4423.