Detail
Semester: 3rd Sem B. Tech. CSE
Section: S1
Team Members :
Detail
The simple traffic light controller design project was introduced to alleviate this shortcoming and gain experience in solving implementation and interfacing problems of a modern digital system. we implement a fully functional traffic signal controller for a four-way intersection between a busy road and village road, where less traffic is present. Intersection is complete with sensors to detect the presence of vehicles waiting at or approaching the inter-section .
These include HDL for modeling and finite state machines, and serial communication. Traffic lights, also known as traffic lamps, traffic signals, stoplight, stop-and-go lights semaphore or robots, are signaling devices positioned at pedestrian crossings, road intersections, and other locations to control competing flows of traffic. Traffic lights have installed in most cities around the world to control the flow of traffic.It assign the right of way to road users by the use of lights in standard colors (Red - Yellow - Green), using a universal color code (and a precise sequence, for color blind). It requires us to develop a state machine based controller for traffic signals at a four-way
Detail
As we know,Traffic lights are an essential part of road safety and help regulate the flow of traffic at intersections.We are implementing this project based on “Finite State Machine(FSM)” concepts to meet the requirements. Our project basically controls the traffic lights between intersection of a very Busy road (eg : highway road) and a normal road (eg : street road) with certain time delays for each of the color to change.
The implementation of a Finite State Machine (FSM) for traffic control at the intersection of a busy highway and a quieter street road demonstrates a systematic and efficient approach to managing traffic flow while prioritizing safety. This system is designed to enhance road safety and optimize traffic management.
In this FSM-based system, the primary objective is to ensure the smooth flow of traffic along the highway road. To accomplish this, the green signal remains active by default, prioritizing the highway road. However, the installation of sensors at the entrance of the street road allows the system to detect the presence of vehicles. When a vehicle is sensed, the sensor triggers a state transition, and the green signal on the highway side is temporarily interrupted.
During this transition, the green light on the highway side switches to red, allowing the vehicle on the street road to access the intersection safely. After a predetermined time delay, the green signal returns to the highway road, resuming the priority flow. This intelligent traffic control system efficiently balances the needs of both the busy highway and the village road, ensuring safety and optimizing traffic flow at the intersection.
Incorporating timers for each traffic light phase is a crucial aspect of your traffic control system, enhancing its precision and safety. The specific timing intervals you've mentioned are well-suited to maintain efficient traffic flow and minimize congestion at the intersection.
- Allowing a 16-second green light for the busy highway road ensures that traffic on this route experiences extended periods of priority. This long duration reduces the frequency of traffic light transitions, promoting smoother traffic flow and reducing the potential for congestion.
- With an 8-second green light for the street road, vehicles from the quieter road have a brief but adequate window of time to enter the intersection when the sensor is triggered. This timing optimizes the throughput for the village road without causing excessive delays for highway traffic.
- The 4-second yellow light phase serves as a crucial safety buffer between the green and red light transitions. It signals to all approaching vehicles that a change in traffic conditions is imminent, allowing them to prepare to stop safely. This yellow phase is especially important at such a high-traffic intersection, where sudden stops could lead to accidents.
Busy road is considered as North-South road and Street road is considered as East-west road. We defined four states named S0,S1,S2,S3 in our Finite State Machine. Each State has a certain time delays from moving to another state. As per the FSM below we want to change the states. Using d-flip flops we can achieve it.
Let us say S1 and S0 represents bits of my present state and A and B represents bits of my Future state, and T be the timer for each of the states. Consider the following truth table.
Using K-map we can get the expression for A and B. Our expression’s are :
A = S1’ S0 T + S1 S0’ + S1 T’
B = S0’ T + S0 T’ = S0 ^ T
Each state implies to 6 outputs such as Red light in North-south road (Busy road) as Rns
Yellow light in North-South road as Yns
Green light in North-South road as Gns
Red light in East-West road (street road) as Rew
Yellow light in East-West road as Yns
Green light in East-West road as Gns
Using K-map we can get the expression for Rns, Yns, Gns, Rew, Yew and Gew. Our expression’s are :
Rns = S1
Yns = S1’ S0
Gns = S1’ S0’
Rew = S1’
Yew = S0 S1
Gew = S1 S0’
We used a timing sequence of (if a vehicle present on the street road) the red signal in east-west road or green in the north-south road remains for 16 seconds in the Hardware part (as per convinience of usage of gates) where as 32 seconds in the verilog code. Yellow remains for 4 seconds and Green light on the street road remains for 8 seconds (in hardware part (logisim)) and 16 seconds in the verilog code. In the hardware part , we implement showing the timers using 7 segment displays using counters.
Detail
`timescale 1ns / 1ps
module Traffic(nsCounter,ewCounter,yellowCounter,NS_VEHICLE_DETECT,EW_VEHICLE_DETECT,NS_RED,NS_GREEN,EW_RED,EW_YELLOW,EW_GREEN);
input [4:0] nsCounter; input [3:0] ewCounter; input [1:0] yellowCounter; input NS_VEHICLE_DETECT; input EW_VEHICLE_DETECT; output reg NS_RED; output reg NS_YELLOW; output reg NS_GREEN; output reg EW_RED; output reg EW_YELLOW; output reg EW_GREEN;
initial begin
NS_RED <= 0;
NS_YELLOW <= 0;
NS_GREEN <= 1;
EW_RED <= 1;
EW_YELLOW <= 0;
EW_GREEN <= 0;
end
always @ (nsCounter) begin
if (nsCounter == 31 & EW_VEHICLE_DETECT & NS_GREEN) begin
NS_RED <= 0;
NS_YELLOW <= 1;
NS_GREEN <= 0;
EW_RED <= 1;
EW_YELLOW <= 0;
EW_GREEN <= 0;
end
end always @ (ewCounter) begin
if (ewCounter == 15 & EW_GREEN) begin
NS_RED <= 1;
NS_YELLOW <= 0;
NS_GREEN <= 0;
EW_RED <= 0;
EW_YELLOW <= 1;
EW_GREEN <= 0;
end
end always @ (yellowCounter) begin
if (yellowCounter == 3 & NS_YELLOW) begin
NS_RED <= 1;
NS_YELLOW <= 0;
NS_GREEN <= 0;
EW_RED <= 0;
EW_YELLOW <= 0;
EW_GREEN <= 1;
end
if (yellowCounter == 3 & EW_YELLOW) begin
NS_RED <= 0;
NS_YELLOW <= 0;
NS_GREEN <= 1;
EW_RED <= 1;
EW_YELLOW <= 0;
EW_GREEN <= 0;
end
end endmodule
/* A Counter for the North-South Traffic Light Counts from 0-31 */ module nsCounter ( input clk, output [4:0] count );
wire clk; reg[4:0] count;
initial count = 0;
always @ ( negedge clk ) count[0] <= ~count[0];
always @ ( negedge count[0] ) count[1] <= ~count[1];
always @ ( negedge count[1] ) count[2] <= ~count[2];
always @ ( negedge count[2] ) count[3] <= ~count[3];
always @ ( negedge count[3] ) count[4] <= ~count[4];
endmodule
module ewCounter ( input clk, output [3:0] count );
wire clk; reg[3:0] count;
initial count = 0;
always @ ( negedge clk ) count[0] <= ~count[0];
always @ ( negedge count[0] ) count[1] <= ~count[1];
always @ ( negedge count[1] ) count[2] <= ~count[2];
always @ ( negedge count[2] ) count[3] <= ~count[3];
endmodule
module yellowCounter ( input clk, output [1:0] count );
wire clk; reg[1:0] count;
initial count = 0;
always @ ( negedge clk ) count[0] <= ~count[0];
always @ ( negedge count[0] ) count[1] <= ~count[1];
endmodule `include"Traffic_eng312_proj3.v" module Traffic_Test_1;
// Inputs reg NS_VEHICLE_DETECT; reg EW_VEHICLE_DETECT;
wire NS_RED; wire NS_YELLOW; wire NS_GREEN; wire EW_RED; wire EW_YELLOW; wire EW_GREEN;
reg clk;
// Counters wire[4:0] count1; wire[3:0] count2; wire[1:0] count3;
nsCounter clock1(clk, count1); // Count a total of 32 seconds ewCounter clock2(clk, count2); // Counts a total of 16 seconds yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
$dumpfile("Traffic_test_1.vcd");
$dumpvars(0,Traffic_Test_1);
$display(" NS | EW ");
$display("R Y G R Y G ");
$monitor("%h %h %h %h %h %h", NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#10 NS_VEHICLE_DETECT = 0;#10 EW_VEHICLE_DETECT = 0;
#10 NS_VEHICLE_DETECT = 0;#10 EW_VEHICLE_DETECT = 1;
#10 NS_VEHICLE_DETECT = 0;#10 EW_VEHICLE_DETECT = 1;
#10 NS_VEHICLE_DETECT = 0;#10 EW_VEHICLE_DETECT = 0;
#10 NS_VEHICLE_DETECT = 0;#10 EW_VEHICLE_DETECT = 0;
#10 NS_VEHICLE_DETECT = 0;#10 EW_VEHICLE_DETECT = 0;
#1000 $finish;
end
always begin #1 clk = ~clk; end endmodule module Traffic_Test_2; reg NS_VEHICLE_DETECT; reg EW_VEHICLE_DETECT;
wire NS_RED; wire NS_YELLOW; wire NS_GREEN; wire EW_RED; wire EW_YELLOW; wire EW_GREEN;
reg clk;
wire[4:0] count1; wire[3:0] count2; wire[1:0] count3;
nsCounter clock1(clk, count1); // Count a total of 32 seconds ewCounter clock2(clk, count2); // Counts a total of 16 seconds yellowCounter clock3(clk, count3); // Counts a total of 4 seconds
Traffic CORE (count1, count2, count3, NS_VEHICLE_DETECT, EW_VEHICLE_DETECT, NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
initial begin
clk = 0;
NS_VEHICLE_DETECT = 0;
EW_VEHICLE_DETECT = 0;
$display(" NS | EW ");
$display("R Y G R Y G ");
$monitor("%h %h %h %h %h %h", NS_RED, NS_YELLOW, NS_GREEN, EW_RED, EW_YELLOW, EW_GREEN);
#1000 $finish;
end
always begin #1 clk = ~clk; end endmodule