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- Upgrade library to be compatible with Xilinx SDAccel 2018.2
This is a workaround for the legacy compiler bug, whereby a channel pop in the conditional term of a loop only occurs on entry to the loop and not on each subsequent iteration.
- Make SDK non-blocking so data can be loaded and retrieved while the FPGA is running
- Zero-initialise World so it can be inspected (e.g. you can now read the input data out)
Added Verilog configuration options for masking the AXI cache options and enabling AXI-3 style support for the write ID signal.