Pre-release
Pre-release

@CampGareth CampGareth released this Dec 12, 2018

Assets 3

Changes

  • Adds workaround for kernel names longer than Vivado 2018.2 supports
Pre-release

@CampGareth CampGareth released this Dec 12, 2018 · 2 commits to master since this release

Assets 3

Changes

  • Upgrade library to be compatible with Xilinx SDAccel 2018.2

@zynaptic zynaptic released this Oct 8, 2018 · 4 commits to master since this release

Assets 3

This is a workaround for the legacy compiler bug, whereby a channel pop in the conditional term of a loop only occurs on entry to the loop and not on each subsequent iteration.

@zynaptic zynaptic released this Oct 2, 2018 · 6 commits to master since this release

Assets 3

Introduces correctness fixes for the SMI library that are required by the new LLVM based Rio compiler.

@reconfig-bot reconfig-bot released this Sep 4, 2018 · 11 commits to master since this release

Assets 3
Deleted duplicate Verilog components from public SDAccel repository.

@CampGareth CampGareth released this Aug 22, 2018 · 12 commits to master since this release

Assets 3

Changes

  • Make SDK non-blocking so data can be loaded and retrieved while the FPGA is running
  • Zero-initialise World so it can be inspected (e.g. you can now read the input data out)

@reconfig-bot reconfig-bot released this Mar 20, 2018 · 21 commits to master since this release

Assets 3

Added Verilog configuration options for masking the AXI cache options and enabling AXI-3 style support for the write ID signal.

@reconfig-bot reconfig-bot released this Feb 16, 2018 · 24 commits to master since this release

Assets 3
Add SMI sub package

@reconfig-bot reconfig-bot released this Dec 12, 2017 · 36 commits to master since this release

Assets 2

Initial release of imported code

Deprecation notice

The Makefile does not build a proper fix.