updated sdmmc driver

Reisyukaku · Jul 24, 2018 · 59bd5dde19b2a68ffc0573f3901e17700b204749 · 59bd5dd
1 parent 11e1cfc
commit 59bd5dde19b2a68ffc0573f3901e17700b204749
diff --git a/src/bootloader.c b/src/bootloader.c
@@ -39,7 +39,7 @@ void mbist_workaround() {
    CLOCK(0x2AC) = 0x40;
    CLOCK(0x294) = 0x40000;
    CLOCK(0x304) = 0x18000000;
-    sleep(2);
+    usleep(2);

    I2S(0x0A0) |= 0x400;
    I2S(0x088) &= 0xFFFFFFFE;
@@ -53,7 +53,7 @@ void mbist_workaround() {
    I2S(0x488) &= 0xFFFFFFFE;
    DISPLAY_A(0xCF8) |= 4;
    VIC(0x8C) = 0xFFFFFFFF;
-    sleep(2);
+    usleep(2);

    CLOCK(0x2A8) = 0x40;
    CLOCK(0x300) = 0x18000000;
diff --git a/src/firmware.c b/src/firmware.c
@@ -60,7 +60,7 @@ void drawSplash() {
        fread((void*)0xC0000000, fsize(), 1);
        fclose();
    }
-    sleep(3000000);
+    usleep(3000000);
 }

 pk11_offs *pkg11_offsentify(u8 *pkg1) {
@@ -335,7 +335,7 @@ void launch() {
    // Boot secmon and Wait for it get ready.
    cluster_boot_cpu0(pk11Offs->secmon_base);
    while (!*SECMON_STATE_ADDR)
-        sleep(1);
+        usleep(1);

    // Disable display.
    if (pre4x)
diff --git a/src/fs.c b/src/fs.c
@@ -40,13 +40,13 @@ u32 sd_mount() {
    return 0;
 }

-u32 fopen(const char *path, const char *mode) {
+u32 *fopen(const char *path, const char *mode) {
    if (f_open(&fp, path, mode[0] == 'w' ? FA_WRITE : FA_READ) != FR_OK) 
        return NULL;
    return 1;
 }

-u32 fread(void *buf, size_t size, size_t ntimes) {
+u32 *fread(void *buf, size_t size, size_t ntimes) {
    u8 *ptr = buf;
    while (size > 0) {
        u32 rsize = MIN(ntimes * size, size);
@@ -61,7 +61,7 @@ u32 fread(void *buf, size_t size, size_t ntimes) {
    return 1;
 }

-u32 fwrite(void *buf, size_t size, size_t ntimes) {
+u32 *fwrite(void *buf, size_t size, size_t ntimes) {
    u8 *ptr = buf;
    while (size > 0) {
        u32 rsize = MIN(ntimes * size, size);
diff --git a/src/fs.h b/src/fs.h
@@ -1,9 +1,9 @@
 #pragma once

 u32 sd_mount();
-u32 fopen(const char *path, const char *mode);
-u32 fread(void *buf, size_t size, size_t ntimes);
-u32 fwrite(void *buf, size_t size, size_t ntimes);
+u32 *fopen(const char *path, const char *mode);
+u32 *fread(void *buf, size_t size, size_t ntimes);
+u32 *fwrite(void *buf, size_t size, size_t ntimes);
 size_t fsize();
 void fclose();
 size_t enumerateDir(char ***output, char *path, char *pattern);
diff --git a/src/hwinit/clock.c b/src/hwinit/clock.c
@@ -20,33 +20,33 @@
 #include "sdmmc.h"

 static const clock_t _clock_uart[] =  {
-	/* UART A */ { 4, 0x10, 0x178, 6, 0, 0 },
-	/* UART B */ { 4, 0x10, 0x17C, 7, 0, 0 },
-	/* UART C */ { 8, 0x14, 0x1A0, 0x17, 0, 0 },
+	/* UART A */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTA, 6, 0, 0 },
+	/* UART B */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_UARTB, 7, 0, 0 },
+	/* UART C */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_UARTC, 0x17, 0, 0 },
 	/* UART D */ { 0 },
 	/* UART E */ { 0 }
 };

 static const clock_t _clock_i2c[] = {
-	/* I2C1 */ { 4, 0x10, 0x124, 0xC, 6, 0 },
+	/* I2C1 */ { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1, 0xC, 6, 0 },
 	/* I2C2 */ { 0 },
 	/* I2C3 */ { 0 },
 	/* I2C4 */ { 0 },
-	/* I2C5 */ { 8, 0x14, 0x128, 0xF, 6, 0 },
+	/* I2C5 */ { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5, 0xF, 6, 0 },
 	/* I2C6 */ { 0 }
 };

-static clock_t _clock_se = { 0x358, 0x360, 0x42C, 0x1F, 0, 0 };
+static clock_t _clock_se = { CLK_RST_CONTROLLER_RST_DEVICES_V, CLK_RST_CONTROLLER_CLK_OUT_ENB_V, 0x42C, 0x1F, 0, 0 };

-static clock_t _clock_host1x = { 4, 0x10, 0x180, 0x1C, 4, 3 };
-static clock_t _clock_tsec = { 0xC, 0x18, 0x1F4, 0x13, 0, 2 };
-static clock_t _clock_sor_safe = { 0x2A4, 0x298, 0, 0x1E, 0, 0 };
-static clock_t _clock_sor0 = { 0x28C, 0x280, 0, 0x16, 0, 0 };
-static clock_t _clock_sor1 = { 0x28C, 0x280, 0x410, 0x17, 0, 2 };
-static clock_t _clock_kfuse = { 8, 0x14, 0, 8, 0, 0 };
+static clock_t _clock_host1x = { CLK_RST_CONTROLLER_RST_DEVICES_L, CLK_RST_CONTROLLER_CLK_OUT_ENB_L, CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X, 0x1C, 4, 3 };
+static clock_t _clock_tsec = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_TSEC, 0x13, 0, 2 };
+static clock_t _clock_sor_safe = { CLK_RST_CONTROLLER_RST_DEVICES_Y, CLK_RST_CONTROLLER_CLK_OUT_ENB_Y, CLK_RST_CONTROLLER_RST_SOURCE, 0x1E, 0, 0 };
+static clock_t _clock_sor0 = { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_RST_SOURCE, 0x16, 0, 0 };
+static clock_t _clock_sor1 = { CLK_RST_CONTROLLER_RST_DEVICES_X, CLK_RST_CONTROLLER_CLK_OUT_ENB_X, CLK_RST_CONTROLLER_CLK_SOURCE_SOR1, 0x17, 0, 2 };
+static clock_t _clock_kfuse = { CLK_RST_CONTROLLER_RST_DEVICES_H, CLK_RST_CONTROLLER_CLK_OUT_ENB_H, CLK_RST_CONTROLLER_RST_SOURCE, 8, 0, 0 };

-static clock_t _clock_cl_dvfs = { 0x35C, 0x364, 0, 0x1B, 0, 0 };
-static clock_t _clock_coresight = { 0xC, 0x18, 0x1D4, 9, 0, 4};
+static clock_t _clock_cl_dvfs = { CLK_RST_CONTROLLER_RST_DEVICES_W, CLK_RST_CONTROLLER_CLK_OUT_ENB_W, CLK_RST_CONTROLLER_RST_SOURCE, 0x1B, 0, 0 };
+static clock_t _clock_coresight = { CLK_RST_CONTROLLER_RST_DEVICES_U, CLK_RST_CONTROLLER_CLK_OUT_ENB_U, CLK_RST_CONTROLLER_CLK_SOURCE_CSITE, 9, 0, 4};

 void clock_enable(const clock_t *clk)
 {
@@ -147,9 +147,9 @@ void clock_enable_kfuse()
 	CLOCK(0x8) = (CLOCK(0x8) & 0xFFFFFEFF) | 0x100;
 	CLOCK(0x14) &= 0xFFFFFEFF;
 	CLOCK(0x14) = (CLOCK(0x14) & 0xFFFFFEFF) | 0x100;
-	sleep(10);
+	usleep(10);
 	CLOCK(0x8) &= 0xFFFFFEFF;
-	sleep(20);
+	usleep(20);
 }

 void clock_disable_kfuse()
@@ -436,7 +436,7 @@ void clock_sdmmc_enable(u32 id, u32 val)
 	_clock_sdmmc_config_clock_source_inner(&div, id, val);
 	_clock_sdmmc_set_enable(id);
 	_clock_sdmmc_is_reset(id);
-	sleep((100000 + div - 1) / div);
+	usleep((100000 + div - 1) / div);
 	_clock_sdmmc_clear_reset(id);
 	_clock_sdmmc_is_reset(id);
 }
diff --git a/src/hwinit/clock.h b/src/hwinit/clock.h
@@ -20,7 +20,9 @@
 #include "types.h"

 /*! Clock registers. */
+#define CLK_RST_CONTROLLER_RST_SOURCE 0x0
 #define CLK_RST_CONTROLLER_RST_DEVICES_L 0x4
+#define CLK_RST_CONTROLLER_RST_DEVICES_H 0x8
 #define CLK_RST_CONTROLLER_RST_DEVICES_U 0xC
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_L 0x10
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_H 0x14
@@ -32,38 +34,79 @@
 #define CLK_RST_CONTROLLER_CLK_SYSTEM_RATE 0x30
 #define CLK_RST_CONTROLLER_MISC_CLK_ENB 0x48
 #define CLK_RST_CONTROLLER_OSC_CTRL 0x50
+#define CLK_RST_CONTROLLER_PLLC_MISC 0x88
+#define CLK_RST_CONTROLLER_PLLM_BASE 0x90
+#define CLK_RST_CONTROLLER_PLLM_MISC1 0x98
+#define CLK_RST_CONTROLLER_PLLM_MISC2 0x9C
+#define CLK_RST_CONTROLLER_PLLP_BASE 0xA0
+#define CLK_RST_CONTROLLER_PLLD_BASE 0xD0
 #define CLK_RST_CONTROLLER_PLLX_BASE 0xE0
 #define CLK_RST_CONTROLLER_PLLX_MISC 0xE4
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRA 0xF8
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRB 0xFC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 0x124
+#define CLK_RST_CONTROLLER_CLK_SOURCE_I2C5 0x128
+#define CLK_RST_CONTROLLER_CLK_SOURCE_VI 0x148
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 0x150
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 0x154
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 0x164
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTA 0x178
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTB 0x17C
+#define CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X 0x180
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UARTC 0x1A0
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 0x1BC
+#define CLK_RST_CONTROLLER_CLK_SOURCE_CSITE 0x1D4
 #define CLK_RST_CONTROLLER_CLK_SOURCE_EMC 0x19C
+#define CLK_RST_CONTROLLER_CLK_SOURCE_TSEC 0x1F4
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_X 0x280
 #define CLK_RST_CONTROLLER_CLK_ENB_X_SET 0x284
+#define CLK_RST_CONTROLLER_CLK_ENB_X_CLR 0x288
+#define CLK_RST_CONTROLLER_RST_DEVICES_X 0x28C
+#define CLK_RST_CONTROLLER_RST_DEV_X_SET 0x290
+#define CLK_RST_CONTROLLER_RST_DEV_X_CLR 0x294
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_Y 0x298
 #define CLK_RST_CONTROLLER_CLK_ENB_Y_SET 0x29C
+#define CLK_RST_CONTROLLER_CLK_ENB_Y_CLR 0x2A0
+#define CLK_RST_CONTROLLER_RST_DEVICES_Y 0x2A4
+#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2A8
+#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2AC
 #define CLK_RST_CONTROLLER_RST_DEV_L_SET 0x300
 #define CLK_RST_CONTROLLER_RST_DEV_L_CLR 0x304
 #define CLK_RST_CONTROLLER_RST_DEV_H_SET 0x308
+#define CLK_RST_CONTROLLER_RST_DEV_H_CLR 0x30C
 #define CLK_RST_CONTROLLER_RST_DEV_U_SET 0x310
 #define CLK_RST_CONTROLLER_RST_DEV_U_CLR 0x314
 #define CLK_RST_CONTROLLER_CLK_ENB_L_SET 0x320
 #define CLK_RST_CONTROLLER_CLK_ENB_L_CLR 0x324
 #define CLK_RST_CONTROLLER_CLK_ENB_H_SET 0x328
+#define CLK_RST_CONTROLLER_CLK_ENB_H_CLR 0x32C
 #define CLK_RST_CONTROLLER_CLK_ENB_U_SET 0x330
 #define CLK_RST_CONTROLLER_CLK_ENB_U_CLR 0x334
 #define CLK_RST_CONTROLLER_RST_DEVICES_V 0x358
+#define CLK_RST_CONTROLLER_RST_DEVICES_W 0x35C
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_V 0x360
 #define CLK_RST_CONTROLLER_CLK_OUT_ENB_W 0x364
 #define CLK_RST_CONTROLLER_CPU_SOFTRST_CTRL2 0x388
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRC 0x3A0
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRD 0x3A4
 #define CLK_RST_CONTROLLER_CLK_SOURCE_MSELECT 0x3B4
+#define CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 0x410
 #define CLK_RST_CONTROLLER_CLK_ENB_V_SET 0x440
+#define CLK_RST_CONTROLLER_CLK_ENB_W_SET 0x448
+#define CLK_RST_CONTROLLER_CLK_ENB_W_CLR 0x44C
 #define CLK_RST_CONTROLLER_RST_CPUG_CMPLX_CLR 0x454
+#define CLK_RST_CONTROLLER_UTMIP_PLL_CFG2 0x488
+#define CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S0 0x4A0
 #define CLK_RST_CONTROLLER_PLLX_MISC_3 0x518
+#define CLK_RST_CONTROLLER_LVL2_CLK_GATE_OVRE 0x554
 #define CLK_RST_CONTROLLER_SPARE_REG0 0x55C
 #define CLK_RST_CONTROLLER_PLLMB_BASE 0x5E8
+#define CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP 0x620
+#define CLK_RST_CONTROLLER_CLK_SOURCE_EMC_DLL 0x664
+#define CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIP_CAL 0x66C
 #define CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM 0x694
+#define CLK_RST_CONTROLLER_CLK_SOURCE_NVENC 0x6A0
+#define CLK_RST_CONTROLLER_SE_SUPER_CLK_DIVIDER 0x704

 /*! Generic clock descriptor. */
 typedef struct _clock_t
diff --git a/src/hwinit/cluster.c b/src/hwinit/cluster.c
@@ -44,7 +44,7 @@ int _cluster_pmc_enable_partition(u32 part, u32 toggle)
 	u32 i = 5001;
 	while (PMC(APBDEV_PMC_PWRGATE_TOGGLE) & 0x100)
 	{
-		sleep(1);
+		usleep(1);
 		i--;
 		if (i < 1)
 			return 0;
@@ -57,7 +57,7 @@ int _cluster_pmc_enable_partition(u32 part, u32 toggle)
 	{
 		if (PMC(APBDEV_PMC_PWRGATE_STATUS) & part)
 			break;
-		sleep(1);
+		usleep(1);
 		i--;
 	}

@@ -74,7 +74,7 @@ void cluster_boot_cpu0(u32 entry)
 	if (!(CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) & 0x40000000))
 	{
 		CLOCK(CLK_RST_CONTROLLER_PLLX_MISC_3) &= 0xFFFFFFF7;
-		sleep(2);
+		usleep(2);
 		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x80404E02;
 		CLOCK(CLK_RST_CONTROLLER_PLLX_BASE) = 0x404E02;
 		CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) = (CLOCK(CLK_RST_CONTROLLER_PLLX_MISC) & 0xFFFBFFFF) | 0x40000;
diff --git a/src/hwinit/di.c b/src/hwinit/di.c
@@ -33,7 +33,7 @@ static void _display_dsi_wait(u32 timeout, u32 off, u32 mask)
 	u32 end = TMR(0x10) + timeout;
 	while (TMR(0x10) < end && DSI(off) & mask)
 		;
-	sleep(5);
+	usleep(5);
 }

 void display_init()
@@ -67,11 +67,11 @@ void display_init()
 	GPIO_3(0x10) = GPIO_3(0x10) & 0xFFFFFFFC | 0x3;
 	GPIO_3(0x20) = GPIO_3(0x20) & 0xFFFFFFFE | 0x1;

-	sleep(10000u);
+	usleep(10000u);

 	GPIO_3(0x20) = GPIO_3(0x20) & 0xFFFFFFFD | 0x2;

-	sleep(10000);
+	usleep(10000);

 	GPIO_6(0x04) = GPIO_6(0x04) & 0xFFFFFFF8 | 0x7;
 	GPIO_6(0x14) = GPIO_6(0x14) & 0xFFFFFFF8 | 0x7;
@@ -84,11 +84,11 @@ void display_init()
 	exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_2, 94);
 	exec_cfg((u32 *)DSI_BASE, _display_config_3, 60);

-	sleep(10000);
+	usleep(10000);

 	GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFB | 0x4;

-	sleep(60000);
+	usleep(60000);

 	DSI(_DSIREG(DSI_DSI_BTA_TIMING)) = 0x50204;
 	DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x337;
@@ -102,7 +102,7 @@ void display_init()
 	DSI(_DSIREG(DSI_HOST_DSI_CONTROL)) = 0x200B;
 	_display_dsi_wait(150000, _DSIREG(DSI_HOST_DSI_CONTROL), 8);

-	sleep(5000);
+	usleep(5000);

 	_display_ver = DSI(_DSIREG(DSI_DSI_RD_DATA));
 	if (_display_ver == 0x10)
@@ -111,25 +111,25 @@ void display_init()
 	DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x1105;
 	DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2;

-	sleep(180000);
+	usleep(180000);

 	DSI(_DSIREG(DSI_DSI_WR_DATA)) = 0x2905;
 	DSI(_DSIREG(DSI_DSI_TRIGGER)) = 0x2;

-	sleep(20000);
+	usleep(20000);

 	exec_cfg((u32 *)DSI_BASE, _display_config_5, 21);
 	exec_cfg((u32 *)CLOCK_BASE, _display_config_6, 3);
 	DISPLAY_A(_DIREG(DC_DISP_DISP_CLOCK_CONTROL)) = 4;
 	exec_cfg((u32 *)DSI_BASE, _display_config_7, 10);

-	sleep(10000);
+	usleep(10000);

 	exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_8, 6);
 	exec_cfg((u32 *)DSI_BASE, _display_config_9, 4);
 	exec_cfg((u32 *)MIPI_CAL_BASE, _display_config_10, 16);

-	sleep(10000);
+	usleep(10000);

 	exec_cfg((u32 *)DISPLAY_A_BASE, _display_config_11, 113);
 }
@@ -155,7 +155,7 @@ void display_color_screen(u32 color)
 	DISPLAY_A(_DIREG(DC_DISP_BLEND_BACKGROUND_COLOR)) = color;
 	DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) = DISPLAY_A(_DIREG(DC_CMD_STATE_CONTROL)) & 0xFFFFFFFE | 1;

-	sleep(35000);
+	usleep(35000);

 	GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFE | 1;
 }
@@ -165,7 +165,7 @@ u32 *display_init_framebuffer()
 	//This configures the framebuffer @ 0xC0000000 with a resolution of 1280x720 (line stride 768).
 	exec_cfg((u32 *)DISPLAY_A_BASE, cfg_display_framebuffer, 32);

-	sleep(35000);
+	usleep(35000);

 	GPIO_6(0x24) = GPIO_6(0x24) & 0xFFFFFFFE | 1;

diff --git a/src/hwinit/i2c.c b/src/hwinit/i2c.c
@@ -26,7 +26,7 @@ static void _i2c_wait(vu32 *base)
 	base[0x23] = 0x25;
 	for (u32 i = 0; i < 20; i++)
 	{
-		sleep(1);
+		usleep(1);
 		if (!(base[0x23] & 1))
 			break;
 	}
@@ -89,7 +89,7 @@ void i2c_init(u32 idx)

 	for (u32 i = 0; i < 10; i++)
 	{
-		sleep(20000);
+		usleep(20000);
 		if (base[0x1A] & 0x800)
 			break;
 	}
diff --git a/src/hwinit/max7762x.c b/src/hwinit/max7762x.c
@@ -103,7 +103,7 @@ int max77620_regulator_set_voltage(u32 id, u32 mv)
 	u8 val = i2c_recv_byte(I2C_5, 0x3C, reg->volt_addr);
 	val = (val & ~reg->volt_mask) | (mult & reg->volt_mask);
 	i2c_send_byte(I2C_5, 0x3C, reg->volt_addr, val);
-	sleep(1000);
+	usleep(1000);

 	return 1;
 }
@@ -122,7 +122,7 @@ int max77620_regulator_enable(u32 id, int enable)
 	else
 		val &= ~reg->enable_mask;
 	i2c_send_byte(I2C_5, 0x3C, addr, val);
-	sleep(1000);
+	usleep(1000);

 	return 1;
 }
diff --git a/src/hwinit/mc.c b/src/hwinit/mc.c
@@ -127,7 +127,7 @@ void mc_enable()
 	//Enable EMC DLL clock.
 	CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) = (CLOCK(CLK_RST_CONTROLLER_CLK_ENB_X_SET) & 0xFFFFBFFF) | 0x4000;
 	CLOCK(CLK_RST_CONTROLLER_RST_DEV_H_SET) = 0x2000001; //Clear EMC and MC reset.
-	sleep(5);
+	usleep(5);

 	//#ifdef CONFIG_ENABLE_AHB_REDIRECT
 	mc_disable_ahb_redirect();