iiit_lfsr- Linear feedback shift register

Description

The Aim of this exercise is to design a linear feedback shift register to produce a random number sequence. We would be using 130nm technology node by Skywater. We would also understand the functionality, pre-layout and post-layout characterstics.

Note: Circuit requires further optimization to improve performance. Design yet to be modified.

Introduction

Linear feedback shift register has 4 d-flipflops and a Ex-or Gate. We would also use multiplexers to initialize the sequence. This design would generate a sequence of numbers(bits). Although the sequence generated can be predicted by observing the previous bits as it would be repeating a cycle. However we can modify the circuit and its feedback paths to make it look more random and decrease the predictibilty. ¹

Application of LFSR(Linear feedback shift register)

LFSR counter has various applications

• Uses in cryptograpgy
• Uses in circuit testing
• Uses in puzzles and games

LFSR - Verilog Block diagram

The Block Diagram of LFSR shown Below :-

Functional Simulation

Waveform :-

²

Softwares used

- iverilog

Icarus Verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format. ³

- gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix, Win32, and Mac OSX which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing. ²

1) Installing necessary softwares:

$ sudo apt-get install git 

$ sudo apt-get install iverilog 

$ sudo apt-get install gtkwave 

2) Executing the Project:

$ git clone 

$ cd iiitb_lfsr

$ iverilog iiitb_lfsr.v iiitb_lfsr_tb.v -o iiitb_lfsr

$ ./iiitb_lfsr

$ gtkwave iiitb_lfsr.vcd

Gate Level Simulation

While performing GLS we use skywater 130 nm technology library files to import the cells from the library. Using those cells we then generate the netlist which would be a new .v file generated by write_verilog command. With this file and the testbench we generated for the RTL simulation we would again get a new waveform for this GLS netlist. This waveform should match with our initial waveform, infact waveforms if every stages of the flow should match the initial design waveform.

1. Go to the directory where verilog code is present and open the terminal.

2. Invoke yosys.

Give the following commands for synthesis:

// reads the library file from sky130//
yosys> read_liberty -lib ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib

// reads the verilog files//
yosys> read_verilog iiitb_lfsr.v

//synthesize the top module of verilog file//
yosys> synth -top iiitb_lfsr

//Generates netlist//
yosys> abc -liberty ../lib/sky130_fd_sc_hd__tt_025C_1v80.lib

//Simplified netlist//
yosys> flatten

//Displays the Netlist circuit//
yosys> show

Synthesized Circuit

⁴

//Writing Netlist//
yosys> write_verilog -noattr iiitb_lfsr_net.v

3. Invoke GLS

$ iverilog ../verilog_model/primitives.v ../verilog_model/sky130_fd_sc_hd.v iiitb_lfsr_net.v iiitb_lfsr_tb.v
$ ./a.out
$ gtkwave iiitb_lfsr_tb.vcd

4. Gate Level Simulation

PHYSICAL DESIGN

Openlane

OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.

more at https://github.com/The-OpenROAD-Project/OpenLane

Installation instructions

$   apt install -y build-essential python3 python3-venv python3-pip

Docker installation process: https://docs.docker.com/engine/install/ubuntu/

goto home directory->

$   git clone https://github.com/The-OpenROAD-Project/OpenLane.git
$   cd OpenLane/
$   sudo make

To test the open lane

$ sudo make test

It takes approximate time of 5min to complete. After 43 steps, if it ended with saying Basic test passed then open lane installed succesfully.

Magic

Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.

More about magic at http://opencircuitdesign.com/magic/index.html

Run following commands one by one to fulfill the system requirement.

$   sudo apt-get install m4
$   sudo apt-get install tcsh
$   sudo apt-get install csh
$   sudo apt-get install libx11-dev
$   sudo apt-get install tcl-dev tk-dev
$   sudo apt-get install libcairo2-dev
$   sudo apt-get install mesa-common-dev libglu1-mesa-dev
$   sudo apt-get install libncurses-dev

To install magic goto home directory

$   git clone https://github.com/RTimothyEdwards/magic
$   cd magic/
$   ./configure
$   sudo make
$   sudo make install

type magic terminal to check whether it installed succesfully or not. type exit to exit magic.

Generating Layout

Open terminal in home directory

$   cd OpenLane/
$   cd designs/
$   mkdir iiitb_lfsr
$   cd iiitb_lfsr/
$   wget https://raw.githubusercontent.com/riteshlalwani/iiitb_lfsr/main/config.json
$   mkdir src
$   cd src/
$   wget https://raw.githubusercontent.com/riteshlalwani/iiitb_lfsr/main/.v
$   cd ../../../
$   sudo make mount
$   ./flow.tcl -design iiitb_lfsr

To see the layout we use a tool called magic which we installed earlier.

open terminal in home directory

$   cd OpenLane/designs/iiitb_lfsr/run
$   ls

select most run directoy from list

$  cd RUN_2022.08.24_18.20.10

run following instruction

$   cd results/final/def

update the highlited text with appropriate path

$ magic -T /home/parallels/Desktop/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../../tmp/merged.max.lef def read iiitb_lfsr.def &

layout will be open in new window

Stats after placeing the vsdinv in our design

We can observe here the number of cells being used and also the different skywater blocks like d-flipflops and all other wires being used. Here the area of our design is also mentioned, which in our case comes out to be 200.192 um^2. There are four inverters being used, all of them are replaced by our designed vsdinv.

Floorplan

Process for getting to the floorplan

After merging the vsdinv with our design we have to get started with the commands to run synthesis and floorplan in our design. Following commands will be given:- #Synthesis For the synthesis we would run the command run_synthesis For floorplan we would first use init_floorplan and then run_floorplan For timing analysis and slack contraints we would use cts command:- run_cts

vsdinv inside the LFSR Floorplan

Post-Layout Results

1. Post-synthesis gate Count

Gate Count = 18

2. Design Area

Area = 6320.172 µm2

3. Performance

Performance = 1/(clock period - slack) = 1/(65.73 - 52.57) = 75.98 MHz

4. Flip-Flop to standard cell ratio

Flop ratio = Number of D Flip flops / Total Number of cells

Flop Ratio = 4/18 = 0.22

5. Power

Internal Power = 1.09e-05 W

Switching Power = 2.47e-06 W

Leakage Power = 2.86e-10 W

Total Power = 1.34e-05 W

Future work:

working on **Tapeout and finding bugs in design , if any **.

Contributors

• Ritesh Lalwani
• Kunal Ghosh
• Tejas B N

Acknowledgments

• Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
• Madhav Rao, Associate Professor, IIIT Bangalore
• V N Muralidhara,Mtech Coordinator, Associate Professor, IIIT Bangalore

# Contact Information

- Ritesh Lalwani, Mtech ECE student, International Institute of Information Technology, Bangalore  ritesh7328@gmail.com
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com
  

References

Footnotes

1. Texas instruments website TI website ↩

2. GTK Wave documentation ↩ ↩²

3. Icarus Verilog - iverilog ↩

4. Yosys synthesis tool ↩