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Highly configurable single-issue, single-core RV32I, RV64I compliant RISC-V CPU intended for the embedded market. The RV12 implements a Harvard architecture for simultaneous instruction and data memory accesses, featuring an optimizing folded 6-stage pipeline, which optimizes overlaps between the execution and memory accesses, thereby reducing stalls and improving efficiency.
- Full Support for Privileged Spec v1.10 and User Spec v 2.2
- Higher performance 6 stage pipeline
- Physical Memory Protection Block support
Below is a summary of key issues addressed. See GitHub Release Milestone for a full list & details.